rtl-llm/chisel-verilog-pairs · Datasets at Hugging Face

prompt stringlengths 162 4.26M	response stringlengths 109 5.16M
Generate the Verilog code corresponding to this FIRRTL code module RenameBusyTable : input clock : Clock input reset : Reset output io : { flip ren_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2], busy_resps : { prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>}[2], flip rebusy_reqs : UInt<1>[2], flip wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip child_rebusys : UInt<2>, debug : { busytable : UInt<80>}} wire wakeups_0 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG : UInt<1>, clock connect wakeups_wu_valid_REG, io.wakeups[0].valid reg wakeups_wu_valid_REG_1 : UInt, clock connect wakeups_wu_valid_REG_1, io.wakeups[0].bits.speculative_mask node _wakeups_wu_valid_T = and(wakeups_wu_valid_REG_1, io.child_rebusys) node _wakeups_wu_valid_T_1 = eq(_wakeups_wu_valid_T, UInt<1>(0h0)) node _wakeups_wu_valid_T_2 = and(wakeups_wu_valid_REG, _wakeups_wu_valid_T_1) connect wakeups_0.valid, _wakeups_wu_valid_T_2 reg wakeups_wu_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG, io.wakeups[0].bits connect wakeups_0.bits, wakeups_wu_bits_REG wire wakeups_1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_2 : UInt<1>, clock connect wakeups_wu_valid_REG_2, io.wakeups[1].valid reg wakeups_wu_valid_REG_3 : UInt, clock connect wakeups_wu_valid_REG_3, io.wakeups[1].bits.speculative_mask node _wakeups_wu_valid_T_3 = and(wakeups_wu_valid_REG_3, io.child_rebusys) node _wakeups_wu_valid_T_4 = eq(_wakeups_wu_valid_T_3, UInt<1>(0h0)) node _wakeups_wu_valid_T_5 = and(wakeups_wu_valid_REG_2, _wakeups_wu_valid_T_4) connect wakeups_1.valid, _wakeups_wu_valid_T_5 reg wakeups_wu_bits_REG_1 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_1, io.wakeups[1].bits connect wakeups_1.bits, wakeups_wu_bits_REG_1 wire wakeups_2 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_4 : UInt<1>, clock connect wakeups_wu_valid_REG_4, io.wakeups[2].valid reg wakeups_wu_valid_REG_5 : UInt, clock connect wakeups_wu_valid_REG_5, io.wakeups[2].bits.speculative_mask node _wakeups_wu_valid_T_6 = and(wakeups_wu_valid_REG_5, io.child_rebusys) node _wakeups_wu_valid_T_7 = eq(_wakeups_wu_valid_T_6, UInt<1>(0h0)) node _wakeups_wu_valid_T_8 = and(wakeups_wu_valid_REG_4, _wakeups_wu_valid_T_7) connect wakeups_2.valid, _wakeups_wu_valid_T_8 reg wakeups_wu_bits_REG_2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_2, io.wakeups[2].bits connect wakeups_2.bits, wakeups_wu_bits_REG_2 wire wakeups_3 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_6 : UInt<1>, clock connect wakeups_wu_valid_REG_6, io.wakeups[3].valid reg wakeups_wu_valid_REG_7 : UInt, clock connect wakeups_wu_valid_REG_7, io.wakeups[3].bits.speculative_mask node _wakeups_wu_valid_T_9 = and(wakeups_wu_valid_REG_7, io.child_rebusys) node _wakeups_wu_valid_T_10 = eq(_wakeups_wu_valid_T_9, UInt<1>(0h0)) node _wakeups_wu_valid_T_11 = and(wakeups_wu_valid_REG_6, _wakeups_wu_valid_T_10) connect wakeups_3.valid, _wakeups_wu_valid_T_11 reg wakeups_wu_bits_REG_3 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_3, io.wakeups[3].bits connect wakeups_3.bits, wakeups_wu_bits_REG_3 regreset busy_table : UInt<80>, clock, reset, UInt<80>(0h0) node _busy_table_wb_T = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_wb_T_1 = eq(wakeups_0.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_2 = and(wakeups_0.valid, _busy_table_wb_T_1) node _busy_table_wb_T_3 = mux(_busy_table_wb_T_2, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_4 = and(_busy_table_wb_T, _busy_table_wb_T_3) node _busy_table_wb_T_5 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_wb_T_6 = eq(wakeups_1.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_7 = and(wakeups_1.valid, _busy_table_wb_T_6) node _busy_table_wb_T_8 = mux(_busy_table_wb_T_7, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_9 = and(_busy_table_wb_T_5, _busy_table_wb_T_8) node _busy_table_wb_T_10 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst) node _busy_table_wb_T_11 = eq(wakeups_2.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_12 = and(wakeups_2.valid, _busy_table_wb_T_11) node _busy_table_wb_T_13 = mux(_busy_table_wb_T_12, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_14 = and(_busy_table_wb_T_10, _busy_table_wb_T_13) node _busy_table_wb_T_15 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst) node _busy_table_wb_T_16 = eq(wakeups_3.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_17 = and(wakeups_3.valid, _busy_table_wb_T_16) node _busy_table_wb_T_18 = mux(_busy_table_wb_T_17, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_19 = and(_busy_table_wb_T_15, _busy_table_wb_T_18) node _busy_table_wb_T_20 = or(_busy_table_wb_T_4, _busy_table_wb_T_9) node _busy_table_wb_T_21 = or(_busy_table_wb_T_20, _busy_table_wb_T_14) node _busy_table_wb_T_22 = or(_busy_table_wb_T_21, _busy_table_wb_T_19) node _busy_table_wb_T_23 = not(_busy_table_wb_T_22) node busy_table_wb = and(busy_table, _busy_table_wb_T_23) node _busy_table_next_T = dshl(UInt<1>(0h1), io.ren_uops[0].pdst) node _busy_table_next_T_1 = mux(io.rebusy_reqs[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_2 = and(_busy_table_next_T, _busy_table_next_T_1) node _busy_table_next_T_3 = dshl(UInt<1>(0h1), io.ren_uops[1].pdst) node _busy_table_next_T_4 = mux(io.rebusy_reqs[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_5 = and(_busy_table_next_T_3, _busy_table_next_T_4) node _busy_table_next_T_6 = or(_busy_table_next_T_2, _busy_table_next_T_5) node _busy_table_next_T_7 = or(busy_table_wb, _busy_table_next_T_6) node _busy_table_next_T_8 = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_next_T_9 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _busy_table_next_T_10 = mux(_busy_table_next_T_9, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_11 = and(_busy_table_next_T_8, _busy_table_next_T_10) node _busy_table_next_T_12 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_next_T_13 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _busy_table_next_T_14 = mux(_busy_table_next_T_13, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_15 = and(_busy_table_next_T_12, _busy_table_next_T_14) node _busy_table_next_T_16 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst) node _busy_table_next_T_17 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _busy_table_next_T_18 = mux(_busy_table_next_T_17, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_19 = and(_busy_table_next_T_16, _busy_table_next_T_18) node _busy_table_next_T_20 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst) node _busy_table_next_T_21 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _busy_table_next_T_22 = mux(_busy_table_next_T_21, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_23 = and(_busy_table_next_T_20, _busy_table_next_T_22) node _busy_table_next_T_24 = or(_busy_table_next_T_11, _busy_table_next_T_15) node _busy_table_next_T_25 = or(_busy_table_next_T_24, _busy_table_next_T_19) node _busy_table_next_T_26 = or(_busy_table_next_T_25, _busy_table_next_T_23) node busy_table_next = or(_busy_table_next_T_7, _busy_table_next_T_26) connect busy_table, busy_table_next node _prs1_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_0 = and(wakeups_0.valid, _prs1_match_T) node _prs1_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_1 = and(wakeups_1.valid, _prs1_match_T_1) node _prs1_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_2 = and(wakeups_2.valid, _prs1_match_T_2) node _prs1_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_3 = and(wakeups_3.valid, _prs1_match_T_3) node _prs2_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_0 = and(wakeups_0.valid, _prs2_match_T) node _prs2_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_1 = and(wakeups_1.valid, _prs2_match_T_1) node _prs2_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_2 = and(wakeups_2.valid, _prs2_match_T_2) node _prs2_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_3 = and(wakeups_3.valid, _prs2_match_T_3) node _prs3_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_0 = and(wakeups_0.valid, _prs3_match_T) node _prs3_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_1 = and(wakeups_1.valid, _prs3_match_T_1) node _prs3_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_2 = and(wakeups_2.valid, _prs3_match_T_2) node _prs3_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_3 = and(wakeups_3.valid, _prs3_match_T_3) node _io_busy_resps_0_prs1_busy_T = dshr(busy_table, io.ren_uops[0].prs1) node _io_busy_resps_0_prs1_busy_T_1 = bits(_io_busy_resps_0_prs1_busy_T, 0, 0) connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_T_1 node _io_busy_resps_0_prs2_busy_T = dshr(busy_table, io.ren_uops[0].prs2) node _io_busy_resps_0_prs2_busy_T_1 = bits(_io_busy_resps_0_prs2_busy_T, 0, 0) connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_T_1 node _io_busy_resps_0_prs3_busy_T = dshr(busy_table, io.ren_uops[0].prs3) node _io_busy_resps_0_prs3_busy_T_1 = bits(_io_busy_resps_0_prs3_busy_T, 0, 0) connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_T_1 node _T = or(prs1_match_0, prs1_match_1) node _T_1 = or(_T, prs1_match_2) node _T_2 = or(_T_1, prs1_match_3) when _T_2 : node _io_busy_resps_0_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_6 = mux(prs1_match_0, _io_busy_resps_0_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_7 = mux(prs1_match_1, _io_busy_resps_0_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_8 = mux(prs1_match_2, _io_busy_resps_0_prs1_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_9 = mux(prs1_match_3, _io_busy_resps_0_prs1_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_10 = or(_io_busy_resps_0_prs1_busy_T_6, _io_busy_resps_0_prs1_busy_T_7) node _io_busy_resps_0_prs1_busy_T_11 = or(_io_busy_resps_0_prs1_busy_T_10, _io_busy_resps_0_prs1_busy_T_8) node _io_busy_resps_0_prs1_busy_T_12 = or(_io_busy_resps_0_prs1_busy_T_11, _io_busy_resps_0_prs1_busy_T_9) wire _io_busy_resps_0_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs1_busy_WIRE, _io_busy_resps_0_prs1_busy_T_12 connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_WIRE node _T_3 = or(prs2_match_0, prs2_match_1) node _T_4 = or(_T_3, prs2_match_2) node _T_5 = or(_T_4, prs2_match_3) when _T_5 : node _io_busy_resps_0_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_6 = mux(prs2_match_0, _io_busy_resps_0_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_7 = mux(prs2_match_1, _io_busy_resps_0_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_8 = mux(prs2_match_2, _io_busy_resps_0_prs2_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_9 = mux(prs2_match_3, _io_busy_resps_0_prs2_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_10 = or(_io_busy_resps_0_prs2_busy_T_6, _io_busy_resps_0_prs2_busy_T_7) node _io_busy_resps_0_prs2_busy_T_11 = or(_io_busy_resps_0_prs2_busy_T_10, _io_busy_resps_0_prs2_busy_T_8) node _io_busy_resps_0_prs2_busy_T_12 = or(_io_busy_resps_0_prs2_busy_T_11, _io_busy_resps_0_prs2_busy_T_9) wire _io_busy_resps_0_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs2_busy_WIRE, _io_busy_resps_0_prs2_busy_T_12 connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_WIRE node _T_6 = or(prs3_match_0, prs3_match_1) node _T_7 = or(_T_6, prs3_match_2) node _T_8 = or(_T_7, prs3_match_3) when _T_8 : node _io_busy_resps_0_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_6 = mux(prs3_match_0, _io_busy_resps_0_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_7 = mux(prs3_match_1, _io_busy_resps_0_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_8 = mux(prs3_match_2, _io_busy_resps_0_prs3_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_9 = mux(prs3_match_3, _io_busy_resps_0_prs3_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_10 = or(_io_busy_resps_0_prs3_busy_T_6, _io_busy_resps_0_prs3_busy_T_7) node _io_busy_resps_0_prs3_busy_T_11 = or(_io_busy_resps_0_prs3_busy_T_10, _io_busy_resps_0_prs3_busy_T_8) node _io_busy_resps_0_prs3_busy_T_12 = or(_io_busy_resps_0_prs3_busy_T_11, _io_busy_resps_0_prs3_busy_T_9) wire _io_busy_resps_0_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs3_busy_WIRE, _io_busy_resps_0_prs3_busy_T_12 connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_WIRE connect io.busy_resps[0].prs3_busy, UInt<1>(0h0) node _prs1_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_0_1 = and(wakeups_0.valid, _prs1_match_T_4) node _prs1_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_1_1 = and(wakeups_1.valid, _prs1_match_T_5) node _prs1_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_2_1 = and(wakeups_2.valid, _prs1_match_T_6) node _prs1_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_3_1 = and(wakeups_3.valid, _prs1_match_T_7) node _prs2_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_0_1 = and(wakeups_0.valid, _prs2_match_T_4) node _prs2_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_1_1 = and(wakeups_1.valid, _prs2_match_T_5) node _prs2_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_2_1 = and(wakeups_2.valid, _prs2_match_T_6) node _prs2_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_3_1 = and(wakeups_3.valid, _prs2_match_T_7) node _prs3_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_0_1 = and(wakeups_0.valid, _prs3_match_T_4) node _prs3_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_1_1 = and(wakeups_1.valid, _prs3_match_T_5) node _prs3_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_2_1 = and(wakeups_2.valid, _prs3_match_T_6) node _prs3_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_3_1 = and(wakeups_3.valid, _prs3_match_T_7) node _io_busy_resps_1_prs1_busy_T = dshr(busy_table, io.ren_uops[1].prs1) node _io_busy_resps_1_prs1_busy_T_1 = bits(_io_busy_resps_1_prs1_busy_T, 0, 0) connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_T_1 node _io_busy_resps_1_prs2_busy_T = dshr(busy_table, io.ren_uops[1].prs2) node _io_busy_resps_1_prs2_busy_T_1 = bits(_io_busy_resps_1_prs2_busy_T, 0, 0) connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_T_1 node _io_busy_resps_1_prs3_busy_T = dshr(busy_table, io.ren_uops[1].prs3) node _io_busy_resps_1_prs3_busy_T_1 = bits(_io_busy_resps_1_prs3_busy_T, 0, 0) connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_T_1 node _T_9 = or(prs1_match_0_1, prs1_match_1_1) node _T_10 = or(_T_9, prs1_match_2_1) node _T_11 = or(_T_10, prs1_match_3_1) when _T_11 : node _io_busy_resps_1_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_6 = mux(prs1_match_0_1, _io_busy_resps_1_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_7 = mux(prs1_match_1_1, _io_busy_resps_1_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_8 = mux(prs1_match_2_1, _io_busy_resps_1_prs1_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_9 = mux(prs1_match_3_1, _io_busy_resps_1_prs1_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_10 = or(_io_busy_resps_1_prs1_busy_T_6, _io_busy_resps_1_prs1_busy_T_7) node _io_busy_resps_1_prs1_busy_T_11 = or(_io_busy_resps_1_prs1_busy_T_10, _io_busy_resps_1_prs1_busy_T_8) node _io_busy_resps_1_prs1_busy_T_12 = or(_io_busy_resps_1_prs1_busy_T_11, _io_busy_resps_1_prs1_busy_T_9) wire _io_busy_resps_1_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs1_busy_WIRE, _io_busy_resps_1_prs1_busy_T_12 connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_WIRE node _T_12 = or(prs2_match_0_1, prs2_match_1_1) node _T_13 = or(_T_12, prs2_match_2_1) node _T_14 = or(_T_13, prs2_match_3_1) when _T_14 : node _io_busy_resps_1_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_6 = mux(prs2_match_0_1, _io_busy_resps_1_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_7 = mux(prs2_match_1_1, _io_busy_resps_1_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_8 = mux(prs2_match_2_1, _io_busy_resps_1_prs2_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_9 = mux(prs2_match_3_1, _io_busy_resps_1_prs2_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_10 = or(_io_busy_resps_1_prs2_busy_T_6, _io_busy_resps_1_prs2_busy_T_7) node _io_busy_resps_1_prs2_busy_T_11 = or(_io_busy_resps_1_prs2_busy_T_10, _io_busy_resps_1_prs2_busy_T_8) node _io_busy_resps_1_prs2_busy_T_12 = or(_io_busy_resps_1_prs2_busy_T_11, _io_busy_resps_1_prs2_busy_T_9) wire _io_busy_resps_1_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs2_busy_WIRE, _io_busy_resps_1_prs2_busy_T_12 connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_WIRE node _T_15 = or(prs3_match_0_1, prs3_match_1_1) node _T_16 = or(_T_15, prs3_match_2_1) node _T_17 = or(_T_16, prs3_match_3_1) when _T_17 : node _io_busy_resps_1_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_6 = mux(prs3_match_0_1, _io_busy_resps_1_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_7 = mux(prs3_match_1_1, _io_busy_resps_1_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_8 = mux(prs3_match_2_1, _io_busy_resps_1_prs3_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_9 = mux(prs3_match_3_1, _io_busy_resps_1_prs3_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_10 = or(_io_busy_resps_1_prs3_busy_T_6, _io_busy_resps_1_prs3_busy_T_7) node _io_busy_resps_1_prs3_busy_T_11 = or(_io_busy_resps_1_prs3_busy_T_10, _io_busy_resps_1_prs3_busy_T_8) node _io_busy_resps_1_prs3_busy_T_12 = or(_io_busy_resps_1_prs3_busy_T_11, _io_busy_resps_1_prs3_busy_T_9) wire _io_busy_resps_1_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs3_busy_WIRE, _io_busy_resps_1_prs3_busy_T_12 connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_WIRE connect io.busy_resps[1].prs3_busy, UInt<1>(0h0) connect io.debug.busytable, busy_table	module RenameBusyTable( // @[rename-busytable.scala:27:7] input clock, // @[rename-busytable.scala:27:7] input reset, // @[rename-busytable.scala:27:7] input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_0_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_0_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_1_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_1_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_0, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_0_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_bypassable, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_speculative_mask, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_rebusy, // @[rename-busytable.scala:36:14] input io_wakeups_1_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_1_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_2_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_2_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_2_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_2_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_2_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_2_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_2_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_3_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_3_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_3_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_3_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_3_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_3_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_3_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input [1:0] io_child_rebusys // @[rename-busytable.scala:36:14] ); wire wakeups_3_valid; // @[rename-busytable.scala:47:18] wire wakeups_2_valid; // @[rename-busytable.scala:47:18] wire wakeups_1_valid; // @[rename-busytable.scala:47:18] wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_0_0 = io_ren_uops_0_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_1_0 = io_ren_uops_0_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_2_0 = io_ren_uops_0_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_3_0 = io_ren_uops_0_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_0_0 = io_ren_uops_0_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_1_0 = io_ren_uops_0_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_2_0 = io_ren_uops_0_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_3_0 = io_ren_uops_0_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_4_0 = io_ren_uops_0_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_5_0 = io_ren_uops_0_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_6_0 = io_ren_uops_0_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_7_0 = io_ren_uops_0_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_8_0 = io_ren_uops_0_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_9_0 = io_ren_uops_0_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_0 = io_ren_uops_0_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_agen_0 = io_ren_uops_0_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_dgen_0 = io_ren_uops_0_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p1_speculative_child_0 = io_ren_uops_0_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p2_speculative_child_0 = io_ren_uops_0_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p1_bypass_hint_0 = io_ren_uops_0_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p2_bypass_hint_0 = io_ren_uops_0_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p3_bypass_hint_0 = io_ren_uops_0_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dis_col_sel_0 = io_ren_uops_0_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_type_0 = io_ren_uops_0_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfence_0 = io_ren_uops_0_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_eret_0 = io_ren_uops_0_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rocc_0 = io_ren_uops_0_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_mov_0 = io_ren_uops_0_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_imm_rename_0 = io_ren_uops_0_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_imm_sel_0 = io_ren_uops_0_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_pimm_0 = io_ren_uops_0_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_op1_sel_0 = io_ren_uops_0_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_op2_sel_0 = io_ren_uops_0_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ldst_0 = io_ren_uops_0_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wen_0 = io_ren_uops_0_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren1_0 = io_ren_uops_0_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren2_0 = io_ren_uops_0_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren3_0 = io_ren_uops_0_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap12_0 = io_ren_uops_0_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap23_0 = io_ren_uops_0_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagIn_0 = io_ren_uops_0_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagOut_0 = io_ren_uops_0_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fromint_0 = io_ren_uops_0_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_toint_0 = io_ren_uops_0_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fastpipe_0 = io_ren_uops_0_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fma_0 = io_ren_uops_0_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_div_0 = io_ren_uops_0_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_sqrt_0 = io_ren_uops_0_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wflags_0 = io_ren_uops_0_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_vec_0 = io_ren_uops_0_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs3_0 = io_ren_uops_0_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_csr_cmd_0 = io_ren_uops_0_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fcn_dw_0 = io_ren_uops_0_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_fcn_op_0 = io_ren_uops_0_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_fp_rm_0 = io_ren_uops_0_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_typ_0 = io_ren_uops_0_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_0_0 = io_ren_uops_1_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_1_0 = io_ren_uops_1_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_2_0 = io_ren_uops_1_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_3_0 = io_ren_uops_1_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_0_0 = io_ren_uops_1_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_1_0 = io_ren_uops_1_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_2_0 = io_ren_uops_1_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_3_0 = io_ren_uops_1_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_4_0 = io_ren_uops_1_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_5_0 = io_ren_uops_1_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_6_0 = io_ren_uops_1_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_7_0 = io_ren_uops_1_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_8_0 = io_ren_uops_1_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_9_0 = io_ren_uops_1_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_0 = io_ren_uops_1_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_agen_0 = io_ren_uops_1_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_dgen_0 = io_ren_uops_1_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p1_speculative_child_0 = io_ren_uops_1_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p2_speculative_child_0 = io_ren_uops_1_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p1_bypass_hint_0 = io_ren_uops_1_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p2_bypass_hint_0 = io_ren_uops_1_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p3_bypass_hint_0 = io_ren_uops_1_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dis_col_sel_0 = io_ren_uops_1_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_type_0 = io_ren_uops_1_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfence_0 = io_ren_uops_1_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_eret_0 = io_ren_uops_1_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rocc_0 = io_ren_uops_1_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_mov_0 = io_ren_uops_1_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_imm_rename_0 = io_ren_uops_1_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_imm_sel_0 = io_ren_uops_1_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_pimm_0 = io_ren_uops_1_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_op1_sel_0 = io_ren_uops_1_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_op2_sel_0 = io_ren_uops_1_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ldst_0 = io_ren_uops_1_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wen_0 = io_ren_uops_1_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren1_0 = io_ren_uops_1_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren2_0 = io_ren_uops_1_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren3_0 = io_ren_uops_1_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap12_0 = io_ren_uops_1_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap23_0 = io_ren_uops_1_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagIn_0 = io_ren_uops_1_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagOut_0 = io_ren_uops_1_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fromint_0 = io_ren_uops_1_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_toint_0 = io_ren_uops_1_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fastpipe_0 = io_ren_uops_1_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fma_0 = io_ren_uops_1_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_div_0 = io_ren_uops_1_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_sqrt_0 = io_ren_uops_1_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wflags_0 = io_ren_uops_1_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_vec_0 = io_ren_uops_1_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs3_0 = io_ren_uops_1_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_csr_cmd_0 = io_ren_uops_1_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fcn_dw_0 = io_ren_uops_1_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_fcn_op_0 = io_ren_uops_1_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_fp_rm_0 = io_ren_uops_1_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_typ_0 = io_ren_uops_1_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_0_0 = io_wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_1_0 = io_wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_2_0 = io_wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_3_0 = io_wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_0_0 = io_wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_1_0 = io_wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_2_0 = io_wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_3_0 = io_wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_4_0 = io_wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_5_0 = io_wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_6_0 = io_wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_7_0 = io_wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_8_0 = io_wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_9_0 = io_wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_0 = io_wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dis_col_sel_0 = io_wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_type_0 = io_wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfence_0 = io_wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_eret_0 = io_wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rocc_0 = io_wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_mov_0 = io_wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_imm_rename_0 = io_wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_imm_sel_0 = io_wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_pimm_0 = io_wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_op1_sel_0 = io_wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_op2_sel_0 = io_wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wen_0 = io_wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_toint_0 = io_wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fma_0 = io_wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_div_0 = io_wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_vec_0 = io_wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0 = io_wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fcn_dw_0 = io_wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_fcn_op_0 = io_wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_fp_rm_0 = io_wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_typ_0 = io_wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_bypassable_0 = io_wakeups_0_bits_bypassable; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_speculative_mask_0 = io_wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_rebusy_0 = io_wakeups_0_bits_rebusy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_0_0 = io_wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_1_0 = io_wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_2_0 = io_wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_3_0 = io_wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_0_0 = io_wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_1_0 = io_wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_2_0 = io_wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_3_0 = io_wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_4_0 = io_wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_5_0 = io_wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_6_0 = io_wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_7_0 = io_wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_8_0 = io_wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_9_0 = io_wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_0 = io_wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dis_col_sel_0 = io_wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_type_0 = io_wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfence_0 = io_wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_eret_0 = io_wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rocc_0 = io_wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_mov_0 = io_wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_imm_rename_0 = io_wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_imm_sel_0 = io_wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_pimm_0 = io_wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_op1_sel_0 = io_wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_op2_sel_0 = io_wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wen_0 = io_wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_toint_0 = io_wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fma_0 = io_wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_div_0 = io_wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_vec_0 = io_wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0 = io_wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fcn_dw_0 = io_wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_fcn_op_0 = io_wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_fp_rm_0 = io_wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_typ_0 = io_wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_valid_0 = io_wakeups_2_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_2_bits_uop_inst_0 = io_wakeups_2_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_2_bits_uop_debug_inst_0 = io_wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_rvc_0 = io_wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_2_bits_uop_debug_pc_0 = io_wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_0_0 = io_wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_1_0 = io_wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_2_0 = io_wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_3_0 = io_wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_0_0 = io_wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_1_0 = io_wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_2_0 = io_wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_3_0 = io_wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_4_0 = io_wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_5_0 = io_wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_6_0 = io_wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_7_0 = io_wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_8_0 = io_wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_9_0 = io_wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_0 = io_wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_iw_p1_speculative_child_0 = io_wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_iw_p2_speculative_child_0 = io_wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_dis_col_sel_0 = io_wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_2_bits_uop_br_mask_0 = io_wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_br_tag_0 = io_wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_br_type_0 = io_wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sfb_0 = io_wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_fence_0 = io_wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_fencei_0 = io_wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sfence_0 = io_wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_amo_0 = io_wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_eret_0 = io_wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sys_pc2epc_0 = io_wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_rocc_0 = io_wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_mov_0 = io_wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_ftq_idx_0 = io_wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_edge_inst_0 = io_wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_pc_lob_0 = io_wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_taken_0 = io_wakeups_2_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_imm_rename_0 = io_wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_imm_sel_0 = io_wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_pimm_0 = io_wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_2_bits_uop_imm_packed_0 = io_wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_op1_sel_0 = io_wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_op2_sel_0 = io_wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ldst_0 = io_wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_wen_0 = io_wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren1_0 = io_wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren2_0 = io_wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren3_0 = io_wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_swap12_0 = io_wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_swap23_0 = io_wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fromint_0 = io_wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_toint_0 = io_wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fma_0 = io_wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_div_0 = io_wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_wflags_0 = io_wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_vec_0 = io_wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_rob_idx_0 = io_wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_ldq_idx_0 = io_wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_stq_idx_0 = io_wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_rxq_idx_0 = io_wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_pdst_0 = io_wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs1_0 = io_wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs2_0 = io_wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs3_0 = io_wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_ppred_0 = io_wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs1_busy_0 = io_wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs2_busy_0 = io_wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs3_busy_0 = io_wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_ppred_busy_0 = io_wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_stale_pdst_0 = io_wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_exception_0 = io_wakeups_2_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_2_bits_uop_exc_cause_0 = io_wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_mem_cmd_0 = io_wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_mem_size_0 = io_wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_mem_signed_0 = io_wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_uses_ldq_0 = io_wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_uses_stq_0 = io_wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_unique_0 = io_wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_flush_on_commit_0 = io_wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_csr_cmd_0 = io_wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_ldst_is_rs1_0 = io_wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_ldst_0 = io_wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs1_0 = io_wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs2_0 = io_wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs3_0 = io_wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_dst_rtype_0 = io_wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_lrs1_rtype_0 = io_wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_lrs2_rtype_0 = io_wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_frs3_en_0 = io_wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fcn_dw_0 = io_wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_fcn_op_0 = io_wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_val_0 = io_wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_fp_rm_0 = io_wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_typ_0 = io_wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_pf_if_0 = io_wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_ae_if_0 = io_wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_ma_if_0 = io_wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_bp_debug_if_0 = io_wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_bp_xcpt_if_0 = io_wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_debug_fsrc_0 = io_wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_debug_tsrc_0 = io_wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_valid_0 = io_wakeups_3_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_3_bits_uop_inst_0 = io_wakeups_3_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_3_bits_uop_debug_inst_0 = io_wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_rvc_0 = io_wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_3_bits_uop_debug_pc_0 = io_wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_0_0 = io_wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_1_0 = io_wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_2_0 = io_wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_3_0 = io_wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_0_0 = io_wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_1_0 = io_wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_2_0 = io_wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_3_0 = io_wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_4_0 = io_wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_5_0 = io_wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_6_0 = io_wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_7_0 = io_wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_8_0 = io_wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_9_0 = io_wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_0 = io_wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_iw_p1_speculative_child_0 = io_wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_iw_p2_speculative_child_0 = io_wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_dis_col_sel_0 = io_wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_3_bits_uop_br_mask_0 = io_wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_br_tag_0 = io_wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_br_type_0 = io_wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sfb_0 = io_wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_fence_0 = io_wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_fencei_0 = io_wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sfence_0 = io_wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_amo_0 = io_wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_eret_0 = io_wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sys_pc2epc_0 = io_wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_rocc_0 = io_wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_mov_0 = io_wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_ftq_idx_0 = io_wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_edge_inst_0 = io_wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_pc_lob_0 = io_wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_taken_0 = io_wakeups_3_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_imm_rename_0 = io_wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_imm_sel_0 = io_wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_pimm_0 = io_wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_3_bits_uop_imm_packed_0 = io_wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_op1_sel_0 = io_wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_op2_sel_0 = io_wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ldst_0 = io_wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_wen_0 = io_wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren1_0 = io_wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren2_0 = io_wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren3_0 = io_wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_swap12_0 = io_wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_swap23_0 = io_wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fromint_0 = io_wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_toint_0 = io_wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fma_0 = io_wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_div_0 = io_wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_wflags_0 = io_wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_vec_0 = io_wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_rob_idx_0 = io_wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_ldq_idx_0 = io_wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_stq_idx_0 = io_wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_rxq_idx_0 = io_wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_pdst_0 = io_wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs1_0 = io_wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs2_0 = io_wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs3_0 = io_wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_ppred_0 = io_wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs1_busy_0 = io_wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs2_busy_0 = io_wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs3_busy_0 = io_wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_ppred_busy_0 = io_wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_stale_pdst_0 = io_wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_exception_0 = io_wakeups_3_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_3_bits_uop_exc_cause_0 = io_wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_mem_cmd_0 = io_wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_mem_size_0 = io_wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_mem_signed_0 = io_wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_uses_ldq_0 = io_wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_uses_stq_0 = io_wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_unique_0 = io_wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_flush_on_commit_0 = io_wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_csr_cmd_0 = io_wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_ldst_is_rs1_0 = io_wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_ldst_0 = io_wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs1_0 = io_wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs2_0 = io_wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs3_0 = io_wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_dst_rtype_0 = io_wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_lrs1_rtype_0 = io_wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_lrs2_rtype_0 = io_wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_frs3_en_0 = io_wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fcn_dw_0 = io_wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_fcn_op_0 = io_wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_val_0 = io_wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_fp_rm_0 = io_wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_typ_0 = io_wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_pf_if_0 = io_wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_ae_if_0 = io_wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_ma_if_0 = io_wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_bp_debug_if_0 = io_wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_bp_xcpt_if_0 = io_wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_debug_fsrc_0 = io_wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_debug_tsrc_0 = io_wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:47:18] wire [1:0] _wakeups_wu_valid_T_3 = 2'h0; // @[rename-busytable.scala:48:72] wire [1:0] io_wakeups_2_bits_speculative_mask = 2'h1; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_2_bits_speculative_mask = 2'h1; // @[rename-busytable.scala:47:18] wire [1:0] io_wakeups_3_bits_speculative_mask = 2'h2; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_3_bits_speculative_mask = 2'h2; // @[rename-busytable.scala:47:18] wire io_wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_4 = 1'h1; // @[rename-busytable.scala:48:92] wire wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18] wire _busy_table_wb_T_6 = 1'h1; // @[rename-busytable.scala:56:59] wire _busy_table_wb_T_11 = 1'h1; // @[rename-busytable.scala:56:59] wire _busy_table_wb_T_16 = 1'h1; // @[rename-busytable.scala:56:59] wire [79:0] _busy_table_next_T_14 = 80'h0; // @[rename-busytable.scala:63:37] wire [79:0] _busy_table_next_T_18 = 80'h0; // @[rename-busytable.scala:63:37] wire [79:0] _busy_table_next_T_22 = 80'h0; // @[rename-busytable.scala:63:37] wire [127:0] _busy_table_next_T_15 = 128'h0; // @[rename-busytable.scala:63:31] wire [127:0] _busy_table_next_T_19 = 128'h0; // @[rename-busytable.scala:63:31] wire [127:0] _busy_table_next_T_23 = 128'h0; // @[rename-busytable.scala:63:31] wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire _busy_table_next_T_13 = 1'h0; // @[rename-busytable.scala:63:56] wire _busy_table_next_T_17 = 1'h0; // @[rename-busytable.scala:63:56] wire _busy_table_next_T_21 = 1'h0; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] wire [79:0] io_debug_busytable; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_2; // @[rename-busytable.scala:48:34] wire wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_bypassable; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18] wire wakeups_0_valid; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG; // @[rename-busytable.scala:48:24] reg [1:0] wakeups_wu_valid_REG_1; // @[rename-busytable.scala:48:46] wire [1:0] _wakeups_wu_valid_T = wakeups_wu_valid_REG_1 & io_child_rebusys_0; // @[rename-busytable.scala:27:7, :48:{46,72}] wire _wakeups_wu_valid_T_1 = _wakeups_wu_valid_T == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_2 = wakeups_wu_valid_REG & _wakeups_wu_valid_T_1; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_0_valid = _wakeups_wu_valid_T_2; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_inst = wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_inst = wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rvc = wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_pc = wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_0 = wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_1 = wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_2 = wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_3 = wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_0 = wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_1 = wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_2 = wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_3 = wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_4 = wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_5 = wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_6 = wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_7 = wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_8 = wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_9 = wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued = wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dis_col_sel = wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_mask = wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_tag = wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_type = wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfb = wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fence = wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fencei = wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfence = wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_amo = wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_eret = wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rocc = wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_mov = wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ftq_idx = wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_edge_inst = wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pc_lob = wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_taken = wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_rename = wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_sel = wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pimm = wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_packed = wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op1_sel = wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op2_sel = wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rob_idx = wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldq_idx = wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stq_idx = wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rxq_idx = wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pdst = wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1 = wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2 = wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3 = wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred = wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1_busy = wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2_busy = wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3_busy = wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred_busy = wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stale_pdst = wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exception = wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exc_cause = wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_cmd = wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_size = wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_signed = wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_ldq = wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_stq = wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_unique = wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_flush_on_commit = wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_csr_cmd = wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst = wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1 = wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2 = wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs3 = wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dst_rtype = wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_frs3_en = wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_dw = wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_op = wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_val = wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_rm = wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_typ = wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_debug_if = wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_fsrc = wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_tsrc = wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_bypassable = wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_speculative_mask = wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_rebusy = wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_5; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_7 = wakeups_1_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:24] assign _wakeups_wu_valid_T_5 = wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:{24,34}] assign wakeups_1_valid = _wakeups_wu_valid_T_5; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_inst = wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_inst = wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rvc = wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_pc = wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_0 = wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_1 = wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_2 = wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_3 = wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_0 = wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_1 = wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_2 = wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_3 = wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_4 = wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_5 = wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_6 = wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_7 = wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_8 = wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_9 = wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued = wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dis_col_sel = wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_mask = wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_tag = wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_type = wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfb = wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fence = wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fencei = wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfence = wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_amo = wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_eret = wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rocc = wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_mov = wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ftq_idx = wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_edge_inst = wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pc_lob = wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_taken = wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_rename = wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_sel = wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pimm = wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_packed = wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op1_sel = wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op2_sel = wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rob_idx = wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldq_idx = wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stq_idx = wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rxq_idx = wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pdst = wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1 = wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2 = wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3 = wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred = wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1_busy = wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2_busy = wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3_busy = wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred_busy = wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stale_pdst = wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exception = wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exc_cause = wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_cmd = wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_size = wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_signed = wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_ldq = wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_stq = wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_unique = wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_flush_on_commit = wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_csr_cmd = wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst = wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1 = wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2 = wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs3 = wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dst_rtype = wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_frs3_en = wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_dw = wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_op = wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_val = wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_rm = wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_typ = wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_debug_if = wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_fsrc = wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_tsrc = wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_8; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_12 = wakeups_2_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_2_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_4; // @[rename-busytable.scala:48:24] wire [1:0] _wakeups_wu_valid_T_6 = io_child_rebusys_0 & 2'h1; // @[rename-busytable.scala:27:7, :48:72] wire _wakeups_wu_valid_T_7 = _wakeups_wu_valid_T_6 == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_8 = wakeups_wu_valid_REG_4 & _wakeups_wu_valid_T_7; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_2_valid = _wakeups_wu_valid_T_8; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_inst = wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_inst = wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_rvc = wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_pc = wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_0 = wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_1 = wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_2 = wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_3 = wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_0 = wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_1 = wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_2 = wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_3 = wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_4 = wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_5 = wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_6 = wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_7 = wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_8 = wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_9 = wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued = wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_dis_col_sel = wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_mask = wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_tag = wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_type = wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sfb = wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_fence = wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_fencei = wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sfence = wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_amo = wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_eret = wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_rocc = wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_mov = wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ftq_idx = wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_edge_inst = wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pc_lob = wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_taken = wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_rename = wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_sel = wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pimm = wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_packed = wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_op1_sel = wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_op2_sel = wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_rob_idx = wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldq_idx = wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_stq_idx = wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_rxq_idx = wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pdst = wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs1 = wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs2 = wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs3 = wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ppred = wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs1_busy = wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs2_busy = wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs3_busy = wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ppred_busy = wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_stale_pdst = wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_exception = wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_exc_cause = wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_cmd = wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_size = wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_signed = wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_uses_ldq = wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_uses_stq = wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_unique = wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_flush_on_commit = wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_csr_cmd = wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldst = wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs1 = wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs2 = wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs3 = wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_dst_rtype = wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_frs3_en = wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fcn_dw = wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fcn_op = wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_val = wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_rm = wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_typ = wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_bp_debug_if = wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_fsrc = wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_tsrc = wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_11; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_17 = wakeups_3_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_3_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_6; // @[rename-busytable.scala:48:24] wire [1:0] _wakeups_wu_valid_T_9 = io_child_rebusys_0 & 2'h2; // @[rename-busytable.scala:27:7, :48:72] wire _wakeups_wu_valid_T_10 = _wakeups_wu_valid_T_9 == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_11 = wakeups_wu_valid_REG_6 & _wakeups_wu_valid_T_10; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_3_valid = _wakeups_wu_valid_T_11; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_inst = wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_inst = wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_rvc = wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_pc = wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_0 = wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_1 = wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_2 = wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_3 = wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_0 = wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_1 = wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_2 = wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_3 = wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_4 = wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_5 = wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_6 = wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_7 = wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_8 = wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_9 = wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued = wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_dis_col_sel = wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_mask = wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_tag = wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_type = wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sfb = wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_fence = wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_fencei = wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sfence = wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_amo = wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_eret = wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_rocc = wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_mov = wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ftq_idx = wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_edge_inst = wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pc_lob = wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_taken = wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_rename = wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_sel = wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pimm = wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_packed = wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_op1_sel = wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_op2_sel = wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_rob_idx = wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldq_idx = wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_stq_idx = wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_rxq_idx = wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pdst = wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs1 = wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs2 = wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs3 = wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ppred = wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs1_busy = wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs2_busy = wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs3_busy = wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ppred_busy = wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_stale_pdst = wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_exception = wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_exc_cause = wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_cmd = wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_size = wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_signed = wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_uses_ldq = wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_uses_stq = wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_unique = wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_flush_on_commit = wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_csr_cmd = wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldst = wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs1 = wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs2 = wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs3 = wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_dst_rtype = wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_frs3_en = wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fcn_dw = wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fcn_op = wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_val = wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_rm = wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_typ = wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_bp_debug_if = wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_fsrc = wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_tsrc = wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg [79:0] busy_table; // @[rename-busytable.scala:53:27] assign io_debug_busytable = busy_table; // @[rename-busytable.scala:27:7, :53:27] wire [127:0] _GEN = 128'h1 << wakeups_0_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T; // @[OneHot.scala:58:35] assign _busy_table_wb_T = _GEN; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_8; // @[OneHot.scala:58:35] assign _busy_table_next_T_8 = _GEN; // @[OneHot.scala:58:35] wire _busy_table_wb_T_1 = ~wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :56:59] wire _busy_table_wb_T_2 = wakeups_0_valid & _busy_table_wb_T_1; // @[rename-busytable.scala:47:18, :56:{56,59}] wire [79:0] _busy_table_wb_T_3 = {80{_busy_table_wb_T_2}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_4 = {48'h0, _busy_table_wb_T[79:0] & _busy_table_wb_T_3}; // @[OneHot.scala:58:35] wire [127:0] _GEN_0 = 128'h1 << wakeups_1_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_5; // @[OneHot.scala:58:35] assign _busy_table_wb_T_5 = _GEN_0; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_12; // @[OneHot.scala:58:35] assign _busy_table_next_T_12 = _GEN_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_8 = {80{_busy_table_wb_T_7}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_9 = {48'h0, _busy_table_wb_T_5[79:0] & _busy_table_wb_T_8}; // @[OneHot.scala:58:35] wire [127:0] _GEN_1 = 128'h1 << wakeups_2_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_10; // @[OneHot.scala:58:35] assign _busy_table_wb_T_10 = _GEN_1; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_16; // @[OneHot.scala:58:35] assign _busy_table_next_T_16 = _GEN_1; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_13 = {80{_busy_table_wb_T_12}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_14 = {48'h0, _busy_table_wb_T_10[79:0] & _busy_table_wb_T_13}; // @[OneHot.scala:58:35] wire [127:0] _GEN_2 = 128'h1 << wakeups_3_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_15; // @[OneHot.scala:58:35] assign _busy_table_wb_T_15 = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_20; // @[OneHot.scala:58:35] assign _busy_table_next_T_20 = _GEN_2; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_18 = {80{_busy_table_wb_T_17}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_19 = {48'h0, _busy_table_wb_T_15[79:0] & _busy_table_wb_T_18}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_20 = _busy_table_wb_T_4 \| _busy_table_wb_T_9; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_21 = _busy_table_wb_T_20 \| _busy_table_wb_T_14; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_22 = _busy_table_wb_T_21 \| _busy_table_wb_T_19; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_23 = ~_busy_table_wb_T_22; // @[rename-busytable.scala:55:36, :57:14] wire [127:0] busy_table_wb = {48'h0, _busy_table_wb_T_23[79:0] & busy_table}; // @[rename-busytable.scala:53:27, :55:{34,36}, :56:31] wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_next_T_1 = {80{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_2 = {48'h0, _busy_table_next_T[79:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_next_T_4 = {80{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_5 = {48'h0, _busy_table_next_T_3[79:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_6 = _busy_table_next_T_2 \| _busy_table_next_T_5; // @[rename-busytable.scala:61:{51,82}] wire [127:0] _busy_table_next_T_7 = busy_table_wb \| _busy_table_next_T_6; // @[rename-busytable.scala:55:34, :59:39, :61:82] wire _GEN_3 = wakeups_0_valid & wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :63:56] wire _busy_table_next_T_9; // @[rename-busytable.scala:63:56] assign _busy_table_next_T_9 = _GEN_3; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_0_prs1_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_0_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_0_prs2_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_0_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_0_prs3_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :85:82] wire _io_busy_resps_1_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_1_prs1_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_1_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_1_prs2_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_1_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_1_prs3_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :85:82] wire [79:0] _busy_table_next_T_10 = {80{_busy_table_next_T_9}}; // @[rename-busytable.scala:63:{37,56}] wire [127:0] _busy_table_next_T_11 = {48'h0, _busy_table_next_T_8[79:0] & _busy_table_next_T_10}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_24 = _busy_table_next_T_11; // @[rename-busytable.scala:63:31, :64:14] wire [127:0] _busy_table_next_T_25 = _busy_table_next_T_24; // @[rename-busytable.scala:64:14] wire [127:0] _busy_table_next_T_26 = _busy_table_next_T_25; // @[rename-busytable.scala:64:14] wire [127:0] busy_table_next = _busy_table_next_T_7 \| _busy_table_next_T_26; // @[rename-busytable.scala:59:39, :62:5, :64:14] wire _prs1_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0 = wakeups_0_valid & _prs1_match_T; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1 = wakeups_1_valid & _prs1_match_T_1; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_2 = wakeups_2_valid & _prs1_match_T_2; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_3 = wakeups_3_valid & _prs1_match_T_3; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0 = wakeups_0_valid & _prs2_match_T; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1 = wakeups_1_valid & _prs2_match_T_1; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_2 = wakeups_2_valid & _prs2_match_T_2; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_3 = wakeups_3_valid & _prs2_match_T_3; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0 = wakeups_0_valid & _prs3_match_T; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1 = wakeups_1_valid & _prs3_match_T_1; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_2 = wakeups_2_valid & _prs3_match_T_2; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_3 = wakeups_3_valid & _prs3_match_T_3; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [79:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [79:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [79:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_0_prs1_busy_T_6 = prs1_match_0 & _io_busy_resps_0_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_10 = _io_busy_resps_0_prs1_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_11 = _io_busy_resps_0_prs1_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_12 = _io_busy_resps_0_prs1_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_WIRE = _io_busy_resps_0_prs1_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_0_prs1_busy_0 = prs1_match_0 \| prs1_match_1 \| prs1_match_2 \| prs1_match_3 ? _io_busy_resps_0_prs1_busy_WIRE : _io_busy_resps_0_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_6 = prs2_match_0 & _io_busy_resps_0_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_10 = _io_busy_resps_0_prs2_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_11 = _io_busy_resps_0_prs2_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_12 = _io_busy_resps_0_prs2_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_WIRE = _io_busy_resps_0_prs2_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_0_prs2_busy_0 = prs2_match_0 \| prs2_match_1 \| prs2_match_2 \| prs2_match_3 ? _io_busy_resps_0_prs2_busy_WIRE : _io_busy_resps_0_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_6 = prs3_match_0 & _io_busy_resps_0_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_10 = _io_busy_resps_0_prs3_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_11 = _io_busy_resps_0_prs3_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_12 = _io_busy_resps_0_prs3_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_WIRE = _io_busy_resps_0_prs3_busy_T_12; // @[Mux.scala:30:73] wire _prs1_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0_1 = wakeups_0_valid & _prs1_match_T_4; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1_1 = wakeups_1_valid & _prs1_match_T_5; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_2_1 = wakeups_2_valid & _prs1_match_T_6; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_3_1 = wakeups_3_valid & _prs1_match_T_7; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0_1 = wakeups_0_valid & _prs2_match_T_4; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1_1 = wakeups_1_valid & _prs2_match_T_5; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_2_1 = wakeups_2_valid & _prs2_match_T_6; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_3_1 = wakeups_3_valid & _prs2_match_T_7; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0_1 = wakeups_0_valid & _prs3_match_T_4; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1_1 = wakeups_1_valid & _prs3_match_T_5; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_2_1 = wakeups_2_valid & _prs3_match_T_6; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_3_1 = wakeups_3_valid & _prs3_match_T_7; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [79:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [79:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [79:0] _io_busy_resps_1_prs3_busy_T = busy_table >> io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_1_prs1_busy_T_6 = prs1_match_0_1 & _io_busy_resps_1_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_10 = _io_busy_resps_1_prs1_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_11 = _io_busy_resps_1_prs1_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_12 = _io_busy_resps_1_prs1_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_WIRE = _io_busy_resps_1_prs1_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_1_prs1_busy_0 = prs1_match_0_1 \| prs1_match_1_1 \| prs1_match_2_1 \| prs1_match_3_1 ? _io_busy_resps_1_prs1_busy_WIRE : _io_busy_resps_1_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_6 = prs2_match_0_1 & _io_busy_resps_1_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_10 = _io_busy_resps_1_prs2_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_11 = _io_busy_resps_1_prs2_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_12 = _io_busy_resps_1_prs2_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_WIRE = _io_busy_resps_1_prs2_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_1_prs2_busy_0 = prs2_match_0_1 \| prs2_match_1_1 \| prs2_match_2_1 \| prs2_match_3_1 ? _io_busy_resps_1_prs2_busy_WIRE : _io_busy_resps_1_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_6 = prs3_match_0_1 & _io_busy_resps_1_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_10 = _io_busy_resps_1_prs3_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_11 = _io_busy_resps_1_prs3_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_12 = _io_busy_resps_1_prs3_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_WIRE = _io_busy_resps_1_prs3_busy_T_12; // @[Mux.scala:30:73] always @(posedge clock) begin // @[rename-busytable.scala:27:7] wakeups_wu_valid_REG <= io_wakeups_0_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_valid_REG_1 <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :48:46] wakeups_wu_bits_REG_uop_inst <= io_wakeups_0_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_inst <= io_wakeups_0_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rvc <= io_wakeups_0_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_pc <= io_wakeups_0_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_0 <= io_wakeups_0_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_1 <= io_wakeups_0_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_2 <= io_wakeups_0_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_3 <= io_wakeups_0_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_0 <= io_wakeups_0_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_1 <= io_wakeups_0_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_2 <= io_wakeups_0_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_3 <= io_wakeups_0_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_4 <= io_wakeups_0_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_5 <= io_wakeups_0_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_6 <= io_wakeups_0_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_7 <= io_wakeups_0_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_8 <= io_wakeups_0_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_9 <= io_wakeups_0_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued <= io_wakeups_0_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_agen <= io_wakeups_0_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_dgen <= io_wakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_speculative_child <= io_wakeups_0_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_speculative_child <= io_wakeups_0_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_bypass_hint <= io_wakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_bypass_hint <= io_wakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p3_bypass_hint <= io_wakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dis_col_sel <= io_wakeups_0_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_mask <= io_wakeups_0_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_tag <= io_wakeups_0_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_type <= io_wakeups_0_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfb <= io_wakeups_0_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fence <= io_wakeups_0_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fencei <= io_wakeups_0_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfence <= io_wakeups_0_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_amo <= io_wakeups_0_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_eret <= io_wakeups_0_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sys_pc2epc <= io_wakeups_0_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rocc <= io_wakeups_0_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_mov <= io_wakeups_0_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ftq_idx <= io_wakeups_0_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_edge_inst <= io_wakeups_0_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pc_lob <= io_wakeups_0_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_taken <= io_wakeups_0_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_rename <= io_wakeups_0_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_sel <= io_wakeups_0_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pimm <= io_wakeups_0_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_packed <= io_wakeups_0_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op1_sel <= io_wakeups_0_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op2_sel <= io_wakeups_0_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ldst <= io_wakeups_0_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wen <= io_wakeups_0_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren1 <= io_wakeups_0_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren2 <= io_wakeups_0_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren3 <= io_wakeups_0_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap12 <= io_wakeups_0_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap23 <= io_wakeups_0_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn <= io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut <= io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fromint <= io_wakeups_0_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_toint <= io_wakeups_0_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe <= io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fma <= io_wakeups_0_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_div <= io_wakeups_0_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_sqrt <= io_wakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wflags <= io_wakeups_0_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_vec <= io_wakeups_0_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rob_idx <= io_wakeups_0_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldq_idx <= io_wakeups_0_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stq_idx <= io_wakeups_0_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rxq_idx <= io_wakeups_0_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pdst <= io_wakeups_0_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1 <= io_wakeups_0_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2 <= io_wakeups_0_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3 <= io_wakeups_0_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred <= io_wakeups_0_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1_busy <= io_wakeups_0_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2_busy <= io_wakeups_0_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3_busy <= io_wakeups_0_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred_busy <= io_wakeups_0_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stale_pdst <= io_wakeups_0_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exception <= io_wakeups_0_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exc_cause <= io_wakeups_0_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_cmd <= io_wakeups_0_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_size <= io_wakeups_0_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_signed <= io_wakeups_0_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_ldq <= io_wakeups_0_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_stq <= io_wakeups_0_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_unique <= io_wakeups_0_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_flush_on_commit <= io_wakeups_0_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_csr_cmd <= io_wakeups_0_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst_is_rs1 <= io_wakeups_0_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst <= io_wakeups_0_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1 <= io_wakeups_0_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2 <= io_wakeups_0_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs3 <= io_wakeups_0_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dst_rtype <= io_wakeups_0_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1_rtype <= io_wakeups_0_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2_rtype <= io_wakeups_0_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_frs3_en <= io_wakeups_0_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_dw <= io_wakeups_0_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_op <= io_wakeups_0_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_val <= io_wakeups_0_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_rm <= io_wakeups_0_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_typ <= io_wakeups_0_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_pf_if <= io_wakeups_0_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ae_if <= io_wakeups_0_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ma_if <= io_wakeups_0_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_debug_if <= io_wakeups_0_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_xcpt_if <= io_wakeups_0_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_fsrc <= io_wakeups_0_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_tsrc <= io_wakeups_0_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_bypassable <= io_wakeups_0_bits_bypassable_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_speculative_mask <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_rebusy <= io_wakeups_0_bits_rebusy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_2 <= io_wakeups_1_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_1_uop_inst <= io_wakeups_1_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_inst <= io_wakeups_1_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rvc <= io_wakeups_1_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_pc <= io_wakeups_1_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_0 <= io_wakeups_1_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_1 <= io_wakeups_1_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_2 <= io_wakeups_1_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_3 <= io_wakeups_1_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_0 <= io_wakeups_1_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_1 <= io_wakeups_1_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_2 <= io_wakeups_1_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_3 <= io_wakeups_1_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_4 <= io_wakeups_1_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_5 <= io_wakeups_1_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_6 <= io_wakeups_1_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_7 <= io_wakeups_1_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_8 <= io_wakeups_1_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_9 <= io_wakeups_1_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued <= io_wakeups_1_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen <= io_wakeups_1_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen <= io_wakeups_1_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child <= io_wakeups_1_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child <= io_wakeups_1_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint <= io_wakeups_1_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint <= io_wakeups_1_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint <= io_wakeups_1_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dis_col_sel <= io_wakeups_1_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_mask <= io_wakeups_1_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_tag <= io_wakeups_1_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_type <= io_wakeups_1_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfb <= io_wakeups_1_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fence <= io_wakeups_1_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fencei <= io_wakeups_1_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfence <= io_wakeups_1_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_amo <= io_wakeups_1_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_eret <= io_wakeups_1_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sys_pc2epc <= io_wakeups_1_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rocc <= io_wakeups_1_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_mov <= io_wakeups_1_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ftq_idx <= io_wakeups_1_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_edge_inst <= io_wakeups_1_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pc_lob <= io_wakeups_1_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_taken <= io_wakeups_1_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_rename <= io_wakeups_1_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_sel <= io_wakeups_1_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pimm <= io_wakeups_1_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_packed <= io_wakeups_1_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op1_sel <= io_wakeups_1_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op2_sel <= io_wakeups_1_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst <= io_wakeups_1_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wen <= io_wakeups_1_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1 <= io_wakeups_1_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2 <= io_wakeups_1_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3 <= io_wakeups_1_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12 <= io_wakeups_1_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23 <= io_wakeups_1_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn <= io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut <= io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint <= io_wakeups_1_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_toint <= io_wakeups_1_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe <= io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fma <= io_wakeups_1_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_div <= io_wakeups_1_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt <= io_wakeups_1_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags <= io_wakeups_1_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_vec <= io_wakeups_1_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rob_idx <= io_wakeups_1_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldq_idx <= io_wakeups_1_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stq_idx <= io_wakeups_1_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rxq_idx <= io_wakeups_1_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pdst <= io_wakeups_1_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1 <= io_wakeups_1_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2 <= io_wakeups_1_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3 <= io_wakeups_1_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred <= io_wakeups_1_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1_busy <= io_wakeups_1_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2_busy <= io_wakeups_1_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3_busy <= io_wakeups_1_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred_busy <= io_wakeups_1_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stale_pdst <= io_wakeups_1_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exception <= io_wakeups_1_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exc_cause <= io_wakeups_1_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_cmd <= io_wakeups_1_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_size <= io_wakeups_1_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_signed <= io_wakeups_1_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_ldq <= io_wakeups_1_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_stq <= io_wakeups_1_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_unique <= io_wakeups_1_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_flush_on_commit <= io_wakeups_1_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_csr_cmd <= io_wakeups_1_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst_is_rs1 <= io_wakeups_1_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst <= io_wakeups_1_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1 <= io_wakeups_1_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2 <= io_wakeups_1_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs3 <= io_wakeups_1_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dst_rtype <= io_wakeups_1_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1_rtype <= io_wakeups_1_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2_rtype <= io_wakeups_1_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_frs3_en <= io_wakeups_1_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_dw <= io_wakeups_1_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_op <= io_wakeups_1_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_val <= io_wakeups_1_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_rm <= io_wakeups_1_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_typ <= io_wakeups_1_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_pf_if <= io_wakeups_1_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ae_if <= io_wakeups_1_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ma_if <= io_wakeups_1_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_debug_if <= io_wakeups_1_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_xcpt_if <= io_wakeups_1_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_fsrc <= io_wakeups_1_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_tsrc <= io_wakeups_1_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_4 <= io_wakeups_2_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_2_uop_inst <= io_wakeups_2_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_inst <= io_wakeups_2_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_rvc <= io_wakeups_2_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_pc <= io_wakeups_2_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_0 <= io_wakeups_2_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_1 <= io_wakeups_2_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_2 <= io_wakeups_2_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_3 <= io_wakeups_2_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_0 <= io_wakeups_2_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_1 <= io_wakeups_2_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_2 <= io_wakeups_2_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_3 <= io_wakeups_2_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_4 <= io_wakeups_2_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_5 <= io_wakeups_2_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_6 <= io_wakeups_2_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_7 <= io_wakeups_2_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_8 <= io_wakeups_2_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_9 <= io_wakeups_2_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_issued <= io_wakeups_2_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child <= io_wakeups_2_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child <= io_wakeups_2_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint <= io_wakeups_2_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint <= io_wakeups_2_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint <= io_wakeups_2_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_dis_col_sel <= io_wakeups_2_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_mask <= io_wakeups_2_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_tag <= io_wakeups_2_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_type <= io_wakeups_2_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sfb <= io_wakeups_2_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_fence <= io_wakeups_2_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_fencei <= io_wakeups_2_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sfence <= io_wakeups_2_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_amo <= io_wakeups_2_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_eret <= io_wakeups_2_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sys_pc2epc <= io_wakeups_2_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_rocc <= io_wakeups_2_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_mov <= io_wakeups_2_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ftq_idx <= io_wakeups_2_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_edge_inst <= io_wakeups_2_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pc_lob <= io_wakeups_2_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_taken <= io_wakeups_2_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_rename <= io_wakeups_2_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_sel <= io_wakeups_2_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pimm <= io_wakeups_2_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_packed <= io_wakeups_2_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_op1_sel <= io_wakeups_2_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_op2_sel <= io_wakeups_2_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst <= io_wakeups_2_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_wen <= io_wakeups_2_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1 <= io_wakeups_2_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2 <= io_wakeups_2_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3 <= io_wakeups_2_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12 <= io_wakeups_2_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23 <= io_wakeups_2_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn <= io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut <= io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint <= io_wakeups_2_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_toint <= io_wakeups_2_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe <= io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fma <= io_wakeups_2_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_div <= io_wakeups_2_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt <= io_wakeups_2_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags <= io_wakeups_2_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_vec <= io_wakeups_2_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_rob_idx <= io_wakeups_2_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldq_idx <= io_wakeups_2_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_stq_idx <= io_wakeups_2_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_rxq_idx <= io_wakeups_2_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pdst <= io_wakeups_2_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs1 <= io_wakeups_2_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs2 <= io_wakeups_2_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs3 <= io_wakeups_2_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ppred <= io_wakeups_2_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs1_busy <= io_wakeups_2_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs2_busy <= io_wakeups_2_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs3_busy <= io_wakeups_2_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ppred_busy <= io_wakeups_2_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_stale_pdst <= io_wakeups_2_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_exception <= io_wakeups_2_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_exc_cause <= io_wakeups_2_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_cmd <= io_wakeups_2_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_size <= io_wakeups_2_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_signed <= io_wakeups_2_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_uses_ldq <= io_wakeups_2_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_uses_stq <= io_wakeups_2_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_unique <= io_wakeups_2_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_flush_on_commit <= io_wakeups_2_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_csr_cmd <= io_wakeups_2_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldst_is_rs1 <= io_wakeups_2_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldst <= io_wakeups_2_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs1 <= io_wakeups_2_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs2 <= io_wakeups_2_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs3 <= io_wakeups_2_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_dst_rtype <= io_wakeups_2_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs1_rtype <= io_wakeups_2_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs2_rtype <= io_wakeups_2_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_frs3_en <= io_wakeups_2_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fcn_dw <= io_wakeups_2_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fcn_op <= io_wakeups_2_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_val <= io_wakeups_2_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_rm <= io_wakeups_2_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_typ <= io_wakeups_2_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_pf_if <= io_wakeups_2_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_ae_if <= io_wakeups_2_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_ma_if <= io_wakeups_2_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_bp_debug_if <= io_wakeups_2_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_bp_xcpt_if <= io_wakeups_2_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_fsrc <= io_wakeups_2_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_tsrc <= io_wakeups_2_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_6 <= io_wakeups_3_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_3_uop_inst <= io_wakeups_3_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_inst <= io_wakeups_3_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_rvc <= io_wakeups_3_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_pc <= io_wakeups_3_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_0 <= io_wakeups_3_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_1 <= io_wakeups_3_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_2 <= io_wakeups_3_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_3 <= io_wakeups_3_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_0 <= io_wakeups_3_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_1 <= io_wakeups_3_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_2 <= io_wakeups_3_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_3 <= io_wakeups_3_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_4 <= io_wakeups_3_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_5 <= io_wakeups_3_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_6 <= io_wakeups_3_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_7 <= io_wakeups_3_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_8 <= io_wakeups_3_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_9 <= io_wakeups_3_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_issued <= io_wakeups_3_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child <= io_wakeups_3_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child <= io_wakeups_3_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint <= io_wakeups_3_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint <= io_wakeups_3_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint <= io_wakeups_3_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_dis_col_sel <= io_wakeups_3_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_mask <= io_wakeups_3_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_tag <= io_wakeups_3_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_type <= io_wakeups_3_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sfb <= io_wakeups_3_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_fence <= io_wakeups_3_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_fencei <= io_wakeups_3_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sfence <= io_wakeups_3_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_amo <= io_wakeups_3_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_eret <= io_wakeups_3_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sys_pc2epc <= io_wakeups_3_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_rocc <= io_wakeups_3_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_mov <= io_wakeups_3_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ftq_idx <= io_wakeups_3_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_edge_inst <= io_wakeups_3_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pc_lob <= io_wakeups_3_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_taken <= io_wakeups_3_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_rename <= io_wakeups_3_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_sel <= io_wakeups_3_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pimm <= io_wakeups_3_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_packed <= io_wakeups_3_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_op1_sel <= io_wakeups_3_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_op2_sel <= io_wakeups_3_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst <= io_wakeups_3_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_wen <= io_wakeups_3_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1 <= io_wakeups_3_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2 <= io_wakeups_3_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3 <= io_wakeups_3_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12 <= io_wakeups_3_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23 <= io_wakeups_3_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn <= io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut <= io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint <= io_wakeups_3_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_toint <= io_wakeups_3_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe <= io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fma <= io_wakeups_3_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_div <= io_wakeups_3_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt <= io_wakeups_3_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags <= io_wakeups_3_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_vec <= io_wakeups_3_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_rob_idx <= io_wakeups_3_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldq_idx <= io_wakeups_3_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_stq_idx <= io_wakeups_3_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_rxq_idx <= io_wakeups_3_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pdst <= io_wakeups_3_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs1 <= io_wakeups_3_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs2 <= io_wakeups_3_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs3 <= io_wakeups_3_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ppred <= io_wakeups_3_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs1_busy <= io_wakeups_3_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs2_busy <= io_wakeups_3_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs3_busy <= io_wakeups_3_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ppred_busy <= io_wakeups_3_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_stale_pdst <= io_wakeups_3_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_exception <= io_wakeups_3_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_exc_cause <= io_wakeups_3_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_cmd <= io_wakeups_3_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_size <= io_wakeups_3_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_signed <= io_wakeups_3_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_uses_ldq <= io_wakeups_3_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_uses_stq <= io_wakeups_3_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_unique <= io_wakeups_3_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_flush_on_commit <= io_wakeups_3_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_csr_cmd <= io_wakeups_3_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldst_is_rs1 <= io_wakeups_3_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldst <= io_wakeups_3_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs1 <= io_wakeups_3_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs2 <= io_wakeups_3_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs3 <= io_wakeups_3_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_dst_rtype <= io_wakeups_3_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs1_rtype <= io_wakeups_3_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs2_rtype <= io_wakeups_3_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_frs3_en <= io_wakeups_3_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fcn_dw <= io_wakeups_3_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fcn_op <= io_wakeups_3_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_val <= io_wakeups_3_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_rm <= io_wakeups_3_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_typ <= io_wakeups_3_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_pf_if <= io_wakeups_3_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_ae_if <= io_wakeups_3_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_ma_if <= io_wakeups_3_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_bp_debug_if <= io_wakeups_3_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_bp_xcpt_if <= io_wakeups_3_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_fsrc <= io_wakeups_3_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_tsrc <= io_wakeups_3_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] if (reset) // @[rename-busytable.scala:27:7] busy_table <= 80'h0; // @[rename-busytable.scala:53:27] else // @[rename-busytable.scala:27:7] busy_table <= busy_table_next[79:0]; // @[rename-busytable.scala:53:27, :62:5, :66:14] always @(posedge) assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_123 = shr(io.in.a.bits.source, 3) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_130 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_240 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_314 = shr(io.in.a.bits.source, 3) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_321 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_428 = shr(io.in.a.bits.source, 3) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_435 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_538 = shr(io.in.a.bits.source, 3) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_545 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_651 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_759 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<27>(0h4000000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<13>(0h1000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = or(_T_772, _T_777) node _T_804 = or(_T_803, _T_782) node _T_805 = or(_T_804, _T_787) node _T_806 = or(_T_805, _T_792) node _T_807 = or(_T_806, _T_797) node _T_808 = or(_T_807, _T_802) node _T_809 = and(_T_767, _T_808) node _T_810 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_811 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_812 = cvt(_T_811) node _T_813 = and(_T_812, asSInt(UInt<17>(0h10000))) node _T_814 = asSInt(_T_813) node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = and(_T_810, _T_815) node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_818 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_819 = and(_T_817, _T_818) node _T_820 = or(UInt<1>(0h0), _T_819) node _T_821 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_822 = cvt(_T_821) node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000))) node _T_824 = asSInt(_T_823) node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0))) node _T_826 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<29>(0h10000000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = or(_T_825, _T_830) node _T_832 = and(_T_820, _T_831) node _T_833 = or(UInt<1>(0h0), _T_809) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_832) node _T_836 = and(_T_763, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_836, UInt<1>(0h1), "") : assert_36 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(is_aligned, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_846 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_846, UInt<1>(0h1), "") : assert_39 node _T_850 = eq(io.in.a.bits.mask, mask) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_850, UInt<1>(0h1), "") : assert_40 node _T_854 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_854 : node _T_855 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_856 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_858 = shr(io.in.a.bits.source, 3) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_9) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_863 = and(_T_861, _T_862) node _T_864 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_865 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_866 = or(_T_863, _T_864) node _T_867 = or(_T_866, _T_865) node _T_868 = and(_T_857, _T_867) node _T_869 = or(UInt<1>(0h0), _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<13>(0h1000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = and(_T_916, _T_921) node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_925 = and(_T_923, _T_924) node _T_926 = or(UInt<1>(0h0), _T_925) node _T_927 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<29>(0h10000000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = or(_T_931, _T_936) node _T_938 = and(_T_926, _T_937) node _T_939 = or(UInt<1>(0h0), _T_915) node _T_940 = or(_T_939, _T_922) node _T_941 = or(_T_940, _T_938) node _T_942 = and(_T_869, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_942, UInt<1>(0h1), "") : assert_41 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(is_aligned, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_952 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_952, UInt<1>(0h1), "") : assert_44 node _T_956 = eq(io.in.a.bits.mask, mask) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_956, UInt<1>(0h1), "") : assert_45 node _T_960 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_960 : node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_962 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_964 = shr(io.in.a.bits.source, 3) node _T_965 = eq(_T_964, UInt<1>(0h0)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_10) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_971 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_972 = or(_T_969, _T_970) node _T_973 = or(_T_972, _T_971) node _T_974 = and(_T_963, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<14>(0h2000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_991, _T_996) node _T_1023 = or(_T_1022, _T_1001) node _T_1024 = or(_T_1023, _T_1006) node _T_1025 = or(_T_1024, _T_1011) node _T_1026 = or(_T_1025, _T_1016) node _T_1027 = or(_T_1026, _T_1021) node _T_1028 = and(_T_986, _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<17>(0h10000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<29>(0h10000000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _T_1044 = and(_T_1032, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_985) node _T_1046 = or(_T_1045, _T_1028) node _T_1047 = or(_T_1046, _T_1044) node _T_1048 = and(_T_975, _T_1047) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_46 node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(is_aligned, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1058 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_49 node _T_1062 = eq(io.in.a.bits.mask, mask) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_50 node _T_1066 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1070 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1074 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1074 : node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok_1, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1078 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_54 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_55 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_56 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_57 node _T_1094 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1094 : node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(source_ok_1, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(sink_ok, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1101 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_60 node _T_1105 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_61 node _T_1109 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_62 node _T_1113 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_63 node _T_1117 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1118 = or(UInt<1>(0h1), _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_64 node _T_1122 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(source_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(sink_ok, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1129 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_67 node _T_1133 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_68 node _T_1137 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_69 node _T_1141 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.d.bits.corrupt) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_70 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h1), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_71 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_73 node _T_1159 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_74 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(UInt<1>(0h1), _T_1163) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_75 node _T_1168 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1168 : node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(source_ok_1, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1172 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_77 node _T_1176 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1177 = or(_T_1176, io.in.d.bits.corrupt) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_78 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h1), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_79 node _T_1186 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1186 : node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(source_ok_1, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1190 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_81 node _T_1194 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_82 node _T_1198 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1199 = or(UInt<1>(0h1), _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1203 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1207 = shr(io.in.b.bits.source, 3) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1213, _T_1218) node _T_1220 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = and(_T_1219, _T_1227) node _T_1237 = and(_T_1236, _T_1235) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1241 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1241 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1242 = shr(io.in.b.bits.source, 3) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1249 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1247 connect _WIRE_4[1], _T_1248 connect _WIRE_4[2], _T_1249 node _T_1250 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1251 = mux(_WIRE_4[0], _T_1250, UInt<1>(0h0)) node _T_1252 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1253 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1252) node _T_1255 = or(_T_1254, _T_1253) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1255 node _T_1256 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1257 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = or(UInt<1>(0h0), _T_1258) node _T_1260 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<14>(0h2000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<13>(0h1000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<18>(0h2f000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<27>(0h4000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1301 = cvt(_T_1300) node _T_1302 = and(_T_1301, asSInt(UInt<13>(0h1000))) node _T_1303 = asSInt(_T_1302) node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0))) node _T_1305 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = or(_T_1264, _T_1269) node _T_1311 = or(_T_1310, _T_1274) node _T_1312 = or(_T_1311, _T_1279) node _T_1313 = or(_T_1312, _T_1284) node _T_1314 = or(_T_1313, _T_1289) node _T_1315 = or(_T_1314, _T_1294) node _T_1316 = or(_T_1315, _T_1299) node _T_1317 = or(_T_1316, _T_1304) node _T_1318 = or(_T_1317, _T_1309) node _T_1319 = and(_T_1259, _T_1318) node _T_1320 = or(UInt<1>(0h0), _T_1319) node _T_1321 = and(_WIRE_5, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_86 node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(address_ok, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(legal_source, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1334 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_90 node _T_1338 = eq(io.in.b.bits.mask, mask_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_91 node _T_1342 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1346 : node _T_1347 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1348 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<14>(0h2000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<13>(0h1000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<18>(0h2f000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<13>(0h1000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<17>(0h10000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<27>(0h4000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<29>(0h10000000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = or(_T_1355, _T_1360) node _T_1402 = or(_T_1401, _T_1365) node _T_1403 = or(_T_1402, _T_1370) node _T_1404 = or(_T_1403, _T_1375) node _T_1405 = or(_T_1404, _T_1380) node _T_1406 = or(_T_1405, _T_1385) node _T_1407 = or(_T_1406, _T_1390) node _T_1408 = or(_T_1407, _T_1395) node _T_1409 = or(_T_1408, _T_1400) node _T_1410 = and(_T_1350, _T_1409) node _T_1411 = or(UInt<1>(0h0), _T_1410) node _T_1412 = and(UInt<1>(0h0), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_93 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(address_ok, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(legal_source, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1425 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_97 node _T_1429 = eq(io.in.b.bits.mask, mask_1) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_98 node _T_1433 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_99 node _T_1437 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1437 : node _T_1438 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1439 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1440 = and(_T_1438, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<14>(0h2000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<13>(0h1000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<18>(0h2f000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<17>(0h10000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<27>(0h4000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<13>(0h1000))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1488 = cvt(_T_1487) node _T_1489 = and(_T_1488, asSInt(UInt<29>(0h10000000))) node _T_1490 = asSInt(_T_1489) node _T_1491 = eq(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = or(_T_1446, _T_1451) node _T_1493 = or(_T_1492, _T_1456) node _T_1494 = or(_T_1493, _T_1461) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1471) node _T_1497 = or(_T_1496, _T_1476) node _T_1498 = or(_T_1497, _T_1481) node _T_1499 = or(_T_1498, _T_1486) node _T_1500 = or(_T_1499, _T_1491) node _T_1501 = and(_T_1441, _T_1500) node _T_1502 = or(UInt<1>(0h0), _T_1501) node _T_1503 = and(UInt<1>(0h0), _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_100 node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(address_ok, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(legal_source, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1516 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_104 node _T_1520 = eq(io.in.b.bits.mask, mask_1) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_105 node _T_1524 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1524 : node _T_1525 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1526 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = or(UInt<1>(0h0), _T_1527) node _T_1529 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<14>(0h2000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<13>(0h1000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<18>(0h2f000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<27>(0h4000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<29>(0h10000000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = or(_T_1533, _T_1538) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1548) node _T_1582 = or(_T_1581, _T_1553) node _T_1583 = or(_T_1582, _T_1558) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1568) node _T_1586 = or(_T_1585, _T_1573) node _T_1587 = or(_T_1586, _T_1578) node _T_1588 = and(_T_1528, _T_1587) node _T_1589 = or(UInt<1>(0h0), _T_1588) node _T_1590 = and(UInt<1>(0h0), _T_1589) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_106 node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(address_ok, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(legal_source, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1603 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_110 node _T_1607 = not(mask_1) node _T_1608 = and(io.in.b.bits.mask, _T_1607) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_111 node _T_1613 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1613 : node _T_1614 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1615 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = or(UInt<1>(0h0), _T_1616) node _T_1618 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<14>(0h2000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<18>(0h2f000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<13>(0h1000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<17>(0h10000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<27>(0h4000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1659 = cvt(_T_1658) node _T_1660 = and(_T_1659, asSInt(UInt<13>(0h1000))) node _T_1661 = asSInt(_T_1660) node _T_1662 = eq(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1664 = cvt(_T_1663) node _T_1665 = and(_T_1664, asSInt(UInt<29>(0h10000000))) node _T_1666 = asSInt(_T_1665) node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0))) node _T_1668 = or(_T_1622, _T_1627) node _T_1669 = or(_T_1668, _T_1632) node _T_1670 = or(_T_1669, _T_1637) node _T_1671 = or(_T_1670, _T_1642) node _T_1672 = or(_T_1671, _T_1647) node _T_1673 = or(_T_1672, _T_1652) node _T_1674 = or(_T_1673, _T_1657) node _T_1675 = or(_T_1674, _T_1662) node _T_1676 = or(_T_1675, _T_1667) node _T_1677 = and(_T_1617, _T_1676) node _T_1678 = or(UInt<1>(0h0), _T_1677) node _T_1679 = and(UInt<1>(0h0), _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_112 node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(address_ok, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(legal_source, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1689 = asUInt(reset) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) when _T_1690 : node _T_1691 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1692 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_116 node _T_1696 = eq(io.in.b.bits.mask, mask_1) node _T_1697 = asUInt(reset) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(_T_1696, UInt<1>(0h0)) when _T_1699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1696, UInt<1>(0h1), "") : assert_117 node _T_1700 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1700 : node _T_1701 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1702 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = or(UInt<1>(0h0), _T_1703) node _T_1705 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<14>(0h2000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<13>(0h1000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<18>(0h2f000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<13>(0h1000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<17>(0h10000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<27>(0h4000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1746 = cvt(_T_1745) node _T_1747 = and(_T_1746, asSInt(UInt<13>(0h1000))) node _T_1748 = asSInt(_T_1747) node _T_1749 = eq(_T_1748, asSInt(UInt<1>(0h0))) node _T_1750 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<29>(0h10000000))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = or(_T_1709, _T_1714) node _T_1756 = or(_T_1755, _T_1719) node _T_1757 = or(_T_1756, _T_1724) node _T_1758 = or(_T_1757, _T_1729) node _T_1759 = or(_T_1758, _T_1734) node _T_1760 = or(_T_1759, _T_1739) node _T_1761 = or(_T_1760, _T_1744) node _T_1762 = or(_T_1761, _T_1749) node _T_1763 = or(_T_1762, _T_1754) node _T_1764 = and(_T_1704, _T_1763) node _T_1765 = or(UInt<1>(0h0), _T_1764) node _T_1766 = and(UInt<1>(0h0), _T_1765) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_118 node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(address_ok, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(legal_source, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1779 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_122 node _T_1783 = eq(io.in.b.bits.mask, mask_1) node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(_T_1783, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1783, UInt<1>(0h1), "") : assert_123 node _T_1787 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1787 : node _T_1788 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1789 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1790 = and(_T_1788, _T_1789) node _T_1791 = or(UInt<1>(0h0), _T_1790) node _T_1792 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<14>(0h2000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<13>(0h1000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1796, _T_1801) node _T_1843 = or(_T_1842, _T_1806) node _T_1844 = or(_T_1843, _T_1811) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1821) node _T_1847 = or(_T_1846, _T_1826) node _T_1848 = or(_T_1847, _T_1831) node _T_1849 = or(_T_1848, _T_1836) node _T_1850 = or(_T_1849, _T_1841) node _T_1851 = and(_T_1791, _T_1850) node _T_1852 = or(UInt<1>(0h0), _T_1851) node _T_1853 = and(UInt<1>(0h0), _T_1852) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_124 node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(address_ok, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(legal_source, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1866 = eq(io.in.b.bits.mask, mask_1) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_128 node _T_1870 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1874 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1878 = shr(io.in.c.bits.source, 3) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) node _T_1885 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) node _T_1893 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = or(_T_1892, _T_1897) node _T_1899 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) node _T_1901 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1890, _T_1898) node _T_1908 = and(_T_1907, _T_1906) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_131 node _T_1912 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1912 : node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(address_ok_1, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok_2, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1919 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_134 node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1926 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_136 node _T_1930 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_137 node _T_1934 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1941 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_140 node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1948 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_142 node _T_1952 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1952 : node _T_1953 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1954 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1955 = and(_T_1953, _T_1954) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_1956 = shr(io.in.c.bits.source, 3) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) node _T_1958 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1959 = and(_T_1957, _T_1958) node _T_1960 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_1961 = and(_T_1959, _T_1960) node _T_1962 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1963 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1964 = or(_T_1961, _T_1962) node _T_1965 = or(_T_1964, _T_1963) node _T_1966 = and(_T_1955, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1966) node _T_1968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<14>(0h2000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<13>(0h1000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<18>(0h2f000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<17>(0h10000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2000 = cvt(_T_1999) node _T_2001 = and(_T_2000, asSInt(UInt<27>(0h4000000))) node _T_2002 = asSInt(_T_2001) node _T_2003 = eq(_T_2002, asSInt(UInt<1>(0h0))) node _T_2004 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2005 = cvt(_T_2004) node _T_2006 = and(_T_2005, asSInt(UInt<13>(0h1000))) node _T_2007 = asSInt(_T_2006) node _T_2008 = eq(_T_2007, asSInt(UInt<1>(0h0))) node _T_2009 = or(_T_1973, _T_1978) node _T_2010 = or(_T_2009, _T_1983) node _T_2011 = or(_T_2010, _T_1988) node _T_2012 = or(_T_2011, _T_1993) node _T_2013 = or(_T_2012, _T_1998) node _T_2014 = or(_T_2013, _T_2003) node _T_2015 = or(_T_2014, _T_2008) node _T_2016 = and(_T_1968, _T_2015) node _T_2017 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2018 = or(UInt<1>(0h0), _T_2017) node _T_2019 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2020 = cvt(_T_2019) node _T_2021 = and(_T_2020, asSInt(UInt<17>(0h10000))) node _T_2022 = asSInt(_T_2021) node _T_2023 = eq(_T_2022, asSInt(UInt<1>(0h0))) node _T_2024 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2025 = cvt(_T_2024) node _T_2026 = and(_T_2025, asSInt(UInt<29>(0h10000000))) node _T_2027 = asSInt(_T_2026) node _T_2028 = eq(_T_2027, asSInt(UInt<1>(0h0))) node _T_2029 = or(_T_2023, _T_2028) node _T_2030 = and(_T_2018, _T_2029) node _T_2031 = or(UInt<1>(0h0), _T_2016) node _T_2032 = or(_T_2031, _T_2030) node _T_2033 = and(_T_1967, _T_2032) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2037 = shr(io.in.c.bits.source, 3) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) node _T_2039 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2040 = and(_T_2038, _T_2039) node _T_2041 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2044 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2042 connect _WIRE_6[1], _T_2043 connect _WIRE_6[2], _T_2044 node _T_2045 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2046 = mux(_WIRE_6[0], _T_2045, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = or(_T_2046, _T_2047) node _T_2050 = or(_T_2049, _T_2048) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2050 node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<14>(0h2000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<13>(0h1000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<18>(0h2f000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<13>(0h1000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<29>(0h10000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2059, _T_2064) node _T_2106 = or(_T_2105, _T_2069) node _T_2107 = or(_T_2106, _T_2074) node _T_2108 = or(_T_2107, _T_2079) node _T_2109 = or(_T_2108, _T_2084) node _T_2110 = or(_T_2109, _T_2089) node _T_2111 = or(_T_2110, _T_2094) node _T_2112 = or(_T_2111, _T_2099) node _T_2113 = or(_T_2112, _T_2104) node _T_2114 = and(_T_2054, _T_2113) node _T_2115 = or(UInt<1>(0h0), _T_2114) node _T_2116 = and(_WIRE_7, _T_2115) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_144 node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(source_ok_2, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2123 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_146 node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2130 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_148 node _T_2134 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_149 node _T_2138 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2138 : node _T_2139 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2140 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2141 = and(_T_2139, _T_2140) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2142 = shr(io.in.c.bits.source, 3) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) node _T_2144 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2149 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2150 = or(_T_2147, _T_2148) node _T_2151 = or(_T_2150, _T_2149) node _T_2152 = and(_T_2141, _T_2151) node _T_2153 = or(UInt<1>(0h0), _T_2152) node _T_2154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2155 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<14>(0h2000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<13>(0h1000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<18>(0h2f000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<17>(0h10000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2186 = cvt(_T_2185) node _T_2187 = and(_T_2186, asSInt(UInt<27>(0h4000000))) node _T_2188 = asSInt(_T_2187) node _T_2189 = eq(_T_2188, asSInt(UInt<1>(0h0))) node _T_2190 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<13>(0h1000))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2159, _T_2164) node _T_2196 = or(_T_2195, _T_2169) node _T_2197 = or(_T_2196, _T_2174) node _T_2198 = or(_T_2197, _T_2179) node _T_2199 = or(_T_2198, _T_2184) node _T_2200 = or(_T_2199, _T_2189) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = and(_T_2154, _T_2201) node _T_2203 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<17>(0h10000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<29>(0h10000000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = or(_T_2209, _T_2214) node _T_2216 = and(_T_2204, _T_2215) node _T_2217 = or(UInt<1>(0h0), _T_2202) node _T_2218 = or(_T_2217, _T_2216) node _T_2219 = and(_T_2153, _T_2218) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2223 = shr(io.in.c.bits.source, 3) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) node _T_2225 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2226 = and(_T_2224, _T_2225) node _T_2227 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2228 = and(_T_2226, _T_2227) node _T_2229 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2230 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2228 connect _WIRE_8[1], _T_2229 connect _WIRE_8[2], _T_2230 node _T_2231 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2232 = mux(_WIRE_8[0], _T_2231, UInt<1>(0h0)) node _T_2233 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2234 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2235 = or(_T_2232, _T_2233) node _T_2236 = or(_T_2235, _T_2234) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2236 node _T_2237 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2238 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2239 = and(_T_2237, _T_2238) node _T_2240 = or(UInt<1>(0h0), _T_2239) node _T_2241 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<14>(0h2000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<13>(0h1000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<18>(0h2f000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<13>(0h1000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<17>(0h10000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<27>(0h4000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2282 = cvt(_T_2281) node _T_2283 = and(_T_2282, asSInt(UInt<13>(0h1000))) node _T_2284 = asSInt(_T_2283) node _T_2285 = eq(_T_2284, asSInt(UInt<1>(0h0))) node _T_2286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2287 = cvt(_T_2286) node _T_2288 = and(_T_2287, asSInt(UInt<29>(0h10000000))) node _T_2289 = asSInt(_T_2288) node _T_2290 = eq(_T_2289, asSInt(UInt<1>(0h0))) node _T_2291 = or(_T_2245, _T_2250) node _T_2292 = or(_T_2291, _T_2255) node _T_2293 = or(_T_2292, _T_2260) node _T_2294 = or(_T_2293, _T_2265) node _T_2295 = or(_T_2294, _T_2270) node _T_2296 = or(_T_2295, _T_2275) node _T_2297 = or(_T_2296, _T_2280) node _T_2298 = or(_T_2297, _T_2285) node _T_2299 = or(_T_2298, _T_2290) node _T_2300 = and(_T_2240, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2300) node _T_2302 = and(_WIRE_9, _T_2301) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_151 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(source_ok_2, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2309 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_153 node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2316 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_155 node _T_2320 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2320 : node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(address_ok_1, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : node _T_2326 = eq(source_ok_2, UInt<1>(0h0)) when _T_2326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2330 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2331 = asUInt(reset) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) when _T_2332 : node _T_2333 = eq(_T_2330, UInt<1>(0h0)) when _T_2333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2330, UInt<1>(0h1), "") : assert_159 node _T_2334 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(_T_2334, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2334, UInt<1>(0h1), "") : assert_160 node _T_2338 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2338 : node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(address_ok_1, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(source_ok_2, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2345 = asUInt(reset) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) when _T_2346 : node _T_2347 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2348 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_164 node _T_2352 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2352 : node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(address_ok_1, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok_2, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2362 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_168 node _T_2366 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2373 = eq(a_first, UInt<1>(0h0)) node _T_2374 = and(io.in.a.valid, _T_2373) when _T_2374 : node _T_2375 = eq(io.in.a.bits.opcode, opcode) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_171 node _T_2379 = eq(io.in.a.bits.param, param) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_172 node _T_2383 = eq(io.in.a.bits.size, size) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_173 node _T_2387 = eq(io.in.a.bits.source, source) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_174 node _T_2391 = eq(io.in.a.bits.address, address) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_175 node _T_2395 = and(io.in.a.ready, io.in.a.valid) node _T_2396 = and(_T_2395, a_first) when _T_2396 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2397 = eq(d_first, UInt<1>(0h0)) node _T_2398 = and(io.in.d.valid, _T_2397) when _T_2398 : node _T_2399 = eq(io.in.d.bits.opcode, opcode_1) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_176 node _T_2403 = eq(io.in.d.bits.param, param_1) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_177 node _T_2407 = eq(io.in.d.bits.size, size_1) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_178 node _T_2411 = eq(io.in.d.bits.source, source_1) node _T_2412 = asUInt(reset) node _T_2413 = eq(_T_2412, UInt<1>(0h0)) when _T_2413 : node _T_2414 = eq(_T_2411, UInt<1>(0h0)) when _T_2414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2411, UInt<1>(0h1), "") : assert_179 node _T_2415 = eq(io.in.d.bits.sink, sink) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_180 node _T_2419 = eq(io.in.d.bits.denied, denied) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_181 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first) when _T_2424 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2425 = eq(b_first, UInt<1>(0h0)) node _T_2426 = and(io.in.b.valid, _T_2425) when _T_2426 : node _T_2427 = eq(io.in.b.bits.opcode, opcode_2) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_182 node _T_2431 = eq(io.in.b.bits.param, param_2) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_183 node _T_2435 = eq(io.in.b.bits.size, size_2) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_184 node _T_2439 = eq(io.in.b.bits.source, source_2) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_185 node _T_2443 = eq(io.in.b.bits.address, address_1) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_186 node _T_2447 = and(io.in.b.ready, io.in.b.valid) node _T_2448 = and(_T_2447, b_first) when _T_2448 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2449 = eq(c_first, UInt<1>(0h0)) node _T_2450 = and(io.in.c.valid, _T_2449) when _T_2450 : node _T_2451 = eq(io.in.c.bits.opcode, opcode_3) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_187 node _T_2455 = eq(io.in.c.bits.param, param_3) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_188 node _T_2459 = eq(io.in.c.bits.size, size_3) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_189 node _T_2463 = eq(io.in.c.bits.source, source_3) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_190 node _T_2467 = eq(io.in.c.bits.address, address_2) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_191 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(_T_2471, c_first) when _T_2472 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2473 = and(io.in.a.valid, a_first_1) node _T_2474 = and(_T_2473, UInt<1>(0h1)) when _T_2474 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2475 = and(io.in.a.ready, io.in.a.valid) node _T_2476 = and(_T_2475, a_first_1) node _T_2477 = and(_T_2476, UInt<1>(0h1)) when _T_2477 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2478 = dshr(inflight, io.in.a.bits.source) node _T_2479 = bits(_T_2478, 0, 0) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2484 = and(io.in.d.valid, d_first_1) node _T_2485 = and(_T_2484, UInt<1>(0h1)) node _T_2486 = eq(d_release_ack, UInt<1>(0h0)) node _T_2487 = and(_T_2485, _T_2486) when _T_2487 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2488 = and(io.in.d.ready, io.in.d.valid) node _T_2489 = and(_T_2488, d_first_1) node _T_2490 = and(_T_2489, UInt<1>(0h1)) node _T_2491 = eq(d_release_ack, UInt<1>(0h0)) node _T_2492 = and(_T_2490, _T_2491) when _T_2492 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2493 = and(io.in.d.valid, d_first_1) node _T_2494 = and(_T_2493, UInt<1>(0h1)) node _T_2495 = eq(d_release_ack, UInt<1>(0h0)) node _T_2496 = and(_T_2494, _T_2495) when _T_2496 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2497 = dshr(inflight, io.in.d.bits.source) node _T_2498 = bits(_T_2497, 0, 0) node _T_2499 = or(_T_2498, same_cycle_resp) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_194 node _T_2509 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_195 else : node _T_2513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2515 = or(_T_2513, _T_2514) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_196 node _T_2519 = eq(io.in.d.bits.size, a_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_197 node _T_2523 = and(io.in.d.valid, d_first_1) node _T_2524 = and(_T_2523, a_first_1) node _T_2525 = and(_T_2524, io.in.a.valid) node _T_2526 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = eq(d_release_ack, UInt<1>(0h0)) node _T_2529 = and(_T_2527, _T_2528) when _T_2529 : node _T_2530 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2531 = or(_T_2530, io.in.a.ready) node _T_2532 = asUInt(reset) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) when _T_2533 : node _T_2534 = eq(_T_2531, UInt<1>(0h0)) when _T_2534 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2531, UInt<1>(0h1), "") : assert_198 node _T_2535 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2536 = orr(a_set_wo_ready) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = or(_T_2535, _T_2537) node _T_2539 = asUInt(reset) node _T_2540 = eq(_T_2539, UInt<1>(0h0)) when _T_2540 : node _T_2541 = eq(_T_2538, UInt<1>(0h0)) when _T_2541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2538, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_2542 = orr(inflight) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) node _T_2544 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2545 = or(_T_2543, _T_2544) node _T_2546 = lt(watchdog, plusarg_reader.out) node _T_2547 = or(_T_2545, _T_2546) node _T_2548 = asUInt(reset) node _T_2549 = eq(_T_2548, UInt<1>(0h0)) when _T_2549 : node _T_2550 = eq(_T_2547, UInt<1>(0h0)) when _T_2550 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2547, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2551 = and(io.in.a.ready, io.in.a.valid) node _T_2552 = and(io.in.d.ready, io.in.d.valid) node _T_2553 = or(_T_2551, _T_2552) when _T_2553 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2554 = and(io.in.c.valid, c_first_1) node _T_2555 = bits(io.in.c.bits.opcode, 2, 2) node _T_2556 = bits(io.in.c.bits.opcode, 1, 1) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = and(_T_2554, _T_2557) when _T_2558 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2559 = and(io.in.c.ready, io.in.c.valid) node _T_2560 = and(_T_2559, c_first_1) node _T_2561 = bits(io.in.c.bits.opcode, 2, 2) node _T_2562 = bits(io.in.c.bits.opcode, 1, 1) node _T_2563 = and(_T_2561, _T_2562) node _T_2564 = and(_T_2560, _T_2563) when _T_2564 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2565 = dshr(inflight_1, io.in.c.bits.source) node _T_2566 = bits(_T_2565, 0, 0) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) node _T_2568 = asUInt(reset) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) when _T_2569 : node _T_2570 = eq(_T_2567, UInt<1>(0h0)) when _T_2570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2567, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2571 = and(io.in.d.valid, d_first_2) node _T_2572 = and(_T_2571, UInt<1>(0h1)) node _T_2573 = and(_T_2572, d_release_ack_1) when _T_2573 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2574 = and(io.in.d.ready, io.in.d.valid) node _T_2575 = and(_T_2574, d_first_2) node _T_2576 = and(_T_2575, UInt<1>(0h1)) node _T_2577 = and(_T_2576, d_release_ack_1) when _T_2577 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2578 = and(io.in.d.valid, d_first_2) node _T_2579 = and(_T_2578, UInt<1>(0h1)) node _T_2580 = and(_T_2579, d_release_ack_1) when _T_2580 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2581 = dshr(inflight_1, io.in.d.bits.source) node _T_2582 = bits(_T_2581, 0, 0) node _T_2583 = or(_T_2582, same_cycle_resp_1) node _T_2584 = asUInt(reset) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) when _T_2585 : node _T_2586 = eq(_T_2583, UInt<1>(0h0)) when _T_2586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2583, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2587 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_203 else : node _T_2591 = eq(io.in.d.bits.size, c_size_lookup) node _T_2592 = asUInt(reset) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) when _T_2593 : node _T_2594 = eq(_T_2591, UInt<1>(0h0)) when _T_2594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2591, UInt<1>(0h1), "") : assert_204 node _T_2595 = and(io.in.d.valid, d_first_2) node _T_2596 = and(_T_2595, c_first_1) node _T_2597 = and(_T_2596, io.in.c.valid) node _T_2598 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2599 = and(_T_2597, _T_2598) node _T_2600 = and(_T_2599, d_release_ack_1) node _T_2601 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2602 = and(_T_2600, _T_2601) when _T_2602 : node _T_2603 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2604 = or(_T_2603, io.in.c.ready) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_205 node _T_2608 = orr(c_set_wo_ready) when _T_2608 : node _T_2609 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_2613 = orr(inflight_1) node _T_2614 = eq(_T_2613, UInt<1>(0h0)) node _T_2615 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2616 = or(_T_2614, _T_2615) node _T_2617 = lt(watchdog_1, plusarg_reader_1.out) node _T_2618 = or(_T_2616, _T_2617) node _T_2619 = asUInt(reset) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) when _T_2620 : node _T_2621 = eq(_T_2618, UInt<1>(0h0)) when _T_2621 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2618, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2622 = and(io.in.c.ready, io.in.c.valid) node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = or(_T_2622, _T_2623) when _T_2624 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2625 = and(io.in.d.ready, io.in.d.valid) node _T_2626 = and(_T_2625, d_first_3) node _T_2627 = bits(io.in.d.bits.opcode, 2, 2) node _T_2628 = bits(io.in.d.bits.opcode, 1, 1) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) node _T_2630 = and(_T_2627, _T_2629) node _T_2631 = and(_T_2626, _T_2630) when _T_2631 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2632 = dshr(inflight_2, io.in.d.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = asUInt(reset) node _T_2636 = eq(_T_2635, UInt<1>(0h0)) when _T_2636 : node _T_2637 = eq(_T_2634, UInt<1>(0h0)) when _T_2637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2634, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2638 = and(io.in.e.ready, io.in.e.valid) node _T_2639 = and(_T_2638, UInt<1>(0h1)) node _T_2640 = and(_T_2639, UInt<1>(0h1)) when _T_2640 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2641 = or(d_set, inflight_2) node _T_2642 = dshr(_T_2641, io.in.e.bits.sink) node _T_2643 = bits(_T_2642, 0, 0) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_8 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_9 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[3]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_9 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_10 = {_legal_source_WIRE_2, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} \| _legal_source_T_10; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2551; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2551; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2625 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2625; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2622 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2622; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2622; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_20 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2551 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2477 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2477 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2477 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_22 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2523 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2625 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2492 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2492 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2492 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_23 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2564 = _T_2622 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2564 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2564 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2564 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2564 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2564 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2577 = _T_2625 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2577 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2577 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2577 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2631 = _T_2625 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_24 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2631 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2640 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = _T_2640 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_38 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_38(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<64>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<64>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_wdat : { data : UInt<64>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<3>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 2, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 3) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 3) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid \|\| queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<3>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<8>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_18 = and(s2_valid, s3_ready) when _T_18 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_19 = eq(s3_ready, UInt<1>(0h0)) node _T_20 = and(s2_valid, _T_19) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<3>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 63, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_21 = eq(s3_full, UInt<1>(0h0)) node _T_22 = eq(s3_need_r, UInt<1>(0h0)) node _T_23 = or(_T_21, _T_22) node _T_24 = or(_T_23, queue.io.deq.valid) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid)\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_28 = and(s3_valid, s4_ready) when _T_28 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_29 = eq(s4_ready, UInt<1>(0h0)) node _T_30 = and(s3_valid, _T_29) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<3>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<64>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_9 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_10 = or(_io_bs_wadr_bits_mask_T_9, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_11 = or(_io_bs_wadr_bits_mask_T_10, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_12 = or(_io_bs_wadr_bits_mask_T_11, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_13 = or(_io_bs_wadr_bits_mask_T_12, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_14 = or(_io_bs_wadr_bits_mask_T_13, _io_bs_wadr_bits_mask_T_7) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_14 connect io.bs_wdat.data, atomics.io.data_out node _T_31 = and(s4_full, s4_need_pb) node _T_32 = and(_T_31, s4_pdata.corrupt) node _T_33 = eq(_T_32, UInt<1>(0h0)) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_38 = and(io.bs_wadr.valid, _T_37) node _T_39 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_40 = and(s4_req.prio[0], _T_39) node _T_41 = eq(s4_req.param, UInt<3>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_44 = and(s4_req.prio[0], _T_43) node _T_45 = eq(s4_req.param, UInt<3>(0h1)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_48 = and(s4_req.prio[0], _T_47) node _T_49 = eq(s4_req.param, UInt<3>(0h2)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_52 = and(s4_req.prio[0], _T_51) node _T_53 = eq(s4_req.param, UInt<3>(0h3)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_56 = and(s4_req.prio[0], _T_55) node _T_57 = eq(s4_req.param, UInt<3>(0h4)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_60 = and(s4_req.prio[0], _T_59) node _T_61 = eq(s4_req.param, UInt<3>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_64 = and(s4_req.prio[0], _T_63) node _T_65 = eq(s4_req.param, UInt<3>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_68 = and(s4_req.prio[0], _T_67) node _T_69 = eq(s4_req.param, UInt<3>(0h2)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_72 = and(s4_req.prio[0], _T_71) node _T_73 = eq(s4_req.param, UInt<3>(0h3)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(s4_need_bs, UInt<1>(0h0)) node _T_76 = or(io.bs_wadr.ready, _T_75) when _T_76 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<3>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<64>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<3>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<64>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<64>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<3>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 2, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<3>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 2, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<3>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 2, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 63, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_77 = and(io.req.valid, s2) node _T_78 = and(_T_77, s3) node _T_79 = and(_T_78, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_80 = and(io.req.valid, s2_1) node _T_81 = and(_T_80, s3_1) node _T_82 = and(_T_81, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_83 = and(io.req.valid, s2_2) node _T_84 = and(_T_83, s3_2) node _T_85 = and(_T_84, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_86 = and(io.req.valid, s2_3) node _T_87 = and(_T_86, s3_3) node _T_88 = and(_T_87, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_89 = and(io.req.valid, s2_4) node _T_90 = and(_T_89, s3_4) node _T_91 = and(_T_90, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_92 = and(io.req.valid, s2_5) node _T_93 = and(_T_92, s3_5) node _T_94 = and(_T_93, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_95 = and(io.req.valid, s2_6) node _T_96 = and(_T_95, s3_6) node _T_97 = and(_T_96, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_98 = and(io.req.valid, s2_7) node _T_99 = and(_T_98, s3_7) node _T_100 = and(_T_99, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 2, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<3>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 2, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<3>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 2, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_rel_pop_ready = 1'h1; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data = 64'h0; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt = 1'h0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : 64'h0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 & io_pb_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = ~s2_req_prio_0 \| io_pb_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_98 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_98( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_13 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x	module PMPChecker_s3_13( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T \| _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T \| _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess \| _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 \| res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 \| _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 \| _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 \| _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 \| res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 \| _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 \| _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 \| _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 \| res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 \| _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 \| _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 \| _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 \| res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 \| _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 \| _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 \| _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 \| res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 \| _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 \| _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 \| _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 \| res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 \| _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 \| _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 \| _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 \| res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 \| _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 \| _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 \| res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RenameFreeList : input clock : Clock input reset : Reset output io : { flip initial_allocation : UInt<80>, flip reqs : UInt<1>[2], alloc_pregs : { valid : UInt<1>, bits : UInt<7>}[2], flip despec : { valid : UInt<1>, bits : UInt<7>}[2], flip dealloc : { valid : UInt<1>, bits : UInt<7>}[2], flip ren_br_tags : { valid : UInt<1>, bits : UInt<4>}[3], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rollback : UInt<1>, debug_freelist : UInt<80>} regreset free_list : UInt<80>, clock, reset, io.initial_allocation regreset spec_alloc_list : UInt<80>, clock, reset, UInt<80>(0h0) reg br_alloc_lists : UInt<80>[12], clock wire sels : UInt<80>[2] node _sels_sels_0_T = bits(free_list, 0, 0) node _sels_sels_0_T_1 = bits(free_list, 1, 1) node _sels_sels_0_T_2 = bits(free_list, 2, 2) node _sels_sels_0_T_3 = bits(free_list, 3, 3) node _sels_sels_0_T_4 = bits(free_list, 4, 4) node _sels_sels_0_T_5 = bits(free_list, 5, 5) node _sels_sels_0_T_6 = bits(free_list, 6, 6) node _sels_sels_0_T_7 = bits(free_list, 7, 7) node _sels_sels_0_T_8 = bits(free_list, 8, 8) node _sels_sels_0_T_9 = bits(free_list, 9, 9) node _sels_sels_0_T_10 = bits(free_list, 10, 10) node _sels_sels_0_T_11 = bits(free_list, 11, 11) node _sels_sels_0_T_12 = bits(free_list, 12, 12) node _sels_sels_0_T_13 = bits(free_list, 13, 13) node _sels_sels_0_T_14 = bits(free_list, 14, 14) node _sels_sels_0_T_15 = bits(free_list, 15, 15) node _sels_sels_0_T_16 = bits(free_list, 16, 16) node _sels_sels_0_T_17 = bits(free_list, 17, 17) node _sels_sels_0_T_18 = bits(free_list, 18, 18) node _sels_sels_0_T_19 = bits(free_list, 19, 19) node _sels_sels_0_T_20 = bits(free_list, 20, 20) node _sels_sels_0_T_21 = bits(free_list, 21, 21) node _sels_sels_0_T_22 = bits(free_list, 22, 22) node _sels_sels_0_T_23 = bits(free_list, 23, 23) node _sels_sels_0_T_24 = bits(free_list, 24, 24) node _sels_sels_0_T_25 = bits(free_list, 25, 25) node _sels_sels_0_T_26 = bits(free_list, 26, 26) node _sels_sels_0_T_27 = bits(free_list, 27, 27) node _sels_sels_0_T_28 = bits(free_list, 28, 28) node _sels_sels_0_T_29 = bits(free_list, 29, 29) node _sels_sels_0_T_30 = bits(free_list, 30, 30) node _sels_sels_0_T_31 = bits(free_list, 31, 31) node _sels_sels_0_T_32 = bits(free_list, 32, 32) node _sels_sels_0_T_33 = bits(free_list, 33, 33) node _sels_sels_0_T_34 = bits(free_list, 34, 34) node _sels_sels_0_T_35 = bits(free_list, 35, 35) node _sels_sels_0_T_36 = bits(free_list, 36, 36) node _sels_sels_0_T_37 = bits(free_list, 37, 37) node _sels_sels_0_T_38 = bits(free_list, 38, 38) node _sels_sels_0_T_39 = bits(free_list, 39, 39) node _sels_sels_0_T_40 = bits(free_list, 40, 40) node _sels_sels_0_T_41 = bits(free_list, 41, 41) node _sels_sels_0_T_42 = bits(free_list, 42, 42) node _sels_sels_0_T_43 = bits(free_list, 43, 43) node _sels_sels_0_T_44 = bits(free_list, 44, 44) node _sels_sels_0_T_45 = bits(free_list, 45, 45) node _sels_sels_0_T_46 = bits(free_list, 46, 46) node _sels_sels_0_T_47 = bits(free_list, 47, 47) node _sels_sels_0_T_48 = bits(free_list, 48, 48) node _sels_sels_0_T_49 = bits(free_list, 49, 49) node _sels_sels_0_T_50 = bits(free_list, 50, 50) node _sels_sels_0_T_51 = bits(free_list, 51, 51) node _sels_sels_0_T_52 = bits(free_list, 52, 52) node _sels_sels_0_T_53 = bits(free_list, 53, 53) node _sels_sels_0_T_54 = bits(free_list, 54, 54) node _sels_sels_0_T_55 = bits(free_list, 55, 55) node _sels_sels_0_T_56 = bits(free_list, 56, 56) node _sels_sels_0_T_57 = bits(free_list, 57, 57) node _sels_sels_0_T_58 = bits(free_list, 58, 58) node _sels_sels_0_T_59 = bits(free_list, 59, 59) node _sels_sels_0_T_60 = bits(free_list, 60, 60) node _sels_sels_0_T_61 = bits(free_list, 61, 61) node _sels_sels_0_T_62 = bits(free_list, 62, 62) node _sels_sels_0_T_63 = bits(free_list, 63, 63) node _sels_sels_0_T_64 = bits(free_list, 64, 64) node _sels_sels_0_T_65 = bits(free_list, 65, 65) node _sels_sels_0_T_66 = bits(free_list, 66, 66) node _sels_sels_0_T_67 = bits(free_list, 67, 67) node _sels_sels_0_T_68 = bits(free_list, 68, 68) node _sels_sels_0_T_69 = bits(free_list, 69, 69) node _sels_sels_0_T_70 = bits(free_list, 70, 70) node _sels_sels_0_T_71 = bits(free_list, 71, 71) node _sels_sels_0_T_72 = bits(free_list, 72, 72) node _sels_sels_0_T_73 = bits(free_list, 73, 73) node _sels_sels_0_T_74 = bits(free_list, 74, 74) node _sels_sels_0_T_75 = bits(free_list, 75, 75) node _sels_sels_0_T_76 = bits(free_list, 76, 76) node _sels_sels_0_T_77 = bits(free_list, 77, 77) node _sels_sels_0_T_78 = bits(free_list, 78, 78) node _sels_sels_0_T_79 = bits(free_list, 79, 79) node _sels_sels_0_T_80 = mux(_sels_sels_0_T_79, UInt<80>(0h80000000000000000000), UInt<80>(0h0)) node _sels_sels_0_T_81 = mux(_sels_sels_0_T_78, UInt<80>(0h40000000000000000000), _sels_sels_0_T_80) node _sels_sels_0_T_82 = mux(_sels_sels_0_T_77, UInt<80>(0h20000000000000000000), _sels_sels_0_T_81) node _sels_sels_0_T_83 = mux(_sels_sels_0_T_76, UInt<80>(0h10000000000000000000), _sels_sels_0_T_82) node _sels_sels_0_T_84 = mux(_sels_sels_0_T_75, UInt<80>(0h8000000000000000000), _sels_sels_0_T_83) node _sels_sels_0_T_85 = mux(_sels_sels_0_T_74, UInt<80>(0h4000000000000000000), _sels_sels_0_T_84) node _sels_sels_0_T_86 = mux(_sels_sels_0_T_73, UInt<80>(0h2000000000000000000), _sels_sels_0_T_85) node _sels_sels_0_T_87 = mux(_sels_sels_0_T_72, UInt<80>(0h1000000000000000000), _sels_sels_0_T_86) node _sels_sels_0_T_88 = mux(_sels_sels_0_T_71, UInt<80>(0h800000000000000000), _sels_sels_0_T_87) node _sels_sels_0_T_89 = mux(_sels_sels_0_T_70, UInt<80>(0h400000000000000000), _sels_sels_0_T_88) node _sels_sels_0_T_90 = mux(_sels_sels_0_T_69, UInt<80>(0h200000000000000000), _sels_sels_0_T_89) node _sels_sels_0_T_91 = mux(_sels_sels_0_T_68, UInt<80>(0h100000000000000000), _sels_sels_0_T_90) node _sels_sels_0_T_92 = mux(_sels_sels_0_T_67, UInt<80>(0h80000000000000000), _sels_sels_0_T_91) node _sels_sels_0_T_93 = mux(_sels_sels_0_T_66, UInt<80>(0h40000000000000000), _sels_sels_0_T_92) node _sels_sels_0_T_94 = mux(_sels_sels_0_T_65, UInt<80>(0h20000000000000000), _sels_sels_0_T_93) node _sels_sels_0_T_95 = mux(_sels_sels_0_T_64, UInt<80>(0h10000000000000000), _sels_sels_0_T_94) node _sels_sels_0_T_96 = mux(_sels_sels_0_T_63, UInt<80>(0h8000000000000000), _sels_sels_0_T_95) node _sels_sels_0_T_97 = mux(_sels_sels_0_T_62, UInt<80>(0h4000000000000000), _sels_sels_0_T_96) node _sels_sels_0_T_98 = mux(_sels_sels_0_T_61, UInt<80>(0h2000000000000000), _sels_sels_0_T_97) node _sels_sels_0_T_99 = mux(_sels_sels_0_T_60, UInt<80>(0h1000000000000000), _sels_sels_0_T_98) node _sels_sels_0_T_100 = mux(_sels_sels_0_T_59, UInt<80>(0h800000000000000), _sels_sels_0_T_99) node _sels_sels_0_T_101 = mux(_sels_sels_0_T_58, UInt<80>(0h400000000000000), _sels_sels_0_T_100) node _sels_sels_0_T_102 = mux(_sels_sels_0_T_57, UInt<80>(0h200000000000000), _sels_sels_0_T_101) node _sels_sels_0_T_103 = mux(_sels_sels_0_T_56, UInt<80>(0h100000000000000), _sels_sels_0_T_102) node _sels_sels_0_T_104 = mux(_sels_sels_0_T_55, UInt<80>(0h80000000000000), _sels_sels_0_T_103) node _sels_sels_0_T_105 = mux(_sels_sels_0_T_54, UInt<80>(0h40000000000000), _sels_sels_0_T_104) node _sels_sels_0_T_106 = mux(_sels_sels_0_T_53, UInt<80>(0h20000000000000), _sels_sels_0_T_105) node _sels_sels_0_T_107 = mux(_sels_sels_0_T_52, UInt<80>(0h10000000000000), _sels_sels_0_T_106) node _sels_sels_0_T_108 = mux(_sels_sels_0_T_51, UInt<80>(0h8000000000000), _sels_sels_0_T_107) node _sels_sels_0_T_109 = mux(_sels_sels_0_T_50, UInt<80>(0h4000000000000), _sels_sels_0_T_108) node _sels_sels_0_T_110 = mux(_sels_sels_0_T_49, UInt<80>(0h2000000000000), _sels_sels_0_T_109) node _sels_sels_0_T_111 = mux(_sels_sels_0_T_48, UInt<80>(0h1000000000000), _sels_sels_0_T_110) node _sels_sels_0_T_112 = mux(_sels_sels_0_T_47, UInt<80>(0h800000000000), _sels_sels_0_T_111) node _sels_sels_0_T_113 = mux(_sels_sels_0_T_46, UInt<80>(0h400000000000), _sels_sels_0_T_112) node _sels_sels_0_T_114 = mux(_sels_sels_0_T_45, UInt<80>(0h200000000000), _sels_sels_0_T_113) node _sels_sels_0_T_115 = mux(_sels_sels_0_T_44, UInt<80>(0h100000000000), _sels_sels_0_T_114) node _sels_sels_0_T_116 = mux(_sels_sels_0_T_43, UInt<80>(0h80000000000), _sels_sels_0_T_115) node _sels_sels_0_T_117 = mux(_sels_sels_0_T_42, UInt<80>(0h40000000000), _sels_sels_0_T_116) node _sels_sels_0_T_118 = mux(_sels_sels_0_T_41, UInt<80>(0h20000000000), _sels_sels_0_T_117) node _sels_sels_0_T_119 = mux(_sels_sels_0_T_40, UInt<80>(0h10000000000), _sels_sels_0_T_118) node _sels_sels_0_T_120 = mux(_sels_sels_0_T_39, UInt<80>(0h8000000000), _sels_sels_0_T_119) node _sels_sels_0_T_121 = mux(_sels_sels_0_T_38, UInt<80>(0h4000000000), _sels_sels_0_T_120) node _sels_sels_0_T_122 = mux(_sels_sels_0_T_37, UInt<80>(0h2000000000), _sels_sels_0_T_121) node _sels_sels_0_T_123 = mux(_sels_sels_0_T_36, UInt<80>(0h1000000000), _sels_sels_0_T_122) node _sels_sels_0_T_124 = mux(_sels_sels_0_T_35, UInt<80>(0h800000000), _sels_sels_0_T_123) node _sels_sels_0_T_125 = mux(_sels_sels_0_T_34, UInt<80>(0h400000000), _sels_sels_0_T_124) node _sels_sels_0_T_126 = mux(_sels_sels_0_T_33, UInt<80>(0h200000000), _sels_sels_0_T_125) node _sels_sels_0_T_127 = mux(_sels_sels_0_T_32, UInt<80>(0h100000000), _sels_sels_0_T_126) node _sels_sels_0_T_128 = mux(_sels_sels_0_T_31, UInt<80>(0h80000000), _sels_sels_0_T_127) node _sels_sels_0_T_129 = mux(_sels_sels_0_T_30, UInt<80>(0h40000000), _sels_sels_0_T_128) node _sels_sels_0_T_130 = mux(_sels_sels_0_T_29, UInt<80>(0h20000000), _sels_sels_0_T_129) node _sels_sels_0_T_131 = mux(_sels_sels_0_T_28, UInt<80>(0h10000000), _sels_sels_0_T_130) node _sels_sels_0_T_132 = mux(_sels_sels_0_T_27, UInt<80>(0h8000000), _sels_sels_0_T_131) node _sels_sels_0_T_133 = mux(_sels_sels_0_T_26, UInt<80>(0h4000000), _sels_sels_0_T_132) node _sels_sels_0_T_134 = mux(_sels_sels_0_T_25, UInt<80>(0h2000000), _sels_sels_0_T_133) node _sels_sels_0_T_135 = mux(_sels_sels_0_T_24, UInt<80>(0h1000000), _sels_sels_0_T_134) node _sels_sels_0_T_136 = mux(_sels_sels_0_T_23, UInt<80>(0h800000), _sels_sels_0_T_135) node _sels_sels_0_T_137 = mux(_sels_sels_0_T_22, UInt<80>(0h400000), _sels_sels_0_T_136) node _sels_sels_0_T_138 = mux(_sels_sels_0_T_21, UInt<80>(0h200000), _sels_sels_0_T_137) node _sels_sels_0_T_139 = mux(_sels_sels_0_T_20, UInt<80>(0h100000), _sels_sels_0_T_138) node _sels_sels_0_T_140 = mux(_sels_sels_0_T_19, UInt<80>(0h80000), _sels_sels_0_T_139) node _sels_sels_0_T_141 = mux(_sels_sels_0_T_18, UInt<80>(0h40000), _sels_sels_0_T_140) node _sels_sels_0_T_142 = mux(_sels_sels_0_T_17, UInt<80>(0h20000), _sels_sels_0_T_141) node _sels_sels_0_T_143 = mux(_sels_sels_0_T_16, UInt<80>(0h10000), _sels_sels_0_T_142) node _sels_sels_0_T_144 = mux(_sels_sels_0_T_15, UInt<80>(0h8000), _sels_sels_0_T_143) node _sels_sels_0_T_145 = mux(_sels_sels_0_T_14, UInt<80>(0h4000), _sels_sels_0_T_144) node _sels_sels_0_T_146 = mux(_sels_sels_0_T_13, UInt<80>(0h2000), _sels_sels_0_T_145) node _sels_sels_0_T_147 = mux(_sels_sels_0_T_12, UInt<80>(0h1000), _sels_sels_0_T_146) node _sels_sels_0_T_148 = mux(_sels_sels_0_T_11, UInt<80>(0h800), _sels_sels_0_T_147) node _sels_sels_0_T_149 = mux(_sels_sels_0_T_10, UInt<80>(0h400), _sels_sels_0_T_148) node _sels_sels_0_T_150 = mux(_sels_sels_0_T_9, UInt<80>(0h200), _sels_sels_0_T_149) node _sels_sels_0_T_151 = mux(_sels_sels_0_T_8, UInt<80>(0h100), _sels_sels_0_T_150) node _sels_sels_0_T_152 = mux(_sels_sels_0_T_7, UInt<80>(0h80), _sels_sels_0_T_151) node _sels_sels_0_T_153 = mux(_sels_sels_0_T_6, UInt<80>(0h40), _sels_sels_0_T_152) node _sels_sels_0_T_154 = mux(_sels_sels_0_T_5, UInt<80>(0h20), _sels_sels_0_T_153) node _sels_sels_0_T_155 = mux(_sels_sels_0_T_4, UInt<80>(0h10), _sels_sels_0_T_154) node _sels_sels_0_T_156 = mux(_sels_sels_0_T_3, UInt<80>(0h8), _sels_sels_0_T_155) node _sels_sels_0_T_157 = mux(_sels_sels_0_T_2, UInt<80>(0h4), _sels_sels_0_T_156) node _sels_sels_0_T_158 = mux(_sels_sels_0_T_1, UInt<80>(0h2), _sels_sels_0_T_157) node _sels_sels_0_T_159 = mux(_sels_sels_0_T, UInt<80>(0h1), _sels_sels_0_T_158) connect sels[0], _sels_sels_0_T_159 node _sels_T = not(sels[0]) node _sels_T_1 = and(free_list, _sels_T) node _sels_sels_1_T = bits(_sels_T_1, 0, 0) node _sels_sels_1_T_1 = bits(_sels_T_1, 1, 1) node _sels_sels_1_T_2 = bits(_sels_T_1, 2, 2) node _sels_sels_1_T_3 = bits(_sels_T_1, 3, 3) node _sels_sels_1_T_4 = bits(_sels_T_1, 4, 4) node _sels_sels_1_T_5 = bits(_sels_T_1, 5, 5) node _sels_sels_1_T_6 = bits(_sels_T_1, 6, 6) node _sels_sels_1_T_7 = bits(_sels_T_1, 7, 7) node _sels_sels_1_T_8 = bits(_sels_T_1, 8, 8) node _sels_sels_1_T_9 = bits(_sels_T_1, 9, 9) node _sels_sels_1_T_10 = bits(_sels_T_1, 10, 10) node _sels_sels_1_T_11 = bits(_sels_T_1, 11, 11) node _sels_sels_1_T_12 = bits(_sels_T_1, 12, 12) node _sels_sels_1_T_13 = bits(_sels_T_1, 13, 13) node _sels_sels_1_T_14 = bits(_sels_T_1, 14, 14) node _sels_sels_1_T_15 = bits(_sels_T_1, 15, 15) node _sels_sels_1_T_16 = bits(_sels_T_1, 16, 16) node _sels_sels_1_T_17 = bits(_sels_T_1, 17, 17) node _sels_sels_1_T_18 = bits(_sels_T_1, 18, 18) node _sels_sels_1_T_19 = bits(_sels_T_1, 19, 19) node _sels_sels_1_T_20 = bits(_sels_T_1, 20, 20) node _sels_sels_1_T_21 = bits(_sels_T_1, 21, 21) node _sels_sels_1_T_22 = bits(_sels_T_1, 22, 22) node _sels_sels_1_T_23 = bits(_sels_T_1, 23, 23) node _sels_sels_1_T_24 = bits(_sels_T_1, 24, 24) node _sels_sels_1_T_25 = bits(_sels_T_1, 25, 25) node _sels_sels_1_T_26 = bits(_sels_T_1, 26, 26) node _sels_sels_1_T_27 = bits(_sels_T_1, 27, 27) node _sels_sels_1_T_28 = bits(_sels_T_1, 28, 28) node _sels_sels_1_T_29 = bits(_sels_T_1, 29, 29) node _sels_sels_1_T_30 = bits(_sels_T_1, 30, 30) node _sels_sels_1_T_31 = bits(_sels_T_1, 31, 31) node _sels_sels_1_T_32 = bits(_sels_T_1, 32, 32) node _sels_sels_1_T_33 = bits(_sels_T_1, 33, 33) node _sels_sels_1_T_34 = bits(_sels_T_1, 34, 34) node _sels_sels_1_T_35 = bits(_sels_T_1, 35, 35) node _sels_sels_1_T_36 = bits(_sels_T_1, 36, 36) node _sels_sels_1_T_37 = bits(_sels_T_1, 37, 37) node _sels_sels_1_T_38 = bits(_sels_T_1, 38, 38) node _sels_sels_1_T_39 = bits(_sels_T_1, 39, 39) node _sels_sels_1_T_40 = bits(_sels_T_1, 40, 40) node _sels_sels_1_T_41 = bits(_sels_T_1, 41, 41) node _sels_sels_1_T_42 = bits(_sels_T_1, 42, 42) node _sels_sels_1_T_43 = bits(_sels_T_1, 43, 43) node _sels_sels_1_T_44 = bits(_sels_T_1, 44, 44) node _sels_sels_1_T_45 = bits(_sels_T_1, 45, 45) node _sels_sels_1_T_46 = bits(_sels_T_1, 46, 46) node _sels_sels_1_T_47 = bits(_sels_T_1, 47, 47) node _sels_sels_1_T_48 = bits(_sels_T_1, 48, 48) node _sels_sels_1_T_49 = bits(_sels_T_1, 49, 49) node _sels_sels_1_T_50 = bits(_sels_T_1, 50, 50) node _sels_sels_1_T_51 = bits(_sels_T_1, 51, 51) node _sels_sels_1_T_52 = bits(_sels_T_1, 52, 52) node _sels_sels_1_T_53 = bits(_sels_T_1, 53, 53) node _sels_sels_1_T_54 = bits(_sels_T_1, 54, 54) node _sels_sels_1_T_55 = bits(_sels_T_1, 55, 55) node _sels_sels_1_T_56 = bits(_sels_T_1, 56, 56) node _sels_sels_1_T_57 = bits(_sels_T_1, 57, 57) node _sels_sels_1_T_58 = bits(_sels_T_1, 58, 58) node _sels_sels_1_T_59 = bits(_sels_T_1, 59, 59) node _sels_sels_1_T_60 = bits(_sels_T_1, 60, 60) node _sels_sels_1_T_61 = bits(_sels_T_1, 61, 61) node _sels_sels_1_T_62 = bits(_sels_T_1, 62, 62) node _sels_sels_1_T_63 = bits(_sels_T_1, 63, 63) node _sels_sels_1_T_64 = bits(_sels_T_1, 64, 64) node _sels_sels_1_T_65 = bits(_sels_T_1, 65, 65) node _sels_sels_1_T_66 = bits(_sels_T_1, 66, 66) node _sels_sels_1_T_67 = bits(_sels_T_1, 67, 67) node _sels_sels_1_T_68 = bits(_sels_T_1, 68, 68) node _sels_sels_1_T_69 = bits(_sels_T_1, 69, 69) node _sels_sels_1_T_70 = bits(_sels_T_1, 70, 70) node _sels_sels_1_T_71 = bits(_sels_T_1, 71, 71) node _sels_sels_1_T_72 = bits(_sels_T_1, 72, 72) node _sels_sels_1_T_73 = bits(_sels_T_1, 73, 73) node _sels_sels_1_T_74 = bits(_sels_T_1, 74, 74) node _sels_sels_1_T_75 = bits(_sels_T_1, 75, 75) node _sels_sels_1_T_76 = bits(_sels_T_1, 76, 76) node _sels_sels_1_T_77 = bits(_sels_T_1, 77, 77) node _sels_sels_1_T_78 = bits(_sels_T_1, 78, 78) node _sels_sels_1_T_79 = bits(_sels_T_1, 79, 79) node _sels_sels_1_T_80 = mux(_sels_sels_1_T_79, UInt<80>(0h80000000000000000000), UInt<80>(0h0)) node _sels_sels_1_T_81 = mux(_sels_sels_1_T_78, UInt<80>(0h40000000000000000000), _sels_sels_1_T_80) node _sels_sels_1_T_82 = mux(_sels_sels_1_T_77, UInt<80>(0h20000000000000000000), _sels_sels_1_T_81) node _sels_sels_1_T_83 = mux(_sels_sels_1_T_76, UInt<80>(0h10000000000000000000), _sels_sels_1_T_82) node _sels_sels_1_T_84 = mux(_sels_sels_1_T_75, UInt<80>(0h8000000000000000000), _sels_sels_1_T_83) node _sels_sels_1_T_85 = mux(_sels_sels_1_T_74, UInt<80>(0h4000000000000000000), _sels_sels_1_T_84) node _sels_sels_1_T_86 = mux(_sels_sels_1_T_73, UInt<80>(0h2000000000000000000), _sels_sels_1_T_85) node _sels_sels_1_T_87 = mux(_sels_sels_1_T_72, UInt<80>(0h1000000000000000000), _sels_sels_1_T_86) node _sels_sels_1_T_88 = mux(_sels_sels_1_T_71, UInt<80>(0h800000000000000000), _sels_sels_1_T_87) node _sels_sels_1_T_89 = mux(_sels_sels_1_T_70, UInt<80>(0h400000000000000000), _sels_sels_1_T_88) node _sels_sels_1_T_90 = mux(_sels_sels_1_T_69, UInt<80>(0h200000000000000000), _sels_sels_1_T_89) node _sels_sels_1_T_91 = mux(_sels_sels_1_T_68, UInt<80>(0h100000000000000000), _sels_sels_1_T_90) node _sels_sels_1_T_92 = mux(_sels_sels_1_T_67, UInt<80>(0h80000000000000000), _sels_sels_1_T_91) node _sels_sels_1_T_93 = mux(_sels_sels_1_T_66, UInt<80>(0h40000000000000000), _sels_sels_1_T_92) node _sels_sels_1_T_94 = mux(_sels_sels_1_T_65, UInt<80>(0h20000000000000000), _sels_sels_1_T_93) node _sels_sels_1_T_95 = mux(_sels_sels_1_T_64, UInt<80>(0h10000000000000000), _sels_sels_1_T_94) node _sels_sels_1_T_96 = mux(_sels_sels_1_T_63, UInt<80>(0h8000000000000000), _sels_sels_1_T_95) node _sels_sels_1_T_97 = mux(_sels_sels_1_T_62, UInt<80>(0h4000000000000000), _sels_sels_1_T_96) node _sels_sels_1_T_98 = mux(_sels_sels_1_T_61, UInt<80>(0h2000000000000000), _sels_sels_1_T_97) node _sels_sels_1_T_99 = mux(_sels_sels_1_T_60, UInt<80>(0h1000000000000000), _sels_sels_1_T_98) node _sels_sels_1_T_100 = mux(_sels_sels_1_T_59, UInt<80>(0h800000000000000), _sels_sels_1_T_99) node _sels_sels_1_T_101 = mux(_sels_sels_1_T_58, UInt<80>(0h400000000000000), _sels_sels_1_T_100) node _sels_sels_1_T_102 = mux(_sels_sels_1_T_57, UInt<80>(0h200000000000000), _sels_sels_1_T_101) node _sels_sels_1_T_103 = mux(_sels_sels_1_T_56, UInt<80>(0h100000000000000), _sels_sels_1_T_102) node _sels_sels_1_T_104 = mux(_sels_sels_1_T_55, UInt<80>(0h80000000000000), _sels_sels_1_T_103) node _sels_sels_1_T_105 = mux(_sels_sels_1_T_54, UInt<80>(0h40000000000000), _sels_sels_1_T_104) node _sels_sels_1_T_106 = mux(_sels_sels_1_T_53, UInt<80>(0h20000000000000), _sels_sels_1_T_105) node _sels_sels_1_T_107 = mux(_sels_sels_1_T_52, UInt<80>(0h10000000000000), _sels_sels_1_T_106) node _sels_sels_1_T_108 = mux(_sels_sels_1_T_51, UInt<80>(0h8000000000000), _sels_sels_1_T_107) node _sels_sels_1_T_109 = mux(_sels_sels_1_T_50, UInt<80>(0h4000000000000), _sels_sels_1_T_108) node _sels_sels_1_T_110 = mux(_sels_sels_1_T_49, UInt<80>(0h2000000000000), _sels_sels_1_T_109) node _sels_sels_1_T_111 = mux(_sels_sels_1_T_48, UInt<80>(0h1000000000000), _sels_sels_1_T_110) node _sels_sels_1_T_112 = mux(_sels_sels_1_T_47, UInt<80>(0h800000000000), _sels_sels_1_T_111) node _sels_sels_1_T_113 = mux(_sels_sels_1_T_46, UInt<80>(0h400000000000), _sels_sels_1_T_112) node _sels_sels_1_T_114 = mux(_sels_sels_1_T_45, UInt<80>(0h200000000000), _sels_sels_1_T_113) node _sels_sels_1_T_115 = mux(_sels_sels_1_T_44, UInt<80>(0h100000000000), _sels_sels_1_T_114) node _sels_sels_1_T_116 = mux(_sels_sels_1_T_43, UInt<80>(0h80000000000), _sels_sels_1_T_115) node _sels_sels_1_T_117 = mux(_sels_sels_1_T_42, UInt<80>(0h40000000000), _sels_sels_1_T_116) node _sels_sels_1_T_118 = mux(_sels_sels_1_T_41, UInt<80>(0h20000000000), _sels_sels_1_T_117) node _sels_sels_1_T_119 = mux(_sels_sels_1_T_40, UInt<80>(0h10000000000), _sels_sels_1_T_118) node _sels_sels_1_T_120 = mux(_sels_sels_1_T_39, UInt<80>(0h8000000000), _sels_sels_1_T_119) node _sels_sels_1_T_121 = mux(_sels_sels_1_T_38, UInt<80>(0h4000000000), _sels_sels_1_T_120) node _sels_sels_1_T_122 = mux(_sels_sels_1_T_37, UInt<80>(0h2000000000), _sels_sels_1_T_121) node _sels_sels_1_T_123 = mux(_sels_sels_1_T_36, UInt<80>(0h1000000000), _sels_sels_1_T_122) node _sels_sels_1_T_124 = mux(_sels_sels_1_T_35, UInt<80>(0h800000000), _sels_sels_1_T_123) node _sels_sels_1_T_125 = mux(_sels_sels_1_T_34, UInt<80>(0h400000000), _sels_sels_1_T_124) node _sels_sels_1_T_126 = mux(_sels_sels_1_T_33, UInt<80>(0h200000000), _sels_sels_1_T_125) node _sels_sels_1_T_127 = mux(_sels_sels_1_T_32, UInt<80>(0h100000000), _sels_sels_1_T_126) node _sels_sels_1_T_128 = mux(_sels_sels_1_T_31, UInt<80>(0h80000000), _sels_sels_1_T_127) node _sels_sels_1_T_129 = mux(_sels_sels_1_T_30, UInt<80>(0h40000000), _sels_sels_1_T_128) node _sels_sels_1_T_130 = mux(_sels_sels_1_T_29, UInt<80>(0h20000000), _sels_sels_1_T_129) node _sels_sels_1_T_131 = mux(_sels_sels_1_T_28, UInt<80>(0h10000000), _sels_sels_1_T_130) node _sels_sels_1_T_132 = mux(_sels_sels_1_T_27, UInt<80>(0h8000000), _sels_sels_1_T_131) node _sels_sels_1_T_133 = mux(_sels_sels_1_T_26, UInt<80>(0h4000000), _sels_sels_1_T_132) node _sels_sels_1_T_134 = mux(_sels_sels_1_T_25, UInt<80>(0h2000000), _sels_sels_1_T_133) node _sels_sels_1_T_135 = mux(_sels_sels_1_T_24, UInt<80>(0h1000000), _sels_sels_1_T_134) node _sels_sels_1_T_136 = mux(_sels_sels_1_T_23, UInt<80>(0h800000), _sels_sels_1_T_135) node _sels_sels_1_T_137 = mux(_sels_sels_1_T_22, UInt<80>(0h400000), _sels_sels_1_T_136) node _sels_sels_1_T_138 = mux(_sels_sels_1_T_21, UInt<80>(0h200000), _sels_sels_1_T_137) node _sels_sels_1_T_139 = mux(_sels_sels_1_T_20, UInt<80>(0h100000), _sels_sels_1_T_138) node _sels_sels_1_T_140 = mux(_sels_sels_1_T_19, UInt<80>(0h80000), _sels_sels_1_T_139) node _sels_sels_1_T_141 = mux(_sels_sels_1_T_18, UInt<80>(0h40000), _sels_sels_1_T_140) node _sels_sels_1_T_142 = mux(_sels_sels_1_T_17, UInt<80>(0h20000), _sels_sels_1_T_141) node _sels_sels_1_T_143 = mux(_sels_sels_1_T_16, UInt<80>(0h10000), _sels_sels_1_T_142) node _sels_sels_1_T_144 = mux(_sels_sels_1_T_15, UInt<80>(0h8000), _sels_sels_1_T_143) node _sels_sels_1_T_145 = mux(_sels_sels_1_T_14, UInt<80>(0h4000), _sels_sels_1_T_144) node _sels_sels_1_T_146 = mux(_sels_sels_1_T_13, UInt<80>(0h2000), _sels_sels_1_T_145) node _sels_sels_1_T_147 = mux(_sels_sels_1_T_12, UInt<80>(0h1000), _sels_sels_1_T_146) node _sels_sels_1_T_148 = mux(_sels_sels_1_T_11, UInt<80>(0h800), _sels_sels_1_T_147) node _sels_sels_1_T_149 = mux(_sels_sels_1_T_10, UInt<80>(0h400), _sels_sels_1_T_148) node _sels_sels_1_T_150 = mux(_sels_sels_1_T_9, UInt<80>(0h200), _sels_sels_1_T_149) node _sels_sels_1_T_151 = mux(_sels_sels_1_T_8, UInt<80>(0h100), _sels_sels_1_T_150) node _sels_sels_1_T_152 = mux(_sels_sels_1_T_7, UInt<80>(0h80), _sels_sels_1_T_151) node _sels_sels_1_T_153 = mux(_sels_sels_1_T_6, UInt<80>(0h40), _sels_sels_1_T_152) node _sels_sels_1_T_154 = mux(_sels_sels_1_T_5, UInt<80>(0h20), _sels_sels_1_T_153) node _sels_sels_1_T_155 = mux(_sels_sels_1_T_4, UInt<80>(0h10), _sels_sels_1_T_154) node _sels_sels_1_T_156 = mux(_sels_sels_1_T_3, UInt<80>(0h8), _sels_sels_1_T_155) node _sels_sels_1_T_157 = mux(_sels_sels_1_T_2, UInt<80>(0h4), _sels_sels_1_T_156) node _sels_sels_1_T_158 = mux(_sels_sels_1_T_1, UInt<80>(0h2), _sels_sels_1_T_157) node _sels_sels_1_T_159 = mux(_sels_sels_1_T, UInt<80>(0h1), _sels_sels_1_T_158) connect sels[1], _sels_sels_1_T_159 node _sels_T_2 = not(sels[1]) node _sels_T_3 = and(_sels_T_1, _sels_T_2) wire sel_fire : UInt<1>[2] node _allocs_T = dshl(UInt<1>(0h1), io.alloc_pregs[0].bits) node allocs_0 = bits(_allocs_T, 79, 0) node _allocs_T_1 = dshl(UInt<1>(0h1), io.alloc_pregs[1].bits) node allocs_1 = bits(_allocs_T_1, 79, 0) node _alloc_masks_T = mux(io.reqs[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _alloc_masks_T_1 = and(allocs_1, _alloc_masks_T) node alloc_masks_1 = or(UInt<80>(0h0), _alloc_masks_T_1) node _alloc_masks_T_2 = mux(io.reqs[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _alloc_masks_T_3 = and(allocs_0, _alloc_masks_T_2) node alloc_masks_0 = or(alloc_masks_1, _alloc_masks_T_3) node _sel_mask_T = mux(sel_fire[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _sel_mask_T_1 = and(sels[0], _sel_mask_T) node _sel_mask_T_2 = mux(sel_fire[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _sel_mask_T_3 = and(sels[1], _sel_mask_T_2) node sel_mask = or(_sel_mask_T_1, _sel_mask_T_3) node _br_deallocs_T = mux(io.brupdate.b2.mispredict, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node br_deallocs = and(br_alloc_lists[io.brupdate.b2.uop.br_tag], _br_deallocs_T) reg com_deallocs_REG : { valid : UInt<1>, bits : UInt<7>}[2], clock connect com_deallocs_REG[0].bits, io.dealloc[0].bits connect com_deallocs_REG[0].valid, io.dealloc[0].valid connect com_deallocs_REG[1].bits, io.dealloc[1].bits connect com_deallocs_REG[1].valid, io.dealloc[1].valid node _com_deallocs_T = dshl(UInt<1>(0h1), com_deallocs_REG[0].bits) node _com_deallocs_T_1 = bits(_com_deallocs_T, 79, 0) node _com_deallocs_T_2 = mux(com_deallocs_REG[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_deallocs_T_3 = and(_com_deallocs_T_1, _com_deallocs_T_2) node _com_deallocs_T_4 = dshl(UInt<1>(0h1), com_deallocs_REG[1].bits) node _com_deallocs_T_5 = bits(_com_deallocs_T_4, 79, 0) node _com_deallocs_T_6 = mux(com_deallocs_REG[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_deallocs_T_7 = and(_com_deallocs_T_5, _com_deallocs_T_6) node com_deallocs = or(_com_deallocs_T_3, _com_deallocs_T_7) node _rollback_deallocs_T = mux(io.rollback, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node rollback_deallocs = and(spec_alloc_list, _rollback_deallocs_T) node _dealloc_mask_T = or(com_deallocs, br_deallocs) node dealloc_mask = or(_dealloc_mask_T, rollback_deallocs) node _com_despec_T = dshl(UInt<1>(0h1), io.despec[0].bits) node _com_despec_T_1 = bits(_com_despec_T, 79, 0) node _com_despec_T_2 = mux(io.despec[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_despec_T_3 = and(_com_despec_T_1, _com_despec_T_2) node _com_despec_T_4 = dshl(UInt<1>(0h1), io.despec[1].bits) node _com_despec_T_5 = bits(_com_despec_T_4, 79, 0) node _com_despec_T_6 = mux(io.despec[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_despec_T_7 = and(_com_despec_T_5, _com_despec_T_6) node com_despec = or(_com_despec_T_3, _com_despec_T_7) node _updated_br_alloc_list_T = not(br_deallocs) node _updated_br_alloc_list_T_1 = and(br_alloc_lists[0], _updated_br_alloc_list_T) node updated_br_alloc_list = or(_updated_br_alloc_list_T_1, alloc_masks_0) connect br_alloc_lists[0], updated_br_alloc_list node _updated_br_alloc_list_T_2 = not(br_deallocs) node _updated_br_alloc_list_T_3 = and(br_alloc_lists[1], _updated_br_alloc_list_T_2) node updated_br_alloc_list_1 = or(_updated_br_alloc_list_T_3, alloc_masks_0) connect br_alloc_lists[1], updated_br_alloc_list_1 node _updated_br_alloc_list_T_4 = not(br_deallocs) node _updated_br_alloc_list_T_5 = and(br_alloc_lists[2], _updated_br_alloc_list_T_4) node updated_br_alloc_list_2 = or(_updated_br_alloc_list_T_5, alloc_masks_0) connect br_alloc_lists[2], updated_br_alloc_list_2 node _updated_br_alloc_list_T_6 = not(br_deallocs) node _updated_br_alloc_list_T_7 = and(br_alloc_lists[3], _updated_br_alloc_list_T_6) node updated_br_alloc_list_3 = or(_updated_br_alloc_list_T_7, alloc_masks_0) connect br_alloc_lists[3], updated_br_alloc_list_3 node _updated_br_alloc_list_T_8 = not(br_deallocs) node _updated_br_alloc_list_T_9 = and(br_alloc_lists[4], _updated_br_alloc_list_T_8) node updated_br_alloc_list_4 = or(_updated_br_alloc_list_T_9, alloc_masks_0) connect br_alloc_lists[4], updated_br_alloc_list_4 node _updated_br_alloc_list_T_10 = not(br_deallocs) node _updated_br_alloc_list_T_11 = and(br_alloc_lists[5], _updated_br_alloc_list_T_10) node updated_br_alloc_list_5 = or(_updated_br_alloc_list_T_11, alloc_masks_0) connect br_alloc_lists[5], updated_br_alloc_list_5 node _updated_br_alloc_list_T_12 = not(br_deallocs) node _updated_br_alloc_list_T_13 = and(br_alloc_lists[6], _updated_br_alloc_list_T_12) node updated_br_alloc_list_6 = or(_updated_br_alloc_list_T_13, alloc_masks_0) connect br_alloc_lists[6], updated_br_alloc_list_6 node _updated_br_alloc_list_T_14 = not(br_deallocs) node _updated_br_alloc_list_T_15 = and(br_alloc_lists[7], _updated_br_alloc_list_T_14) node updated_br_alloc_list_7 = or(_updated_br_alloc_list_T_15, alloc_masks_0) connect br_alloc_lists[7], updated_br_alloc_list_7 node _updated_br_alloc_list_T_16 = not(br_deallocs) node _updated_br_alloc_list_T_17 = and(br_alloc_lists[8], _updated_br_alloc_list_T_16) node updated_br_alloc_list_8 = or(_updated_br_alloc_list_T_17, alloc_masks_0) connect br_alloc_lists[8], updated_br_alloc_list_8 node _updated_br_alloc_list_T_18 = not(br_deallocs) node _updated_br_alloc_list_T_19 = and(br_alloc_lists[9], _updated_br_alloc_list_T_18) node updated_br_alloc_list_9 = or(_updated_br_alloc_list_T_19, alloc_masks_0) connect br_alloc_lists[9], updated_br_alloc_list_9 node _updated_br_alloc_list_T_20 = not(br_deallocs) node _updated_br_alloc_list_T_21 = and(br_alloc_lists[10], _updated_br_alloc_list_T_20) node updated_br_alloc_list_10 = or(_updated_br_alloc_list_T_21, alloc_masks_0) connect br_alloc_lists[10], updated_br_alloc_list_10 node _updated_br_alloc_list_T_22 = not(br_deallocs) node _updated_br_alloc_list_T_23 = and(br_alloc_lists[11], _updated_br_alloc_list_T_22) node updated_br_alloc_list_11 = or(_updated_br_alloc_list_T_23, alloc_masks_0) connect br_alloc_lists[11], updated_br_alloc_list_11 wire _br_slots_WIRE : UInt<1>[3] connect _br_slots_WIRE[0], io.ren_br_tags[0].valid connect _br_slots_WIRE[1], io.ren_br_tags[1].valid connect _br_slots_WIRE[2], io.ren_br_tags[2].valid node br_slots_hi = cat(_br_slots_WIRE[2], _br_slots_WIRE[1]) node br_slots = cat(br_slots_hi, _br_slots_WIRE[0]) node _list_req_T = eq(io.ren_br_tags[0].bits, UInt<1>(0h0)) node _list_req_T_1 = eq(io.ren_br_tags[1].bits, UInt<1>(0h0)) node _list_req_T_2 = eq(io.ren_br_tags[2].bits, UInt<1>(0h0)) wire _list_req_WIRE : UInt<1>[3] connect _list_req_WIRE[0], _list_req_T connect _list_req_WIRE[1], _list_req_T_1 connect _list_req_WIRE[2], _list_req_T_2 node list_req_hi = cat(_list_req_WIRE[2], _list_req_WIRE[1]) node _list_req_T_3 = cat(list_req_hi, _list_req_WIRE[0]) node list_req = and(_list_req_T_3, br_slots) node new_list = orr(list_req) when new_list : node _br_alloc_lists_0_T = bits(list_req, 0, 0) node _br_alloc_lists_0_T_1 = bits(list_req, 1, 1) node _br_alloc_lists_0_T_2 = bits(list_req, 2, 2) node _br_alloc_lists_0_T_3 = mux(_br_alloc_lists_0_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_0_T_4 = mux(_br_alloc_lists_0_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_0_T_5 = mux(_br_alloc_lists_0_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_0_T_6 = or(_br_alloc_lists_0_T_3, _br_alloc_lists_0_T_4) node _br_alloc_lists_0_T_7 = or(_br_alloc_lists_0_T_6, _br_alloc_lists_0_T_5) wire _br_alloc_lists_0_WIRE : UInt<80> connect _br_alloc_lists_0_WIRE, _br_alloc_lists_0_T_7 connect br_alloc_lists[0], _br_alloc_lists_0_WIRE node _list_req_T_4 = eq(io.ren_br_tags[0].bits, UInt<1>(0h1)) node _list_req_T_5 = eq(io.ren_br_tags[1].bits, UInt<1>(0h1)) node _list_req_T_6 = eq(io.ren_br_tags[2].bits, UInt<1>(0h1)) wire _list_req_WIRE_1 : UInt<1>[3] connect _list_req_WIRE_1[0], _list_req_T_4 connect _list_req_WIRE_1[1], _list_req_T_5 connect _list_req_WIRE_1[2], _list_req_T_6 node list_req_hi_1 = cat(_list_req_WIRE_1[2], _list_req_WIRE_1[1]) node _list_req_T_7 = cat(list_req_hi_1, _list_req_WIRE_1[0]) node list_req_1 = and(_list_req_T_7, br_slots) node new_list_1 = orr(list_req_1) when new_list_1 : node _br_alloc_lists_1_T = bits(list_req_1, 0, 0) node _br_alloc_lists_1_T_1 = bits(list_req_1, 1, 1) node _br_alloc_lists_1_T_2 = bits(list_req_1, 2, 2) node _br_alloc_lists_1_T_3 = mux(_br_alloc_lists_1_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_1_T_4 = mux(_br_alloc_lists_1_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_1_T_5 = mux(_br_alloc_lists_1_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_1_T_6 = or(_br_alloc_lists_1_T_3, _br_alloc_lists_1_T_4) node _br_alloc_lists_1_T_7 = or(_br_alloc_lists_1_T_6, _br_alloc_lists_1_T_5) wire _br_alloc_lists_1_WIRE : UInt<80> connect _br_alloc_lists_1_WIRE, _br_alloc_lists_1_T_7 connect br_alloc_lists[1], _br_alloc_lists_1_WIRE node _list_req_T_8 = eq(io.ren_br_tags[0].bits, UInt<2>(0h2)) node _list_req_T_9 = eq(io.ren_br_tags[1].bits, UInt<2>(0h2)) node _list_req_T_10 = eq(io.ren_br_tags[2].bits, UInt<2>(0h2)) wire _list_req_WIRE_2 : UInt<1>[3] connect _list_req_WIRE_2[0], _list_req_T_8 connect _list_req_WIRE_2[1], _list_req_T_9 connect _list_req_WIRE_2[2], _list_req_T_10 node list_req_hi_2 = cat(_list_req_WIRE_2[2], _list_req_WIRE_2[1]) node _list_req_T_11 = cat(list_req_hi_2, _list_req_WIRE_2[0]) node list_req_2 = and(_list_req_T_11, br_slots) node new_list_2 = orr(list_req_2) when new_list_2 : node _br_alloc_lists_2_T = bits(list_req_2, 0, 0) node _br_alloc_lists_2_T_1 = bits(list_req_2, 1, 1) node _br_alloc_lists_2_T_2 = bits(list_req_2, 2, 2) node _br_alloc_lists_2_T_3 = mux(_br_alloc_lists_2_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_2_T_4 = mux(_br_alloc_lists_2_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_2_T_5 = mux(_br_alloc_lists_2_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_2_T_6 = or(_br_alloc_lists_2_T_3, _br_alloc_lists_2_T_4) node _br_alloc_lists_2_T_7 = or(_br_alloc_lists_2_T_6, _br_alloc_lists_2_T_5) wire _br_alloc_lists_2_WIRE : UInt<80> connect _br_alloc_lists_2_WIRE, _br_alloc_lists_2_T_7 connect br_alloc_lists[2], _br_alloc_lists_2_WIRE node _list_req_T_12 = eq(io.ren_br_tags[0].bits, UInt<2>(0h3)) node _list_req_T_13 = eq(io.ren_br_tags[1].bits, UInt<2>(0h3)) node _list_req_T_14 = eq(io.ren_br_tags[2].bits, UInt<2>(0h3)) wire _list_req_WIRE_3 : UInt<1>[3] connect _list_req_WIRE_3[0], _list_req_T_12 connect _list_req_WIRE_3[1], _list_req_T_13 connect _list_req_WIRE_3[2], _list_req_T_14 node list_req_hi_3 = cat(_list_req_WIRE_3[2], _list_req_WIRE_3[1]) node _list_req_T_15 = cat(list_req_hi_3, _list_req_WIRE_3[0]) node list_req_3 = and(_list_req_T_15, br_slots) node new_list_3 = orr(list_req_3) when new_list_3 : node _br_alloc_lists_3_T = bits(list_req_3, 0, 0) node _br_alloc_lists_3_T_1 = bits(list_req_3, 1, 1) node _br_alloc_lists_3_T_2 = bits(list_req_3, 2, 2) node _br_alloc_lists_3_T_3 = mux(_br_alloc_lists_3_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_3_T_4 = mux(_br_alloc_lists_3_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_3_T_5 = mux(_br_alloc_lists_3_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_3_T_6 = or(_br_alloc_lists_3_T_3, _br_alloc_lists_3_T_4) node _br_alloc_lists_3_T_7 = or(_br_alloc_lists_3_T_6, _br_alloc_lists_3_T_5) wire _br_alloc_lists_3_WIRE : UInt<80> connect _br_alloc_lists_3_WIRE, _br_alloc_lists_3_T_7 connect br_alloc_lists[3], _br_alloc_lists_3_WIRE node _list_req_T_16 = eq(io.ren_br_tags[0].bits, UInt<3>(0h4)) node _list_req_T_17 = eq(io.ren_br_tags[1].bits, UInt<3>(0h4)) node _list_req_T_18 = eq(io.ren_br_tags[2].bits, UInt<3>(0h4)) wire _list_req_WIRE_4 : UInt<1>[3] connect _list_req_WIRE_4[0], _list_req_T_16 connect _list_req_WIRE_4[1], _list_req_T_17 connect _list_req_WIRE_4[2], _list_req_T_18 node list_req_hi_4 = cat(_list_req_WIRE_4[2], _list_req_WIRE_4[1]) node _list_req_T_19 = cat(list_req_hi_4, _list_req_WIRE_4[0]) node list_req_4 = and(_list_req_T_19, br_slots) node new_list_4 = orr(list_req_4) when new_list_4 : node _br_alloc_lists_4_T = bits(list_req_4, 0, 0) node _br_alloc_lists_4_T_1 = bits(list_req_4, 1, 1) node _br_alloc_lists_4_T_2 = bits(list_req_4, 2, 2) node _br_alloc_lists_4_T_3 = mux(_br_alloc_lists_4_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_4_T_4 = mux(_br_alloc_lists_4_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_4_T_5 = mux(_br_alloc_lists_4_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_4_T_6 = or(_br_alloc_lists_4_T_3, _br_alloc_lists_4_T_4) node _br_alloc_lists_4_T_7 = or(_br_alloc_lists_4_T_6, _br_alloc_lists_4_T_5) wire _br_alloc_lists_4_WIRE : UInt<80> connect _br_alloc_lists_4_WIRE, _br_alloc_lists_4_T_7 connect br_alloc_lists[4], _br_alloc_lists_4_WIRE node _list_req_T_20 = eq(io.ren_br_tags[0].bits, UInt<3>(0h5)) node _list_req_T_21 = eq(io.ren_br_tags[1].bits, UInt<3>(0h5)) node _list_req_T_22 = eq(io.ren_br_tags[2].bits, UInt<3>(0h5)) wire _list_req_WIRE_5 : UInt<1>[3] connect _list_req_WIRE_5[0], _list_req_T_20 connect _list_req_WIRE_5[1], _list_req_T_21 connect _list_req_WIRE_5[2], _list_req_T_22 node list_req_hi_5 = cat(_list_req_WIRE_5[2], _list_req_WIRE_5[1]) node _list_req_T_23 = cat(list_req_hi_5, _list_req_WIRE_5[0]) node list_req_5 = and(_list_req_T_23, br_slots) node new_list_5 = orr(list_req_5) when new_list_5 : node _br_alloc_lists_5_T = bits(list_req_5, 0, 0) node _br_alloc_lists_5_T_1 = bits(list_req_5, 1, 1) node _br_alloc_lists_5_T_2 = bits(list_req_5, 2, 2) node _br_alloc_lists_5_T_3 = mux(_br_alloc_lists_5_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_5_T_4 = mux(_br_alloc_lists_5_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_5_T_5 = mux(_br_alloc_lists_5_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_5_T_6 = or(_br_alloc_lists_5_T_3, _br_alloc_lists_5_T_4) node _br_alloc_lists_5_T_7 = or(_br_alloc_lists_5_T_6, _br_alloc_lists_5_T_5) wire _br_alloc_lists_5_WIRE : UInt<80> connect _br_alloc_lists_5_WIRE, _br_alloc_lists_5_T_7 connect br_alloc_lists[5], _br_alloc_lists_5_WIRE node _list_req_T_24 = eq(io.ren_br_tags[0].bits, UInt<3>(0h6)) node _list_req_T_25 = eq(io.ren_br_tags[1].bits, UInt<3>(0h6)) node _list_req_T_26 = eq(io.ren_br_tags[2].bits, UInt<3>(0h6)) wire _list_req_WIRE_6 : UInt<1>[3] connect _list_req_WIRE_6[0], _list_req_T_24 connect _list_req_WIRE_6[1], _list_req_T_25 connect _list_req_WIRE_6[2], _list_req_T_26 node list_req_hi_6 = cat(_list_req_WIRE_6[2], _list_req_WIRE_6[1]) node _list_req_T_27 = cat(list_req_hi_6, _list_req_WIRE_6[0]) node list_req_6 = and(_list_req_T_27, br_slots) node new_list_6 = orr(list_req_6) when new_list_6 : node _br_alloc_lists_6_T = bits(list_req_6, 0, 0) node _br_alloc_lists_6_T_1 = bits(list_req_6, 1, 1) node _br_alloc_lists_6_T_2 = bits(list_req_6, 2, 2) node _br_alloc_lists_6_T_3 = mux(_br_alloc_lists_6_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_6_T_4 = mux(_br_alloc_lists_6_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_6_T_5 = mux(_br_alloc_lists_6_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_6_T_6 = or(_br_alloc_lists_6_T_3, _br_alloc_lists_6_T_4) node _br_alloc_lists_6_T_7 = or(_br_alloc_lists_6_T_6, _br_alloc_lists_6_T_5) wire _br_alloc_lists_6_WIRE : UInt<80> connect _br_alloc_lists_6_WIRE, _br_alloc_lists_6_T_7 connect br_alloc_lists[6], _br_alloc_lists_6_WIRE node _list_req_T_28 = eq(io.ren_br_tags[0].bits, UInt<3>(0h7)) node _list_req_T_29 = eq(io.ren_br_tags[1].bits, UInt<3>(0h7)) node _list_req_T_30 = eq(io.ren_br_tags[2].bits, UInt<3>(0h7)) wire _list_req_WIRE_7 : UInt<1>[3] connect _list_req_WIRE_7[0], _list_req_T_28 connect _list_req_WIRE_7[1], _list_req_T_29 connect _list_req_WIRE_7[2], _list_req_T_30 node list_req_hi_7 = cat(_list_req_WIRE_7[2], _list_req_WIRE_7[1]) node _list_req_T_31 = cat(list_req_hi_7, _list_req_WIRE_7[0]) node list_req_7 = and(_list_req_T_31, br_slots) node new_list_7 = orr(list_req_7) when new_list_7 : node _br_alloc_lists_7_T = bits(list_req_7, 0, 0) node _br_alloc_lists_7_T_1 = bits(list_req_7, 1, 1) node _br_alloc_lists_7_T_2 = bits(list_req_7, 2, 2) node _br_alloc_lists_7_T_3 = mux(_br_alloc_lists_7_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_7_T_4 = mux(_br_alloc_lists_7_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_7_T_5 = mux(_br_alloc_lists_7_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_7_T_6 = or(_br_alloc_lists_7_T_3, _br_alloc_lists_7_T_4) node _br_alloc_lists_7_T_7 = or(_br_alloc_lists_7_T_6, _br_alloc_lists_7_T_5) wire _br_alloc_lists_7_WIRE : UInt<80> connect _br_alloc_lists_7_WIRE, _br_alloc_lists_7_T_7 connect br_alloc_lists[7], _br_alloc_lists_7_WIRE node _list_req_T_32 = eq(io.ren_br_tags[0].bits, UInt<4>(0h8)) node _list_req_T_33 = eq(io.ren_br_tags[1].bits, UInt<4>(0h8)) node _list_req_T_34 = eq(io.ren_br_tags[2].bits, UInt<4>(0h8)) wire _list_req_WIRE_8 : UInt<1>[3] connect _list_req_WIRE_8[0], _list_req_T_32 connect _list_req_WIRE_8[1], _list_req_T_33 connect _list_req_WIRE_8[2], _list_req_T_34 node list_req_hi_8 = cat(_list_req_WIRE_8[2], _list_req_WIRE_8[1]) node _list_req_T_35 = cat(list_req_hi_8, _list_req_WIRE_8[0]) node list_req_8 = and(_list_req_T_35, br_slots) node new_list_8 = orr(list_req_8) when new_list_8 : node _br_alloc_lists_8_T = bits(list_req_8, 0, 0) node _br_alloc_lists_8_T_1 = bits(list_req_8, 1, 1) node _br_alloc_lists_8_T_2 = bits(list_req_8, 2, 2) node _br_alloc_lists_8_T_3 = mux(_br_alloc_lists_8_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_8_T_4 = mux(_br_alloc_lists_8_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_8_T_5 = mux(_br_alloc_lists_8_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_8_T_6 = or(_br_alloc_lists_8_T_3, _br_alloc_lists_8_T_4) node _br_alloc_lists_8_T_7 = or(_br_alloc_lists_8_T_6, _br_alloc_lists_8_T_5) wire _br_alloc_lists_8_WIRE : UInt<80> connect _br_alloc_lists_8_WIRE, _br_alloc_lists_8_T_7 connect br_alloc_lists[8], _br_alloc_lists_8_WIRE node _list_req_T_36 = eq(io.ren_br_tags[0].bits, UInt<4>(0h9)) node _list_req_T_37 = eq(io.ren_br_tags[1].bits, UInt<4>(0h9)) node _list_req_T_38 = eq(io.ren_br_tags[2].bits, UInt<4>(0h9)) wire _list_req_WIRE_9 : UInt<1>[3] connect _list_req_WIRE_9[0], _list_req_T_36 connect _list_req_WIRE_9[1], _list_req_T_37 connect _list_req_WIRE_9[2], _list_req_T_38 node list_req_hi_9 = cat(_list_req_WIRE_9[2], _list_req_WIRE_9[1]) node _list_req_T_39 = cat(list_req_hi_9, _list_req_WIRE_9[0]) node list_req_9 = and(_list_req_T_39, br_slots) node new_list_9 = orr(list_req_9) when new_list_9 : node _br_alloc_lists_9_T = bits(list_req_9, 0, 0) node _br_alloc_lists_9_T_1 = bits(list_req_9, 1, 1) node _br_alloc_lists_9_T_2 = bits(list_req_9, 2, 2) node _br_alloc_lists_9_T_3 = mux(_br_alloc_lists_9_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_9_T_4 = mux(_br_alloc_lists_9_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_9_T_5 = mux(_br_alloc_lists_9_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_9_T_6 = or(_br_alloc_lists_9_T_3, _br_alloc_lists_9_T_4) node _br_alloc_lists_9_T_7 = or(_br_alloc_lists_9_T_6, _br_alloc_lists_9_T_5) wire _br_alloc_lists_9_WIRE : UInt<80> connect _br_alloc_lists_9_WIRE, _br_alloc_lists_9_T_7 connect br_alloc_lists[9], _br_alloc_lists_9_WIRE node _list_req_T_40 = eq(io.ren_br_tags[0].bits, UInt<4>(0ha)) node _list_req_T_41 = eq(io.ren_br_tags[1].bits, UInt<4>(0ha)) node _list_req_T_42 = eq(io.ren_br_tags[2].bits, UInt<4>(0ha)) wire _list_req_WIRE_10 : UInt<1>[3] connect _list_req_WIRE_10[0], _list_req_T_40 connect _list_req_WIRE_10[1], _list_req_T_41 connect _list_req_WIRE_10[2], _list_req_T_42 node list_req_hi_10 = cat(_list_req_WIRE_10[2], _list_req_WIRE_10[1]) node _list_req_T_43 = cat(list_req_hi_10, _list_req_WIRE_10[0]) node list_req_10 = and(_list_req_T_43, br_slots) node new_list_10 = orr(list_req_10) when new_list_10 : node _br_alloc_lists_10_T = bits(list_req_10, 0, 0) node _br_alloc_lists_10_T_1 = bits(list_req_10, 1, 1) node _br_alloc_lists_10_T_2 = bits(list_req_10, 2, 2) node _br_alloc_lists_10_T_3 = mux(_br_alloc_lists_10_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_10_T_4 = mux(_br_alloc_lists_10_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_10_T_5 = mux(_br_alloc_lists_10_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_10_T_6 = or(_br_alloc_lists_10_T_3, _br_alloc_lists_10_T_4) node _br_alloc_lists_10_T_7 = or(_br_alloc_lists_10_T_6, _br_alloc_lists_10_T_5) wire _br_alloc_lists_10_WIRE : UInt<80> connect _br_alloc_lists_10_WIRE, _br_alloc_lists_10_T_7 connect br_alloc_lists[10], _br_alloc_lists_10_WIRE node _list_req_T_44 = eq(io.ren_br_tags[0].bits, UInt<4>(0hb)) node _list_req_T_45 = eq(io.ren_br_tags[1].bits, UInt<4>(0hb)) node _list_req_T_46 = eq(io.ren_br_tags[2].bits, UInt<4>(0hb)) wire _list_req_WIRE_11 : UInt<1>[3] connect _list_req_WIRE_11[0], _list_req_T_44 connect _list_req_WIRE_11[1], _list_req_T_45 connect _list_req_WIRE_11[2], _list_req_T_46 node list_req_hi_11 = cat(_list_req_WIRE_11[2], _list_req_WIRE_11[1]) node _list_req_T_47 = cat(list_req_hi_11, _list_req_WIRE_11[0]) node list_req_11 = and(_list_req_T_47, br_slots) node new_list_11 = orr(list_req_11) when new_list_11 : node _br_alloc_lists_11_T = bits(list_req_11, 0, 0) node _br_alloc_lists_11_T_1 = bits(list_req_11, 1, 1) node _br_alloc_lists_11_T_2 = bits(list_req_11, 2, 2) node _br_alloc_lists_11_T_3 = mux(_br_alloc_lists_11_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_11_T_4 = mux(_br_alloc_lists_11_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_11_T_5 = mux(_br_alloc_lists_11_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_11_T_6 = or(_br_alloc_lists_11_T_3, _br_alloc_lists_11_T_4) node _br_alloc_lists_11_T_7 = or(_br_alloc_lists_11_T_6, _br_alloc_lists_11_T_5) wire _br_alloc_lists_11_WIRE : UInt<80> connect _br_alloc_lists_11_WIRE, _br_alloc_lists_11_T_7 connect br_alloc_lists[11], _br_alloc_lists_11_WIRE node _spec_alloc_list_T = or(spec_alloc_list, alloc_masks_0) node _spec_alloc_list_T_1 = not(dealloc_mask) node _spec_alloc_list_T_2 = and(_spec_alloc_list_T, _spec_alloc_list_T_1) node _spec_alloc_list_T_3 = not(com_despec) node _spec_alloc_list_T_4 = and(_spec_alloc_list_T_2, _spec_alloc_list_T_3) connect spec_alloc_list, _spec_alloc_list_T_4 node _free_list_T = not(sel_mask) node _free_list_T_1 = and(free_list, _free_list_T) node _free_list_T_2 = or(_free_list_T_1, dealloc_mask) connect free_list, _free_list_T_2 node can_sel = orr(sels[0]) regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0) node r_sel_hi = bits(sels[0], 79, 64) node r_sel_lo = bits(sels[0], 63, 0) node _r_sel_T = orr(r_sel_hi) node _r_sel_T_1 = or(r_sel_hi, r_sel_lo) node r_sel_hi_1 = bits(_r_sel_T_1, 63, 32) node r_sel_lo_1 = bits(_r_sel_T_1, 31, 0) node _r_sel_T_2 = orr(r_sel_hi_1) node _r_sel_T_3 = or(r_sel_hi_1, r_sel_lo_1) node r_sel_hi_2 = bits(_r_sel_T_3, 31, 16) node r_sel_lo_2 = bits(_r_sel_T_3, 15, 0) node _r_sel_T_4 = orr(r_sel_hi_2) node _r_sel_T_5 = or(r_sel_hi_2, r_sel_lo_2) node r_sel_hi_3 = bits(_r_sel_T_5, 15, 8) node r_sel_lo_3 = bits(_r_sel_T_5, 7, 0) node _r_sel_T_6 = orr(r_sel_hi_3) node _r_sel_T_7 = or(r_sel_hi_3, r_sel_lo_3) node r_sel_hi_4 = bits(_r_sel_T_7, 7, 4) node r_sel_lo_4 = bits(_r_sel_T_7, 3, 0) node _r_sel_T_8 = orr(r_sel_hi_4) node _r_sel_T_9 = or(r_sel_hi_4, r_sel_lo_4) node r_sel_hi_5 = bits(_r_sel_T_9, 3, 2) node r_sel_lo_5 = bits(_r_sel_T_9, 1, 0) node _r_sel_T_10 = orr(r_sel_hi_5) node _r_sel_T_11 = or(r_sel_hi_5, r_sel_lo_5) node _r_sel_T_12 = bits(_r_sel_T_11, 1, 1) node _r_sel_T_13 = cat(_r_sel_T_10, _r_sel_T_12) node _r_sel_T_14 = cat(_r_sel_T_8, _r_sel_T_13) node _r_sel_T_15 = cat(_r_sel_T_6, _r_sel_T_14) node _r_sel_T_16 = cat(_r_sel_T_4, _r_sel_T_15) node _r_sel_T_17 = cat(_r_sel_T_2, _r_sel_T_16) node _r_sel_T_18 = cat(_r_sel_T, _r_sel_T_17) reg r_sel : UInt<7>, clock when sel_fire[0] : connect r_sel, _r_sel_T_18 node _r_valid_T = eq(io.reqs[0], UInt<1>(0h0)) node _r_valid_T_1 = and(r_valid, _r_valid_T) node _r_valid_T_2 = or(_r_valid_T_1, can_sel) connect r_valid, _r_valid_T_2 node _sel_fire_0_T = eq(r_valid, UInt<1>(0h0)) node _sel_fire_0_T_1 = or(_sel_fire_0_T, io.reqs[0]) node _sel_fire_0_T_2 = and(_sel_fire_0_T_1, can_sel) connect sel_fire[0], _sel_fire_0_T_2 connect io.alloc_pregs[0].bits, r_sel connect io.alloc_pregs[0].valid, r_valid node can_sel_1 = orr(sels[1]) regreset r_valid_1 : UInt<1>, clock, reset, UInt<1>(0h0) node r_sel_hi_6 = bits(sels[1], 79, 64) node r_sel_lo_6 = bits(sels[1], 63, 0) node _r_sel_T_19 = orr(r_sel_hi_6) node _r_sel_T_20 = or(r_sel_hi_6, r_sel_lo_6) node r_sel_hi_7 = bits(_r_sel_T_20, 63, 32) node r_sel_lo_7 = bits(_r_sel_T_20, 31, 0) node _r_sel_T_21 = orr(r_sel_hi_7) node _r_sel_T_22 = or(r_sel_hi_7, r_sel_lo_7) node r_sel_hi_8 = bits(_r_sel_T_22, 31, 16) node r_sel_lo_8 = bits(_r_sel_T_22, 15, 0) node _r_sel_T_23 = orr(r_sel_hi_8) node _r_sel_T_24 = or(r_sel_hi_8, r_sel_lo_8) node r_sel_hi_9 = bits(_r_sel_T_24, 15, 8) node r_sel_lo_9 = bits(_r_sel_T_24, 7, 0) node _r_sel_T_25 = orr(r_sel_hi_9) node _r_sel_T_26 = or(r_sel_hi_9, r_sel_lo_9) node r_sel_hi_10 = bits(_r_sel_T_26, 7, 4) node r_sel_lo_10 = bits(_r_sel_T_26, 3, 0) node _r_sel_T_27 = orr(r_sel_hi_10) node _r_sel_T_28 = or(r_sel_hi_10, r_sel_lo_10) node r_sel_hi_11 = bits(_r_sel_T_28, 3, 2) node r_sel_lo_11 = bits(_r_sel_T_28, 1, 0) node _r_sel_T_29 = orr(r_sel_hi_11) node _r_sel_T_30 = or(r_sel_hi_11, r_sel_lo_11) node _r_sel_T_31 = bits(_r_sel_T_30, 1, 1) node _r_sel_T_32 = cat(_r_sel_T_29, _r_sel_T_31) node _r_sel_T_33 = cat(_r_sel_T_27, _r_sel_T_32) node _r_sel_T_34 = cat(_r_sel_T_25, _r_sel_T_33) node _r_sel_T_35 = cat(_r_sel_T_23, _r_sel_T_34) node _r_sel_T_36 = cat(_r_sel_T_21, _r_sel_T_35) node _r_sel_T_37 = cat(_r_sel_T_19, _r_sel_T_36) reg r_sel_1 : UInt<7>, clock when sel_fire[1] : connect r_sel_1, _r_sel_T_37 node _r_valid_T_3 = eq(io.reqs[1], UInt<1>(0h0)) node _r_valid_T_4 = and(r_valid_1, _r_valid_T_3) node _r_valid_T_5 = or(_r_valid_T_4, can_sel_1) connect r_valid_1, _r_valid_T_5 node _sel_fire_1_T = eq(r_valid_1, UInt<1>(0h0)) node _sel_fire_1_T_1 = or(_sel_fire_1_T, io.reqs[1]) node _sel_fire_1_T_2 = and(_sel_fire_1_T_1, can_sel_1) connect sel_fire[1], _sel_fire_1_T_2 connect io.alloc_pregs[1].bits, r_sel_1 connect io.alloc_pregs[1].valid, r_valid_1 node _io_debug_freelist_T = dshl(UInt<1>(0h1), io.alloc_pregs[0].bits) node _io_debug_freelist_T_1 = bits(_io_debug_freelist_T, 79, 0) node _io_debug_freelist_T_2 = mux(io.alloc_pregs[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _io_debug_freelist_T_3 = and(_io_debug_freelist_T_1, _io_debug_freelist_T_2) node _io_debug_freelist_T_4 = dshl(UInt<1>(0h1), io.alloc_pregs[1].bits) node _io_debug_freelist_T_5 = bits(_io_debug_freelist_T_4, 79, 0) node _io_debug_freelist_T_6 = mux(io.alloc_pregs[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _io_debug_freelist_T_7 = and(_io_debug_freelist_T_5, _io_debug_freelist_T_6) node _io_debug_freelist_T_8 = or(_io_debug_freelist_T_3, _io_debug_freelist_T_7) node _io_debug_freelist_T_9 = or(free_list, _io_debug_freelist_T_8) connect io.debug_freelist, _io_debug_freelist_T_9 node _T = and(io.debug_freelist, dealloc_mask) node _T_1 = orr(_T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: [freelist] Returning a free physical register.\n at rename-freelist.scala:137 assert (!(io.debug_freelist & dealloc_mask).orR, \"[freelist] Returning a free physical register.\")\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert	module RenameFreeList( // @[rename-freelist.scala:52:7] input clock, // @[rename-freelist.scala:52:7] input reset, // @[rename-freelist.scala:52:7] input io_reqs_0, // @[rename-freelist.scala:29:14] input io_reqs_1, // @[rename-freelist.scala:29:14] output io_alloc_pregs_0_valid, // @[rename-freelist.scala:29:14] output [6:0] io_alloc_pregs_0_bits, // @[rename-freelist.scala:29:14] output io_alloc_pregs_1_valid, // @[rename-freelist.scala:29:14] output [6:0] io_alloc_pregs_1_bits, // @[rename-freelist.scala:29:14] input io_despec_0_valid, // @[rename-freelist.scala:29:14] input [6:0] io_despec_0_bits, // @[rename-freelist.scala:29:14] input io_despec_1_valid, // @[rename-freelist.scala:29:14] input [6:0] io_despec_1_bits, // @[rename-freelist.scala:29:14] input io_dealloc_0_valid, // @[rename-freelist.scala:29:14] input [6:0] io_dealloc_0_bits, // @[rename-freelist.scala:29:14] input io_dealloc_1_valid, // @[rename-freelist.scala:29:14] input [6:0] io_dealloc_1_bits, // @[rename-freelist.scala:29:14] input io_ren_br_tags_1_valid, // @[rename-freelist.scala:29:14] input [3:0] io_ren_br_tags_1_bits, // @[rename-freelist.scala:29:14] input io_ren_br_tags_2_valid, // @[rename-freelist.scala:29:14] input [3:0] io_ren_br_tags_2_bits, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b1_resolve_mask, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[rename-freelist.scala:29:14] input [31:0] io_brupdate_b2_uop_inst, // @[rename-freelist.scala:29:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_rvc, // @[rename-freelist.scala:29:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_0, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_0, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_4, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_5, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_6, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_7, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_8, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_9, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_br_type, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sfb, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_fence, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_fencei, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sfence, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_amo, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_eret, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_rocc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_mov, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_edge_inst, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_taken, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_imm_rename, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_pimm, // @[rename-freelist.scala:29:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_pdst, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs1, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs2, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs3, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_ppred, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs1_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs2_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs3_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_ppred_busy, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_exception, // @[rename-freelist.scala:29:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_mem_signed, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_uses_ldq, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_uses_stq, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_unique, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_flush_on_commit, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_ldst, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_frs3_en, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fcn_dw, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_val, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_bp_debug_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_mispredict, // @[rename-freelist.scala:29:14] input io_brupdate_b2_taken, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_cfi_type, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_pc_sel, // @[rename-freelist.scala:29:14] input [39:0] io_brupdate_b2_jalr_target, // @[rename-freelist.scala:29:14] input [20:0] io_brupdate_b2_target_offset, // @[rename-freelist.scala:29:14] input io_rollback, // @[rename-freelist.scala:29:14] output [79:0] io_debug_freelist // @[rename-freelist.scala:29:14] ); wire io_reqs_0_0 = io_reqs_0; // @[rename-freelist.scala:52:7] wire io_reqs_1_0 = io_reqs_1; // @[rename-freelist.scala:52:7] wire io_despec_0_valid_0 = io_despec_0_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_despec_0_bits_0 = io_despec_0_bits; // @[rename-freelist.scala:52:7] wire io_despec_1_valid_0 = io_despec_1_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_despec_1_bits_0 = io_despec_1_bits; // @[rename-freelist.scala:52:7] wire io_dealloc_0_valid_0 = io_dealloc_0_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_dealloc_0_bits_0 = io_dealloc_0_bits; // @[rename-freelist.scala:52:7] wire io_dealloc_1_valid_0 = io_dealloc_1_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_dealloc_1_bits_0 = io_dealloc_1_bits; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_1_valid_0 = io_ren_br_tags_1_valid; // @[rename-freelist.scala:52:7] wire [3:0] io_ren_br_tags_1_bits_0 = io_ren_br_tags_1_bits; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_2_valid_0 = io_ren_br_tags_2_valid; // @[rename-freelist.scala:52:7] wire [3:0] io_ren_br_tags_2_bits_0 = io_ren_br_tags_2_bits; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-freelist.scala:52:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-freelist.scala:52:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-freelist.scala:52:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[rename-freelist.scala:52:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-freelist.scala:52:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-freelist.scala:52:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-freelist.scala:52:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-freelist.scala:52:7] wire io_rollback_0 = io_rollback; // @[rename-freelist.scala:52:7] wire [79:0] io_initial_allocation = 80'hFFFFFFFFFFFF00000000; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_0_valid = 1'h0; // @[rename-freelist.scala:52:7] wire _br_slots_WIRE_0 = 1'h0; // @[rename-freelist.scala:96:27] wire _list_req_T_4 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_1_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_8 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_2_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_12 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_3_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_16 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_4_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_20 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_5_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_24 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_6_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_28 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_7_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_32 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_8_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_36 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_9_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_40 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_10_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_44 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_11_0 = 1'h0; // @[rename-freelist.scala:99:29] wire [3:0] io_ren_br_tags_0_bits = 4'h0; // @[rename-freelist.scala:52:7] wire [79:0] _br_alloc_lists_0_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_T_5 = 80'h0; // @[Mux.scala:30:73] wire _list_req_T = 1'h1; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_0 = 1'h1; // @[rename-freelist.scala:99:29] wire _br_slots_WIRE_1 = io_ren_br_tags_1_valid_0; // @[rename-freelist.scala:52:7, :96:27] wire _br_slots_WIRE_2 = io_ren_br_tags_2_valid_0; // @[rename-freelist.scala:52:7, :96:27] wire [79:0] _io_debug_freelist_T_9; // @[rename-freelist.scala:134:34] wire io_alloc_pregs_0_valid_0; // @[rename-freelist.scala:52:7] wire [6:0] io_alloc_pregs_0_bits_0; // @[rename-freelist.scala:52:7] wire io_alloc_pregs_1_valid_0; // @[rename-freelist.scala:52:7] wire [6:0] io_alloc_pregs_1_bits_0; // @[rename-freelist.scala:52:7] wire [79:0] io_debug_freelist_0; // @[rename-freelist.scala:52:7] reg [79:0] free_list; // @[rename-freelist.scala:62:26] reg [79:0] spec_alloc_list; // @[rename-freelist.scala:63:32] reg [79:0] br_alloc_lists_0; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_1; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_2; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_3; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_4; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_5; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_6; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_7; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_8; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_9; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_10; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_11; // @[rename-freelist.scala:64:27] wire [79:0] _sels_sels_0_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_sels_1_T_159; // @[Mux.scala:50:70] wire [79:0] sels_0; // @[util.scala:415:20] wire [79:0] sels_1; // @[util.scala:415:20] wire _sels_sels_0_T = free_list[0]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_1 = free_list[1]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_2 = free_list[2]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_3 = free_list[3]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_4 = free_list[4]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_5 = free_list[5]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_6 = free_list[6]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_7 = free_list[7]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_8 = free_list[8]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_9 = free_list[9]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_10 = free_list[10]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_11 = free_list[11]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_12 = free_list[12]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_13 = free_list[13]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_14 = free_list[14]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_15 = free_list[15]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_16 = free_list[16]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_17 = free_list[17]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_18 = free_list[18]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_19 = free_list[19]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_20 = free_list[20]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_21 = free_list[21]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_22 = free_list[22]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_23 = free_list[23]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_24 = free_list[24]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_25 = free_list[25]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_26 = free_list[26]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_27 = free_list[27]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_28 = free_list[28]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_29 = free_list[29]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_30 = free_list[30]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_31 = free_list[31]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_32 = free_list[32]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_33 = free_list[33]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_34 = free_list[34]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_35 = free_list[35]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_36 = free_list[36]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_37 = free_list[37]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_38 = free_list[38]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_39 = free_list[39]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_40 = free_list[40]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_41 = free_list[41]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_42 = free_list[42]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_43 = free_list[43]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_44 = free_list[44]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_45 = free_list[45]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_46 = free_list[46]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_47 = free_list[47]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_48 = free_list[48]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_49 = free_list[49]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_50 = free_list[50]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_51 = free_list[51]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_52 = free_list[52]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_53 = free_list[53]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_54 = free_list[54]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_55 = free_list[55]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_56 = free_list[56]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_57 = free_list[57]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_58 = free_list[58]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_59 = free_list[59]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_60 = free_list[60]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_61 = free_list[61]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_62 = free_list[62]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_63 = free_list[63]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_64 = free_list[64]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_65 = free_list[65]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_66 = free_list[66]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_67 = free_list[67]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_68 = free_list[68]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_69 = free_list[69]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_70 = free_list[70]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_71 = free_list[71]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_72 = free_list[72]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_73 = free_list[73]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_74 = free_list[74]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_75 = free_list[75]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_76 = free_list[76]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_77 = free_list[77]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_78 = free_list[78]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_79 = free_list[79]; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_80 = {_sels_sels_0_T_79, 79'h0}; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_81 = _sels_sels_0_T_78 ? 80'h40000000000000000000 : _sels_sels_0_T_80; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_82 = _sels_sels_0_T_77 ? 80'h20000000000000000000 : _sels_sels_0_T_81; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_83 = _sels_sels_0_T_76 ? 80'h10000000000000000000 : _sels_sels_0_T_82; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_84 = _sels_sels_0_T_75 ? 80'h8000000000000000000 : _sels_sels_0_T_83; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_85 = _sels_sels_0_T_74 ? 80'h4000000000000000000 : _sels_sels_0_T_84; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_86 = _sels_sels_0_T_73 ? 80'h2000000000000000000 : _sels_sels_0_T_85; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_87 = _sels_sels_0_T_72 ? 80'h1000000000000000000 : _sels_sels_0_T_86; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_88 = _sels_sels_0_T_71 ? 80'h800000000000000000 : _sels_sels_0_T_87; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_89 = _sels_sels_0_T_70 ? 80'h400000000000000000 : _sels_sels_0_T_88; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_90 = _sels_sels_0_T_69 ? 80'h200000000000000000 : _sels_sels_0_T_89; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_91 = _sels_sels_0_T_68 ? 80'h100000000000000000 : _sels_sels_0_T_90; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_92 = _sels_sels_0_T_67 ? 80'h80000000000000000 : _sels_sels_0_T_91; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_93 = _sels_sels_0_T_66 ? 80'h40000000000000000 : _sels_sels_0_T_92; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_94 = _sels_sels_0_T_65 ? 80'h20000000000000000 : _sels_sels_0_T_93; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_95 = _sels_sels_0_T_64 ? 80'h10000000000000000 : _sels_sels_0_T_94; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_96 = _sels_sels_0_T_63 ? 80'h8000000000000000 : _sels_sels_0_T_95; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_97 = _sels_sels_0_T_62 ? 80'h4000000000000000 : _sels_sels_0_T_96; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_98 = _sels_sels_0_T_61 ? 80'h2000000000000000 : _sels_sels_0_T_97; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_99 = _sels_sels_0_T_60 ? 80'h1000000000000000 : _sels_sels_0_T_98; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_100 = _sels_sels_0_T_59 ? 80'h800000000000000 : _sels_sels_0_T_99; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_101 = _sels_sels_0_T_58 ? 80'h400000000000000 : _sels_sels_0_T_100; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_102 = _sels_sels_0_T_57 ? 80'h200000000000000 : _sels_sels_0_T_101; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_103 = _sels_sels_0_T_56 ? 80'h100000000000000 : _sels_sels_0_T_102; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_104 = _sels_sels_0_T_55 ? 80'h80000000000000 : _sels_sels_0_T_103; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_105 = _sels_sels_0_T_54 ? 80'h40000000000000 : _sels_sels_0_T_104; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_106 = _sels_sels_0_T_53 ? 80'h20000000000000 : _sels_sels_0_T_105; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_107 = _sels_sels_0_T_52 ? 80'h10000000000000 : _sels_sels_0_T_106; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_108 = _sels_sels_0_T_51 ? 80'h8000000000000 : _sels_sels_0_T_107; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_109 = _sels_sels_0_T_50 ? 80'h4000000000000 : _sels_sels_0_T_108; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_110 = _sels_sels_0_T_49 ? 80'h2000000000000 : _sels_sels_0_T_109; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_111 = _sels_sels_0_T_48 ? 80'h1000000000000 : _sels_sels_0_T_110; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_112 = _sels_sels_0_T_47 ? 80'h800000000000 : _sels_sels_0_T_111; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_113 = _sels_sels_0_T_46 ? 80'h400000000000 : _sels_sels_0_T_112; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_114 = _sels_sels_0_T_45 ? 80'h200000000000 : _sels_sels_0_T_113; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_115 = _sels_sels_0_T_44 ? 80'h100000000000 : _sels_sels_0_T_114; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_116 = _sels_sels_0_T_43 ? 80'h80000000000 : _sels_sels_0_T_115; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_117 = _sels_sels_0_T_42 ? 80'h40000000000 : _sels_sels_0_T_116; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_118 = _sels_sels_0_T_41 ? 80'h20000000000 : _sels_sels_0_T_117; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_119 = _sels_sels_0_T_40 ? 80'h10000000000 : _sels_sels_0_T_118; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_120 = _sels_sels_0_T_39 ? 80'h8000000000 : _sels_sels_0_T_119; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_121 = _sels_sels_0_T_38 ? 80'h4000000000 : _sels_sels_0_T_120; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_122 = _sels_sels_0_T_37 ? 80'h2000000000 : _sels_sels_0_T_121; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_123 = _sels_sels_0_T_36 ? 80'h1000000000 : _sels_sels_0_T_122; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_124 = _sels_sels_0_T_35 ? 80'h800000000 : _sels_sels_0_T_123; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_125 = _sels_sels_0_T_34 ? 80'h400000000 : _sels_sels_0_T_124; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_126 = _sels_sels_0_T_33 ? 80'h200000000 : _sels_sels_0_T_125; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_127 = _sels_sels_0_T_32 ? 80'h100000000 : _sels_sels_0_T_126; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_128 = _sels_sels_0_T_31 ? 80'h80000000 : _sels_sels_0_T_127; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_129 = _sels_sels_0_T_30 ? 80'h40000000 : _sels_sels_0_T_128; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_130 = _sels_sels_0_T_29 ? 80'h20000000 : _sels_sels_0_T_129; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_131 = _sels_sels_0_T_28 ? 80'h10000000 : _sels_sels_0_T_130; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_132 = _sels_sels_0_T_27 ? 80'h8000000 : _sels_sels_0_T_131; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_133 = _sels_sels_0_T_26 ? 80'h4000000 : _sels_sels_0_T_132; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_134 = _sels_sels_0_T_25 ? 80'h2000000 : _sels_sels_0_T_133; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_135 = _sels_sels_0_T_24 ? 80'h1000000 : _sels_sels_0_T_134; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_136 = _sels_sels_0_T_23 ? 80'h800000 : _sels_sels_0_T_135; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_137 = _sels_sels_0_T_22 ? 80'h400000 : _sels_sels_0_T_136; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_138 = _sels_sels_0_T_21 ? 80'h200000 : _sels_sels_0_T_137; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_139 = _sels_sels_0_T_20 ? 80'h100000 : _sels_sels_0_T_138; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_140 = _sels_sels_0_T_19 ? 80'h80000 : _sels_sels_0_T_139; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_141 = _sels_sels_0_T_18 ? 80'h40000 : _sels_sels_0_T_140; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_142 = _sels_sels_0_T_17 ? 80'h20000 : _sels_sels_0_T_141; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_143 = _sels_sels_0_T_16 ? 80'h10000 : _sels_sels_0_T_142; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_144 = _sels_sels_0_T_15 ? 80'h8000 : _sels_sels_0_T_143; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_145 = _sels_sels_0_T_14 ? 80'h4000 : _sels_sels_0_T_144; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_146 = _sels_sels_0_T_13 ? 80'h2000 : _sels_sels_0_T_145; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_147 = _sels_sels_0_T_12 ? 80'h1000 : _sels_sels_0_T_146; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_148 = _sels_sels_0_T_11 ? 80'h800 : _sels_sels_0_T_147; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_149 = _sels_sels_0_T_10 ? 80'h400 : _sels_sels_0_T_148; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_150 = _sels_sels_0_T_9 ? 80'h200 : _sels_sels_0_T_149; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_151 = _sels_sels_0_T_8 ? 80'h100 : _sels_sels_0_T_150; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_152 = _sels_sels_0_T_7 ? 80'h80 : _sels_sels_0_T_151; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_153 = _sels_sels_0_T_6 ? 80'h40 : _sels_sels_0_T_152; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_154 = _sels_sels_0_T_5 ? 80'h20 : _sels_sels_0_T_153; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_155 = _sels_sels_0_T_4 ? 80'h10 : _sels_sels_0_T_154; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_156 = _sels_sels_0_T_3 ? 80'h8 : _sels_sels_0_T_155; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_157 = _sels_sels_0_T_2 ? 80'h4 : _sels_sels_0_T_156; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_158 = _sels_sels_0_T_1 ? 80'h2 : _sels_sels_0_T_157; // @[OneHot.scala:85:71] assign _sels_sels_0_T_159 = _sels_sels_0_T ? 80'h1 : _sels_sels_0_T_158; // @[OneHot.scala:85:71] assign sels_0 = _sels_sels_0_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_T = ~sels_0; // @[util.scala:415:20, :420:21] wire [79:0] _sels_T_1 = free_list & _sels_T; // @[util.scala:420:{19,21}] wire _sels_sels_1_T = _sels_T_1[0]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_1 = _sels_T_1[1]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_2 = _sels_T_1[2]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_3 = _sels_T_1[3]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_4 = _sels_T_1[4]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_5 = _sels_T_1[5]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_6 = _sels_T_1[6]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_7 = _sels_T_1[7]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_8 = _sels_T_1[8]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_9 = _sels_T_1[9]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_10 = _sels_T_1[10]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_11 = _sels_T_1[11]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_12 = _sels_T_1[12]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_13 = _sels_T_1[13]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_14 = _sels_T_1[14]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_15 = _sels_T_1[15]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_16 = _sels_T_1[16]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_17 = _sels_T_1[17]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_18 = _sels_T_1[18]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_19 = _sels_T_1[19]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_20 = _sels_T_1[20]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_21 = _sels_T_1[21]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_22 = _sels_T_1[22]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_23 = _sels_T_1[23]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_24 = _sels_T_1[24]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_25 = _sels_T_1[25]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_26 = _sels_T_1[26]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_27 = _sels_T_1[27]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_28 = _sels_T_1[28]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_29 = _sels_T_1[29]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_30 = _sels_T_1[30]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_31 = _sels_T_1[31]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_32 = _sels_T_1[32]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_33 = _sels_T_1[33]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_34 = _sels_T_1[34]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_35 = _sels_T_1[35]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_36 = _sels_T_1[36]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_37 = _sels_T_1[37]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_38 = _sels_T_1[38]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_39 = _sels_T_1[39]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_40 = _sels_T_1[40]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_41 = _sels_T_1[41]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_42 = _sels_T_1[42]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_43 = _sels_T_1[43]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_44 = _sels_T_1[44]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_45 = _sels_T_1[45]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_46 = _sels_T_1[46]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_47 = _sels_T_1[47]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_48 = _sels_T_1[48]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_49 = _sels_T_1[49]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_50 = _sels_T_1[50]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_51 = _sels_T_1[51]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_52 = _sels_T_1[52]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_53 = _sels_T_1[53]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_54 = _sels_T_1[54]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_55 = _sels_T_1[55]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_56 = _sels_T_1[56]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_57 = _sels_T_1[57]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_58 = _sels_T_1[58]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_59 = _sels_T_1[59]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_60 = _sels_T_1[60]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_61 = _sels_T_1[61]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_62 = _sels_T_1[62]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_63 = _sels_T_1[63]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_64 = _sels_T_1[64]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_65 = _sels_T_1[65]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_66 = _sels_T_1[66]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_67 = _sels_T_1[67]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_68 = _sels_T_1[68]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_69 = _sels_T_1[69]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_70 = _sels_T_1[70]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_71 = _sels_T_1[71]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_72 = _sels_T_1[72]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_73 = _sels_T_1[73]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_74 = _sels_T_1[74]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_75 = _sels_T_1[75]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_76 = _sels_T_1[76]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_77 = _sels_T_1[77]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_78 = _sels_T_1[78]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_79 = _sels_T_1[79]; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_80 = {_sels_sels_1_T_79, 79'h0}; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_81 = _sels_sels_1_T_78 ? 80'h40000000000000000000 : _sels_sels_1_T_80; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_82 = _sels_sels_1_T_77 ? 80'h20000000000000000000 : _sels_sels_1_T_81; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_83 = _sels_sels_1_T_76 ? 80'h10000000000000000000 : _sels_sels_1_T_82; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_84 = _sels_sels_1_T_75 ? 80'h8000000000000000000 : _sels_sels_1_T_83; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_85 = _sels_sels_1_T_74 ? 80'h4000000000000000000 : _sels_sels_1_T_84; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_86 = _sels_sels_1_T_73 ? 80'h2000000000000000000 : _sels_sels_1_T_85; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_87 = _sels_sels_1_T_72 ? 80'h1000000000000000000 : _sels_sels_1_T_86; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_88 = _sels_sels_1_T_71 ? 80'h800000000000000000 : _sels_sels_1_T_87; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_89 = _sels_sels_1_T_70 ? 80'h400000000000000000 : _sels_sels_1_T_88; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_90 = _sels_sels_1_T_69 ? 80'h200000000000000000 : _sels_sels_1_T_89; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_91 = _sels_sels_1_T_68 ? 80'h100000000000000000 : _sels_sels_1_T_90; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_92 = _sels_sels_1_T_67 ? 80'h80000000000000000 : _sels_sels_1_T_91; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_93 = _sels_sels_1_T_66 ? 80'h40000000000000000 : _sels_sels_1_T_92; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_94 = _sels_sels_1_T_65 ? 80'h20000000000000000 : _sels_sels_1_T_93; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_95 = _sels_sels_1_T_64 ? 80'h10000000000000000 : _sels_sels_1_T_94; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_96 = _sels_sels_1_T_63 ? 80'h8000000000000000 : _sels_sels_1_T_95; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_97 = _sels_sels_1_T_62 ? 80'h4000000000000000 : _sels_sels_1_T_96; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_98 = _sels_sels_1_T_61 ? 80'h2000000000000000 : _sels_sels_1_T_97; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_99 = _sels_sels_1_T_60 ? 80'h1000000000000000 : _sels_sels_1_T_98; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_100 = _sels_sels_1_T_59 ? 80'h800000000000000 : _sels_sels_1_T_99; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_101 = _sels_sels_1_T_58 ? 80'h400000000000000 : _sels_sels_1_T_100; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_102 = _sels_sels_1_T_57 ? 80'h200000000000000 : _sels_sels_1_T_101; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_103 = _sels_sels_1_T_56 ? 80'h100000000000000 : _sels_sels_1_T_102; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_104 = _sels_sels_1_T_55 ? 80'h80000000000000 : _sels_sels_1_T_103; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_105 = _sels_sels_1_T_54 ? 80'h40000000000000 : _sels_sels_1_T_104; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_106 = _sels_sels_1_T_53 ? 80'h20000000000000 : _sels_sels_1_T_105; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_107 = _sels_sels_1_T_52 ? 80'h10000000000000 : _sels_sels_1_T_106; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_108 = _sels_sels_1_T_51 ? 80'h8000000000000 : _sels_sels_1_T_107; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_109 = _sels_sels_1_T_50 ? 80'h4000000000000 : _sels_sels_1_T_108; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_110 = _sels_sels_1_T_49 ? 80'h2000000000000 : _sels_sels_1_T_109; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_111 = _sels_sels_1_T_48 ? 80'h1000000000000 : _sels_sels_1_T_110; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_112 = _sels_sels_1_T_47 ? 80'h800000000000 : _sels_sels_1_T_111; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_113 = _sels_sels_1_T_46 ? 80'h400000000000 : _sels_sels_1_T_112; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_114 = _sels_sels_1_T_45 ? 80'h200000000000 : _sels_sels_1_T_113; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_115 = _sels_sels_1_T_44 ? 80'h100000000000 : _sels_sels_1_T_114; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_116 = _sels_sels_1_T_43 ? 80'h80000000000 : _sels_sels_1_T_115; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_117 = _sels_sels_1_T_42 ? 80'h40000000000 : _sels_sels_1_T_116; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_118 = _sels_sels_1_T_41 ? 80'h20000000000 : _sels_sels_1_T_117; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_119 = _sels_sels_1_T_40 ? 80'h10000000000 : _sels_sels_1_T_118; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_120 = _sels_sels_1_T_39 ? 80'h8000000000 : _sels_sels_1_T_119; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_121 = _sels_sels_1_T_38 ? 80'h4000000000 : _sels_sels_1_T_120; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_122 = _sels_sels_1_T_37 ? 80'h2000000000 : _sels_sels_1_T_121; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_123 = _sels_sels_1_T_36 ? 80'h1000000000 : _sels_sels_1_T_122; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_124 = _sels_sels_1_T_35 ? 80'h800000000 : _sels_sels_1_T_123; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_125 = _sels_sels_1_T_34 ? 80'h400000000 : _sels_sels_1_T_124; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_126 = _sels_sels_1_T_33 ? 80'h200000000 : _sels_sels_1_T_125; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_127 = _sels_sels_1_T_32 ? 80'h100000000 : _sels_sels_1_T_126; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_128 = _sels_sels_1_T_31 ? 80'h80000000 : _sels_sels_1_T_127; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_129 = _sels_sels_1_T_30 ? 80'h40000000 : _sels_sels_1_T_128; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_130 = _sels_sels_1_T_29 ? 80'h20000000 : _sels_sels_1_T_129; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_131 = _sels_sels_1_T_28 ? 80'h10000000 : _sels_sels_1_T_130; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_132 = _sels_sels_1_T_27 ? 80'h8000000 : _sels_sels_1_T_131; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_133 = _sels_sels_1_T_26 ? 80'h4000000 : _sels_sels_1_T_132; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_134 = _sels_sels_1_T_25 ? 80'h2000000 : _sels_sels_1_T_133; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_135 = _sels_sels_1_T_24 ? 80'h1000000 : _sels_sels_1_T_134; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_136 = _sels_sels_1_T_23 ? 80'h800000 : _sels_sels_1_T_135; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_137 = _sels_sels_1_T_22 ? 80'h400000 : _sels_sels_1_T_136; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_138 = _sels_sels_1_T_21 ? 80'h200000 : _sels_sels_1_T_137; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_139 = _sels_sels_1_T_20 ? 80'h100000 : _sels_sels_1_T_138; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_140 = _sels_sels_1_T_19 ? 80'h80000 : _sels_sels_1_T_139; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_141 = _sels_sels_1_T_18 ? 80'h40000 : _sels_sels_1_T_140; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_142 = _sels_sels_1_T_17 ? 80'h20000 : _sels_sels_1_T_141; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_143 = _sels_sels_1_T_16 ? 80'h10000 : _sels_sels_1_T_142; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_144 = _sels_sels_1_T_15 ? 80'h8000 : _sels_sels_1_T_143; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_145 = _sels_sels_1_T_14 ? 80'h4000 : _sels_sels_1_T_144; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_146 = _sels_sels_1_T_13 ? 80'h2000 : _sels_sels_1_T_145; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_147 = _sels_sels_1_T_12 ? 80'h1000 : _sels_sels_1_T_146; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_148 = _sels_sels_1_T_11 ? 80'h800 : _sels_sels_1_T_147; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_149 = _sels_sels_1_T_10 ? 80'h400 : _sels_sels_1_T_148; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_150 = _sels_sels_1_T_9 ? 80'h200 : _sels_sels_1_T_149; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_151 = _sels_sels_1_T_8 ? 80'h100 : _sels_sels_1_T_150; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_152 = _sels_sels_1_T_7 ? 80'h80 : _sels_sels_1_T_151; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_153 = _sels_sels_1_T_6 ? 80'h40 : _sels_sels_1_T_152; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_154 = _sels_sels_1_T_5 ? 80'h20 : _sels_sels_1_T_153; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_155 = _sels_sels_1_T_4 ? 80'h10 : _sels_sels_1_T_154; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_156 = _sels_sels_1_T_3 ? 80'h8 : _sels_sels_1_T_155; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_157 = _sels_sels_1_T_2 ? 80'h4 : _sels_sels_1_T_156; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_158 = _sels_sels_1_T_1 ? 80'h2 : _sels_sels_1_T_157; // @[OneHot.scala:85:71] assign _sels_sels_1_T_159 = _sels_sels_1_T ? 80'h1 : _sels_sels_1_T_158; // @[OneHot.scala:85:71] assign sels_1 = _sels_sels_1_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_T_2 = ~sels_1; // @[util.scala:415:20, :420:21] wire [79:0] _sels_T_3 = _sels_T_1 & _sels_T_2; // @[util.scala:420:{19,21}] wire _sel_fire_0_T_2; // @[rename-freelist.scala:128:45] wire _sel_fire_1_T_2; // @[rename-freelist.scala:128:45] wire sel_fire_0; // @[rename-freelist.scala:68:23] wire sel_fire_1; // @[rename-freelist.scala:68:23] wire [127:0] _GEN = 128'h1 << io_alloc_pregs_0_bits_0; // @[OneHot.scala:58:35] wire [127:0] _allocs_T; // @[OneHot.scala:58:35] assign _allocs_T = _GEN; // @[OneHot.scala:58:35] wire [127:0] _io_debug_freelist_T; // @[OneHot.scala:58:35] assign _io_debug_freelist_T = _GEN; // @[OneHot.scala:58:35] wire [79:0] allocs_0 = _allocs_T[79:0]; // @[OneHot.scala:58:35] wire [127:0] _GEN_0 = 128'h1 << io_alloc_pregs_1_bits_0; // @[OneHot.scala:58:35] wire [127:0] _allocs_T_1; // @[OneHot.scala:58:35] assign _allocs_T_1 = _GEN_0; // @[OneHot.scala:58:35] wire [127:0] _io_debug_freelist_T_4; // @[OneHot.scala:58:35] assign _io_debug_freelist_T_4 = _GEN_0; // @[OneHot.scala:58:35] wire [79:0] allocs_1 = _allocs_T_1[79:0]; // @[OneHot.scala:58:35] wire [79:0] _alloc_masks_T = {80{io_reqs_1_0}}; // @[rename-freelist.scala:52:7, :72:94] wire [79:0] _alloc_masks_T_1 = allocs_1 & _alloc_masks_T; // @[rename-freelist.scala:71:57, :72:{88,94}] wire [79:0] alloc_masks_1 = _alloc_masks_T_1; // @[rename-freelist.scala:72:{84,88}] wire [79:0] _alloc_masks_T_2 = {80{io_reqs_0_0}}; // @[rename-freelist.scala:52:7, :72:94] wire [79:0] _alloc_masks_T_3 = allocs_0 & _alloc_masks_T_2; // @[rename-freelist.scala:71:57, :72:{88,94}] wire [79:0] alloc_masks_0 = alloc_masks_1 \| _alloc_masks_T_3; // @[rename-freelist.scala:72:{84,88}] wire [79:0] _sel_mask_T = {80{sel_fire_0}}; // @[rename-freelist.scala:68:23, :75:66] wire [79:0] _sel_mask_T_1 = sels_0 & _sel_mask_T; // @[util.scala:415:20] wire [79:0] _sel_mask_T_2 = {80{sel_fire_1}}; // @[rename-freelist.scala:68:23, :75:66] wire [79:0] _sel_mask_T_3 = sels_1 & _sel_mask_T_2; // @[util.scala:415:20] wire [79:0] sel_mask = _sel_mask_T_1 \| _sel_mask_T_3; // @[rename-freelist.scala:75:{60,82}] wire [79:0] _br_deallocs_T = {80{io_brupdate_b2_mispredict_0}}; // @[rename-freelist.scala:52:7, :77:69] wire [15:0][79:0] _GEN_1 = {{br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_11}, {br_alloc_lists_10}, {br_alloc_lists_9}, {br_alloc_lists_8}, {br_alloc_lists_7}, {br_alloc_lists_6}, {br_alloc_lists_5}, {br_alloc_lists_4}, {br_alloc_lists_3}, {br_alloc_lists_2}, {br_alloc_lists_1}, {br_alloc_lists_0}}; // @[rename-freelist.scala:64:27, :77:63] wire [79:0] br_deallocs = _GEN_1[io_brupdate_b2_uop_br_tag_0] & _br_deallocs_T; // @[rename-freelist.scala:52:7, :77:{63,69}] reg com_deallocs_REG_0_valid; // @[rename-freelist.scala:78:29] reg [6:0] com_deallocs_REG_0_bits; // @[rename-freelist.scala:78:29] reg com_deallocs_REG_1_valid; // @[rename-freelist.scala:78:29] reg [6:0] com_deallocs_REG_1_bits; // @[rename-freelist.scala:78:29] wire [127:0] _com_deallocs_T = 128'h1 << com_deallocs_REG_0_bits; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_1 = _com_deallocs_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_2 = {80{com_deallocs_REG_0_valid}}; // @[rename-freelist.scala:78:{29,88}] wire [79:0] _com_deallocs_T_3 = _com_deallocs_T_1 & _com_deallocs_T_2; // @[rename-freelist.scala:78:{67,82,88}] wire [127:0] _com_deallocs_T_4 = 128'h1 << com_deallocs_REG_1_bits; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_5 = _com_deallocs_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_6 = {80{com_deallocs_REG_1_valid}}; // @[rename-freelist.scala:78:{29,88}] wire [79:0] _com_deallocs_T_7 = _com_deallocs_T_5 & _com_deallocs_T_6; // @[rename-freelist.scala:78:{67,82,88}] wire [79:0] com_deallocs = _com_deallocs_T_3 \| _com_deallocs_T_7; // @[rename-freelist.scala:78:{82,109}] wire [79:0] _rollback_deallocs_T = {80{io_rollback_0}}; // @[rename-freelist.scala:52:7, :79:49] wire [79:0] rollback_deallocs = spec_alloc_list & _rollback_deallocs_T; // @[rename-freelist.scala:63:32, :79:{43,49}] wire [79:0] _dealloc_mask_T = com_deallocs \| br_deallocs; // @[rename-freelist.scala:77:63, :78:109, :80:35] wire [79:0] dealloc_mask = _dealloc_mask_T \| rollback_deallocs; // @[rename-freelist.scala:79:43, :80:{35,49}] wire [127:0] _com_despec_T = 128'h1 << io_despec_0_bits_0; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_1 = _com_despec_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_2 = {80{io_despec_0_valid_0}}; // @[rename-freelist.scala:52:7, :82:76] wire [79:0] _com_despec_T_3 = _com_despec_T_1 & _com_despec_T_2; // @[rename-freelist.scala:82:{55,70,76}] wire [127:0] _com_despec_T_4 = 128'h1 << io_despec_1_bits_0; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_5 = _com_despec_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_6 = {80{io_despec_1_valid_0}}; // @[rename-freelist.scala:52:7, :82:76] wire [79:0] _com_despec_T_7 = _com_despec_T_5 & _com_despec_T_6; // @[rename-freelist.scala:82:{55,70,76}] wire [79:0] com_despec = _com_despec_T_3 \| _com_despec_T_7; // @[rename-freelist.scala:82:{70,97}] wire [79:0] _updated_br_alloc_list_T = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_1 = br_alloc_lists_0 & _updated_br_alloc_list_T; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list = _updated_br_alloc_list_T_1 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_2 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_3 = br_alloc_lists_1 & _updated_br_alloc_list_T_2; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_1 = _updated_br_alloc_list_T_3 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_4 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_5 = br_alloc_lists_2 & _updated_br_alloc_list_T_4; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_2 = _updated_br_alloc_list_T_5 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_6 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_7 = br_alloc_lists_3 & _updated_br_alloc_list_T_6; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_3 = _updated_br_alloc_list_T_7 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_8 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_9 = br_alloc_lists_4 & _updated_br_alloc_list_T_8; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_4 = _updated_br_alloc_list_T_9 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_10 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_11 = br_alloc_lists_5 & _updated_br_alloc_list_T_10; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_5 = _updated_br_alloc_list_T_11 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_12 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_13 = br_alloc_lists_6 & _updated_br_alloc_list_T_12; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_6 = _updated_br_alloc_list_T_13 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_14 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_15 = br_alloc_lists_7 & _updated_br_alloc_list_T_14; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_7 = _updated_br_alloc_list_T_15 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_16 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_17 = br_alloc_lists_8 & _updated_br_alloc_list_T_16; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_8 = _updated_br_alloc_list_T_17 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_18 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_19 = br_alloc_lists_9 & _updated_br_alloc_list_T_18; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_9 = _updated_br_alloc_list_T_19 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_20 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_21 = br_alloc_lists_10 & _updated_br_alloc_list_T_20; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_10 = _updated_br_alloc_list_T_21 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_22 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_23 = br_alloc_lists_11 & _updated_br_alloc_list_T_22; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_11 = _updated_br_alloc_list_T_23 \| alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [1:0] br_slots_hi = {_br_slots_WIRE_2, _br_slots_WIRE_1}; // @[rename-freelist.scala:96:{27,66}] wire [2:0] br_slots = {br_slots_hi, 1'h0}; // @[rename-freelist.scala:96:66] wire _list_req_T_1 = io_ren_br_tags_1_bits_0 == 4'h0; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1 = _list_req_T_1; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_2 = io_ren_br_tags_2_bits_0 == 4'h0; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2 = _list_req_T_2; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi = {_list_req_WIRE_2, _list_req_WIRE_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_3 = {list_req_hi, 1'h1}; // @[rename-freelist.scala:99:75] wire [2:0] list_req = _list_req_T_3 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list = \|list_req; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_0_T = list_req[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_0_T_1 = list_req[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_0_T_2 = list_req[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_0_T_3 = _br_alloc_lists_0_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_0_T_4 = _br_alloc_lists_0_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_0_T_6 = _br_alloc_lists_0_T_3 \| _br_alloc_lists_0_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_0_T_7 = _br_alloc_lists_0_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_0_WIRE = _br_alloc_lists_0_T_7; // @[Mux.scala:30:73] wire _list_req_T_5 = io_ren_br_tags_1_bits_0 == 4'h1; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1_1 = _list_req_T_5; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_6 = io_ren_br_tags_2_bits_0 == 4'h1; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1_2 = _list_req_T_6; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_1 = {_list_req_WIRE_1_2, _list_req_WIRE_1_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_7 = {list_req_hi_1, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_1 = _list_req_T_7 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_1 = \|list_req_1; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_1_T = list_req_1[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_1_T_1 = list_req_1[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_1_T_2 = list_req_1[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_1_T_3 = _br_alloc_lists_1_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_1_T_4 = _br_alloc_lists_1_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_1_T_6 = _br_alloc_lists_1_T_3 \| _br_alloc_lists_1_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_T_7 = _br_alloc_lists_1_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_WIRE = _br_alloc_lists_1_T_7; // @[Mux.scala:30:73] wire _list_req_T_9 = io_ren_br_tags_1_bits_0 == 4'h2; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2_1 = _list_req_T_9; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_10 = io_ren_br_tags_2_bits_0 == 4'h2; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2_2 = _list_req_T_10; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_2 = {_list_req_WIRE_2_2, _list_req_WIRE_2_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_11 = {list_req_hi_2, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_2 = _list_req_T_11 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_2 = \|list_req_2; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_2_T = list_req_2[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_2_T_1 = list_req_2[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_2_T_2 = list_req_2[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_2_T_3 = _br_alloc_lists_2_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_2_T_4 = _br_alloc_lists_2_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_2_T_6 = _br_alloc_lists_2_T_3 \| _br_alloc_lists_2_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_T_7 = _br_alloc_lists_2_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_WIRE = _br_alloc_lists_2_T_7; // @[Mux.scala:30:73] wire _list_req_T_13 = io_ren_br_tags_1_bits_0 == 4'h3; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_3_1 = _list_req_T_13; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_14 = io_ren_br_tags_2_bits_0 == 4'h3; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_3_2 = _list_req_T_14; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_3 = {_list_req_WIRE_3_2, _list_req_WIRE_3_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_15 = {list_req_hi_3, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_3 = _list_req_T_15 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_3 = \|list_req_3; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_3_T = list_req_3[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_3_T_1 = list_req_3[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_3_T_2 = list_req_3[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_3_T_3 = _br_alloc_lists_3_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_3_T_4 = _br_alloc_lists_3_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_3_T_6 = _br_alloc_lists_3_T_3 \| _br_alloc_lists_3_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_T_7 = _br_alloc_lists_3_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_WIRE = _br_alloc_lists_3_T_7; // @[Mux.scala:30:73] wire _list_req_T_17 = io_ren_br_tags_1_bits_0 == 4'h4; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_4_1 = _list_req_T_17; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_18 = io_ren_br_tags_2_bits_0 == 4'h4; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_4_2 = _list_req_T_18; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_4 = {_list_req_WIRE_4_2, _list_req_WIRE_4_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_19 = {list_req_hi_4, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_4 = _list_req_T_19 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_4 = \|list_req_4; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_4_T = list_req_4[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_4_T_1 = list_req_4[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_4_T_2 = list_req_4[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_4_T_3 = _br_alloc_lists_4_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_4_T_4 = _br_alloc_lists_4_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_4_T_6 = _br_alloc_lists_4_T_3 \| _br_alloc_lists_4_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_T_7 = _br_alloc_lists_4_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_WIRE = _br_alloc_lists_4_T_7; // @[Mux.scala:30:73] wire _list_req_T_21 = io_ren_br_tags_1_bits_0 == 4'h5; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_5_1 = _list_req_T_21; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_22 = io_ren_br_tags_2_bits_0 == 4'h5; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_5_2 = _list_req_T_22; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_5 = {_list_req_WIRE_5_2, _list_req_WIRE_5_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_23 = {list_req_hi_5, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_5 = _list_req_T_23 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_5 = \|list_req_5; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_5_T = list_req_5[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_5_T_1 = list_req_5[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_5_T_2 = list_req_5[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_5_T_3 = _br_alloc_lists_5_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_5_T_4 = _br_alloc_lists_5_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_5_T_6 = _br_alloc_lists_5_T_3 \| _br_alloc_lists_5_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_T_7 = _br_alloc_lists_5_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_WIRE = _br_alloc_lists_5_T_7; // @[Mux.scala:30:73] wire _list_req_T_25 = io_ren_br_tags_1_bits_0 == 4'h6; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_6_1 = _list_req_T_25; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_26 = io_ren_br_tags_2_bits_0 == 4'h6; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_6_2 = _list_req_T_26; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_6 = {_list_req_WIRE_6_2, _list_req_WIRE_6_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_27 = {list_req_hi_6, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_6 = _list_req_T_27 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_6 = \|list_req_6; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_6_T = list_req_6[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_6_T_1 = list_req_6[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_6_T_2 = list_req_6[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_6_T_3 = _br_alloc_lists_6_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_6_T_4 = _br_alloc_lists_6_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_6_T_6 = _br_alloc_lists_6_T_3 \| _br_alloc_lists_6_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_T_7 = _br_alloc_lists_6_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_WIRE = _br_alloc_lists_6_T_7; // @[Mux.scala:30:73] wire _list_req_T_29 = io_ren_br_tags_1_bits_0 == 4'h7; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_7_1 = _list_req_T_29; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_30 = io_ren_br_tags_2_bits_0 == 4'h7; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_7_2 = _list_req_T_30; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_7 = {_list_req_WIRE_7_2, _list_req_WIRE_7_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_31 = {list_req_hi_7, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_7 = _list_req_T_31 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_7 = \|list_req_7; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_7_T = list_req_7[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_7_T_1 = list_req_7[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_7_T_2 = list_req_7[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_7_T_3 = _br_alloc_lists_7_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_7_T_4 = _br_alloc_lists_7_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_7_T_6 = _br_alloc_lists_7_T_3 \| _br_alloc_lists_7_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_T_7 = _br_alloc_lists_7_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_WIRE = _br_alloc_lists_7_T_7; // @[Mux.scala:30:73] wire _list_req_T_33 = io_ren_br_tags_1_bits_0 == 4'h8; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_8_1 = _list_req_T_33; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_34 = io_ren_br_tags_2_bits_0 == 4'h8; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_8_2 = _list_req_T_34; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_8 = {_list_req_WIRE_8_2, _list_req_WIRE_8_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_35 = {list_req_hi_8, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_8 = _list_req_T_35 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_8 = \|list_req_8; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_8_T = list_req_8[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_8_T_1 = list_req_8[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_8_T_2 = list_req_8[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_8_T_3 = _br_alloc_lists_8_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_8_T_4 = _br_alloc_lists_8_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_8_T_6 = _br_alloc_lists_8_T_3 \| _br_alloc_lists_8_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_T_7 = _br_alloc_lists_8_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_WIRE = _br_alloc_lists_8_T_7; // @[Mux.scala:30:73] wire _list_req_T_37 = io_ren_br_tags_1_bits_0 == 4'h9; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_9_1 = _list_req_T_37; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_38 = io_ren_br_tags_2_bits_0 == 4'h9; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_9_2 = _list_req_T_38; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_9 = {_list_req_WIRE_9_2, _list_req_WIRE_9_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_39 = {list_req_hi_9, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_9 = _list_req_T_39 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_9 = \|list_req_9; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_9_T = list_req_9[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_9_T_1 = list_req_9[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_9_T_2 = list_req_9[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_9_T_3 = _br_alloc_lists_9_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_9_T_4 = _br_alloc_lists_9_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_9_T_6 = _br_alloc_lists_9_T_3 \| _br_alloc_lists_9_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_T_7 = _br_alloc_lists_9_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_WIRE = _br_alloc_lists_9_T_7; // @[Mux.scala:30:73] wire _list_req_T_41 = io_ren_br_tags_1_bits_0 == 4'hA; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_10_1 = _list_req_T_41; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_42 = io_ren_br_tags_2_bits_0 == 4'hA; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_10_2 = _list_req_T_42; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_10 = {_list_req_WIRE_10_2, _list_req_WIRE_10_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_43 = {list_req_hi_10, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_10 = _list_req_T_43 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_10 = \|list_req_10; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_10_T = list_req_10[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_10_T_1 = list_req_10[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_10_T_2 = list_req_10[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_10_T_3 = _br_alloc_lists_10_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_10_T_4 = _br_alloc_lists_10_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_10_T_6 = _br_alloc_lists_10_T_3 \| _br_alloc_lists_10_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_T_7 = _br_alloc_lists_10_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_WIRE = _br_alloc_lists_10_T_7; // @[Mux.scala:30:73] wire _list_req_T_45 = io_ren_br_tags_1_bits_0 == 4'hB; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_11_1 = _list_req_T_45; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_46 = io_ren_br_tags_2_bits_0 == 4'hB; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_11_2 = _list_req_T_46; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_11 = {_list_req_WIRE_11_2, _list_req_WIRE_11_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_47 = {list_req_hi_11, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_11 = _list_req_T_47 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_11 = \|list_req_11; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_11_T = list_req_11[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_11_T_1 = list_req_11[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_11_T_2 = list_req_11[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_11_T_3 = _br_alloc_lists_11_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_11_T_4 = _br_alloc_lists_11_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_11_T_6 = _br_alloc_lists_11_T_3 \| _br_alloc_lists_11_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_T_7 = _br_alloc_lists_11_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_WIRE = _br_alloc_lists_11_T_7; // @[Mux.scala:30:73] wire [79:0] _spec_alloc_list_T = spec_alloc_list \| alloc_masks_0; // @[rename-freelist.scala:63:32, :72:84, :116:39] wire [79:0] _spec_alloc_list_T_1 = ~dealloc_mask; // @[rename-freelist.scala:80:49, :116:59] wire [79:0] _spec_alloc_list_T_2 = _spec_alloc_list_T & _spec_alloc_list_T_1; // @[rename-freelist.scala:116:{39,57,59}] wire [79:0] _spec_alloc_list_T_3 = ~com_despec; // @[rename-freelist.scala:82:97, :116:75] wire [79:0] _spec_alloc_list_T_4 = _spec_alloc_list_T_2 & _spec_alloc_list_T_3; // @[rename-freelist.scala:116:{57,73,75}] wire [79:0] _free_list_T = ~sel_mask; // @[rename-freelist.scala:75:82, :119:33] wire [79:0] _free_list_T_1 = free_list & _free_list_T; // @[rename-freelist.scala:62:26, :119:{31,33}] wire [79:0] _free_list_T_2 = _free_list_T_1 \| dealloc_mask; // @[rename-freelist.scala:80:49, :119:{31,44}] wire can_sel = \|sels_0; // @[util.scala:415:20] reg r_valid; // @[rename-freelist.scala:124:26] assign io_alloc_pregs_0_valid_0 = r_valid; // @[rename-freelist.scala:52:7, :124:26] wire [15:0] r_sel_hi = sels_0[79:64]; // @[OneHot.scala:30:18] wire [63:0] r_sel_lo = sels_0[63:0]; // @[OneHot.scala:31:18] wire _r_sel_T = \|r_sel_hi; // @[OneHot.scala:30:18, :32:14] wire [63:0] _r_sel_T_1 = {48'h0, r_sel_hi} \| r_sel_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [31:0] r_sel_hi_1 = _r_sel_T_1[63:32]; // @[OneHot.scala:30:18, :32:28] wire [31:0] r_sel_lo_1 = _r_sel_T_1[31:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_2 = \|r_sel_hi_1; // @[OneHot.scala:30:18, :32:14] wire [31:0] _r_sel_T_3 = r_sel_hi_1 \| r_sel_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] r_sel_hi_2 = _r_sel_T_3[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] r_sel_lo_2 = _r_sel_T_3[15:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_4 = \|r_sel_hi_2; // @[OneHot.scala:30:18, :32:14] wire [15:0] _r_sel_T_5 = r_sel_hi_2 \| r_sel_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] r_sel_hi_3 = _r_sel_T_5[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] r_sel_lo_3 = _r_sel_T_5[7:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_6 = \|r_sel_hi_3; // @[OneHot.scala:30:18, :32:14] wire [7:0] _r_sel_T_7 = r_sel_hi_3 \| r_sel_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] r_sel_hi_4 = _r_sel_T_7[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] r_sel_lo_4 = _r_sel_T_7[3:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_8 = \|r_sel_hi_4; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sel_T_9 = r_sel_hi_4 \| r_sel_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sel_hi_5 = _r_sel_T_9[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sel_lo_5 = _r_sel_T_9[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_10 = \|r_sel_hi_5; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sel_T_11 = r_sel_hi_5 \| r_sel_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sel_T_12 = _r_sel_T_11[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sel_T_13 = {_r_sel_T_10, _r_sel_T_12}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sel_T_14 = {_r_sel_T_8, _r_sel_T_13}; // @[OneHot.scala:32:{10,14}] wire [3:0] _r_sel_T_15 = {_r_sel_T_6, _r_sel_T_14}; // @[OneHot.scala:32:{10,14}] wire [4:0] _r_sel_T_16 = {_r_sel_T_4, _r_sel_T_15}; // @[OneHot.scala:32:{10,14}] wire [5:0] _r_sel_T_17 = {_r_sel_T_2, _r_sel_T_16}; // @[OneHot.scala:32:{10,14}] wire [6:0] _r_sel_T_18 = {_r_sel_T, _r_sel_T_17}; // @[OneHot.scala:32:{10,14}] reg [6:0] r_sel; // @[rename-freelist.scala:125:28] assign io_alloc_pregs_0_bits_0 = r_sel; // @[rename-freelist.scala:52:7, :125:28] wire _r_valid_T = ~io_reqs_0_0; // @[rename-freelist.scala:52:7, :127:27] wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-freelist.scala:124:26, :127:{24,27}] wire _r_valid_T_2 = _r_valid_T_1 \| can_sel; // @[rename-freelist.scala:123:27, :127:{24,39}] wire _sel_fire_0_T = ~r_valid; // @[rename-freelist.scala:124:26, :128:21] wire _sel_fire_0_T_1 = _sel_fire_0_T \| io_reqs_0_0; // @[rename-freelist.scala:52:7, :128:{21,30}] assign _sel_fire_0_T_2 = _sel_fire_0_T_1 & can_sel; // @[rename-freelist.scala:123:27, :128:{30,45}] assign sel_fire_0 = _sel_fire_0_T_2; // @[rename-freelist.scala:68:23, :128:45] wire can_sel_1 = \|sels_1; // @[util.scala:415:20] reg r_valid_1; // @[rename-freelist.scala:124:26] assign io_alloc_pregs_1_valid_0 = r_valid_1; // @[rename-freelist.scala:52:7, :124:26] wire [15:0] r_sel_hi_6 = sels_1[79:64]; // @[OneHot.scala:30:18] wire [63:0] r_sel_lo_6 = sels_1[63:0]; // @[OneHot.scala:31:18] wire _r_sel_T_19 = \|r_sel_hi_6; // @[OneHot.scala:30:18, :32:14] wire [63:0] _r_sel_T_20 = {48'h0, r_sel_hi_6} \| r_sel_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [31:0] r_sel_hi_7 = _r_sel_T_20[63:32]; // @[OneHot.scala:30:18, :32:28] wire [31:0] r_sel_lo_7 = _r_sel_T_20[31:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_21 = \|r_sel_hi_7; // @[OneHot.scala:30:18, :32:14] wire [31:0] _r_sel_T_22 = r_sel_hi_7 \| r_sel_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] r_sel_hi_8 = _r_sel_T_22[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] r_sel_lo_8 = _r_sel_T_22[15:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_23 = \|r_sel_hi_8; // @[OneHot.scala:30:18, :32:14] wire [15:0] _r_sel_T_24 = r_sel_hi_8 \| r_sel_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] r_sel_hi_9 = _r_sel_T_24[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] r_sel_lo_9 = _r_sel_T_24[7:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_25 = \|r_sel_hi_9; // @[OneHot.scala:30:18, :32:14] wire [7:0] _r_sel_T_26 = r_sel_hi_9 \| r_sel_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] r_sel_hi_10 = _r_sel_T_26[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] r_sel_lo_10 = _r_sel_T_26[3:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_27 = \|r_sel_hi_10; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sel_T_28 = r_sel_hi_10 \| r_sel_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sel_hi_11 = _r_sel_T_28[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sel_lo_11 = _r_sel_T_28[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_29 = \|r_sel_hi_11; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sel_T_30 = r_sel_hi_11 \| r_sel_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sel_T_31 = _r_sel_T_30[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sel_T_32 = {_r_sel_T_29, _r_sel_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sel_T_33 = {_r_sel_T_27, _r_sel_T_32}; // @[OneHot.scala:32:{10,14}] wire [3:0] _r_sel_T_34 = {_r_sel_T_25, _r_sel_T_33}; // @[OneHot.scala:32:{10,14}] wire [4:0] _r_sel_T_35 = {_r_sel_T_23, _r_sel_T_34}; // @[OneHot.scala:32:{10,14}] wire [5:0] _r_sel_T_36 = {_r_sel_T_21, _r_sel_T_35}; // @[OneHot.scala:32:{10,14}] wire [6:0] _r_sel_T_37 = {_r_sel_T_19, _r_sel_T_36}; // @[OneHot.scala:32:{10,14}] reg [6:0] r_sel_1; // @[rename-freelist.scala:125:28] assign io_alloc_pregs_1_bits_0 = r_sel_1; // @[rename-freelist.scala:52:7, :125:28] wire _r_valid_T_3 = ~io_reqs_1_0; // @[rename-freelist.scala:52:7, :127:27] wire _r_valid_T_4 = r_valid_1 & _r_valid_T_3; // @[rename-freelist.scala:124:26, :127:{24,27}] wire _r_valid_T_5 = _r_valid_T_4 \| can_sel_1; // @[rename-freelist.scala:123:27, :127:{24,39}] wire _sel_fire_1_T = ~r_valid_1; // @[rename-freelist.scala:124:26, :128:21] wire _sel_fire_1_T_1 = _sel_fire_1_T \| io_reqs_1_0; // @[rename-freelist.scala:52:7, :128:{21,30}] assign _sel_fire_1_T_2 = _sel_fire_1_T_1 & can_sel_1; // @[rename-freelist.scala:123:27, :128:{30,45}] assign sel_fire_1 = _sel_fire_1_T_2; // @[rename-freelist.scala:68:23, :128:45] wire [79:0] _io_debug_freelist_T_1 = _io_debug_freelist_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _io_debug_freelist_T_2 = {80{io_alloc_pregs_0_valid_0}}; // @[rename-freelist.scala:52:7, :134:90] wire [79:0] _io_debug_freelist_T_3 = _io_debug_freelist_T_1 & _io_debug_freelist_T_2; // @[rename-freelist.scala:134:{76,84,90}] wire [79:0] _io_debug_freelist_T_5 = _io_debug_freelist_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _io_debug_freelist_T_6 = {80{io_alloc_pregs_1_valid_0}}; // @[rename-freelist.scala:52:7, :134:90] wire [79:0] _io_debug_freelist_T_7 = _io_debug_freelist_T_5 & _io_debug_freelist_T_6; // @[rename-freelist.scala:134:{76,84,90}] wire [79:0] _io_debug_freelist_T_8 = _io_debug_freelist_T_3 \| _io_debug_freelist_T_7; // @[rename-freelist.scala:134:{84,111}] assign _io_debug_freelist_T_9 = free_list \| _io_debug_freelist_T_8; // @[rename-freelist.scala:62:26, :134:{34,111}] assign io_debug_freelist_0 = _io_debug_freelist_T_9; // @[rename-freelist.scala:52:7, :134:34]
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_3 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { offset : UInt<2>}, flip lb_resp : UInt<128>, lb_write : { valid : UInt<1>, bits : { offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 4) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_7 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect rpq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect rpq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect rpq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect rpq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect rpq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect rpq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect rpq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect rpq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect rpq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect rpq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect rpq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect rpq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect rpq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect rpq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect rpq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect rpq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect rpq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect rpq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect rpq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect rpq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect rpq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect rpq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect rpq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect rpq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect rpq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect rpq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect rpq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect rpq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect rpq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect rpq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect rpq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect rpq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect rpq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect rpq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect rpq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect rpq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect rpq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_typ, io.req.uop.fp_typ connect rpq.io.enq.bits.uop.fp_rm, io.req.uop.fp_rm connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.fcn_op, io.req.uop.fcn_op connect rpq.io.enq.bits.uop.fcn_dw, io.req.uop.fcn_dw connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.csr_cmd, io.req.uop.csr_cmd connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.fp_ctrl.vec, io.req.uop.fp_ctrl.vec connect rpq.io.enq.bits.uop.fp_ctrl.wflags, io.req.uop.fp_ctrl.wflags connect rpq.io.enq.bits.uop.fp_ctrl.sqrt, io.req.uop.fp_ctrl.sqrt connect rpq.io.enq.bits.uop.fp_ctrl.div, io.req.uop.fp_ctrl.div connect rpq.io.enq.bits.uop.fp_ctrl.fma, io.req.uop.fp_ctrl.fma connect rpq.io.enq.bits.uop.fp_ctrl.fastpipe, io.req.uop.fp_ctrl.fastpipe connect rpq.io.enq.bits.uop.fp_ctrl.toint, io.req.uop.fp_ctrl.toint connect rpq.io.enq.bits.uop.fp_ctrl.fromint, io.req.uop.fp_ctrl.fromint connect rpq.io.enq.bits.uop.fp_ctrl.typeTagOut, io.req.uop.fp_ctrl.typeTagOut connect rpq.io.enq.bits.uop.fp_ctrl.typeTagIn, io.req.uop.fp_ctrl.typeTagIn connect rpq.io.enq.bits.uop.fp_ctrl.swap23, io.req.uop.fp_ctrl.swap23 connect rpq.io.enq.bits.uop.fp_ctrl.swap12, io.req.uop.fp_ctrl.swap12 connect rpq.io.enq.bits.uop.fp_ctrl.ren3, io.req.uop.fp_ctrl.ren3 connect rpq.io.enq.bits.uop.fp_ctrl.ren2, io.req.uop.fp_ctrl.ren2 connect rpq.io.enq.bits.uop.fp_ctrl.ren1, io.req.uop.fp_ctrl.ren1 connect rpq.io.enq.bits.uop.fp_ctrl.wen, io.req.uop.fp_ctrl.wen connect rpq.io.enq.bits.uop.fp_ctrl.ldst, io.req.uop.fp_ctrl.ldst connect rpq.io.enq.bits.uop.op2_sel, io.req.uop.op2_sel connect rpq.io.enq.bits.uop.op1_sel, io.req.uop.op1_sel connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.pimm, io.req.uop.pimm connect rpq.io.enq.bits.uop.imm_sel, io.req.uop.imm_sel connect rpq.io.enq.bits.uop.imm_rename, io.req.uop.imm_rename connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.is_mov, io.req.uop.is_mov connect rpq.io.enq.bits.uop.is_rocc, io.req.uop.is_rocc connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.is_eret, io.req.uop.is_eret connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_sfence, io.req.uop.is_sfence connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.br_type, io.req.uop.br_type connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.dis_col_sel, io.req.uop.dis_col_sel connect rpq.io.enq.bits.uop.iw_p3_bypass_hint, io.req.uop.iw_p3_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_bypass_hint, io.req.uop.iw_p2_bypass_hint connect rpq.io.enq.bits.uop.iw_p1_bypass_hint, io.req.uop.iw_p1_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_speculative_child, io.req.uop.iw_p2_speculative_child connect rpq.io.enq.bits.uop.iw_p1_speculative_child, io.req.uop.iw_p1_speculative_child connect rpq.io.enq.bits.uop.iw_issued_partial_dgen, io.req.uop.iw_issued_partial_dgen connect rpq.io.enq.bits.uop.iw_issued_partial_agen, io.req.uop.iw_issued_partial_agen connect rpq.io.enq.bits.uop.iw_issued, io.req.uop.iw_issued connect rpq.io.enq.bits.uop.fu_code[0], io.req.uop.fu_code[0] connect rpq.io.enq.bits.uop.fu_code[1], io.req.uop.fu_code[1] connect rpq.io.enq.bits.uop.fu_code[2], io.req.uop.fu_code[2] connect rpq.io.enq.bits.uop.fu_code[3], io.req.uop.fu_code[3] connect rpq.io.enq.bits.uop.fu_code[4], io.req.uop.fu_code[4] connect rpq.io.enq.bits.uop.fu_code[5], io.req.uop.fu_code[5] connect rpq.io.enq.bits.uop.fu_code[6], io.req.uop.fu_code[6] connect rpq.io.enq.bits.uop.fu_code[7], io.req.uop.fu_code[7] connect rpq.io.enq.bits.uop.fu_code[8], io.req.uop.fu_code[8] connect rpq.io.enq.bits.uop.fu_code[9], io.req.uop.fu_code[9] connect rpq.io.enq.bits.uop.iq_type[0], io.req.uop.iq_type[0] connect rpq.io.enq.bits.uop.iq_type[1], io.req.uop.iq_type[1] connect rpq.io.enq.bits.uop.iq_type[2], io.req.uop.iq_type[2] connect rpq.io.enq.bits.uop.iq_type[3], io.req.uop.iq_type[3] connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock reg refill_ctr : UInt<2>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en connect io.meta_write.bits.tag, req_tag connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2) node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2) node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2) node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4) node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2) node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5) node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2) node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6) node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2) node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8) node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8) node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9) node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9) node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10) node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10) node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11) node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11) node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12) node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12) node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13) node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13) node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14) node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14) node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15) node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15) node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo) node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8) node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo) node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12) node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a connect io.refill.valid, UInt<1>(0h0) node _io_refill_bits_addr_T = shl(refill_ctr, 4) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<2>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp connect io.replay.valid, UInt<1>(0h0) connect io.replay.bits, rpq.io.deq.bits connect io.wb_req.valid, UInt<1>(0h0) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) connect io.resp.valid, UInt<1>(0h0) connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella connect io.resp.bits.data, rpq.io.deq.bits.data connect io.resp.bits.uop, rpq.io.deq.bits.uop connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en connect io.mem_finish.valid, UInt<1>(0h0) connect io.mem_finish.bits, grantack.bits connect io.lb_write.valid, UInt<1>(0h0) node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data connect io.mem_grant.ready, UInt<1>(0h0) node _io_lb_read_offset_T = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.offset, _io_lb_read_offset_T node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : connect io.mem_grant.ready, UInt<1>(0h1) node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.lb_write.valid, io.mem_grant.valid else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<4>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:261 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node word_idx = bits(rp_addr, 3, 3) node _data_word_T = cat(word_idx, UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T node _io_lb_read_offset_T_1 = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.offset, _io_lb_read_offset_T_1 node _io_resp_valid_T = and(rpq.io.deq.valid, drain_load) connect io.resp.valid, _io_resp_valid_T node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.offset, refill_ctr connect io.refill.valid, UInt<1>(0h1) node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<2>(0h3)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:345 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1	module BoomMSHR_3( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input io_req_uop_iq_type_0, // @[mshrs.scala:39:14] input io_req_uop_iq_type_1, // @[mshrs.scala:39:14] input io_req_uop_iq_type_2, // @[mshrs.scala:39:14] input io_req_uop_iq_type_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_0, // @[mshrs.scala:39:14] input io_req_uop_fu_code_1, // @[mshrs.scala:39:14] input io_req_uop_fu_code_2, // @[mshrs.scala:39:14] input io_req_uop_fu_code_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_4, // @[mshrs.scala:39:14] input io_req_uop_fu_code_5, // @[mshrs.scala:39:14] input io_req_uop_fu_code_6, // @[mshrs.scala:39:14] input io_req_uop_fu_code_7, // @[mshrs.scala:39:14] input io_req_uop_fu_code_8, // @[mshrs.scala:39:14] input io_req_uop_fu_code_9, // @[mshrs.scala:39:14] input io_req_uop_iw_issued, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] input [2:0] io_req_uop_dis_col_sel, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_type, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_sfence, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_is_eret, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_rocc, // @[mshrs.scala:39:14] input io_req_uop_is_mov, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input io_req_uop_imm_rename, // @[mshrs.scala:39:14] input [2:0] io_req_uop_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_pimm, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [1:0] io_req_uop_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_op2_sel, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_div, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input [2:0] io_req_uop_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fcn_dw, // @[mshrs.scala:39:14] input [4:0] io_req_uop_fcn_op, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input [2:0] io_req_uop_fp_rm, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_typ, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] output [1:0] io_lb_read_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :234:30, :241:40, :246:41, :266:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_4; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_5; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_6; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_7; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_8; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_9; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_dis_col_sel; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_type; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_eret; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rocc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_mov; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_imm_rename; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_pimm; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_op2_sel; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_toint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fma; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_div; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_vec; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fcn_dw; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_fcn_op; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_fp_rm; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_typ; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_data; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire [7:0] _rpq_io_deq_bits_way_en; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_0_0 = io_req_uop_iq_type_0; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_1_0 = io_req_uop_iq_type_1; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_2_0 = io_req_uop_iq_type_2; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_3_0 = io_req_uop_iq_type_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_0_0 = io_req_uop_fu_code_0; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_1_0 = io_req_uop_fu_code_1; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_2_0 = io_req_uop_fu_code_2; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_3_0 = io_req_uop_fu_code_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_4_0 = io_req_uop_fu_code_4; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_5_0 = io_req_uop_fu_code_5; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_6_0 = io_req_uop_fu_code_6; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_7_0 = io_req_uop_fu_code_7; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_8_0 = io_req_uop_fu_code_8; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_9_0 = io_req_uop_fu_code_9; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_0 = io_req_uop_iw_issued; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_agen_0 = io_req_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_dgen_0 = io_req_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iw_p1_speculative_child_0 = io_req_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iw_p2_speculative_child_0 = io_req_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_bypass_hint_0 = io_req_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_bypass_hint_0 = io_req_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p3_bypass_hint_0 = io_req_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_dis_col_sel_0 = io_req_uop_dis_col_sel; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_type_0 = io_req_uop_br_type; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_sfence_0 = io_req_uop_is_sfence; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_is_eret_0 = io_req_uop_is_eret; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_rocc_0 = io_req_uop_is_rocc; // @[mshrs.scala:36:7] wire io_req_uop_is_mov_0 = io_req_uop_is_mov; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire io_req_uop_imm_rename_0 = io_req_uop_imm_rename; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_imm_sel_0 = io_req_uop_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_pimm_0 = io_req_uop_pimm; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_op1_sel_0 = io_req_uop_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_op2_sel_0 = io_req_uop_op2_sel; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ldst_0 = io_req_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wen_0 = io_req_uop_fp_ctrl_wen; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren1_0 = io_req_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren2_0 = io_req_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren3_0 = io_req_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap12_0 = io_req_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap23_0 = io_req_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagIn_0 = io_req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagOut_0 = io_req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fromint_0 = io_req_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_toint_0 = io_req_uop_fp_ctrl_toint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fastpipe_0 = io_req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fma_0 = io_req_uop_fp_ctrl_fma; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_div_0 = io_req_uop_fp_ctrl_div; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_sqrt_0 = io_req_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wflags_0 = io_req_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_vec_0 = io_req_uop_fp_ctrl_vec; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_csr_cmd_0 = io_req_uop_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fcn_dw_0 = io_req_uop_fcn_dw; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_fcn_op_0 = io_req_uop_fcn_op; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_fp_rm_0 = io_req_uop_fp_rm; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_typ_0 = io_req_uop_fp_typ; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:213:11] wire _state_T_26 = reset; // @[mshrs.scala:220:15] wire _state_T_34 = reset; // @[mshrs.scala:213:11] wire _state_T_60 = reset; // @[mshrs.scala:220:15] wire [1:0] io_id = 2'h3; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:174:28] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h3; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h3; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h3; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:163:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_offset_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg req_uop_iq_type_0; // @[mshrs.scala:109:20] reg req_uop_iq_type_1; // @[mshrs.scala:109:20] reg req_uop_iq_type_2; // @[mshrs.scala:109:20] reg req_uop_iq_type_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_0; // @[mshrs.scala:109:20] reg req_uop_fu_code_1; // @[mshrs.scala:109:20] reg req_uop_fu_code_2; // @[mshrs.scala:109:20] reg req_uop_fu_code_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_4; // @[mshrs.scala:109:20] reg req_uop_fu_code_5; // @[mshrs.scala:109:20] reg req_uop_fu_code_6; // @[mshrs.scala:109:20] reg req_uop_fu_code_7; // @[mshrs.scala:109:20] reg req_uop_fu_code_8; // @[mshrs.scala:109:20] reg req_uop_fu_code_9; // @[mshrs.scala:109:20] reg req_uop_iw_issued; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:109:20] reg [2:0] req_uop_iw_p1_speculative_child; // @[mshrs.scala:109:20] reg [2:0] req_uop_iw_p2_speculative_child; // @[mshrs.scala:109:20] reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:109:20] reg [2:0] req_uop_dis_col_sel; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_type; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_sfence; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_is_eret; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_rocc; // @[mshrs.scala:109:20] reg req_uop_is_mov; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg req_uop_imm_rename; // @[mshrs.scala:109:20] reg [2:0] req_uop_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_pimm; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [1:0] req_uop_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_op2_sel; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wen; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_toint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fma; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_div; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_vec; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fcn_dw; // @[mshrs.scala:109:20] reg [4:0] req_uop_fcn_op; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg [2:0] req_uop_fp_rm; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_typ; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign io_meta_write_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :163:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :163:37] wire [33:0] _GEN_27 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :168:26] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:168:26] assign _io_mem_acquire_bits_T = _GEN_27; // @[mshrs.scala:168:26] wire [33:0] rp_addr_hi; // @[mshrs.scala:271:22] assign rp_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :271:22] wire [33:0] hi; // @[mshrs.scala:276:10] assign hi = _GEN_27; // @[mshrs.scala:168:26, :276:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:341:31] assign io_replay_bits_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :341:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:168:{26,45}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 \| _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 \| _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 \| _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :172:57] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :172:{43,57}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :172:{25,43}] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :197:{27,49}] wire [35:0] _io_lb_read_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45] wire [35:0] _io_lb_read_offset_T_1 = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45, :282:47] wire [4:0] state_new_state; // @[mshrs.scala:210:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:213:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire [3:0] _GEN_28 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_28; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_28; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:220:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :260:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :269:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:267:59, :268:60, :269:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :271:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:271:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:271:22, :272:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:272:56, :274:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :274:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & drain_load; // @[mshrs.scala:36:7, :268:60, :280:40] wire _io_resp_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :268:60, :284:43] wire _GEN_41 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_41 & _io_probe_rdy_T_4 & _io_resp_valid_T; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _GEN_41 \| ~_io_probe_rdy_T_4 ? _rpq_io_deq_bits_data : _io_resp_bits_data_T_23; // @[package.scala:16:47] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :290:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :268:60, :296:{31,52,55}] assign io_commit_val_0 = ~_GEN_41 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :303:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :303:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:303:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :303:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :303:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:303:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :307:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :309:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :311:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:311:{17,18}, :312:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :313:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :319:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :324:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :328:22] wire _GEN_42 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :200:21, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:41] assign io_lb_read_offset_0 = _GEN_41 ? _io_lb_read_offset_T[1:0] : _io_probe_rdy_T_4 ? _io_lb_read_offset_T_1[1:0] : _GEN_42 \| ~_T_43 ? _io_lb_read_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_43 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_42; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_43) & _T_43; // @[package.scala:16:47] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :333:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:333:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :338:22] wire _GEN_44 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :176:26, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:39] wire _GEN_45 = _io_probe_rdy_T_4 \| _GEN_44; // @[package.scala:16:47] wire _GEN_46 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~_GEN_46 & _T_46 & _rpq_io_deq_valid; // @[mshrs.scala:36:7, :128:19, :176:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}, :339:15] assign rpq_io_deq_ready = ~_GEN_41 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T : ~_GEN_44 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire _GEN_47 = _GEN_46 \| ~_T_46; // @[mshrs.scala:176:26, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}] assign io_replay_bits_way_en_0 = _GEN_47 ? _rpq_io_deq_bits_way_en : req_way_en; // @[mshrs.scala:36:7, :109:20, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :341:70] wire [39:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:341:{31,70}] assign io_replay_bits_addr_0 = _GEN_47 ? _rpq_io_deq_bits_addr : _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39, :341:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_48 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:{22,39}, :351:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_48 & _sec_rdy_T_4); // @[package.scala:16:47] wire _GEN_49 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _GEN_48; // @[mshrs.scala:148:129, :156:26, :158:31, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:36, :324:37, :328:41, :338:39, :351:44] assign io_meta_write_bits_data_coh_state_0 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_49 \| ~_sec_rdy_T_4 ? coh_on_clear_state : new_coh_state; // @[package.scala:16:47] wire _GEN_50 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_50) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :368:17] wire _GEN_51 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_52 = _T_46 \| _GEN_51; // @[mshrs.scala:162:26, :338:{22,39}, :351:44, :361:42, :367:42, :369:38] wire _GEN_53 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_52; // @[package.scala:16:47] wire _GEN_54 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_53; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_54 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :371:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:210:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:213:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:220:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_142 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_246 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_142( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_246 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ITLB_5 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_238 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s2_5 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_17 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_239 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_240 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_241 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_242 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_243 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_244 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_245 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_246 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_247 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_248 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_249 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_250 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_251 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gf_inst_array, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)	module ITLB_5( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output io_ptw_req_bits_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input io_ptw_gstatus_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[TLB.scala:320:14] input io_kill // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire io_kill_0 = io_kill; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_resp_size = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8] wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8] wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53] wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46] wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33] wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [3:0] _misaligned_T_2 = 4'h3; // @[TLB.scala:550:69] wire [4:0] _misaligned_T_1 = 5'h3; // @[TLB.scala:550:69] wire [3:0] _misaligned_T = 4'h4; // @[OneHot.scala:58:35] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire _io_ptw_req_bits_valid_T; // @[TLB.scala:663:28] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 \| sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 \| sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 \| sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 \| sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 \| sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 \| sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 \| sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 \| sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 \| _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 \| _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 \| _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 \| _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 \| _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 \| _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 \| _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 \| _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 \| _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 \| _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 \| _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 \| _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 \| _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 \| _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 \| _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 \| _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T \| sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 \| _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {38'h0, io_req_bits_vaddr_0[1:0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 \| lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {\|hi_1, \|hi_2, hi_2[1] \| lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {\|hi_4, hi_4[1] \| lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 \| _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 \| _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 \| multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 \| multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 \| _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 \| multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 \| multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 \| multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 \| multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 \| _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 \| multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 \| multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 \| _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 \| multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 \| multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 \| _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[TLB.scala:318:7, :663:28] assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[TLB.scala:318:7, :663:28] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 \| sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 \| sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 \| sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 \| sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = \|r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 \| r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 \| superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T \| superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 \| superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = \|r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 \| r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_144 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_144( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1_1 : input clock : Clock input reset : Reset output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in inst chain of SynchronizerShiftReg_w1_d3_1 connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] wire _WIRE : UInt<1>[1] wire _WIRE_1 : UInt<1> connect _WIRE_1, chain.io.q node _T = bits(_WIRE_1, 0, 0) connect _WIRE[0], _T connect nodeOut, _WIRE	module IntSyncAsyncCrossingSink_n1x1_1( // @[Crossing.scala:74:9] input clock, // @[Crossing.scala:74:9] input reset, // @[Crossing.scala:74:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:74:9] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:74:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:74:9] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9] SynchronizerShiftReg_w1_d3_1 chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (nodeIn_sync_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_0) ); // @[ShiftReg.scala:45:23] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_22 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_22( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageTable_3 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<8>(0hff)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) node idx_history = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 7, 0) node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) node tag_history = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1) node _tag_T = shr(_T_1, 8) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 7, 0) smem hi_us : UInt<1>[4] [256] smem lo_us : UInt<1>[4] [256] smem table : UInt<12>[4] [256] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire _s2_req_rtage_WIRE : UInt<8> invalidate _s2_req_rtage_WIRE when io.f1_req_valid : connect _s2_req_rtage_WIRE, s1_hashed_idx read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_2 : UInt<12> connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0] node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0) connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 10, 3) connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1 node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 11, 11) connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2 wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_4 : UInt<12> connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1] node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0) connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3 node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 10, 3) connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4 node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 11, 11) connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5 wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_6 : UInt<12> connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2] node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0) connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6 node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 10, 3) connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7 node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 11, 11) connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8 wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_8 : UInt<12> connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3] node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0) connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9 node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 10, 3) connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10 node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 11, 11) connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11 wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid wire _s2_req_rhius_WIRE : UInt<8> invalidate _s2_req_rhius_WIRE when io.f1_req_valid : connect _s2_req_rhius_WIRE, s1_hashed_idx read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock wire _s2_req_rlous_WIRE : UInt<8> invalidate _s2_req_rlous_WIRE when io.f1_req_valid : connect _s2_req_rlous_WIRE, s1_hashed_idx read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 reg io_f3_resp_0_valid_REG : UInt<1>, clock connect io_f3_resp_0_valid_REG, s2_req_rhits[0] connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0]) reg io_f3_resp_0_bits_u_REG : UInt, clock connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG reg io_f3_resp_0_bits_ctr_REG : UInt, clock connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG reg io_f3_resp_1_valid_REG : UInt<1>, clock connect io_f3_resp_1_valid_REG, s2_req_rhits[1] connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1]) reg io_f3_resp_1_bits_u_REG : UInt, clock connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG reg io_f3_resp_1_bits_ctr_REG : UInt, clock connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG reg io_f3_resp_2_valid_REG : UInt<1>, clock connect io_f3_resp_2_valid_REG, s2_req_rhits[2] connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2]) reg io_f3_resp_2_bits_u_REG : UInt, clock connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG reg io_f3_resp_2_bits_ctr_REG : UInt, clock connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG reg io_f3_resp_3_valid_REG : UInt<1>, clock connect io_f3_resp_3_valid_REG, s2_req_rhits[3] connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3]) reg io_f3_resp_3_bits_u_REG : UInt, clock connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG reg io_f3_resp_3_bits_ctr_REG : UInt, clock connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _doing_clear_u_hi_T = bits(clear_u_ctr, 19, 19) node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1)) node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1) node _doing_clear_u_lo_T = bits(clear_u_ctr, 19, 19) node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0)) node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1) node clear_u_idx = shr(clear_u_ctr, 11) node _T_2 = shr(io.update_pc, 4) node idx_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) node idx_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) node idx_history_1 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 7, 0) node tag_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) node tag_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) node tag_history_1 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1) node _tag_T_2 = shr(_T_2, 8) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 7, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] node _T_3 = mux(doing_reset, reset_idx, update_idx) wire _WIRE : UInt<12>[4] connect _WIRE[0], UInt<12>(0h0) connect _WIRE[1], UInt<12>(0h0) connect _WIRE[2], UInt<12>(0h0) connect _WIRE[3], UInt<12>(0h0) node hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _T_4 = cat(hi, update_wdata[0].ctr) node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _T_5 = cat(hi_1, update_wdata[1].ctr) node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _T_6 = cat(hi_2, update_wdata[2].ctr) node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _T_7 = cat(hi_3, update_wdata[3].ctr) wire _WIRE_1 : UInt<12>[4] connect _WIRE_1[0], _T_4 connect _WIRE_1[1], _T_5 connect _WIRE_1[2], _T_6 connect _WIRE_1[3], _T_7 node _T_8 = mux(doing_reset, _WIRE, _WIRE_1) node _T_9 = not(UInt<4>(0h0)) node lo = cat(io.update_mask[1], io.update_mask[0]) node hi_4 = cat(io.update_mask[3], io.update_mask[2]) node _T_10 = cat(hi_4, lo) node _T_11 = mux(doing_reset, _T_9, _T_10) node _T_12 = bits(_T_11, 0, 0) node _T_13 = bits(_T_11, 1, 1) node _T_14 = bits(_T_11, 2, 2) node _T_15 = bits(_T_11, 3, 3) write mport MPORT = table[_T_3], clock when _T_12 : connect MPORT[0], _T_8[0] when _T_13 : connect MPORT[1], _T_8[1] when _T_14 : connect MPORT[2], _T_8[2] when _T_15 : connect MPORT[3], _T_8[3] wire update_hi_wdata : UInt<1>[4] node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx) node _T_17 = mux(doing_reset, reset_idx, _T_16) node _T_18 = or(doing_reset, doing_clear_u_hi) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], UInt<1>(0h0) connect _WIRE_2[1], UInt<1>(0h0) connect _WIRE_2[2], UInt<1>(0h0) connect _WIRE_2[3], UInt<1>(0h0) node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata) node _T_20 = or(doing_reset, doing_clear_u_hi) node _T_21 = not(UInt<4>(0h0)) node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_22 = cat(hi_5, lo_1) node _T_23 = mux(_T_20, _T_21, _T_22) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = bits(_T_23, 2, 2) node _T_27 = bits(_T_23, 3, 3) node _T_28 = bits(_T_17, 7, 0) write mport MPORT_1 = hi_us[_T_28], clock when _T_24 : connect MPORT_1[0], _T_19[0] when _T_25 : connect MPORT_1[1], _T_19[1] when _T_26 : connect MPORT_1[2], _T_19[2] when _T_27 : connect MPORT_1[3], _T_19[3] wire update_lo_wdata : UInt<1>[4] node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx) node _T_30 = mux(doing_reset, reset_idx, _T_29) node _T_31 = or(doing_reset, doing_clear_u_lo) wire _WIRE_3 : UInt<1>[4] connect _WIRE_3[0], UInt<1>(0h0) connect _WIRE_3[1], UInt<1>(0h0) connect _WIRE_3[2], UInt<1>(0h0) connect _WIRE_3[3], UInt<1>(0h0) node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata) node _T_33 = or(doing_reset, doing_clear_u_lo) node _T_34 = not(UInt<4>(0h0)) node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_35 = cat(hi_6, lo_2) node _T_36 = mux(_T_33, _T_34, _T_35) node _T_37 = bits(_T_36, 0, 0) node _T_38 = bits(_T_36, 1, 1) node _T_39 = bits(_T_36, 2, 2) node _T_40 = bits(_T_36, 3, 3) node _T_41 = bits(_T_30, 7, 0) write mport MPORT_2 = lo_us[_T_41], clock when _T_37 : connect MPORT_2[0], _T_32[0] when _T_38 : connect MPORT_2[1], _T_32[1] when _T_39 : connect MPORT_2[2], _T_32[2] when _T_40 : connect MPORT_2[3], _T_32[3] reg wrbypass_tags : UInt<8>[2], clock reg wrbypass_idxs : UInt<8>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1) connect update_hi_wdata[0], _update_hi_wdata_0_T node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0) connect update_lo_wdata[0], _update_lo_wdata_0_T node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1) connect update_hi_wdata[1], _update_hi_wdata_1_T node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0) connect update_lo_wdata[1], _update_lo_wdata_1_T node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1) connect update_hi_wdata[2], _update_hi_wdata_2_T node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0) connect update_lo_wdata[2], _update_lo_wdata_2_T node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1) connect update_hi_wdata[3], _update_hi_wdata_3_T node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0) connect update_lo_wdata[3], _update_lo_wdata_3_T node _T_42 = or(io.update_mask[0], io.update_mask[1]) node _T_43 = or(_T_42, io.update_mask[2]) node _T_44 = or(_T_43, io.update_mask[3]) when _T_44 : node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_45 : wire _WIRE_4 : UInt<3>[4] connect _WIRE_4[0], update_wdata[0].ctr connect _WIRE_4[1], update_wdata[1].ctr connect _WIRE_4[2], update_wdata[2].ctr connect _WIRE_4[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_4 else : wire _WIRE_5 : UInt<3>[4] connect _WIRE_5[0], update_wdata[0].ctr connect _WIRE_5[1], update_wdata[1].ctr connect _WIRE_5[2], update_wdata[2].ctr connect _WIRE_5[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_5 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2	module TageTable_3( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [11:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [47:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [7:0] reset_idx; // @[tage.scala:73:26] wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26] wire [7:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:162:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:162:35] wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [7:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [7:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [7:0] tag_history = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}] wire [11:0] _s2_req_rtage_WIRE_2 = _table_R0_data[11:0]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_4 = _table_R0_data[23:12]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_6 = _table_R0_data[35:24]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_8 = _table_R0_data[47:36]; // @[tage.scala:91:27, :97:87] reg [7:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [19:0] clear_u_ctr; // @[tage.scala:109:28] wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85] wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33] wire [7:0] idx_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_1 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:162:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:162:35] wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] tag_history_1 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}] wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [8:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 12'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 12'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 12'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 12'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset \| doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset \| doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [7:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [7:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [7:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [7:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 \| io_update_mask_1_0 \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 8'h0; // @[tage.scala:73:26] clear_u_ctr <= 20'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 \| wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 \| _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_2 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_2 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_2 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_1 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_1 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut	module DivSqrtRecFMToRaw_small_e5_s11_1( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_1 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_3 : output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 63, 52) node _rawA_isZero_T = bits(rawA_exp, 11, 9) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 64, 64) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 63, 52) node _rawB_isZero_T = bits(rawB_exp, 11, 9) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 64, 64) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 51, 51) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 51, 51) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T	module CompareRecFN_3( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7] wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt_0; // @[CompareRecFN.scala:42:7] wire io_eq_0; // @[CompareRecFN.scala:42:7] wire io_gt; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}] wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T \| _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_7 \| _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_2 \| _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_1 = bothInfs \| common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros \| _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}] wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_2 \| _invalid_T_5; // @[common.scala:82:46] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}] wire invalid = _invalid_T_6 \| _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7] assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_74 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_148 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_149 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_74( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 \| _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 \| _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 \| _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 \| _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 \| _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 \| _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 \| _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 \| _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 \| _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 \| _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 \| _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 \| _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 \| _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 \| _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 \| _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 \| _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 \| _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 \| _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 \| _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 \| _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 \| _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 \| _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 \| _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 \| _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 \| _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 \| _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 \| _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 \| _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 \| _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a12d64s9k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a12d64s9k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [8:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [11:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [8:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [11:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [8:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [11:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [8:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [11:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [8:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [11:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [8:0] saved_source; // @[Repeater.scala:21:18] reg [11:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SystemBus_1 : output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, system_bus_xbar_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip csbus0_clock_groups_in : { member : { csbus0_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst csbus0_clock_groups of ClockGroupAggregator_csbus0 inst clockGroup of ClockGroup_6 inst fixedClockNode of FixedClockBroadcast_7_1 inst broadcast of BundleBridgeNexus_NoOutput_6 inst system_bus_xbar of TLXbar_csbus0_i4_o1_a32d64s4k3z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer_5 connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_csbus0_from_rockettile connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset inst coupler_from_rockettile_1 of TLInterconnectCoupler_csbus0_from_rockettile_1 connect coupler_from_rockettile_1.clock, childClock connect coupler_from_rockettile_1.reset, childReset inst coupler_from_rockettile_2 of TLInterconnectCoupler_csbus0_from_rockettile_2 connect coupler_from_rockettile_2.clock, childClock connect coupler_from_rockettile_2.reset, childReset inst coupler_from_rockettile_3 of TLInterconnectCoupler_csbus0_from_rockettile_3 connect coupler_from_rockettile_3.clock, childClock connect coupler_from_rockettile_3.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, csbus0_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2 connect system_bus_xbar.auto.anon_in_3, fixer.auto.anon_out_3 connect fixer.auto.anon_in_0, coupler_from_rockettile.auto.tl_out connect fixer.auto.anon_in_1, coupler_from_rockettile_1.auto.tl_out connect fixer.auto.anon_in_2, coupler_from_rockettile_2.auto.tl_out connect fixer.auto.anon_in_3, coupler_from_rockettile_3.auto.tl_out connect csbus0_clock_groups.auto.in, auto.csbus0_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5 connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6 connect auto.system_bus_xbar_anon_out.e.bits, system_bus_xbar.auto.anon_out.e.bits connect auto.system_bus_xbar_anon_out.e.valid, system_bus_xbar.auto.anon_out.e.valid connect system_bus_xbar.auto.anon_out.e.ready, auto.system_bus_xbar_anon_out.e.ready connect system_bus_xbar.auto.anon_out.d, auto.system_bus_xbar_anon_out.d connect auto.system_bus_xbar_anon_out.c.bits, system_bus_xbar.auto.anon_out.c.bits connect auto.system_bus_xbar_anon_out.c.valid, system_bus_xbar.auto.anon_out.c.valid connect system_bus_xbar.auto.anon_out.c.ready, auto.system_bus_xbar_anon_out.c.ready connect system_bus_xbar.auto.anon_out.b, auto.system_bus_xbar_anon_out.b connect auto.system_bus_xbar_anon_out.a.bits, system_bus_xbar.auto.anon_out.a.bits connect auto.system_bus_xbar_anon_out.a.valid, system_bus_xbar.auto.anon_out.a.valid connect system_bus_xbar.auto.anon_out.a.ready, auto.system_bus_xbar_anon_out.a.ready connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_0 connect coupler_from_rockettile_1.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_1 connect coupler_from_rockettile_2.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_2 connect coupler_from_rockettile_3.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_3 connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module SystemBus_1( // @[ClockDomain.scala:14:9] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_system_bus_xbar_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_system_bus_xbar_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_system_bus_xbar_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_system_bus_xbar_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_system_bus_xbar_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_system_bus_xbar_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_system_bus_xbar_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_system_bus_xbar_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_system_bus_xbar_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_system_bus_xbar_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_system_bus_xbar_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_csbus0_clock_groups_in_member_csbus0_0_clock, // @[LazyModuleImp.scala:107:25] input auto_csbus0_clock_groups_in_member_csbus0_0_reset // @[LazyModuleImp.scala:107:25] ); wire fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire csbus0_clock_groups_auto_out_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_auto_out_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_ready_0 = auto_system_bus_xbar_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_valid_0 = auto_system_bus_xbar_anon_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode_0 = auto_system_bus_xbar_anon_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_system_bus_xbar_anon_out_b_bits_param_0 = auto_system_bus_xbar_anon_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_b_bits_size_0 = auto_system_bus_xbar_anon_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_b_bits_source_0 = auto_system_bus_xbar_anon_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_b_bits_address_0 = auto_system_bus_xbar_anon_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_system_bus_xbar_anon_out_b_bits_mask_0 = auto_system_bus_xbar_anon_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_b_bits_data_0 = auto_system_bus_xbar_anon_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_bits_corrupt_0 = auto_system_bus_xbar_anon_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_ready_0 = auto_system_bus_xbar_anon_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_valid_0 = auto_system_bus_xbar_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode_0 = auto_system_bus_xbar_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_system_bus_xbar_anon_out_d_bits_param_0 = auto_system_bus_xbar_anon_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_d_bits_size_0 = auto_system_bus_xbar_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_d_bits_source_0 = auto_system_bus_xbar_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_d_bits_sink_0 = auto_system_bus_xbar_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_bits_denied_0 = auto_system_bus_xbar_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_d_bits_data_0 = auto_system_bus_xbar_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_bits_corrupt_0 = auto_system_bus_xbar_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_e_ready_0 = auto_system_bus_xbar_anon_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_csbus0_clock_groups_in_member_csbus0_0_clock_0 = auto_csbus0_clock_groups_in_member_csbus0_0_clock; // @[ClockDomain.scala:14:9] wire auto_csbus0_clock_groups_in_member_csbus0_0_reset_0 = auto_csbus0_clock_groups_in_member_csbus0_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] fixer__allIDs_FIFOed_T = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_1 = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_2 = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_3 = 3'h7; // @[FIFOFixer.scala:127:48] wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_14 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_6 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_7 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_6 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_7 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_19 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_9 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_10 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_9 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_10 = 1'h1; // @[FIFOFixer.scala:96:47] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire csbus0_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire csbus0_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire csbus0_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_90 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_2 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_2_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_121 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_3 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_3_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_18 = 33'h0; // @[Parameters.scala:137:46] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire csbus0_clock_groups_auto_in_member_csbus0_0_clock = auto_csbus0_clock_groups_in_member_csbus0_0_clock_0; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_auto_in_member_csbus0_0_reset = auto_csbus0_clock_groups_in_member_csbus0_0_reset_0; // @[ClockGroup.scala:53:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire csbus0_clock_groups_nodeIn_member_csbus0_0_clock = csbus0_clock_groups_auto_in_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_nodeOut_member_csbus0_0_clock; // @[MixedNode.scala:542:17] wire csbus0_clock_groups_nodeIn_member_csbus0_0_reset = csbus0_clock_groups_auto_in_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_nodeOut_member_csbus0_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_csbus0_0_clock = csbus0_clock_groups_auto_out_member_csbus0_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_csbus0_0_reset = csbus0_clock_groups_auto_out_member_csbus0_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign csbus0_clock_groups_auto_out_member_csbus0_0_clock = csbus0_clock_groups_nodeOut_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] assign csbus0_clock_groups_auto_out_member_csbus0_0_reset = csbus0_clock_groups_nodeOut_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] assign csbus0_clock_groups_nodeOut_member_csbus0_0_clock = csbus0_clock_groups_nodeIn_member_csbus0_0_clock; // @[MixedNode.scala:542:17, :551:17] assign csbus0_clock_groups_nodeOut_member_csbus0_0_reset = csbus0_clock_groups_nodeIn_member_csbus0_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_csbus0_0_clock = clockGroup_auto_in_member_csbus0_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_csbus0_0_reset = clockGroup_auto_in_member_csbus0_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_csbus0_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_csbus0_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_x1_anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_a_ready = fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_a_valid = fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_a_bits_opcode = fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_a_bits_param = fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_2_a_bits_size = fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_2_a_bits_source = fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_2_a_bits_address = fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_2_a_bits_mask = fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_2_a_bits_data = fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_a_bits_corrupt = fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_b_ready = fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_b_valid = fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_2_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_param = fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_auto_tl_out_b_bits_size = fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_source = fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_2_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_auto_tl_out_b_bits_address = fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_2_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_3_auto_tl_out_b_bits_mask = fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_auto_tl_out_b_bits_data = fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_ready = fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_c_valid = fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_c_bits_opcode = fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_c_bits_param = fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_2_c_bits_size = fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_2_c_bits_source = fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_2_c_bits_address = fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_2_c_bits_data = fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_c_bits_corrupt = fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_d_ready = fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_valid = fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_param = fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_auto_tl_out_d_bits_size = fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_source = fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_sink = fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_bits_denied = fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_auto_tl_out_d_bits_data = fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_e_ready = fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_e_valid = fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_e_bits_sink = fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_ready = fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_valid = fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_opcode = fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_param = fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_a_bits_size = fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_a_bits_source = fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_a_bits_address = fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_1_a_bits_mask = fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_1_a_bits_data = fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_bits_corrupt = fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_b_ready = fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_b_valid = fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_param = fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_auto_tl_out_b_bits_size = fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_source = fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_1_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_auto_tl_out_b_bits_address = fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_1_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_2_auto_tl_out_b_bits_mask = fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_auto_tl_out_b_bits_data = fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_ready = fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_valid = fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_opcode = fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_param = fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_c_bits_size = fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_c_bits_source = fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_c_bits_address = fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_1_c_bits_data = fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_bits_corrupt = fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_d_ready = fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_valid = fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_param = fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_auto_tl_out_d_bits_size = fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_source = fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_sink = fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_bits_denied = fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_auto_tl_out_d_bits_data = fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_e_ready = fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_e_valid = fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_e_bits_sink = fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_b_ready = fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_b_valid = fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_param = fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_auto_tl_out_b_bits_size = fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_source = fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_auto_tl_out_b_bits_address = fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_1_auto_tl_out_b_bits_mask = fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_auto_tl_out_b_bits_data = fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_ready = fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_valid = fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_opcode = fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_param = fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_c_bits_size = fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_c_bits_source = fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_c_bits_address = fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_c_bits_data = fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_bits_corrupt = fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_e_ready = fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_e_valid = fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_e_bits_sink = fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_ready = fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_b_ready = fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_b_valid = fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_param = fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_b_bits_size = fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_source = fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_auto_tl_out_b_bits_address = fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_auto_tl_out_b_bits_mask = fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_auto_tl_out_b_bits_data = fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_ready = fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_c_valid = fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_c_bits_opcode = fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_c_bits_param = fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_anonIn_c_bits_size = fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_anonIn_c_bits_source = fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_anonIn_c_bits_address = fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_anonIn_c_bits_data = fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_c_bits_corrupt = fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_valid = fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_param = fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_d_bits_size = fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_source = fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_auto_tl_out_d_bits_data = fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_e_ready = fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_e_valid = fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_e_bits_sink = fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_a_ready = fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_b_valid = fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_b_bits_opcode = fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_b_bits_param = fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_2_b_bits_size = fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_b_bits_source = fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_2_b_bits_address = fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_2_b_bits_mask = fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_2_b_bits_data = fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_b_bits_corrupt = fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_c_ready = fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_2_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_2_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_2_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_2_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_d_valid = fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_d_bits_opcode = fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_d_bits_param = fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_2_d_bits_size = fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_d_bits_source = fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_d_bits_sink = fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_d_bits_denied = fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_2_d_bits_data = fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_d_bits_corrupt = fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_e_ready = fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_a_ready = fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_valid = fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_b_bits_opcode = fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_param = fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_b_bits_size = fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_source = fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_1_b_bits_address = fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_1_b_bits_mask = fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_1_b_bits_data = fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_b_bits_corrupt = fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_ready = fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_valid = fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_d_bits_opcode = fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_param = fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_d_bits_size = fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_source = fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_d_bits_sink = fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_denied = fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_1_d_bits_data = fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_corrupt = fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_ready = fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_valid = fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_b_bits_opcode = fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_param = fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_b_bits_size = fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_source = fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_b_bits_address = fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_b_bits_mask = fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_b_bits_data = fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_b_bits_corrupt = fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_ready = fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_ready = fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_b_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_b_valid = fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_b_bits_opcode = fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_b_bits_param = fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_b_bits_size = fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_b_bits_source = fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_anonOut_b_bits_address = fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonOut_b_bits_mask = fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_b_bits_data = fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_b_bits_corrupt = fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_c_ready = fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_e_ready = fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] fixer_auto_anon_out_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_e_valid; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_b_ready = fixer_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_b_valid = fixer_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_opcode = fixer_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_param = fixer_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_size = fixer_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_source = fixer_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_address = fixer_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_mask = fixer_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_data = fixer_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_corrupt = fixer_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_c_ready = fixer_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_0_c_valid = fixer_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_opcode = fixer_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_param = fixer_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_size = fixer_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_source = fixer_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_address = fixer_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_data = fixer_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_corrupt = fixer_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_e_ready = fixer_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_0_e_valid = fixer_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_e_bits_sink = fixer_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_b_ready = fixer_x1_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_b_valid = fixer_x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_opcode = fixer_x1_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_param = fixer_x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_size = fixer_x1_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_source = fixer_x1_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_address = fixer_x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_mask = fixer_x1_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_data = fixer_x1_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_corrupt = fixer_x1_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_c_ready = fixer_x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_c_valid = fixer_x1_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_opcode = fixer_x1_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_param = fixer_x1_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_size = fixer_x1_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_source = fixer_x1_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_address = fixer_x1_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_data = fixer_x1_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_corrupt = fixer_x1_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_e_ready = fixer_x1_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_e_valid = fixer_x1_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_e_bits_sink = fixer_x1_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_8 = fixer_x1_anonOut_1_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_2_a_valid = fixer_x1_anonOut_1_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_opcode = fixer_x1_anonOut_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_param = fixer_x1_anonOut_1_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_size = fixer_x1_anonOut_1_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_source = fixer_x1_anonOut_1_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_address = fixer_x1_anonOut_1_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_mask = fixer_x1_anonOut_1_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_data = fixer_x1_anonOut_1_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_corrupt = fixer_x1_anonOut_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_b_ready = fixer_x1_anonOut_1_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_b_valid = fixer_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_opcode = fixer_x1_anonOut_1_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_param = fixer_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_size = fixer_x1_anonOut_1_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_source = fixer_x1_anonOut_1_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_address = fixer_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_mask = fixer_x1_anonOut_1_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_data = fixer_x1_anonOut_1_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_corrupt = fixer_x1_anonOut_1_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_c_ready = fixer_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_c_valid = fixer_x1_anonOut_1_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_opcode = fixer_x1_anonOut_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_param = fixer_x1_anonOut_1_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_size = fixer_x1_anonOut_1_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_source = fixer_x1_anonOut_1_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_address = fixer_x1_anonOut_1_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_data = fixer_x1_anonOut_1_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_corrupt = fixer_x1_anonOut_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_d_ready = fixer_x1_anonOut_1_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_d_valid = fixer_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_opcode = fixer_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_param = fixer_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_size = fixer_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_source = fixer_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_sink = fixer_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_denied = fixer_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_data = fixer_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_corrupt = fixer_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_e_ready = fixer_x1_anonOut_1_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_e_valid = fixer_x1_anonOut_1_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_e_bits_sink = fixer_x1_anonOut_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_11 = fixer_x1_anonOut_2_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_3_a_valid = fixer_x1_anonOut_2_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_opcode = fixer_x1_anonOut_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_param = fixer_x1_anonOut_2_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_size = fixer_x1_anonOut_2_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_source = fixer_x1_anonOut_2_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_address = fixer_x1_anonOut_2_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_mask = fixer_x1_anonOut_2_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_data = fixer_x1_anonOut_2_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_corrupt = fixer_x1_anonOut_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_b_ready = fixer_x1_anonOut_2_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_2_b_valid = fixer_x1_anonOut_2_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_opcode = fixer_x1_anonOut_2_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_param = fixer_x1_anonOut_2_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_size = fixer_x1_anonOut_2_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_source = fixer_x1_anonOut_2_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_address = fixer_x1_anonOut_2_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_mask = fixer_x1_anonOut_2_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_data = fixer_x1_anonOut_2_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_corrupt = fixer_x1_anonOut_2_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_c_ready = fixer_x1_anonOut_2_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_3_c_valid = fixer_x1_anonOut_2_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_opcode = fixer_x1_anonOut_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_param = fixer_x1_anonOut_2_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_size = fixer_x1_anonOut_2_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_source = fixer_x1_anonOut_2_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_address = fixer_x1_anonOut_2_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_data = fixer_x1_anonOut_2_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_corrupt = fixer_x1_anonOut_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_d_ready = fixer_x1_anonOut_2_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_2_d_valid = fixer_x1_anonOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_opcode = fixer_x1_anonOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_param = fixer_x1_anonOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_size = fixer_x1_anonOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_source = fixer_x1_anonOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_sink = fixer_x1_anonOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_denied = fixer_x1_anonOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_data = fixer_x1_anonOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_corrupt = fixer_x1_anonOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_e_ready = fixer_x1_anonOut_2_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_3_e_valid = fixer_x1_anonOut_2_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_e_bits_sink = fixer_x1_anonOut_2_e_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_b_ready = fixer_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_b_valid = fixer_anonIn_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_opcode = fixer_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_param = fixer_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_size = fixer_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_source = fixer_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_address = fixer_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_mask = fixer_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_data = fixer_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_corrupt = fixer_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_c_ready = fixer_anonIn_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonOut_c_valid = fixer_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_opcode = fixer_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_param = fixer_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_size = fixer_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_source = fixer_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_address = fixer_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_data = fixer_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_corrupt = fixer_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_e_ready = fixer_anonIn_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonOut_e_valid = fixer_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_e_bits_sink = fixer_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_b_ready = fixer_x1_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_b_valid = fixer_x1_anonIn_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_opcode = fixer_x1_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_param = fixer_x1_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_size = fixer_x1_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_source = fixer_x1_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_address = fixer_x1_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_mask = fixer_x1_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_data = fixer_x1_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_corrupt = fixer_x1_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_c_ready = fixer_x1_anonIn_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_c_valid = fixer_x1_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_opcode = fixer_x1_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_param = fixer_x1_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_size = fixer_x1_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_source = fixer_x1_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_address = fixer_x1_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_data = fixer_x1_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_corrupt = fixer_x1_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_e_ready = fixer_x1_anonIn_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_e_valid = fixer_x1_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_e_bits_sink = fixer_x1_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_a_ready = fixer_x1_anonIn_1_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_8 = fixer_x1_anonIn_1_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_1_a_bits_opcode = fixer_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_param = fixer_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_size = fixer_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_source = fixer_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_address = fixer_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_62 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_10 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_1_a_bits_mask = fixer_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_data = fixer_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_corrupt = fixer_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_b_ready = fixer_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_b_valid = fixer_x1_anonIn_1_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_opcode = fixer_x1_anonIn_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_param = fixer_x1_anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_size = fixer_x1_anonIn_1_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_source = fixer_x1_anonIn_1_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_address = fixer_x1_anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_mask = fixer_x1_anonIn_1_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_data = fixer_x1_anonIn_1_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_corrupt = fixer_x1_anonIn_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_c_ready = fixer_x1_anonIn_1_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_c_valid = fixer_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_opcode = fixer_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_param = fixer_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_size = fixer_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_source = fixer_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_address = fixer_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_data = fixer_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_corrupt = fixer_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_d_ready = fixer_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_d_valid = fixer_x1_anonIn_1_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_opcode = fixer_x1_anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_param = fixer_x1_anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_size = fixer_x1_anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_source = fixer_x1_anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_sink = fixer_x1_anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_denied = fixer_x1_anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_data = fixer_x1_anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_corrupt = fixer_x1_anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_e_ready = fixer_x1_anonIn_1_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_e_valid = fixer_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_e_bits_sink = fixer_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_a_ready = fixer_x1_anonIn_2_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_11 = fixer_x1_anonIn_2_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_2_a_bits_opcode = fixer_x1_anonIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_param = fixer_x1_anonIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_size = fixer_x1_anonIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_source = fixer_x1_anonIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_address = fixer_x1_anonIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_93 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_15 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_2_a_bits_mask = fixer_x1_anonIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_data = fixer_x1_anonIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_corrupt = fixer_x1_anonIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_b_ready = fixer_x1_anonIn_2_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_b_valid = fixer_x1_anonIn_2_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_opcode = fixer_x1_anonIn_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_param = fixer_x1_anonIn_2_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_size = fixer_x1_anonIn_2_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_source = fixer_x1_anonIn_2_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_address = fixer_x1_anonIn_2_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_mask = fixer_x1_anonIn_2_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_data = fixer_x1_anonIn_2_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_corrupt = fixer_x1_anonIn_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_c_ready = fixer_x1_anonIn_2_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_2_c_valid = fixer_x1_anonIn_2_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_opcode = fixer_x1_anonIn_2_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_param = fixer_x1_anonIn_2_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_size = fixer_x1_anonIn_2_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_source = fixer_x1_anonIn_2_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_address = fixer_x1_anonIn_2_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_data = fixer_x1_anonIn_2_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_corrupt = fixer_x1_anonIn_2_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_d_ready = fixer_x1_anonIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_d_valid = fixer_x1_anonIn_2_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_opcode = fixer_x1_anonIn_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_param = fixer_x1_anonIn_2_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_size = fixer_x1_anonIn_2_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_source = fixer_x1_anonIn_2_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_sink = fixer_x1_anonIn_2_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_denied = fixer_x1_anonIn_2_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_data = fixer_x1_anonIn_2_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_corrupt = fixer_x1_anonIn_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_e_ready = fixer_x1_anonIn_2_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_2_e_valid = fixer_x1_anonIn_2_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_e_bits_sink = fixer_x1_anonIn_2_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 \| fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 \| fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 \| fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73] wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T \| fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T \| fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T = 4'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T = 4'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed \| fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 \| fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 \| fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 \| fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73] wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_1 = fixer_a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_1 = fixer__a_first_last_T_2 \| fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_1 = fixer__d_first_last_T_2 \| fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73] wire fixer__T_18 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_1 = 4'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_1 = 4'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_18 ? fixer__SourceIdClear_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 \| fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_63 = {1'h0, fixer__a_notFIFO_T_62}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_64 = fixer__a_notFIFO_T_63 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_66 = fixer__a_notFIFO_T_65 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_67 = {fixer_x1_anonIn_1_a_bits_address[31:17], fixer_x1_anonIn_1_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_68 = {1'h0, fixer__a_notFIFO_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_72 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_73 = {1'h0, fixer__a_notFIFO_T_72}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_75 = fixer__a_notFIFO_T_74; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_76 = fixer__a_notFIFO_T_75 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_77 = fixer__a_notFIFO_T_66 \| fixer__a_notFIFO_T_71; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_78 = fixer__a_notFIFO_T_77 \| fixer__a_notFIFO_T_76; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_79 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_80 = {1'h0, fixer__a_notFIFO_T_79}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_81 = fixer__a_notFIFO_T_80 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_82 = fixer__a_notFIFO_T_81; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_83 = fixer__a_notFIFO_T_82 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_84 = fixer_x1_anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_85 = {1'h0, fixer__a_notFIFO_T_84}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_86 = fixer__a_notFIFO_T_85 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_87 = fixer__a_notFIFO_T_86; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_88 = fixer__a_notFIFO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_89 = fixer__a_notFIFO_T_83 \| fixer__a_notFIFO_T_88; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_91 = fixer__a_notFIFO_T_89; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_92 = fixer__a_notFIFO_T_91; // @[Mux.scala:30:73] wire fixer_a_notFIFO_2 = fixer__a_notFIFO_T_92; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_2 = fixer_x1_anonIn_1_a_ready & fixer_x1_anonIn_1_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonIn_1_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_7 = fixer__a_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_8 = ~fixer__a_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_2 = fixer__a_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_2 = fixer_x1_anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_2 = ~fixer__a_first_beats1_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_2 = fixer_a_first_beats1_opdata_2 ? fixer_a_first_beats1_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_2; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_2 = {1'h0, fixer_a_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_2 = fixer__a_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_2 = fixer_a_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_4 = fixer_a_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_5 = fixer_a_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_2 = fixer__a_first_last_T_4 \| fixer__a_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_2 = fixer_a_first_last_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_2 = ~fixer_a_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_2 = fixer_a_first_beats1_2 & fixer__a_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_2 = fixer_a_first_2 ? fixer_a_first_beats1_2 : fixer_a_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_4 = fixer_x1_anonOut_1_d_ready & fixer_x1_anonOut_1_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonOut_1_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_7 = fixer__d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_8 = ~fixer__d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_2 = fixer__d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_2 = fixer_x1_anonOut_1_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_2 = fixer_d_first_beats1_opdata_2 ? fixer_d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_2 = {1'h0, fixer_d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_2 = fixer__d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_2 = fixer_d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_4 = fixer_d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_5 = fixer_d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_2 = fixer__d_first_last_T_4 \| fixer__d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_2 = fixer_d_first_last_2 & fixer__d_first_T_4; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_2 = ~fixer_d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_2 = fixer_d_first_beats1_2 & fixer__d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_2 = fixer_d_first_first_2 ? fixer_d_first_beats1_2 : fixer_d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_5 = fixer_x1_anonOut_1_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_2 = fixer_d_first_first_2 & fixer__d_first_T_5; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_2_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_2 = ~fixer_a_notFIFO_2; // @[Mux.scala:30:73] wire fixer__T_34 = fixer_x1_anonIn_1_d_ready & fixer_x1_anonIn_1_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_1_a_valid = fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_1_a_ready = fixer__anonIn_a_ready_T_8; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_2; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_2; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_2 = 4'h1 << fixer_x1_anonIn_1_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_2 = fixer_a_first_2 & fixer__a_first_T_2 & ~fixer_a_notFIFO_2 ? fixer__SourceIdSet_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_2 = 4'h1 << fixer_x1_anonIn_1_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_2 = fixer_d_first_2 & fixer__T_34 ? fixer__SourceIdClear_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_2 = fixer_SourceIdFIFOed_2 \| fixer_SourceIdSet_2; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_2 = &fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_94 = {1'h0, fixer__a_notFIFO_T_93}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_95 = fixer__a_notFIFO_T_94 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_96 = fixer__a_notFIFO_T_95; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_97 = fixer__a_notFIFO_T_96 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_98 = {fixer_x1_anonIn_2_a_bits_address[31:17], fixer_x1_anonIn_2_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_99 = {1'h0, fixer__a_notFIFO_T_98}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_100 = fixer__a_notFIFO_T_99 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_101 = fixer__a_notFIFO_T_100; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_102 = fixer__a_notFIFO_T_101 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_103 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_104 = {1'h0, fixer__a_notFIFO_T_103}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_105 = fixer__a_notFIFO_T_104 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_106 = fixer__a_notFIFO_T_105; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_107 = fixer__a_notFIFO_T_106 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_108 = fixer__a_notFIFO_T_97 \| fixer__a_notFIFO_T_102; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_109 = fixer__a_notFIFO_T_108 \| fixer__a_notFIFO_T_107; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_110 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_111 = {1'h0, fixer__a_notFIFO_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_112 = fixer__a_notFIFO_T_111 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_113 = fixer__a_notFIFO_T_112; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_114 = fixer__a_notFIFO_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_115 = fixer_x1_anonIn_2_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_116 = {1'h0, fixer__a_notFIFO_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_117 = fixer__a_notFIFO_T_116 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_118 = fixer__a_notFIFO_T_117; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_119 = fixer__a_notFIFO_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_120 = fixer__a_notFIFO_T_114 \| fixer__a_notFIFO_T_119; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_122 = fixer__a_notFIFO_T_120; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_123 = fixer__a_notFIFO_T_122; // @[Mux.scala:30:73] wire fixer_a_notFIFO_3 = fixer__a_notFIFO_T_123; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_16 = {1'h0, fixer__a_id_T_15}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_3 = fixer_x1_anonIn_2_a_ready & fixer_x1_anonIn_2_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonIn_2_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_10 = fixer__a_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_11 = ~fixer__a_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_3 = fixer__a_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_3 = fixer_x1_anonIn_2_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_3 = ~fixer__a_first_beats1_opdata_T_3; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_3 = fixer_a_first_beats1_opdata_3 ? fixer_a_first_beats1_decode_3 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_3; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_3 = {1'h0, fixer_a_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_3 = fixer__a_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_3 = fixer_a_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_6 = fixer_a_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_7 = fixer_a_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_3 = fixer__a_first_last_T_6 \| fixer__a_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_3 = fixer_a_first_last_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_3 = ~fixer_a_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_3 = fixer_a_first_beats1_3 & fixer__a_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_3 = fixer_a_first_3 ? fixer_a_first_beats1_3 : fixer_a_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_6 = fixer_x1_anonOut_2_d_ready & fixer_x1_anonOut_2_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonOut_2_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_10 = fixer__d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_11 = ~fixer__d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_3 = fixer__d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_3 = fixer_x1_anonOut_2_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_3 = fixer_d_first_beats1_opdata_3 ? fixer_d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_3 = {1'h0, fixer_d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_3 = fixer__d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_3 = fixer_d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_6 = fixer_d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_7 = fixer_d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_3 = fixer__d_first_last_T_6 \| fixer__d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_3 = fixer_d_first_last_3 & fixer__d_first_T_6; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_3 = ~fixer_d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_3 = fixer_d_first_beats1_3 & fixer__d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_3 = fixer_d_first_first_3 ? fixer_d_first_beats1_3 : fixer_d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_7 = fixer_x1_anonOut_2_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_3 = fixer_d_first_first_3 & fixer__d_first_T_7; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_3_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_3_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_3_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_3 = ~fixer_a_notFIFO_3; // @[Mux.scala:30:73] wire fixer__T_50 = fixer_x1_anonIn_2_d_ready & fixer_x1_anonIn_2_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_2_a_valid = fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_2_a_ready = fixer__anonIn_a_ready_T_11; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_3; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_3; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_3 = 4'h1 << fixer_x1_anonIn_2_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_3 = fixer_a_first_3 & fixer__a_first_T_3 & ~fixer_a_notFIFO_3 ? fixer__SourceIdSet_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_3 = 4'h1 << fixer_x1_anonIn_2_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_3 = fixer_d_first_3 & fixer__T_50 ? fixer__SourceIdClear_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_3 = fixer_SourceIdFIFOed_3 \| fixer_SourceIdSet_3; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_3 = &fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35, :127:41] wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_b_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_c_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_e_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_valid = coupler_from_rockettile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_opcode = coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_param = coupler_from_rockettile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_size = coupler_from_rockettile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_source = coupler_from_rockettile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_address = coupler_from_rockettile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_mask = coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_data = coupler_from_rockettile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_b_ready = coupler_from_rockettile_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_b_valid = coupler_from_rockettile_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_b_bits_opcode = coupler_from_rockettile_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_b_bits_param = coupler_from_rockettile_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlOut_b_bits_size = coupler_from_rockettile_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_b_bits_source = coupler_from_rockettile_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlOut_b_bits_address = coupler_from_rockettile_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_tlOut_b_bits_mask = coupler_from_rockettile_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlOut_b_bits_data = coupler_from_rockettile_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_b_bits_corrupt = coupler_from_rockettile_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_c_ready = coupler_from_rockettile_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_valid = coupler_from_rockettile_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_opcode = coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_param = coupler_from_rockettile_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_size = coupler_from_rockettile_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_source = coupler_from_rockettile_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_address = coupler_from_rockettile_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_data = coupler_from_rockettile_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_corrupt = coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_d_ready = coupler_from_rockettile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_e_ready = coupler_from_rockettile_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_e_valid = coupler_from_rockettile_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_e_bits_sink = coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_b_ready = coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_b_valid = coupler_from_rockettile_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_b_bits_opcode = coupler_from_rockettile_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_b_bits_param = coupler_from_rockettile_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlIn_b_bits_size = coupler_from_rockettile_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_b_bits_source = coupler_from_rockettile_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlIn_b_bits_address = coupler_from_rockettile_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlIn_b_bits_mask = coupler_from_rockettile_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlIn_b_bits_data = coupler_from_rockettile_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_b_bits_corrupt = coupler_from_rockettile_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_c_ready = coupler_from_rockettile_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_valid = coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_opcode = coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_param = coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_size = coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_source = coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_address = coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_data = coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_e_ready = coupler_from_rockettile_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_e_valid = coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_e_bits_sink = coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_b_ready = coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_valid = coupler_from_rockettile_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_b_bits_opcode = coupler_from_rockettile_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_param = coupler_from_rockettile_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_b_bits_size = coupler_from_rockettile_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_source = coupler_from_rockettile_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_b_bits_address = coupler_from_rockettile_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferOut_b_bits_mask = coupler_from_rockettile_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_b_bits_data = coupler_from_rockettile_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_ready = coupler_from_rockettile_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_valid = coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_opcode = coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_param = coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_size = coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_source = coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_address = coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_data = coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_corrupt = coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_e_ready = coupler_from_rockettile_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_e_valid = coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_e_bits_sink = coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_b_ready = coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_valid = coupler_from_rockettile_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_b_bits_opcode = coupler_from_rockettile_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_param = coupler_from_rockettile_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_b_bits_size = coupler_from_rockettile_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_source = coupler_from_rockettile_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_b_bits_address = coupler_from_rockettile_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferIn_b_bits_mask = coupler_from_rockettile_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_b_bits_data = coupler_from_rockettile_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_ready = coupler_from_rockettile_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_valid = coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_opcode = coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_param = coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_size = coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_source = coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_address = coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_data = coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_corrupt = coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_e_ready = coupler_from_rockettile_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_e_valid = coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_e_bits_sink = coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_b_ready = coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_valid = coupler_from_rockettile_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_ready = coupler_from_rockettile_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_valid = coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_opcode = coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_param = coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_size = coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_source = coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_address = coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_data = coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_e_ready = coupler_from_rockettile_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_e_valid = coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_e_bits_sink = coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_b_ready = coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_valid = coupler_from_rockettile_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_c_ready = coupler_from_rockettile_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_valid = coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_param = coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_size = coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_source = coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_address = coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_data = coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_e_ready = coupler_from_rockettile_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_e_valid = coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_e_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_b_ready = coupler_from_rockettile_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_valid = coupler_from_rockettile_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_e_valid = coupler_from_rockettile_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_e_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlOut_a_ready = coupler_from_rockettile_1_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_1_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_b_ready = coupler_from_rockettile_1_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_b_valid = coupler_from_rockettile_1_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_b_bits_opcode = coupler_from_rockettile_1_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_param = coupler_from_rockettile_1_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlOut_b_bits_size = coupler_from_rockettile_1_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_source = coupler_from_rockettile_1_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlOut_b_bits_address = coupler_from_rockettile_1_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_1_tlOut_b_bits_mask = coupler_from_rockettile_1_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlOut_b_bits_data = coupler_from_rockettile_1_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_b_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_c_ready = coupler_from_rockettile_1_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_valid = coupler_from_rockettile_1_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_opcode = coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_param = coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_size = coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_source = coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_address = coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_data = coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_1_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_d_valid = coupler_from_rockettile_1_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_opcode = coupler_from_rockettile_1_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_param = coupler_from_rockettile_1_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlOut_d_bits_size = coupler_from_rockettile_1_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_source = coupler_from_rockettile_1_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_sink = coupler_from_rockettile_1_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_d_bits_denied = coupler_from_rockettile_1_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlOut_d_bits_data = coupler_from_rockettile_1_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_d_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_e_ready = coupler_from_rockettile_1_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_valid = coupler_from_rockettile_1_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_bits_sink = coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlIn_a_ready = coupler_from_rockettile_1_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_valid = coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_opcode = coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_param = coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_size = coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_source = coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_address = coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_mask = coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_data = coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_b_ready = coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_b_valid = coupler_from_rockettile_1_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_b_bits_opcode = coupler_from_rockettile_1_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_param = coupler_from_rockettile_1_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlIn_b_bits_size = coupler_from_rockettile_1_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_source = coupler_from_rockettile_1_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlIn_b_bits_address = coupler_from_rockettile_1_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlIn_b_bits_mask = coupler_from_rockettile_1_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlIn_b_bits_data = coupler_from_rockettile_1_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_b_bits_corrupt = coupler_from_rockettile_1_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_c_ready = coupler_from_rockettile_1_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_valid = coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_opcode = coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_param = coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_size = coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_source = coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_address = coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_data = coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_d_ready = coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_d_valid = coupler_from_rockettile_1_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_opcode = coupler_from_rockettile_1_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_param = coupler_from_rockettile_1_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlIn_d_bits_size = coupler_from_rockettile_1_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_source = coupler_from_rockettile_1_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_sink = coupler_from_rockettile_1_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_d_bits_denied = coupler_from_rockettile_1_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlIn_d_bits_data = coupler_from_rockettile_1_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_d_bits_corrupt = coupler_from_rockettile_1_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_e_ready = coupler_from_rockettile_1_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_e_valid = coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_e_bits_sink = coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_no_bufferOut_a_ready = coupler_from_rockettile_1_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_valid = coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_opcode = coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_param = coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_size = coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_source = coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_address = coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_mask = coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_data = coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_corrupt = coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_b_ready = coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_valid = coupler_from_rockettile_1_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_b_bits_opcode = coupler_from_rockettile_1_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_param = coupler_from_rockettile_1_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_b_bits_size = coupler_from_rockettile_1_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_source = coupler_from_rockettile_1_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_b_bits_address = coupler_from_rockettile_1_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferOut_b_bits_mask = coupler_from_rockettile_1_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_b_bits_data = coupler_from_rockettile_1_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_1_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_ready = coupler_from_rockettile_1_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_valid = coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_opcode = coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_param = coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_size = coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_source = coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_address = coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_data = coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_corrupt = coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_d_ready = coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_valid = coupler_from_rockettile_1_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_opcode = coupler_from_rockettile_1_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_param = coupler_from_rockettile_1_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_d_bits_size = coupler_from_rockettile_1_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_source = coupler_from_rockettile_1_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_sink = coupler_from_rockettile_1_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_bits_denied = coupler_from_rockettile_1_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_d_bits_data = coupler_from_rockettile_1_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_1_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_e_ready = coupler_from_rockettile_1_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_e_valid = coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_e_bits_sink = coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_ready = coupler_from_rockettile_1_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_valid = coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_opcode = coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_param = coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_size = coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_source = coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_address = coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_mask = coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_data = coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_b_ready = coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_valid = coupler_from_rockettile_1_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_b_bits_opcode = coupler_from_rockettile_1_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_param = coupler_from_rockettile_1_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_b_bits_size = coupler_from_rockettile_1_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_source = coupler_from_rockettile_1_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_b_bits_address = coupler_from_rockettile_1_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferIn_b_bits_mask = coupler_from_rockettile_1_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_b_bits_data = coupler_from_rockettile_1_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_ready = coupler_from_rockettile_1_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_valid = coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_opcode = coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_param = coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_size = coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_source = coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_address = coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_data = coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_d_ready = coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_valid = coupler_from_rockettile_1_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_opcode = coupler_from_rockettile_1_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_param = coupler_from_rockettile_1_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_d_bits_size = coupler_from_rockettile_1_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_source = coupler_from_rockettile_1_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_sink = coupler_from_rockettile_1_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_bits_denied = coupler_from_rockettile_1_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_d_bits_data = coupler_from_rockettile_1_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_e_ready = coupler_from_rockettile_1_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_e_valid = coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_e_bits_sink = coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_ready = coupler_from_rockettile_1_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_valid = coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_opcode = coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_param = coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_size = coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_source = coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_address = coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_mask = coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_data = coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_b_ready = coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_valid = coupler_from_rockettile_1_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_1_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_1_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_1_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_1_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_1_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_1_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_1_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_ready = coupler_from_rockettile_1_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_valid = coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_opcode = coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_param = coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_size = coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_source = coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_address = coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_data = coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_d_ready = coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_valid = coupler_from_rockettile_1_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_1_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_1_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_1_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_1_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_1_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_1_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_1_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_e_ready = coupler_from_rockettile_1_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_e_valid = coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_e_bits_sink = coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_a_ready = coupler_from_rockettile_1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_valid = coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_b_ready = coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_valid = coupler_from_rockettile_1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_c_ready = coupler_from_rockettile_1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_valid = coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_d_ready = coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_valid = coupler_from_rockettile_1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_e_ready = coupler_from_rockettile_1_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_e_valid = coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_valid = coupler_from_rockettile_1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_b_ready = coupler_from_rockettile_1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_valid = coupler_from_rockettile_1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_d_ready = coupler_from_rockettile_1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_e_valid = coupler_from_rockettile_1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_e_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlOut_a_ready = coupler_from_rockettile_2_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_valid = coupler_from_rockettile_2_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_opcode = coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_param = coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_size = coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_source = coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_address = coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_mask = coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_data = coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_b_ready = coupler_from_rockettile_2_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_b_valid = coupler_from_rockettile_2_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_b_bits_opcode = coupler_from_rockettile_2_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_param = coupler_from_rockettile_2_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlOut_b_bits_size = coupler_from_rockettile_2_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_source = coupler_from_rockettile_2_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlOut_b_bits_address = coupler_from_rockettile_2_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_2_tlOut_b_bits_mask = coupler_from_rockettile_2_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlOut_b_bits_data = coupler_from_rockettile_2_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_b_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_c_ready = coupler_from_rockettile_2_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_valid = coupler_from_rockettile_2_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_opcode = coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_param = coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_size = coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_source = coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_address = coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_data = coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_d_ready = coupler_from_rockettile_2_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_d_valid = coupler_from_rockettile_2_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_opcode = coupler_from_rockettile_2_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_param = coupler_from_rockettile_2_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlOut_d_bits_size = coupler_from_rockettile_2_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_source = coupler_from_rockettile_2_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_sink = coupler_from_rockettile_2_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_d_bits_denied = coupler_from_rockettile_2_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlOut_d_bits_data = coupler_from_rockettile_2_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_d_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_e_ready = coupler_from_rockettile_2_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_valid = coupler_from_rockettile_2_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_bits_sink = coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlIn_a_ready = coupler_from_rockettile_2_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_valid = coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_opcode = coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_param = coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_size = coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_source = coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_address = coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_mask = coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_data = coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_b_ready = coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_b_valid = coupler_from_rockettile_2_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_b_bits_opcode = coupler_from_rockettile_2_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_param = coupler_from_rockettile_2_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlIn_b_bits_size = coupler_from_rockettile_2_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_source = coupler_from_rockettile_2_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlIn_b_bits_address = coupler_from_rockettile_2_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlIn_b_bits_mask = coupler_from_rockettile_2_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlIn_b_bits_data = coupler_from_rockettile_2_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_b_bits_corrupt = coupler_from_rockettile_2_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_c_ready = coupler_from_rockettile_2_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_valid = coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_opcode = coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_param = coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_size = coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_source = coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_address = coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_data = coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_d_ready = coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_d_valid = coupler_from_rockettile_2_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_opcode = coupler_from_rockettile_2_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_param = coupler_from_rockettile_2_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlIn_d_bits_size = coupler_from_rockettile_2_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_source = coupler_from_rockettile_2_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_sink = coupler_from_rockettile_2_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_d_bits_denied = coupler_from_rockettile_2_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlIn_d_bits_data = coupler_from_rockettile_2_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_d_bits_corrupt = coupler_from_rockettile_2_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_e_ready = coupler_from_rockettile_2_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_e_valid = coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_e_bits_sink = coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_no_bufferOut_a_ready = coupler_from_rockettile_2_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_valid = coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_opcode = coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_param = coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_size = coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_source = coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_address = coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_mask = coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_data = coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_corrupt = coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_b_ready = coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_valid = coupler_from_rockettile_2_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_b_bits_opcode = coupler_from_rockettile_2_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_param = coupler_from_rockettile_2_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_b_bits_size = coupler_from_rockettile_2_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_source = coupler_from_rockettile_2_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_b_bits_address = coupler_from_rockettile_2_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferOut_b_bits_mask = coupler_from_rockettile_2_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_b_bits_data = coupler_from_rockettile_2_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_2_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_ready = coupler_from_rockettile_2_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_valid = coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_opcode = coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_param = coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_size = coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_source = coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_address = coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_data = coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_corrupt = coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_d_ready = coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_valid = coupler_from_rockettile_2_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_opcode = coupler_from_rockettile_2_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_param = coupler_from_rockettile_2_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_d_bits_size = coupler_from_rockettile_2_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_source = coupler_from_rockettile_2_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_sink = coupler_from_rockettile_2_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_bits_denied = coupler_from_rockettile_2_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_d_bits_data = coupler_from_rockettile_2_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_2_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_e_ready = coupler_from_rockettile_2_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_e_valid = coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_e_bits_sink = coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_ready = coupler_from_rockettile_2_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_valid = coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_opcode = coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_param = coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_size = coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_source = coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_address = coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_mask = coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_data = coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_b_ready = coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_valid = coupler_from_rockettile_2_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_b_bits_opcode = coupler_from_rockettile_2_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_param = coupler_from_rockettile_2_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_b_bits_size = coupler_from_rockettile_2_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_source = coupler_from_rockettile_2_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_b_bits_address = coupler_from_rockettile_2_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferIn_b_bits_mask = coupler_from_rockettile_2_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_b_bits_data = coupler_from_rockettile_2_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_ready = coupler_from_rockettile_2_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_valid = coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_opcode = coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_param = coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_size = coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_source = coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_address = coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_data = coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_d_ready = coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_valid = coupler_from_rockettile_2_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_opcode = coupler_from_rockettile_2_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_param = coupler_from_rockettile_2_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_d_bits_size = coupler_from_rockettile_2_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_source = coupler_from_rockettile_2_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_sink = coupler_from_rockettile_2_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_bits_denied = coupler_from_rockettile_2_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_d_bits_data = coupler_from_rockettile_2_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_e_ready = coupler_from_rockettile_2_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_e_valid = coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_e_bits_sink = coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_ready = coupler_from_rockettile_2_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_valid = coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_opcode = coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_param = coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_size = coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_source = coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_address = coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_mask = coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_data = coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_b_ready = coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_valid = coupler_from_rockettile_2_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_2_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_2_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_2_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_2_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_2_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_2_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_2_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_ready = coupler_from_rockettile_2_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_valid = coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_opcode = coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_param = coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_size = coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_source = coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_address = coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_data = coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_d_ready = coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_valid = coupler_from_rockettile_2_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_2_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_2_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_2_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_2_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_2_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_2_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_2_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_e_ready = coupler_from_rockettile_2_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_e_valid = coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_e_bits_sink = coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_a_ready = coupler_from_rockettile_2_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_valid = coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_b_ready = coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_valid = coupler_from_rockettile_2_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_c_ready = coupler_from_rockettile_2_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_valid = coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_d_ready = coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_valid = coupler_from_rockettile_2_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_e_ready = coupler_from_rockettile_2_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_e_valid = coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_valid = coupler_from_rockettile_2_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_b_ready = coupler_from_rockettile_2_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_valid = coupler_from_rockettile_2_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_d_ready = coupler_from_rockettile_2_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_e_valid = coupler_from_rockettile_2_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_e_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlOut_a_ready = coupler_from_rockettile_3_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_valid = coupler_from_rockettile_3_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_opcode = coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_param = coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_size = coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_source = coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_address = coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_mask = coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_data = coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_b_ready = coupler_from_rockettile_3_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_b_valid = coupler_from_rockettile_3_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_b_bits_opcode = coupler_from_rockettile_3_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_param = coupler_from_rockettile_3_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlOut_b_bits_size = coupler_from_rockettile_3_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_source = coupler_from_rockettile_3_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlOut_b_bits_address = coupler_from_rockettile_3_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_3_tlOut_b_bits_mask = coupler_from_rockettile_3_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlOut_b_bits_data = coupler_from_rockettile_3_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_b_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_c_ready = coupler_from_rockettile_3_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_valid = coupler_from_rockettile_3_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_opcode = coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_param = coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_size = coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_source = coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_address = coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_data = coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_d_ready = coupler_from_rockettile_3_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_d_valid = coupler_from_rockettile_3_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_opcode = coupler_from_rockettile_3_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_param = coupler_from_rockettile_3_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlOut_d_bits_size = coupler_from_rockettile_3_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_source = coupler_from_rockettile_3_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_sink = coupler_from_rockettile_3_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_d_bits_denied = coupler_from_rockettile_3_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlOut_d_bits_data = coupler_from_rockettile_3_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_d_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_e_ready = coupler_from_rockettile_3_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_e_valid = coupler_from_rockettile_3_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_e_bits_sink = coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlIn_a_ready = coupler_from_rockettile_3_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_valid = coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_opcode = coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_param = coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_size = coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_source = coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_address = coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_mask = coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_data = coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_b_ready = coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_b_valid = coupler_from_rockettile_3_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_b_bits_opcode = coupler_from_rockettile_3_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_param = coupler_from_rockettile_3_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlIn_b_bits_size = coupler_from_rockettile_3_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_source = coupler_from_rockettile_3_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlIn_b_bits_address = coupler_from_rockettile_3_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlIn_b_bits_mask = coupler_from_rockettile_3_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlIn_b_bits_data = coupler_from_rockettile_3_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_b_bits_corrupt = coupler_from_rockettile_3_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_c_ready = coupler_from_rockettile_3_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_valid = coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_opcode = coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_param = coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_size = coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_source = coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_address = coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_data = coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_d_ready = coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_d_valid = coupler_from_rockettile_3_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_opcode = coupler_from_rockettile_3_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_param = coupler_from_rockettile_3_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlIn_d_bits_size = coupler_from_rockettile_3_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_source = coupler_from_rockettile_3_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_sink = coupler_from_rockettile_3_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_d_bits_denied = coupler_from_rockettile_3_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlIn_d_bits_data = coupler_from_rockettile_3_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_d_bits_corrupt = coupler_from_rockettile_3_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_e_ready = coupler_from_rockettile_3_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_e_valid = coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_e_bits_sink = coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_no_bufferOut_a_ready = coupler_from_rockettile_3_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_valid = coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_opcode = coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_param = coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_size = coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_source = coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_address = coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_mask = coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_data = coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_corrupt = coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_b_ready = coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_valid = coupler_from_rockettile_3_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_b_bits_opcode = coupler_from_rockettile_3_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_param = coupler_from_rockettile_3_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_b_bits_size = coupler_from_rockettile_3_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_source = coupler_from_rockettile_3_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_b_bits_address = coupler_from_rockettile_3_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferOut_b_bits_mask = coupler_from_rockettile_3_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_b_bits_data = coupler_from_rockettile_3_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_3_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_ready = coupler_from_rockettile_3_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_valid = coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_opcode = coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_param = coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_size = coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_source = coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_address = coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_data = coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_corrupt = coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_d_ready = coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_valid = coupler_from_rockettile_3_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_opcode = coupler_from_rockettile_3_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_param = coupler_from_rockettile_3_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_d_bits_size = coupler_from_rockettile_3_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_source = coupler_from_rockettile_3_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_sink = coupler_from_rockettile_3_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_bits_denied = coupler_from_rockettile_3_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_d_bits_data = coupler_from_rockettile_3_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_3_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_e_ready = coupler_from_rockettile_3_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_e_valid = coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_e_bits_sink = coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_ready = coupler_from_rockettile_3_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_valid = coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_opcode = coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_param = coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_size = coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_source = coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_address = coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_mask = coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_data = coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_b_ready = coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_valid = coupler_from_rockettile_3_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_b_bits_opcode = coupler_from_rockettile_3_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_param = coupler_from_rockettile_3_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_b_bits_size = coupler_from_rockettile_3_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_source = coupler_from_rockettile_3_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_b_bits_address = coupler_from_rockettile_3_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferIn_b_bits_mask = coupler_from_rockettile_3_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_b_bits_data = coupler_from_rockettile_3_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_ready = coupler_from_rockettile_3_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_valid = coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_opcode = coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_param = coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_size = coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_source = coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_address = coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_data = coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_d_ready = coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_valid = coupler_from_rockettile_3_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_opcode = coupler_from_rockettile_3_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_param = coupler_from_rockettile_3_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_d_bits_size = coupler_from_rockettile_3_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_source = coupler_from_rockettile_3_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_sink = coupler_from_rockettile_3_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_bits_denied = coupler_from_rockettile_3_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_d_bits_data = coupler_from_rockettile_3_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_e_ready = coupler_from_rockettile_3_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_e_valid = coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_e_bits_sink = coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_ready = coupler_from_rockettile_3_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_valid = coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_opcode = coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_param = coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_size = coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_source = coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_address = coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_mask = coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_data = coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_b_ready = coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_valid = coupler_from_rockettile_3_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_3_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_3_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_3_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_3_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_3_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_3_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_3_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_ready = coupler_from_rockettile_3_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_valid = coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_opcode = coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_param = coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_size = coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_source = coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_address = coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_data = coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_d_ready = coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_valid = coupler_from_rockettile_3_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_3_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_3_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_3_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_3_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_3_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_3_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_3_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_e_ready = coupler_from_rockettile_3_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_e_valid = coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_e_bits_sink = coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_a_ready = coupler_from_rockettile_3_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_valid = coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_b_ready = coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_valid = coupler_from_rockettile_3_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_c_ready = coupler_from_rockettile_3_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_valid = coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_d_ready = coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_valid = coupler_from_rockettile_3_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_e_ready = coupler_from_rockettile_3_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_e_valid = coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_valid = coupler_from_rockettile_3_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_b_ready = coupler_from_rockettile_3_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_valid = coupler_from_rockettile_3_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_d_ready = coupler_from_rockettile_3_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_e_valid = coupler_from_rockettile_3_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire fixer__T_17 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire fixer__T_19 = fixer_d_first_1 & fixer__T_18; // @[Decoupled.scala:51:35] wire fixer__T_33 = fixer_a_first_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire fixer__T_35 = fixer_d_first_2 & fixer__T_34; // @[Decoupled.scala:51:35] wire fixer__T_49 = fixer_a_first_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35] wire fixer__T_51 = fixer_d_first_3 & fixer__T_50; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_1 <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_2 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_2 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_2_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_2 <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_3 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_3 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_3_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_3 <= 3'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_1) // @[Decoupled.scala:51:35] fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_2) // @[Decoupled.scala:51:35] fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21] fixer_flight_1_0 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h0) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_1 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h1) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_2 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h2) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_2) // @[Decoupled.scala:51:35] fixer_a_first_counter_2 <= fixer__a_first_counter_T_2; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_4) // @[Decoupled.scala:51:35] fixer_d_first_counter_2 <= fixer__d_first_counter_T_2; // @[Edges.scala:229:27, :236:21] fixer_flight_2_0 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h0) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h0 ? fixer__flight_T_2 : fixer_flight_2_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_1 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h1) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h1 ? fixer__flight_T_2 : fixer_flight_2_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_2 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h2) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h2 ? fixer__flight_T_2 : fixer_flight_2_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_2 <= fixer__SourceIdFIFOed_T_2; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_3) // @[Decoupled.scala:51:35] fixer_a_first_counter_3 <= fixer__a_first_counter_T_3; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_6) // @[Decoupled.scala:51:35] fixer_d_first_counter_3 <= fixer__d_first_counter_T_3; // @[Edges.scala:229:27, :236:21] fixer_flight_3_0 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h0) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h0 ? fixer__flight_T_3 : fixer_flight_3_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3_1 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h1) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h1 ? fixer__flight_T_3 : fixer_flight_3_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3_2 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h2) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h2 ? fixer__flight_T_3 : fixer_flight_3_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_3 <= fixer__SourceIdFIFOed_T_3; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_7_1 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_csbus0_i4_o1_a32d64s4k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_3_a_ready (fixer_auto_anon_out_3_a_ready), .auto_anon_in_3_a_valid (fixer_auto_anon_out_3_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_opcode (fixer_auto_anon_out_3_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_param (fixer_auto_anon_out_3_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_size (fixer_auto_anon_out_3_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_source (fixer_auto_anon_out_3_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_address (fixer_auto_anon_out_3_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_mask (fixer_auto_anon_out_3_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_data (fixer_auto_anon_out_3_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_corrupt (fixer_auto_anon_out_3_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_b_ready (fixer_auto_anon_out_3_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_b_valid (fixer_auto_anon_out_3_b_valid), .auto_anon_in_3_b_bits_opcode (fixer_auto_anon_out_3_b_bits_opcode), .auto_anon_in_3_b_bits_param (fixer_auto_anon_out_3_b_bits_param), .auto_anon_in_3_b_bits_size (fixer_auto_anon_out_3_b_bits_size), .auto_anon_in_3_b_bits_source (fixer_auto_anon_out_3_b_bits_source), .auto_anon_in_3_b_bits_address (fixer_auto_anon_out_3_b_bits_address), .auto_anon_in_3_b_bits_mask (fixer_auto_anon_out_3_b_bits_mask), .auto_anon_in_3_b_bits_data (fixer_auto_anon_out_3_b_bits_data), .auto_anon_in_3_b_bits_corrupt (fixer_auto_anon_out_3_b_bits_corrupt), .auto_anon_in_3_c_ready (fixer_auto_anon_out_3_c_ready), .auto_anon_in_3_c_valid (fixer_auto_anon_out_3_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_opcode (fixer_auto_anon_out_3_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_param (fixer_auto_anon_out_3_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_size (fixer_auto_anon_out_3_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_source (fixer_auto_anon_out_3_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_address (fixer_auto_anon_out_3_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_data (fixer_auto_anon_out_3_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_corrupt (fixer_auto_anon_out_3_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_d_ready (fixer_auto_anon_out_3_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_d_valid (fixer_auto_anon_out_3_d_valid), .auto_anon_in_3_d_bits_opcode (fixer_auto_anon_out_3_d_bits_opcode), .auto_anon_in_3_d_bits_param (fixer_auto_anon_out_3_d_bits_param), .auto_anon_in_3_d_bits_size (fixer_auto_anon_out_3_d_bits_size), .auto_anon_in_3_d_bits_source (fixer_auto_anon_out_3_d_bits_source), .auto_anon_in_3_d_bits_sink (fixer_auto_anon_out_3_d_bits_sink), .auto_anon_in_3_d_bits_denied (fixer_auto_anon_out_3_d_bits_denied), .auto_anon_in_3_d_bits_data (fixer_auto_anon_out_3_d_bits_data), .auto_anon_in_3_d_bits_corrupt (fixer_auto_anon_out_3_d_bits_corrupt), .auto_anon_in_3_e_ready (fixer_auto_anon_out_3_e_ready), .auto_anon_in_3_e_valid (fixer_auto_anon_out_3_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_e_bits_sink (fixer_auto_anon_out_3_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_ready (fixer_auto_anon_out_2_a_ready), .auto_anon_in_2_a_valid (fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_opcode (fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_param (fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_size (fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_source (fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_address (fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_mask (fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_data (fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_corrupt (fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_ready (fixer_auto_anon_out_2_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_valid (fixer_auto_anon_out_2_b_valid), .auto_anon_in_2_b_bits_opcode (fixer_auto_anon_out_2_b_bits_opcode), .auto_anon_in_2_b_bits_param (fixer_auto_anon_out_2_b_bits_param), .auto_anon_in_2_b_bits_size (fixer_auto_anon_out_2_b_bits_size), .auto_anon_in_2_b_bits_source (fixer_auto_anon_out_2_b_bits_source), .auto_anon_in_2_b_bits_address (fixer_auto_anon_out_2_b_bits_address), .auto_anon_in_2_b_bits_mask (fixer_auto_anon_out_2_b_bits_mask), .auto_anon_in_2_b_bits_data (fixer_auto_anon_out_2_b_bits_data), .auto_anon_in_2_b_bits_corrupt (fixer_auto_anon_out_2_b_bits_corrupt), .auto_anon_in_2_c_ready (fixer_auto_anon_out_2_c_ready), .auto_anon_in_2_c_valid (fixer_auto_anon_out_2_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_opcode (fixer_auto_anon_out_2_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_param (fixer_auto_anon_out_2_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_size (fixer_auto_anon_out_2_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_source (fixer_auto_anon_out_2_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_address (fixer_auto_anon_out_2_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_data (fixer_auto_anon_out_2_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_corrupt (fixer_auto_anon_out_2_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_ready (fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_valid (fixer_auto_anon_out_2_d_valid), .auto_anon_in_2_d_bits_opcode (fixer_auto_anon_out_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (fixer_auto_anon_out_2_d_bits_param), .auto_anon_in_2_d_bits_size (fixer_auto_anon_out_2_d_bits_size), .auto_anon_in_2_d_bits_source (fixer_auto_anon_out_2_d_bits_source), .auto_anon_in_2_d_bits_sink (fixer_auto_anon_out_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (fixer_auto_anon_out_2_d_bits_denied), .auto_anon_in_2_d_bits_data (fixer_auto_anon_out_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (fixer_auto_anon_out_2_d_bits_corrupt), .auto_anon_in_2_e_ready (fixer_auto_anon_out_2_e_ready), .auto_anon_in_2_e_valid (fixer_auto_anon_out_2_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_e_bits_sink (fixer_auto_anon_out_2_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready), .auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_ready (fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_valid (fixer_auto_anon_out_1_b_valid), .auto_anon_in_1_b_bits_opcode (fixer_auto_anon_out_1_b_bits_opcode), .auto_anon_in_1_b_bits_param (fixer_auto_anon_out_1_b_bits_param), .auto_anon_in_1_b_bits_size (fixer_auto_anon_out_1_b_bits_size), .auto_anon_in_1_b_bits_source (fixer_auto_anon_out_1_b_bits_source), .auto_anon_in_1_b_bits_address (fixer_auto_anon_out_1_b_bits_address), .auto_anon_in_1_b_bits_mask (fixer_auto_anon_out_1_b_bits_mask), .auto_anon_in_1_b_bits_data (fixer_auto_anon_out_1_b_bits_data), .auto_anon_in_1_b_bits_corrupt (fixer_auto_anon_out_1_b_bits_corrupt), .auto_anon_in_1_c_ready (fixer_auto_anon_out_1_c_ready), .auto_anon_in_1_c_valid (fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_opcode (fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_param (fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_size (fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_source (fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_address (fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_data (fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_corrupt (fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid), .auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param), .auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size), .auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source), .auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied), .auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt), .auto_anon_in_1_e_ready (fixer_auto_anon_out_1_e_ready), .auto_anon_in_1_e_valid (fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_e_bits_sink (fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready), .auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_b_ready (fixer_auto_anon_out_0_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_b_valid (fixer_auto_anon_out_0_b_valid), .auto_anon_in_0_b_bits_opcode (fixer_auto_anon_out_0_b_bits_opcode), .auto_anon_in_0_b_bits_param (fixer_auto_anon_out_0_b_bits_param), .auto_anon_in_0_b_bits_size (fixer_auto_anon_out_0_b_bits_size), .auto_anon_in_0_b_bits_source (fixer_auto_anon_out_0_b_bits_source), .auto_anon_in_0_b_bits_address (fixer_auto_anon_out_0_b_bits_address), .auto_anon_in_0_b_bits_mask (fixer_auto_anon_out_0_b_bits_mask), .auto_anon_in_0_b_bits_data (fixer_auto_anon_out_0_b_bits_data), .auto_anon_in_0_b_bits_corrupt (fixer_auto_anon_out_0_b_bits_corrupt), .auto_anon_in_0_c_ready (fixer_auto_anon_out_0_c_ready), .auto_anon_in_0_c_valid (fixer_auto_anon_out_0_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_opcode (fixer_auto_anon_out_0_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_param (fixer_auto_anon_out_0_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_size (fixer_auto_anon_out_0_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_source (fixer_auto_anon_out_0_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_address (fixer_auto_anon_out_0_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_data (fixer_auto_anon_out_0_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_corrupt (fixer_auto_anon_out_0_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid), .auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param), .auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size), .auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source), .auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied), .auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt), .auto_anon_in_0_e_ready (fixer_auto_anon_out_0_e_ready), .auto_anon_in_0_e_valid (fixer_auto_anon_out_0_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_e_bits_sink (fixer_auto_anon_out_0_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_out_a_ready (auto_system_bus_xbar_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_a_valid (auto_system_bus_xbar_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_system_bus_xbar_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_system_bus_xbar_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_system_bus_xbar_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_system_bus_xbar_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_system_bus_xbar_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_system_bus_xbar_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_system_bus_xbar_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_system_bus_xbar_anon_out_a_bits_corrupt_0), .auto_anon_out_b_ready (auto_system_bus_xbar_anon_out_b_ready_0), .auto_anon_out_b_valid (auto_system_bus_xbar_anon_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_opcode (auto_system_bus_xbar_anon_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_param (auto_system_bus_xbar_anon_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_size (auto_system_bus_xbar_anon_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_source (auto_system_bus_xbar_anon_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_address (auto_system_bus_xbar_anon_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_mask (auto_system_bus_xbar_anon_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_data (auto_system_bus_xbar_anon_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_corrupt (auto_system_bus_xbar_anon_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_out_c_ready (auto_system_bus_xbar_anon_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_c_valid (auto_system_bus_xbar_anon_out_c_valid_0), .auto_anon_out_c_bits_opcode (auto_system_bus_xbar_anon_out_c_bits_opcode_0), .auto_anon_out_c_bits_param (auto_system_bus_xbar_anon_out_c_bits_param_0), .auto_anon_out_c_bits_size (auto_system_bus_xbar_anon_out_c_bits_size_0), .auto_anon_out_c_bits_source (auto_system_bus_xbar_anon_out_c_bits_source_0), .auto_anon_out_c_bits_address (auto_system_bus_xbar_anon_out_c_bits_address_0), .auto_anon_out_c_bits_data (auto_system_bus_xbar_anon_out_c_bits_data_0), .auto_anon_out_c_bits_corrupt (auto_system_bus_xbar_anon_out_c_bits_corrupt_0), .auto_anon_out_d_ready (auto_system_bus_xbar_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_system_bus_xbar_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_opcode (auto_system_bus_xbar_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_param (auto_system_bus_xbar_anon_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_size (auto_system_bus_xbar_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_source (auto_system_bus_xbar_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_sink (auto_system_bus_xbar_anon_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_denied (auto_system_bus_xbar_anon_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_data (auto_system_bus_xbar_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_corrupt (auto_system_bus_xbar_anon_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_out_e_ready (auto_system_bus_xbar_anon_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_e_valid (auto_system_bus_xbar_anon_out_e_valid_0), .auto_anon_out_e_bits_sink (auto_system_bus_xbar_anon_out_e_bits_sink_0) ); // @[SystemBus.scala:47:43] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_valid = auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_opcode = auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_param = auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_size = auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_source = auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_address = auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_mask = auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_data = auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_corrupt = auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_b_ready = auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_valid = auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_opcode = auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_param = auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_size = auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_source = auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_address = auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_data = auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_corrupt = auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_d_ready = auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_e_valid = auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_e_bits_sink = auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_19 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_19( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_159 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_159( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_6 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_12 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_6 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`2`[1], io.router_resp.vc_sel.`2`[1] connect route_q.io.enq.bits.vc_sel.`2`[2], io.router_resp.vc_sel.`2`[2] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_13 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_6 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[1], io.vcalloc_resp.vc_sel.`2`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[2], io.vcalloc_resp.vc_sel.`2`[2] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _c_T_2 = cat(c_hi_2, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node c_lo = cat(_c_T_1, _c_T) node c_hi_3 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], _c_T_2) node _c_T_3 = cat(c_hi_3, c_lo) node c_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _c_T_4 = cat(c_hi_4, io.out_credit_available.`0`[0]) node c_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _c_T_5 = cat(c_hi_5, io.out_credit_available.`1`[0]) node c_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _c_T_6 = cat(c_hi_6, io.out_credit_available.`2`[0]) node c_lo_1 = cat(_c_T_5, _c_T_4) node c_hi_7 = cat(io.out_credit_available.`3`[0], _c_T_6) node _c_T_7 = cat(c_hi_7, c_lo_1) node _c_T_8 = and(_c_T_3, _c_T_7) node c = neq(_c_T_8, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2]) node _out_channel_oh_T_2 = or(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node out_channel_oh_2 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`2`[2]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2) node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0) node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8) node out_bundle_bits_out_virt_channel_hi_4 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _out_bundle_bits_out_virt_channel_T_10 = cat(out_bundle_bits_out_virt_channel_hi_4, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node out_bundle_bits_out_virt_channel_hi_5 = bits(_out_bundle_bits_out_virt_channel_T_10, 2, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_10, 1, 0) node _out_bundle_bits_out_virt_channel_T_11 = orr(out_bundle_bits_out_virt_channel_hi_5) node _out_bundle_bits_out_virt_channel_T_12 = or(out_bundle_bits_out_virt_channel_hi_5, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_13 = bits(_out_bundle_bits_out_virt_channel_T_12, 1, 1) node _out_bundle_bits_out_virt_channel_T_14 = cat(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_15 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_16 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_17 = mux(out_channel_oh_2, _out_bundle_bits_out_virt_channel_T_14, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_18 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_19 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_16) node _out_bundle_bits_out_virt_channel_T_20 = or(_out_bundle_bits_out_virt_channel_T_19, _out_bundle_bits_out_virt_channel_T_17) node _out_bundle_bits_out_virt_channel_T_21 = or(_out_bundle_bits_out_virt_channel_T_20, _out_bundle_bits_out_virt_channel_T_18) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_21 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_6( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_4 \| _route_buffer_io_enq_bits_flow_egress_node_id_T_5 \| _route_buffer_io_enq_bits_flow_egress_node_id_T_6 \| _route_buffer_io_enq_bits_flow_egress_node_id_T_7}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h1; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h1; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module SinkE : input clock : Clock input reset : Reset output io : { resp : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} connect io.e.ready, UInt<1>(0h1) connect io.resp.valid, io.e.valid connect io.resp.bits.sink, io.e.bits.sink	module SinkE( // @[SinkE.scala:29:7] input clock, // @[SinkE.scala:29:7] input reset, // @[SinkE.scala:29:7] output io_resp_valid, // @[SinkE.scala:31:14] output [2:0] io_resp_bits_sink, // @[SinkE.scala:31:14] input io_e_valid, // @[SinkE.scala:31:14] input [2:0] io_e_bits_sink // @[SinkE.scala:31:14] ); wire io_e_valid_0 = io_e_valid; // @[SinkE.scala:29:7] wire [2:0] io_e_bits_sink_0 = io_e_bits_sink; // @[SinkE.scala:29:7] wire io_e_ready = 1'h1; // @[SinkE.scala:29:7] wire io_resp_valid_0 = io_e_valid_0; // @[SinkE.scala:29:7] wire [2:0] io_resp_bits_sink_0 = io_e_bits_sink_0; // @[SinkE.scala:29:7] assign io_resp_valid = io_resp_valid_0; // @[SinkE.scala:29:7] assign io_resp_bits_sink = io_resp_bits_sink_0; // @[SinkE.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_64 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24_64( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain : output auto : { flip plic_int_in : UInt<1>[1], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_1 : { sync : UInt<1>[1]}, int_in_clock_xing_out_0 : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst plic of TLPLIC connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[1]} invalidate intInClockXingOut.sync[0] wire intInClockXingIn : { sync : UInt<1>[1]} invalidate intInClockXingIn.sync[0] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 connect intsource.auto.in[0], plic.auto.int_out_0[0] connect intsource_1.auto.in[0], plic.auto.int_out_1[0] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect plic.auto.in, auto.plic_in connect plic.auto.int_in[0], auto.plic_int_in[0] connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_101 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] TLPLIC plic ( // @[Plic.scala:367:46] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9] .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready_0), .auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_plic_in_d_valid_0), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_plic_in_d_bits_size_0), .auto_in_d_bits_source (auto_plic_in_d_bits_source_0), .auto_in_d_bits_data (auto_plic_in_d_bits_data_0) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_27 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} inst main of BranchKillableQueue_26 connect main.clock, clock connect main.reset, reset reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect main.io.enq, io.enq connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect main.io.brupdate.b2.taken, io.brupdate.b2.taken connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect main.io.flush, io.flush node _io_empty_T = eq(out_valid, UInt<1>(0h0)) node _io_empty_T_1 = and(main.io.empty, _io_empty_T) connect io.empty, _io_empty_T_1 node _io_count_T = add(main.io.count, out_valid) node _io_count_T_1 = tail(_io_count_T, 1) connect io.count, _io_count_T_1 connect io.deq.valid, out_valid connect io.deq.bits, out_reg connect io.deq.bits.uop, out_uop wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out, out_uop node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T) connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1 connect out_uop, out_uop_out node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask) node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0)) node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0)) node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0)) node _out_valid_T_4 = and(out_valid, _out_valid_T_3) node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq) node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0)) node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6) connect out_valid, _out_valid_T_7 connect main.io.deq.ready, UInt<1>(0h0) node _T = and(io.deq.ready, io.deq.valid) node _T_1 = eq(out_valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) when _T_2 : node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask) node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0)) node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0)) node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0)) node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11) node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq) node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0)) node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14) connect out_valid, _out_valid_T_15 connect out_reg, main.io.deq.bits wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out_1, main.io.deq.bits.uop node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2) connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3 connect out_uop, out_uop_out_1 connect main.io.deq.ready, UInt<1>(0h1)	module BranchKillableQueue_27( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _out_valid_T_12; // @[util.scala:496:38] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27] wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94] wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [33:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [33:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22] reg [1:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 \| ~out_valid; // @[Decoupled.scala:51:35] wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}] wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_26 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_out_valid_T_12), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_19 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24_19( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_72 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[5], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[5], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} reg states : { `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 4, 4) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`4`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`4`.occupied, UInt<1>(0h1), "") : assert connect states.`4`.occupied, UInt<1>(0h0) when io.allocs[4].alloc : connect states.`4`.occupied, UInt<1>(0h1) connect states.`4`.flow, io.allocs[4].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node free = bits(io.out.credit_return, 0, 0) node free_1 = bits(io.out.credit_return, 1, 1) node free_2 = bits(io.out.credit_return, 2, 2) node free_3 = bits(io.out.credit_return, 3, 3) node free_4 = bits(io.out.credit_return, 4, 4) node _states_4_c_T = add(states.`4`.c, free_4) node _states_4_c_T_1 = sub(_states_4_c_T, io.credit_alloc[4].alloc) node _states_4_c_T_2 = tail(_states_4_c_T_1, 1) connect states.`4`.c, _states_4_c_T_2 node _T_4 = asUInt(reset) when _T_4 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4)	module OutputUnit_72( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [4:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [4:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i5_o2_a32d128s7k4z4c : input clock : Clock input reset : Reset output auto : { flip anon_in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_1.e.bits.sink invalidate anonIn_1.e.valid invalidate anonIn_1.e.ready invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.c.bits.corrupt invalidate anonIn_1.c.bits.data invalidate anonIn_1.c.bits.address invalidate anonIn_1.c.bits.source invalidate anonIn_1.c.bits.size invalidate anonIn_1.c.bits.param invalidate anonIn_1.c.bits.opcode invalidate anonIn_1.c.valid invalidate anonIn_1.c.ready invalidate anonIn_1.b.bits.corrupt invalidate anonIn_1.b.bits.data invalidate anonIn_1.b.bits.mask invalidate anonIn_1.b.bits.address invalidate anonIn_1.b.bits.source invalidate anonIn_1.b.bits.size invalidate anonIn_1.b.bits.param invalidate anonIn_1.b.bits.opcode invalidate anonIn_1.b.valid invalidate anonIn_1.b.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_2.e.bits.sink invalidate anonIn_2.e.valid invalidate anonIn_2.e.ready invalidate anonIn_2.d.bits.corrupt invalidate anonIn_2.d.bits.data invalidate anonIn_2.d.bits.denied invalidate anonIn_2.d.bits.sink invalidate anonIn_2.d.bits.source invalidate anonIn_2.d.bits.size invalidate anonIn_2.d.bits.param invalidate anonIn_2.d.bits.opcode invalidate anonIn_2.d.valid invalidate anonIn_2.d.ready invalidate anonIn_2.c.bits.corrupt invalidate anonIn_2.c.bits.data invalidate anonIn_2.c.bits.address invalidate anonIn_2.c.bits.source invalidate anonIn_2.c.bits.size invalidate anonIn_2.c.bits.param invalidate anonIn_2.c.bits.opcode invalidate anonIn_2.c.valid invalidate anonIn_2.c.ready invalidate anonIn_2.b.bits.corrupt invalidate anonIn_2.b.bits.data invalidate anonIn_2.b.bits.mask invalidate anonIn_2.b.bits.address invalidate anonIn_2.b.bits.source invalidate anonIn_2.b.bits.size invalidate anonIn_2.b.bits.param invalidate anonIn_2.b.bits.opcode invalidate anonIn_2.b.valid invalidate anonIn_2.b.ready invalidate anonIn_2.a.bits.corrupt invalidate anonIn_2.a.bits.data invalidate anonIn_2.a.bits.mask invalidate anonIn_2.a.bits.address invalidate anonIn_2.a.bits.source invalidate anonIn_2.a.bits.size invalidate anonIn_2.a.bits.param invalidate anonIn_2.a.bits.opcode invalidate anonIn_2.a.valid invalidate anonIn_2.a.ready wire anonIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_3.e.bits.sink invalidate anonIn_3.e.valid invalidate anonIn_3.e.ready invalidate anonIn_3.d.bits.corrupt invalidate anonIn_3.d.bits.data invalidate anonIn_3.d.bits.denied invalidate anonIn_3.d.bits.sink invalidate anonIn_3.d.bits.source invalidate anonIn_3.d.bits.size invalidate anonIn_3.d.bits.param invalidate anonIn_3.d.bits.opcode invalidate anonIn_3.d.valid invalidate anonIn_3.d.ready invalidate anonIn_3.c.bits.corrupt invalidate anonIn_3.c.bits.data invalidate anonIn_3.c.bits.address invalidate anonIn_3.c.bits.source invalidate anonIn_3.c.bits.size invalidate anonIn_3.c.bits.param invalidate anonIn_3.c.bits.opcode invalidate anonIn_3.c.valid invalidate anonIn_3.c.ready invalidate anonIn_3.b.bits.corrupt invalidate anonIn_3.b.bits.data invalidate anonIn_3.b.bits.mask invalidate anonIn_3.b.bits.address invalidate anonIn_3.b.bits.source invalidate anonIn_3.b.bits.size invalidate anonIn_3.b.bits.param invalidate anonIn_3.b.bits.opcode invalidate anonIn_3.b.valid invalidate anonIn_3.b.ready invalidate anonIn_3.a.bits.corrupt invalidate anonIn_3.a.bits.data invalidate anonIn_3.a.bits.mask invalidate anonIn_3.a.bits.address invalidate anonIn_3.a.bits.source invalidate anonIn_3.a.bits.size invalidate anonIn_3.a.bits.param invalidate anonIn_3.a.bits.opcode invalidate anonIn_3.a.valid invalidate anonIn_3.a.ready wire anonIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_4.e.bits.sink invalidate anonIn_4.e.valid invalidate anonIn_4.e.ready invalidate anonIn_4.d.bits.corrupt invalidate anonIn_4.d.bits.data invalidate anonIn_4.d.bits.denied invalidate anonIn_4.d.bits.sink invalidate anonIn_4.d.bits.source invalidate anonIn_4.d.bits.size invalidate anonIn_4.d.bits.param invalidate anonIn_4.d.bits.opcode invalidate anonIn_4.d.valid invalidate anonIn_4.d.ready invalidate anonIn_4.c.bits.corrupt invalidate anonIn_4.c.bits.data invalidate anonIn_4.c.bits.address invalidate anonIn_4.c.bits.source invalidate anonIn_4.c.bits.size invalidate anonIn_4.c.bits.param invalidate anonIn_4.c.bits.opcode invalidate anonIn_4.c.valid invalidate anonIn_4.c.ready invalidate anonIn_4.b.bits.corrupt invalidate anonIn_4.b.bits.data invalidate anonIn_4.b.bits.mask invalidate anonIn_4.b.bits.address invalidate anonIn_4.b.bits.source invalidate anonIn_4.b.bits.size invalidate anonIn_4.b.bits.param invalidate anonIn_4.b.bits.opcode invalidate anonIn_4.b.valid invalidate anonIn_4.b.ready invalidate anonIn_4.a.bits.corrupt invalidate anonIn_4.a.bits.data invalidate anonIn_4.a.bits.mask invalidate anonIn_4.a.bits.address invalidate anonIn_4.a.bits.source invalidate anonIn_4.a.bits.size invalidate anonIn_4.a.bits.param invalidate anonIn_4.a.bits.opcode invalidate anonIn_4.a.valid invalidate anonIn_4.a.ready inst monitor of TLMonitor connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_1 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink connect monitor_1.io.in.e.valid, anonIn_1.e.valid connect monitor_1.io.in.e.ready, anonIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, anonIn_1.c.valid connect monitor_1.io.in.c.ready, anonIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, anonIn_1.b.valid connect monitor_1.io.in.b.ready, anonIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready inst monitor_2 of TLMonitor_2 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.e.bits.sink, anonIn_2.e.bits.sink connect monitor_2.io.in.e.valid, anonIn_2.e.valid connect monitor_2.io.in.e.ready, anonIn_2.e.ready connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, anonIn_2.d.valid connect monitor_2.io.in.d.ready, anonIn_2.d.ready connect monitor_2.io.in.c.bits.corrupt, anonIn_2.c.bits.corrupt connect monitor_2.io.in.c.bits.data, anonIn_2.c.bits.data connect monitor_2.io.in.c.bits.address, anonIn_2.c.bits.address connect monitor_2.io.in.c.bits.source, anonIn_2.c.bits.source connect monitor_2.io.in.c.bits.size, anonIn_2.c.bits.size connect monitor_2.io.in.c.bits.param, anonIn_2.c.bits.param connect monitor_2.io.in.c.bits.opcode, anonIn_2.c.bits.opcode connect monitor_2.io.in.c.valid, anonIn_2.c.valid connect monitor_2.io.in.c.ready, anonIn_2.c.ready connect monitor_2.io.in.b.bits.corrupt, anonIn_2.b.bits.corrupt connect monitor_2.io.in.b.bits.data, anonIn_2.b.bits.data connect monitor_2.io.in.b.bits.mask, anonIn_2.b.bits.mask connect monitor_2.io.in.b.bits.address, anonIn_2.b.bits.address connect monitor_2.io.in.b.bits.source, anonIn_2.b.bits.source connect monitor_2.io.in.b.bits.size, anonIn_2.b.bits.size connect monitor_2.io.in.b.bits.param, anonIn_2.b.bits.param connect monitor_2.io.in.b.bits.opcode, anonIn_2.b.bits.opcode connect monitor_2.io.in.b.valid, anonIn_2.b.valid connect monitor_2.io.in.b.ready, anonIn_2.b.ready connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, anonIn_2.a.valid connect monitor_2.io.in.a.ready, anonIn_2.a.ready inst monitor_3 of TLMonitor_3 connect monitor_3.clock, clock connect monitor_3.reset, reset connect monitor_3.io.in.e.bits.sink, anonIn_3.e.bits.sink connect monitor_3.io.in.e.valid, anonIn_3.e.valid connect monitor_3.io.in.e.ready, anonIn_3.e.ready connect monitor_3.io.in.d.bits.corrupt, anonIn_3.d.bits.corrupt connect monitor_3.io.in.d.bits.data, anonIn_3.d.bits.data connect monitor_3.io.in.d.bits.denied, anonIn_3.d.bits.denied connect monitor_3.io.in.d.bits.sink, anonIn_3.d.bits.sink connect monitor_3.io.in.d.bits.source, anonIn_3.d.bits.source connect monitor_3.io.in.d.bits.size, anonIn_3.d.bits.size connect monitor_3.io.in.d.bits.param, anonIn_3.d.bits.param connect monitor_3.io.in.d.bits.opcode, anonIn_3.d.bits.opcode connect monitor_3.io.in.d.valid, anonIn_3.d.valid connect monitor_3.io.in.d.ready, anonIn_3.d.ready connect monitor_3.io.in.c.bits.corrupt, anonIn_3.c.bits.corrupt connect monitor_3.io.in.c.bits.data, anonIn_3.c.bits.data connect monitor_3.io.in.c.bits.address, anonIn_3.c.bits.address connect monitor_3.io.in.c.bits.source, anonIn_3.c.bits.source connect monitor_3.io.in.c.bits.size, anonIn_3.c.bits.size connect monitor_3.io.in.c.bits.param, anonIn_3.c.bits.param connect monitor_3.io.in.c.bits.opcode, anonIn_3.c.bits.opcode connect monitor_3.io.in.c.valid, anonIn_3.c.valid connect monitor_3.io.in.c.ready, anonIn_3.c.ready connect monitor_3.io.in.b.bits.corrupt, anonIn_3.b.bits.corrupt connect monitor_3.io.in.b.bits.data, anonIn_3.b.bits.data connect monitor_3.io.in.b.bits.mask, anonIn_3.b.bits.mask connect monitor_3.io.in.b.bits.address, anonIn_3.b.bits.address connect monitor_3.io.in.b.bits.source, anonIn_3.b.bits.source connect monitor_3.io.in.b.bits.size, anonIn_3.b.bits.size connect monitor_3.io.in.b.bits.param, anonIn_3.b.bits.param connect monitor_3.io.in.b.bits.opcode, anonIn_3.b.bits.opcode connect monitor_3.io.in.b.valid, anonIn_3.b.valid connect monitor_3.io.in.b.ready, anonIn_3.b.ready connect monitor_3.io.in.a.bits.corrupt, anonIn_3.a.bits.corrupt connect monitor_3.io.in.a.bits.data, anonIn_3.a.bits.data connect monitor_3.io.in.a.bits.mask, anonIn_3.a.bits.mask connect monitor_3.io.in.a.bits.address, anonIn_3.a.bits.address connect monitor_3.io.in.a.bits.source, anonIn_3.a.bits.source connect monitor_3.io.in.a.bits.size, anonIn_3.a.bits.size connect monitor_3.io.in.a.bits.param, anonIn_3.a.bits.param connect monitor_3.io.in.a.bits.opcode, anonIn_3.a.bits.opcode connect monitor_3.io.in.a.valid, anonIn_3.a.valid connect monitor_3.io.in.a.ready, anonIn_3.a.ready inst monitor_4 of TLMonitor_4 connect monitor_4.clock, clock connect monitor_4.reset, reset connect monitor_4.io.in.e.bits.sink, anonIn_4.e.bits.sink connect monitor_4.io.in.e.valid, anonIn_4.e.valid connect monitor_4.io.in.e.ready, anonIn_4.e.ready connect monitor_4.io.in.d.bits.corrupt, anonIn_4.d.bits.corrupt connect monitor_4.io.in.d.bits.data, anonIn_4.d.bits.data connect monitor_4.io.in.d.bits.denied, anonIn_4.d.bits.denied connect monitor_4.io.in.d.bits.sink, anonIn_4.d.bits.sink connect monitor_4.io.in.d.bits.source, anonIn_4.d.bits.source connect monitor_4.io.in.d.bits.size, anonIn_4.d.bits.size connect monitor_4.io.in.d.bits.param, anonIn_4.d.bits.param connect monitor_4.io.in.d.bits.opcode, anonIn_4.d.bits.opcode connect monitor_4.io.in.d.valid, anonIn_4.d.valid connect monitor_4.io.in.d.ready, anonIn_4.d.ready connect monitor_4.io.in.c.bits.corrupt, anonIn_4.c.bits.corrupt connect monitor_4.io.in.c.bits.data, anonIn_4.c.bits.data connect monitor_4.io.in.c.bits.address, anonIn_4.c.bits.address connect monitor_4.io.in.c.bits.source, anonIn_4.c.bits.source connect monitor_4.io.in.c.bits.size, anonIn_4.c.bits.size connect monitor_4.io.in.c.bits.param, anonIn_4.c.bits.param connect monitor_4.io.in.c.bits.opcode, anonIn_4.c.bits.opcode connect monitor_4.io.in.c.valid, anonIn_4.c.valid connect monitor_4.io.in.c.ready, anonIn_4.c.ready connect monitor_4.io.in.b.bits.corrupt, anonIn_4.b.bits.corrupt connect monitor_4.io.in.b.bits.data, anonIn_4.b.bits.data connect monitor_4.io.in.b.bits.mask, anonIn_4.b.bits.mask connect monitor_4.io.in.b.bits.address, anonIn_4.b.bits.address connect monitor_4.io.in.b.bits.source, anonIn_4.b.bits.source connect monitor_4.io.in.b.bits.size, anonIn_4.b.bits.size connect monitor_4.io.in.b.bits.param, anonIn_4.b.bits.param connect monitor_4.io.in.b.bits.opcode, anonIn_4.b.bits.opcode connect monitor_4.io.in.b.valid, anonIn_4.b.valid connect monitor_4.io.in.b.ready, anonIn_4.b.ready connect monitor_4.io.in.a.bits.corrupt, anonIn_4.a.bits.corrupt connect monitor_4.io.in.a.bits.data, anonIn_4.a.bits.data connect monitor_4.io.in.a.bits.mask, anonIn_4.a.bits.mask connect monitor_4.io.in.a.bits.address, anonIn_4.a.bits.address connect monitor_4.io.in.a.bits.source, anonIn_4.a.bits.source connect monitor_4.io.in.a.bits.size, anonIn_4.a.bits.size connect monitor_4.io.in.a.bits.param, anonIn_4.a.bits.param connect monitor_4.io.in.a.bits.opcode, anonIn_4.a.bits.opcode connect monitor_4.io.in.a.valid, anonIn_4.a.valid connect monitor_4.io.in.a.ready, anonIn_4.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate x1_anonOut.e.bits.sink invalidate x1_anonOut.e.valid invalidate x1_anonOut.e.ready invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.c.bits.corrupt invalidate x1_anonOut.c.bits.data invalidate x1_anonOut.c.bits.address invalidate x1_anonOut.c.bits.source invalidate x1_anonOut.c.bits.size invalidate x1_anonOut.c.bits.param invalidate x1_anonOut.c.bits.opcode invalidate x1_anonOut.c.valid invalidate x1_anonOut.c.ready invalidate x1_anonOut.b.bits.corrupt invalidate x1_anonOut.b.bits.data invalidate x1_anonOut.b.bits.mask invalidate x1_anonOut.b.bits.address invalidate x1_anonOut.b.bits.source invalidate x1_anonOut.b.bits.size invalidate x1_anonOut.b.bits.param invalidate x1_anonOut.b.bits.opcode invalidate x1_anonOut.b.valid invalidate x1_anonOut.b.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonIn_2, auto.anon_in_2 connect anonIn_3, auto.anon_in_3 connect anonIn_4, auto.anon_in_4 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[5] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode invalidate in[0].b.valid invalidate in[0].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[0].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.mask, UInt<16>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[0].c.bits.corrupt invalidate in[0].c.bits.data invalidate in[0].c.bits.address invalidate in[0].c.bits.source invalidate in[0].c.bits.size invalidate in[0].c.bits.param invalidate in[0].c.bits.opcode invalidate in[0].c.valid invalidate in[0].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[0].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T invalidate in[0].e.bits.sink invalidate in[0].e.valid invalidate in[0].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_8.bits.sink, UInt<4>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[0].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits.sink, UInt<4>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<7>(0h44)) connect in[1].a.bits.source, _in_1_a_bits_source_T connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt connect anonIn_1.b.bits.data, in[1].b.bits.data connect anonIn_1.b.bits.mask, in[1].b.bits.mask connect anonIn_1.b.bits.address, in[1].b.bits.address connect anonIn_1.b.bits.source, in[1].b.bits.source connect anonIn_1.b.bits.size, in[1].b.bits.size connect anonIn_1.b.bits.param, in[1].b.bits.param connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode connect anonIn_1.b.valid, in[1].b.valid connect in[1].b.ready, anonIn_1.b.ready node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0) connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt connect in[1].c.bits.data, anonIn_1.c.bits.data connect in[1].c.bits.address, anonIn_1.c.bits.address connect in[1].c.bits.source, anonIn_1.c.bits.source connect in[1].c.bits.size, anonIn_1.c.bits.size connect in[1].c.bits.param, anonIn_1.c.bits.param connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode connect in[1].c.valid, anonIn_1.c.valid connect anonIn_1.c.ready, in[1].c.ready node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<7>(0h44)) connect in[1].c.bits.source, _in_1_c_bits_source_T connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 connect in[1].e.bits.sink, anonIn_1.e.bits.sink connect in[1].e.valid, anonIn_1.e.valid connect anonIn_1.e.ready, in[1].e.ready connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt connect in[2].a.bits.data, anonIn_2.a.bits.data connect in[2].a.bits.mask, anonIn_2.a.bits.mask connect in[2].a.bits.address, anonIn_2.a.bits.address connect in[2].a.bits.source, anonIn_2.a.bits.source connect in[2].a.bits.size, anonIn_2.a.bits.size connect in[2].a.bits.param, anonIn_2.a.bits.param connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode connect in[2].a.valid, anonIn_2.a.valid connect anonIn_2.a.ready, in[2].a.ready node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<7>(0h40)) connect in[2].a.bits.source, _in_2_a_bits_source_T connect anonIn_2.b.bits.corrupt, in[2].b.bits.corrupt connect anonIn_2.b.bits.data, in[2].b.bits.data connect anonIn_2.b.bits.mask, in[2].b.bits.mask connect anonIn_2.b.bits.address, in[2].b.bits.address connect anonIn_2.b.bits.source, in[2].b.bits.source connect anonIn_2.b.bits.size, in[2].b.bits.size connect anonIn_2.b.bits.param, in[2].b.bits.param connect anonIn_2.b.bits.opcode, in[2].b.bits.opcode connect anonIn_2.b.valid, in[2].b.valid connect in[2].b.ready, anonIn_2.b.ready node _anonIn_b_bits_source_T_1 = bits(in[2].b.bits.source, 1, 0) connect anonIn_2.b.bits.source, _anonIn_b_bits_source_T_1 connect in[2].c.bits.corrupt, anonIn_2.c.bits.corrupt connect in[2].c.bits.data, anonIn_2.c.bits.data connect in[2].c.bits.address, anonIn_2.c.bits.address connect in[2].c.bits.source, anonIn_2.c.bits.source connect in[2].c.bits.size, anonIn_2.c.bits.size connect in[2].c.bits.param, anonIn_2.c.bits.param connect in[2].c.bits.opcode, anonIn_2.c.bits.opcode connect in[2].c.valid, anonIn_2.c.valid connect anonIn_2.c.ready, in[2].c.ready node _in_2_c_bits_source_T = or(anonIn_2.c.bits.source, UInt<7>(0h40)) connect in[2].c.bits.source, _in_2_c_bits_source_T connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt connect anonIn_2.d.bits.data, in[2].d.bits.data connect anonIn_2.d.bits.denied, in[2].d.bits.denied connect anonIn_2.d.bits.sink, in[2].d.bits.sink connect anonIn_2.d.bits.source, in[2].d.bits.source connect anonIn_2.d.bits.size, in[2].d.bits.size connect anonIn_2.d.bits.param, in[2].d.bits.param connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode connect anonIn_2.d.valid, in[2].d.valid connect in[2].d.ready, anonIn_2.d.ready node _anonIn_d_bits_source_T_2 = bits(in[2].d.bits.source, 1, 0) connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_2 connect in[2].e.bits.sink, anonIn_2.e.bits.sink connect in[2].e.valid, anonIn_2.e.valid connect anonIn_2.e.ready, in[2].e.ready connect in[3].a.bits.corrupt, anonIn_3.a.bits.corrupt connect in[3].a.bits.data, anonIn_3.a.bits.data connect in[3].a.bits.mask, anonIn_3.a.bits.mask connect in[3].a.bits.address, anonIn_3.a.bits.address connect in[3].a.bits.source, anonIn_3.a.bits.source connect in[3].a.bits.size, anonIn_3.a.bits.size connect in[3].a.bits.param, anonIn_3.a.bits.param connect in[3].a.bits.opcode, anonIn_3.a.bits.opcode connect in[3].a.valid, anonIn_3.a.valid connect anonIn_3.a.ready, in[3].a.ready node _in_3_a_bits_source_T = or(anonIn_3.a.bits.source, UInt<6>(0h30)) connect in[3].a.bits.source, _in_3_a_bits_source_T connect anonIn_3.b.bits.corrupt, in[3].b.bits.corrupt connect anonIn_3.b.bits.data, in[3].b.bits.data connect anonIn_3.b.bits.mask, in[3].b.bits.mask connect anonIn_3.b.bits.address, in[3].b.bits.address connect anonIn_3.b.bits.source, in[3].b.bits.source connect anonIn_3.b.bits.size, in[3].b.bits.size connect anonIn_3.b.bits.param, in[3].b.bits.param connect anonIn_3.b.bits.opcode, in[3].b.bits.opcode connect anonIn_3.b.valid, in[3].b.valid connect in[3].b.ready, anonIn_3.b.ready node _anonIn_b_bits_source_T_2 = bits(in[3].b.bits.source, 3, 0) connect anonIn_3.b.bits.source, _anonIn_b_bits_source_T_2 connect in[3].c.bits.corrupt, anonIn_3.c.bits.corrupt connect in[3].c.bits.data, anonIn_3.c.bits.data connect in[3].c.bits.address, anonIn_3.c.bits.address connect in[3].c.bits.source, anonIn_3.c.bits.source connect in[3].c.bits.size, anonIn_3.c.bits.size connect in[3].c.bits.param, anonIn_3.c.bits.param connect in[3].c.bits.opcode, anonIn_3.c.bits.opcode connect in[3].c.valid, anonIn_3.c.valid connect anonIn_3.c.ready, in[3].c.ready node _in_3_c_bits_source_T = or(anonIn_3.c.bits.source, UInt<6>(0h30)) connect in[3].c.bits.source, _in_3_c_bits_source_T connect anonIn_3.d.bits.corrupt, in[3].d.bits.corrupt connect anonIn_3.d.bits.data, in[3].d.bits.data connect anonIn_3.d.bits.denied, in[3].d.bits.denied connect anonIn_3.d.bits.sink, in[3].d.bits.sink connect anonIn_3.d.bits.source, in[3].d.bits.source connect anonIn_3.d.bits.size, in[3].d.bits.size connect anonIn_3.d.bits.param, in[3].d.bits.param connect anonIn_3.d.bits.opcode, in[3].d.bits.opcode connect anonIn_3.d.valid, in[3].d.valid connect in[3].d.ready, anonIn_3.d.ready node _anonIn_d_bits_source_T_3 = bits(in[3].d.bits.source, 3, 0) connect anonIn_3.d.bits.source, _anonIn_d_bits_source_T_3 connect in[3].e.bits.sink, anonIn_3.e.bits.sink connect in[3].e.valid, anonIn_3.e.valid connect anonIn_3.e.ready, in[3].e.ready connect in[4].a.bits.corrupt, anonIn_4.a.bits.corrupt connect in[4].a.bits.data, anonIn_4.a.bits.data connect in[4].a.bits.mask, anonIn_4.a.bits.mask connect in[4].a.bits.address, anonIn_4.a.bits.address connect in[4].a.bits.source, anonIn_4.a.bits.source connect in[4].a.bits.size, anonIn_4.a.bits.size connect in[4].a.bits.param, anonIn_4.a.bits.param connect in[4].a.bits.opcode, anonIn_4.a.bits.opcode connect in[4].a.valid, anonIn_4.a.valid connect anonIn_4.a.ready, in[4].a.ready node _in_4_a_bits_source_T = or(anonIn_4.a.bits.source, UInt<6>(0h20)) connect in[4].a.bits.source, _in_4_a_bits_source_T connect anonIn_4.b.bits.corrupt, in[4].b.bits.corrupt connect anonIn_4.b.bits.data, in[4].b.bits.data connect anonIn_4.b.bits.mask, in[4].b.bits.mask connect anonIn_4.b.bits.address, in[4].b.bits.address connect anonIn_4.b.bits.source, in[4].b.bits.source connect anonIn_4.b.bits.size, in[4].b.bits.size connect anonIn_4.b.bits.param, in[4].b.bits.param connect anonIn_4.b.bits.opcode, in[4].b.bits.opcode connect anonIn_4.b.valid, in[4].b.valid connect in[4].b.ready, anonIn_4.b.ready node _anonIn_b_bits_source_T_3 = bits(in[4].b.bits.source, 3, 0) connect anonIn_4.b.bits.source, _anonIn_b_bits_source_T_3 connect in[4].c.bits.corrupt, anonIn_4.c.bits.corrupt connect in[4].c.bits.data, anonIn_4.c.bits.data connect in[4].c.bits.address, anonIn_4.c.bits.address connect in[4].c.bits.source, anonIn_4.c.bits.source connect in[4].c.bits.size, anonIn_4.c.bits.size connect in[4].c.bits.param, anonIn_4.c.bits.param connect in[4].c.bits.opcode, anonIn_4.c.bits.opcode connect in[4].c.valid, anonIn_4.c.valid connect anonIn_4.c.ready, in[4].c.ready node _in_4_c_bits_source_T = or(anonIn_4.c.bits.source, UInt<6>(0h20)) connect in[4].c.bits.source, _in_4_c_bits_source_T connect anonIn_4.d.bits.corrupt, in[4].d.bits.corrupt connect anonIn_4.d.bits.data, in[4].d.bits.data connect anonIn_4.d.bits.denied, in[4].d.bits.denied connect anonIn_4.d.bits.sink, in[4].d.bits.sink connect anonIn_4.d.bits.source, in[4].d.bits.source connect anonIn_4.d.bits.size, in[4].d.bits.size connect anonIn_4.d.bits.param, in[4].d.bits.param connect anonIn_4.d.bits.opcode, in[4].d.bits.opcode connect anonIn_4.d.valid, in[4].d.valid connect in[4].d.ready, anonIn_4.d.ready node _anonIn_d_bits_source_T_4 = bits(in[4].d.bits.source, 3, 0) connect anonIn_4.d.bits.source, _anonIn_d_bits_source_T_4 connect in[4].e.bits.sink, anonIn_4.e.bits.sink connect in[4].e.valid, anonIn_4.e.valid connect anonIn_4.e.ready, in[4].e.ready wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready invalidate out[0].b.bits.corrupt invalidate out[0].b.bits.data invalidate out[0].b.bits.mask invalidate out[0].b.bits.address invalidate out[0].b.bits.source invalidate out[0].b.bits.size invalidate out[0].b.bits.param invalidate out[0].b.bits.opcode invalidate out[0].b.valid invalidate out[0].b.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.mask, UInt<16>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<2>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready invalidate _WIRE_13.bits.corrupt invalidate _WIRE_13.bits.data invalidate _WIRE_13.bits.mask invalidate _WIRE_13.bits.address invalidate _WIRE_13.bits.source invalidate _WIRE_13.bits.size invalidate _WIRE_13.bits.param invalidate _WIRE_13.bits.opcode invalidate _WIRE_13.valid invalidate _WIRE_13.ready connect out[0].b.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.mask, UInt<16>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<2>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].c.valid invalidate out[0].c.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.corrupt invalidate _WIRE_17.bits.data invalidate _WIRE_17.bits.address invalidate _WIRE_17.bits.source invalidate _WIRE_17.bits.size invalidate _WIRE_17.bits.param invalidate _WIRE_17.bits.opcode invalidate _WIRE_17.valid invalidate _WIRE_17.ready connect out[0].c.ready, UInt<1>(0h1) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T invalidate out[0].e.bits.sink invalidate out[0].e.valid invalidate out[0].e.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready invalidate _WIRE_21.bits.sink invalidate _WIRE_21.valid invalidate _WIRE_21.ready connect out[0].e.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt connect out[1].b.bits.data, x1_anonOut.b.bits.data connect out[1].b.bits.mask, x1_anonOut.b.bits.mask connect out[1].b.bits.address, x1_anonOut.b.bits.address connect out[1].b.bits.source, x1_anonOut.b.bits.source connect out[1].b.bits.size, x1_anonOut.b.bits.size connect out[1].b.bits.param, x1_anonOut.b.bits.param connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode connect out[1].b.valid, x1_anonOut.b.valid connect x1_anonOut.b.ready, out[1].b.ready connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt connect x1_anonOut.c.bits.data, out[1].c.bits.data connect x1_anonOut.c.bits.address, out[1].c.bits.address connect x1_anonOut.c.bits.source, out[1].c.bits.source connect x1_anonOut.c.bits.size, out[1].c.bits.size connect x1_anonOut.c.bits.param, out[1].c.bits.param connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode connect x1_anonOut.c.valid, out[1].c.valid connect out[1].c.ready, x1_anonOut.c.ready connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T connect x1_anonOut.e.bits.sink, out[1].e.bits.sink connect x1_anonOut.e.valid, out[1].e.valid connect out[1].e.ready, x1_anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 3, 0) connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9) node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16) node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_18 = cvt(_requestAIO_T_17) node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_20 = asSInt(_requestAIO_T_19) node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0))) node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_23 = cvt(_requestAIO_T_22) node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_25 = asSInt(_requestAIO_T_24) node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0))) node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27) node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_29 = cvt(_requestAIO_T_28) node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_31 = asSInt(_requestAIO_T_30) node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0))) node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_34 = cvt(_requestAIO_T_33) node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_36 = asSInt(_requestAIO_T_35) node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0))) node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_39 = cvt(_requestAIO_T_38) node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_41 = asSInt(_requestAIO_T_40) node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0))) node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37) node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42) node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44) node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_46 = cvt(_requestAIO_T_45) node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_48 = asSInt(_requestAIO_T_47) node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0))) node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_51 = cvt(_requestAIO_T_50) node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_53 = asSInt(_requestAIO_T_52) node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0))) node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54) node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55) node _requestAIO_T_56 = xor(in[2].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_57 = cvt(_requestAIO_T_56) node _requestAIO_T_58 = and(_requestAIO_T_57, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_59 = asSInt(_requestAIO_T_58) node _requestAIO_T_60 = eq(_requestAIO_T_59, asSInt(UInt<1>(0h0))) node _requestAIO_T_61 = xor(in[2].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_62 = cvt(_requestAIO_T_61) node _requestAIO_T_63 = and(_requestAIO_T_62, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_64 = asSInt(_requestAIO_T_63) node _requestAIO_T_65 = eq(_requestAIO_T_64, asSInt(UInt<1>(0h0))) node _requestAIO_T_66 = xor(in[2].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_67 = cvt(_requestAIO_T_66) node _requestAIO_T_68 = and(_requestAIO_T_67, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_69 = asSInt(_requestAIO_T_68) node _requestAIO_T_70 = eq(_requestAIO_T_69, asSInt(UInt<1>(0h0))) node _requestAIO_T_71 = or(_requestAIO_T_60, _requestAIO_T_65) node _requestAIO_T_72 = or(_requestAIO_T_71, _requestAIO_T_70) node requestAIO_2_0 = or(UInt<1>(0h0), _requestAIO_T_72) node _requestAIO_T_73 = xor(in[2].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_74 = cvt(_requestAIO_T_73) node _requestAIO_T_75 = and(_requestAIO_T_74, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_76 = asSInt(_requestAIO_T_75) node _requestAIO_T_77 = eq(_requestAIO_T_76, asSInt(UInt<1>(0h0))) node _requestAIO_T_78 = xor(in[2].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_79 = cvt(_requestAIO_T_78) node _requestAIO_T_80 = and(_requestAIO_T_79, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_81 = asSInt(_requestAIO_T_80) node _requestAIO_T_82 = eq(_requestAIO_T_81, asSInt(UInt<1>(0h0))) node _requestAIO_T_83 = or(_requestAIO_T_77, _requestAIO_T_82) node requestAIO_2_1 = or(UInt<1>(0h0), _requestAIO_T_83) node _requestAIO_T_84 = xor(in[3].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_85 = cvt(_requestAIO_T_84) node _requestAIO_T_86 = and(_requestAIO_T_85, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_87 = asSInt(_requestAIO_T_86) node _requestAIO_T_88 = eq(_requestAIO_T_87, asSInt(UInt<1>(0h0))) node _requestAIO_T_89 = xor(in[3].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_90 = cvt(_requestAIO_T_89) node _requestAIO_T_91 = and(_requestAIO_T_90, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_92 = asSInt(_requestAIO_T_91) node _requestAIO_T_93 = eq(_requestAIO_T_92, asSInt(UInt<1>(0h0))) node _requestAIO_T_94 = xor(in[3].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_95 = cvt(_requestAIO_T_94) node _requestAIO_T_96 = and(_requestAIO_T_95, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_97 = asSInt(_requestAIO_T_96) node _requestAIO_T_98 = eq(_requestAIO_T_97, asSInt(UInt<1>(0h0))) node _requestAIO_T_99 = or(_requestAIO_T_88, _requestAIO_T_93) node _requestAIO_T_100 = or(_requestAIO_T_99, _requestAIO_T_98) node requestAIO_3_0 = or(UInt<1>(0h0), _requestAIO_T_100) node _requestAIO_T_101 = xor(in[3].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_102 = cvt(_requestAIO_T_101) node _requestAIO_T_103 = and(_requestAIO_T_102, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_104 = asSInt(_requestAIO_T_103) node _requestAIO_T_105 = eq(_requestAIO_T_104, asSInt(UInt<1>(0h0))) node _requestAIO_T_106 = xor(in[3].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_107 = cvt(_requestAIO_T_106) node _requestAIO_T_108 = and(_requestAIO_T_107, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_109 = asSInt(_requestAIO_T_108) node _requestAIO_T_110 = eq(_requestAIO_T_109, asSInt(UInt<1>(0h0))) node _requestAIO_T_111 = or(_requestAIO_T_105, _requestAIO_T_110) node requestAIO_3_1 = or(UInt<1>(0h0), _requestAIO_T_111) node _requestAIO_T_112 = xor(in[4].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_113 = cvt(_requestAIO_T_112) node _requestAIO_T_114 = and(_requestAIO_T_113, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_115 = asSInt(_requestAIO_T_114) node _requestAIO_T_116 = eq(_requestAIO_T_115, asSInt(UInt<1>(0h0))) node _requestAIO_T_117 = xor(in[4].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_118 = cvt(_requestAIO_T_117) node _requestAIO_T_119 = and(_requestAIO_T_118, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_120 = asSInt(_requestAIO_T_119) node _requestAIO_T_121 = eq(_requestAIO_T_120, asSInt(UInt<1>(0h0))) node _requestAIO_T_122 = xor(in[4].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_123 = cvt(_requestAIO_T_122) node _requestAIO_T_124 = and(_requestAIO_T_123, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_125 = asSInt(_requestAIO_T_124) node _requestAIO_T_126 = eq(_requestAIO_T_125, asSInt(UInt<1>(0h0))) node _requestAIO_T_127 = or(_requestAIO_T_116, _requestAIO_T_121) node _requestAIO_T_128 = or(_requestAIO_T_127, _requestAIO_T_126) node requestAIO_4_0 = or(UInt<1>(0h0), _requestAIO_T_128) node _requestAIO_T_129 = xor(in[4].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_130 = cvt(_requestAIO_T_129) node _requestAIO_T_131 = and(_requestAIO_T_130, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_132 = asSInt(_requestAIO_T_131) node _requestAIO_T_133 = eq(_requestAIO_T_132, asSInt(UInt<1>(0h0))) node _requestAIO_T_134 = xor(in[4].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_135 = cvt(_requestAIO_T_134) node _requestAIO_T_136 = and(_requestAIO_T_135, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_137 = asSInt(_requestAIO_T_136) node _requestAIO_T_138 = eq(_requestAIO_T_137, asSInt(UInt<1>(0h0))) node _requestAIO_T_139 = or(_requestAIO_T_133, _requestAIO_T_138) node requestAIO_4_1 = or(UInt<1>(0h0), _requestAIO_T_139) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19) node _requestCIO_T_20 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_21 = cvt(_requestCIO_T_20) node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0))) node _requestCIO_T_23 = asSInt(_requestCIO_T_22) node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0))) node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_24) node _requestCIO_T_25 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_26 = cvt(_requestCIO_T_25) node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0))) node _requestCIO_T_28 = asSInt(_requestCIO_T_27) node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0))) node requestCIO_2_1 = or(UInt<1>(0h1), _requestCIO_T_29) node _requestCIO_T_30 = xor(in[3].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_31 = cvt(_requestCIO_T_30) node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0))) node _requestCIO_T_33 = asSInt(_requestCIO_T_32) node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0))) node requestCIO_3_0 = or(UInt<1>(0h1), _requestCIO_T_34) node _requestCIO_T_35 = xor(in[3].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_36 = cvt(_requestCIO_T_35) node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0))) node _requestCIO_T_38 = asSInt(_requestCIO_T_37) node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0))) node requestCIO_3_1 = or(UInt<1>(0h1), _requestCIO_T_39) node _requestCIO_T_40 = xor(in[4].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_41 = cvt(_requestCIO_T_40) node _requestCIO_T_42 = and(_requestCIO_T_41, asSInt(UInt<1>(0h0))) node _requestCIO_T_43 = asSInt(_requestCIO_T_42) node _requestCIO_T_44 = eq(_requestCIO_T_43, asSInt(UInt<1>(0h0))) node requestCIO_4_0 = or(UInt<1>(0h1), _requestCIO_T_44) node _requestCIO_T_45 = xor(in[4].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_46 = cvt(_requestCIO_T_45) node _requestCIO_T_47 = and(_requestCIO_T_46, asSInt(UInt<1>(0h0))) node _requestCIO_T_48 = asSInt(_requestCIO_T_47) node _requestCIO_T_49 = eq(_requestCIO_T_48, asSInt(UInt<1>(0h0))) node requestCIO_4_1 = or(UInt<1>(0h1), _requestCIO_T_49) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(out[0].b.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0) node _requestBOI_T_5 = shr(out[0].b.bits.source, 2) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<5>(0h11)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3)) node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestBOI_uncommonBits_T_2 = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 1, 0) node _requestBOI_T_10 = shr(out[0].b.bits.source, 2) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<5>(0h10)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<2>(0h3)) node requestBOI_0_2 = and(_requestBOI_T_13, _requestBOI_T_14) node _requestBOI_uncommonBits_T_3 = or(out[0].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 3, 0) node _requestBOI_T_15 = shr(out[0].b.bits.source, 4) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<2>(0h3)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<4>(0hf)) node requestBOI_0_3 = and(_requestBOI_T_18, _requestBOI_T_19) node _requestBOI_uncommonBits_T_4 = or(out[0].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 3, 0) node _requestBOI_T_20 = shr(out[0].b.bits.source, 4) node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<2>(0h2)) node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4) node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22) node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<4>(0hf)) node requestBOI_0_4 = and(_requestBOI_T_23, _requestBOI_T_24) node _requestBOI_uncommonBits_T_5 = or(out[1].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 4, 0) node _requestBOI_T_25 = shr(out[1].b.bits.source, 5) node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0)) node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5) node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27) node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_28, _requestBOI_T_29) node _requestBOI_uncommonBits_T_6 = or(out[1].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 1, 0) node _requestBOI_T_30 = shr(out[1].b.bits.source, 2) node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<5>(0h11)) node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6) node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32) node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<2>(0h3)) node requestBOI_1_1 = and(_requestBOI_T_33, _requestBOI_T_34) node _requestBOI_uncommonBits_T_7 = or(out[1].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 1, 0) node _requestBOI_T_35 = shr(out[1].b.bits.source, 2) node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<5>(0h10)) node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7) node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37) node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<2>(0h3)) node requestBOI_1_2 = and(_requestBOI_T_38, _requestBOI_T_39) node _requestBOI_uncommonBits_T_8 = or(out[1].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_8 = bits(_requestBOI_uncommonBits_T_8, 3, 0) node _requestBOI_T_40 = shr(out[1].b.bits.source, 4) node _requestBOI_T_41 = eq(_requestBOI_T_40, UInt<2>(0h3)) node _requestBOI_T_42 = leq(UInt<1>(0h0), requestBOI_uncommonBits_8) node _requestBOI_T_43 = and(_requestBOI_T_41, _requestBOI_T_42) node _requestBOI_T_44 = leq(requestBOI_uncommonBits_8, UInt<4>(0hf)) node requestBOI_1_3 = and(_requestBOI_T_43, _requestBOI_T_44) node _requestBOI_uncommonBits_T_9 = or(out[1].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_9 = bits(_requestBOI_uncommonBits_T_9, 3, 0) node _requestBOI_T_45 = shr(out[1].b.bits.source, 4) node _requestBOI_T_46 = eq(_requestBOI_T_45, UInt<2>(0h2)) node _requestBOI_T_47 = leq(UInt<1>(0h0), requestBOI_uncommonBits_9) node _requestBOI_T_48 = and(_requestBOI_T_46, _requestBOI_T_47) node _requestBOI_T_49 = leq(requestBOI_uncommonBits_9, UInt<4>(0hf)) node requestBOI_1_4 = and(_requestBOI_T_48, _requestBOI_T_49) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0) node _requestDOI_T_5 = shr(out[0].d.bits.source, 2) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<5>(0h11)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3)) node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 1, 0) node _requestDOI_T_10 = shr(out[0].d.bits.source, 2) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<5>(0h10)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<2>(0h3)) node requestDOI_0_2 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 3, 0) node _requestDOI_T_15 = shr(out[0].d.bits.source, 4) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<2>(0h3)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<4>(0hf)) node requestDOI_0_3 = and(_requestDOI_T_18, _requestDOI_T_19) node _requestDOI_uncommonBits_T_4 = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 3, 0) node _requestDOI_T_20 = shr(out[0].d.bits.source, 4) node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<2>(0h2)) node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4) node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22) node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<4>(0hf)) node requestDOI_0_4 = and(_requestDOI_T_23, _requestDOI_T_24) node _requestDOI_uncommonBits_T_5 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 4, 0) node _requestDOI_T_25 = shr(out[1].d.bits.source, 5) node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0)) node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5) node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27) node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_28, _requestDOI_T_29) node _requestDOI_uncommonBits_T_6 = or(out[1].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 1, 0) node _requestDOI_T_30 = shr(out[1].d.bits.source, 2) node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<5>(0h11)) node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6) node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32) node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<2>(0h3)) node requestDOI_1_1 = and(_requestDOI_T_33, _requestDOI_T_34) node _requestDOI_uncommonBits_T_7 = or(out[1].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 1, 0) node _requestDOI_T_35 = shr(out[1].d.bits.source, 2) node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<5>(0h10)) node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7) node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37) node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<2>(0h3)) node requestDOI_1_2 = and(_requestDOI_T_38, _requestDOI_T_39) node _requestDOI_uncommonBits_T_8 = or(out[1].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_8 = bits(_requestDOI_uncommonBits_T_8, 3, 0) node _requestDOI_T_40 = shr(out[1].d.bits.source, 4) node _requestDOI_T_41 = eq(_requestDOI_T_40, UInt<2>(0h3)) node _requestDOI_T_42 = leq(UInt<1>(0h0), requestDOI_uncommonBits_8) node _requestDOI_T_43 = and(_requestDOI_T_41, _requestDOI_T_42) node _requestDOI_T_44 = leq(requestDOI_uncommonBits_8, UInt<4>(0hf)) node requestDOI_1_3 = and(_requestDOI_T_43, _requestDOI_T_44) node _requestDOI_uncommonBits_T_9 = or(out[1].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_9 = bits(_requestDOI_uncommonBits_T_9, 3, 0) node _requestDOI_T_45 = shr(out[1].d.bits.source, 4) node _requestDOI_T_46 = eq(_requestDOI_T_45, UInt<2>(0h2)) node _requestDOI_T_47 = leq(UInt<1>(0h0), requestDOI_uncommonBits_9) node _requestDOI_T_48 = and(_requestDOI_T_46, _requestDOI_T_47) node _requestDOI_T_49 = leq(requestDOI_uncommonBits_9, UInt<4>(0hf)) node requestDOI_1_4 = and(_requestDOI_T_48, _requestDOI_T_49) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 3, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 4) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<4>(0hf)) node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 3, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 4) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<4>(0hf)) node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9) node _requestEIO_uncommonBits_T_2 = or(in[2].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_2 = bits(_requestEIO_uncommonBits_T_2, 3, 0) node _requestEIO_T_10 = shr(in[2].e.bits.sink, 4) node _requestEIO_T_11 = eq(_requestEIO_T_10, UInt<1>(0h0)) node _requestEIO_T_12 = leq(UInt<1>(0h0), requestEIO_uncommonBits_2) node _requestEIO_T_13 = and(_requestEIO_T_11, _requestEIO_T_12) node _requestEIO_T_14 = leq(requestEIO_uncommonBits_2, UInt<4>(0hf)) node requestEIO_2_1 = and(_requestEIO_T_13, _requestEIO_T_14) node _requestEIO_uncommonBits_T_3 = or(in[3].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_3 = bits(_requestEIO_uncommonBits_T_3, 3, 0) node _requestEIO_T_15 = shr(in[3].e.bits.sink, 4) node _requestEIO_T_16 = eq(_requestEIO_T_15, UInt<1>(0h0)) node _requestEIO_T_17 = leq(UInt<1>(0h0), requestEIO_uncommonBits_3) node _requestEIO_T_18 = and(_requestEIO_T_16, _requestEIO_T_17) node _requestEIO_T_19 = leq(requestEIO_uncommonBits_3, UInt<4>(0hf)) node requestEIO_3_1 = and(_requestEIO_T_18, _requestEIO_T_19) node _requestEIO_uncommonBits_T_4 = or(in[4].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_4 = bits(_requestEIO_uncommonBits_T_4, 3, 0) node _requestEIO_T_20 = shr(in[4].e.bits.sink, 4) node _requestEIO_T_21 = eq(_requestEIO_T_20, UInt<1>(0h0)) node _requestEIO_T_22 = leq(UInt<1>(0h0), requestEIO_uncommonBits_4) node _requestEIO_T_23 = and(_requestEIO_T_21, _requestEIO_T_22) node _requestEIO_T_24 = leq(requestEIO_uncommonBits_4, UInt<4>(0hf)) node requestEIO_4_1 = and(_requestEIO_T_23, _requestEIO_T_24) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 4) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 4) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size) node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0) node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7) node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 4) node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2) node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0)) node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0)) node _beatsAI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].a.bits.size) node _beatsAI_decode_T_10 = bits(_beatsAI_decode_T_9, 11, 0) node _beatsAI_decode_T_11 = not(_beatsAI_decode_T_10) node beatsAI_decode_3 = shr(_beatsAI_decode_T_11, 4) node _beatsAI_opdata_T_3 = bits(in[3].a.bits.opcode, 2, 2) node beatsAI_opdata_3 = eq(_beatsAI_opdata_T_3, UInt<1>(0h0)) node beatsAI_3 = mux(beatsAI_opdata_3, beatsAI_decode_3, UInt<1>(0h0)) node _beatsAI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].a.bits.size) node _beatsAI_decode_T_13 = bits(_beatsAI_decode_T_12, 11, 0) node _beatsAI_decode_T_14 = not(_beatsAI_decode_T_13) node beatsAI_decode_4 = shr(_beatsAI_decode_T_14, 4) node _beatsAI_opdata_T_4 = bits(in[4].a.bits.opcode, 2, 2) node beatsAI_opdata_4 = eq(_beatsAI_opdata_T_4, UInt<1>(0h0)) node beatsAI_4 = mux(beatsAI_opdata_4, beatsAI_decode_4, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 4) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 4) node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 4) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 4) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].c.bits.size) node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0) node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7) node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 4) node beatsCI_opdata_2 = bits(in[2].c.bits.opcode, 0, 0) node beatsCI_2 = mux(beatsCI_opdata_2, beatsCI_decode_2, UInt<1>(0h0)) node _beatsCI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].c.bits.size) node _beatsCI_decode_T_10 = bits(_beatsCI_decode_T_9, 11, 0) node _beatsCI_decode_T_11 = not(_beatsCI_decode_T_10) node beatsCI_decode_3 = shr(_beatsCI_decode_T_11, 4) node beatsCI_opdata_3 = bits(in[3].c.bits.opcode, 0, 0) node beatsCI_3 = mux(beatsCI_opdata_3, beatsCI_decode_3, UInt<1>(0h0)) node _beatsCI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].c.bits.size) node _beatsCI_decode_T_13 = bits(_beatsCI_decode_T_12, 11, 0) node _beatsCI_decode_T_14 = not(_beatsCI_decode_T_13) node beatsCI_decode_4 = shr(_beatsCI_decode_T_14, 4) node beatsCI_opdata_4 = bits(in[4].c.bits.opcode, 0, 0) node beatsCI_4 = mux(beatsCI_opdata_4, beatsCI_decode_4, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 4) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 4) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect portsAOI_filtered_1[1].bits, in[1].a.bits node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2) connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3 node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1) wire _portsAOI_in_1_a_ready_WIRE : UInt<1> connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2 connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_2[0].bits, in[2].a.bits node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4) connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5 connect portsAOI_filtered_2[1].bits, in[2].a.bits node _portsAOI_filtered_1_valid_T_4 = or(requestAIO_2_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_1_valid_T_4) connect portsAOI_filtered_2[1].valid, _portsAOI_filtered_1_valid_T_5 node _portsAOI_in_2_a_ready_T = mux(requestAIO_2_0, portsAOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_1 = mux(requestAIO_2_1, portsAOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_2 = or(_portsAOI_in_2_a_ready_T, _portsAOI_in_2_a_ready_T_1) wire _portsAOI_in_2_a_ready_WIRE : UInt<1> connect _portsAOI_in_2_a_ready_WIRE, _portsAOI_in_2_a_ready_T_2 connect in[2].a.ready, _portsAOI_in_2_a_ready_WIRE wire portsAOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_3[0].bits, in[3].a.bits node _portsAOI_filtered_0_valid_T_6 = or(requestAIO_3_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_0_valid_T_6) connect portsAOI_filtered_3[0].valid, _portsAOI_filtered_0_valid_T_7 connect portsAOI_filtered_3[1].bits, in[3].a.bits node _portsAOI_filtered_1_valid_T_6 = or(requestAIO_3_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_1_valid_T_6) connect portsAOI_filtered_3[1].valid, _portsAOI_filtered_1_valid_T_7 node _portsAOI_in_3_a_ready_T = mux(requestAIO_3_0, portsAOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsAOI_in_3_a_ready_T_1 = mux(requestAIO_3_1, portsAOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsAOI_in_3_a_ready_T_2 = or(_portsAOI_in_3_a_ready_T, _portsAOI_in_3_a_ready_T_1) wire _portsAOI_in_3_a_ready_WIRE : UInt<1> connect _portsAOI_in_3_a_ready_WIRE, _portsAOI_in_3_a_ready_T_2 connect in[3].a.ready, _portsAOI_in_3_a_ready_WIRE wire portsAOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_4[0].bits, in[4].a.bits node _portsAOI_filtered_0_valid_T_8 = or(requestAIO_4_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_0_valid_T_8) connect portsAOI_filtered_4[0].valid, _portsAOI_filtered_0_valid_T_9 connect portsAOI_filtered_4[1].bits, in[4].a.bits node _portsAOI_filtered_1_valid_T_8 = or(requestAIO_4_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_1_valid_T_8) connect portsAOI_filtered_4[1].valid, _portsAOI_filtered_1_valid_T_9 node _portsAOI_in_4_a_ready_T = mux(requestAIO_4_0, portsAOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsAOI_in_4_a_ready_T_1 = mux(requestAIO_4_1, portsAOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsAOI_in_4_a_ready_T_2 = or(_portsAOI_in_4_a_ready_T, _portsAOI_in_4_a_ready_T_1) wire _portsAOI_in_4_a_ready_WIRE : UInt<1> connect _portsAOI_in_4_a_ready_WIRE, _portsAOI_in_4_a_ready_T_2 connect in[4].a.ready, _portsAOI_in_4_a_ready_WIRE wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 connect portsBIO_filtered[2].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[2].bits.data, out[0].b.bits.data connect portsBIO_filtered[2].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[2].bits.address, out[0].b.bits.address connect portsBIO_filtered[2].bits.source, out[0].b.bits.source connect portsBIO_filtered[2].bits.size, out[0].b.bits.size connect portsBIO_filtered[2].bits.param, out[0].b.bits.param connect portsBIO_filtered[2].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_2_valid_T) connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1 connect portsBIO_filtered[3].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[3].bits.data, out[0].b.bits.data connect portsBIO_filtered[3].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[3].bits.address, out[0].b.bits.address connect portsBIO_filtered[3].bits.source, out[0].b.bits.source connect portsBIO_filtered[3].bits.size, out[0].b.bits.size connect portsBIO_filtered[3].bits.param, out[0].b.bits.param connect portsBIO_filtered[3].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_3_valid_T = or(requestBOI_0_3, UInt<1>(0h0)) node _portsBIO_filtered_3_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_3_valid_T) connect portsBIO_filtered[3].valid, _portsBIO_filtered_3_valid_T_1 connect portsBIO_filtered[4].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[4].bits.data, out[0].b.bits.data connect portsBIO_filtered[4].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[4].bits.address, out[0].b.bits.address connect portsBIO_filtered[4].bits.source, out[0].b.bits.source connect portsBIO_filtered[4].bits.size, out[0].b.bits.size connect portsBIO_filtered[4].bits.param, out[0].b.bits.param connect portsBIO_filtered[4].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_4_valid_T = or(requestBOI_0_4, UInt<1>(0h0)) node _portsBIO_filtered_4_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_4_valid_T) connect portsBIO_filtered[4].valid, _portsBIO_filtered_4_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_3 = mux(requestBOI_0_3, portsBIO_filtered[3].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_4 = mux(requestBOI_0_4, portsBIO_filtered[4].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_5 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) node _portsBIO_out_0_b_ready_T_6 = or(_portsBIO_out_0_b_ready_T_5, _portsBIO_out_0_b_ready_T_2) node _portsBIO_out_0_b_ready_T_7 = or(_portsBIO_out_0_b_ready_T_6, _portsBIO_out_0_b_ready_T_3) node _portsBIO_out_0_b_ready_T_8 = or(_portsBIO_out_0_b_ready_T_7, _portsBIO_out_0_b_ready_T_4) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_8 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2) connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3 connect portsBIO_filtered_1[2].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[2].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[2].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[2].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[2].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[2].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[2].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[2].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_2_valid_T_2 = or(requestBOI_1_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_2_valid_T_2) connect portsBIO_filtered_1[2].valid, _portsBIO_filtered_2_valid_T_3 connect portsBIO_filtered_1[3].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[3].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[3].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[3].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[3].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[3].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[3].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[3].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_3_valid_T_2 = or(requestBOI_1_3, UInt<1>(0h0)) node _portsBIO_filtered_3_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_3_valid_T_2) connect portsBIO_filtered_1[3].valid, _portsBIO_filtered_3_valid_T_3 connect portsBIO_filtered_1[4].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[4].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[4].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[4].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[4].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[4].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[4].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[4].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_4_valid_T_2 = or(requestBOI_1_4, UInt<1>(0h0)) node _portsBIO_filtered_4_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_4_valid_T_2) connect portsBIO_filtered_1[4].valid, _portsBIO_filtered_4_valid_T_3 node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_2 = mux(requestBOI_1_2, portsBIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_3 = mux(requestBOI_1_3, portsBIO_filtered_1[3].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_4 = mux(requestBOI_1_4, portsBIO_filtered_1[4].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_5 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1) node _portsBIO_out_1_b_ready_T_6 = or(_portsBIO_out_1_b_ready_T_5, _portsBIO_out_1_b_ready_T_2) node _portsBIO_out_1_b_ready_T_7 = or(_portsBIO_out_1_b_ready_T_6, _portsBIO_out_1_b_ready_T_3) node _portsBIO_out_1_b_ready_T_8 = or(_portsBIO_out_1_b_ready_T_7, _portsBIO_out_1_b_ready_T_4) wire _portsBIO_out_1_b_ready_WIRE : UInt<1> connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_8 connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, in[0].c.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1) wire _portsCOI_in_0_c_ready_WIRE : UInt<1> connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2 connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect portsCOI_filtered_1[1].bits, in[1].c.bits node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2) connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3 node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1) wire _portsCOI_in_1_c_ready_WIRE : UInt<1> connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2 connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_2[0].bits, in[2].c.bits node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_0_valid_T_4) connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5 connect portsCOI_filtered_2[1].bits, in[2].c.bits node _portsCOI_filtered_1_valid_T_4 = or(requestCIO_2_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_1_valid_T_4) connect portsCOI_filtered_2[1].valid, _portsCOI_filtered_1_valid_T_5 node _portsCOI_in_2_c_ready_T = mux(requestCIO_2_0, portsCOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_1 = mux(requestCIO_2_1, portsCOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_2 = or(_portsCOI_in_2_c_ready_T, _portsCOI_in_2_c_ready_T_1) wire _portsCOI_in_2_c_ready_WIRE : UInt<1> connect _portsCOI_in_2_c_ready_WIRE, _portsCOI_in_2_c_ready_T_2 connect in[2].c.ready, _portsCOI_in_2_c_ready_WIRE wire portsCOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_3[0].bits, in[3].c.bits node _portsCOI_filtered_0_valid_T_6 = or(requestCIO_3_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_0_valid_T_6) connect portsCOI_filtered_3[0].valid, _portsCOI_filtered_0_valid_T_7 connect portsCOI_filtered_3[1].bits, in[3].c.bits node _portsCOI_filtered_1_valid_T_6 = or(requestCIO_3_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_1_valid_T_6) connect portsCOI_filtered_3[1].valid, _portsCOI_filtered_1_valid_T_7 node _portsCOI_in_3_c_ready_T = mux(requestCIO_3_0, portsCOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsCOI_in_3_c_ready_T_1 = mux(requestCIO_3_1, portsCOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsCOI_in_3_c_ready_T_2 = or(_portsCOI_in_3_c_ready_T, _portsCOI_in_3_c_ready_T_1) wire _portsCOI_in_3_c_ready_WIRE : UInt<1> connect _portsCOI_in_3_c_ready_WIRE, _portsCOI_in_3_c_ready_T_2 connect in[3].c.ready, _portsCOI_in_3_c_ready_WIRE wire portsCOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_4[0].bits, in[4].c.bits node _portsCOI_filtered_0_valid_T_8 = or(requestCIO_4_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_0_valid_T_8) connect portsCOI_filtered_4[0].valid, _portsCOI_filtered_0_valid_T_9 connect portsCOI_filtered_4[1].bits, in[4].c.bits node _portsCOI_filtered_1_valid_T_8 = or(requestCIO_4_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_1_valid_T_8) connect portsCOI_filtered_4[1].valid, _portsCOI_filtered_1_valid_T_9 node _portsCOI_in_4_c_ready_T = mux(requestCIO_4_0, portsCOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsCOI_in_4_c_ready_T_1 = mux(requestCIO_4_1, portsCOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsCOI_in_4_c_ready_T_2 = or(_portsCOI_in_4_c_ready_T, _portsCOI_in_4_c_ready_T_1) wire _portsCOI_in_4_c_ready_WIRE : UInt<1> connect _portsCOI_in_4_c_ready_WIRE, _portsCOI_in_4_c_ready_T_2 connect in[4].c.ready, _portsCOI_in_4_c_ready_WIRE wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[2].bits.data, out[0].d.bits.data connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[2].bits.source, out[0].d.bits.source connect portsDIO_filtered[2].bits.size, out[0].d.bits.size connect portsDIO_filtered[2].bits.param, out[0].d.bits.param connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T) connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1 connect portsDIO_filtered[3].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[3].bits.data, out[0].d.bits.data connect portsDIO_filtered[3].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[3].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[3].bits.source, out[0].d.bits.source connect portsDIO_filtered[3].bits.size, out[0].d.bits.size connect portsDIO_filtered[3].bits.param, out[0].d.bits.param connect portsDIO_filtered[3].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_3_valid_T = or(requestDOI_0_3, UInt<1>(0h0)) node _portsDIO_filtered_3_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_3_valid_T) connect portsDIO_filtered[3].valid, _portsDIO_filtered_3_valid_T_1 connect portsDIO_filtered[4].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[4].bits.data, out[0].d.bits.data connect portsDIO_filtered[4].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[4].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[4].bits.source, out[0].d.bits.source connect portsDIO_filtered[4].bits.size, out[0].d.bits.size connect portsDIO_filtered[4].bits.param, out[0].d.bits.param connect portsDIO_filtered[4].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_4_valid_T = or(requestDOI_0_4, UInt<1>(0h0)) node _portsDIO_filtered_4_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_4_valid_T) connect portsDIO_filtered[4].valid, _portsDIO_filtered_4_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_3 = mux(requestDOI_0_3, portsDIO_filtered[3].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_4 = mux(requestDOI_0_4, portsDIO_filtered[4].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_5 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) node _portsDIO_out_0_d_ready_T_6 = or(_portsDIO_out_0_d_ready_T_5, _portsDIO_out_0_d_ready_T_2) node _portsDIO_out_0_d_ready_T_7 = or(_portsDIO_out_0_d_ready_T_6, _portsDIO_out_0_d_ready_T_3) node _portsDIO_out_0_d_ready_T_8 = or(_portsDIO_out_0_d_ready_T_7, _portsDIO_out_0_d_ready_T_4) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_8 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2) connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3 connect portsDIO_filtered_1[2].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[2].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[2].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[2].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[2].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[2].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[2].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[2].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_2_valid_T_2 = or(requestDOI_1_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_2_valid_T_2) connect portsDIO_filtered_1[2].valid, _portsDIO_filtered_2_valid_T_3 connect portsDIO_filtered_1[3].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[3].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[3].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[3].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[3].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[3].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[3].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[3].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_3_valid_T_2 = or(requestDOI_1_3, UInt<1>(0h0)) node _portsDIO_filtered_3_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_3_valid_T_2) connect portsDIO_filtered_1[3].valid, _portsDIO_filtered_3_valid_T_3 connect portsDIO_filtered_1[4].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[4].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[4].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[4].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[4].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[4].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[4].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[4].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_4_valid_T_2 = or(requestDOI_1_4, UInt<1>(0h0)) node _portsDIO_filtered_4_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_4_valid_T_2) connect portsDIO_filtered_1[4].valid, _portsDIO_filtered_4_valid_T_3 node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_2 = mux(requestDOI_1_2, portsDIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_3 = mux(requestDOI_1_3, portsDIO_filtered_1[3].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_4 = mux(requestDOI_1_4, portsDIO_filtered_1[4].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_5 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1) node _portsDIO_out_1_d_ready_T_6 = or(_portsDIO_out_1_d_ready_T_5, _portsDIO_out_1_d_ready_T_2) node _portsDIO_out_1_d_ready_T_7 = or(_portsDIO_out_1_d_ready_T_6, _portsDIO_out_1_d_ready_T_3) node _portsDIO_out_1_d_ready_T_8 = or(_portsDIO_out_1_d_ready_T_7, _portsDIO_out_1_d_ready_T_4) wire _portsDIO_out_1_d_ready_WIRE : UInt<1> connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_8 connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, in[0].e.bits node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1) wire _portsEOI_in_0_e_ready_WIRE : UInt<1> connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2 connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect portsEOI_filtered_1[1].bits, in[1].e.bits node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2) connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3 node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1) wire _portsEOI_in_1_e_ready_WIRE : UInt<1> connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2 connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_2[0].bits, in[2].e.bits node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_0_valid_T_4) connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5 connect portsEOI_filtered_2[1].bits, in[2].e.bits node _portsEOI_filtered_1_valid_T_4 = or(requestEIO_2_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_1_valid_T_4) connect portsEOI_filtered_2[1].valid, _portsEOI_filtered_1_valid_T_5 node _portsEOI_in_2_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_1 = mux(requestEIO_2_1, portsEOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_2 = or(_portsEOI_in_2_e_ready_T, _portsEOI_in_2_e_ready_T_1) wire _portsEOI_in_2_e_ready_WIRE : UInt<1> connect _portsEOI_in_2_e_ready_WIRE, _portsEOI_in_2_e_ready_T_2 connect in[2].e.ready, _portsEOI_in_2_e_ready_WIRE wire portsEOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_3[0].bits, in[3].e.bits node _portsEOI_filtered_0_valid_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_0_valid_T_6) connect portsEOI_filtered_3[0].valid, _portsEOI_filtered_0_valid_T_7 connect portsEOI_filtered_3[1].bits, in[3].e.bits node _portsEOI_filtered_1_valid_T_6 = or(requestEIO_3_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_1_valid_T_6) connect portsEOI_filtered_3[1].valid, _portsEOI_filtered_1_valid_T_7 node _portsEOI_in_3_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsEOI_in_3_e_ready_T_1 = mux(requestEIO_3_1, portsEOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsEOI_in_3_e_ready_T_2 = or(_portsEOI_in_3_e_ready_T, _portsEOI_in_3_e_ready_T_1) wire _portsEOI_in_3_e_ready_WIRE : UInt<1> connect _portsEOI_in_3_e_ready_WIRE, _portsEOI_in_3_e_ready_T_2 connect in[3].e.ready, _portsEOI_in_3_e_ready_WIRE wire portsEOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_4[0].bits, in[4].e.bits node _portsEOI_filtered_0_valid_T_8 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_0_valid_T_8) connect portsEOI_filtered_4[0].valid, _portsEOI_filtered_0_valid_T_9 connect portsEOI_filtered_4[1].bits, in[4].e.bits node _portsEOI_filtered_1_valid_T_8 = or(requestEIO_4_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_1_valid_T_8) connect portsEOI_filtered_4[1].valid, _portsEOI_filtered_1_valid_T_9 node _portsEOI_in_4_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsEOI_in_4_e_ready_T_1 = mux(requestEIO_4_1, portsEOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsEOI_in_4_e_ready_T_2 = or(_portsEOI_in_4_e_ready_T, _portsEOI_in_4_e_ready_T_1) wire _portsEOI_in_4_e_ready_WIRE : UInt<1> connect _portsEOI_in_4_e_ready_WIRE, _portsEOI_in_4_e_ready_T_2 connect in[4].e.ready, _portsEOI_in_4_e_ready_WIRE regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node readys_lo = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_hi_hi = cat(portsAOI_filtered_4[0].valid, portsAOI_filtered_3[0].valid) node readys_hi = cat(readys_hi_hi, portsAOI_filtered_2[0].valid) node _readys_T = cat(readys_hi, readys_lo) node readys_valid = bits(_readys_T, 4, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<5>, clock, reset, UInt<5>(0h1f) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) node _readys_unready_T_4 = shr(_readys_unready_T_3, 4) node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_unready_T_6 = bits(_readys_unready_T_5, 9, 0) node _readys_unready_T_7 = shr(_readys_unready_T_6, 1) node _readys_unready_T_8 = shl(readys_mask, 5) node readys_unready = or(_readys_unready_T_7, _readys_unready_T_8) node _readys_readys_T = shr(readys_unready, 5) node _readys_readys_T_1 = bits(readys_unready, 4, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 4, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) node _readys_mask_T_5 = bits(_readys_mask_T_4, 4, 0) node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) node _readys_mask_T_7 = shl(_readys_mask_T_6, 4) node _readys_mask_T_8 = bits(_readys_mask_T_7, 4, 0) node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8) node _readys_mask_T_10 = bits(_readys_mask_T_9, 4, 0) connect readys_mask, _readys_mask_T_10 node _readys_T_7 = bits(readys_readys, 4, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) node _readys_T_10 = bits(_readys_T_7, 2, 2) node _readys_T_11 = bits(_readys_T_7, 3, 3) node _readys_T_12 = bits(_readys_T_7, 4, 4) wire readys : UInt<1>[5] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 connect readys[2], _readys_T_10 connect readys[3], _readys_T_11 connect readys[4], _readys_T_12 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid) node _winner_T_3 = and(readys[3], portsAOI_filtered_3[0].valid) node _winner_T_4 = and(readys[4], portsAOI_filtered_4[0].valid) wire winner : UInt<1>[5] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 connect winner[3], _winner_T_3 connect winner[4], _winner_T_4 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node prefixOR_3 = or(prefixOR_2, winner[2]) node prefixOR_4 = or(prefixOR_3, winner[3]) node _prefixOR_T = or(prefixOR_4, winner[4]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) node _T_7 = eq(winner[2], UInt<1>(0h0)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(prefixOR_3, UInt<1>(0h0)) node _T_10 = eq(winner[3], UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = eq(prefixOR_4, UInt<1>(0h0)) node _T_13 = eq(winner[4], UInt<1>(0h0)) node _T_14 = or(_T_12, _T_13) node _T_15 = and(_T_2, _T_5) node _T_16 = and(_T_15, _T_8) node _T_17 = and(_T_16, _T_11) node _T_18 = and(_T_17, _T_14) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert node _T_22 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_23 = or(_T_22, portsAOI_filtered_2[0].valid) node _T_24 = or(_T_23, portsAOI_filtered_3[0].valid) node _T_25 = or(_T_24, portsAOI_filtered_4[0].valid) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = or(winner[0], winner[1]) node _T_28 = or(_T_27, winner[2]) node _T_29 = or(_T_28, winner[3]) node _T_30 = or(_T_29, winner[4]) node _T_31 = or(_T_26, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_31, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0)) node maskedBeats_3 = mux(winner[3], beatsAI_3, UInt<1>(0h0)) node maskedBeats_4 = mux(winner[4], beatsAI_4, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2) node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3) node initBeats = or(_initBeats_T_2, maskedBeats_4) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[5] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) connect _state_WIRE[3], UInt<1>(0h0) connect _state_WIRE[4], UInt<1>(0h0) regreset state : UInt<1>[5], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2]) connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2 node _filtered_0_ready_T_3 = and(out[0].a.ready, allowed[3]) connect portsAOI_filtered_3[0].ready, _filtered_0_ready_T_3 node _filtered_0_ready_T_4 = and(out[0].a.ready, allowed[4]) connect portsAOI_filtered_4[0].ready, _filtered_0_ready_T_4 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid) node _out_0_a_valid_T_2 = or(_out_0_a_valid_T_1, portsAOI_filtered_3[0].valid) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_2, portsAOI_filtered_4[0].valid) node _out_0_a_valid_T_4 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_5 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_6 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_7 = mux(state[3], portsAOI_filtered_3[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_8 = mux(state[4], portsAOI_filtered_4[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_9 = or(_out_0_a_valid_T_4, _out_0_a_valid_T_5) node _out_0_a_valid_T_10 = or(_out_0_a_valid_T_9, _out_0_a_valid_T_6) node _out_0_a_valid_T_11 = or(_out_0_a_valid_T_10, _out_0_a_valid_T_7) node _out_0_a_valid_T_12 = or(_out_0_a_valid_T_11, _out_0_a_valid_T_8) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_12 node _out_0_a_valid_T_13 = mux(idle, _out_0_a_valid_T_3, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_13 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_3 = mux(muxState[3], portsAOI_filtered_3[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[4], portsAOI_filtered_4[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) node _out_0_a_bits_T_6 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_2) node _out_0_a_bits_T_7 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_3) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_7, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_11 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_12 = mux(muxState[3], portsAOI_filtered_3[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[4], portsAOI_filtered_4[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) node _out_0_a_bits_T_15 = or(_out_0_a_bits_T_14, _out_0_a_bits_T_11) node _out_0_a_bits_T_16 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_12) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_16, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_2 : UInt<128> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_20 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_21 = mux(muxState[3], portsAOI_filtered_3[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[4], portsAOI_filtered_4[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_20) node _out_0_a_bits_T_25 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_21) node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_3 : UInt<16> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_26 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_29 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_30 = mux(muxState[3], portsAOI_filtered_3[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_31 = mux(muxState[4], portsAOI_filtered_4[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_32, _out_0_a_bits_T_29) node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_30) node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_34, _out_0_a_bits_T_31) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_35 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_38 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_39 = mux(muxState[3], portsAOI_filtered_3[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_40 = mux(muxState[4], portsAOI_filtered_4[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) node _out_0_a_bits_T_42 = or(_out_0_a_bits_T_41, _out_0_a_bits_T_38) node _out_0_a_bits_T_43 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_39) node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_43, _out_0_a_bits_T_40) wire _out_0_a_bits_WIRE_7 : UInt<7> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_44 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_45 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_46 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_47 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_48 = mux(muxState[3], portsAOI_filtered_3[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_49 = mux(muxState[4], portsAOI_filtered_4[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_50 = or(_out_0_a_bits_T_45, _out_0_a_bits_T_46) node _out_0_a_bits_T_51 = or(_out_0_a_bits_T_50, _out_0_a_bits_T_47) node _out_0_a_bits_T_52 = or(_out_0_a_bits_T_51, _out_0_a_bits_T_48) node _out_0_a_bits_T_53 = or(_out_0_a_bits_T_52, _out_0_a_bits_T_49) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_53 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_54 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_55 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_56 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_57 = mux(muxState[3], portsAOI_filtered_3[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_58 = mux(muxState[4], portsAOI_filtered_4[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_59 = or(_out_0_a_bits_T_54, _out_0_a_bits_T_55) node _out_0_a_bits_T_60 = or(_out_0_a_bits_T_59, _out_0_a_bits_T_56) node _out_0_a_bits_T_61 = or(_out_0_a_bits_T_60, _out_0_a_bits_T_57) node _out_0_a_bits_T_62 = or(_out_0_a_bits_T_61, _out_0_a_bits_T_58) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_62 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_63 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_64 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_65 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_66 = mux(muxState[3], portsAOI_filtered_3[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_67 = mux(muxState[4], portsAOI_filtered_4[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_68 = or(_out_0_a_bits_T_63, _out_0_a_bits_T_64) node _out_0_a_bits_T_69 = or(_out_0_a_bits_T_68, _out_0_a_bits_T_65) node _out_0_a_bits_T_70 = or(_out_0_a_bits_T_69, _out_0_a_bits_T_66) node _out_0_a_bits_T_71 = or(_out_0_a_bits_T_70, _out_0_a_bits_T_67) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_71 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].e.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsCOI_filtered_2[0].ready, UInt<1>(0h0) connect portsCOI_filtered_3[0].ready, UInt<1>(0h0) connect portsCOI_filtered_4[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_2[0].ready, UInt<1>(0h0) connect portsEOI_filtered_3[0].ready, UInt<1>(0h0) connect portsEOI_filtered_4[0].ready, UInt<1>(0h0) regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, out[1].a.ready) node readys_lo_1 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid) node readys_hi_hi_1 = cat(portsAOI_filtered_4[1].valid, portsAOI_filtered_3[1].valid) node readys_hi_1 = cat(readys_hi_hi_1, portsAOI_filtered_2[1].valid) node _readys_T_13 = cat(readys_hi_1, readys_lo_1) node readys_valid_1 = bits(_readys_T_13, 4, 0) node _readys_T_14 = eq(readys_valid_1, _readys_T_13) node _readys_T_15 = asUInt(reset) node _readys_T_16 = eq(_readys_T_15, UInt<1>(0h0)) when _readys_T_16 : node _readys_T_17 = eq(_readys_T_14, UInt<1>(0h0)) when _readys_T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1 assert(clock, _readys_T_14, UInt<1>(0h1), "") : readys_assert_1 regreset readys_mask_1 : UInt<5>, clock, reset, UInt<5>(0h1f) node _readys_filter_T_2 = not(readys_mask_1) node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2) node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1) node _readys_unready_T_9 = shr(readys_filter_1, 1) node _readys_unready_T_10 = or(readys_filter_1, _readys_unready_T_9) node _readys_unready_T_11 = shr(_readys_unready_T_10, 2) node _readys_unready_T_12 = or(_readys_unready_T_10, _readys_unready_T_11) node _readys_unready_T_13 = shr(_readys_unready_T_12, 4) node _readys_unready_T_14 = or(_readys_unready_T_12, _readys_unready_T_13) node _readys_unready_T_15 = bits(_readys_unready_T_14, 9, 0) node _readys_unready_T_16 = shr(_readys_unready_T_15, 1) node _readys_unready_T_17 = shl(readys_mask_1, 5) node readys_unready_1 = or(_readys_unready_T_16, _readys_unready_T_17) node _readys_readys_T_3 = shr(readys_unready_1, 5) node _readys_readys_T_4 = bits(readys_unready_1, 4, 0) node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4) node readys_readys_1 = not(_readys_readys_T_5) node _readys_T_18 = orr(readys_valid_1) node _readys_T_19 = and(latch_1, _readys_T_18) when _readys_T_19 : node _readys_mask_T_11 = and(readys_readys_1, readys_valid_1) node _readys_mask_T_12 = shl(_readys_mask_T_11, 1) node _readys_mask_T_13 = bits(_readys_mask_T_12, 4, 0) node _readys_mask_T_14 = or(_readys_mask_T_11, _readys_mask_T_13) node _readys_mask_T_15 = shl(_readys_mask_T_14, 2) node _readys_mask_T_16 = bits(_readys_mask_T_15, 4, 0) node _readys_mask_T_17 = or(_readys_mask_T_14, _readys_mask_T_16) node _readys_mask_T_18 = shl(_readys_mask_T_17, 4) node _readys_mask_T_19 = bits(_readys_mask_T_18, 4, 0) node _readys_mask_T_20 = or(_readys_mask_T_17, _readys_mask_T_19) node _readys_mask_T_21 = bits(_readys_mask_T_20, 4, 0) connect readys_mask_1, _readys_mask_T_21 node _readys_T_20 = bits(readys_readys_1, 4, 0) node _readys_T_21 = bits(_readys_T_20, 0, 0) node _readys_T_22 = bits(_readys_T_20, 1, 1) node _readys_T_23 = bits(_readys_T_20, 2, 2) node _readys_T_24 = bits(_readys_T_20, 3, 3) node _readys_T_25 = bits(_readys_T_20, 4, 4) wire readys_1 : UInt<1>[5] connect readys_1[0], _readys_T_21 connect readys_1[1], _readys_T_22 connect readys_1[2], _readys_T_23 connect readys_1[3], _readys_T_24 connect readys_1[4], _readys_T_25 node _winner_T_5 = and(readys_1[0], portsAOI_filtered[1].valid) node _winner_T_6 = and(readys_1[1], portsAOI_filtered_1[1].valid) node _winner_T_7 = and(readys_1[2], portsAOI_filtered_2[1].valid) node _winner_T_8 = and(readys_1[3], portsAOI_filtered_3[1].valid) node _winner_T_9 = and(readys_1[4], portsAOI_filtered_4[1].valid) wire winner_1 : UInt<1>[5] connect winner_1[0], _winner_T_5 connect winner_1[1], _winner_T_6 connect winner_1[2], _winner_T_7 connect winner_1[3], _winner_T_8 connect winner_1[4], _winner_T_9 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node prefixOR_2_1 = or(prefixOR_1_1, winner_1[1]) node prefixOR_3_1 = or(prefixOR_2_1, winner_1[2]) node prefixOR_4_1 = or(prefixOR_3_1, winner_1[3]) node _prefixOR_T_1 = or(prefixOR_4_1, winner_1[4]) node _T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_36 = eq(winner_1[0], UInt<1>(0h0)) node _T_37 = or(_T_35, _T_36) node _T_38 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_39 = eq(winner_1[1], UInt<1>(0h0)) node _T_40 = or(_T_38, _T_39) node _T_41 = eq(prefixOR_2_1, UInt<1>(0h0)) node _T_42 = eq(winner_1[2], UInt<1>(0h0)) node _T_43 = or(_T_41, _T_42) node _T_44 = eq(prefixOR_3_1, UInt<1>(0h0)) node _T_45 = eq(winner_1[3], UInt<1>(0h0)) node _T_46 = or(_T_44, _T_45) node _T_47 = eq(prefixOR_4_1, UInt<1>(0h0)) node _T_48 = eq(winner_1[4], UInt<1>(0h0)) node _T_49 = or(_T_47, _T_48) node _T_50 = and(_T_37, _T_40) node _T_51 = and(_T_50, _T_43) node _T_52 = and(_T_51, _T_46) node _T_53 = and(_T_52, _T_49) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_53, UInt<1>(0h1), "") : assert_2 node _T_57 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _T_58 = or(_T_57, portsAOI_filtered_2[1].valid) node _T_59 = or(_T_58, portsAOI_filtered_3[1].valid) node _T_60 = or(_T_59, portsAOI_filtered_4[1].valid) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = or(winner_1[0], winner_1[1]) node _T_63 = or(_T_62, winner_1[2]) node _T_64 = or(_T_63, winner_1[3]) node _T_65 = or(_T_64, winner_1[4]) node _T_66 = or(_T_61, _T_65) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_3 assert(clock, _T_66, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2_1 = mux(winner_1[2], beatsAI_2, UInt<1>(0h0)) node maskedBeats_3_1 = mux(winner_1[3], beatsAI_3, UInt<1>(0h0)) node maskedBeats_4_1 = mux(winner_1[4], beatsAI_4, UInt<1>(0h0)) node _initBeats_T_3 = or(maskedBeats_0_1, maskedBeats_1_1) node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_2_1) node _initBeats_T_5 = or(_initBeats_T_4, maskedBeats_3_1) node initBeats_1 = or(_initBeats_T_5, maskedBeats_4_1) node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[5] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) connect _state_WIRE_1[2], UInt<1>(0h0) connect _state_WIRE_1[3], UInt<1>(0h0) connect _state_WIRE_1[4], UInt<1>(0h0) regreset state_1 : UInt<1>[5], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0]) connect portsAOI_filtered[1].ready, _filtered_1_ready_T node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1]) connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1 node _filtered_1_ready_T_2 = and(out[1].a.ready, allowed_1[2]) connect portsAOI_filtered_2[1].ready, _filtered_1_ready_T_2 node _filtered_1_ready_T_3 = and(out[1].a.ready, allowed_1[3]) connect portsAOI_filtered_3[1].ready, _filtered_1_ready_T_3 node _filtered_1_ready_T_4 = and(out[1].a.ready, allowed_1[4]) connect portsAOI_filtered_4[1].ready, _filtered_1_ready_T_4 node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _out_1_a_valid_T_1 = or(_out_1_a_valid_T, portsAOI_filtered_2[1].valid) node _out_1_a_valid_T_2 = or(_out_1_a_valid_T_1, portsAOI_filtered_3[1].valid) node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_2, portsAOI_filtered_4[1].valid) node _out_1_a_valid_T_4 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_5 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_6 = mux(state_1[2], portsAOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_7 = mux(state_1[3], portsAOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_8 = mux(state_1[4], portsAOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_9 = or(_out_1_a_valid_T_4, _out_1_a_valid_T_5) node _out_1_a_valid_T_10 = or(_out_1_a_valid_T_9, _out_1_a_valid_T_6) node _out_1_a_valid_T_11 = or(_out_1_a_valid_T_10, _out_1_a_valid_T_7) node _out_1_a_valid_T_12 = or(_out_1_a_valid_T_11, _out_1_a_valid_T_8) wire _out_1_a_valid_WIRE : UInt<1> connect _out_1_a_valid_WIRE, _out_1_a_valid_T_12 node _out_1_a_valid_T_13 = mux(idle_1, _out_1_a_valid_T_3, _out_1_a_valid_WIRE) connect out[1].a.valid, _out_1_a_valid_T_13 wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_2 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_3 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_4 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_5 = or(_out_1_a_bits_T, _out_1_a_bits_T_1) node _out_1_a_bits_T_6 = or(_out_1_a_bits_T_5, _out_1_a_bits_T_2) node _out_1_a_bits_T_7 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_3) node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_7, _out_1_a_bits_T_4) wire _out_1_a_bits_WIRE_1 : UInt<1> connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_8 connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1 node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_11 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_12 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_13 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10) node _out_1_a_bits_T_15 = or(_out_1_a_bits_T_14, _out_1_a_bits_T_11) node _out_1_a_bits_T_16 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_12) node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_16, _out_1_a_bits_T_13) wire _out_1_a_bits_WIRE_2 : UInt<128> connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_17 connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2 node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_20 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_21 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_22 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19) node _out_1_a_bits_T_24 = or(_out_1_a_bits_T_23, _out_1_a_bits_T_20) node _out_1_a_bits_T_25 = or(_out_1_a_bits_T_24, _out_1_a_bits_T_21) node _out_1_a_bits_T_26 = or(_out_1_a_bits_T_25, _out_1_a_bits_T_22) wire _out_1_a_bits_WIRE_3 : UInt<16> connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_26 connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3 wire _out_1_a_bits_WIRE_4 : { } connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4 wire _out_1_a_bits_WIRE_5 : { } connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5 node _out_1_a_bits_T_27 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_28 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_29 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_30 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_31 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_32 = or(_out_1_a_bits_T_27, _out_1_a_bits_T_28) node _out_1_a_bits_T_33 = or(_out_1_a_bits_T_32, _out_1_a_bits_T_29) node _out_1_a_bits_T_34 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_30) node _out_1_a_bits_T_35 = or(_out_1_a_bits_T_34, _out_1_a_bits_T_31) wire _out_1_a_bits_WIRE_6 : UInt<32> connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_35 connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6 node _out_1_a_bits_T_36 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_37 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_38 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_39 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_40 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_41 = or(_out_1_a_bits_T_36, _out_1_a_bits_T_37) node _out_1_a_bits_T_42 = or(_out_1_a_bits_T_41, _out_1_a_bits_T_38) node _out_1_a_bits_T_43 = or(_out_1_a_bits_T_42, _out_1_a_bits_T_39) node _out_1_a_bits_T_44 = or(_out_1_a_bits_T_43, _out_1_a_bits_T_40) wire _out_1_a_bits_WIRE_7 : UInt<7> connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_44 connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7 node _out_1_a_bits_T_45 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_46 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_47 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_48 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_49 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_50 = or(_out_1_a_bits_T_45, _out_1_a_bits_T_46) node _out_1_a_bits_T_51 = or(_out_1_a_bits_T_50, _out_1_a_bits_T_47) node _out_1_a_bits_T_52 = or(_out_1_a_bits_T_51, _out_1_a_bits_T_48) node _out_1_a_bits_T_53 = or(_out_1_a_bits_T_52, _out_1_a_bits_T_49) wire _out_1_a_bits_WIRE_8 : UInt<4> connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_53 connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8 node _out_1_a_bits_T_54 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_55 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_56 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_57 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_58 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_59 = or(_out_1_a_bits_T_54, _out_1_a_bits_T_55) node _out_1_a_bits_T_60 = or(_out_1_a_bits_T_59, _out_1_a_bits_T_56) node _out_1_a_bits_T_61 = or(_out_1_a_bits_T_60, _out_1_a_bits_T_57) node _out_1_a_bits_T_62 = or(_out_1_a_bits_T_61, _out_1_a_bits_T_58) wire _out_1_a_bits_WIRE_9 : UInt<3> connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_62 connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9 node _out_1_a_bits_T_63 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_64 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_65 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_66 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_67 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_68 = or(_out_1_a_bits_T_63, _out_1_a_bits_T_64) node _out_1_a_bits_T_69 = or(_out_1_a_bits_T_68, _out_1_a_bits_T_65) node _out_1_a_bits_T_70 = or(_out_1_a_bits_T_69, _out_1_a_bits_T_66) node _out_1_a_bits_T_71 = or(_out_1_a_bits_T_70, _out_1_a_bits_T_67) wire _out_1_a_bits_WIRE_10 : UInt<3> connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_71 connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10 connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt connect out[1].a.bits.data, _out_1_a_bits_WIRE.data connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask connect out[1].a.bits.address, _out_1_a_bits_WIRE.address connect out[1].a.bits.source, _out_1_a_bits_WIRE.source connect out[1].a.bits.size, _out_1_a_bits_WIRE.size connect out[1].a.bits.param, _out_1_a_bits_WIRE.param connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0) node idle_2 = eq(beatsLeft_2, UInt<1>(0h0)) node latch_2 = and(idle_2, out[1].c.ready) node readys_lo_2 = cat(portsCOI_filtered_2[1].valid, portsCOI_filtered_1[1].valid) node readys_hi_2 = cat(portsCOI_filtered_4[1].valid, portsCOI_filtered_3[1].valid) node _readys_T_26 = cat(readys_hi_2, readys_lo_2) node readys_valid_2 = bits(_readys_T_26, 3, 0) node _readys_T_27 = eq(readys_valid_2, _readys_T_26) node _readys_T_28 = asUInt(reset) node _readys_T_29 = eq(_readys_T_28, UInt<1>(0h0)) when _readys_T_29 : node _readys_T_30 = eq(_readys_T_27, UInt<1>(0h0)) when _readys_T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2 assert(clock, _readys_T_27, UInt<1>(0h1), "") : readys_assert_2 regreset readys_mask_2 : UInt<4>, clock, reset, UInt<4>(0hf) node _readys_filter_T_4 = not(readys_mask_2) node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4) node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2) node _readys_unready_T_18 = shr(readys_filter_2, 1) node _readys_unready_T_19 = or(readys_filter_2, _readys_unready_T_18) node _readys_unready_T_20 = shr(_readys_unready_T_19, 2) node _readys_unready_T_21 = or(_readys_unready_T_19, _readys_unready_T_20) node _readys_unready_T_22 = bits(_readys_unready_T_21, 7, 0) node _readys_unready_T_23 = shr(_readys_unready_T_22, 1) node _readys_unready_T_24 = shl(readys_mask_2, 4) node readys_unready_2 = or(_readys_unready_T_23, _readys_unready_T_24) node _readys_readys_T_6 = shr(readys_unready_2, 4) node _readys_readys_T_7 = bits(readys_unready_2, 3, 0) node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7) node readys_readys_2 = not(_readys_readys_T_8) node _readys_T_31 = orr(readys_valid_2) node _readys_T_32 = and(latch_2, _readys_T_31) when _readys_T_32 : node _readys_mask_T_22 = and(readys_readys_2, readys_valid_2) node _readys_mask_T_23 = shl(_readys_mask_T_22, 1) node _readys_mask_T_24 = bits(_readys_mask_T_23, 3, 0) node _readys_mask_T_25 = or(_readys_mask_T_22, _readys_mask_T_24) node _readys_mask_T_26 = shl(_readys_mask_T_25, 2) node _readys_mask_T_27 = bits(_readys_mask_T_26, 3, 0) node _readys_mask_T_28 = or(_readys_mask_T_25, _readys_mask_T_27) node _readys_mask_T_29 = bits(_readys_mask_T_28, 3, 0) connect readys_mask_2, _readys_mask_T_29 node _readys_T_33 = bits(readys_readys_2, 3, 0) node _readys_T_34 = bits(_readys_T_33, 0, 0) node _readys_T_35 = bits(_readys_T_33, 1, 1) node _readys_T_36 = bits(_readys_T_33, 2, 2) node _readys_T_37 = bits(_readys_T_33, 3, 3) wire readys_2 : UInt<1>[4] connect readys_2[0], _readys_T_34 connect readys_2[1], _readys_T_35 connect readys_2[2], _readys_T_36 connect readys_2[3], _readys_T_37 node _winner_T_10 = and(readys_2[0], portsCOI_filtered_1[1].valid) node _winner_T_11 = and(readys_2[1], portsCOI_filtered_2[1].valid) node _winner_T_12 = and(readys_2[2], portsCOI_filtered_3[1].valid) node _winner_T_13 = and(readys_2[3], portsCOI_filtered_4[1].valid) wire winner_2 : UInt<1>[4] connect winner_2[0], _winner_T_10 connect winner_2[1], _winner_T_11 connect winner_2[2], _winner_T_12 connect winner_2[3], _winner_T_13 node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0]) node prefixOR_2_2 = or(prefixOR_1_2, winner_2[1]) node prefixOR_3_2 = or(prefixOR_2_2, winner_2[2]) node _prefixOR_T_2 = or(prefixOR_3_2, winner_2[3]) node _T_70 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_71 = eq(winner_2[0], UInt<1>(0h0)) node _T_72 = or(_T_70, _T_71) node _T_73 = eq(prefixOR_1_2, UInt<1>(0h0)) node _T_74 = eq(winner_2[1], UInt<1>(0h0)) node _T_75 = or(_T_73, _T_74) node _T_76 = eq(prefixOR_2_2, UInt<1>(0h0)) node _T_77 = eq(winner_2[2], UInt<1>(0h0)) node _T_78 = or(_T_76, _T_77) node _T_79 = eq(prefixOR_3_2, UInt<1>(0h0)) node _T_80 = eq(winner_2[3], UInt<1>(0h0)) node _T_81 = or(_T_79, _T_80) node _T_82 = and(_T_72, _T_75) node _T_83 = and(_T_82, _T_78) node _T_84 = and(_T_83, _T_81) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_84, UInt<1>(0h1), "") : assert_4 node _T_88 = or(portsCOI_filtered_1[1].valid, portsCOI_filtered_2[1].valid) node _T_89 = or(_T_88, portsCOI_filtered_3[1].valid) node _T_90 = or(_T_89, portsCOI_filtered_4[1].valid) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = or(winner_2[0], winner_2[1]) node _T_93 = or(_T_92, winner_2[2]) node _T_94 = or(_T_93, winner_2[3]) node _T_95 = or(_T_91, _T_94) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_5 assert(clock, _T_95, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_2 = mux(winner_2[0], beatsCI_1, UInt<1>(0h0)) node maskedBeats_1_2 = mux(winner_2[1], beatsCI_2, UInt<1>(0h0)) node maskedBeats_2_2 = mux(winner_2[2], beatsCI_3, UInt<1>(0h0)) node maskedBeats_3_2 = mux(winner_2[3], beatsCI_4, UInt<1>(0h0)) node _initBeats_T_6 = or(maskedBeats_0_2, maskedBeats_1_2) node _initBeats_T_7 = or(_initBeats_T_6, maskedBeats_2_2) node initBeats_2 = or(_initBeats_T_7, maskedBeats_3_2) node _beatsLeft_T_8 = and(out[1].c.ready, out[1].c.valid) node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8) node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1) node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10) connect beatsLeft_2, _beatsLeft_T_11 wire _state_WIRE_2 : UInt<1>[4] connect _state_WIRE_2[0], UInt<1>(0h0) connect _state_WIRE_2[1], UInt<1>(0h0) connect _state_WIRE_2[2], UInt<1>(0h0) connect _state_WIRE_2[3], UInt<1>(0h0) regreset state_2 : UInt<1>[4], clock, reset, _state_WIRE_2 node muxState_2 = mux(idle_2, winner_2, state_2) connect state_2, muxState_2 node allowed_2 = mux(idle_2, readys_2, state_2) node _filtered_1_ready_T_5 = and(out[1].c.ready, allowed_2[0]) connect portsCOI_filtered_1[1].ready, _filtered_1_ready_T_5 node _filtered_1_ready_T_6 = and(out[1].c.ready, allowed_2[1]) connect portsCOI_filtered_2[1].ready, _filtered_1_ready_T_6 node _filtered_1_ready_T_7 = and(out[1].c.ready, allowed_2[2]) connect portsCOI_filtered_3[1].ready, _filtered_1_ready_T_7 node _filtered_1_ready_T_8 = and(out[1].c.ready, allowed_2[3]) connect portsCOI_filtered_4[1].ready, _filtered_1_ready_T_8 node _out_1_c_valid_T = or(portsCOI_filtered_1[1].valid, portsCOI_filtered_2[1].valid) node _out_1_c_valid_T_1 = or(_out_1_c_valid_T, portsCOI_filtered_3[1].valid) node _out_1_c_valid_T_2 = or(_out_1_c_valid_T_1, portsCOI_filtered_4[1].valid) node _out_1_c_valid_T_3 = mux(state_2[0], portsCOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_4 = mux(state_2[1], portsCOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_5 = mux(state_2[2], portsCOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_6 = mux(state_2[3], portsCOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_7 = or(_out_1_c_valid_T_3, _out_1_c_valid_T_4) node _out_1_c_valid_T_8 = or(_out_1_c_valid_T_7, _out_1_c_valid_T_5) node _out_1_c_valid_T_9 = or(_out_1_c_valid_T_8, _out_1_c_valid_T_6) wire _out_1_c_valid_WIRE : UInt<1> connect _out_1_c_valid_WIRE, _out_1_c_valid_T_9 node _out_1_c_valid_T_10 = mux(idle_2, _out_1_c_valid_T_2, _out_1_c_valid_WIRE) connect out[1].c.valid, _out_1_c_valid_T_10 wire _out_1_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _out_1_c_bits_T = mux(muxState_2[0], portsCOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_1 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_2 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_3 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_4 = or(_out_1_c_bits_T, _out_1_c_bits_T_1) node _out_1_c_bits_T_5 = or(_out_1_c_bits_T_4, _out_1_c_bits_T_2) node _out_1_c_bits_T_6 = or(_out_1_c_bits_T_5, _out_1_c_bits_T_3) wire _out_1_c_bits_WIRE_1 : UInt<1> connect _out_1_c_bits_WIRE_1, _out_1_c_bits_T_6 connect _out_1_c_bits_WIRE.corrupt, _out_1_c_bits_WIRE_1 node _out_1_c_bits_T_7 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_8 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_9 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_10 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_11 = or(_out_1_c_bits_T_7, _out_1_c_bits_T_8) node _out_1_c_bits_T_12 = or(_out_1_c_bits_T_11, _out_1_c_bits_T_9) node _out_1_c_bits_T_13 = or(_out_1_c_bits_T_12, _out_1_c_bits_T_10) wire _out_1_c_bits_WIRE_2 : UInt<128> connect _out_1_c_bits_WIRE_2, _out_1_c_bits_T_13 connect _out_1_c_bits_WIRE.data, _out_1_c_bits_WIRE_2 wire _out_1_c_bits_WIRE_3 : { } connect _out_1_c_bits_WIRE.echo, _out_1_c_bits_WIRE_3 wire _out_1_c_bits_WIRE_4 : { } connect _out_1_c_bits_WIRE.user, _out_1_c_bits_WIRE_4 node _out_1_c_bits_T_14 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_15 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_16 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_17 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_18 = or(_out_1_c_bits_T_14, _out_1_c_bits_T_15) node _out_1_c_bits_T_19 = or(_out_1_c_bits_T_18, _out_1_c_bits_T_16) node _out_1_c_bits_T_20 = or(_out_1_c_bits_T_19, _out_1_c_bits_T_17) wire _out_1_c_bits_WIRE_5 : UInt<32> connect _out_1_c_bits_WIRE_5, _out_1_c_bits_T_20 connect _out_1_c_bits_WIRE.address, _out_1_c_bits_WIRE_5 node _out_1_c_bits_T_21 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_22 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_23 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_24 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_25 = or(_out_1_c_bits_T_21, _out_1_c_bits_T_22) node _out_1_c_bits_T_26 = or(_out_1_c_bits_T_25, _out_1_c_bits_T_23) node _out_1_c_bits_T_27 = or(_out_1_c_bits_T_26, _out_1_c_bits_T_24) wire _out_1_c_bits_WIRE_6 : UInt<7> connect _out_1_c_bits_WIRE_6, _out_1_c_bits_T_27 connect _out_1_c_bits_WIRE.source, _out_1_c_bits_WIRE_6 node _out_1_c_bits_T_28 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_29 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_30 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_31 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_32 = or(_out_1_c_bits_T_28, _out_1_c_bits_T_29) node _out_1_c_bits_T_33 = or(_out_1_c_bits_T_32, _out_1_c_bits_T_30) node _out_1_c_bits_T_34 = or(_out_1_c_bits_T_33, _out_1_c_bits_T_31) wire _out_1_c_bits_WIRE_7 : UInt<4> connect _out_1_c_bits_WIRE_7, _out_1_c_bits_T_34 connect _out_1_c_bits_WIRE.size, _out_1_c_bits_WIRE_7 node _out_1_c_bits_T_35 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_36 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_37 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_38 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_39 = or(_out_1_c_bits_T_35, _out_1_c_bits_T_36) node _out_1_c_bits_T_40 = or(_out_1_c_bits_T_39, _out_1_c_bits_T_37) node _out_1_c_bits_T_41 = or(_out_1_c_bits_T_40, _out_1_c_bits_T_38) wire _out_1_c_bits_WIRE_8 : UInt<3> connect _out_1_c_bits_WIRE_8, _out_1_c_bits_T_41 connect _out_1_c_bits_WIRE.param, _out_1_c_bits_WIRE_8 node _out_1_c_bits_T_42 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_43 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_44 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_45 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_46 = or(_out_1_c_bits_T_42, _out_1_c_bits_T_43) node _out_1_c_bits_T_47 = or(_out_1_c_bits_T_46, _out_1_c_bits_T_44) node _out_1_c_bits_T_48 = or(_out_1_c_bits_T_47, _out_1_c_bits_T_45) wire _out_1_c_bits_WIRE_9 : UInt<3> connect _out_1_c_bits_WIRE_9, _out_1_c_bits_T_48 connect _out_1_c_bits_WIRE.opcode, _out_1_c_bits_WIRE_9 connect out[1].c.bits.corrupt, _out_1_c_bits_WIRE.corrupt connect out[1].c.bits.data, _out_1_c_bits_WIRE.data connect out[1].c.bits.address, _out_1_c_bits_WIRE.address connect out[1].c.bits.source, _out_1_c_bits_WIRE.source connect out[1].c.bits.size, _out_1_c_bits_WIRE.size connect out[1].c.bits.param, _out_1_c_bits_WIRE.param connect out[1].c.bits.opcode, _out_1_c_bits_WIRE.opcode regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0) node idle_3 = eq(beatsLeft_3, UInt<1>(0h0)) node latch_3 = and(idle_3, out[1].e.ready) node readys_lo_3 = cat(portsEOI_filtered_2[1].valid, portsEOI_filtered_1[1].valid) node readys_hi_3 = cat(portsEOI_filtered_4[1].valid, portsEOI_filtered_3[1].valid) node _readys_T_38 = cat(readys_hi_3, readys_lo_3) node readys_valid_3 = bits(_readys_T_38, 3, 0) node _readys_T_39 = eq(readys_valid_3, _readys_T_38) node _readys_T_40 = asUInt(reset) node _readys_T_41 = eq(_readys_T_40, UInt<1>(0h0)) when _readys_T_41 : node _readys_T_42 = eq(_readys_T_39, UInt<1>(0h0)) when _readys_T_42 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3 assert(clock, _readys_T_39, UInt<1>(0h1), "") : readys_assert_3 regreset readys_mask_3 : UInt<4>, clock, reset, UInt<4>(0hf) node _readys_filter_T_6 = not(readys_mask_3) node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6) node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3) node _readys_unready_T_25 = shr(readys_filter_3, 1) node _readys_unready_T_26 = or(readys_filter_3, _readys_unready_T_25) node _readys_unready_T_27 = shr(_readys_unready_T_26, 2) node _readys_unready_T_28 = or(_readys_unready_T_26, _readys_unready_T_27) node _readys_unready_T_29 = bits(_readys_unready_T_28, 7, 0) node _readys_unready_T_30 = shr(_readys_unready_T_29, 1) node _readys_unready_T_31 = shl(readys_mask_3, 4) node readys_unready_3 = or(_readys_unready_T_30, _readys_unready_T_31) node _readys_readys_T_9 = shr(readys_unready_3, 4) node _readys_readys_T_10 = bits(readys_unready_3, 3, 0) node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10) node readys_readys_3 = not(_readys_readys_T_11) node _readys_T_43 = orr(readys_valid_3) node _readys_T_44 = and(latch_3, _readys_T_43) when _readys_T_44 : node _readys_mask_T_30 = and(readys_readys_3, readys_valid_3) node _readys_mask_T_31 = shl(_readys_mask_T_30, 1) node _readys_mask_T_32 = bits(_readys_mask_T_31, 3, 0) node _readys_mask_T_33 = or(_readys_mask_T_30, _readys_mask_T_32) node _readys_mask_T_34 = shl(_readys_mask_T_33, 2) node _readys_mask_T_35 = bits(_readys_mask_T_34, 3, 0) node _readys_mask_T_36 = or(_readys_mask_T_33, _readys_mask_T_35) node _readys_mask_T_37 = bits(_readys_mask_T_36, 3, 0) connect readys_mask_3, _readys_mask_T_37 node _readys_T_45 = bits(readys_readys_3, 3, 0) node _readys_T_46 = bits(_readys_T_45, 0, 0) node _readys_T_47 = bits(_readys_T_45, 1, 1) node _readys_T_48 = bits(_readys_T_45, 2, 2) node _readys_T_49 = bits(_readys_T_45, 3, 3) wire readys_3 : UInt<1>[4] connect readys_3[0], _readys_T_46 connect readys_3[1], _readys_T_47 connect readys_3[2], _readys_T_48 connect readys_3[3], _readys_T_49 node _winner_T_14 = and(readys_3[0], portsEOI_filtered_1[1].valid) node _winner_T_15 = and(readys_3[1], portsEOI_filtered_2[1].valid) node _winner_T_16 = and(readys_3[2], portsEOI_filtered_3[1].valid) node _winner_T_17 = and(readys_3[3], portsEOI_filtered_4[1].valid) wire winner_3 : UInt<1>[4] connect winner_3[0], _winner_T_14 connect winner_3[1], _winner_T_15 connect winner_3[2], _winner_T_16 connect winner_3[3], _winner_T_17 node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0]) node prefixOR_2_3 = or(prefixOR_1_3, winner_3[1]) node prefixOR_3_3 = or(prefixOR_2_3, winner_3[2]) node _prefixOR_T_3 = or(prefixOR_3_3, winner_3[3]) node _T_99 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_100 = eq(winner_3[0], UInt<1>(0h0)) node _T_101 = or(_T_99, _T_100) node _T_102 = eq(prefixOR_1_3, UInt<1>(0h0)) node _T_103 = eq(winner_3[1], UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(prefixOR_2_3, UInt<1>(0h0)) node _T_106 = eq(winner_3[2], UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) node _T_108 = eq(prefixOR_3_3, UInt<1>(0h0)) node _T_109 = eq(winner_3[3], UInt<1>(0h0)) node _T_110 = or(_T_108, _T_109) node _T_111 = and(_T_101, _T_104) node _T_112 = and(_T_111, _T_107) node _T_113 = and(_T_112, _T_110) node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : node _T_116 = eq(_T_113, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_6 assert(clock, _T_113, UInt<1>(0h1), "") : assert_6 node _T_117 = or(portsEOI_filtered_1[1].valid, portsEOI_filtered_2[1].valid) node _T_118 = or(_T_117, portsEOI_filtered_3[1].valid) node _T_119 = or(_T_118, portsEOI_filtered_4[1].valid) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = or(winner_3[0], winner_3[1]) node _T_122 = or(_T_121, winner_3[2]) node _T_123 = or(_T_122, winner_3[3]) node _T_124 = or(_T_120, _T_123) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_7 assert(clock, _T_124, UInt<1>(0h1), "") : assert_7 node maskedBeats_0_3 = mux(winner_3[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1_3 = mux(winner_3[1], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_2_3 = mux(winner_3[2], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_3_3 = mux(winner_3[3], UInt<1>(0h0), UInt<1>(0h0)) node _initBeats_T_8 = or(maskedBeats_0_3, maskedBeats_1_3) node _initBeats_T_9 = or(_initBeats_T_8, maskedBeats_2_3) node initBeats_3 = or(_initBeats_T_9, maskedBeats_3_3) node _beatsLeft_T_12 = and(out[1].e.ready, out[1].e.valid) node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12) node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1) node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14) connect beatsLeft_3, _beatsLeft_T_15 wire _state_WIRE_3 : UInt<1>[4] connect _state_WIRE_3[0], UInt<1>(0h0) connect _state_WIRE_3[1], UInt<1>(0h0) connect _state_WIRE_3[2], UInt<1>(0h0) connect _state_WIRE_3[3], UInt<1>(0h0) regreset state_3 : UInt<1>[4], clock, reset, _state_WIRE_3 node muxState_3 = mux(idle_3, winner_3, state_3) connect state_3, muxState_3 node allowed_3 = mux(idle_3, readys_3, state_3) node _filtered_1_ready_T_9 = and(out[1].e.ready, allowed_3[0]) connect portsEOI_filtered_1[1].ready, _filtered_1_ready_T_9 node _filtered_1_ready_T_10 = and(out[1].e.ready, allowed_3[1]) connect portsEOI_filtered_2[1].ready, _filtered_1_ready_T_10 node _filtered_1_ready_T_11 = and(out[1].e.ready, allowed_3[2]) connect portsEOI_filtered_3[1].ready, _filtered_1_ready_T_11 node _filtered_1_ready_T_12 = and(out[1].e.ready, allowed_3[3]) connect portsEOI_filtered_4[1].ready, _filtered_1_ready_T_12 node _out_1_e_valid_T = or(portsEOI_filtered_1[1].valid, portsEOI_filtered_2[1].valid) node _out_1_e_valid_T_1 = or(_out_1_e_valid_T, portsEOI_filtered_3[1].valid) node _out_1_e_valid_T_2 = or(_out_1_e_valid_T_1, portsEOI_filtered_4[1].valid) node _out_1_e_valid_T_3 = mux(state_3[0], portsEOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_4 = mux(state_3[1], portsEOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_5 = mux(state_3[2], portsEOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_6 = mux(state_3[3], portsEOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_7 = or(_out_1_e_valid_T_3, _out_1_e_valid_T_4) node _out_1_e_valid_T_8 = or(_out_1_e_valid_T_7, _out_1_e_valid_T_5) node _out_1_e_valid_T_9 = or(_out_1_e_valid_T_8, _out_1_e_valid_T_6) wire _out_1_e_valid_WIRE : UInt<1> connect _out_1_e_valid_WIRE, _out_1_e_valid_T_9 node _out_1_e_valid_T_10 = mux(idle_3, _out_1_e_valid_T_2, _out_1_e_valid_WIRE) connect out[1].e.valid, _out_1_e_valid_T_10 wire _out_1_e_bits_WIRE : { sink : UInt<4>} node _out_1_e_bits_T = mux(muxState_3[0], portsEOI_filtered_1[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_1 = mux(muxState_3[1], portsEOI_filtered_2[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_2 = mux(muxState_3[2], portsEOI_filtered_3[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_3 = mux(muxState_3[3], portsEOI_filtered_4[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_4 = or(_out_1_e_bits_T, _out_1_e_bits_T_1) node _out_1_e_bits_T_5 = or(_out_1_e_bits_T_4, _out_1_e_bits_T_2) node _out_1_e_bits_T_6 = or(_out_1_e_bits_T_5, _out_1_e_bits_T_3) wire _out_1_e_bits_WIRE_1 : UInt<4> connect _out_1_e_bits_WIRE_1, _out_1_e_bits_T_6 connect _out_1_e_bits_WIRE.sink, _out_1_e_bits_WIRE_1 connect out[1].e.bits.sink, _out_1_e_bits_WIRE.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0) node idle_4 = eq(beatsLeft_4, UInt<1>(0h0)) node latch_4 = and(idle_4, in[0].d.ready) node _readys_T_50 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid_4 = bits(_readys_T_50, 1, 0) node _readys_T_51 = eq(readys_valid_4, _readys_T_50) node _readys_T_52 = asUInt(reset) node _readys_T_53 = eq(_readys_T_52, UInt<1>(0h0)) when _readys_T_53 : node _readys_T_54 = eq(_readys_T_51, UInt<1>(0h0)) when _readys_T_54 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_4 assert(clock, _readys_T_51, UInt<1>(0h1), "") : readys_assert_4 regreset readys_mask_4 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_8 = not(readys_mask_4) node _readys_filter_T_9 = and(readys_valid_4, _readys_filter_T_8) node readys_filter_4 = cat(_readys_filter_T_9, readys_valid_4) node _readys_unready_T_32 = shr(readys_filter_4, 1) node _readys_unready_T_33 = or(readys_filter_4, _readys_unready_T_32) node _readys_unready_T_34 = bits(_readys_unready_T_33, 3, 0) node _readys_unready_T_35 = shr(_readys_unready_T_34, 1) node _readys_unready_T_36 = shl(readys_mask_4, 2) node readys_unready_4 = or(_readys_unready_T_35, _readys_unready_T_36) node _readys_readys_T_12 = shr(readys_unready_4, 2) node _readys_readys_T_13 = bits(readys_unready_4, 1, 0) node _readys_readys_T_14 = and(_readys_readys_T_12, _readys_readys_T_13) node readys_readys_4 = not(_readys_readys_T_14) node _readys_T_55 = orr(readys_valid_4) node _readys_T_56 = and(latch_4, _readys_T_55) when _readys_T_56 : node _readys_mask_T_38 = and(readys_readys_4, readys_valid_4) node _readys_mask_T_39 = shl(_readys_mask_T_38, 1) node _readys_mask_T_40 = bits(_readys_mask_T_39, 1, 0) node _readys_mask_T_41 = or(_readys_mask_T_38, _readys_mask_T_40) node _readys_mask_T_42 = bits(_readys_mask_T_41, 1, 0) connect readys_mask_4, _readys_mask_T_42 node _readys_T_57 = bits(readys_readys_4, 1, 0) node _readys_T_58 = bits(_readys_T_57, 0, 0) node _readys_T_59 = bits(_readys_T_57, 1, 1) wire readys_4 : UInt<1>[2] connect readys_4[0], _readys_T_58 connect readys_4[1], _readys_T_59 node _winner_T_18 = and(readys_4[0], portsDIO_filtered[0].valid) node _winner_T_19 = and(readys_4[1], portsDIO_filtered_1[0].valid) wire winner_4 : UInt<1>[2] connect winner_4[0], _winner_T_18 connect winner_4[1], _winner_T_19 node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0]) node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1]) node _T_128 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = eq(winner_4[0], UInt<1>(0h0)) node _T_130 = or(_T_128, _T_129) node _T_131 = eq(prefixOR_1_4, UInt<1>(0h0)) node _T_132 = eq(winner_4[1], UInt<1>(0h0)) node _T_133 = or(_T_131, _T_132) node _T_134 = and(_T_130, _T_133) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_8 assert(clock, _T_134, UInt<1>(0h1), "") : assert_8 node _T_138 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_139 = eq(_T_138, UInt<1>(0h0)) node _T_140 = or(winner_4[0], winner_4[1]) node _T_141 = or(_T_139, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_9 assert(clock, _T_141, UInt<1>(0h1), "") : assert_9 node maskedBeats_0_4 = mux(winner_4[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_4 = mux(winner_4[1], beatsDO_1, UInt<1>(0h0)) node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4) node _beatsLeft_T_16 = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16) node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1) node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18) connect beatsLeft_4, _beatsLeft_T_19 wire _state_WIRE_4 : UInt<1>[2] connect _state_WIRE_4[0], UInt<1>(0h0) connect _state_WIRE_4[1], UInt<1>(0h0) regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4 node muxState_4 = mux(idle_4, winner_4, state_4) connect state_4, muxState_4 node allowed_4 = mux(idle_4, readys_4, state_4) node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed_4[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T_5 node _filtered_0_ready_T_6 = and(in[0].d.ready, allowed_4[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_6 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state_4[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state_4[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle_4, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState_4[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState_4[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<128> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState_4[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState_4[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<4> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState_4[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<7> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState_4[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState_4[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState_4[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) connect in[1].b, portsBIO_filtered_1[1] regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0) node idle_5 = eq(beatsLeft_5, UInt<1>(0h0)) node latch_5 = and(idle_5, in[1].d.ready) node _readys_T_60 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid) node readys_valid_5 = bits(_readys_T_60, 1, 0) node _readys_T_61 = eq(readys_valid_5, _readys_T_60) node _readys_T_62 = asUInt(reset) node _readys_T_63 = eq(_readys_T_62, UInt<1>(0h0)) when _readys_T_63 : node _readys_T_64 = eq(_readys_T_61, UInt<1>(0h0)) when _readys_T_64 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_5 assert(clock, _readys_T_61, UInt<1>(0h1), "") : readys_assert_5 regreset readys_mask_5 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_10 = not(readys_mask_5) node _readys_filter_T_11 = and(readys_valid_5, _readys_filter_T_10) node readys_filter_5 = cat(_readys_filter_T_11, readys_valid_5) node _readys_unready_T_37 = shr(readys_filter_5, 1) node _readys_unready_T_38 = or(readys_filter_5, _readys_unready_T_37) node _readys_unready_T_39 = bits(_readys_unready_T_38, 3, 0) node _readys_unready_T_40 = shr(_readys_unready_T_39, 1) node _readys_unready_T_41 = shl(readys_mask_5, 2) node readys_unready_5 = or(_readys_unready_T_40, _readys_unready_T_41) node _readys_readys_T_15 = shr(readys_unready_5, 2) node _readys_readys_T_16 = bits(readys_unready_5, 1, 0) node _readys_readys_T_17 = and(_readys_readys_T_15, _readys_readys_T_16) node readys_readys_5 = not(_readys_readys_T_17) node _readys_T_65 = orr(readys_valid_5) node _readys_T_66 = and(latch_5, _readys_T_65) when _readys_T_66 : node _readys_mask_T_43 = and(readys_readys_5, readys_valid_5) node _readys_mask_T_44 = shl(_readys_mask_T_43, 1) node _readys_mask_T_45 = bits(_readys_mask_T_44, 1, 0) node _readys_mask_T_46 = or(_readys_mask_T_43, _readys_mask_T_45) node _readys_mask_T_47 = bits(_readys_mask_T_46, 1, 0) connect readys_mask_5, _readys_mask_T_47 node _readys_T_67 = bits(readys_readys_5, 1, 0) node _readys_T_68 = bits(_readys_T_67, 0, 0) node _readys_T_69 = bits(_readys_T_67, 1, 1) wire readys_5 : UInt<1>[2] connect readys_5[0], _readys_T_68 connect readys_5[1], _readys_T_69 node _winner_T_20 = and(readys_5[0], portsDIO_filtered[1].valid) node _winner_T_21 = and(readys_5[1], portsDIO_filtered_1[1].valid) wire winner_5 : UInt<1>[2] connect winner_5[0], _winner_T_20 connect winner_5[1], _winner_T_21 node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0]) node _prefixOR_T_5 = or(prefixOR_1_5, winner_5[1]) node _T_145 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_146 = eq(winner_5[0], UInt<1>(0h0)) node _T_147 = or(_T_145, _T_146) node _T_148 = eq(prefixOR_1_5, UInt<1>(0h0)) node _T_149 = eq(winner_5[1], UInt<1>(0h0)) node _T_150 = or(_T_148, _T_149) node _T_151 = and(_T_147, _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_10 assert(clock, _T_151, UInt<1>(0h1), "") : assert_10 node _T_155 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = or(winner_5[0], winner_5[1]) node _T_158 = or(_T_156, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_11 assert(clock, _T_158, UInt<1>(0h1), "") : assert_11 node maskedBeats_0_5 = mux(winner_5[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_5 = mux(winner_5[1], beatsDO_1, UInt<1>(0h0)) node initBeats_5 = or(maskedBeats_0_5, maskedBeats_1_5) node _beatsLeft_T_20 = and(in[1].d.ready, in[1].d.valid) node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20) node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1) node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22) connect beatsLeft_5, _beatsLeft_T_23 wire _state_WIRE_5 : UInt<1>[2] connect _state_WIRE_5[0], UInt<1>(0h0) connect _state_WIRE_5[1], UInt<1>(0h0) regreset state_5 : UInt<1>[2], clock, reset, _state_WIRE_5 node muxState_5 = mux(idle_5, winner_5, state_5) connect state_5, muxState_5 node allowed_5 = mux(idle_5, readys_5, state_5) node _filtered_1_ready_T_13 = and(in[1].d.ready, allowed_5[0]) connect portsDIO_filtered[1].ready, _filtered_1_ready_T_13 node _filtered_1_ready_T_14 = and(in[1].d.ready, allowed_5[1]) connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_14 node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _in_1_d_valid_T_1 = mux(state_5[0], portsDIO_filtered[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_2 = mux(state_5[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2) wire _in_1_d_valid_WIRE : UInt<1> connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3 node _in_1_d_valid_T_4 = mux(idle_5, _in_1_d_valid_T, _in_1_d_valid_WIRE) connect in[1].d.valid, _in_1_d_valid_T_4 wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_1_d_bits_T = mux(muxState_5[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_1 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1) wire _in_1_d_bits_WIRE_1 : UInt<1> connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2 connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1 node _in_1_d_bits_T_3 = mux(muxState_5[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_4 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4) wire _in_1_d_bits_WIRE_2 : UInt<128> connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5 connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2 wire _in_1_d_bits_WIRE_3 : { } connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3 wire _in_1_d_bits_WIRE_4 : { } connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4 node _in_1_d_bits_T_6 = mux(muxState_5[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_7 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7) wire _in_1_d_bits_WIRE_5 : UInt<1> connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8 connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5 node _in_1_d_bits_T_9 = mux(muxState_5[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_10 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10) wire _in_1_d_bits_WIRE_6 : UInt<4> connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11 connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6 node _in_1_d_bits_T_12 = mux(muxState_5[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_13 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13) wire _in_1_d_bits_WIRE_7 : UInt<7> connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14 connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7 node _in_1_d_bits_T_15 = mux(muxState_5[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_16 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16) wire _in_1_d_bits_WIRE_8 : UInt<4> connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17 connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8 node _in_1_d_bits_T_18 = mux(muxState_5[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_19 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19) wire _in_1_d_bits_WIRE_9 : UInt<2> connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20 connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9 node _in_1_d_bits_T_21 = mux(muxState_5[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_22 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22) wire _in_1_d_bits_WIRE_10 : UInt<3> connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23 connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10 connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt connect in[1].d.bits.data, _in_1_d_bits_WIRE.data connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink connect in[1].d.bits.source, _in_1_d_bits_WIRE.source connect in[1].d.bits.size, _in_1_d_bits_WIRE.size connect in[1].d.bits.param, _in_1_d_bits_WIRE.param connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode connect portsBIO_filtered[1].ready, UInt<1>(0h0) connect in[2].b, portsBIO_filtered_1[2] regreset beatsLeft_6 : UInt, clock, reset, UInt<1>(0h0) node idle_6 = eq(beatsLeft_6, UInt<1>(0h0)) node latch_6 = and(idle_6, in[2].d.ready) node _readys_T_70 = cat(portsDIO_filtered_1[2].valid, portsDIO_filtered[2].valid) node readys_valid_6 = bits(_readys_T_70, 1, 0) node _readys_T_71 = eq(readys_valid_6, _readys_T_70) node _readys_T_72 = asUInt(reset) node _readys_T_73 = eq(_readys_T_72, UInt<1>(0h0)) when _readys_T_73 : node _readys_T_74 = eq(_readys_T_71, UInt<1>(0h0)) when _readys_T_74 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_6 assert(clock, _readys_T_71, UInt<1>(0h1), "") : readys_assert_6 regreset readys_mask_6 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_12 = not(readys_mask_6) node _readys_filter_T_13 = and(readys_valid_6, _readys_filter_T_12) node readys_filter_6 = cat(_readys_filter_T_13, readys_valid_6) node _readys_unready_T_42 = shr(readys_filter_6, 1) node _readys_unready_T_43 = or(readys_filter_6, _readys_unready_T_42) node _readys_unready_T_44 = bits(_readys_unready_T_43, 3, 0) node _readys_unready_T_45 = shr(_readys_unready_T_44, 1) node _readys_unready_T_46 = shl(readys_mask_6, 2) node readys_unready_6 = or(_readys_unready_T_45, _readys_unready_T_46) node _readys_readys_T_18 = shr(readys_unready_6, 2) node _readys_readys_T_19 = bits(readys_unready_6, 1, 0) node _readys_readys_T_20 = and(_readys_readys_T_18, _readys_readys_T_19) node readys_readys_6 = not(_readys_readys_T_20) node _readys_T_75 = orr(readys_valid_6) node _readys_T_76 = and(latch_6, _readys_T_75) when _readys_T_76 : node _readys_mask_T_48 = and(readys_readys_6, readys_valid_6) node _readys_mask_T_49 = shl(_readys_mask_T_48, 1) node _readys_mask_T_50 = bits(_readys_mask_T_49, 1, 0) node _readys_mask_T_51 = or(_readys_mask_T_48, _readys_mask_T_50) node _readys_mask_T_52 = bits(_readys_mask_T_51, 1, 0) connect readys_mask_6, _readys_mask_T_52 node _readys_T_77 = bits(readys_readys_6, 1, 0) node _readys_T_78 = bits(_readys_T_77, 0, 0) node _readys_T_79 = bits(_readys_T_77, 1, 1) wire readys_6 : UInt<1>[2] connect readys_6[0], _readys_T_78 connect readys_6[1], _readys_T_79 node _winner_T_22 = and(readys_6[0], portsDIO_filtered[2].valid) node _winner_T_23 = and(readys_6[1], portsDIO_filtered_1[2].valid) wire winner_6 : UInt<1>[2] connect winner_6[0], _winner_T_22 connect winner_6[1], _winner_T_23 node prefixOR_1_6 = or(UInt<1>(0h0), winner_6[0]) node _prefixOR_T_6 = or(prefixOR_1_6, winner_6[1]) node _T_162 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_163 = eq(winner_6[0], UInt<1>(0h0)) node _T_164 = or(_T_162, _T_163) node _T_165 = eq(prefixOR_1_6, UInt<1>(0h0)) node _T_166 = eq(winner_6[1], UInt<1>(0h0)) node _T_167 = or(_T_165, _T_166) node _T_168 = and(_T_164, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_12 assert(clock, _T_168, UInt<1>(0h1), "") : assert_12 node _T_172 = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = or(winner_6[0], winner_6[1]) node _T_175 = or(_T_173, _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_13 assert(clock, _T_175, UInt<1>(0h1), "") : assert_13 node maskedBeats_0_6 = mux(winner_6[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_6 = mux(winner_6[1], beatsDO_1, UInt<1>(0h0)) node initBeats_6 = or(maskedBeats_0_6, maskedBeats_1_6) node _beatsLeft_T_24 = and(in[2].d.ready, in[2].d.valid) node _beatsLeft_T_25 = sub(beatsLeft_6, _beatsLeft_T_24) node _beatsLeft_T_26 = tail(_beatsLeft_T_25, 1) node _beatsLeft_T_27 = mux(latch_6, initBeats_6, _beatsLeft_T_26) connect beatsLeft_6, _beatsLeft_T_27 wire _state_WIRE_6 : UInt<1>[2] connect _state_WIRE_6[0], UInt<1>(0h0) connect _state_WIRE_6[1], UInt<1>(0h0) regreset state_6 : UInt<1>[2], clock, reset, _state_WIRE_6 node muxState_6 = mux(idle_6, winner_6, state_6) connect state_6, muxState_6 node allowed_6 = mux(idle_6, readys_6, state_6) node _filtered_2_ready_T = and(in[2].d.ready, allowed_6[0]) connect portsDIO_filtered[2].ready, _filtered_2_ready_T node _filtered_2_ready_T_1 = and(in[2].d.ready, allowed_6[1]) connect portsDIO_filtered_1[2].ready, _filtered_2_ready_T_1 node _in_2_d_valid_T = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _in_2_d_valid_T_1 = mux(state_6[0], portsDIO_filtered[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_2 = mux(state_6[1], portsDIO_filtered_1[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_3 = or(_in_2_d_valid_T_1, _in_2_d_valid_T_2) wire _in_2_d_valid_WIRE : UInt<1> connect _in_2_d_valid_WIRE, _in_2_d_valid_T_3 node _in_2_d_valid_T_4 = mux(idle_6, _in_2_d_valid_T, _in_2_d_valid_WIRE) connect in[2].d.valid, _in_2_d_valid_T_4 wire _in_2_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_2_d_bits_T = mux(muxState_6[0], portsDIO_filtered[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_1 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_2 = or(_in_2_d_bits_T, _in_2_d_bits_T_1) wire _in_2_d_bits_WIRE_1 : UInt<1> connect _in_2_d_bits_WIRE_1, _in_2_d_bits_T_2 connect _in_2_d_bits_WIRE.corrupt, _in_2_d_bits_WIRE_1 node _in_2_d_bits_T_3 = mux(muxState_6[0], portsDIO_filtered[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_4 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_5 = or(_in_2_d_bits_T_3, _in_2_d_bits_T_4) wire _in_2_d_bits_WIRE_2 : UInt<128> connect _in_2_d_bits_WIRE_2, _in_2_d_bits_T_5 connect _in_2_d_bits_WIRE.data, _in_2_d_bits_WIRE_2 wire _in_2_d_bits_WIRE_3 : { } connect _in_2_d_bits_WIRE.echo, _in_2_d_bits_WIRE_3 wire _in_2_d_bits_WIRE_4 : { } connect _in_2_d_bits_WIRE.user, _in_2_d_bits_WIRE_4 node _in_2_d_bits_T_6 = mux(muxState_6[0], portsDIO_filtered[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_7 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_8 = or(_in_2_d_bits_T_6, _in_2_d_bits_T_7) wire _in_2_d_bits_WIRE_5 : UInt<1> connect _in_2_d_bits_WIRE_5, _in_2_d_bits_T_8 connect _in_2_d_bits_WIRE.denied, _in_2_d_bits_WIRE_5 node _in_2_d_bits_T_9 = mux(muxState_6[0], portsDIO_filtered[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_10 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_11 = or(_in_2_d_bits_T_9, _in_2_d_bits_T_10) wire _in_2_d_bits_WIRE_6 : UInt<4> connect _in_2_d_bits_WIRE_6, _in_2_d_bits_T_11 connect _in_2_d_bits_WIRE.sink, _in_2_d_bits_WIRE_6 node _in_2_d_bits_T_12 = mux(muxState_6[0], portsDIO_filtered[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_13 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_14 = or(_in_2_d_bits_T_12, _in_2_d_bits_T_13) wire _in_2_d_bits_WIRE_7 : UInt<7> connect _in_2_d_bits_WIRE_7, _in_2_d_bits_T_14 connect _in_2_d_bits_WIRE.source, _in_2_d_bits_WIRE_7 node _in_2_d_bits_T_15 = mux(muxState_6[0], portsDIO_filtered[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_16 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_17 = or(_in_2_d_bits_T_15, _in_2_d_bits_T_16) wire _in_2_d_bits_WIRE_8 : UInt<4> connect _in_2_d_bits_WIRE_8, _in_2_d_bits_T_17 connect _in_2_d_bits_WIRE.size, _in_2_d_bits_WIRE_8 node _in_2_d_bits_T_18 = mux(muxState_6[0], portsDIO_filtered[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_19 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_20 = or(_in_2_d_bits_T_18, _in_2_d_bits_T_19) wire _in_2_d_bits_WIRE_9 : UInt<2> connect _in_2_d_bits_WIRE_9, _in_2_d_bits_T_20 connect _in_2_d_bits_WIRE.param, _in_2_d_bits_WIRE_9 node _in_2_d_bits_T_21 = mux(muxState_6[0], portsDIO_filtered[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_22 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_23 = or(_in_2_d_bits_T_21, _in_2_d_bits_T_22) wire _in_2_d_bits_WIRE_10 : UInt<3> connect _in_2_d_bits_WIRE_10, _in_2_d_bits_T_23 connect _in_2_d_bits_WIRE.opcode, _in_2_d_bits_WIRE_10 connect in[2].d.bits.corrupt, _in_2_d_bits_WIRE.corrupt connect in[2].d.bits.data, _in_2_d_bits_WIRE.data connect in[2].d.bits.denied, _in_2_d_bits_WIRE.denied connect in[2].d.bits.sink, _in_2_d_bits_WIRE.sink connect in[2].d.bits.source, _in_2_d_bits_WIRE.source connect in[2].d.bits.size, _in_2_d_bits_WIRE.size connect in[2].d.bits.param, _in_2_d_bits_WIRE.param connect in[2].d.bits.opcode, _in_2_d_bits_WIRE.opcode connect portsBIO_filtered[2].ready, UInt<1>(0h0) connect in[3].b, portsBIO_filtered_1[3] regreset beatsLeft_7 : UInt, clock, reset, UInt<1>(0h0) node idle_7 = eq(beatsLeft_7, UInt<1>(0h0)) node latch_7 = and(idle_7, in[3].d.ready) node _readys_T_80 = cat(portsDIO_filtered_1[3].valid, portsDIO_filtered[3].valid) node readys_valid_7 = bits(_readys_T_80, 1, 0) node _readys_T_81 = eq(readys_valid_7, _readys_T_80) node _readys_T_82 = asUInt(reset) node _readys_T_83 = eq(_readys_T_82, UInt<1>(0h0)) when _readys_T_83 : node _readys_T_84 = eq(_readys_T_81, UInt<1>(0h0)) when _readys_T_84 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_7 assert(clock, _readys_T_81, UInt<1>(0h1), "") : readys_assert_7 regreset readys_mask_7 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_14 = not(readys_mask_7) node _readys_filter_T_15 = and(readys_valid_7, _readys_filter_T_14) node readys_filter_7 = cat(_readys_filter_T_15, readys_valid_7) node _readys_unready_T_47 = shr(readys_filter_7, 1) node _readys_unready_T_48 = or(readys_filter_7, _readys_unready_T_47) node _readys_unready_T_49 = bits(_readys_unready_T_48, 3, 0) node _readys_unready_T_50 = shr(_readys_unready_T_49, 1) node _readys_unready_T_51 = shl(readys_mask_7, 2) node readys_unready_7 = or(_readys_unready_T_50, _readys_unready_T_51) node _readys_readys_T_21 = shr(readys_unready_7, 2) node _readys_readys_T_22 = bits(readys_unready_7, 1, 0) node _readys_readys_T_23 = and(_readys_readys_T_21, _readys_readys_T_22) node readys_readys_7 = not(_readys_readys_T_23) node _readys_T_85 = orr(readys_valid_7) node _readys_T_86 = and(latch_7, _readys_T_85) when _readys_T_86 : node _readys_mask_T_53 = and(readys_readys_7, readys_valid_7) node _readys_mask_T_54 = shl(_readys_mask_T_53, 1) node _readys_mask_T_55 = bits(_readys_mask_T_54, 1, 0) node _readys_mask_T_56 = or(_readys_mask_T_53, _readys_mask_T_55) node _readys_mask_T_57 = bits(_readys_mask_T_56, 1, 0) connect readys_mask_7, _readys_mask_T_57 node _readys_T_87 = bits(readys_readys_7, 1, 0) node _readys_T_88 = bits(_readys_T_87, 0, 0) node _readys_T_89 = bits(_readys_T_87, 1, 1) wire readys_7 : UInt<1>[2] connect readys_7[0], _readys_T_88 connect readys_7[1], _readys_T_89 node _winner_T_24 = and(readys_7[0], portsDIO_filtered[3].valid) node _winner_T_25 = and(readys_7[1], portsDIO_filtered_1[3].valid) wire winner_7 : UInt<1>[2] connect winner_7[0], _winner_T_24 connect winner_7[1], _winner_T_25 node prefixOR_1_7 = or(UInt<1>(0h0), winner_7[0]) node _prefixOR_T_7 = or(prefixOR_1_7, winner_7[1]) node _T_179 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = eq(winner_7[0], UInt<1>(0h0)) node _T_181 = or(_T_179, _T_180) node _T_182 = eq(prefixOR_1_7, UInt<1>(0h0)) node _T_183 = eq(winner_7[1], UInt<1>(0h0)) node _T_184 = or(_T_182, _T_183) node _T_185 = and(_T_181, _T_184) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_14 assert(clock, _T_185, UInt<1>(0h1), "") : assert_14 node _T_189 = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = or(winner_7[0], winner_7[1]) node _T_192 = or(_T_190, _T_191) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_15 assert(clock, _T_192, UInt<1>(0h1), "") : assert_15 node maskedBeats_0_7 = mux(winner_7[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_7 = mux(winner_7[1], beatsDO_1, UInt<1>(0h0)) node initBeats_7 = or(maskedBeats_0_7, maskedBeats_1_7) node _beatsLeft_T_28 = and(in[3].d.ready, in[3].d.valid) node _beatsLeft_T_29 = sub(beatsLeft_7, _beatsLeft_T_28) node _beatsLeft_T_30 = tail(_beatsLeft_T_29, 1) node _beatsLeft_T_31 = mux(latch_7, initBeats_7, _beatsLeft_T_30) connect beatsLeft_7, _beatsLeft_T_31 wire _state_WIRE_7 : UInt<1>[2] connect _state_WIRE_7[0], UInt<1>(0h0) connect _state_WIRE_7[1], UInt<1>(0h0) regreset state_7 : UInt<1>[2], clock, reset, _state_WIRE_7 node muxState_7 = mux(idle_7, winner_7, state_7) connect state_7, muxState_7 node allowed_7 = mux(idle_7, readys_7, state_7) node _filtered_3_ready_T = and(in[3].d.ready, allowed_7[0]) connect portsDIO_filtered[3].ready, _filtered_3_ready_T node _filtered_3_ready_T_1 = and(in[3].d.ready, allowed_7[1]) connect portsDIO_filtered_1[3].ready, _filtered_3_ready_T_1 node _in_3_d_valid_T = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid) node _in_3_d_valid_T_1 = mux(state_7[0], portsDIO_filtered[3].valid, UInt<1>(0h0)) node _in_3_d_valid_T_2 = mux(state_7[1], portsDIO_filtered_1[3].valid, UInt<1>(0h0)) node _in_3_d_valid_T_3 = or(_in_3_d_valid_T_1, _in_3_d_valid_T_2) wire _in_3_d_valid_WIRE : UInt<1> connect _in_3_d_valid_WIRE, _in_3_d_valid_T_3 node _in_3_d_valid_T_4 = mux(idle_7, _in_3_d_valid_T, _in_3_d_valid_WIRE) connect in[3].d.valid, _in_3_d_valid_T_4 wire _in_3_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_3_d_bits_T = mux(muxState_7[0], portsDIO_filtered[3].bits.corrupt, UInt<1>(0h0)) node _in_3_d_bits_T_1 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.corrupt, UInt<1>(0h0)) node _in_3_d_bits_T_2 = or(_in_3_d_bits_T, _in_3_d_bits_T_1) wire _in_3_d_bits_WIRE_1 : UInt<1> connect _in_3_d_bits_WIRE_1, _in_3_d_bits_T_2 connect _in_3_d_bits_WIRE.corrupt, _in_3_d_bits_WIRE_1 node _in_3_d_bits_T_3 = mux(muxState_7[0], portsDIO_filtered[3].bits.data, UInt<1>(0h0)) node _in_3_d_bits_T_4 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.data, UInt<1>(0h0)) node _in_3_d_bits_T_5 = or(_in_3_d_bits_T_3, _in_3_d_bits_T_4) wire _in_3_d_bits_WIRE_2 : UInt<128> connect _in_3_d_bits_WIRE_2, _in_3_d_bits_T_5 connect _in_3_d_bits_WIRE.data, _in_3_d_bits_WIRE_2 wire _in_3_d_bits_WIRE_3 : { } connect _in_3_d_bits_WIRE.echo, _in_3_d_bits_WIRE_3 wire _in_3_d_bits_WIRE_4 : { } connect _in_3_d_bits_WIRE.user, _in_3_d_bits_WIRE_4 node _in_3_d_bits_T_6 = mux(muxState_7[0], portsDIO_filtered[3].bits.denied, UInt<1>(0h0)) node _in_3_d_bits_T_7 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.denied, UInt<1>(0h0)) node _in_3_d_bits_T_8 = or(_in_3_d_bits_T_6, _in_3_d_bits_T_7) wire _in_3_d_bits_WIRE_5 : UInt<1> connect _in_3_d_bits_WIRE_5, _in_3_d_bits_T_8 connect _in_3_d_bits_WIRE.denied, _in_3_d_bits_WIRE_5 node _in_3_d_bits_T_9 = mux(muxState_7[0], portsDIO_filtered[3].bits.sink, UInt<1>(0h0)) node _in_3_d_bits_T_10 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.sink, UInt<1>(0h0)) node _in_3_d_bits_T_11 = or(_in_3_d_bits_T_9, _in_3_d_bits_T_10) wire _in_3_d_bits_WIRE_6 : UInt<4> connect _in_3_d_bits_WIRE_6, _in_3_d_bits_T_11 connect _in_3_d_bits_WIRE.sink, _in_3_d_bits_WIRE_6 node _in_3_d_bits_T_12 = mux(muxState_7[0], portsDIO_filtered[3].bits.source, UInt<1>(0h0)) node _in_3_d_bits_T_13 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.source, UInt<1>(0h0)) node _in_3_d_bits_T_14 = or(_in_3_d_bits_T_12, _in_3_d_bits_T_13) wire _in_3_d_bits_WIRE_7 : UInt<7> connect _in_3_d_bits_WIRE_7, _in_3_d_bits_T_14 connect _in_3_d_bits_WIRE.source, _in_3_d_bits_WIRE_7 node _in_3_d_bits_T_15 = mux(muxState_7[0], portsDIO_filtered[3].bits.size, UInt<1>(0h0)) node _in_3_d_bits_T_16 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.size, UInt<1>(0h0)) node _in_3_d_bits_T_17 = or(_in_3_d_bits_T_15, _in_3_d_bits_T_16) wire _in_3_d_bits_WIRE_8 : UInt<4> connect _in_3_d_bits_WIRE_8, _in_3_d_bits_T_17 connect _in_3_d_bits_WIRE.size, _in_3_d_bits_WIRE_8 node _in_3_d_bits_T_18 = mux(muxState_7[0], portsDIO_filtered[3].bits.param, UInt<1>(0h0)) node _in_3_d_bits_T_19 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.param, UInt<1>(0h0)) node _in_3_d_bits_T_20 = or(_in_3_d_bits_T_18, _in_3_d_bits_T_19) wire _in_3_d_bits_WIRE_9 : UInt<2> connect _in_3_d_bits_WIRE_9, _in_3_d_bits_T_20 connect _in_3_d_bits_WIRE.param, _in_3_d_bits_WIRE_9 node _in_3_d_bits_T_21 = mux(muxState_7[0], portsDIO_filtered[3].bits.opcode, UInt<1>(0h0)) node _in_3_d_bits_T_22 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.opcode, UInt<1>(0h0)) node _in_3_d_bits_T_23 = or(_in_3_d_bits_T_21, _in_3_d_bits_T_22) wire _in_3_d_bits_WIRE_10 : UInt<3> connect _in_3_d_bits_WIRE_10, _in_3_d_bits_T_23 connect _in_3_d_bits_WIRE.opcode, _in_3_d_bits_WIRE_10 connect in[3].d.bits.corrupt, _in_3_d_bits_WIRE.corrupt connect in[3].d.bits.data, _in_3_d_bits_WIRE.data connect in[3].d.bits.denied, _in_3_d_bits_WIRE.denied connect in[3].d.bits.sink, _in_3_d_bits_WIRE.sink connect in[3].d.bits.source, _in_3_d_bits_WIRE.source connect in[3].d.bits.size, _in_3_d_bits_WIRE.size connect in[3].d.bits.param, _in_3_d_bits_WIRE.param connect in[3].d.bits.opcode, _in_3_d_bits_WIRE.opcode connect portsBIO_filtered[3].ready, UInt<1>(0h0) connect in[4].b, portsBIO_filtered_1[4] regreset beatsLeft_8 : UInt, clock, reset, UInt<1>(0h0) node idle_8 = eq(beatsLeft_8, UInt<1>(0h0)) node latch_8 = and(idle_8, in[4].d.ready) node _readys_T_90 = cat(portsDIO_filtered_1[4].valid, portsDIO_filtered[4].valid) node readys_valid_8 = bits(_readys_T_90, 1, 0) node _readys_T_91 = eq(readys_valid_8, _readys_T_90) node _readys_T_92 = asUInt(reset) node _readys_T_93 = eq(_readys_T_92, UInt<1>(0h0)) when _readys_T_93 : node _readys_T_94 = eq(_readys_T_91, UInt<1>(0h0)) when _readys_T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_8 assert(clock, _readys_T_91, UInt<1>(0h1), "") : readys_assert_8 regreset readys_mask_8 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_16 = not(readys_mask_8) node _readys_filter_T_17 = and(readys_valid_8, _readys_filter_T_16) node readys_filter_8 = cat(_readys_filter_T_17, readys_valid_8) node _readys_unready_T_52 = shr(readys_filter_8, 1) node _readys_unready_T_53 = or(readys_filter_8, _readys_unready_T_52) node _readys_unready_T_54 = bits(_readys_unready_T_53, 3, 0) node _readys_unready_T_55 = shr(_readys_unready_T_54, 1) node _readys_unready_T_56 = shl(readys_mask_8, 2) node readys_unready_8 = or(_readys_unready_T_55, _readys_unready_T_56) node _readys_readys_T_24 = shr(readys_unready_8, 2) node _readys_readys_T_25 = bits(readys_unready_8, 1, 0) node _readys_readys_T_26 = and(_readys_readys_T_24, _readys_readys_T_25) node readys_readys_8 = not(_readys_readys_T_26) node _readys_T_95 = orr(readys_valid_8) node _readys_T_96 = and(latch_8, _readys_T_95) when _readys_T_96 : node _readys_mask_T_58 = and(readys_readys_8, readys_valid_8) node _readys_mask_T_59 = shl(_readys_mask_T_58, 1) node _readys_mask_T_60 = bits(_readys_mask_T_59, 1, 0) node _readys_mask_T_61 = or(_readys_mask_T_58, _readys_mask_T_60) node _readys_mask_T_62 = bits(_readys_mask_T_61, 1, 0) connect readys_mask_8, _readys_mask_T_62 node _readys_T_97 = bits(readys_readys_8, 1, 0) node _readys_T_98 = bits(_readys_T_97, 0, 0) node _readys_T_99 = bits(_readys_T_97, 1, 1) wire readys_8 : UInt<1>[2] connect readys_8[0], _readys_T_98 connect readys_8[1], _readys_T_99 node _winner_T_26 = and(readys_8[0], portsDIO_filtered[4].valid) node _winner_T_27 = and(readys_8[1], portsDIO_filtered_1[4].valid) wire winner_8 : UInt<1>[2] connect winner_8[0], _winner_T_26 connect winner_8[1], _winner_T_27 node prefixOR_1_8 = or(UInt<1>(0h0), winner_8[0]) node _prefixOR_T_8 = or(prefixOR_1_8, winner_8[1]) node _T_196 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = eq(winner_8[0], UInt<1>(0h0)) node _T_198 = or(_T_196, _T_197) node _T_199 = eq(prefixOR_1_8, UInt<1>(0h0)) node _T_200 = eq(winner_8[1], UInt<1>(0h0)) node _T_201 = or(_T_199, _T_200) node _T_202 = and(_T_198, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_16 assert(clock, _T_202, UInt<1>(0h1), "") : assert_16 node _T_206 = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = or(winner_8[0], winner_8[1]) node _T_209 = or(_T_207, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_17 assert(clock, _T_209, UInt<1>(0h1), "") : assert_17 node maskedBeats_0_8 = mux(winner_8[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_8 = mux(winner_8[1], beatsDO_1, UInt<1>(0h0)) node initBeats_8 = or(maskedBeats_0_8, maskedBeats_1_8) node _beatsLeft_T_32 = and(in[4].d.ready, in[4].d.valid) node _beatsLeft_T_33 = sub(beatsLeft_8, _beatsLeft_T_32) node _beatsLeft_T_34 = tail(_beatsLeft_T_33, 1) node _beatsLeft_T_35 = mux(latch_8, initBeats_8, _beatsLeft_T_34) connect beatsLeft_8, _beatsLeft_T_35 wire _state_WIRE_8 : UInt<1>[2] connect _state_WIRE_8[0], UInt<1>(0h0) connect _state_WIRE_8[1], UInt<1>(0h0) regreset state_8 : UInt<1>[2], clock, reset, _state_WIRE_8 node muxState_8 = mux(idle_8, winner_8, state_8) connect state_8, muxState_8 node allowed_8 = mux(idle_8, readys_8, state_8) node _filtered_4_ready_T = and(in[4].d.ready, allowed_8[0]) connect portsDIO_filtered[4].ready, _filtered_4_ready_T node _filtered_4_ready_T_1 = and(in[4].d.ready, allowed_8[1]) connect portsDIO_filtered_1[4].ready, _filtered_4_ready_T_1 node _in_4_d_valid_T = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid) node _in_4_d_valid_T_1 = mux(state_8[0], portsDIO_filtered[4].valid, UInt<1>(0h0)) node _in_4_d_valid_T_2 = mux(state_8[1], portsDIO_filtered_1[4].valid, UInt<1>(0h0)) node _in_4_d_valid_T_3 = or(_in_4_d_valid_T_1, _in_4_d_valid_T_2) wire _in_4_d_valid_WIRE : UInt<1> connect _in_4_d_valid_WIRE, _in_4_d_valid_T_3 node _in_4_d_valid_T_4 = mux(idle_8, _in_4_d_valid_T, _in_4_d_valid_WIRE) connect in[4].d.valid, _in_4_d_valid_T_4 wire _in_4_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_4_d_bits_T = mux(muxState_8[0], portsDIO_filtered[4].bits.corrupt, UInt<1>(0h0)) node _in_4_d_bits_T_1 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.corrupt, UInt<1>(0h0)) node _in_4_d_bits_T_2 = or(_in_4_d_bits_T, _in_4_d_bits_T_1) wire _in_4_d_bits_WIRE_1 : UInt<1> connect _in_4_d_bits_WIRE_1, _in_4_d_bits_T_2 connect _in_4_d_bits_WIRE.corrupt, _in_4_d_bits_WIRE_1 node _in_4_d_bits_T_3 = mux(muxState_8[0], portsDIO_filtered[4].bits.data, UInt<1>(0h0)) node _in_4_d_bits_T_4 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.data, UInt<1>(0h0)) node _in_4_d_bits_T_5 = or(_in_4_d_bits_T_3, _in_4_d_bits_T_4) wire _in_4_d_bits_WIRE_2 : UInt<128> connect _in_4_d_bits_WIRE_2, _in_4_d_bits_T_5 connect _in_4_d_bits_WIRE.data, _in_4_d_bits_WIRE_2 wire _in_4_d_bits_WIRE_3 : { } connect _in_4_d_bits_WIRE.echo, _in_4_d_bits_WIRE_3 wire _in_4_d_bits_WIRE_4 : { } connect _in_4_d_bits_WIRE.user, _in_4_d_bits_WIRE_4 node _in_4_d_bits_T_6 = mux(muxState_8[0], portsDIO_filtered[4].bits.denied, UInt<1>(0h0)) node _in_4_d_bits_T_7 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.denied, UInt<1>(0h0)) node _in_4_d_bits_T_8 = or(_in_4_d_bits_T_6, _in_4_d_bits_T_7) wire _in_4_d_bits_WIRE_5 : UInt<1> connect _in_4_d_bits_WIRE_5, _in_4_d_bits_T_8 connect _in_4_d_bits_WIRE.denied, _in_4_d_bits_WIRE_5 node _in_4_d_bits_T_9 = mux(muxState_8[0], portsDIO_filtered[4].bits.sink, UInt<1>(0h0)) node _in_4_d_bits_T_10 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.sink, UInt<1>(0h0)) node _in_4_d_bits_T_11 = or(_in_4_d_bits_T_9, _in_4_d_bits_T_10) wire _in_4_d_bits_WIRE_6 : UInt<4> connect _in_4_d_bits_WIRE_6, _in_4_d_bits_T_11 connect _in_4_d_bits_WIRE.sink, _in_4_d_bits_WIRE_6 node _in_4_d_bits_T_12 = mux(muxState_8[0], portsDIO_filtered[4].bits.source, UInt<1>(0h0)) node _in_4_d_bits_T_13 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.source, UInt<1>(0h0)) node _in_4_d_bits_T_14 = or(_in_4_d_bits_T_12, _in_4_d_bits_T_13) wire _in_4_d_bits_WIRE_7 : UInt<7> connect _in_4_d_bits_WIRE_7, _in_4_d_bits_T_14 connect _in_4_d_bits_WIRE.source, _in_4_d_bits_WIRE_7 node _in_4_d_bits_T_15 = mux(muxState_8[0], portsDIO_filtered[4].bits.size, UInt<1>(0h0)) node _in_4_d_bits_T_16 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.size, UInt<1>(0h0)) node _in_4_d_bits_T_17 = or(_in_4_d_bits_T_15, _in_4_d_bits_T_16) wire _in_4_d_bits_WIRE_8 : UInt<4> connect _in_4_d_bits_WIRE_8, _in_4_d_bits_T_17 connect _in_4_d_bits_WIRE.size, _in_4_d_bits_WIRE_8 node _in_4_d_bits_T_18 = mux(muxState_8[0], portsDIO_filtered[4].bits.param, UInt<1>(0h0)) node _in_4_d_bits_T_19 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.param, UInt<1>(0h0)) node _in_4_d_bits_T_20 = or(_in_4_d_bits_T_18, _in_4_d_bits_T_19) wire _in_4_d_bits_WIRE_9 : UInt<2> connect _in_4_d_bits_WIRE_9, _in_4_d_bits_T_20 connect _in_4_d_bits_WIRE.param, _in_4_d_bits_WIRE_9 node _in_4_d_bits_T_21 = mux(muxState_8[0], portsDIO_filtered[4].bits.opcode, UInt<1>(0h0)) node _in_4_d_bits_T_22 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.opcode, UInt<1>(0h0)) node _in_4_d_bits_T_23 = or(_in_4_d_bits_T_21, _in_4_d_bits_T_22) wire _in_4_d_bits_WIRE_10 : UInt<3> connect _in_4_d_bits_WIRE_10, _in_4_d_bits_T_23 connect _in_4_d_bits_WIRE.opcode, _in_4_d_bits_WIRE_10 connect in[4].d.bits.corrupt, _in_4_d_bits_WIRE.corrupt connect in[4].d.bits.data, _in_4_d_bits_WIRE.data connect in[4].d.bits.denied, _in_4_d_bits_WIRE.denied connect in[4].d.bits.sink, _in_4_d_bits_WIRE.sink connect in[4].d.bits.source, _in_4_d_bits_WIRE.source connect in[4].d.bits.size, _in_4_d_bits_WIRE.size connect in[4].d.bits.param, _in_4_d_bits_WIRE.param connect in[4].d.bits.opcode, _in_4_d_bits_WIRE.opcode connect portsBIO_filtered[4].ready, UInt<1>(0h0)	module TLXbar_sbus_i5_o2_a32d128s7k4z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_4_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_4_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_4_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_4_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_4_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire portsEOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire [3:0] out_1_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_4_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_4_a_valid_0 = auto_anon_in_4_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_a_bits_opcode_0 = auto_anon_in_4_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_a_bits_param_0 = auto_anon_in_4_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_a_bits_size_0 = auto_anon_in_4_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_a_bits_source_0 = auto_anon_in_4_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_a_bits_address_0 = auto_anon_in_4_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_4_a_bits_mask_0 = auto_anon_in_4_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_a_bits_data_0 = auto_anon_in_4_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_4_a_bits_corrupt_0 = auto_anon_in_4_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_4_b_ready_0 = auto_anon_in_4_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_valid_0 = auto_anon_in_4_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_c_bits_opcode_0 = auto_anon_in_4_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_c_bits_param_0 = auto_anon_in_4_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_c_bits_size_0 = auto_anon_in_4_c_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_c_bits_source_0 = auto_anon_in_4_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_c_bits_address_0 = auto_anon_in_4_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_c_bits_data_0 = auto_anon_in_4_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_bits_corrupt_0 = auto_anon_in_4_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_ready_0 = auto_anon_in_4_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_4_e_valid_0 = auto_anon_in_4_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_e_bits_sink_0 = auto_anon_in_4_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_valid_0 = auto_anon_in_3_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_a_bits_opcode_0 = auto_anon_in_3_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_a_bits_param_0 = auto_anon_in_3_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_a_bits_size_0 = auto_anon_in_3_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_a_bits_source_0 = auto_anon_in_3_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_a_bits_address_0 = auto_anon_in_3_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_3_a_bits_mask_0 = auto_anon_in_3_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_a_bits_data_0 = auto_anon_in_3_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_bits_corrupt_0 = auto_anon_in_3_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_ready_0 = auto_anon_in_3_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_valid_0 = auto_anon_in_3_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_c_bits_opcode_0 = auto_anon_in_3_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_c_bits_param_0 = auto_anon_in_3_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_c_bits_size_0 = auto_anon_in_3_c_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_c_bits_source_0 = auto_anon_in_3_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_c_bits_address_0 = auto_anon_in_3_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_c_bits_data_0 = auto_anon_in_3_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_bits_corrupt_0 = auto_anon_in_3_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_ready_0 = auto_anon_in_3_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_3_e_valid_0 = auto_anon_in_3_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_e_bits_sink_0 = auto_anon_in_3_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_opcode_0 = auto_anon_in_2_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_param_0 = auto_anon_in_2_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_a_bits_size_0 = auto_anon_in_2_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_a_bits_source_0 = auto_anon_in_2_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_2_a_bits_mask_0 = auto_anon_in_2_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_a_bits_data_0 = auto_anon_in_2_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_bits_corrupt_0 = auto_anon_in_2_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_ready_0 = auto_anon_in_2_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_valid_0 = auto_anon_in_2_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_opcode_0 = auto_anon_in_2_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_param_0 = auto_anon_in_2_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_c_bits_size_0 = auto_anon_in_2_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_c_bits_source_0 = auto_anon_in_2_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_c_bits_address_0 = auto_anon_in_2_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_c_bits_data_0 = auto_anon_in_2_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_bits_corrupt_0 = auto_anon_in_2_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_ready_0 = auto_anon_in_2_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_valid_0 = auto_anon_in_2_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_e_bits_sink_0 = auto_anon_in_2_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_b_bits_source_0 = auto_anon_out_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire _readys_T_15 = reset; // @[Arbiter.scala:22:12] wire _readys_T_28 = reset; // @[Arbiter.scala:22:12] wire _readys_T_40 = reset; // @[Arbiter.scala:22:12] wire _readys_T_52 = reset; // @[Arbiter.scala:22:12] wire _readys_T_62 = reset; // @[Arbiter.scala:22:12] wire _readys_T_72 = reset; // @[Arbiter.scala:22:12] wire _readys_T_82 = reset; // @[Arbiter.scala:22:12] wire _readys_T_92 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_4_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_size = 3'h6; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_3_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_4_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_3_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_4_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_2_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_3_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_4_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [3:0] auto_anon_in_4_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_2_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_3_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_4_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] out_1_b_bits_size = 4'h6; // @[Xbar.scala:216:19] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_2_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_3_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_4_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [15:0] auto_anon_in_4_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_3_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_2_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_2_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_3_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_4_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] x1_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] in_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_2_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_3_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_4_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] out_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] portsBIO_filtered_1_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_1_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_2_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_3_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_4_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_anon_in_4_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_2_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_3_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_4_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] x1_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_0_c_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_2_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_3_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_4_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] out_0_c_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] out_1_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_2_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_3_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_4_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_2_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_3_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_4_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_anon_in_4_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_3_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_4_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_3_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_4_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_b_ready = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_e_valid = 1'h0; // @[Xbar.scala:216:19] wire out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_11 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_13 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_2 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_16 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_18 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_3 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_21 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_23 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_4 = 1'h0; // @[Parameters.scala:56:48] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_15 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_20 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire beatsBO_opdata_1 = 1'h0; // @[Edges.scala:97:28] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_3_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_4_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_6 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_7 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_8 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_1_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_in_0_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_1_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_2_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_3_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_4_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_0_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_1_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_4 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_2_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_6 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_3_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_8 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_4_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_4 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_3 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_0_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_3_3 = 1'h0; // @[Arbiter.scala:82:69] wire _initBeats_T_8 = 1'h0; // @[Arbiter.scala:84:44] wire _initBeats_T_9 = 1'h0; // @[Arbiter.scala:84:44] wire initBeats_3 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_7_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_7_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_8_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_8_1 = 1'h0; // @[Arbiter.scala:88:34] wire auto_anon_out_1_e_ready = 1'h1; // @[Xbar.scala:74:9] wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18] wire out_0_c_ready = 1'h1; // @[Xbar.scala:216:19] wire out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire out_1_e_ready = 1'h1; // @[Xbar.scala:216:19] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_34 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_3_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_39 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_3_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_44 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_4_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_49 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_4_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_2_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_16 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_18 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_19 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_3_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_21 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_23 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_24 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_4_1 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _beatsBO_opdata_T_1 = 1'h1; // @[Edges.scala:97:37] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_0_e_bits_sink = 4'h0; // @[Xbar.scala:159:18] wire [3:0] out_0_b_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] out_0_c_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] out_0_e_bits_sink = 4'h0; // @[Xbar.scala:216:19] wire [3:0] requestBOI_uncommonBits_3 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] requestBOI_uncommonBits_4 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] _requestEIO_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] requestEIO_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_3_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_4_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_0_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_1_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] out_0_b_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] out_0_c_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_3_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_4_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [6:0] in_0_b_bits_source = 7'h0; // @[Xbar.scala:159:18] wire [6:0] in_0_c_bits_source = 7'h0; // @[Xbar.scala:159:18] wire [6:0] out_0_b_bits_source = 7'h0; // @[Xbar.scala:216:19] wire [6:0] out_0_c_bits_source = 7'h0; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_2 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_3 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_4 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_2_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_3_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_4_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] out_0_b_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_param = 3'h0; // @[Xbar.scala:216:19] wire [2:0] _requestBOI_T_15 = 3'h0; // @[Parameters.scala:54:10] wire [2:0] _requestBOI_T_20 = 3'h0; // @[Parameters.scala:54:10] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_3_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_4_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [15:0] in_0_b_bits_mask = 16'h0; // @[Xbar.scala:159:18] wire [15:0] out_0_b_bits_mask = 16'h0; // @[Xbar.scala:216:19] wire [15:0] portsBIO_filtered_0_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_2_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_3_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_4_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_b_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_T = 2'h0; // @[Parameters.scala:54:10] wire [1:0] requestBOI_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] requestBOI_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] beatsBO_1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_2_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_3_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_4_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [7:0] beatsBO_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsCI_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsCI_0 = 8'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [1:0] beatsBO_decode_1 = 2'h3; // @[Edges.scala:220:59] wire [5:0] _beatsBO_decode_T_5 = 6'h3F; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_4 = 6'h0; // @[package.scala:243:76] wire [20:0] _beatsBO_decode_T_3 = 21'hFC0; // @[package.scala:243:71] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_5 = 5'h0; // @[Parameters.scala:54:10] wire [4:0] _requestBOI_T_10 = 5'h0; // @[Parameters.scala:54:10] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_22 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_23 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_27 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_28 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_32 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_33 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_42 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_43 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_47 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_48 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_4_a_ready; // @[MixedNode.scala:551:17] wire anonIn_4_a_valid = auto_anon_in_4_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_a_bits_opcode = auto_anon_in_4_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_a_bits_param = auto_anon_in_4_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_a_bits_size = auto_anon_in_4_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_a_bits_source = auto_anon_in_4_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_4_a_bits_address = auto_anon_in_4_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_4_a_bits_mask = auto_anon_in_4_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_4_a_bits_data = auto_anon_in_4_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_4_a_bits_corrupt = auto_anon_in_4_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_4_b_ready = auto_anon_in_4_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_4_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_4_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_4_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_4_c_ready; // @[MixedNode.scala:551:17] wire anonIn_4_c_valid = auto_anon_in_4_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_c_bits_opcode = auto_anon_in_4_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_c_bits_param = auto_anon_in_4_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_c_bits_size = auto_anon_in_4_c_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_c_bits_source = auto_anon_in_4_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_4_c_bits_address = auto_anon_in_4_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_4_c_bits_data = auto_anon_in_4_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_4_c_bits_corrupt = auto_anon_in_4_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_4_d_ready = auto_anon_in_4_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_4_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_4_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_4_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_4_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_4_e_ready; // @[MixedNode.scala:551:17] wire anonIn_4_e_valid = auto_anon_in_4_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_3_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_e_bits_sink = auto_anon_in_4_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_3_a_valid = auto_anon_in_3_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_a_bits_opcode = auto_anon_in_3_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_a_bits_param = auto_anon_in_3_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_a_bits_size = auto_anon_in_3_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_a_bits_source = auto_anon_in_3_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_3_a_bits_address = auto_anon_in_3_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_3_a_bits_mask = auto_anon_in_3_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_3_a_bits_data = auto_anon_in_3_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_3_a_bits_corrupt = auto_anon_in_3_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_3_b_ready = auto_anon_in_3_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_3_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_3_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_3_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_3_c_ready; // @[MixedNode.scala:551:17] wire anonIn_3_c_valid = auto_anon_in_3_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_c_bits_opcode = auto_anon_in_3_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_c_bits_param = auto_anon_in_3_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_c_bits_size = auto_anon_in_3_c_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_c_bits_source = auto_anon_in_3_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_3_c_bits_address = auto_anon_in_3_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_3_c_bits_data = auto_anon_in_3_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_3_c_bits_corrupt = auto_anon_in_3_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_3_d_ready = auto_anon_in_3_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_3_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_3_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_3_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_3_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_3_e_ready; // @[MixedNode.scala:551:17] wire anonIn_3_e_valid = auto_anon_in_3_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_e_bits_sink = auto_anon_in_3_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_param = auto_anon_in_2_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_a_bits_size = auto_anon_in_2_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_a_bits_source = auto_anon_in_2_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_2_a_bits_mask = auto_anon_in_2_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_2_a_bits_data = auto_anon_in_2_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_b_ready = auto_anon_in_2_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_2_c_ready; // @[MixedNode.scala:551:17] wire anonIn_2_c_valid = auto_anon_in_2_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_opcode = auto_anon_in_2_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_param = auto_anon_in_2_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_c_bits_size = auto_anon_in_2_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_c_bits_source = auto_anon_in_2_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_c_bits_address = auto_anon_in_2_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_2_c_bits_data = auto_anon_in_2_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_c_bits_corrupt = auto_anon_in_2_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_d_ready = auto_anon_in_2_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_2_e_ready; // @[MixedNode.scala:551:17] wire anonIn_2_e_valid = auto_anon_in_2_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_e_bits_sink = auto_anon_in_2_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_b_bits_source = auto_anon_out_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_4_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_4_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_3_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_3_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_b_ready = anonIn_1_b_ready; // @[Xbar.scala:159:18] wire in_1_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_1_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_1_b_bits_source_0 = anonIn_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_1_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[Xbar.scala:74:9] wire in_1_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[Xbar.scala:74:9] wire in_1_c_valid = anonIn_1_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = anonIn_1_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = anonIn_1_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = anonIn_1_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = anonIn_1_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_1_c_bits_data = anonIn_1_c_bits_data; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_e_ready_0 = anonIn_1_e_ready; // @[Xbar.scala:74:9] wire in_1_e_valid = anonIn_1_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_1_e_bits_sink = anonIn_1_e_bits_sink; // @[Xbar.scala:159:18] wire in_2_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9] wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_opcode = anonIn_2_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_param = anonIn_2_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_a_bits_size = anonIn_2_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_2_a_bits_mask = anonIn_2_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_2_a_bits_data = anonIn_2_a_bits_data; // @[Xbar.scala:159:18] wire in_2_a_bits_corrupt = anonIn_2_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_b_ready = anonIn_2_b_ready; // @[Xbar.scala:159:18] wire in_2_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_valid_0 = anonIn_2_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_2_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_param_0 = anonIn_2_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_2_b_bits_source_0 = anonIn_2_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_2_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_address_0 = anonIn_2_b_bits_address; // @[Xbar.scala:74:9] wire in_2_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_c_ready_0 = anonIn_2_c_ready; // @[Xbar.scala:74:9] wire in_2_c_valid = anonIn_2_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_opcode = anonIn_2_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_param = anonIn_2_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_c_bits_size = anonIn_2_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_c_bits_address = anonIn_2_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_2_c_bits_data = anonIn_2_c_bits_data; // @[Xbar.scala:159:18] wire in_2_c_bits_corrupt = anonIn_2_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_d_ready = anonIn_2_d_ready; // @[Xbar.scala:159:18] wire in_2_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] assign auto_anon_in_2_d_bits_source_0 = anonIn_2_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_2_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9] wire in_2_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_2_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9] wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_2_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_e_ready_0 = anonIn_2_e_ready; // @[Xbar.scala:74:9] wire in_2_e_valid = anonIn_2_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_2_e_bits_sink = anonIn_2_e_bits_sink; // @[Xbar.scala:159:18] wire in_3_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_a_ready_0 = anonIn_3_a_ready; // @[Xbar.scala:74:9] wire in_3_a_valid = anonIn_3_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_3_a_bits_opcode = anonIn_3_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_3_a_bits_param = anonIn_3_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_3_a_bits_size = anonIn_3_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_3_a_bits_address = anonIn_3_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_3_a_bits_mask = anonIn_3_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_3_a_bits_data = anonIn_3_a_bits_data; // @[Xbar.scala:159:18] wire in_3_a_bits_corrupt = anonIn_3_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_3_b_ready = anonIn_3_b_ready; // @[Xbar.scala:159:18] wire in_3_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_valid_0 = anonIn_3_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_3_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_bits_param_0 = anonIn_3_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] _anonIn_b_bits_source_T_2; // @[Xbar.scala:156:69] assign auto_anon_in_3_b_bits_source_0 = anonIn_3_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_3_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_bits_address_0 = anonIn_3_b_bits_address; // @[Xbar.scala:74:9] wire in_3_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_c_ready_0 = anonIn_3_c_ready; // @[Xbar.scala:74:9] wire in_3_c_valid = anonIn_3_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_3_c_bits_opcode = anonIn_3_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_3_c_bits_param = anonIn_3_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_3_c_bits_size = anonIn_3_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_3_c_bits_address = anonIn_3_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_3_c_bits_data = anonIn_3_c_bits_data; // @[Xbar.scala:159:18] wire in_3_c_bits_corrupt = anonIn_3_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_3_d_ready = anonIn_3_d_ready; // @[Xbar.scala:159:18] wire in_3_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_valid_0 = anonIn_3_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_3_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_opcode_0 = anonIn_3_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_3_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_param_0 = anonIn_3_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_3_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_size_0 = anonIn_3_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69] assign auto_anon_in_3_d_bits_source_0 = anonIn_3_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_3_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_sink_0 = anonIn_3_d_bits_sink; // @[Xbar.scala:74:9] wire in_3_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_denied_0 = anonIn_3_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_3_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_data_0 = anonIn_3_d_bits_data; // @[Xbar.scala:74:9] wire in_3_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_corrupt_0 = anonIn_3_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_3_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_e_ready_0 = anonIn_3_e_ready; // @[Xbar.scala:74:9] wire in_3_e_valid = anonIn_3_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_3_e_bits_sink = anonIn_3_e_bits_sink; // @[Xbar.scala:159:18] wire in_4_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_a_ready_0 = anonIn_4_a_ready; // @[Xbar.scala:74:9] wire in_4_a_valid = anonIn_4_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_4_a_bits_opcode = anonIn_4_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_4_a_bits_param = anonIn_4_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_4_a_bits_size = anonIn_4_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_4_a_bits_address = anonIn_4_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_4_a_bits_mask = anonIn_4_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_4_a_bits_data = anonIn_4_a_bits_data; // @[Xbar.scala:159:18] wire in_4_a_bits_corrupt = anonIn_4_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_4_b_ready = anonIn_4_b_ready; // @[Xbar.scala:159:18] wire in_4_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_valid_0 = anonIn_4_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_4_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_bits_param_0 = anonIn_4_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] _anonIn_b_bits_source_T_3; // @[Xbar.scala:156:69] assign auto_anon_in_4_b_bits_source_0 = anonIn_4_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_4_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_bits_address_0 = anonIn_4_b_bits_address; // @[Xbar.scala:74:9] wire in_4_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_c_ready_0 = anonIn_4_c_ready; // @[Xbar.scala:74:9] wire in_4_c_valid = anonIn_4_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_4_c_bits_opcode = anonIn_4_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_4_c_bits_param = anonIn_4_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_4_c_bits_size = anonIn_4_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_4_c_bits_address = anonIn_4_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_4_c_bits_data = anonIn_4_c_bits_data; // @[Xbar.scala:159:18] wire in_4_c_bits_corrupt = anonIn_4_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_4_d_ready = anonIn_4_d_ready; // @[Xbar.scala:159:18] wire in_4_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_valid_0 = anonIn_4_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_4_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_opcode_0 = anonIn_4_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_4_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_param_0 = anonIn_4_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_4_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_size_0 = anonIn_4_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69] assign auto_anon_in_4_d_bits_source_0 = anonIn_4_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_4_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_sink_0 = anonIn_4_d_bits_sink; // @[Xbar.scala:74:9] wire in_4_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_denied_0 = anonIn_4_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_4_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_data_0 = anonIn_4_d_bits_data; // @[Xbar.scala:74:9] wire in_4_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_corrupt_0 = anonIn_4_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_4_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_e_ready_0 = anonIn_4_e_ready; // @[Xbar.scala:74:9] wire in_4_e_valid = anonIn_4_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_4_e_bits_sink = anonIn_4_e_bits_sink; // @[Xbar.scala:159:18] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[Xbar.scala:74:9] wire out_1_b_valid = x1_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] out_1_b_bits_param = x1_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_1_b_bits_source = x1_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_1_b_bits_address = x1_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire out_1_c_ready = x1_anonOut_c_ready; // @[Xbar.scala:216:19] wire out_1_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] out_1_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_1_c_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[Xbar.scala:74:9] wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_ready = in_1_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_b_valid = in_1_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_param = in_1_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_address = in_1_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_c_ready = in_1_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_1_0_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_1_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_1_0_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_1_1_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_1_0_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_1_1_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_10 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_15 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_1_0_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_1_1_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_1_0_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_1_1_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_0_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_1_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_e_ready = in_1_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_3 = in_1_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_1 = in_1_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_1_0_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_1_1_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_2_0_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_0_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_2_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_2_0_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_2_1_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_2_0_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_2_1_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_56 = in_2_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_2_1_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_2_0_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_2_1_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_2_0_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_2_1_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_0_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_1_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_ready = in_2_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_valid; // @[Xbar.scala:352:24] assign anonIn_2_b_valid = in_2_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_param = in_2_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_address = in_2_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_c_ready = in_2_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_2_0_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_0_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_2_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_2_0_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_2_1_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_2_0_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_2_1_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_20 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_25 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_2_0_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_2_1_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_2_0_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_2_1_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_0_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_1_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_2_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_e_ready = in_2_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_5 = in_2_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_2 = in_2_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_2_0_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_2_1_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_3_a_ready = in_3_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_3_0_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_1_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_0_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_1_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_3_0_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_3_1_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_3_0_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_3_1_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_84 = in_3_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_3_0_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_3_1_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_3_0_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_3_1_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_3_0_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_3_1_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_3_0_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_3_1_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_3_ready = in_3_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_3_valid; // @[Xbar.scala:352:24] assign anonIn_3_b_valid = in_3_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_3_bits_param; // @[Xbar.scala:352:24] assign anonIn_3_b_bits_param = in_3_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_3_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_3_bits_address; // @[Xbar.scala:352:24] assign anonIn_3_b_bits_address = in_3_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_3_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_3_c_ready = in_3_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_7 = in_3_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_7 = in_3_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_3_0_bits_opcode = in_3_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_1_bits_opcode = in_3_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_0_bits_param = in_3_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_1_bits_param = in_3_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_3_0_bits_size = in_3_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_3_1_bits_size = in_3_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_3_0_bits_source = in_3_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_3_1_bits_source = in_3_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_30 = in_3_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_35 = in_3_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_3_0_bits_address = in_3_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_3_1_bits_address = in_3_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_3_0_bits_data = in_3_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_3_1_bits_data = in_3_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_3_0_bits_corrupt = in_3_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_3_1_bits_corrupt = in_3_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_3_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_3_d_valid = in_3_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_3_d_bits_opcode = in_3_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_3_d_bits_param = in_3_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_3_d_bits_size = in_3_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_3_d_bits_sink = in_3_d_bits_sink; // @[Xbar.scala:159:18] wire _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_3_d_bits_denied = in_3_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_3_d_bits_data = in_3_d_bits_data; // @[Xbar.scala:159:18] wire _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_3_d_bits_corrupt = in_3_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_3_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_3_e_ready = in_3_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_7 = in_3_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_3 = in_3_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_3_0_bits_sink = in_3_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_3_1_bits_sink = in_3_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_4_a_ready = in_4_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_4_0_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_1_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_0_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_1_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_4_0_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_4_1_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_4_0_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_4_1_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_112 = in_4_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_4_0_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_4_1_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_4_0_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_4_1_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_4_0_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_4_1_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_4_0_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_4_1_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_4_ready = in_4_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_4_valid; // @[Xbar.scala:352:24] assign anonIn_4_b_valid = in_4_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_4_bits_param; // @[Xbar.scala:352:24] assign anonIn_4_b_bits_param = in_4_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_4_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_4_bits_address; // @[Xbar.scala:352:24] assign anonIn_4_b_bits_address = in_4_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_4_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_4_c_ready = in_4_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_9 = in_4_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_9 = in_4_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_4_0_bits_opcode = in_4_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_1_bits_opcode = in_4_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_0_bits_param = in_4_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_1_bits_param = in_4_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_4_0_bits_size = in_4_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_4_1_bits_size = in_4_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_4_0_bits_source = in_4_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_4_1_bits_source = in_4_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_40 = in_4_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_45 = in_4_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_4_0_bits_address = in_4_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_4_1_bits_address = in_4_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_4_0_bits_data = in_4_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_4_1_bits_data = in_4_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_4_0_bits_corrupt = in_4_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_4_1_bits_corrupt = in_4_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_4_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_4_d_valid = in_4_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_4_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_4_d_bits_opcode = in_4_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_4_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_4_d_bits_param = in_4_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_4_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_4_d_bits_size = in_4_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_4_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_4_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_4_d_bits_sink = in_4_d_bits_sink; // @[Xbar.scala:159:18] wire _in_4_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_4_d_bits_denied = in_4_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_4_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_4_d_bits_data = in_4_d_bits_data; // @[Xbar.scala:159:18] wire _in_4_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_4_d_bits_corrupt = in_4_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_4_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_4_e_ready = in_4_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_9 = in_4_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_4 = in_4_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] portsEOI_filtered_4_0_bits_sink = in_4_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_4_1_bits_sink = in_4_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {2'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_a_bits_source_T = {5'h11, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T = in_1_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_c_bits_source_T = {5'h11, anonIn_1_c_bits_source}; // @[Xbar.scala:187:55] assign in_1_c_bits_source = _in_1_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_a_bits_source_T = {5'h10, anonIn_2_a_bits_source}; // @[Xbar.scala:166:55] assign in_2_a_bits_source = _in_2_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T_1 = in_2_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_b_bits_source = _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_c_bits_source_T = {5'h10, anonIn_2_c_bits_source}; // @[Xbar.scala:187:55] assign in_2_c_bits_source = _in_2_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_2 = in_2_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_d_bits_source = _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] wire [5:0] _in_3_a_bits_source_T = {2'h3, anonIn_3_a_bits_source}; // @[Xbar.scala:166:55] assign in_3_a_bits_source = {1'h0, _in_3_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T_2 = in_3_b_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_3_b_bits_source = _anonIn_b_bits_source_T_2; // @[Xbar.scala:156:69] wire [5:0] _in_3_c_bits_source_T = {2'h3, anonIn_3_c_bits_source}; // @[Xbar.scala:187:55] assign in_3_c_bits_source = {1'h0, _in_3_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T_3 = in_3_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_3_d_bits_source = _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69] wire [5:0] _in_4_a_bits_source_T = {2'h2, anonIn_4_a_bits_source}; // @[Xbar.scala:166:55] assign in_4_a_bits_source = {1'h0, _in_4_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T_3 = in_4_b_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_4_b_bits_source = _anonIn_b_bits_source_T_3; // @[Xbar.scala:156:69] wire [5:0] _in_4_c_bits_source_T = {2'h2, anonIn_4_c_bits_source}; // @[Xbar.scala:187:55] assign in_4_c_bits_source = {1'h0, _in_4_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T_4 = in_4_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_4_d_bits_source = _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_13; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [6:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_3_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_4_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_3_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_4_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_3_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_4_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_2 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_3 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_4 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_3_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_4_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_3_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_4_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_3_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_4_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_3_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_4_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_3_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_4_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_a_valid_T_13; // @[Arbiter.scala:96:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] wire [15:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_b_ready = out_1_b_ready; // @[Xbar.scala:216:19] wire [1:0] portsBIO_filtered_1_0_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestBOI_uncommonBits_T_5 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_6 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_7 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_8 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_9 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsBIO_filtered_1_0_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_0_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire _out_1_c_valid_T_10; // @[Arbiter.scala:96:24] assign x1_anonOut_c_valid = out_1_c_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_opcode = out_1_c_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_param = out_1_c_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_source = out_1_c_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_address = out_1_c_bits_address; // @[Xbar.scala:216:19] wire [127:0] _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_data = out_1_c_bits_data; // @[Xbar.scala:216:19] wire _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_corrupt = out_1_c_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_2_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_3_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_4_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_2_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_3_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_4_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_2_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_3_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_4_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_5 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_6 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_7 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_8 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_9 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_2_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_3_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_4_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_2_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_3_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_4_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_3_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_4_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_2_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_3_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_4_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_3_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_4_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_e_valid_T_10; // @[Arbiter.scala:96:24] assign x1_anonOut_e_valid = out_1_e_valid; // @[Xbar.scala:216:19] wire _beatsLeft_T_12 = out_1_e_valid; // @[Decoupled.scala:51:35] wire [3:0] _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_1_e_bits_sink; // @[Xbar.scala:156:69, :216:19] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_1_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = {3'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_c_bits_size = out_1_c_bits_size[2:0]; // @[Xbar.scala:216:19, :241:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_4 \| _requestAIO_T_9; // @[Xbar.scala:291:92] wire _requestAIO_T_16 = _requestAIO_T_15 \| _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46] wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46] wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_27 = _requestAIO_T_21 \| _requestAIO_T_26; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46] wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46] wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46] wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_43 = _requestAIO_T_32 \| _requestAIO_T_37; // @[Xbar.scala:291:92] wire _requestAIO_T_44 = _requestAIO_T_43 \| _requestAIO_T_42; // @[Xbar.scala:291:92] wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46] wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46] wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_55 = _requestAIO_T_49 \| _requestAIO_T_54; // @[Xbar.scala:291:92] wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_57 = {1'h0, _requestAIO_T_56}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_58 = _requestAIO_T_57 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_59 = _requestAIO_T_58; // @[Parameters.scala:137:46] wire _requestAIO_T_60 = _requestAIO_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_61 = {in_2_a_bits_address[31:17], in_2_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_62 = {1'h0, _requestAIO_T_61}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_63 = _requestAIO_T_62 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_64 = _requestAIO_T_63; // @[Parameters.scala:137:46] wire _requestAIO_T_65 = _requestAIO_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_66 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_67 = {1'h0, _requestAIO_T_66}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_68 = _requestAIO_T_67 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_69 = _requestAIO_T_68; // @[Parameters.scala:137:46] wire _requestAIO_T_70 = _requestAIO_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_71 = _requestAIO_T_60 \| _requestAIO_T_65; // @[Xbar.scala:291:92] wire _requestAIO_T_72 = _requestAIO_T_71 \| _requestAIO_T_70; // @[Xbar.scala:291:92] wire requestAIO_2_0 = _requestAIO_T_72; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_4 = requestAIO_2_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_73 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_74 = {1'h0, _requestAIO_T_73}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_75 = _requestAIO_T_74 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_76 = _requestAIO_T_75; // @[Parameters.scala:137:46] wire _requestAIO_T_77 = _requestAIO_T_76 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_78 = in_2_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_79 = {1'h0, _requestAIO_T_78}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_80 = _requestAIO_T_79 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_81 = _requestAIO_T_80; // @[Parameters.scala:137:46] wire _requestAIO_T_82 = _requestAIO_T_81 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_83 = _requestAIO_T_77 \| _requestAIO_T_82; // @[Xbar.scala:291:92] wire requestAIO_2_1 = _requestAIO_T_83; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_4 = requestAIO_2_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_85 = {1'h0, _requestAIO_T_84}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_86 = _requestAIO_T_85 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_87 = _requestAIO_T_86; // @[Parameters.scala:137:46] wire _requestAIO_T_88 = _requestAIO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_89 = {in_3_a_bits_address[31:17], in_3_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_90 = {1'h0, _requestAIO_T_89}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_91 = _requestAIO_T_90 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_92 = _requestAIO_T_91; // @[Parameters.scala:137:46] wire _requestAIO_T_93 = _requestAIO_T_92 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_94 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_95 = {1'h0, _requestAIO_T_94}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_96 = _requestAIO_T_95 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_97 = _requestAIO_T_96; // @[Parameters.scala:137:46] wire _requestAIO_T_98 = _requestAIO_T_97 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_99 = _requestAIO_T_88 \| _requestAIO_T_93; // @[Xbar.scala:291:92] wire _requestAIO_T_100 = _requestAIO_T_99 \| _requestAIO_T_98; // @[Xbar.scala:291:92] wire requestAIO_3_0 = _requestAIO_T_100; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_6 = requestAIO_3_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_101 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_102 = {1'h0, _requestAIO_T_101}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_103 = _requestAIO_T_102 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_104 = _requestAIO_T_103; // @[Parameters.scala:137:46] wire _requestAIO_T_105 = _requestAIO_T_104 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_106 = in_3_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_107 = {1'h0, _requestAIO_T_106}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_108 = _requestAIO_T_107 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_109 = _requestAIO_T_108; // @[Parameters.scala:137:46] wire _requestAIO_T_110 = _requestAIO_T_109 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_111 = _requestAIO_T_105 \| _requestAIO_T_110; // @[Xbar.scala:291:92] wire requestAIO_3_1 = _requestAIO_T_111; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_6 = requestAIO_3_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_113 = {1'h0, _requestAIO_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_114 = _requestAIO_T_113 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_115 = _requestAIO_T_114; // @[Parameters.scala:137:46] wire _requestAIO_T_116 = _requestAIO_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_117 = {in_4_a_bits_address[31:17], in_4_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_118 = {1'h0, _requestAIO_T_117}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_119 = _requestAIO_T_118 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_120 = _requestAIO_T_119; // @[Parameters.scala:137:46] wire _requestAIO_T_121 = _requestAIO_T_120 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_122 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_123 = {1'h0, _requestAIO_T_122}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_124 = _requestAIO_T_123 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_125 = _requestAIO_T_124; // @[Parameters.scala:137:46] wire _requestAIO_T_126 = _requestAIO_T_125 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_127 = _requestAIO_T_116 \| _requestAIO_T_121; // @[Xbar.scala:291:92] wire _requestAIO_T_128 = _requestAIO_T_127 \| _requestAIO_T_126; // @[Xbar.scala:291:92] wire requestAIO_4_0 = _requestAIO_T_128; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_8 = requestAIO_4_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_129 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_130 = {1'h0, _requestAIO_T_129}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_131 = _requestAIO_T_130 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_132 = _requestAIO_T_131; // @[Parameters.scala:137:46] wire _requestAIO_T_133 = _requestAIO_T_132 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_134 = in_4_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_135 = {1'h0, _requestAIO_T_134}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_136 = _requestAIO_T_135 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_137 = _requestAIO_T_136; // @[Parameters.scala:137:46] wire _requestAIO_T_138 = _requestAIO_T_137 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_139 = _requestAIO_T_133 \| _requestAIO_T_138; // @[Xbar.scala:291:92] wire requestAIO_4_1 = _requestAIO_T_139; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_8 = requestAIO_4_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestCIO_T_11 = {1'h0, _requestCIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_16 = {1'h0, _requestCIO_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_21 = {1'h0, _requestCIO_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_26 = {1'h0, _requestCIO_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_31 = {1'h0, _requestCIO_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_36 = {1'h0, _requestCIO_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_41 = {1'h0, _requestCIO_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_46 = {1'h0, _requestCIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [4:0] requestBOI_uncommonBits_5 = _requestBOI_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestBOI_T_25 = out_1_b_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestBOI_T_26 = _requestBOI_T_25 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_28 = _requestBOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_0 = _requestBOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T_2 = requestBOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_6 = _requestBOI_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestBOI_T_30 = out_1_b_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestBOI_T_35 = out_1_b_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestBOI_T_31 = _requestBOI_T_30 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_33 = _requestBOI_T_31; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_1 = _requestBOI_T_33; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_1_valid_T_2 = requestBOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_7 = _requestBOI_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_36 = _requestBOI_T_35 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_38 = _requestBOI_T_36; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_2 = _requestBOI_T_38; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_2_valid_T_2 = requestBOI_1_2; // @[Xbar.scala:355:54] wire [3:0] requestBOI_uncommonBits_8 = _requestBOI_uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestBOI_T_40 = out_1_b_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestBOI_T_45 = out_1_b_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestBOI_T_41 = _requestBOI_T_40 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_43 = _requestBOI_T_41; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_3 = _requestBOI_T_43; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_3_valid_T_2 = requestBOI_1_3; // @[Xbar.scala:355:54] wire [3:0] requestBOI_uncommonBits_9 = _requestBOI_uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_46 = _requestBOI_T_45 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_48 = _requestBOI_T_46; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_4 = _requestBOI_T_48; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_4_valid_T_2 = requestBOI_1_4; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestDOI_T = out_0_d_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = _requestDOI_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_5 = out_0_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestDOI_T_10 = out_0_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_6 = _requestDOI_T_5 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_11 = _requestDOI_T_10 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_2 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestDOI_T_15 = out_0_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestDOI_T_20 = out_0_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestDOI_T_16 = _requestDOI_T_15 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_3 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_3_valid_T = requestDOI_0_3; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_21 = _requestDOI_T_20 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_23 = _requestDOI_T_21; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_4 = _requestDOI_T_23; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_4_valid_T = requestDOI_0_4; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestDOI_T_25 = out_1_d_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestDOI_T_26 = _requestDOI_T_25 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_28 = _requestDOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_0 = _requestDOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_6 = _requestDOI_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_30 = out_1_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestDOI_T_35 = out_1_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_31 = _requestDOI_T_30 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_33 = _requestDOI_T_31; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_1 = _requestDOI_T_33; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_7 = _requestDOI_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_36 = _requestDOI_T_35 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_38 = _requestDOI_T_36; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_2 = _requestDOI_T_38; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T_2 = requestDOI_1_2; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_8 = _requestDOI_uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestDOI_T_40 = out_1_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestDOI_T_45 = out_1_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestDOI_T_41 = _requestDOI_T_40 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_43 = _requestDOI_T_41; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_3 = _requestDOI_T_43; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_3_valid_T_2 = requestDOI_1_3; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_9 = _requestDOI_uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_46 = _requestDOI_T_45 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_48 = _requestDOI_T_46; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_4 = _requestDOI_T_48; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_4_valid_T_2 = requestDOI_1_4; // @[Xbar.scala:355:54] wire [3:0] requestEIO_uncommonBits_1 = _requestEIO_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_2 = _requestEIO_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_3 = _requestEIO_uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_4 = _requestEIO_uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_6 = 27'hFFF << in_2_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_7 = _beatsAI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_8 = ~_beatsAI_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_2 = _beatsAI_decode_T_8[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_2 = in_2_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_2 = ~_beatsAI_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_2 = beatsAI_opdata_2 ? beatsAI_decode_2 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_9 = 27'hFFF << in_3_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_10 = _beatsAI_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_11 = ~_beatsAI_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_3 = _beatsAI_decode_T_11[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_3 = in_3_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_3 = ~_beatsAI_opdata_T_3; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_3 = beatsAI_opdata_3 ? beatsAI_decode_3 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_12 = 27'hFFF << in_4_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_13 = _beatsAI_decode_T_12[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_14 = ~_beatsAI_decode_T_13; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_4 = _beatsAI_decode_T_14[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_4 = in_4_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_4 = ~_beatsAI_opdata_T_4; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_4 = beatsAI_opdata_4 ? beatsAI_decode_4 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF << in_1_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_4 = _beatsCI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_5 = ~_beatsCI_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_1 = _beatsCI_decode_T_5[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_1 = in_1_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_1 = beatsCI_opdata_1 ? beatsCI_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_6 = 27'hFFF << in_2_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_7 = _beatsCI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_8 = ~_beatsCI_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_2 = _beatsCI_decode_T_8[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_2 = in_2_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_2 = beatsCI_opdata_2 ? beatsCI_decode_2 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_9 = 27'hFFF << in_3_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_10 = _beatsCI_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_11 = ~_beatsCI_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_3 = _beatsCI_decode_T_11[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_3 = in_3_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_3 = beatsCI_opdata_3 ? beatsCI_decode_3 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_12 = 27'hFFF << in_4_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_13 = _beatsCI_decode_T_12[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_14 = ~_beatsCI_decode_T_13; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_4 = _beatsCI_decode_T_14[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_4 = in_4_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_4 = beatsCI_opdata_4 ? beatsCI_decode_4 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:4]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T \| _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73] assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:355:40] wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_5 = in_2_a_valid & _portsAOI_filtered_0_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_5 = in_2_a_valid & _portsAOI_filtered_1_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_1_valid = _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_2_a_ready_T = requestAIO_2_0 & portsAOI_filtered_2_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_1 = requestAIO_2_1 & portsAOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_2 = _portsAOI_in_2_a_ready_T \| _portsAOI_in_2_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_2_a_ready_WIRE = _portsAOI_in_2_a_ready_T_2; // @[Mux.scala:30:73] assign in_2_a_ready = _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:355:40] wire portsAOI_filtered_3_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_7 = in_3_a_valid & _portsAOI_filtered_0_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_3_0_valid = _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_7 = in_3_a_valid & _portsAOI_filtered_1_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_3_1_valid = _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_3_a_ready_T = requestAIO_3_0 & portsAOI_filtered_3_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_3_a_ready_T_1 = requestAIO_3_1 & portsAOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_3_a_ready_T_2 = _portsAOI_in_3_a_ready_T \| _portsAOI_in_3_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_3_a_ready_WIRE = _portsAOI_in_3_a_ready_T_2; // @[Mux.scala:30:73] assign in_3_a_ready = _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_4; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:355:40] wire portsAOI_filtered_4_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_9 = in_4_a_valid & _portsAOI_filtered_0_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_4_0_valid = _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_9 = in_4_a_valid & _portsAOI_filtered_1_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_4_1_valid = _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_4_a_ready_T = requestAIO_4_0 & portsAOI_filtered_4_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_4_a_ready_T_1 = requestAIO_4_1 & portsAOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_4_a_ready_T_2 = _portsAOI_in_4_a_ready_T \| _portsAOI_in_4_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_4_a_ready_WIRE = _portsAOI_in_4_a_ready_T_2; // @[Mux.scala:30:73] assign in_4_a_ready = _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73] wire _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] assign in_1_b_valid = portsBIO_filtered_1_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_param = portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_source = portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_address = portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] assign in_2_b_valid = portsBIO_filtered_1_2_valid; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_param = portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_source = portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_address = portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_3_valid_T_3; // @[Xbar.scala:355:40] assign in_3_b_valid = portsBIO_filtered_1_3_valid; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_param = portsBIO_filtered_1_3_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_source = portsBIO_filtered_1_3_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_address = portsBIO_filtered_1_3_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_4_valid_T_3; // @[Xbar.scala:355:40] assign in_4_b_valid = portsBIO_filtered_1_4_valid; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_param = portsBIO_filtered_1_4_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_source = portsBIO_filtered_1_4_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_address = portsBIO_filtered_1_4_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_3 = out_1_b_valid & _portsBIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_0_valid = _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_3 = out_1_b_valid & _portsBIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_1_valid = _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_2_valid_T_3 = out_1_b_valid & _portsBIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_2_valid = _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_3_valid_T_3 = out_1_b_valid & _portsBIO_filtered_3_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_3_valid = _portsBIO_filtered_3_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_4_valid_T_3 = out_1_b_valid & _portsBIO_filtered_4_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_4_valid = _portsBIO_filtered_4_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_1_b_ready_T_1 = requestBOI_1_1 & portsBIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_5 = _portsBIO_out_1_b_ready_T_1; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_2 = requestBOI_1_2 & portsBIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_3 = requestBOI_1_3 & portsBIO_filtered_1_3_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_4 = requestBOI_1_4 & portsBIO_filtered_1_4_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_6 = _portsBIO_out_1_b_ready_T_5 \| _portsBIO_out_1_b_ready_T_2; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_7 = _portsBIO_out_1_b_ready_T_6 \| _portsBIO_out_1_b_ready_T_3; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_8 = _portsBIO_out_1_b_ready_T_7 \| _portsBIO_out_1_b_ready_T_4; // @[Mux.scala:30:73] assign _portsBIO_out_1_b_ready_WIRE = _portsBIO_out_1_b_ready_T_8; // @[Mux.scala:30:73] assign out_1_b_ready = _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_5; // @[Arbiter.scala:94:31] wire _portsCOI_in_1_c_ready_T_1 = portsCOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_1_0_valid = _portsCOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_1_1_valid = _portsCOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_1_c_ready_T_2 = _portsCOI_in_1_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_1_c_ready_WIRE = _portsCOI_in_1_c_ready_T_2; // @[Mux.scala:30:73] assign in_1_c_ready = _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_6; // @[Arbiter.scala:94:31] wire _portsCOI_in_2_c_ready_T_1 = portsCOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_2_0_valid = _portsCOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_2_1_valid = _portsCOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_2_c_ready_T_2 = _portsCOI_in_2_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_2_c_ready_WIRE = _portsCOI_in_2_c_ready_T_2; // @[Mux.scala:30:73] assign in_2_c_ready = _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_7; // @[Arbiter.scala:94:31] wire _portsCOI_in_3_c_ready_T_1 = portsCOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_3_0_valid = _portsCOI_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_3_1_valid = _portsCOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_3_c_ready_T_2 = _portsCOI_in_3_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_3_c_ready_WIRE = _portsCOI_in_3_c_ready_T_2; // @[Mux.scala:30:73] assign in_3_c_ready = _portsCOI_in_3_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_8; // @[Arbiter.scala:94:31] wire _portsCOI_in_4_c_ready_T_1 = portsCOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_4_0_valid = _portsCOI_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_4_1_valid = _portsCOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_4_c_ready_T_2 = _portsCOI_in_4_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_4_c_ready_WIRE = _portsCOI_in_4_c_ready_T_2; // @[Mux.scala:30:73] assign in_4_c_ready = _portsCOI_in_4_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_5; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_13; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_2_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_3_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_4_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_3_valid_T_1 = out_0_d_valid & _portsDIO_filtered_3_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_3_valid = _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_4_valid_T_1 = out_0_d_valid & _portsDIO_filtered_4_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_4_valid = _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2 & portsDIO_filtered_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_3 = requestDOI_0_3 & portsDIO_filtered_3_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_4 = requestDOI_0_4 & portsDIO_filtered_4_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_5 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_6 = _portsDIO_out_0_d_ready_T_5 \| _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_7 = _portsDIO_out_0_d_ready_T_6 \| _portsDIO_out_0_d_ready_T_3; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_8 = _portsDIO_out_0_d_ready_T_7 \| _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_8; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_6; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_14; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_2_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_3_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_4_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_3_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_4_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_3 = out_1_d_valid & _portsDIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_2_valid = _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_3_valid_T_3 = out_1_d_valid & _portsDIO_filtered_3_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_3_valid = _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_4_valid_T_3 = out_1_d_valid & _portsDIO_filtered_4_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_4_valid = _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_2 = requestDOI_1_2 & portsDIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_3 = requestDOI_1_3 & portsDIO_filtered_1_3_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_4 = requestDOI_1_4 & portsDIO_filtered_1_4_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_5 = _portsDIO_out_1_d_ready_T \| _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_6 = _portsDIO_out_1_d_ready_T_5 \| _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_7 = _portsDIO_out_1_d_ready_T_6 \| _portsDIO_out_1_d_ready_T_3; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_8 = _portsDIO_out_1_d_ready_T_7 \| _portsDIO_out_1_d_ready_T_4; // @[Mux.scala:30:73] assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_8; // @[Mux.scala:30:73] assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_9; // @[Arbiter.scala:94:31] wire _portsEOI_in_1_e_ready_T_1 = portsEOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_1_1_valid = _portsEOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_1_e_ready_T_2 = _portsEOI_in_1_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_1_e_ready_WIRE = _portsEOI_in_1_e_ready_T_2; // @[Mux.scala:30:73] assign in_1_e_ready = _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_10; // @[Arbiter.scala:94:31] wire _portsEOI_in_2_e_ready_T_1 = portsEOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_valid = _portsEOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_2_e_ready_T_2 = _portsEOI_in_2_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_2_e_ready_WIRE = _portsEOI_in_2_e_ready_T_2; // @[Mux.scala:30:73] assign in_2_e_ready = _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_11; // @[Arbiter.scala:94:31] wire _portsEOI_in_3_e_ready_T_1 = portsEOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_3_1_valid = _portsEOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_3_e_ready_T_2 = _portsEOI_in_3_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_3_e_ready_WIRE = _portsEOI_in_3_e_ready_T_2; // @[Mux.scala:30:73] assign in_3_e_ready = _portsEOI_in_3_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_12; // @[Arbiter.scala:94:31] wire _portsEOI_in_4_e_ready_T_1 = portsEOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_4_1_valid = _portsEOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_4_e_ready_T_2 = _portsEOI_in_4_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_4_e_ready_WIRE = _portsEOI_in_4_e_ready_T_2; // @[Mux.scala:30:73] assign in_4_e_ready = _portsEOI_in_4_e_ready_WIRE; // @[Mux.scala:30:73] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_hi = {portsAOI_filtered_4_0_valid, portsAOI_filtered_3_0_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_hi = {readys_hi_hi, portsAOI_filtered_2_0_valid}; // @[Xbar.scala:352:24] wire [4:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51] wire [4:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [4:0] readys_mask; // @[Arbiter.scala:23:23] wire [4:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [4:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [9:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [8:0] _readys_unready_T = readys_filter[9:1]; // @[package.scala:262:48] wire [9:0] _readys_unready_T_1 = {readys_filter[9], readys_filter[8:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_2 = _readys_unready_T_1[9:2]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_3 = {_readys_unready_T_1[9:8], _readys_unready_T_1[7:0] \| _readys_unready_T_2}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_4 = _readys_unready_T_3[9:4]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_5 = {_readys_unready_T_3[9:6], _readys_unready_T_3[5:0] \| _readys_unready_T_4}; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_6 = _readys_unready_T_5; // @[package.scala:262:43, :263:17] wire [8:0] _readys_unready_T_7 = _readys_unready_T_6[9:1]; // @[package.scala:263:17] wire [9:0] _readys_unready_T_8 = {readys_mask, 5'h0}; // @[Arbiter.scala:23:23, :25:66] wire [9:0] readys_unready = {1'h0, _readys_unready_T_7} \| _readys_unready_T_8; // @[Arbiter.scala:25:{52,58,66}] wire [4:0] _readys_readys_T = readys_unready[9:5]; // @[Arbiter.scala:25:58, :26:29] wire [4:0] _readys_readys_T_1 = readys_unready[4:0]; // @[Arbiter.scala:25:58, :26:48] wire [4:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [4:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [4:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [4:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [5:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [4:0] _readys_mask_T_2 = _readys_mask_T_1[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [6:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_5 = _readys_mask_T_4[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_6 = _readys_mask_T_3 \| _readys_mask_T_5; // @[package.scala:253:{43,53}] wire [8:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_8 = _readys_mask_T_7[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_9 = _readys_mask_T_6 \| _readys_mask_T_8; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_10 = _readys_mask_T_9; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}] wire _readys_T_11 = _readys_T_7[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_3 = _readys_T_11; // @[Arbiter.scala:68:{27,76}] wire _readys_T_12 = _readys_T_7[4]; // @[Arbiter.scala:30:11, :68:76] wire readys_4 = _readys_T_12; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_3 & portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_4 & portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3 = prefixOR_2 \| winner_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4 = prefixOR_3 \| winner_3; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_4 \| winner_4; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2 = winner_2 ? beatsAI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3 = winner_3 ? beatsAI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_4 = winner_4 ? beatsAI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T = maskedBeats_0 \| maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_1 = _initBeats_T \| maskedBeats_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_2 = _initBeats_T_1 \| maskedBeats_3; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats = _initBeats_T_2 \| maskedBeats_4; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {8'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_2 = _beatsLeft_T_1[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] reg state_3; // @[Arbiter.scala:88:26] reg state_4; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3 = idle ? winner_3 : state_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4 = idle ? winner_4 : state_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_2 = out_0_a_ready & allowed_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_3 = out_0_a_ready & allowed_3; // @[Xbar.scala:216:19] assign portsAOI_filtered_3_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_4 = out_0_a_ready & allowed_4; // @[Xbar.scala:216:19] assign portsAOI_filtered_4_0_ready = _filtered_0_ready_T_4; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_1 = _out_0_a_valid_T \| portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_2 = _out_0_a_valid_T_1 \| portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_3 = _out_0_a_valid_T_2 \| portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_4 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_5 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_6 = state_2 & portsAOI_filtered_2_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_7 = state_3 & portsAOI_filtered_3_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_8 = state_4 & portsAOI_filtered_4_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_9 = _out_0_a_valid_T_4 \| _out_0_a_valid_T_5; // @[Mux.scala:30:73] wire _out_0_a_valid_T_10 = _out_0_a_valid_T_9 \| _out_0_a_valid_T_6; // @[Mux.scala:30:73] wire _out_0_a_valid_T_11 = _out_0_a_valid_T_10 \| _out_0_a_valid_T_7; // @[Mux.scala:30:73] wire _out_0_a_valid_T_12 = _out_0_a_valid_T_11 \| _out_0_a_valid_T_8; // @[Mux.scala:30:73] wire _out_0_a_valid_WIRE = _out_0_a_valid_T_12; // @[Mux.scala:30:73] assign _out_0_a_valid_T_13 = idle ? _out_0_a_valid_T_3 : _out_0_a_valid_WIRE; // @[Mux.scala:30:73] assign out_0_a_valid = _out_0_a_valid_T_13; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = muxState_2 & portsAOI_filtered_2_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_3 = muxState_3 & portsAOI_filtered_3_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_4 = muxState_4 & portsAOI_filtered_4_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_5 = _out_0_a_bits_T \| _out_0_a_bits_T_1; // @[Mux.scala:30:73] wire _out_0_a_bits_T_6 = _out_0_a_bits_T_5 \| _out_0_a_bits_T_2; // @[Mux.scala:30:73] wire _out_0_a_bits_T_7 = _out_0_a_bits_T_6 \| _out_0_a_bits_T_3; // @[Mux.scala:30:73] wire _out_0_a_bits_T_8 = _out_0_a_bits_T_7 \| _out_0_a_bits_T_4; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_8; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_9 = muxState_0 ? portsAOI_filtered_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_10 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_11 = muxState_2 ? portsAOI_filtered_2_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_12 = muxState_3 ? portsAOI_filtered_3_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_13 = muxState_4 ? portsAOI_filtered_4_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_9 \| _out_0_a_bits_T_10; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_15 = _out_0_a_bits_T_14 \| _out_0_a_bits_T_11; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_16 = _out_0_a_bits_T_15 \| _out_0_a_bits_T_12; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_17 = _out_0_a_bits_T_16 \| _out_0_a_bits_T_13; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_17; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_18 = muxState_0 ? portsAOI_filtered_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_19 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_20 = muxState_2 ? portsAOI_filtered_2_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_21 = muxState_3 ? portsAOI_filtered_3_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_22 = muxState_4 ? portsAOI_filtered_4_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_18 \| _out_0_a_bits_T_19; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_24 = _out_0_a_bits_T_23 \| _out_0_a_bits_T_20; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_25 = _out_0_a_bits_T_24 \| _out_0_a_bits_T_21; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_26 = _out_0_a_bits_T_25 \| _out_0_a_bits_T_22; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_26; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_27 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_28 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_29 = muxState_2 ? portsAOI_filtered_2_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_30 = muxState_3 ? portsAOI_filtered_3_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_31 = muxState_4 ? portsAOI_filtered_4_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_32 = _out_0_a_bits_T_27 \| _out_0_a_bits_T_28; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_33 = _out_0_a_bits_T_32 \| _out_0_a_bits_T_29; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_34 = _out_0_a_bits_T_33 \| _out_0_a_bits_T_30; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_35 = _out_0_a_bits_T_34 \| _out_0_a_bits_T_31; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_35; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_36 = muxState_0 ? portsAOI_filtered_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_37 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_38 = muxState_2 ? portsAOI_filtered_2_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_39 = muxState_3 ? portsAOI_filtered_3_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_40 = muxState_4 ? portsAOI_filtered_4_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_41 = _out_0_a_bits_T_36 \| _out_0_a_bits_T_37; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_42 = _out_0_a_bits_T_41 \| _out_0_a_bits_T_38; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_43 = _out_0_a_bits_T_42 \| _out_0_a_bits_T_39; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_44 = _out_0_a_bits_T_43 \| _out_0_a_bits_T_40; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_44; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_45 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_46 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_47 = muxState_2 ? portsAOI_filtered_2_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_48 = muxState_3 ? portsAOI_filtered_3_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_49 = muxState_4 ? portsAOI_filtered_4_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_50 = _out_0_a_bits_T_45 \| _out_0_a_bits_T_46; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_51 = _out_0_a_bits_T_50 \| _out_0_a_bits_T_47; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_52 = _out_0_a_bits_T_51 \| _out_0_a_bits_T_48; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_53 = _out_0_a_bits_T_52 \| _out_0_a_bits_T_49; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_53; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_54 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_55 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_56 = muxState_2 ? portsAOI_filtered_2_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_57 = muxState_3 ? portsAOI_filtered_3_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_58 = muxState_4 ? portsAOI_filtered_4_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_59 = _out_0_a_bits_T_54 \| _out_0_a_bits_T_55; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_60 = _out_0_a_bits_T_59 \| _out_0_a_bits_T_56; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_61 = _out_0_a_bits_T_60 \| _out_0_a_bits_T_57; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_62 = _out_0_a_bits_T_61 \| _out_0_a_bits_T_58; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_62; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_63 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_64 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_65 = muxState_2 ? portsAOI_filtered_2_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_66 = muxState_3 ? portsAOI_filtered_3_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_67 = muxState_4 ? portsAOI_filtered_4_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_68 = _out_0_a_bits_T_63 \| _out_0_a_bits_T_64; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_69 = _out_0_a_bits_T_68 \| _out_0_a_bits_T_65; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_70 = _out_0_a_bits_T_69 \| _out_0_a_bits_T_66; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_71 = _out_0_a_bits_T_70 \| _out_0_a_bits_T_67; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_71; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo_1 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_hi_1 = {portsAOI_filtered_4_1_valid, portsAOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_hi_1 = {readys_hi_hi_1, portsAOI_filtered_2_1_valid}; // @[Xbar.scala:352:24] wire [4:0] _readys_T_13 = {readys_hi_1, readys_lo_1}; // @[Arbiter.scala:68:51] wire [4:0] readys_valid_1 = _readys_T_13; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_14 = readys_valid_1 == _readys_T_13; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_16 = ~_readys_T_15; // @[Arbiter.scala:22:12] wire _readys_T_17 = ~_readys_T_14; // @[Arbiter.scala:22:{12,19}] reg [4:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [4:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30] wire [4:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}] wire [9:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [8:0] _readys_unready_T_9 = readys_filter_1[9:1]; // @[package.scala:262:48] wire [9:0] _readys_unready_T_10 = {readys_filter_1[9], readys_filter_1[8:0] \| _readys_unready_T_9}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_11 = _readys_unready_T_10[9:2]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_12 = {_readys_unready_T_10[9:8], _readys_unready_T_10[7:0] \| _readys_unready_T_11}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_13 = _readys_unready_T_12[9:4]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_14 = {_readys_unready_T_12[9:6], _readys_unready_T_12[5:0] \| _readys_unready_T_13}; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_15 = _readys_unready_T_14; // @[package.scala:262:43, :263:17] wire [8:0] _readys_unready_T_16 = _readys_unready_T_15[9:1]; // @[package.scala:263:17] wire [9:0] _readys_unready_T_17 = {readys_mask_1, 5'h0}; // @[Arbiter.scala:23:23, :25:66] wire [9:0] readys_unready_1 = {1'h0, _readys_unready_T_16} \| _readys_unready_T_17; // @[Arbiter.scala:25:{52,58,66}] wire [4:0] _readys_readys_T_3 = readys_unready_1[9:5]; // @[Arbiter.scala:25:58, :26:29] wire [4:0] _readys_readys_T_4 = readys_unready_1[4:0]; // @[Arbiter.scala:25:58, :26:48] wire [4:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}] wire [4:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}] wire [4:0] _readys_T_20 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_18 = \|readys_valid_1; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_19 = latch_1 & _readys_T_18; // @[Arbiter.scala:27:{18,27}, :62:24] wire [4:0] _readys_mask_T_11 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [5:0] _readys_mask_T_12 = {_readys_mask_T_11, 1'h0}; // @[package.scala:253:48] wire [4:0] _readys_mask_T_13 = _readys_mask_T_12[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_14 = _readys_mask_T_11 \| _readys_mask_T_13; // @[package.scala:253:{43,53}] wire [6:0] _readys_mask_T_15 = {_readys_mask_T_14, 2'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_16 = _readys_mask_T_15[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_17 = _readys_mask_T_14 \| _readys_mask_T_16; // @[package.scala:253:{43,53}] wire [8:0] _readys_mask_T_18 = {_readys_mask_T_17, 4'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_19 = _readys_mask_T_18[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_20 = _readys_mask_T_17 \| _readys_mask_T_19; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_21 = _readys_mask_T_20; // @[package.scala:253:43, :254:17] wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _readys_T_24 = _readys_T_20[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_3 = _readys_T_24; // @[Arbiter.scala:68:{27,76}] wire _readys_T_25 = _readys_T_20[4]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_4 = _readys_T_25; // @[Arbiter.scala:68:{27,76}] wire _winner_T_5 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_1_0 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire _winner_T_6 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_1_1 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_1_2 & portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_1_2 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire _winner_T_8 = readys_1_3 & portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_1_3 = _winner_T_8; // @[Arbiter.scala:71:{27,69}] wire _winner_T_9 = readys_1_4 & portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_1_4 = _winner_T_9; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_1 = prefixOR_1_1 \| winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_1 = prefixOR_2_1 \| winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4_1 = prefixOR_3_1 \| winner_1_3; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_4_1 \| winner_1_4; // @[Arbiter.scala:71:27, :76:48] wire _out_1_a_valid_T = portsAOI_filtered_1_valid \| portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2_1 = winner_1_2 ? beatsAI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3_1 = winner_1_3 ? beatsAI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_4_1 = winner_1_4 ? beatsAI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T_3 = maskedBeats_0_1 \| maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_4 = _initBeats_T_3 \| maskedBeats_2_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_5 = _initBeats_T_4 \| maskedBeats_3_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats_1 = _initBeats_T_5 \| maskedBeats_4_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {8'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_6 = _beatsLeft_T_5[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] reg state_1_2; // @[Arbiter.scala:88:26] reg state_1_3; // @[Arbiter.scala:88:26] reg state_1_4; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_3 = idle_1 ? winner_1_3 : state_1_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_4 = idle_1 ? winner_1_4 : state_1_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_3 = idle_1 ? readys_1_3 : state_1_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_4 = idle_1 ? readys_1_4 : state_1_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_2 = out_1_a_ready & allowed_1_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_1_ready = _filtered_1_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_3 = out_1_a_ready & allowed_1_3; // @[Xbar.scala:216:19] assign portsAOI_filtered_3_1_ready = _filtered_1_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_4 = out_1_a_ready & allowed_1_4; // @[Xbar.scala:216:19] assign portsAOI_filtered_4_1_ready = _filtered_1_ready_T_4; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_1 = _out_1_a_valid_T \| portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_2 = _out_1_a_valid_T_1 \| portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_3 = _out_1_a_valid_T_2 \| portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_4 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_5 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_6 = state_1_2 & portsAOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_7 = state_1_3 & portsAOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_8 = state_1_4 & portsAOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_9 = _out_1_a_valid_T_4 \| _out_1_a_valid_T_5; // @[Mux.scala:30:73] wire _out_1_a_valid_T_10 = _out_1_a_valid_T_9 \| _out_1_a_valid_T_6; // @[Mux.scala:30:73] wire _out_1_a_valid_T_11 = _out_1_a_valid_T_10 \| _out_1_a_valid_T_7; // @[Mux.scala:30:73] wire _out_1_a_valid_T_12 = _out_1_a_valid_T_11 \| _out_1_a_valid_T_8; // @[Mux.scala:30:73] wire _out_1_a_valid_WIRE = _out_1_a_valid_T_12; // @[Mux.scala:30:73] assign _out_1_a_valid_T_13 = idle_1 ? _out_1_a_valid_T_3 : _out_1_a_valid_WIRE; // @[Mux.scala:30:73] assign out_1_a_valid = _out_1_a_valid_T_13; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_2 = muxState_1_2 & portsAOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_3 = muxState_1_3 & portsAOI_filtered_3_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_4 = muxState_1_4 & portsAOI_filtered_4_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_5 = _out_1_a_bits_T \| _out_1_a_bits_T_1; // @[Mux.scala:30:73] wire _out_1_a_bits_T_6 = _out_1_a_bits_T_5 \| _out_1_a_bits_T_2; // @[Mux.scala:30:73] wire _out_1_a_bits_T_7 = _out_1_a_bits_T_6 \| _out_1_a_bits_T_3; // @[Mux.scala:30:73] wire _out_1_a_bits_T_8 = _out_1_a_bits_T_7 \| _out_1_a_bits_T_4; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_8; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_9 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_10 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_11 = muxState_1_2 ? portsAOI_filtered_2_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_12 = muxState_1_3 ? portsAOI_filtered_3_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_13 = muxState_1_4 ? portsAOI_filtered_4_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_9 \| _out_1_a_bits_T_10; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_15 = _out_1_a_bits_T_14 \| _out_1_a_bits_T_11; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_16 = _out_1_a_bits_T_15 \| _out_1_a_bits_T_12; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_17 = _out_1_a_bits_T_16 \| _out_1_a_bits_T_13; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_17; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_18 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_19 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_20 = muxState_1_2 ? portsAOI_filtered_2_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_21 = muxState_1_3 ? portsAOI_filtered_3_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_22 = muxState_1_4 ? portsAOI_filtered_4_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_18 \| _out_1_a_bits_T_19; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_24 = _out_1_a_bits_T_23 \| _out_1_a_bits_T_20; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_25 = _out_1_a_bits_T_24 \| _out_1_a_bits_T_21; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_26 = _out_1_a_bits_T_25 \| _out_1_a_bits_T_22; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_26; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_27 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_28 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_29 = muxState_1_2 ? portsAOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_30 = muxState_1_3 ? portsAOI_filtered_3_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_31 = muxState_1_4 ? portsAOI_filtered_4_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_32 = _out_1_a_bits_T_27 \| _out_1_a_bits_T_28; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_33 = _out_1_a_bits_T_32 \| _out_1_a_bits_T_29; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_34 = _out_1_a_bits_T_33 \| _out_1_a_bits_T_30; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_35 = _out_1_a_bits_T_34 \| _out_1_a_bits_T_31; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_35; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_36 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_37 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_38 = muxState_1_2 ? portsAOI_filtered_2_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_39 = muxState_1_3 ? portsAOI_filtered_3_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_40 = muxState_1_4 ? portsAOI_filtered_4_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_41 = _out_1_a_bits_T_36 \| _out_1_a_bits_T_37; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_42 = _out_1_a_bits_T_41 \| _out_1_a_bits_T_38; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_43 = _out_1_a_bits_T_42 \| _out_1_a_bits_T_39; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_44 = _out_1_a_bits_T_43 \| _out_1_a_bits_T_40; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_44; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_45 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_46 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_47 = muxState_1_2 ? portsAOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_48 = muxState_1_3 ? portsAOI_filtered_3_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_49 = muxState_1_4 ? portsAOI_filtered_4_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_50 = _out_1_a_bits_T_45 \| _out_1_a_bits_T_46; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_51 = _out_1_a_bits_T_50 \| _out_1_a_bits_T_47; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_52 = _out_1_a_bits_T_51 \| _out_1_a_bits_T_48; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_53 = _out_1_a_bits_T_52 \| _out_1_a_bits_T_49; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_53; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_54 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_55 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_56 = muxState_1_2 ? portsAOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_57 = muxState_1_3 ? portsAOI_filtered_3_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_58 = muxState_1_4 ? portsAOI_filtered_4_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_59 = _out_1_a_bits_T_54 \| _out_1_a_bits_T_55; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_60 = _out_1_a_bits_T_59 \| _out_1_a_bits_T_56; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_61 = _out_1_a_bits_T_60 \| _out_1_a_bits_T_57; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_62 = _out_1_a_bits_T_61 \| _out_1_a_bits_T_58; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_62; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_63 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_64 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_65 = muxState_1_2 ? portsAOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_66 = muxState_1_3 ? portsAOI_filtered_3_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_67 = muxState_1_4 ? portsAOI_filtered_4_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_68 = _out_1_a_bits_T_63 \| _out_1_a_bits_T_64; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_69 = _out_1_a_bits_T_68 \| _out_1_a_bits_T_65; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_70 = _out_1_a_bits_T_69 \| _out_1_a_bits_T_66; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_71 = _out_1_a_bits_T_70 \| _out_1_a_bits_T_67; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_71; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_2 = idle_2 & out_1_c_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo_2 = {portsCOI_filtered_2_1_valid, portsCOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_2 = {portsCOI_filtered_4_1_valid, portsCOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [3:0] _readys_T_26 = {readys_hi_2, readys_lo_2}; // @[Arbiter.scala:68:51] wire [3:0] readys_valid_2 = _readys_T_26; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_27 = readys_valid_2 == _readys_T_26; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_29 = ~_readys_T_28; // @[Arbiter.scala:22:12] wire _readys_T_30 = ~_readys_T_27; // @[Arbiter.scala:22:{12,19}] reg [3:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [3:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30] wire [3:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}] wire [7:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [6:0] _readys_unready_T_18 = readys_filter_2[7:1]; // @[package.scala:262:48] wire [7:0] _readys_unready_T_19 = {readys_filter_2[7], readys_filter_2[6:0] \| _readys_unready_T_18}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_20 = _readys_unready_T_19[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_21 = {_readys_unready_T_19[7:6], _readys_unready_T_19[5:0] \| _readys_unready_T_20}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_22 = _readys_unready_T_21; // @[package.scala:262:43, :263:17] wire [6:0] _readys_unready_T_23 = _readys_unready_T_22[7:1]; // @[package.scala:263:17] wire [7:0] _readys_unready_T_24 = {readys_mask_2, 4'h0}; // @[Arbiter.scala:23:23, :25:66] wire [7:0] readys_unready_2 = {1'h0, _readys_unready_T_23} \| _readys_unready_T_24; // @[Arbiter.scala:25:{52,58,66}] wire [3:0] _readys_readys_T_6 = readys_unready_2[7:4]; // @[Arbiter.scala:25:58, :26:29] wire [3:0] _readys_readys_T_7 = readys_unready_2[3:0]; // @[Arbiter.scala:25:58, :26:48] wire [3:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}] wire [3:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}] wire [3:0] _readys_T_33 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_31 = \|readys_valid_2; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_32 = latch_2 & _readys_T_31; // @[Arbiter.scala:27:{18,27}, :62:24] wire [3:0] _readys_mask_T_22 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [4:0] _readys_mask_T_23 = {_readys_mask_T_22, 1'h0}; // @[package.scala:253:48] wire [3:0] _readys_mask_T_24 = _readys_mask_T_23[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_25 = _readys_mask_T_22 \| _readys_mask_T_24; // @[package.scala:253:{43,53}] wire [5:0] _readys_mask_T_26 = {_readys_mask_T_25, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _readys_mask_T_27 = _readys_mask_T_26[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_28 = _readys_mask_T_25 \| _readys_mask_T_27; // @[package.scala:253:{43,53}] wire [3:0] _readys_mask_T_29 = _readys_mask_T_28; // @[package.scala:253:43, :254:17] wire _readys_T_34 = _readys_T_33[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_0 = _readys_T_34; // @[Arbiter.scala:68:{27,76}] wire _readys_T_35 = _readys_T_33[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_1 = _readys_T_35; // @[Arbiter.scala:68:{27,76}] wire _readys_T_36 = _readys_T_33[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_2 = _readys_T_36; // @[Arbiter.scala:68:{27,76}] wire _readys_T_37 = _readys_T_33[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_3 = _readys_T_37; // @[Arbiter.scala:68:{27,76}] wire _winner_T_10 = readys_2_0 & portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_2_0 = _winner_T_10; // @[Arbiter.scala:71:{27,69}] wire _winner_T_11 = readys_2_1 & portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_2_1 = _winner_T_11; // @[Arbiter.scala:71:{27,69}] wire _winner_T_12 = readys_2_2 & portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_2_2 = _winner_T_12; // @[Arbiter.scala:71:{27,69}] wire _winner_T_13 = readys_2_3 & portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_2_3 = _winner_T_13; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_2 = prefixOR_1_2 \| winner_2_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_2 = prefixOR_2_2 \| winner_2_2; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_2 = prefixOR_3_2 \| winner_2_3; // @[Arbiter.scala:71:27, :76:48] wire _out_1_c_valid_T = portsCOI_filtered_1_1_valid \| portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_2 = winner_2_0 ? beatsCI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1_2 = winner_2_1 ? beatsCI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2_2 = winner_2_2 ? beatsCI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3_2 = winner_2_3 ? beatsCI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T_6 = maskedBeats_0_2 \| maskedBeats_1_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_7 = _initBeats_T_6 \| maskedBeats_2_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats_2 = _initBeats_T_7 \| maskedBeats_3_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_8 = out_1_c_ready & out_1_c_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {8'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_10 = _beatsLeft_T_9[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] reg state_2_2; // @[Arbiter.scala:88:26] reg state_2_3; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_2 = idle_2 ? winner_2_2 : state_2_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_3 = idle_2 ? winner_2_3 : state_2_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_2 = idle_2 ? readys_2_2 : state_2_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_3 = idle_2 ? readys_2_3 : state_2_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_5 = out_1_c_ready & allowed_2_0; // @[Xbar.scala:216:19] assign portsCOI_filtered_1_1_ready = _filtered_1_ready_T_5; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_6 = out_1_c_ready & allowed_2_1; // @[Xbar.scala:216:19] assign portsCOI_filtered_2_1_ready = _filtered_1_ready_T_6; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_7 = out_1_c_ready & allowed_2_2; // @[Xbar.scala:216:19] assign portsCOI_filtered_3_1_ready = _filtered_1_ready_T_7; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_8 = out_1_c_ready & allowed_2_3; // @[Xbar.scala:216:19] assign portsCOI_filtered_4_1_ready = _filtered_1_ready_T_8; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_1 = _out_1_c_valid_T \| portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_2 = _out_1_c_valid_T_1 \| portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_3 = state_2_0 & portsCOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_4 = state_2_1 & portsCOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_5 = state_2_2 & portsCOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_6 = state_2_3 & portsCOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_7 = _out_1_c_valid_T_3 \| _out_1_c_valid_T_4; // @[Mux.scala:30:73] wire _out_1_c_valid_T_8 = _out_1_c_valid_T_7 \| _out_1_c_valid_T_5; // @[Mux.scala:30:73] wire _out_1_c_valid_T_9 = _out_1_c_valid_T_8 \| _out_1_c_valid_T_6; // @[Mux.scala:30:73] wire _out_1_c_valid_WIRE = _out_1_c_valid_T_9; // @[Mux.scala:30:73] assign _out_1_c_valid_T_10 = idle_2 ? _out_1_c_valid_T_2 : _out_1_c_valid_WIRE; // @[Mux.scala:30:73] assign out_1_c_valid = _out_1_c_valid_T_10; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_c_bits_opcode = _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_c_bits_param = _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_c_bits_size = _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_c_bits_source = _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] assign out_1_c_bits_address = _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_c_bits_data = _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_c_bits_corrupt = _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T = muxState_2_0 & portsCOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_1 = muxState_2_1 & portsCOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_2 = muxState_2_2 & portsCOI_filtered_3_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_3 = muxState_2_3 & portsCOI_filtered_4_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_4 = _out_1_c_bits_T \| _out_1_c_bits_T_1; // @[Mux.scala:30:73] wire _out_1_c_bits_T_5 = _out_1_c_bits_T_4 \| _out_1_c_bits_T_2; // @[Mux.scala:30:73] wire _out_1_c_bits_T_6 = _out_1_c_bits_T_5 \| _out_1_c_bits_T_3; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_1 = _out_1_c_bits_T_6; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_corrupt = _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_7 = muxState_2_0 ? portsCOI_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_8 = muxState_2_1 ? portsCOI_filtered_2_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_9 = muxState_2_2 ? portsCOI_filtered_3_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_10 = muxState_2_3 ? portsCOI_filtered_4_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_11 = _out_1_c_bits_T_7 \| _out_1_c_bits_T_8; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_12 = _out_1_c_bits_T_11 \| _out_1_c_bits_T_9; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_13 = _out_1_c_bits_T_12 \| _out_1_c_bits_T_10; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_2 = _out_1_c_bits_T_13; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_data = _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_14 = muxState_2_0 ? portsCOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_15 = muxState_2_1 ? portsCOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_16 = muxState_2_2 ? portsCOI_filtered_3_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_17 = muxState_2_3 ? portsCOI_filtered_4_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_18 = _out_1_c_bits_T_14 \| _out_1_c_bits_T_15; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_19 = _out_1_c_bits_T_18 \| _out_1_c_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_20 = _out_1_c_bits_T_19 \| _out_1_c_bits_T_17; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_5 = _out_1_c_bits_T_20; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_address = _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_21 = muxState_2_0 ? portsCOI_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_22 = muxState_2_1 ? portsCOI_filtered_2_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_23 = muxState_2_2 ? portsCOI_filtered_3_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_24 = muxState_2_3 ? portsCOI_filtered_4_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_25 = _out_1_c_bits_T_21 \| _out_1_c_bits_T_22; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_26 = _out_1_c_bits_T_25 \| _out_1_c_bits_T_23; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_27 = _out_1_c_bits_T_26 \| _out_1_c_bits_T_24; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_6 = _out_1_c_bits_T_27; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_source = _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_28 = muxState_2_0 ? portsCOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_29 = muxState_2_1 ? portsCOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_30 = muxState_2_2 ? portsCOI_filtered_3_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_31 = muxState_2_3 ? portsCOI_filtered_4_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_32 = _out_1_c_bits_T_28 \| _out_1_c_bits_T_29; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_33 = _out_1_c_bits_T_32 \| _out_1_c_bits_T_30; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_34 = _out_1_c_bits_T_33 \| _out_1_c_bits_T_31; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_7 = _out_1_c_bits_T_34; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_size = _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_35 = muxState_2_0 ? portsCOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_36 = muxState_2_1 ? portsCOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_37 = muxState_2_2 ? portsCOI_filtered_3_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_38 = muxState_2_3 ? portsCOI_filtered_4_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_39 = _out_1_c_bits_T_35 \| _out_1_c_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_40 = _out_1_c_bits_T_39 \| _out_1_c_bits_T_37; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_41 = _out_1_c_bits_T_40 \| _out_1_c_bits_T_38; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_8 = _out_1_c_bits_T_41; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_param = _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_42 = muxState_2_0 ? portsCOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_43 = muxState_2_1 ? portsCOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_44 = muxState_2_2 ? portsCOI_filtered_3_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_45 = muxState_2_3 ? portsCOI_filtered_4_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_46 = _out_1_c_bits_T_42 \| _out_1_c_bits_T_43; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_47 = _out_1_c_bits_T_46 \| _out_1_c_bits_T_44; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_48 = _out_1_c_bits_T_47 \| _out_1_c_bits_T_45; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_9 = _out_1_c_bits_T_48; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_opcode = _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] reg beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = ~beatsLeft_3; // @[Arbiter.scala:60:30, :61:28] wire latch_3 = idle_3; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_lo_3 = {portsEOI_filtered_2_1_valid, portsEOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_3 = {portsEOI_filtered_4_1_valid, portsEOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [3:0] _readys_T_38 = {readys_hi_3, readys_lo_3}; // @[Arbiter.scala:68:51] wire [3:0] readys_valid_3 = _readys_T_38; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_39 = readys_valid_3 == _readys_T_38; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_41 = ~_readys_T_40; // @[Arbiter.scala:22:12] wire _readys_T_42 = ~_readys_T_39; // @[Arbiter.scala:22:{12,19}] reg [3:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [3:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30] wire [3:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}] wire [7:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [6:0] _readys_unready_T_25 = readys_filter_3[7:1]; // @[package.scala:262:48] wire [7:0] _readys_unready_T_26 = {readys_filter_3[7], readys_filter_3[6:0] \| _readys_unready_T_25}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_27 = _readys_unready_T_26[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_28 = {_readys_unready_T_26[7:6], _readys_unready_T_26[5:0] \| _readys_unready_T_27}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_29 = _readys_unready_T_28; // @[package.scala:262:43, :263:17] wire [6:0] _readys_unready_T_30 = _readys_unready_T_29[7:1]; // @[package.scala:263:17] wire [7:0] _readys_unready_T_31 = {readys_mask_3, 4'h0}; // @[Arbiter.scala:23:23, :25:66] wire [7:0] readys_unready_3 = {1'h0, _readys_unready_T_30} \| _readys_unready_T_31; // @[Arbiter.scala:25:{52,58,66}] wire [3:0] _readys_readys_T_9 = readys_unready_3[7:4]; // @[Arbiter.scala:25:58, :26:29] wire [3:0] _readys_readys_T_10 = readys_unready_3[3:0]; // @[Arbiter.scala:25:58, :26:48] wire [3:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}] wire [3:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}] wire [3:0] _readys_T_45 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_43 = \|readys_valid_3; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_44 = latch_3 & _readys_T_43; // @[Arbiter.scala:27:{18,27}, :62:24] wire [3:0] _readys_mask_T_30 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [4:0] _readys_mask_T_31 = {_readys_mask_T_30, 1'h0}; // @[package.scala:253:48] wire [3:0] _readys_mask_T_32 = _readys_mask_T_31[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_33 = _readys_mask_T_30 \| _readys_mask_T_32; // @[package.scala:253:{43,53}] wire [5:0] _readys_mask_T_34 = {_readys_mask_T_33, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _readys_mask_T_35 = _readys_mask_T_34[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_36 = _readys_mask_T_33 \| _readys_mask_T_35; // @[package.scala:253:{43,53}] wire [3:0] _readys_mask_T_37 = _readys_mask_T_36; // @[package.scala:253:43, :254:17] wire _readys_T_46 = _readys_T_45[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_0 = _readys_T_46; // @[Arbiter.scala:68:{27,76}] wire _readys_T_47 = _readys_T_45[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_1 = _readys_T_47; // @[Arbiter.scala:68:{27,76}] wire _readys_T_48 = _readys_T_45[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_2 = _readys_T_48; // @[Arbiter.scala:68:{27,76}] wire _readys_T_49 = _readys_T_45[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_3 = _readys_T_49; // @[Arbiter.scala:68:{27,76}] wire _winner_T_14 = readys_3_0 & portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_3_0 = _winner_T_14; // @[Arbiter.scala:71:{27,69}] wire _winner_T_15 = readys_3_1 & portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_3_1 = _winner_T_15; // @[Arbiter.scala:71:{27,69}] wire _winner_T_16 = readys_3_2 & portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_3_2 = _winner_T_16; // @[Arbiter.scala:71:{27,69}] wire _winner_T_17 = readys_3_3 & portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_3_3 = _winner_T_17; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_3 = prefixOR_1_3 \| winner_3_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_3 = prefixOR_2_3 \| winner_3_2; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_3 = prefixOR_3_3 \| winner_3_3; // @[Arbiter.scala:71:27, :76:48] wire _out_1_e_valid_T = portsEOI_filtered_1_1_valid \| portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [1:0] _beatsLeft_T_13 = {1'h0, beatsLeft_3} - {1'h0, _beatsLeft_T_12}; // @[Decoupled.scala:51:35] wire _beatsLeft_T_14 = _beatsLeft_T_13[0]; // @[Arbiter.scala:85:52] wire _beatsLeft_T_15 = ~latch_3 & _beatsLeft_T_14; // @[Arbiter.scala:62:24, :85:{23,52}] reg state_3_0; // @[Arbiter.scala:88:26] reg state_3_1; // @[Arbiter.scala:88:26] reg state_3_2; // @[Arbiter.scala:88:26] reg state_3_3; // @[Arbiter.scala:88:26] wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_2 = idle_3 ? winner_3_2 : state_3_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_3 = idle_3 ? winner_3_3 : state_3_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_3_0 = idle_3 ? readys_3_0 : state_3_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_1 = idle_3 ? readys_3_1 : state_3_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_2 = idle_3 ? readys_3_2 : state_3_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_3 = idle_3 ? readys_3_3 : state_3_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_9 = allowed_3_0; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_10 = allowed_3_1; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_11 = allowed_3_2; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_12 = allowed_3_3; // @[Arbiter.scala:92:24, :94:31] assign portsEOI_filtered_1_1_ready = _filtered_1_ready_T_9; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_ready = _filtered_1_ready_T_10; // @[Xbar.scala:352:24] assign portsEOI_filtered_3_1_ready = _filtered_1_ready_T_11; // @[Xbar.scala:352:24] assign portsEOI_filtered_4_1_ready = _filtered_1_ready_T_12; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_1 = _out_1_e_valid_T \| portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_2 = _out_1_e_valid_T_1 \| portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_3 = state_3_0 & portsEOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_4 = state_3_1 & portsEOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_5 = state_3_2 & portsEOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_6 = state_3_3 & portsEOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_7 = _out_1_e_valid_T_3 \| _out_1_e_valid_T_4; // @[Mux.scala:30:73] wire _out_1_e_valid_T_8 = _out_1_e_valid_T_7 \| _out_1_e_valid_T_5; // @[Mux.scala:30:73] wire _out_1_e_valid_T_9 = _out_1_e_valid_T_8 \| _out_1_e_valid_T_6; // @[Mux.scala:30:73] wire _out_1_e_valid_WIRE = _out_1_e_valid_T_9; // @[Mux.scala:30:73] assign _out_1_e_valid_T_10 = idle_3 ? _out_1_e_valid_T_2 : _out_1_e_valid_WIRE; // @[Mux.scala:30:73] assign out_1_e_valid = _out_1_e_valid_T_10; // @[Xbar.scala:216:19] wire [3:0] _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_e_bits_sink = _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T = muxState_3_0 ? portsEOI_filtered_1_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_1 = muxState_3_1 ? portsEOI_filtered_2_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_2 = muxState_3_2 ? portsEOI_filtered_3_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_3 = muxState_3_3 ? portsEOI_filtered_4_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_4 = _out_1_e_bits_T \| _out_1_e_bits_T_1; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_5 = _out_1_e_bits_T_4 \| _out_1_e_bits_T_2; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_6 = _out_1_e_bits_T_5 \| _out_1_e_bits_T_3; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_1 = _out_1_e_bits_T_6; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_sink = _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] reg [7:0] beatsLeft_4; // @[Arbiter.scala:60:30] wire idle_4 = beatsLeft_4 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_4 = idle_4 & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_50 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_4 = _readys_T_50; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_51 = readys_valid_4 == _readys_T_50; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_53 = ~_readys_T_52; // @[Arbiter.scala:22:12] wire _readys_T_54 = ~_readys_T_51; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_8 = ~readys_mask_4; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_9 = readys_valid_4 & _readys_filter_T_8; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_4 = {_readys_filter_T_9, readys_valid_4}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_32 = readys_filter_4[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_33 = {readys_filter_4[3], readys_filter_4[2:0] \| _readys_unready_T_32}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_34 = _readys_unready_T_33; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_35 = _readys_unready_T_34[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_36 = {readys_mask_4, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_4 = {1'h0, _readys_unready_T_35} \| _readys_unready_T_36; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_12 = readys_unready_4[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_13 = readys_unready_4[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_14 = _readys_readys_T_12 & _readys_readys_T_13; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_4 = ~_readys_readys_T_14; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_57 = readys_readys_4; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_55 = \|readys_valid_4; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_56 = latch_4 & _readys_T_55; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_38 = readys_readys_4 & readys_valid_4; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_39 = {_readys_mask_T_38, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_40 = _readys_mask_T_39[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_41 = _readys_mask_T_38 \| _readys_mask_T_40; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_42 = _readys_mask_T_41; // @[package.scala:253:43, :254:17] wire _readys_T_58 = _readys_T_57[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_0 = _readys_T_58; // @[Arbiter.scala:68:{27,76}] wire _readys_T_59 = _readys_T_57[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_1 = _readys_T_59; // @[Arbiter.scala:68:{27,76}] wire _winner_T_18 = readys_4_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_4_0 = _winner_T_18; // @[Arbiter.scala:71:{27,69}] wire _winner_T_19 = readys_4_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_4_1 = _winner_T_19; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_4 = winner_4_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_4 = prefixOR_1_4 \| winner_4_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_4 = winner_4_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_4 = winner_4_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_4 = {maskedBeats_0_4[7:2], maskedBeats_0_4[1:0] \| maskedBeats_1_4}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_16 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_17 = {1'h0, beatsLeft_4} - {8'h0, _beatsLeft_T_16}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_18 = _beatsLeft_T_17[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_19 = latch_4 ? initBeats_4 : _beatsLeft_T_18; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_4_0; // @[Arbiter.scala:88:26] reg state_4_1; // @[Arbiter.scala:88:26] wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_4_0 = idle_4 ? readys_4_0 : state_4_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4_1 = idle_4 ? readys_4_1 : state_4_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T_5 = in_0_d_ready & allowed_4_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_0_ready = _filtered_0_ready_T_5; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_6 = in_0_d_ready & allowed_4_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_6; // @[Xbar.scala:352:24] wire _in_0_d_valid_T_1 = state_4_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_2 = state_4_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 \| _in_0_d_valid_T_2; // @[Mux.scala:30:73] wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73] assign _in_0_d_valid_T_4 = idle_4 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73] assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T = muxState_4_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = muxState_4_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = _in_0_d_bits_T \| _in_0_d_bits_T_1; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_3 = muxState_4_0 ? portsDIO_filtered_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_4 = muxState_4_1 ? portsDIO_filtered_1_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 \| _in_0_d_bits_T_4; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = muxState_4_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = muxState_4_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 \| _in_0_d_bits_T_7; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_9 = muxState_4_0 ? portsDIO_filtered_0_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_10 = muxState_4_1 ? portsDIO_filtered_1_0_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 \| _in_0_d_bits_T_10; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_12 = muxState_4_0 ? portsDIO_filtered_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_13 = muxState_4_1 ? portsDIO_filtered_1_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 \| _in_0_d_bits_T_13; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_15 = muxState_4_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_16 = muxState_4_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 \| _in_0_d_bits_T_16; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = muxState_4_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = muxState_4_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 \| _in_0_d_bits_T_19; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_21 = muxState_4_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = muxState_4_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 \| _in_0_d_bits_T_22; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_5; // @[Arbiter.scala:60:30] wire idle_5 = beatsLeft_5 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_5 = idle_5 & in_1_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_60 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_5 = _readys_T_60; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_61 = readys_valid_5 == _readys_T_60; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_63 = ~_readys_T_62; // @[Arbiter.scala:22:12] wire _readys_T_64 = ~_readys_T_61; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_5; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_10 = ~readys_mask_5; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_11 = readys_valid_5 & _readys_filter_T_10; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_5 = {_readys_filter_T_11, readys_valid_5}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_37 = readys_filter_5[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_38 = {readys_filter_5[3], readys_filter_5[2:0] \| _readys_unready_T_37}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_39 = _readys_unready_T_38; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_40 = _readys_unready_T_39[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_41 = {readys_mask_5, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_5 = {1'h0, _readys_unready_T_40} \| _readys_unready_T_41; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_15 = readys_unready_5[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_16 = readys_unready_5[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_17 = _readys_readys_T_15 & _readys_readys_T_16; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_5 = ~_readys_readys_T_17; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_67 = readys_readys_5; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_65 = \|readys_valid_5; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_66 = latch_5 & _readys_T_65; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_43 = readys_readys_5 & readys_valid_5; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_44 = {_readys_mask_T_43, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_45 = _readys_mask_T_44[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_46 = _readys_mask_T_43 \| _readys_mask_T_45; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_47 = _readys_mask_T_46; // @[package.scala:253:43, :254:17] wire _readys_T_68 = _readys_T_67[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_0 = _readys_T_68; // @[Arbiter.scala:68:{27,76}] wire _readys_T_69 = _readys_T_67[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_1 = _readys_T_69; // @[Arbiter.scala:68:{27,76}] wire _winner_T_20 = readys_5_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_5_0 = _winner_T_20; // @[Arbiter.scala:71:{27,69}] wire _winner_T_21 = readys_5_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_5_1 = _winner_T_21; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_5 = winner_5_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_5 = prefixOR_1_5 \| winner_5_1; // @[Arbiter.scala:71:27, :76:48] wire _in_1_d_valid_T = portsDIO_filtered_1_valid \| portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_5 = winner_5_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_5 = winner_5_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_5 = {maskedBeats_0_5[7:2], maskedBeats_0_5[1:0] \| maskedBeats_1_5}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_20 = in_1_d_ready & in_1_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_21 = {1'h0, beatsLeft_5} - {8'h0, _beatsLeft_T_20}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_22 = _beatsLeft_T_21[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_23 = latch_5 ? initBeats_5 : _beatsLeft_T_22; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_5_0; // @[Arbiter.scala:88:26] reg state_5_1; // @[Arbiter.scala:88:26] wire muxState_5_0 = idle_5 ? winner_5_0 : state_5_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_5_0 = idle_5 ? readys_5_0 : state_5_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_5_1 = idle_5 ? readys_5_1 : state_5_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_13 = in_1_d_ready & allowed_5_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_ready = _filtered_1_ready_T_13; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_14 = in_1_d_ready & allowed_5_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_1_ready = _filtered_1_ready_T_14; // @[Xbar.scala:352:24] wire _in_1_d_valid_T_1 = state_5_0 & portsDIO_filtered_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_2 = state_5_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_3 = _in_1_d_valid_T_1 \| _in_1_d_valid_T_2; // @[Mux.scala:30:73] wire _in_1_d_valid_WIRE = _in_1_d_valid_T_3; // @[Mux.scala:30:73] assign _in_1_d_valid_T_4 = idle_5 ? _in_1_d_valid_T : _in_1_d_valid_WIRE; // @[Mux.scala:30:73] assign in_1_d_valid = _in_1_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_1_d_bits_opcode = _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_1_d_bits_param = _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_1_d_bits_size = _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_1_d_bits_source = _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_1_d_bits_sink = _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_1_d_bits_denied = _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_1_d_bits_data = _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_1_d_bits_corrupt = _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T = muxState_5_0 & portsDIO_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_1 = muxState_5_1 & portsDIO_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_2 = _in_1_d_bits_T \| _in_1_d_bits_T_1; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_1 = _in_1_d_bits_T_2; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_corrupt = _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_3 = muxState_5_0 ? portsDIO_filtered_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_4 = muxState_5_1 ? portsDIO_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_5 = _in_1_d_bits_T_3 \| _in_1_d_bits_T_4; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_2 = _in_1_d_bits_T_5; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_data = _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_1_d_bits_T_6 = muxState_5_0 & portsDIO_filtered_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_7 = muxState_5_1 & portsDIO_filtered_1_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_8 = _in_1_d_bits_T_6 \| _in_1_d_bits_T_7; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_5 = _in_1_d_bits_T_8; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_denied = _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_9 = muxState_5_0 ? portsDIO_filtered_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_10 = muxState_5_1 ? portsDIO_filtered_1_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_11 = _in_1_d_bits_T_9 \| _in_1_d_bits_T_10; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_6 = _in_1_d_bits_T_11; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_sink = _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_12 = muxState_5_0 ? portsDIO_filtered_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_13 = muxState_5_1 ? portsDIO_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_14 = _in_1_d_bits_T_12 \| _in_1_d_bits_T_13; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_7 = _in_1_d_bits_T_14; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_source = _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_15 = muxState_5_0 ? portsDIO_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_16 = muxState_5_1 ? portsDIO_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_17 = _in_1_d_bits_T_15 \| _in_1_d_bits_T_16; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_8 = _in_1_d_bits_T_17; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_size = _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_18 = muxState_5_0 ? portsDIO_filtered_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_19 = muxState_5_1 ? portsDIO_filtered_1_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_20 = _in_1_d_bits_T_18 \| _in_1_d_bits_T_19; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_9 = _in_1_d_bits_T_20; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_param = _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_21 = muxState_5_0 ? portsDIO_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_22 = muxState_5_1 ? portsDIO_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_23 = _in_1_d_bits_T_21 \| _in_1_d_bits_T_22; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_10 = _in_1_d_bits_T_23; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_opcode = _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_6; // @[Arbiter.scala:60:30] wire idle_6 = beatsLeft_6 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_6 = idle_6 & in_2_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_70 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_6 = _readys_T_70; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_71 = readys_valid_6 == _readys_T_70; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_73 = ~_readys_T_72; // @[Arbiter.scala:22:12] wire _readys_T_74 = ~_readys_T_71; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_6; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_12 = ~readys_mask_6; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_13 = readys_valid_6 & _readys_filter_T_12; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_6 = {_readys_filter_T_13, readys_valid_6}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_42 = readys_filter_6[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_43 = {readys_filter_6[3], readys_filter_6[2:0] \| _readys_unready_T_42}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_44 = _readys_unready_T_43; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_45 = _readys_unready_T_44[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_46 = {readys_mask_6, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_6 = {1'h0, _readys_unready_T_45} \| _readys_unready_T_46; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_18 = readys_unready_6[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_19 = readys_unready_6[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_20 = _readys_readys_T_18 & _readys_readys_T_19; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_6 = ~_readys_readys_T_20; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_77 = readys_readys_6; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_75 = \|readys_valid_6; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_76 = latch_6 & _readys_T_75; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_48 = readys_readys_6 & readys_valid_6; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_49 = {_readys_mask_T_48, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_50 = _readys_mask_T_49[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_51 = _readys_mask_T_48 \| _readys_mask_T_50; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_52 = _readys_mask_T_51; // @[package.scala:253:43, :254:17] wire _readys_T_78 = _readys_T_77[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_0 = _readys_T_78; // @[Arbiter.scala:68:{27,76}] wire _readys_T_79 = _readys_T_77[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_1 = _readys_T_79; // @[Arbiter.scala:68:{27,76}] wire _winner_T_22 = readys_6_0 & portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] wire winner_6_0 = _winner_T_22; // @[Arbiter.scala:71:{27,69}] wire _winner_T_23 = readys_6_1 & portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire winner_6_1 = _winner_T_23; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_6 = winner_6_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_6 = prefixOR_1_6 \| winner_6_1; // @[Arbiter.scala:71:27, :76:48] wire _in_2_d_valid_T = portsDIO_filtered_2_valid \| portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_6 = winner_6_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_6 = winner_6_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_6 = {maskedBeats_0_6[7:2], maskedBeats_0_6[1:0] \| maskedBeats_1_6}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_24 = in_2_d_ready & in_2_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_25 = {1'h0, beatsLeft_6} - {8'h0, _beatsLeft_T_24}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_26 = _beatsLeft_T_25[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_27 = latch_6 ? initBeats_6 : _beatsLeft_T_26; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_6_0; // @[Arbiter.scala:88:26] reg state_6_1; // @[Arbiter.scala:88:26] wire muxState_6_0 = idle_6 ? winner_6_0 : state_6_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_6_1 = idle_6 ? winner_6_1 : state_6_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_6_0 = idle_6 ? readys_6_0 : state_6_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_6_1 = idle_6 ? readys_6_1 : state_6_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_2_ready_T = in_2_d_ready & allowed_6_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_2_ready = _filtered_2_ready_T; // @[Xbar.scala:352:24] assign _filtered_2_ready_T_1 = in_2_d_ready & allowed_6_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_2_ready = _filtered_2_ready_T_1; // @[Xbar.scala:352:24] wire _in_2_d_valid_T_1 = state_6_0 & portsDIO_filtered_2_valid; // @[Mux.scala:30:73] wire _in_2_d_valid_T_2 = state_6_1 & portsDIO_filtered_1_2_valid; // @[Mux.scala:30:73] wire _in_2_d_valid_T_3 = _in_2_d_valid_T_1 \| _in_2_d_valid_T_2; // @[Mux.scala:30:73] wire _in_2_d_valid_WIRE = _in_2_d_valid_T_3; // @[Mux.scala:30:73] assign _in_2_d_valid_T_4 = idle_6 ? _in_2_d_valid_T : _in_2_d_valid_WIRE; // @[Mux.scala:30:73] assign in_2_d_valid = _in_2_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_2_d_bits_opcode = _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_2_d_bits_param = _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_2_d_bits_size = _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_2_d_bits_source = _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_2_d_bits_sink = _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_2_d_bits_denied = _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_2_d_bits_data = _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_2_d_bits_corrupt = _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T = muxState_6_0 & portsDIO_filtered_2_bits_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T_1 = muxState_6_1 & portsDIO_filtered_1_2_bits_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T_2 = _in_2_d_bits_T \| _in_2_d_bits_T_1; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_1 = _in_2_d_bits_T_2; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_corrupt = _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_3 = muxState_6_0 ? portsDIO_filtered_2_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_4 = muxState_6_1 ? portsDIO_filtered_1_2_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_5 = _in_2_d_bits_T_3 \| _in_2_d_bits_T_4; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_2 = _in_2_d_bits_T_5; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_data = _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_2_d_bits_T_6 = muxState_6_0 & portsDIO_filtered_2_bits_denied; // @[Mux.scala:30:73] wire _in_2_d_bits_T_7 = muxState_6_1 & portsDIO_filtered_1_2_bits_denied; // @[Mux.scala:30:73] wire _in_2_d_bits_T_8 = _in_2_d_bits_T_6 \| _in_2_d_bits_T_7; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_5 = _in_2_d_bits_T_8; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_denied = _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_9 = muxState_6_0 ? portsDIO_filtered_2_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_10 = muxState_6_1 ? portsDIO_filtered_1_2_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_11 = _in_2_d_bits_T_9 \| _in_2_d_bits_T_10; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_6 = _in_2_d_bits_T_11; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_sink = _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_12 = muxState_6_0 ? portsDIO_filtered_2_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_13 = muxState_6_1 ? portsDIO_filtered_1_2_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_14 = _in_2_d_bits_T_12 \| _in_2_d_bits_T_13; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_7 = _in_2_d_bits_T_14; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_source = _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_15 = muxState_6_0 ? portsDIO_filtered_2_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_16 = muxState_6_1 ? portsDIO_filtered_1_2_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_17 = _in_2_d_bits_T_15 \| _in_2_d_bits_T_16; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_8 = _in_2_d_bits_T_17; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_size = _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_18 = muxState_6_0 ? portsDIO_filtered_2_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_19 = muxState_6_1 ? portsDIO_filtered_1_2_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_20 = _in_2_d_bits_T_18 \| _in_2_d_bits_T_19; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_9 = _in_2_d_bits_T_20; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_param = _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_21 = muxState_6_0 ? portsDIO_filtered_2_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_22 = muxState_6_1 ? portsDIO_filtered_1_2_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_23 = _in_2_d_bits_T_21 \| _in_2_d_bits_T_22; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_10 = _in_2_d_bits_T_23; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_opcode = _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_7; // @[Arbiter.scala:60:30] wire idle_7 = beatsLeft_7 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_7 = idle_7 & in_3_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_80 = {portsDIO_filtered_1_3_valid, portsDIO_filtered_3_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_7 = _readys_T_80; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_81 = readys_valid_7 == _readys_T_80; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_83 = ~_readys_T_82; // @[Arbiter.scala:22:12] wire _readys_T_84 = ~_readys_T_81; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_7; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_14 = ~readys_mask_7; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_15 = readys_valid_7 & _readys_filter_T_14; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_7 = {_readys_filter_T_15, readys_valid_7}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_47 = readys_filter_7[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_48 = {readys_filter_7[3], readys_filter_7[2:0] \| _readys_unready_T_47}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_49 = _readys_unready_T_48; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_50 = _readys_unready_T_49[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_51 = {readys_mask_7, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_7 = {1'h0, _readys_unready_T_50} \| _readys_unready_T_51; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_21 = readys_unready_7[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_22 = readys_unready_7[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_23 = _readys_readys_T_21 & _readys_readys_T_22; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_7 = ~_readys_readys_T_23; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_87 = readys_readys_7; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_85 = \|readys_valid_7; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_86 = latch_7 & _readys_T_85; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_53 = readys_readys_7 & readys_valid_7; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_54 = {_readys_mask_T_53, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_55 = _readys_mask_T_54[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_56 = _readys_mask_T_53 \| _readys_mask_T_55; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_57 = _readys_mask_T_56; // @[package.scala:253:43, :254:17] wire _readys_T_88 = _readys_T_87[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_7_0 = _readys_T_88; // @[Arbiter.scala:68:{27,76}] wire _readys_T_89 = _readys_T_87[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_7_1 = _readys_T_89; // @[Arbiter.scala:68:{27,76}] wire _winner_T_24 = readys_7_0 & portsDIO_filtered_3_valid; // @[Xbar.scala:352:24] wire winner_7_0 = _winner_T_24; // @[Arbiter.scala:71:{27,69}] wire _winner_T_25 = readys_7_1 & portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire winner_7_1 = _winner_T_25; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_7 = winner_7_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_7 = prefixOR_1_7 \| winner_7_1; // @[Arbiter.scala:71:27, :76:48] wire _in_3_d_valid_T = portsDIO_filtered_3_valid \| portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_7 = winner_7_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_7 = winner_7_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_7 = {maskedBeats_0_7[7:2], maskedBeats_0_7[1:0] \| maskedBeats_1_7}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_28 = in_3_d_ready & in_3_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_29 = {1'h0, beatsLeft_7} - {8'h0, _beatsLeft_T_28}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_30 = _beatsLeft_T_29[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_31 = latch_7 ? initBeats_7 : _beatsLeft_T_30; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_7_0; // @[Arbiter.scala:88:26] reg state_7_1; // @[Arbiter.scala:88:26] wire muxState_7_0 = idle_7 ? winner_7_0 : state_7_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_7_1 = idle_7 ? winner_7_1 : state_7_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_7_0 = idle_7 ? readys_7_0 : state_7_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_7_1 = idle_7 ? readys_7_1 : state_7_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_3_ready_T = in_3_d_ready & allowed_7_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_3_ready = _filtered_3_ready_T; // @[Xbar.scala:352:24] assign _filtered_3_ready_T_1 = in_3_d_ready & allowed_7_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_3_ready = _filtered_3_ready_T_1; // @[Xbar.scala:352:24] wire _in_3_d_valid_T_1 = state_7_0 & portsDIO_filtered_3_valid; // @[Mux.scala:30:73] wire _in_3_d_valid_T_2 = state_7_1 & portsDIO_filtered_1_3_valid; // @[Mux.scala:30:73] wire _in_3_d_valid_T_3 = _in_3_d_valid_T_1 \| _in_3_d_valid_T_2; // @[Mux.scala:30:73] wire _in_3_d_valid_WIRE = _in_3_d_valid_T_3; // @[Mux.scala:30:73] assign _in_3_d_valid_T_4 = idle_7 ? _in_3_d_valid_T : _in_3_d_valid_WIRE; // @[Mux.scala:30:73] assign in_3_d_valid = _in_3_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_3_d_bits_opcode = _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_3_d_bits_param = _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_3_d_bits_size = _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_3_d_bits_source = _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_3_d_bits_sink = _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_3_d_bits_denied = _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_3_d_bits_data = _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_3_d_bits_corrupt = _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T = muxState_7_0 & portsDIO_filtered_3_bits_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T_1 = muxState_7_1 & portsDIO_filtered_1_3_bits_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T_2 = _in_3_d_bits_T \| _in_3_d_bits_T_1; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_1 = _in_3_d_bits_T_2; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_corrupt = _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_3 = muxState_7_0 ? portsDIO_filtered_3_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_4 = muxState_7_1 ? portsDIO_filtered_1_3_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_5 = _in_3_d_bits_T_3 \| _in_3_d_bits_T_4; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_2 = _in_3_d_bits_T_5; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_data = _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_3_d_bits_T_6 = muxState_7_0 & portsDIO_filtered_3_bits_denied; // @[Mux.scala:30:73] wire _in_3_d_bits_T_7 = muxState_7_1 & portsDIO_filtered_1_3_bits_denied; // @[Mux.scala:30:73] wire _in_3_d_bits_T_8 = _in_3_d_bits_T_6 \| _in_3_d_bits_T_7; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_5 = _in_3_d_bits_T_8; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_denied = _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_9 = muxState_7_0 ? portsDIO_filtered_3_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_10 = muxState_7_1 ? portsDIO_filtered_1_3_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_11 = _in_3_d_bits_T_9 \| _in_3_d_bits_T_10; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_6 = _in_3_d_bits_T_11; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_sink = _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_12 = muxState_7_0 ? portsDIO_filtered_3_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_13 = muxState_7_1 ? portsDIO_filtered_1_3_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_14 = _in_3_d_bits_T_12 \| _in_3_d_bits_T_13; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_7 = _in_3_d_bits_T_14; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_source = _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_15 = muxState_7_0 ? portsDIO_filtered_3_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_16 = muxState_7_1 ? portsDIO_filtered_1_3_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_17 = _in_3_d_bits_T_15 \| _in_3_d_bits_T_16; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_8 = _in_3_d_bits_T_17; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_size = _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_18 = muxState_7_0 ? portsDIO_filtered_3_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_19 = muxState_7_1 ? portsDIO_filtered_1_3_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_20 = _in_3_d_bits_T_18 \| _in_3_d_bits_T_19; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_9 = _in_3_d_bits_T_20; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_param = _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_21 = muxState_7_0 ? portsDIO_filtered_3_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_22 = muxState_7_1 ? portsDIO_filtered_1_3_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_23 = _in_3_d_bits_T_21 \| _in_3_d_bits_T_22; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_10 = _in_3_d_bits_T_23; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_opcode = _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_8; // @[Arbiter.scala:60:30] wire idle_8 = beatsLeft_8 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_8 = idle_8 & in_4_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_90 = {portsDIO_filtered_1_4_valid, portsDIO_filtered_4_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_8 = _readys_T_90; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_91 = readys_valid_8 == _readys_T_90; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_93 = ~_readys_T_92; // @[Arbiter.scala:22:12] wire _readys_T_94 = ~_readys_T_91; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_8; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_16 = ~readys_mask_8; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_17 = readys_valid_8 & _readys_filter_T_16; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_8 = {_readys_filter_T_17, readys_valid_8}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_52 = readys_filter_8[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_53 = {readys_filter_8[3], readys_filter_8[2:0] \| _readys_unready_T_52}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_54 = _readys_unready_T_53; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_55 = _readys_unready_T_54[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_56 = {readys_mask_8, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_8 = {1'h0, _readys_unready_T_55} \| _readys_unready_T_56; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_24 = readys_unready_8[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_25 = readys_unready_8[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_26 = _readys_readys_T_24 & _readys_readys_T_25; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_8 = ~_readys_readys_T_26; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_97 = readys_readys_8; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_95 = \|readys_valid_8; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_96 = latch_8 & _readys_T_95; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_58 = readys_readys_8 & readys_valid_8; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_59 = {_readys_mask_T_58, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_60 = _readys_mask_T_59[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_61 = _readys_mask_T_58 \| _readys_mask_T_60; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_62 = _readys_mask_T_61; // @[package.scala:253:43, :254:17] wire _readys_T_98 = _readys_T_97[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_8_0 = _readys_T_98; // @[Arbiter.scala:68:{27,76}] wire _readys_T_99 = _readys_T_97[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_8_1 = _readys_T_99; // @[Arbiter.scala:68:{27,76}] wire _winner_T_26 = readys_8_0 & portsDIO_filtered_4_valid; // @[Xbar.scala:352:24] wire winner_8_0 = _winner_T_26; // @[Arbiter.scala:71:{27,69}] wire _winner_T_27 = readys_8_1 & portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24] wire winner_8_1 = _winner_T_27; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_8 = winner_8_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_8 = prefixOR_1_8 \| winner_8_1; // @[Arbiter.scala:71:27, :76:48] wire _in_4_d_valid_T = portsDIO_filtered_4_valid \| portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = or(_T_37, _T_42) node _T_44 = and(_T_32, _T_43) node _T_45 = or(UInt<1>(0h0), _T_44) node _T_46 = and(_T_31, _T_45) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_46, UInt<1>(0h1), "") : assert_2 node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_52 = and(_T_50, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = or(_T_58, _T_63) node _T_65 = and(_T_53, _T_64) node _T_66 = or(UInt<1>(0h0), _T_65) node _T_67 = and(UInt<1>(0h0), _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(is_aligned, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_81, UInt<1>(0h1), "") : assert_7 node _T_85 = not(io.in.a.bits.mask) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_86, UInt<1>(0h1), "") : assert_8 node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_94 : node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_97 = and(_T_95, _T_96) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_98 = shr(io.in.a.bits.source, 4) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) node _T_101 = and(_T_99, _T_100) node _T_102 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_103 = and(_T_101, _T_102) node _T_104 = and(_T_97, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(_T_105, _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_120, UInt<1>(0h1), "") : assert_10 node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_126 = and(_T_124, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_129 = cvt(_T_128) node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000))) node _T_131 = asSInt(_T_130) node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_134 = cvt(_T_133) node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000))) node _T_136 = asSInt(_T_135) node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = or(_T_132, _T_137) node _T_139 = and(_T_127, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = and(UInt<1>(0h0), _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_141, UInt<1>(0h1), "") : assert_11 node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_148, UInt<1>(0h1), "") : assert_13 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_155, UInt<1>(0h1), "") : assert_15 node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_159, UInt<1>(0h1), "") : assert_16 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_164, UInt<1>(0h1), "") : assert_17 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_168, UInt<1>(0h1), "") : assert_18 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_176 = shr(io.in.a.bits.source, 4) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_181 = and(_T_179, _T_180) node _T_182 = and(_T_175, _T_181) node _T_183 = or(UInt<1>(0h0), _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_183, UInt<1>(0h1), "") : assert_19 node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = or(_T_195, _T_200) node _T_202 = and(_T_190, _T_201) node _T_203 = or(UInt<1>(0h0), _T_202) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_203, UInt<1>(0h1), "") : assert_20 node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(is_aligned, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_213, UInt<1>(0h1), "") : assert_23 node _T_217 = eq(io.in.a.bits.mask, mask) node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(_T_217, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_217, UInt<1>(0h1), "") : assert_24 node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_221, UInt<1>(0h1), "") : assert_25 node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_225 : node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_229 = shr(io.in.a.bits.source, 4) node _T_230 = eq(_T_229, UInt<1>(0h0)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_234 = and(_T_232, _T_233) node _T_235 = and(_T_228, _T_234) node _T_236 = or(UInt<1>(0h0), _T_235) node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_239 = and(_T_237, _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_236, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_254, UInt<1>(0h1), "") : assert_26 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_264, UInt<1>(0h1), "") : assert_29 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_268, UInt<1>(0h1), "") : assert_30 node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_272 : node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_276 = shr(io.in.a.bits.source, 4) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_281 = and(_T_279, _T_280) node _T_282 = and(_T_275, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = or(_T_292, _T_297) node _T_299 = and(_T_287, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = and(_T_283, _T_300) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_301, UInt<1>(0h1), "") : assert_31 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(is_aligned, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_311, UInt<1>(0h1), "") : assert_34 node _T_315 = not(mask) node _T_316 = and(io.in.a.bits.mask, _T_315) node _T_317 = eq(_T_316, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_317, UInt<1>(0h1), "") : assert_35 node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_325 = shr(io.in.a.bits.source, 4) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_330 = and(_T_328, _T_329) node _T_331 = and(_T_324, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = or(_T_338, _T_343) node _T_345 = and(_T_333, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_332, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_347, UInt<1>(0h1), "") : assert_36 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(is_aligned, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_357, UInt<1>(0h1), "") : assert_39 node _T_361 = eq(io.in.a.bits.mask, mask) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_361, UInt<1>(0h1), "") : assert_40 node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_365 : node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_369 = shr(io.in.a.bits.source, 4) node _T_370 = eq(_T_369, UInt<1>(0h0)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_374 = and(_T_372, _T_373) node _T_375 = and(_T_368, _T_374) node _T_376 = or(UInt<1>(0h0), _T_375) node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = or(_T_382, _T_387) node _T_389 = and(_T_377, _T_388) node _T_390 = or(UInt<1>(0h0), _T_389) node _T_391 = and(_T_376, _T_390) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_391, UInt<1>(0h1), "") : assert_41 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(is_aligned, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_401, UInt<1>(0h1), "") : assert_44 node _T_405 = eq(io.in.a.bits.mask, mask) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_405, UInt<1>(0h1), "") : assert_45 node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_409 : node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_413 = shr(io.in.a.bits.source, 4) node _T_414 = eq(_T_413, UInt<1>(0h0)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_418 = and(_T_416, _T_417) node _T_419 = and(_T_412, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_423 = cvt(_T_422) node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000))) node _T_425 = asSInt(_T_424) node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = or(_T_426, _T_431) node _T_433 = and(_T_421, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = and(_T_420, _T_434) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_435, UInt<1>(0h1), "") : assert_46 node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(is_aligned, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_445, UInt<1>(0h1), "") : assert_49 node _T_449 = eq(io.in.a.bits.mask, mask) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_449, UInt<1>(0h1), "") : assert_50 node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_453, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_457, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_461 : node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_465, UInt<1>(0h1), "") : assert_54 node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_469, UInt<1>(0h1), "") : assert_55 node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_473, UInt<1>(0h1), "") : assert_56 node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_477, UInt<1>(0h1), "") : assert_57 node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(sink_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_488, UInt<1>(0h1), "") : assert_60 node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_492, UInt<1>(0h1), "") : assert_61 node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_496, UInt<1>(0h1), "") : assert_62 node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_500, UInt<1>(0h1), "") : assert_63 node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_505 = or(UInt<1>(0h1), _T_504) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_505, UInt<1>(0h1), "") : assert_64 node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_509 : node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(sink_ok, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_516, UInt<1>(0h1), "") : assert_67 node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_520, UInt<1>(0h1), "") : assert_68 node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_524, UInt<1>(0h1), "") : assert_69 node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_529 = or(_T_528, io.in.d.bits.corrupt) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_529, UInt<1>(0h1), "") : assert_70 node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_534 = or(UInt<1>(0h1), _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_534, UInt<1>(0h1), "") : assert_71 node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_538 : node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_542, UInt<1>(0h1), "") : assert_73 node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_546, UInt<1>(0h1), "") : assert_74 node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_551 = or(UInt<1>(0h1), _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_551, UInt<1>(0h1), "") : assert_75 node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_555 : node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_559, UInt<1>(0h1), "") : assert_77 node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_564 = or(_T_563, io.in.d.bits.corrupt) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_564, UInt<1>(0h1), "") : assert_78 node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_569 = or(UInt<1>(0h1), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_569, UInt<1>(0h1), "") : assert_79 node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_573 : node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_577, UInt<1>(0h1), "") : assert_81 node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_581, UInt<1>(0h1), "") : assert_82 node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_586 = or(UInt<1>(0h1), _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_586, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_590, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_594, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_598, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_602 = eq(a_first, UInt<1>(0h0)) node _T_603 = and(io.in.a.valid, _T_602) when _T_603 : node _T_604 = eq(io.in.a.bits.opcode, opcode) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_604, UInt<1>(0h1), "") : assert_87 node _T_608 = eq(io.in.a.bits.param, param) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_608, UInt<1>(0h1), "") : assert_88 node _T_612 = eq(io.in.a.bits.size, size) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_612, UInt<1>(0h1), "") : assert_89 node _T_616 = eq(io.in.a.bits.source, source) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_616, UInt<1>(0h1), "") : assert_90 node _T_620 = eq(io.in.a.bits.address, address) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_620, UInt<1>(0h1), "") : assert_91 node _T_624 = and(io.in.a.ready, io.in.a.valid) node _T_625 = and(_T_624, a_first) when _T_625 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_626 = eq(d_first, UInt<1>(0h0)) node _T_627 = and(io.in.d.valid, _T_626) when _T_627 : node _T_628 = eq(io.in.d.bits.opcode, opcode_1) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_628, UInt<1>(0h1), "") : assert_92 node _T_632 = eq(io.in.d.bits.param, param_1) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_632, UInt<1>(0h1), "") : assert_93 node _T_636 = eq(io.in.d.bits.size, size_1) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_636, UInt<1>(0h1), "") : assert_94 node _T_640 = eq(io.in.d.bits.source, source_1) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_640, UInt<1>(0h1), "") : assert_95 node _T_644 = eq(io.in.d.bits.sink, sink) node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(_T_644, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_644, UInt<1>(0h1), "") : assert_96 node _T_648 = eq(io.in.d.bits.denied, denied) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_648, UInt<1>(0h1), "") : assert_97 node _T_652 = and(io.in.d.ready, io.in.d.valid) node _T_653 = and(_T_652, d_first) when _T_653 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_654 = and(io.in.a.valid, a_first_1) node _T_655 = and(_T_654, UInt<1>(0h1)) when _T_655 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_656 = and(io.in.a.ready, io.in.a.valid) node _T_657 = and(_T_656, a_first_1) node _T_658 = and(_T_657, UInt<1>(0h1)) when _T_658 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_659 = dshr(inflight, io.in.a.bits.source) node _T_660 = bits(_T_659, 0, 0) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_661, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_665 = and(io.in.d.valid, d_first_1) node _T_666 = and(_T_665, UInt<1>(0h1)) node _T_667 = eq(d_release_ack, UInt<1>(0h0)) node _T_668 = and(_T_666, _T_667) when _T_668 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_669 = and(io.in.d.ready, io.in.d.valid) node _T_670 = and(_T_669, d_first_1) node _T_671 = and(_T_670, UInt<1>(0h1)) node _T_672 = eq(d_release_ack, UInt<1>(0h0)) node _T_673 = and(_T_671, _T_672) when _T_673 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_674 = and(io.in.d.valid, d_first_1) node _T_675 = and(_T_674, UInt<1>(0h1)) node _T_676 = eq(d_release_ack, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) when _T_677 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_678 = dshr(inflight, io.in.d.bits.source) node _T_679 = bits(_T_678, 0, 0) node _T_680 = or(_T_679, same_cycle_resp) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_680, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_686 = or(_T_684, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_686, UInt<1>(0h1), "") : assert_100 node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_690, UInt<1>(0h1), "") : assert_101 else : node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_696 = or(_T_694, _T_695) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_696, UInt<1>(0h1), "") : assert_102 node _T_700 = eq(io.in.d.bits.size, a_size_lookup) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_700, UInt<1>(0h1), "") : assert_103 node _T_704 = and(io.in.d.valid, d_first_1) node _T_705 = and(_T_704, a_first_1) node _T_706 = and(_T_705, io.in.a.valid) node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(d_release_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_712 = or(_T_711, io.in.a.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_712, UInt<1>(0h1), "") : assert_104 node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_717 = orr(a_set_wo_ready) node _T_718 = eq(_T_717, UInt<1>(0h0)) node _T_719 = or(_T_716, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_719, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_92 node _T_723 = orr(inflight) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_726 = or(_T_724, _T_725) node _T_727 = lt(watchdog, plusarg_reader.out) node _T_728 = or(_T_726, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_728, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_732 = and(io.in.a.ready, io.in.a.valid) node _T_733 = and(io.in.d.ready, io.in.d.valid) node _T_734 = or(_T_732, _T_733) when _T_734 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_735 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_738 = and(_T_736, _T_737) node _T_739 = and(_T_735, _T_738) when _T_739 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_741 = and(_T_740, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_744 = and(_T_742, _T_743) node _T_745 = and(_T_741, _T_744) when _T_745 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) node _T_747 = bits(_T_746, 0, 0) node _T_748 = eq(_T_747, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_748, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_752 = and(io.in.d.valid, d_first_2) node _T_753 = and(_T_752, UInt<1>(0h1)) node _T_754 = and(_T_753, d_release_ack_1) when _T_754 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_755 = and(io.in.d.ready, io.in.d.valid) node _T_756 = and(_T_755, d_first_2) node _T_757 = and(_T_756, UInt<1>(0h1)) node _T_758 = and(_T_757, d_release_ack_1) when _T_758 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_759 = and(io.in.d.valid, d_first_2) node _T_760 = and(_T_759, UInt<1>(0h1)) node _T_761 = and(_T_760, d_release_ack_1) when _T_761 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_762 = dshr(inflight_1, io.in.d.bits.source) node _T_763 = bits(_T_762, 0, 0) node _T_764 = or(_T_763, same_cycle_resp_1) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_764, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_768, UInt<1>(0h1), "") : assert_109 else : node _T_772 = eq(io.in.d.bits.size, c_size_lookup) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_772, UInt<1>(0h1), "") : assert_110 node _T_776 = and(io.in.d.valid, d_first_2) node _T_777 = and(_T_776, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_778 = and(_T_777, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_780 = and(_T_778, _T_779) node _T_781 = and(_T_780, d_release_ack_1) node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) when _T_783 : node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_785 = or(_T_784, _WIRE_23.ready) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_785, UInt<1>(0h1), "") : assert_111 node _T_789 = orr(c_set_wo_ready) when _T_789 : node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_790, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_93 node _T_794 = orr(inflight_1) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_797 = or(_T_795, _T_796) node _T_798 = lt(watchdog_1, plusarg_reader_1.out) node _T_799 = or(_T_797, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_799, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_804 = and(io.in.d.ready, io.in.d.valid) node _T_805 = or(_T_803, _T_804) when _T_805 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PLICFanIn : input clock : Clock input reset : Reset output io : { flip prio : UInt<2>[2], flip ip : UInt<2>, dev : UInt<2>, max : UInt<2>} node effectivePriority_0 = shl(UInt<1>(0h1), 2) node _effectivePriority_T = bits(io.ip, 0, 0) node _effectivePriority_T_1 = bits(io.ip, 1, 1) node effectivePriority_1 = cat(_effectivePriority_T, io.prio[0]) node effectivePriority_2 = cat(_effectivePriority_T_1, io.prio[1]) node _left_T = geq(effectivePriority_0, effectivePriority_1) node _left_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) node left_1 = mux(_left_T, effectivePriority_0, effectivePriority_1) node left_2 = mux(_left_T, UInt<1>(0h0), _left_T_1) node _T = geq(left_1, effectivePriority_2) node _T_1 = or(UInt<2>(0h2), UInt<1>(0h0)) node maxPri = mux(_T, left_1, effectivePriority_2) node maxDev = mux(_T, left_2, _T_1) connect io.max, maxPri connect io.dev, maxDev	module PLICFanIn( // @[Plic.scala:338:7] input [1:0] io_prio_0, // @[Plic.scala:339:14] input [1:0] io_prio_1, // @[Plic.scala:339:14] input [1:0] io_ip, // @[Plic.scala:339:14] output [1:0] io_dev, // @[Plic.scala:339:14] output [1:0] io_max // @[Plic.scala:339:14] ); wire [2:0] effectivePriority_1 = {io_ip[0], io_prio_0}; // @[Plic.scala:355:{55,100}] wire [2:0] left_1 = effectivePriority_1 < 3'h5 ? 3'h4 : effectivePriority_1; // @[Misc.scala:35:9] wire _GEN = left_1 >= {io_ip[1], io_prio_1}; // @[Misc.scala:35:9] assign io_dev = _GEN ? {1'h0, effectivePriority_1 > 3'h4} : 2'h2; // @[Misc.scala:35:36] assign io_max = _GEN ? left_1[1:0] : io_prio_1; // @[Misc.scala:35:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_60 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_60( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_172 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_428 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_172( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_428 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE : UInt<1>[13] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[7]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[8]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[9]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[10]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[11]) node source_ok = or(_source_ok_T_43, _source_ok_WIRE[12]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = and(_T_11, _T_24) node _T_129 = and(_T_128, _T_37) node _T_130 = and(_T_129, _T_50) node _T_131 = and(_T_130, _T_63) node _T_132 = and(_T_131, _T_71) node _T_133 = and(_T_132, _T_79) node _T_134 = and(_T_133, _T_87) node _T_135 = and(_T_134, _T_95) node _T_136 = and(_T_135, _T_103) node _T_137 = and(_T_136, _T_111) node _T_138 = and(_T_137, _T_119) node _T_139 = and(_T_138, _T_127) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_139, UInt<1>(0h1), "") : assert_1 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_4) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<1>(0h1)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_5) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_160 = shr(io.in.a.bits.source, 2) node _T_161 = eq(_T_160, UInt<2>(0h2)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_6) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_166 = shr(io.in.a.bits.source, 2) node _T_167 = eq(_T_166, UInt<2>(0h3)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_7) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_173 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_174 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_175 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_177 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_180 = or(_T_147, _T_153) node _T_181 = or(_T_180, _T_159) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_171) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_173) node _T_186 = or(_T_185, _T_174) node _T_187 = or(_T_186, _T_175) node _T_188 = or(_T_187, _T_176) node _T_189 = or(_T_188, _T_177) node _T_190 = or(_T_189, _T_178) node _T_191 = or(_T_190, _T_179) node _T_192 = and(_T_146, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_195 = or(UInt<1>(0h0), _T_194) node _T_196 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<29>(0h10000000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _T_207 = and(_T_195, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = and(_T_193, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_209, UInt<1>(0h1), "") : assert_2 node _T_213 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<1>(0h0)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_8) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h1)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_9) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<2>(0h2)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_10) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h3)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_11) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _WIRE : UInt<1>[13] connect _WIRE[0], _T_213 connect _WIRE[1], _T_219 connect _WIRE[2], _T_225 connect _WIRE[3], _T_231 connect _WIRE[4], _T_237 connect _WIRE[5], _T_238 connect _WIRE[6], _T_239 connect _WIRE[7], _T_240 connect _WIRE[8], _T_241 connect _WIRE[9], _T_242 connect _WIRE[10], _T_243 connect _WIRE[11], _T_244 connect _WIRE[12], _T_245 node _T_246 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_247 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_250 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_251 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_252 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[5], _T_246, UInt<1>(0h0)) node _T_258 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[7], _T_247, UInt<1>(0h0)) node _T_260 = mux(_WIRE[8], _T_248, UInt<1>(0h0)) node _T_261 = mux(_WIRE[9], _T_249, UInt<1>(0h0)) node _T_262 = mux(_WIRE[10], _T_250, UInt<1>(0h0)) node _T_263 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[12], _T_251, UInt<1>(0h0)) node _T_265 = or(_T_252, _T_253) node _T_266 = or(_T_265, _T_254) node _T_267 = or(_T_266, _T_255) node _T_268 = or(_T_267, _T_256) node _T_269 = or(_T_268, _T_257) node _T_270 = or(_T_269, _T_258) node _T_271 = or(_T_270, _T_259) node _T_272 = or(_T_271, _T_260) node _T_273 = or(_T_272, _T_261) node _T_274 = or(_T_273, _T_262) node _T_275 = or(_T_274, _T_263) node _T_276 = or(_T_275, _T_264) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_276 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<17>(0h10000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<29>(0h10000000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = or(_T_285, _T_290) node _T_292 = and(_T_280, _T_291) node _T_293 = or(UInt<1>(0h0), _T_292) node _T_294 = and(_WIRE_1, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_294, UInt<1>(0h1), "") : assert_3 node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(source_ok, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_301 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_301, UInt<1>(0h1), "") : assert_5 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(is_aligned, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_308 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_308, UInt<1>(0h1), "") : assert_7 node _T_312 = not(io.in.a.bits.mask) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_313, UInt<1>(0h1), "") : assert_8 node _T_317 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_317, UInt<1>(0h1), "") : assert_9 node _T_321 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_326 = shr(io.in.a.bits.source, 2) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = leq(UInt<1>(0h0), uncommonBits_12) node _T_329 = and(_T_327, _T_328) node _T_330 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_331 = and(_T_329, _T_330) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_332 = shr(io.in.a.bits.source, 2) node _T_333 = eq(_T_332, UInt<1>(0h1)) node _T_334 = leq(UInt<1>(0h0), uncommonBits_13) node _T_335 = and(_T_333, _T_334) node _T_336 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_337 = and(_T_335, _T_336) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_338 = shr(io.in.a.bits.source, 2) node _T_339 = eq(_T_338, UInt<2>(0h2)) node _T_340 = leq(UInt<1>(0h0), uncommonBits_14) node _T_341 = and(_T_339, _T_340) node _T_342 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_343 = and(_T_341, _T_342) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_344 = shr(io.in.a.bits.source, 2) node _T_345 = eq(_T_344, UInt<2>(0h3)) node _T_346 = leq(UInt<1>(0h0), uncommonBits_15) node _T_347 = and(_T_345, _T_346) node _T_348 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_352 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_356 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_358 = or(_T_325, _T_331) node _T_359 = or(_T_358, _T_337) node _T_360 = or(_T_359, _T_343) node _T_361 = or(_T_360, _T_349) node _T_362 = or(_T_361, _T_350) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_353) node _T_366 = or(_T_365, _T_354) node _T_367 = or(_T_366, _T_355) node _T_368 = or(_T_367, _T_356) node _T_369 = or(_T_368, _T_357) node _T_370 = and(_T_324, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<17>(0h10000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_378, _T_383) node _T_385 = and(_T_373, _T_384) node _T_386 = or(UInt<1>(0h0), _T_385) node _T_387 = and(_T_371, _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_387, UInt<1>(0h1), "") : assert_10 node _T_391 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<1>(0h0)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_16) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_398 = shr(io.in.a.bits.source, 2) node _T_399 = eq(_T_398, UInt<1>(0h1)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_17) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_404 = shr(io.in.a.bits.source, 2) node _T_405 = eq(_T_404, UInt<2>(0h2)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_18) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_410 = shr(io.in.a.bits.source, 2) node _T_411 = eq(_T_410, UInt<2>(0h3)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_19) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _WIRE_2 : UInt<1>[13] connect _WIRE_2[0], _T_391 connect _WIRE_2[1], _T_397 connect _WIRE_2[2], _T_403 connect _WIRE_2[3], _T_409 connect _WIRE_2[4], _T_415 connect _WIRE_2[5], _T_416 connect _WIRE_2[6], _T_417 connect _WIRE_2[7], _T_418 connect _WIRE_2[8], _T_419 connect _WIRE_2[9], _T_420 connect _WIRE_2[10], _T_421 connect _WIRE_2[11], _T_422 connect _WIRE_2[12], _T_423 node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_425 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_426 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_427 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_428 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_429 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_430 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_432 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_434 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE_2[5], _T_424, UInt<1>(0h0)) node _T_436 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = mux(_WIRE_2[7], _T_425, UInt<1>(0h0)) node _T_438 = mux(_WIRE_2[8], _T_426, UInt<1>(0h0)) node _T_439 = mux(_WIRE_2[9], _T_427, UInt<1>(0h0)) node _T_440 = mux(_WIRE_2[10], _T_428, UInt<1>(0h0)) node _T_441 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_442 = mux(_WIRE_2[12], _T_429, UInt<1>(0h0)) node _T_443 = or(_T_430, _T_431) node _T_444 = or(_T_443, _T_432) node _T_445 = or(_T_444, _T_433) node _T_446 = or(_T_445, _T_434) node _T_447 = or(_T_446, _T_435) node _T_448 = or(_T_447, _T_436) node _T_449 = or(_T_448, _T_437) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_439) node _T_452 = or(_T_451, _T_440) node _T_453 = or(_T_452, _T_441) node _T_454 = or(_T_453, _T_442) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_454 node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _T_458 = or(UInt<1>(0h0), _T_457) node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<29>(0h10000000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = or(_T_463, _T_468) node _T_470 = and(_T_458, _T_469) node _T_471 = or(UInt<1>(0h0), _T_470) node _T_472 = and(_WIRE_3, _T_471) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_472, UInt<1>(0h1), "") : assert_11 node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(source_ok, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_479 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_479, UInt<1>(0h1), "") : assert_13 node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(is_aligned, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_486 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_486, UInt<1>(0h1), "") : assert_15 node _T_490 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_490, UInt<1>(0h1), "") : assert_16 node _T_494 = not(io.in.a.bits.mask) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_495, UInt<1>(0h1), "") : assert_17 node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_499, UInt<1>(0h1), "") : assert_18 node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_503 : node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_20) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_514 = shr(io.in.a.bits.source, 2) node _T_515 = eq(_T_514, UInt<1>(0h1)) node _T_516 = leq(UInt<1>(0h0), uncommonBits_21) node _T_517 = and(_T_515, _T_516) node _T_518 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_519 = and(_T_517, _T_518) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_520 = shr(io.in.a.bits.source, 2) node _T_521 = eq(_T_520, UInt<2>(0h2)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_22) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_525 = and(_T_523, _T_524) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<2>(0h3)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_23) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_536 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_537 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_538 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_540 = or(_T_507, _T_513) node _T_541 = or(_T_540, _T_519) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_531) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_533) node _T_546 = or(_T_545, _T_534) node _T_547 = or(_T_546, _T_535) node _T_548 = or(_T_547, _T_536) node _T_549 = or(_T_548, _T_537) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_539) node _T_552 = and(_T_506, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_553, UInt<1>(0h1), "") : assert_19 node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<29>(0h10000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = or(_T_565, _T_570) node _T_572 = and(_T_560, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_573, UInt<1>(0h1), "") : assert_20 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_583, UInt<1>(0h1), "") : assert_23 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_587, UInt<1>(0h1), "") : assert_24 node _T_591 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_591, UInt<1>(0h1), "") : assert_25 node _T_595 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_595 : node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_600 = shr(io.in.a.bits.source, 2) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_24) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_606 = shr(io.in.a.bits.source, 2) node _T_607 = eq(_T_606, UInt<1>(0h1)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_25) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_612 = shr(io.in.a.bits.source, 2) node _T_613 = eq(_T_612, UInt<2>(0h2)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_26) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<2>(0h3)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_27) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_628 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_631 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_632 = or(_T_599, _T_605) node _T_633 = or(_T_632, _T_611) node _T_634 = or(_T_633, _T_617) node _T_635 = or(_T_634, _T_623) node _T_636 = or(_T_635, _T_624) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_626) node _T_639 = or(_T_638, _T_627) node _T_640 = or(_T_639, _T_628) node _T_641 = or(_T_640, _T_629) node _T_642 = or(_T_641, _T_630) node _T_643 = or(_T_642, _T_631) node _T_644 = and(_T_598, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_647 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_648 = and(_T_646, _T_647) node _T_649 = or(UInt<1>(0h0), _T_648) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<29>(0h10000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_654, _T_659) node _T_661 = and(_T_649, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = and(_T_645, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_663, UInt<1>(0h1), "") : assert_26 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_673, UInt<1>(0h1), "") : assert_29 node _T_677 = eq(io.in.a.bits.mask, mask) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_677, UInt<1>(0h1), "") : assert_30 node _T_681 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_681 : node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_28) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_692 = shr(io.in.a.bits.source, 2) node _T_693 = eq(_T_692, UInt<1>(0h1)) node _T_694 = leq(UInt<1>(0h0), uncommonBits_29) node _T_695 = and(_T_693, _T_694) node _T_696 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_697 = and(_T_695, _T_696) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<2>(0h2)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_30) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<2>(0h3)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_31) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_712 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_718 = or(_T_685, _T_691) node _T_719 = or(_T_718, _T_697) node _T_720 = or(_T_719, _T_703) node _T_721 = or(_T_720, _T_709) node _T_722 = or(_T_721, _T_710) node _T_723 = or(_T_722, _T_711) node _T_724 = or(_T_723, _T_712) node _T_725 = or(_T_724, _T_713) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_715) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_717) node _T_730 = and(_T_684, _T_729) node _T_731 = or(UInt<1>(0h0), _T_730) node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_733 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_734 = and(_T_732, _T_733) node _T_735 = or(UInt<1>(0h0), _T_734) node _T_736 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<29>(0h10000000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = or(_T_740, _T_745) node _T_747 = and(_T_735, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_731, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_749, UInt<1>(0h1), "") : assert_31 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_759 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_759, UInt<1>(0h1), "") : assert_34 node _T_763 = not(mask) node _T_764 = and(io.in.a.bits.mask, _T_763) node _T_765 = eq(_T_764, UInt<1>(0h0)) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_765, UInt<1>(0h1), "") : assert_35 node _T_769 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_769 : node _T_770 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_771 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_774 = shr(io.in.a.bits.source, 2) node _T_775 = eq(_T_774, UInt<1>(0h0)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_32) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_780 = shr(io.in.a.bits.source, 2) node _T_781 = eq(_T_780, UInt<1>(0h1)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_33) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_786 = shr(io.in.a.bits.source, 2) node _T_787 = eq(_T_786, UInt<2>(0h2)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_34) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_792 = shr(io.in.a.bits.source, 2) node _T_793 = eq(_T_792, UInt<2>(0h3)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_35) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_797 = and(_T_795, _T_796) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_806 = or(_T_773, _T_779) node _T_807 = or(_T_806, _T_785) node _T_808 = or(_T_807, _T_791) node _T_809 = or(_T_808, _T_797) node _T_810 = or(_T_809, _T_798) node _T_811 = or(_T_810, _T_799) node _T_812 = or(_T_811, _T_800) node _T_813 = or(_T_812, _T_801) node _T_814 = or(_T_813, _T_802) node _T_815 = or(_T_814, _T_803) node _T_816 = or(_T_815, _T_804) node _T_817 = or(_T_816, _T_805) node _T_818 = and(_T_772, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<17>(0h10000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<29>(0h10000000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = or(_T_828, _T_833) node _T_835 = and(_T_823, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_819, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_837, UInt<1>(0h1), "") : assert_36 node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(source_ok, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(is_aligned, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_847 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_847, UInt<1>(0h1), "") : assert_39 node _T_851 = eq(io.in.a.bits.mask, mask) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_851, UInt<1>(0h1), "") : assert_40 node _T_855 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_855 : node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<1>(0h0)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_36) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_866 = shr(io.in.a.bits.source, 2) node _T_867 = eq(_T_866, UInt<1>(0h1)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_37) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_872 = shr(io.in.a.bits.source, 2) node _T_873 = eq(_T_872, UInt<2>(0h2)) node _T_874 = leq(UInt<1>(0h0), uncommonBits_38) node _T_875 = and(_T_873, _T_874) node _T_876 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_877 = and(_T_875, _T_876) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<2>(0h3)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_39) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_892 = or(_T_859, _T_865) node _T_893 = or(_T_892, _T_871) node _T_894 = or(_T_893, _T_877) node _T_895 = or(_T_894, _T_883) node _T_896 = or(_T_895, _T_884) node _T_897 = or(_T_896, _T_885) node _T_898 = or(_T_897, _T_886) node _T_899 = or(_T_898, _T_887) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_889) node _T_902 = or(_T_901, _T_890) node _T_903 = or(_T_902, _T_891) node _T_904 = and(_T_858, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_921) node _T_923 = and(_T_905, _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_923, UInt<1>(0h1), "") : assert_41 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(source_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(is_aligned, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_933 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_933, UInt<1>(0h1), "") : assert_44 node _T_937 = eq(io.in.a.bits.mask, mask) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_937, UInt<1>(0h1), "") : assert_45 node _T_941 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_941 : node _T_942 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_943 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_944 = and(_T_942, _T_943) node _T_945 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<1>(0h0)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_40) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<1>(0h1)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_41) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<2>(0h2)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_42) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_964 = shr(io.in.a.bits.source, 2) node _T_965 = eq(_T_964, UInt<2>(0h3)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_43) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_978 = or(_T_945, _T_951) node _T_979 = or(_T_978, _T_957) node _T_980 = or(_T_979, _T_963) node _T_981 = or(_T_980, _T_969) node _T_982 = or(_T_981, _T_970) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_972) node _T_985 = or(_T_984, _T_973) node _T_986 = or(_T_985, _T_974) node _T_987 = or(_T_986, _T_975) node _T_988 = or(_T_987, _T_976) node _T_989 = or(_T_988, _T_977) node _T_990 = and(_T_944, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_994 = and(_T_992, _T_993) node _T_995 = or(UInt<1>(0h0), _T_994) node _T_996 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_997 = cvt(_T_996) node _T_998 = and(_T_997, asSInt(UInt<17>(0h10000))) node _T_999 = asSInt(_T_998) node _T_1000 = eq(_T_999, asSInt(UInt<1>(0h0))) node _T_1001 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1002 = cvt(_T_1001) node _T_1003 = and(_T_1002, asSInt(UInt<29>(0h10000000))) node _T_1004 = asSInt(_T_1003) node _T_1005 = eq(_T_1004, asSInt(UInt<1>(0h0))) node _T_1006 = or(_T_1000, _T_1005) node _T_1007 = and(_T_995, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_T_991, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_46 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(is_aligned, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1019 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_49 node _T_1023 = eq(io.in.a.bits.mask, mask) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_50 node _T_1027 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1031 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_52 node _source_ok_T_44 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h0)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<1>(0h1)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h2)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<2>(0h3)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_1 : UInt<1>[13] connect _source_ok_WIRE_1[0], _source_ok_T_44 connect _source_ok_WIRE_1[1], _source_ok_T_50 connect _source_ok_WIRE_1[2], _source_ok_T_56 connect _source_ok_WIRE_1[3], _source_ok_T_62 connect _source_ok_WIRE_1[4], _source_ok_T_68 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 connect _source_ok_WIRE_1[8], _source_ok_T_72 connect _source_ok_WIRE_1[9], _source_ok_T_73 connect _source_ok_WIRE_1[10], _source_ok_T_74 connect _source_ok_WIRE_1[11], _source_ok_T_75 connect _source_ok_WIRE_1[12], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[11]) node source_ok_1 = or(_source_ok_T_87, _source_ok_WIRE_1[12]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1035 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(source_ok_1, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1039 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_54 node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_55 node _T_1047 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_56 node _T_1051 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_57 node _T_1055 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(sink_ok, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1062 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_60 node _T_1066 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_61 node _T_1070 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_62 node _T_1074 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_63 node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1079 = or(UInt<1>(0h1), _T_1078) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_64 node _T_1083 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1083 : node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok_1, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(sink_ok, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1090 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_67 node _T_1094 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_68 node _T_1098 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_69 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(_T_1102, io.in.d.bits.corrupt) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_70 node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1108 = or(UInt<1>(0h1), _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_71 node _T_1112 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1112 : node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1116 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_73 node _T_1120 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_74 node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1125 = or(UInt<1>(0h1), _T_1124) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_75 node _T_1129 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1129 : node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(source_ok_1, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1133 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_77 node _T_1137 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1138 = or(_T_1137, io.in.d.bits.corrupt) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_78 node _T_1142 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1143 = or(UInt<1>(0h1), _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_79 node _T_1147 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1147 : node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(source_ok_1, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1151 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_81 node _T_1155 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_82 node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1160 = or(UInt<1>(0h1), _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1164 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_84 node _T_1168 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) node _T_1170 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<1>(0h0))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1169, _T_1174) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1176 = shr(io.in.b.bits.source, 2) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) node _T_1178 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) node _T_1183 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1184 = cvt(_T_1183) node _T_1185 = and(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = asSInt(_T_1185) node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) node _T_1188 = or(_T_1182, _T_1187) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1189 = shr(io.in.b.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h1)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) node _T_1196 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1197 = cvt(_T_1196) node _T_1198 = and(_T_1197, asSInt(UInt<1>(0h0))) node _T_1199 = asSInt(_T_1198) node _T_1200 = eq(_T_1199, asSInt(UInt<1>(0h0))) node _T_1201 = or(_T_1195, _T_1200) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1202 = shr(io.in.b.bits.source, 2) node _T_1203 = eq(_T_1202, UInt<2>(0h2)) node _T_1204 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1210 = cvt(_T_1209) node _T_1211 = and(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = asSInt(_T_1211) node _T_1213 = eq(_T_1212, asSInt(UInt<1>(0h0))) node _T_1214 = or(_T_1208, _T_1213) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1215 = shr(io.in.b.bits.source, 2) node _T_1216 = eq(_T_1215, UInt<2>(0h3)) node _T_1217 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1220 = and(_T_1218, _T_1219) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) node _T_1238 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<1>(0h0))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = or(_T_1237, _T_1242) node _T_1244 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) node _T_1246 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1247 = cvt(_T_1246) node _T_1248 = and(_T_1247, asSInt(UInt<1>(0h0))) node _T_1249 = asSInt(_T_1248) node _T_1250 = eq(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = or(_T_1245, _T_1250) node _T_1252 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) node _T_1254 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = or(_T_1253, _T_1258) node _T_1260 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) node _T_1262 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1263 = cvt(_T_1262) node _T_1264 = and(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = asSInt(_T_1264) node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0))) node _T_1267 = or(_T_1261, _T_1266) node _T_1268 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) node _T_1270 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = or(_T_1269, _T_1274) node _T_1276 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) node _T_1278 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1277, _T_1282) node _T_1284 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = or(_T_1285, _T_1290) node _T_1292 = and(_T_1175, _T_1188) node _T_1293 = and(_T_1292, _T_1201) node _T_1294 = and(_T_1293, _T_1214) node _T_1295 = and(_T_1294, _T_1227) node _T_1296 = and(_T_1295, _T_1235) node _T_1297 = and(_T_1296, _T_1243) node _T_1298 = and(_T_1297, _T_1251) node _T_1299 = and(_T_1298, _T_1259) node _T_1300 = and(_T_1299, _T_1267) node _T_1301 = and(_T_1300, _T_1275) node _T_1302 = and(_T_1301, _T_1283) node _T_1303 = and(_T_1302, _T_1291) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h20)) wire _legal_source_WIRE : UInt<1>[13] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_41 = mux(_legal_source_WIRE[8], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[9], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[10], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[11], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[12], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_46 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_35) node _legal_source_T_48 = or(_legal_source_T_47, _legal_source_T_36) node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_37) node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_38) node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_39) node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_40) node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_41) node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_42) node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_43) node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_44) node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_45) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_57 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1307 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1307 : node _T_1308 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1309 = shr(io.in.b.bits.source, 2) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) node _T_1311 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1314 = and(_T_1312, _T_1313) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1315 = shr(io.in.b.bits.source, 2) node _T_1316 = eq(_T_1315, UInt<1>(0h1)) node _T_1317 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1318 = and(_T_1316, _T_1317) node _T_1319 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1320 = and(_T_1318, _T_1319) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1321 = shr(io.in.b.bits.source, 2) node _T_1322 = eq(_T_1321, UInt<2>(0h2)) node _T_1323 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1324 = and(_T_1322, _T_1323) node _T_1325 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1326 = and(_T_1324, _T_1325) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1327 = shr(io.in.b.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<2>(0h3)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _T_1333 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1334 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1335 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1336 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1337 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1338 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1339 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1340 = eq(io.in.b.bits.source, UInt<6>(0h20)) wire _WIRE_4 : UInt<1>[13] connect _WIRE_4[0], _T_1308 connect _WIRE_4[1], _T_1314 connect _WIRE_4[2], _T_1320 connect _WIRE_4[3], _T_1326 connect _WIRE_4[4], _T_1332 connect _WIRE_4[5], _T_1333 connect _WIRE_4[6], _T_1334 connect _WIRE_4[7], _T_1335 connect _WIRE_4[8], _T_1336 connect _WIRE_4[9], _T_1337 connect _WIRE_4[10], _T_1338 connect _WIRE_4[11], _T_1339 connect _WIRE_4[12], _T_1340 node _T_1341 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1342 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1343 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1344 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1345 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1346 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1347 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1349 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1350 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1351 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1352 = mux(_WIRE_4[5], _T_1341, UInt<1>(0h0)) node _T_1353 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1354 = mux(_WIRE_4[7], _T_1342, UInt<1>(0h0)) node _T_1355 = mux(_WIRE_4[8], _T_1343, UInt<1>(0h0)) node _T_1356 = mux(_WIRE_4[9], _T_1344, UInt<1>(0h0)) node _T_1357 = mux(_WIRE_4[10], _T_1345, UInt<1>(0h0)) node _T_1358 = mux(_WIRE_4[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1359 = mux(_WIRE_4[12], _T_1346, UInt<1>(0h0)) node _T_1360 = or(_T_1347, _T_1348) node _T_1361 = or(_T_1360, _T_1349) node _T_1362 = or(_T_1361, _T_1350) node _T_1363 = or(_T_1362, _T_1351) node _T_1364 = or(_T_1363, _T_1352) node _T_1365 = or(_T_1364, _T_1353) node _T_1366 = or(_T_1365, _T_1354) node _T_1367 = or(_T_1366, _T_1355) node _T_1368 = or(_T_1367, _T_1356) node _T_1369 = or(_T_1368, _T_1357) node _T_1370 = or(_T_1369, _T_1358) node _T_1371 = or(_T_1370, _T_1359) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1371 node _T_1372 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1373 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _T_1375 = or(UInt<1>(0h0), _T_1374) node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<17>(0h10000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<29>(0h10000000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = or(_T_1380, _T_1385) node _T_1387 = and(_T_1375, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = and(_WIRE_5, _T_1388) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_86 node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(address_ok, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(legal_source, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1402 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_90 node _T_1406 = eq(io.in.b.bits.mask, mask_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_91 node _T_1410 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_92 node _T_1414 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1414 : node _T_1415 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1416 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = or(UInt<1>(0h0), _T_1417) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<29>(0h10000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = or(_T_1423, _T_1428) node _T_1430 = and(_T_1418, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = and(UInt<1>(0h0), _T_1431) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_93 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(address_ok, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(legal_source, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1445 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_97 node _T_1449 = eq(io.in.b.bits.mask, mask_1) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_98 node _T_1453 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_99 node _T_1457 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1457 : node _T_1458 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1459 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1460 = and(_T_1458, _T_1459) node _T_1461 = or(UInt<1>(0h0), _T_1460) node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<29>(0h10000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = or(_T_1466, _T_1471) node _T_1473 = and(_T_1461, _T_1472) node _T_1474 = or(UInt<1>(0h0), _T_1473) node _T_1475 = and(UInt<1>(0h0), _T_1474) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_100 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(address_ok, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(legal_source, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1488 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_104 node _T_1492 = eq(io.in.b.bits.mask, mask_1) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_105 node _T_1496 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1496 : node _T_1497 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1498 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1499 = and(_T_1497, _T_1498) node _T_1500 = or(UInt<1>(0h0), _T_1499) node _T_1501 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<17>(0h10000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<29>(0h10000000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = or(_T_1505, _T_1510) node _T_1512 = and(_T_1500, _T_1511) node _T_1513 = or(UInt<1>(0h0), _T_1512) node _T_1514 = and(UInt<1>(0h0), _T_1513) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_106 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(address_ok, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(legal_source, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1527 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_110 node _T_1531 = not(mask_1) node _T_1532 = and(io.in.b.bits.mask, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_111 node _T_1537 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1537 : node _T_1538 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1539 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1540 = and(_T_1538, _T_1539) node _T_1541 = or(UInt<1>(0h0), _T_1540) node _T_1542 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1543 = cvt(_T_1542) node _T_1544 = and(_T_1543, asSInt(UInt<17>(0h10000))) node _T_1545 = asSInt(_T_1544) node _T_1546 = eq(_T_1545, asSInt(UInt<1>(0h0))) node _T_1547 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<29>(0h10000000))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _T_1553 = and(_T_1541, _T_1552) node _T_1554 = or(UInt<1>(0h0), _T_1553) node _T_1555 = and(UInt<1>(0h0), _T_1554) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_112 node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(address_ok, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(legal_source, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1568 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_116 node _T_1572 = eq(io.in.b.bits.mask, mask_1) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_117 node _T_1576 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1576 : node _T_1577 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1578 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1579 = and(_T_1577, _T_1578) node _T_1580 = or(UInt<1>(0h0), _T_1579) node _T_1581 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1582 = cvt(_T_1581) node _T_1583 = and(_T_1582, asSInt(UInt<17>(0h10000))) node _T_1584 = asSInt(_T_1583) node _T_1585 = eq(_T_1584, asSInt(UInt<1>(0h0))) node _T_1586 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1587 = cvt(_T_1586) node _T_1588 = and(_T_1587, asSInt(UInt<29>(0h10000000))) node _T_1589 = asSInt(_T_1588) node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0))) node _T_1591 = or(_T_1585, _T_1590) node _T_1592 = and(_T_1580, _T_1591) node _T_1593 = or(UInt<1>(0h0), _T_1592) node _T_1594 = and(UInt<1>(0h0), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_118 node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(address_ok, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(legal_source, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1607 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_122 node _T_1611 = eq(io.in.b.bits.mask, mask_1) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_123 node _T_1615 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1615 : node _T_1616 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1617 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1618 = and(_T_1616, _T_1617) node _T_1619 = or(UInt<1>(0h0), _T_1618) node _T_1620 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1621 = cvt(_T_1620) node _T_1622 = and(_T_1621, asSInt(UInt<17>(0h10000))) node _T_1623 = asSInt(_T_1622) node _T_1624 = eq(_T_1623, asSInt(UInt<1>(0h0))) node _T_1625 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1626 = cvt(_T_1625) node _T_1627 = and(_T_1626, asSInt(UInt<29>(0h10000000))) node _T_1628 = asSInt(_T_1627) node _T_1629 = eq(_T_1628, asSInt(UInt<1>(0h0))) node _T_1630 = or(_T_1624, _T_1629) node _T_1631 = and(_T_1619, _T_1630) node _T_1632 = or(UInt<1>(0h0), _T_1631) node _T_1633 = and(UInt<1>(0h0), _T_1632) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_124 node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(address_ok, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(legal_source, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1646 = eq(io.in.b.bits.mask, mask_1) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_128 node _T_1650 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1654 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_130 node _source_ok_T_88 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_89 = shr(io.in.c.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<1>(0h0)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_95 = shr(io.in.c.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<1>(0h1)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_101 = shr(io.in.c.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<2>(0h2)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_107 = shr(io.in.c.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<2>(0h3)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_114 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_115 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_116 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_118 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_2 : UInt<1>[13] connect _source_ok_WIRE_2[0], _source_ok_T_88 connect _source_ok_WIRE_2[1], _source_ok_T_94 connect _source_ok_WIRE_2[2], _source_ok_T_100 connect _source_ok_WIRE_2[3], _source_ok_T_106 connect _source_ok_WIRE_2[4], _source_ok_T_112 connect _source_ok_WIRE_2[5], _source_ok_T_113 connect _source_ok_WIRE_2[6], _source_ok_T_114 connect _source_ok_WIRE_2[7], _source_ok_T_115 connect _source_ok_WIRE_2[8], _source_ok_T_116 connect _source_ok_WIRE_2[9], _source_ok_T_117 connect _source_ok_WIRE_2[10], _source_ok_T_118 connect _source_ok_WIRE_2[11], _source_ok_T_119 connect _source_ok_WIRE_2[12], _source_ok_T_120 node _source_ok_T_121 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_2[2]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_2[3]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_2[4]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_2[5]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_2[6]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_2[7]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_2[8]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_2[9]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_2[10]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_2[11]) node source_ok_2 = or(_source_ok_T_131, _source_ok_WIRE_2[12]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1658 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) node _T_1660 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = or(_T_1659, _T_1664) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1666 = shr(io.in.c.bits.source, 2) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) node _T_1668 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1669 = and(_T_1667, _T_1668) node _T_1670 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) node _T_1673 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1674 = cvt(_T_1673) node _T_1675 = and(_T_1674, asSInt(UInt<1>(0h0))) node _T_1676 = asSInt(_T_1675) node _T_1677 = eq(_T_1676, asSInt(UInt<1>(0h0))) node _T_1678 = or(_T_1672, _T_1677) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1679 = shr(io.in.c.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<1>(0h1)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) node _T_1686 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1687 = cvt(_T_1686) node _T_1688 = and(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = asSInt(_T_1688) node _T_1690 = eq(_T_1689, asSInt(UInt<1>(0h0))) node _T_1691 = or(_T_1685, _T_1690) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1692 = shr(io.in.c.bits.source, 2) node _T_1693 = eq(_T_1692, UInt<2>(0h2)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1697 = and(_T_1695, _T_1696) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) node _T_1699 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = or(_T_1698, _T_1703) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1705 = shr(io.in.c.bits.source, 2) node _T_1706 = eq(_T_1705, UInt<2>(0h3)) node _T_1707 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1710 = and(_T_1708, _T_1709) node _T_1711 = eq(_T_1710, UInt<1>(0h0)) node _T_1712 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1713 = cvt(_T_1712) node _T_1714 = and(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = asSInt(_T_1714) node _T_1716 = eq(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = or(_T_1711, _T_1716) node _T_1718 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) node _T_1720 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = or(_T_1719, _T_1724) node _T_1726 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) node _T_1728 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<1>(0h0))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = or(_T_1727, _T_1732) node _T_1734 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) node _T_1736 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1737 = cvt(_T_1736) node _T_1738 = and(_T_1737, asSInt(UInt<1>(0h0))) node _T_1739 = asSInt(_T_1738) node _T_1740 = eq(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = or(_T_1735, _T_1740) node _T_1742 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) node _T_1744 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = or(_T_1743, _T_1748) node _T_1750 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) node _T_1752 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1751, _T_1756) node _T_1758 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1761 = cvt(_T_1760) node _T_1762 = and(_T_1761, asSInt(UInt<1>(0h0))) node _T_1763 = asSInt(_T_1762) node _T_1764 = eq(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = or(_T_1759, _T_1764) node _T_1766 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1769 = cvt(_T_1768) node _T_1770 = and(_T_1769, asSInt(UInt<1>(0h0))) node _T_1771 = asSInt(_T_1770) node _T_1772 = eq(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = or(_T_1767, _T_1772) node _T_1774 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) node _T_1776 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = or(_T_1775, _T_1780) node _T_1782 = and(_T_1665, _T_1678) node _T_1783 = and(_T_1782, _T_1691) node _T_1784 = and(_T_1783, _T_1704) node _T_1785 = and(_T_1784, _T_1717) node _T_1786 = and(_T_1785, _T_1725) node _T_1787 = and(_T_1786, _T_1733) node _T_1788 = and(_T_1787, _T_1741) node _T_1789 = and(_T_1788, _T_1749) node _T_1790 = and(_T_1789, _T_1757) node _T_1791 = and(_T_1790, _T_1765) node _T_1792 = and(_T_1791, _T_1773) node _T_1793 = and(_T_1792, _T_1781) node _T_1794 = asUInt(reset) node _T_1795 = eq(_T_1794, UInt<1>(0h0)) when _T_1795 : node _T_1796 = eq(_T_1793, UInt<1>(0h0)) when _T_1796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1793, UInt<1>(0h1), "") : assert_131 node _T_1797 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1797 : node _T_1798 = asUInt(reset) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) when _T_1799 : node _T_1800 = eq(address_ok_1, UInt<1>(0h0)) when _T_1800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(source_ok_2, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1804 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1805 = asUInt(reset) node _T_1806 = eq(_T_1805, UInt<1>(0h0)) when _T_1806 : node _T_1807 = eq(_T_1804, UInt<1>(0h0)) when _T_1807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1804, UInt<1>(0h1), "") : assert_134 node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1811 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_136 node _T_1815 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_137 node _T_1819 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1819 : node _T_1820 = asUInt(reset) node _T_1821 = eq(_T_1820, UInt<1>(0h0)) when _T_1821 : node _T_1822 = eq(address_ok_1, UInt<1>(0h0)) when _T_1822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(source_ok_2, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1826 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1827 = asUInt(reset) node _T_1828 = eq(_T_1827, UInt<1>(0h0)) when _T_1828 : node _T_1829 = eq(_T_1826, UInt<1>(0h0)) when _T_1829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1826, UInt<1>(0h1), "") : assert_140 node _T_1830 = asUInt(reset) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) when _T_1831 : node _T_1832 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1832 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1833 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_142 node _T_1837 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1837 : node _T_1838 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1839 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1840 = and(_T_1838, _T_1839) node _T_1841 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1842 = shr(io.in.c.bits.source, 2) node _T_1843 = eq(_T_1842, UInt<1>(0h0)) node _T_1844 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1845 = and(_T_1843, _T_1844) node _T_1846 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1847 = and(_T_1845, _T_1846) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1848 = shr(io.in.c.bits.source, 2) node _T_1849 = eq(_T_1848, UInt<1>(0h1)) node _T_1850 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1851 = and(_T_1849, _T_1850) node _T_1852 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1853 = and(_T_1851, _T_1852) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1854 = shr(io.in.c.bits.source, 2) node _T_1855 = eq(_T_1854, UInt<2>(0h2)) node _T_1856 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1857 = and(_T_1855, _T_1856) node _T_1858 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1860 = shr(io.in.c.bits.source, 2) node _T_1861 = eq(_T_1860, UInt<2>(0h3)) node _T_1862 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1863 = and(_T_1861, _T_1862) node _T_1864 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1867 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1868 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1869 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1870 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1871 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1872 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1873 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1874 = or(_T_1841, _T_1847) node _T_1875 = or(_T_1874, _T_1853) node _T_1876 = or(_T_1875, _T_1859) node _T_1877 = or(_T_1876, _T_1865) node _T_1878 = or(_T_1877, _T_1866) node _T_1879 = or(_T_1878, _T_1867) node _T_1880 = or(_T_1879, _T_1868) node _T_1881 = or(_T_1880, _T_1869) node _T_1882 = or(_T_1881, _T_1870) node _T_1883 = or(_T_1882, _T_1871) node _T_1884 = or(_T_1883, _T_1872) node _T_1885 = or(_T_1884, _T_1873) node _T_1886 = and(_T_1840, _T_1885) node _T_1887 = or(UInt<1>(0h0), _T_1886) node _T_1888 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1889 = or(UInt<1>(0h0), _T_1888) node _T_1890 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1891 = cvt(_T_1890) node _T_1892 = and(_T_1891, asSInt(UInt<17>(0h10000))) node _T_1893 = asSInt(_T_1892) node _T_1894 = eq(_T_1893, asSInt(UInt<1>(0h0))) node _T_1895 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1896 = cvt(_T_1895) node _T_1897 = and(_T_1896, asSInt(UInt<29>(0h10000000))) node _T_1898 = asSInt(_T_1897) node _T_1899 = eq(_T_1898, asSInt(UInt<1>(0h0))) node _T_1900 = or(_T_1894, _T_1899) node _T_1901 = and(_T_1889, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = and(_T_1887, _T_1902) node _T_1904 = asUInt(reset) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) when _T_1905 : node _T_1906 = eq(_T_1903, UInt<1>(0h0)) when _T_1906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1903, UInt<1>(0h1), "") : assert_143 node _T_1907 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1908 = shr(io.in.c.bits.source, 2) node _T_1909 = eq(_T_1908, UInt<1>(0h0)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1914 = shr(io.in.c.bits.source, 2) node _T_1915 = eq(_T_1914, UInt<1>(0h1)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1920 = shr(io.in.c.bits.source, 2) node _T_1921 = eq(_T_1920, UInt<2>(0h2)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1925 = and(_T_1923, _T_1924) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1926 = shr(io.in.c.bits.source, 2) node _T_1927 = eq(_T_1926, UInt<2>(0h3)) node _T_1928 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1929 = and(_T_1927, _T_1928) node _T_1930 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1931 = and(_T_1929, _T_1930) node _T_1932 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1933 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1934 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1935 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1936 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1937 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1938 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1939 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _WIRE_6 : UInt<1>[13] connect _WIRE_6[0], _T_1907 connect _WIRE_6[1], _T_1913 connect _WIRE_6[2], _T_1919 connect _WIRE_6[3], _T_1925 connect _WIRE_6[4], _T_1931 connect _WIRE_6[5], _T_1932 connect _WIRE_6[6], _T_1933 connect _WIRE_6[7], _T_1934 connect _WIRE_6[8], _T_1935 connect _WIRE_6[9], _T_1936 connect _WIRE_6[10], _T_1937 connect _WIRE_6[11], _T_1938 connect _WIRE_6[12], _T_1939 node _T_1940 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1941 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1942 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1943 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1944 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1945 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1946 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1947 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1948 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1949 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1950 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1951 = mux(_WIRE_6[5], _T_1940, UInt<1>(0h0)) node _T_1952 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1953 = mux(_WIRE_6[7], _T_1941, UInt<1>(0h0)) node _T_1954 = mux(_WIRE_6[8], _T_1942, UInt<1>(0h0)) node _T_1955 = mux(_WIRE_6[9], _T_1943, UInt<1>(0h0)) node _T_1956 = mux(_WIRE_6[10], _T_1944, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[12], _T_1945, UInt<1>(0h0)) node _T_1959 = or(_T_1946, _T_1947) node _T_1960 = or(_T_1959, _T_1948) node _T_1961 = or(_T_1960, _T_1949) node _T_1962 = or(_T_1961, _T_1950) node _T_1963 = or(_T_1962, _T_1951) node _T_1964 = or(_T_1963, _T_1952) node _T_1965 = or(_T_1964, _T_1953) node _T_1966 = or(_T_1965, _T_1954) node _T_1967 = or(_T_1966, _T_1955) node _T_1968 = or(_T_1967, _T_1956) node _T_1969 = or(_T_1968, _T_1957) node _T_1970 = or(_T_1969, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1970 node _T_1971 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1972 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1973 = and(_T_1971, _T_1972) node _T_1974 = or(UInt<1>(0h0), _T_1973) node _T_1975 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<29>(0h10000000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = or(_T_1979, _T_1984) node _T_1986 = and(_T_1974, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = and(_WIRE_7, _T_1987) node _T_1989 = asUInt(reset) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) when _T_1990 : node _T_1991 = eq(_T_1988, UInt<1>(0h0)) when _T_1991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1988, UInt<1>(0h1), "") : assert_144 node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(source_ok_2, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1995 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_146 node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2002 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_148 node _T_2006 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_149 node _T_2010 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2010 : node _T_2011 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2012 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2013 = and(_T_2011, _T_2012) node _T_2014 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2015 = shr(io.in.c.bits.source, 2) node _T_2016 = eq(_T_2015, UInt<1>(0h0)) node _T_2017 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2018 = and(_T_2016, _T_2017) node _T_2019 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2020 = and(_T_2018, _T_2019) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2021 = shr(io.in.c.bits.source, 2) node _T_2022 = eq(_T_2021, UInt<1>(0h1)) node _T_2023 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2024 = and(_T_2022, _T_2023) node _T_2025 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2026 = and(_T_2024, _T_2025) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2027 = shr(io.in.c.bits.source, 2) node _T_2028 = eq(_T_2027, UInt<2>(0h2)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2032 = and(_T_2030, _T_2031) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2033 = shr(io.in.c.bits.source, 2) node _T_2034 = eq(_T_2033, UInt<2>(0h3)) node _T_2035 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2036 = and(_T_2034, _T_2035) node _T_2037 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2038 = and(_T_2036, _T_2037) node _T_2039 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2040 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2041 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2042 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2043 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2044 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2045 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2046 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2047 = or(_T_2014, _T_2020) node _T_2048 = or(_T_2047, _T_2026) node _T_2049 = or(_T_2048, _T_2032) node _T_2050 = or(_T_2049, _T_2038) node _T_2051 = or(_T_2050, _T_2039) node _T_2052 = or(_T_2051, _T_2040) node _T_2053 = or(_T_2052, _T_2041) node _T_2054 = or(_T_2053, _T_2042) node _T_2055 = or(_T_2054, _T_2043) node _T_2056 = or(_T_2055, _T_2044) node _T_2057 = or(_T_2056, _T_2045) node _T_2058 = or(_T_2057, _T_2046) node _T_2059 = and(_T_2013, _T_2058) node _T_2060 = or(UInt<1>(0h0), _T_2059) node _T_2061 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2062 = or(UInt<1>(0h0), _T_2061) node _T_2063 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2064 = cvt(_T_2063) node _T_2065 = and(_T_2064, asSInt(UInt<17>(0h10000))) node _T_2066 = asSInt(_T_2065) node _T_2067 = eq(_T_2066, asSInt(UInt<1>(0h0))) node _T_2068 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2069 = cvt(_T_2068) node _T_2070 = and(_T_2069, asSInt(UInt<29>(0h10000000))) node _T_2071 = asSInt(_T_2070) node _T_2072 = eq(_T_2071, asSInt(UInt<1>(0h0))) node _T_2073 = or(_T_2067, _T_2072) node _T_2074 = and(_T_2062, _T_2073) node _T_2075 = or(UInt<1>(0h0), _T_2074) node _T_2076 = and(_T_2060, _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_150 node _T_2080 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2081 = shr(io.in.c.bits.source, 2) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) node _T_2083 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2084 = and(_T_2082, _T_2083) node _T_2085 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2086 = and(_T_2084, _T_2085) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2087 = shr(io.in.c.bits.source, 2) node _T_2088 = eq(_T_2087, UInt<1>(0h1)) node _T_2089 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2090 = and(_T_2088, _T_2089) node _T_2091 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2092 = and(_T_2090, _T_2091) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2093 = shr(io.in.c.bits.source, 2) node _T_2094 = eq(_T_2093, UInt<2>(0h2)) node _T_2095 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2098 = and(_T_2096, _T_2097) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2099 = shr(io.in.c.bits.source, 2) node _T_2100 = eq(_T_2099, UInt<2>(0h3)) node _T_2101 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2102 = and(_T_2100, _T_2101) node _T_2103 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2104 = and(_T_2102, _T_2103) node _T_2105 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2106 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2107 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2109 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2110 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2111 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2112 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _WIRE_8 : UInt<1>[13] connect _WIRE_8[0], _T_2080 connect _WIRE_8[1], _T_2086 connect _WIRE_8[2], _T_2092 connect _WIRE_8[3], _T_2098 connect _WIRE_8[4], _T_2104 connect _WIRE_8[5], _T_2105 connect _WIRE_8[6], _T_2106 connect _WIRE_8[7], _T_2107 connect _WIRE_8[8], _T_2108 connect _WIRE_8[9], _T_2109 connect _WIRE_8[10], _T_2110 connect _WIRE_8[11], _T_2111 connect _WIRE_8[12], _T_2112 node _T_2113 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2114 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2115 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2116 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2117 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2118 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2119 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2120 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2121 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2122 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2123 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2124 = mux(_WIRE_8[5], _T_2113, UInt<1>(0h0)) node _T_2125 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2126 = mux(_WIRE_8[7], _T_2114, UInt<1>(0h0)) node _T_2127 = mux(_WIRE_8[8], _T_2115, UInt<1>(0h0)) node _T_2128 = mux(_WIRE_8[9], _T_2116, UInt<1>(0h0)) node _T_2129 = mux(_WIRE_8[10], _T_2117, UInt<1>(0h0)) node _T_2130 = mux(_WIRE_8[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_2131 = mux(_WIRE_8[12], _T_2118, UInt<1>(0h0)) node _T_2132 = or(_T_2119, _T_2120) node _T_2133 = or(_T_2132, _T_2121) node _T_2134 = or(_T_2133, _T_2122) node _T_2135 = or(_T_2134, _T_2123) node _T_2136 = or(_T_2135, _T_2124) node _T_2137 = or(_T_2136, _T_2125) node _T_2138 = or(_T_2137, _T_2126) node _T_2139 = or(_T_2138, _T_2127) node _T_2140 = or(_T_2139, _T_2128) node _T_2141 = or(_T_2140, _T_2129) node _T_2142 = or(_T_2141, _T_2130) node _T_2143 = or(_T_2142, _T_2131) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2143 node _T_2144 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2145 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2146 = and(_T_2144, _T_2145) node _T_2147 = or(UInt<1>(0h0), _T_2146) node _T_2148 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2149 = cvt(_T_2148) node _T_2150 = and(_T_2149, asSInt(UInt<17>(0h10000))) node _T_2151 = asSInt(_T_2150) node _T_2152 = eq(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2154 = cvt(_T_2153) node _T_2155 = and(_T_2154, asSInt(UInt<29>(0h10000000))) node _T_2156 = asSInt(_T_2155) node _T_2157 = eq(_T_2156, asSInt(UInt<1>(0h0))) node _T_2158 = or(_T_2152, _T_2157) node _T_2159 = and(_T_2147, _T_2158) node _T_2160 = or(UInt<1>(0h0), _T_2159) node _T_2161 = and(_WIRE_9, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_151 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(source_ok_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2168 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_153 node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2175 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_155 node _T_2179 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2179 : node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(address_ok_1, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(source_ok_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2186 = asUInt(reset) node _T_2187 = eq(_T_2186, UInt<1>(0h0)) when _T_2187 : node _T_2188 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2189 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2190 = asUInt(reset) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) when _T_2191 : node _T_2192 = eq(_T_2189, UInt<1>(0h0)) when _T_2192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2189, UInt<1>(0h1), "") : assert_159 node _T_2193 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(_T_2193, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2193, UInt<1>(0h1), "") : assert_160 node _T_2197 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2197 : node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(address_ok_1, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(source_ok_2, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2207 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_164 node _T_2211 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2211 : node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(address_ok_1, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2215 = asUInt(reset) node _T_2216 = eq(_T_2215, UInt<1>(0h0)) when _T_2216 : node _T_2217 = eq(source_ok_2, UInt<1>(0h0)) when _T_2217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2221 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_168 node _T_2225 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2229 = asUInt(reset) node _T_2230 = eq(_T_2229, UInt<1>(0h0)) when _T_2230 : node _T_2231 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2232 = eq(a_first, UInt<1>(0h0)) node _T_2233 = and(io.in.a.valid, _T_2232) when _T_2233 : node _T_2234 = eq(io.in.a.bits.opcode, opcode) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_171 node _T_2238 = eq(io.in.a.bits.param, param) node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(_T_2238, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2238, UInt<1>(0h1), "") : assert_172 node _T_2242 = eq(io.in.a.bits.size, size) node _T_2243 = asUInt(reset) node _T_2244 = eq(_T_2243, UInt<1>(0h0)) when _T_2244 : node _T_2245 = eq(_T_2242, UInt<1>(0h0)) when _T_2245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2242, UInt<1>(0h1), "") : assert_173 node _T_2246 = eq(io.in.a.bits.source, source) node _T_2247 = asUInt(reset) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) when _T_2248 : node _T_2249 = eq(_T_2246, UInt<1>(0h0)) when _T_2249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2246, UInt<1>(0h1), "") : assert_174 node _T_2250 = eq(io.in.a.bits.address, address) node _T_2251 = asUInt(reset) node _T_2252 = eq(_T_2251, UInt<1>(0h0)) when _T_2252 : node _T_2253 = eq(_T_2250, UInt<1>(0h0)) when _T_2253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2250, UInt<1>(0h1), "") : assert_175 node _T_2254 = and(io.in.a.ready, io.in.a.valid) node _T_2255 = and(_T_2254, a_first) when _T_2255 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2256 = eq(d_first, UInt<1>(0h0)) node _T_2257 = and(io.in.d.valid, _T_2256) when _T_2257 : node _T_2258 = eq(io.in.d.bits.opcode, opcode_1) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_176 node _T_2262 = eq(io.in.d.bits.param, param_1) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_177 node _T_2266 = eq(io.in.d.bits.size, size_1) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_178 node _T_2270 = eq(io.in.d.bits.source, source_1) node _T_2271 = asUInt(reset) node _T_2272 = eq(_T_2271, UInt<1>(0h0)) when _T_2272 : node _T_2273 = eq(_T_2270, UInt<1>(0h0)) when _T_2273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2270, UInt<1>(0h1), "") : assert_179 node _T_2274 = eq(io.in.d.bits.sink, sink) node _T_2275 = asUInt(reset) node _T_2276 = eq(_T_2275, UInt<1>(0h0)) when _T_2276 : node _T_2277 = eq(_T_2274, UInt<1>(0h0)) when _T_2277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2274, UInt<1>(0h1), "") : assert_180 node _T_2278 = eq(io.in.d.bits.denied, denied) node _T_2279 = asUInt(reset) node _T_2280 = eq(_T_2279, UInt<1>(0h0)) when _T_2280 : node _T_2281 = eq(_T_2278, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2278, UInt<1>(0h1), "") : assert_181 node _T_2282 = and(io.in.d.ready, io.in.d.valid) node _T_2283 = and(_T_2282, d_first) when _T_2283 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2284 = eq(b_first, UInt<1>(0h0)) node _T_2285 = and(io.in.b.valid, _T_2284) when _T_2285 : node _T_2286 = eq(io.in.b.bits.opcode, opcode_2) node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(_T_2286, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2286, UInt<1>(0h1), "") : assert_182 node _T_2290 = eq(io.in.b.bits.param, param_2) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_183 node _T_2294 = eq(io.in.b.bits.size, size_2) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_184 node _T_2298 = eq(io.in.b.bits.source, source_2) node _T_2299 = asUInt(reset) node _T_2300 = eq(_T_2299, UInt<1>(0h0)) when _T_2300 : node _T_2301 = eq(_T_2298, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2298, UInt<1>(0h1), "") : assert_185 node _T_2302 = eq(io.in.b.bits.address, address_1) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_186 node _T_2306 = and(io.in.b.ready, io.in.b.valid) node _T_2307 = and(_T_2306, b_first) when _T_2307 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2308 = eq(c_first, UInt<1>(0h0)) node _T_2309 = and(io.in.c.valid, _T_2308) when _T_2309 : node _T_2310 = eq(io.in.c.bits.opcode, opcode_3) node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(_T_2310, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2310, UInt<1>(0h1), "") : assert_187 node _T_2314 = eq(io.in.c.bits.param, param_3) node _T_2315 = asUInt(reset) node _T_2316 = eq(_T_2315, UInt<1>(0h0)) when _T_2316 : node _T_2317 = eq(_T_2314, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2314, UInt<1>(0h1), "") : assert_188 node _T_2318 = eq(io.in.c.bits.size, size_3) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_189 node _T_2322 = eq(io.in.c.bits.source, source_3) node _T_2323 = asUInt(reset) node _T_2324 = eq(_T_2323, UInt<1>(0h0)) when _T_2324 : node _T_2325 = eq(_T_2322, UInt<1>(0h0)) when _T_2325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2322, UInt<1>(0h1), "") : assert_190 node _T_2326 = eq(io.in.c.bits.address, address_2) node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(_T_2326, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2326, UInt<1>(0h1), "") : assert_191 node _T_2330 = and(io.in.c.ready, io.in.c.valid) node _T_2331 = and(_T_2330, c_first) when _T_2331 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes : UInt<188>, clock, reset, UInt<188>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<47> connect a_set, UInt<47>(0h0) wire a_set_wo_ready : UInt<47> connect a_set_wo_ready, UInt<47>(0h0) wire a_opcodes_set : UInt<188> connect a_opcodes_set, UInt<188>(0h0) wire a_sizes_set : UInt<188> connect a_sizes_set, UInt<188>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2332 = and(io.in.a.valid, a_first_1) node _T_2333 = and(_T_2332, UInt<1>(0h1)) when _T_2333 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2334 = and(io.in.a.ready, io.in.a.valid) node _T_2335 = and(_T_2334, a_first_1) node _T_2336 = and(_T_2335, UInt<1>(0h1)) when _T_2336 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2337 = dshr(inflight, io.in.a.bits.source) node _T_2338 = bits(_T_2337, 0, 0) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<47> connect d_clr, UInt<47>(0h0) wire d_clr_wo_ready : UInt<47> connect d_clr_wo_ready, UInt<47>(0h0) wire d_opcodes_clr : UInt<188> connect d_opcodes_clr, UInt<188>(0h0) wire d_sizes_clr : UInt<188> connect d_sizes_clr, UInt<188>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2343 = and(io.in.d.valid, d_first_1) node _T_2344 = and(_T_2343, UInt<1>(0h1)) node _T_2345 = eq(d_release_ack, UInt<1>(0h0)) node _T_2346 = and(_T_2344, _T_2345) when _T_2346 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2347 = and(io.in.d.ready, io.in.d.valid) node _T_2348 = and(_T_2347, d_first_1) node _T_2349 = and(_T_2348, UInt<1>(0h1)) node _T_2350 = eq(d_release_ack, UInt<1>(0h0)) node _T_2351 = and(_T_2349, _T_2350) when _T_2351 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2352 = and(io.in.d.valid, d_first_1) node _T_2353 = and(_T_2352, UInt<1>(0h1)) node _T_2354 = eq(d_release_ack, UInt<1>(0h0)) node _T_2355 = and(_T_2353, _T_2354) when _T_2355 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2356 = dshr(inflight, io.in.d.bits.source) node _T_2357 = bits(_T_2356, 0, 0) node _T_2358 = or(_T_2357, same_cycle_resp) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2362 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2363 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2364 = or(_T_2362, _T_2363) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_194 node _T_2368 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_195 else : node _T_2372 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2373 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2374 = or(_T_2372, _T_2373) node _T_2375 = asUInt(reset) node _T_2376 = eq(_T_2375, UInt<1>(0h0)) when _T_2376 : node _T_2377 = eq(_T_2374, UInt<1>(0h0)) when _T_2377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2374, UInt<1>(0h1), "") : assert_196 node _T_2378 = eq(io.in.d.bits.size, a_size_lookup) node _T_2379 = asUInt(reset) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) when _T_2380 : node _T_2381 = eq(_T_2378, UInt<1>(0h0)) when _T_2381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2378, UInt<1>(0h1), "") : assert_197 node _T_2382 = and(io.in.d.valid, d_first_1) node _T_2383 = and(_T_2382, a_first_1) node _T_2384 = and(_T_2383, io.in.a.valid) node _T_2385 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2386 = and(_T_2384, _T_2385) node _T_2387 = eq(d_release_ack, UInt<1>(0h0)) node _T_2388 = and(_T_2386, _T_2387) when _T_2388 : node _T_2389 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2390 = or(_T_2389, io.in.a.ready) node _T_2391 = asUInt(reset) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) when _T_2392 : node _T_2393 = eq(_T_2390, UInt<1>(0h0)) when _T_2393 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2390, UInt<1>(0h1), "") : assert_198 node _T_2394 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2395 = orr(a_set_wo_ready) node _T_2396 = eq(_T_2395, UInt<1>(0h0)) node _T_2397 = or(_T_2394, _T_2396) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_100 node _T_2401 = orr(inflight) node _T_2402 = eq(_T_2401, UInt<1>(0h0)) node _T_2403 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2404 = or(_T_2402, _T_2403) node _T_2405 = lt(watchdog, plusarg_reader.out) node _T_2406 = or(_T_2404, _T_2405) node _T_2407 = asUInt(reset) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) when _T_2408 : node _T_2409 = eq(_T_2406, UInt<1>(0h0)) when _T_2409 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2406, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2410 = and(io.in.a.ready, io.in.a.valid) node _T_2411 = and(io.in.d.ready, io.in.d.valid) node _T_2412 = or(_T_2410, _T_2411) when _T_2412 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes_1 : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes_1 : UInt<188>, clock, reset, UInt<188>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<47> connect c_set, UInt<47>(0h0) wire c_set_wo_ready : UInt<47> connect c_set_wo_ready, UInt<47>(0h0) wire c_opcodes_set : UInt<188> connect c_opcodes_set, UInt<188>(0h0) wire c_sizes_set : UInt<188> connect c_sizes_set, UInt<188>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2413 = and(io.in.c.valid, c_first_1) node _T_2414 = bits(io.in.c.bits.opcode, 2, 2) node _T_2415 = bits(io.in.c.bits.opcode, 1, 1) node _T_2416 = and(_T_2414, _T_2415) node _T_2417 = and(_T_2413, _T_2416) when _T_2417 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2418 = and(io.in.c.ready, io.in.c.valid) node _T_2419 = and(_T_2418, c_first_1) node _T_2420 = bits(io.in.c.bits.opcode, 2, 2) node _T_2421 = bits(io.in.c.bits.opcode, 1, 1) node _T_2422 = and(_T_2420, _T_2421) node _T_2423 = and(_T_2419, _T_2422) when _T_2423 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2424 = dshr(inflight_1, io.in.c.bits.source) node _T_2425 = bits(_T_2424, 0, 0) node _T_2426 = eq(_T_2425, UInt<1>(0h0)) node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(_T_2426, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2426, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<47> connect d_clr_1, UInt<47>(0h0) wire d_clr_wo_ready_1 : UInt<47> connect d_clr_wo_ready_1, UInt<47>(0h0) wire d_opcodes_clr_1 : UInt<188> connect d_opcodes_clr_1, UInt<188>(0h0) wire d_sizes_clr_1 : UInt<188> connect d_sizes_clr_1, UInt<188>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2430 = and(io.in.d.valid, d_first_2) node _T_2431 = and(_T_2430, UInt<1>(0h1)) node _T_2432 = and(_T_2431, d_release_ack_1) when _T_2432 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2433 = and(io.in.d.ready, io.in.d.valid) node _T_2434 = and(_T_2433, d_first_2) node _T_2435 = and(_T_2434, UInt<1>(0h1)) node _T_2436 = and(_T_2435, d_release_ack_1) when _T_2436 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2437 = and(io.in.d.valid, d_first_2) node _T_2438 = and(_T_2437, UInt<1>(0h1)) node _T_2439 = and(_T_2438, d_release_ack_1) when _T_2439 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2440 = dshr(inflight_1, io.in.d.bits.source) node _T_2441 = bits(_T_2440, 0, 0) node _T_2442 = or(_T_2441, same_cycle_resp_1) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2446 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_203 else : node _T_2450 = eq(io.in.d.bits.size, c_size_lookup) node _T_2451 = asUInt(reset) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) when _T_2452 : node _T_2453 = eq(_T_2450, UInt<1>(0h0)) when _T_2453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2450, UInt<1>(0h1), "") : assert_204 node _T_2454 = and(io.in.d.valid, d_first_2) node _T_2455 = and(_T_2454, c_first_1) node _T_2456 = and(_T_2455, io.in.c.valid) node _T_2457 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2458 = and(_T_2456, _T_2457) node _T_2459 = and(_T_2458, d_release_ack_1) node _T_2460 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2461 = and(_T_2459, _T_2460) when _T_2461 : node _T_2462 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2463 = or(_T_2462, io.in.c.ready) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_205 node _T_2467 = orr(c_set_wo_ready) when _T_2467 : node _T_2468 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_101 node _T_2472 = orr(inflight_1) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) node _T_2474 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = lt(watchdog_1, plusarg_reader_1.out) node _T_2477 = or(_T_2475, _T_2476) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2481 = and(io.in.c.ready, io.in.c.valid) node _T_2482 = and(io.in.d.ready, io.in.d.valid) node _T_2483 = or(_T_2481, _T_2482) when _T_2483 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2484 = and(io.in.d.ready, io.in.d.valid) node _T_2485 = and(_T_2484, d_first_3) node _T_2486 = bits(io.in.d.bits.opcode, 2, 2) node _T_2487 = bits(io.in.d.bits.opcode, 1, 1) node _T_2488 = eq(_T_2487, UInt<1>(0h0)) node _T_2489 = and(_T_2486, _T_2488) node _T_2490 = and(_T_2485, _T_2489) when _T_2490 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2491 = dshr(inflight_2, io.in.d.bits.sink) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) node _T_2494 = asUInt(reset) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) when _T_2495 : node _T_2496 = eq(_T_2493, UInt<1>(0h0)) when _T_2496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2493, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2497 = and(io.in.e.ready, io.in.e.valid) node _T_2498 = and(_T_2497, UInt<1>(0h1)) node _T_2499 = and(_T_2498, UInt<1>(0h1)) when _T_2499 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2500 = or(d_set, inflight_2) node _T_2501 = dshr(_T_2500, io.in.e.bits.sink) node _T_2502 = bits(_T_2501, 0, 0) node _T_2503 = asUInt(reset) node _T_2504 = eq(_T_2503, UInt<1>(0h0)) when _T_2504 : node _T_2505 = eq(_T_2502, UInt<1>(0h0)) when _T_2505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2502, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8	module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [5:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_91 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_2 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_3 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_43 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_57 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_63 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_46 = _source_ok_T_45 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_86 = _source_ok_T_85 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_87 = _source_ok_T_86 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_87 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire _legal_source_T = io_in_b_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _legal_source_T_1 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_7 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_13 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_19 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_25 = io_in_b_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _legal_source_T_26 = io_in_b_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _legal_source_T_27 = io_in_b_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _legal_source_T_28 = io_in_b_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _legal_source_T_29 = io_in_b_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _legal_source_T_30 = io_in_b_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _legal_source_T_31 = io_in_b_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _legal_source_T_32 = io_in_b_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_2 = _legal_source_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_8 = _legal_source_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_10 = _legal_source_T_8; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_12 = _legal_source_T_10; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_2 = _legal_source_T_12; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_2 = _legal_source_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_14 = _legal_source_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_16 = _legal_source_T_14; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_18 = _legal_source_T_16; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_3 = _legal_source_T_18; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_3 = _legal_source_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_20 = _legal_source_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_22 = _legal_source_T_20; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_24 = _legal_source_T_22; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_4 = _legal_source_T_24; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = _legal_source_T_25; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = _legal_source_T_26; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = _legal_source_T_27; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = _legal_source_T_28; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_9 = _legal_source_T_29; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_10 = _legal_source_T_30; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_11 = _legal_source_T_31; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_12 = _legal_source_T_32; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_33 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_46 = _legal_source_T_33; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_35 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = {_legal_source_WIRE_3, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = _legal_source_WIRE_4 ? 4'hC : 4'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_38 = _legal_source_WIRE_5 ? 6'h24 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_39 = _legal_source_WIRE_6 ? 6'h26 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = _legal_source_WIRE_7 ? 6'h2E : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_41 = _legal_source_WIRE_8 ? 6'h2C : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_42 = _legal_source_WIRE_9 ? 6'h2A : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_43 = _legal_source_WIRE_10 ? 6'h28 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = _legal_source_WIRE_11 ? 6'h22 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = {_legal_source_WIRE_12, 5'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_47 = {_legal_source_T_46[4:3], _legal_source_T_46[2:0] \| _legal_source_T_35}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_48 = {_legal_source_T_47[4], _legal_source_T_47[3:0] \| _legal_source_T_36}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_49 = {_legal_source_T_48[4], _legal_source_T_48[3:0] \| _legal_source_T_37}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_50 = {1'h0, _legal_source_T_49} \| _legal_source_T_38; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_51 = _legal_source_T_50 \| _legal_source_T_39; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_52 = _legal_source_T_51 \| _legal_source_T_40; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_53 = _legal_source_T_52 \| _legal_source_T_41; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_54 = _legal_source_T_53 \| _legal_source_T_42; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_55 = _legal_source_T_54 \| _legal_source_T_43; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_56 = _legal_source_T_55 \| _legal_source_T_44; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_57 = _legal_source_T_56 \| _legal_source_T_45; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1_0 = _legal_source_T_57; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_88 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_89 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_95 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_101 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_107 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_90 = _source_ok_T_89 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_92 = _source_ok_T_90; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_96 = _source_ok_T_95 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_102 = _source_ok_T_101 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_108 = _source_ok_T_107 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_c_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_5 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_c_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_c_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_c_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_8 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_9 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_10 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_c_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_11 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_c_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_12 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 \| _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 \| _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 \| _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 \| _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 \| _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 \| _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_128 = _source_ok_T_127 \| _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 \| _source_ok_WIRE_2_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 \| _source_ok_WIRE_2_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 \| _source_ok_WIRE_2_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_131 \| _source_ok_WIRE_2_12; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_2410 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2410; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2410; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2484; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2481 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2481; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2481; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [46:0] inflight; // @[Monitor.scala:614:27] reg [187:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [187:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [46:0] a_set; // @[Monitor.scala:626:34] wire [46:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [187:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [187:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [187:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [187:0] _a_opcode_lookup_T_6 = {184'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [187:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[187:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [187:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [187:0] _a_size_lookup_T_6 = {184'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [187:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[187:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2336 = _T_2410 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2336 ? _a_set_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2336 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2336 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2336 ? _a_opcodes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2336 ? _a_sizes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [46:0] d_clr; // @[Monitor.scala:664:34] wire [46:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [187:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [187:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2382 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2382 & ~d_release_ack ? _d_clr_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2351 = _T_2484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2351 ? _d_clr_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2351 ? _d_opcodes_clr_T_5[187:0] : 188'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2351 ? _d_sizes_clr_T_5[187:0] : 188'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [46:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [46:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [46:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [187:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [187:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [187:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [187:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [187:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [187:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [46:0] inflight_1; // @[Monitor.scala:726:35] reg [187:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [187:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [46:0] c_set; // @[Monitor.scala:738:34] wire [46:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [187:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [187:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [187:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [187:0] _c_opcode_lookup_T_6 = {184'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [187:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[187:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [187:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [187:0] _c_size_lookup_T_6 = {184'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [187:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[187:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2423 = _T_2481 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2423 ? _c_set_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2423 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2423 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2423 ? _c_opcodes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2423 ? _c_sizes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [46:0] d_clr_1; // @[Monitor.scala:774:34] wire [46:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [187:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [187:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2454 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2454 & d_release_ack_1 ? _d_clr_wo_ready_T_1[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2436 = _T_2484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2436 ? _d_clr_T_1[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2436 ? _d_opcodes_clr_T_11[187:0] : 188'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2436 ? _d_sizes_clr_T_11[187:0] : 188'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [46:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [46:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [46:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [187:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [187:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [187:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [187:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [187:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [187:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_2490 = _T_2484 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2490 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module SystemBus : output auto : { flip coupler_from_nvdla_dbb_no_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst sbus_clock_groups of ClockGroupAggregator_sbus inst clockGroup of ClockGroup inst fixedClockNode of FixedClockBroadcast_5 inst broadcast of BundleBridgeNexus_NoOutput inst system_bus_xbar of TLXbar_sbus_i3_o2_a32d64s9k3z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus connect coupler_to_bus_named_cbus.clock, childClock connect coupler_to_bus_named_cbus.reset, childReset inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus connect coupler_from_bus_named_fbus.clock, childClock connect coupler_from_bus_named_fbus.reset, childReset inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh connect coupler_to_bus_named_coh.clock, childClock connect coupler_to_bus_named_coh.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset inst coupler_from_nvdla_dbb of TLInterconnectCoupler_sbus_from_nvdla_dbb connect coupler_from_nvdla_dbb.clock, childClock connect coupler_from_nvdla_dbb.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0 connect coupler_to_bus_named_coh.auto.widget_anon_in, system_bus_xbar.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2 connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out connect fixer.auto.anon_in_2, coupler_from_nvdla_dbb.auto.tl_out connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1 connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in connect auto.coupler_to_bus_named_coh_widget_anon_out.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.d, auto.coupler_to_bus_named_coh_widget_anon_out.d connect auto.coupler_to_bus_named_coh_widget_anon_out.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.b, auto.coupler_to_bus_named_coh_widget_anon_out.b connect auto.coupler_to_bus_named_coh_widget_anon_out.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out.a.ready connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in connect coupler_from_nvdla_dbb.auto.no_buffer_in, auto.coupler_from_nvdla_dbb_no_buffer_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module SystemBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_nvdla_dbb_no_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire _fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:152:27] wire [1:0] _fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:152:27] wire [1:0] _fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:152:27] wire [4:0] _fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:152:27] wire _system_bus_xbar_auto_anon_in_2_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_2_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_2_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_2_d_bits_size; // @[SystemBus.scala:47:43] wire [7:0] _system_bus_xbar_auto_anon_in_2_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_2_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_2_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_b_valid; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_b_bits_param; // @[SystemBus.scala:47:43] wire [31:0] _system_bus_xbar_auto_anon_in_1_b_bits_address; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_c_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_1_d_bits_size; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_1_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_0_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_0_d_bits_size; // @[SystemBus.scala:47:43] wire [4:0] _system_bus_xbar_auto_anon_in_0_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_0_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_5 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_sbus_clock_groups_in_member_sbus_0_clock), .auto_anon_in_reset (auto_sbus_clock_groups_in_member_sbus_0_reset), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_sbus_i3_o2_a32d64s9k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_2_a_ready (_system_bus_xbar_auto_anon_in_2_a_ready), .auto_anon_in_2_a_valid (_fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_opcode (_fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_param (_fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_size (_fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_source (_fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_address (_fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_2_a_bits_user_amba_prot_secure), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_mask (_fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_data (_fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_corrupt (_fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_d_ready (_fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_d_valid (_system_bus_xbar_auto_anon_in_2_d_valid), .auto_anon_in_2_d_bits_opcode (_system_bus_xbar_auto_anon_in_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (_system_bus_xbar_auto_anon_in_2_d_bits_param), .auto_anon_in_2_d_bits_size (_system_bus_xbar_auto_anon_in_2_d_bits_size), .auto_anon_in_2_d_bits_source (_system_bus_xbar_auto_anon_in_2_d_bits_source), .auto_anon_in_2_d_bits_sink (_system_bus_xbar_auto_anon_in_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (_system_bus_xbar_auto_anon_in_2_d_bits_denied), .auto_anon_in_2_d_bits_data (_system_bus_xbar_auto_anon_in_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (_system_bus_xbar_auto_anon_in_2_d_bits_corrupt), .auto_anon_in_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_b_ready (_fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid), .auto_anon_in_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param), .auto_anon_in_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address), .auto_anon_in_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready), .auto_anon_in_1_c_valid (_fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_d_ready (_fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_1_e_valid (_fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready), .auto_anon_in_0_a_valid (_fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_0_a_bits_user_amba_prot_secure), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_d_ready (_fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size), .auto_anon_in_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source), .auto_anon_in_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt), .auto_anon_out_1_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_a_ready), .auto_anon_out_1_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_anon_out_1_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_anon_out_1_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_anon_out_1_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_anon_out_1_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_anon_out_1_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_anon_out_1_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_anon_out_1_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_anon_out_1_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_anon_out_1_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_anon_out_1_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_b_valid), .auto_anon_out_1_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param), .auto_anon_out_1_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address), .auto_anon_out_1_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_c_ready), .auto_anon_out_1_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_anon_out_1_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_anon_out_1_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_anon_out_1_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_anon_out_1_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_anon_out_1_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_anon_out_1_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_anon_out_1_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_anon_out_1_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_anon_out_1_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_d_valid), .auto_anon_out_1_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode), .auto_anon_out_1_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param), .auto_anon_out_1_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size), .auto_anon_out_1_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source), .auto_anon_out_1_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink), .auto_anon_out_1_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied), .auto_anon_out_1_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data), .auto_anon_out_1_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt), .auto_anon_out_1_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_anon_out_1_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_anon_out_0_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready), .auto_anon_out_0_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_anon_out_0_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_anon_out_0_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_anon_out_0_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_anon_out_0_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_anon_out_0_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_anon_out_0_a_bits_user_amba_prot_bufferable (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_bufferable), .auto_anon_out_0_a_bits_user_amba_prot_modifiable (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_modifiable), .auto_anon_out_0_a_bits_user_amba_prot_readalloc (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_readalloc), .auto_anon_out_0_a_bits_user_amba_prot_writealloc (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_writealloc), .auto_anon_out_0_a_bits_user_amba_prot_privileged (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_privileged), .auto_anon_out_0_a_bits_user_amba_prot_secure (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_secure), .auto_anon_out_0_a_bits_user_amba_prot_fetch (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_fetch), .auto_anon_out_0_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_anon_out_0_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_anon_out_0_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_anon_out_0_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_anon_out_0_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid), .auto_anon_out_0_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode), .auto_anon_out_0_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param), .auto_anon_out_0_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size), .auto_anon_out_0_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source), .auto_anon_out_0_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink), .auto_anon_out_0_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied), .auto_anon_out_0_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data), .auto_anon_out_0_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt) ); // @[SystemBus.scala:47:43] TLFIFOFixer fixer ( // @[FIFOFixer.scala:152:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_2_a_ready (auto_coupler_from_nvdla_dbb_no_buffer_in_a_ready), .auto_anon_in_2_a_valid (auto_coupler_from_nvdla_dbb_no_buffer_in_a_valid), .auto_anon_in_2_a_bits_opcode (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_opcode), .auto_anon_in_2_a_bits_param (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_param), .auto_anon_in_2_a_bits_size (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_size), .auto_anon_in_2_a_bits_source (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_source), .auto_anon_in_2_a_bits_address (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_address), .auto_anon_in_2_a_bits_user_amba_prot_bufferable (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_bufferable), .auto_anon_in_2_a_bits_user_amba_prot_modifiable (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_modifiable), .auto_anon_in_2_a_bits_user_amba_prot_readalloc (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_readalloc), .auto_anon_in_2_a_bits_user_amba_prot_writealloc (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_writealloc), .auto_anon_in_2_a_bits_user_amba_prot_privileged (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_privileged), .auto_anon_in_2_a_bits_user_amba_prot_secure (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_secure), .auto_anon_in_2_a_bits_user_amba_prot_fetch (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_fetch), .auto_anon_in_2_a_bits_mask (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_mask), .auto_anon_in_2_a_bits_data (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_data), .auto_anon_in_2_a_bits_corrupt (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_corrupt), .auto_anon_in_2_d_ready (auto_coupler_from_nvdla_dbb_no_buffer_in_d_ready), .auto_anon_in_2_d_valid (auto_coupler_from_nvdla_dbb_no_buffer_in_d_valid), .auto_anon_in_2_d_bits_opcode (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_opcode), .auto_anon_in_2_d_bits_param (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_param), .auto_anon_in_2_d_bits_size (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_size), .auto_anon_in_2_d_bits_source (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_source), .auto_anon_in_2_d_bits_sink (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_sink), .auto_anon_in_2_d_bits_denied (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_denied), .auto_anon_in_2_d_bits_data (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_data), .auto_anon_in_2_d_bits_corrupt (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_corrupt), .auto_anon_in_1_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready), .auto_anon_in_1_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid), .auto_anon_in_1_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode), .auto_anon_in_1_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param), .auto_anon_in_1_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size), .auto_anon_in_1_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source), .auto_anon_in_1_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address), .auto_anon_in_1_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask), .auto_anon_in_1_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data), .auto_anon_in_1_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt), .auto_anon_in_1_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready), .auto_anon_in_1_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid), .auto_anon_in_1_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param), .auto_anon_in_1_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address), .auto_anon_in_1_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready), .auto_anon_in_1_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid), .auto_anon_in_1_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode), .auto_anon_in_1_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param), .auto_anon_in_1_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size), .auto_anon_in_1_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source), .auto_anon_in_1_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address), .auto_anon_in_1_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data), .auto_anon_in_1_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt), .auto_anon_in_1_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready), .auto_anon_in_1_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid), .auto_anon_in_1_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode), .auto_anon_in_1_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param), .auto_anon_in_1_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size), .auto_anon_in_1_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source), .auto_anon_in_1_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink), .auto_anon_in_1_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied), .auto_anon_in_1_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data), .auto_anon_in_1_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt), .auto_anon_in_1_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid), .auto_anon_in_1_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink), .auto_anon_in_0_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_anon_in_0_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid), .auto_anon_in_0_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode), .auto_anon_in_0_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param), .auto_anon_in_0_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size), .auto_anon_in_0_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source), .auto_anon_in_0_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address), .auto_anon_in_0_a_bits_user_amba_prot_bufferable (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_bufferable), .auto_anon_in_0_a_bits_user_amba_prot_modifiable (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_modifiable), .auto_anon_in_0_a_bits_user_amba_prot_readalloc (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_readalloc), .auto_anon_in_0_a_bits_user_amba_prot_writealloc (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_writealloc), .auto_anon_in_0_a_bits_user_amba_prot_privileged (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_privileged), .auto_anon_in_0_a_bits_user_amba_prot_secure (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_secure), .auto_anon_in_0_a_bits_user_amba_prot_fetch (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_fetch), .auto_anon_in_0_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask), .auto_anon_in_0_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data), .auto_anon_in_0_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt), .auto_anon_in_0_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready), .auto_anon_in_0_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_anon_in_0_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_anon_in_0_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_anon_in_0_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_anon_in_0_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_anon_in_0_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_anon_in_0_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_anon_in_0_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_anon_in_0_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_anon_out_2_a_ready (_system_bus_xbar_auto_anon_in_2_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_2_a_valid (_fixer_auto_anon_out_2_a_valid), .auto_anon_out_2_a_bits_opcode (_fixer_auto_anon_out_2_a_bits_opcode), .auto_anon_out_2_a_bits_param (_fixer_auto_anon_out_2_a_bits_param), .auto_anon_out_2_a_bits_size (_fixer_auto_anon_out_2_a_bits_size), .auto_anon_out_2_a_bits_source (_fixer_auto_anon_out_2_a_bits_source), .auto_anon_out_2_a_bits_address (_fixer_auto_anon_out_2_a_bits_address), .auto_anon_out_2_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable), .auto_anon_out_2_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable), .auto_anon_out_2_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc), .auto_anon_out_2_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc), .auto_anon_out_2_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged), .auto_anon_out_2_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_2_a_bits_user_amba_prot_secure), .auto_anon_out_2_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch), .auto_anon_out_2_a_bits_mask (_fixer_auto_anon_out_2_a_bits_mask), .auto_anon_out_2_a_bits_data (_fixer_auto_anon_out_2_a_bits_data), .auto_anon_out_2_a_bits_corrupt (_fixer_auto_anon_out_2_a_bits_corrupt), .auto_anon_out_2_d_ready (_fixer_auto_anon_out_2_d_ready), .auto_anon_out_2_d_valid (_system_bus_xbar_auto_anon_in_2_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_opcode (_system_bus_xbar_auto_anon_in_2_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_param (_system_bus_xbar_auto_anon_in_2_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_size (_system_bus_xbar_auto_anon_in_2_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_source (_system_bus_xbar_auto_anon_in_2_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_sink (_system_bus_xbar_auto_anon_in_2_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_denied (_system_bus_xbar_auto_anon_in_2_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_data (_system_bus_xbar_auto_anon_in_2_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_corrupt (_system_bus_xbar_auto_anon_in_2_d_bits_corrupt), // @[SystemBus.scala:47:43] .auto_anon_out_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_1_a_valid (_fixer_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_b_ready (_fixer_auto_anon_out_1_b_ready), .auto_anon_out_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid), // @[SystemBus.scala:47:43] .auto_anon_out_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address), // @[SystemBus.scala:47:43] .auto_anon_out_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready), // @[SystemBus.scala:47:43] .auto_anon_out_1_c_valid (_fixer_auto_anon_out_1_c_valid), .auto_anon_out_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode), .auto_anon_out_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param), .auto_anon_out_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size), .auto_anon_out_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source), .auto_anon_out_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address), .auto_anon_out_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data), .auto_anon_out_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt), .auto_anon_out_1_d_ready (_fixer_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt), // @[SystemBus.scala:47:43] .auto_anon_out_1_e_valid (_fixer_auto_anon_out_1_e_valid), .auto_anon_out_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink), .auto_anon_out_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_0_a_valid (_fixer_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable), .auto_anon_out_0_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable), .auto_anon_out_0_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc), .auto_anon_out_0_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc), .auto_anon_out_0_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged), .auto_anon_out_0_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_0_a_bits_user_amba_prot_secure), .auto_anon_out_0_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch), .auto_anon_out_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_fixer_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt) // @[SystemBus.scala:47:43] ); // @[FIFOFixer.scala:152:27] assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_70 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = or(_T_12, _T_19) node _T_21 = or(_T_5, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = or(_T_32, _T_39) node _T_69 = or(_T_68, _T_46) node _T_70 = or(_T_69, _T_53) node _T_71 = or(_T_70, _T_60) node _T_72 = or(_T_71, _T_67) node _T_73 = or(_T_25, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2	module NoCMonitor_70( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module Tile_142 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_398 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_142( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_398 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_335 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_79 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_335( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_79 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_13 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_13( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_4 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x	module PMPChecker_s3_4( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [5:0] _res_hit_lsbMask_T = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_3 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_16 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_29 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_42 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_55 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_68 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_81 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_94 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14 = 6'hE; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_4 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_1 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_4 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_17 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_3 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_7 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_30 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_5 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_10 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_43 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_7 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_13 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_56 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_9 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_16 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_69 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_11 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_19 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_82 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_13 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_22 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_95 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_15 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_2 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_5 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_5 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_18 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_1 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_8 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_31 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_2 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_11 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_44 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_3 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_14 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_57 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_4 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_17 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_70 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_5 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_20 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_83 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_6 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_23 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_96 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_7 = 3'h1; // @[package.scala:243:46] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_size = 2'h1; // @[PMP.scala:143:7, :146:14] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T \| 3'h1}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess \| _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 \| _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = \|_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = \|_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound \| res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = _res_aligned_pow2Aligned_T_1 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 \| _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 \| _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = \|_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = \|_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 \| res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = _res_aligned_pow2Aligned_T_4 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 \| _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 \| _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = \|_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = \|_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 \| res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = _res_aligned_pow2Aligned_T_7 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 \| _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 \| _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = \|_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = \|_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 \| res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = _res_aligned_pow2Aligned_T_10 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 \| _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 \| _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = \|_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = \|_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 \| res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = _res_aligned_pow2Aligned_T_13 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 \| _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 \| _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = \|_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = \|_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 \| res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = _res_aligned_pow2Aligned_T_16 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 \| _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 \| _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = \|_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = \|_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 \| res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = _res_aligned_pow2Aligned_T_19 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 \| 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 \| 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 \| _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 \| 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = \|_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = _res_aligned_pow2Aligned_T_22 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 13, 0) node _source_ok_T = shr(io.in.a.bits.source, 14) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<14>(0h200f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits = bits(_uncommonBits_T, 13, 0) node _T_4 = shr(io.in.a.bits.source, 14) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<14>(0h200f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 13, 0) node _T_24 = shr(io.in.a.bits.source, 14) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<14>(0h200f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 13, 0) node _T_86 = shr(io.in.a.bits.source, 14) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<14>(0h200f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 13, 0) node _T_152 = shr(io.in.a.bits.source, 14) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<14>(0h200f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 13, 0) node _T_199 = shr(io.in.a.bits.source, 14) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<14>(0h200f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 13, 0) node _T_240 = shr(io.in.a.bits.source, 14) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<14>(0h200f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 13, 0) node _T_283 = shr(io.in.a.bits.source, 14) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<14>(0h200f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 13, 0) node _T_321 = shr(io.in.a.bits.source, 14) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<14>(0h200f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 13, 0) node _T_359 = shr(io.in.a.bits.source, 14) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<14>(0h200f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 13, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 14) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<14>(0h200f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes : UInt<32832>, clock, reset, UInt<32832>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<8208> connect a_set, UInt<8208>(0h0) wire a_set_wo_ready : UInt<8208> connect a_set_wo_ready, UInt<8208>(0h0) wire a_opcodes_set : UInt<32832> connect a_opcodes_set, UInt<32832>(0h0) wire a_sizes_set : UInt<32832> connect a_sizes_set, UInt<32832>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<8208> connect d_clr, UInt<8208>(0h0) wire d_clr_wo_ready : UInt<8208> connect d_clr_wo_ready, UInt<8208>(0h0) wire d_opcodes_clr : UInt<32832> connect d_opcodes_clr, UInt<32832>(0h0) wire d_sizes_clr : UInt<32832> connect d_sizes_clr, UInt<32832>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<14>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<14>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<8208> connect c_set, UInt<8208>(0h0) wire c_set_wo_ready : UInt<8208> connect c_set_wo_ready, UInt<8208>(0h0) wire c_opcodes_set : UInt<32832> connect c_opcodes_set, UInt<32832>(0h0) wire c_sizes_set : UInt<32832> connect c_sizes_set, UInt<32832>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<14>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<14>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<14>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<14>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<14>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<14>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<8208> connect d_clr_1, UInt<8208>(0h0) wire d_clr_wo_ready_1 : UInt<8208> connect d_clr_wo_ready_1, UInt<8208>(0h0) wire d_opcodes_clr_1 : UInt<32832> connect d_opcodes_clr_1, UInt<32832>(0h0) wire d_sizes_clr_1 : UInt<32832> connect d_sizes_clr_1, UInt<32832>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<14>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<14>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<14>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<14>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<14>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_146 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_146( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_7 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_7 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h18), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h12), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h14), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow	module EgressUnit_7( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_46 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_46( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_3 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} inst a of TLAFromNoC_3 connect a.clock, clock connect a.reset, reset inst b of TLBToNoC_3 connect b.clock, clock connect b.reset, reset inst c of TLCFromNoC_3 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_3 connect d.clock, clock connect d.reset, reset inst e of TLEFromNoC_3 connect e.clock, clock connect e.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect b.io.protocol, io.tilelink.b connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect io.tilelink.e.bits, e.io.protocol.bits connect io.tilelink.e.valid, e.io.protocol.valid connect e.io.protocol.ready, io.tilelink.e.ready connect a.io.flit, io.flits.a connect io.flits.b.bits, b.io.flit.bits connect io.flits.b.valid, b.io.flit.valid connect b.io.flit.ready, io.flits.b.ready connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready connect e.io.flit, io.flits.e	module TLSlaveToNoC_3( // @[Tilelink.scala:125:7] input clock, // @[Tilelink.scala:125:7] input reset, // @[Tilelink.scala:125:7] input io_tilelink_a_ready, // @[Tilelink.scala:132:14] output io_tilelink_a_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_b_ready, // @[Tilelink.scala:132:14] input io_tilelink_b_valid, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:132:14] input [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:132:14] input io_tilelink_c_ready, // @[Tilelink.scala:132:14] output io_tilelink_c_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_d_ready, // @[Tilelink.scala:132:14] input io_tilelink_d_valid, // @[Tilelink.scala:132:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_e_valid, // @[Tilelink.scala:132:14] output [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:132:14] output io_flits_a_ready, // @[Tilelink.scala:132:14] input io_flits_a_valid, // @[Tilelink.scala:132:14] input io_flits_a_bits_head, // @[Tilelink.scala:132:14] input io_flits_a_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14] input io_flits_b_ready, // @[Tilelink.scala:132:14] output io_flits_b_valid, // @[Tilelink.scala:132:14] output io_flits_b_bits_head, // @[Tilelink.scala:132:14] output io_flits_b_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_b_bits_egress_id, // @[Tilelink.scala:132:14] output io_flits_c_ready, // @[Tilelink.scala:132:14] input io_flits_c_valid, // @[Tilelink.scala:132:14] input io_flits_c_bits_head, // @[Tilelink.scala:132:14] input io_flits_c_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:132:14] input io_flits_d_ready, // @[Tilelink.scala:132:14] output io_flits_d_valid, // @[Tilelink.scala:132:14] output io_flits_d_bits_head, // @[Tilelink.scala:132:14] output io_flits_d_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14] input io_flits_e_valid, // @[Tilelink.scala:132:14] input io_flits_e_bits_head, // @[Tilelink.scala:132:14] input io_flits_e_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_e_bits_payload // @[Tilelink.scala:132:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17] TLAFromNoC a ( // @[Tilelink.scala:143:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:143:17] TLBToNoC_1 b ( // @[Tilelink.scala:144:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload), .io_flit_bits_egress_id (io_flits_b_bits_egress_id) ); // @[Tilelink.scala:144:17] TLCFromNoC_1 c ( // @[Tilelink.scala:145:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:156:14] ); // @[Tilelink.scala:145:17] TLDToNoC_3 d ( // @[Tilelink.scala:146:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:146:17] TLEFromNoC_1 e ( // @[Tilelink.scala:147:17] .clock (clock), .reset (reset), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_tail (io_flits_e_bits_tail), .io_flit_bits_payload (io_flits_e_bits_payload[4:0]) // @[Tilelink.scala:158:14] ); // @[Tilelink.scala:147:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_7 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_14 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_7 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h4), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<3>(0h5), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(route_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_15 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_7 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_24 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_25 = and(vcalloc_q.io.enq.valid, _T_24) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_26, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_7( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h19; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h1C; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) \| ((&io_in_bits_egress_id) ? 4'hA : 4'h0); // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h2; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h2; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node doEarlyAck = bits(anonOut.d.bits.source, 4, 4) node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(doEarlyAck, dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 5) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a32d64s7k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node aFull = eq(repeater.io.deq.bits.opcode, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_lo = cat(aToggle, aFragnum) node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aFull) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, anonOut_a_bits_source_lo) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full \|\| !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full \|\| in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLFragmenter_1( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [31:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [32:0] _find_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _find_T_3 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [31:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData \| _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] \| dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = \|dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} \| dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = \|dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 \| dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire doEarlyAck = anonOut_d_bits_source[4]; // @[Fragmenter.scala:231:54] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_1 = doEarlyAck ? dFirst : dLast; // @[Fragmenter.scala:205:29, :206:30, :231:54, :234:37] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready \| drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:5]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [31:0] _find_T; // @[Parameters.scala:137:31] wire [32:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _GEN = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T; // @[Fragmenter.scala:288:49] assign _limit_T = _GEN; // @[Fragmenter.scala:288:49] wire aFull; // @[Fragmenter.scala:310:78] assign aFull = _GEN; // @[Fragmenter.scala:288:49, :310:78] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(\|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = \|aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T \| _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] \| aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[31:6], _repeater_io_deq_bits_address[5:0] \| _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [3:0] anonOut_a_bits_source_lo = {aToggle, aFragnum}; // @[Fragmenter.scala:307:24, :309:23, :317:33] wire [7:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aFull}; // @[Fragmenter.scala:274:30, :310:78, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, anonOut_a_bits_source_lo}; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_32 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_32( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_33 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_33( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module SimpleHellaCacheIF : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, cache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} invalidate io.cache.clock_enabled invalidate io.cache.keep_clock_enabled invalidate io.cache.perf.storeBufferEmptyAfterStore invalidate io.cache.perf.storeBufferEmptyAfterLoad invalidate io.cache.perf.canAcceptLoadThenLoad invalidate io.cache.perf.canAcceptStoreThenRMW invalidate io.cache.perf.canAcceptStoreThenLoad invalidate io.cache.perf.blocked invalidate io.cache.perf.tlbMiss invalidate io.cache.perf.grant invalidate io.cache.perf.release invalidate io.cache.perf.acquire invalidate io.cache.store_pending invalidate io.cache.ordered invalidate io.cache.s2_gpa_is_pte invalidate io.cache.s2_gpa invalidate io.cache.s2_xcpt.ae.st invalidate io.cache.s2_xcpt.ae.ld invalidate io.cache.s2_xcpt.gf.st invalidate io.cache.s2_xcpt.gf.ld invalidate io.cache.s2_xcpt.pf.st invalidate io.cache.s2_xcpt.pf.ld invalidate io.cache.s2_xcpt.ma.st invalidate io.cache.s2_xcpt.ma.ld invalidate io.cache.replay_next invalidate io.cache.resp.bits.store_data invalidate io.cache.resp.bits.data_raw invalidate io.cache.resp.bits.data_word_bypass invalidate io.cache.resp.bits.has_data invalidate io.cache.resp.bits.replay invalidate io.cache.resp.bits.mask invalidate io.cache.resp.bits.data invalidate io.cache.resp.bits.dv invalidate io.cache.resp.bits.dprv invalidate io.cache.resp.bits.signed invalidate io.cache.resp.bits.size invalidate io.cache.resp.bits.cmd invalidate io.cache.resp.bits.tag invalidate io.cache.resp.bits.addr invalidate io.cache.resp.valid invalidate io.cache.s2_paddr invalidate io.cache.s2_uncached invalidate io.cache.s2_kill invalidate io.cache.s2_nack_cause_raw invalidate io.cache.s2_nack invalidate io.cache.s1_data.mask invalidate io.cache.s1_data.data invalidate io.cache.s1_kill invalidate io.cache.req.bits.mask invalidate io.cache.req.bits.data invalidate io.cache.req.bits.no_xcpt invalidate io.cache.req.bits.no_alloc invalidate io.cache.req.bits.no_resp invalidate io.cache.req.bits.phys invalidate io.cache.req.bits.dv invalidate io.cache.req.bits.dprv invalidate io.cache.req.bits.signed invalidate io.cache.req.bits.size invalidate io.cache.req.bits.cmd invalidate io.cache.req.bits.tag invalidate io.cache.req.bits.addr invalidate io.cache.req.valid invalidate io.cache.req.ready invalidate io.requestor.clock_enabled invalidate io.requestor.keep_clock_enabled invalidate io.requestor.perf.storeBufferEmptyAfterStore invalidate io.requestor.perf.storeBufferEmptyAfterLoad invalidate io.requestor.perf.canAcceptLoadThenLoad invalidate io.requestor.perf.canAcceptStoreThenRMW invalidate io.requestor.perf.canAcceptStoreThenLoad invalidate io.requestor.perf.blocked invalidate io.requestor.perf.tlbMiss invalidate io.requestor.perf.grant invalidate io.requestor.perf.release invalidate io.requestor.perf.acquire invalidate io.requestor.store_pending invalidate io.requestor.ordered invalidate io.requestor.s2_gpa_is_pte invalidate io.requestor.s2_gpa invalidate io.requestor.s2_xcpt.ae.st invalidate io.requestor.s2_xcpt.ae.ld invalidate io.requestor.s2_xcpt.gf.st invalidate io.requestor.s2_xcpt.gf.ld invalidate io.requestor.s2_xcpt.pf.st invalidate io.requestor.s2_xcpt.pf.ld invalidate io.requestor.s2_xcpt.ma.st invalidate io.requestor.s2_xcpt.ma.ld invalidate io.requestor.replay_next invalidate io.requestor.resp.bits.store_data invalidate io.requestor.resp.bits.data_raw invalidate io.requestor.resp.bits.data_word_bypass invalidate io.requestor.resp.bits.has_data invalidate io.requestor.resp.bits.replay invalidate io.requestor.resp.bits.mask invalidate io.requestor.resp.bits.data invalidate io.requestor.resp.bits.dv invalidate io.requestor.resp.bits.dprv invalidate io.requestor.resp.bits.signed invalidate io.requestor.resp.bits.size invalidate io.requestor.resp.bits.cmd invalidate io.requestor.resp.bits.tag invalidate io.requestor.resp.bits.addr invalidate io.requestor.resp.valid invalidate io.requestor.s2_paddr invalidate io.requestor.s2_uncached invalidate io.requestor.s2_kill invalidate io.requestor.s2_nack_cause_raw invalidate io.requestor.s2_nack invalidate io.requestor.s1_data.mask invalidate io.requestor.s1_data.data invalidate io.requestor.s1_kill invalidate io.requestor.req.bits.mask invalidate io.requestor.req.bits.data invalidate io.requestor.req.bits.no_xcpt invalidate io.requestor.req.bits.no_alloc invalidate io.requestor.req.bits.no_resp invalidate io.requestor.req.bits.phys invalidate io.requestor.req.bits.dv invalidate io.requestor.req.bits.dprv invalidate io.requestor.req.bits.signed invalidate io.requestor.req.bits.size invalidate io.requestor.req.bits.cmd invalidate io.requestor.req.bits.tag invalidate io.requestor.req.bits.addr invalidate io.requestor.req.valid invalidate io.requestor.req.ready inst replayq of SimpleHellaCacheIFReplayQueue connect replayq.clock, clock connect replayq.reset, reset inst req_arb of Arbiter2_HellaCacheReq connect req_arb.clock, clock connect req_arb.reset, reset connect req_arb.io.in[0], replayq.io.replay node _req_arb_io_in_1_valid_T = and(replayq.io.req.ready, io.requestor.req.valid) connect req_arb.io.in[1].valid, _req_arb_io_in_1_valid_T connect req_arb.io.in[1].bits.mask, io.requestor.req.bits.mask connect req_arb.io.in[1].bits.data, io.requestor.req.bits.data connect req_arb.io.in[1].bits.no_xcpt, io.requestor.req.bits.no_xcpt connect req_arb.io.in[1].bits.no_alloc, io.requestor.req.bits.no_alloc connect req_arb.io.in[1].bits.no_resp, io.requestor.req.bits.no_resp connect req_arb.io.in[1].bits.phys, io.requestor.req.bits.phys connect req_arb.io.in[1].bits.dv, io.requestor.req.bits.dv connect req_arb.io.in[1].bits.dprv, io.requestor.req.bits.dprv connect req_arb.io.in[1].bits.signed, io.requestor.req.bits.signed connect req_arb.io.in[1].bits.size, io.requestor.req.bits.size connect req_arb.io.in[1].bits.cmd, io.requestor.req.bits.cmd connect req_arb.io.in[1].bits.tag, io.requestor.req.bits.tag connect req_arb.io.in[1].bits.addr, io.requestor.req.bits.addr node _io_requestor_req_ready_T = and(req_arb.io.in[1].ready, replayq.io.req.ready) connect io.requestor.req.ready, _io_requestor_req_ready_T node _replayq_io_req_valid_T = and(req_arb.io.in[1].ready, io.requestor.req.valid) connect replayq.io.req.valid, _replayq_io_req_valid_T connect replayq.io.req.bits.mask, io.requestor.req.bits.mask connect replayq.io.req.bits.data, io.requestor.req.bits.data connect replayq.io.req.bits.no_xcpt, io.requestor.req.bits.no_xcpt connect replayq.io.req.bits.no_alloc, io.requestor.req.bits.no_alloc connect replayq.io.req.bits.no_resp, io.requestor.req.bits.no_resp connect replayq.io.req.bits.phys, io.requestor.req.bits.phys connect replayq.io.req.bits.dv, io.requestor.req.bits.dv connect replayq.io.req.bits.dprv, io.requestor.req.bits.dprv connect replayq.io.req.bits.signed, io.requestor.req.bits.signed connect replayq.io.req.bits.size, io.requestor.req.bits.size connect replayq.io.req.bits.cmd, io.requestor.req.bits.cmd connect replayq.io.req.bits.tag, io.requestor.req.bits.tag connect replayq.io.req.bits.addr, io.requestor.req.bits.addr node s0_req_fire = and(io.cache.req.ready, io.cache.req.valid) reg s1_req_fire : UInt<1>, clock connect s1_req_fire, s0_req_fire reg s2_req_fire : UInt<1>, clock connect s2_req_fire, s1_req_fire reg s1_req_tag : UInt, clock connect s1_req_tag, io.cache.req.bits.tag reg s2_req_tag : UInt, clock connect s2_req_tag, s1_req_tag reg REG : UInt<1>, clock connect REG, io.cache.s2_nack node _T = eq(REG, UInt<1>(0h0)) node _T_1 = eq(s2_req_fire, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = or(_T_2, io.cache.s2_nack) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:124 assert(!RegNext(io.cache.s2_nack) \|\| !s2_req_fire \|\| io.cache.s2_nack)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(io.cache.s2_nack, UInt<1>(0h0)) node _T_8 = eq(io.cache.req.ready, UInt<1>(0h0)) node _T_9 = or(_T_7, _T_8) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:125 assert(!io.cache.s2_nack \|\| !io.cache.req.ready)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 connect io.cache.req.bits, req_arb.io.out.bits connect io.cache.req.valid, req_arb.io.out.valid connect req_arb.io.out.ready, io.cache.req.ready connect io.cache.s1_kill, UInt<1>(0h0) reg io_cache_s1_data_r : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock when s0_req_fire : connect io_cache_s1_data_r, req_arb.io.out.bits connect io.cache.s1_data.mask, io_cache_s1_data_r.mask connect io.cache.s1_data.data, io_cache_s1_data_r.data connect io.cache.s2_kill, UInt<1>(0h0) node _replayq_io_nack_valid_T = and(io.cache.s2_nack, s2_req_fire) connect replayq.io.nack.valid, _replayq_io_nack_valid_T connect replayq.io.nack.bits, s2_req_tag connect replayq.io.resp.bits.store_data, io.cache.resp.bits.store_data connect replayq.io.resp.bits.data_raw, io.cache.resp.bits.data_raw connect replayq.io.resp.bits.data_word_bypass, io.cache.resp.bits.data_word_bypass connect replayq.io.resp.bits.has_data, io.cache.resp.bits.has_data connect replayq.io.resp.bits.replay, io.cache.resp.bits.replay connect replayq.io.resp.bits.mask, io.cache.resp.bits.mask connect replayq.io.resp.bits.data, io.cache.resp.bits.data connect replayq.io.resp.bits.dv, io.cache.resp.bits.dv connect replayq.io.resp.bits.dprv, io.cache.resp.bits.dprv connect replayq.io.resp.bits.signed, io.cache.resp.bits.signed connect replayq.io.resp.bits.size, io.cache.resp.bits.size connect replayq.io.resp.bits.cmd, io.cache.resp.bits.cmd connect replayq.io.resp.bits.tag, io.cache.resp.bits.tag connect replayq.io.resp.bits.addr, io.cache.resp.bits.addr connect replayq.io.resp.valid, io.cache.resp.valid connect io.requestor.resp, io.cache.resp node _T_13 = eq(s2_req_fire, UInt<1>(0h0)) node _T_14 = cat(io.cache.s2_xcpt.ae.ld, io.cache.s2_xcpt.ae.st) node _T_15 = cat(io.cache.s2_xcpt.gf.ld, io.cache.s2_xcpt.gf.st) node _T_16 = cat(io.cache.s2_xcpt.pf.ld, io.cache.s2_xcpt.pf.st) node _T_17 = cat(io.cache.s2_xcpt.ma.ld, io.cache.s2_xcpt.ma.st) node lo = cat(_T_15, _T_14) node hi = cat(_T_17, _T_16) node _T_18 = cat(hi, lo) node _T_19 = orr(_T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = or(_T_13, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed: SimpleHellaCacheIF exception\n at SimpleHellaCacheIF.scala:137 assert(!s2_req_fire \|\| !io.cache.s2_xcpt.asUInt.orR, \"SimpleHellaCacheIF exception\")\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2	module SimpleHellaCacheIF( // @[SimpleHellaCacheIF.scala:95:7] input clock, // @[SimpleHellaCacheIF.scala:95:7] input reset, // @[SimpleHellaCacheIF.scala:95:7] output io_requestor_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] output [39:0] io_requestor_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [4:0] io_requestor_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_valid, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_cache_s1_data_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_cache_s1_data_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack_cause_raw, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_uncached, // @[SimpleHellaCacheIF.scala:97:14] input [31:0] io_cache_s2_paddr, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [4:0] io_cache_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_replay_next, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_st, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_s2_gpa, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_ordered, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_store_pending, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_acquire, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_release, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_grant, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_tlbMiss, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_blocked, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenRMW, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptLoadThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterStore // @[SimpleHellaCacheIF.scala:97:14] ); wire _req_arb_io_in_0_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_in_1_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _replayq_io_req_ready; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_valid; // @[SimpleHellaCacheIF.scala:103:23] wire io_cache_req_ready_0 = io_cache_req_ready; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_0 = io_cache_s2_nack; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_cause_raw_0 = io_cache_s2_nack_cause_raw; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_uncached_0 = io_cache_s2_uncached; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_cache_s2_paddr_0 = io_cache_s2_paddr; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_valid_0 = io_cache_resp_valid; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_resp_bits_addr_0 = io_cache_resp_bits_addr; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_tag_0 = io_cache_resp_bits_tag; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_resp_bits_cmd_0 = io_cache_resp_bits_cmd; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_size_0 = io_cache_resp_bits_size; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_signed_0 = io_cache_resp_bits_signed; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_dprv_0 = io_cache_resp_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_dv_0 = io_cache_resp_bits_dv; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_0 = io_cache_resp_bits_data; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_mask_0 = io_cache_resp_bits_mask; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_replay_0 = io_cache_resp_bits_replay; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_has_data_0 = io_cache_resp_bits_has_data; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_store_data_0 = io_cache_resp_bits_store_data; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_replay_next_0 = io_cache_replay_next; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_ld_0 = io_cache_s2_xcpt_ma_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_st_0 = io_cache_s2_xcpt_ma_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_ld_0 = io_cache_s2_xcpt_pf_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_st_0 = io_cache_s2_xcpt_pf_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_ld_0 = io_cache_s2_xcpt_ae_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_st_0 = io_cache_s2_xcpt_ae_st; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_s2_gpa_0 = io_cache_s2_gpa; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_ordered_0 = io_cache_ordered; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_store_pending_0 = io_cache_store_pending; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_acquire_0 = io_cache_perf_acquire; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_release_0 = io_cache_perf_release; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_grant_0 = io_cache_perf_grant; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_tlbMiss_0 = io_cache_perf_tlbMiss; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_blocked_0 = io_cache_perf_blocked; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenLoad_0 = io_cache_perf_canAcceptStoreThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenRMW_0 = io_cache_perf_canAcceptStoreThenRMW; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptLoadThenLoad_0 = io_cache_perf_canAcceptLoadThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterLoad_0 = io_cache_perf_storeBufferEmptyAfterLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterStore_0 = io_cache_perf_storeBufferEmptyAfterStore; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_req_bits_addr = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_s2_gpa = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_req_bits_addr = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_tag = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_s1_data_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_tag = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_size = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_dprv = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_size = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_dprv = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_valid = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_dv = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack_cause_raw = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_uncached = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_replay_next = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_ordered = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_store_pending = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_acquire = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_release = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_grant = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_tlbMiss = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_blocked = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenRMW = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptLoadThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterStore = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_dv = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire _req_arb_io_in_1_valid_T = 1'h0; // @[Misc.scala:26:53] wire _replayq_io_req_valid_T = 1'h0; // @[Misc.scala:26:53] wire [63:0] io_requestor_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_s1_data_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_keep_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_requestor_s2_paddr = 32'h0; // @[SimpleHellaCacheIF.scala:95:7] wire _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire io_requestor_resp_valid_0 = io_cache_resp_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_resp_bits_addr_0 = io_cache_resp_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_tag_0 = io_cache_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_resp_bits_cmd_0 = io_cache_resp_bits_cmd_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_size_0 = io_cache_resp_bits_size_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_signed_0 = io_cache_resp_bits_signed_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_dprv_0 = io_cache_resp_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_dv_0 = io_cache_resp_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_0 = io_cache_resp_bits_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_mask_0 = io_cache_resp_bits_mask_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_replay_0 = io_cache_resp_bits_replay_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_has_data_0 = io_cache_resp_bits_has_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_store_data_0 = io_cache_resp_bits_store_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_ready_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_s1_data_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_s1_data_mask_0; // @[SimpleHellaCacheIF.scala:95:7] assign _io_requestor_req_ready_T = _req_arb_io_in_1_ready & _replayq_io_req_ready; // @[Misc.scala:26:53] assign io_requestor_req_ready_0 = _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire s0_req_fire = io_cache_req_ready_0 & io_cache_req_valid_0; // @[Decoupled.scala:51:35] reg s1_req_fire; // @[SimpleHellaCacheIF.scala:119:28] reg s2_req_fire; // @[SimpleHellaCacheIF.scala:120:28] reg [7:0] s1_req_tag; // @[SimpleHellaCacheIF.scala:121:27] reg [7:0] s2_req_tag; // @[SimpleHellaCacheIF.scala:122:27] reg REG; // @[SimpleHellaCacheIF.scala:124:18] reg [39:0] io_cache_s1_data_r_addr; // @[SimpleHellaCacheIF.scala:129:32] reg [7:0] io_cache_s1_data_r_tag; // @[SimpleHellaCacheIF.scala:129:32] reg [4:0] io_cache_s1_data_r_cmd; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_size; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_signed; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_dprv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_dv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_phys; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_resp; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_alloc; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_xcpt; // @[SimpleHellaCacheIF.scala:129:32] reg [63:0] io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_data_0 = io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:95:7, :129:32] reg [7:0] io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_mask_0 = io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:95:7, :129:32] wire _replayq_io_nack_valid_T = io_cache_s2_nack_0 & s2_req_fire; // @[SimpleHellaCacheIF.scala:95:7, :120:28, :132:45] wire [3:0] lo = {2'h0, io_cache_s2_xcpt_ae_ld_0, io_cache_s2_xcpt_ae_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44] wire [3:0] hi = {io_cache_s2_xcpt_ma_ld_0, io_cache_s2_xcpt_ma_st_0, io_cache_s2_xcpt_pf_ld_0, io_cache_s2_xcpt_pf_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_29 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_29( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64ToRaw_mulAddZ31 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} regreset cycleNum_A : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_B : UInt<4>, clock, reset, UInt<4>(0h0) regreset cycleNum_C : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_E : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid_PA : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PA : UInt<1>, clock reg majorExc_PA : UInt<1>, clock reg isNaN_PA : UInt<1>, clock reg isInf_PA : UInt<1>, clock reg isZero_PA : UInt<1>, clock reg sign_PA : UInt<1>, clock reg sExp_PA : SInt<13>, clock reg fractB_PA : UInt<52>, clock reg fractA_PA : UInt<52>, clock reg roundingMode_PA : UInt<3>, clock regreset valid_PB : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PB : UInt<1>, clock reg majorExc_PB : UInt<1>, clock reg isNaN_PB : UInt<1>, clock reg isInf_PB : UInt<1>, clock reg isZero_PB : UInt<1>, clock reg sign_PB : UInt<1>, clock reg sExp_PB : SInt<13>, clock reg bit0FractA_PB : UInt<1>, clock reg fractB_PB : UInt<52>, clock reg roundingMode_PB : UInt<3>, clock regreset valid_PC : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PC : UInt<1>, clock reg majorExc_PC : UInt<1>, clock reg isNaN_PC : UInt<1>, clock reg isInf_PC : UInt<1>, clock reg isZero_PC : UInt<1>, clock reg sign_PC : UInt<1>, clock reg sExp_PC : SInt<13>, clock reg bit0FractA_PC : UInt<1>, clock reg fractB_PC : UInt<52>, clock reg roundingMode_PC : UInt<3>, clock reg fractR0_A : UInt<9>, clock reg hiSqrR0_A_sqrt : UInt<10>, clock reg partNegSigma0_A : UInt<21>, clock reg nextMulAdd9A_A : UInt<9>, clock reg nextMulAdd9B_A : UInt<9>, clock reg ER1_B_sqrt : UInt<17>, clock reg ESqrR1_B_sqrt : UInt<32>, clock reg sigX1_B : UInt<58>, clock reg sqrSigma1_C : UInt<33>, clock reg sigXN_C : UInt<58>, clock reg u_C_sqrt : UInt<31>, clock reg E_E_div : UInt<1>, clock reg sigT_E : UInt<54>, clock reg isNegRemT_E : UInt<1>, clock reg isZeroRemT_E : UInt<1>, clock wire ready_PA : UInt<1> wire ready_PB : UInt<1> wire ready_PC : UInt<1> wire leaving_PA : UInt<1> wire leaving_PB : UInt<1> wire leaving_PC : UInt<1> wire zSigma1_B4 : UInt wire sigXNU_B3_CX : UInt wire zComplSigT_C1_sqrt : UInt wire zComplSigT_C1 : UInt node _cyc_S_div_T = and(io.inReady_div, io.inValid) node _cyc_S_div_T_1 = eq(io.sqrtOp, UInt<1>(0h0)) node cyc_S_div = and(_cyc_S_div_T, _cyc_S_div_T_1) node _cyc_S_sqrt_T = and(io.inReady_sqrt, io.inValid) node cyc_S_sqrt = and(_cyc_S_sqrt_T, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) node rawA_S_exp = bits(io.a, 63, 52) node _rawA_S_isZero_T = bits(rawA_S_exp, 11, 9) node rawA_S_isZero = eq(_rawA_S_isZero_T, UInt<1>(0h0)) node _rawA_S_isSpecial_T = bits(rawA_S_exp, 11, 10) node rawA_S_isSpecial = eq(_rawA_S_isSpecial_T, UInt<2>(0h3)) wire rawA_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_S_out_isNaN_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isNaN_T_1 = and(rawA_S_isSpecial, _rawA_S_out_isNaN_T) connect rawA_S.isNaN, _rawA_S_out_isNaN_T_1 node _rawA_S_out_isInf_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isInf_T_1 = eq(_rawA_S_out_isInf_T, UInt<1>(0h0)) node _rawA_S_out_isInf_T_2 = and(rawA_S_isSpecial, _rawA_S_out_isInf_T_1) connect rawA_S.isInf, _rawA_S_out_isInf_T_2 connect rawA_S.isZero, rawA_S_isZero node _rawA_S_out_sign_T = bits(io.a, 64, 64) connect rawA_S.sign, _rawA_S_out_sign_T node _rawA_S_out_sExp_T = cvt(rawA_S_exp) connect rawA_S.sExp, _rawA_S_out_sExp_T node _rawA_S_out_sig_T = eq(rawA_S_isZero, UInt<1>(0h0)) node _rawA_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_S_out_sig_T) node _rawA_S_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_S_out_sig_T_3 = cat(_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2) connect rawA_S.sig, _rawA_S_out_sig_T_3 node rawB_S_exp = bits(io.b, 63, 52) node _rawB_S_isZero_T = bits(rawB_S_exp, 11, 9) node rawB_S_isZero = eq(_rawB_S_isZero_T, UInt<1>(0h0)) node _rawB_S_isSpecial_T = bits(rawB_S_exp, 11, 10) node rawB_S_isSpecial = eq(_rawB_S_isSpecial_T, UInt<2>(0h3)) wire rawB_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_S_out_isNaN_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isNaN_T_1 = and(rawB_S_isSpecial, _rawB_S_out_isNaN_T) connect rawB_S.isNaN, _rawB_S_out_isNaN_T_1 node _rawB_S_out_isInf_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isInf_T_1 = eq(_rawB_S_out_isInf_T, UInt<1>(0h0)) node _rawB_S_out_isInf_T_2 = and(rawB_S_isSpecial, _rawB_S_out_isInf_T_1) connect rawB_S.isInf, _rawB_S_out_isInf_T_2 connect rawB_S.isZero, rawB_S_isZero node _rawB_S_out_sign_T = bits(io.b, 64, 64) connect rawB_S.sign, _rawB_S_out_sign_T node _rawB_S_out_sExp_T = cvt(rawB_S_exp) connect rawB_S.sExp, _rawB_S_out_sExp_T node _rawB_S_out_sig_T = eq(rawB_S_isZero, UInt<1>(0h0)) node _rawB_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_S_out_sig_T) node _rawB_S_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_S_out_sig_T_3 = cat(_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2) connect rawB_S.sig, _rawB_S_out_sig_T_3 node _notSigNaNIn_invalidExc_S_div_T = and(rawA_S.isZero, rawB_S.isZero) node _notSigNaNIn_invalidExc_S_div_T_1 = and(rawA_S.isInf, rawB_S.isInf) node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) node _notSigNaNIn_invalidExc_S_sqrt_T = eq(rawB_S.isNaN, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(rawB_S.isZero, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, rawB_S.sign) node _majorExc_S_T = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) node _majorExc_S_T_2 = and(rawB_S.isNaN, _majorExc_S_T_1) node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) node _majorExc_S_T_4 = bits(rawA_S.sig, 51, 51) node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) node _majorExc_S_T_6 = and(rawA_S.isNaN, _majorExc_S_T_5) node _majorExc_S_T_7 = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) node _majorExc_S_T_9 = and(rawB_S.isNaN, _majorExc_S_T_8) node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) node _majorExc_S_T_12 = eq(rawA_S.isNaN, UInt<1>(0h0)) node _majorExc_S_T_13 = eq(rawA_S.isInf, UInt<1>(0h0)) node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) node _majorExc_S_T_15 = and(_majorExc_S_T_14, rawB_S.isZero) node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) node _isNaN_S_T = or(rawB_S.isNaN, notSigNaNIn_invalidExc_S_sqrt) node _isNaN_S_T_1 = or(rawA_S.isNaN, rawB_S.isNaN) node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) node _isInf_S_T = or(rawA_S.isInf, rawB_S.isZero) node isInf_S = mux(io.sqrtOp, rawB_S.isInf, _isInf_S_T) node _isZero_S_T = or(rawA_S.isZero, rawB_S.isInf) node isZero_S = mux(io.sqrtOp, rawB_S.isZero, _isZero_S_T) node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sign_S_T_1 = and(_sign_S_T, rawA_S.sign) node sign_S = xor(_sign_S_T_1, rawB_S.sign) node _specialCaseA_S_T = or(rawA_S.isNaN, rawA_S.isInf) node specialCaseA_S = or(_specialCaseA_S_T, rawA_S.isZero) node _specialCaseB_S_T = or(rawB_S.isNaN, rawB_S.isInf) node specialCaseB_S = or(_specialCaseB_S_T, rawB_S.isZero) node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) node _normalCase_S_sqrt_T = eq(specialCaseB_S, UInt<1>(0h0)) node _normalCase_S_sqrt_T_1 = eq(rawB_S.sign, UInt<1>(0h0)) node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node _sExpQuot_S_div_T = bits(rawB_S.sExp, 11, 11) node _sExpQuot_S_div_T_1 = bits(rawB_S.sExp, 10, 0) node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) node sExpQuot_S_div = add(rawA_S.sExp, _sExpQuot_S_div_T_4) node _sSatExpQuot_S_div_T = leq(asSInt(UInt<13>(0he00)), sExpQuot_S_div) node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 12, 9) node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 8, 0) node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) node _T = neq(cycleNum_A, UInt<1>(0h0)) node _T_1 = or(entering_PA_normalCase, _T) when _T_1 : node _cycleNum_A_T = mux(entering_PA_normalCase_div, UInt<2>(0h3), UInt<1>(0h0)) node _cycleNum_A_T_1 = mux(entering_PA_normalCase_sqrt, UInt<3>(0h6), UInt<1>(0h0)) node _cycleNum_A_T_2 = or(_cycleNum_A_T, _cycleNum_A_T_1) node _cycleNum_A_T_3 = eq(entering_PA_normalCase, UInt<1>(0h0)) node _cycleNum_A_T_4 = sub(cycleNum_A, UInt<1>(0h1)) node _cycleNum_A_T_5 = tail(_cycleNum_A_T_4, 1) node _cycleNum_A_T_6 = mux(_cycleNum_A_T_3, _cycleNum_A_T_5, UInt<1>(0h0)) node _cycleNum_A_T_7 = or(_cycleNum_A_T_2, _cycleNum_A_T_6) connect cycleNum_A, _cycleNum_A_T_7 node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>(0h6)) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>(0h5)) node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>(0h4)) node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) node cyc_A3 = eq(cycleNum_A, UInt<2>(0h3)) node cyc_A2 = eq(cycleNum_A, UInt<2>(0h2)) node cyc_A1 = eq(cycleNum_A, UInt<1>(0h1)) node _cyc_A3_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A3_div = and(cyc_A3, _cyc_A3_div_T) node _cyc_A2_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A2_div = and(cyc_A2, _cyc_A2_div_T) node _cyc_A1_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A1_div = and(cyc_A1, _cyc_A1_div_T) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) node _T_2 = neq(cycleNum_B, UInt<1>(0h0)) node _T_3 = or(cyc_A1, _T_2) when _T_3 : node _cycleNum_B_T = mux(sqrtOp_PA, UInt<4>(0ha), UInt<3>(0h6)) node _cycleNum_B_T_1 = sub(cycleNum_B, UInt<1>(0h1)) node _cycleNum_B_T_2 = tail(_cycleNum_B_T_1, 1) node _cycleNum_B_T_3 = mux(cyc_A1, _cycleNum_B_T, _cycleNum_B_T_2) connect cycleNum_B, _cycleNum_B_T_3 node cyc_B10_sqrt = eq(cycleNum_B, UInt<4>(0ha)) node cyc_B9_sqrt = eq(cycleNum_B, UInt<4>(0h9)) node cyc_B8_sqrt = eq(cycleNum_B, UInt<4>(0h8)) node cyc_B7_sqrt = eq(cycleNum_B, UInt<3>(0h7)) node cyc_B6 = eq(cycleNum_B, UInt<3>(0h6)) node cyc_B5 = eq(cycleNum_B, UInt<3>(0h5)) node cyc_B4 = eq(cycleNum_B, UInt<3>(0h4)) node cyc_B3 = eq(cycleNum_B, UInt<2>(0h3)) node cyc_B2 = eq(cycleNum_B, UInt<2>(0h2)) node cyc_B1 = eq(cycleNum_B, UInt<1>(0h1)) node _cyc_B6_div_T = and(cyc_B6, valid_PA) node _cyc_B6_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B6_div = and(_cyc_B6_div_T, _cyc_B6_div_T_1) node _cyc_B5_div_T = and(cyc_B5, valid_PA) node _cyc_B5_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B5_div = and(_cyc_B5_div_T, _cyc_B5_div_T_1) node _cyc_B4_div_T = and(cyc_B4, valid_PA) node _cyc_B4_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B4_div = and(_cyc_B4_div_T, _cyc_B4_div_T_1) node _cyc_B3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B3_div = and(cyc_B3, _cyc_B3_div_T) node _cyc_B2_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B2_div = and(cyc_B2, _cyc_B2_div_T) node _cyc_B1_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B1_div = and(cyc_B1, _cyc_B1_div_T) node _cyc_B6_sqrt_T = and(cyc_B6, valid_PB) node cyc_B6_sqrt = and(_cyc_B6_sqrt_T, sqrtOp_PB) node _cyc_B5_sqrt_T = and(cyc_B5, valid_PB) node cyc_B5_sqrt = and(_cyc_B5_sqrt_T, sqrtOp_PB) node _cyc_B4_sqrt_T = and(cyc_B4, valid_PB) node cyc_B4_sqrt = and(_cyc_B4_sqrt_T, sqrtOp_PB) node cyc_B3_sqrt = and(cyc_B3, sqrtOp_PB) node cyc_B2_sqrt = and(cyc_B2, sqrtOp_PB) node cyc_B1_sqrt = and(cyc_B1, sqrtOp_PB) node _T_4 = neq(cycleNum_C, UInt<1>(0h0)) node _T_5 = or(cyc_B1, _T_4) when _T_5 : node _cycleNum_C_T = mux(sqrtOp_PB, UInt<3>(0h6), UInt<3>(0h5)) node _cycleNum_C_T_1 = sub(cycleNum_C, UInt<1>(0h1)) node _cycleNum_C_T_2 = tail(_cycleNum_C_T_1, 1) node _cycleNum_C_T_3 = mux(cyc_B1, _cycleNum_C_T, _cycleNum_C_T_2) connect cycleNum_C, _cycleNum_C_T_3 node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>(0h6)) node cyc_C5 = eq(cycleNum_C, UInt<3>(0h5)) node cyc_C4 = eq(cycleNum_C, UInt<3>(0h4)) node cyc_C3 = eq(cycleNum_C, UInt<2>(0h3)) node cyc_C2 = eq(cycleNum_C, UInt<2>(0h2)) node cyc_C1 = eq(cycleNum_C, UInt<1>(0h1)) node _cyc_C5_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C5_div = and(cyc_C5, _cyc_C5_div_T) node _cyc_C4_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C4_div = and(cyc_C4, _cyc_C4_div_T) node _cyc_C3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C3_div = and(cyc_C3, _cyc_C3_div_T) node _cyc_C2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C2_div = and(cyc_C2, _cyc_C2_div_T) node _cyc_C1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C1_div = and(cyc_C1, _cyc_C1_div_T) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) node _T_6 = neq(cycleNum_E, UInt<1>(0h0)) node _T_7 = or(cyc_C1, _T_6) when _T_7 : node _cycleNum_E_T = sub(cycleNum_E, UInt<1>(0h1)) node _cycleNum_E_T_1 = tail(_cycleNum_E_T, 1) node _cycleNum_E_T_2 = mux(cyc_C1, UInt<3>(0h4), _cycleNum_E_T_1) connect cycleNum_E, _cycleNum_E_T_2 node cyc_E4 = eq(cycleNum_E, UInt<3>(0h4)) node cyc_E3 = eq(cycleNum_E, UInt<2>(0h3)) node cyc_E2 = eq(cycleNum_E, UInt<2>(0h2)) node cyc_E1 = eq(cycleNum_E, UInt<1>(0h1)) node _cyc_E4_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E4_div = and(cyc_E4, _cyc_E4_div_T) node _cyc_E3_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E3_div = and(cyc_E3, _cyc_E3_div_T) node _cyc_E2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E2_div = and(cyc_E2, _cyc_E2_div_T) node _cyc_E1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E1_div = and(cyc_E1, _cyc_E1_div_T) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node _entering_PA_T = eq(ready_PB, UInt<1>(0h0)) node _entering_PA_T_1 = or(valid_PA, _entering_PA_T) node _entering_PA_T_2 = and(cyc_S, _entering_PA_T_1) node entering_PA = or(entering_PA_normalCase, _entering_PA_T_2) node _T_8 = or(entering_PA, leaving_PA) when _T_8 : connect valid_PA, entering_PA when entering_PA : connect sqrtOp_PA, io.sqrtOp connect majorExc_PA, majorExc_S connect isNaN_PA, isNaN_S connect isInf_PA, isInf_S connect isZero_PA, isZero_S connect sign_PA, sign_S when entering_PA_normalCase : node _sExp_PA_T = mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div) connect sExp_PA, _sExp_PA_T node _fractB_PA_T = bits(rawB_S.sig, 51, 0) connect fractB_PA, _fractB_PA_T connect roundingMode_PA, io.roundingMode when entering_PA_normalCase_div : node _fractA_PA_T = bits(rawA_S.sig, 51, 0) connect fractA_PA, _fractA_PA_T node _normalCase_PA_T = eq(isNaN_PA, UInt<1>(0h0)) node _normalCase_PA_T_1 = eq(isInf_PA, UInt<1>(0h0)) node _normalCase_PA_T_2 = and(_normalCase_PA_T, _normalCase_PA_T_1) node _normalCase_PA_T_3 = eq(isZero_PA, UInt<1>(0h0)) node normalCase_PA = and(_normalCase_PA_T_2, _normalCase_PA_T_3) node sigA_PA = cat(UInt<1>(0h1), fractA_PA) node sigB_PA = cat(UInt<1>(0h1), fractB_PA) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) node _leaving_PA_T = and(valid_PA, valid_leaving_PA) connect leaving_PA, _leaving_PA_T node _ready_PA_T = eq(valid_PA, UInt<1>(0h0)) node _ready_PA_T_1 = or(_ready_PA_T, valid_leaving_PA) connect ready_PA, _ready_PA_T_1 node _entering_PB_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PB_S_T_1 = and(cyc_S, _entering_PB_S_T) node _entering_PB_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PB_S_T_3 = and(_entering_PB_S_T_1, _entering_PB_S_T_2) node _entering_PB_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PB_S_T_5 = eq(ready_PC, UInt<1>(0h0)) node _entering_PB_S_T_6 = and(_entering_PB_S_T_4, _entering_PB_S_T_5) node _entering_PB_S_T_7 = or(leaving_PB, _entering_PB_S_T_6) node entering_PB_S = and(_entering_PB_S_T_3, _entering_PB_S_T_7) node _entering_PB_normalCase_T = and(valid_PA, normalCase_PA) node entering_PB_normalCase = and(_entering_PB_normalCase_T, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) node _T_9 = or(entering_PB, leaving_PB) when _T_9 : connect valid_PB, entering_PB when entering_PB : node _sqrtOp_PB_T = mux(valid_PA, sqrtOp_PA, io.sqrtOp) connect sqrtOp_PB, _sqrtOp_PB_T node _majorExc_PB_T = mux(valid_PA, majorExc_PA, majorExc_S) connect majorExc_PB, _majorExc_PB_T node _isNaN_PB_T = mux(valid_PA, isNaN_PA, isNaN_S) connect isNaN_PB, _isNaN_PB_T node _isInf_PB_T = mux(valid_PA, isInf_PA, isInf_S) connect isInf_PB, _isInf_PB_T node _isZero_PB_T = mux(valid_PA, isZero_PA, isZero_S) connect isZero_PB, _isZero_PB_T node _sign_PB_T = mux(valid_PA, sign_PA, sign_S) connect sign_PB, _sign_PB_T when entering_PB_normalCase : connect sExp_PB, sExp_PA node _bit0FractA_PB_T = bits(fractA_PA, 0, 0) connect bit0FractA_PB, _bit0FractA_PB_T connect fractB_PB, fractB_PA node _roundingMode_PB_T = mux(valid_PA, roundingMode_PA, io.roundingMode) connect roundingMode_PB, _roundingMode_PB_T node _normalCase_PB_T = eq(isNaN_PB, UInt<1>(0h0)) node _normalCase_PB_T_1 = eq(isInf_PB, UInt<1>(0h0)) node _normalCase_PB_T_2 = and(_normalCase_PB_T, _normalCase_PB_T_1) node _normalCase_PB_T_3 = eq(isZero_PB, UInt<1>(0h0)) node normalCase_PB = and(_normalCase_PB_T_2, _normalCase_PB_T_3) node valid_leaving_PB = mux(normalCase_PB, cyc_C3, ready_PC) node _leaving_PB_T = and(valid_PB, valid_leaving_PB) connect leaving_PB, _leaving_PB_T node _ready_PB_T = eq(valid_PB, UInt<1>(0h0)) node _ready_PB_T_1 = or(_ready_PB_T, valid_leaving_PB) connect ready_PB, _ready_PB_T_1 node _entering_PC_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PC_S_T_1 = and(cyc_S, _entering_PC_S_T) node _entering_PC_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PC_S_T_3 = and(_entering_PC_S_T_1, _entering_PC_S_T_2) node _entering_PC_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PC_S_T_5 = and(_entering_PC_S_T_3, _entering_PC_S_T_4) node entering_PC_S = and(_entering_PC_S_T_5, ready_PC) node _entering_PC_normalCase_T = and(valid_PB, normalCase_PB) node entering_PC_normalCase = and(_entering_PC_normalCase_T, cyc_C3) node entering_PC = or(entering_PC_S, leaving_PB) node _T_10 = or(entering_PC, leaving_PC) when _T_10 : connect valid_PC, entering_PC when entering_PC : node _sqrtOp_PC_T = mux(valid_PB, sqrtOp_PB, io.sqrtOp) connect sqrtOp_PC, _sqrtOp_PC_T node _majorExc_PC_T = mux(valid_PB, majorExc_PB, majorExc_S) connect majorExc_PC, _majorExc_PC_T node _isNaN_PC_T = mux(valid_PB, isNaN_PB, isNaN_S) connect isNaN_PC, _isNaN_PC_T node _isInf_PC_T = mux(valid_PB, isInf_PB, isInf_S) connect isInf_PC, _isInf_PC_T node _isZero_PC_T = mux(valid_PB, isZero_PB, isZero_S) connect isZero_PC, _isZero_PC_T node _sign_PC_T = mux(valid_PB, sign_PB, sign_S) connect sign_PC, _sign_PC_T when entering_PC_normalCase : connect sExp_PC, sExp_PB connect bit0FractA_PC, bit0FractA_PB connect fractB_PC, fractB_PB node _roundingMode_PC_T = mux(valid_PB, roundingMode_PB, io.roundingMode) connect roundingMode_PC, _roundingMode_PC_T node _normalCase_PC_T = eq(isNaN_PC, UInt<1>(0h0)) node _normalCase_PC_T_1 = eq(isInf_PC, UInt<1>(0h0)) node _normalCase_PC_T_2 = and(_normalCase_PC_T, _normalCase_PC_T_1) node _normalCase_PC_T_3 = eq(isZero_PC, UInt<1>(0h0)) node normalCase_PC = and(_normalCase_PC_T_2, _normalCase_PC_T_3) node sigB_PC = cat(UInt<1>(0h1), fractB_PC) node _valid_leaving_PC_T = eq(normalCase_PC, UInt<1>(0h0)) node valid_leaving_PC = or(_valid_leaving_PC_T, cyc_E1) node _leaving_PC_T = and(valid_PC, valid_leaving_PC) connect leaving_PC, _leaving_PC_T node _ready_PC_T = eq(valid_PC, UInt<1>(0h0)) node _ready_PC_T_1 = or(_ready_PC_T, valid_leaving_PC) connect ready_PC, _ready_PC_T_1 node _io_inReady_div_T = eq(cyc_B7_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_1 = and(ready_PA, _io_inReady_div_T) node _io_inReady_div_T_2 = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_3 = and(_io_inReady_div_T_1, _io_inReady_div_T_2) node _io_inReady_div_T_4 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_5 = and(_io_inReady_div_T_3, _io_inReady_div_T_4) node _io_inReady_div_T_6 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_7 = and(_io_inReady_div_T_5, _io_inReady_div_T_6) node _io_inReady_div_T_8 = eq(cyc_B3, UInt<1>(0h0)) node _io_inReady_div_T_9 = and(_io_inReady_div_T_7, _io_inReady_div_T_8) node _io_inReady_div_T_10 = eq(cyc_B2, UInt<1>(0h0)) node _io_inReady_div_T_11 = and(_io_inReady_div_T_9, _io_inReady_div_T_10) node _io_inReady_div_T_12 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_13 = and(_io_inReady_div_T_11, _io_inReady_div_T_12) node _io_inReady_div_T_14 = eq(cyc_C5, UInt<1>(0h0)) node _io_inReady_div_T_15 = and(_io_inReady_div_T_13, _io_inReady_div_T_14) node _io_inReady_div_T_16 = eq(cyc_C4, UInt<1>(0h0)) node _io_inReady_div_T_17 = and(_io_inReady_div_T_15, _io_inReady_div_T_16) connect io.inReady_div, _io_inReady_div_T_17 node _io_inReady_sqrt_T = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_1 = and(ready_PA, _io_inReady_sqrt_T) node _io_inReady_sqrt_T_2 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_3 = and(_io_inReady_sqrt_T_1, _io_inReady_sqrt_T_2) node _io_inReady_sqrt_T_4 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_5 = and(_io_inReady_sqrt_T_3, _io_inReady_sqrt_T_4) node _io_inReady_sqrt_T_6 = eq(cyc_B2_div, UInt<1>(0h0)) node _io_inReady_sqrt_T_7 = and(_io_inReady_sqrt_T_5, _io_inReady_sqrt_T_6) node _io_inReady_sqrt_T_8 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_9 = and(_io_inReady_sqrt_T_7, _io_inReady_sqrt_T_8) connect io.inReady_sqrt, _io_inReady_sqrt_T_9 node _zFractB_A4_div_T = bits(rawB_S.sig, 51, 0) node zFractB_A4_div = mux(entering_PA_normalCase_div, _zFractB_A4_div_T, UInt<1>(0h0)) node _zLinPiece_0_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_0_A4_div_T_1 = eq(_zLinPiece_0_A4_div_T, UInt<1>(0h0)) node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, _zLinPiece_0_A4_div_T_1) node _zLinPiece_1_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_1_A4_div_T_1 = eq(_zLinPiece_1_A4_div_T, UInt<1>(0h1)) node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, _zLinPiece_1_A4_div_T_1) node _zLinPiece_2_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_2_A4_div_T_1 = eq(_zLinPiece_2_A4_div_T, UInt<2>(0h2)) node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, _zLinPiece_2_A4_div_T_1) node _zLinPiece_3_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_3_A4_div_T_1 = eq(_zLinPiece_3_A4_div_T, UInt<2>(0h3)) node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, _zLinPiece_3_A4_div_T_1) node _zLinPiece_4_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_4_A4_div_T_1 = eq(_zLinPiece_4_A4_div_T, UInt<3>(0h4)) node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, _zLinPiece_4_A4_div_T_1) node _zLinPiece_5_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_5_A4_div_T_1 = eq(_zLinPiece_5_A4_div_T, UInt<3>(0h5)) node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, _zLinPiece_5_A4_div_T_1) node _zLinPiece_6_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_6_A4_div_T_1 = eq(_zLinPiece_6_A4_div_T, UInt<3>(0h6)) node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, _zLinPiece_6_A4_div_T_1) node _zLinPiece_7_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_7_A4_div_T_1 = eq(_zLinPiece_7_A4_div_T, UInt<3>(0h7)) node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, _zLinPiece_7_A4_div_T_1) node _zK1_A4_div_T = mux(zLinPiece_0_A4_div, UInt<9>(0h1c7), UInt<1>(0h0)) node _zK1_A4_div_T_1 = mux(zLinPiece_1_A4_div, UInt<9>(0h16c), UInt<1>(0h0)) node _zK1_A4_div_T_2 = or(_zK1_A4_div_T, _zK1_A4_div_T_1) node _zK1_A4_div_T_3 = mux(zLinPiece_2_A4_div, UInt<9>(0h12a), UInt<1>(0h0)) node _zK1_A4_div_T_4 = or(_zK1_A4_div_T_2, _zK1_A4_div_T_3) node _zK1_A4_div_T_5 = mux(zLinPiece_3_A4_div, UInt<8>(0hf8), UInt<1>(0h0)) node _zK1_A4_div_T_6 = or(_zK1_A4_div_T_4, _zK1_A4_div_T_5) node _zK1_A4_div_T_7 = mux(zLinPiece_4_A4_div, UInt<8>(0hd2), UInt<1>(0h0)) node _zK1_A4_div_T_8 = or(_zK1_A4_div_T_6, _zK1_A4_div_T_7) node _zK1_A4_div_T_9 = mux(zLinPiece_5_A4_div, UInt<8>(0hb4), UInt<1>(0h0)) node _zK1_A4_div_T_10 = or(_zK1_A4_div_T_8, _zK1_A4_div_T_9) node _zK1_A4_div_T_11 = mux(zLinPiece_6_A4_div, UInt<8>(0h9c), UInt<1>(0h0)) node _zK1_A4_div_T_12 = or(_zK1_A4_div_T_10, _zK1_A4_div_T_11) node _zK1_A4_div_T_13 = mux(zLinPiece_7_A4_div, UInt<8>(0h89), UInt<1>(0h0)) node zK1_A4_div = or(_zK1_A4_div_T_12, _zK1_A4_div_T_13) node _zComplFractK0_A4_div_T = not(UInt<12>(0hfe3)) node _zComplFractK0_A4_div_T_1 = mux(zLinPiece_0_A4_div, _zComplFractK0_A4_div_T, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_2 = not(UInt<12>(0hc5d)) node _zComplFractK0_A4_div_T_3 = mux(zLinPiece_1_A4_div, _zComplFractK0_A4_div_T_2, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_4 = or(_zComplFractK0_A4_div_T_1, _zComplFractK0_A4_div_T_3) node _zComplFractK0_A4_div_T_5 = not(UInt<12>(0h98a)) node _zComplFractK0_A4_div_T_6 = mux(zLinPiece_2_A4_div, _zComplFractK0_A4_div_T_5, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_7 = or(_zComplFractK0_A4_div_T_4, _zComplFractK0_A4_div_T_6) node _zComplFractK0_A4_div_T_8 = not(UInt<12>(0h739)) node _zComplFractK0_A4_div_T_9 = mux(zLinPiece_3_A4_div, _zComplFractK0_A4_div_T_8, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_10 = or(_zComplFractK0_A4_div_T_7, _zComplFractK0_A4_div_T_9) node _zComplFractK0_A4_div_T_11 = not(UInt<12>(0h54b)) node _zComplFractK0_A4_div_T_12 = mux(zLinPiece_4_A4_div, _zComplFractK0_A4_div_T_11, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_13 = or(_zComplFractK0_A4_div_T_10, _zComplFractK0_A4_div_T_12) node _zComplFractK0_A4_div_T_14 = not(UInt<12>(0h3a9)) node _zComplFractK0_A4_div_T_15 = mux(zLinPiece_5_A4_div, _zComplFractK0_A4_div_T_14, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_16 = or(_zComplFractK0_A4_div_T_13, _zComplFractK0_A4_div_T_15) node _zComplFractK0_A4_div_T_17 = not(UInt<12>(0h242)) node _zComplFractK0_A4_div_T_18 = mux(zLinPiece_6_A4_div, _zComplFractK0_A4_div_T_17, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_19 = or(_zComplFractK0_A4_div_T_16, _zComplFractK0_A4_div_T_18) node _zComplFractK0_A4_div_T_20 = not(UInt<12>(0h10b)) node _zComplFractK0_A4_div_T_21 = mux(zLinPiece_7_A4_div, _zComplFractK0_A4_div_T_20, UInt<1>(0h0)) node zComplFractK0_A4_div = or(_zComplFractK0_A4_div_T_19, _zComplFractK0_A4_div_T_21) node _zFractB_A7_sqrt_T = bits(rawB_S.sig, 51, 0) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, _zFractB_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_0_A7_sqrt_T_1 = eq(_zQuadPiece_0_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_0_A7_sqrt_T_1) node _zQuadPiece_0_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_0_A7_sqrt_T_4 = eq(_zQuadPiece_0_A7_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A7_sqrt = and(_zQuadPiece_0_A7_sqrt_T_2, _zQuadPiece_0_A7_sqrt_T_4) node _zQuadPiece_1_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_1_A7_sqrt_T_1 = eq(_zQuadPiece_1_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_1_A7_sqrt_T_1) node _zQuadPiece_1_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node zQuadPiece_1_A7_sqrt = and(_zQuadPiece_1_A7_sqrt_T_2, _zQuadPiece_1_A7_sqrt_T_3) node _zQuadPiece_2_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_2_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_2_A7_sqrt_T) node _zQuadPiece_2_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_2_A7_sqrt_T_3 = eq(_zQuadPiece_2_A7_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A7_sqrt = and(_zQuadPiece_2_A7_sqrt_T_1, _zQuadPiece_2_A7_sqrt_T_3) node _zQuadPiece_3_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_3_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_3_A7_sqrt_T) node _zQuadPiece_3_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node zQuadPiece_3_A7_sqrt = and(_zQuadPiece_3_A7_sqrt_T_1, _zQuadPiece_3_A7_sqrt_T_2) node _zK2_A7_sqrt_T = mux(zQuadPiece_0_A7_sqrt, UInt<9>(0h1c8), UInt<1>(0h0)) node _zK2_A7_sqrt_T_1 = mux(zQuadPiece_1_A7_sqrt, UInt<8>(0hc1), UInt<1>(0h0)) node _zK2_A7_sqrt_T_2 = or(_zK2_A7_sqrt_T, _zK2_A7_sqrt_T_1) node _zK2_A7_sqrt_T_3 = mux(zQuadPiece_2_A7_sqrt, UInt<9>(0h143), UInt<1>(0h0)) node _zK2_A7_sqrt_T_4 = or(_zK2_A7_sqrt_T_2, _zK2_A7_sqrt_T_3) node _zK2_A7_sqrt_T_5 = mux(zQuadPiece_3_A7_sqrt, UInt<8>(0h89), UInt<1>(0h0)) node zK2_A7_sqrt = or(_zK2_A7_sqrt_T_4, _zK2_A7_sqrt_T_5) node _zComplK1_A7_sqrt_T = not(UInt<10>(0h3d0)) node _zComplK1_A7_sqrt_T_1 = mux(zQuadPiece_0_A7_sqrt, _zComplK1_A7_sqrt_T, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_2 = not(UInt<10>(0h220)) node _zComplK1_A7_sqrt_T_3 = mux(zQuadPiece_1_A7_sqrt, _zComplK1_A7_sqrt_T_2, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_4 = or(_zComplK1_A7_sqrt_T_1, _zComplK1_A7_sqrt_T_3) node _zComplK1_A7_sqrt_T_5 = not(UInt<10>(0h2b2)) node _zComplK1_A7_sqrt_T_6 = mux(zQuadPiece_2_A7_sqrt, _zComplK1_A7_sqrt_T_5, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_7 = or(_zComplK1_A7_sqrt_T_4, _zComplK1_A7_sqrt_T_6) node _zComplK1_A7_sqrt_T_8 = not(UInt<10>(0h181)) node _zComplK1_A7_sqrt_T_9 = mux(zQuadPiece_3_A7_sqrt, _zComplK1_A7_sqrt_T_8, UInt<1>(0h0)) node zComplK1_A7_sqrt = or(_zComplK1_A7_sqrt_T_7, _zComplK1_A7_sqrt_T_9) node _zQuadPiece_0_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_0_A6_sqrt_T_1 = eq(_zQuadPiece_0_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_0_A6_sqrt_T_1) node _zQuadPiece_0_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node _zQuadPiece_0_A6_sqrt_T_4 = eq(_zQuadPiece_0_A6_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A6_sqrt = and(_zQuadPiece_0_A6_sqrt_T_2, _zQuadPiece_0_A6_sqrt_T_4) node _zQuadPiece_1_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_1_A6_sqrt_T_1 = eq(_zQuadPiece_1_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_1_A6_sqrt_T_1) node _zQuadPiece_1_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node zQuadPiece_1_A6_sqrt = and(_zQuadPiece_1_A6_sqrt_T_2, _zQuadPiece_1_A6_sqrt_T_3) node _zQuadPiece_2_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_2_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_2_A6_sqrt_T) node _zQuadPiece_2_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node _zQuadPiece_2_A6_sqrt_T_3 = eq(_zQuadPiece_2_A6_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A6_sqrt = and(_zQuadPiece_2_A6_sqrt_T_1, _zQuadPiece_2_A6_sqrt_T_3) node _zQuadPiece_3_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_3_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_3_A6_sqrt_T) node _zQuadPiece_3_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node zQuadPiece_3_A6_sqrt = and(_zQuadPiece_3_A6_sqrt_T_1, _zQuadPiece_3_A6_sqrt_T_2) node _zComplFractK0_A6_sqrt_T = not(UInt<13>(0h1fe5)) node _zComplFractK0_A6_sqrt_T_1 = mux(zQuadPiece_0_A6_sqrt, _zComplFractK0_A6_sqrt_T, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_2 = not(UInt<13>(0h1435)) node _zComplFractK0_A6_sqrt_T_3 = mux(zQuadPiece_1_A6_sqrt, _zComplFractK0_A6_sqrt_T_2, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_4 = or(_zComplFractK0_A6_sqrt_T_1, _zComplFractK0_A6_sqrt_T_3) node _zComplFractK0_A6_sqrt_T_5 = not(UInt<13>(0hd2c)) node _zComplFractK0_A6_sqrt_T_6 = mux(zQuadPiece_2_A6_sqrt, _zComplFractK0_A6_sqrt_T_5, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_7 = or(_zComplFractK0_A6_sqrt_T_4, _zComplFractK0_A6_sqrt_T_6) node _zComplFractK0_A6_sqrt_T_8 = not(UInt<13>(0h4e8)) node _zComplFractK0_A6_sqrt_T_9 = mux(zQuadPiece_3_A6_sqrt, _zComplFractK0_A6_sqrt_T_8, UInt<1>(0h0)) node zComplFractK0_A6_sqrt = or(_zComplFractK0_A6_sqrt_T_7, _zComplFractK0_A6_sqrt_T_9) node _mulAdd9A_A_T = bits(zFractB_A4_div, 48, 40) node _mulAdd9A_A_T_1 = or(_mulAdd9A_A_T, zK2_A7_sqrt) node _mulAdd9A_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9A_A_T_3 = mux(_mulAdd9A_A_T_2, nextMulAdd9A_A, UInt<1>(0h0)) node mulAdd9A_A = or(_mulAdd9A_A_T_1, _mulAdd9A_A_T_3) node _mulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _mulAdd9B_A_T_1 = or(zK1_A4_div, _mulAdd9B_A_T) node _mulAdd9B_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9B_A_T_3 = mux(_mulAdd9B_A_T_2, nextMulAdd9B_A, UInt<1>(0h0)) node mulAdd9B_A = or(_mulAdd9B_A_T_1, _mulAdd9B_A_T_3) node _mulAdd9C_A_T = mux(entering_PA_normalCase_sqrt, UInt<10>(0h3ff), UInt<10>(0h0)) node _mulAdd9C_A_T_1 = cat(zComplK1_A7_sqrt, _mulAdd9C_A_T) node _mulAdd9C_A_T_2 = mux(cyc_A6_sqrt, UInt<6>(0h3f), UInt<6>(0h0)) node mulAdd9C_A_hi = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) node _mulAdd9C_A_T_3 = cat(mulAdd9C_A_hi, _mulAdd9C_A_T_2) node _mulAdd9C_A_T_4 = or(_mulAdd9C_A_T_1, _mulAdd9C_A_T_3) node _mulAdd9C_A_T_5 = mux(entering_PA_normalCase_div, UInt<8>(0hff), UInt<8>(0h0)) node mulAdd9C_A_hi_1 = cat(entering_PA_normalCase_div, zComplFractK0_A4_div) node _mulAdd9C_A_T_6 = cat(mulAdd9C_A_hi_1, _mulAdd9C_A_T_5) node _mulAdd9C_A_T_7 = or(_mulAdd9C_A_T_4, _mulAdd9C_A_T_6) node _mulAdd9C_A_T_8 = shl(fractR0_A, 10) node _mulAdd9C_A_T_9 = add(UInt<19>(0h40000), _mulAdd9C_A_T_8) node _mulAdd9C_A_T_10 = mux(cyc_A5_sqrt, _mulAdd9C_A_T_9, UInt<1>(0h0)) node _mulAdd9C_A_T_11 = or(_mulAdd9C_A_T_7, _mulAdd9C_A_T_10) node _mulAdd9C_A_T_12 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_13 = eq(_mulAdd9C_A_T_12, UInt<1>(0h0)) node _mulAdd9C_A_T_14 = and(cyc_A4_sqrt, _mulAdd9C_A_T_13) node _mulAdd9C_A_T_15 = mux(_mulAdd9C_A_T_14, UInt<11>(0h400), UInt<1>(0h0)) node _mulAdd9C_A_T_16 = or(_mulAdd9C_A_T_11, _mulAdd9C_A_T_15) node _mulAdd9C_A_T_17 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_18 = and(cyc_A4_sqrt, _mulAdd9C_A_T_17) node _mulAdd9C_A_T_19 = or(_mulAdd9C_A_T_18, cyc_A3_div) node _mulAdd9C_A_T_20 = bits(sigB_PA, 46, 26) node _mulAdd9C_A_T_21 = add(_mulAdd9C_A_T_20, UInt<11>(0h400)) node _mulAdd9C_A_T_22 = tail(_mulAdd9C_A_T_21, 1) node _mulAdd9C_A_T_23 = mux(_mulAdd9C_A_T_19, _mulAdd9C_A_T_22, UInt<1>(0h0)) node _mulAdd9C_A_T_24 = or(_mulAdd9C_A_T_16, _mulAdd9C_A_T_23) node _mulAdd9C_A_T_25 = or(cyc_A3_sqrt, cyc_A2) node _mulAdd9C_A_T_26 = mux(_mulAdd9C_A_T_25, partNegSigma0_A, UInt<1>(0h0)) node _mulAdd9C_A_T_27 = or(_mulAdd9C_A_T_24, _mulAdd9C_A_T_26) node _mulAdd9C_A_T_28 = shl(fractR0_A, 16) node _mulAdd9C_A_T_29 = mux(cyc_A1_sqrt, _mulAdd9C_A_T_28, UInt<1>(0h0)) node _mulAdd9C_A_T_30 = or(_mulAdd9C_A_T_27, _mulAdd9C_A_T_29) node _mulAdd9C_A_T_31 = shl(fractR0_A, 15) node _mulAdd9C_A_T_32 = mux(cyc_A1_div, _mulAdd9C_A_T_31, UInt<1>(0h0)) node mulAdd9C_A = or(_mulAdd9C_A_T_30, _mulAdd9C_A_T_32) node _loMulAdd9Out_A_T = mul(mulAdd9A_A, mulAdd9B_A) node _loMulAdd9Out_A_T_1 = bits(mulAdd9C_A, 17, 0) node loMulAdd9Out_A = add(_loMulAdd9Out_A_T, _loMulAdd9Out_A_T_1) node _mulAdd9Out_A_T = bits(loMulAdd9Out_A, 18, 18) node _mulAdd9Out_A_T_1 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_2 = add(_mulAdd9Out_A_T_1, UInt<1>(0h1)) node _mulAdd9Out_A_T_3 = tail(_mulAdd9Out_A_T_2, 1) node _mulAdd9Out_A_T_4 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_5 = mux(_mulAdd9Out_A_T, _mulAdd9Out_A_T_3, _mulAdd9Out_A_T_4) node _mulAdd9Out_A_T_6 = bits(loMulAdd9Out_A, 17, 0) node mulAdd9Out_A = cat(_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6) node _zFractR0_A6_sqrt_T = bits(mulAdd9Out_A, 19, 19) node _zFractR0_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zFractR0_A6_sqrt_T) node _zFractR0_A6_sqrt_T_2 = shr(mulAdd9Out_A, 10) node _zFractR0_A6_sqrt_T_3 = not(_zFractR0_A6_sqrt_T_2) node zFractR0_A6_sqrt = mux(_zFractR0_A6_sqrt_T_1, _zFractR0_A6_sqrt_T_3, UInt<1>(0h0)) node _sqrR0_A5_sqrt_T = bits(sExp_PA, 0, 0) node _sqrR0_A5_sqrt_T_1 = shl(mulAdd9Out_A, 1) node sqrR0_A5_sqrt = mux(_sqrR0_A5_sqrt_T, _sqrR0_A5_sqrt_T_1, mulAdd9Out_A) node _zFractR0_A4_div_T = bits(mulAdd9Out_A, 20, 20) node _zFractR0_A4_div_T_1 = and(entering_PA_normalCase_div, _zFractR0_A4_div_T) node _zFractR0_A4_div_T_2 = shr(mulAdd9Out_A, 11) node _zFractR0_A4_div_T_3 = not(_zFractR0_A4_div_T_2) node zFractR0_A4_div = mux(_zFractR0_A4_div_T_1, _zFractR0_A4_div_T_3, UInt<1>(0h0)) node _zSigma0_A2_T = bits(mulAdd9Out_A, 11, 11) node _zSigma0_A2_T_1 = and(cyc_A2, _zSigma0_A2_T) node _zSigma0_A2_T_2 = shr(mulAdd9Out_A, 2) node _zSigma0_A2_T_3 = not(_zSigma0_A2_T_2) node zSigma0_A2 = mux(_zSigma0_A2_T_1, _zSigma0_A2_T_3, UInt<1>(0h0)) node _r1_A1_T = shr(mulAdd9Out_A, 10) node _r1_A1_T_1 = shr(mulAdd9Out_A, 9) node _r1_A1_T_2 = mux(sqrtOp_PA, _r1_A1_T, _r1_A1_T_1) node r1_A1 = or(UInt<16>(0h8000), _r1_A1_T_2) node _ER1_A1_sqrt_T = bits(sExp_PA, 0, 0) node _ER1_A1_sqrt_T_1 = shl(r1_A1, 1) node ER1_A1_sqrt = mux(_ER1_A1_sqrt_T, _ER1_A1_sqrt_T_1, r1_A1) node _T_11 = or(cyc_A6_sqrt, entering_PA_normalCase_div) when _T_11 : node _fractR0_A_T = or(zFractR0_A6_sqrt, zFractR0_A4_div) connect fractR0_A, _fractR0_A_T when cyc_A5_sqrt : node _hiSqrR0_A_sqrt_T = shr(sqrR0_A5_sqrt, 10) connect hiSqrR0_A_sqrt, _hiSqrR0_A_sqrt_T node _T_12 = or(cyc_A4_sqrt, cyc_A3) when _T_12 : node _partNegSigma0_A_T = shr(mulAdd9Out_A, 9) node _partNegSigma0_A_T_1 = mux(cyc_A4_sqrt, mulAdd9Out_A, _partNegSigma0_A_T) connect partNegSigma0_A, _partNegSigma0_A_T_1 node _T_13 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_14 = or(_T_13, cyc_A5_sqrt) node _T_15 = or(_T_14, cyc_A4) node _T_16 = or(_T_15, cyc_A3) node _T_17 = or(_T_16, cyc_A2) when _T_17 : node _nextMulAdd9A_A_T = not(mulAdd9Out_A) node _nextMulAdd9A_A_T_1 = shr(_nextMulAdd9A_A_T, 11) node _nextMulAdd9A_A_T_2 = mux(entering_PA_normalCase_sqrt, _nextMulAdd9A_A_T_1, UInt<1>(0h0)) node _nextMulAdd9A_A_T_3 = or(_nextMulAdd9A_A_T_2, zFractR0_A6_sqrt) node _nextMulAdd9A_A_T_4 = bits(sigB_PA, 43, 35) node _nextMulAdd9A_A_T_5 = mux(cyc_A4_sqrt, _nextMulAdd9A_A_T_4, UInt<1>(0h0)) node _nextMulAdd9A_A_T_6 = or(_nextMulAdd9A_A_T_3, _nextMulAdd9A_A_T_5) node _nextMulAdd9A_A_T_7 = bits(zFractB_A4_div, 43, 35) node _nextMulAdd9A_A_T_8 = or(_nextMulAdd9A_A_T_6, _nextMulAdd9A_A_T_7) node _nextMulAdd9A_A_T_9 = or(cyc_A5_sqrt, cyc_A3) node _nextMulAdd9A_A_T_10 = bits(sigB_PA, 52, 44) node _nextMulAdd9A_A_T_11 = mux(_nextMulAdd9A_A_T_9, _nextMulAdd9A_A_T_10, UInt<1>(0h0)) node _nextMulAdd9A_A_T_12 = or(_nextMulAdd9A_A_T_8, _nextMulAdd9A_A_T_11) node _nextMulAdd9A_A_T_13 = or(_nextMulAdd9A_A_T_12, zSigma0_A2) connect nextMulAdd9A_A, _nextMulAdd9A_A_T_13 node _T_18 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_19 = or(_T_18, cyc_A5_sqrt) node _T_20 = or(_T_19, cyc_A4) node _T_21 = or(_T_20, cyc_A2) when _T_21 : node _nextMulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _nextMulAdd9B_A_T_1 = or(_nextMulAdd9B_A_T, zFractR0_A6_sqrt) node _nextMulAdd9B_A_T_2 = bits(sqrR0_A5_sqrt, 9, 1) node _nextMulAdd9B_A_T_3 = mux(cyc_A5_sqrt, _nextMulAdd9B_A_T_2, UInt<1>(0h0)) node _nextMulAdd9B_A_T_4 = or(_nextMulAdd9B_A_T_1, _nextMulAdd9B_A_T_3) node _nextMulAdd9B_A_T_5 = or(_nextMulAdd9B_A_T_4, zFractR0_A4_div) node _nextMulAdd9B_A_T_6 = bits(hiSqrR0_A_sqrt, 8, 0) node _nextMulAdd9B_A_T_7 = mux(cyc_A4_sqrt, _nextMulAdd9B_A_T_6, UInt<1>(0h0)) node _nextMulAdd9B_A_T_8 = or(_nextMulAdd9B_A_T_5, _nextMulAdd9B_A_T_7) node _nextMulAdd9B_A_T_9 = bits(fractR0_A, 8, 1) node _nextMulAdd9B_A_T_10 = cat(UInt<1>(0h1), _nextMulAdd9B_A_T_9) node _nextMulAdd9B_A_T_11 = mux(cyc_A2, _nextMulAdd9B_A_T_10, UInt<1>(0h0)) node _nextMulAdd9B_A_T_12 = or(_nextMulAdd9B_A_T_8, _nextMulAdd9B_A_T_11) connect nextMulAdd9B_A, _nextMulAdd9B_A_T_12 when cyc_A1_sqrt : connect ER1_B_sqrt, ER1_A1_sqrt node _io_latchMulAddA_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddA_0_T_1 = or(_io_latchMulAddA_0_T, cyc_B6_div) node _io_latchMulAddA_0_T_2 = or(_io_latchMulAddA_0_T_1, cyc_B4) node _io_latchMulAddA_0_T_3 = or(_io_latchMulAddA_0_T_2, cyc_B3) node _io_latchMulAddA_0_T_4 = or(_io_latchMulAddA_0_T_3, cyc_C6_sqrt) node _io_latchMulAddA_0_T_5 = or(_io_latchMulAddA_0_T_4, cyc_C4) node _io_latchMulAddA_0_T_6 = or(_io_latchMulAddA_0_T_5, cyc_C1) connect io.latchMulAddA_0, _io_latchMulAddA_0_T_6 node _io_mulAddA_0_T = shl(ER1_A1_sqrt, 36) node _io_mulAddA_0_T_1 = mux(cyc_A1_sqrt, _io_mulAddA_0_T, UInt<1>(0h0)) node _io_mulAddA_0_T_2 = or(cyc_B7_sqrt, cyc_A1_div) node _io_mulAddA_0_T_3 = mux(_io_mulAddA_0_T_2, sigB_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_4 = or(_io_mulAddA_0_T_1, _io_mulAddA_0_T_3) node _io_mulAddA_0_T_5 = mux(cyc_B6_div, sigA_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_6 = or(_io_mulAddA_0_T_4, _io_mulAddA_0_T_5) node _io_mulAddA_0_T_7 = bits(zSigma1_B4, 45, 12) node _io_mulAddA_0_T_8 = or(_io_mulAddA_0_T_6, _io_mulAddA_0_T_7) node _io_mulAddA_0_T_9 = or(cyc_B3, cyc_C6_sqrt) node _io_mulAddA_0_T_10 = bits(sigXNU_B3_CX, 57, 12) node _io_mulAddA_0_T_11 = mux(_io_mulAddA_0_T_9, _io_mulAddA_0_T_10, UInt<1>(0h0)) node _io_mulAddA_0_T_12 = or(_io_mulAddA_0_T_8, _io_mulAddA_0_T_11) node _io_mulAddA_0_T_13 = bits(sigXN_C, 57, 25) node _io_mulAddA_0_T_14 = shl(_io_mulAddA_0_T_13, 13) node _io_mulAddA_0_T_15 = mux(cyc_C4_div, _io_mulAddA_0_T_14, UInt<1>(0h0)) node _io_mulAddA_0_T_16 = or(_io_mulAddA_0_T_12, _io_mulAddA_0_T_15) node _io_mulAddA_0_T_17 = shl(u_C_sqrt, 15) node _io_mulAddA_0_T_18 = mux(cyc_C4_sqrt, _io_mulAddA_0_T_17, UInt<1>(0h0)) node _io_mulAddA_0_T_19 = or(_io_mulAddA_0_T_16, _io_mulAddA_0_T_18) node _io_mulAddA_0_T_20 = mux(cyc_C1_div, sigB_PC, UInt<1>(0h0)) node _io_mulAddA_0_T_21 = or(_io_mulAddA_0_T_19, _io_mulAddA_0_T_20) node _io_mulAddA_0_T_22 = or(_io_mulAddA_0_T_21, zComplSigT_C1_sqrt) connect io.mulAddA_0, _io_mulAddA_0_T_22 node _io_latchMulAddB_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddB_0_T_1 = or(_io_latchMulAddB_0_T, cyc_B6_sqrt) node _io_latchMulAddB_0_T_2 = or(_io_latchMulAddB_0_T_1, cyc_B4) node _io_latchMulAddB_0_T_3 = or(_io_latchMulAddB_0_T_2, cyc_C6_sqrt) node _io_latchMulAddB_0_T_4 = or(_io_latchMulAddB_0_T_3, cyc_C4) node _io_latchMulAddB_0_T_5 = or(_io_latchMulAddB_0_T_4, cyc_C1) connect io.latchMulAddB_0, _io_latchMulAddB_0_T_5 node _io_mulAddB_0_T = shl(r1_A1, 36) node _io_mulAddB_0_T_1 = mux(cyc_A1, _io_mulAddB_0_T, UInt<1>(0h0)) node _io_mulAddB_0_T_2 = shl(ESqrR1_B_sqrt, 19) node _io_mulAddB_0_T_3 = mux(cyc_B7_sqrt, _io_mulAddB_0_T_2, UInt<1>(0h0)) node _io_mulAddB_0_T_4 = or(_io_mulAddB_0_T_1, _io_mulAddB_0_T_3) node _io_mulAddB_0_T_5 = shl(ER1_B_sqrt, 36) node _io_mulAddB_0_T_6 = mux(cyc_B6_sqrt, _io_mulAddB_0_T_5, UInt<1>(0h0)) node _io_mulAddB_0_T_7 = or(_io_mulAddB_0_T_4, _io_mulAddB_0_T_6) node _io_mulAddB_0_T_8 = or(_io_mulAddB_0_T_7, zSigma1_B4) node _io_mulAddB_0_T_9 = bits(sqrSigma1_C, 30, 1) node _io_mulAddB_0_T_10 = mux(cyc_C6_sqrt, _io_mulAddB_0_T_9, UInt<1>(0h0)) node _io_mulAddB_0_T_11 = or(_io_mulAddB_0_T_8, _io_mulAddB_0_T_10) node _io_mulAddB_0_T_12 = mux(cyc_C4, sqrSigma1_C, UInt<1>(0h0)) node _io_mulAddB_0_T_13 = or(_io_mulAddB_0_T_11, _io_mulAddB_0_T_12) node _io_mulAddB_0_T_14 = or(_io_mulAddB_0_T_13, zComplSigT_C1) connect io.mulAddB_0, _io_mulAddB_0_T_14 node _io_usingMulAdd_T = or(cyc_A4, cyc_A3_div) node _io_usingMulAdd_T_1 = or(_io_usingMulAdd_T, cyc_A1_div) node _io_usingMulAdd_T_2 = or(_io_usingMulAdd_T_1, cyc_B10_sqrt) node _io_usingMulAdd_T_3 = or(_io_usingMulAdd_T_2, cyc_B9_sqrt) node _io_usingMulAdd_T_4 = or(_io_usingMulAdd_T_3, cyc_B7_sqrt) node _io_usingMulAdd_T_5 = or(_io_usingMulAdd_T_4, cyc_B6) node _io_usingMulAdd_T_6 = or(_io_usingMulAdd_T_5, cyc_B5_sqrt) node _io_usingMulAdd_T_7 = or(_io_usingMulAdd_T_6, cyc_B3_sqrt) node _io_usingMulAdd_T_8 = or(_io_usingMulAdd_T_7, cyc_B2_div) node _io_usingMulAdd_T_9 = or(_io_usingMulAdd_T_8, cyc_B1_sqrt) node _io_usingMulAdd_T_10 = or(_io_usingMulAdd_T_9, cyc_C4) node _io_usingMulAdd_T_11 = or(cyc_A3, cyc_A2_div) node _io_usingMulAdd_T_12 = or(_io_usingMulAdd_T_11, cyc_B9_sqrt) node _io_usingMulAdd_T_13 = or(_io_usingMulAdd_T_12, cyc_B8_sqrt) node _io_usingMulAdd_T_14 = or(_io_usingMulAdd_T_13, cyc_B6) node _io_usingMulAdd_T_15 = or(_io_usingMulAdd_T_14, cyc_B5) node _io_usingMulAdd_T_16 = or(_io_usingMulAdd_T_15, cyc_B4_sqrt) node _io_usingMulAdd_T_17 = or(_io_usingMulAdd_T_16, cyc_B2_sqrt) node _io_usingMulAdd_T_18 = or(_io_usingMulAdd_T_17, cyc_B1_div) node _io_usingMulAdd_T_19 = or(_io_usingMulAdd_T_18, cyc_C6_sqrt) node _io_usingMulAdd_T_20 = or(_io_usingMulAdd_T_19, cyc_C3) node _io_usingMulAdd_T_21 = or(cyc_A2, cyc_A1_div) node _io_usingMulAdd_T_22 = or(_io_usingMulAdd_T_21, cyc_B8_sqrt) node _io_usingMulAdd_T_23 = or(_io_usingMulAdd_T_22, cyc_B7_sqrt) node _io_usingMulAdd_T_24 = or(_io_usingMulAdd_T_23, cyc_B5) node _io_usingMulAdd_T_25 = or(_io_usingMulAdd_T_24, cyc_B4) node _io_usingMulAdd_T_26 = or(_io_usingMulAdd_T_25, cyc_B3_sqrt) node _io_usingMulAdd_T_27 = or(_io_usingMulAdd_T_26, cyc_B1_sqrt) node _io_usingMulAdd_T_28 = or(_io_usingMulAdd_T_27, cyc_C5) node _io_usingMulAdd_T_29 = or(_io_usingMulAdd_T_28, cyc_C2) node _io_usingMulAdd_T_30 = or(io.latchMulAddA_0, cyc_B6) node _io_usingMulAdd_T_31 = or(_io_usingMulAdd_T_30, cyc_B2_sqrt) node io_usingMulAdd_lo = cat(_io_usingMulAdd_T_29, _io_usingMulAdd_T_31) node io_usingMulAdd_hi = cat(_io_usingMulAdd_T_10, _io_usingMulAdd_T_20) node _io_usingMulAdd_T_32 = cat(io_usingMulAdd_hi, io_usingMulAdd_lo) connect io.usingMulAdd, _io_usingMulAdd_T_32 node _io_mulAddC_2_T = shl(sigX1_B, 47) node _io_mulAddC_2_T_1 = mux(cyc_B1, _io_mulAddC_2_T, UInt<1>(0h0)) node _io_mulAddC_2_T_2 = shl(sigX1_B, 46) node _io_mulAddC_2_T_3 = mux(cyc_C6_sqrt, _io_mulAddC_2_T_2, UInt<1>(0h0)) node _io_mulAddC_2_T_4 = or(_io_mulAddC_2_T_1, _io_mulAddC_2_T_3) node _io_mulAddC_2_T_5 = or(cyc_C4_sqrt, cyc_C2) node _io_mulAddC_2_T_6 = shl(sigXN_C, 47) node _io_mulAddC_2_T_7 = mux(_io_mulAddC_2_T_5, _io_mulAddC_2_T_6, UInt<1>(0h0)) node _io_mulAddC_2_T_8 = or(_io_mulAddC_2_T_4, _io_mulAddC_2_T_7) node _io_mulAddC_2_T_9 = eq(E_E_div, UInt<1>(0h0)) node _io_mulAddC_2_T_10 = and(cyc_E3_div, _io_mulAddC_2_T_9) node _io_mulAddC_2_T_11 = shl(bit0FractA_PC, 53) node _io_mulAddC_2_T_12 = mux(_io_mulAddC_2_T_10, _io_mulAddC_2_T_11, UInt<1>(0h0)) node _io_mulAddC_2_T_13 = or(_io_mulAddC_2_T_8, _io_mulAddC_2_T_12) node _io_mulAddC_2_T_14 = bits(sExp_PC, 0, 0) node _io_mulAddC_2_T_15 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_16 = shl(_io_mulAddC_2_T_15, 1) node _io_mulAddC_2_T_17 = bits(sigB_PC, 1, 1) node _io_mulAddC_2_T_18 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_19 = xor(_io_mulAddC_2_T_17, _io_mulAddC_2_T_18) node _io_mulAddC_2_T_20 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_21 = cat(_io_mulAddC_2_T_19, _io_mulAddC_2_T_20) node _io_mulAddC_2_T_22 = mux(_io_mulAddC_2_T_14, _io_mulAddC_2_T_16, _io_mulAddC_2_T_21) node _io_mulAddC_2_T_23 = bits(sigT_E, 0, 0) node _io_mulAddC_2_T_24 = not(_io_mulAddC_2_T_23) node _io_mulAddC_2_T_25 = shl(_io_mulAddC_2_T_24, 1) node _io_mulAddC_2_T_26 = xor(_io_mulAddC_2_T_22, _io_mulAddC_2_T_25) node _io_mulAddC_2_T_27 = shl(_io_mulAddC_2_T_26, 54) node _io_mulAddC_2_T_28 = mux(cyc_E3_sqrt, _io_mulAddC_2_T_27, UInt<1>(0h0)) node _io_mulAddC_2_T_29 = or(_io_mulAddC_2_T_13, _io_mulAddC_2_T_28) connect io.mulAddC_2, _io_mulAddC_2_T_29 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) node _zSigma1_B4_T = bits(io.mulAddResult_3, 90, 45) node _zSigma1_B4_T_1 = not(_zSigma1_B4_T) node _zSigma1_B4_T_2 = mux(cyc_B4, _zSigma1_B4_T_1, UInt<1>(0h0)) connect zSigma1_B4, _zSigma1_B4_T_2 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) node _sigXNU_B3_CX_T = bits(io.mulAddResult_3, 104, 47) connect sigXNU_B3_CX, _sigXNU_B3_CX_T node _E_C1_div_T = bits(io.mulAddResult_3, 104, 104) node E_C1_div = eq(_E_C1_div_T, UInt<1>(0h0)) node _zComplSigT_C1_T = eq(E_C1_div, UInt<1>(0h0)) node _zComplSigT_C1_T_1 = and(cyc_C1_div, _zComplSigT_C1_T) node _zComplSigT_C1_T_2 = or(_zComplSigT_C1_T_1, cyc_C1_sqrt) node _zComplSigT_C1_T_3 = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_T_4 = not(_zComplSigT_C1_T_3) node _zComplSigT_C1_T_5 = mux(_zComplSigT_C1_T_2, _zComplSigT_C1_T_4, UInt<1>(0h0)) node _zComplSigT_C1_T_6 = and(cyc_C1_div, E_C1_div) node _zComplSigT_C1_T_7 = bits(io.mulAddResult_3, 102, 50) node _zComplSigT_C1_T_8 = not(_zComplSigT_C1_T_7) node _zComplSigT_C1_T_9 = mux(_zComplSigT_C1_T_6, _zComplSigT_C1_T_8, UInt<1>(0h0)) node _zComplSigT_C1_T_10 = or(_zComplSigT_C1_T_5, _zComplSigT_C1_T_9) connect zComplSigT_C1, _zComplSigT_C1_T_10 node _zComplSigT_C1_sqrt_T = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_sqrt_T_1 = not(_zComplSigT_C1_sqrt_T) node _zComplSigT_C1_sqrt_T_2 = mux(cyc_C1_sqrt, _zComplSigT_C1_sqrt_T_1, UInt<1>(0h0)) connect zComplSigT_C1_sqrt, _zComplSigT_C1_sqrt_T_2 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : connect ESqrR1_B_sqrt, ESqrR1_B8_sqrt when cyc_B3 : connect sigX1_B, sigXNU_B3_CX when cyc_B1 : connect sqrSigma1_C, sqrSigma1_B1 node _T_22 = or(cyc_C6_sqrt, cyc_C5_div) node _T_23 = or(_T_22, cyc_C3_sqrt) when _T_23 : connect sigXN_C, sigXNU_B3_CX when cyc_C5_sqrt : node _u_C_sqrt_T = bits(sigXNU_B3_CX, 56, 26) connect u_C_sqrt, _u_C_sqrt_T when cyc_C1 : connect E_E_div, E_C1_div connect sigT_E, sigT_C1 when cyc_E2 : node _isNegRemT_E_T = bits(remT_E2, 55, 55) node _isNegRemT_E_T_1 = bits(remT_E2, 53, 53) node _isNegRemT_E_T_2 = mux(sqrtOp_PC, _isNegRemT_E_T, _isNegRemT_E_T_1) connect isNegRemT_E, _isNegRemT_E_T_2 node _isZeroRemT_E_T = bits(remT_E2, 53, 0) node _isZeroRemT_E_T_1 = eq(_isZeroRemT_E_T, UInt<1>(0h0)) node _isZeroRemT_E_T_2 = eq(sqrtOp_PC, UInt<1>(0h0)) node _isZeroRemT_E_T_3 = bits(remT_E2, 55, 54) node _isZeroRemT_E_T_4 = eq(_isZeroRemT_E_T_3, UInt<1>(0h0)) node _isZeroRemT_E_T_5 = or(_isZeroRemT_E_T_2, _isZeroRemT_E_T_4) node _isZeroRemT_E_T_6 = and(_isZeroRemT_E_T_1, _isZeroRemT_E_T_5) connect isZeroRemT_E, _isZeroRemT_E_T_6 node _trueLtX_E1_T = eq(isNegRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_2 = and(_trueLtX_E1_T, _trueLtX_E1_T_1) node trueLtX_E1 = mux(sqrtOp_PC, _trueLtX_E1_T_2, isNegRemT_E) node _sExpP1_PC_T = add(sExp_PC, asSInt(UInt<2>(0h1))) node _sExpP1_PC_T_1 = tail(_sExpP1_PC_T, 1) node sExpP1_PC = asSInt(_sExpP1_PC_T_1) node sigTP1_E = add(sigT_E, UInt<1>(0h1)) node _io_rawOutValid_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOutValid_div_T_1 = and(leaving_PC, _io_rawOutValid_div_T) connect io.rawOutValid_div, _io_rawOutValid_div_T_1 node _io_rawOutValid_sqrt_T = and(leaving_PC, sqrtOp_PC) connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T connect io.roundingModeOut, roundingMode_PC node _io_invalidExc_T = and(majorExc_PC, isNaN_PC) connect io.invalidExc, _io_invalidExc_T node _io_infiniteExc_T = eq(isNaN_PC, UInt<1>(0h0)) node _io_infiniteExc_T_1 = and(majorExc_PC, _io_infiniteExc_T) connect io.infiniteExc, _io_infiniteExc_T_1 connect io.rawOut.isNaN, isNaN_PC connect io.rawOut.isInf, isInf_PC connect io.rawOut.isZero, isZero_PC connect io.rawOut.sign, sign_PC node _io_rawOut_sExp_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_1 = and(_io_rawOut_sExp_T, E_E_div) node _io_rawOut_sExp_T_2 = mux(_io_rawOut_sExp_T_1, sExp_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_3 = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_4 = eq(E_E_div, UInt<1>(0h0)) node _io_rawOut_sExp_T_5 = and(_io_rawOut_sExp_T_3, _io_rawOut_sExp_T_4) node _io_rawOut_sExp_T_6 = mux(_io_rawOut_sExp_T_5, sExpP1_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_7 = or(_io_rawOut_sExp_T_2, _io_rawOut_sExp_T_6) node _io_rawOut_sExp_T_8 = asSInt(_io_rawOut_sExp_T_7) node _io_rawOut_sExp_T_9 = shr(sExp_PC, 1) node _io_rawOut_sExp_T_10 = add(_io_rawOut_sExp_T_9, asSInt(UInt<12>(0h400))) node _io_rawOut_sExp_T_11 = mux(sqrtOp_PC, _io_rawOut_sExp_T_10, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_12 = or(_io_rawOut_sExp_T_8, _io_rawOut_sExp_T_11) node _io_rawOut_sExp_T_13 = asSInt(_io_rawOut_sExp_T_12) connect io.rawOut.sExp, _io_rawOut_sExp_T_13 node _io_rawOut_sig_T = mux(trueLtX_E1, sigT_E, sigTP1_E) node _io_rawOut_sig_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _io_rawOut_sig_T_2 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_1) connect io.rawOut.sig, _io_rawOut_sig_T_2	module DivSqrtRecF64ToRaw_mulAddZ31( // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_invalidExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_infiniteExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isNaN, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isInf, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isZero, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_sign, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [12:0] io_rawOut_sExp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [55:0] io_rawOut_sig // @[DivSqrtRecF64_mulAddZ31.scala:53:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [11:0] _zComplFractK0_A4_div_T = 12'h1C; // @[DivSqrtRecF64_mulAddZ31.scala:460:33] wire [11:0] _zComplFractK0_A4_div_T_2 = 12'h3A2; // @[DivSqrtRecF64_mulAddZ31.scala:461:33] wire [11:0] _zComplFractK0_A4_div_T_5 = 12'h675; // @[DivSqrtRecF64_mulAddZ31.scala:462:33] wire [11:0] _zComplFractK0_A4_div_T_8 = 12'h8C6; // @[DivSqrtRecF64_mulAddZ31.scala:463:33] wire [11:0] _zComplFractK0_A4_div_T_11 = 12'hAB4; // @[DivSqrtRecF64_mulAddZ31.scala:464:33] wire [11:0] _zComplFractK0_A4_div_T_14 = 12'hC56; // @[DivSqrtRecF64_mulAddZ31.scala:465:33] wire [11:0] _zComplFractK0_A4_div_T_17 = 12'hDBD; // @[DivSqrtRecF64_mulAddZ31.scala:466:33] wire [11:0] _zComplFractK0_A4_div_T_20 = 12'hEF4; // @[DivSqrtRecF64_mulAddZ31.scala:467:33] wire [9:0] _zComplK1_A7_sqrt_T = 10'h2F; // @[DivSqrtRecF64_mulAddZ31.scala:484:35] wire [9:0] _zComplK1_A7_sqrt_T_2 = 10'h1DF; // @[DivSqrtRecF64_mulAddZ31.scala:485:35] wire [9:0] _zComplK1_A7_sqrt_T_5 = 10'h14D; // @[DivSqrtRecF64_mulAddZ31.scala:486:35] wire [9:0] _zComplK1_A7_sqrt_T_8 = 10'h27E; // @[DivSqrtRecF64_mulAddZ31.scala:487:35] wire [12:0] _zComplFractK0_A6_sqrt_T = 13'h1A; // @[DivSqrtRecF64_mulAddZ31.scala:494:35] wire [12:0] _zComplFractK0_A6_sqrt_T_2 = 13'hBCA; // @[DivSqrtRecF64_mulAddZ31.scala:495:35] wire [12:0] _zComplFractK0_A6_sqrt_T_5 = 13'h12D3; // @[DivSqrtRecF64_mulAddZ31.scala:496:35] wire _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:432:22] wire [12:0] _zComplFractK0_A6_sqrt_T_8 = 13'h1B17; // @[DivSqrtRecF64_mulAddZ31.scala:497:35] wire _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:435:26] wire [3:0] _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] wire _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:578:35] wire [53:0] _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:588:63] wire _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:592:35] wire [53:0] _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:599:51] wire [104:0] _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:622:62] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:699:39] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:700:39] wire _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:702:40] wire _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:703:40] wire [12:0] _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] wire [55:0] _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:712:56] wire io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] reg [2:0] cycleNum_A; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] reg [3:0] cycleNum_B; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] reg [2:0] cycleNum_C; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] reg [2:0] cycleNum_E; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] reg valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] reg sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30] reg majorExc_PA; // @[DivSqrtRecF64_mulAddZ31.scala:93:30] reg isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30] reg isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30] reg isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30] reg sign_PA; // @[DivSqrtRecF64_mulAddZ31.scala:98:30] reg [12:0] sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30] reg [51:0] fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30] reg [51:0] fractA_PA; // @[DivSqrtRecF64_mulAddZ31.scala:101:30] reg [2:0] roundingMode_PA; // @[DivSqrtRecF64_mulAddZ31.scala:102:30] reg valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] reg sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30] reg majorExc_PB; // @[DivSqrtRecF64_mulAddZ31.scala:106:30] reg isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30] reg isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30] reg isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30] reg sign_PB; // @[DivSqrtRecF64_mulAddZ31.scala:111:30] reg [12:0] sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30] reg bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30] reg [51:0] fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30] reg [2:0] roundingMode_PB; // @[DivSqrtRecF64_mulAddZ31.scala:115:30] reg valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] reg sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30] reg majorExc_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30] reg isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30] assign io_rawOut_isNaN_0 = isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :121:30] reg isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30] assign io_rawOut_isInf_0 = isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :122:30] reg isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30] assign io_rawOut_isZero_0 = isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :123:30] reg sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:124:30] assign io_rawOut_sign_0 = sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :124:30] reg [12:0] sExp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:125:30] reg bit0FractA_PC; // @[DivSqrtRecF64_mulAddZ31.scala:126:30] reg [51:0] fractB_PC; // @[DivSqrtRecF64_mulAddZ31.scala:127:30] reg [2:0] roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:128:30] assign io_roundingModeOut_0 = roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :128:30] reg [8:0] fractR0_A; // @[DivSqrtRecF64_mulAddZ31.scala:130:30] reg [9:0] hiSqrR0_A_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:132:30] reg [20:0] partNegSigma0_A; // @[DivSqrtRecF64_mulAddZ31.scala:133:30] reg [8:0] nextMulAdd9A_A; // @[DivSqrtRecF64_mulAddZ31.scala:134:30] reg [8:0] nextMulAdd9B_A; // @[DivSqrtRecF64_mulAddZ31.scala:135:30] reg [16:0] ER1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30] reg [31:0] ESqrR1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30] reg [57:0] sigX1_B; // @[DivSqrtRecF64_mulAddZ31.scala:139:30] reg [32:0] sqrSigma1_C; // @[DivSqrtRecF64_mulAddZ31.scala:140:30] reg [57:0] sigXN_C; // @[DivSqrtRecF64_mulAddZ31.scala:141:30] reg [30:0] u_C_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:142:30] reg E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30] reg [53:0] sigT_E; // @[DivSqrtRecF64_mulAddZ31.scala:144:30] reg isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30] reg isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30] wire _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:355:28] wire ready_PA; // @[DivSqrtRecF64_mulAddZ31.scala:150:26] wire _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:390:28] wire ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26] wire _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:423:28] wire ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26] wire _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:354:28] wire leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26] wire _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:389:28] wire leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26] wire _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:422:28] wire leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:155:26] wire [45:0] _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:633:22] wire [45:0] zSigma1_B4; // @[DivSqrtRecF64_mulAddZ31.scala:157:34] wire [57:0] _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:635:38] wire [57:0] sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:158:34] wire [53:0] _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:644:12] wire [53:0] zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34] wire [53:0] _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:641:11] wire [53:0] zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34] wire _cyc_S_div_T = io_inReady_div_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:38] wire _cyc_S_div_T_1 = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55] wire cyc_S_div = _cyc_S_div_T & _cyc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:164:{38,52,55}] wire _cyc_S_sqrt_T = io_inReady_sqrt_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:38] wire cyc_S_sqrt = _cyc_S_sqrt_T & io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:{38,52}] wire cyc_S = cyc_S_div \| cyc_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :165:52, :166:27] wire [11:0] rawA_S_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_S_isZero_T = rawA_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_S_isZero = _rawA_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_S_isZero_0 = rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_S_isSpecial_T = rawA_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_S_isSpecial = &_rawA_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_S_out_isNaN_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_S_out_isInf_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_S_out_isNaN_T_1 = rawA_S_isSpecial & _rawA_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_S_isNaN = _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_S_out_isInf_T_1 = ~_rawA_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_S_out_isInf_T_2 = rawA_S_isSpecial & _rawA_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_S_isInf = _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_S_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_S_sign = _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_S_out_sExp_T = {1'h0, rawA_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_S_sExp = _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_S_out_sig_T = ~rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_S_out_sig_T_1 = {1'h0, _rawA_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_S_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_S_out_sig_T_3 = {_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_S_sig = _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_S_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_S_isZero_T = rawB_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_S_isZero = _rawB_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_S_isZero_0 = rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_S_isSpecial_T = rawB_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_S_isSpecial = &_rawB_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_S_out_isNaN_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_S_out_isInf_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_S_out_isNaN_T_1 = rawB_S_isSpecial & _rawB_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_S_isNaN = _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_S_out_isInf_T_1 = ~_rawB_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_S_out_isInf_T_2 = rawB_S_isSpecial & _rawB_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_S_isInf = _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_S_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_S_sign = _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_S_out_sExp_T = {1'h0, rawB_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_S_sExp = _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_S_out_sig_T = ~rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_S_out_sig_T_1 = {1'h0, _rawB_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_S_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_S_out_sig_T_3 = {_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_S_sig = _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _notSigNaNIn_invalidExc_S_div_T = rawA_S_isZero_0 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_div_T_1 = rawA_S_isInf & rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T \| _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:172:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:174:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_7 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = rawB_S_isNaN & _majorExc_S_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_3 = _majorExc_S_T_2 \| notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_4 = rawA_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = rawA_S_isNaN & _majorExc_S_T_5; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = rawB_S_isNaN & _majorExc_S_T_8; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_10 = _majorExc_S_T_6 \| _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :178:{38,66}] wire _majorExc_S_T_12 = ~rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_13 = ~rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:180:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_16 = _majorExc_S_T_11 \| _majorExc_S_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:178:66, :179:46, :180:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :176:12, :177:38, :179:46] wire _isNaN_S_T = rawB_S_isNaN \| notSigNaNIn_invalidExc_S_sqrt; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_1 = rawA_S_isNaN \| rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_2 = _isNaN_S_T_1 \| notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :185:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :183:12, :184:26, :185:42] wire _isInf_S_T = rawA_S_isInf \| rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire isInf_S = io_sqrtOp_0 ? rawB_S_isInf : _isInf_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _isZero_S_T = rawA_S_isZero_0 \| rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire isZero_S = io_sqrtOp_0 ? rawB_S_isZero_0 : _isZero_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55, :189:19] wire _sign_S_T_1 = _sign_S_T & rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire sign_S = _sign_S_T_1 ^ rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseA_S_T = rawA_S_isNaN \| rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseA_S = _specialCaseA_S_T \| rawA_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseB_S_T = rawB_S_isNaN \| rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseB_S = _specialCaseB_S_T \| rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecF64_mulAddZ31.scala:191:55, :193:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:193:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48, :194:29] wire _normalCase_S_sqrt_T_1 = ~rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:194:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :193:45, :194:46, :195:27] wire _sExpQuot_S_div_T = rawB_S_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_1 = rawB_S_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:198:{44,56}] wire [11:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:198:{36,41,44}] wire [11:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:198:{41,65}] wire [13:0] sExpQuot_S_div = {rawA_S_sExp[12], rawA_S_sExp} + {{2{_sExpQuot_S_div_T_4[11]}}, _sExpQuot_S_div_T_4}; // @[rawFloatFromRecFN.scala:55:23] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 14'shDFF; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :201:24] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[12:9]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :203:27] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:201:{13,24}, :203:27, :257:30] wire [8:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :205:27] wire [12:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:201:13, :204:15, :205:27] wire [12:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:204:15, :206:11] wire entering_PA_normalCase_div = cyc_S_div & normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :193:45, :210:50] wire entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:165:52, :194:46, :211:50] wire entering_PA_normalCase = entering_PA_normalCase_div \| entering_PA_normalCase_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :211:50, :213:36] wire [1:0] _cycleNum_A_T = {2{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :219:16] wire [2:0] _cycleNum_A_T_1 = entering_PA_normalCase_sqrt ? 3'h6 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :220:16] wire [2:0] _cycleNum_A_T_2 = {1'h0, _cycleNum_A_T} \| _cycleNum_A_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:219:{16,69}, :220:16] wire _cycleNum_A_T_3 = ~entering_PA_normalCase; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :221:17] wire [3:0] _cycleNum_A_T_4 = {1'h0, cycleNum_A} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :221:57] wire [2:0] _cycleNum_A_T_5 = _cycleNum_A_T_4[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:221:57] wire [2:0] _cycleNum_A_T_6 = _cycleNum_A_T_3 ? _cycleNum_A_T_5 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:221:{16,17,57}] wire [2:0] _cycleNum_A_T_7 = _cycleNum_A_T_2 \| _cycleNum_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:219:69, :220:69, :221:16] wire cyc_A6_sqrt = cycleNum_A == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :225:35] wire cyc_A5_sqrt = cycleNum_A == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :226:35] wire cyc_A4_sqrt = cycleNum_A == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :227:35] wire cyc_A4 = cyc_A4_sqrt \| entering_PA_normalCase_div; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :227:35, :231:30] wire cyc_A3 = cycleNum_A == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :232:30] wire cyc_A2 = cycleNum_A == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :233:30] wire cyc_A1 = cycleNum_A == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :234:30] wire _cyc_A3_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32] wire cyc_A3_div = cyc_A3 & _cyc_A3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :236:{29,32}] wire _cyc_A2_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :237:32] wire cyc_A2_div = cyc_A2 & _cyc_A2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :237:{29,32}] wire _cyc_A1_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :238:32] wire cyc_A1_div = cyc_A1 & _cyc_A1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :238:{29,32}] wire cyc_A3_sqrt = cyc_A3 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :232:30, :240:30] wire cyc_A2_sqrt = cyc_A2 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :233:30, :241:30] wire cyc_A1_sqrt = cyc_A1 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :234:30, :242:30] wire [3:0] _cycleNum_B_T = sqrtOp_PA ? 4'hA : 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :247:20, :257:30] wire [4:0] _cycleNum_B_T_1 = {1'h0, cycleNum_B} - 5'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :248:28] wire [3:0] _cycleNum_B_T_2 = _cycleNum_B_T_1[3:0]; // @[DivSqrtRecF64_mulAddZ31.scala:248:28] wire [3:0] _cycleNum_B_T_3 = cyc_A1 ? _cycleNum_B_T : _cycleNum_B_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :246:16, :247:20, :248:28] wire cyc_B10_sqrt = cycleNum_B == 4'hA; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :252:36] wire cyc_B9_sqrt = cycleNum_B == 4'h9; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :253:36] wire cyc_B8_sqrt = cycleNum_B == 4'h8; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :254:36] wire cyc_B7_sqrt = cycleNum_B == 4'h7; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :255:36] wire cyc_B6 = cycleNum_B == 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :257:30] wire cyc_B5 = cycleNum_B == 4'h5; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :258:30] wire cyc_B4 = cycleNum_B == 4'h4; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :259:30] wire cyc_B3 = cycleNum_B == 4'h3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :260:30] wire cyc_B2 = cycleNum_B == 4'h2; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :261:30] wire cyc_B1 = cycleNum_B == 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :262:30] wire _cyc_B6_div_T = cyc_B6 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :257:30, :264:29] wire _cyc_B6_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :264:44] wire cyc_B6_div = _cyc_B6_div_T & _cyc_B6_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:264:{29,41,44}] wire _cyc_B5_div_T = cyc_B5 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :258:30, :265:29] wire _cyc_B5_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :265:44] wire cyc_B5_div = _cyc_B5_div_T & _cyc_B5_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:265:{29,41,44}] wire _cyc_B4_div_T = cyc_B4 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :259:30, :266:29] wire _cyc_B4_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :266:44] wire cyc_B4_div = _cyc_B4_div_T & _cyc_B4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:266:{29,41,44}] wire _cyc_B3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32] wire cyc_B3_div = cyc_B3 & _cyc_B3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :267:{29,32}] wire _cyc_B2_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :268:32] wire cyc_B2_div = cyc_B2 & _cyc_B2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :268:{29,32}] wire _cyc_B1_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :269:32] wire cyc_B1_div = cyc_B1 & _cyc_B1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :269:{29,32}] wire _cyc_B6_sqrt_T = cyc_B6 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :257:30, :271:30] wire cyc_B6_sqrt = _cyc_B6_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :271:{30,42}] wire _cyc_B5_sqrt_T = cyc_B5 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :258:30, :272:30] wire cyc_B5_sqrt = _cyc_B5_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :272:{30,42}] wire _cyc_B4_sqrt_T = cyc_B4 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :259:30, :273:30] wire cyc_B4_sqrt = _cyc_B4_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :273:{30,42}] wire cyc_B3_sqrt = cyc_B3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :260:30, :274:30] wire cyc_B2_sqrt = cyc_B2 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :261:30, :275:30] wire cyc_B1_sqrt = cyc_B1 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :262:30, :276:30] wire [2:0] _cycleNum_C_T = sqrtOp_PB ? 3'h6 : 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :280:28] wire [3:0] _cycleNum_C_T_1 = {1'h0, cycleNum_C} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:62] wire [2:0] _cycleNum_C_T_2 = _cycleNum_C_T_1[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:280:62] wire [2:0] _cycleNum_C_T_3 = cyc_B1 ? _cycleNum_C_T : _cycleNum_C_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :280:{16,28,62}] wire cyc_C6_sqrt = cycleNum_C == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :283:35] wire cyc_C5 = cycleNum_C == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :285:30] wire cyc_C4 = cycleNum_C == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :286:30] wire cyc_C3 = cycleNum_C == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :287:30] wire cyc_C2 = cycleNum_C == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :288:30] wire cyc_C1 = cycleNum_C == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :289:30] wire _cyc_C5_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :291:32] wire cyc_C5_div = cyc_C5 & _cyc_C5_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :291:{29,32}] wire _cyc_C4_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :292:32] wire cyc_C4_div = cyc_C4 & _cyc_C4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :292:{29,32}] wire _cyc_C3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :293:32] wire cyc_C3_div = cyc_C3 & _cyc_C3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :293:{29,32}] wire _cyc_C2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32] wire cyc_C2_div = cyc_C2 & _cyc_C2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :294:{29,32}] wire _cyc_C1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :295:32] wire cyc_C1_div = cyc_C1 & _cyc_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :295:{29,32}] wire cyc_C5_sqrt = cyc_C5 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :285:30, :297:30] wire cyc_C4_sqrt = cyc_C4 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :286:30, :298:30] wire cyc_C3_sqrt = cyc_C3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :287:30, :299:30] wire cyc_C2_sqrt = cyc_C2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :288:30, :300:30] wire cyc_C1_sqrt = cyc_C1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :289:30, :301:30] wire [3:0] _cycleNum_E_T = {1'h0, cycleNum_E} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:51] wire [2:0] _cycleNum_E_T_1 = _cycleNum_E_T[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:304:51] wire [2:0] _cycleNum_E_T_2 = cyc_C1 ? 3'h4 : _cycleNum_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :304:{26,51}] wire cyc_E4 = cycleNum_E == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :307:30] wire cyc_E3 = cycleNum_E == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :308:30] wire cyc_E2 = cycleNum_E == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :309:30] wire cyc_E1 = cycleNum_E == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :310:30] wire _cyc_E4_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :312:32] wire cyc_E4_div = cyc_E4 & _cyc_E4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:307:30, :312:{29,32}] wire _cyc_E3_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :313:32] wire cyc_E3_div = cyc_E3 & _cyc_E3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:308:30, :313:{29,32}] wire _cyc_E2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :314:32] wire cyc_E2_div = cyc_E2 & _cyc_E2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:309:30, :314:{29,32}] wire _cyc_E1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :315:32] wire cyc_E1_div = cyc_E1 & _cyc_E1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :315:{29,32}] wire cyc_E4_sqrt = cyc_E4 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :307:30, :317:30] wire cyc_E3_sqrt = cyc_E3 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :308:30, :318:30] wire cyc_E2_sqrt = cyc_E2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :309:30, :319:30] wire cyc_E1_sqrt = cyc_E1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :310:30, :320:30] wire _entering_PA_T = ~ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :325:58] wire _entering_PA_T_1 = valid_PA \| _entering_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:{55,58}] wire _entering_PA_T_2 = cyc_S & _entering_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :325:{42,55}] wire entering_PA = entering_PA_normalCase \| _entering_PA_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :325:{32,42}] wire [12:0] _sExp_PA_T = io_sqrtOp_0 ? rawB_S_sExp : sSatExpQuot_S_div; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractB_PA_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A4_div_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A7_sqrt_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractA_PA_T = rawA_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_PA_T = ~isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :347:25] wire _normalCase_PA_T_1 = ~isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :347:39] wire _normalCase_PA_T_2 = _normalCase_PA_T & _normalCase_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:347:{25,36,39}] wire _normalCase_PA_T_3 = ~isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :347:53] wire normalCase_PA = _normalCase_PA_T_2 & _normalCase_PA_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:347:{36,50,53}] wire [52:0] sigA_PA = {1'h1, fractA_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :348:28] wire [52:0] sigB_PA = {1'h1, fractB_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :349:28] wire valid_normalCase_leaving_PA = cyc_B4_div \| cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :266:41, :351:50] wire valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :347:50, :351:50, :353:12] assign _leaving_PA_T = valid_PA & valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :353:12, :354:28] assign leaving_PA = _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :354:28] wire _ready_PA_T = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17] assign _ready_PA_T_1 = _ready_PA_T \| valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:353:12, :355:{17,28}] assign ready_PA = _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :355:28] wire _entering_PB_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18] wire _entering_PB_S_T_1 = cyc_S & _entering_PB_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :360:{15,18}] wire _entering_PB_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :360:36] wire _entering_PB_S_T_3 = _entering_PB_S_T_1 & _entering_PB_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:360:{15,33,36}] wire _entering_PB_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29] wire _entering_PB_S_T_5 = ~ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :361:43] wire _entering_PB_S_T_6 = _entering_PB_S_T_4 & _entering_PB_S_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:361:{29,40,43}] wire _entering_PB_S_T_7 = leaving_PB \| _entering_PB_S_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :361:{25,40}] wire entering_PB_S = _entering_PB_S_T_3 & _entering_PB_S_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:360:{33,47}, :361:25] wire _entering_PB_normalCase_T = valid_PA & normalCase_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :347:50, :363:18] wire entering_PB_normalCase = _entering_PB_normalCase_T & valid_normalCase_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:351:50, :363:{18,35}] wire entering_PB = entering_PB_S \| leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :360:47, :364:37] wire _sqrtOp_PB_T = valid_PA ? sqrtOp_PA : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :92:30, :370:27] wire _majorExc_PB_T = valid_PA ? majorExc_PA : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :93:30, :176:12, :371:27] wire _isNaN_PB_T = valid_PA ? isNaN_PA : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :95:30, :183:12, :372:27] wire _isInf_PB_T = valid_PA ? isInf_PA : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :96:30, :187:23, :373:27] wire _isZero_PB_T = valid_PA ? isZero_PA : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :97:30, :188:23, :374:27] wire _sign_PB_T = valid_PA ? sign_PA : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :98:30, :189:47, :375:27] wire _bit0FractA_PB_T = fractA_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :379:37] wire [2:0] _roundingMode_PB_T = valid_PA ? roundingMode_PA : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :102:30, :381:31] wire _normalCase_PB_T = ~isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :384:25] wire _normalCase_PB_T_1 = ~isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :384:39] wire _normalCase_PB_T_2 = _normalCase_PB_T & _normalCase_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:384:{25,36,39}] wire _normalCase_PB_T_3 = ~isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :384:53] wire normalCase_PB = _normalCase_PB_T_2 & _normalCase_PB_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:384:{36,50,53}] wire valid_leaving_PB = normalCase_PB ? cyc_C3 : ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :287:30, :384:50, :388:12] assign _leaving_PB_T = valid_PB & valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :388:12, :389:28] assign leaving_PB = _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :389:28] wire _ready_PB_T = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :390:17] assign _ready_PB_T_1 = _ready_PB_T \| valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:388:12, :390:{17,28}] assign ready_PB = _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :390:28] wire _entering_PC_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18, :395:18] wire _entering_PC_S_T_1 = cyc_S & _entering_PC_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :395:{15,18}] wire _entering_PC_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :395:36] wire _entering_PC_S_T_3 = _entering_PC_S_T_1 & _entering_PC_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:395:{15,33,36}] wire _entering_PC_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :395:50] wire _entering_PC_S_T_5 = _entering_PC_S_T_3 & _entering_PC_S_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:395:{33,47,50}] wire entering_PC_S = _entering_PC_S_T_5 & ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :395:{47,61}] wire _entering_PC_normalCase_T = valid_PB & normalCase_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :384:50, :397:18] wire entering_PC_normalCase = _entering_PC_normalCase_T & cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :397:{18,35}] wire entering_PC = entering_PC_S \| leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :395:61, :398:37] wire _sqrtOp_PC_T = valid_PB ? sqrtOp_PB : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :105:30, :404:27] wire _majorExc_PC_T = valid_PB ? majorExc_PB : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :106:30, :176:12, :405:27] wire _isNaN_PC_T = valid_PB ? isNaN_PB : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :108:30, :183:12, :406:27] wire _isInf_PC_T = valid_PB ? isInf_PB : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :109:30, :187:23, :407:27] wire _isZero_PC_T = valid_PB ? isZero_PB : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :110:30, :188:23, :408:27] wire _sign_PC_T = valid_PB ? sign_PB : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :111:30, :189:47, :409:27] wire [2:0] _roundingMode_PC_T = valid_PB ? roundingMode_PB : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :115:30, :415:31] wire _normalCase_PC_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25] wire _normalCase_PC_T_1 = ~isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :418:39] wire _normalCase_PC_T_2 = _normalCase_PC_T & _normalCase_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:418:{25,36,39}] wire _normalCase_PC_T_3 = ~isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :418:53] wire normalCase_PC = _normalCase_PC_T_2 & _normalCase_PC_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:418:{36,50,53}] wire [52:0] sigB_PC = {1'h1, fractB_PC}; // @[DivSqrtRecF64_mulAddZ31.scala:127:30, :419:28] wire _valid_leaving_PC_T = ~normalCase_PC; // @[DivSqrtRecF64_mulAddZ31.scala:418:50, :421:28] wire valid_leaving_PC = _valid_leaving_PC_T \| cyc_E1; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :421:{28,44}] assign _leaving_PC_T = valid_PC & valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :421:44, :422:28] assign leaving_PC = _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :422:28] wire _ready_PC_T = ~valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :423:17] assign _ready_PC_T_1 = _ready_PC_T \| valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:421:44, :423:{17,28}] assign ready_PC = _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :423:28] wire _io_inReady_div_T = ~cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :430:21] wire _io_inReady_div_T_1 = ready_PA & _io_inReady_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :430:{18,21}] wire _io_inReady_div_T_2 = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38] wire _io_inReady_div_T_3 = _io_inReady_div_T_1 & _io_inReady_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:430:{18,35,38}] wire _io_inReady_div_T_4 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55] wire _io_inReady_div_T_5 = _io_inReady_div_T_3 & _io_inReady_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:430:{35,52,55}] wire _io_inReady_div_T_6 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13] wire _io_inReady_div_T_7 = _io_inReady_div_T_5 & _io_inReady_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:430:{52,69}, :431:13] wire _io_inReady_div_T_8 = ~cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :431:30] wire _io_inReady_div_T_9 = _io_inReady_div_T_7 & _io_inReady_div_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:430:69, :431:{27,30}] wire _io_inReady_div_T_10 = ~cyc_B2; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :431:42] wire _io_inReady_div_T_11 = _io_inReady_div_T_9 & _io_inReady_div_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:431:{27,39,42}] wire _io_inReady_div_T_12 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54] wire _io_inReady_div_T_13 = _io_inReady_div_T_11 & _io_inReady_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:431:{39,51,54}] wire _io_inReady_div_T_14 = ~cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :432:13] wire _io_inReady_div_T_15 = _io_inReady_div_T_13 & _io_inReady_div_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:431:{51,68}, :432:13] wire _io_inReady_div_T_16 = ~cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :432:25] assign _io_inReady_div_T_17 = _io_inReady_div_T_15 & _io_inReady_div_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:431:68, :432:{22,25}] assign io_inReady_div_0 = _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :432:22] wire _io_inReady_sqrt_T = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38, :434:21] wire _io_inReady_sqrt_T_1 = ready_PA & _io_inReady_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :434:{18,21}] wire _io_inReady_sqrt_T_2 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55, :434:38] wire _io_inReady_sqrt_T_3 = _io_inReady_sqrt_T_1 & _io_inReady_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:434:{18,35,38}] wire _io_inReady_sqrt_T_4 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13, :434:55] wire _io_inReady_sqrt_T_5 = _io_inReady_sqrt_T_3 & _io_inReady_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:434:{35,52,55}] wire _io_inReady_sqrt_T_6 = ~cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :435:13] wire _io_inReady_sqrt_T_7 = _io_inReady_sqrt_T_5 & _io_inReady_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:434:{52,69}, :435:13] wire _io_inReady_sqrt_T_8 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54, :435:29] assign _io_inReady_sqrt_T_9 = _io_inReady_sqrt_T_7 & _io_inReady_sqrt_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:434:69, :435:{26,29}] assign io_inReady_sqrt_0 = _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :435:26] wire [51:0] zFractB_A4_div = entering_PA_normalCase_div ? _zFractB_A4_div_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :440:{29,52}] wire [2:0] _zLinPiece_0_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_1_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_2_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_3_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_4_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_5_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_6_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_7_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire _zLinPiece_0_A4_div_T_1 = _zLinPiece_0_A4_div_T == 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:{55,64}] wire zLinPiece_0_A4_div = entering_PA_normalCase_div & _zLinPiece_0_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :442:{41,64}] wire _zLinPiece_1_A4_div_T_1 = _zLinPiece_1_A4_div_T == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:443:{55,64}] wire zLinPiece_1_A4_div = entering_PA_normalCase_div & _zLinPiece_1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :443:{41,64}] wire _zLinPiece_2_A4_div_T_1 = _zLinPiece_2_A4_div_T == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:444:{55,64}] wire zLinPiece_2_A4_div = entering_PA_normalCase_div & _zLinPiece_2_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :444:{41,64}] wire _zLinPiece_3_A4_div_T_1 = _zLinPiece_3_A4_div_T == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:445:{55,64}] wire zLinPiece_3_A4_div = entering_PA_normalCase_div & _zLinPiece_3_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :445:{41,64}] wire _zLinPiece_4_A4_div_T_1 = _zLinPiece_4_A4_div_T == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:446:{55,64}] wire zLinPiece_4_A4_div = entering_PA_normalCase_div & _zLinPiece_4_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :446:{41,64}] wire _zLinPiece_5_A4_div_T_1 = _zLinPiece_5_A4_div_T == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:447:{55,64}] wire zLinPiece_5_A4_div = entering_PA_normalCase_div & _zLinPiece_5_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :447:{41,64}] wire _zLinPiece_6_A4_div_T_1 = _zLinPiece_6_A4_div_T == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:448:{55,64}] wire zLinPiece_6_A4_div = entering_PA_normalCase_div & _zLinPiece_6_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :448:{41,64}] wire _zLinPiece_7_A4_div_T_1 = &_zLinPiece_7_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:449:{55,64}] wire zLinPiece_7_A4_div = entering_PA_normalCase_div & _zLinPiece_7_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :449:{41,64}] wire [8:0] _zK1_A4_div_T = zLinPiece_0_A4_div ? 9'h1C7 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :451:12] wire [8:0] _zK1_A4_div_T_1 = zLinPiece_1_A4_div ? 9'h16C : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :452:12] wire [8:0] _zK1_A4_div_T_2 = _zK1_A4_div_T \| _zK1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:451:{12,48}, :452:12] wire [8:0] _zK1_A4_div_T_3 = zLinPiece_2_A4_div ? 9'h12A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :453:12] wire [8:0] _zK1_A4_div_T_4 = _zK1_A4_div_T_2 \| _zK1_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:451:48, :452:48, :453:12] wire [7:0] _zK1_A4_div_T_5 = zLinPiece_3_A4_div ? 8'hF8 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :454:12] wire [8:0] _zK1_A4_div_T_6 = {_zK1_A4_div_T_4[8], _zK1_A4_div_T_4[7:0] \| _zK1_A4_div_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:452:48, :453:48, :454:12] wire [7:0] _zK1_A4_div_T_7 = zLinPiece_4_A4_div ? 8'hD2 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :455:12] wire [8:0] _zK1_A4_div_T_8 = {_zK1_A4_div_T_6[8], _zK1_A4_div_T_6[7:0] \| _zK1_A4_div_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:453:48, :454:48, :455:12] wire [7:0] _zK1_A4_div_T_9 = zLinPiece_5_A4_div ? 8'hB4 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :456:12] wire [8:0] _zK1_A4_div_T_10 = {_zK1_A4_div_T_8[8], _zK1_A4_div_T_8[7:0] \| _zK1_A4_div_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:454:48, :455:48, :456:12] wire [7:0] _zK1_A4_div_T_11 = zLinPiece_6_A4_div ? 8'h9C : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :457:12] wire [8:0] _zK1_A4_div_T_12 = {_zK1_A4_div_T_10[8], _zK1_A4_div_T_10[7:0] \| _zK1_A4_div_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:455:48, :456:48, :457:12] wire [7:0] _zK1_A4_div_T_13 = zLinPiece_7_A4_div ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :458:12] wire [8:0] zK1_A4_div = {_zK1_A4_div_T_12[8], _zK1_A4_div_T_12[7:0] \| _zK1_A4_div_T_13}; // @[DivSqrtRecF64_mulAddZ31.scala:456:48, :457:48, :458:12] wire [11:0] _zComplFractK0_A4_div_T_1 = zLinPiece_0_A4_div ? 12'h1C : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :460:12] wire [11:0] _zComplFractK0_A4_div_T_3 = zLinPiece_1_A4_div ? 12'h3A2 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :461:12] wire [11:0] _zComplFractK0_A4_div_T_4 = _zComplFractK0_A4_div_T_1 \| _zComplFractK0_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:460:{12,55}, :461:12] wire [11:0] _zComplFractK0_A4_div_T_6 = zLinPiece_2_A4_div ? 12'h675 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :462:12] wire [11:0] _zComplFractK0_A4_div_T_7 = _zComplFractK0_A4_div_T_4 \| _zComplFractK0_A4_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:460:55, :461:55, :462:12] wire [11:0] _zComplFractK0_A4_div_T_9 = zLinPiece_3_A4_div ? 12'h8C6 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :463:12] wire [11:0] _zComplFractK0_A4_div_T_10 = _zComplFractK0_A4_div_T_7 \| _zComplFractK0_A4_div_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:461:55, :462:55, :463:12] wire [11:0] _zComplFractK0_A4_div_T_12 = zLinPiece_4_A4_div ? 12'hAB4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :464:12] wire [11:0] _zComplFractK0_A4_div_T_13 = _zComplFractK0_A4_div_T_10 \| _zComplFractK0_A4_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:462:55, :463:55, :464:12] wire [11:0] _zComplFractK0_A4_div_T_15 = zLinPiece_5_A4_div ? 12'hC56 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :465:12] wire [11:0] _zComplFractK0_A4_div_T_16 = _zComplFractK0_A4_div_T_13 \| _zComplFractK0_A4_div_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:463:55, :464:55, :465:12] wire [11:0] _zComplFractK0_A4_div_T_18 = zLinPiece_6_A4_div ? 12'hDBD : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :466:12] wire [11:0] _zComplFractK0_A4_div_T_19 = _zComplFractK0_A4_div_T_16 \| _zComplFractK0_A4_div_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:464:55, :465:55, :466:12] wire [11:0] _zComplFractK0_A4_div_T_21 = zLinPiece_7_A4_div ? 12'hEF4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :467:12] wire [11:0] zComplFractK0_A4_div = _zComplFractK0_A4_div_T_19 \| _zComplFractK0_A4_div_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:465:55, :466:55, :467:12] wire [51:0] zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? _zFractB_A7_sqrt_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :469:{30,54}] wire _zQuadPiece_0_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_1 = ~_zQuadPiece_0_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:472:{24,37}] wire _zQuadPiece_0_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_0_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :472:{21,24}] wire _zQuadPiece_0_A7_sqrt_T_4 = ~_zQuadPiece_0_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:472:{44,56}] wire zQuadPiece_0_A7_sqrt = _zQuadPiece_0_A7_sqrt_T_2 & _zQuadPiece_0_A7_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:472:{21,41,44}] wire _zQuadPiece_1_A7_sqrt_T_1 = ~_zQuadPiece_1_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:474:{24,37}] wire _zQuadPiece_1_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_1_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :474:{21,24}] wire zQuadPiece_1_A7_sqrt = _zQuadPiece_1_A7_sqrt_T_2 & _zQuadPiece_1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:474:{21,41,56}] wire _zQuadPiece_2_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_2_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :476:{21,37}] wire _zQuadPiece_2_A7_sqrt_T_3 = ~_zQuadPiece_2_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:476:{44,56}] wire zQuadPiece_2_A7_sqrt = _zQuadPiece_2_A7_sqrt_T_1 & _zQuadPiece_2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:476:{21,41,44}] wire _zQuadPiece_3_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_3_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :477:{44,58}] wire zQuadPiece_3_A7_sqrt = _zQuadPiece_3_A7_sqrt_T_1 & _zQuadPiece_3_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:477:{44,62,75}] wire [8:0] _zK2_A7_sqrt_T = zQuadPiece_0_A7_sqrt ? 9'h1C8 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :479:12] wire [7:0] _zK2_A7_sqrt_T_1 = zQuadPiece_1_A7_sqrt ? 8'hC1 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :480:12] wire [8:0] _zK2_A7_sqrt_T_2 = {_zK2_A7_sqrt_T[8], _zK2_A7_sqrt_T[7:0] \| _zK2_A7_sqrt_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:479:{12,50}, :480:12] wire [8:0] _zK2_A7_sqrt_T_3 = zQuadPiece_2_A7_sqrt ? 9'h143 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :481:12] wire [8:0] _zK2_A7_sqrt_T_4 = _zK2_A7_sqrt_T_2 \| _zK2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:479:50, :480:50, :481:12] wire [7:0] _zK2_A7_sqrt_T_5 = zQuadPiece_3_A7_sqrt ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :482:12] wire [8:0] zK2_A7_sqrt = {_zK2_A7_sqrt_T_4[8], _zK2_A7_sqrt_T_4[7:0] \| _zK2_A7_sqrt_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:480:50, :481:50, :482:12] wire [9:0] _zComplK1_A7_sqrt_T_1 = zQuadPiece_0_A7_sqrt ? 10'h2F : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :484:12] wire [9:0] _zComplK1_A7_sqrt_T_3 = zQuadPiece_1_A7_sqrt ? 10'h1DF : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_4 = _zComplK1_A7_sqrt_T_1 \| _zComplK1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:484:{12,57}, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_6 = zQuadPiece_2_A7_sqrt ? 10'h14D : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_7 = _zComplK1_A7_sqrt_T_4 \| _zComplK1_A7_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:484:57, :485:57, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_9 = zQuadPiece_3_A7_sqrt ? 10'h27E : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :487:12] wire [9:0] zComplK1_A7_sqrt = _zComplK1_A7_sqrt_T_7 \| _zComplK1_A7_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:485:57, :486:57, :487:12] wire _zQuadPiece_0_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56] wire _zQuadPiece_1_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :490:56] wire _zQuadPiece_2_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :491:56] wire _zQuadPiece_3_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :492:56] wire _sqrR0_A5_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :533:36] wire _ER1_A1_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :539:34] wire _zQuadPiece_0_A6_sqrt_T_1 = ~_zQuadPiece_0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:489:{47,56}] wire _zQuadPiece_0_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_0_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :489:{44,47}] wire _zQuadPiece_0_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72] wire _zQuadPiece_1_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :490:72] wire _zQuadPiece_2_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :491:72] wire _zQuadPiece_3_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :492:72] wire _zQuadPiece_0_A6_sqrt_T_4 = ~_zQuadPiece_0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:489:{63,72}] wire zQuadPiece_0_A6_sqrt = _zQuadPiece_0_A6_sqrt_T_2 & _zQuadPiece_0_A6_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:489:{44,60,63}] wire _zQuadPiece_1_A6_sqrt_T_1 = ~_zQuadPiece_1_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:490:{47,56}] wire _zQuadPiece_1_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_1_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :490:{44,47}] wire zQuadPiece_1_A6_sqrt = _zQuadPiece_1_A6_sqrt_T_2 & _zQuadPiece_1_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:490:{44,60,72}] wire _zQuadPiece_2_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_2_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :491:{44,56}] wire _zQuadPiece_2_A6_sqrt_T_3 = ~_zQuadPiece_2_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:491:{63,72}] wire zQuadPiece_2_A6_sqrt = _zQuadPiece_2_A6_sqrt_T_1 & _zQuadPiece_2_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:491:{44,60,63}] wire _zQuadPiece_3_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_3_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :492:{44,56}] wire zQuadPiece_3_A6_sqrt = _zQuadPiece_3_A6_sqrt_T_1 & _zQuadPiece_3_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:492:{44,60,72}] wire [12:0] _zComplFractK0_A6_sqrt_T_1 = zQuadPiece_0_A6_sqrt ? 13'h1A : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:489:60, :494:12] wire [12:0] _zComplFractK0_A6_sqrt_T_3 = zQuadPiece_1_A6_sqrt ? 13'hBCA : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:490:60, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_4 = _zComplFractK0_A6_sqrt_T_1 \| _zComplFractK0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:494:{12,58}, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_6 = zQuadPiece_2_A6_sqrt ? 13'h12D3 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:491:60, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_7 = _zComplFractK0_A6_sqrt_T_4 \| _zComplFractK0_A6_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:494:58, :495:58, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_9 = zQuadPiece_3_A6_sqrt ? 13'h1B17 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:492:60, :497:12] wire [12:0] zComplFractK0_A6_sqrt = _zComplFractK0_A6_sqrt_T_7 \| _zComplFractK0_A6_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:495:58, :496:58, :497:12] wire [8:0] _mulAdd9A_A_T = zFractB_A4_div[48:40]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :500:23] wire [8:0] _mulAdd9A_A_T_1 = _mulAdd9A_A_T \| zK2_A7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:481:50, :500:{23,32}] wire _mulAdd9A_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17] wire [8:0] _mulAdd9A_A_T_3 = _mulAdd9A_A_T_2 ? nextMulAdd9A_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :501:{16,17}] wire [8:0] mulAdd9A_A = _mulAdd9A_A_T_1 \| _mulAdd9A_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:500:{32,46}, :501:16] wire [8:0] _mulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37] wire [8:0] _nextMulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37, :563:28] wire [8:0] _mulAdd9B_A_T_1 = zK1_A4_div \| _mulAdd9B_A_T; // @[DivSqrtRecF64_mulAddZ31.scala:457:48, :503:{20,37}] wire _mulAdd9B_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17, :504:17] wire [8:0] _mulAdd9B_A_T_3 = _mulAdd9B_A_T_2 ? nextMulAdd9B_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :504:{16,17}] wire [8:0] mulAdd9B_A = _mulAdd9B_A_T_1 \| _mulAdd9B_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:503:{20,46}, :504:16] wire [9:0] _mulAdd9C_A_T = {10{entering_PA_normalCase_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :507:50] wire [19:0] _mulAdd9C_A_T_1 = {zComplK1_A7_sqrt, _mulAdd9C_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:486:57, :507:{26,50}] wire [5:0] _mulAdd9C_A_T_2 = {6{cyc_A6_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :508:53] wire [13:0] mulAdd9C_A_hi = {cyc_A6_sqrt, zComplFractK0_A6_sqrt}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :496:58, :508:12] wire [19:0] _mulAdd9C_A_T_3 = {mulAdd9C_A_hi, _mulAdd9C_A_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:508:{12,53}] wire [19:0] _mulAdd9C_A_T_4 = _mulAdd9C_A_T_1 \| _mulAdd9C_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:507:{26,68}, :508:12] wire [7:0] _mulAdd9C_A_T_5 = {8{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :509:53] wire [12:0] mulAdd9C_A_hi_1 = {entering_PA_normalCase_div, zComplFractK0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :466:55, :509:12] wire [20:0] _mulAdd9C_A_T_6 = {mulAdd9C_A_hi_1, _mulAdd9C_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:509:{12,53}] wire [20:0] _mulAdd9C_A_T_7 = {1'h0, _mulAdd9C_A_T_4} \| _mulAdd9C_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:507:68, :508:71, :509:12] wire [18:0] _mulAdd9C_A_T_8 = {fractR0_A, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :510:53] wire [19:0] _mulAdd9C_A_T_9 = {1'h0, _mulAdd9C_A_T_8} + 20'h40000; // @[DivSqrtRecF64_mulAddZ31.scala:510:{40,53}] wire [19:0] _mulAdd9C_A_T_10 = cyc_A5_sqrt ? _mulAdd9C_A_T_9 : 20'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :510:{12,40}] wire [20:0] _mulAdd9C_A_T_11 = {_mulAdd9C_A_T_7[20], _mulAdd9C_A_T_7[19:0] \| _mulAdd9C_A_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:508:71, :509:71, :510:12] wire _mulAdd9C_A_T_12 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44] wire _mulAdd9C_A_T_17 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44, :512:43] wire _mulAdd9C_A_T_13 = ~_mulAdd9C_A_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:511:{28,44}] wire _mulAdd9C_A_T_14 = cyc_A4_sqrt & _mulAdd9C_A_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :511:{25,28}] wire [10:0] _mulAdd9C_A_T_15 = {_mulAdd9C_A_T_14, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:511:{12,25}] wire [20:0] _mulAdd9C_A_T_16 = {_mulAdd9C_A_T_11[20:11], _mulAdd9C_A_T_11[10:0] \| _mulAdd9C_A_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:509:71, :510:65, :511:12] wire _mulAdd9C_A_T_18 = cyc_A4_sqrt & _mulAdd9C_A_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :512:{26,43}] wire _mulAdd9C_A_T_19 = _mulAdd9C_A_T_18 \| cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:236:29, :512:{26,48}] wire [20:0] _mulAdd9C_A_T_20 = sigB_PA[46:26]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :513:20] wire [21:0] _mulAdd9C_A_T_21 = {1'h0, _mulAdd9C_A_T_20} + 22'h400; // @[DivSqrtRecF64_mulAddZ31.scala:513:{20,29}] wire [20:0] _mulAdd9C_A_T_22 = _mulAdd9C_A_T_21[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:513:29] wire [20:0] _mulAdd9C_A_T_23 = _mulAdd9C_A_T_19 ? _mulAdd9C_A_T_22 : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:512:{12,48}, :513:29] wire [20:0] _mulAdd9C_A_T_24 = _mulAdd9C_A_T_16 \| _mulAdd9C_A_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:510:65, :511:65, :512:12] wire _mulAdd9C_A_T_25 = cyc_A3_sqrt \| cyc_A2; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :240:30, :516:25] wire [20:0] _mulAdd9C_A_T_26 = _mulAdd9C_A_T_25 ? partNegSigma0_A : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :516:{12,25}] wire [20:0] _mulAdd9C_A_T_27 = _mulAdd9C_A_T_24 \| _mulAdd9C_A_T_26; // @[DivSqrtRecF64_mulAddZ31.scala:511:65, :515:11, :516:12] wire [24:0] _mulAdd9C_A_T_28 = {fractR0_A, 16'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :517:45] wire [24:0] _mulAdd9C_A_T_29 = cyc_A1_sqrt ? _mulAdd9C_A_T_28 : 25'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :517:{12,45}] wire [24:0] _mulAdd9C_A_T_30 = {4'h0, _mulAdd9C_A_T_27} \| _mulAdd9C_A_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:515:11, :516:58, :517:12] wire [23:0] _mulAdd9C_A_T_31 = {fractR0_A, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :518:45] wire [23:0] _mulAdd9C_A_T_32 = cyc_A1_div ? _mulAdd9C_A_T_31 : 24'h0; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :518:{12,45}] wire [24:0] mulAdd9C_A = {_mulAdd9C_A_T_30[24], _mulAdd9C_A_T_30[23:0] \| _mulAdd9C_A_T_32}; // @[DivSqrtRecF64_mulAddZ31.scala:516:58, :517:58, :518:12] wire [17:0] _loMulAdd9Out_A_T = {9'h0, mulAdd9A_A} * {9'h0, mulAdd9B_A}; // @[DivSqrtRecF64_mulAddZ31.scala:500:46, :503:46, :519:37] wire [17:0] _loMulAdd9Out_A_T_1 = mulAdd9C_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :519:63] wire [18:0] loMulAdd9Out_A = {1'h0, _loMulAdd9Out_A_T} + {1'h0, _loMulAdd9Out_A_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:519:{37,50,63}] wire _mulAdd9Out_A_T = loMulAdd9Out_A[18]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :521:31] wire [6:0] _mulAdd9Out_A_T_1 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27] wire [6:0] _mulAdd9Out_A_T_4 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27, :523:27] wire [7:0] _mulAdd9Out_A_T_2 = {1'h0, _mulAdd9Out_A_T_1} + 8'h1; // @[DivSqrtRecF64_mulAddZ31.scala:522:{27,36}] wire [6:0] _mulAdd9Out_A_T_3 = _mulAdd9Out_A_T_2[6:0]; // @[DivSqrtRecF64_mulAddZ31.scala:522:36] wire [6:0] _mulAdd9Out_A_T_5 = _mulAdd9Out_A_T ? _mulAdd9Out_A_T_3 : _mulAdd9Out_A_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:521:{16,31}, :522:36, :523:27] wire [17:0] _mulAdd9Out_A_T_6 = loMulAdd9Out_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :525:27] wire [24:0] mulAdd9Out_A = {_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6}; // @[DivSqrtRecF64_mulAddZ31.scala:521:{12,16}, :525:27] wire _zFractR0_A6_sqrt_T = mulAdd9Out_A[19]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:40] wire _zFractR0_A6_sqrt_T_1 = cyc_A6_sqrt & _zFractR0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :529:{25,40}] wire [14:0] _zFractR0_A6_sqrt_T_2 = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60] wire [14:0] _r1_A1_T = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60, :538:56] wire [14:0] _zFractR0_A6_sqrt_T_3 = ~_zFractR0_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:529:{46,60}] wire [14:0] zFractR0_A6_sqrt = _zFractR0_A6_sqrt_T_1 ? _zFractR0_A6_sqrt_T_3 : 15'h0; // @[DivSqrtRecF64_mulAddZ31.scala:529:{12,25,46}] wire [25:0] _sqrR0_A5_sqrt_T_1 = {mulAdd9Out_A, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:53] wire [25:0] sqrR0_A5_sqrt = _sqrR0_A5_sqrt_T ? _sqrR0_A5_sqrt_T_1 : {1'h0, mulAdd9Out_A}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:{28,36,53}] wire _zFractR0_A4_div_T = mulAdd9Out_A[20]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:39] wire _zFractR0_A4_div_T_1 = entering_PA_normalCase_div & _zFractR0_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :535:{24,39}] wire [13:0] _zFractR0_A4_div_T_2 = mulAdd9Out_A[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:59] wire [13:0] _zFractR0_A4_div_T_3 = ~_zFractR0_A4_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:535:{45,59}] wire [13:0] zFractR0_A4_div = _zFractR0_A4_div_T_1 ? _zFractR0_A4_div_T_3 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:535:{12,24,45}] wire _zSigma0_A2_T = mulAdd9Out_A[11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:35] wire _zSigma0_A2_T_1 = cyc_A2 & _zSigma0_A2_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :537:{20,35}] wire [22:0] _zSigma0_A2_T_2 = mulAdd9Out_A[24:2]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:55] wire [22:0] _zSigma0_A2_T_3 = ~_zSigma0_A2_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:537:{41,55}] wire [22:0] zSigma0_A2 = _zSigma0_A2_T_1 ? _zSigma0_A2_T_3 : 23'h0; // @[DivSqrtRecF64_mulAddZ31.scala:537:{12,20,41}] wire [15:0] _r1_A1_T_1 = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74] wire [15:0] _partNegSigma0_A_T = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74, :548:71] wire [15:0] _r1_A1_T_2 = sqrtOp_PA ? {1'h0, _r1_A1_T} : _r1_A1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :538:{32,56,74}] wire [15:0] r1_A1 = _r1_A1_T_2 \| 16'h8000; // @[DivSqrtRecF64_mulAddZ31.scala:538:{27,32}] wire [16:0] _ER1_A1_sqrt_T_1 = {r1_A1, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:44] wire [16:0] ER1_A1_sqrt = _ER1_A1_sqrt_T ? _ER1_A1_sqrt_T_1 : {1'h0, r1_A1}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:{26,34,44}] wire [14:0] _fractR0_A_T = {zFractR0_A6_sqrt[14], zFractR0_A6_sqrt[13:0] \| zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :535:12, :542:39] wire [15:0] _hiSqrR0_A_sqrt_T = sqrR0_A5_sqrt[25:10]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :545:40] wire [24:0] _partNegSigma0_A_T_1 = cyc_A4_sqrt ? mulAdd9Out_A : {9'h0, _partNegSigma0_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :521:12, :548:{31,71}] wire [24:0] _nextMulAdd9A_A_T = ~mulAdd9Out_A; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :554:40] wire [13:0] _nextMulAdd9A_A_T_1 = _nextMulAdd9A_A_T[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:554:{40,53}] wire [13:0] _nextMulAdd9A_A_T_2 = entering_PA_normalCase_sqrt ? _nextMulAdd9A_A_T_1 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :554:{16,53}] wire [14:0] _nextMulAdd9A_A_T_3 = {1'h0, _nextMulAdd9A_A_T_2} \| zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :554:{16,64}] wire [8:0] _nextMulAdd9A_A_T_4 = sigB_PA[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :556:47] wire [8:0] _nextMulAdd9A_A_T_5 = cyc_A4_sqrt ? _nextMulAdd9A_A_T_4 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :556:{16,47}] wire [14:0] _nextMulAdd9A_A_T_6 = {_nextMulAdd9A_A_T_3[14:9], _nextMulAdd9A_A_T_3[8:0] \| _nextMulAdd9A_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:554:64, :555:68, :556:16] wire [8:0] _nextMulAdd9A_A_T_7 = zFractB_A4_div[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :557:27] wire [14:0] _nextMulAdd9A_A_T_8 = {_nextMulAdd9A_A_T_6[14:9], _nextMulAdd9A_A_T_6[8:0] \| _nextMulAdd9A_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:555:68, :556:64, :557:27] wire _nextMulAdd9A_A_T_9 = cyc_A5_sqrt \| cyc_A3; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :232:30, :558:29] wire [8:0] _nextMulAdd9A_A_T_10 = sigB_PA[52:44]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :558:47] wire [8:0] _nextMulAdd9A_A_T_11 = _nextMulAdd9A_A_T_9 ? _nextMulAdd9A_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:558:{16,29,47}] wire [14:0] _nextMulAdd9A_A_T_12 = {_nextMulAdd9A_A_T_8[14:9], _nextMulAdd9A_A_T_8[8:0] \| _nextMulAdd9A_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:556:64, :557:68, :558:16] wire [22:0] _nextMulAdd9A_A_T_13 = {8'h0, _nextMulAdd9A_A_T_12} \| zSigma0_A2; // @[DivSqrtRecF64_mulAddZ31.scala:537:12, :557:68, :558:64] wire [14:0] _nextMulAdd9B_A_T_1 = {6'h0, _nextMulAdd9B_A_T} \| zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :563:{28,73}] wire [8:0] _nextMulAdd9B_A_T_2 = sqrR0_A5_sqrt[9:1]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :565:43] wire [8:0] _nextMulAdd9B_A_T_3 = cyc_A5_sqrt ? _nextMulAdd9B_A_T_2 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :565:{16,43}] wire [14:0] _nextMulAdd9B_A_T_4 = {_nextMulAdd9B_A_T_1[14:9], _nextMulAdd9B_A_T_1[8:0] \| _nextMulAdd9B_A_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:563:73, :564:73, :565:16] wire [14:0] _nextMulAdd9B_A_T_5 = {_nextMulAdd9B_A_T_4[14], _nextMulAdd9B_A_T_4[13:0] \| zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:535:12, :564:73, :565:69] wire [8:0] _nextMulAdd9B_A_T_6 = hiSqrR0_A_sqrt[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :567:44] wire [8:0] _nextMulAdd9B_A_T_7 = cyc_A4_sqrt ? _nextMulAdd9B_A_T_6 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :567:{16,44}] wire [14:0] _nextMulAdd9B_A_T_8 = {_nextMulAdd9B_A_T_5[14:9], _nextMulAdd9B_A_T_5[8:0] \| _nextMulAdd9B_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:565:69, :566:73, :567:16] wire [7:0] _nextMulAdd9B_A_T_9 = fractR0_A[8:1]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :568:53] wire [8:0] _nextMulAdd9B_A_T_10 = {1'h1, _nextMulAdd9B_A_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:568:{33,53}] wire [8:0] _nextMulAdd9B_A_T_11 = cyc_A2 ? _nextMulAdd9B_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :568:{16,33}] wire [14:0] _nextMulAdd9B_A_T_12 = {_nextMulAdd9B_A_T_8[14:9], _nextMulAdd9B_A_T_8[8:0] \| _nextMulAdd9B_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:566:73, :567:69, :568:16] wire _GEN = cyc_A1 \| cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :255:36, :577:16] wire _io_latchMulAddA_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] assign _io_latchMulAddA_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] wire _io_latchMulAddB_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:591:16] assign _io_latchMulAddB_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16, :591:16] wire _io_latchMulAddA_0_T_1 = _io_latchMulAddA_0_T \| cyc_B6_div; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :577:{16,31}] wire _io_latchMulAddA_0_T_2 = _io_latchMulAddA_0_T_1 \| cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :577:{31,45}] wire _io_latchMulAddA_0_T_3 = _io_latchMulAddA_0_T_2 \| cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :577:{45,55}] wire _io_latchMulAddA_0_T_4 = _io_latchMulAddA_0_T_3 \| cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :577:{55,65}] wire _io_latchMulAddA_0_T_5 = _io_latchMulAddA_0_T_4 \| cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :577:65, :578:25] assign _io_latchMulAddA_0_T_6 = _io_latchMulAddA_0_T_5 \| cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :578:{25,35}] assign io_latchMulAddA_0_0 = _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :578:35] wire [52:0] _io_mulAddA_0_T = {ER1_A1_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:539:26, :580:51] wire [52:0] _io_mulAddA_0_T_1 = cyc_A1_sqrt ? _io_mulAddA_0_T : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :580:{12,51}] wire _io_mulAddA_0_T_2 = cyc_B7_sqrt \| cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :255:36, :581:25] wire [52:0] _io_mulAddA_0_T_3 = _io_mulAddA_0_T_2 ? sigB_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :581:{12,25}] wire [52:0] _io_mulAddA_0_T_4 = _io_mulAddA_0_T_1 \| _io_mulAddA_0_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:580:{12,63}, :581:12] wire [52:0] _io_mulAddA_0_T_5 = cyc_B6_div ? sigA_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :348:28, :582:12] wire [52:0] _io_mulAddA_0_T_6 = _io_mulAddA_0_T_4 \| _io_mulAddA_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:580:63, :581:63, :582:12] wire [33:0] _io_mulAddA_0_T_7 = zSigma1_B4[45:12]; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :583:19] wire [52:0] _io_mulAddA_0_T_8 = {_io_mulAddA_0_T_6[52:34], _io_mulAddA_0_T_6[33:0] \| _io_mulAddA_0_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:581:63, :582:63, :583:19] wire _io_mulAddA_0_T_9 = cyc_B3 \| cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :283:35, :585:20] wire [45:0] _io_mulAddA_0_T_10 = sigXNU_B3_CX[57:12]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :585:48] wire [45:0] _io_mulAddA_0_T_11 = _io_mulAddA_0_T_9 ? _io_mulAddA_0_T_10 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:585:{12,20,48}] wire [52:0] _io_mulAddA_0_T_12 = {_io_mulAddA_0_T_8[52:46], _io_mulAddA_0_T_8[45:0] \| _io_mulAddA_0_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:582:63, :583:67, :585:12] wire [32:0] _io_mulAddA_0_T_13 = sigXN_C[57:25]; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :586:43] wire [45:0] _io_mulAddA_0_T_14 = {_io_mulAddA_0_T_13, 13'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:586:{43,51}] wire [45:0] _io_mulAddA_0_T_15 = cyc_C4_div ? _io_mulAddA_0_T_14 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:292:29, :586:{12,51}] wire [52:0] _io_mulAddA_0_T_16 = {_io_mulAddA_0_T_12[52:46], _io_mulAddA_0_T_12[45:0] \| _io_mulAddA_0_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:583:67, :585:63, :586:12] wire [45:0] _io_mulAddA_0_T_17 = {u_C_sqrt, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :587:44] wire [45:0] _io_mulAddA_0_T_18 = cyc_C4_sqrt ? _io_mulAddA_0_T_17 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:298:30, :587:{12,44}] wire [52:0] _io_mulAddA_0_T_19 = {_io_mulAddA_0_T_16[52:46], _io_mulAddA_0_T_16[45:0] \| _io_mulAddA_0_T_18}; // @[DivSqrtRecF64_mulAddZ31.scala:585:63, :586:63, :587:12] wire [52:0] _io_mulAddA_0_T_20 = cyc_C1_div ? sigB_PC : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :419:28, :588:12] wire [52:0] _io_mulAddA_0_T_21 = _io_mulAddA_0_T_19 \| _io_mulAddA_0_T_20; // @[DivSqrtRecF64_mulAddZ31.scala:586:63, :587:63, :588:12] assign _io_mulAddA_0_T_22 = {1'h0, _io_mulAddA_0_T_21} \| zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :587:63, :588:63] assign io_mulAddA_0_0 = _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :588:63] wire _io_latchMulAddB_0_T_1 = _io_latchMulAddB_0_T \| cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :591:{16,31}] wire _io_latchMulAddB_0_T_2 = _io_latchMulAddB_0_T_1 \| cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :591:{31,46}] wire _io_latchMulAddB_0_T_3 = _io_latchMulAddB_0_T_2 \| cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :591:{46,56}] wire _io_latchMulAddB_0_T_4 = _io_latchMulAddB_0_T_3 \| cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :591:56, :592:25] assign _io_latchMulAddB_0_T_5 = _io_latchMulAddB_0_T_4 \| cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :592:{25,35}] assign io_latchMulAddB_0_0 = _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :592:35] wire [51:0] _io_mulAddB_0_T = {r1_A1, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :580:51, :594:31] wire [51:0] _io_mulAddB_0_T_1 = cyc_A1 ? _io_mulAddB_0_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :594:{12,31}] wire [50:0] _io_mulAddB_0_T_2 = {ESqrR1_B_sqrt, 19'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :595:39] wire [50:0] _io_mulAddB_0_T_3 = cyc_B7_sqrt ? _io_mulAddB_0_T_2 : 51'h0; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :595:{12,39}] wire [51:0] _io_mulAddB_0_T_4 = {_io_mulAddB_0_T_1[51], _io_mulAddB_0_T_1[50:0] \| _io_mulAddB_0_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:594:{12,51}, :595:12] wire [52:0] _io_mulAddB_0_T_5 = {ER1_B_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :580:51, :596:36] wire [52:0] _io_mulAddB_0_T_6 = cyc_B6_sqrt ? _io_mulAddB_0_T_5 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :596:{12,36}] wire [52:0] _io_mulAddB_0_T_7 = {1'h0, _io_mulAddB_0_T_4} \| _io_mulAddB_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:594:51, :595:51, :596:12] wire [52:0] _io_mulAddB_0_T_8 = {_io_mulAddB_0_T_7[52:46], _io_mulAddB_0_T_7[45:0] \| zSigma1_B4}; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :595:51, :596:51] wire [29:0] _io_mulAddB_0_T_9 = sqrSigma1_C[30:1]; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :598:37] wire [29:0] _io_mulAddB_0_T_10 = cyc_C6_sqrt ? _io_mulAddB_0_T_9 : 30'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :598:{12,37}] wire [52:0] _io_mulAddB_0_T_11 = {_io_mulAddB_0_T_8[52:30], _io_mulAddB_0_T_8[29:0] \| _io_mulAddB_0_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:596:51, :597:55, :598:12] wire [32:0] _io_mulAddB_0_T_12 = cyc_C4 ? sqrSigma1_C : 33'h0; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :286:30, :599:12] wire [52:0] _io_mulAddB_0_T_13 = {_io_mulAddB_0_T_11[52:33], _io_mulAddB_0_T_11[32:0] \| _io_mulAddB_0_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:597:55, :598:51, :599:12] assign _io_mulAddB_0_T_14 = {1'h0, _io_mulAddB_0_T_13} \| zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :598:51, :599:51] assign io_mulAddB_0_0 = _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :599:51] wire _io_usingMulAdd_T = cyc_A4 \| cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:231:30, :236:29, :603:20] wire _io_usingMulAdd_T_1 = _io_usingMulAdd_T \| cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :603:{20,34}] wire _io_usingMulAdd_T_2 = _io_usingMulAdd_T_1 \| cyc_B10_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:252:36, :603:{34,48}] wire _io_usingMulAdd_T_3 = _io_usingMulAdd_T_2 \| cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :603:48, :604:30] wire _io_usingMulAdd_T_4 = _io_usingMulAdd_T_3 \| cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :604:{30,45}] wire _io_usingMulAdd_T_5 = _io_usingMulAdd_T_4 \| cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :604:{45,60}] wire _io_usingMulAdd_T_6 = _io_usingMulAdd_T_5 \| cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :604:{60,70}] wire _io_usingMulAdd_T_7 = _io_usingMulAdd_T_6 \| cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :604:70, :605:29] wire _io_usingMulAdd_T_8 = _io_usingMulAdd_T_7 \| cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :605:{29,44}] wire _io_usingMulAdd_T_9 = _io_usingMulAdd_T_8 \| cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :605:{44,58}] wire _io_usingMulAdd_T_10 = _io_usingMulAdd_T_9 \| cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :605:{58,73}] wire _io_usingMulAdd_T_11 = cyc_A3 \| cyc_A2_div; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :237:29, :607:20] wire _io_usingMulAdd_T_12 = _io_usingMulAdd_T_11 \| cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :607:{20,34}] wire _io_usingMulAdd_T_13 = _io_usingMulAdd_T_12 \| cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :607:34, :608:29] wire _io_usingMulAdd_T_14 = _io_usingMulAdd_T_13 \| cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :608:{29,44}] wire _io_usingMulAdd_T_15 = _io_usingMulAdd_T_14 \| cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :608:{44,54}] wire _io_usingMulAdd_T_16 = _io_usingMulAdd_T_15 \| cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :608:{54,64}] wire _io_usingMulAdd_T_17 = _io_usingMulAdd_T_16 \| cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :608:64, :609:29] wire _io_usingMulAdd_T_18 = _io_usingMulAdd_T_17 \| cyc_B1_div; // @[DivSqrtRecF64_mulAddZ31.scala:269:29, :609:{29,44}] wire _io_usingMulAdd_T_19 = _io_usingMulAdd_T_18 \| cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :609:{44,58}] wire _io_usingMulAdd_T_20 = _io_usingMulAdd_T_19 \| cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :609:{58,73}] wire _io_usingMulAdd_T_21 = cyc_A2 \| cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :238:29, :611:20] wire _io_usingMulAdd_T_22 = _io_usingMulAdd_T_21 \| cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :611:{20,34}] wire _io_usingMulAdd_T_23 = _io_usingMulAdd_T_22 \| cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :611:34, :612:29] wire _io_usingMulAdd_T_24 = _io_usingMulAdd_T_23 \| cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :612:{29,44}] wire _io_usingMulAdd_T_25 = _io_usingMulAdd_T_24 \| cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :612:{44,54}] wire _io_usingMulAdd_T_26 = _io_usingMulAdd_T_25 \| cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :612:{54,64}] wire _io_usingMulAdd_T_27 = _io_usingMulAdd_T_26 \| cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :612:64, :613:29] wire _io_usingMulAdd_T_28 = _io_usingMulAdd_T_27 \| cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :613:{29,44}] wire _io_usingMulAdd_T_29 = _io_usingMulAdd_T_28 \| cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :613:{44,54}] wire _io_usingMulAdd_T_30 = io_latchMulAddA_0_0 \| cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :257:30, :615:31] wire _io_usingMulAdd_T_31 = _io_usingMulAdd_T_30 \| cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :615:{31,41}] wire [1:0] io_usingMulAdd_lo = {_io_usingMulAdd_T_29, _io_usingMulAdd_T_31}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :613:54, :615:41] wire [1:0] io_usingMulAdd_hi = {_io_usingMulAdd_T_10, _io_usingMulAdd_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :605:73, :609:73] assign _io_usingMulAdd_T_32 = {io_usingMulAdd_hi, io_usingMulAdd_lo}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] assign io_usingMulAdd_0 = _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :603:12] wire [104:0] _io_mulAddC_2_T = {sigX1_B, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :619:45] wire [104:0] _io_mulAddC_2_T_1 = cyc_B1 ? _io_mulAddC_2_T : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :619:{12,45}] wire [103:0] _io_mulAddC_2_T_2 = {sigX1_B, 46'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :620:45] wire [103:0] _io_mulAddC_2_T_3 = cyc_C6_sqrt ? _io_mulAddC_2_T_2 : 104'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :620:{12,45}] wire [104:0] _io_mulAddC_2_T_4 = {_io_mulAddC_2_T_1[104], _io_mulAddC_2_T_1[103:0] \| _io_mulAddC_2_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:619:{12,62}, :620:12] wire _io_mulAddC_2_T_5 = cyc_C4_sqrt \| cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :298:30, :621:25] wire [104:0] _io_mulAddC_2_T_6 = {sigXN_C, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :619:45, :621:45] wire [104:0] _io_mulAddC_2_T_7 = _io_mulAddC_2_T_5 ? _io_mulAddC_2_T_6 : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:621:{12,25,45}] wire [104:0] _io_mulAddC_2_T_8 = _io_mulAddC_2_T_4 \| _io_mulAddC_2_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:619:62, :620:62, :621:12] wire _io_mulAddC_2_T_9 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27] wire _io_mulAddC_2_T_10 = cyc_E3_div & _io_mulAddC_2_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:313:29, :622:{24,27}] wire [53:0] _io_mulAddC_2_T_11 = {bit0FractA_PC, 53'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:126:30, :622:51] wire [53:0] _io_mulAddC_2_T_12 = _io_mulAddC_2_T_10 ? _io_mulAddC_2_T_11 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:622:{12,24,51}] wire [104:0] _io_mulAddC_2_T_13 = {_io_mulAddC_2_T_8[104:54], _io_mulAddC_2_T_8[53:0] \| _io_mulAddC_2_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:620:62, :621:62, :622:12] wire _io_mulAddC_2_T_14 = sExp_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :624:25] wire _io_mulAddC_2_T_15 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25] wire _io_mulAddC_2_T_18 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:39] wire _io_mulAddC_2_T_20 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:54] wire [1:0] _io_mulAddC_2_T_16 = {_io_mulAddC_2_T_15, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:625:{25,28}] wire _io_mulAddC_2_T_17 = sigB_PC[1]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :626:26] wire _io_mulAddC_2_T_19 = _io_mulAddC_2_T_17 ^ _io_mulAddC_2_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:626:{26,30,39}] wire [1:0] _io_mulAddC_2_T_21 = {_io_mulAddC_2_T_19, _io_mulAddC_2_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:626:{30,44,54}] wire [1:0] _io_mulAddC_2_T_22 = _io_mulAddC_2_T_14 ? _io_mulAddC_2_T_16 : _io_mulAddC_2_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:624:{17,25}, :625:28, :626:44] wire _io_mulAddC_2_T_23 = sigT_E[0]; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :627:28] wire _io_mulAddC_2_T_24 = ~_io_mulAddC_2_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,28}] wire [1:0] _io_mulAddC_2_T_25 = {_io_mulAddC_2_T_24, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,32}] wire [1:0] _io_mulAddC_2_T_26 = _io_mulAddC_2_T_22 ^ _io_mulAddC_2_T_25; // @[DivSqrtRecF64_mulAddZ31.scala:624:17, :627:{16,32}] wire [55:0] _io_mulAddC_2_T_27 = {_io_mulAddC_2_T_26, 54'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:16, :628:14] wire [55:0] _io_mulAddC_2_T_28 = cyc_E3_sqrt ? _io_mulAddC_2_T_27 : 56'h0; // @[DivSqrtRecF64_mulAddZ31.scala:318:30, :623:12, :628:14] assign _io_mulAddC_2_T_29 = {_io_mulAddC_2_T_13[104:56], _io_mulAddC_2_T_13[55:0] \| _io_mulAddC_2_T_28}; // @[DivSqrtRecF64_mulAddZ31.scala:621:62, :622:62, :623:12] assign io_mulAddC_2_0 = _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :622:62] wire [31:0] ESqrR1_B8_sqrt = io_mulAddResult_3_0[103:72]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :632:43] wire [45:0] _zSigma1_B4_T = io_mulAddResult_3_0[90:45]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :633:49] wire [45:0] _zSigma1_B4_T_1 = ~_zSigma1_B4_T; // @[DivSqrtRecF64_mulAddZ31.scala:633:{31,49}] assign _zSigma1_B4_T_2 = cyc_B4 ? _zSigma1_B4_T_1 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :633:{22,31}] assign zSigma1_B4 = _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :633:22] wire [32:0] sqrSigma1_B1 = io_mulAddResult_3_0[79:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :634:41] assign _sigXNU_B3_CX_T = io_mulAddResult_3_0[104:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :635:38] assign sigXNU_B3_CX = _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :635:38] wire _E_C1_div_T = io_mulAddResult_3_0[104]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :636:39] wire E_C1_div = ~_E_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:636:{20,39}] wire _zComplSigT_C1_T = ~E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:636:20, :638:28] wire _zComplSigT_C1_T_1 = cyc_C1_div & _zComplSigT_C1_T; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :638:{25,28}] wire _zComplSigT_C1_T_2 = _zComplSigT_C1_T_1 \| cyc_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :638:{25,40}] wire [53:0] _zComplSigT_C1_T_3 = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31] wire [53:0] _zComplSigT_C1_sqrt_T = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31, :644:44] wire [53:0] _zComplSigT_C1_T_4 = ~_zComplSigT_C1_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:639:{13,31}] wire [53:0] _zComplSigT_C1_T_5 = _zComplSigT_C1_T_2 ? _zComplSigT_C1_T_4 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:638:{12,40}, :639:13] wire _zComplSigT_C1_T_6 = cyc_C1_div & E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :636:20, :642:24] wire [52:0] _zComplSigT_C1_T_7 = io_mulAddResult_3_0[102:50]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :642:55] wire [52:0] _zComplSigT_C1_T_8 = ~_zComplSigT_C1_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:642:{37,55}] wire [52:0] _zComplSigT_C1_T_9 = _zComplSigT_C1_T_6 ? _zComplSigT_C1_T_8 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:642:{12,24,37}] assign _zComplSigT_C1_T_10 = {_zComplSigT_C1_T_5[53], _zComplSigT_C1_T_5[52:0] \| _zComplSigT_C1_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:638:12, :641:11, :642:12] assign zComplSigT_C1 = _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :641:11] wire [53:0] _zComplSigT_C1_sqrt_T_1 = ~_zComplSigT_C1_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:644:{26,44}] assign _zComplSigT_C1_sqrt_T_2 = cyc_C1_sqrt ? _zComplSigT_C1_sqrt_T_1 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :644:{12,26}] assign zComplSigT_C1_sqrt = _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :644:12] wire [53:0] sigT_C1 = ~zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :648:19] wire [55:0] remT_E2 = io_mulAddResult_3_0[55:0]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :649:36] wire [30:0] _u_C_sqrt_T = sigXNU_B3_CX[56:26]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :665:33] wire _isNegRemT_E_T = remT_E2[55]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:47] wire _isNegRemT_E_T_1 = remT_E2[53]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:61] wire _isNegRemT_E_T_2 = sqrtOp_PC ? _isNegRemT_E_T : _isNegRemT_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :673:{27,47,61}] wire [53:0] _isZeroRemT_E_T = remT_E2[53:0]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :675:21] wire _isZeroRemT_E_T_1 = _isZeroRemT_E_T == 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:675:{21,29}] wire _isZeroRemT_E_T_2 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :676:18] wire [1:0] _isZeroRemT_E_T_3 = remT_E2[55:54]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :676:41] wire _isZeroRemT_E_T_4 = _isZeroRemT_E_T_3 == 2'h0; // @[DivSqrtRecF64_mulAddZ31.scala:676:{41,50}] wire _isZeroRemT_E_T_5 = _isZeroRemT_E_T_2 \| _isZeroRemT_E_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:676:{18,30,50}] wire _isZeroRemT_E_T_6 = _isZeroRemT_E_T_1 & _isZeroRemT_E_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:675:{29,38}, :676:30] wire _trueLtX_E1_T = ~isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :686:24] wire _trueLtX_E1_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41] wire _trueLtX_E1_T_2 = _trueLtX_E1_T & _trueLtX_E1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:686:{24,38,41}] wire trueLtX_E1 = sqrtOp_PC ? _trueLtX_E1_T_2 : isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :145:30, :686:{12,38}] wire [13:0] _sExpP1_PC_T = {sExp_PC[12], sExp_PC} + 14'h1; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :694:29] wire [12:0] _sExpP1_PC_T_1 = _sExpP1_PC_T[12:0]; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [12:0] sExpP1_PC = _sExpP1_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [54:0] _GEN_0 = {1'h0, sigT_E}; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :695:27] wire [54:0] sigTP1_E = _GEN_0 + 55'h1; // @[DivSqrtRecF64_mulAddZ31.scala:695:27] wire _io_rawOutValid_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :699:42] assign _io_rawOutValid_div_T_1 = leaving_PC & _io_rawOutValid_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :699:{39,42}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :699:39] assign _io_rawOutValid_sqrt_T = leaving_PC & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :155:26, :700:39] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :700:39] assign _io_invalidExc_T = majorExc_PC & isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :121:30, :702:40] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :702:40] wire _io_infiniteExc_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25, :703:43] assign _io_infiniteExc_T_1 = majorExc_PC & _io_infiniteExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :703:{40,43}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :703:40] wire _io_rawOut_sExp_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :709:13] wire _io_rawOut_sExp_T_1 = _io_rawOut_sExp_T & E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :709:{13,25}] wire [12:0] _io_rawOut_sExp_T_2 = _io_rawOut_sExp_T_1 ? sExp_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :709:{12,25}] wire _io_rawOut_sExp_T_3 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :710:13] wire _io_rawOut_sExp_T_4 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27, :710:28] wire _io_rawOut_sExp_T_5 = _io_rawOut_sExp_T_3 & _io_rawOut_sExp_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:710:{13,25,28}] wire [12:0] _io_rawOut_sExp_T_6 = _io_rawOut_sExp_T_5 ? sExpP1_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:694:29, :710:{12,25}] wire [12:0] _io_rawOut_sExp_T_7 = _io_rawOut_sExp_T_2 \| _io_rawOut_sExp_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:709:{12,72}, :710:12] wire [12:0] _io_rawOut_sExp_T_8 = _io_rawOut_sExp_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:709:72] wire [11:0] _io_rawOut_sExp_T_9 = sExp_PC[12:1]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :711:47] wire [12:0] _io_rawOut_sExp_T_10 = {_io_rawOut_sExp_T_9[11], _io_rawOut_sExp_T_9} + 13'h400; // @[DivSqrtRecF64_mulAddZ31.scala:711:{47,52}] wire [12:0] _io_rawOut_sExp_T_11 = sqrtOp_PC ? _io_rawOut_sExp_T_10 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :711:{12,52}] wire [12:0] _io_rawOut_sExp_T_12 = _io_rawOut_sExp_T_8 \| _io_rawOut_sExp_T_11; // @[DivSqrtRecF64_mulAddZ31.scala:709:72, :710:72, :711:12] assign _io_rawOut_sExp_T_13 = _io_rawOut_sExp_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :710:72] wire [54:0] _io_rawOut_sig_T = trueLtX_E1 ? _GEN_0 : sigTP1_E; // @[DivSqrtRecF64_mulAddZ31.scala:686:12, :695:27, :712:25] wire _io_rawOut_sig_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41, :712:59] assign _io_rawOut_sig_T_2 = {_io_rawOut_sig_T, _io_rawOut_sig_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:712:{25,56,59}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :712:56] wire _T_18 = entering_PA_normalCase_sqrt \| cyc_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :225:35, :551:21] always @(posedge clock) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (reset) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] cycleNum_A <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] cycleNum_B <= 4'h0; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] cycleNum_C <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] cycleNum_E <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] valid_PA <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] valid_PB <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] valid_PC <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] end else begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (\|{entering_PA_normalCase, cycleNum_A}) // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :213:36, :217:{34,49}] cycleNum_A <= _cycleNum_A_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :220:69] if (\|{cyc_A1, cycleNum_B}) // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :234:30, :244:{18,33}] cycleNum_B <= _cycleNum_B_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :246:16] if (\|{cyc_B1, cycleNum_C}) // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :262:30, :278:{18,33}] cycleNum_C <= _cycleNum_C_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:16] if (\|{cyc_C1, cycleNum_E}) // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :289:30, :303:{18,33}] cycleNum_E <= _cycleNum_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:26] if (entering_PA \| leaving_PA) // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :325:32, :327:23] valid_PA <= entering_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:32] if (entering_PB \| leaving_PB) // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :364:37, :366:23] valid_PB <= entering_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :364:37] if (entering_PC \| leaving_PC) // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :398:37, :400:23] valid_PC <= entering_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :398:37] end if (entering_PA) begin // @[DivSqrtRecF64_mulAddZ31.scala:325:32] sqrtOp_PA <= io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :92:30] majorExc_PA <= majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:93:30, :176:12] isNaN_PA <= isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :183:12] isInf_PA <= isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :187:23] isZero_PA <= isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :188:23] sign_PA <= sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:98:30, :189:47] end if (entering_PA_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:213:36] sExp_PA <= _sExp_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :339:23] fractB_PA <= _fractB_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :340:32] roundingMode_PA <= io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :102:30] end if (entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50] fractA_PA <= _fractA_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :344:32] if (entering_PB) begin // @[DivSqrtRecF64_mulAddZ31.scala:364:37] sqrtOp_PB <= _sqrtOp_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :370:27] majorExc_PB <= _majorExc_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:106:30, :371:27] isNaN_PB <= _isNaN_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :372:27] isInf_PB <= _isInf_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :373:27] isZero_PB <= _isZero_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :374:27] sign_PB <= _sign_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:111:30, :375:27] end if (entering_PB_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:363:35] sExp_PB <= sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :112:30] bit0FractA_PB <= _bit0FractA_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :379:37] fractB_PB <= fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :114:30] roundingMode_PB <= _roundingMode_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:115:30, :381:31] end if (entering_PC) begin // @[DivSqrtRecF64_mulAddZ31.scala:398:37] sqrtOp_PC <= _sqrtOp_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :404:27] majorExc_PC <= _majorExc_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :405:27] isNaN_PC <= _isNaN_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :406:27] isInf_PC <= _isInf_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :407:27] isZero_PC <= _isZero_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :408:27] sign_PC <= _sign_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:124:30, :409:27] end if (entering_PC_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:397:35] sExp_PC <= sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30, :125:30] bit0FractA_PC <= bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :126:30] fractB_PC <= fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30, :127:30] roundingMode_PC <= _roundingMode_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:128:30, :415:31] end if (cyc_A6_sqrt \| entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :225:35, :541:23] fractR0_A <= _fractR0_A_T[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :542:{19,39}] if (cyc_A5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:226:35] hiSqrR0_A_sqrt <= _hiSqrR0_A_sqrt_T[9:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :545:{24,40}] if (cyc_A4_sqrt \| cyc_A3) // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :232:30, :547:23] partNegSigma0_A <= _partNegSigma0_A_T_1[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :548:{25,31}] if (_T_18 \| cyc_A5_sqrt \| cyc_A4 \| cyc_A3 \| cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :232:30, :233:30, :551:{21,36,51,61,71}] nextMulAdd9A_A <= _nextMulAdd9A_A_T_13[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :553:24, :558:64] if (_T_18 \| cyc_A5_sqrt \| cyc_A4 \| cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :233:30, :551:21, :561:{38,53,63}] nextMulAdd9B_A <= _nextMulAdd9B_A_T_12[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :562:24, :567:69] if (cyc_A1_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:242:30] ER1_B_sqrt <= ER1_A1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :539:26] if (cyc_B8_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:254:36] ESqrR1_B_sqrt <= ESqrR1_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :632:43] if (cyc_B3) // @[DivSqrtRecF64_mulAddZ31.scala:260:30] sigX1_B <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :158:34] if (cyc_B1) // @[DivSqrtRecF64_mulAddZ31.scala:262:30] sqrSigma1_C <= sqrSigma1_B1; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :634:41] if (cyc_C6_sqrt \| cyc_C5_div \| cyc_C3_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :291:29, :299:30, :661:{23,37}] sigXN_C <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :158:34] if (cyc_C5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:297:30] u_C_sqrt <= _u_C_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :665:33] if (cyc_C1) begin // @[DivSqrtRecF64_mulAddZ31.scala:289:30] E_E_div <= E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :636:20] sigT_E <= sigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :648:19] end if (cyc_E2) begin // @[DivSqrtRecF64_mulAddZ31.scala:309:30] isNegRemT_E <= _isNegRemT_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :673:27] isZeroRemT_E <= _isZeroRemT_E_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :675:38] end always @(posedge) assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<32>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<4>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<32>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<4>, mask : UInt<1>}}, bs_wdat : { data : UInt<32>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<4>, clock, reset, UInt<4>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<2>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 0, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 1, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<3>(0h7)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h2)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 2) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 2) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid \|\| queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<4>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<4>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_18 = and(s2_valid, s3_ready) when _T_18 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_19 = eq(s3_ready, UInt<1>(0h0)) node _T_20 = and(s2_valid, _T_19) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<4>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 31, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 31, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_21 = eq(s3_full, UInt<1>(0h0)) node _T_22 = eq(s3_need_r, UInt<1>(0h0)) node _T_23 = or(_T_21, _T_22) node _T_24 = or(_T_23, queue.io.deq.valid) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid)\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_28 = and(s3_valid, s4_ready) when _T_28 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_29 = eq(s4_ready, UInt<1>(0h0)) node _T_30 = and(s3_valid, _T_29) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<4>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<32>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_5 = or(_io_bs_wadr_bits_mask_T_4, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_6 = or(_io_bs_wadr_bits_mask_T_5, _io_bs_wadr_bits_mask_T_3) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_6 connect io.bs_wdat.data, atomics.io.data_out node _T_31 = and(s4_full, s4_need_pb) node _T_32 = and(_T_31, s4_pdata.corrupt) node _T_33 = eq(_T_32, UInt<1>(0h0)) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_38 = and(io.bs_wadr.valid, _T_37) node _T_39 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_40 = and(s4_req.prio[0], _T_39) node _T_41 = eq(s4_req.param, UInt<3>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_44 = and(s4_req.prio[0], _T_43) node _T_45 = eq(s4_req.param, UInt<3>(0h1)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_48 = and(s4_req.prio[0], _T_47) node _T_49 = eq(s4_req.param, UInt<3>(0h2)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_52 = and(s4_req.prio[0], _T_51) node _T_53 = eq(s4_req.param, UInt<3>(0h3)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_56 = and(s4_req.prio[0], _T_55) node _T_57 = eq(s4_req.param, UInt<3>(0h4)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_60 = and(s4_req.prio[0], _T_59) node _T_61 = eq(s4_req.param, UInt<3>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_64 = and(s4_req.prio[0], _T_63) node _T_65 = eq(s4_req.param, UInt<3>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_68 = and(s4_req.prio[0], _T_67) node _T_69 = eq(s4_req.param, UInt<3>(0h2)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_72 = and(s4_req.prio[0], _T_71) node _T_73 = eq(s4_req.param, UInt<3>(0h3)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(s4_need_bs, UInt<1>(0h0)) node _T_76 = or(io.bs_wadr.ready, _T_75) when _T_76 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<4>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<32>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<4>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<32>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<32>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<2>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 0, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 1, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<2>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 0, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 1, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<2>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 0, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 1, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 31, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 31, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 31, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 31, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 31, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 31, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_77 = and(io.req.valid, s2) node _T_78 = and(_T_77, s3) node _T_79 = and(_T_78, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_80 = and(io.req.valid, s2_1) node _T_81 = and(_T_80, s3_1) node _T_82 = and(_T_81, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_83 = and(io.req.valid, s2_2) node _T_84 = and(_T_83, s3_2) node _T_85 = and(_T_84, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_86 = and(io.req.valid, s2_3) node _T_87 = and(_T_86, s3_3) node _T_88 = and(_T_87, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_89 = and(io.req.valid, s2_4) node _T_90 = and(_T_89, s3_4) node _T_91 = and(_T_90, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_92 = and(io.req.valid, s2_5) node _T_93 = and(_T_92, s3_5) node _T_94 = and(_T_93, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_95 = and(io.req.valid, s2_6) node _T_96 = and(_T_95, s3_6) node _T_97 = and(_T_96, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_98 = and(io.req.valid, s2_7) node _T_99 = and(_T_98, s3_7) node _T_100 = and(_T_99, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<2>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 0, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 1, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<2>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 0, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 1, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<2>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 0, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 1, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [31:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [31:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [3:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [31:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [31:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [31:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [31:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [3:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [31:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_rel_pop_ready = 1'h1; // @[SourceD.scala:48:7] wire [31:0] io_rel_beat_data = 32'h0; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt = 1'h0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [2:0] s1_mask_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_4_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_5_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_6_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_2_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_3_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_4_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [3:0] _s2_pdata_raw_mask_T = 4'hF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [31:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [3:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [31:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [31:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [3:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _s1_mask_sizeOH_T_1 = 2'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h2; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [3:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:2]; // @[package.scala:243:46] wire [3:0] s1_beats1 = s1_single ? 4'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [3:0] _s1_beat_T = s1_req_offset[5:2]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 4'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [4:0] _s1_counter_T = {1'h0, s1_counter} + 5'h1; // @[SourceD.scala:86:27, :130:30] wire [3:0] _s1_counter_T_1 = _s1_counter_T[3:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [3:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [31:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [3:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [31:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [3:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [31:0] s2_pdata_r_data; // @[package.scala:88:63] reg [3:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [31:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [3:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : 32'h0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 4'hF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 & io_pb_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = ~s2_req_prio_0 \| io_pb_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [3:0] s3_beat; // @[SourceD.scala:192:26] wire [3:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [31:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [3:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [31:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [31:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [31:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [31:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [31:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [3:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [3:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [31:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [3:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [31:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_5 = _io_bs_wadr_bits_mask_T_4 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_6 = _io_bs_wadr_bits_mask_T_5 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:48:7, :275:87]
Generate the Verilog code corresponding to this FIRRTL code module Tile_91 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_347 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_91( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_347 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = and(_T_318, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = and(_T_317, _T_325) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_326, UInt<1>(0h1), "") : assert_2 node _T_330 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<7>(0h40)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_24) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<7>(0h41)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_25) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<7>(0h42)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_26) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<7>(0h43)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_27) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_356 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_357 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_358 = shr(io.in.a.bits.source, 5) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_28) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_364 = shr(io.in.a.bits.source, 5) node _T_365 = eq(_T_364, UInt<1>(0h1)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_29) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_370 = shr(io.in.a.bits.source, 5) node _T_371 = eq(_T_370, UInt<2>(0h2)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_30) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_376 = shr(io.in.a.bits.source, 5) node _T_377 = eq(_T_376, UInt<2>(0h3)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_31) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_382 = shr(io.in.a.bits.source, 5) node _T_383 = eq(_T_382, UInt<3>(0h4)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_32) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_388 = shr(io.in.a.bits.source, 5) node _T_389 = eq(_T_388, UInt<3>(0h5)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_33) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_394 = shr(io.in.a.bits.source, 5) node _T_395 = eq(_T_394, UInt<3>(0h6)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_34) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<3>(0h7)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_35) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_330 connect _WIRE[1], _T_336 connect _WIRE[2], _T_342 connect _WIRE[3], _T_348 connect _WIRE[4], _T_354 connect _WIRE[5], _T_355 connect _WIRE[6], _T_356 connect _WIRE[7], _T_357 connect _WIRE[8], _T_363 connect _WIRE[9], _T_369 connect _WIRE[10], _T_375 connect _WIRE[11], _T_381 connect _WIRE[12], _T_387 connect _WIRE[13], _T_393 connect _WIRE[14], _T_399 connect _WIRE[15], _T_405 connect _WIRE[16], _T_406 node _T_407 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_408 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_410 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_411 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_412 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_413 = mux(_WIRE[5], _T_407, UInt<1>(0h0)) node _T_414 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_415 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_416 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = or(_T_408, _T_409) node _T_426 = or(_T_425, _T_410) node _T_427 = or(_T_426, _T_411) node _T_428 = or(_T_427, _T_412) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_414) node _T_431 = or(_T_430, _T_415) node _T_432 = or(_T_431, _T_416) node _T_433 = or(_T_432, _T_417) node _T_434 = or(_T_433, _T_418) node _T_435 = or(_T_434, _T_419) node _T_436 = or(_T_435, _T_420) node _T_437 = or(_T_436, _T_421) node _T_438 = or(_T_437, _T_422) node _T_439 = or(_T_438, _T_423) node _T_440 = or(_T_439, _T_424) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_440 node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _T_444 = or(UInt<1>(0h0), _T_443) node _T_445 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_446 = cvt(_T_445) node _T_447 = and(_T_446, asSInt(UInt<13>(0h1000))) node _T_448 = asSInt(_T_447) node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0))) node _T_450 = and(_T_444, _T_449) node _T_451 = or(UInt<1>(0h0), _T_450) node _T_452 = and(_WIRE_1, _T_451) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_452, UInt<1>(0h1), "") : assert_3 node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(source_ok, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_459 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_459, UInt<1>(0h1), "") : assert_5 node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(is_aligned, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_466 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_466, UInt<1>(0h1), "") : assert_7 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_471, UInt<1>(0h1), "") : assert_8 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_475, UInt<1>(0h1), "") : assert_9 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<7>(0h40)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_36) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<7>(0h41)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_37) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<7>(0h42)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_38) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<7>(0h43)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_39) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_509 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_510 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_511 = shr(io.in.a.bits.source, 5) node _T_512 = eq(_T_511, UInt<1>(0h0)) node _T_513 = leq(UInt<1>(0h0), uncommonBits_40) node _T_514 = and(_T_512, _T_513) node _T_515 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_517 = shr(io.in.a.bits.source, 5) node _T_518 = eq(_T_517, UInt<1>(0h1)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_41) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_522 = and(_T_520, _T_521) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_523 = shr(io.in.a.bits.source, 5) node _T_524 = eq(_T_523, UInt<2>(0h2)) node _T_525 = leq(UInt<1>(0h0), uncommonBits_42) node _T_526 = and(_T_524, _T_525) node _T_527 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_528 = and(_T_526, _T_527) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_529 = shr(io.in.a.bits.source, 5) node _T_530 = eq(_T_529, UInt<2>(0h3)) node _T_531 = leq(UInt<1>(0h0), uncommonBits_43) node _T_532 = and(_T_530, _T_531) node _T_533 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_534 = and(_T_532, _T_533) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_535 = shr(io.in.a.bits.source, 5) node _T_536 = eq(_T_535, UInt<3>(0h4)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_44) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_541 = shr(io.in.a.bits.source, 5) node _T_542 = eq(_T_541, UInt<3>(0h5)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_45) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_547 = shr(io.in.a.bits.source, 5) node _T_548 = eq(_T_547, UInt<3>(0h6)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_46) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_553 = shr(io.in.a.bits.source, 5) node _T_554 = eq(_T_553, UInt<3>(0h7)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_47) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_560 = or(_T_483, _T_489) node _T_561 = or(_T_560, _T_495) node _T_562 = or(_T_561, _T_501) node _T_563 = or(_T_562, _T_507) node _T_564 = or(_T_563, _T_508) node _T_565 = or(_T_564, _T_509) node _T_566 = or(_T_565, _T_510) node _T_567 = or(_T_566, _T_516) node _T_568 = or(_T_567, _T_522) node _T_569 = or(_T_568, _T_528) node _T_570 = or(_T_569, _T_534) node _T_571 = or(_T_570, _T_540) node _T_572 = or(_T_571, _T_546) node _T_573 = or(_T_572, _T_552) node _T_574 = or(_T_573, _T_558) node _T_575 = or(_T_574, _T_559) node _T_576 = and(_T_482, _T_575) node _T_577 = or(UInt<1>(0h0), _T_576) node _T_578 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = and(_T_578, _T_583) node _T_585 = or(UInt<1>(0h0), _T_584) node _T_586 = and(_T_577, _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_586, UInt<1>(0h1), "") : assert_10 node _T_590 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<7>(0h40)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_48) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<7>(0h41)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_49) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<7>(0h42)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_50) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_609 = shr(io.in.a.bits.source, 2) node _T_610 = eq(_T_609, UInt<7>(0h43)) node _T_611 = leq(UInt<1>(0h0), uncommonBits_51) node _T_612 = and(_T_610, _T_611) node _T_613 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_616 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_617 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_52) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<1>(0h1)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_53) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<2>(0h2)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_54) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<2>(0h3)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_55) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_642 = shr(io.in.a.bits.source, 5) node _T_643 = eq(_T_642, UInt<3>(0h4)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_56) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_647 = and(_T_645, _T_646) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_648 = shr(io.in.a.bits.source, 5) node _T_649 = eq(_T_648, UInt<3>(0h5)) node _T_650 = leq(UInt<1>(0h0), uncommonBits_57) node _T_651 = and(_T_649, _T_650) node _T_652 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_653 = and(_T_651, _T_652) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_654 = shr(io.in.a.bits.source, 5) node _T_655 = eq(_T_654, UInt<3>(0h6)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_58) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_660 = shr(io.in.a.bits.source, 5) node _T_661 = eq(_T_660, UInt<3>(0h7)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_59) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_665 = and(_T_663, _T_664) node _T_666 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_590 connect _WIRE_2[1], _T_596 connect _WIRE_2[2], _T_602 connect _WIRE_2[3], _T_608 connect _WIRE_2[4], _T_614 connect _WIRE_2[5], _T_615 connect _WIRE_2[6], _T_616 connect _WIRE_2[7], _T_617 connect _WIRE_2[8], _T_623 connect _WIRE_2[9], _T_629 connect _WIRE_2[10], _T_635 connect _WIRE_2[11], _T_641 connect _WIRE_2[12], _T_647 connect _WIRE_2[13], _T_653 connect _WIRE_2[14], _T_659 connect _WIRE_2[15], _T_665 connect _WIRE_2[16], _T_666 node _T_667 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_668 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_673 = mux(_WIRE_2[5], _T_667, UInt<1>(0h0)) node _T_674 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_676 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = or(_T_668, _T_669) node _T_686 = or(_T_685, _T_670) node _T_687 = or(_T_686, _T_671) node _T_688 = or(_T_687, _T_672) node _T_689 = or(_T_688, _T_673) node _T_690 = or(_T_689, _T_674) node _T_691 = or(_T_690, _T_675) node _T_692 = or(_T_691, _T_676) node _T_693 = or(_T_692, _T_677) node _T_694 = or(_T_693, _T_678) node _T_695 = or(_T_694, _T_679) node _T_696 = or(_T_695, _T_680) node _T_697 = or(_T_696, _T_681) node _T_698 = or(_T_697, _T_682) node _T_699 = or(_T_698, _T_683) node _T_700 = or(_T_699, _T_684) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_700 node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<13>(0h1000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = and(_T_704, _T_709) node _T_711 = or(UInt<1>(0h0), _T_710) node _T_712 = and(_WIRE_3, _T_711) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_712, UInt<1>(0h1), "") : assert_11 node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(source_ok, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_719 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_719, UInt<1>(0h1), "") : assert_13 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(is_aligned, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_726 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_726, UInt<1>(0h1), "") : assert_15 node _T_730 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_730, UInt<1>(0h1), "") : assert_16 node _T_734 = not(io.in.a.bits.mask) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_735, UInt<1>(0h1), "") : assert_17 node _T_739 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_739, UInt<1>(0h1), "") : assert_18 node _T_743 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_743 : node _T_744 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_745 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_746 = and(_T_744, _T_745) node _T_747 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_748 = shr(io.in.a.bits.source, 2) node _T_749 = eq(_T_748, UInt<7>(0h40)) node _T_750 = leq(UInt<1>(0h0), uncommonBits_60) node _T_751 = and(_T_749, _T_750) node _T_752 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_754 = shr(io.in.a.bits.source, 2) node _T_755 = eq(_T_754, UInt<7>(0h41)) node _T_756 = leq(UInt<1>(0h0), uncommonBits_61) node _T_757 = and(_T_755, _T_756) node _T_758 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_759 = and(_T_757, _T_758) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<7>(0h42)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_62) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<7>(0h43)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_63) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _T_772 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_774 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_775 = shr(io.in.a.bits.source, 5) node _T_776 = eq(_T_775, UInt<1>(0h0)) node _T_777 = leq(UInt<1>(0h0), uncommonBits_64) node _T_778 = and(_T_776, _T_777) node _T_779 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_780 = and(_T_778, _T_779) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_781 = shr(io.in.a.bits.source, 5) node _T_782 = eq(_T_781, UInt<1>(0h1)) node _T_783 = leq(UInt<1>(0h0), uncommonBits_65) node _T_784 = and(_T_782, _T_783) node _T_785 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_786 = and(_T_784, _T_785) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_787 = shr(io.in.a.bits.source, 5) node _T_788 = eq(_T_787, UInt<2>(0h2)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_66) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_793 = shr(io.in.a.bits.source, 5) node _T_794 = eq(_T_793, UInt<2>(0h3)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_67) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_799 = shr(io.in.a.bits.source, 5) node _T_800 = eq(_T_799, UInt<3>(0h4)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_68) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_805 = shr(io.in.a.bits.source, 5) node _T_806 = eq(_T_805, UInt<3>(0h5)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_69) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_810 = and(_T_808, _T_809) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_811 = shr(io.in.a.bits.source, 5) node _T_812 = eq(_T_811, UInt<3>(0h6)) node _T_813 = leq(UInt<1>(0h0), uncommonBits_70) node _T_814 = and(_T_812, _T_813) node _T_815 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_816 = and(_T_814, _T_815) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_817 = shr(io.in.a.bits.source, 5) node _T_818 = eq(_T_817, UInt<3>(0h7)) node _T_819 = leq(UInt<1>(0h0), uncommonBits_71) node _T_820 = and(_T_818, _T_819) node _T_821 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_822 = and(_T_820, _T_821) node _T_823 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_824 = or(_T_747, _T_753) node _T_825 = or(_T_824, _T_759) node _T_826 = or(_T_825, _T_765) node _T_827 = or(_T_826, _T_771) node _T_828 = or(_T_827, _T_772) node _T_829 = or(_T_828, _T_773) node _T_830 = or(_T_829, _T_774) node _T_831 = or(_T_830, _T_780) node _T_832 = or(_T_831, _T_786) node _T_833 = or(_T_832, _T_792) node _T_834 = or(_T_833, _T_798) node _T_835 = or(_T_834, _T_804) node _T_836 = or(_T_835, _T_810) node _T_837 = or(_T_836, _T_816) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = and(_T_746, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_841, UInt<1>(0h1), "") : assert_19 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = and(_T_848, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_855, UInt<1>(0h1), "") : assert_20 node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(source_ok, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(is_aligned, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_865 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_865, UInt<1>(0h1), "") : assert_23 node _T_869 = eq(io.in.a.bits.mask, mask) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_869, UInt<1>(0h1), "") : assert_24 node _T_873 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_873, UInt<1>(0h1), "") : assert_25 node _T_877 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_877 : node _T_878 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_879 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_880 = and(_T_878, _T_879) node _T_881 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_882 = shr(io.in.a.bits.source, 2) node _T_883 = eq(_T_882, UInt<7>(0h40)) node _T_884 = leq(UInt<1>(0h0), uncommonBits_72) node _T_885 = and(_T_883, _T_884) node _T_886 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_887 = and(_T_885, _T_886) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_888 = shr(io.in.a.bits.source, 2) node _T_889 = eq(_T_888, UInt<7>(0h41)) node _T_890 = leq(UInt<1>(0h0), uncommonBits_73) node _T_891 = and(_T_889, _T_890) node _T_892 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_893 = and(_T_891, _T_892) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_894 = shr(io.in.a.bits.source, 2) node _T_895 = eq(_T_894, UInt<7>(0h42)) node _T_896 = leq(UInt<1>(0h0), uncommonBits_74) node _T_897 = and(_T_895, _T_896) node _T_898 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_900 = shr(io.in.a.bits.source, 2) node _T_901 = eq(_T_900, UInt<7>(0h43)) node _T_902 = leq(UInt<1>(0h0), uncommonBits_75) node _T_903 = and(_T_901, _T_902) node _T_904 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_905 = and(_T_903, _T_904) node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_909 = shr(io.in.a.bits.source, 5) node _T_910 = eq(_T_909, UInt<1>(0h0)) node _T_911 = leq(UInt<1>(0h0), uncommonBits_76) node _T_912 = and(_T_910, _T_911) node _T_913 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_914 = and(_T_912, _T_913) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_915 = shr(io.in.a.bits.source, 5) node _T_916 = eq(_T_915, UInt<1>(0h1)) node _T_917 = leq(UInt<1>(0h0), uncommonBits_77) node _T_918 = and(_T_916, _T_917) node _T_919 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_920 = and(_T_918, _T_919) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_921 = shr(io.in.a.bits.source, 5) node _T_922 = eq(_T_921, UInt<2>(0h2)) node _T_923 = leq(UInt<1>(0h0), uncommonBits_78) node _T_924 = and(_T_922, _T_923) node _T_925 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_926 = and(_T_924, _T_925) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_927 = shr(io.in.a.bits.source, 5) node _T_928 = eq(_T_927, UInt<2>(0h3)) node _T_929 = leq(UInt<1>(0h0), uncommonBits_79) node _T_930 = and(_T_928, _T_929) node _T_931 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_932 = and(_T_930, _T_931) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_933 = shr(io.in.a.bits.source, 5) node _T_934 = eq(_T_933, UInt<3>(0h4)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_80) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_938 = and(_T_936, _T_937) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_939 = shr(io.in.a.bits.source, 5) node _T_940 = eq(_T_939, UInt<3>(0h5)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_81) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_945 = shr(io.in.a.bits.source, 5) node _T_946 = eq(_T_945, UInt<3>(0h6)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_82) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_951 = shr(io.in.a.bits.source, 5) node _T_952 = eq(_T_951, UInt<3>(0h7)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_83) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_956 = and(_T_954, _T_955) node _T_957 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_958 = or(_T_881, _T_887) node _T_959 = or(_T_958, _T_893) node _T_960 = or(_T_959, _T_899) node _T_961 = or(_T_960, _T_905) node _T_962 = or(_T_961, _T_906) node _T_963 = or(_T_962, _T_907) node _T_964 = or(_T_963, _T_908) node _T_965 = or(_T_964, _T_914) node _T_966 = or(_T_965, _T_920) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_932) node _T_969 = or(_T_968, _T_938) node _T_970 = or(_T_969, _T_944) node _T_971 = or(_T_970, _T_950) node _T_972 = or(_T_971, _T_956) node _T_973 = or(_T_972, _T_957) node _T_974 = and(_T_880, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), _T_985) node _T_987 = and(_T_975, _T_986) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_987, UInt<1>(0h1), "") : assert_26 node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(source_ok, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(is_aligned, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_997 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_997, UInt<1>(0h1), "") : assert_29 node _T_1001 = eq(io.in.a.bits.mask, mask) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_30 node _T_1005 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1005 : node _T_1006 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1007 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1010 = shr(io.in.a.bits.source, 2) node _T_1011 = eq(_T_1010, UInt<7>(0h40)) node _T_1012 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1013 = and(_T_1011, _T_1012) node _T_1014 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1015 = and(_T_1013, _T_1014) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1016 = shr(io.in.a.bits.source, 2) node _T_1017 = eq(_T_1016, UInt<7>(0h41)) node _T_1018 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1021 = and(_T_1019, _T_1020) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1022 = shr(io.in.a.bits.source, 2) node _T_1023 = eq(_T_1022, UInt<7>(0h42)) node _T_1024 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1025 = and(_T_1023, _T_1024) node _T_1026 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1027 = and(_T_1025, _T_1026) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<7>(0h43)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _T_1034 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1035 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1036 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1037 = shr(io.in.a.bits.source, 5) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) node _T_1039 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1042 = and(_T_1040, _T_1041) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1043 = shr(io.in.a.bits.source, 5) node _T_1044 = eq(_T_1043, UInt<1>(0h1)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1049 = shr(io.in.a.bits.source, 5) node _T_1050 = eq(_T_1049, UInt<2>(0h2)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1055 = shr(io.in.a.bits.source, 5) node _T_1056 = eq(_T_1055, UInt<2>(0h3)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1061 = shr(io.in.a.bits.source, 5) node _T_1062 = eq(_T_1061, UInt<3>(0h4)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1066 = and(_T_1064, _T_1065) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1067 = shr(io.in.a.bits.source, 5) node _T_1068 = eq(_T_1067, UInt<3>(0h5)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1072 = and(_T_1070, _T_1071) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1073 = shr(io.in.a.bits.source, 5) node _T_1074 = eq(_T_1073, UInt<3>(0h6)) node _T_1075 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1076 = and(_T_1074, _T_1075) node _T_1077 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1079 = shr(io.in.a.bits.source, 5) node _T_1080 = eq(_T_1079, UInt<3>(0h7)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1086 = or(_T_1009, _T_1015) node _T_1087 = or(_T_1086, _T_1021) node _T_1088 = or(_T_1087, _T_1027) node _T_1089 = or(_T_1088, _T_1033) node _T_1090 = or(_T_1089, _T_1034) node _T_1091 = or(_T_1090, _T_1035) node _T_1092 = or(_T_1091, _T_1036) node _T_1093 = or(_T_1092, _T_1042) node _T_1094 = or(_T_1093, _T_1048) node _T_1095 = or(_T_1094, _T_1054) node _T_1096 = or(_T_1095, _T_1060) node _T_1097 = or(_T_1096, _T_1066) node _T_1098 = or(_T_1097, _T_1072) node _T_1099 = or(_T_1098, _T_1078) node _T_1100 = or(_T_1099, _T_1084) node _T_1101 = or(_T_1100, _T_1085) node _T_1102 = and(_T_1008, _T_1101) node _T_1103 = or(UInt<1>(0h0), _T_1102) node _T_1104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1109 = cvt(_T_1108) node _T_1110 = and(_T_1109, asSInt(UInt<13>(0h1000))) node _T_1111 = asSInt(_T_1110) node _T_1112 = eq(_T_1111, asSInt(UInt<1>(0h0))) node _T_1113 = and(_T_1107, _T_1112) node _T_1114 = or(UInt<1>(0h0), _T_1113) node _T_1115 = and(_T_1103, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_31 node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(source_ok, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(is_aligned, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1125 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_34 node _T_1129 = not(mask) node _T_1130 = and(io.in.a.bits.mask, _T_1129) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_35 node _T_1135 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1135 : node _T_1136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1138 = and(_T_1136, _T_1137) node _T_1139 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1140 = shr(io.in.a.bits.source, 2) node _T_1141 = eq(_T_1140, UInt<7>(0h40)) node _T_1142 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1145 = and(_T_1143, _T_1144) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1146 = shr(io.in.a.bits.source, 2) node _T_1147 = eq(_T_1146, UInt<7>(0h41)) node _T_1148 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1151 = and(_T_1149, _T_1150) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1152 = shr(io.in.a.bits.source, 2) node _T_1153 = eq(_T_1152, UInt<7>(0h42)) node _T_1154 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1157 = and(_T_1155, _T_1156) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1158 = shr(io.in.a.bits.source, 2) node _T_1159 = eq(_T_1158, UInt<7>(0h43)) node _T_1160 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1165 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1166 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1167 = shr(io.in.a.bits.source, 5) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) node _T_1169 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1170 = and(_T_1168, _T_1169) node _T_1171 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1172 = and(_T_1170, _T_1171) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1173 = shr(io.in.a.bits.source, 5) node _T_1174 = eq(_T_1173, UInt<1>(0h1)) node _T_1175 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1176 = and(_T_1174, _T_1175) node _T_1177 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1178 = and(_T_1176, _T_1177) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1179 = shr(io.in.a.bits.source, 5) node _T_1180 = eq(_T_1179, UInt<2>(0h2)) node _T_1181 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1184 = and(_T_1182, _T_1183) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1185 = shr(io.in.a.bits.source, 5) node _T_1186 = eq(_T_1185, UInt<2>(0h3)) node _T_1187 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1190 = and(_T_1188, _T_1189) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1191 = shr(io.in.a.bits.source, 5) node _T_1192 = eq(_T_1191, UInt<3>(0h4)) node _T_1193 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1196 = and(_T_1194, _T_1195) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1197 = shr(io.in.a.bits.source, 5) node _T_1198 = eq(_T_1197, UInt<3>(0h5)) node _T_1199 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1200 = and(_T_1198, _T_1199) node _T_1201 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1202 = and(_T_1200, _T_1201) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1203 = shr(io.in.a.bits.source, 5) node _T_1204 = eq(_T_1203, UInt<3>(0h6)) node _T_1205 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1206 = and(_T_1204, _T_1205) node _T_1207 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1208 = and(_T_1206, _T_1207) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1209 = shr(io.in.a.bits.source, 5) node _T_1210 = eq(_T_1209, UInt<3>(0h7)) node _T_1211 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1216 = or(_T_1139, _T_1145) node _T_1217 = or(_T_1216, _T_1151) node _T_1218 = or(_T_1217, _T_1157) node _T_1219 = or(_T_1218, _T_1163) node _T_1220 = or(_T_1219, _T_1164) node _T_1221 = or(_T_1220, _T_1165) node _T_1222 = or(_T_1221, _T_1166) node _T_1223 = or(_T_1222, _T_1172) node _T_1224 = or(_T_1223, _T_1178) node _T_1225 = or(_T_1224, _T_1184) node _T_1226 = or(_T_1225, _T_1190) node _T_1227 = or(_T_1226, _T_1196) node _T_1228 = or(_T_1227, _T_1202) node _T_1229 = or(_T_1228, _T_1208) node _T_1230 = or(_T_1229, _T_1214) node _T_1231 = or(_T_1230, _T_1215) node _T_1232 = and(_T_1138, _T_1231) node _T_1233 = or(UInt<1>(0h0), _T_1232) node _T_1234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1235 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = or(UInt<1>(0h0), _T_1236) node _T_1238 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = and(_T_1237, _T_1242) node _T_1244 = or(UInt<1>(0h0), _T_1243) node _T_1245 = and(_T_1233, _T_1244) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_36 node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(source_ok, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(is_aligned, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1255 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_39 node _T_1259 = eq(io.in.a.bits.mask, mask) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_40 node _T_1263 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1263 : node _T_1264 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1265 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1268 = shr(io.in.a.bits.source, 2) node _T_1269 = eq(_T_1268, UInt<7>(0h40)) node _T_1270 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1273 = and(_T_1271, _T_1272) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1274 = shr(io.in.a.bits.source, 2) node _T_1275 = eq(_T_1274, UInt<7>(0h41)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1279 = and(_T_1277, _T_1278) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1280 = shr(io.in.a.bits.source, 2) node _T_1281 = eq(_T_1280, UInt<7>(0h42)) node _T_1282 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1283 = and(_T_1281, _T_1282) node _T_1284 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1285 = and(_T_1283, _T_1284) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1286 = shr(io.in.a.bits.source, 2) node _T_1287 = eq(_T_1286, UInt<7>(0h43)) node _T_1288 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1289 = and(_T_1287, _T_1288) node _T_1290 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1291 = and(_T_1289, _T_1290) node _T_1292 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1293 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1294 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1295 = shr(io.in.a.bits.source, 5) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) node _T_1297 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1300 = and(_T_1298, _T_1299) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1301 = shr(io.in.a.bits.source, 5) node _T_1302 = eq(_T_1301, UInt<1>(0h1)) node _T_1303 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1304 = and(_T_1302, _T_1303) node _T_1305 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1306 = and(_T_1304, _T_1305) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1307 = shr(io.in.a.bits.source, 5) node _T_1308 = eq(_T_1307, UInt<2>(0h2)) node _T_1309 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1310 = and(_T_1308, _T_1309) node _T_1311 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1312 = and(_T_1310, _T_1311) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1313 = shr(io.in.a.bits.source, 5) node _T_1314 = eq(_T_1313, UInt<2>(0h3)) node _T_1315 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1318 = and(_T_1316, _T_1317) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1319 = shr(io.in.a.bits.source, 5) node _T_1320 = eq(_T_1319, UInt<3>(0h4)) node _T_1321 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1324 = and(_T_1322, _T_1323) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1325 = shr(io.in.a.bits.source, 5) node _T_1326 = eq(_T_1325, UInt<3>(0h5)) node _T_1327 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1330 = and(_T_1328, _T_1329) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1331 = shr(io.in.a.bits.source, 5) node _T_1332 = eq(_T_1331, UInt<3>(0h6)) node _T_1333 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1336 = and(_T_1334, _T_1335) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<3>(0h7)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1344 = or(_T_1267, _T_1273) node _T_1345 = or(_T_1344, _T_1279) node _T_1346 = or(_T_1345, _T_1285) node _T_1347 = or(_T_1346, _T_1291) node _T_1348 = or(_T_1347, _T_1292) node _T_1349 = or(_T_1348, _T_1293) node _T_1350 = or(_T_1349, _T_1294) node _T_1351 = or(_T_1350, _T_1300) node _T_1352 = or(_T_1351, _T_1306) node _T_1353 = or(_T_1352, _T_1312) node _T_1354 = or(_T_1353, _T_1318) node _T_1355 = or(_T_1354, _T_1324) node _T_1356 = or(_T_1355, _T_1330) node _T_1357 = or(_T_1356, _T_1336) node _T_1358 = or(_T_1357, _T_1342) node _T_1359 = or(_T_1358, _T_1343) node _T_1360 = and(_T_1266, _T_1359) node _T_1361 = or(UInt<1>(0h0), _T_1360) node _T_1362 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1363 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = or(UInt<1>(0h0), _T_1364) node _T_1366 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = and(_T_1365, _T_1370) node _T_1372 = or(UInt<1>(0h0), _T_1371) node _T_1373 = and(_T_1361, _T_1372) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_41 node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(source_ok, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(is_aligned, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1383 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_44 node _T_1387 = eq(io.in.a.bits.mask, mask) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_45 node _T_1391 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1391 : node _T_1392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1394 = and(_T_1392, _T_1393) node _T_1395 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1396 = shr(io.in.a.bits.source, 2) node _T_1397 = eq(_T_1396, UInt<7>(0h40)) node _T_1398 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1399 = and(_T_1397, _T_1398) node _T_1400 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1401 = and(_T_1399, _T_1400) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1402 = shr(io.in.a.bits.source, 2) node _T_1403 = eq(_T_1402, UInt<7>(0h41)) node _T_1404 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1405 = and(_T_1403, _T_1404) node _T_1406 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1407 = and(_T_1405, _T_1406) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1408 = shr(io.in.a.bits.source, 2) node _T_1409 = eq(_T_1408, UInt<7>(0h42)) node _T_1410 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1413 = and(_T_1411, _T_1412) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1414 = shr(io.in.a.bits.source, 2) node _T_1415 = eq(_T_1414, UInt<7>(0h43)) node _T_1416 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1421 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1422 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1423 = shr(io.in.a.bits.source, 5) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) node _T_1425 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1426 = and(_T_1424, _T_1425) node _T_1427 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1428 = and(_T_1426, _T_1427) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1429 = shr(io.in.a.bits.source, 5) node _T_1430 = eq(_T_1429, UInt<1>(0h1)) node _T_1431 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1432 = and(_T_1430, _T_1431) node _T_1433 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1434 = and(_T_1432, _T_1433) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1435 = shr(io.in.a.bits.source, 5) node _T_1436 = eq(_T_1435, UInt<2>(0h2)) node _T_1437 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1438 = and(_T_1436, _T_1437) node _T_1439 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1440 = and(_T_1438, _T_1439) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1441 = shr(io.in.a.bits.source, 5) node _T_1442 = eq(_T_1441, UInt<2>(0h3)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1446 = and(_T_1444, _T_1445) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1447 = shr(io.in.a.bits.source, 5) node _T_1448 = eq(_T_1447, UInt<3>(0h4)) node _T_1449 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1450 = and(_T_1448, _T_1449) node _T_1451 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1452 = and(_T_1450, _T_1451) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1453 = shr(io.in.a.bits.source, 5) node _T_1454 = eq(_T_1453, UInt<3>(0h5)) node _T_1455 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1458 = and(_T_1456, _T_1457) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1459 = shr(io.in.a.bits.source, 5) node _T_1460 = eq(_T_1459, UInt<3>(0h6)) node _T_1461 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1462 = and(_T_1460, _T_1461) node _T_1463 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1464 = and(_T_1462, _T_1463) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1465 = shr(io.in.a.bits.source, 5) node _T_1466 = eq(_T_1465, UInt<3>(0h7)) node _T_1467 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1472 = or(_T_1395, _T_1401) node _T_1473 = or(_T_1472, _T_1407) node _T_1474 = or(_T_1473, _T_1413) node _T_1475 = or(_T_1474, _T_1419) node _T_1476 = or(_T_1475, _T_1420) node _T_1477 = or(_T_1476, _T_1421) node _T_1478 = or(_T_1477, _T_1422) node _T_1479 = or(_T_1478, _T_1428) node _T_1480 = or(_T_1479, _T_1434) node _T_1481 = or(_T_1480, _T_1440) node _T_1482 = or(_T_1481, _T_1446) node _T_1483 = or(_T_1482, _T_1452) node _T_1484 = or(_T_1483, _T_1458) node _T_1485 = or(_T_1484, _T_1464) node _T_1486 = or(_T_1485, _T_1470) node _T_1487 = or(_T_1486, _T_1471) node _T_1488 = and(_T_1394, _T_1487) node _T_1489 = or(UInt<1>(0h0), _T_1488) node _T_1490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1492 = and(_T_1490, _T_1491) node _T_1493 = or(UInt<1>(0h0), _T_1492) node _T_1494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = and(_T_1493, _T_1498) node _T_1500 = or(UInt<1>(0h0), _T_1499) node _T_1501 = and(_T_1489, _T_1500) node _T_1502 = asUInt(reset) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) when _T_1503 : node _T_1504 = eq(_T_1501, UInt<1>(0h0)) when _T_1504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1501, UInt<1>(0h1), "") : assert_46 node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(is_aligned, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1511 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(_T_1511, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1511, UInt<1>(0h1), "") : assert_49 node _T_1515 = eq(io.in.a.bits.mask, mask) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_50 node _T_1519 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1523 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1527 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1527 : node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(source_ok_1, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_54 node _T_1535 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_55 node _T_1539 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_56 node _T_1543 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_57 node _T_1547 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1547 : node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(source_ok_1, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(sink_ok, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1554 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_60 node _T_1558 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_61 node _T_1562 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_62 node _T_1566 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_63 node _T_1570 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1571 = or(UInt<1>(0h1), _T_1570) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_64 node _T_1575 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1575 : node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(source_ok_1, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(sink_ok, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1582 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_67 node _T_1586 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(_T_1586, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1586, UInt<1>(0h1), "") : assert_68 node _T_1590 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_69 node _T_1594 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1595 = or(_T_1594, io.in.d.bits.corrupt) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_70 node _T_1599 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1600 = or(UInt<1>(0h1), _T_1599) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_71 node _T_1604 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1604 : node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(source_ok_1, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1608 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_73 node _T_1612 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_74 node _T_1616 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1617 = or(UInt<1>(0h1), _T_1616) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_75 node _T_1621 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1621 : node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(source_ok_1, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1625 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_77 node _T_1629 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1630 = or(_T_1629, io.in.d.bits.corrupt) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_78 node _T_1634 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1635 = or(UInt<1>(0h1), _T_1634) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_79 node _T_1639 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1639 : node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(source_ok_1, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1643 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_81 node _T_1647 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_82 node _T_1651 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1652 = or(UInt<1>(0h1), _T_1651) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1656 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1660 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1664 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1668 = eq(a_first, UInt<1>(0h0)) node _T_1669 = and(io.in.a.valid, _T_1668) when _T_1669 : node _T_1670 = eq(io.in.a.bits.opcode, opcode) node _T_1671 = asUInt(reset) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) when _T_1672 : node _T_1673 = eq(_T_1670, UInt<1>(0h0)) when _T_1673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1670, UInt<1>(0h1), "") : assert_87 node _T_1674 = eq(io.in.a.bits.param, param) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_88 node _T_1678 = eq(io.in.a.bits.size, size) node _T_1679 = asUInt(reset) node _T_1680 = eq(_T_1679, UInt<1>(0h0)) when _T_1680 : node _T_1681 = eq(_T_1678, UInt<1>(0h0)) when _T_1681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1678, UInt<1>(0h1), "") : assert_89 node _T_1682 = eq(io.in.a.bits.source, source) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_90 node _T_1686 = eq(io.in.a.bits.address, address) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_91 node _T_1690 = and(io.in.a.ready, io.in.a.valid) node _T_1691 = and(_T_1690, a_first) when _T_1691 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1692 = eq(d_first, UInt<1>(0h0)) node _T_1693 = and(io.in.d.valid, _T_1692) when _T_1693 : node _T_1694 = eq(io.in.d.bits.opcode, opcode_1) node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(_T_1694, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1694, UInt<1>(0h1), "") : assert_92 node _T_1698 = eq(io.in.d.bits.param, param_1) node _T_1699 = asUInt(reset) node _T_1700 = eq(_T_1699, UInt<1>(0h0)) when _T_1700 : node _T_1701 = eq(_T_1698, UInt<1>(0h0)) when _T_1701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1698, UInt<1>(0h1), "") : assert_93 node _T_1702 = eq(io.in.d.bits.size, size_1) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_94 node _T_1706 = eq(io.in.d.bits.source, source_1) node _T_1707 = asUInt(reset) node _T_1708 = eq(_T_1707, UInt<1>(0h0)) when _T_1708 : node _T_1709 = eq(_T_1706, UInt<1>(0h0)) when _T_1709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1706, UInt<1>(0h1), "") : assert_95 node _T_1710 = eq(io.in.d.bits.sink, sink) node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(_T_1710, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1710, UInt<1>(0h1), "") : assert_96 node _T_1714 = eq(io.in.d.bits.denied, denied) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_97 node _T_1718 = and(io.in.d.ready, io.in.d.valid) node _T_1719 = and(_T_1718, d_first) when _T_1719 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1720 = and(io.in.a.valid, a_first_1) node _T_1721 = and(_T_1720, UInt<1>(0h1)) when _T_1721 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1722 = and(io.in.a.ready, io.in.a.valid) node _T_1723 = and(_T_1722, a_first_1) node _T_1724 = and(_T_1723, UInt<1>(0h1)) when _T_1724 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1725 = dshr(inflight, io.in.a.bits.source) node _T_1726 = bits(_T_1725, 0, 0) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(_T_1727, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1727, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1731 = and(io.in.d.valid, d_first_1) node _T_1732 = and(_T_1731, UInt<1>(0h1)) node _T_1733 = eq(d_release_ack, UInt<1>(0h0)) node _T_1734 = and(_T_1732, _T_1733) when _T_1734 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1735 = and(io.in.d.ready, io.in.d.valid) node _T_1736 = and(_T_1735, d_first_1) node _T_1737 = and(_T_1736, UInt<1>(0h1)) node _T_1738 = eq(d_release_ack, UInt<1>(0h0)) node _T_1739 = and(_T_1737, _T_1738) when _T_1739 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1744 = dshr(inflight, io.in.d.bits.source) node _T_1745 = bits(_T_1744, 0, 0) node _T_1746 = or(_T_1745, same_cycle_resp) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1750 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1751 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1752 = or(_T_1750, _T_1751) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_100 node _T_1756 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_101 else : node _T_1760 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1761 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1762 = or(_T_1760, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_102 node _T_1766 = eq(io.in.d.bits.size, a_size_lookup) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_103 node _T_1770 = and(io.in.d.valid, d_first_1) node _T_1771 = and(_T_1770, a_first_1) node _T_1772 = and(_T_1771, io.in.a.valid) node _T_1773 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1774 = and(_T_1772, _T_1773) node _T_1775 = eq(d_release_ack, UInt<1>(0h0)) node _T_1776 = and(_T_1774, _T_1775) when _T_1776 : node _T_1777 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1778 = or(_T_1777, io.in.a.ready) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_104 node _T_1782 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1783 = orr(a_set_wo_ready) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = or(_T_1782, _T_1784) node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(_T_1785, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1785, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_56 node _T_1789 = orr(inflight) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) node _T_1791 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1792 = or(_T_1790, _T_1791) node _T_1793 = lt(watchdog, plusarg_reader.out) node _T_1794 = or(_T_1792, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1798 = and(io.in.a.ready, io.in.a.valid) node _T_1799 = and(io.in.d.ready, io.in.d.valid) node _T_1800 = or(_T_1798, _T_1799) when _T_1800 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1801 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1802 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1803 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1804 = and(_T_1802, _T_1803) node _T_1805 = and(_T_1801, _T_1804) when _T_1805 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1806 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1807 = and(_T_1806, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1808 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1809 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1810 = and(_T_1808, _T_1809) node _T_1811 = and(_T_1807, _T_1810) when _T_1811 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1812 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1813 = bits(_T_1812, 0, 0) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) node _T_1815 = asUInt(reset) node _T_1816 = eq(_T_1815, UInt<1>(0h0)) when _T_1816 : node _T_1817 = eq(_T_1814, UInt<1>(0h0)) when _T_1817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1814, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1818 = and(io.in.d.valid, d_first_2) node _T_1819 = and(_T_1818, UInt<1>(0h1)) node _T_1820 = and(_T_1819, d_release_ack_1) when _T_1820 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1821 = and(io.in.d.ready, io.in.d.valid) node _T_1822 = and(_T_1821, d_first_2) node _T_1823 = and(_T_1822, UInt<1>(0h1)) node _T_1824 = and(_T_1823, d_release_ack_1) when _T_1824 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1825 = and(io.in.d.valid, d_first_2) node _T_1826 = and(_T_1825, UInt<1>(0h1)) node _T_1827 = and(_T_1826, d_release_ack_1) when _T_1827 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1828 = dshr(inflight_1, io.in.d.bits.source) node _T_1829 = bits(_T_1828, 0, 0) node _T_1830 = or(_T_1829, same_cycle_resp_1) node _T_1831 = asUInt(reset) node _T_1832 = eq(_T_1831, UInt<1>(0h0)) when _T_1832 : node _T_1833 = eq(_T_1830, UInt<1>(0h0)) when _T_1833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1830, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1834 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_109 else : node _T_1838 = eq(io.in.d.bits.size, c_size_lookup) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_110 node _T_1842 = and(io.in.d.valid, d_first_2) node _T_1843 = and(_T_1842, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1844 = and(_T_1843, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1845 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1846 = and(_T_1844, _T_1845) node _T_1847 = and(_T_1846, d_release_ack_1) node _T_1848 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1849 = and(_T_1847, _T_1848) when _T_1849 : node _T_1850 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1851 = or(_T_1850, _WIRE_27.ready) node _T_1852 = asUInt(reset) node _T_1853 = eq(_T_1852, UInt<1>(0h0)) when _T_1853 : node _T_1854 = eq(_T_1851, UInt<1>(0h0)) when _T_1854 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1851, UInt<1>(0h1), "") : assert_111 node _T_1855 = orr(c_set_wo_ready) when _T_1855 : node _T_1856 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_57 node _T_1860 = orr(inflight_1) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) node _T_1862 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1863 = or(_T_1861, _T_1862) node _T_1864 = lt(watchdog_1, plusarg_reader_1.out) node _T_1865 = or(_T_1863, _T_1864) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1869 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1870 = and(io.in.d.ready, io.in.d.valid) node _T_1871 = or(_T_1869, _T_1870) when _T_1871 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_28( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module ZstdRawLiteralEncoder : input clock : Clock input reset : Reset output io : { l2io_read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, flip dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, l2io_write : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, bytes_written : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}} inst memloader of MemLoader_1 connect memloader.clock, clock connect memloader.reset, reset connect memloader.io.l2helperUser.no_memops_inflight, io.l2io_read.no_memops_inflight connect memloader.io.l2helperUser.resp, io.l2io_read.resp connect io.l2io_read.req.bits, memloader.io.l2helperUser.req.bits connect io.l2io_read.req.valid, memloader.io.l2helperUser.req.valid connect memloader.io.l2helperUser.req.ready, io.l2io_read.req.ready inst src_size_q of Queue4_UInt64_10 connect src_size_q.clock, clock connect src_size_q.reset, reset inst send_done_q of Queue4_Bool_1 connect send_done_q.clock, clock connect send_done_q.reset, reset connect memloader.io.src_info.bits.isize, io.src_info.bits.isize connect memloader.io.src_info.bits.ip, io.src_info.bits.ip node _memloader_io_src_info_valid_T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _memloader_io_src_info_valid_T_1 = and(_memloader_io_src_info_valid_T, io.src_info.valid) connect memloader.io.src_info.valid, _memloader_io_src_info_valid_T_1 connect src_size_q.io.enq.bits, io.src_info.bits.isize node _src_size_q_io_enq_valid_T = and(send_done_q.io.enq.ready, memloader.io.src_info.ready) node _src_size_q_io_enq_valid_T_1 = and(_src_size_q_io_enq_valid_T, io.src_info.valid) connect src_size_q.io.enq.valid, _src_size_q_io_enq_valid_T_1 connect send_done_q.io.enq.bits, UInt<1>(0h1) node _send_done_q_io_enq_valid_T = and(src_size_q.io.enq.ready, memloader.io.src_info.ready) node _send_done_q_io_enq_valid_T_1 = and(_send_done_q_io_enq_valid_T, io.src_info.valid) connect send_done_q.io.enq.valid, _send_done_q_io_enq_valid_T_1 node _io_src_info_ready_T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _io_src_info_ready_T_1 = and(_io_src_info_ready_T, memloader.io.src_info.ready) connect io.src_info.ready, _io_src_info_ready_T_1 regreset input_copy_req_count : UInt<64>, clock, reset, UInt<64>(0h0) node _T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _T_1 = and(_T, memloader.io.src_info.ready) node _T_2 = and(_T_1, io.src_info.valid) when _T_2 : node _nxt_input_copy_req_cnt_T = add(input_copy_req_count, UInt<1>(0h1)) node nxt_input_copy_req_cnt = tail(_nxt_input_copy_req_cnt_T, 1) connect input_copy_req_count, nxt_input_copy_req_cnt regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "MEMCPY_SRC_FIRE, input_copy_req_count: %d, src_addr: 0x%x, src_size: %d\n", nxt_input_copy_req_cnt, io.src_info.bits.ip, io.src_info.bits.isize) : printf_1 node _flSize_T = gt(src_size_q.io.deq.bits, UInt<5>(0h1f)) node _flSize_T_1 = mux(_flSize_T, UInt<1>(0h1), UInt<1>(0h0)) node _flSize_T_2 = add(UInt<1>(0h1), _flSize_T_1) node _flSize_T_3 = tail(_flSize_T_2, 1) node _flSize_T_4 = gt(src_size_q.io.deq.bits, UInt<12>(0hfff)) node _flSize_T_5 = mux(_flSize_T_4, UInt<1>(0h1), UInt<1>(0h0)) node _flSize_T_6 = add(_flSize_T_3, _flSize_T_5) node flSize = tail(_flSize_T_6, 1) wire header : UInt<24> node _header_T = eq(flSize, UInt<1>(0h1)) node _header_T_1 = dshl(src_size_q.io.deq.bits, UInt<2>(0h3)) node _header_T_2 = add(UInt<1>(0h0), _header_T_1) node _header_T_3 = tail(_header_T_2, 1) node _header_T_4 = eq(flSize, UInt<2>(0h2)) node _header_T_5 = add(UInt<1>(0h0), UInt<3>(0h4)) node _header_T_6 = tail(_header_T_5, 1) node _header_T_7 = dshl(src_size_q.io.deq.bits, UInt<3>(0h4)) node _header_T_8 = add(_header_T_6, _header_T_7) node _header_T_9 = tail(_header_T_8, 1) node _header_T_10 = add(UInt<1>(0h0), UInt<4>(0hc)) node _header_T_11 = tail(_header_T_10, 1) node _header_T_12 = dshl(src_size_q.io.deq.bits, UInt<3>(0h4)) node _header_T_13 = add(_header_T_11, _header_T_12) node _header_T_14 = tail(_header_T_13, 1) node _header_T_15 = mux(_header_T_4, _header_T_9, _header_T_14) node _header_T_16 = mux(_header_T, _header_T_3, _header_T_15) connect header, _header_T_16 inst memwriter of ZstdCompressorMemWriter_2 connect memwriter.clock, clock connect memwriter.reset, reset connect memwriter.io.l2io.no_memops_inflight, io.l2io_write.no_memops_inflight connect memwriter.io.l2io.resp, io.l2io_write.resp connect io.l2io_write.req.bits, memwriter.io.l2io.req.bits connect io.l2io_write.req.valid, memwriter.io.l2io.req.valid connect memwriter.io.l2io.req.ready, io.l2io_write.req.ready connect memwriter.io.dest_info, io.dst_info regreset header_written : UInt<1>, clock, reset, UInt<1>(0h0) node _T_7 = eq(header_written, UInt<1>(0h0)) node _T_8 = and(src_size_q.io.deq.valid, _T_7) node _T_9 = and(_T_8, memwriter.io.memwrites_in.ready) when _T_9 : connect header_written, UInt<1>(0h1) node _src_size_q_io_deq_ready_T = and(_T_7, memwriter.io.memwrites_in.ready) connect src_size_q.io.deq.ready, _src_size_q_io_deq_ready_T node _header_fire_T = and(src_size_q.io.deq.valid, _T_7) node header_fire = and(_header_fire_T, memwriter.io.memwrites_in.ready) node _memwriter_io_memwrites_in_valid_T = and(src_size_q.io.deq.valid, _T_7) node _memwriter_io_memwrites_in_valid_T_1 = and(memloader.io.consumer.output_valid, header_written) node _memwriter_io_memwrites_in_valid_T_2 = or(_memwriter_io_memwrites_in_valid_T, _memwriter_io_memwrites_in_valid_T_1) connect memwriter.io.memwrites_in.valid, _memwriter_io_memwrites_in_valid_T_2 node _memwriter_io_memwrites_in_bits_data_T = mux(header_fire, header, memloader.io.consumer.output_data) connect memwriter.io.memwrites_in.bits.data, _memwriter_io_memwrites_in_bits_data_T node _memwriter_io_memwrites_in_bits_validbytes_T = mux(header_fire, flSize, memloader.io.consumer.available_output_bytes) connect memwriter.io.memwrites_in.bits.validbytes, _memwriter_io_memwrites_in_bits_validbytes_T node _memwriter_io_memwrites_in_bits_end_of_message_T = mux(header_fire, UInt<1>(0h0), memloader.io.consumer.output_last_chunk) connect memwriter.io.memwrites_in.bits.end_of_message, _memwriter_io_memwrites_in_bits_end_of_message_T node _memloader_io_consumer_output_ready_T = and(memwriter.io.memwrites_in.ready, header_written) connect memloader.io.consumer.output_ready, _memloader_io_consumer_output_ready_T connect memloader.io.consumer.user_consumed_bytes, memloader.io.consumer.available_output_bytes regreset bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _T_10 = and(memwriter.io.memwrites_in.ready, memwriter.io.memwrites_in.valid) when _T_10 : node _bytes_written_T = add(bytes_written, memwriter.io.memwrites_in.bits.validbytes) node _bytes_written_T_1 = tail(_bytes_written_T, 1) connect bytes_written, _bytes_written_T_1 node _T_11 = eq(memwriter.io.bufs_completed, input_copy_req_count) node _io_bytes_written_valid_T = and(_T_11, memwriter.io.no_writes_inflight) node _io_bytes_written_valid_T_1 = and(_io_bytes_written_valid_T, send_done_q.io.deq.valid) connect io.bytes_written.valid, _io_bytes_written_valid_T_1 connect io.bytes_written.bits, bytes_written node _send_done_q_io_deq_ready_T = and(_T_11, memwriter.io.no_writes_inflight) node _send_done_q_io_deq_ready_T_1 = and(_send_done_q_io_deq_ready_T, io.bytes_written.ready) connect send_done_q.io.deq.ready, _send_done_q_io_deq_ready_T_1 node _T_12 = and(_T_11, memwriter.io.no_writes_inflight) node _T_13 = and(_T_12, io.bytes_written.ready) node _T_14 = and(_T_13, send_done_q.io.deq.valid) when _T_14 : connect header_written, UInt<1>(0h0) connect bytes_written, UInt<1>(0h0) regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "MEMCPY_DONE_FIRE, bytes_written: %d\n", bytes_written) : printf_3	module ZstdRawLiteralEncoder( // @[ZstdRawLiteralEncoder.scala:23:7] input clock, // @[ZstdRawLiteralEncoder.scala:23:7] input reset, // @[ZstdRawLiteralEncoder.scala:23:7] input io_l2io_read_req_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_read_req_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [70:0] io_l2io_read_req_bits_addr, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_read_resp_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_read_resp_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [255:0] io_l2io_read_resp_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_read_no_memops_inflight, // @[ZstdRawLiteralEncoder.scala:24:14] output io_src_info_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_src_info_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_src_info_bits_ip, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_src_info_bits_isize, // @[ZstdRawLiteralEncoder.scala:24:14] output io_dst_info_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_dst_info_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_op, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_cmpflag, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_cmpval, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_req_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_write_req_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [63:0] io_l2io_write_req_bits_addr, // @[ZstdRawLiteralEncoder.scala:24:14] output [2:0] io_l2io_write_req_bits_size, // @[ZstdRawLiteralEncoder.scala:24:14] output [255:0] io_l2io_write_req_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_resp_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [255:0] io_l2io_write_resp_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_no_memops_inflight, // @[ZstdRawLiteralEncoder.scala:24:14] input io_bytes_written_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_bytes_written_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [63:0] io_bytes_written_bits // @[ZstdRawLiteralEncoder.scala:24:14] ); wire _memwriter_io_memwrites_in_ready; // @[ZstdRawLiteralEncoder.scala:68:25] wire [63:0] _memwriter_io_bufs_completed; // @[ZstdRawLiteralEncoder.scala:68:25] wire _memwriter_io_no_writes_inflight; // @[ZstdRawLiteralEncoder.scala:68:25] wire _send_done_q_io_enq_ready; // @[ZstdRawLiteralEncoder.scala:30:27] wire _send_done_q_io_deq_valid; // @[ZstdRawLiteralEncoder.scala:30:27] wire _src_size_q_io_enq_ready; // @[ZstdRawLiteralEncoder.scala:29:26] wire _src_size_q_io_deq_valid; // @[ZstdRawLiteralEncoder.scala:29:26] wire [63:0] _src_size_q_io_deq_bits; // @[ZstdRawLiteralEncoder.scala:29:26] wire _memloader_io_src_info_ready; // @[ZstdRawLiteralEncoder.scala:26:25] wire [5:0] _memloader_io_consumer_available_output_bytes; // @[ZstdRawLiteralEncoder.scala:26:25] wire _memloader_io_consumer_output_valid; // @[ZstdRawLiteralEncoder.scala:26:25] wire [255:0] _memloader_io_consumer_output_data; // @[ZstdRawLiteralEncoder.scala:26:25] wire _memloader_io_consumer_output_last_chunk; // @[ZstdRawLiteralEncoder.scala:26:25] wire io_l2io_read_req_ready_0 = io_l2io_read_req_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_resp_valid_0 = io_l2io_read_resp_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_read_resp_bits_data_0 = io_l2io_read_resp_bits_data; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_no_memops_inflight_0 = io_l2io_read_no_memops_inflight; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_src_info_valid_0 = io_src_info_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_dst_info_valid_0 = io_dst_info_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_op_0 = io_dst_info_bits_op; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_cmpflag_0 = io_dst_info_bits_cmpflag; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_cmpval_0 = io_dst_info_bits_cmpval; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_req_ready_0 = io_l2io_write_req_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_resp_valid_0 = io_l2io_write_resp_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_write_resp_bits_data_0 = io_l2io_write_resp_bits_data; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_no_memops_inflight_0 = io_l2io_write_no_memops_inflight; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_bytes_written_ready_0 = io_bytes_written_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire [2:0] io_l2io_read_req_bits_size = 3'h5; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_read_req_bits_data = 256'h0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_req_bits_cmd = 1'h0; // @[ZstdRawLiteralEncoder.scala:23:7] wire _header_T_4 = 1'h0; // @[ZstdRawLiteralEncoder.scala:65:26] wire io_l2io_write_req_bits_cmd = 1'h1; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_resp_ready = 1'h1; // @[ZstdRawLiteralEncoder.scala:23:7] wire [3:0] _header_T_11 = 4'hC; // @[ZstdRawLiteralEncoder.scala:66:27] wire [2:0] _header_T_6 = 3'h4; // @[ZstdRawLiteralEncoder.scala:65:45] wire [4:0] _header_T_10 = 5'hC; // @[ZstdRawLiteralEncoder.scala:66:27] wire [3:0] _header_T_5 = 4'h4; // @[ZstdRawLiteralEncoder.scala:65:45] wire _io_src_info_ready_T_1; // @[Misc.scala:26:53] wire _io_bytes_written_valid_T_1; // @[Misc.scala:26:53] wire [70:0] io_l2io_read_req_bits_addr_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_req_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_resp_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_src_info_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_dst_info_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_l2io_write_req_bits_addr_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [2:0] io_l2io_write_req_bits_size_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_write_req_bits_data_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_req_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_bytes_written_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_bytes_written_bits_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire _T = _send_done_q_io_enq_ready & _src_size_q_io_enq_ready; // @[Misc.scala:26:53] wire _memloader_io_src_info_valid_T; // @[Misc.scala:26:53] assign _memloader_io_src_info_valid_T = _T; // @[Misc.scala:26:53] wire _io_src_info_ready_T; // @[Misc.scala:26:53] assign _io_src_info_ready_T = _T; // @[Misc.scala:26:53] wire _memloader_io_src_info_valid_T_1 = _memloader_io_src_info_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] wire _src_size_q_io_enq_valid_T = _send_done_q_io_enq_ready & _memloader_io_src_info_ready; // @[Misc.scala:26:53] wire _src_size_q_io_enq_valid_T_1 = _src_size_q_io_enq_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] wire _send_done_q_io_enq_valid_T = _src_size_q_io_enq_ready & _memloader_io_src_info_ready; // @[Misc.scala:26:53] wire _send_done_q_io_enq_valid_T_1 = _send_done_q_io_enq_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] assign _io_src_info_ready_T_1 = _io_src_info_ready_T & _memloader_io_src_info_ready; // @[Misc.scala:26:53] assign io_src_info_ready_0 = _io_src_info_ready_T_1; // @[Misc.scala:26:53] reg [63:0] input_copy_req_count; // @[ZstdRawLiteralEncoder.scala:49:37] wire _T_2 = _T & _memloader_io_src_info_ready & io_src_info_valid_0; // @[Misc.scala:26:53, :29:18] wire [64:0] _nxt_input_copy_req_cnt_T = {1'h0, input_copy_req_count} + 65'h1; // @[ZstdRawLiteralEncoder.scala:49:37, :51:55] wire [63:0] nxt_input_copy_req_cnt = _nxt_input_copy_req_cnt_T[63:0]; // @[ZstdRawLiteralEncoder.scala:51:55] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _flSize_T = \|(_src_size_q_io_deq_bits[63:5]); // @[ZstdRawLiteralEncoder.scala:29:26, :62:41] wire _flSize_T_1 = _flSize_T; // @[ZstdRawLiteralEncoder.scala:62:{25,41}] wire [1:0] _flSize_T_2 = {1'h0, _flSize_T_1} + 2'h1; // @[ZstdRawLiteralEncoder.scala:62:{20,25}] wire _flSize_T_3 = _flSize_T_2[0]; // @[ZstdRawLiteralEncoder.scala:62:20] wire _flSize_T_4 = \|(_src_size_q_io_deq_bits[63:12]); // @[ZstdRawLiteralEncoder.scala:29:26, :62:80] wire _flSize_T_5 = _flSize_T_4; // @[ZstdRawLiteralEncoder.scala:62:{64,80}] wire [1:0] _flSize_T_6 = {1'h0, _flSize_T_3} + {1'h0, _flSize_T_5}; // @[ZstdRawLiteralEncoder.scala:62:{20,59,64}] wire flSize = _flSize_T_6[0]; // @[ZstdRawLiteralEncoder.scala:62:59] wire _header_T = flSize; // @[ZstdRawLiteralEncoder.scala:62:59, :64:24] wire [23:0] header; // @[ZstdRawLiteralEncoder.scala:63:20] wire [66:0] _header_T_1 = {_src_size_q_io_deq_bits, 3'h0}; // @[ZstdRawLiteralEncoder.scala:29:26, :64:61] wire [67:0] _header_T_2 = {1'h0, _header_T_1}; // @[ZstdRawLiteralEncoder.scala:64:{43,61}] wire [66:0] _header_T_3 = _header_T_2[66:0]; // @[ZstdRawLiteralEncoder.scala:64:43] wire [70:0] _GEN = {3'h0, _src_size_q_io_deq_bits, 4'h0}; // @[ZstdRawLiteralEncoder.scala:29:26, :64:61, :65:76] wire [70:0] _header_T_7; // @[ZstdRawLiteralEncoder.scala:65:76] assign _header_T_7 = _GEN; // @[ZstdRawLiteralEncoder.scala:65:76] wire [70:0] _header_T_12; // @[ZstdRawLiteralEncoder.scala:66:58] assign _header_T_12 = _GEN; // @[ZstdRawLiteralEncoder.scala:65:76, :66:58] wire [71:0] _header_T_8 = {1'h0, _header_T_7} + 72'h4; // @[ZstdRawLiteralEncoder.scala:65:{58,76}] wire [70:0] _header_T_9 = _header_T_8[70:0]; // @[ZstdRawLiteralEncoder.scala:65:58] wire [71:0] _header_T_13 = {1'h0, _header_T_12} + 72'hC; // @[ZstdRawLiteralEncoder.scala:66:{40,58}] wire [70:0] _header_T_14 = _header_T_13[70:0]; // @[ZstdRawLiteralEncoder.scala:66:40] wire [70:0] _header_T_15 = _header_T_4 ? _header_T_9 : _header_T_14; // @[ZstdRawLiteralEncoder.scala:65:{18,26,58}, :66:40] wire [70:0] _header_T_16 = _header_T ? {4'h0, _header_T_3} : _header_T_15; // @[ZstdRawLiteralEncoder.scala:64:{16,24,43}, :65:{18,76}] assign header = _header_T_16[23:0]; // @[ZstdRawLiteralEncoder.scala:63:20, :64:{10,16}] reg header_written; // @[ZstdRawLiteralEncoder.scala:72:31] wire _T_8 = _src_size_q_io_deq_valid & ~header_written; // @[Misc.scala:29:18] wire _header_fire_T; // @[Misc.scala:29:18] assign _header_fire_T = _T_8; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_valid_T; // @[Misc.scala:26:53] assign _memwriter_io_memwrites_in_valid_T = _T_8; // @[Misc.scala:26:53, :29:18] wire _src_size_q_io_deq_ready_T = ~header_written & _memwriter_io_memwrites_in_ready; // @[Misc.scala:26:53] wire header_fire = _header_fire_T & _memwriter_io_memwrites_in_ready; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_valid_T_1 = _memloader_io_consumer_output_valid & header_written; // @[Misc.scala:26:53] wire _memwriter_io_memwrites_in_valid_T_2 = _memwriter_io_memwrites_in_valid_T \| _memwriter_io_memwrites_in_valid_T_1; // @[Misc.scala:26:53] wire [255:0] _memwriter_io_memwrites_in_bits_data_T = header_fire ? {232'h0, header} : _memloader_io_consumer_output_data; // @[Misc.scala:29:18] wire [5:0] _memwriter_io_memwrites_in_bits_validbytes_T = header_fire ? {5'h0, flSize} : _memloader_io_consumer_available_output_bytes; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_bits_end_of_message_T = ~header_fire & _memloader_io_consumer_output_last_chunk; // @[Misc.scala:29:18] wire _memloader_io_consumer_output_ready_T = _memwriter_io_memwrites_in_ready & header_written; // @[Misc.scala:26:53] reg [63:0] bytes_written; // @[ZstdRawLiteralEncoder.scala:104:30] assign io_bytes_written_bits_0 = bytes_written; // @[ZstdRawLiteralEncoder.scala:23:7, :104:30] wire [64:0] _bytes_written_T = {1'h0, bytes_written} + {59'h0, _memwriter_io_memwrites_in_bits_validbytes_T}; // @[ZstdRawLiteralEncoder.scala:96:51, :104:30, :106:36] wire [63:0] _bytes_written_T_1 = _bytes_written_T[63:0]; // @[ZstdRawLiteralEncoder.scala:106:36] wire _T_12 = _memwriter_io_bufs_completed == input_copy_req_count & _memwriter_io_no_writes_inflight; // @[Misc.scala:26:53] wire _io_bytes_written_valid_T; // @[Misc.scala:26:53] assign _io_bytes_written_valid_T = _T_12; // @[Misc.scala:26:53] wire _send_done_q_io_deq_ready_T; // @[Misc.scala:26:53] assign _send_done_q_io_deq_ready_T = _T_12; // @[Misc.scala:26:53] assign _io_bytes_written_valid_T_1 = _io_bytes_written_valid_T & _send_done_q_io_deq_valid; // @[Misc.scala:26:53] assign io_bytes_written_valid_0 = _io_bytes_written_valid_T_1; // @[Misc.scala:26:53] wire _send_done_q_io_deq_ready_T_1 = _send_done_q_io_deq_ready_T & io_bytes_written_ready_0; // @[Misc.scala:26:53] wire _T_14 = _T_12 & io_bytes_written_ready_0 & _send_done_q_io_deq_valid; // @[Misc.scala:26:53, :29:18] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_1 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_1 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_1 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_2 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFNPipe_l2_e5_s11_1( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 \| roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_1 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_1 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_2 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module LSU : input clock : Clock input reset : Reset output io : { ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, core : { flip agen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[1], flip dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[3], iwakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1], iresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], fresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip dis_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], dis_ldq_idx : UInt<5>[3], dis_stq_idx : UInt<5>[3], ldq_full : UInt<1>[3], stq_full : UInt<1>[3], flip commit : { valids : UInt<1>[3], arch_valids : UInt<1>[3], uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[3], debug_wdata : UInt<64>[3]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<7>}[3], clr_unsafe : { valid : UInt<1>, bits : UInt<7>}[1], flip fence_dmem : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip tsc_reg : UInt, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt, flip scontext : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip s1_nack_advisory : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip store_ack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip ll_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, exception : UInt<1>, rob_pnr_idx : UInt<7>, rob_head_idx : UInt<7>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}, flip hellacache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg ldq_valid : UInt<1>[24], clock reg ldq_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock reg ldq_addr : { valid : UInt<1>, bits : UInt<40>}[24], clock reg ldq_addr_is_virtual : UInt<1>[24], clock reg ldq_addr_is_uncacheable : UInt<1>[24], clock reg ldq_executed : UInt<1>[24], clock reg ldq_succeeded : UInt<1>[24], clock reg ldq_order_fail : UInt<1>[24], clock reg ldq_observed : UInt<1>[24], clock reg ldq_st_dep_mask : UInt<24>[24], clock reg ldq_ld_byte_mask : UInt<8>[24], clock reg ldq_forward_std_val : UInt<1>[24], clock reg ldq_forward_stq_idx : UInt<5>[24], clock reg ldq_debug_wb_data : UInt<64>[24], clock reg stq_valid : UInt<1>[24], clock reg stq_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock reg stq_addr : { valid : UInt<1>, bits : UInt<40>}[24], clock reg stq_addr_is_virtual : UInt<1>[24], clock reg stq_data : { valid : UInt<1>, bits : UInt<64>}[24], clock reg stq_committed : UInt<1>[24], clock reg stq_succeeded : UInt<1>[24], clock reg stq_can_execute : UInt<1>[24], clock reg stq_cleared : UInt<1>[24], clock reg stq_debug_wb_data : UInt<64>[24], clock reg ldq_head : UInt<5>, clock reg ldq_tail : UInt<5>, clock reg stq_head : UInt<5>, clock reg stq_tail : UInt<5>, clock reg stq_commit_head : UInt<5>, clock reg stq_execute_head : UInt<5>, clock regreset hella_state : UInt<3>, clock, reset, UInt<3>(0h0) reg hella_req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock reg hella_data : { data : UInt<64>, mask : UInt<8>}, clock reg hella_paddr : UInt<32>, clock reg hella_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, clock inst dtlb of NBDTLB connect dtlb.clock, clock connect dtlb.reset, reset connect dtlb.io.ptw.customCSRs, io.ptw.customCSRs connect dtlb.io.ptw.pmp[0], io.ptw.pmp[0] connect dtlb.io.ptw.pmp[1], io.ptw.pmp[1] connect dtlb.io.ptw.pmp[2], io.ptw.pmp[2] connect dtlb.io.ptw.pmp[3], io.ptw.pmp[3] connect dtlb.io.ptw.pmp[4], io.ptw.pmp[4] connect dtlb.io.ptw.pmp[5], io.ptw.pmp[5] connect dtlb.io.ptw.pmp[6], io.ptw.pmp[6] connect dtlb.io.ptw.pmp[7], io.ptw.pmp[7] connect dtlb.io.ptw.gstatus, io.ptw.gstatus connect dtlb.io.ptw.hstatus, io.ptw.hstatus connect dtlb.io.ptw.status, io.ptw.status connect dtlb.io.ptw.vsatp, io.ptw.vsatp connect dtlb.io.ptw.hgatp, io.ptw.hgatp connect dtlb.io.ptw.ptbr, io.ptw.ptbr connect dtlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, dtlb.io.ptw.req.bits connect io.ptw.req.valid, dtlb.io.ptw.req.valid connect dtlb.io.ptw.req.ready, io.ptw.req.ready node _io_core_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.core.perf.tlbMiss, _io_core_perf_tlbMiss_T connect io.core.perf.acquire, io.dmem.perf.acquire connect io.core.perf.release, io.dmem.perf.release wire clear_store : UInt<1> connect clear_store, UInt<1>(0h0) wire ldq_will_succeed : UInt<1>[24] connect ldq_will_succeed, ldq_succeeded connect ldq_succeeded, ldq_will_succeed when clear_store : node _ldq_st_dep_mask_0_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_0_T_1 = not(_ldq_st_dep_mask_0_T) node _ldq_st_dep_mask_0_T_2 = and(ldq_st_dep_mask[0], _ldq_st_dep_mask_0_T_1) connect ldq_st_dep_mask[0], _ldq_st_dep_mask_0_T_2 when clear_store : node _ldq_st_dep_mask_1_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_1_T_1 = not(_ldq_st_dep_mask_1_T) node _ldq_st_dep_mask_1_T_2 = and(ldq_st_dep_mask[1], _ldq_st_dep_mask_1_T_1) connect ldq_st_dep_mask[1], _ldq_st_dep_mask_1_T_2 when clear_store : node _ldq_st_dep_mask_2_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_2_T_1 = not(_ldq_st_dep_mask_2_T) node _ldq_st_dep_mask_2_T_2 = and(ldq_st_dep_mask[2], _ldq_st_dep_mask_2_T_1) connect ldq_st_dep_mask[2], _ldq_st_dep_mask_2_T_2 when clear_store : node _ldq_st_dep_mask_3_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_3_T_1 = not(_ldq_st_dep_mask_3_T) node _ldq_st_dep_mask_3_T_2 = and(ldq_st_dep_mask[3], _ldq_st_dep_mask_3_T_1) connect ldq_st_dep_mask[3], _ldq_st_dep_mask_3_T_2 when clear_store : node _ldq_st_dep_mask_4_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_4_T_1 = not(_ldq_st_dep_mask_4_T) node _ldq_st_dep_mask_4_T_2 = and(ldq_st_dep_mask[4], _ldq_st_dep_mask_4_T_1) connect ldq_st_dep_mask[4], _ldq_st_dep_mask_4_T_2 when clear_store : node _ldq_st_dep_mask_5_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_5_T_1 = not(_ldq_st_dep_mask_5_T) node _ldq_st_dep_mask_5_T_2 = and(ldq_st_dep_mask[5], _ldq_st_dep_mask_5_T_1) connect ldq_st_dep_mask[5], _ldq_st_dep_mask_5_T_2 when clear_store : node _ldq_st_dep_mask_6_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_6_T_1 = not(_ldq_st_dep_mask_6_T) node _ldq_st_dep_mask_6_T_2 = and(ldq_st_dep_mask[6], _ldq_st_dep_mask_6_T_1) connect ldq_st_dep_mask[6], _ldq_st_dep_mask_6_T_2 when clear_store : node _ldq_st_dep_mask_7_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_7_T_1 = not(_ldq_st_dep_mask_7_T) node _ldq_st_dep_mask_7_T_2 = and(ldq_st_dep_mask[7], _ldq_st_dep_mask_7_T_1) connect ldq_st_dep_mask[7], _ldq_st_dep_mask_7_T_2 when clear_store : node _ldq_st_dep_mask_8_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_8_T_1 = not(_ldq_st_dep_mask_8_T) node _ldq_st_dep_mask_8_T_2 = and(ldq_st_dep_mask[8], _ldq_st_dep_mask_8_T_1) connect ldq_st_dep_mask[8], _ldq_st_dep_mask_8_T_2 when clear_store : node _ldq_st_dep_mask_9_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_9_T_1 = not(_ldq_st_dep_mask_9_T) node _ldq_st_dep_mask_9_T_2 = and(ldq_st_dep_mask[9], _ldq_st_dep_mask_9_T_1) connect ldq_st_dep_mask[9], _ldq_st_dep_mask_9_T_2 when clear_store : node _ldq_st_dep_mask_10_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_10_T_1 = not(_ldq_st_dep_mask_10_T) node _ldq_st_dep_mask_10_T_2 = and(ldq_st_dep_mask[10], _ldq_st_dep_mask_10_T_1) connect ldq_st_dep_mask[10], _ldq_st_dep_mask_10_T_2 when clear_store : node _ldq_st_dep_mask_11_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_11_T_1 = not(_ldq_st_dep_mask_11_T) node _ldq_st_dep_mask_11_T_2 = and(ldq_st_dep_mask[11], _ldq_st_dep_mask_11_T_1) connect ldq_st_dep_mask[11], _ldq_st_dep_mask_11_T_2 when clear_store : node _ldq_st_dep_mask_12_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_12_T_1 = not(_ldq_st_dep_mask_12_T) node _ldq_st_dep_mask_12_T_2 = and(ldq_st_dep_mask[12], _ldq_st_dep_mask_12_T_1) connect ldq_st_dep_mask[12], _ldq_st_dep_mask_12_T_2 when clear_store : node _ldq_st_dep_mask_13_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_13_T_1 = not(_ldq_st_dep_mask_13_T) node _ldq_st_dep_mask_13_T_2 = and(ldq_st_dep_mask[13], _ldq_st_dep_mask_13_T_1) connect ldq_st_dep_mask[13], _ldq_st_dep_mask_13_T_2 when clear_store : node _ldq_st_dep_mask_14_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_14_T_1 = not(_ldq_st_dep_mask_14_T) node _ldq_st_dep_mask_14_T_2 = and(ldq_st_dep_mask[14], _ldq_st_dep_mask_14_T_1) connect ldq_st_dep_mask[14], _ldq_st_dep_mask_14_T_2 when clear_store : node _ldq_st_dep_mask_15_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_15_T_1 = not(_ldq_st_dep_mask_15_T) node _ldq_st_dep_mask_15_T_2 = and(ldq_st_dep_mask[15], _ldq_st_dep_mask_15_T_1) connect ldq_st_dep_mask[15], _ldq_st_dep_mask_15_T_2 when clear_store : node _ldq_st_dep_mask_16_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_16_T_1 = not(_ldq_st_dep_mask_16_T) node _ldq_st_dep_mask_16_T_2 = and(ldq_st_dep_mask[16], _ldq_st_dep_mask_16_T_1) connect ldq_st_dep_mask[16], _ldq_st_dep_mask_16_T_2 when clear_store : node _ldq_st_dep_mask_17_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_17_T_1 = not(_ldq_st_dep_mask_17_T) node _ldq_st_dep_mask_17_T_2 = and(ldq_st_dep_mask[17], _ldq_st_dep_mask_17_T_1) connect ldq_st_dep_mask[17], _ldq_st_dep_mask_17_T_2 when clear_store : node _ldq_st_dep_mask_18_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_18_T_1 = not(_ldq_st_dep_mask_18_T) node _ldq_st_dep_mask_18_T_2 = and(ldq_st_dep_mask[18], _ldq_st_dep_mask_18_T_1) connect ldq_st_dep_mask[18], _ldq_st_dep_mask_18_T_2 when clear_store : node _ldq_st_dep_mask_19_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_19_T_1 = not(_ldq_st_dep_mask_19_T) node _ldq_st_dep_mask_19_T_2 = and(ldq_st_dep_mask[19], _ldq_st_dep_mask_19_T_1) connect ldq_st_dep_mask[19], _ldq_st_dep_mask_19_T_2 when clear_store : node _ldq_st_dep_mask_20_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_20_T_1 = not(_ldq_st_dep_mask_20_T) node _ldq_st_dep_mask_20_T_2 = and(ldq_st_dep_mask[20], _ldq_st_dep_mask_20_T_1) connect ldq_st_dep_mask[20], _ldq_st_dep_mask_20_T_2 when clear_store : node _ldq_st_dep_mask_21_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_21_T_1 = not(_ldq_st_dep_mask_21_T) node _ldq_st_dep_mask_21_T_2 = and(ldq_st_dep_mask[21], _ldq_st_dep_mask_21_T_1) connect ldq_st_dep_mask[21], _ldq_st_dep_mask_21_T_2 when clear_store : node _ldq_st_dep_mask_22_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_22_T_1 = not(_ldq_st_dep_mask_22_T) node _ldq_st_dep_mask_22_T_2 = and(ldq_st_dep_mask[22], _ldq_st_dep_mask_22_T_1) connect ldq_st_dep_mask[22], _ldq_st_dep_mask_22_T_2 when clear_store : node _ldq_st_dep_mask_23_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_23_T_1 = not(_ldq_st_dep_mask_23_T) node _ldq_st_dep_mask_23_T_2 = and(ldq_st_dep_mask[23], _ldq_st_dep_mask_23_T_1) connect ldq_st_dep_mask[23], _ldq_st_dep_mask_23_T_2 reg dis_ldq_oh : UInt<1>[24], clock reg dis_stq_oh : UInt<1>[24], clock connect dis_ldq_oh[0], UInt<1>(0h0) connect dis_ldq_oh[1], UInt<1>(0h0) connect dis_ldq_oh[2], UInt<1>(0h0) connect dis_ldq_oh[3], UInt<1>(0h0) connect dis_ldq_oh[4], UInt<1>(0h0) connect dis_ldq_oh[5], UInt<1>(0h0) connect dis_ldq_oh[6], UInt<1>(0h0) connect dis_ldq_oh[7], UInt<1>(0h0) connect dis_ldq_oh[8], UInt<1>(0h0) connect dis_ldq_oh[9], UInt<1>(0h0) connect dis_ldq_oh[10], UInt<1>(0h0) connect dis_ldq_oh[11], UInt<1>(0h0) connect dis_ldq_oh[12], UInt<1>(0h0) connect dis_ldq_oh[13], UInt<1>(0h0) connect dis_ldq_oh[14], UInt<1>(0h0) connect dis_ldq_oh[15], UInt<1>(0h0) connect dis_ldq_oh[16], UInt<1>(0h0) connect dis_ldq_oh[17], UInt<1>(0h0) connect dis_ldq_oh[18], UInt<1>(0h0) connect dis_ldq_oh[19], UInt<1>(0h0) connect dis_ldq_oh[20], UInt<1>(0h0) connect dis_ldq_oh[21], UInt<1>(0h0) connect dis_ldq_oh[22], UInt<1>(0h0) connect dis_ldq_oh[23], UInt<1>(0h0) connect dis_stq_oh[0], UInt<1>(0h0) connect dis_stq_oh[1], UInt<1>(0h0) connect dis_stq_oh[2], UInt<1>(0h0) connect dis_stq_oh[3], UInt<1>(0h0) connect dis_stq_oh[4], UInt<1>(0h0) connect dis_stq_oh[5], UInt<1>(0h0) connect dis_stq_oh[6], UInt<1>(0h0) connect dis_stq_oh[7], UInt<1>(0h0) connect dis_stq_oh[8], UInt<1>(0h0) connect dis_stq_oh[9], UInt<1>(0h0) connect dis_stq_oh[10], UInt<1>(0h0) connect dis_stq_oh[11], UInt<1>(0h0) connect dis_stq_oh[12], UInt<1>(0h0) connect dis_stq_oh[13], UInt<1>(0h0) connect dis_stq_oh[14], UInt<1>(0h0) connect dis_stq_oh[15], UInt<1>(0h0) connect dis_stq_oh[16], UInt<1>(0h0) connect dis_stq_oh[17], UInt<1>(0h0) connect dis_stq_oh[18], UInt<1>(0h0) connect dis_stq_oh[19], UInt<1>(0h0) connect dis_stq_oh[20], UInt<1>(0h0) connect dis_stq_oh[21], UInt<1>(0h0) connect dis_stq_oh[22], UInt<1>(0h0) connect dis_stq_oh[23], UInt<1>(0h0) reg dis_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], clock node live_store_mask_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node live_store_mask_lo_lo_lo = cat(live_store_mask_lo_lo_lo_hi, stq_valid[0]) node live_store_mask_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node live_store_mask_lo_lo_hi = cat(live_store_mask_lo_lo_hi_hi, stq_valid[3]) node live_store_mask_lo_lo = cat(live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo) node live_store_mask_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node live_store_mask_lo_hi_lo = cat(live_store_mask_lo_hi_lo_hi, stq_valid[6]) node live_store_mask_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node live_store_mask_lo_hi_hi = cat(live_store_mask_lo_hi_hi_hi, stq_valid[9]) node live_store_mask_lo_hi = cat(live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo) node live_store_mask_lo = cat(live_store_mask_lo_hi, live_store_mask_lo_lo) node live_store_mask_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node live_store_mask_hi_lo_lo = cat(live_store_mask_hi_lo_lo_hi, stq_valid[12]) node live_store_mask_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node live_store_mask_hi_lo_hi = cat(live_store_mask_hi_lo_hi_hi, stq_valid[15]) node live_store_mask_hi_lo = cat(live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo) node live_store_mask_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node live_store_mask_hi_hi_lo = cat(live_store_mask_hi_hi_lo_hi, stq_valid[18]) node live_store_mask_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node live_store_mask_hi_hi_hi = cat(live_store_mask_hi_hi_hi_hi, stq_valid[21]) node live_store_mask_hi_hi = cat(live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo) node live_store_mask_hi = cat(live_store_mask_hi_hi, live_store_mask_hi_lo) node _live_store_mask_T = cat(live_store_mask_hi, live_store_mask_lo) node live_store_mask_lo_lo_lo_hi_1 = cat(dis_stq_oh[2], dis_stq_oh[1]) node live_store_mask_lo_lo_lo_1 = cat(live_store_mask_lo_lo_lo_hi_1, dis_stq_oh[0]) node live_store_mask_lo_lo_hi_hi_1 = cat(dis_stq_oh[5], dis_stq_oh[4]) node live_store_mask_lo_lo_hi_1 = cat(live_store_mask_lo_lo_hi_hi_1, dis_stq_oh[3]) node live_store_mask_lo_lo_1 = cat(live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1) node live_store_mask_lo_hi_lo_hi_1 = cat(dis_stq_oh[8], dis_stq_oh[7]) node live_store_mask_lo_hi_lo_1 = cat(live_store_mask_lo_hi_lo_hi_1, dis_stq_oh[6]) node live_store_mask_lo_hi_hi_hi_1 = cat(dis_stq_oh[11], dis_stq_oh[10]) node live_store_mask_lo_hi_hi_1 = cat(live_store_mask_lo_hi_hi_hi_1, dis_stq_oh[9]) node live_store_mask_lo_hi_1 = cat(live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1) node live_store_mask_lo_1 = cat(live_store_mask_lo_hi_1, live_store_mask_lo_lo_1) node live_store_mask_hi_lo_lo_hi_1 = cat(dis_stq_oh[14], dis_stq_oh[13]) node live_store_mask_hi_lo_lo_1 = cat(live_store_mask_hi_lo_lo_hi_1, dis_stq_oh[12]) node live_store_mask_hi_lo_hi_hi_1 = cat(dis_stq_oh[17], dis_stq_oh[16]) node live_store_mask_hi_lo_hi_1 = cat(live_store_mask_hi_lo_hi_hi_1, dis_stq_oh[15]) node live_store_mask_hi_lo_1 = cat(live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1) node live_store_mask_hi_hi_lo_hi_1 = cat(dis_stq_oh[20], dis_stq_oh[19]) node live_store_mask_hi_hi_lo_1 = cat(live_store_mask_hi_hi_lo_hi_1, dis_stq_oh[18]) node live_store_mask_hi_hi_hi_hi_1 = cat(dis_stq_oh[23], dis_stq_oh[22]) node live_store_mask_hi_hi_hi_1 = cat(live_store_mask_hi_hi_hi_hi_1, dis_stq_oh[21]) node live_store_mask_hi_hi_1 = cat(live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1) node live_store_mask_hi_1 = cat(live_store_mask_hi_hi_1, live_store_mask_hi_lo_1) node _live_store_mask_T_1 = cat(live_store_mask_hi_1, live_store_mask_lo_1) node live_store_mask = or(_live_store_mask_T, _live_store_mask_T_1) node _next_live_store_mask_T = dshl(UInt<1>(0h1), stq_head) node _next_live_store_mask_T_1 = not(_next_live_store_mask_T) node _next_live_store_mask_T_2 = and(live_store_mask, _next_live_store_mask_T_1) node next_live_store_mask = mux(clear_store, _next_live_store_mask_T_2, live_store_mask) node _ldq_tail_oh_T = dshl(UInt<1>(0h1), ldq_tail) node ldq_tail_oh = bits(_ldq_tail_oh_T, 23, 0) node ldq_valids_lo_lo_lo_hi = cat(ldq_valid[2], ldq_valid[1]) node ldq_valids_lo_lo_lo = cat(ldq_valids_lo_lo_lo_hi, ldq_valid[0]) node ldq_valids_lo_lo_hi_hi = cat(ldq_valid[5], ldq_valid[4]) node ldq_valids_lo_lo_hi = cat(ldq_valids_lo_lo_hi_hi, ldq_valid[3]) node ldq_valids_lo_lo = cat(ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo) node ldq_valids_lo_hi_lo_hi = cat(ldq_valid[8], ldq_valid[7]) node ldq_valids_lo_hi_lo = cat(ldq_valids_lo_hi_lo_hi, ldq_valid[6]) node ldq_valids_lo_hi_hi_hi = cat(ldq_valid[11], ldq_valid[10]) node ldq_valids_lo_hi_hi = cat(ldq_valids_lo_hi_hi_hi, ldq_valid[9]) node ldq_valids_lo_hi = cat(ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo) node ldq_valids_lo = cat(ldq_valids_lo_hi, ldq_valids_lo_lo) node ldq_valids_hi_lo_lo_hi = cat(ldq_valid[14], ldq_valid[13]) node ldq_valids_hi_lo_lo = cat(ldq_valids_hi_lo_lo_hi, ldq_valid[12]) node ldq_valids_hi_lo_hi_hi = cat(ldq_valid[17], ldq_valid[16]) node ldq_valids_hi_lo_hi = cat(ldq_valids_hi_lo_hi_hi, ldq_valid[15]) node ldq_valids_hi_lo = cat(ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo) node ldq_valids_hi_hi_lo_hi = cat(ldq_valid[20], ldq_valid[19]) node ldq_valids_hi_hi_lo = cat(ldq_valids_hi_hi_lo_hi, ldq_valid[18]) node ldq_valids_hi_hi_hi_hi = cat(ldq_valid[23], ldq_valid[22]) node ldq_valids_hi_hi_hi = cat(ldq_valids_hi_hi_hi_hi, ldq_valid[21]) node ldq_valids_hi_hi = cat(ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo) node ldq_valids_hi = cat(ldq_valids_hi_hi, ldq_valids_hi_lo) node _ldq_valids_T = cat(ldq_valids_hi, ldq_valids_lo) node ldq_valids_lo_lo_lo_hi_1 = cat(dis_ldq_oh[2], dis_ldq_oh[1]) node ldq_valids_lo_lo_lo_1 = cat(ldq_valids_lo_lo_lo_hi_1, dis_ldq_oh[0]) node ldq_valids_lo_lo_hi_hi_1 = cat(dis_ldq_oh[5], dis_ldq_oh[4]) node ldq_valids_lo_lo_hi_1 = cat(ldq_valids_lo_lo_hi_hi_1, dis_ldq_oh[3]) node ldq_valids_lo_lo_1 = cat(ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1) node ldq_valids_lo_hi_lo_hi_1 = cat(dis_ldq_oh[8], dis_ldq_oh[7]) node ldq_valids_lo_hi_lo_1 = cat(ldq_valids_lo_hi_lo_hi_1, dis_ldq_oh[6]) node ldq_valids_lo_hi_hi_hi_1 = cat(dis_ldq_oh[11], dis_ldq_oh[10]) node ldq_valids_lo_hi_hi_1 = cat(ldq_valids_lo_hi_hi_hi_1, dis_ldq_oh[9]) node ldq_valids_lo_hi_1 = cat(ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1) node ldq_valids_lo_1 = cat(ldq_valids_lo_hi_1, ldq_valids_lo_lo_1) node ldq_valids_hi_lo_lo_hi_1 = cat(dis_ldq_oh[14], dis_ldq_oh[13]) node ldq_valids_hi_lo_lo_1 = cat(ldq_valids_hi_lo_lo_hi_1, dis_ldq_oh[12]) node ldq_valids_hi_lo_hi_hi_1 = cat(dis_ldq_oh[17], dis_ldq_oh[16]) node ldq_valids_hi_lo_hi_1 = cat(ldq_valids_hi_lo_hi_hi_1, dis_ldq_oh[15]) node ldq_valids_hi_lo_1 = cat(ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1) node ldq_valids_hi_hi_lo_hi_1 = cat(dis_ldq_oh[20], dis_ldq_oh[19]) node ldq_valids_hi_hi_lo_1 = cat(ldq_valids_hi_hi_lo_hi_1, dis_ldq_oh[18]) node ldq_valids_hi_hi_hi_hi_1 = cat(dis_ldq_oh[23], dis_ldq_oh[22]) node ldq_valids_hi_hi_hi_1 = cat(ldq_valids_hi_hi_hi_hi_1, dis_ldq_oh[21]) node ldq_valids_hi_hi_1 = cat(ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1) node ldq_valids_hi_1 = cat(ldq_valids_hi_hi_1, ldq_valids_hi_lo_1) node _ldq_valids_T_1 = cat(ldq_valids_hi_1, ldq_valids_lo_1) node ldq_valids = or(_ldq_valids_T, _ldq_valids_T_1) node _stq_tail_oh_T = dshl(UInt<1>(0h1), stq_tail) node stq_tail_oh = bits(_stq_tail_oh_T, 23, 0) node stq_valids_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node stq_valids_lo_lo_lo = cat(stq_valids_lo_lo_lo_hi, stq_valid[0]) node stq_valids_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node stq_valids_lo_lo_hi = cat(stq_valids_lo_lo_hi_hi, stq_valid[3]) node stq_valids_lo_lo = cat(stq_valids_lo_lo_hi, stq_valids_lo_lo_lo) node stq_valids_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node stq_valids_lo_hi_lo = cat(stq_valids_lo_hi_lo_hi, stq_valid[6]) node stq_valids_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node stq_valids_lo_hi_hi = cat(stq_valids_lo_hi_hi_hi, stq_valid[9]) node stq_valids_lo_hi = cat(stq_valids_lo_hi_hi, stq_valids_lo_hi_lo) node stq_valids_lo = cat(stq_valids_lo_hi, stq_valids_lo_lo) node stq_valids_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node stq_valids_hi_lo_lo = cat(stq_valids_hi_lo_lo_hi, stq_valid[12]) node stq_valids_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node stq_valids_hi_lo_hi = cat(stq_valids_hi_lo_hi_hi, stq_valid[15]) node stq_valids_hi_lo = cat(stq_valids_hi_lo_hi, stq_valids_hi_lo_lo) node stq_valids_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node stq_valids_hi_hi_lo = cat(stq_valids_hi_hi_lo_hi, stq_valid[18]) node stq_valids_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node stq_valids_hi_hi_hi = cat(stq_valids_hi_hi_hi_hi, stq_valid[21]) node stq_valids_hi_hi = cat(stq_valids_hi_hi_hi, stq_valids_hi_hi_lo) node stq_valids_hi = cat(stq_valids_hi_hi, stq_valids_hi_lo) node _stq_valids_T = cat(stq_valids_hi, stq_valids_lo) node stq_valids_lo_lo_lo_hi_1 = cat(dis_stq_oh[2], dis_stq_oh[1]) node stq_valids_lo_lo_lo_1 = cat(stq_valids_lo_lo_lo_hi_1, dis_stq_oh[0]) node stq_valids_lo_lo_hi_hi_1 = cat(dis_stq_oh[5], dis_stq_oh[4]) node stq_valids_lo_lo_hi_1 = cat(stq_valids_lo_lo_hi_hi_1, dis_stq_oh[3]) node stq_valids_lo_lo_1 = cat(stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1) node stq_valids_lo_hi_lo_hi_1 = cat(dis_stq_oh[8], dis_stq_oh[7]) node stq_valids_lo_hi_lo_1 = cat(stq_valids_lo_hi_lo_hi_1, dis_stq_oh[6]) node stq_valids_lo_hi_hi_hi_1 = cat(dis_stq_oh[11], dis_stq_oh[10]) node stq_valids_lo_hi_hi_1 = cat(stq_valids_lo_hi_hi_hi_1, dis_stq_oh[9]) node stq_valids_lo_hi_1 = cat(stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1) node stq_valids_lo_1 = cat(stq_valids_lo_hi_1, stq_valids_lo_lo_1) node stq_valids_hi_lo_lo_hi_1 = cat(dis_stq_oh[14], dis_stq_oh[13]) node stq_valids_hi_lo_lo_1 = cat(stq_valids_hi_lo_lo_hi_1, dis_stq_oh[12]) node stq_valids_hi_lo_hi_hi_1 = cat(dis_stq_oh[17], dis_stq_oh[16]) node stq_valids_hi_lo_hi_1 = cat(stq_valids_hi_lo_hi_hi_1, dis_stq_oh[15]) node stq_valids_hi_lo_1 = cat(stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1) node stq_valids_hi_hi_lo_hi_1 = cat(dis_stq_oh[20], dis_stq_oh[19]) node stq_valids_hi_hi_lo_1 = cat(stq_valids_hi_hi_lo_hi_1, dis_stq_oh[18]) node stq_valids_hi_hi_hi_hi_1 = cat(dis_stq_oh[23], dis_stq_oh[22]) node stq_valids_hi_hi_hi_1 = cat(stq_valids_hi_hi_hi_hi_1, dis_stq_oh[21]) node stq_valids_hi_hi_1 = cat(stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1) node stq_valids_hi_1 = cat(stq_valids_hi_hi_1, stq_valids_hi_lo_1) node _stq_valids_T_1 = cat(stq_valids_hi_1, stq_valids_lo_1) node stq_valids = or(_stq_valids_T, _stq_valids_T_1) node _stq_nonempty_T = or(stq_valid[0], stq_valid[1]) node _stq_nonempty_T_1 = or(_stq_nonempty_T, stq_valid[2]) node _stq_nonempty_T_2 = or(_stq_nonempty_T_1, stq_valid[3]) node _stq_nonempty_T_3 = or(_stq_nonempty_T_2, stq_valid[4]) node _stq_nonempty_T_4 = or(_stq_nonempty_T_3, stq_valid[5]) node _stq_nonempty_T_5 = or(_stq_nonempty_T_4, stq_valid[6]) node _stq_nonempty_T_6 = or(_stq_nonempty_T_5, stq_valid[7]) node _stq_nonempty_T_7 = or(_stq_nonempty_T_6, stq_valid[8]) node _stq_nonempty_T_8 = or(_stq_nonempty_T_7, stq_valid[9]) node _stq_nonempty_T_9 = or(_stq_nonempty_T_8, stq_valid[10]) node _stq_nonempty_T_10 = or(_stq_nonempty_T_9, stq_valid[11]) node _stq_nonempty_T_11 = or(_stq_nonempty_T_10, stq_valid[12]) node _stq_nonempty_T_12 = or(_stq_nonempty_T_11, stq_valid[13]) node _stq_nonempty_T_13 = or(_stq_nonempty_T_12, stq_valid[14]) node _stq_nonempty_T_14 = or(_stq_nonempty_T_13, stq_valid[15]) node _stq_nonempty_T_15 = or(_stq_nonempty_T_14, stq_valid[16]) node _stq_nonempty_T_16 = or(_stq_nonempty_T_15, stq_valid[17]) node _stq_nonempty_T_17 = or(_stq_nonempty_T_16, stq_valid[18]) node _stq_nonempty_T_18 = or(_stq_nonempty_T_17, stq_valid[19]) node _stq_nonempty_T_19 = or(_stq_nonempty_T_18, stq_valid[20]) node _stq_nonempty_T_20 = or(_stq_nonempty_T_19, stq_valid[21]) node _stq_nonempty_T_21 = or(_stq_nonempty_T_20, stq_valid[22]) node stq_nonempty = or(_stq_nonempty_T_21, stq_valid[23]) node _ldq_full_T = and(ldq_tail_oh, ldq_valids) node ldq_full = orr(_ldq_full_T) connect io.core.ldq_full[0], ldq_full connect io.core.dis_ldq_idx[0], ldq_tail node _stq_full_T = and(stq_tail_oh, stq_valids) node stq_full = orr(_stq_full_T) connect io.core.stq_full[0], stq_full connect io.core.dis_stq_idx[0], stq_tail node _dis_ld_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_ldq) node _dis_ld_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node dis_ld_val = and(_dis_ld_val_T, _dis_ld_val_T_1) node _dis_st_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_stq) node _dis_st_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node dis_st_val = and(_dis_st_val_T, _dis_st_val_T_1) node _dis_uops_0_valid_T = or(dis_ld_val, dis_st_val) connect dis_uops[0].valid, _dis_uops_0_valid_T connect dis_uops[0].bits, io.core.dis_uops[0].bits when dis_ld_val : connect dis_ldq_oh[ldq_tail], UInt<1>(0h1) connect ldq_st_dep_mask[ldq_tail], next_live_store_mask node _T = eq(ldq_tail, io.core.dis_uops[0].bits.ldq_idx) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _T_4 = eq(ldq_valid[ldq_tail], UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_1 assert(clock, _T_4, UInt<1>(0h1), "") : assert_1 when dis_st_val : connect dis_stq_oh[stq_tail], UInt<1>(0h1) node _T_8 = eq(stq_tail, io.core.dis_uops[0].bits.stq_idx) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_2 assert(clock, _T_8, UInt<1>(0h1), "") : assert_2 node _T_12 = eq(stq_valid[stq_tail], UInt<1>(0h0)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_3 assert(clock, _T_12, UInt<1>(0h1), "") : assert_3 node _T_16 = and(dis_uops[0].valid, dis_uops[0].bits.uses_ldq) when _T_16 : node _ldq_valid_T = and(io.core.brupdate.b1.mispredict_mask, dis_uops[0].bits.br_mask) node _ldq_valid_T_1 = neq(_ldq_valid_T, UInt<1>(0h0)) node _ldq_valid_T_2 = or(_ldq_valid_T_1, io.core.exception) node _ldq_valid_T_3 = eq(_ldq_valid_T_2, UInt<1>(0h0)) connect ldq_valid[dis_uops[0].bits.ldq_idx], _ldq_valid_T_3 wire ldq_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out, dis_uops[0].bits node _ldq_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_1 = and(dis_uops[0].bits.br_mask, _ldq_uop_out_br_mask_T) connect ldq_uop_out.br_mask, _ldq_uop_out_br_mask_T_1 connect ldq_uop[dis_uops[0].bits.ldq_idx], ldq_uop_out connect ldq_addr[dis_uops[0].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) node _T_17 = and(dis_uops[0].valid, dis_uops[0].bits.uses_stq) when _T_17 : node _stq_valid_T = and(io.core.brupdate.b1.mispredict_mask, dis_uops[0].bits.br_mask) node _stq_valid_T_1 = neq(_stq_valid_T, UInt<1>(0h0)) node _stq_valid_T_2 = or(_stq_valid_T_1, io.core.exception) node _stq_valid_T_3 = eq(_stq_valid_T_2, UInt<1>(0h0)) connect stq_valid[dis_uops[0].bits.stq_idx], _stq_valid_T_3 wire stq_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out, dis_uops[0].bits node _stq_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_1 = and(dis_uops[0].bits.br_mask, _stq_uop_out_br_mask_T) connect stq_uop_out.br_mask, _stq_uop_out_br_mask_T_1 connect stq_uop[dis_uops[0].bits.stq_idx], stq_uop_out connect stq_addr[dis_uops[0].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[0].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[0].bits.stq_idx], UInt<1>(0h0) node wrap = eq(ldq_tail, UInt<5>(0h17)) node _T_18 = add(ldq_tail, UInt<1>(0h1)) node _T_19 = tail(_T_18, 1) node _T_20 = mux(wrap, UInt<1>(0h0), _T_19) node _T_21 = mux(dis_ld_val, _T_20, ldq_tail) node _T_22 = dshl(UInt<1>(0h1), stq_tail) node _T_23 = or(next_live_store_mask, _T_22) node _T_24 = mux(dis_st_val, _T_23, next_live_store_mask) node wrap_1 = eq(stq_tail, UInt<5>(0h17)) node _T_25 = add(stq_tail, UInt<1>(0h1)) node _T_26 = tail(_T_25, 1) node _T_27 = mux(wrap_1, UInt<1>(0h0), _T_26) node _T_28 = mux(dis_st_val, _T_27, stq_tail) node _T_29 = and(dis_ld_val, dis_st_val) node _T_30 = eq(_T_29, UInt<1>(0h0)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_4 assert(clock, _T_30, UInt<1>(0h1), "") : assert_4 node _T_34 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node _T_35 = and(io.core.dis_uops[0].bits.uses_ldq, _T_34) node _T_36 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_37 = or(_T_35, _T_36) node _out_T = bits(ldq_tail_oh, 22, 0) node _out_T_1 = bits(ldq_tail_oh, 23, 23) node out = cat(_out_T, _out_T_1) node _T_38 = mux(_T_37, out, ldq_tail_oh) node _T_39 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node _T_40 = and(io.core.dis_uops[0].bits.uses_stq, _T_39) node _T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _out_T_2 = bits(stq_tail_oh, 22, 0) node _out_T_3 = bits(stq_tail_oh, 23, 23) node out_1 = cat(_out_T_2, _out_T_3) node _T_43 = mux(_T_42, out_1, stq_tail_oh) node _ldq_full_T_1 = and(_T_38, ldq_valids) node ldq_full_1 = orr(_ldq_full_T_1) connect io.core.ldq_full[1], ldq_full_1 connect io.core.dis_ldq_idx[1], _T_21 node _stq_full_T_1 = and(_T_43, stq_valids) node stq_full_1 = orr(_stq_full_T_1) connect io.core.stq_full[1], stq_full_1 connect io.core.dis_stq_idx[1], _T_28 node _dis_ld_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_ldq) node _dis_ld_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node dis_ld_val_1 = and(_dis_ld_val_T_2, _dis_ld_val_T_3) node _dis_st_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_stq) node _dis_st_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node dis_st_val_1 = and(_dis_st_val_T_2, _dis_st_val_T_3) node _dis_uops_1_valid_T = or(dis_ld_val_1, dis_st_val_1) connect dis_uops[1].valid, _dis_uops_1_valid_T connect dis_uops[1].bits, io.core.dis_uops[1].bits when dis_ld_val_1 : connect dis_ldq_oh[_T_21], UInt<1>(0h1) connect ldq_st_dep_mask[_T_21], _T_24 node _T_44 = eq(_T_21, io.core.dis_uops[1].bits.ldq_idx) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_5 assert(clock, _T_44, UInt<1>(0h1), "") : assert_5 node _T_48 = eq(ldq_valid[_T_21], UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_6 assert(clock, _T_48, UInt<1>(0h1), "") : assert_6 when dis_st_val_1 : connect dis_stq_oh[_T_28], UInt<1>(0h1) node _T_52 = eq(_T_28, io.core.dis_uops[1].bits.stq_idx) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 node _T_56 = eq(stq_valid[_T_28], UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_8 assert(clock, _T_56, UInt<1>(0h1), "") : assert_8 node _T_60 = and(dis_uops[1].valid, dis_uops[1].bits.uses_ldq) when _T_60 : node _ldq_valid_T_4 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[1].bits.br_mask) node _ldq_valid_T_5 = neq(_ldq_valid_T_4, UInt<1>(0h0)) node _ldq_valid_T_6 = or(_ldq_valid_T_5, io.core.exception) node _ldq_valid_T_7 = eq(_ldq_valid_T_6, UInt<1>(0h0)) connect ldq_valid[dis_uops[1].bits.ldq_idx], _ldq_valid_T_7 wire ldq_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out_1, dis_uops[1].bits node _ldq_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_3 = and(dis_uops[1].bits.br_mask, _ldq_uop_out_br_mask_T_2) connect ldq_uop_out_1.br_mask, _ldq_uop_out_br_mask_T_3 connect ldq_uop[dis_uops[1].bits.ldq_idx], ldq_uop_out_1 connect ldq_addr[dis_uops[1].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) node _T_61 = and(dis_uops[1].valid, dis_uops[1].bits.uses_stq) when _T_61 : node _stq_valid_T_4 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[1].bits.br_mask) node _stq_valid_T_5 = neq(_stq_valid_T_4, UInt<1>(0h0)) node _stq_valid_T_6 = or(_stq_valid_T_5, io.core.exception) node _stq_valid_T_7 = eq(_stq_valid_T_6, UInt<1>(0h0)) connect stq_valid[dis_uops[1].bits.stq_idx], _stq_valid_T_7 wire stq_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out_1, dis_uops[1].bits node _stq_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_3 = and(dis_uops[1].bits.br_mask, _stq_uop_out_br_mask_T_2) connect stq_uop_out_1.br_mask, _stq_uop_out_br_mask_T_3 connect stq_uop[dis_uops[1].bits.stq_idx], stq_uop_out_1 connect stq_addr[dis_uops[1].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[1].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[1].bits.stq_idx], UInt<1>(0h0) node wrap_2 = eq(_T_21, UInt<5>(0h17)) node _T_62 = add(_T_21, UInt<1>(0h1)) node _T_63 = tail(_T_62, 1) node _T_64 = mux(wrap_2, UInt<1>(0h0), _T_63) node _T_65 = mux(dis_ld_val_1, _T_64, _T_21) node _T_66 = dshl(UInt<1>(0h1), _T_28) node _T_67 = or(_T_24, _T_66) node _T_68 = mux(dis_st_val_1, _T_67, _T_24) node wrap_3 = eq(_T_28, UInt<5>(0h17)) node _T_69 = add(_T_28, UInt<1>(0h1)) node _T_70 = tail(_T_69, 1) node _T_71 = mux(wrap_3, UInt<1>(0h0), _T_70) node _T_72 = mux(dis_st_val_1, _T_71, _T_28) node _T_73 = and(dis_ld_val_1, dis_st_val_1) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_9 assert(clock, _T_74, UInt<1>(0h1), "") : assert_9 node _T_78 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node _T_79 = and(io.core.dis_uops[1].bits.uses_ldq, _T_78) node _T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_81 = or(_T_79, _T_80) node _out_T_4 = bits(_T_38, 22, 0) node _out_T_5 = bits(_T_38, 23, 23) node out_2 = cat(_out_T_4, _out_T_5) node _T_82 = mux(_T_81, out_2, _T_38) node _T_83 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node _T_84 = and(io.core.dis_uops[1].bits.uses_stq, _T_83) node _T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_86 = or(_T_84, _T_85) node _out_T_6 = bits(_T_43, 22, 0) node _out_T_7 = bits(_T_43, 23, 23) node out_3 = cat(_out_T_6, _out_T_7) node _T_87 = mux(_T_86, out_3, _T_43) node _ldq_full_T_2 = and(_T_82, ldq_valids) node ldq_full_2 = orr(_ldq_full_T_2) connect io.core.ldq_full[2], ldq_full_2 connect io.core.dis_ldq_idx[2], _T_65 node _stq_full_T_2 = and(_T_87, stq_valids) node stq_full_2 = orr(_stq_full_T_2) connect io.core.stq_full[2], stq_full_2 connect io.core.dis_stq_idx[2], _T_72 node _dis_ld_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_ldq) node _dis_ld_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node dis_ld_val_2 = and(_dis_ld_val_T_4, _dis_ld_val_T_5) node _dis_st_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_stq) node _dis_st_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node dis_st_val_2 = and(_dis_st_val_T_4, _dis_st_val_T_5) node _dis_uops_2_valid_T = or(dis_ld_val_2, dis_st_val_2) connect dis_uops[2].valid, _dis_uops_2_valid_T connect dis_uops[2].bits, io.core.dis_uops[2].bits when dis_ld_val_2 : connect dis_ldq_oh[_T_65], UInt<1>(0h1) connect ldq_st_dep_mask[_T_65], _T_68 node _T_88 = eq(_T_65, io.core.dis_uops[2].bits.ldq_idx) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_10 assert(clock, _T_88, UInt<1>(0h1), "") : assert_10 node _T_92 = eq(ldq_valid[_T_65], UInt<1>(0h0)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_11 assert(clock, _T_92, UInt<1>(0h1), "") : assert_11 when dis_st_val_2 : connect dis_stq_oh[_T_72], UInt<1>(0h1) node _T_96 = eq(_T_72, io.core.dis_uops[2].bits.stq_idx) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_12 assert(clock, _T_96, UInt<1>(0h1), "") : assert_12 node _T_100 = eq(stq_valid[_T_72], UInt<1>(0h0)) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_13 assert(clock, _T_100, UInt<1>(0h1), "") : assert_13 node _T_104 = and(dis_uops[2].valid, dis_uops[2].bits.uses_ldq) when _T_104 : node _ldq_valid_T_8 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[2].bits.br_mask) node _ldq_valid_T_9 = neq(_ldq_valid_T_8, UInt<1>(0h0)) node _ldq_valid_T_10 = or(_ldq_valid_T_9, io.core.exception) node _ldq_valid_T_11 = eq(_ldq_valid_T_10, UInt<1>(0h0)) connect ldq_valid[dis_uops[2].bits.ldq_idx], _ldq_valid_T_11 wire ldq_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out_2, dis_uops[2].bits node _ldq_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_5 = and(dis_uops[2].bits.br_mask, _ldq_uop_out_br_mask_T_4) connect ldq_uop_out_2.br_mask, _ldq_uop_out_br_mask_T_5 connect ldq_uop[dis_uops[2].bits.ldq_idx], ldq_uop_out_2 connect ldq_addr[dis_uops[2].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) node _T_105 = and(dis_uops[2].valid, dis_uops[2].bits.uses_stq) when _T_105 : node _stq_valid_T_8 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[2].bits.br_mask) node _stq_valid_T_9 = neq(_stq_valid_T_8, UInt<1>(0h0)) node _stq_valid_T_10 = or(_stq_valid_T_9, io.core.exception) node _stq_valid_T_11 = eq(_stq_valid_T_10, UInt<1>(0h0)) connect stq_valid[dis_uops[2].bits.stq_idx], _stq_valid_T_11 wire stq_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out_2, dis_uops[2].bits node _stq_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_5 = and(dis_uops[2].bits.br_mask, _stq_uop_out_br_mask_T_4) connect stq_uop_out_2.br_mask, _stq_uop_out_br_mask_T_5 connect stq_uop[dis_uops[2].bits.stq_idx], stq_uop_out_2 connect stq_addr[dis_uops[2].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[2].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[2].bits.stq_idx], UInt<1>(0h0) node wrap_4 = eq(_T_65, UInt<5>(0h17)) node _T_106 = add(_T_65, UInt<1>(0h1)) node _T_107 = tail(_T_106, 1) node _T_108 = mux(wrap_4, UInt<1>(0h0), _T_107) node _T_109 = mux(dis_ld_val_2, _T_108, _T_65) node _T_110 = dshl(UInt<1>(0h1), _T_72) node _T_111 = or(_T_68, _T_110) node _T_112 = mux(dis_st_val_2, _T_111, _T_68) node wrap_5 = eq(_T_72, UInt<5>(0h17)) node _T_113 = add(_T_72, UInt<1>(0h1)) node _T_114 = tail(_T_113, 1) node _T_115 = mux(wrap_5, UInt<1>(0h0), _T_114) node _T_116 = mux(dis_st_val_2, _T_115, _T_72) node _T_117 = and(dis_ld_val_2, dis_st_val_2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_14 assert(clock, _T_118, UInt<1>(0h1), "") : assert_14 node _T_122 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node _T_123 = and(io.core.dis_uops[2].bits.uses_ldq, _T_122) node _T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_125 = or(_T_123, _T_124) node _out_T_8 = bits(_T_82, 22, 0) node _out_T_9 = bits(_T_82, 23, 23) node out_4 = cat(_out_T_8, _out_T_9) node _T_126 = mux(_T_125, out_4, _T_82) node _T_127 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node _T_128 = and(io.core.dis_uops[2].bits.uses_stq, _T_127) node _T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_130 = or(_T_128, _T_129) node _out_T_10 = bits(_T_87, 22, 0) node _out_T_11 = bits(_T_87, 23, 23) node out_5 = cat(_out_T_10, _out_T_11) node _T_131 = mux(_T_130, out_5, _T_87) connect ldq_tail, _T_109 connect stq_tail, _T_116 node _T_132 = or(io.core.brupdate.b2.mispredict, stq_valid[stq_execute_head]) node _T_133 = or(_T_132, dis_stq_oh[stq_execute_head]) node _T_134 = eq(stq_head, stq_execute_head) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(stq_tail, stq_execute_head) node _T_137 = or(_T_135, _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: stq_execute_head got off track.\n at lsu.scala:438 assert (io.core.brupdate.b2.mispredict \|\|\n") : printf_15 assert(clock, _T_137, UInt<1>(0h1), "") : assert_15 connect io.dmem.force_order, io.core.fence_dmem node _io_core_fencei_rdy_T = eq(stq_nonempty, UInt<1>(0h0)) node _io_core_fencei_rdy_T_1 = and(_io_core_fencei_rdy_T, io.dmem.ordered) connect io.core.fencei_rdy, _io_core_fencei_rdy_T_1 wire mem_xcpt_valid : UInt<1> wire mem_xcpt_cause : UInt wire mem_xcpt_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire mem_xcpt_vaddr : UInt wire will_fire_load_agen_exec : UInt<1>[1] wire will_fire_load_agen : UInt<1>[1] wire will_fire_store_agen : UInt<1>[1] wire will_fire_sfence : UInt<1>[1] wire will_fire_hella_incoming : UInt<1>[1] wire will_fire_hella_wakeup : UInt<1>[1] wire will_fire_release : UInt<1>[1] wire will_fire_load_retry : UInt<1>[1] wire will_fire_store_retry : UInt<1>[1] wire will_fire_store_commit_fast : UInt<1>[1] wire will_fire_store_commit_slow : UInt<1>[1] wire will_fire_load_wakeup : UInt<1>[1] wire _block_load_mask_WIRE : UInt<1>[24] connect _block_load_mask_WIRE[0], UInt<1>(0h0) connect _block_load_mask_WIRE[1], UInt<1>(0h0) connect _block_load_mask_WIRE[2], UInt<1>(0h0) connect _block_load_mask_WIRE[3], UInt<1>(0h0) connect _block_load_mask_WIRE[4], UInt<1>(0h0) connect _block_load_mask_WIRE[5], UInt<1>(0h0) connect _block_load_mask_WIRE[6], UInt<1>(0h0) connect _block_load_mask_WIRE[7], UInt<1>(0h0) connect _block_load_mask_WIRE[8], UInt<1>(0h0) connect _block_load_mask_WIRE[9], UInt<1>(0h0) connect _block_load_mask_WIRE[10], UInt<1>(0h0) connect _block_load_mask_WIRE[11], UInt<1>(0h0) connect _block_load_mask_WIRE[12], UInt<1>(0h0) connect _block_load_mask_WIRE[13], UInt<1>(0h0) connect _block_load_mask_WIRE[14], UInt<1>(0h0) connect _block_load_mask_WIRE[15], UInt<1>(0h0) connect _block_load_mask_WIRE[16], UInt<1>(0h0) connect _block_load_mask_WIRE[17], UInt<1>(0h0) connect _block_load_mask_WIRE[18], UInt<1>(0h0) connect _block_load_mask_WIRE[19], UInt<1>(0h0) connect _block_load_mask_WIRE[20], UInt<1>(0h0) connect _block_load_mask_WIRE[21], UInt<1>(0h0) connect _block_load_mask_WIRE[22], UInt<1>(0h0) connect _block_load_mask_WIRE[23], UInt<1>(0h0) wire block_load_mask : UInt<1>[24] connect block_load_mask, _block_load_mask_WIRE reg p1_block_load_mask : UInt<1>[24], clock connect p1_block_load_mask, block_load_mask reg p2_block_load_mask : UInt<1>[24], clock connect p2_block_load_mask, p1_block_load_mask node _stq_tail_plus_sum_T = cat(UInt<1>(0h0), stq_tail) node _stq_tail_plus_sum_T_1 = cat(UInt<1>(0h0), UInt<3>(0h6)) node _stq_tail_plus_sum_T_2 = add(_stq_tail_plus_sum_T, _stq_tail_plus_sum_T_1) node stq_tail_plus_sum = tail(_stq_tail_plus_sum_T_2, 1) node _stq_tail_plus_T = geq(stq_tail_plus_sum, UInt<5>(0h18)) node _stq_tail_plus_T_1 = sub(stq_tail_plus_sum, UInt<5>(0h18)) node _stq_tail_plus_T_2 = tail(_stq_tail_plus_T_1, 1) node stq_tail_plus = mux(_stq_tail_plus_T, _stq_tail_plus_T_2, stq_tail_plus_sum) node _stq_almost_full_T = lt(stq_head, stq_tail_plus) node _stq_almost_full_T_1 = lt(stq_head, stq_tail) node _stq_almost_full_T_2 = xor(_stq_almost_full_T, _stq_almost_full_T_1) node _stq_almost_full_T_3 = lt(stq_tail_plus, stq_tail) node _stq_almost_full_T_4 = xor(_stq_almost_full_T_2, _stq_almost_full_T_3) reg stq_almost_full : UInt<1>, clock connect stq_almost_full, _stq_almost_full_T_4 wire store_needs_order : UInt<1> connect store_needs_order, UInt<1>(0h0) wire ldq_incoming_idx : UInt<5>[1] connect ldq_incoming_idx[0], io.core.agen[0].bits.uop.ldq_idx wire ldq_incoming_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_incoming_e_e.valid, ldq_valid[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.uop, ldq_uop[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr, ldq_addr[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.executed, ldq_executed[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.succeeded, ldq_succeeded[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.order_fail, ldq_order_fail[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.observed, ldq_observed[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.st_dep_mask, ldq_st_dep_mask[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.forward_std_val, ldq_forward_std_val[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.debug_wb_data, ldq_debug_wb_data[ldq_incoming_idx[0]] wire _ldq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect _ldq_incoming_e_WIRE, ldq_incoming_e_e wire ldq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect ldq_incoming_e[0], _ldq_incoming_e_WIRE wire stq_incoming_idx : UInt<5>[1] connect stq_incoming_idx[0], io.core.agen[0].bits.uop.stq_idx wire stq_incoming_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_incoming_e_e.valid, stq_valid[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.uop, stq_uop[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.addr, stq_addr[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.data, stq_data[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.committed, stq_committed[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.succeeded, stq_succeeded[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.can_execute, stq_can_execute[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.cleared, stq_cleared[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_incoming_idx[0]] wire _stq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect _stq_incoming_e_WIRE, stq_incoming_e_e wire stq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect stq_incoming_e[0], _stq_incoming_e_WIRE node ldq_wakeup_idx_block = or(block_load_mask[0], p1_block_load_mask[0]) node _ldq_wakeup_idx_T = eq(ldq_executed[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_1 = and(ldq_addr[0].valid, _ldq_wakeup_idx_T) node _ldq_wakeup_idx_T_2 = eq(ldq_succeeded[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_3 = and(_ldq_wakeup_idx_T_1, _ldq_wakeup_idx_T_2) node _ldq_wakeup_idx_T_4 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_5 = and(_ldq_wakeup_idx_T_3, _ldq_wakeup_idx_T_4) node _ldq_wakeup_idx_T_6 = eq(ldq_wakeup_idx_block, UInt<1>(0h0)) node _ldq_wakeup_idx_T_7 = and(_ldq_wakeup_idx_T_5, _ldq_wakeup_idx_T_6) node ldq_wakeup_idx_block_1 = or(block_load_mask[1], p1_block_load_mask[1]) node _ldq_wakeup_idx_T_8 = eq(ldq_executed[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_9 = and(ldq_addr[1].valid, _ldq_wakeup_idx_T_8) node _ldq_wakeup_idx_T_10 = eq(ldq_succeeded[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_11 = and(_ldq_wakeup_idx_T_9, _ldq_wakeup_idx_T_10) node _ldq_wakeup_idx_T_12 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_13 = and(_ldq_wakeup_idx_T_11, _ldq_wakeup_idx_T_12) node _ldq_wakeup_idx_T_14 = eq(ldq_wakeup_idx_block_1, UInt<1>(0h0)) node _ldq_wakeup_idx_T_15 = and(_ldq_wakeup_idx_T_13, _ldq_wakeup_idx_T_14) node ldq_wakeup_idx_block_2 = or(block_load_mask[2], p1_block_load_mask[2]) node _ldq_wakeup_idx_T_16 = eq(ldq_executed[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_17 = and(ldq_addr[2].valid, _ldq_wakeup_idx_T_16) node _ldq_wakeup_idx_T_18 = eq(ldq_succeeded[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_19 = and(_ldq_wakeup_idx_T_17, _ldq_wakeup_idx_T_18) node _ldq_wakeup_idx_T_20 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_21 = and(_ldq_wakeup_idx_T_19, _ldq_wakeup_idx_T_20) node _ldq_wakeup_idx_T_22 = eq(ldq_wakeup_idx_block_2, UInt<1>(0h0)) node _ldq_wakeup_idx_T_23 = and(_ldq_wakeup_idx_T_21, _ldq_wakeup_idx_T_22) node ldq_wakeup_idx_block_3 = or(block_load_mask[3], p1_block_load_mask[3]) node _ldq_wakeup_idx_T_24 = eq(ldq_executed[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_25 = and(ldq_addr[3].valid, _ldq_wakeup_idx_T_24) node _ldq_wakeup_idx_T_26 = eq(ldq_succeeded[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_27 = and(_ldq_wakeup_idx_T_25, _ldq_wakeup_idx_T_26) node _ldq_wakeup_idx_T_28 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_29 = and(_ldq_wakeup_idx_T_27, _ldq_wakeup_idx_T_28) node _ldq_wakeup_idx_T_30 = eq(ldq_wakeup_idx_block_3, UInt<1>(0h0)) node _ldq_wakeup_idx_T_31 = and(_ldq_wakeup_idx_T_29, _ldq_wakeup_idx_T_30) node ldq_wakeup_idx_block_4 = or(block_load_mask[4], p1_block_load_mask[4]) node _ldq_wakeup_idx_T_32 = eq(ldq_executed[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_33 = and(ldq_addr[4].valid, _ldq_wakeup_idx_T_32) node _ldq_wakeup_idx_T_34 = eq(ldq_succeeded[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_35 = and(_ldq_wakeup_idx_T_33, _ldq_wakeup_idx_T_34) node _ldq_wakeup_idx_T_36 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_37 = and(_ldq_wakeup_idx_T_35, _ldq_wakeup_idx_T_36) node _ldq_wakeup_idx_T_38 = eq(ldq_wakeup_idx_block_4, UInt<1>(0h0)) node _ldq_wakeup_idx_T_39 = and(_ldq_wakeup_idx_T_37, _ldq_wakeup_idx_T_38) node ldq_wakeup_idx_block_5 = or(block_load_mask[5], p1_block_load_mask[5]) node _ldq_wakeup_idx_T_40 = eq(ldq_executed[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_41 = and(ldq_addr[5].valid, _ldq_wakeup_idx_T_40) node _ldq_wakeup_idx_T_42 = eq(ldq_succeeded[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_43 = and(_ldq_wakeup_idx_T_41, _ldq_wakeup_idx_T_42) node _ldq_wakeup_idx_T_44 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_45 = and(_ldq_wakeup_idx_T_43, _ldq_wakeup_idx_T_44) node _ldq_wakeup_idx_T_46 = eq(ldq_wakeup_idx_block_5, UInt<1>(0h0)) node _ldq_wakeup_idx_T_47 = and(_ldq_wakeup_idx_T_45, _ldq_wakeup_idx_T_46) node ldq_wakeup_idx_block_6 = or(block_load_mask[6], p1_block_load_mask[6]) node _ldq_wakeup_idx_T_48 = eq(ldq_executed[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_49 = and(ldq_addr[6].valid, _ldq_wakeup_idx_T_48) node _ldq_wakeup_idx_T_50 = eq(ldq_succeeded[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_51 = and(_ldq_wakeup_idx_T_49, _ldq_wakeup_idx_T_50) node _ldq_wakeup_idx_T_52 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_53 = and(_ldq_wakeup_idx_T_51, _ldq_wakeup_idx_T_52) node _ldq_wakeup_idx_T_54 = eq(ldq_wakeup_idx_block_6, UInt<1>(0h0)) node _ldq_wakeup_idx_T_55 = and(_ldq_wakeup_idx_T_53, _ldq_wakeup_idx_T_54) node ldq_wakeup_idx_block_7 = or(block_load_mask[7], p1_block_load_mask[7]) node _ldq_wakeup_idx_T_56 = eq(ldq_executed[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_57 = and(ldq_addr[7].valid, _ldq_wakeup_idx_T_56) node _ldq_wakeup_idx_T_58 = eq(ldq_succeeded[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_59 = and(_ldq_wakeup_idx_T_57, _ldq_wakeup_idx_T_58) node _ldq_wakeup_idx_T_60 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_61 = and(_ldq_wakeup_idx_T_59, _ldq_wakeup_idx_T_60) node _ldq_wakeup_idx_T_62 = eq(ldq_wakeup_idx_block_7, UInt<1>(0h0)) node _ldq_wakeup_idx_T_63 = and(_ldq_wakeup_idx_T_61, _ldq_wakeup_idx_T_62) node ldq_wakeup_idx_block_8 = or(block_load_mask[8], p1_block_load_mask[8]) node _ldq_wakeup_idx_T_64 = eq(ldq_executed[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_65 = and(ldq_addr[8].valid, _ldq_wakeup_idx_T_64) node _ldq_wakeup_idx_T_66 = eq(ldq_succeeded[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_67 = and(_ldq_wakeup_idx_T_65, _ldq_wakeup_idx_T_66) node _ldq_wakeup_idx_T_68 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_69 = and(_ldq_wakeup_idx_T_67, _ldq_wakeup_idx_T_68) node _ldq_wakeup_idx_T_70 = eq(ldq_wakeup_idx_block_8, UInt<1>(0h0)) node _ldq_wakeup_idx_T_71 = and(_ldq_wakeup_idx_T_69, _ldq_wakeup_idx_T_70) node ldq_wakeup_idx_block_9 = or(block_load_mask[9], p1_block_load_mask[9]) node _ldq_wakeup_idx_T_72 = eq(ldq_executed[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_73 = and(ldq_addr[9].valid, _ldq_wakeup_idx_T_72) node _ldq_wakeup_idx_T_74 = eq(ldq_succeeded[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_75 = and(_ldq_wakeup_idx_T_73, _ldq_wakeup_idx_T_74) node _ldq_wakeup_idx_T_76 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_77 = and(_ldq_wakeup_idx_T_75, _ldq_wakeup_idx_T_76) node _ldq_wakeup_idx_T_78 = eq(ldq_wakeup_idx_block_9, UInt<1>(0h0)) node _ldq_wakeup_idx_T_79 = and(_ldq_wakeup_idx_T_77, _ldq_wakeup_idx_T_78) node ldq_wakeup_idx_block_10 = or(block_load_mask[10], p1_block_load_mask[10]) node _ldq_wakeup_idx_T_80 = eq(ldq_executed[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_81 = and(ldq_addr[10].valid, _ldq_wakeup_idx_T_80) node _ldq_wakeup_idx_T_82 = eq(ldq_succeeded[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_83 = and(_ldq_wakeup_idx_T_81, _ldq_wakeup_idx_T_82) node _ldq_wakeup_idx_T_84 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_85 = and(_ldq_wakeup_idx_T_83, _ldq_wakeup_idx_T_84) node _ldq_wakeup_idx_T_86 = eq(ldq_wakeup_idx_block_10, UInt<1>(0h0)) node _ldq_wakeup_idx_T_87 = and(_ldq_wakeup_idx_T_85, _ldq_wakeup_idx_T_86) node ldq_wakeup_idx_block_11 = or(block_load_mask[11], p1_block_load_mask[11]) node _ldq_wakeup_idx_T_88 = eq(ldq_executed[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_89 = and(ldq_addr[11].valid, _ldq_wakeup_idx_T_88) node _ldq_wakeup_idx_T_90 = eq(ldq_succeeded[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_91 = and(_ldq_wakeup_idx_T_89, _ldq_wakeup_idx_T_90) node _ldq_wakeup_idx_T_92 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_93 = and(_ldq_wakeup_idx_T_91, _ldq_wakeup_idx_T_92) node _ldq_wakeup_idx_T_94 = eq(ldq_wakeup_idx_block_11, UInt<1>(0h0)) node _ldq_wakeup_idx_T_95 = and(_ldq_wakeup_idx_T_93, _ldq_wakeup_idx_T_94) node ldq_wakeup_idx_block_12 = or(block_load_mask[12], p1_block_load_mask[12]) node _ldq_wakeup_idx_T_96 = eq(ldq_executed[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_97 = and(ldq_addr[12].valid, _ldq_wakeup_idx_T_96) node _ldq_wakeup_idx_T_98 = eq(ldq_succeeded[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_99 = and(_ldq_wakeup_idx_T_97, _ldq_wakeup_idx_T_98) node _ldq_wakeup_idx_T_100 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_101 = and(_ldq_wakeup_idx_T_99, _ldq_wakeup_idx_T_100) node _ldq_wakeup_idx_T_102 = eq(ldq_wakeup_idx_block_12, UInt<1>(0h0)) node _ldq_wakeup_idx_T_103 = and(_ldq_wakeup_idx_T_101, _ldq_wakeup_idx_T_102) node ldq_wakeup_idx_block_13 = or(block_load_mask[13], p1_block_load_mask[13]) node _ldq_wakeup_idx_T_104 = eq(ldq_executed[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_105 = and(ldq_addr[13].valid, _ldq_wakeup_idx_T_104) node _ldq_wakeup_idx_T_106 = eq(ldq_succeeded[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_107 = and(_ldq_wakeup_idx_T_105, _ldq_wakeup_idx_T_106) node _ldq_wakeup_idx_T_108 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_109 = and(_ldq_wakeup_idx_T_107, _ldq_wakeup_idx_T_108) node _ldq_wakeup_idx_T_110 = eq(ldq_wakeup_idx_block_13, UInt<1>(0h0)) node _ldq_wakeup_idx_T_111 = and(_ldq_wakeup_idx_T_109, _ldq_wakeup_idx_T_110) node ldq_wakeup_idx_block_14 = or(block_load_mask[14], p1_block_load_mask[14]) node _ldq_wakeup_idx_T_112 = eq(ldq_executed[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_113 = and(ldq_addr[14].valid, _ldq_wakeup_idx_T_112) node _ldq_wakeup_idx_T_114 = eq(ldq_succeeded[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_115 = and(_ldq_wakeup_idx_T_113, _ldq_wakeup_idx_T_114) node _ldq_wakeup_idx_T_116 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_117 = and(_ldq_wakeup_idx_T_115, _ldq_wakeup_idx_T_116) node _ldq_wakeup_idx_T_118 = eq(ldq_wakeup_idx_block_14, UInt<1>(0h0)) node _ldq_wakeup_idx_T_119 = and(_ldq_wakeup_idx_T_117, _ldq_wakeup_idx_T_118) node ldq_wakeup_idx_block_15 = or(block_load_mask[15], p1_block_load_mask[15]) node _ldq_wakeup_idx_T_120 = eq(ldq_executed[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_121 = and(ldq_addr[15].valid, _ldq_wakeup_idx_T_120) node _ldq_wakeup_idx_T_122 = eq(ldq_succeeded[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_123 = and(_ldq_wakeup_idx_T_121, _ldq_wakeup_idx_T_122) node _ldq_wakeup_idx_T_124 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_125 = and(_ldq_wakeup_idx_T_123, _ldq_wakeup_idx_T_124) node _ldq_wakeup_idx_T_126 = eq(ldq_wakeup_idx_block_15, UInt<1>(0h0)) node _ldq_wakeup_idx_T_127 = and(_ldq_wakeup_idx_T_125, _ldq_wakeup_idx_T_126) node ldq_wakeup_idx_block_16 = or(block_load_mask[16], p1_block_load_mask[16]) node _ldq_wakeup_idx_T_128 = eq(ldq_executed[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_129 = and(ldq_addr[16].valid, _ldq_wakeup_idx_T_128) node _ldq_wakeup_idx_T_130 = eq(ldq_succeeded[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_131 = and(_ldq_wakeup_idx_T_129, _ldq_wakeup_idx_T_130) node _ldq_wakeup_idx_T_132 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_133 = and(_ldq_wakeup_idx_T_131, _ldq_wakeup_idx_T_132) node _ldq_wakeup_idx_T_134 = eq(ldq_wakeup_idx_block_16, UInt<1>(0h0)) node _ldq_wakeup_idx_T_135 = and(_ldq_wakeup_idx_T_133, _ldq_wakeup_idx_T_134) node ldq_wakeup_idx_block_17 = or(block_load_mask[17], p1_block_load_mask[17]) node _ldq_wakeup_idx_T_136 = eq(ldq_executed[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_137 = and(ldq_addr[17].valid, _ldq_wakeup_idx_T_136) node _ldq_wakeup_idx_T_138 = eq(ldq_succeeded[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_139 = and(_ldq_wakeup_idx_T_137, _ldq_wakeup_idx_T_138) node _ldq_wakeup_idx_T_140 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_141 = and(_ldq_wakeup_idx_T_139, _ldq_wakeup_idx_T_140) node _ldq_wakeup_idx_T_142 = eq(ldq_wakeup_idx_block_17, UInt<1>(0h0)) node _ldq_wakeup_idx_T_143 = and(_ldq_wakeup_idx_T_141, _ldq_wakeup_idx_T_142) node ldq_wakeup_idx_block_18 = or(block_load_mask[18], p1_block_load_mask[18]) node _ldq_wakeup_idx_T_144 = eq(ldq_executed[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_145 = and(ldq_addr[18].valid, _ldq_wakeup_idx_T_144) node _ldq_wakeup_idx_T_146 = eq(ldq_succeeded[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_147 = and(_ldq_wakeup_idx_T_145, _ldq_wakeup_idx_T_146) node _ldq_wakeup_idx_T_148 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_149 = and(_ldq_wakeup_idx_T_147, _ldq_wakeup_idx_T_148) node _ldq_wakeup_idx_T_150 = eq(ldq_wakeup_idx_block_18, UInt<1>(0h0)) node _ldq_wakeup_idx_T_151 = and(_ldq_wakeup_idx_T_149, _ldq_wakeup_idx_T_150) node ldq_wakeup_idx_block_19 = or(block_load_mask[19], p1_block_load_mask[19]) node _ldq_wakeup_idx_T_152 = eq(ldq_executed[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_153 = and(ldq_addr[19].valid, _ldq_wakeup_idx_T_152) node _ldq_wakeup_idx_T_154 = eq(ldq_succeeded[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_155 = and(_ldq_wakeup_idx_T_153, _ldq_wakeup_idx_T_154) node _ldq_wakeup_idx_T_156 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_157 = and(_ldq_wakeup_idx_T_155, _ldq_wakeup_idx_T_156) node _ldq_wakeup_idx_T_158 = eq(ldq_wakeup_idx_block_19, UInt<1>(0h0)) node _ldq_wakeup_idx_T_159 = and(_ldq_wakeup_idx_T_157, _ldq_wakeup_idx_T_158) node ldq_wakeup_idx_block_20 = or(block_load_mask[20], p1_block_load_mask[20]) node _ldq_wakeup_idx_T_160 = eq(ldq_executed[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_161 = and(ldq_addr[20].valid, _ldq_wakeup_idx_T_160) node _ldq_wakeup_idx_T_162 = eq(ldq_succeeded[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_163 = and(_ldq_wakeup_idx_T_161, _ldq_wakeup_idx_T_162) node _ldq_wakeup_idx_T_164 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_165 = and(_ldq_wakeup_idx_T_163, _ldq_wakeup_idx_T_164) node _ldq_wakeup_idx_T_166 = eq(ldq_wakeup_idx_block_20, UInt<1>(0h0)) node _ldq_wakeup_idx_T_167 = and(_ldq_wakeup_idx_T_165, _ldq_wakeup_idx_T_166) node ldq_wakeup_idx_block_21 = or(block_load_mask[21], p1_block_load_mask[21]) node _ldq_wakeup_idx_T_168 = eq(ldq_executed[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_169 = and(ldq_addr[21].valid, _ldq_wakeup_idx_T_168) node _ldq_wakeup_idx_T_170 = eq(ldq_succeeded[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_171 = and(_ldq_wakeup_idx_T_169, _ldq_wakeup_idx_T_170) node _ldq_wakeup_idx_T_172 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_173 = and(_ldq_wakeup_idx_T_171, _ldq_wakeup_idx_T_172) node _ldq_wakeup_idx_T_174 = eq(ldq_wakeup_idx_block_21, UInt<1>(0h0)) node _ldq_wakeup_idx_T_175 = and(_ldq_wakeup_idx_T_173, _ldq_wakeup_idx_T_174) node ldq_wakeup_idx_block_22 = or(block_load_mask[22], p1_block_load_mask[22]) node _ldq_wakeup_idx_T_176 = eq(ldq_executed[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_177 = and(ldq_addr[22].valid, _ldq_wakeup_idx_T_176) node _ldq_wakeup_idx_T_178 = eq(ldq_succeeded[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_179 = and(_ldq_wakeup_idx_T_177, _ldq_wakeup_idx_T_178) node _ldq_wakeup_idx_T_180 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_181 = and(_ldq_wakeup_idx_T_179, _ldq_wakeup_idx_T_180) node _ldq_wakeup_idx_T_182 = eq(ldq_wakeup_idx_block_22, UInt<1>(0h0)) node _ldq_wakeup_idx_T_183 = and(_ldq_wakeup_idx_T_181, _ldq_wakeup_idx_T_182) node ldq_wakeup_idx_block_23 = or(block_load_mask[23], p1_block_load_mask[23]) node _ldq_wakeup_idx_T_184 = eq(ldq_executed[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_185 = and(ldq_addr[23].valid, _ldq_wakeup_idx_T_184) node _ldq_wakeup_idx_T_186 = eq(ldq_succeeded[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_187 = and(_ldq_wakeup_idx_T_185, _ldq_wakeup_idx_T_186) node _ldq_wakeup_idx_T_188 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_189 = and(_ldq_wakeup_idx_T_187, _ldq_wakeup_idx_T_188) node _ldq_wakeup_idx_T_190 = eq(ldq_wakeup_idx_block_23, UInt<1>(0h0)) node _ldq_wakeup_idx_T_191 = and(_ldq_wakeup_idx_T_189, _ldq_wakeup_idx_T_190) node _ldq_wakeup_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node ldq_wakeup_idx_temp_vec_0 = and(_ldq_wakeup_idx_T_7, _ldq_wakeup_idx_temp_vec_T) node _ldq_wakeup_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node ldq_wakeup_idx_temp_vec_1 = and(_ldq_wakeup_idx_T_15, _ldq_wakeup_idx_temp_vec_T_1) node _ldq_wakeup_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node ldq_wakeup_idx_temp_vec_2 = and(_ldq_wakeup_idx_T_23, _ldq_wakeup_idx_temp_vec_T_2) node _ldq_wakeup_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node ldq_wakeup_idx_temp_vec_3 = and(_ldq_wakeup_idx_T_31, _ldq_wakeup_idx_temp_vec_T_3) node _ldq_wakeup_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node ldq_wakeup_idx_temp_vec_4 = and(_ldq_wakeup_idx_T_39, _ldq_wakeup_idx_temp_vec_T_4) node _ldq_wakeup_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node ldq_wakeup_idx_temp_vec_5 = and(_ldq_wakeup_idx_T_47, _ldq_wakeup_idx_temp_vec_T_5) node _ldq_wakeup_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node ldq_wakeup_idx_temp_vec_6 = and(_ldq_wakeup_idx_T_55, _ldq_wakeup_idx_temp_vec_T_6) node _ldq_wakeup_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node ldq_wakeup_idx_temp_vec_7 = and(_ldq_wakeup_idx_T_63, _ldq_wakeup_idx_temp_vec_T_7) node _ldq_wakeup_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node ldq_wakeup_idx_temp_vec_8 = and(_ldq_wakeup_idx_T_71, _ldq_wakeup_idx_temp_vec_T_8) node _ldq_wakeup_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node ldq_wakeup_idx_temp_vec_9 = and(_ldq_wakeup_idx_T_79, _ldq_wakeup_idx_temp_vec_T_9) node _ldq_wakeup_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node ldq_wakeup_idx_temp_vec_10 = and(_ldq_wakeup_idx_T_87, _ldq_wakeup_idx_temp_vec_T_10) node _ldq_wakeup_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node ldq_wakeup_idx_temp_vec_11 = and(_ldq_wakeup_idx_T_95, _ldq_wakeup_idx_temp_vec_T_11) node _ldq_wakeup_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node ldq_wakeup_idx_temp_vec_12 = and(_ldq_wakeup_idx_T_103, _ldq_wakeup_idx_temp_vec_T_12) node _ldq_wakeup_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node ldq_wakeup_idx_temp_vec_13 = and(_ldq_wakeup_idx_T_111, _ldq_wakeup_idx_temp_vec_T_13) node _ldq_wakeup_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node ldq_wakeup_idx_temp_vec_14 = and(_ldq_wakeup_idx_T_119, _ldq_wakeup_idx_temp_vec_T_14) node _ldq_wakeup_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node ldq_wakeup_idx_temp_vec_15 = and(_ldq_wakeup_idx_T_127, _ldq_wakeup_idx_temp_vec_T_15) node _ldq_wakeup_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node ldq_wakeup_idx_temp_vec_16 = and(_ldq_wakeup_idx_T_135, _ldq_wakeup_idx_temp_vec_T_16) node _ldq_wakeup_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node ldq_wakeup_idx_temp_vec_17 = and(_ldq_wakeup_idx_T_143, _ldq_wakeup_idx_temp_vec_T_17) node _ldq_wakeup_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node ldq_wakeup_idx_temp_vec_18 = and(_ldq_wakeup_idx_T_151, _ldq_wakeup_idx_temp_vec_T_18) node _ldq_wakeup_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node ldq_wakeup_idx_temp_vec_19 = and(_ldq_wakeup_idx_T_159, _ldq_wakeup_idx_temp_vec_T_19) node _ldq_wakeup_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node ldq_wakeup_idx_temp_vec_20 = and(_ldq_wakeup_idx_T_167, _ldq_wakeup_idx_temp_vec_T_20) node _ldq_wakeup_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node ldq_wakeup_idx_temp_vec_21 = and(_ldq_wakeup_idx_T_175, _ldq_wakeup_idx_temp_vec_T_21) node _ldq_wakeup_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node ldq_wakeup_idx_temp_vec_22 = and(_ldq_wakeup_idx_T_183, _ldq_wakeup_idx_temp_vec_T_22) node _ldq_wakeup_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node ldq_wakeup_idx_temp_vec_23 = and(_ldq_wakeup_idx_T_191, _ldq_wakeup_idx_temp_vec_T_23) node _ldq_wakeup_idx_idx_T = mux(_ldq_wakeup_idx_T_183, UInt<6>(0h36), UInt<6>(0h37)) node _ldq_wakeup_idx_idx_T_1 = mux(_ldq_wakeup_idx_T_175, UInt<6>(0h35), _ldq_wakeup_idx_idx_T) node _ldq_wakeup_idx_idx_T_2 = mux(_ldq_wakeup_idx_T_167, UInt<6>(0h34), _ldq_wakeup_idx_idx_T_1) node _ldq_wakeup_idx_idx_T_3 = mux(_ldq_wakeup_idx_T_159, UInt<6>(0h33), _ldq_wakeup_idx_idx_T_2) node _ldq_wakeup_idx_idx_T_4 = mux(_ldq_wakeup_idx_T_151, UInt<6>(0h32), _ldq_wakeup_idx_idx_T_3) node _ldq_wakeup_idx_idx_T_5 = mux(_ldq_wakeup_idx_T_143, UInt<6>(0h31), _ldq_wakeup_idx_idx_T_4) node _ldq_wakeup_idx_idx_T_6 = mux(_ldq_wakeup_idx_T_135, UInt<6>(0h30), _ldq_wakeup_idx_idx_T_5) node _ldq_wakeup_idx_idx_T_7 = mux(_ldq_wakeup_idx_T_127, UInt<6>(0h2f), _ldq_wakeup_idx_idx_T_6) node _ldq_wakeup_idx_idx_T_8 = mux(_ldq_wakeup_idx_T_119, UInt<6>(0h2e), _ldq_wakeup_idx_idx_T_7) node _ldq_wakeup_idx_idx_T_9 = mux(_ldq_wakeup_idx_T_111, UInt<6>(0h2d), _ldq_wakeup_idx_idx_T_8) node _ldq_wakeup_idx_idx_T_10 = mux(_ldq_wakeup_idx_T_103, UInt<6>(0h2c), _ldq_wakeup_idx_idx_T_9) node _ldq_wakeup_idx_idx_T_11 = mux(_ldq_wakeup_idx_T_95, UInt<6>(0h2b), _ldq_wakeup_idx_idx_T_10) node _ldq_wakeup_idx_idx_T_12 = mux(_ldq_wakeup_idx_T_87, UInt<6>(0h2a), _ldq_wakeup_idx_idx_T_11) node _ldq_wakeup_idx_idx_T_13 = mux(_ldq_wakeup_idx_T_79, UInt<6>(0h29), _ldq_wakeup_idx_idx_T_12) node _ldq_wakeup_idx_idx_T_14 = mux(_ldq_wakeup_idx_T_71, UInt<6>(0h28), _ldq_wakeup_idx_idx_T_13) node _ldq_wakeup_idx_idx_T_15 = mux(_ldq_wakeup_idx_T_63, UInt<6>(0h27), _ldq_wakeup_idx_idx_T_14) node _ldq_wakeup_idx_idx_T_16 = mux(_ldq_wakeup_idx_T_55, UInt<6>(0h26), _ldq_wakeup_idx_idx_T_15) node _ldq_wakeup_idx_idx_T_17 = mux(_ldq_wakeup_idx_T_47, UInt<6>(0h25), _ldq_wakeup_idx_idx_T_16) node _ldq_wakeup_idx_idx_T_18 = mux(_ldq_wakeup_idx_T_39, UInt<6>(0h24), _ldq_wakeup_idx_idx_T_17) node _ldq_wakeup_idx_idx_T_19 = mux(_ldq_wakeup_idx_T_31, UInt<6>(0h23), _ldq_wakeup_idx_idx_T_18) node _ldq_wakeup_idx_idx_T_20 = mux(_ldq_wakeup_idx_T_23, UInt<6>(0h22), _ldq_wakeup_idx_idx_T_19) node _ldq_wakeup_idx_idx_T_21 = mux(_ldq_wakeup_idx_T_15, UInt<6>(0h21), _ldq_wakeup_idx_idx_T_20) node _ldq_wakeup_idx_idx_T_22 = mux(_ldq_wakeup_idx_T_7, UInt<6>(0h20), _ldq_wakeup_idx_idx_T_21) node _ldq_wakeup_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_wakeup_idx_idx_T_22) node _ldq_wakeup_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_wakeup_idx_idx_T_23) node _ldq_wakeup_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_wakeup_idx_idx_T_24) node _ldq_wakeup_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_wakeup_idx_idx_T_25) node _ldq_wakeup_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_wakeup_idx_idx_T_26) node _ldq_wakeup_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_wakeup_idx_idx_T_27) node _ldq_wakeup_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_wakeup_idx_idx_T_28) node _ldq_wakeup_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_wakeup_idx_idx_T_29) node _ldq_wakeup_idx_idx_T_31 = mux(ldq_wakeup_idx_temp_vec_23, UInt<5>(0h17), _ldq_wakeup_idx_idx_T_30) node _ldq_wakeup_idx_idx_T_32 = mux(ldq_wakeup_idx_temp_vec_22, UInt<5>(0h16), _ldq_wakeup_idx_idx_T_31) node _ldq_wakeup_idx_idx_T_33 = mux(ldq_wakeup_idx_temp_vec_21, UInt<5>(0h15), _ldq_wakeup_idx_idx_T_32) node _ldq_wakeup_idx_idx_T_34 = mux(ldq_wakeup_idx_temp_vec_20, UInt<5>(0h14), _ldq_wakeup_idx_idx_T_33) node _ldq_wakeup_idx_idx_T_35 = mux(ldq_wakeup_idx_temp_vec_19, UInt<5>(0h13), _ldq_wakeup_idx_idx_T_34) node _ldq_wakeup_idx_idx_T_36 = mux(ldq_wakeup_idx_temp_vec_18, UInt<5>(0h12), _ldq_wakeup_idx_idx_T_35) node _ldq_wakeup_idx_idx_T_37 = mux(ldq_wakeup_idx_temp_vec_17, UInt<5>(0h11), _ldq_wakeup_idx_idx_T_36) node _ldq_wakeup_idx_idx_T_38 = mux(ldq_wakeup_idx_temp_vec_16, UInt<5>(0h10), _ldq_wakeup_idx_idx_T_37) node _ldq_wakeup_idx_idx_T_39 = mux(ldq_wakeup_idx_temp_vec_15, UInt<4>(0hf), _ldq_wakeup_idx_idx_T_38) node _ldq_wakeup_idx_idx_T_40 = mux(ldq_wakeup_idx_temp_vec_14, UInt<4>(0he), _ldq_wakeup_idx_idx_T_39) node _ldq_wakeup_idx_idx_T_41 = mux(ldq_wakeup_idx_temp_vec_13, UInt<4>(0hd), _ldq_wakeup_idx_idx_T_40) node _ldq_wakeup_idx_idx_T_42 = mux(ldq_wakeup_idx_temp_vec_12, UInt<4>(0hc), _ldq_wakeup_idx_idx_T_41) node _ldq_wakeup_idx_idx_T_43 = mux(ldq_wakeup_idx_temp_vec_11, UInt<4>(0hb), _ldq_wakeup_idx_idx_T_42) node _ldq_wakeup_idx_idx_T_44 = mux(ldq_wakeup_idx_temp_vec_10, UInt<4>(0ha), _ldq_wakeup_idx_idx_T_43) node _ldq_wakeup_idx_idx_T_45 = mux(ldq_wakeup_idx_temp_vec_9, UInt<4>(0h9), _ldq_wakeup_idx_idx_T_44) node _ldq_wakeup_idx_idx_T_46 = mux(ldq_wakeup_idx_temp_vec_8, UInt<4>(0h8), _ldq_wakeup_idx_idx_T_45) node _ldq_wakeup_idx_idx_T_47 = mux(ldq_wakeup_idx_temp_vec_7, UInt<3>(0h7), _ldq_wakeup_idx_idx_T_46) node _ldq_wakeup_idx_idx_T_48 = mux(ldq_wakeup_idx_temp_vec_6, UInt<3>(0h6), _ldq_wakeup_idx_idx_T_47) node _ldq_wakeup_idx_idx_T_49 = mux(ldq_wakeup_idx_temp_vec_5, UInt<3>(0h5), _ldq_wakeup_idx_idx_T_48) node _ldq_wakeup_idx_idx_T_50 = mux(ldq_wakeup_idx_temp_vec_4, UInt<3>(0h4), _ldq_wakeup_idx_idx_T_49) node _ldq_wakeup_idx_idx_T_51 = mux(ldq_wakeup_idx_temp_vec_3, UInt<2>(0h3), _ldq_wakeup_idx_idx_T_50) node _ldq_wakeup_idx_idx_T_52 = mux(ldq_wakeup_idx_temp_vec_2, UInt<2>(0h2), _ldq_wakeup_idx_idx_T_51) node _ldq_wakeup_idx_idx_T_53 = mux(ldq_wakeup_idx_temp_vec_1, UInt<1>(0h1), _ldq_wakeup_idx_idx_T_52) node ldq_wakeup_idx_idx = mux(ldq_wakeup_idx_temp_vec_0, UInt<1>(0h0), _ldq_wakeup_idx_idx_T_53) node _ldq_wakeup_idx_T_192 = bits(ldq_wakeup_idx_idx, 4, 0) reg ldq_wakeup_idx : UInt, clock connect ldq_wakeup_idx, _ldq_wakeup_idx_T_192 wire ldq_wakeup_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} node _ldq_wakeup_e_e_valid_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_valid_T_1 = bits(_ldq_wakeup_e_e_valid_T, 4, 0) connect ldq_wakeup_e_e.valid, ldq_valid[_ldq_wakeup_e_e_valid_T_1] node _ldq_wakeup_e_e_bits_uop_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_uop_T_1 = bits(_ldq_wakeup_e_e_bits_uop_T, 4, 0) connect ldq_wakeup_e_e.bits.uop, ldq_uop[_ldq_wakeup_e_e_bits_uop_T_1] node _ldq_wakeup_e_e_bits_addr_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_T_1 = bits(_ldq_wakeup_e_e_bits_addr_T, 4, 0) connect ldq_wakeup_e_e.bits.addr, ldq_addr[_ldq_wakeup_e_e_bits_addr_T_1] node _ldq_wakeup_e_e_bits_addr_is_virtual_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = bits(_ldq_wakeup_e_e_bits_addr_is_virtual_T, 4, 0) connect ldq_wakeup_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1] node _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = bits(_ldq_wakeup_e_e_bits_addr_is_uncacheable_T, 4, 0) connect ldq_wakeup_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1] node _ldq_wakeup_e_e_bits_executed_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_executed_T_1 = bits(_ldq_wakeup_e_e_bits_executed_T, 4, 0) connect ldq_wakeup_e_e.bits.executed, ldq_executed[_ldq_wakeup_e_e_bits_executed_T_1] node _ldq_wakeup_e_e_bits_succeeded_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_succeeded_T_1 = bits(_ldq_wakeup_e_e_bits_succeeded_T, 4, 0) connect ldq_wakeup_e_e.bits.succeeded, ldq_succeeded[_ldq_wakeup_e_e_bits_succeeded_T_1] node _ldq_wakeup_e_e_bits_order_fail_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_order_fail_T_1 = bits(_ldq_wakeup_e_e_bits_order_fail_T, 4, 0) connect ldq_wakeup_e_e.bits.order_fail, ldq_order_fail[_ldq_wakeup_e_e_bits_order_fail_T_1] node _ldq_wakeup_e_e_bits_observed_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_observed_T_1 = bits(_ldq_wakeup_e_e_bits_observed_T, 4, 0) connect ldq_wakeup_e_e.bits.observed, ldq_observed[_ldq_wakeup_e_e_bits_observed_T_1] node _ldq_wakeup_e_e_bits_st_dep_mask_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = bits(_ldq_wakeup_e_e_bits_st_dep_mask_T, 4, 0) connect ldq_wakeup_e_e.bits.st_dep_mask, ldq_st_dep_mask[_ldq_wakeup_e_e_bits_st_dep_mask_T_1] node _ldq_wakeup_e_e_bits_ld_byte_mask_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = bits(_ldq_wakeup_e_e_bits_ld_byte_mask_T, 4, 0) connect ldq_wakeup_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1] node _ldq_wakeup_e_e_bits_forward_std_val_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_forward_std_val_T_1 = bits(_ldq_wakeup_e_e_bits_forward_std_val_T, 4, 0) connect ldq_wakeup_e_e.bits.forward_std_val, ldq_forward_std_val[_ldq_wakeup_e_e_bits_forward_std_val_T_1] node _ldq_wakeup_e_e_bits_forward_stq_idx_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = bits(_ldq_wakeup_e_e_bits_forward_stq_idx_T, 4, 0) connect ldq_wakeup_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1] node _ldq_wakeup_e_e_bits_debug_wb_data_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = bits(_ldq_wakeup_e_e_bits_debug_wb_data_T, 4, 0) connect ldq_wakeup_e_e.bits.debug_wb_data, ldq_debug_wb_data[_ldq_wakeup_e_e_bits_debug_wb_data_T_1] wire ldq_wakeup_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_wakeup_e, ldq_wakeup_e_e reg ldq_enq_retry_idx : UInt<5>, clock node _ldq_enq_retry_idx_T = and(ldq_addr[0].valid, ldq_addr_is_virtual[0]) node _ldq_enq_retry_idx_T_1 = neq(UInt<1>(0h0), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_2 = and(_ldq_enq_retry_idx_T, _ldq_enq_retry_idx_T_1) node _ldq_enq_retry_idx_T_3 = and(ldq_addr[1].valid, ldq_addr_is_virtual[1]) node _ldq_enq_retry_idx_T_4 = neq(UInt<1>(0h1), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_5 = and(_ldq_enq_retry_idx_T_3, _ldq_enq_retry_idx_T_4) node _ldq_enq_retry_idx_T_6 = and(ldq_addr[2].valid, ldq_addr_is_virtual[2]) node _ldq_enq_retry_idx_T_7 = neq(UInt<2>(0h2), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_8 = and(_ldq_enq_retry_idx_T_6, _ldq_enq_retry_idx_T_7) node _ldq_enq_retry_idx_T_9 = and(ldq_addr[3].valid, ldq_addr_is_virtual[3]) node _ldq_enq_retry_idx_T_10 = neq(UInt<2>(0h3), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_11 = and(_ldq_enq_retry_idx_T_9, _ldq_enq_retry_idx_T_10) node _ldq_enq_retry_idx_T_12 = and(ldq_addr[4].valid, ldq_addr_is_virtual[4]) node _ldq_enq_retry_idx_T_13 = neq(UInt<3>(0h4), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_14 = and(_ldq_enq_retry_idx_T_12, _ldq_enq_retry_idx_T_13) node _ldq_enq_retry_idx_T_15 = and(ldq_addr[5].valid, ldq_addr_is_virtual[5]) node _ldq_enq_retry_idx_T_16 = neq(UInt<3>(0h5), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_17 = and(_ldq_enq_retry_idx_T_15, _ldq_enq_retry_idx_T_16) node _ldq_enq_retry_idx_T_18 = and(ldq_addr[6].valid, ldq_addr_is_virtual[6]) node _ldq_enq_retry_idx_T_19 = neq(UInt<3>(0h6), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_20 = and(_ldq_enq_retry_idx_T_18, _ldq_enq_retry_idx_T_19) node _ldq_enq_retry_idx_T_21 = and(ldq_addr[7].valid, ldq_addr_is_virtual[7]) node _ldq_enq_retry_idx_T_22 = neq(UInt<3>(0h7), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_23 = and(_ldq_enq_retry_idx_T_21, _ldq_enq_retry_idx_T_22) node _ldq_enq_retry_idx_T_24 = and(ldq_addr[8].valid, ldq_addr_is_virtual[8]) node _ldq_enq_retry_idx_T_25 = neq(UInt<4>(0h8), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_26 = and(_ldq_enq_retry_idx_T_24, _ldq_enq_retry_idx_T_25) node _ldq_enq_retry_idx_T_27 = and(ldq_addr[9].valid, ldq_addr_is_virtual[9]) node _ldq_enq_retry_idx_T_28 = neq(UInt<4>(0h9), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_29 = and(_ldq_enq_retry_idx_T_27, _ldq_enq_retry_idx_T_28) node _ldq_enq_retry_idx_T_30 = and(ldq_addr[10].valid, ldq_addr_is_virtual[10]) node _ldq_enq_retry_idx_T_31 = neq(UInt<4>(0ha), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_32 = and(_ldq_enq_retry_idx_T_30, _ldq_enq_retry_idx_T_31) node _ldq_enq_retry_idx_T_33 = and(ldq_addr[11].valid, ldq_addr_is_virtual[11]) node _ldq_enq_retry_idx_T_34 = neq(UInt<4>(0hb), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_35 = and(_ldq_enq_retry_idx_T_33, _ldq_enq_retry_idx_T_34) node _ldq_enq_retry_idx_T_36 = and(ldq_addr[12].valid, ldq_addr_is_virtual[12]) node _ldq_enq_retry_idx_T_37 = neq(UInt<4>(0hc), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_38 = and(_ldq_enq_retry_idx_T_36, _ldq_enq_retry_idx_T_37) node _ldq_enq_retry_idx_T_39 = and(ldq_addr[13].valid, ldq_addr_is_virtual[13]) node _ldq_enq_retry_idx_T_40 = neq(UInt<4>(0hd), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_41 = and(_ldq_enq_retry_idx_T_39, _ldq_enq_retry_idx_T_40) node _ldq_enq_retry_idx_T_42 = and(ldq_addr[14].valid, ldq_addr_is_virtual[14]) node _ldq_enq_retry_idx_T_43 = neq(UInt<4>(0he), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_44 = and(_ldq_enq_retry_idx_T_42, _ldq_enq_retry_idx_T_43) node _ldq_enq_retry_idx_T_45 = and(ldq_addr[15].valid, ldq_addr_is_virtual[15]) node _ldq_enq_retry_idx_T_46 = neq(UInt<4>(0hf), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_47 = and(_ldq_enq_retry_idx_T_45, _ldq_enq_retry_idx_T_46) node _ldq_enq_retry_idx_T_48 = and(ldq_addr[16].valid, ldq_addr_is_virtual[16]) node _ldq_enq_retry_idx_T_49 = neq(UInt<5>(0h10), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_50 = and(_ldq_enq_retry_idx_T_48, _ldq_enq_retry_idx_T_49) node _ldq_enq_retry_idx_T_51 = and(ldq_addr[17].valid, ldq_addr_is_virtual[17]) node _ldq_enq_retry_idx_T_52 = neq(UInt<5>(0h11), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_53 = and(_ldq_enq_retry_idx_T_51, _ldq_enq_retry_idx_T_52) node _ldq_enq_retry_idx_T_54 = and(ldq_addr[18].valid, ldq_addr_is_virtual[18]) node _ldq_enq_retry_idx_T_55 = neq(UInt<5>(0h12), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_56 = and(_ldq_enq_retry_idx_T_54, _ldq_enq_retry_idx_T_55) node _ldq_enq_retry_idx_T_57 = and(ldq_addr[19].valid, ldq_addr_is_virtual[19]) node _ldq_enq_retry_idx_T_58 = neq(UInt<5>(0h13), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_59 = and(_ldq_enq_retry_idx_T_57, _ldq_enq_retry_idx_T_58) node _ldq_enq_retry_idx_T_60 = and(ldq_addr[20].valid, ldq_addr_is_virtual[20]) node _ldq_enq_retry_idx_T_61 = neq(UInt<5>(0h14), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_62 = and(_ldq_enq_retry_idx_T_60, _ldq_enq_retry_idx_T_61) node _ldq_enq_retry_idx_T_63 = and(ldq_addr[21].valid, ldq_addr_is_virtual[21]) node _ldq_enq_retry_idx_T_64 = neq(UInt<5>(0h15), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_65 = and(_ldq_enq_retry_idx_T_63, _ldq_enq_retry_idx_T_64) node _ldq_enq_retry_idx_T_66 = and(ldq_addr[22].valid, ldq_addr_is_virtual[22]) node _ldq_enq_retry_idx_T_67 = neq(UInt<5>(0h16), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_68 = and(_ldq_enq_retry_idx_T_66, _ldq_enq_retry_idx_T_67) node _ldq_enq_retry_idx_T_69 = and(ldq_addr[23].valid, ldq_addr_is_virtual[23]) node _ldq_enq_retry_idx_T_70 = neq(UInt<5>(0h17), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_71 = and(_ldq_enq_retry_idx_T_69, _ldq_enq_retry_idx_T_70) node _ldq_enq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node ldq_enq_retry_idx_temp_vec_0 = and(_ldq_enq_retry_idx_T_2, _ldq_enq_retry_idx_temp_vec_T) node _ldq_enq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node ldq_enq_retry_idx_temp_vec_1 = and(_ldq_enq_retry_idx_T_5, _ldq_enq_retry_idx_temp_vec_T_1) node _ldq_enq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node ldq_enq_retry_idx_temp_vec_2 = and(_ldq_enq_retry_idx_T_8, _ldq_enq_retry_idx_temp_vec_T_2) node _ldq_enq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node ldq_enq_retry_idx_temp_vec_3 = and(_ldq_enq_retry_idx_T_11, _ldq_enq_retry_idx_temp_vec_T_3) node _ldq_enq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node ldq_enq_retry_idx_temp_vec_4 = and(_ldq_enq_retry_idx_T_14, _ldq_enq_retry_idx_temp_vec_T_4) node _ldq_enq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node ldq_enq_retry_idx_temp_vec_5 = and(_ldq_enq_retry_idx_T_17, _ldq_enq_retry_idx_temp_vec_T_5) node _ldq_enq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node ldq_enq_retry_idx_temp_vec_6 = and(_ldq_enq_retry_idx_T_20, _ldq_enq_retry_idx_temp_vec_T_6) node _ldq_enq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node ldq_enq_retry_idx_temp_vec_7 = and(_ldq_enq_retry_idx_T_23, _ldq_enq_retry_idx_temp_vec_T_7) node _ldq_enq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node ldq_enq_retry_idx_temp_vec_8 = and(_ldq_enq_retry_idx_T_26, _ldq_enq_retry_idx_temp_vec_T_8) node _ldq_enq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node ldq_enq_retry_idx_temp_vec_9 = and(_ldq_enq_retry_idx_T_29, _ldq_enq_retry_idx_temp_vec_T_9) node _ldq_enq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node ldq_enq_retry_idx_temp_vec_10 = and(_ldq_enq_retry_idx_T_32, _ldq_enq_retry_idx_temp_vec_T_10) node _ldq_enq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node ldq_enq_retry_idx_temp_vec_11 = and(_ldq_enq_retry_idx_T_35, _ldq_enq_retry_idx_temp_vec_T_11) node _ldq_enq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node ldq_enq_retry_idx_temp_vec_12 = and(_ldq_enq_retry_idx_T_38, _ldq_enq_retry_idx_temp_vec_T_12) node _ldq_enq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node ldq_enq_retry_idx_temp_vec_13 = and(_ldq_enq_retry_idx_T_41, _ldq_enq_retry_idx_temp_vec_T_13) node _ldq_enq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node ldq_enq_retry_idx_temp_vec_14 = and(_ldq_enq_retry_idx_T_44, _ldq_enq_retry_idx_temp_vec_T_14) node _ldq_enq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node ldq_enq_retry_idx_temp_vec_15 = and(_ldq_enq_retry_idx_T_47, _ldq_enq_retry_idx_temp_vec_T_15) node _ldq_enq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node ldq_enq_retry_idx_temp_vec_16 = and(_ldq_enq_retry_idx_T_50, _ldq_enq_retry_idx_temp_vec_T_16) node _ldq_enq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node ldq_enq_retry_idx_temp_vec_17 = and(_ldq_enq_retry_idx_T_53, _ldq_enq_retry_idx_temp_vec_T_17) node _ldq_enq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node ldq_enq_retry_idx_temp_vec_18 = and(_ldq_enq_retry_idx_T_56, _ldq_enq_retry_idx_temp_vec_T_18) node _ldq_enq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node ldq_enq_retry_idx_temp_vec_19 = and(_ldq_enq_retry_idx_T_59, _ldq_enq_retry_idx_temp_vec_T_19) node _ldq_enq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node ldq_enq_retry_idx_temp_vec_20 = and(_ldq_enq_retry_idx_T_62, _ldq_enq_retry_idx_temp_vec_T_20) node _ldq_enq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node ldq_enq_retry_idx_temp_vec_21 = and(_ldq_enq_retry_idx_T_65, _ldq_enq_retry_idx_temp_vec_T_21) node _ldq_enq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node ldq_enq_retry_idx_temp_vec_22 = and(_ldq_enq_retry_idx_T_68, _ldq_enq_retry_idx_temp_vec_T_22) node _ldq_enq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node ldq_enq_retry_idx_temp_vec_23 = and(_ldq_enq_retry_idx_T_71, _ldq_enq_retry_idx_temp_vec_T_23) node _ldq_enq_retry_idx_idx_T = mux(_ldq_enq_retry_idx_T_68, UInt<6>(0h36), UInt<6>(0h37)) node _ldq_enq_retry_idx_idx_T_1 = mux(_ldq_enq_retry_idx_T_65, UInt<6>(0h35), _ldq_enq_retry_idx_idx_T) node _ldq_enq_retry_idx_idx_T_2 = mux(_ldq_enq_retry_idx_T_62, UInt<6>(0h34), _ldq_enq_retry_idx_idx_T_1) node _ldq_enq_retry_idx_idx_T_3 = mux(_ldq_enq_retry_idx_T_59, UInt<6>(0h33), _ldq_enq_retry_idx_idx_T_2) node _ldq_enq_retry_idx_idx_T_4 = mux(_ldq_enq_retry_idx_T_56, UInt<6>(0h32), _ldq_enq_retry_idx_idx_T_3) node _ldq_enq_retry_idx_idx_T_5 = mux(_ldq_enq_retry_idx_T_53, UInt<6>(0h31), _ldq_enq_retry_idx_idx_T_4) node _ldq_enq_retry_idx_idx_T_6 = mux(_ldq_enq_retry_idx_T_50, UInt<6>(0h30), _ldq_enq_retry_idx_idx_T_5) node _ldq_enq_retry_idx_idx_T_7 = mux(_ldq_enq_retry_idx_T_47, UInt<6>(0h2f), _ldq_enq_retry_idx_idx_T_6) node _ldq_enq_retry_idx_idx_T_8 = mux(_ldq_enq_retry_idx_T_44, UInt<6>(0h2e), _ldq_enq_retry_idx_idx_T_7) node _ldq_enq_retry_idx_idx_T_9 = mux(_ldq_enq_retry_idx_T_41, UInt<6>(0h2d), _ldq_enq_retry_idx_idx_T_8) node _ldq_enq_retry_idx_idx_T_10 = mux(_ldq_enq_retry_idx_T_38, UInt<6>(0h2c), _ldq_enq_retry_idx_idx_T_9) node _ldq_enq_retry_idx_idx_T_11 = mux(_ldq_enq_retry_idx_T_35, UInt<6>(0h2b), _ldq_enq_retry_idx_idx_T_10) node _ldq_enq_retry_idx_idx_T_12 = mux(_ldq_enq_retry_idx_T_32, UInt<6>(0h2a), _ldq_enq_retry_idx_idx_T_11) node _ldq_enq_retry_idx_idx_T_13 = mux(_ldq_enq_retry_idx_T_29, UInt<6>(0h29), _ldq_enq_retry_idx_idx_T_12) node _ldq_enq_retry_idx_idx_T_14 = mux(_ldq_enq_retry_idx_T_26, UInt<6>(0h28), _ldq_enq_retry_idx_idx_T_13) node _ldq_enq_retry_idx_idx_T_15 = mux(_ldq_enq_retry_idx_T_23, UInt<6>(0h27), _ldq_enq_retry_idx_idx_T_14) node _ldq_enq_retry_idx_idx_T_16 = mux(_ldq_enq_retry_idx_T_20, UInt<6>(0h26), _ldq_enq_retry_idx_idx_T_15) node _ldq_enq_retry_idx_idx_T_17 = mux(_ldq_enq_retry_idx_T_17, UInt<6>(0h25), _ldq_enq_retry_idx_idx_T_16) node _ldq_enq_retry_idx_idx_T_18 = mux(_ldq_enq_retry_idx_T_14, UInt<6>(0h24), _ldq_enq_retry_idx_idx_T_17) node _ldq_enq_retry_idx_idx_T_19 = mux(_ldq_enq_retry_idx_T_11, UInt<6>(0h23), _ldq_enq_retry_idx_idx_T_18) node _ldq_enq_retry_idx_idx_T_20 = mux(_ldq_enq_retry_idx_T_8, UInt<6>(0h22), _ldq_enq_retry_idx_idx_T_19) node _ldq_enq_retry_idx_idx_T_21 = mux(_ldq_enq_retry_idx_T_5, UInt<6>(0h21), _ldq_enq_retry_idx_idx_T_20) node _ldq_enq_retry_idx_idx_T_22 = mux(_ldq_enq_retry_idx_T_2, UInt<6>(0h20), _ldq_enq_retry_idx_idx_T_21) node _ldq_enq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_enq_retry_idx_idx_T_22) node _ldq_enq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_enq_retry_idx_idx_T_23) node _ldq_enq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_enq_retry_idx_idx_T_24) node _ldq_enq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_enq_retry_idx_idx_T_25) node _ldq_enq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_enq_retry_idx_idx_T_26) node _ldq_enq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_enq_retry_idx_idx_T_27) node _ldq_enq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_enq_retry_idx_idx_T_28) node _ldq_enq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_enq_retry_idx_idx_T_29) node _ldq_enq_retry_idx_idx_T_31 = mux(ldq_enq_retry_idx_temp_vec_23, UInt<5>(0h17), _ldq_enq_retry_idx_idx_T_30) node _ldq_enq_retry_idx_idx_T_32 = mux(ldq_enq_retry_idx_temp_vec_22, UInt<5>(0h16), _ldq_enq_retry_idx_idx_T_31) node _ldq_enq_retry_idx_idx_T_33 = mux(ldq_enq_retry_idx_temp_vec_21, UInt<5>(0h15), _ldq_enq_retry_idx_idx_T_32) node _ldq_enq_retry_idx_idx_T_34 = mux(ldq_enq_retry_idx_temp_vec_20, UInt<5>(0h14), _ldq_enq_retry_idx_idx_T_33) node _ldq_enq_retry_idx_idx_T_35 = mux(ldq_enq_retry_idx_temp_vec_19, UInt<5>(0h13), _ldq_enq_retry_idx_idx_T_34) node _ldq_enq_retry_idx_idx_T_36 = mux(ldq_enq_retry_idx_temp_vec_18, UInt<5>(0h12), _ldq_enq_retry_idx_idx_T_35) node _ldq_enq_retry_idx_idx_T_37 = mux(ldq_enq_retry_idx_temp_vec_17, UInt<5>(0h11), _ldq_enq_retry_idx_idx_T_36) node _ldq_enq_retry_idx_idx_T_38 = mux(ldq_enq_retry_idx_temp_vec_16, UInt<5>(0h10), _ldq_enq_retry_idx_idx_T_37) node _ldq_enq_retry_idx_idx_T_39 = mux(ldq_enq_retry_idx_temp_vec_15, UInt<4>(0hf), _ldq_enq_retry_idx_idx_T_38) node _ldq_enq_retry_idx_idx_T_40 = mux(ldq_enq_retry_idx_temp_vec_14, UInt<4>(0he), _ldq_enq_retry_idx_idx_T_39) node _ldq_enq_retry_idx_idx_T_41 = mux(ldq_enq_retry_idx_temp_vec_13, UInt<4>(0hd), _ldq_enq_retry_idx_idx_T_40) node _ldq_enq_retry_idx_idx_T_42 = mux(ldq_enq_retry_idx_temp_vec_12, UInt<4>(0hc), _ldq_enq_retry_idx_idx_T_41) node _ldq_enq_retry_idx_idx_T_43 = mux(ldq_enq_retry_idx_temp_vec_11, UInt<4>(0hb), _ldq_enq_retry_idx_idx_T_42) node _ldq_enq_retry_idx_idx_T_44 = mux(ldq_enq_retry_idx_temp_vec_10, UInt<4>(0ha), _ldq_enq_retry_idx_idx_T_43) node _ldq_enq_retry_idx_idx_T_45 = mux(ldq_enq_retry_idx_temp_vec_9, UInt<4>(0h9), _ldq_enq_retry_idx_idx_T_44) node _ldq_enq_retry_idx_idx_T_46 = mux(ldq_enq_retry_idx_temp_vec_8, UInt<4>(0h8), _ldq_enq_retry_idx_idx_T_45) node _ldq_enq_retry_idx_idx_T_47 = mux(ldq_enq_retry_idx_temp_vec_7, UInt<3>(0h7), _ldq_enq_retry_idx_idx_T_46) node _ldq_enq_retry_idx_idx_T_48 = mux(ldq_enq_retry_idx_temp_vec_6, UInt<3>(0h6), _ldq_enq_retry_idx_idx_T_47) node _ldq_enq_retry_idx_idx_T_49 = mux(ldq_enq_retry_idx_temp_vec_5, UInt<3>(0h5), _ldq_enq_retry_idx_idx_T_48) node _ldq_enq_retry_idx_idx_T_50 = mux(ldq_enq_retry_idx_temp_vec_4, UInt<3>(0h4), _ldq_enq_retry_idx_idx_T_49) node _ldq_enq_retry_idx_idx_T_51 = mux(ldq_enq_retry_idx_temp_vec_3, UInt<2>(0h3), _ldq_enq_retry_idx_idx_T_50) node _ldq_enq_retry_idx_idx_T_52 = mux(ldq_enq_retry_idx_temp_vec_2, UInt<2>(0h2), _ldq_enq_retry_idx_idx_T_51) node _ldq_enq_retry_idx_idx_T_53 = mux(ldq_enq_retry_idx_temp_vec_1, UInt<1>(0h1), _ldq_enq_retry_idx_idx_T_52) node ldq_enq_retry_idx_idx = mux(ldq_enq_retry_idx_temp_vec_0, UInt<1>(0h0), _ldq_enq_retry_idx_idx_T_53) node _ldq_enq_retry_idx_T_72 = bits(ldq_enq_retry_idx_idx, 4, 0) connect ldq_enq_retry_idx, _ldq_enq_retry_idx_T_72 wire ldq_enq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_enq_retry_e_e.valid, ldq_valid[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.uop, ldq_uop[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr, ldq_addr[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.executed, ldq_executed[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.succeeded, ldq_succeeded[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.order_fail, ldq_order_fail[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.observed, ldq_observed[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.st_dep_mask, ldq_st_dep_mask[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.forward_std_val, ldq_forward_std_val[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.debug_wb_data, ldq_debug_wb_data[ldq_enq_retry_idx] wire ldq_enq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_enq_retry_e, ldq_enq_retry_e_e reg stq_enq_retry_idx : UInt<5>, clock node _stq_enq_retry_idx_T = and(stq_addr[0].valid, stq_addr_is_virtual[0]) node _stq_enq_retry_idx_T_1 = neq(UInt<1>(0h0), stq_enq_retry_idx) node _stq_enq_retry_idx_T_2 = and(_stq_enq_retry_idx_T, _stq_enq_retry_idx_T_1) node _stq_enq_retry_idx_T_3 = and(stq_addr[1].valid, stq_addr_is_virtual[1]) node _stq_enq_retry_idx_T_4 = neq(UInt<1>(0h1), stq_enq_retry_idx) node _stq_enq_retry_idx_T_5 = and(_stq_enq_retry_idx_T_3, _stq_enq_retry_idx_T_4) node _stq_enq_retry_idx_T_6 = and(stq_addr[2].valid, stq_addr_is_virtual[2]) node _stq_enq_retry_idx_T_7 = neq(UInt<2>(0h2), stq_enq_retry_idx) node _stq_enq_retry_idx_T_8 = and(_stq_enq_retry_idx_T_6, _stq_enq_retry_idx_T_7) node _stq_enq_retry_idx_T_9 = and(stq_addr[3].valid, stq_addr_is_virtual[3]) node _stq_enq_retry_idx_T_10 = neq(UInt<2>(0h3), stq_enq_retry_idx) node _stq_enq_retry_idx_T_11 = and(_stq_enq_retry_idx_T_9, _stq_enq_retry_idx_T_10) node _stq_enq_retry_idx_T_12 = and(stq_addr[4].valid, stq_addr_is_virtual[4]) node _stq_enq_retry_idx_T_13 = neq(UInt<3>(0h4), stq_enq_retry_idx) node _stq_enq_retry_idx_T_14 = and(_stq_enq_retry_idx_T_12, _stq_enq_retry_idx_T_13) node _stq_enq_retry_idx_T_15 = and(stq_addr[5].valid, stq_addr_is_virtual[5]) node _stq_enq_retry_idx_T_16 = neq(UInt<3>(0h5), stq_enq_retry_idx) node _stq_enq_retry_idx_T_17 = and(_stq_enq_retry_idx_T_15, _stq_enq_retry_idx_T_16) node _stq_enq_retry_idx_T_18 = and(stq_addr[6].valid, stq_addr_is_virtual[6]) node _stq_enq_retry_idx_T_19 = neq(UInt<3>(0h6), stq_enq_retry_idx) node _stq_enq_retry_idx_T_20 = and(_stq_enq_retry_idx_T_18, _stq_enq_retry_idx_T_19) node _stq_enq_retry_idx_T_21 = and(stq_addr[7].valid, stq_addr_is_virtual[7]) node _stq_enq_retry_idx_T_22 = neq(UInt<3>(0h7), stq_enq_retry_idx) node _stq_enq_retry_idx_T_23 = and(_stq_enq_retry_idx_T_21, _stq_enq_retry_idx_T_22) node _stq_enq_retry_idx_T_24 = and(stq_addr[8].valid, stq_addr_is_virtual[8]) node _stq_enq_retry_idx_T_25 = neq(UInt<4>(0h8), stq_enq_retry_idx) node _stq_enq_retry_idx_T_26 = and(_stq_enq_retry_idx_T_24, _stq_enq_retry_idx_T_25) node _stq_enq_retry_idx_T_27 = and(stq_addr[9].valid, stq_addr_is_virtual[9]) node _stq_enq_retry_idx_T_28 = neq(UInt<4>(0h9), stq_enq_retry_idx) node _stq_enq_retry_idx_T_29 = and(_stq_enq_retry_idx_T_27, _stq_enq_retry_idx_T_28) node _stq_enq_retry_idx_T_30 = and(stq_addr[10].valid, stq_addr_is_virtual[10]) node _stq_enq_retry_idx_T_31 = neq(UInt<4>(0ha), stq_enq_retry_idx) node _stq_enq_retry_idx_T_32 = and(_stq_enq_retry_idx_T_30, _stq_enq_retry_idx_T_31) node _stq_enq_retry_idx_T_33 = and(stq_addr[11].valid, stq_addr_is_virtual[11]) node _stq_enq_retry_idx_T_34 = neq(UInt<4>(0hb), stq_enq_retry_idx) node _stq_enq_retry_idx_T_35 = and(_stq_enq_retry_idx_T_33, _stq_enq_retry_idx_T_34) node _stq_enq_retry_idx_T_36 = and(stq_addr[12].valid, stq_addr_is_virtual[12]) node _stq_enq_retry_idx_T_37 = neq(UInt<4>(0hc), stq_enq_retry_idx) node _stq_enq_retry_idx_T_38 = and(_stq_enq_retry_idx_T_36, _stq_enq_retry_idx_T_37) node _stq_enq_retry_idx_T_39 = and(stq_addr[13].valid, stq_addr_is_virtual[13]) node _stq_enq_retry_idx_T_40 = neq(UInt<4>(0hd), stq_enq_retry_idx) node _stq_enq_retry_idx_T_41 = and(_stq_enq_retry_idx_T_39, _stq_enq_retry_idx_T_40) node _stq_enq_retry_idx_T_42 = and(stq_addr[14].valid, stq_addr_is_virtual[14]) node _stq_enq_retry_idx_T_43 = neq(UInt<4>(0he), stq_enq_retry_idx) node _stq_enq_retry_idx_T_44 = and(_stq_enq_retry_idx_T_42, _stq_enq_retry_idx_T_43) node _stq_enq_retry_idx_T_45 = and(stq_addr[15].valid, stq_addr_is_virtual[15]) node _stq_enq_retry_idx_T_46 = neq(UInt<4>(0hf), stq_enq_retry_idx) node _stq_enq_retry_idx_T_47 = and(_stq_enq_retry_idx_T_45, _stq_enq_retry_idx_T_46) node _stq_enq_retry_idx_T_48 = and(stq_addr[16].valid, stq_addr_is_virtual[16]) node _stq_enq_retry_idx_T_49 = neq(UInt<5>(0h10), stq_enq_retry_idx) node _stq_enq_retry_idx_T_50 = and(_stq_enq_retry_idx_T_48, _stq_enq_retry_idx_T_49) node _stq_enq_retry_idx_T_51 = and(stq_addr[17].valid, stq_addr_is_virtual[17]) node _stq_enq_retry_idx_T_52 = neq(UInt<5>(0h11), stq_enq_retry_idx) node _stq_enq_retry_idx_T_53 = and(_stq_enq_retry_idx_T_51, _stq_enq_retry_idx_T_52) node _stq_enq_retry_idx_T_54 = and(stq_addr[18].valid, stq_addr_is_virtual[18]) node _stq_enq_retry_idx_T_55 = neq(UInt<5>(0h12), stq_enq_retry_idx) node _stq_enq_retry_idx_T_56 = and(_stq_enq_retry_idx_T_54, _stq_enq_retry_idx_T_55) node _stq_enq_retry_idx_T_57 = and(stq_addr[19].valid, stq_addr_is_virtual[19]) node _stq_enq_retry_idx_T_58 = neq(UInt<5>(0h13), stq_enq_retry_idx) node _stq_enq_retry_idx_T_59 = and(_stq_enq_retry_idx_T_57, _stq_enq_retry_idx_T_58) node _stq_enq_retry_idx_T_60 = and(stq_addr[20].valid, stq_addr_is_virtual[20]) node _stq_enq_retry_idx_T_61 = neq(UInt<5>(0h14), stq_enq_retry_idx) node _stq_enq_retry_idx_T_62 = and(_stq_enq_retry_idx_T_60, _stq_enq_retry_idx_T_61) node _stq_enq_retry_idx_T_63 = and(stq_addr[21].valid, stq_addr_is_virtual[21]) node _stq_enq_retry_idx_T_64 = neq(UInt<5>(0h15), stq_enq_retry_idx) node _stq_enq_retry_idx_T_65 = and(_stq_enq_retry_idx_T_63, _stq_enq_retry_idx_T_64) node _stq_enq_retry_idx_T_66 = and(stq_addr[22].valid, stq_addr_is_virtual[22]) node _stq_enq_retry_idx_T_67 = neq(UInt<5>(0h16), stq_enq_retry_idx) node _stq_enq_retry_idx_T_68 = and(_stq_enq_retry_idx_T_66, _stq_enq_retry_idx_T_67) node _stq_enq_retry_idx_T_69 = and(stq_addr[23].valid, stq_addr_is_virtual[23]) node _stq_enq_retry_idx_T_70 = neq(UInt<5>(0h17), stq_enq_retry_idx) node _stq_enq_retry_idx_T_71 = and(_stq_enq_retry_idx_T_69, _stq_enq_retry_idx_T_70) node _stq_enq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), stq_commit_head) node stq_enq_retry_idx_temp_vec_0 = and(_stq_enq_retry_idx_T_2, _stq_enq_retry_idx_temp_vec_T) node _stq_enq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), stq_commit_head) node stq_enq_retry_idx_temp_vec_1 = and(_stq_enq_retry_idx_T_5, _stq_enq_retry_idx_temp_vec_T_1) node _stq_enq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), stq_commit_head) node stq_enq_retry_idx_temp_vec_2 = and(_stq_enq_retry_idx_T_8, _stq_enq_retry_idx_temp_vec_T_2) node _stq_enq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), stq_commit_head) node stq_enq_retry_idx_temp_vec_3 = and(_stq_enq_retry_idx_T_11, _stq_enq_retry_idx_temp_vec_T_3) node _stq_enq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), stq_commit_head) node stq_enq_retry_idx_temp_vec_4 = and(_stq_enq_retry_idx_T_14, _stq_enq_retry_idx_temp_vec_T_4) node _stq_enq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), stq_commit_head) node stq_enq_retry_idx_temp_vec_5 = and(_stq_enq_retry_idx_T_17, _stq_enq_retry_idx_temp_vec_T_5) node _stq_enq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), stq_commit_head) node stq_enq_retry_idx_temp_vec_6 = and(_stq_enq_retry_idx_T_20, _stq_enq_retry_idx_temp_vec_T_6) node _stq_enq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), stq_commit_head) node stq_enq_retry_idx_temp_vec_7 = and(_stq_enq_retry_idx_T_23, _stq_enq_retry_idx_temp_vec_T_7) node _stq_enq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), stq_commit_head) node stq_enq_retry_idx_temp_vec_8 = and(_stq_enq_retry_idx_T_26, _stq_enq_retry_idx_temp_vec_T_8) node _stq_enq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), stq_commit_head) node stq_enq_retry_idx_temp_vec_9 = and(_stq_enq_retry_idx_T_29, _stq_enq_retry_idx_temp_vec_T_9) node _stq_enq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), stq_commit_head) node stq_enq_retry_idx_temp_vec_10 = and(_stq_enq_retry_idx_T_32, _stq_enq_retry_idx_temp_vec_T_10) node _stq_enq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), stq_commit_head) node stq_enq_retry_idx_temp_vec_11 = and(_stq_enq_retry_idx_T_35, _stq_enq_retry_idx_temp_vec_T_11) node _stq_enq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), stq_commit_head) node stq_enq_retry_idx_temp_vec_12 = and(_stq_enq_retry_idx_T_38, _stq_enq_retry_idx_temp_vec_T_12) node _stq_enq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), stq_commit_head) node stq_enq_retry_idx_temp_vec_13 = and(_stq_enq_retry_idx_T_41, _stq_enq_retry_idx_temp_vec_T_13) node _stq_enq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), stq_commit_head) node stq_enq_retry_idx_temp_vec_14 = and(_stq_enq_retry_idx_T_44, _stq_enq_retry_idx_temp_vec_T_14) node _stq_enq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), stq_commit_head) node stq_enq_retry_idx_temp_vec_15 = and(_stq_enq_retry_idx_T_47, _stq_enq_retry_idx_temp_vec_T_15) node _stq_enq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), stq_commit_head) node stq_enq_retry_idx_temp_vec_16 = and(_stq_enq_retry_idx_T_50, _stq_enq_retry_idx_temp_vec_T_16) node _stq_enq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), stq_commit_head) node stq_enq_retry_idx_temp_vec_17 = and(_stq_enq_retry_idx_T_53, _stq_enq_retry_idx_temp_vec_T_17) node _stq_enq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), stq_commit_head) node stq_enq_retry_idx_temp_vec_18 = and(_stq_enq_retry_idx_T_56, _stq_enq_retry_idx_temp_vec_T_18) node _stq_enq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), stq_commit_head) node stq_enq_retry_idx_temp_vec_19 = and(_stq_enq_retry_idx_T_59, _stq_enq_retry_idx_temp_vec_T_19) node _stq_enq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), stq_commit_head) node stq_enq_retry_idx_temp_vec_20 = and(_stq_enq_retry_idx_T_62, _stq_enq_retry_idx_temp_vec_T_20) node _stq_enq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), stq_commit_head) node stq_enq_retry_idx_temp_vec_21 = and(_stq_enq_retry_idx_T_65, _stq_enq_retry_idx_temp_vec_T_21) node _stq_enq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), stq_commit_head) node stq_enq_retry_idx_temp_vec_22 = and(_stq_enq_retry_idx_T_68, _stq_enq_retry_idx_temp_vec_T_22) node _stq_enq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), stq_commit_head) node stq_enq_retry_idx_temp_vec_23 = and(_stq_enq_retry_idx_T_71, _stq_enq_retry_idx_temp_vec_T_23) node _stq_enq_retry_idx_idx_T = mux(_stq_enq_retry_idx_T_68, UInt<6>(0h36), UInt<6>(0h37)) node _stq_enq_retry_idx_idx_T_1 = mux(_stq_enq_retry_idx_T_65, UInt<6>(0h35), _stq_enq_retry_idx_idx_T) node _stq_enq_retry_idx_idx_T_2 = mux(_stq_enq_retry_idx_T_62, UInt<6>(0h34), _stq_enq_retry_idx_idx_T_1) node _stq_enq_retry_idx_idx_T_3 = mux(_stq_enq_retry_idx_T_59, UInt<6>(0h33), _stq_enq_retry_idx_idx_T_2) node _stq_enq_retry_idx_idx_T_4 = mux(_stq_enq_retry_idx_T_56, UInt<6>(0h32), _stq_enq_retry_idx_idx_T_3) node _stq_enq_retry_idx_idx_T_5 = mux(_stq_enq_retry_idx_T_53, UInt<6>(0h31), _stq_enq_retry_idx_idx_T_4) node _stq_enq_retry_idx_idx_T_6 = mux(_stq_enq_retry_idx_T_50, UInt<6>(0h30), _stq_enq_retry_idx_idx_T_5) node _stq_enq_retry_idx_idx_T_7 = mux(_stq_enq_retry_idx_T_47, UInt<6>(0h2f), _stq_enq_retry_idx_idx_T_6) node _stq_enq_retry_idx_idx_T_8 = mux(_stq_enq_retry_idx_T_44, UInt<6>(0h2e), _stq_enq_retry_idx_idx_T_7) node _stq_enq_retry_idx_idx_T_9 = mux(_stq_enq_retry_idx_T_41, UInt<6>(0h2d), _stq_enq_retry_idx_idx_T_8) node _stq_enq_retry_idx_idx_T_10 = mux(_stq_enq_retry_idx_T_38, UInt<6>(0h2c), _stq_enq_retry_idx_idx_T_9) node _stq_enq_retry_idx_idx_T_11 = mux(_stq_enq_retry_idx_T_35, UInt<6>(0h2b), _stq_enq_retry_idx_idx_T_10) node _stq_enq_retry_idx_idx_T_12 = mux(_stq_enq_retry_idx_T_32, UInt<6>(0h2a), _stq_enq_retry_idx_idx_T_11) node _stq_enq_retry_idx_idx_T_13 = mux(_stq_enq_retry_idx_T_29, UInt<6>(0h29), _stq_enq_retry_idx_idx_T_12) node _stq_enq_retry_idx_idx_T_14 = mux(_stq_enq_retry_idx_T_26, UInt<6>(0h28), _stq_enq_retry_idx_idx_T_13) node _stq_enq_retry_idx_idx_T_15 = mux(_stq_enq_retry_idx_T_23, UInt<6>(0h27), _stq_enq_retry_idx_idx_T_14) node _stq_enq_retry_idx_idx_T_16 = mux(_stq_enq_retry_idx_T_20, UInt<6>(0h26), _stq_enq_retry_idx_idx_T_15) node _stq_enq_retry_idx_idx_T_17 = mux(_stq_enq_retry_idx_T_17, UInt<6>(0h25), _stq_enq_retry_idx_idx_T_16) node _stq_enq_retry_idx_idx_T_18 = mux(_stq_enq_retry_idx_T_14, UInt<6>(0h24), _stq_enq_retry_idx_idx_T_17) node _stq_enq_retry_idx_idx_T_19 = mux(_stq_enq_retry_idx_T_11, UInt<6>(0h23), _stq_enq_retry_idx_idx_T_18) node _stq_enq_retry_idx_idx_T_20 = mux(_stq_enq_retry_idx_T_8, UInt<6>(0h22), _stq_enq_retry_idx_idx_T_19) node _stq_enq_retry_idx_idx_T_21 = mux(_stq_enq_retry_idx_T_5, UInt<6>(0h21), _stq_enq_retry_idx_idx_T_20) node _stq_enq_retry_idx_idx_T_22 = mux(_stq_enq_retry_idx_T_2, UInt<6>(0h20), _stq_enq_retry_idx_idx_T_21) node _stq_enq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _stq_enq_retry_idx_idx_T_22) node _stq_enq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _stq_enq_retry_idx_idx_T_23) node _stq_enq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _stq_enq_retry_idx_idx_T_24) node _stq_enq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _stq_enq_retry_idx_idx_T_25) node _stq_enq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _stq_enq_retry_idx_idx_T_26) node _stq_enq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _stq_enq_retry_idx_idx_T_27) node _stq_enq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _stq_enq_retry_idx_idx_T_28) node _stq_enq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _stq_enq_retry_idx_idx_T_29) node _stq_enq_retry_idx_idx_T_31 = mux(stq_enq_retry_idx_temp_vec_23, UInt<5>(0h17), _stq_enq_retry_idx_idx_T_30) node _stq_enq_retry_idx_idx_T_32 = mux(stq_enq_retry_idx_temp_vec_22, UInt<5>(0h16), _stq_enq_retry_idx_idx_T_31) node _stq_enq_retry_idx_idx_T_33 = mux(stq_enq_retry_idx_temp_vec_21, UInt<5>(0h15), _stq_enq_retry_idx_idx_T_32) node _stq_enq_retry_idx_idx_T_34 = mux(stq_enq_retry_idx_temp_vec_20, UInt<5>(0h14), _stq_enq_retry_idx_idx_T_33) node _stq_enq_retry_idx_idx_T_35 = mux(stq_enq_retry_idx_temp_vec_19, UInt<5>(0h13), _stq_enq_retry_idx_idx_T_34) node _stq_enq_retry_idx_idx_T_36 = mux(stq_enq_retry_idx_temp_vec_18, UInt<5>(0h12), _stq_enq_retry_idx_idx_T_35) node _stq_enq_retry_idx_idx_T_37 = mux(stq_enq_retry_idx_temp_vec_17, UInt<5>(0h11), _stq_enq_retry_idx_idx_T_36) node _stq_enq_retry_idx_idx_T_38 = mux(stq_enq_retry_idx_temp_vec_16, UInt<5>(0h10), _stq_enq_retry_idx_idx_T_37) node _stq_enq_retry_idx_idx_T_39 = mux(stq_enq_retry_idx_temp_vec_15, UInt<4>(0hf), _stq_enq_retry_idx_idx_T_38) node _stq_enq_retry_idx_idx_T_40 = mux(stq_enq_retry_idx_temp_vec_14, UInt<4>(0he), _stq_enq_retry_idx_idx_T_39) node _stq_enq_retry_idx_idx_T_41 = mux(stq_enq_retry_idx_temp_vec_13, UInt<4>(0hd), _stq_enq_retry_idx_idx_T_40) node _stq_enq_retry_idx_idx_T_42 = mux(stq_enq_retry_idx_temp_vec_12, UInt<4>(0hc), _stq_enq_retry_idx_idx_T_41) node _stq_enq_retry_idx_idx_T_43 = mux(stq_enq_retry_idx_temp_vec_11, UInt<4>(0hb), _stq_enq_retry_idx_idx_T_42) node _stq_enq_retry_idx_idx_T_44 = mux(stq_enq_retry_idx_temp_vec_10, UInt<4>(0ha), _stq_enq_retry_idx_idx_T_43) node _stq_enq_retry_idx_idx_T_45 = mux(stq_enq_retry_idx_temp_vec_9, UInt<4>(0h9), _stq_enq_retry_idx_idx_T_44) node _stq_enq_retry_idx_idx_T_46 = mux(stq_enq_retry_idx_temp_vec_8, UInt<4>(0h8), _stq_enq_retry_idx_idx_T_45) node _stq_enq_retry_idx_idx_T_47 = mux(stq_enq_retry_idx_temp_vec_7, UInt<3>(0h7), _stq_enq_retry_idx_idx_T_46) node _stq_enq_retry_idx_idx_T_48 = mux(stq_enq_retry_idx_temp_vec_6, UInt<3>(0h6), _stq_enq_retry_idx_idx_T_47) node _stq_enq_retry_idx_idx_T_49 = mux(stq_enq_retry_idx_temp_vec_5, UInt<3>(0h5), _stq_enq_retry_idx_idx_T_48) node _stq_enq_retry_idx_idx_T_50 = mux(stq_enq_retry_idx_temp_vec_4, UInt<3>(0h4), _stq_enq_retry_idx_idx_T_49) node _stq_enq_retry_idx_idx_T_51 = mux(stq_enq_retry_idx_temp_vec_3, UInt<2>(0h3), _stq_enq_retry_idx_idx_T_50) node _stq_enq_retry_idx_idx_T_52 = mux(stq_enq_retry_idx_temp_vec_2, UInt<2>(0h2), _stq_enq_retry_idx_idx_T_51) node _stq_enq_retry_idx_idx_T_53 = mux(stq_enq_retry_idx_temp_vec_1, UInt<1>(0h1), _stq_enq_retry_idx_idx_T_52) node stq_enq_retry_idx_idx = mux(stq_enq_retry_idx_temp_vec_0, UInt<1>(0h0), _stq_enq_retry_idx_idx_T_53) node _stq_enq_retry_idx_T_72 = bits(stq_enq_retry_idx_idx, 4, 0) connect stq_enq_retry_idx, _stq_enq_retry_idx_T_72 wire stq_enq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_retry_e_e.valid, stq_valid[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.uop, stq_uop[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.addr, stq_addr[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.data, stq_data[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.committed, stq_committed[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.succeeded, stq_succeeded[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.can_execute, stq_can_execute[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.cleared, stq_cleared[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_enq_retry_idx] wire stq_enq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_retry_e, stq_enq_retry_e_e node _can_enq_load_retry_T = and(ldq_enq_retry_e.valid, ldq_enq_retry_e.bits.addr.valid) node can_enq_load_retry = and(_can_enq_load_retry_T, ldq_enq_retry_e.bits.addr_is_virtual) node _can_enq_store_retry_T = and(stq_enq_retry_e.valid, stq_enq_retry_e.bits.addr.valid) node can_enq_store_retry = and(_can_enq_store_retry_T, stq_enq_retry_e.bits.addr_is_virtual) inst retry_queue of BranchKillableQueue_11 connect retry_queue.clock, clock connect retry_queue.reset, reset connect retry_queue.io.brupdate.b2.target_offset, io.core.brupdate.b2.target_offset connect retry_queue.io.brupdate.b2.jalr_target, io.core.brupdate.b2.jalr_target connect retry_queue.io.brupdate.b2.pc_sel, io.core.brupdate.b2.pc_sel connect retry_queue.io.brupdate.b2.cfi_type, io.core.brupdate.b2.cfi_type connect retry_queue.io.brupdate.b2.taken, io.core.brupdate.b2.taken connect retry_queue.io.brupdate.b2.mispredict, io.core.brupdate.b2.mispredict connect retry_queue.io.brupdate.b2.uop.debug_tsrc, io.core.brupdate.b2.uop.debug_tsrc connect retry_queue.io.brupdate.b2.uop.debug_fsrc, io.core.brupdate.b2.uop.debug_fsrc connect retry_queue.io.brupdate.b2.uop.bp_xcpt_if, io.core.brupdate.b2.uop.bp_xcpt_if connect retry_queue.io.brupdate.b2.uop.bp_debug_if, io.core.brupdate.b2.uop.bp_debug_if connect retry_queue.io.brupdate.b2.uop.xcpt_ma_if, io.core.brupdate.b2.uop.xcpt_ma_if connect retry_queue.io.brupdate.b2.uop.xcpt_ae_if, io.core.brupdate.b2.uop.xcpt_ae_if connect retry_queue.io.brupdate.b2.uop.xcpt_pf_if, io.core.brupdate.b2.uop.xcpt_pf_if connect retry_queue.io.brupdate.b2.uop.fp_typ, io.core.brupdate.b2.uop.fp_typ connect retry_queue.io.brupdate.b2.uop.fp_rm, io.core.brupdate.b2.uop.fp_rm connect retry_queue.io.brupdate.b2.uop.fp_val, io.core.brupdate.b2.uop.fp_val connect retry_queue.io.brupdate.b2.uop.fcn_op, io.core.brupdate.b2.uop.fcn_op connect retry_queue.io.brupdate.b2.uop.fcn_dw, io.core.brupdate.b2.uop.fcn_dw connect retry_queue.io.brupdate.b2.uop.frs3_en, io.core.brupdate.b2.uop.frs3_en connect retry_queue.io.brupdate.b2.uop.lrs2_rtype, io.core.brupdate.b2.uop.lrs2_rtype connect retry_queue.io.brupdate.b2.uop.lrs1_rtype, io.core.brupdate.b2.uop.lrs1_rtype connect retry_queue.io.brupdate.b2.uop.dst_rtype, io.core.brupdate.b2.uop.dst_rtype connect retry_queue.io.brupdate.b2.uop.lrs3, io.core.brupdate.b2.uop.lrs3 connect retry_queue.io.brupdate.b2.uop.lrs2, io.core.brupdate.b2.uop.lrs2 connect retry_queue.io.brupdate.b2.uop.lrs1, io.core.brupdate.b2.uop.lrs1 connect retry_queue.io.brupdate.b2.uop.ldst, io.core.brupdate.b2.uop.ldst connect retry_queue.io.brupdate.b2.uop.ldst_is_rs1, io.core.brupdate.b2.uop.ldst_is_rs1 connect retry_queue.io.brupdate.b2.uop.csr_cmd, io.core.brupdate.b2.uop.csr_cmd connect retry_queue.io.brupdate.b2.uop.flush_on_commit, io.core.brupdate.b2.uop.flush_on_commit connect retry_queue.io.brupdate.b2.uop.is_unique, io.core.brupdate.b2.uop.is_unique connect retry_queue.io.brupdate.b2.uop.uses_stq, io.core.brupdate.b2.uop.uses_stq connect retry_queue.io.brupdate.b2.uop.uses_ldq, io.core.brupdate.b2.uop.uses_ldq connect retry_queue.io.brupdate.b2.uop.mem_signed, io.core.brupdate.b2.uop.mem_signed connect retry_queue.io.brupdate.b2.uop.mem_size, io.core.brupdate.b2.uop.mem_size connect retry_queue.io.brupdate.b2.uop.mem_cmd, io.core.brupdate.b2.uop.mem_cmd connect retry_queue.io.brupdate.b2.uop.exc_cause, io.core.brupdate.b2.uop.exc_cause connect retry_queue.io.brupdate.b2.uop.exception, io.core.brupdate.b2.uop.exception connect retry_queue.io.brupdate.b2.uop.stale_pdst, io.core.brupdate.b2.uop.stale_pdst connect retry_queue.io.brupdate.b2.uop.ppred_busy, io.core.brupdate.b2.uop.ppred_busy connect retry_queue.io.brupdate.b2.uop.prs3_busy, io.core.brupdate.b2.uop.prs3_busy connect retry_queue.io.brupdate.b2.uop.prs2_busy, io.core.brupdate.b2.uop.prs2_busy connect retry_queue.io.brupdate.b2.uop.prs1_busy, io.core.brupdate.b2.uop.prs1_busy connect retry_queue.io.brupdate.b2.uop.ppred, io.core.brupdate.b2.uop.ppred connect retry_queue.io.brupdate.b2.uop.prs3, io.core.brupdate.b2.uop.prs3 connect retry_queue.io.brupdate.b2.uop.prs2, io.core.brupdate.b2.uop.prs2 connect retry_queue.io.brupdate.b2.uop.prs1, io.core.brupdate.b2.uop.prs1 connect retry_queue.io.brupdate.b2.uop.pdst, io.core.brupdate.b2.uop.pdst connect retry_queue.io.brupdate.b2.uop.rxq_idx, io.core.brupdate.b2.uop.rxq_idx connect retry_queue.io.brupdate.b2.uop.stq_idx, io.core.brupdate.b2.uop.stq_idx connect retry_queue.io.brupdate.b2.uop.ldq_idx, io.core.brupdate.b2.uop.ldq_idx connect retry_queue.io.brupdate.b2.uop.rob_idx, io.core.brupdate.b2.uop.rob_idx connect retry_queue.io.brupdate.b2.uop.fp_ctrl.vec, io.core.brupdate.b2.uop.fp_ctrl.vec connect retry_queue.io.brupdate.b2.uop.fp_ctrl.wflags, io.core.brupdate.b2.uop.fp_ctrl.wflags connect retry_queue.io.brupdate.b2.uop.fp_ctrl.sqrt, io.core.brupdate.b2.uop.fp_ctrl.sqrt connect retry_queue.io.brupdate.b2.uop.fp_ctrl.div, io.core.brupdate.b2.uop.fp_ctrl.div connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fma, io.core.brupdate.b2.uop.fp_ctrl.fma connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.core.brupdate.b2.uop.fp_ctrl.fastpipe connect retry_queue.io.brupdate.b2.uop.fp_ctrl.toint, io.core.brupdate.b2.uop.fp_ctrl.toint connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fromint, io.core.brupdate.b2.uop.fp_ctrl.fromint connect retry_queue.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.core.brupdate.b2.uop.fp_ctrl.typeTagOut connect retry_queue.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.core.brupdate.b2.uop.fp_ctrl.typeTagIn connect retry_queue.io.brupdate.b2.uop.fp_ctrl.swap23, io.core.brupdate.b2.uop.fp_ctrl.swap23 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.swap12, io.core.brupdate.b2.uop.fp_ctrl.swap12 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren3, io.core.brupdate.b2.uop.fp_ctrl.ren3 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren2, io.core.brupdate.b2.uop.fp_ctrl.ren2 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren1, io.core.brupdate.b2.uop.fp_ctrl.ren1 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.wen, io.core.brupdate.b2.uop.fp_ctrl.wen connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ldst, io.core.brupdate.b2.uop.fp_ctrl.ldst connect retry_queue.io.brupdate.b2.uop.op2_sel, io.core.brupdate.b2.uop.op2_sel connect retry_queue.io.brupdate.b2.uop.op1_sel, io.core.brupdate.b2.uop.op1_sel connect retry_queue.io.brupdate.b2.uop.imm_packed, io.core.brupdate.b2.uop.imm_packed connect retry_queue.io.brupdate.b2.uop.pimm, io.core.brupdate.b2.uop.pimm connect retry_queue.io.brupdate.b2.uop.imm_sel, io.core.brupdate.b2.uop.imm_sel connect retry_queue.io.brupdate.b2.uop.imm_rename, io.core.brupdate.b2.uop.imm_rename connect retry_queue.io.brupdate.b2.uop.taken, io.core.brupdate.b2.uop.taken connect retry_queue.io.brupdate.b2.uop.pc_lob, io.core.brupdate.b2.uop.pc_lob connect retry_queue.io.brupdate.b2.uop.edge_inst, io.core.brupdate.b2.uop.edge_inst connect retry_queue.io.brupdate.b2.uop.ftq_idx, io.core.brupdate.b2.uop.ftq_idx connect retry_queue.io.brupdate.b2.uop.is_mov, io.core.brupdate.b2.uop.is_mov connect retry_queue.io.brupdate.b2.uop.is_rocc, io.core.brupdate.b2.uop.is_rocc connect retry_queue.io.brupdate.b2.uop.is_sys_pc2epc, io.core.brupdate.b2.uop.is_sys_pc2epc connect retry_queue.io.brupdate.b2.uop.is_eret, io.core.brupdate.b2.uop.is_eret connect retry_queue.io.brupdate.b2.uop.is_amo, io.core.brupdate.b2.uop.is_amo connect retry_queue.io.brupdate.b2.uop.is_sfence, io.core.brupdate.b2.uop.is_sfence connect retry_queue.io.brupdate.b2.uop.is_fencei, io.core.brupdate.b2.uop.is_fencei connect retry_queue.io.brupdate.b2.uop.is_fence, io.core.brupdate.b2.uop.is_fence connect retry_queue.io.brupdate.b2.uop.is_sfb, io.core.brupdate.b2.uop.is_sfb connect retry_queue.io.brupdate.b2.uop.br_type, io.core.brupdate.b2.uop.br_type connect retry_queue.io.brupdate.b2.uop.br_tag, io.core.brupdate.b2.uop.br_tag connect retry_queue.io.brupdate.b2.uop.br_mask, io.core.brupdate.b2.uop.br_mask connect retry_queue.io.brupdate.b2.uop.dis_col_sel, io.core.brupdate.b2.uop.dis_col_sel connect retry_queue.io.brupdate.b2.uop.iw_p3_bypass_hint, io.core.brupdate.b2.uop.iw_p3_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p2_bypass_hint, io.core.brupdate.b2.uop.iw_p2_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p1_bypass_hint, io.core.brupdate.b2.uop.iw_p1_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p2_speculative_child, io.core.brupdate.b2.uop.iw_p2_speculative_child connect retry_queue.io.brupdate.b2.uop.iw_p1_speculative_child, io.core.brupdate.b2.uop.iw_p1_speculative_child connect retry_queue.io.brupdate.b2.uop.iw_issued_partial_dgen, io.core.brupdate.b2.uop.iw_issued_partial_dgen connect retry_queue.io.brupdate.b2.uop.iw_issued_partial_agen, io.core.brupdate.b2.uop.iw_issued_partial_agen connect retry_queue.io.brupdate.b2.uop.iw_issued, io.core.brupdate.b2.uop.iw_issued connect retry_queue.io.brupdate.b2.uop.fu_code[0], io.core.brupdate.b2.uop.fu_code[0] connect retry_queue.io.brupdate.b2.uop.fu_code[1], io.core.brupdate.b2.uop.fu_code[1] connect retry_queue.io.brupdate.b2.uop.fu_code[2], io.core.brupdate.b2.uop.fu_code[2] connect retry_queue.io.brupdate.b2.uop.fu_code[3], io.core.brupdate.b2.uop.fu_code[3] connect retry_queue.io.brupdate.b2.uop.fu_code[4], io.core.brupdate.b2.uop.fu_code[4] connect retry_queue.io.brupdate.b2.uop.fu_code[5], io.core.brupdate.b2.uop.fu_code[5] connect retry_queue.io.brupdate.b2.uop.fu_code[6], io.core.brupdate.b2.uop.fu_code[6] connect retry_queue.io.brupdate.b2.uop.fu_code[7], io.core.brupdate.b2.uop.fu_code[7] connect retry_queue.io.brupdate.b2.uop.fu_code[8], io.core.brupdate.b2.uop.fu_code[8] connect retry_queue.io.brupdate.b2.uop.fu_code[9], io.core.brupdate.b2.uop.fu_code[9] connect retry_queue.io.brupdate.b2.uop.iq_type[0], io.core.brupdate.b2.uop.iq_type[0] connect retry_queue.io.brupdate.b2.uop.iq_type[1], io.core.brupdate.b2.uop.iq_type[1] connect retry_queue.io.brupdate.b2.uop.iq_type[2], io.core.brupdate.b2.uop.iq_type[2] connect retry_queue.io.brupdate.b2.uop.iq_type[3], io.core.brupdate.b2.uop.iq_type[3] connect retry_queue.io.brupdate.b2.uop.debug_pc, io.core.brupdate.b2.uop.debug_pc connect retry_queue.io.brupdate.b2.uop.is_rvc, io.core.brupdate.b2.uop.is_rvc connect retry_queue.io.brupdate.b2.uop.debug_inst, io.core.brupdate.b2.uop.debug_inst connect retry_queue.io.brupdate.b2.uop.inst, io.core.brupdate.b2.uop.inst connect retry_queue.io.brupdate.b1.mispredict_mask, io.core.brupdate.b1.mispredict_mask connect retry_queue.io.brupdate.b1.resolve_mask, io.core.brupdate.b1.resolve_mask connect retry_queue.io.flush, io.core.exception node _retry_queue_io_enq_valid_T = or(can_enq_store_retry, can_enq_load_retry) connect retry_queue.io.enq.valid, _retry_queue_io_enq_valid_T invalidate retry_queue.io.enq.bits.data invalidate retry_queue.io.enq.bits.uop.debug_tsrc invalidate retry_queue.io.enq.bits.uop.debug_fsrc invalidate retry_queue.io.enq.bits.uop.bp_xcpt_if invalidate retry_queue.io.enq.bits.uop.bp_debug_if invalidate retry_queue.io.enq.bits.uop.xcpt_ma_if invalidate retry_queue.io.enq.bits.uop.xcpt_ae_if invalidate retry_queue.io.enq.bits.uop.xcpt_pf_if invalidate retry_queue.io.enq.bits.uop.fp_typ invalidate retry_queue.io.enq.bits.uop.fp_rm invalidate retry_queue.io.enq.bits.uop.fp_val invalidate retry_queue.io.enq.bits.uop.fcn_op invalidate retry_queue.io.enq.bits.uop.fcn_dw invalidate retry_queue.io.enq.bits.uop.frs3_en invalidate retry_queue.io.enq.bits.uop.lrs2_rtype invalidate retry_queue.io.enq.bits.uop.lrs1_rtype invalidate retry_queue.io.enq.bits.uop.dst_rtype invalidate retry_queue.io.enq.bits.uop.lrs3 invalidate retry_queue.io.enq.bits.uop.lrs2 invalidate retry_queue.io.enq.bits.uop.lrs1 invalidate retry_queue.io.enq.bits.uop.ldst invalidate retry_queue.io.enq.bits.uop.ldst_is_rs1 invalidate retry_queue.io.enq.bits.uop.csr_cmd invalidate retry_queue.io.enq.bits.uop.flush_on_commit invalidate retry_queue.io.enq.bits.uop.is_unique invalidate retry_queue.io.enq.bits.uop.uses_stq invalidate retry_queue.io.enq.bits.uop.uses_ldq invalidate retry_queue.io.enq.bits.uop.mem_signed invalidate retry_queue.io.enq.bits.uop.mem_size invalidate retry_queue.io.enq.bits.uop.mem_cmd invalidate retry_queue.io.enq.bits.uop.exc_cause invalidate retry_queue.io.enq.bits.uop.exception invalidate retry_queue.io.enq.bits.uop.stale_pdst invalidate retry_queue.io.enq.bits.uop.ppred_busy invalidate retry_queue.io.enq.bits.uop.prs3_busy invalidate retry_queue.io.enq.bits.uop.prs2_busy invalidate retry_queue.io.enq.bits.uop.prs1_busy invalidate retry_queue.io.enq.bits.uop.ppred invalidate retry_queue.io.enq.bits.uop.prs3 invalidate retry_queue.io.enq.bits.uop.prs2 invalidate retry_queue.io.enq.bits.uop.prs1 invalidate retry_queue.io.enq.bits.uop.pdst invalidate retry_queue.io.enq.bits.uop.rxq_idx invalidate retry_queue.io.enq.bits.uop.stq_idx invalidate retry_queue.io.enq.bits.uop.ldq_idx invalidate retry_queue.io.enq.bits.uop.rob_idx invalidate retry_queue.io.enq.bits.uop.fp_ctrl.vec invalidate retry_queue.io.enq.bits.uop.fp_ctrl.wflags invalidate retry_queue.io.enq.bits.uop.fp_ctrl.sqrt invalidate retry_queue.io.enq.bits.uop.fp_ctrl.div invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fma invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fastpipe invalidate retry_queue.io.enq.bits.uop.fp_ctrl.toint invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fromint invalidate retry_queue.io.enq.bits.uop.fp_ctrl.typeTagOut invalidate retry_queue.io.enq.bits.uop.fp_ctrl.typeTagIn invalidate retry_queue.io.enq.bits.uop.fp_ctrl.swap23 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.swap12 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren3 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren2 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren1 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.wen invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ldst invalidate retry_queue.io.enq.bits.uop.op2_sel invalidate retry_queue.io.enq.bits.uop.op1_sel invalidate retry_queue.io.enq.bits.uop.imm_packed invalidate retry_queue.io.enq.bits.uop.pimm invalidate retry_queue.io.enq.bits.uop.imm_sel invalidate retry_queue.io.enq.bits.uop.imm_rename invalidate retry_queue.io.enq.bits.uop.taken invalidate retry_queue.io.enq.bits.uop.pc_lob invalidate retry_queue.io.enq.bits.uop.edge_inst invalidate retry_queue.io.enq.bits.uop.ftq_idx invalidate retry_queue.io.enq.bits.uop.is_mov invalidate retry_queue.io.enq.bits.uop.is_rocc invalidate retry_queue.io.enq.bits.uop.is_sys_pc2epc invalidate retry_queue.io.enq.bits.uop.is_eret invalidate retry_queue.io.enq.bits.uop.is_amo invalidate retry_queue.io.enq.bits.uop.is_sfence invalidate retry_queue.io.enq.bits.uop.is_fencei invalidate retry_queue.io.enq.bits.uop.is_fence invalidate retry_queue.io.enq.bits.uop.is_sfb invalidate retry_queue.io.enq.bits.uop.br_type invalidate retry_queue.io.enq.bits.uop.br_tag invalidate retry_queue.io.enq.bits.uop.br_mask invalidate retry_queue.io.enq.bits.uop.dis_col_sel invalidate retry_queue.io.enq.bits.uop.iw_p3_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p2_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p1_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p2_speculative_child invalidate retry_queue.io.enq.bits.uop.iw_p1_speculative_child invalidate retry_queue.io.enq.bits.uop.iw_issued_partial_dgen invalidate retry_queue.io.enq.bits.uop.iw_issued_partial_agen invalidate retry_queue.io.enq.bits.uop.iw_issued invalidate retry_queue.io.enq.bits.uop.fu_code[0] invalidate retry_queue.io.enq.bits.uop.fu_code[1] invalidate retry_queue.io.enq.bits.uop.fu_code[2] invalidate retry_queue.io.enq.bits.uop.fu_code[3] invalidate retry_queue.io.enq.bits.uop.fu_code[4] invalidate retry_queue.io.enq.bits.uop.fu_code[5] invalidate retry_queue.io.enq.bits.uop.fu_code[6] invalidate retry_queue.io.enq.bits.uop.fu_code[7] invalidate retry_queue.io.enq.bits.uop.fu_code[8] invalidate retry_queue.io.enq.bits.uop.fu_code[9] invalidate retry_queue.io.enq.bits.uop.iq_type[0] invalidate retry_queue.io.enq.bits.uop.iq_type[1] invalidate retry_queue.io.enq.bits.uop.iq_type[2] invalidate retry_queue.io.enq.bits.uop.iq_type[3] invalidate retry_queue.io.enq.bits.uop.debug_pc invalidate retry_queue.io.enq.bits.uop.is_rvc invalidate retry_queue.io.enq.bits.uop.debug_inst invalidate retry_queue.io.enq.bits.uop.inst node _retry_queue_io_enq_bits_data_T = mux(can_enq_store_retry, stq_enq_retry_e.bits.addr.bits, ldq_enq_retry_e.bits.addr.bits) connect retry_queue.io.enq.bits.data, _retry_queue_io_enq_bits_data_T node _retry_queue_io_enq_bits_uop_T = mux(can_enq_store_retry, stq_enq_retry_e.bits.uop, ldq_enq_retry_e.bits.uop) connect retry_queue.io.enq.bits.uop.debug_tsrc, _retry_queue_io_enq_bits_uop_T.debug_tsrc connect retry_queue.io.enq.bits.uop.debug_fsrc, _retry_queue_io_enq_bits_uop_T.debug_fsrc connect retry_queue.io.enq.bits.uop.bp_xcpt_if, _retry_queue_io_enq_bits_uop_T.bp_xcpt_if connect retry_queue.io.enq.bits.uop.bp_debug_if, _retry_queue_io_enq_bits_uop_T.bp_debug_if connect retry_queue.io.enq.bits.uop.xcpt_ma_if, _retry_queue_io_enq_bits_uop_T.xcpt_ma_if connect retry_queue.io.enq.bits.uop.xcpt_ae_if, _retry_queue_io_enq_bits_uop_T.xcpt_ae_if connect retry_queue.io.enq.bits.uop.xcpt_pf_if, _retry_queue_io_enq_bits_uop_T.xcpt_pf_if connect retry_queue.io.enq.bits.uop.fp_typ, _retry_queue_io_enq_bits_uop_T.fp_typ connect retry_queue.io.enq.bits.uop.fp_rm, _retry_queue_io_enq_bits_uop_T.fp_rm connect retry_queue.io.enq.bits.uop.fp_val, _retry_queue_io_enq_bits_uop_T.fp_val connect retry_queue.io.enq.bits.uop.fcn_op, _retry_queue_io_enq_bits_uop_T.fcn_op connect retry_queue.io.enq.bits.uop.fcn_dw, _retry_queue_io_enq_bits_uop_T.fcn_dw connect retry_queue.io.enq.bits.uop.frs3_en, _retry_queue_io_enq_bits_uop_T.frs3_en connect retry_queue.io.enq.bits.uop.lrs2_rtype, _retry_queue_io_enq_bits_uop_T.lrs2_rtype connect retry_queue.io.enq.bits.uop.lrs1_rtype, _retry_queue_io_enq_bits_uop_T.lrs1_rtype connect retry_queue.io.enq.bits.uop.dst_rtype, _retry_queue_io_enq_bits_uop_T.dst_rtype connect retry_queue.io.enq.bits.uop.lrs3, _retry_queue_io_enq_bits_uop_T.lrs3 connect retry_queue.io.enq.bits.uop.lrs2, _retry_queue_io_enq_bits_uop_T.lrs2 connect retry_queue.io.enq.bits.uop.lrs1, _retry_queue_io_enq_bits_uop_T.lrs1 connect retry_queue.io.enq.bits.uop.ldst, _retry_queue_io_enq_bits_uop_T.ldst connect retry_queue.io.enq.bits.uop.ldst_is_rs1, _retry_queue_io_enq_bits_uop_T.ldst_is_rs1 connect retry_queue.io.enq.bits.uop.csr_cmd, _retry_queue_io_enq_bits_uop_T.csr_cmd connect retry_queue.io.enq.bits.uop.flush_on_commit, _retry_queue_io_enq_bits_uop_T.flush_on_commit connect retry_queue.io.enq.bits.uop.is_unique, _retry_queue_io_enq_bits_uop_T.is_unique connect retry_queue.io.enq.bits.uop.uses_stq, _retry_queue_io_enq_bits_uop_T.uses_stq connect retry_queue.io.enq.bits.uop.uses_ldq, _retry_queue_io_enq_bits_uop_T.uses_ldq connect retry_queue.io.enq.bits.uop.mem_signed, _retry_queue_io_enq_bits_uop_T.mem_signed connect retry_queue.io.enq.bits.uop.mem_size, _retry_queue_io_enq_bits_uop_T.mem_size connect retry_queue.io.enq.bits.uop.mem_cmd, _retry_queue_io_enq_bits_uop_T.mem_cmd connect retry_queue.io.enq.bits.uop.exc_cause, _retry_queue_io_enq_bits_uop_T.exc_cause connect retry_queue.io.enq.bits.uop.exception, _retry_queue_io_enq_bits_uop_T.exception connect retry_queue.io.enq.bits.uop.stale_pdst, _retry_queue_io_enq_bits_uop_T.stale_pdst connect retry_queue.io.enq.bits.uop.ppred_busy, _retry_queue_io_enq_bits_uop_T.ppred_busy connect retry_queue.io.enq.bits.uop.prs3_busy, _retry_queue_io_enq_bits_uop_T.prs3_busy connect retry_queue.io.enq.bits.uop.prs2_busy, _retry_queue_io_enq_bits_uop_T.prs2_busy connect retry_queue.io.enq.bits.uop.prs1_busy, _retry_queue_io_enq_bits_uop_T.prs1_busy connect retry_queue.io.enq.bits.uop.ppred, _retry_queue_io_enq_bits_uop_T.ppred connect retry_queue.io.enq.bits.uop.prs3, _retry_queue_io_enq_bits_uop_T.prs3 connect retry_queue.io.enq.bits.uop.prs2, _retry_queue_io_enq_bits_uop_T.prs2 connect retry_queue.io.enq.bits.uop.prs1, _retry_queue_io_enq_bits_uop_T.prs1 connect retry_queue.io.enq.bits.uop.pdst, _retry_queue_io_enq_bits_uop_T.pdst connect retry_queue.io.enq.bits.uop.rxq_idx, _retry_queue_io_enq_bits_uop_T.rxq_idx connect retry_queue.io.enq.bits.uop.stq_idx, _retry_queue_io_enq_bits_uop_T.stq_idx connect retry_queue.io.enq.bits.uop.ldq_idx, _retry_queue_io_enq_bits_uop_T.ldq_idx connect retry_queue.io.enq.bits.uop.rob_idx, _retry_queue_io_enq_bits_uop_T.rob_idx connect retry_queue.io.enq.bits.uop.fp_ctrl.vec, _retry_queue_io_enq_bits_uop_T.fp_ctrl.vec connect retry_queue.io.enq.bits.uop.fp_ctrl.wflags, _retry_queue_io_enq_bits_uop_T.fp_ctrl.wflags connect retry_queue.io.enq.bits.uop.fp_ctrl.sqrt, _retry_queue_io_enq_bits_uop_T.fp_ctrl.sqrt connect retry_queue.io.enq.bits.uop.fp_ctrl.div, _retry_queue_io_enq_bits_uop_T.fp_ctrl.div connect retry_queue.io.enq.bits.uop.fp_ctrl.fma, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fma connect retry_queue.io.enq.bits.uop.fp_ctrl.fastpipe, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fastpipe connect retry_queue.io.enq.bits.uop.fp_ctrl.toint, _retry_queue_io_enq_bits_uop_T.fp_ctrl.toint connect retry_queue.io.enq.bits.uop.fp_ctrl.fromint, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fromint connect retry_queue.io.enq.bits.uop.fp_ctrl.typeTagOut, _retry_queue_io_enq_bits_uop_T.fp_ctrl.typeTagOut connect retry_queue.io.enq.bits.uop.fp_ctrl.typeTagIn, _retry_queue_io_enq_bits_uop_T.fp_ctrl.typeTagIn connect retry_queue.io.enq.bits.uop.fp_ctrl.swap23, _retry_queue_io_enq_bits_uop_T.fp_ctrl.swap23 connect retry_queue.io.enq.bits.uop.fp_ctrl.swap12, _retry_queue_io_enq_bits_uop_T.fp_ctrl.swap12 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren3, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren3 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren2, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren2 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren1, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren1 connect retry_queue.io.enq.bits.uop.fp_ctrl.wen, _retry_queue_io_enq_bits_uop_T.fp_ctrl.wen connect retry_queue.io.enq.bits.uop.fp_ctrl.ldst, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ldst connect retry_queue.io.enq.bits.uop.op2_sel, _retry_queue_io_enq_bits_uop_T.op2_sel connect retry_queue.io.enq.bits.uop.op1_sel, _retry_queue_io_enq_bits_uop_T.op1_sel connect retry_queue.io.enq.bits.uop.imm_packed, _retry_queue_io_enq_bits_uop_T.imm_packed connect retry_queue.io.enq.bits.uop.pimm, _retry_queue_io_enq_bits_uop_T.pimm connect retry_queue.io.enq.bits.uop.imm_sel, _retry_queue_io_enq_bits_uop_T.imm_sel connect retry_queue.io.enq.bits.uop.imm_rename, _retry_queue_io_enq_bits_uop_T.imm_rename connect retry_queue.io.enq.bits.uop.taken, _retry_queue_io_enq_bits_uop_T.taken connect retry_queue.io.enq.bits.uop.pc_lob, _retry_queue_io_enq_bits_uop_T.pc_lob connect retry_queue.io.enq.bits.uop.edge_inst, _retry_queue_io_enq_bits_uop_T.edge_inst connect retry_queue.io.enq.bits.uop.ftq_idx, _retry_queue_io_enq_bits_uop_T.ftq_idx connect retry_queue.io.enq.bits.uop.is_mov, _retry_queue_io_enq_bits_uop_T.is_mov connect retry_queue.io.enq.bits.uop.is_rocc, _retry_queue_io_enq_bits_uop_T.is_rocc connect retry_queue.io.enq.bits.uop.is_sys_pc2epc, _retry_queue_io_enq_bits_uop_T.is_sys_pc2epc connect retry_queue.io.enq.bits.uop.is_eret, _retry_queue_io_enq_bits_uop_T.is_eret connect retry_queue.io.enq.bits.uop.is_amo, _retry_queue_io_enq_bits_uop_T.is_amo connect retry_queue.io.enq.bits.uop.is_sfence, _retry_queue_io_enq_bits_uop_T.is_sfence connect retry_queue.io.enq.bits.uop.is_fencei, _retry_queue_io_enq_bits_uop_T.is_fencei connect retry_queue.io.enq.bits.uop.is_fence, _retry_queue_io_enq_bits_uop_T.is_fence connect retry_queue.io.enq.bits.uop.is_sfb, _retry_queue_io_enq_bits_uop_T.is_sfb connect retry_queue.io.enq.bits.uop.br_type, _retry_queue_io_enq_bits_uop_T.br_type connect retry_queue.io.enq.bits.uop.br_tag, _retry_queue_io_enq_bits_uop_T.br_tag connect retry_queue.io.enq.bits.uop.br_mask, _retry_queue_io_enq_bits_uop_T.br_mask connect retry_queue.io.enq.bits.uop.dis_col_sel, _retry_queue_io_enq_bits_uop_T.dis_col_sel connect retry_queue.io.enq.bits.uop.iw_p3_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p3_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p2_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p2_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p1_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p1_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p2_speculative_child, _retry_queue_io_enq_bits_uop_T.iw_p2_speculative_child connect retry_queue.io.enq.bits.uop.iw_p1_speculative_child, _retry_queue_io_enq_bits_uop_T.iw_p1_speculative_child connect retry_queue.io.enq.bits.uop.iw_issued_partial_dgen, _retry_queue_io_enq_bits_uop_T.iw_issued_partial_dgen connect retry_queue.io.enq.bits.uop.iw_issued_partial_agen, _retry_queue_io_enq_bits_uop_T.iw_issued_partial_agen connect retry_queue.io.enq.bits.uop.iw_issued, _retry_queue_io_enq_bits_uop_T.iw_issued connect retry_queue.io.enq.bits.uop.fu_code[0], _retry_queue_io_enq_bits_uop_T.fu_code[0] connect retry_queue.io.enq.bits.uop.fu_code[1], _retry_queue_io_enq_bits_uop_T.fu_code[1] connect retry_queue.io.enq.bits.uop.fu_code[2], _retry_queue_io_enq_bits_uop_T.fu_code[2] connect retry_queue.io.enq.bits.uop.fu_code[3], _retry_queue_io_enq_bits_uop_T.fu_code[3] connect retry_queue.io.enq.bits.uop.fu_code[4], _retry_queue_io_enq_bits_uop_T.fu_code[4] connect retry_queue.io.enq.bits.uop.fu_code[5], _retry_queue_io_enq_bits_uop_T.fu_code[5] connect retry_queue.io.enq.bits.uop.fu_code[6], _retry_queue_io_enq_bits_uop_T.fu_code[6] connect retry_queue.io.enq.bits.uop.fu_code[7], _retry_queue_io_enq_bits_uop_T.fu_code[7] connect retry_queue.io.enq.bits.uop.fu_code[8], _retry_queue_io_enq_bits_uop_T.fu_code[8] connect retry_queue.io.enq.bits.uop.fu_code[9], _retry_queue_io_enq_bits_uop_T.fu_code[9] connect retry_queue.io.enq.bits.uop.iq_type[0], _retry_queue_io_enq_bits_uop_T.iq_type[0] connect retry_queue.io.enq.bits.uop.iq_type[1], _retry_queue_io_enq_bits_uop_T.iq_type[1] connect retry_queue.io.enq.bits.uop.iq_type[2], _retry_queue_io_enq_bits_uop_T.iq_type[2] connect retry_queue.io.enq.bits.uop.iq_type[3], _retry_queue_io_enq_bits_uop_T.iq_type[3] connect retry_queue.io.enq.bits.uop.debug_pc, _retry_queue_io_enq_bits_uop_T.debug_pc connect retry_queue.io.enq.bits.uop.is_rvc, _retry_queue_io_enq_bits_uop_T.is_rvc connect retry_queue.io.enq.bits.uop.debug_inst, _retry_queue_io_enq_bits_uop_T.debug_inst connect retry_queue.io.enq.bits.uop.inst, _retry_queue_io_enq_bits_uop_T.inst node _retry_queue_io_enq_bits_uop_uses_ldq_T = eq(can_enq_store_retry, UInt<1>(0h0)) node _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = and(can_enq_load_retry, _retry_queue_io_enq_bits_uop_uses_ldq_T) connect retry_queue.io.enq.bits.uop.uses_ldq, _retry_queue_io_enq_bits_uop_uses_ldq_T_1 connect retry_queue.io.enq.bits.uop.ldq_idx, ldq_enq_retry_idx connect retry_queue.io.enq.bits.uop.uses_stq, can_enq_store_retry connect retry_queue.io.enq.bits.uop.stq_idx, stq_enq_retry_idx node _T_141 = and(retry_queue.io.enq.ready, retry_queue.io.enq.valid) node _T_142 = and(can_enq_store_retry, _T_141) when _T_142 : connect stq_addr[stq_enq_retry_idx].valid, UInt<1>(0h0) else : node _T_143 = and(retry_queue.io.enq.ready, retry_queue.io.enq.valid) node _T_144 = and(can_enq_load_retry, _T_143) when _T_144 : connect ldq_addr[ldq_enq_retry_idx].valid, UInt<1>(0h0) node _retry_queue_io_deq_ready_T = or(will_fire_load_retry[0], will_fire_store_retry[0]) connect retry_queue.io.deq.ready, _retry_queue_io_deq_ready_T wire stq_execute_queue_flush : UInt<1> connect stq_execute_queue_flush, UInt<1>(0h0) node _T_145 = asUInt(reset) node _T_146 = or(_T_145, stq_execute_queue_flush) inst stq_execute_queue of Queue4_STQEntry connect stq_execute_queue.clock, clock connect stq_execute_queue.reset, _T_146 wire stq_enq_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_e_e.valid, stq_valid[stq_execute_head] connect stq_enq_e_e.bits.uop, stq_uop[stq_execute_head] connect stq_enq_e_e.bits.addr, stq_addr[stq_execute_head] connect stq_enq_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_execute_head] connect stq_enq_e_e.bits.data, stq_data[stq_execute_head] connect stq_enq_e_e.bits.committed, stq_committed[stq_execute_head] connect stq_enq_e_e.bits.succeeded, stq_succeeded[stq_execute_head] connect stq_enq_e_e.bits.can_execute, stq_can_execute[stq_execute_head] connect stq_enq_e_e.bits.cleared, stq_cleared[stq_execute_head] connect stq_enq_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_execute_head] wire stq_enq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_e, stq_enq_e_e connect stq_execute_queue.io.enq.bits.debug_wb_data, stq_enq_e.bits.debug_wb_data connect stq_execute_queue.io.enq.bits.cleared, stq_enq_e.bits.cleared connect stq_execute_queue.io.enq.bits.can_execute, stq_enq_e.bits.can_execute connect stq_execute_queue.io.enq.bits.succeeded, stq_enq_e.bits.succeeded connect stq_execute_queue.io.enq.bits.committed, stq_enq_e.bits.committed connect stq_execute_queue.io.enq.bits.data.bits, stq_enq_e.bits.data.bits connect stq_execute_queue.io.enq.bits.data.valid, stq_enq_e.bits.data.valid connect stq_execute_queue.io.enq.bits.addr_is_virtual, stq_enq_e.bits.addr_is_virtual connect stq_execute_queue.io.enq.bits.addr.bits, stq_enq_e.bits.addr.bits connect stq_execute_queue.io.enq.bits.addr.valid, stq_enq_e.bits.addr.valid connect stq_execute_queue.io.enq.bits.uop.debug_tsrc, stq_enq_e.bits.uop.debug_tsrc connect stq_execute_queue.io.enq.bits.uop.debug_fsrc, stq_enq_e.bits.uop.debug_fsrc connect stq_execute_queue.io.enq.bits.uop.bp_xcpt_if, stq_enq_e.bits.uop.bp_xcpt_if connect stq_execute_queue.io.enq.bits.uop.bp_debug_if, stq_enq_e.bits.uop.bp_debug_if connect stq_execute_queue.io.enq.bits.uop.xcpt_ma_if, stq_enq_e.bits.uop.xcpt_ma_if connect stq_execute_queue.io.enq.bits.uop.xcpt_ae_if, stq_enq_e.bits.uop.xcpt_ae_if connect stq_execute_queue.io.enq.bits.uop.xcpt_pf_if, stq_enq_e.bits.uop.xcpt_pf_if connect stq_execute_queue.io.enq.bits.uop.fp_typ, stq_enq_e.bits.uop.fp_typ connect stq_execute_queue.io.enq.bits.uop.fp_rm, stq_enq_e.bits.uop.fp_rm connect stq_execute_queue.io.enq.bits.uop.fp_val, stq_enq_e.bits.uop.fp_val connect stq_execute_queue.io.enq.bits.uop.fcn_op, stq_enq_e.bits.uop.fcn_op connect stq_execute_queue.io.enq.bits.uop.fcn_dw, stq_enq_e.bits.uop.fcn_dw connect stq_execute_queue.io.enq.bits.uop.frs3_en, stq_enq_e.bits.uop.frs3_en connect stq_execute_queue.io.enq.bits.uop.lrs2_rtype, stq_enq_e.bits.uop.lrs2_rtype connect stq_execute_queue.io.enq.bits.uop.lrs1_rtype, stq_enq_e.bits.uop.lrs1_rtype connect stq_execute_queue.io.enq.bits.uop.dst_rtype, stq_enq_e.bits.uop.dst_rtype connect stq_execute_queue.io.enq.bits.uop.lrs3, stq_enq_e.bits.uop.lrs3 connect stq_execute_queue.io.enq.bits.uop.lrs2, stq_enq_e.bits.uop.lrs2 connect stq_execute_queue.io.enq.bits.uop.lrs1, stq_enq_e.bits.uop.lrs1 connect stq_execute_queue.io.enq.bits.uop.ldst, stq_enq_e.bits.uop.ldst connect stq_execute_queue.io.enq.bits.uop.ldst_is_rs1, stq_enq_e.bits.uop.ldst_is_rs1 connect stq_execute_queue.io.enq.bits.uop.csr_cmd, stq_enq_e.bits.uop.csr_cmd connect stq_execute_queue.io.enq.bits.uop.flush_on_commit, stq_enq_e.bits.uop.flush_on_commit connect stq_execute_queue.io.enq.bits.uop.is_unique, stq_enq_e.bits.uop.is_unique connect stq_execute_queue.io.enq.bits.uop.uses_stq, stq_enq_e.bits.uop.uses_stq connect stq_execute_queue.io.enq.bits.uop.uses_ldq, stq_enq_e.bits.uop.uses_ldq connect stq_execute_queue.io.enq.bits.uop.mem_signed, stq_enq_e.bits.uop.mem_signed connect stq_execute_queue.io.enq.bits.uop.mem_size, stq_enq_e.bits.uop.mem_size connect stq_execute_queue.io.enq.bits.uop.mem_cmd, stq_enq_e.bits.uop.mem_cmd connect stq_execute_queue.io.enq.bits.uop.exc_cause, stq_enq_e.bits.uop.exc_cause connect stq_execute_queue.io.enq.bits.uop.exception, stq_enq_e.bits.uop.exception connect stq_execute_queue.io.enq.bits.uop.stale_pdst, stq_enq_e.bits.uop.stale_pdst connect stq_execute_queue.io.enq.bits.uop.ppred_busy, stq_enq_e.bits.uop.ppred_busy connect stq_execute_queue.io.enq.bits.uop.prs3_busy, stq_enq_e.bits.uop.prs3_busy connect stq_execute_queue.io.enq.bits.uop.prs2_busy, stq_enq_e.bits.uop.prs2_busy connect stq_execute_queue.io.enq.bits.uop.prs1_busy, stq_enq_e.bits.uop.prs1_busy connect stq_execute_queue.io.enq.bits.uop.ppred, stq_enq_e.bits.uop.ppred connect stq_execute_queue.io.enq.bits.uop.prs3, stq_enq_e.bits.uop.prs3 connect stq_execute_queue.io.enq.bits.uop.prs2, stq_enq_e.bits.uop.prs2 connect stq_execute_queue.io.enq.bits.uop.prs1, stq_enq_e.bits.uop.prs1 connect stq_execute_queue.io.enq.bits.uop.pdst, stq_enq_e.bits.uop.pdst connect stq_execute_queue.io.enq.bits.uop.rxq_idx, stq_enq_e.bits.uop.rxq_idx connect stq_execute_queue.io.enq.bits.uop.stq_idx, stq_enq_e.bits.uop.stq_idx connect stq_execute_queue.io.enq.bits.uop.ldq_idx, stq_enq_e.bits.uop.ldq_idx connect stq_execute_queue.io.enq.bits.uop.rob_idx, stq_enq_e.bits.uop.rob_idx connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.vec, stq_enq_e.bits.uop.fp_ctrl.vec connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.wflags, stq_enq_e.bits.uop.fp_ctrl.wflags connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.sqrt, stq_enq_e.bits.uop.fp_ctrl.sqrt connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.div, stq_enq_e.bits.uop.fp_ctrl.div connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fma, stq_enq_e.bits.uop.fp_ctrl.fma connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fastpipe, stq_enq_e.bits.uop.fp_ctrl.fastpipe connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.toint, stq_enq_e.bits.uop.fp_ctrl.toint connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fromint, stq_enq_e.bits.uop.fp_ctrl.fromint connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.typeTagOut, stq_enq_e.bits.uop.fp_ctrl.typeTagOut connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.typeTagIn, stq_enq_e.bits.uop.fp_ctrl.typeTagIn connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.swap23, stq_enq_e.bits.uop.fp_ctrl.swap23 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.swap12, stq_enq_e.bits.uop.fp_ctrl.swap12 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren3, stq_enq_e.bits.uop.fp_ctrl.ren3 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren2, stq_enq_e.bits.uop.fp_ctrl.ren2 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren1, stq_enq_e.bits.uop.fp_ctrl.ren1 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.wen, stq_enq_e.bits.uop.fp_ctrl.wen connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ldst, stq_enq_e.bits.uop.fp_ctrl.ldst connect stq_execute_queue.io.enq.bits.uop.op2_sel, stq_enq_e.bits.uop.op2_sel connect stq_execute_queue.io.enq.bits.uop.op1_sel, stq_enq_e.bits.uop.op1_sel connect stq_execute_queue.io.enq.bits.uop.imm_packed, stq_enq_e.bits.uop.imm_packed connect stq_execute_queue.io.enq.bits.uop.pimm, stq_enq_e.bits.uop.pimm connect stq_execute_queue.io.enq.bits.uop.imm_sel, stq_enq_e.bits.uop.imm_sel connect stq_execute_queue.io.enq.bits.uop.imm_rename, stq_enq_e.bits.uop.imm_rename connect stq_execute_queue.io.enq.bits.uop.taken, stq_enq_e.bits.uop.taken connect stq_execute_queue.io.enq.bits.uop.pc_lob, stq_enq_e.bits.uop.pc_lob connect stq_execute_queue.io.enq.bits.uop.edge_inst, stq_enq_e.bits.uop.edge_inst connect stq_execute_queue.io.enq.bits.uop.ftq_idx, stq_enq_e.bits.uop.ftq_idx connect stq_execute_queue.io.enq.bits.uop.is_mov, stq_enq_e.bits.uop.is_mov connect stq_execute_queue.io.enq.bits.uop.is_rocc, stq_enq_e.bits.uop.is_rocc connect stq_execute_queue.io.enq.bits.uop.is_sys_pc2epc, stq_enq_e.bits.uop.is_sys_pc2epc connect stq_execute_queue.io.enq.bits.uop.is_eret, stq_enq_e.bits.uop.is_eret connect stq_execute_queue.io.enq.bits.uop.is_amo, stq_enq_e.bits.uop.is_amo connect stq_execute_queue.io.enq.bits.uop.is_sfence, stq_enq_e.bits.uop.is_sfence connect stq_execute_queue.io.enq.bits.uop.is_fencei, stq_enq_e.bits.uop.is_fencei connect stq_execute_queue.io.enq.bits.uop.is_fence, stq_enq_e.bits.uop.is_fence connect stq_execute_queue.io.enq.bits.uop.is_sfb, stq_enq_e.bits.uop.is_sfb connect stq_execute_queue.io.enq.bits.uop.br_type, stq_enq_e.bits.uop.br_type connect stq_execute_queue.io.enq.bits.uop.br_tag, stq_enq_e.bits.uop.br_tag connect stq_execute_queue.io.enq.bits.uop.br_mask, stq_enq_e.bits.uop.br_mask connect stq_execute_queue.io.enq.bits.uop.dis_col_sel, stq_enq_e.bits.uop.dis_col_sel connect stq_execute_queue.io.enq.bits.uop.iw_p3_bypass_hint, stq_enq_e.bits.uop.iw_p3_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p2_bypass_hint, stq_enq_e.bits.uop.iw_p2_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p1_bypass_hint, stq_enq_e.bits.uop.iw_p1_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p2_speculative_child, stq_enq_e.bits.uop.iw_p2_speculative_child connect stq_execute_queue.io.enq.bits.uop.iw_p1_speculative_child, stq_enq_e.bits.uop.iw_p1_speculative_child connect stq_execute_queue.io.enq.bits.uop.iw_issued_partial_dgen, stq_enq_e.bits.uop.iw_issued_partial_dgen connect stq_execute_queue.io.enq.bits.uop.iw_issued_partial_agen, stq_enq_e.bits.uop.iw_issued_partial_agen connect stq_execute_queue.io.enq.bits.uop.iw_issued, stq_enq_e.bits.uop.iw_issued connect stq_execute_queue.io.enq.bits.uop.fu_code[0], stq_enq_e.bits.uop.fu_code[0] connect stq_execute_queue.io.enq.bits.uop.fu_code[1], stq_enq_e.bits.uop.fu_code[1] connect stq_execute_queue.io.enq.bits.uop.fu_code[2], stq_enq_e.bits.uop.fu_code[2] connect stq_execute_queue.io.enq.bits.uop.fu_code[3], stq_enq_e.bits.uop.fu_code[3] connect stq_execute_queue.io.enq.bits.uop.fu_code[4], stq_enq_e.bits.uop.fu_code[4] connect stq_execute_queue.io.enq.bits.uop.fu_code[5], stq_enq_e.bits.uop.fu_code[5] connect stq_execute_queue.io.enq.bits.uop.fu_code[6], stq_enq_e.bits.uop.fu_code[6] connect stq_execute_queue.io.enq.bits.uop.fu_code[7], stq_enq_e.bits.uop.fu_code[7] connect stq_execute_queue.io.enq.bits.uop.fu_code[8], stq_enq_e.bits.uop.fu_code[8] connect stq_execute_queue.io.enq.bits.uop.fu_code[9], stq_enq_e.bits.uop.fu_code[9] connect stq_execute_queue.io.enq.bits.uop.iq_type[0], stq_enq_e.bits.uop.iq_type[0] connect stq_execute_queue.io.enq.bits.uop.iq_type[1], stq_enq_e.bits.uop.iq_type[1] connect stq_execute_queue.io.enq.bits.uop.iq_type[2], stq_enq_e.bits.uop.iq_type[2] connect stq_execute_queue.io.enq.bits.uop.iq_type[3], stq_enq_e.bits.uop.iq_type[3] connect stq_execute_queue.io.enq.bits.uop.debug_pc, stq_enq_e.bits.uop.debug_pc connect stq_execute_queue.io.enq.bits.uop.is_rvc, stq_enq_e.bits.uop.is_rvc connect stq_execute_queue.io.enq.bits.uop.debug_inst, stq_enq_e.bits.uop.debug_inst connect stq_execute_queue.io.enq.bits.uop.inst, stq_enq_e.bits.uop.inst connect stq_execute_queue.io.enq.bits.uop.stq_idx, stq_execute_head node _stq_execute_queue_io_deq_ready_T = or(will_fire_store_commit_fast[0], will_fire_store_commit_slow[0]) connect stq_execute_queue.io.deq.ready, _stq_execute_queue_io_deq_ready_T node _can_enq_store_execute_T = and(stq_enq_e.valid, stq_enq_e.bits.addr.valid) node _can_enq_store_execute_T_1 = and(_can_enq_store_execute_T, stq_enq_e.bits.data.valid) node _can_enq_store_execute_T_2 = eq(stq_enq_e.bits.addr_is_virtual, UInt<1>(0h0)) node _can_enq_store_execute_T_3 = and(_can_enq_store_execute_T_1, _can_enq_store_execute_T_2) node _can_enq_store_execute_T_4 = eq(stq_enq_e.bits.uop.exception, UInt<1>(0h0)) node _can_enq_store_execute_T_5 = and(_can_enq_store_execute_T_3, _can_enq_store_execute_T_4) node _can_enq_store_execute_T_6 = eq(stq_enq_e.bits.uop.is_fence, UInt<1>(0h0)) node _can_enq_store_execute_T_7 = and(_can_enq_store_execute_T_5, _can_enq_store_execute_T_6) node _can_enq_store_execute_T_8 = or(stq_enq_e.bits.committed, stq_enq_e.bits.uop.is_amo) node can_enq_store_execute = and(_can_enq_store_execute_T_7, _can_enq_store_execute_T_8) connect stq_execute_queue.io.enq.valid, can_enq_store_execute node _T_147 = and(stq_execute_queue.io.enq.ready, stq_execute_queue.io.enq.valid) node _T_148 = and(can_enq_store_execute, _T_147) when _T_148 : node stq_execute_head_wrap = eq(stq_execute_head, UInt<5>(0h17)) node _stq_execute_head_T = add(stq_execute_head, UInt<1>(0h1)) node _stq_execute_head_T_1 = tail(_stq_execute_head_T, 1) node _stq_execute_head_T_2 = mux(stq_execute_head_wrap, UInt<1>(0h0), _stq_execute_head_T_1) connect stq_execute_head, _stq_execute_head_T_2 node _can_fire_load_agen_exec_T = and(io.core.agen[0].valid, io.core.agen[0].bits.uop.uses_ldq) wire can_fire_load_agen_exec : UInt<1>[1] connect can_fire_load_agen_exec[0], _can_fire_load_agen_exec_T node _can_fire_store_agen_T = and(io.core.agen[0].valid, io.core.agen[0].bits.uop.uses_stq) wire can_fire_store_agen : UInt<1>[1] connect can_fire_store_agen[0], _can_fire_store_agen_T wire can_fire_sfence : UInt<1>[1] connect can_fire_sfence[0], io.core.sfence.valid node _can_fire_release_T = and(UInt<1>(0h1), io.dmem.release.valid) wire can_fire_release : UInt<1>[1] connect can_fire_release[0], _can_fire_release_T connect io.dmem.release.ready, will_fire_release[0] node _can_fire_load_retry_T = and(retry_queue.io.deq.valid, retry_queue.io.deq.bits.uop.uses_ldq) reg can_fire_load_retry_REG : UInt<1>, clock connect can_fire_load_retry_REG, store_needs_order node _can_fire_load_retry_T_1 = eq(can_fire_load_retry_REG, UInt<1>(0h0)) node _can_fire_load_retry_T_2 = and(_can_fire_load_retry_T, _can_fire_load_retry_T_1) node _can_fire_load_retry_T_3 = and(_can_fire_load_retry_T_2, UInt<1>(0h1)) wire can_fire_load_retry : UInt<1>[1] connect can_fire_load_retry[0], _can_fire_load_retry_T_3 node _can_fire_store_retry_T = and(retry_queue.io.deq.valid, retry_queue.io.deq.bits.uop.uses_stq) node _can_fire_store_retry_T_1 = and(_can_fire_store_retry_T, UInt<1>(0h1)) wire can_fire_store_retry : UInt<1>[1] connect can_fire_store_retry[0], _can_fire_store_retry_T_1 node _can_fire_store_commit_slow_T = eq(mem_xcpt_valid, UInt<1>(0h0)) node _can_fire_store_commit_slow_T_1 = and(stq_execute_queue.io.deq.valid, _can_fire_store_commit_slow_T) node _can_fire_store_commit_slow_T_2 = and(_can_fire_store_commit_slow_T_1, UInt<1>(0h1)) wire can_fire_store_commit_slow : UInt<1>[1] connect can_fire_store_commit_slow[0], _can_fire_store_commit_slow_T_2 node _can_fire_store_commit_fast_T = and(can_fire_store_commit_slow[0], stq_almost_full) wire can_fire_store_commit_fast : UInt<1>[1] connect can_fire_store_commit_fast[0], _can_fire_store_commit_fast_T wire block_load_wakeup : UInt<1> connect block_load_wakeup, UInt<1>(0h0) node _can_fire_load_wakeup_T = and(ldq_wakeup_e.valid, ldq_wakeup_e.bits.addr.valid) node _can_fire_load_wakeup_T_1 = eq(ldq_wakeup_e.bits.succeeded, UInt<1>(0h0)) node _can_fire_load_wakeup_T_2 = and(_can_fire_load_wakeup_T, _can_fire_load_wakeup_T_1) node _can_fire_load_wakeup_T_3 = eq(ldq_wakeup_e.bits.addr_is_virtual, UInt<1>(0h0)) node _can_fire_load_wakeup_T_4 = and(_can_fire_load_wakeup_T_2, _can_fire_load_wakeup_T_3) node _can_fire_load_wakeup_T_5 = eq(ldq_wakeup_e.bits.executed, UInt<1>(0h0)) node _can_fire_load_wakeup_T_6 = and(_can_fire_load_wakeup_T_4, _can_fire_load_wakeup_T_5) node _can_fire_load_wakeup_T_7 = eq(ldq_wakeup_e.bits.order_fail, UInt<1>(0h0)) node _can_fire_load_wakeup_T_8 = and(_can_fire_load_wakeup_T_6, _can_fire_load_wakeup_T_7) node _can_fire_load_wakeup_T_9 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _can_fire_load_wakeup_T_10 = bits(_can_fire_load_wakeup_T_9, 4, 0) node _can_fire_load_wakeup_T_11 = eq(p1_block_load_mask[_can_fire_load_wakeup_T_10], UInt<1>(0h0)) node _can_fire_load_wakeup_T_12 = and(_can_fire_load_wakeup_T_8, _can_fire_load_wakeup_T_11) node _can_fire_load_wakeup_T_13 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _can_fire_load_wakeup_T_14 = bits(_can_fire_load_wakeup_T_13, 4, 0) node _can_fire_load_wakeup_T_15 = eq(p2_block_load_mask[_can_fire_load_wakeup_T_14], UInt<1>(0h0)) node _can_fire_load_wakeup_T_16 = and(_can_fire_load_wakeup_T_12, _can_fire_load_wakeup_T_15) reg can_fire_load_wakeup_REG : UInt<1>, clock connect can_fire_load_wakeup_REG, store_needs_order node _can_fire_load_wakeup_T_17 = eq(can_fire_load_wakeup_REG, UInt<1>(0h0)) node _can_fire_load_wakeup_T_18 = and(_can_fire_load_wakeup_T_16, _can_fire_load_wakeup_T_17) node _can_fire_load_wakeup_T_19 = eq(block_load_wakeup, UInt<1>(0h0)) node _can_fire_load_wakeup_T_20 = and(_can_fire_load_wakeup_T_18, _can_fire_load_wakeup_T_19) node _can_fire_load_wakeup_T_21 = and(_can_fire_load_wakeup_T_20, UInt<1>(0h1)) node _can_fire_load_wakeup_T_22 = eq(ldq_wakeup_e.bits.addr_is_uncacheable, UInt<1>(0h0)) node _can_fire_load_wakeup_T_23 = eq(ldq_head, ldq_wakeup_idx) node _can_fire_load_wakeup_T_24 = and(io.core.commit_load_at_rob_head, _can_fire_load_wakeup_T_23) node _can_fire_load_wakeup_T_25 = eq(ldq_wakeup_e.bits.st_dep_mask, UInt<1>(0h0)) node _can_fire_load_wakeup_T_26 = and(_can_fire_load_wakeup_T_24, _can_fire_load_wakeup_T_25) node _can_fire_load_wakeup_T_27 = or(_can_fire_load_wakeup_T_22, _can_fire_load_wakeup_T_26) node _can_fire_load_wakeup_T_28 = and(_can_fire_load_wakeup_T_21, _can_fire_load_wakeup_T_27) wire can_fire_load_wakeup : UInt<1>[1] connect can_fire_load_wakeup[0], _can_fire_load_wakeup_T_28 wire _can_fire_hella_incoming_WIRE : UInt<1>[1] connect _can_fire_hella_incoming_WIRE[0], UInt<1>(0h0) wire can_fire_hella_incoming : UInt<1>[1] connect can_fire_hella_incoming, _can_fire_hella_incoming_WIRE wire _can_fire_hella_wakeup_WIRE : UInt<1>[1] connect _can_fire_hella_wakeup_WIRE[0], UInt<1>(0h0) wire can_fire_hella_wakeup : UInt<1>[1] connect can_fire_hella_wakeup, _can_fire_hella_wakeup_WIRE wire exe_tlb_valid : UInt<1>[1] node _will_fire_sfence_0_will_fire_T = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_sfence_0_will_fire_T) node _will_fire_sfence_0_will_fire_T_2 = eq(_will_fire_sfence_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_3 = and(can_fire_sfence[0], _will_fire_sfence_0_will_fire_T_2) node _will_fire_sfence_0_will_fire_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_4) node _will_fire_sfence_0_will_fire_T_6 = eq(_will_fire_sfence_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_7 = and(_will_fire_sfence_0_will_fire_T_3, _will_fire_sfence_0_will_fire_T_6) node _will_fire_sfence_0_will_fire_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_8) node _will_fire_sfence_0_will_fire_T_10 = eq(_will_fire_sfence_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_sfence_0_will_fire = and(_will_fire_sfence_0_will_fire_T_7, _will_fire_sfence_0_will_fire_T_10) node _will_fire_sfence_0_T = and(will_fire_sfence_0_will_fire, UInt<1>(0h1)) node _will_fire_sfence_0_T_1 = eq(_will_fire_sfence_0_T, UInt<1>(0h0)) node _will_fire_sfence_0_T_2 = and(UInt<1>(0h1), _will_fire_sfence_0_T_1) node _will_fire_sfence_0_T_3 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0)) node _will_fire_sfence_0_T_4 = eq(_will_fire_sfence_0_T_3, UInt<1>(0h0)) node _will_fire_sfence_0_T_5 = and(UInt<1>(0h1), _will_fire_sfence_0_T_4) node _will_fire_sfence_0_T_6 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0)) node _will_fire_sfence_0_T_7 = eq(_will_fire_sfence_0_T_6, UInt<1>(0h0)) node _will_fire_sfence_0_T_8 = and(UInt<1>(0h1), _will_fire_sfence_0_T_7) connect will_fire_sfence[0], will_fire_sfence_0_will_fire node _will_fire_store_commit_fast_0_will_fire_T = eq(_will_fire_sfence_0_T_2, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_store_commit_fast_0_will_fire_T) node _will_fire_store_commit_fast_0_will_fire_T_2 = eq(_will_fire_store_commit_fast_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_3 = and(can_fire_store_commit_fast[0], _will_fire_store_commit_fast_0_will_fire_T_2) node _will_fire_store_commit_fast_0_will_fire_T_4 = eq(_will_fire_sfence_0_T_5, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_store_commit_fast_0_will_fire_T_4) node _will_fire_store_commit_fast_0_will_fire_T_6 = eq(_will_fire_store_commit_fast_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_7 = and(_will_fire_store_commit_fast_0_will_fire_T_3, _will_fire_store_commit_fast_0_will_fire_T_6) node _will_fire_store_commit_fast_0_will_fire_T_8 = eq(_will_fire_sfence_0_T_8, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_store_commit_fast_0_will_fire_T_8) node _will_fire_store_commit_fast_0_will_fire_T_10 = eq(_will_fire_store_commit_fast_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_commit_fast_0_will_fire = and(_will_fire_store_commit_fast_0_will_fire_T_7, _will_fire_store_commit_fast_0_will_fire_T_10) node _will_fire_store_commit_fast_0_T = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_1 = eq(_will_fire_store_commit_fast_0_T, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_2 = and(_will_fire_sfence_0_T_2, _will_fire_store_commit_fast_0_T_1) node _will_fire_store_commit_fast_0_T_3 = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_4 = eq(_will_fire_store_commit_fast_0_T_3, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_5 = and(_will_fire_sfence_0_T_5, _will_fire_store_commit_fast_0_T_4) node _will_fire_store_commit_fast_0_T_6 = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h1)) node _will_fire_store_commit_fast_0_T_7 = eq(_will_fire_store_commit_fast_0_T_6, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_8 = and(_will_fire_sfence_0_T_8, _will_fire_store_commit_fast_0_T_7) connect will_fire_store_commit_fast[0], will_fire_store_commit_fast_0_will_fire node _will_fire_load_agen_exec_0_will_fire_T = eq(_will_fire_store_commit_fast_0_T_2, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T) node _will_fire_load_agen_exec_0_will_fire_T_2 = eq(_will_fire_load_agen_exec_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_3 = and(can_fire_load_agen_exec[0], _will_fire_load_agen_exec_0_will_fire_T_2) node _will_fire_load_agen_exec_0_will_fire_T_4 = eq(_will_fire_store_commit_fast_0_T_5, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T_4) node _will_fire_load_agen_exec_0_will_fire_T_6 = eq(_will_fire_load_agen_exec_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_7 = and(_will_fire_load_agen_exec_0_will_fire_T_3, _will_fire_load_agen_exec_0_will_fire_T_6) node _will_fire_load_agen_exec_0_will_fire_T_8 = eq(_will_fire_store_commit_fast_0_T_8, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T_8) node _will_fire_load_agen_exec_0_will_fire_T_10 = eq(_will_fire_load_agen_exec_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_agen_exec_0_will_fire = and(_will_fire_load_agen_exec_0_will_fire_T_7, _will_fire_load_agen_exec_0_will_fire_T_10) node _will_fire_load_agen_exec_0_T = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_1 = eq(_will_fire_load_agen_exec_0_T, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_2 = and(_will_fire_store_commit_fast_0_T_2, _will_fire_load_agen_exec_0_T_1) node _will_fire_load_agen_exec_0_T_3 = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_4 = eq(_will_fire_load_agen_exec_0_T_3, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_5 = and(_will_fire_store_commit_fast_0_T_5, _will_fire_load_agen_exec_0_T_4) node _will_fire_load_agen_exec_0_T_6 = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_7 = eq(_will_fire_load_agen_exec_0_T_6, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_8 = and(_will_fire_store_commit_fast_0_T_8, _will_fire_load_agen_exec_0_T_7) connect will_fire_load_agen_exec[0], will_fire_load_agen_exec_0_will_fire node _will_fire_load_agen_0_will_fire_T = eq(_will_fire_load_agen_exec_0_T_2, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_agen_0_will_fire_T) node _will_fire_load_agen_0_will_fire_T_2 = eq(_will_fire_load_agen_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_3 = and(can_fire_load_agen_exec[0], _will_fire_load_agen_0_will_fire_T_2) node _will_fire_load_agen_0_will_fire_T_4 = eq(_will_fire_load_agen_exec_0_T_5, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_agen_0_will_fire_T_4) node _will_fire_load_agen_0_will_fire_T_6 = eq(_will_fire_load_agen_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_7 = and(_will_fire_load_agen_0_will_fire_T_3, _will_fire_load_agen_0_will_fire_T_6) node _will_fire_load_agen_0_will_fire_T_8 = eq(_will_fire_load_agen_exec_0_T_8, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_load_agen_0_will_fire_T_8) node _will_fire_load_agen_0_will_fire_T_10 = eq(_will_fire_load_agen_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_agen_0_will_fire = and(_will_fire_load_agen_0_will_fire_T_7, _will_fire_load_agen_0_will_fire_T_10) node _will_fire_load_agen_0_T = and(will_fire_load_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_0_T_1 = eq(_will_fire_load_agen_0_T, UInt<1>(0h0)) node _will_fire_load_agen_0_T_2 = and(_will_fire_load_agen_exec_0_T_2, _will_fire_load_agen_0_T_1) node _will_fire_load_agen_0_T_3 = and(will_fire_load_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_0_T_4 = eq(_will_fire_load_agen_0_T_3, UInt<1>(0h0)) node _will_fire_load_agen_0_T_5 = and(_will_fire_load_agen_exec_0_T_5, _will_fire_load_agen_0_T_4) node _will_fire_load_agen_0_T_6 = and(will_fire_load_agen_0_will_fire, UInt<1>(0h0)) node _will_fire_load_agen_0_T_7 = eq(_will_fire_load_agen_0_T_6, UInt<1>(0h0)) node _will_fire_load_agen_0_T_8 = and(_will_fire_load_agen_exec_0_T_8, _will_fire_load_agen_0_T_7) connect will_fire_load_agen[0], will_fire_load_agen_0_will_fire node _will_fire_store_agen_0_will_fire_T = eq(_will_fire_load_agen_0_T_2, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_store_agen_0_will_fire_T) node _will_fire_store_agen_0_will_fire_T_2 = eq(_will_fire_store_agen_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_3 = and(can_fire_store_agen[0], _will_fire_store_agen_0_will_fire_T_2) node _will_fire_store_agen_0_will_fire_T_4 = eq(_will_fire_load_agen_0_T_5, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_store_agen_0_will_fire_T_4) node _will_fire_store_agen_0_will_fire_T_6 = eq(_will_fire_store_agen_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_7 = and(_will_fire_store_agen_0_will_fire_T_3, _will_fire_store_agen_0_will_fire_T_6) node _will_fire_store_agen_0_will_fire_T_8 = eq(_will_fire_load_agen_0_T_8, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_store_agen_0_will_fire_T_8) node _will_fire_store_agen_0_will_fire_T_10 = eq(_will_fire_store_agen_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_agen_0_will_fire = and(_will_fire_store_agen_0_will_fire_T_7, _will_fire_store_agen_0_will_fire_T_10) node _will_fire_store_agen_0_T = and(will_fire_store_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_store_agen_0_T_1 = eq(_will_fire_store_agen_0_T, UInt<1>(0h0)) node _will_fire_store_agen_0_T_2 = and(_will_fire_load_agen_0_T_2, _will_fire_store_agen_0_T_1) node _will_fire_store_agen_0_T_3 = and(will_fire_store_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_store_agen_0_T_4 = eq(_will_fire_store_agen_0_T_3, UInt<1>(0h0)) node _will_fire_store_agen_0_T_5 = and(_will_fire_load_agen_0_T_5, _will_fire_store_agen_0_T_4) node _will_fire_store_agen_0_T_6 = and(will_fire_store_agen_0_will_fire, UInt<1>(0h0)) node _will_fire_store_agen_0_T_7 = eq(_will_fire_store_agen_0_T_6, UInt<1>(0h0)) node _will_fire_store_agen_0_T_8 = and(_will_fire_load_agen_0_T_8, _will_fire_store_agen_0_T_7) connect will_fire_store_agen[0], will_fire_store_agen_0_will_fire node _will_fire_release_0_will_fire_T = eq(_will_fire_store_agen_0_T_2, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T) node _will_fire_release_0_will_fire_T_2 = eq(_will_fire_release_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_3 = and(can_fire_release[0], _will_fire_release_0_will_fire_T_2) node _will_fire_release_0_will_fire_T_4 = eq(_will_fire_store_agen_0_T_5, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_release_0_will_fire_T_4) node _will_fire_release_0_will_fire_T_6 = eq(_will_fire_release_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_7 = and(_will_fire_release_0_will_fire_T_3, _will_fire_release_0_will_fire_T_6) node _will_fire_release_0_will_fire_T_8 = eq(_will_fire_store_agen_0_T_8, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T_8) node _will_fire_release_0_will_fire_T_10 = eq(_will_fire_release_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_release_0_will_fire = and(_will_fire_release_0_will_fire_T_7, _will_fire_release_0_will_fire_T_10) node _will_fire_release_0_T = and(will_fire_release_0_will_fire, UInt<1>(0h0)) node _will_fire_release_0_T_1 = eq(_will_fire_release_0_T, UInt<1>(0h0)) node _will_fire_release_0_T_2 = and(_will_fire_store_agen_0_T_2, _will_fire_release_0_T_1) node _will_fire_release_0_T_3 = and(will_fire_release_0_will_fire, UInt<1>(0h1)) node _will_fire_release_0_T_4 = eq(_will_fire_release_0_T_3, UInt<1>(0h0)) node _will_fire_release_0_T_5 = and(_will_fire_store_agen_0_T_5, _will_fire_release_0_T_4) node _will_fire_release_0_T_6 = and(will_fire_release_0_will_fire, UInt<1>(0h0)) node _will_fire_release_0_T_7 = eq(_will_fire_release_0_T_6, UInt<1>(0h0)) node _will_fire_release_0_T_8 = and(_will_fire_store_agen_0_T_8, _will_fire_release_0_T_7) connect will_fire_release[0], will_fire_release_0_will_fire node _will_fire_hella_incoming_0_will_fire_T = eq(_will_fire_release_0_T_2, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T) node _will_fire_hella_incoming_0_will_fire_T_2 = eq(_will_fire_hella_incoming_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_3 = and(can_fire_hella_incoming[0], _will_fire_hella_incoming_0_will_fire_T_2) node _will_fire_hella_incoming_0_will_fire_T_4 = eq(_will_fire_release_0_T_5, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_incoming_0_will_fire_T_4) node _will_fire_hella_incoming_0_will_fire_T_6 = eq(_will_fire_hella_incoming_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_7 = and(_will_fire_hella_incoming_0_will_fire_T_3, _will_fire_hella_incoming_0_will_fire_T_6) node _will_fire_hella_incoming_0_will_fire_T_8 = eq(_will_fire_release_0_T_8, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T_8) node _will_fire_hella_incoming_0_will_fire_T_10 = eq(_will_fire_hella_incoming_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_hella_incoming_0_will_fire = and(_will_fire_hella_incoming_0_will_fire_T_7, _will_fire_hella_incoming_0_will_fire_T_10) node _will_fire_hella_incoming_0_T = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_incoming_0_T_1 = eq(_will_fire_hella_incoming_0_T, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_2 = and(_will_fire_release_0_T_2, _will_fire_hella_incoming_0_T_1) node _will_fire_hella_incoming_0_T_3 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_4 = eq(_will_fire_hella_incoming_0_T_3, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_5 = and(_will_fire_release_0_T_5, _will_fire_hella_incoming_0_T_4) node _will_fire_hella_incoming_0_T_6 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_incoming_0_T_7 = eq(_will_fire_hella_incoming_0_T_6, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_8 = and(_will_fire_release_0_T_8, _will_fire_hella_incoming_0_T_7) connect will_fire_hella_incoming[0], will_fire_hella_incoming_0_will_fire node _will_fire_hella_wakeup_0_will_fire_T = eq(_will_fire_hella_incoming_0_T_2, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T) node _will_fire_hella_wakeup_0_will_fire_T_2 = eq(_will_fire_hella_wakeup_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_3 = and(can_fire_hella_wakeup[0], _will_fire_hella_wakeup_0_will_fire_T_2) node _will_fire_hella_wakeup_0_will_fire_T_4 = eq(_will_fire_hella_incoming_0_T_5, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T_4) node _will_fire_hella_wakeup_0_will_fire_T_6 = eq(_will_fire_hella_wakeup_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_7 = and(_will_fire_hella_wakeup_0_will_fire_T_3, _will_fire_hella_wakeup_0_will_fire_T_6) node _will_fire_hella_wakeup_0_will_fire_T_8 = eq(_will_fire_hella_incoming_0_T_8, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_wakeup_0_will_fire_T_8) node _will_fire_hella_wakeup_0_will_fire_T_10 = eq(_will_fire_hella_wakeup_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_hella_wakeup_0_will_fire = and(_will_fire_hella_wakeup_0_will_fire_T_7, _will_fire_hella_wakeup_0_will_fire_T_10) node _will_fire_hella_wakeup_0_T = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_1 = eq(_will_fire_hella_wakeup_0_T, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_2 = and(_will_fire_hella_incoming_0_T_2, _will_fire_hella_wakeup_0_T_1) node _will_fire_hella_wakeup_0_T_3 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_4 = eq(_will_fire_hella_wakeup_0_T_3, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_5 = and(_will_fire_hella_incoming_0_T_5, _will_fire_hella_wakeup_0_T_4) node _will_fire_hella_wakeup_0_T_6 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_wakeup_0_T_7 = eq(_will_fire_hella_wakeup_0_T_6, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_8 = and(_will_fire_hella_incoming_0_T_8, _will_fire_hella_wakeup_0_T_7) connect will_fire_hella_wakeup[0], will_fire_hella_wakeup_0_will_fire node _will_fire_store_retry_0_will_fire_T = eq(_will_fire_hella_wakeup_0_T_2, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_store_retry_0_will_fire_T) node _will_fire_store_retry_0_will_fire_T_2 = eq(_will_fire_store_retry_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_3 = and(can_fire_store_retry[0], _will_fire_store_retry_0_will_fire_T_2) node _will_fire_store_retry_0_will_fire_T_4 = eq(_will_fire_hella_wakeup_0_T_5, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_store_retry_0_will_fire_T_4) node _will_fire_store_retry_0_will_fire_T_6 = eq(_will_fire_store_retry_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_7 = and(_will_fire_store_retry_0_will_fire_T_3, _will_fire_store_retry_0_will_fire_T_6) node _will_fire_store_retry_0_will_fire_T_8 = eq(_will_fire_hella_wakeup_0_T_8, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_store_retry_0_will_fire_T_8) node _will_fire_store_retry_0_will_fire_T_10 = eq(_will_fire_store_retry_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_retry_0_will_fire = and(_will_fire_store_retry_0_will_fire_T_7, _will_fire_store_retry_0_will_fire_T_10) node _will_fire_store_retry_0_T = and(will_fire_store_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_store_retry_0_T_1 = eq(_will_fire_store_retry_0_T, UInt<1>(0h0)) node _will_fire_store_retry_0_T_2 = and(_will_fire_hella_wakeup_0_T_2, _will_fire_store_retry_0_T_1) node _will_fire_store_retry_0_T_3 = and(will_fire_store_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_store_retry_0_T_4 = eq(_will_fire_store_retry_0_T_3, UInt<1>(0h0)) node _will_fire_store_retry_0_T_5 = and(_will_fire_hella_wakeup_0_T_5, _will_fire_store_retry_0_T_4) node _will_fire_store_retry_0_T_6 = and(will_fire_store_retry_0_will_fire, UInt<1>(0h0)) node _will_fire_store_retry_0_T_7 = eq(_will_fire_store_retry_0_T_6, UInt<1>(0h0)) node _will_fire_store_retry_0_T_8 = and(_will_fire_hella_wakeup_0_T_8, _will_fire_store_retry_0_T_7) connect will_fire_store_retry[0], will_fire_store_retry_0_will_fire node _will_fire_load_retry_0_will_fire_T = eq(_will_fire_store_retry_0_T_2, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T) node _will_fire_load_retry_0_will_fire_T_2 = eq(_will_fire_load_retry_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_3 = and(can_fire_load_retry[0], _will_fire_load_retry_0_will_fire_T_2) node _will_fire_load_retry_0_will_fire_T_4 = eq(_will_fire_store_retry_0_T_5, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_4) node _will_fire_load_retry_0_will_fire_T_6 = eq(_will_fire_load_retry_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_7 = and(_will_fire_load_retry_0_will_fire_T_3, _will_fire_load_retry_0_will_fire_T_6) node _will_fire_load_retry_0_will_fire_T_8 = eq(_will_fire_store_retry_0_T_8, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_8) node _will_fire_load_retry_0_will_fire_T_10 = eq(_will_fire_load_retry_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_retry_0_will_fire = and(_will_fire_load_retry_0_will_fire_T_7, _will_fire_load_retry_0_will_fire_T_10) node _will_fire_load_retry_0_T = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_1 = eq(_will_fire_load_retry_0_T, UInt<1>(0h0)) node _will_fire_load_retry_0_T_2 = and(_will_fire_store_retry_0_T_2, _will_fire_load_retry_0_T_1) node _will_fire_load_retry_0_T_3 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_4 = eq(_will_fire_load_retry_0_T_3, UInt<1>(0h0)) node _will_fire_load_retry_0_T_5 = and(_will_fire_store_retry_0_T_5, _will_fire_load_retry_0_T_4) node _will_fire_load_retry_0_T_6 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_7 = eq(_will_fire_load_retry_0_T_6, UInt<1>(0h0)) node _will_fire_load_retry_0_T_8 = and(_will_fire_store_retry_0_T_8, _will_fire_load_retry_0_T_7) connect will_fire_load_retry[0], will_fire_load_retry_0_will_fire node _will_fire_load_wakeup_0_will_fire_T = eq(_will_fire_load_retry_0_T_2, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_load_wakeup_0_will_fire_T) node _will_fire_load_wakeup_0_will_fire_T_2 = eq(_will_fire_load_wakeup_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_3 = and(can_fire_load_wakeup[0], _will_fire_load_wakeup_0_will_fire_T_2) node _will_fire_load_wakeup_0_will_fire_T_4 = eq(_will_fire_load_retry_0_T_5, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_4) node _will_fire_load_wakeup_0_will_fire_T_6 = eq(_will_fire_load_wakeup_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_7 = and(_will_fire_load_wakeup_0_will_fire_T_3, _will_fire_load_wakeup_0_will_fire_T_6) node _will_fire_load_wakeup_0_will_fire_T_8 = eq(_will_fire_load_retry_0_T_8, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_8) node _will_fire_load_wakeup_0_will_fire_T_10 = eq(_will_fire_load_wakeup_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_wakeup_0_will_fire = and(_will_fire_load_wakeup_0_will_fire_T_7, _will_fire_load_wakeup_0_will_fire_T_10) node _will_fire_load_wakeup_0_T = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_1 = eq(_will_fire_load_wakeup_0_T, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_2 = and(_will_fire_load_retry_0_T_2, _will_fire_load_wakeup_0_T_1) node _will_fire_load_wakeup_0_T_3 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_load_wakeup_0_T_4 = eq(_will_fire_load_wakeup_0_T_3, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_5 = and(_will_fire_load_retry_0_T_5, _will_fire_load_wakeup_0_T_4) node _will_fire_load_wakeup_0_T_6 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_load_wakeup_0_T_7 = eq(_will_fire_load_wakeup_0_T_6, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_8 = and(_will_fire_load_retry_0_T_8, _will_fire_load_wakeup_0_T_7) connect will_fire_load_wakeup[0], will_fire_load_wakeup_0_will_fire node _will_fire_store_commit_slow_0_will_fire_T = eq(_will_fire_load_wakeup_0_T_2, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_store_commit_slow_0_will_fire_T) node _will_fire_store_commit_slow_0_will_fire_T_2 = eq(_will_fire_store_commit_slow_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_3 = and(can_fire_store_commit_slow[0], _will_fire_store_commit_slow_0_will_fire_T_2) node _will_fire_store_commit_slow_0_will_fire_T_4 = eq(_will_fire_load_wakeup_0_T_5, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_store_commit_slow_0_will_fire_T_4) node _will_fire_store_commit_slow_0_will_fire_T_6 = eq(_will_fire_store_commit_slow_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_7 = and(_will_fire_store_commit_slow_0_will_fire_T_3, _will_fire_store_commit_slow_0_will_fire_T_6) node _will_fire_store_commit_slow_0_will_fire_T_8 = eq(_will_fire_load_wakeup_0_T_8, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_store_commit_slow_0_will_fire_T_8) node _will_fire_store_commit_slow_0_will_fire_T_10 = eq(_will_fire_store_commit_slow_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_commit_slow_0_will_fire = and(_will_fire_store_commit_slow_0_will_fire_T_7, _will_fire_store_commit_slow_0_will_fire_T_10) node _will_fire_store_commit_slow_0_T = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_1 = eq(_will_fire_store_commit_slow_0_T, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_2 = and(_will_fire_load_wakeup_0_T_2, _will_fire_store_commit_slow_0_T_1) node _will_fire_store_commit_slow_0_T_3 = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_4 = eq(_will_fire_store_commit_slow_0_T_3, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_5 = and(_will_fire_load_wakeup_0_T_5, _will_fire_store_commit_slow_0_T_4) node _will_fire_store_commit_slow_0_T_6 = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h1)) node _will_fire_store_commit_slow_0_T_7 = eq(_will_fire_store_commit_slow_0_T_6, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_8 = and(_will_fire_load_wakeup_0_T_8, _will_fire_store_commit_slow_0_T_7) connect will_fire_store_commit_slow[0], will_fire_store_commit_slow_0_will_fire node _T_149 = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _T_150 = or(_T_149, will_fire_store_agen[0]) node _T_151 = eq(_T_150, UInt<1>(0h0)) node _T_152 = and(io.core.agen[0].valid, _T_151) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:687 assert(!(agen(w).valid && !(will_fire_load_agen_exec(w) \|\| will_fire_load_agen(w) \|\| will_fire_store_agen(w))))\n") : printf_16 assert(clock, _T_153, UInt<1>(0h1), "") : assert_16 when will_fire_load_wakeup[0] : node _T_157 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _T_158 = bits(_T_157, 4, 0) connect block_load_mask[_T_158], UInt<1>(0h1) else : node _T_159 = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) when _T_159 : connect block_load_mask[io.core.agen[0].bits.uop.ldq_idx], UInt<1>(0h1) else : when will_fire_load_retry[0] : connect block_load_mask[retry_queue.io.deq.bits.uop.ldq_idx], UInt<1>(0h1) node _exe_tlb_valid_0_T = eq(_will_fire_store_commit_slow_0_T_2, UInt<1>(0h0)) connect exe_tlb_valid[0], _exe_tlb_valid_0_T node _T_160 = eq(will_fire_hella_incoming[0], UInt<1>(0h0)) node _T_161 = eq(will_fire_hella_wakeup[0], UInt<1>(0h0)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(will_fire_load_retry[0], UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(will_fire_store_retry[0], UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(will_fire_store_commit_fast[0], UInt<1>(0h0)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(will_fire_store_commit_slow[0], UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = eq(will_fire_load_wakeup[0], UInt<1>(0h0)) node _T_172 = and(_T_170, _T_171) node _T_173 = or(UInt<1>(0h1), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: Some operations is proceeding down multiple pipes\n at lsu.scala:698 assert((lsuWidth == 1).B \|\|\n") : printf_17 assert(clock, _T_173, UInt<1>(0h1), "") : assert_17 node _T_177 = neq(hella_state, UInt<3>(0h0)) node _T_178 = eq(hella_req.cmd, UInt<5>(0h14)) node _T_179 = and(_T_177, _T_178) node _T_180 = eq(_T_179, UInt<1>(0h0)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: SFENCE through hella interface not supported\n at lsu.scala:713 assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),\n") : printf_18 assert(clock, _T_180, UInt<1>(0h1), "") : assert_18 node _exe_tlb_uop_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_tlb_uop_T_1 = or(will_fire_load_retry[0], will_fire_store_retry[0]) wire _exe_tlb_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _exe_tlb_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_typ, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_rm, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.fp_val, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fcn_op, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.frs3_en, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.lrs3, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.lrs2, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.lrs1, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.ldst, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_unique, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.uses_stq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.mem_signed, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.mem_size, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.exc_cause, UInt<64>(0h0) connect _exe_tlb_uop_WIRE.exception, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.ppred, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.prs3, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.prs2, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.prs1, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.stq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.rob_idx, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.op2_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.op1_sel, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.imm_packed, UInt<20>(0h0) connect _exe_tlb_uop_WIRE.pimm, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.imm_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.imm_rename, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.taken, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.pc_lob, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.edge_inst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.is_mov, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_rocc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_eret, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_amo, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sfence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_fencei, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_fence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sfb, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.br_type, UInt<4>(0h0) connect _exe_tlb_uop_WIRE.br_tag, UInt<4>(0h0) connect _exe_tlb_uop_WIRE.br_mask, UInt<16>(0h0) connect _exe_tlb_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_issued, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.debug_pc, UInt<40>(0h0) connect _exe_tlb_uop_WIRE.is_rvc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.debug_inst, UInt<32>(0h0) connect _exe_tlb_uop_WIRE.inst, UInt<32>(0h0) wire _exe_tlb_uop_WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _exe_tlb_uop_WIRE_1.debug_tsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.debug_fsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.bp_xcpt_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.bp_debug_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_ma_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_ae_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_pf_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_typ, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_rm, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.fp_val, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fcn_op, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.fcn_dw, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.frs3_en, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.lrs2_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.lrs1_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.dst_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.lrs3, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.lrs2, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.lrs1, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.ldst, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.ldst_is_rs1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.csr_cmd, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.flush_on_commit, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_unique, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.uses_stq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.uses_ldq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.mem_signed, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.mem_size, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.mem_cmd, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.exc_cause, UInt<64>(0h0) connect _exe_tlb_uop_WIRE_1.exception, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.stale_pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.ppred_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs3_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs2_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs1_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.ppred, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.prs3, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.prs2, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.prs1, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.rxq_idx, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.stq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.ldq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.rob_idx, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.vec, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.wflags, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.sqrt, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.div, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fma, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fastpipe, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.toint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fromint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.swap23, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.swap12, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren3, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren2, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.wen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ldst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.op2_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.op1_sel, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.imm_packed, UInt<20>(0h0) connect _exe_tlb_uop_WIRE_1.pimm, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.imm_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.imm_rename, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.taken, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.pc_lob, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.edge_inst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.ftq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.is_mov, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_rocc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sys_pc2epc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_eret, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_amo, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sfence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_fencei, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_fence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sfb, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.br_type, UInt<4>(0h0) connect _exe_tlb_uop_WIRE_1.br_tag, UInt<4>(0h0) connect _exe_tlb_uop_WIRE_1.br_mask, UInt<16>(0h0) connect _exe_tlb_uop_WIRE_1.dis_col_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p2_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p1_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[4], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[5], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[6], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[7], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[8], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[9], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.debug_pc, UInt<40>(0h0) connect _exe_tlb_uop_WIRE_1.is_rvc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.debug_inst, UInt<32>(0h0) connect _exe_tlb_uop_WIRE_1.inst, UInt<32>(0h0) node _exe_tlb_uop_T_2 = mux(will_fire_hella_incoming[0], _exe_tlb_uop_WIRE, _exe_tlb_uop_WIRE_1) node _exe_tlb_uop_T_3 = mux(_exe_tlb_uop_T_1, retry_queue.io.deq.bits.uop, _exe_tlb_uop_T_2) node _exe_tlb_uop_T_4 = mux(will_fire_store_agen[0], stq_incoming_e[0].bits.uop, _exe_tlb_uop_T_3) node _exe_tlb_uop_T_5 = mux(_exe_tlb_uop_T, ldq_incoming_e[0].bits.uop, _exe_tlb_uop_T_4) wire exe_tlb_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect exe_tlb_uop[0], _exe_tlb_uop_T_5 node _exe_tlb_vaddr_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_tlb_vaddr_T_1 = or(_exe_tlb_vaddr_T, will_fire_store_agen[0]) node _exe_tlb_vaddr_T_2 = or(will_fire_load_retry[0], will_fire_store_retry[0]) node _exe_tlb_vaddr_T_3 = mux(will_fire_hella_incoming[0], hella_req.addr, UInt<1>(0h0)) node _exe_tlb_vaddr_T_4 = mux(_exe_tlb_vaddr_T_2, retry_queue.io.deq.bits.data, _exe_tlb_vaddr_T_3) node _exe_tlb_vaddr_T_5 = mux(will_fire_sfence[0], io.core.sfence.bits.addr, _exe_tlb_vaddr_T_4) node _exe_tlb_vaddr_T_6 = mux(_exe_tlb_vaddr_T_1, io.core.agen[0].bits.data, _exe_tlb_vaddr_T_5) wire exe_tlb_vaddr : UInt<64>[1] connect exe_tlb_vaddr[0], _exe_tlb_vaddr_T_6 node _exe_size_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_size_T_1 = or(_exe_size_T, will_fire_store_agen[0]) node _exe_size_T_2 = or(_exe_size_T_1, will_fire_load_retry[0]) node _exe_size_T_3 = or(_exe_size_T_2, will_fire_store_retry[0]) node _exe_size_T_4 = mux(will_fire_hella_incoming[0], hella_req.size, UInt<1>(0h0)) node _exe_size_T_5 = mux(_exe_size_T_3, exe_tlb_uop[0].mem_size, _exe_size_T_4) wire exe_size : UInt<2>[1] connect exe_size[0], _exe_size_T_5 node _exe_cmd_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_cmd_T_1 = or(_exe_cmd_T, will_fire_store_agen[0]) node _exe_cmd_T_2 = or(_exe_cmd_T_1, will_fire_load_retry[0]) node _exe_cmd_T_3 = or(_exe_cmd_T_2, will_fire_store_retry[0]) node _exe_cmd_T_4 = mux(will_fire_sfence[0], UInt<5>(0h14), UInt<1>(0h0)) node _exe_cmd_T_5 = mux(will_fire_hella_incoming[0], hella_req.cmd, _exe_cmd_T_4) node _exe_cmd_T_6 = mux(_exe_cmd_T_3, exe_tlb_uop[0].mem_cmd, _exe_cmd_T_5) wire exe_cmd : UInt<5>[1] connect exe_cmd[0], _exe_cmd_T_6 node _exe_passthr_T = mux(will_fire_hella_incoming[0], hella_req.phys, UInt<1>(0h0)) wire exe_passthr : UInt<1>[1] connect exe_passthr[0], _exe_passthr_T node _exe_kill_T = mux(will_fire_hella_incoming[0], io.hellacache.s1_kill, UInt<1>(0h0)) wire exe_kill : UInt<1>[1] connect exe_kill[0], _exe_kill_T inst bkptu_0 of BreakpointUnit_8 connect bkptu_0.clock, clock connect bkptu_0.reset, reset connect dtlb.io.req[0].valid, exe_tlb_valid[0] connect dtlb.io.req[0].bits.vaddr, exe_tlb_vaddr[0] connect dtlb.io.req[0].bits.size, exe_size[0] connect dtlb.io.req[0].bits.cmd, exe_cmd[0] connect dtlb.io.req[0].bits.passthrough, exe_passthr[0] connect dtlb.io.req[0].bits.prv, io.ptw.status.prv connect dtlb.io.req[0].bits.v, io.ptw.status.v connect bkptu_0.io.status.uie, io.core.status.uie connect bkptu_0.io.status.sie, io.core.status.sie connect bkptu_0.io.status.hie, io.core.status.hie connect bkptu_0.io.status.mie, io.core.status.mie connect bkptu_0.io.status.upie, io.core.status.upie connect bkptu_0.io.status.spie, io.core.status.spie connect bkptu_0.io.status.ube, io.core.status.ube connect bkptu_0.io.status.mpie, io.core.status.mpie connect bkptu_0.io.status.spp, io.core.status.spp connect bkptu_0.io.status.vs, io.core.status.vs connect bkptu_0.io.status.mpp, io.core.status.mpp connect bkptu_0.io.status.fs, io.core.status.fs connect bkptu_0.io.status.xs, io.core.status.xs connect bkptu_0.io.status.mprv, io.core.status.mprv connect bkptu_0.io.status.sum, io.core.status.sum connect bkptu_0.io.status.mxr, io.core.status.mxr connect bkptu_0.io.status.tvm, io.core.status.tvm connect bkptu_0.io.status.tw, io.core.status.tw connect bkptu_0.io.status.tsr, io.core.status.tsr connect bkptu_0.io.status.zero1, io.core.status.zero1 connect bkptu_0.io.status.sd_rv32, io.core.status.sd_rv32 connect bkptu_0.io.status.uxl, io.core.status.uxl connect bkptu_0.io.status.sxl, io.core.status.sxl connect bkptu_0.io.status.sbe, io.core.status.sbe connect bkptu_0.io.status.mbe, io.core.status.mbe connect bkptu_0.io.status.gva, io.core.status.gva connect bkptu_0.io.status.mpv, io.core.status.mpv connect bkptu_0.io.status.zero2, io.core.status.zero2 connect bkptu_0.io.status.sd, io.core.status.sd connect bkptu_0.io.status.v, io.core.status.v connect bkptu_0.io.status.prv, io.core.status.prv connect bkptu_0.io.status.dv, io.core.status.dv connect bkptu_0.io.status.dprv, io.core.status.dprv connect bkptu_0.io.status.isa, io.core.status.isa connect bkptu_0.io.status.wfi, io.core.status.wfi connect bkptu_0.io.status.cease, io.core.status.cease connect bkptu_0.io.status.debug, io.core.status.debug invalidate bkptu_0.io.pc connect bkptu_0.io.ea, exe_tlb_vaddr[0] connect bkptu_0.io.mcontext, io.core.mcontext connect bkptu_0.io.scontext, io.core.scontext connect dtlb.io.kill, exe_kill[0] connect dtlb.io.sfence.bits.hg, io.core.sfence.bits.hg connect dtlb.io.sfence.bits.hv, io.core.sfence.bits.hv connect dtlb.io.sfence.bits.asid, io.core.sfence.bits.asid connect dtlb.io.sfence.bits.addr, io.core.sfence.bits.addr connect dtlb.io.sfence.bits.rs2, io.core.sfence.bits.rs2 connect dtlb.io.sfence.bits.rs1, io.core.sfence.bits.rs1 connect dtlb.io.sfence.valid, io.core.sfence.valid node _ma_ld_T = and(dtlb.io.resp[0].ma.ld, exe_tlb_uop[0].uses_ldq) wire ma_ld : UInt<1>[1] connect ma_ld[0], _ma_ld_T node _ma_st_T = and(dtlb.io.resp[0].ma.st, exe_tlb_uop[0].uses_stq) node _ma_st_T_1 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _ma_st_T_2 = and(_ma_st_T, _ma_st_T_1) wire ma_st : UInt<1>[1] connect ma_st[0], _ma_st_T_2 node _pf_ld_T = and(dtlb.io.resp[0].pf.ld, exe_tlb_uop[0].uses_ldq) wire pf_ld : UInt<1>[1] connect pf_ld[0], _pf_ld_T node _pf_st_T = and(dtlb.io.resp[0].pf.st, exe_tlb_uop[0].uses_stq) wire pf_st : UInt<1>[1] connect pf_st[0], _pf_st_T node _ae_ld_T = and(dtlb.io.resp[0].ae.ld, exe_tlb_uop[0].uses_ldq) wire ae_ld : UInt<1>[1] connect ae_ld[0], _ae_ld_T node _ae_st_T = and(dtlb.io.resp[0].ae.st, exe_tlb_uop[0].uses_stq) wire ae_st : UInt<1>[1] connect ae_st[0], _ae_st_T node _dbg_bp_T = and(exe_tlb_uop[0].uses_ldq, bkptu_0.io.debug_ld) node _dbg_bp_T_1 = and(exe_tlb_uop[0].uses_stq, bkptu_0.io.debug_st) node _dbg_bp_T_2 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _dbg_bp_T_3 = and(_dbg_bp_T_1, _dbg_bp_T_2) node _dbg_bp_T_4 = or(_dbg_bp_T, _dbg_bp_T_3) node _dbg_bp_T_5 = and(bkptu_0.io.debug_st, _dbg_bp_T_4) wire dbg_bp : UInt<1>[1] connect dbg_bp[0], _dbg_bp_T_5 node _bp_T = and(exe_tlb_uop[0].uses_ldq, bkptu_0.io.xcpt_ld) node _bp_T_1 = and(exe_tlb_uop[0].uses_stq, bkptu_0.io.xcpt_st) node _bp_T_2 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _bp_T_3 = and(_bp_T_1, _bp_T_2) node _bp_T_4 = or(_bp_T, _bp_T_3) node _bp_T_5 = and(bkptu_0.io.debug_st, _bp_T_4) wire bp : UInt<1>[1] connect bp[0], _bp_T_5 node _mem_xcpt_valids_T = or(pf_ld[0], pf_st[0]) node _mem_xcpt_valids_T_1 = or(_mem_xcpt_valids_T, ae_ld[0]) node _mem_xcpt_valids_T_2 = or(_mem_xcpt_valids_T_1, ae_st[0]) node _mem_xcpt_valids_T_3 = or(_mem_xcpt_valids_T_2, ma_ld[0]) node _mem_xcpt_valids_T_4 = or(_mem_xcpt_valids_T_3, ma_st[0]) node _mem_xcpt_valids_T_5 = or(_mem_xcpt_valids_T_4, dbg_bp[0]) node _mem_xcpt_valids_T_6 = or(_mem_xcpt_valids_T_5, bp[0]) node _mem_xcpt_valids_T_7 = and(exe_tlb_valid[0], _mem_xcpt_valids_T_6) node _mem_xcpt_valids_T_8 = and(io.core.brupdate.b1.mispredict_mask, exe_tlb_uop[0].br_mask) node _mem_xcpt_valids_T_9 = neq(_mem_xcpt_valids_T_8, UInt<1>(0h0)) node _mem_xcpt_valids_T_10 = or(_mem_xcpt_valids_T_9, io.core.exception) node _mem_xcpt_valids_T_11 = eq(_mem_xcpt_valids_T_10, UInt<1>(0h0)) node _mem_xcpt_valids_T_12 = and(_mem_xcpt_valids_T_7, _mem_xcpt_valids_T_11) wire _mem_xcpt_valids_WIRE : UInt<1>[1] connect _mem_xcpt_valids_WIRE[0], _mem_xcpt_valids_T_12 reg mem_xcpt_valids : UInt<1>[1], clock connect mem_xcpt_valids, _mem_xcpt_valids_WIRE wire mem_xcpt_uops_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect mem_xcpt_uops_out, exe_tlb_uop[0] node _mem_xcpt_uops_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_xcpt_uops_out_br_mask_T_1 = and(exe_tlb_uop[0].br_mask, _mem_xcpt_uops_out_br_mask_T) connect mem_xcpt_uops_out.br_mask, _mem_xcpt_uops_out_br_mask_T_1 wire _mem_xcpt_uops_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect _mem_xcpt_uops_WIRE[0], mem_xcpt_uops_out reg mem_xcpt_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1], clock connect mem_xcpt_uops, _mem_xcpt_uops_WIRE node _mem_xcpt_causes_T = mux(ae_ld[0], UInt<3>(0h5), UInt<1>(0h0)) node _mem_xcpt_causes_T_1 = mux(ae_st[0], UInt<3>(0h7), _mem_xcpt_causes_T) node _mem_xcpt_causes_T_2 = mux(pf_ld[0], UInt<4>(0hd), _mem_xcpt_causes_T_1) node _mem_xcpt_causes_T_3 = mux(pf_st[0], UInt<4>(0hf), _mem_xcpt_causes_T_2) node _mem_xcpt_causes_T_4 = mux(ma_ld[0], UInt<3>(0h4), _mem_xcpt_causes_T_3) node _mem_xcpt_causes_T_5 = mux(ma_st[0], UInt<3>(0h6), _mem_xcpt_causes_T_4) node _mem_xcpt_causes_T_6 = mux(bp[0], UInt<2>(0h3), _mem_xcpt_causes_T_5) node _mem_xcpt_causes_T_7 = mux(dbg_bp[0], UInt<4>(0he), _mem_xcpt_causes_T_6) wire _mem_xcpt_causes_WIRE : UInt<4>[1] connect _mem_xcpt_causes_WIRE[0], _mem_xcpt_causes_T_7 reg mem_xcpt_causes : UInt<4>[1], clock connect mem_xcpt_causes, _mem_xcpt_causes_WIRE reg mem_xcpt_vaddrs : UInt<64>[1], clock connect mem_xcpt_vaddrs, exe_tlb_vaddr node _T_184 = and(dtlb.io.req[0].valid, exe_tlb_uop[0].is_fence) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: Fence is pretending to talk to the TLB\n at lsu.scala:813 assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), \"Fence is pretending to talk to the TLB\")\n") : printf_19 assert(clock, _T_185, UInt<1>(0h1), "") : assert_19 connect mem_xcpt_valid, mem_xcpt_valids[0] connect mem_xcpt_cause, mem_xcpt_causes[0] connect mem_xcpt_uop, mem_xcpt_uops[0] connect mem_xcpt_vaddr, mem_xcpt_vaddrs[0] node _exe_tlb_miss_T = eq(dtlb.io.req[0].ready, UInt<1>(0h0)) node _exe_tlb_miss_T_1 = or(dtlb.io.resp[0].miss, _exe_tlb_miss_T) node _exe_tlb_miss_T_2 = and(dtlb.io.req[0].valid, _exe_tlb_miss_T_1) wire exe_tlb_miss : UInt<1>[1] connect exe_tlb_miss[0], _exe_tlb_miss_T_2 node _exe_tlb_paddr_T = bits(dtlb.io.resp[0].paddr, 31, 12) node _exe_tlb_paddr_T_1 = bits(exe_tlb_vaddr[0], 11, 0) node _exe_tlb_paddr_T_2 = cat(_exe_tlb_paddr_T, _exe_tlb_paddr_T_1) wire exe_tlb_paddr : UInt<32>[1] connect exe_tlb_paddr[0], _exe_tlb_paddr_T_2 node _exe_tlb_uncacheable_T = eq(dtlb.io.resp[0].cacheable, UInt<1>(0h0)) wire exe_tlb_uncacheable : UInt<1>[1] connect exe_tlb_uncacheable[0], _exe_tlb_uncacheable_T node _T_189 = eq(exe_tlb_paddr[0], dtlb.io.resp[0].paddr) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] paddrs should match.\n at lsu.scala:841 assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr, \"[lsu] paddrs should match.\")\n") : printf_20 assert(clock, _T_189, UInt<1>(0h1), "") : assert_20 when mem_xcpt_valids[0] : node _T_193 = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _T_194 = or(_T_193, will_fire_store_agen[0]) node _T_195 = or(_T_194, will_fire_load_retry[0]) node _T_196 = or(_T_195, will_fire_store_retry[0]) reg REG : UInt<1>, clock connect REG, _T_196 node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(REG, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:845 assert(RegNext(will_fire_load_agen_exec(w) \|\| will_fire_load_agen(w) \|\| will_fire_store_agen(w) \|\|\n") : printf_21 assert(clock, REG, UInt<1>(0h1), "") : assert_21 node _T_200 = xor(mem_xcpt_uops[0].uses_ldq, mem_xcpt_uops[0].uses_stq) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:848 assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)\n") : printf_22 assert(clock, _T_200, UInt<1>(0h1), "") : assert_22 when mem_xcpt_uops[0].uses_ldq : connect ldq_uop[mem_xcpt_uops[0].ldq_idx].exception, UInt<1>(0h1) else : connect stq_uop[mem_xcpt_uops[0].stq_idx].exception, UInt<1>(0h1) node _exe_agen_killed_T = and(io.core.brupdate.b1.mispredict_mask, io.core.agen[0].bits.uop.br_mask) node _exe_agen_killed_T_1 = neq(_exe_agen_killed_T, UInt<1>(0h0)) node _exe_agen_killed_T_2 = or(_exe_agen_killed_T_1, io.core.exception) wire exe_agen_killed : UInt<1>[1] connect exe_agen_killed[0], _exe_agen_killed_T_2 connect io.dmem.brupdate, io.core.brupdate connect io.dmem.exception, io.core.exception connect io.dmem.rob_head_idx, io.core.rob_head_idx connect io.dmem.rob_pnr_idx, io.core.rob_pnr_idx wire dmem_req : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1] connect io.dmem.req.valid, dmem_req[0].valid connect io.dmem.req.bits, dmem_req node _dmem_req_fire_T = and(io.dmem.req.ready, io.dmem.req.valid) node _dmem_req_fire_T_1 = and(dmem_req[0].valid, _dmem_req_fire_T) wire dmem_req_fire : UInt<1>[1] connect dmem_req_fire[0], _dmem_req_fire_T_1 wire _s0_executing_loads_WIRE : UInt<1>[24] connect _s0_executing_loads_WIRE[0], UInt<1>(0h0) connect _s0_executing_loads_WIRE[1], UInt<1>(0h0) connect _s0_executing_loads_WIRE[2], UInt<1>(0h0) connect _s0_executing_loads_WIRE[3], UInt<1>(0h0) connect _s0_executing_loads_WIRE[4], UInt<1>(0h0) connect _s0_executing_loads_WIRE[5], UInt<1>(0h0) connect _s0_executing_loads_WIRE[6], UInt<1>(0h0) connect _s0_executing_loads_WIRE[7], UInt<1>(0h0) connect _s0_executing_loads_WIRE[8], UInt<1>(0h0) connect _s0_executing_loads_WIRE[9], UInt<1>(0h0) connect _s0_executing_loads_WIRE[10], UInt<1>(0h0) connect _s0_executing_loads_WIRE[11], UInt<1>(0h0) connect _s0_executing_loads_WIRE[12], UInt<1>(0h0) connect _s0_executing_loads_WIRE[13], UInt<1>(0h0) connect _s0_executing_loads_WIRE[14], UInt<1>(0h0) connect _s0_executing_loads_WIRE[15], UInt<1>(0h0) connect _s0_executing_loads_WIRE[16], UInt<1>(0h0) connect _s0_executing_loads_WIRE[17], UInt<1>(0h0) connect _s0_executing_loads_WIRE[18], UInt<1>(0h0) connect _s0_executing_loads_WIRE[19], UInt<1>(0h0) connect _s0_executing_loads_WIRE[20], UInt<1>(0h0) connect _s0_executing_loads_WIRE[21], UInt<1>(0h0) connect _s0_executing_loads_WIRE[22], UInt<1>(0h0) connect _s0_executing_loads_WIRE[23], UInt<1>(0h0) wire s0_executing_loads : UInt<1>[24] connect s0_executing_loads, _s0_executing_loads_WIRE wire s0_kills : UInt<1>[1] connect dmem_req[0].valid, UInt<1>(0h0) wire _dmem_req_0_bits_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _dmem_req_0_bits_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_typ, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_rm, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_val, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fcn_op, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.frs3_en, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs3, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs2, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs1, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldst, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_unique, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.uses_stq, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_signed, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_size, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.exc_cause, UInt<64>(0h0) connect _dmem_req_0_bits_uop_WIRE.exception, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.ppred, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs3, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs2, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs1, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.pdst, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.stq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.rob_idx, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.op2_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.op1_sel, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_packed, UInt<20>(0h0) connect _dmem_req_0_bits_uop_WIRE.pimm, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_rename, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.taken, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.pc_lob, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.edge_inst, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_mov, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_rocc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_eret, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_amo, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sfence, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_fencei, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_fence, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sfb, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_type, UInt<4>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_tag, UInt<4>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_mask, UInt<16>(0h0) connect _dmem_req_0_bits_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_pc, UInt<40>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_rvc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_inst, UInt<32>(0h0) connect _dmem_req_0_bits_uop_WIRE.inst, UInt<32>(0h0) connect dmem_req[0].bits.uop, _dmem_req_0_bits_uop_WIRE connect dmem_req[0].bits.addr, UInt<1>(0h0) connect dmem_req[0].bits.data, UInt<1>(0h0) connect dmem_req[0].bits.is_hella, UInt<1>(0h0) connect s0_kills[0], UInt<1>(0h0) node _io_dmem_s1_kill_0_T = and(s0_kills[0], dmem_req_fire[0]) reg io_dmem_s1_kill_0_REG : UInt<1>, clock connect io_dmem_s1_kill_0_REG, _io_dmem_s1_kill_0_T connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG when will_fire_load_agen_exec[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, exe_tlb_paddr[0] connect dmem_req[0].bits.uop, exe_tlb_uop[0] node _s0_kills_0_T = or(exe_tlb_miss[0], exe_tlb_uncacheable[0]) node _s0_kills_0_T_1 = or(_s0_kills_0_T, ma_ld[0]) node _s0_kills_0_T_2 = or(_s0_kills_0_T_1, ae_ld[0]) node _s0_kills_0_T_3 = or(_s0_kills_0_T_2, pf_ld[0]) connect s0_kills[0], _s0_kills_0_T_3 node _s0_executing_loads_T = eq(s0_kills[0], UInt<1>(0h0)) node _s0_executing_loads_T_1 = and(dmem_req_fire[0], _s0_executing_loads_T) connect s0_executing_loads[ldq_incoming_idx[0]], _s0_executing_loads_T_1 node _T_204 = eq(ldq_incoming_e[0].bits.executed, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:903 assert(!ldq_incoming_e(w).bits.executed)\n") : printf_23 assert(clock, _T_204, UInt<1>(0h1), "") : assert_23 else : when will_fire_load_retry[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, exe_tlb_paddr[0] connect dmem_req[0].bits.uop, exe_tlb_uop[0] node _s0_kills_0_T_4 = or(exe_tlb_miss[0], exe_tlb_uncacheable[0]) node _s0_kills_0_T_5 = or(_s0_kills_0_T_4, ma_ld[0]) node _s0_kills_0_T_6 = or(_s0_kills_0_T_5, ae_ld[0]) node _s0_kills_0_T_7 = or(_s0_kills_0_T_6, pf_ld[0]) connect s0_kills[0], _s0_kills_0_T_7 node _s0_executing_loads_T_2 = eq(s0_kills[0], UInt<1>(0h0)) node _s0_executing_loads_T_3 = and(dmem_req_fire[0], _s0_executing_loads_T_2) connect s0_executing_loads[retry_queue.io.deq.bits.uop.ldq_idx], _s0_executing_loads_T_3 else : node _T_208 = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) when _T_208 : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, stq_execute_queue.io.deq.bits.addr.bits wire dmem_req_0_bits_data_size : UInt<2> connect dmem_req_0_bits_data_size, stq_execute_queue.io.deq.bits.uop.mem_size node _dmem_req_0_bits_data_T = eq(dmem_req_0_bits_data_size, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_1 = bits(stq_execute_queue.io.deq.bits.data.bits, 7, 0) node _dmem_req_0_bits_data_T_2 = cat(_dmem_req_0_bits_data_T_1, _dmem_req_0_bits_data_T_1) node _dmem_req_0_bits_data_T_3 = cat(_dmem_req_0_bits_data_T_2, _dmem_req_0_bits_data_T_2) node _dmem_req_0_bits_data_T_4 = cat(_dmem_req_0_bits_data_T_3, _dmem_req_0_bits_data_T_3) node _dmem_req_0_bits_data_T_5 = eq(dmem_req_0_bits_data_size, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_6 = bits(stq_execute_queue.io.deq.bits.data.bits, 15, 0) node _dmem_req_0_bits_data_T_7 = cat(_dmem_req_0_bits_data_T_6, _dmem_req_0_bits_data_T_6) node _dmem_req_0_bits_data_T_8 = cat(_dmem_req_0_bits_data_T_7, _dmem_req_0_bits_data_T_7) node _dmem_req_0_bits_data_T_9 = eq(dmem_req_0_bits_data_size, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_10 = bits(stq_execute_queue.io.deq.bits.data.bits, 31, 0) node _dmem_req_0_bits_data_T_11 = cat(_dmem_req_0_bits_data_T_10, _dmem_req_0_bits_data_T_10) node _dmem_req_0_bits_data_T_12 = mux(_dmem_req_0_bits_data_T_9, _dmem_req_0_bits_data_T_11, stq_execute_queue.io.deq.bits.data.bits) node _dmem_req_0_bits_data_T_13 = mux(_dmem_req_0_bits_data_T_5, _dmem_req_0_bits_data_T_8, _dmem_req_0_bits_data_T_12) node _dmem_req_0_bits_data_T_14 = mux(_dmem_req_0_bits_data_T, _dmem_req_0_bits_data_T_4, _dmem_req_0_bits_data_T_13) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_14 connect dmem_req[0].bits.uop, stq_execute_queue.io.deq.bits.uop node _T_209 = eq(dmem_req_fire[0], UInt<1>(0h0)) when _T_209 : connect stq_execute_queue_flush, UInt<1>(0h1) connect stq_execute_head, stq_execute_queue.io.deq.bits.uop.stq_idx connect stq_succeeded[stq_execute_queue.io.deq.bits.uop.stq_idx], UInt<1>(0h0) else : when will_fire_load_wakeup[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, ldq_wakeup_e.bits.addr.bits connect dmem_req[0].bits.uop, ldq_wakeup_e.bits.uop node _T_210 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _T_211 = bits(_T_210, 4, 0) connect s0_executing_loads[_T_211], dmem_req_fire[0] node _T_212 = eq(ldq_wakeup_e.bits.executed, UInt<1>(0h0)) node _T_213 = eq(ldq_wakeup_e.bits.addr_is_virtual, UInt<1>(0h0)) node _T_214 = and(_T_212, _T_213) node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_T_214, UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:933 assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)\n") : printf_24 assert(clock, _T_214, UInt<1>(0h1), "") : assert_24 else : when will_fire_hella_incoming[0] : node _T_218 = eq(hella_state, UInt<3>(0h1)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:935 assert(hella_state === h_s1)\n") : printf_25 assert(clock, _T_218, UInt<1>(0h1), "") : assert_25 node _dmem_req_0_valid_T = eq(io.hellacache.s1_kill, UInt<1>(0h0)) node _dmem_req_0_valid_T_1 = eq(exe_tlb_miss[0], UInt<1>(0h0)) node _dmem_req_0_valid_T_2 = or(_dmem_req_0_valid_T_1, hella_req.phys) node _dmem_req_0_valid_T_3 = and(_dmem_req_0_valid_T, _dmem_req_0_valid_T_2) connect dmem_req[0].valid, _dmem_req_0_valid_T_3 connect dmem_req[0].bits.addr, exe_tlb_paddr[0] wire dmem_req_0_bits_data_size_1 : UInt<2> connect dmem_req_0_bits_data_size_1, hella_req.size node _dmem_req_0_bits_data_T_15 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_16 = bits(io.hellacache.s1_data.data, 7, 0) node _dmem_req_0_bits_data_T_17 = cat(_dmem_req_0_bits_data_T_16, _dmem_req_0_bits_data_T_16) node _dmem_req_0_bits_data_T_18 = cat(_dmem_req_0_bits_data_T_17, _dmem_req_0_bits_data_T_17) node _dmem_req_0_bits_data_T_19 = cat(_dmem_req_0_bits_data_T_18, _dmem_req_0_bits_data_T_18) node _dmem_req_0_bits_data_T_20 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_21 = bits(io.hellacache.s1_data.data, 15, 0) node _dmem_req_0_bits_data_T_22 = cat(_dmem_req_0_bits_data_T_21, _dmem_req_0_bits_data_T_21) node _dmem_req_0_bits_data_T_23 = cat(_dmem_req_0_bits_data_T_22, _dmem_req_0_bits_data_T_22) node _dmem_req_0_bits_data_T_24 = eq(dmem_req_0_bits_data_size_1, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_25 = bits(io.hellacache.s1_data.data, 31, 0) node _dmem_req_0_bits_data_T_26 = cat(_dmem_req_0_bits_data_T_25, _dmem_req_0_bits_data_T_25) node _dmem_req_0_bits_data_T_27 = mux(_dmem_req_0_bits_data_T_24, _dmem_req_0_bits_data_T_26, io.hellacache.s1_data.data) node _dmem_req_0_bits_data_T_28 = mux(_dmem_req_0_bits_data_T_20, _dmem_req_0_bits_data_T_23, _dmem_req_0_bits_data_T_27) node _dmem_req_0_bits_data_T_29 = mux(_dmem_req_0_bits_data_T_15, _dmem_req_0_bits_data_T_19, _dmem_req_0_bits_data_T_28) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_29 connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd connect dmem_req[0].bits.uop.mem_size, hella_req.size connect dmem_req[0].bits.uop.mem_signed, hella_req.signed connect dmem_req[0].bits.is_hella, UInt<1>(0h1) connect hella_paddr, exe_tlb_paddr[0] else : when will_fire_hella_wakeup[0] : node _T_222 = eq(hella_state, UInt<3>(0h5)) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:952 assert(hella_state === h_replay)\n") : printf_26 assert(clock, _T_222, UInt<1>(0h1), "") : assert_26 connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, hella_paddr wire dmem_req_0_bits_data_size_2 : UInt<2> connect dmem_req_0_bits_data_size_2, hella_req.size node _dmem_req_0_bits_data_T_30 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_31 = bits(hella_data.data, 7, 0) node _dmem_req_0_bits_data_T_32 = cat(_dmem_req_0_bits_data_T_31, _dmem_req_0_bits_data_T_31) node _dmem_req_0_bits_data_T_33 = cat(_dmem_req_0_bits_data_T_32, _dmem_req_0_bits_data_T_32) node _dmem_req_0_bits_data_T_34 = cat(_dmem_req_0_bits_data_T_33, _dmem_req_0_bits_data_T_33) node _dmem_req_0_bits_data_T_35 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_36 = bits(hella_data.data, 15, 0) node _dmem_req_0_bits_data_T_37 = cat(_dmem_req_0_bits_data_T_36, _dmem_req_0_bits_data_T_36) node _dmem_req_0_bits_data_T_38 = cat(_dmem_req_0_bits_data_T_37, _dmem_req_0_bits_data_T_37) node _dmem_req_0_bits_data_T_39 = eq(dmem_req_0_bits_data_size_2, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_40 = bits(hella_data.data, 31, 0) node _dmem_req_0_bits_data_T_41 = cat(_dmem_req_0_bits_data_T_40, _dmem_req_0_bits_data_T_40) node _dmem_req_0_bits_data_T_42 = mux(_dmem_req_0_bits_data_T_39, _dmem_req_0_bits_data_T_41, hella_data.data) node _dmem_req_0_bits_data_T_43 = mux(_dmem_req_0_bits_data_T_35, _dmem_req_0_bits_data_T_38, _dmem_req_0_bits_data_T_42) node _dmem_req_0_bits_data_T_44 = mux(_dmem_req_0_bits_data_T_30, _dmem_req_0_bits_data_T_34, _dmem_req_0_bits_data_T_43) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_44 connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd connect dmem_req[0].bits.uop.mem_size, hella_req.size connect dmem_req[0].bits.uop.mem_signed, hella_req.signed connect dmem_req[0].bits.is_hella, UInt<1>(0h1) node _T_226 = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) node _T_227 = or(_T_226, will_fire_load_retry[0]) when _T_227 : node _ldq_idx_T = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) node ldq_idx = mux(_ldq_idx_T, ldq_incoming_idx[0], retry_queue.io.deq.bits.uop.ldq_idx) node _ldq_addr_valid_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _ldq_addr_valid_T_1 = or(_ldq_addr_valid_T, will_fire_load_retry[0]) connect ldq_addr[ldq_idx].valid, _ldq_addr_valid_T_1 node _ldq_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0]) connect ldq_addr[ldq_idx].bits, _ldq_addr_bits_T wire ldq_ld_byte_mask_mask : UInt<8> node _ldq_ld_byte_mask_mask_T = eq(exe_tlb_uop[0].mem_size, UInt<1>(0h0)) node _ldq_ld_byte_mask_mask_T_1 = bits(exe_tlb_vaddr[0], 2, 0) node _ldq_ld_byte_mask_mask_T_2 = dshl(UInt<8>(0h1), _ldq_ld_byte_mask_mask_T_1) node _ldq_ld_byte_mask_mask_T_3 = eq(exe_tlb_uop[0].mem_size, UInt<1>(0h1)) node _ldq_ld_byte_mask_mask_T_4 = bits(exe_tlb_vaddr[0], 2, 1) node _ldq_ld_byte_mask_mask_T_5 = dshl(_ldq_ld_byte_mask_mask_T_4, UInt<1>(0h1)) node _ldq_ld_byte_mask_mask_T_6 = dshl(UInt<8>(0h3), _ldq_ld_byte_mask_mask_T_5) node _ldq_ld_byte_mask_mask_T_7 = eq(exe_tlb_uop[0].mem_size, UInt<2>(0h2)) node _ldq_ld_byte_mask_mask_T_8 = bits(exe_tlb_vaddr[0], 2, 2) node _ldq_ld_byte_mask_mask_T_9 = mux(_ldq_ld_byte_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _ldq_ld_byte_mask_mask_T_10 = eq(exe_tlb_uop[0].mem_size, UInt<2>(0h3)) node _ldq_ld_byte_mask_mask_T_11 = mux(_ldq_ld_byte_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _ldq_ld_byte_mask_mask_T_12 = mux(_ldq_ld_byte_mask_mask_T_7, _ldq_ld_byte_mask_mask_T_9, _ldq_ld_byte_mask_mask_T_11) node _ldq_ld_byte_mask_mask_T_13 = mux(_ldq_ld_byte_mask_mask_T_3, _ldq_ld_byte_mask_mask_T_6, _ldq_ld_byte_mask_mask_T_12) node _ldq_ld_byte_mask_mask_T_14 = mux(_ldq_ld_byte_mask_mask_T, _ldq_ld_byte_mask_mask_T_2, _ldq_ld_byte_mask_mask_T_13) connect ldq_ld_byte_mask_mask, _ldq_ld_byte_mask_mask_T_14 connect ldq_ld_byte_mask[ldq_idx], ldq_ld_byte_mask_mask connect ldq_uop[ldq_idx].pdst, exe_tlb_uop[0].pdst connect ldq_addr_is_virtual[ldq_idx], exe_tlb_miss[0] node _ldq_addr_is_uncacheable_T = eq(exe_tlb_miss[0], UInt<1>(0h0)) node _ldq_addr_is_uncacheable_T_1 = and(exe_tlb_uncacheable[0], _ldq_addr_is_uncacheable_T) connect ldq_addr_is_uncacheable[ldq_idx], _ldq_addr_is_uncacheable_T_1 node _T_228 = eq(ldq_addr[ldq_idx].valid, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Translating load is overwriting a valid address\n at lsu.scala:977 assert(!ldq_addr(ldq_idx).valid,\n") : printf_27 assert(clock, _T_228, UInt<1>(0h1), "") : assert_27 node _T_232 = or(will_fire_store_agen[0], will_fire_store_retry[0]) when _T_232 : node stq_idx = mux(will_fire_store_agen[0], stq_incoming_idx[0], retry_queue.io.deq.bits.uop.stq_idx) node _stq_addr_valid_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _stq_addr_valid_T_1 = or(_stq_addr_valid_T, will_fire_store_retry[0]) node _stq_addr_valid_T_2 = eq(pf_st[0], UInt<1>(0h0)) node _stq_addr_valid_T_3 = and(_stq_addr_valid_T_1, _stq_addr_valid_T_2) connect stq_addr[stq_idx].valid, _stq_addr_valid_T_3 node _stq_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0]) connect stq_addr[stq_idx].bits, _stq_addr_bits_T connect stq_uop[stq_idx].pdst, exe_tlb_uop[0].pdst connect stq_addr_is_virtual[stq_idx], exe_tlb_miss[0] node _T_233 = eq(stq_addr[stq_idx].valid, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Translating store is overwriting a valid address\n at lsu.scala:991 assert(!stq_addr(stq_idx).valid,\n") : printf_28 assert(clock, _T_233, UInt<1>(0h1), "") : assert_28 when io.core.dgen[0].valid : connect stq_data[io.core.dgen[0].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[0].bits.uop.stq_idx].bits, io.core.dgen[0].bits.data node _T_237 = eq(stq_data[io.core.dgen[0].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_238 = eq(stq_data[io.core.dgen[0].bits.uop.stq_idx].bits, io.core.dgen[0].bits.data) node _T_239 = or(_T_237, _T_238) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid \|\| (stq_data(sidx).bits === dgen.bits.data))\n") : printf_29 assert(clock, _T_239, UInt<1>(0h1), "") : assert_29 when io.core.dgen[1].valid : connect stq_data[io.core.dgen[1].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[1].bits.uop.stq_idx].bits, io.core.dgen[1].bits.data node _T_243 = eq(stq_data[io.core.dgen[1].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_244 = eq(stq_data[io.core.dgen[1].bits.uop.stq_idx].bits, io.core.dgen[1].bits.data) node _T_245 = or(_T_243, _T_244) node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(_T_245, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid \|\| (stq_data(sidx).bits === dgen.bits.data))\n") : printf_30 assert(clock, _T_245, UInt<1>(0h1), "") : assert_30 when io.core.dgen[2].valid : connect stq_data[io.core.dgen[2].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[2].bits.uop.stq_idx].bits, io.core.dgen[2].bits.data node _T_249 = eq(stq_data[io.core.dgen[2].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_250 = eq(stq_data[io.core.dgen[2].bits.uop.stq_idx].bits, io.core.dgen[2].bits.data) node _T_251 = or(_T_249, _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid \|\| (stq_data(sidx).bits === dgen.bits.data))\n") : printf_31 assert(clock, _T_251, UInt<1>(0h1), "") : assert_31 inst wakeupArbs_0 of Arbiter2_Wakeup connect wakeupArbs_0.clock, clock connect wakeupArbs_0.reset, reset connect wakeupArbs_0.io.out.ready, UInt<1>(0h1) invalidate wakeupArbs_0.io.in[0].bits.rebusy invalidate wakeupArbs_0.io.in[0].bits.speculative_mask invalidate wakeupArbs_0.io.in[0].bits.bypassable invalidate wakeupArbs_0.io.in[0].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[0].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[0].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[0].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[0].bits.uop.fp_val invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[0].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[0].bits.uop.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[0].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[0].bits.uop.is_unique invalidate wakeupArbs_0.io.in[0].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[0].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[0].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[0].bits.uop.mem_size invalidate wakeupArbs_0.io.in[0].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[0].bits.uop.exception invalidate wakeupArbs_0.io.in[0].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[0].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[0].bits.uop.ppred invalidate wakeupArbs_0.io.in[0].bits.uop.prs3 invalidate wakeupArbs_0.io.in[0].bits.uop.prs2 invalidate wakeupArbs_0.io.in[0].bits.uop.prs1 invalidate wakeupArbs_0.io.in[0].bits.uop.pdst invalidate wakeupArbs_0.io.in[0].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[0].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[0].bits.uop.pimm invalidate wakeupArbs_0.io.in[0].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[0].bits.uop.taken invalidate wakeupArbs_0.io.in[0].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[0].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[0].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.is_mov invalidate wakeupArbs_0.io.in[0].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[0].bits.uop.is_eret invalidate wakeupArbs_0.io.in[0].bits.uop.is_amo invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[0].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[0].bits.uop.is_fence invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[0].bits.uop.br_type invalidate wakeupArbs_0.io.in[0].bits.uop.br_tag invalidate wakeupArbs_0.io.in[0].bits.uop.br_mask invalidate wakeupArbs_0.io.in[0].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[0].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[0].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[0].bits.uop.inst invalidate wakeupArbs_0.io.in[0].valid invalidate wakeupArbs_0.io.in[0].ready invalidate wakeupArbs_0.io.in[1].bits.rebusy invalidate wakeupArbs_0.io.in[1].bits.speculative_mask invalidate wakeupArbs_0.io.in[1].bits.bypassable invalidate wakeupArbs_0.io.in[1].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[1].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[1].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[1].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[1].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[1].bits.uop.fp_val invalidate wakeupArbs_0.io.in[1].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[1].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[1].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[1].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[1].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[1].bits.uop.ldst invalidate wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[1].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[1].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[1].bits.uop.is_unique invalidate wakeupArbs_0.io.in[1].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[1].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[1].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[1].bits.uop.mem_size invalidate wakeupArbs_0.io.in[1].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[1].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[1].bits.uop.exception invalidate wakeupArbs_0.io.in[1].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[1].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[1].bits.uop.ppred invalidate wakeupArbs_0.io.in[1].bits.uop.prs3 invalidate wakeupArbs_0.io.in[1].bits.uop.prs2 invalidate wakeupArbs_0.io.in[1].bits.uop.prs1 invalidate wakeupArbs_0.io.in[1].bits.uop.pdst invalidate wakeupArbs_0.io.in[1].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[1].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[1].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[1].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[1].bits.uop.pimm invalidate wakeupArbs_0.io.in[1].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[1].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[1].bits.uop.taken invalidate wakeupArbs_0.io.in[1].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[1].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[1].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.is_mov invalidate wakeupArbs_0.io.in[1].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[1].bits.uop.is_eret invalidate wakeupArbs_0.io.in[1].bits.uop.is_amo invalidate wakeupArbs_0.io.in[1].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[1].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[1].bits.uop.is_fence invalidate wakeupArbs_0.io.in[1].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[1].bits.uop.br_type invalidate wakeupArbs_0.io.in[1].bits.uop.br_tag invalidate wakeupArbs_0.io.in[1].bits.uop.br_mask invalidate wakeupArbs_0.io.in[1].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[1].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[1].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[1].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[1].bits.uop.inst invalidate wakeupArbs_0.io.in[1].valid invalidate wakeupArbs_0.io.in[1].ready connect io.core.iwakeups[0].bits, wakeupArbs_0.io.out.bits connect io.core.iwakeups[0].valid, wakeupArbs_0.io.out.valid node _fired_load_agen_exec_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_load_agen_exec_T_1 = and(will_fire_load_agen_exec[0], _fired_load_agen_exec_T) reg fired_load_agen_exec_REG : UInt<1>, clock connect fired_load_agen_exec_REG, _fired_load_agen_exec_T_1 wire fired_load_agen_exec : UInt<1>[1] connect fired_load_agen_exec[0], fired_load_agen_exec_REG node _fired_load_agen_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_load_agen_T_1 = and(will_fire_load_agen[0], _fired_load_agen_T) reg fired_load_agen_REG : UInt<1>, clock connect fired_load_agen_REG, _fired_load_agen_T_1 wire fired_load_agen : UInt<1>[1] connect fired_load_agen[0], fired_load_agen_REG node _fired_store_agen_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_store_agen_T_1 = and(will_fire_store_agen[0], _fired_store_agen_T) reg fired_store_agen_REG : UInt<1>, clock connect fired_store_agen_REG, _fired_store_agen_T_1 wire fired_store_agen : UInt<1>[1] connect fired_store_agen[0], fired_store_agen_REG reg fired_sfence : UInt<1>[1], clock connect fired_sfence, will_fire_sfence reg fired_release : UInt<1>[1], clock connect fired_release, will_fire_release node _fired_load_retry_T = and(io.core.brupdate.b1.mispredict_mask, retry_queue.io.deq.bits.uop.br_mask) node _fired_load_retry_T_1 = neq(_fired_load_retry_T, UInt<1>(0h0)) node _fired_load_retry_T_2 = or(_fired_load_retry_T_1, io.core.exception) node _fired_load_retry_T_3 = eq(_fired_load_retry_T_2, UInt<1>(0h0)) node _fired_load_retry_T_4 = and(will_fire_load_retry[0], _fired_load_retry_T_3) reg fired_load_retry_REG : UInt<1>, clock connect fired_load_retry_REG, _fired_load_retry_T_4 wire fired_load_retry : UInt<1>[1] connect fired_load_retry[0], fired_load_retry_REG node _fired_store_retry_T = and(io.core.brupdate.b1.mispredict_mask, retry_queue.io.deq.bits.uop.br_mask) node _fired_store_retry_T_1 = neq(_fired_store_retry_T, UInt<1>(0h0)) node _fired_store_retry_T_2 = or(_fired_store_retry_T_1, io.core.exception) node _fired_store_retry_T_3 = eq(_fired_store_retry_T_2, UInt<1>(0h0)) node _fired_store_retry_T_4 = and(will_fire_store_retry[0], _fired_store_retry_T_3) reg fired_store_retry_REG : UInt<1>, clock connect fired_store_retry_REG, _fired_store_retry_T_4 wire fired_store_retry : UInt<1>[1] connect fired_store_retry[0], fired_store_retry_REG node _fired_store_commit_T = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) reg fired_store_commit_REG : UInt<1>, clock connect fired_store_commit_REG, _fired_store_commit_T wire fired_store_commit : UInt<1>[1] connect fired_store_commit[0], fired_store_commit_REG node _fired_load_wakeup_T = and(io.core.brupdate.b1.mispredict_mask, ldq_wakeup_e.bits.uop.br_mask) node _fired_load_wakeup_T_1 = neq(_fired_load_wakeup_T, UInt<1>(0h0)) node _fired_load_wakeup_T_2 = or(_fired_load_wakeup_T_1, io.core.exception) node _fired_load_wakeup_T_3 = eq(_fired_load_wakeup_T_2, UInt<1>(0h0)) node _fired_load_wakeup_T_4 = and(will_fire_load_wakeup[0], _fired_load_wakeup_T_3) reg fired_load_wakeup_REG : UInt<1>, clock connect fired_load_wakeup_REG, _fired_load_wakeup_T_4 wire fired_load_wakeup : UInt<1>[1] connect fired_load_wakeup[0], fired_load_wakeup_REG reg fired_hella_incoming : UInt<1>[1], clock connect fired_hella_incoming, will_fire_hella_incoming reg fired_hella_wakeup : UInt<1>[1], clock connect fired_hella_wakeup, will_fire_hella_wakeup wire mem_incoming_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect mem_incoming_uop_out, io.core.agen[0].bits.uop node _mem_incoming_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_incoming_uop_out_br_mask_T_1 = and(io.core.agen[0].bits.uop.br_mask, _mem_incoming_uop_out_br_mask_T) connect mem_incoming_uop_out.br_mask, _mem_incoming_uop_out_br_mask_T_1 wire _mem_incoming_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect _mem_incoming_uop_WIRE[0], mem_incoming_uop_out reg mem_incoming_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1], clock connect mem_incoming_uop, _mem_incoming_uop_WIRE wire mem_ldq_incoming_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_incoming_e_out, ldq_incoming_e[0] node _mem_ldq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = and(ldq_incoming_e[0].bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T) connect mem_ldq_incoming_e_out.bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 node _mem_ldq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq_incoming_e[0].bits.uop.br_mask) node _mem_ldq_incoming_e_out_valid_T_1 = neq(_mem_ldq_incoming_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_incoming_e_out_valid_T_2 = or(_mem_ldq_incoming_e_out_valid_T_1, io.core.exception) node _mem_ldq_incoming_e_out_valid_T_3 = eq(_mem_ldq_incoming_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_incoming_e_out_valid_T_4 = and(ldq_incoming_e[0].valid, _mem_ldq_incoming_e_out_valid_T_3) connect mem_ldq_incoming_e_out.valid, _mem_ldq_incoming_e_out_valid_T_4 wire _mem_ldq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect _mem_ldq_incoming_e_WIRE[0], mem_ldq_incoming_e_out reg mem_ldq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1], clock connect mem_ldq_incoming_e, _mem_ldq_incoming_e_WIRE wire mem_stq_incoming_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_incoming_e_out, stq_incoming_e[0] node _mem_stq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = and(stq_incoming_e[0].bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T) connect mem_stq_incoming_e_out.bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 node _mem_stq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, stq_incoming_e[0].bits.uop.br_mask) node _mem_stq_incoming_e_out_valid_T_1 = neq(_mem_stq_incoming_e_out_valid_T, UInt<1>(0h0)) node _mem_stq_incoming_e_out_valid_T_2 = or(_mem_stq_incoming_e_out_valid_T_1, io.core.exception) node _mem_stq_incoming_e_out_valid_T_3 = eq(_mem_stq_incoming_e_out_valid_T_2, UInt<1>(0h0)) node _mem_stq_incoming_e_out_valid_T_4 = and(stq_incoming_e[0].valid, _mem_stq_incoming_e_out_valid_T_3) connect mem_stq_incoming_e_out.valid, _mem_stq_incoming_e_out_valid_T_4 wire _mem_stq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect _mem_stq_incoming_e_WIRE[0], mem_stq_incoming_e_out reg mem_stq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1], clock connect mem_stq_incoming_e, _mem_stq_incoming_e_WIRE wire mem_ldq_wakeup_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_wakeup_e_out, ldq_wakeup_e node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = and(ldq_wakeup_e.bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T) connect mem_ldq_wakeup_e_out.bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 node _mem_ldq_wakeup_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq_wakeup_e.bits.uop.br_mask) node _mem_ldq_wakeup_e_out_valid_T_1 = neq(_mem_ldq_wakeup_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_wakeup_e_out_valid_T_2 = or(_mem_ldq_wakeup_e_out_valid_T_1, io.core.exception) node _mem_ldq_wakeup_e_out_valid_T_3 = eq(_mem_ldq_wakeup_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_wakeup_e_out_valid_T_4 = and(ldq_wakeup_e.valid, _mem_ldq_wakeup_e_out_valid_T_3) connect mem_ldq_wakeup_e_out.valid, _mem_ldq_wakeup_e_out_valid_T_4 reg mem_ldq_wakeup_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock connect mem_ldq_wakeup_e, mem_ldq_wakeup_e_out wire mem_ldq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_retry_e_e.valid, ldq_valid[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.uop, ldq_uop[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr, ldq_addr[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.executed, ldq_executed[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.succeeded, ldq_succeeded[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.order_fail, ldq_order_fail[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.observed, ldq_observed[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.st_dep_mask, ldq_st_dep_mask[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.forward_std_val, ldq_forward_std_val[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.debug_wb_data, ldq_debug_wb_data[retry_queue.io.deq.bits.uop.ldq_idx] wire mem_ldq_retry_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_retry_e_out, mem_ldq_retry_e_e node _mem_ldq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = and(mem_ldq_retry_e_e.bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T) connect mem_ldq_retry_e_out.bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 node _mem_ldq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, mem_ldq_retry_e_e.bits.uop.br_mask) node _mem_ldq_retry_e_out_valid_T_1 = neq(_mem_ldq_retry_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_retry_e_out_valid_T_2 = or(_mem_ldq_retry_e_out_valid_T_1, io.core.exception) node _mem_ldq_retry_e_out_valid_T_3 = eq(_mem_ldq_retry_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_retry_e_out_valid_T_4 = and(mem_ldq_retry_e_e.valid, _mem_ldq_retry_e_out_valid_T_3) connect mem_ldq_retry_e_out.valid, _mem_ldq_retry_e_out_valid_T_4 reg mem_ldq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock connect mem_ldq_retry_e, mem_ldq_retry_e_out wire mem_stq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_retry_e_e.valid, stq_valid[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.uop, stq_uop[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.addr, stq_addr[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.addr_is_virtual, stq_addr_is_virtual[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.data, stq_data[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.committed, stq_committed[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.succeeded, stq_succeeded[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.can_execute, stq_can_execute[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.cleared, stq_cleared[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.debug_wb_data, stq_debug_wb_data[retry_queue.io.deq.bits.uop.stq_idx] wire mem_stq_retry_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_retry_e_out, mem_stq_retry_e_e node _mem_stq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = and(mem_stq_retry_e_e.bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T) connect mem_stq_retry_e_out.bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T_1 node _mem_stq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, mem_stq_retry_e_e.bits.uop.br_mask) node _mem_stq_retry_e_out_valid_T_1 = neq(_mem_stq_retry_e_out_valid_T, UInt<1>(0h0)) node _mem_stq_retry_e_out_valid_T_2 = or(_mem_stq_retry_e_out_valid_T_1, io.core.exception) node _mem_stq_retry_e_out_valid_T_3 = eq(_mem_stq_retry_e_out_valid_T_2, UInt<1>(0h0)) node _mem_stq_retry_e_out_valid_T_4 = and(mem_stq_retry_e_e.valid, _mem_stq_retry_e_out_valid_T_3) connect mem_stq_retry_e_out.valid, _mem_stq_retry_e_out_valid_T_4 reg mem_stq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}, clock connect mem_stq_retry_e, mem_stq_retry_e_out node _mem_ldq_e_T = or(fired_load_agen[0], fired_load_agen_exec[0]) wire _mem_ldq_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect _mem_ldq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0) connect _mem_ldq_e_WIRE.bits.forward_stq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.forward_std_val, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.ld_byte_mask, UInt<8>(0h0) connect _mem_ldq_e_WIRE.bits.st_dep_mask, UInt<24>(0h0) connect _mem_ldq_e_WIRE.bits.observed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.order_fail, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.succeeded, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.executed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr_is_uncacheable, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr.bits, UInt<40>(0h0) connect _mem_ldq_e_WIRE.bits.addr.valid, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_tsrc, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_fsrc, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_typ, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_rm, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fcn_op, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fcn_dw, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldst, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.csr_cmd, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0) connect _mem_ldq_e_WIRE.bits.uop.exception, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ppred, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs3, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs2, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs1, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pdst, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.vec, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.wflags, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.sqrt, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.div, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fma, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fastpipe, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.toint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fromint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.swap23, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.swap12, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren3, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren2, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren1, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.wen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ldst, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.op2_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.op1_sel, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pimm, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_rename, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.taken, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_mov, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_rocc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_eret, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sfence, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_type, UInt<4>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0) connect _mem_ldq_e_WIRE.bits.uop.dis_col_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p3_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p2_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p1_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p2_speculative_child, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p1_speculative_child, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued_partial_dgen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued_partial_agen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[0], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[1], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[2], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[3], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[4], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[5], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[6], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[7], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[8], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[9], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[0], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[1], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[2], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[3], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0) connect _mem_ldq_e_WIRE.bits.uop.inst, UInt<32>(0h0) connect _mem_ldq_e_WIRE.valid, UInt<1>(0h0) node _mem_ldq_e_T_1 = mux(fired_load_wakeup[0], mem_ldq_wakeup_e, _mem_ldq_e_WIRE) node _mem_ldq_e_T_2 = mux(fired_load_retry[0], mem_ldq_retry_e, _mem_ldq_e_T_1) node _mem_ldq_e_T_3 = mux(_mem_ldq_e_T, mem_ldq_incoming_e[0], _mem_ldq_e_T_2) wire mem_ldq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect mem_ldq_e[0], _mem_ldq_e_T_3 wire _mem_stq_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect _mem_stq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.cleared, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.can_execute, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.succeeded, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.committed, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.data.bits, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.data.valid, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.addr.bits, UInt<40>(0h0) connect _mem_stq_e_WIRE.bits.addr.valid, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_tsrc, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_fsrc, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_typ, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_rm, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fcn_op, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.fcn_dw, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldst, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.csr_cmd, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.uop.exception, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.ppred, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs3, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs2, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs1, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.pdst, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.vec, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.wflags, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.sqrt, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.div, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fma, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fastpipe, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.toint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fromint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.swap23, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.swap12, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren3, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren2, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren1, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.wen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ldst, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.op2_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.op1_sel, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0) connect _mem_stq_e_WIRE.bits.uop.pimm, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_rename, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.taken, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_mov, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_rocc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_eret, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sfence, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_type, UInt<4>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0) connect _mem_stq_e_WIRE.bits.uop.dis_col_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p3_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p2_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p1_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p2_speculative_child, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p1_speculative_child, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued_partial_dgen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued_partial_agen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[0], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[1], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[2], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[3], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[4], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[5], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[6], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[7], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[8], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[9], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[0], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[1], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[2], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[3], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0) connect _mem_stq_e_WIRE.bits.uop.inst, UInt<32>(0h0) connect _mem_stq_e_WIRE.valid, UInt<1>(0h0) node _mem_stq_e_T = mux(fired_store_retry[0], mem_stq_retry_e, _mem_stq_e_WIRE) node _mem_stq_e_T_1 = mux(fired_store_agen[0], mem_stq_incoming_e[0], _mem_stq_e_T) wire mem_stq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect mem_stq_e[0], _mem_stq_e_T_1 reg mem_tlb_miss : UInt<1>[1], clock connect mem_tlb_miss, exe_tlb_miss reg mem_tlb_uncacheable : UInt<1>[1], clock connect mem_tlb_uncacheable, exe_tlb_uncacheable wire _mem_paddr_WIRE : UInt<40>[1] connect _mem_paddr_WIRE[0], dmem_req[0].bits.addr reg mem_paddr : UInt<40>[1], clock connect mem_paddr, _mem_paddr_WIRE node _stq_clr_head_idx_T = eq(stq_cleared[0], UInt<1>(0h0)) node _stq_clr_head_idx_T_1 = and(stq_valid[0], _stq_clr_head_idx_T) node _stq_clr_head_idx_T_2 = eq(stq_cleared[1], UInt<1>(0h0)) node _stq_clr_head_idx_T_3 = and(stq_valid[1], _stq_clr_head_idx_T_2) node _stq_clr_head_idx_T_4 = eq(stq_cleared[2], UInt<1>(0h0)) node _stq_clr_head_idx_T_5 = and(stq_valid[2], _stq_clr_head_idx_T_4) node _stq_clr_head_idx_T_6 = eq(stq_cleared[3], UInt<1>(0h0)) node _stq_clr_head_idx_T_7 = and(stq_valid[3], _stq_clr_head_idx_T_6) node _stq_clr_head_idx_T_8 = eq(stq_cleared[4], UInt<1>(0h0)) node _stq_clr_head_idx_T_9 = and(stq_valid[4], _stq_clr_head_idx_T_8) node _stq_clr_head_idx_T_10 = eq(stq_cleared[5], UInt<1>(0h0)) node _stq_clr_head_idx_T_11 = and(stq_valid[5], _stq_clr_head_idx_T_10) node _stq_clr_head_idx_T_12 = eq(stq_cleared[6], UInt<1>(0h0)) node _stq_clr_head_idx_T_13 = and(stq_valid[6], _stq_clr_head_idx_T_12) node _stq_clr_head_idx_T_14 = eq(stq_cleared[7], UInt<1>(0h0)) node _stq_clr_head_idx_T_15 = and(stq_valid[7], _stq_clr_head_idx_T_14) node _stq_clr_head_idx_T_16 = eq(stq_cleared[8], UInt<1>(0h0)) node _stq_clr_head_idx_T_17 = and(stq_valid[8], _stq_clr_head_idx_T_16) node _stq_clr_head_idx_T_18 = eq(stq_cleared[9], UInt<1>(0h0)) node _stq_clr_head_idx_T_19 = and(stq_valid[9], _stq_clr_head_idx_T_18) node _stq_clr_head_idx_T_20 = eq(stq_cleared[10], UInt<1>(0h0)) node _stq_clr_head_idx_T_21 = and(stq_valid[10], _stq_clr_head_idx_T_20) node _stq_clr_head_idx_T_22 = eq(stq_cleared[11], UInt<1>(0h0)) node _stq_clr_head_idx_T_23 = and(stq_valid[11], _stq_clr_head_idx_T_22) node _stq_clr_head_idx_T_24 = eq(stq_cleared[12], UInt<1>(0h0)) node _stq_clr_head_idx_T_25 = and(stq_valid[12], _stq_clr_head_idx_T_24) node _stq_clr_head_idx_T_26 = eq(stq_cleared[13], UInt<1>(0h0)) node _stq_clr_head_idx_T_27 = and(stq_valid[13], _stq_clr_head_idx_T_26) node _stq_clr_head_idx_T_28 = eq(stq_cleared[14], UInt<1>(0h0)) node _stq_clr_head_idx_T_29 = and(stq_valid[14], _stq_clr_head_idx_T_28) node _stq_clr_head_idx_T_30 = eq(stq_cleared[15], UInt<1>(0h0)) node _stq_clr_head_idx_T_31 = and(stq_valid[15], _stq_clr_head_idx_T_30) node _stq_clr_head_idx_T_32 = eq(stq_cleared[16], UInt<1>(0h0)) node _stq_clr_head_idx_T_33 = and(stq_valid[16], _stq_clr_head_idx_T_32) node _stq_clr_head_idx_T_34 = eq(stq_cleared[17], UInt<1>(0h0)) node _stq_clr_head_idx_T_35 = and(stq_valid[17], _stq_clr_head_idx_T_34) node _stq_clr_head_idx_T_36 = eq(stq_cleared[18], UInt<1>(0h0)) node _stq_clr_head_idx_T_37 = and(stq_valid[18], _stq_clr_head_idx_T_36) node _stq_clr_head_idx_T_38 = eq(stq_cleared[19], UInt<1>(0h0)) node _stq_clr_head_idx_T_39 = and(stq_valid[19], _stq_clr_head_idx_T_38) node _stq_clr_head_idx_T_40 = eq(stq_cleared[20], UInt<1>(0h0)) node _stq_clr_head_idx_T_41 = and(stq_valid[20], _stq_clr_head_idx_T_40) node _stq_clr_head_idx_T_42 = eq(stq_cleared[21], UInt<1>(0h0)) node _stq_clr_head_idx_T_43 = and(stq_valid[21], _stq_clr_head_idx_T_42) node _stq_clr_head_idx_T_44 = eq(stq_cleared[22], UInt<1>(0h0)) node _stq_clr_head_idx_T_45 = and(stq_valid[22], _stq_clr_head_idx_T_44) node _stq_clr_head_idx_T_46 = eq(stq_cleared[23], UInt<1>(0h0)) node _stq_clr_head_idx_T_47 = and(stq_valid[23], _stq_clr_head_idx_T_46) node _stq_clr_head_idx_temp_vec_T = geq(UInt<1>(0h0), stq_commit_head) node stq_clr_head_idx_temp_vec_0 = and(_stq_clr_head_idx_T_1, _stq_clr_head_idx_temp_vec_T) node _stq_clr_head_idx_temp_vec_T_1 = geq(UInt<1>(0h1), stq_commit_head) node stq_clr_head_idx_temp_vec_1 = and(_stq_clr_head_idx_T_3, _stq_clr_head_idx_temp_vec_T_1) node _stq_clr_head_idx_temp_vec_T_2 = geq(UInt<2>(0h2), stq_commit_head) node stq_clr_head_idx_temp_vec_2 = and(_stq_clr_head_idx_T_5, _stq_clr_head_idx_temp_vec_T_2) node _stq_clr_head_idx_temp_vec_T_3 = geq(UInt<2>(0h3), stq_commit_head) node stq_clr_head_idx_temp_vec_3 = and(_stq_clr_head_idx_T_7, _stq_clr_head_idx_temp_vec_T_3) node _stq_clr_head_idx_temp_vec_T_4 = geq(UInt<3>(0h4), stq_commit_head) node stq_clr_head_idx_temp_vec_4 = and(_stq_clr_head_idx_T_9, _stq_clr_head_idx_temp_vec_T_4) node _stq_clr_head_idx_temp_vec_T_5 = geq(UInt<3>(0h5), stq_commit_head) node stq_clr_head_idx_temp_vec_5 = and(_stq_clr_head_idx_T_11, _stq_clr_head_idx_temp_vec_T_5) node _stq_clr_head_idx_temp_vec_T_6 = geq(UInt<3>(0h6), stq_commit_head) node stq_clr_head_idx_temp_vec_6 = and(_stq_clr_head_idx_T_13, _stq_clr_head_idx_temp_vec_T_6) node _stq_clr_head_idx_temp_vec_T_7 = geq(UInt<3>(0h7), stq_commit_head) node stq_clr_head_idx_temp_vec_7 = and(_stq_clr_head_idx_T_15, _stq_clr_head_idx_temp_vec_T_7) node _stq_clr_head_idx_temp_vec_T_8 = geq(UInt<4>(0h8), stq_commit_head) node stq_clr_head_idx_temp_vec_8 = and(_stq_clr_head_idx_T_17, _stq_clr_head_idx_temp_vec_T_8) node _stq_clr_head_idx_temp_vec_T_9 = geq(UInt<4>(0h9), stq_commit_head) node stq_clr_head_idx_temp_vec_9 = and(_stq_clr_head_idx_T_19, _stq_clr_head_idx_temp_vec_T_9) node _stq_clr_head_idx_temp_vec_T_10 = geq(UInt<4>(0ha), stq_commit_head) node stq_clr_head_idx_temp_vec_10 = and(_stq_clr_head_idx_T_21, _stq_clr_head_idx_temp_vec_T_10) node _stq_clr_head_idx_temp_vec_T_11 = geq(UInt<4>(0hb), stq_commit_head) node stq_clr_head_idx_temp_vec_11 = and(_stq_clr_head_idx_T_23, _stq_clr_head_idx_temp_vec_T_11) node _stq_clr_head_idx_temp_vec_T_12 = geq(UInt<4>(0hc), stq_commit_head) node stq_clr_head_idx_temp_vec_12 = and(_stq_clr_head_idx_T_25, _stq_clr_head_idx_temp_vec_T_12) node _stq_clr_head_idx_temp_vec_T_13 = geq(UInt<4>(0hd), stq_commit_head) node stq_clr_head_idx_temp_vec_13 = and(_stq_clr_head_idx_T_27, _stq_clr_head_idx_temp_vec_T_13) node _stq_clr_head_idx_temp_vec_T_14 = geq(UInt<4>(0he), stq_commit_head) node stq_clr_head_idx_temp_vec_14 = and(_stq_clr_head_idx_T_29, _stq_clr_head_idx_temp_vec_T_14) node _stq_clr_head_idx_temp_vec_T_15 = geq(UInt<4>(0hf), stq_commit_head) node stq_clr_head_idx_temp_vec_15 = and(_stq_clr_head_idx_T_31, _stq_clr_head_idx_temp_vec_T_15) node _stq_clr_head_idx_temp_vec_T_16 = geq(UInt<5>(0h10), stq_commit_head) node stq_clr_head_idx_temp_vec_16 = and(_stq_clr_head_idx_T_33, _stq_clr_head_idx_temp_vec_T_16) node _stq_clr_head_idx_temp_vec_T_17 = geq(UInt<5>(0h11), stq_commit_head) node stq_clr_head_idx_temp_vec_17 = and(_stq_clr_head_idx_T_35, _stq_clr_head_idx_temp_vec_T_17) node _stq_clr_head_idx_temp_vec_T_18 = geq(UInt<5>(0h12), stq_commit_head) node stq_clr_head_idx_temp_vec_18 = and(_stq_clr_head_idx_T_37, _stq_clr_head_idx_temp_vec_T_18) node _stq_clr_head_idx_temp_vec_T_19 = geq(UInt<5>(0h13), stq_commit_head) node stq_clr_head_idx_temp_vec_19 = and(_stq_clr_head_idx_T_39, _stq_clr_head_idx_temp_vec_T_19) node _stq_clr_head_idx_temp_vec_T_20 = geq(UInt<5>(0h14), stq_commit_head) node stq_clr_head_idx_temp_vec_20 = and(_stq_clr_head_idx_T_41, _stq_clr_head_idx_temp_vec_T_20) node _stq_clr_head_idx_temp_vec_T_21 = geq(UInt<5>(0h15), stq_commit_head) node stq_clr_head_idx_temp_vec_21 = and(_stq_clr_head_idx_T_43, _stq_clr_head_idx_temp_vec_T_21) node _stq_clr_head_idx_temp_vec_T_22 = geq(UInt<5>(0h16), stq_commit_head) node stq_clr_head_idx_temp_vec_22 = and(_stq_clr_head_idx_T_45, _stq_clr_head_idx_temp_vec_T_22) node _stq_clr_head_idx_temp_vec_T_23 = geq(UInt<5>(0h17), stq_commit_head) node stq_clr_head_idx_temp_vec_23 = and(_stq_clr_head_idx_T_47, _stq_clr_head_idx_temp_vec_T_23) node _stq_clr_head_idx_idx_T = mux(_stq_clr_head_idx_T_45, UInt<6>(0h36), UInt<6>(0h37)) node _stq_clr_head_idx_idx_T_1 = mux(_stq_clr_head_idx_T_43, UInt<6>(0h35), _stq_clr_head_idx_idx_T) node _stq_clr_head_idx_idx_T_2 = mux(_stq_clr_head_idx_T_41, UInt<6>(0h34), _stq_clr_head_idx_idx_T_1) node _stq_clr_head_idx_idx_T_3 = mux(_stq_clr_head_idx_T_39, UInt<6>(0h33), _stq_clr_head_idx_idx_T_2) node _stq_clr_head_idx_idx_T_4 = mux(_stq_clr_head_idx_T_37, UInt<6>(0h32), _stq_clr_head_idx_idx_T_3) node _stq_clr_head_idx_idx_T_5 = mux(_stq_clr_head_idx_T_35, UInt<6>(0h31), _stq_clr_head_idx_idx_T_4) node _stq_clr_head_idx_idx_T_6 = mux(_stq_clr_head_idx_T_33, UInt<6>(0h30), _stq_clr_head_idx_idx_T_5) node _stq_clr_head_idx_idx_T_7 = mux(_stq_clr_head_idx_T_31, UInt<6>(0h2f), _stq_clr_head_idx_idx_T_6) node _stq_clr_head_idx_idx_T_8 = mux(_stq_clr_head_idx_T_29, UInt<6>(0h2e), _stq_clr_head_idx_idx_T_7) node _stq_clr_head_idx_idx_T_9 = mux(_stq_clr_head_idx_T_27, UInt<6>(0h2d), _stq_clr_head_idx_idx_T_8) node _stq_clr_head_idx_idx_T_10 = mux(_stq_clr_head_idx_T_25, UInt<6>(0h2c), _stq_clr_head_idx_idx_T_9) node _stq_clr_head_idx_idx_T_11 = mux(_stq_clr_head_idx_T_23, UInt<6>(0h2b), _stq_clr_head_idx_idx_T_10) node _stq_clr_head_idx_idx_T_12 = mux(_stq_clr_head_idx_T_21, UInt<6>(0h2a), _stq_clr_head_idx_idx_T_11) node _stq_clr_head_idx_idx_T_13 = mux(_stq_clr_head_idx_T_19, UInt<6>(0h29), _stq_clr_head_idx_idx_T_12) node _stq_clr_head_idx_idx_T_14 = mux(_stq_clr_head_idx_T_17, UInt<6>(0h28), _stq_clr_head_idx_idx_T_13) node _stq_clr_head_idx_idx_T_15 = mux(_stq_clr_head_idx_T_15, UInt<6>(0h27), _stq_clr_head_idx_idx_T_14) node _stq_clr_head_idx_idx_T_16 = mux(_stq_clr_head_idx_T_13, UInt<6>(0h26), _stq_clr_head_idx_idx_T_15) node _stq_clr_head_idx_idx_T_17 = mux(_stq_clr_head_idx_T_11, UInt<6>(0h25), _stq_clr_head_idx_idx_T_16) node _stq_clr_head_idx_idx_T_18 = mux(_stq_clr_head_idx_T_9, UInt<6>(0h24), _stq_clr_head_idx_idx_T_17) node _stq_clr_head_idx_idx_T_19 = mux(_stq_clr_head_idx_T_7, UInt<6>(0h23), _stq_clr_head_idx_idx_T_18) node _stq_clr_head_idx_idx_T_20 = mux(_stq_clr_head_idx_T_5, UInt<6>(0h22), _stq_clr_head_idx_idx_T_19) node _stq_clr_head_idx_idx_T_21 = mux(_stq_clr_head_idx_T_3, UInt<6>(0h21), _stq_clr_head_idx_idx_T_20) node _stq_clr_head_idx_idx_T_22 = mux(_stq_clr_head_idx_T_1, UInt<6>(0h20), _stq_clr_head_idx_idx_T_21) node _stq_clr_head_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _stq_clr_head_idx_idx_T_22) node _stq_clr_head_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _stq_clr_head_idx_idx_T_23) node _stq_clr_head_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _stq_clr_head_idx_idx_T_24) node _stq_clr_head_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _stq_clr_head_idx_idx_T_25) node _stq_clr_head_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _stq_clr_head_idx_idx_T_26) node _stq_clr_head_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _stq_clr_head_idx_idx_T_27) node _stq_clr_head_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _stq_clr_head_idx_idx_T_28) node _stq_clr_head_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _stq_clr_head_idx_idx_T_29) node _stq_clr_head_idx_idx_T_31 = mux(stq_clr_head_idx_temp_vec_23, UInt<5>(0h17), _stq_clr_head_idx_idx_T_30) node _stq_clr_head_idx_idx_T_32 = mux(stq_clr_head_idx_temp_vec_22, UInt<5>(0h16), _stq_clr_head_idx_idx_T_31) node _stq_clr_head_idx_idx_T_33 = mux(stq_clr_head_idx_temp_vec_21, UInt<5>(0h15), _stq_clr_head_idx_idx_T_32) node _stq_clr_head_idx_idx_T_34 = mux(stq_clr_head_idx_temp_vec_20, UInt<5>(0h14), _stq_clr_head_idx_idx_T_33) node _stq_clr_head_idx_idx_T_35 = mux(stq_clr_head_idx_temp_vec_19, UInt<5>(0h13), _stq_clr_head_idx_idx_T_34) node _stq_clr_head_idx_idx_T_36 = mux(stq_clr_head_idx_temp_vec_18, UInt<5>(0h12), _stq_clr_head_idx_idx_T_35) node _stq_clr_head_idx_idx_T_37 = mux(stq_clr_head_idx_temp_vec_17, UInt<5>(0h11), _stq_clr_head_idx_idx_T_36) node _stq_clr_head_idx_idx_T_38 = mux(stq_clr_head_idx_temp_vec_16, UInt<5>(0h10), _stq_clr_head_idx_idx_T_37) node _stq_clr_head_idx_idx_T_39 = mux(stq_clr_head_idx_temp_vec_15, UInt<4>(0hf), _stq_clr_head_idx_idx_T_38) node _stq_clr_head_idx_idx_T_40 = mux(stq_clr_head_idx_temp_vec_14, UInt<4>(0he), _stq_clr_head_idx_idx_T_39) node _stq_clr_head_idx_idx_T_41 = mux(stq_clr_head_idx_temp_vec_13, UInt<4>(0hd), _stq_clr_head_idx_idx_T_40) node _stq_clr_head_idx_idx_T_42 = mux(stq_clr_head_idx_temp_vec_12, UInt<4>(0hc), _stq_clr_head_idx_idx_T_41) node _stq_clr_head_idx_idx_T_43 = mux(stq_clr_head_idx_temp_vec_11, UInt<4>(0hb), _stq_clr_head_idx_idx_T_42) node _stq_clr_head_idx_idx_T_44 = mux(stq_clr_head_idx_temp_vec_10, UInt<4>(0ha), _stq_clr_head_idx_idx_T_43) node _stq_clr_head_idx_idx_T_45 = mux(stq_clr_head_idx_temp_vec_9, UInt<4>(0h9), _stq_clr_head_idx_idx_T_44) node _stq_clr_head_idx_idx_T_46 = mux(stq_clr_head_idx_temp_vec_8, UInt<4>(0h8), _stq_clr_head_idx_idx_T_45) node _stq_clr_head_idx_idx_T_47 = mux(stq_clr_head_idx_temp_vec_7, UInt<3>(0h7), _stq_clr_head_idx_idx_T_46) node _stq_clr_head_idx_idx_T_48 = mux(stq_clr_head_idx_temp_vec_6, UInt<3>(0h6), _stq_clr_head_idx_idx_T_47) node _stq_clr_head_idx_idx_T_49 = mux(stq_clr_head_idx_temp_vec_5, UInt<3>(0h5), _stq_clr_head_idx_idx_T_48) node _stq_clr_head_idx_idx_T_50 = mux(stq_clr_head_idx_temp_vec_4, UInt<3>(0h4), _stq_clr_head_idx_idx_T_49) node _stq_clr_head_idx_idx_T_51 = mux(stq_clr_head_idx_temp_vec_3, UInt<2>(0h3), _stq_clr_head_idx_idx_T_50) node _stq_clr_head_idx_idx_T_52 = mux(stq_clr_head_idx_temp_vec_2, UInt<2>(0h2), _stq_clr_head_idx_idx_T_51) node _stq_clr_head_idx_idx_T_53 = mux(stq_clr_head_idx_temp_vec_1, UInt<1>(0h1), _stq_clr_head_idx_idx_T_52) node stq_clr_head_idx_idx = mux(stq_clr_head_idx_temp_vec_0, UInt<1>(0h0), _stq_clr_head_idx_idx_T_53) node _stq_clr_head_idx_T_48 = bits(stq_clr_head_idx_idx, 4, 0) reg stq_clr_head_idx : UInt, clock connect stq_clr_head_idx, _stq_clr_head_idx_T_48 reg clr_valid : UInt<1>, clock connect clr_valid, UInt<1>(0h0) reg clr_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop.br_mask) node _clr_valid_1_T_1 = neq(_clr_valid_1_T, UInt<1>(0h0)) node _clr_valid_1_T_2 = or(_clr_valid_1_T_1, io.core.exception) node _clr_valid_1_T_3 = eq(_clr_valid_1_T_2, UInt<1>(0h0)) node _clr_valid_1_T_4 = and(clr_valid, _clr_valid_1_T_3) reg clr_valid_1 : UInt<1>, clock connect clr_valid_1, _clr_valid_1_T_4 wire clr_uop_1_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out, clr_uop node _clr_uop_1_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_1 = and(clr_uop.br_mask, _clr_uop_1_out_br_mask_T) connect clr_uop_1_out.br_mask, _clr_uop_1_out_br_mask_T_1 reg clr_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1, clr_uop_1_out node _s_uop_T = or(stq_clr_head_idx, UInt<5>(0h0)) node _s_uop_T_1 = bits(_s_uop_T, 4, 0) wire s_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop, stq_uop[_s_uop_T_1] node _T_255 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_256 = bits(_T_255, 4, 0) node _T_257 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_258 = bits(_T_257, 4, 0) node _T_259 = and(stq_valid[_T_256], stq_addr[_T_258].valid) node _T_260 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_261 = bits(_T_260, 4, 0) node _T_262 = and(_T_259, stq_data[_T_261].valid) node _T_263 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_264 = bits(_T_263, 4, 0) node _T_265 = eq(stq_addr_is_virtual[_T_264], UInt<1>(0h0)) node _T_266 = and(_T_262, _T_265) node _T_267 = eq(s_uop.is_amo, UInt<1>(0h0)) node _T_268 = and(_T_266, _T_267) node _T_269 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_270 = bits(_T_269, 4, 0) node _T_271 = eq(stq_cleared[_T_270], UInt<1>(0h0)) node _T_272 = and(_T_268, _T_271) node _T_273 = and(io.core.brupdate.b1.mispredict_mask, s_uop.br_mask) node _T_274 = neq(_T_273, UInt<1>(0h0)) node _T_275 = or(_T_274, io.core.exception) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = and(_T_272, _T_276) when _T_277 : connect clr_valid, UInt<1>(0h1) wire clr_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out, s_uop node _clr_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_1 = and(s_uop.br_mask, _clr_uop_out_br_mask_T) connect clr_uop_out.br_mask, _clr_uop_out_br_mask_T_1 connect clr_uop, clr_uop_out node _T_278 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_279 = bits(_T_278, 4, 0) connect stq_cleared[_T_279], UInt<1>(0h1) node _io_core_clr_bsy_0_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1.br_mask) node _io_core_clr_bsy_0_valid_T_1 = neq(_io_core_clr_bsy_0_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_0_valid_T_2 = or(_io_core_clr_bsy_0_valid_T_1, io.core.exception) node _io_core_clr_bsy_0_valid_T_3 = eq(_io_core_clr_bsy_0_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_0_valid_T_4 = and(clr_valid_1, _io_core_clr_bsy_0_valid_T_3) connect io.core.clr_bsy[0].valid, _io_core_clr_bsy_0_valid_T_4 connect io.core.clr_bsy[0].bits, clr_uop_1.rob_idx node wrap_6 = eq(stq_clr_head_idx, UInt<5>(0h17)) node _T_280 = add(stq_clr_head_idx, UInt<1>(0h1)) node _T_281 = tail(_T_280, 1) node _T_282 = mux(wrap_6, UInt<1>(0h0), _T_281) reg clr_valid_2 : UInt<1>, clock connect clr_valid_2, UInt<1>(0h0) reg clr_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T_5 = and(io.core.brupdate.b1.mispredict_mask, clr_uop_2.br_mask) node _clr_valid_1_T_6 = neq(_clr_valid_1_T_5, UInt<1>(0h0)) node _clr_valid_1_T_7 = or(_clr_valid_1_T_6, io.core.exception) node _clr_valid_1_T_8 = eq(_clr_valid_1_T_7, UInt<1>(0h0)) node _clr_valid_1_T_9 = and(clr_valid_2, _clr_valid_1_T_8) reg clr_valid_1_1 : UInt<1>, clock connect clr_valid_1_1, _clr_valid_1_T_9 wire clr_uop_1_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out_1, clr_uop_2 node _clr_uop_1_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_3 = and(clr_uop_2.br_mask, _clr_uop_1_out_br_mask_T_2) connect clr_uop_1_out_1.br_mask, _clr_uop_1_out_br_mask_T_3 reg clr_uop_1_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1_1, clr_uop_1_out_1 node _s_uop_T_2 = or(_T_282, UInt<5>(0h0)) node _s_uop_T_3 = bits(_s_uop_T_2, 4, 0) wire s_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_1, stq_uop[_s_uop_T_3] node _T_283 = or(_T_282, UInt<5>(0h0)) node _T_284 = bits(_T_283, 4, 0) node _T_285 = or(_T_282, UInt<5>(0h0)) node _T_286 = bits(_T_285, 4, 0) node _T_287 = and(stq_valid[_T_284], stq_addr[_T_286].valid) node _T_288 = or(_T_282, UInt<5>(0h0)) node _T_289 = bits(_T_288, 4, 0) node _T_290 = and(_T_287, stq_data[_T_289].valid) node _T_291 = or(_T_282, UInt<5>(0h0)) node _T_292 = bits(_T_291, 4, 0) node _T_293 = eq(stq_addr_is_virtual[_T_292], UInt<1>(0h0)) node _T_294 = and(_T_290, _T_293) node _T_295 = eq(s_uop_1.is_amo, UInt<1>(0h0)) node _T_296 = and(_T_294, _T_295) node _T_297 = or(_T_282, UInt<5>(0h0)) node _T_298 = bits(_T_297, 4, 0) node _T_299 = eq(stq_cleared[_T_298], UInt<1>(0h0)) node _T_300 = and(_T_296, _T_299) node _T_301 = and(io.core.brupdate.b1.mispredict_mask, s_uop_1.br_mask) node _T_302 = neq(_T_301, UInt<1>(0h0)) node _T_303 = or(_T_302, io.core.exception) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = and(_T_300, _T_304) when _T_305 : connect clr_valid_2, UInt<1>(0h1) wire clr_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out_1, s_uop_1 node _clr_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_3 = and(s_uop_1.br_mask, _clr_uop_out_br_mask_T_2) connect clr_uop_out_1.br_mask, _clr_uop_out_br_mask_T_3 connect clr_uop_2, clr_uop_out_1 node _T_306 = or(_T_282, UInt<5>(0h0)) node _T_307 = bits(_T_306, 4, 0) connect stq_cleared[_T_307], UInt<1>(0h1) node _io_core_clr_bsy_1_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1_1.br_mask) node _io_core_clr_bsy_1_valid_T_1 = neq(_io_core_clr_bsy_1_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_1_valid_T_2 = or(_io_core_clr_bsy_1_valid_T_1, io.core.exception) node _io_core_clr_bsy_1_valid_T_3 = eq(_io_core_clr_bsy_1_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_1_valid_T_4 = and(clr_valid_1_1, _io_core_clr_bsy_1_valid_T_3) connect io.core.clr_bsy[1].valid, _io_core_clr_bsy_1_valid_T_4 connect io.core.clr_bsy[1].bits, clr_uop_1_1.rob_idx node wrap_7 = eq(_T_282, UInt<5>(0h17)) node _T_308 = add(_T_282, UInt<1>(0h1)) node _T_309 = tail(_T_308, 1) node _T_310 = mux(wrap_7, UInt<1>(0h0), _T_309) reg clr_valid_3 : UInt<1>, clock connect clr_valid_3, UInt<1>(0h0) reg clr_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T_10 = and(io.core.brupdate.b1.mispredict_mask, clr_uop_3.br_mask) node _clr_valid_1_T_11 = neq(_clr_valid_1_T_10, UInt<1>(0h0)) node _clr_valid_1_T_12 = or(_clr_valid_1_T_11, io.core.exception) node _clr_valid_1_T_13 = eq(_clr_valid_1_T_12, UInt<1>(0h0)) node _clr_valid_1_T_14 = and(clr_valid_3, _clr_valid_1_T_13) reg clr_valid_1_2 : UInt<1>, clock connect clr_valid_1_2, _clr_valid_1_T_14 wire clr_uop_1_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out_2, clr_uop_3 node _clr_uop_1_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_5 = and(clr_uop_3.br_mask, _clr_uop_1_out_br_mask_T_4) connect clr_uop_1_out_2.br_mask, _clr_uop_1_out_br_mask_T_5 reg clr_uop_1_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1_2, clr_uop_1_out_2 node _s_uop_T_4 = or(_T_310, UInt<5>(0h0)) node _s_uop_T_5 = bits(_s_uop_T_4, 4, 0) wire s_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_2, stq_uop[_s_uop_T_5] node _T_311 = or(_T_310, UInt<5>(0h0)) node _T_312 = bits(_T_311, 4, 0) node _T_313 = or(_T_310, UInt<5>(0h0)) node _T_314 = bits(_T_313, 4, 0) node _T_315 = and(stq_valid[_T_312], stq_addr[_T_314].valid) node _T_316 = or(_T_310, UInt<5>(0h0)) node _T_317 = bits(_T_316, 4, 0) node _T_318 = and(_T_315, stq_data[_T_317].valid) node _T_319 = or(_T_310, UInt<5>(0h0)) node _T_320 = bits(_T_319, 4, 0) node _T_321 = eq(stq_addr_is_virtual[_T_320], UInt<1>(0h0)) node _T_322 = and(_T_318, _T_321) node _T_323 = eq(s_uop_2.is_amo, UInt<1>(0h0)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(_T_310, UInt<5>(0h0)) node _T_326 = bits(_T_325, 4, 0) node _T_327 = eq(stq_cleared[_T_326], UInt<1>(0h0)) node _T_328 = and(_T_324, _T_327) node _T_329 = and(io.core.brupdate.b1.mispredict_mask, s_uop_2.br_mask) node _T_330 = neq(_T_329, UInt<1>(0h0)) node _T_331 = or(_T_330, io.core.exception) node _T_332 = eq(_T_331, UInt<1>(0h0)) node _T_333 = and(_T_328, _T_332) when _T_333 : connect clr_valid_3, UInt<1>(0h1) wire clr_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out_2, s_uop_2 node _clr_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_5 = and(s_uop_2.br_mask, _clr_uop_out_br_mask_T_4) connect clr_uop_out_2.br_mask, _clr_uop_out_br_mask_T_5 connect clr_uop_3, clr_uop_out_2 node _T_334 = or(_T_310, UInt<5>(0h0)) node _T_335 = bits(_T_334, 4, 0) connect stq_cleared[_T_335], UInt<1>(0h1) node _io_core_clr_bsy_2_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1_2.br_mask) node _io_core_clr_bsy_2_valid_T_1 = neq(_io_core_clr_bsy_2_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_2_valid_T_2 = or(_io_core_clr_bsy_2_valid_T_1, io.core.exception) node _io_core_clr_bsy_2_valid_T_3 = eq(_io_core_clr_bsy_2_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_2_valid_T_4 = and(clr_valid_1_2, _io_core_clr_bsy_2_valid_T_3) connect io.core.clr_bsy[2].valid, _io_core_clr_bsy_2_valid_T_4 connect io.core.clr_bsy[2].bits, clr_uop_1_2.rob_idx node wrap_8 = eq(_T_310, UInt<5>(0h17)) node _T_336 = add(_T_310, UInt<1>(0h1)) node _T_337 = tail(_T_336, 1) node _T_338 = mux(wrap_8, UInt<1>(0h0), _T_337) node _do_st_search_T = or(fired_store_agen[0], fired_store_retry[0]) node _do_st_search_T_1 = eq(mem_tlb_miss[0], UInt<1>(0h0)) node _do_st_search_T_2 = and(_do_st_search_T, _do_st_search_T_1) wire do_st_search : UInt<1>[1] connect do_st_search[0], _do_st_search_T_2 node _do_ld_search_T = or(fired_load_agen[0], fired_load_agen_exec[0]) node _do_ld_search_T_1 = or(_do_ld_search_T, fired_load_retry[0]) node _do_ld_search_T_2 = eq(mem_tlb_miss[0], UInt<1>(0h0)) node _do_ld_search_T_3 = and(_do_ld_search_T_1, _do_ld_search_T_2) node _do_ld_search_T_4 = or(_do_ld_search_T_3, fired_load_wakeup[0]) wire do_ld_search : UInt<1>[1] connect do_ld_search[0], _do_ld_search_T_4 wire do_release_search : UInt<1>[1] connect do_release_search[0], fired_release[0] node _lcam_addr_T = or(fired_store_agen[0], fired_store_retry[0]) node _lcam_addr_T_1 = or(_lcam_addr_T, fired_load_agen[0]) node _lcam_addr_T_2 = or(_lcam_addr_T_1, fired_load_agen_exec[0]) reg lcam_addr_REG : UInt, clock connect lcam_addr_REG, exe_tlb_paddr[0] reg lcam_addr_REG_1 : UInt, clock connect lcam_addr_REG_1, io.dmem.release.bits.address node _lcam_addr_T_3 = mux(fired_release[0], lcam_addr_REG_1, mem_paddr[0]) node _lcam_addr_T_4 = mux(_lcam_addr_T_2, lcam_addr_REG, _lcam_addr_T_3) wire lcam_addr : UInt[1] connect lcam_addr[0], _lcam_addr_T_4 wire _lcam_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _lcam_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _lcam_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _lcam_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _lcam_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_typ, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_rm, UInt<3>(0h0) connect _lcam_uop_WIRE.fp_val, UInt<1>(0h0) connect _lcam_uop_WIRE.fcn_op, UInt<5>(0h0) connect _lcam_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _lcam_uop_WIRE.frs3_en, UInt<1>(0h0) connect _lcam_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.lrs3, UInt<6>(0h0) connect _lcam_uop_WIRE.lrs2, UInt<6>(0h0) connect _lcam_uop_WIRE.lrs1, UInt<6>(0h0) connect _lcam_uop_WIRE.ldst, UInt<6>(0h0) connect _lcam_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _lcam_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _lcam_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _lcam_uop_WIRE.is_unique, UInt<1>(0h0) connect _lcam_uop_WIRE.uses_stq, UInt<1>(0h0) connect _lcam_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _lcam_uop_WIRE.mem_signed, UInt<1>(0h0) connect _lcam_uop_WIRE.mem_size, UInt<2>(0h0) connect _lcam_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _lcam_uop_WIRE.exc_cause, UInt<64>(0h0) connect _lcam_uop_WIRE.exception, UInt<1>(0h0) connect _lcam_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _lcam_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.ppred, UInt<5>(0h0) connect _lcam_uop_WIRE.prs3, UInt<7>(0h0) connect _lcam_uop_WIRE.prs2, UInt<7>(0h0) connect _lcam_uop_WIRE.prs1, UInt<7>(0h0) connect _lcam_uop_WIRE.pdst, UInt<7>(0h0) connect _lcam_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _lcam_uop_WIRE.stq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.rob_idx, UInt<7>(0h0) connect _lcam_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _lcam_uop_WIRE.op2_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.op1_sel, UInt<2>(0h0) connect _lcam_uop_WIRE.imm_packed, UInt<20>(0h0) connect _lcam_uop_WIRE.pimm, UInt<5>(0h0) connect _lcam_uop_WIRE.imm_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.imm_rename, UInt<1>(0h0) connect _lcam_uop_WIRE.taken, UInt<1>(0h0) connect _lcam_uop_WIRE.pc_lob, UInt<6>(0h0) connect _lcam_uop_WIRE.edge_inst, UInt<1>(0h0) connect _lcam_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.is_mov, UInt<1>(0h0) connect _lcam_uop_WIRE.is_rocc, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _lcam_uop_WIRE.is_eret, UInt<1>(0h0) connect _lcam_uop_WIRE.is_amo, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sfence, UInt<1>(0h0) connect _lcam_uop_WIRE.is_fencei, UInt<1>(0h0) connect _lcam_uop_WIRE.is_fence, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sfb, UInt<1>(0h0) connect _lcam_uop_WIRE.br_type, UInt<4>(0h0) connect _lcam_uop_WIRE.br_tag, UInt<4>(0h0) connect _lcam_uop_WIRE.br_mask, UInt<16>(0h0) connect _lcam_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_issued, UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _lcam_uop_WIRE.debug_pc, UInt<40>(0h0) connect _lcam_uop_WIRE.is_rvc, UInt<1>(0h0) connect _lcam_uop_WIRE.debug_inst, UInt<32>(0h0) connect _lcam_uop_WIRE.inst, UInt<32>(0h0) node _lcam_uop_T = mux(do_ld_search[0], mem_ldq_e[0].bits.uop, _lcam_uop_WIRE) node _lcam_uop_T_1 = mux(do_st_search[0], mem_stq_e[0].bits.uop, _lcam_uop_T) wire lcam_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect lcam_uop[0], _lcam_uop_T_1 wire lcam_mask_mask : UInt<8> node _lcam_mask_mask_T = eq(lcam_uop[0].mem_size, UInt<1>(0h0)) node _lcam_mask_mask_T_1 = bits(lcam_addr[0], 2, 0) node _lcam_mask_mask_T_2 = dshl(UInt<8>(0h1), _lcam_mask_mask_T_1) node _lcam_mask_mask_T_3 = eq(lcam_uop[0].mem_size, UInt<1>(0h1)) node _lcam_mask_mask_T_4 = bits(lcam_addr[0], 2, 1) node _lcam_mask_mask_T_5 = dshl(_lcam_mask_mask_T_4, UInt<1>(0h1)) node _lcam_mask_mask_T_6 = dshl(UInt<8>(0h3), _lcam_mask_mask_T_5) node _lcam_mask_mask_T_7 = eq(lcam_uop[0].mem_size, UInt<2>(0h2)) node _lcam_mask_mask_T_8 = bits(lcam_addr[0], 2, 2) node _lcam_mask_mask_T_9 = mux(_lcam_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _lcam_mask_mask_T_10 = eq(lcam_uop[0].mem_size, UInt<2>(0h3)) node _lcam_mask_mask_T_11 = mux(_lcam_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _lcam_mask_mask_T_12 = mux(_lcam_mask_mask_T_7, _lcam_mask_mask_T_9, _lcam_mask_mask_T_11) node _lcam_mask_mask_T_13 = mux(_lcam_mask_mask_T_3, _lcam_mask_mask_T_6, _lcam_mask_mask_T_12) node _lcam_mask_mask_T_14 = mux(_lcam_mask_mask_T, _lcam_mask_mask_T_2, _lcam_mask_mask_T_13) connect lcam_mask_mask, _lcam_mask_mask_T_14 wire lcam_mask : UInt<8>[1] connect lcam_mask[0], lcam_mask_mask wire lcam_st_dep_mask : UInt<24>[1] connect lcam_st_dep_mask[0], mem_ldq_e[0].bits.st_dep_mask wire lcam_is_release : UInt<1>[1] connect lcam_is_release[0], fired_release[0] node _lcam_ldq_idx_T = or(fired_load_agen[0], fired_load_agen_exec[0]) reg lcam_ldq_idx_REG : UInt, clock connect lcam_ldq_idx_REG, ldq_wakeup_idx reg lcam_ldq_idx_REG_1 : UInt, clock connect lcam_ldq_idx_REG_1, retry_queue.io.deq.bits.uop.ldq_idx node _lcam_ldq_idx_T_1 = mux(fired_load_retry[0], lcam_ldq_idx_REG_1, UInt<1>(0h0)) node _lcam_ldq_idx_T_2 = mux(fired_load_wakeup[0], lcam_ldq_idx_REG, _lcam_ldq_idx_T_1) node _lcam_ldq_idx_T_3 = mux(_lcam_ldq_idx_T, mem_incoming_uop[0].ldq_idx, _lcam_ldq_idx_T_2) wire lcam_ldq_idx : UInt[1] connect lcam_ldq_idx[0], _lcam_ldq_idx_T_3 reg lcam_stq_idx_REG : UInt, clock connect lcam_stq_idx_REG, retry_queue.io.deq.bits.uop.stq_idx node _lcam_stq_idx_T = mux(fired_store_retry[0], lcam_stq_idx_REG, UInt<1>(0h0)) node _lcam_stq_idx_T_1 = mux(fired_store_agen[0], mem_incoming_uop[0].stq_idx, _lcam_stq_idx_T) wire lcam_stq_idx : UInt[1] connect lcam_stq_idx[0], _lcam_stq_idx_T_1 node _lcam_younger_load_mask_hi_mask_T = dshl(UInt<1>(0h1), lcam_ldq_idx[0]) node _lcam_younger_load_mask_hi_mask_T_1 = bits(_lcam_younger_load_mask_hi_mask_T, 23, 0) node _lcam_younger_load_mask_hi_mask_T_2 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<1>(0h0)) node _lcam_younger_load_mask_hi_mask_T_3 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<1>(0h1)) node _lcam_younger_load_mask_hi_mask_T_4 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<2>(0h2)) node _lcam_younger_load_mask_hi_mask_T_5 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<2>(0h3)) node _lcam_younger_load_mask_hi_mask_T_6 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h4)) node _lcam_younger_load_mask_hi_mask_T_7 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h5)) node _lcam_younger_load_mask_hi_mask_T_8 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h6)) node _lcam_younger_load_mask_hi_mask_T_9 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h7)) node _lcam_younger_load_mask_hi_mask_T_10 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0h8)) node _lcam_younger_load_mask_hi_mask_T_11 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0h9)) node _lcam_younger_load_mask_hi_mask_T_12 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0ha)) node _lcam_younger_load_mask_hi_mask_T_13 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hb)) node _lcam_younger_load_mask_hi_mask_T_14 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hc)) node _lcam_younger_load_mask_hi_mask_T_15 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hd)) node _lcam_younger_load_mask_hi_mask_T_16 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0he)) node _lcam_younger_load_mask_hi_mask_T_17 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hf)) node _lcam_younger_load_mask_hi_mask_T_18 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h10)) node _lcam_younger_load_mask_hi_mask_T_19 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h11)) node _lcam_younger_load_mask_hi_mask_T_20 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h12)) node _lcam_younger_load_mask_hi_mask_T_21 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h13)) node _lcam_younger_load_mask_hi_mask_T_22 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h14)) node _lcam_younger_load_mask_hi_mask_T_23 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h15)) node _lcam_younger_load_mask_hi_mask_T_24 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h16)) node _lcam_younger_load_mask_hi_mask_T_25 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h17)) node _lcam_younger_load_mask_hi_mask_T_26 = or(_lcam_younger_load_mask_hi_mask_T_2, _lcam_younger_load_mask_hi_mask_T_3) node _lcam_younger_load_mask_hi_mask_T_27 = or(_lcam_younger_load_mask_hi_mask_T_26, _lcam_younger_load_mask_hi_mask_T_4) node _lcam_younger_load_mask_hi_mask_T_28 = or(_lcam_younger_load_mask_hi_mask_T_27, _lcam_younger_load_mask_hi_mask_T_5) node _lcam_younger_load_mask_hi_mask_T_29 = or(_lcam_younger_load_mask_hi_mask_T_28, _lcam_younger_load_mask_hi_mask_T_6) node _lcam_younger_load_mask_hi_mask_T_30 = or(_lcam_younger_load_mask_hi_mask_T_29, _lcam_younger_load_mask_hi_mask_T_7) node _lcam_younger_load_mask_hi_mask_T_31 = or(_lcam_younger_load_mask_hi_mask_T_30, _lcam_younger_load_mask_hi_mask_T_8) node _lcam_younger_load_mask_hi_mask_T_32 = or(_lcam_younger_load_mask_hi_mask_T_31, _lcam_younger_load_mask_hi_mask_T_9) node _lcam_younger_load_mask_hi_mask_T_33 = or(_lcam_younger_load_mask_hi_mask_T_32, _lcam_younger_load_mask_hi_mask_T_10) node _lcam_younger_load_mask_hi_mask_T_34 = or(_lcam_younger_load_mask_hi_mask_T_33, _lcam_younger_load_mask_hi_mask_T_11) node _lcam_younger_load_mask_hi_mask_T_35 = or(_lcam_younger_load_mask_hi_mask_T_34, _lcam_younger_load_mask_hi_mask_T_12) node _lcam_younger_load_mask_hi_mask_T_36 = or(_lcam_younger_load_mask_hi_mask_T_35, _lcam_younger_load_mask_hi_mask_T_13) node _lcam_younger_load_mask_hi_mask_T_37 = or(_lcam_younger_load_mask_hi_mask_T_36, _lcam_younger_load_mask_hi_mask_T_14) node _lcam_younger_load_mask_hi_mask_T_38 = or(_lcam_younger_load_mask_hi_mask_T_37, _lcam_younger_load_mask_hi_mask_T_15) node _lcam_younger_load_mask_hi_mask_T_39 = or(_lcam_younger_load_mask_hi_mask_T_38, _lcam_younger_load_mask_hi_mask_T_16) node _lcam_younger_load_mask_hi_mask_T_40 = or(_lcam_younger_load_mask_hi_mask_T_39, _lcam_younger_load_mask_hi_mask_T_17) node _lcam_younger_load_mask_hi_mask_T_41 = or(_lcam_younger_load_mask_hi_mask_T_40, _lcam_younger_load_mask_hi_mask_T_18) node _lcam_younger_load_mask_hi_mask_T_42 = or(_lcam_younger_load_mask_hi_mask_T_41, _lcam_younger_load_mask_hi_mask_T_19) node _lcam_younger_load_mask_hi_mask_T_43 = or(_lcam_younger_load_mask_hi_mask_T_42, _lcam_younger_load_mask_hi_mask_T_20) node _lcam_younger_load_mask_hi_mask_T_44 = or(_lcam_younger_load_mask_hi_mask_T_43, _lcam_younger_load_mask_hi_mask_T_21) node _lcam_younger_load_mask_hi_mask_T_45 = or(_lcam_younger_load_mask_hi_mask_T_44, _lcam_younger_load_mask_hi_mask_T_22) node _lcam_younger_load_mask_hi_mask_T_46 = or(_lcam_younger_load_mask_hi_mask_T_45, _lcam_younger_load_mask_hi_mask_T_23) node _lcam_younger_load_mask_hi_mask_T_47 = or(_lcam_younger_load_mask_hi_mask_T_46, _lcam_younger_load_mask_hi_mask_T_24) node _lcam_younger_load_mask_hi_mask_T_48 = or(_lcam_younger_load_mask_hi_mask_T_47, _lcam_younger_load_mask_hi_mask_T_25) node lcam_younger_load_mask_hi_mask = not(_lcam_younger_load_mask_hi_mask_T_48) node _lcam_younger_load_mask_lo_mask_T = dshl(UInt<1>(0h1), ldq_head) node _lcam_younger_load_mask_lo_mask_T_1 = bits(_lcam_younger_load_mask_lo_mask_T, 23, 0) node _lcam_younger_load_mask_lo_mask_T_2 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<1>(0h0)) node _lcam_younger_load_mask_lo_mask_T_3 = bits(_lcam_younger_load_mask_lo_mask_T_2, 23, 0) node _lcam_younger_load_mask_lo_mask_T_4 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<1>(0h1)) node _lcam_younger_load_mask_lo_mask_T_5 = bits(_lcam_younger_load_mask_lo_mask_T_4, 23, 0) node _lcam_younger_load_mask_lo_mask_T_6 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<2>(0h2)) node _lcam_younger_load_mask_lo_mask_T_7 = bits(_lcam_younger_load_mask_lo_mask_T_6, 23, 0) node _lcam_younger_load_mask_lo_mask_T_8 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<2>(0h3)) node _lcam_younger_load_mask_lo_mask_T_9 = bits(_lcam_younger_load_mask_lo_mask_T_8, 23, 0) node _lcam_younger_load_mask_lo_mask_T_10 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h4)) node _lcam_younger_load_mask_lo_mask_T_11 = bits(_lcam_younger_load_mask_lo_mask_T_10, 23, 0) node _lcam_younger_load_mask_lo_mask_T_12 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h5)) node _lcam_younger_load_mask_lo_mask_T_13 = bits(_lcam_younger_load_mask_lo_mask_T_12, 23, 0) node _lcam_younger_load_mask_lo_mask_T_14 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h6)) node _lcam_younger_load_mask_lo_mask_T_15 = bits(_lcam_younger_load_mask_lo_mask_T_14, 23, 0) node _lcam_younger_load_mask_lo_mask_T_16 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h7)) node _lcam_younger_load_mask_lo_mask_T_17 = bits(_lcam_younger_load_mask_lo_mask_T_16, 23, 0) node _lcam_younger_load_mask_lo_mask_T_18 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0h8)) node _lcam_younger_load_mask_lo_mask_T_19 = bits(_lcam_younger_load_mask_lo_mask_T_18, 23, 0) node _lcam_younger_load_mask_lo_mask_T_20 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0h9)) node _lcam_younger_load_mask_lo_mask_T_21 = bits(_lcam_younger_load_mask_lo_mask_T_20, 23, 0) node _lcam_younger_load_mask_lo_mask_T_22 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0ha)) node _lcam_younger_load_mask_lo_mask_T_23 = bits(_lcam_younger_load_mask_lo_mask_T_22, 23, 0) node _lcam_younger_load_mask_lo_mask_T_24 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hb)) node _lcam_younger_load_mask_lo_mask_T_25 = bits(_lcam_younger_load_mask_lo_mask_T_24, 23, 0) node _lcam_younger_load_mask_lo_mask_T_26 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hc)) node _lcam_younger_load_mask_lo_mask_T_27 = bits(_lcam_younger_load_mask_lo_mask_T_26, 23, 0) node _lcam_younger_load_mask_lo_mask_T_28 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hd)) node _lcam_younger_load_mask_lo_mask_T_29 = bits(_lcam_younger_load_mask_lo_mask_T_28, 23, 0) node _lcam_younger_load_mask_lo_mask_T_30 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0he)) node _lcam_younger_load_mask_lo_mask_T_31 = bits(_lcam_younger_load_mask_lo_mask_T_30, 23, 0) node _lcam_younger_load_mask_lo_mask_T_32 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hf)) node _lcam_younger_load_mask_lo_mask_T_33 = bits(_lcam_younger_load_mask_lo_mask_T_32, 23, 0) node _lcam_younger_load_mask_lo_mask_T_34 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h10)) node _lcam_younger_load_mask_lo_mask_T_35 = bits(_lcam_younger_load_mask_lo_mask_T_34, 23, 0) node _lcam_younger_load_mask_lo_mask_T_36 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h11)) node _lcam_younger_load_mask_lo_mask_T_37 = bits(_lcam_younger_load_mask_lo_mask_T_36, 23, 0) node _lcam_younger_load_mask_lo_mask_T_38 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h12)) node _lcam_younger_load_mask_lo_mask_T_39 = bits(_lcam_younger_load_mask_lo_mask_T_38, 23, 0) node _lcam_younger_load_mask_lo_mask_T_40 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h13)) node _lcam_younger_load_mask_lo_mask_T_41 = bits(_lcam_younger_load_mask_lo_mask_T_40, 23, 0) node _lcam_younger_load_mask_lo_mask_T_42 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h14)) node _lcam_younger_load_mask_lo_mask_T_43 = bits(_lcam_younger_load_mask_lo_mask_T_42, 23, 0) node _lcam_younger_load_mask_lo_mask_T_44 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h15)) node _lcam_younger_load_mask_lo_mask_T_45 = bits(_lcam_younger_load_mask_lo_mask_T_44, 23, 0) node _lcam_younger_load_mask_lo_mask_T_46 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h16)) node _lcam_younger_load_mask_lo_mask_T_47 = bits(_lcam_younger_load_mask_lo_mask_T_46, 23, 0) node _lcam_younger_load_mask_lo_mask_T_48 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h17)) node _lcam_younger_load_mask_lo_mask_T_49 = bits(_lcam_younger_load_mask_lo_mask_T_48, 23, 0) node _lcam_younger_load_mask_lo_mask_T_50 = or(_lcam_younger_load_mask_lo_mask_T_3, _lcam_younger_load_mask_lo_mask_T_5) node _lcam_younger_load_mask_lo_mask_T_51 = or(_lcam_younger_load_mask_lo_mask_T_50, _lcam_younger_load_mask_lo_mask_T_7) node _lcam_younger_load_mask_lo_mask_T_52 = or(_lcam_younger_load_mask_lo_mask_T_51, _lcam_younger_load_mask_lo_mask_T_9) node _lcam_younger_load_mask_lo_mask_T_53 = or(_lcam_younger_load_mask_lo_mask_T_52, _lcam_younger_load_mask_lo_mask_T_11) node _lcam_younger_load_mask_lo_mask_T_54 = or(_lcam_younger_load_mask_lo_mask_T_53, _lcam_younger_load_mask_lo_mask_T_13) node _lcam_younger_load_mask_lo_mask_T_55 = or(_lcam_younger_load_mask_lo_mask_T_54, _lcam_younger_load_mask_lo_mask_T_15) node _lcam_younger_load_mask_lo_mask_T_56 = or(_lcam_younger_load_mask_lo_mask_T_55, _lcam_younger_load_mask_lo_mask_T_17) node _lcam_younger_load_mask_lo_mask_T_57 = or(_lcam_younger_load_mask_lo_mask_T_56, _lcam_younger_load_mask_lo_mask_T_19) node _lcam_younger_load_mask_lo_mask_T_58 = or(_lcam_younger_load_mask_lo_mask_T_57, _lcam_younger_load_mask_lo_mask_T_21) node _lcam_younger_load_mask_lo_mask_T_59 = or(_lcam_younger_load_mask_lo_mask_T_58, _lcam_younger_load_mask_lo_mask_T_23) node _lcam_younger_load_mask_lo_mask_T_60 = or(_lcam_younger_load_mask_lo_mask_T_59, _lcam_younger_load_mask_lo_mask_T_25) node _lcam_younger_load_mask_lo_mask_T_61 = or(_lcam_younger_load_mask_lo_mask_T_60, _lcam_younger_load_mask_lo_mask_T_27) node _lcam_younger_load_mask_lo_mask_T_62 = or(_lcam_younger_load_mask_lo_mask_T_61, _lcam_younger_load_mask_lo_mask_T_29) node _lcam_younger_load_mask_lo_mask_T_63 = or(_lcam_younger_load_mask_lo_mask_T_62, _lcam_younger_load_mask_lo_mask_T_31) node _lcam_younger_load_mask_lo_mask_T_64 = or(_lcam_younger_load_mask_lo_mask_T_63, _lcam_younger_load_mask_lo_mask_T_33) node _lcam_younger_load_mask_lo_mask_T_65 = or(_lcam_younger_load_mask_lo_mask_T_64, _lcam_younger_load_mask_lo_mask_T_35) node _lcam_younger_load_mask_lo_mask_T_66 = or(_lcam_younger_load_mask_lo_mask_T_65, _lcam_younger_load_mask_lo_mask_T_37) node _lcam_younger_load_mask_lo_mask_T_67 = or(_lcam_younger_load_mask_lo_mask_T_66, _lcam_younger_load_mask_lo_mask_T_39) node _lcam_younger_load_mask_lo_mask_T_68 = or(_lcam_younger_load_mask_lo_mask_T_67, _lcam_younger_load_mask_lo_mask_T_41) node _lcam_younger_load_mask_lo_mask_T_69 = or(_lcam_younger_load_mask_lo_mask_T_68, _lcam_younger_load_mask_lo_mask_T_43) node _lcam_younger_load_mask_lo_mask_T_70 = or(_lcam_younger_load_mask_lo_mask_T_69, _lcam_younger_load_mask_lo_mask_T_45) node _lcam_younger_load_mask_lo_mask_T_71 = or(_lcam_younger_load_mask_lo_mask_T_70, _lcam_younger_load_mask_lo_mask_T_47) node _lcam_younger_load_mask_lo_mask_T_72 = or(_lcam_younger_load_mask_lo_mask_T_71, _lcam_younger_load_mask_lo_mask_T_49) node lcam_younger_load_mask_lo_mask = not(_lcam_younger_load_mask_lo_mask_T_72) node _lcam_younger_load_mask_T = lt(lcam_ldq_idx[0], ldq_head) node _lcam_younger_load_mask_T_1 = and(lcam_younger_load_mask_hi_mask, lcam_younger_load_mask_lo_mask) node _lcam_younger_load_mask_T_2 = or(lcam_younger_load_mask_hi_mask, lcam_younger_load_mask_lo_mask) node _lcam_younger_load_mask_T_3 = mux(_lcam_younger_load_mask_T, _lcam_younger_load_mask_T_1, _lcam_younger_load_mask_T_2) node _lcam_younger_load_mask_T_4 = bits(_lcam_younger_load_mask_T_3, 23, 0) wire lcam_younger_load_mask : UInt<24>[1] connect lcam_younger_load_mask[0], _lcam_younger_load_mask_T_4 node _can_forward_T = or(fired_load_agen[0], fired_load_agen_exec[0]) node _can_forward_T_1 = or(_can_forward_T, fired_load_retry[0]) node _can_forward_T_2 = eq(mem_tlb_uncacheable[0], UInt<1>(0h0)) node _can_forward_T_3 = eq(mem_ldq_wakeup_e.bits.addr_is_uncacheable, UInt<1>(0h0)) node _can_forward_T_4 = mux(_can_forward_T_1, _can_forward_T_2, _can_forward_T_3) wire can_forward : UInt<1>[1] connect can_forward[0], _can_forward_T_4 wire _kill_forward_WIRE : UInt<1>[1] connect _kill_forward_WIRE[0], UInt<1>(0h0) wire kill_forward : UInt<1>[1] connect kill_forward, _kill_forward_WIRE wire ldst_addr_matches : UInt<24>[1] wire ldst_forward_matches : UInt<24>[1] wire stld_prs2_matches : UInt<24>[1] reg s1_executing_loads : UInt<1>[24], clock connect s1_executing_loads, s0_executing_loads wire s1_set_execute : UInt<1>[24] connect s1_set_execute, s1_executing_loads reg wb_ldst_forward_matches : UInt<24>[1], clock connect wb_ldst_forward_matches, ldst_forward_matches wire wb_ldst_forward_valid : UInt<1>[1] wire wb_ldst_forward_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} node _wb_ldst_forward_e_e_valid_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_valid_T_1 = bits(_wb_ldst_forward_e_e_valid_T, 4, 0) connect wb_ldst_forward_e_e.valid, ldq_valid[_wb_ldst_forward_e_e_valid_T_1] node _wb_ldst_forward_e_e_bits_uop_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_uop_T_1 = bits(_wb_ldst_forward_e_e_bits_uop_T, 4, 0) connect wb_ldst_forward_e_e.bits.uop, ldq_uop[_wb_ldst_forward_e_e_bits_uop_T_1] node _wb_ldst_forward_e_e_bits_addr_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr, ldq_addr[_wb_ldst_forward_e_e_bits_addr_T_1] node _wb_ldst_forward_e_e_bits_addr_is_virtual_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_is_virtual_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1] node _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1] node _wb_ldst_forward_e_e_bits_executed_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_executed_T_1 = bits(_wb_ldst_forward_e_e_bits_executed_T, 4, 0) connect wb_ldst_forward_e_e.bits.executed, ldq_executed[_wb_ldst_forward_e_e_bits_executed_T_1] node _wb_ldst_forward_e_e_bits_succeeded_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_succeeded_T_1 = bits(_wb_ldst_forward_e_e_bits_succeeded_T, 4, 0) connect wb_ldst_forward_e_e.bits.succeeded, ldq_succeeded[_wb_ldst_forward_e_e_bits_succeeded_T_1] node _wb_ldst_forward_e_e_bits_order_fail_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_order_fail_T_1 = bits(_wb_ldst_forward_e_e_bits_order_fail_T, 4, 0) connect wb_ldst_forward_e_e.bits.order_fail, ldq_order_fail[_wb_ldst_forward_e_e_bits_order_fail_T_1] node _wb_ldst_forward_e_e_bits_observed_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_observed_T_1 = bits(_wb_ldst_forward_e_e_bits_observed_T, 4, 0) connect wb_ldst_forward_e_e.bits.observed, ldq_observed[_wb_ldst_forward_e_e_bits_observed_T_1] node _wb_ldst_forward_e_e_bits_st_dep_mask_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = bits(_wb_ldst_forward_e_e_bits_st_dep_mask_T, 4, 0) connect wb_ldst_forward_e_e.bits.st_dep_mask, ldq_st_dep_mask[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1] node _wb_ldst_forward_e_e_bits_ld_byte_mask_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = bits(_wb_ldst_forward_e_e_bits_ld_byte_mask_T, 4, 0) connect wb_ldst_forward_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1] node _wb_ldst_forward_e_e_bits_forward_std_val_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = bits(_wb_ldst_forward_e_e_bits_forward_std_val_T, 4, 0) connect wb_ldst_forward_e_e.bits.forward_std_val, ldq_forward_std_val[_wb_ldst_forward_e_e_bits_forward_std_val_T_1] node _wb_ldst_forward_e_e_bits_forward_stq_idx_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = bits(_wb_ldst_forward_e_e_bits_forward_stq_idx_T, 4, 0) connect wb_ldst_forward_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1] node _wb_ldst_forward_e_e_bits_debug_wb_data_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = bits(_wb_ldst_forward_e_e_bits_debug_wb_data_T, 4, 0) connect wb_ldst_forward_e_e.bits.debug_wb_data, ldq_debug_wb_data[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1] wire wb_ldst_forward_e_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>} connect wb_ldst_forward_e_out, wb_ldst_forward_e_e.bits node _wb_ldst_forward_e_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _wb_ldst_forward_e_out_uop_br_mask_T_1 = and(wb_ldst_forward_e_e.bits.uop.br_mask, _wb_ldst_forward_e_out_uop_br_mask_T) connect wb_ldst_forward_e_out.uop.br_mask, _wb_ldst_forward_e_out_uop_br_mask_T_1 reg wb_ldst_forward_e_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}, clock connect wb_ldst_forward_e_REG, wb_ldst_forward_e_out wire wb_ldst_forward_e : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}[1] connect wb_ldst_forward_e[0], wb_ldst_forward_e_REG reg wb_ldst_forward_ldq_idx : UInt[1], clock connect wb_ldst_forward_ldq_idx, lcam_ldq_idx reg wb_ldst_forward_ld_addr : UInt[1], clock connect wb_ldst_forward_ld_addr, lcam_addr wire wb_ldst_forward_stq_idx : UInt<5>[1] wire failed_load : UInt<1> connect failed_load, UInt<1>(0h0) wire l_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop, ldq_uop[0] node _block_addr_matches_T = shr(lcam_addr[0], 6) node _block_addr_matches_T_1 = shr(ldq_addr[0].bits, 6) node _block_addr_matches_T_2 = eq(_block_addr_matches_T, _block_addr_matches_T_1) wire block_addr_matches : UInt<1>[1] connect block_addr_matches[0], _block_addr_matches_T_2 node _dword_addr_matches_T = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_1 = bits(ldq_addr[0].bits, 5, 3) node _dword_addr_matches_T_2 = eq(_dword_addr_matches_T, _dword_addr_matches_T_1) node _dword_addr_matches_T_3 = and(block_addr_matches[0], _dword_addr_matches_T_2) wire dword_addr_matches : UInt<1>[1] connect dword_addr_matches[0], _dword_addr_matches_T_3 node _mask_match_T = and(ldq_ld_byte_mask[0], lcam_mask[0]) node _mask_match_T_1 = eq(_mask_match_T, ldq_ld_byte_mask[0]) wire mask_match : UInt<1>[1] connect mask_match[0], _mask_match_T_1 node _mask_overlap_T = and(ldq_ld_byte_mask[0], lcam_mask[0]) node _mask_overlap_T_1 = orr(_mask_overlap_T) wire mask_overlap : UInt<1>[1] connect mask_overlap[0], _mask_overlap_T_1 node _T_339 = and(do_release_search[0], ldq_valid[0]) node _T_340 = and(_T_339, ldq_addr[0].valid) node _T_341 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_342 = and(_T_340, _T_341) node _T_343 = and(_T_342, block_addr_matches[0]) when _T_343 : connect ldq_observed[0], UInt<1>(0h1) node _T_344 = and(do_st_search[0], ldq_valid[0]) node _T_345 = and(_T_344, ldq_addr[0].valid) node _T_346 = or(ldq_executed[0], ldq_succeeded[0]) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = dshr(ldq_st_dep_mask[0], lcam_stq_idx[0]) node _T_351 = bits(_T_350, 0, 0) node _T_352 = and(_T_349, _T_351) node _T_353 = and(_T_352, dword_addr_matches[0]) node _T_354 = and(_T_353, mask_overlap[0]) when _T_354 : node _forwarded_is_older_T = lt(ldq_forward_stq_idx[0], lcam_stq_idx[0]) node _forwarded_is_older_T_1 = lt(ldq_forward_stq_idx[0], l_uop.stq_idx) node _forwarded_is_older_T_2 = xor(_forwarded_is_older_T, _forwarded_is_older_T_1) node _forwarded_is_older_T_3 = lt(lcam_stq_idx[0], l_uop.stq_idx) node forwarded_is_older = xor(_forwarded_is_older_T_2, _forwarded_is_older_T_3) node _T_355 = eq(ldq_forward_std_val[0], UInt<1>(0h0)) node _T_356 = neq(ldq_forward_stq_idx[0], lcam_stq_idx[0]) node _T_357 = and(_T_356, forwarded_is_older) node _T_358 = or(_T_355, _T_357) when _T_358 : connect ldq_order_fail[0], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_359 = and(do_ld_search[0], ldq_valid[0]) node _T_360 = and(_T_359, ldq_addr[0].valid) node _T_361 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_362 = and(_T_360, _T_361) node _T_363 = and(_T_362, dword_addr_matches[0]) node _T_364 = and(_T_363, mask_overlap[0]) when _T_364 : node searcher_is_older = bits(lcam_younger_load_mask[0], 0, 0) node _T_365 = lt(lcam_ldq_idx[0], UInt<1>(0h0)) node _T_366 = lt(lcam_ldq_idx[0], ldq_head) node _T_367 = xor(_T_365, _T_366) node _T_368 = lt(UInt<1>(0h0), ldq_head) node _T_369 = xor(_T_367, _T_368) node _T_370 = eq(_T_369, searcher_is_older) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_32 assert(clock, _T_370, UInt<1>(0h1), "") : assert_32 when searcher_is_older : node _T_374 = or(ldq_executed[0], ldq_succeeded[0]) node _T_375 = eq(s1_executing_loads[0], UInt<1>(0h0)) node _T_376 = and(_T_374, _T_375) node _T_377 = and(_T_376, ldq_observed[0]) when _T_377 : node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_33 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_33 else : node _T_381 = neq(lcam_ldq_idx[0], UInt<1>(0h0)) when _T_381 : node _T_382 = or(ldq_succeeded[0], ldq_will_succeed[0]) node _T_383 = and(ldq_executed[0], _T_382) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_386 = bits(_T_385, 4, 0) connect s1_set_execute[_T_386], UInt<1>(0h0) node _T_387 = eq(s0_kills[0], UInt<1>(0h0)) node _T_388 = and(dmem_req_fire[0], _T_387) reg REG_1 : UInt<1>, clock connect REG_1, _T_388 node _T_389 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_390 = and(REG_1, _T_389) when _T_390 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_1, ldq_uop[1] node _block_addr_matches_T_3 = shr(lcam_addr[0], 6) node _block_addr_matches_T_4 = shr(ldq_addr[1].bits, 6) node _block_addr_matches_T_5 = eq(_block_addr_matches_T_3, _block_addr_matches_T_4) wire block_addr_matches_1 : UInt<1>[1] connect block_addr_matches_1[0], _block_addr_matches_T_5 node _dword_addr_matches_T_4 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_5 = bits(ldq_addr[1].bits, 5, 3) node _dword_addr_matches_T_6 = eq(_dword_addr_matches_T_4, _dword_addr_matches_T_5) node _dword_addr_matches_T_7 = and(block_addr_matches_1[0], _dword_addr_matches_T_6) wire dword_addr_matches_1 : UInt<1>[1] connect dword_addr_matches_1[0], _dword_addr_matches_T_7 node _mask_match_T_2 = and(ldq_ld_byte_mask[1], lcam_mask[0]) node _mask_match_T_3 = eq(_mask_match_T_2, ldq_ld_byte_mask[1]) wire mask_match_1 : UInt<1>[1] connect mask_match_1[0], _mask_match_T_3 node _mask_overlap_T_2 = and(ldq_ld_byte_mask[1], lcam_mask[0]) node _mask_overlap_T_3 = orr(_mask_overlap_T_2) wire mask_overlap_1 : UInt<1>[1] connect mask_overlap_1[0], _mask_overlap_T_3 node _T_391 = and(do_release_search[0], ldq_valid[1]) node _T_392 = and(_T_391, ldq_addr[1].valid) node _T_393 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_394 = and(_T_392, _T_393) node _T_395 = and(_T_394, block_addr_matches_1[0]) when _T_395 : connect ldq_observed[1], UInt<1>(0h1) node _T_396 = and(do_st_search[0], ldq_valid[1]) node _T_397 = and(_T_396, ldq_addr[1].valid) node _T_398 = or(ldq_executed[1], ldq_succeeded[1]) node _T_399 = and(_T_397, _T_398) node _T_400 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_401 = and(_T_399, _T_400) node _T_402 = dshr(ldq_st_dep_mask[1], lcam_stq_idx[0]) node _T_403 = bits(_T_402, 0, 0) node _T_404 = and(_T_401, _T_403) node _T_405 = and(_T_404, dword_addr_matches_1[0]) node _T_406 = and(_T_405, mask_overlap_1[0]) when _T_406 : node _forwarded_is_older_T_4 = lt(ldq_forward_stq_idx[1], lcam_stq_idx[0]) node _forwarded_is_older_T_5 = lt(ldq_forward_stq_idx[1], l_uop_1.stq_idx) node _forwarded_is_older_T_6 = xor(_forwarded_is_older_T_4, _forwarded_is_older_T_5) node _forwarded_is_older_T_7 = lt(lcam_stq_idx[0], l_uop_1.stq_idx) node forwarded_is_older_1 = xor(_forwarded_is_older_T_6, _forwarded_is_older_T_7) node _T_407 = eq(ldq_forward_std_val[1], UInt<1>(0h0)) node _T_408 = neq(ldq_forward_stq_idx[1], lcam_stq_idx[0]) node _T_409 = and(_T_408, forwarded_is_older_1) node _T_410 = or(_T_407, _T_409) when _T_410 : connect ldq_order_fail[1], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_411 = and(do_ld_search[0], ldq_valid[1]) node _T_412 = and(_T_411, ldq_addr[1].valid) node _T_413 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_414 = and(_T_412, _T_413) node _T_415 = and(_T_414, dword_addr_matches_1[0]) node _T_416 = and(_T_415, mask_overlap_1[0]) when _T_416 : node searcher_is_older_1 = bits(lcam_younger_load_mask[0], 1, 1) node _T_417 = lt(lcam_ldq_idx[0], UInt<1>(0h1)) node _T_418 = lt(lcam_ldq_idx[0], ldq_head) node _T_419 = xor(_T_417, _T_418) node _T_420 = lt(UInt<1>(0h1), ldq_head) node _T_421 = xor(_T_419, _T_420) node _T_422 = eq(_T_421, searcher_is_older_1) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_34 assert(clock, _T_422, UInt<1>(0h1), "") : assert_34 when searcher_is_older_1 : node _T_426 = or(ldq_executed[1], ldq_succeeded[1]) node _T_427 = eq(s1_executing_loads[1], UInt<1>(0h0)) node _T_428 = and(_T_426, _T_427) node _T_429 = and(_T_428, ldq_observed[1]) when _T_429 : node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_35 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_35 else : node _T_433 = neq(lcam_ldq_idx[0], UInt<1>(0h1)) when _T_433 : node _T_434 = or(ldq_succeeded[1], ldq_will_succeed[1]) node _T_435 = and(ldq_executed[1], _T_434) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_438 = bits(_T_437, 4, 0) connect s1_set_execute[_T_438], UInt<1>(0h0) node _T_439 = eq(s0_kills[0], UInt<1>(0h0)) node _T_440 = and(dmem_req_fire[0], _T_439) reg REG_2 : UInt<1>, clock connect REG_2, _T_440 node _T_441 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_442 = and(REG_2, _T_441) when _T_442 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_2, ldq_uop[2] node _block_addr_matches_T_6 = shr(lcam_addr[0], 6) node _block_addr_matches_T_7 = shr(ldq_addr[2].bits, 6) node _block_addr_matches_T_8 = eq(_block_addr_matches_T_6, _block_addr_matches_T_7) wire block_addr_matches_2 : UInt<1>[1] connect block_addr_matches_2[0], _block_addr_matches_T_8 node _dword_addr_matches_T_8 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_9 = bits(ldq_addr[2].bits, 5, 3) node _dword_addr_matches_T_10 = eq(_dword_addr_matches_T_8, _dword_addr_matches_T_9) node _dword_addr_matches_T_11 = and(block_addr_matches_2[0], _dword_addr_matches_T_10) wire dword_addr_matches_2 : UInt<1>[1] connect dword_addr_matches_2[0], _dword_addr_matches_T_11 node _mask_match_T_4 = and(ldq_ld_byte_mask[2], lcam_mask[0]) node _mask_match_T_5 = eq(_mask_match_T_4, ldq_ld_byte_mask[2]) wire mask_match_2 : UInt<1>[1] connect mask_match_2[0], _mask_match_T_5 node _mask_overlap_T_4 = and(ldq_ld_byte_mask[2], lcam_mask[0]) node _mask_overlap_T_5 = orr(_mask_overlap_T_4) wire mask_overlap_2 : UInt<1>[1] connect mask_overlap_2[0], _mask_overlap_T_5 node _T_443 = and(do_release_search[0], ldq_valid[2]) node _T_444 = and(_T_443, ldq_addr[2].valid) node _T_445 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_446 = and(_T_444, _T_445) node _T_447 = and(_T_446, block_addr_matches_2[0]) when _T_447 : connect ldq_observed[2], UInt<1>(0h1) node _T_448 = and(do_st_search[0], ldq_valid[2]) node _T_449 = and(_T_448, ldq_addr[2].valid) node _T_450 = or(ldq_executed[2], ldq_succeeded[2]) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_453 = and(_T_451, _T_452) node _T_454 = dshr(ldq_st_dep_mask[2], lcam_stq_idx[0]) node _T_455 = bits(_T_454, 0, 0) node _T_456 = and(_T_453, _T_455) node _T_457 = and(_T_456, dword_addr_matches_2[0]) node _T_458 = and(_T_457, mask_overlap_2[0]) when _T_458 : node _forwarded_is_older_T_8 = lt(ldq_forward_stq_idx[2], lcam_stq_idx[0]) node _forwarded_is_older_T_9 = lt(ldq_forward_stq_idx[2], l_uop_2.stq_idx) node _forwarded_is_older_T_10 = xor(_forwarded_is_older_T_8, _forwarded_is_older_T_9) node _forwarded_is_older_T_11 = lt(lcam_stq_idx[0], l_uop_2.stq_idx) node forwarded_is_older_2 = xor(_forwarded_is_older_T_10, _forwarded_is_older_T_11) node _T_459 = eq(ldq_forward_std_val[2], UInt<1>(0h0)) node _T_460 = neq(ldq_forward_stq_idx[2], lcam_stq_idx[0]) node _T_461 = and(_T_460, forwarded_is_older_2) node _T_462 = or(_T_459, _T_461) when _T_462 : connect ldq_order_fail[2], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_463 = and(do_ld_search[0], ldq_valid[2]) node _T_464 = and(_T_463, ldq_addr[2].valid) node _T_465 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_466 = and(_T_464, _T_465) node _T_467 = and(_T_466, dword_addr_matches_2[0]) node _T_468 = and(_T_467, mask_overlap_2[0]) when _T_468 : node searcher_is_older_2 = bits(lcam_younger_load_mask[0], 2, 2) node _T_469 = lt(lcam_ldq_idx[0], UInt<2>(0h2)) node _T_470 = lt(lcam_ldq_idx[0], ldq_head) node _T_471 = xor(_T_469, _T_470) node _T_472 = lt(UInt<2>(0h2), ldq_head) node _T_473 = xor(_T_471, _T_472) node _T_474 = eq(_T_473, searcher_is_older_2) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_36 assert(clock, _T_474, UInt<1>(0h1), "") : assert_36 when searcher_is_older_2 : node _T_478 = or(ldq_executed[2], ldq_succeeded[2]) node _T_479 = eq(s1_executing_loads[2], UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = and(_T_480, ldq_observed[2]) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_37 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_37 else : node _T_485 = neq(lcam_ldq_idx[0], UInt<2>(0h2)) when _T_485 : node _T_486 = or(ldq_succeeded[2], ldq_will_succeed[2]) node _T_487 = and(ldq_executed[2], _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_490 = bits(_T_489, 4, 0) connect s1_set_execute[_T_490], UInt<1>(0h0) node _T_491 = eq(s0_kills[0], UInt<1>(0h0)) node _T_492 = and(dmem_req_fire[0], _T_491) reg REG_3 : UInt<1>, clock connect REG_3, _T_492 node _T_493 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_494 = and(REG_3, _T_493) when _T_494 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_3, ldq_uop[3] node _block_addr_matches_T_9 = shr(lcam_addr[0], 6) node _block_addr_matches_T_10 = shr(ldq_addr[3].bits, 6) node _block_addr_matches_T_11 = eq(_block_addr_matches_T_9, _block_addr_matches_T_10) wire block_addr_matches_3 : UInt<1>[1] connect block_addr_matches_3[0], _block_addr_matches_T_11 node _dword_addr_matches_T_12 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_13 = bits(ldq_addr[3].bits, 5, 3) node _dword_addr_matches_T_14 = eq(_dword_addr_matches_T_12, _dword_addr_matches_T_13) node _dword_addr_matches_T_15 = and(block_addr_matches_3[0], _dword_addr_matches_T_14) wire dword_addr_matches_3 : UInt<1>[1] connect dword_addr_matches_3[0], _dword_addr_matches_T_15 node _mask_match_T_6 = and(ldq_ld_byte_mask[3], lcam_mask[0]) node _mask_match_T_7 = eq(_mask_match_T_6, ldq_ld_byte_mask[3]) wire mask_match_3 : UInt<1>[1] connect mask_match_3[0], _mask_match_T_7 node _mask_overlap_T_6 = and(ldq_ld_byte_mask[3], lcam_mask[0]) node _mask_overlap_T_7 = orr(_mask_overlap_T_6) wire mask_overlap_3 : UInt<1>[1] connect mask_overlap_3[0], _mask_overlap_T_7 node _T_495 = and(do_release_search[0], ldq_valid[3]) node _T_496 = and(_T_495, ldq_addr[3].valid) node _T_497 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = and(_T_498, block_addr_matches_3[0]) when _T_499 : connect ldq_observed[3], UInt<1>(0h1) node _T_500 = and(do_st_search[0], ldq_valid[3]) node _T_501 = and(_T_500, ldq_addr[3].valid) node _T_502 = or(ldq_executed[3], ldq_succeeded[3]) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = dshr(ldq_st_dep_mask[3], lcam_stq_idx[0]) node _T_507 = bits(_T_506, 0, 0) node _T_508 = and(_T_505, _T_507) node _T_509 = and(_T_508, dword_addr_matches_3[0]) node _T_510 = and(_T_509, mask_overlap_3[0]) when _T_510 : node _forwarded_is_older_T_12 = lt(ldq_forward_stq_idx[3], lcam_stq_idx[0]) node _forwarded_is_older_T_13 = lt(ldq_forward_stq_idx[3], l_uop_3.stq_idx) node _forwarded_is_older_T_14 = xor(_forwarded_is_older_T_12, _forwarded_is_older_T_13) node _forwarded_is_older_T_15 = lt(lcam_stq_idx[0], l_uop_3.stq_idx) node forwarded_is_older_3 = xor(_forwarded_is_older_T_14, _forwarded_is_older_T_15) node _T_511 = eq(ldq_forward_std_val[3], UInt<1>(0h0)) node _T_512 = neq(ldq_forward_stq_idx[3], lcam_stq_idx[0]) node _T_513 = and(_T_512, forwarded_is_older_3) node _T_514 = or(_T_511, _T_513) when _T_514 : connect ldq_order_fail[3], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_515 = and(do_ld_search[0], ldq_valid[3]) node _T_516 = and(_T_515, ldq_addr[3].valid) node _T_517 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_518 = and(_T_516, _T_517) node _T_519 = and(_T_518, dword_addr_matches_3[0]) node _T_520 = and(_T_519, mask_overlap_3[0]) when _T_520 : node searcher_is_older_3 = bits(lcam_younger_load_mask[0], 3, 3) node _T_521 = lt(lcam_ldq_idx[0], UInt<2>(0h3)) node _T_522 = lt(lcam_ldq_idx[0], ldq_head) node _T_523 = xor(_T_521, _T_522) node _T_524 = lt(UInt<2>(0h3), ldq_head) node _T_525 = xor(_T_523, _T_524) node _T_526 = eq(_T_525, searcher_is_older_3) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_38 assert(clock, _T_526, UInt<1>(0h1), "") : assert_38 when searcher_is_older_3 : node _T_530 = or(ldq_executed[3], ldq_succeeded[3]) node _T_531 = eq(s1_executing_loads[3], UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = and(_T_532, ldq_observed[3]) when _T_533 : node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_39 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_39 else : node _T_537 = neq(lcam_ldq_idx[0], UInt<2>(0h3)) when _T_537 : node _T_538 = or(ldq_succeeded[3], ldq_will_succeed[3]) node _T_539 = and(ldq_executed[3], _T_538) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_542 = bits(_T_541, 4, 0) connect s1_set_execute[_T_542], UInt<1>(0h0) node _T_543 = eq(s0_kills[0], UInt<1>(0h0)) node _T_544 = and(dmem_req_fire[0], _T_543) reg REG_4 : UInt<1>, clock connect REG_4, _T_544 node _T_545 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_546 = and(REG_4, _T_545) when _T_546 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_4, ldq_uop[4] node _block_addr_matches_T_12 = shr(lcam_addr[0], 6) node _block_addr_matches_T_13 = shr(ldq_addr[4].bits, 6) node _block_addr_matches_T_14 = eq(_block_addr_matches_T_12, _block_addr_matches_T_13) wire block_addr_matches_4 : UInt<1>[1] connect block_addr_matches_4[0], _block_addr_matches_T_14 node _dword_addr_matches_T_16 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_17 = bits(ldq_addr[4].bits, 5, 3) node _dword_addr_matches_T_18 = eq(_dword_addr_matches_T_16, _dword_addr_matches_T_17) node _dword_addr_matches_T_19 = and(block_addr_matches_4[0], _dword_addr_matches_T_18) wire dword_addr_matches_4 : UInt<1>[1] connect dword_addr_matches_4[0], _dword_addr_matches_T_19 node _mask_match_T_8 = and(ldq_ld_byte_mask[4], lcam_mask[0]) node _mask_match_T_9 = eq(_mask_match_T_8, ldq_ld_byte_mask[4]) wire mask_match_4 : UInt<1>[1] connect mask_match_4[0], _mask_match_T_9 node _mask_overlap_T_8 = and(ldq_ld_byte_mask[4], lcam_mask[0]) node _mask_overlap_T_9 = orr(_mask_overlap_T_8) wire mask_overlap_4 : UInt<1>[1] connect mask_overlap_4[0], _mask_overlap_T_9 node _T_547 = and(do_release_search[0], ldq_valid[4]) node _T_548 = and(_T_547, ldq_addr[4].valid) node _T_549 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) node _T_551 = and(_T_550, block_addr_matches_4[0]) when _T_551 : connect ldq_observed[4], UInt<1>(0h1) node _T_552 = and(do_st_search[0], ldq_valid[4]) node _T_553 = and(_T_552, ldq_addr[4].valid) node _T_554 = or(ldq_executed[4], ldq_succeeded[4]) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_557 = and(_T_555, _T_556) node _T_558 = dshr(ldq_st_dep_mask[4], lcam_stq_idx[0]) node _T_559 = bits(_T_558, 0, 0) node _T_560 = and(_T_557, _T_559) node _T_561 = and(_T_560, dword_addr_matches_4[0]) node _T_562 = and(_T_561, mask_overlap_4[0]) when _T_562 : node _forwarded_is_older_T_16 = lt(ldq_forward_stq_idx[4], lcam_stq_idx[0]) node _forwarded_is_older_T_17 = lt(ldq_forward_stq_idx[4], l_uop_4.stq_idx) node _forwarded_is_older_T_18 = xor(_forwarded_is_older_T_16, _forwarded_is_older_T_17) node _forwarded_is_older_T_19 = lt(lcam_stq_idx[0], l_uop_4.stq_idx) node forwarded_is_older_4 = xor(_forwarded_is_older_T_18, _forwarded_is_older_T_19) node _T_563 = eq(ldq_forward_std_val[4], UInt<1>(0h0)) node _T_564 = neq(ldq_forward_stq_idx[4], lcam_stq_idx[0]) node _T_565 = and(_T_564, forwarded_is_older_4) node _T_566 = or(_T_563, _T_565) when _T_566 : connect ldq_order_fail[4], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_567 = and(do_ld_search[0], ldq_valid[4]) node _T_568 = and(_T_567, ldq_addr[4].valid) node _T_569 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_570 = and(_T_568, _T_569) node _T_571 = and(_T_570, dword_addr_matches_4[0]) node _T_572 = and(_T_571, mask_overlap_4[0]) when _T_572 : node searcher_is_older_4 = bits(lcam_younger_load_mask[0], 4, 4) node _T_573 = lt(lcam_ldq_idx[0], UInt<3>(0h4)) node _T_574 = lt(lcam_ldq_idx[0], ldq_head) node _T_575 = xor(_T_573, _T_574) node _T_576 = lt(UInt<3>(0h4), ldq_head) node _T_577 = xor(_T_575, _T_576) node _T_578 = eq(_T_577, searcher_is_older_4) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_40 assert(clock, _T_578, UInt<1>(0h1), "") : assert_40 when searcher_is_older_4 : node _T_582 = or(ldq_executed[4], ldq_succeeded[4]) node _T_583 = eq(s1_executing_loads[4], UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = and(_T_584, ldq_observed[4]) when _T_585 : node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_41 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_41 else : node _T_589 = neq(lcam_ldq_idx[0], UInt<3>(0h4)) when _T_589 : node _T_590 = or(ldq_succeeded[4], ldq_will_succeed[4]) node _T_591 = and(ldq_executed[4], _T_590) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_594 = bits(_T_593, 4, 0) connect s1_set_execute[_T_594], UInt<1>(0h0) node _T_595 = eq(s0_kills[0], UInt<1>(0h0)) node _T_596 = and(dmem_req_fire[0], _T_595) reg REG_5 : UInt<1>, clock connect REG_5, _T_596 node _T_597 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_598 = and(REG_5, _T_597) when _T_598 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_5, ldq_uop[5] node _block_addr_matches_T_15 = shr(lcam_addr[0], 6) node _block_addr_matches_T_16 = shr(ldq_addr[5].bits, 6) node _block_addr_matches_T_17 = eq(_block_addr_matches_T_15, _block_addr_matches_T_16) wire block_addr_matches_5 : UInt<1>[1] connect block_addr_matches_5[0], _block_addr_matches_T_17 node _dword_addr_matches_T_20 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_21 = bits(ldq_addr[5].bits, 5, 3) node _dword_addr_matches_T_22 = eq(_dword_addr_matches_T_20, _dword_addr_matches_T_21) node _dword_addr_matches_T_23 = and(block_addr_matches_5[0], _dword_addr_matches_T_22) wire dword_addr_matches_5 : UInt<1>[1] connect dword_addr_matches_5[0], _dword_addr_matches_T_23 node _mask_match_T_10 = and(ldq_ld_byte_mask[5], lcam_mask[0]) node _mask_match_T_11 = eq(_mask_match_T_10, ldq_ld_byte_mask[5]) wire mask_match_5 : UInt<1>[1] connect mask_match_5[0], _mask_match_T_11 node _mask_overlap_T_10 = and(ldq_ld_byte_mask[5], lcam_mask[0]) node _mask_overlap_T_11 = orr(_mask_overlap_T_10) wire mask_overlap_5 : UInt<1>[1] connect mask_overlap_5[0], _mask_overlap_T_11 node _T_599 = and(do_release_search[0], ldq_valid[5]) node _T_600 = and(_T_599, ldq_addr[5].valid) node _T_601 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) node _T_603 = and(_T_602, block_addr_matches_5[0]) when _T_603 : connect ldq_observed[5], UInt<1>(0h1) node _T_604 = and(do_st_search[0], ldq_valid[5]) node _T_605 = and(_T_604, ldq_addr[5].valid) node _T_606 = or(ldq_executed[5], ldq_succeeded[5]) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_609 = and(_T_607, _T_608) node _T_610 = dshr(ldq_st_dep_mask[5], lcam_stq_idx[0]) node _T_611 = bits(_T_610, 0, 0) node _T_612 = and(_T_609, _T_611) node _T_613 = and(_T_612, dword_addr_matches_5[0]) node _T_614 = and(_T_613, mask_overlap_5[0]) when _T_614 : node _forwarded_is_older_T_20 = lt(ldq_forward_stq_idx[5], lcam_stq_idx[0]) node _forwarded_is_older_T_21 = lt(ldq_forward_stq_idx[5], l_uop_5.stq_idx) node _forwarded_is_older_T_22 = xor(_forwarded_is_older_T_20, _forwarded_is_older_T_21) node _forwarded_is_older_T_23 = lt(lcam_stq_idx[0], l_uop_5.stq_idx) node forwarded_is_older_5 = xor(_forwarded_is_older_T_22, _forwarded_is_older_T_23) node _T_615 = eq(ldq_forward_std_val[5], UInt<1>(0h0)) node _T_616 = neq(ldq_forward_stq_idx[5], lcam_stq_idx[0]) node _T_617 = and(_T_616, forwarded_is_older_5) node _T_618 = or(_T_615, _T_617) when _T_618 : connect ldq_order_fail[5], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_619 = and(do_ld_search[0], ldq_valid[5]) node _T_620 = and(_T_619, ldq_addr[5].valid) node _T_621 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) node _T_623 = and(_T_622, dword_addr_matches_5[0]) node _T_624 = and(_T_623, mask_overlap_5[0]) when _T_624 : node searcher_is_older_5 = bits(lcam_younger_load_mask[0], 5, 5) node _T_625 = lt(lcam_ldq_idx[0], UInt<3>(0h5)) node _T_626 = lt(lcam_ldq_idx[0], ldq_head) node _T_627 = xor(_T_625, _T_626) node _T_628 = lt(UInt<3>(0h5), ldq_head) node _T_629 = xor(_T_627, _T_628) node _T_630 = eq(_T_629, searcher_is_older_5) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_42 assert(clock, _T_630, UInt<1>(0h1), "") : assert_42 when searcher_is_older_5 : node _T_634 = or(ldq_executed[5], ldq_succeeded[5]) node _T_635 = eq(s1_executing_loads[5], UInt<1>(0h0)) node _T_636 = and(_T_634, _T_635) node _T_637 = and(_T_636, ldq_observed[5]) when _T_637 : node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_43 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_43 else : node _T_641 = neq(lcam_ldq_idx[0], UInt<3>(0h5)) when _T_641 : node _T_642 = or(ldq_succeeded[5], ldq_will_succeed[5]) node _T_643 = and(ldq_executed[5], _T_642) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_646 = bits(_T_645, 4, 0) connect s1_set_execute[_T_646], UInt<1>(0h0) node _T_647 = eq(s0_kills[0], UInt<1>(0h0)) node _T_648 = and(dmem_req_fire[0], _T_647) reg REG_6 : UInt<1>, clock connect REG_6, _T_648 node _T_649 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_650 = and(REG_6, _T_649) when _T_650 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_6, ldq_uop[6] node _block_addr_matches_T_18 = shr(lcam_addr[0], 6) node _block_addr_matches_T_19 = shr(ldq_addr[6].bits, 6) node _block_addr_matches_T_20 = eq(_block_addr_matches_T_18, _block_addr_matches_T_19) wire block_addr_matches_6 : UInt<1>[1] connect block_addr_matches_6[0], _block_addr_matches_T_20 node _dword_addr_matches_T_24 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_25 = bits(ldq_addr[6].bits, 5, 3) node _dword_addr_matches_T_26 = eq(_dword_addr_matches_T_24, _dword_addr_matches_T_25) node _dword_addr_matches_T_27 = and(block_addr_matches_6[0], _dword_addr_matches_T_26) wire dword_addr_matches_6 : UInt<1>[1] connect dword_addr_matches_6[0], _dword_addr_matches_T_27 node _mask_match_T_12 = and(ldq_ld_byte_mask[6], lcam_mask[0]) node _mask_match_T_13 = eq(_mask_match_T_12, ldq_ld_byte_mask[6]) wire mask_match_6 : UInt<1>[1] connect mask_match_6[0], _mask_match_T_13 node _mask_overlap_T_12 = and(ldq_ld_byte_mask[6], lcam_mask[0]) node _mask_overlap_T_13 = orr(_mask_overlap_T_12) wire mask_overlap_6 : UInt<1>[1] connect mask_overlap_6[0], _mask_overlap_T_13 node _T_651 = and(do_release_search[0], ldq_valid[6]) node _T_652 = and(_T_651, ldq_addr[6].valid) node _T_653 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_654 = and(_T_652, _T_653) node _T_655 = and(_T_654, block_addr_matches_6[0]) when _T_655 : connect ldq_observed[6], UInt<1>(0h1) node _T_656 = and(do_st_search[0], ldq_valid[6]) node _T_657 = and(_T_656, ldq_addr[6].valid) node _T_658 = or(ldq_executed[6], ldq_succeeded[6]) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_661 = and(_T_659, _T_660) node _T_662 = dshr(ldq_st_dep_mask[6], lcam_stq_idx[0]) node _T_663 = bits(_T_662, 0, 0) node _T_664 = and(_T_661, _T_663) node _T_665 = and(_T_664, dword_addr_matches_6[0]) node _T_666 = and(_T_665, mask_overlap_6[0]) when _T_666 : node _forwarded_is_older_T_24 = lt(ldq_forward_stq_idx[6], lcam_stq_idx[0]) node _forwarded_is_older_T_25 = lt(ldq_forward_stq_idx[6], l_uop_6.stq_idx) node _forwarded_is_older_T_26 = xor(_forwarded_is_older_T_24, _forwarded_is_older_T_25) node _forwarded_is_older_T_27 = lt(lcam_stq_idx[0], l_uop_6.stq_idx) node forwarded_is_older_6 = xor(_forwarded_is_older_T_26, _forwarded_is_older_T_27) node _T_667 = eq(ldq_forward_std_val[6], UInt<1>(0h0)) node _T_668 = neq(ldq_forward_stq_idx[6], lcam_stq_idx[0]) node _T_669 = and(_T_668, forwarded_is_older_6) node _T_670 = or(_T_667, _T_669) when _T_670 : connect ldq_order_fail[6], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_671 = and(do_ld_search[0], ldq_valid[6]) node _T_672 = and(_T_671, ldq_addr[6].valid) node _T_673 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_674 = and(_T_672, _T_673) node _T_675 = and(_T_674, dword_addr_matches_6[0]) node _T_676 = and(_T_675, mask_overlap_6[0]) when _T_676 : node searcher_is_older_6 = bits(lcam_younger_load_mask[0], 6, 6) node _T_677 = lt(lcam_ldq_idx[0], UInt<3>(0h6)) node _T_678 = lt(lcam_ldq_idx[0], ldq_head) node _T_679 = xor(_T_677, _T_678) node _T_680 = lt(UInt<3>(0h6), ldq_head) node _T_681 = xor(_T_679, _T_680) node _T_682 = eq(_T_681, searcher_is_older_6) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_44 assert(clock, _T_682, UInt<1>(0h1), "") : assert_44 when searcher_is_older_6 : node _T_686 = or(ldq_executed[6], ldq_succeeded[6]) node _T_687 = eq(s1_executing_loads[6], UInt<1>(0h0)) node _T_688 = and(_T_686, _T_687) node _T_689 = and(_T_688, ldq_observed[6]) when _T_689 : node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_45 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_45 else : node _T_693 = neq(lcam_ldq_idx[0], UInt<3>(0h6)) when _T_693 : node _T_694 = or(ldq_succeeded[6], ldq_will_succeed[6]) node _T_695 = and(ldq_executed[6], _T_694) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_698 = bits(_T_697, 4, 0) connect s1_set_execute[_T_698], UInt<1>(0h0) node _T_699 = eq(s0_kills[0], UInt<1>(0h0)) node _T_700 = and(dmem_req_fire[0], _T_699) reg REG_7 : UInt<1>, clock connect REG_7, _T_700 node _T_701 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_702 = and(REG_7, _T_701) when _T_702 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_7, ldq_uop[7] node _block_addr_matches_T_21 = shr(lcam_addr[0], 6) node _block_addr_matches_T_22 = shr(ldq_addr[7].bits, 6) node _block_addr_matches_T_23 = eq(_block_addr_matches_T_21, _block_addr_matches_T_22) wire block_addr_matches_7 : UInt<1>[1] connect block_addr_matches_7[0], _block_addr_matches_T_23 node _dword_addr_matches_T_28 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_29 = bits(ldq_addr[7].bits, 5, 3) node _dword_addr_matches_T_30 = eq(_dword_addr_matches_T_28, _dword_addr_matches_T_29) node _dword_addr_matches_T_31 = and(block_addr_matches_7[0], _dword_addr_matches_T_30) wire dword_addr_matches_7 : UInt<1>[1] connect dword_addr_matches_7[0], _dword_addr_matches_T_31 node _mask_match_T_14 = and(ldq_ld_byte_mask[7], lcam_mask[0]) node _mask_match_T_15 = eq(_mask_match_T_14, ldq_ld_byte_mask[7]) wire mask_match_7 : UInt<1>[1] connect mask_match_7[0], _mask_match_T_15 node _mask_overlap_T_14 = and(ldq_ld_byte_mask[7], lcam_mask[0]) node _mask_overlap_T_15 = orr(_mask_overlap_T_14) wire mask_overlap_7 : UInt<1>[1] connect mask_overlap_7[0], _mask_overlap_T_15 node _T_703 = and(do_release_search[0], ldq_valid[7]) node _T_704 = and(_T_703, ldq_addr[7].valid) node _T_705 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, block_addr_matches_7[0]) when _T_707 : connect ldq_observed[7], UInt<1>(0h1) node _T_708 = and(do_st_search[0], ldq_valid[7]) node _T_709 = and(_T_708, ldq_addr[7].valid) node _T_710 = or(ldq_executed[7], ldq_succeeded[7]) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_713 = and(_T_711, _T_712) node _T_714 = dshr(ldq_st_dep_mask[7], lcam_stq_idx[0]) node _T_715 = bits(_T_714, 0, 0) node _T_716 = and(_T_713, _T_715) node _T_717 = and(_T_716, dword_addr_matches_7[0]) node _T_718 = and(_T_717, mask_overlap_7[0]) when _T_718 : node _forwarded_is_older_T_28 = lt(ldq_forward_stq_idx[7], lcam_stq_idx[0]) node _forwarded_is_older_T_29 = lt(ldq_forward_stq_idx[7], l_uop_7.stq_idx) node _forwarded_is_older_T_30 = xor(_forwarded_is_older_T_28, _forwarded_is_older_T_29) node _forwarded_is_older_T_31 = lt(lcam_stq_idx[0], l_uop_7.stq_idx) node forwarded_is_older_7 = xor(_forwarded_is_older_T_30, _forwarded_is_older_T_31) node _T_719 = eq(ldq_forward_std_val[7], UInt<1>(0h0)) node _T_720 = neq(ldq_forward_stq_idx[7], lcam_stq_idx[0]) node _T_721 = and(_T_720, forwarded_is_older_7) node _T_722 = or(_T_719, _T_721) when _T_722 : connect ldq_order_fail[7], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_723 = and(do_ld_search[0], ldq_valid[7]) node _T_724 = and(_T_723, ldq_addr[7].valid) node _T_725 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_726 = and(_T_724, _T_725) node _T_727 = and(_T_726, dword_addr_matches_7[0]) node _T_728 = and(_T_727, mask_overlap_7[0]) when _T_728 : node searcher_is_older_7 = bits(lcam_younger_load_mask[0], 7, 7) node _T_729 = lt(lcam_ldq_idx[0], UInt<3>(0h7)) node _T_730 = lt(lcam_ldq_idx[0], ldq_head) node _T_731 = xor(_T_729, _T_730) node _T_732 = lt(UInt<3>(0h7), ldq_head) node _T_733 = xor(_T_731, _T_732) node _T_734 = eq(_T_733, searcher_is_older_7) node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_T_734, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_46 assert(clock, _T_734, UInt<1>(0h1), "") : assert_46 when searcher_is_older_7 : node _T_738 = or(ldq_executed[7], ldq_succeeded[7]) node _T_739 = eq(s1_executing_loads[7], UInt<1>(0h0)) node _T_740 = and(_T_738, _T_739) node _T_741 = and(_T_740, ldq_observed[7]) when _T_741 : node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_47 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_47 else : node _T_745 = neq(lcam_ldq_idx[0], UInt<3>(0h7)) when _T_745 : node _T_746 = or(ldq_succeeded[7], ldq_will_succeed[7]) node _T_747 = and(ldq_executed[7], _T_746) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_750 = bits(_T_749, 4, 0) connect s1_set_execute[_T_750], UInt<1>(0h0) node _T_751 = eq(s0_kills[0], UInt<1>(0h0)) node _T_752 = and(dmem_req_fire[0], _T_751) reg REG_8 : UInt<1>, clock connect REG_8, _T_752 node _T_753 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_754 = and(REG_8, _T_753) when _T_754 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_8, ldq_uop[8] node _block_addr_matches_T_24 = shr(lcam_addr[0], 6) node _block_addr_matches_T_25 = shr(ldq_addr[8].bits, 6) node _block_addr_matches_T_26 = eq(_block_addr_matches_T_24, _block_addr_matches_T_25) wire block_addr_matches_8 : UInt<1>[1] connect block_addr_matches_8[0], _block_addr_matches_T_26 node _dword_addr_matches_T_32 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_33 = bits(ldq_addr[8].bits, 5, 3) node _dword_addr_matches_T_34 = eq(_dword_addr_matches_T_32, _dword_addr_matches_T_33) node _dword_addr_matches_T_35 = and(block_addr_matches_8[0], _dword_addr_matches_T_34) wire dword_addr_matches_8 : UInt<1>[1] connect dword_addr_matches_8[0], _dword_addr_matches_T_35 node _mask_match_T_16 = and(ldq_ld_byte_mask[8], lcam_mask[0]) node _mask_match_T_17 = eq(_mask_match_T_16, ldq_ld_byte_mask[8]) wire mask_match_8 : UInt<1>[1] connect mask_match_8[0], _mask_match_T_17 node _mask_overlap_T_16 = and(ldq_ld_byte_mask[8], lcam_mask[0]) node _mask_overlap_T_17 = orr(_mask_overlap_T_16) wire mask_overlap_8 : UInt<1>[1] connect mask_overlap_8[0], _mask_overlap_T_17 node _T_755 = and(do_release_search[0], ldq_valid[8]) node _T_756 = and(_T_755, ldq_addr[8].valid) node _T_757 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_758 = and(_T_756, _T_757) node _T_759 = and(_T_758, block_addr_matches_8[0]) when _T_759 : connect ldq_observed[8], UInt<1>(0h1) node _T_760 = and(do_st_search[0], ldq_valid[8]) node _T_761 = and(_T_760, ldq_addr[8].valid) node _T_762 = or(ldq_executed[8], ldq_succeeded[8]) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_765 = and(_T_763, _T_764) node _T_766 = dshr(ldq_st_dep_mask[8], lcam_stq_idx[0]) node _T_767 = bits(_T_766, 0, 0) node _T_768 = and(_T_765, _T_767) node _T_769 = and(_T_768, dword_addr_matches_8[0]) node _T_770 = and(_T_769, mask_overlap_8[0]) when _T_770 : node _forwarded_is_older_T_32 = lt(ldq_forward_stq_idx[8], lcam_stq_idx[0]) node _forwarded_is_older_T_33 = lt(ldq_forward_stq_idx[8], l_uop_8.stq_idx) node _forwarded_is_older_T_34 = xor(_forwarded_is_older_T_32, _forwarded_is_older_T_33) node _forwarded_is_older_T_35 = lt(lcam_stq_idx[0], l_uop_8.stq_idx) node forwarded_is_older_8 = xor(_forwarded_is_older_T_34, _forwarded_is_older_T_35) node _T_771 = eq(ldq_forward_std_val[8], UInt<1>(0h0)) node _T_772 = neq(ldq_forward_stq_idx[8], lcam_stq_idx[0]) node _T_773 = and(_T_772, forwarded_is_older_8) node _T_774 = or(_T_771, _T_773) when _T_774 : connect ldq_order_fail[8], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_775 = and(do_ld_search[0], ldq_valid[8]) node _T_776 = and(_T_775, ldq_addr[8].valid) node _T_777 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_778 = and(_T_776, _T_777) node _T_779 = and(_T_778, dword_addr_matches_8[0]) node _T_780 = and(_T_779, mask_overlap_8[0]) when _T_780 : node searcher_is_older_8 = bits(lcam_younger_load_mask[0], 8, 8) node _T_781 = lt(lcam_ldq_idx[0], UInt<4>(0h8)) node _T_782 = lt(lcam_ldq_idx[0], ldq_head) node _T_783 = xor(_T_781, _T_782) node _T_784 = lt(UInt<4>(0h8), ldq_head) node _T_785 = xor(_T_783, _T_784) node _T_786 = eq(_T_785, searcher_is_older_8) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_48 assert(clock, _T_786, UInt<1>(0h1), "") : assert_48 when searcher_is_older_8 : node _T_790 = or(ldq_executed[8], ldq_succeeded[8]) node _T_791 = eq(s1_executing_loads[8], UInt<1>(0h0)) node _T_792 = and(_T_790, _T_791) node _T_793 = and(_T_792, ldq_observed[8]) when _T_793 : node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_49 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_49 else : node _T_797 = neq(lcam_ldq_idx[0], UInt<4>(0h8)) when _T_797 : node _T_798 = or(ldq_succeeded[8], ldq_will_succeed[8]) node _T_799 = and(ldq_executed[8], _T_798) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_802 = bits(_T_801, 4, 0) connect s1_set_execute[_T_802], UInt<1>(0h0) node _T_803 = eq(s0_kills[0], UInt<1>(0h0)) node _T_804 = and(dmem_req_fire[0], _T_803) reg REG_9 : UInt<1>, clock connect REG_9, _T_804 node _T_805 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_806 = and(REG_9, _T_805) when _T_806 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_9, ldq_uop[9] node _block_addr_matches_T_27 = shr(lcam_addr[0], 6) node _block_addr_matches_T_28 = shr(ldq_addr[9].bits, 6) node _block_addr_matches_T_29 = eq(_block_addr_matches_T_27, _block_addr_matches_T_28) wire block_addr_matches_9 : UInt<1>[1] connect block_addr_matches_9[0], _block_addr_matches_T_29 node _dword_addr_matches_T_36 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_37 = bits(ldq_addr[9].bits, 5, 3) node _dword_addr_matches_T_38 = eq(_dword_addr_matches_T_36, _dword_addr_matches_T_37) node _dword_addr_matches_T_39 = and(block_addr_matches_9[0], _dword_addr_matches_T_38) wire dword_addr_matches_9 : UInt<1>[1] connect dword_addr_matches_9[0], _dword_addr_matches_T_39 node _mask_match_T_18 = and(ldq_ld_byte_mask[9], lcam_mask[0]) node _mask_match_T_19 = eq(_mask_match_T_18, ldq_ld_byte_mask[9]) wire mask_match_9 : UInt<1>[1] connect mask_match_9[0], _mask_match_T_19 node _mask_overlap_T_18 = and(ldq_ld_byte_mask[9], lcam_mask[0]) node _mask_overlap_T_19 = orr(_mask_overlap_T_18) wire mask_overlap_9 : UInt<1>[1] connect mask_overlap_9[0], _mask_overlap_T_19 node _T_807 = and(do_release_search[0], ldq_valid[9]) node _T_808 = and(_T_807, ldq_addr[9].valid) node _T_809 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_810 = and(_T_808, _T_809) node _T_811 = and(_T_810, block_addr_matches_9[0]) when _T_811 : connect ldq_observed[9], UInt<1>(0h1) node _T_812 = and(do_st_search[0], ldq_valid[9]) node _T_813 = and(_T_812, ldq_addr[9].valid) node _T_814 = or(ldq_executed[9], ldq_succeeded[9]) node _T_815 = and(_T_813, _T_814) node _T_816 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_817 = and(_T_815, _T_816) node _T_818 = dshr(ldq_st_dep_mask[9], lcam_stq_idx[0]) node _T_819 = bits(_T_818, 0, 0) node _T_820 = and(_T_817, _T_819) node _T_821 = and(_T_820, dword_addr_matches_9[0]) node _T_822 = and(_T_821, mask_overlap_9[0]) when _T_822 : node _forwarded_is_older_T_36 = lt(ldq_forward_stq_idx[9], lcam_stq_idx[0]) node _forwarded_is_older_T_37 = lt(ldq_forward_stq_idx[9], l_uop_9.stq_idx) node _forwarded_is_older_T_38 = xor(_forwarded_is_older_T_36, _forwarded_is_older_T_37) node _forwarded_is_older_T_39 = lt(lcam_stq_idx[0], l_uop_9.stq_idx) node forwarded_is_older_9 = xor(_forwarded_is_older_T_38, _forwarded_is_older_T_39) node _T_823 = eq(ldq_forward_std_val[9], UInt<1>(0h0)) node _T_824 = neq(ldq_forward_stq_idx[9], lcam_stq_idx[0]) node _T_825 = and(_T_824, forwarded_is_older_9) node _T_826 = or(_T_823, _T_825) when _T_826 : connect ldq_order_fail[9], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_827 = and(do_ld_search[0], ldq_valid[9]) node _T_828 = and(_T_827, ldq_addr[9].valid) node _T_829 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_830 = and(_T_828, _T_829) node _T_831 = and(_T_830, dword_addr_matches_9[0]) node _T_832 = and(_T_831, mask_overlap_9[0]) when _T_832 : node searcher_is_older_9 = bits(lcam_younger_load_mask[0], 9, 9) node _T_833 = lt(lcam_ldq_idx[0], UInt<4>(0h9)) node _T_834 = lt(lcam_ldq_idx[0], ldq_head) node _T_835 = xor(_T_833, _T_834) node _T_836 = lt(UInt<4>(0h9), ldq_head) node _T_837 = xor(_T_835, _T_836) node _T_838 = eq(_T_837, searcher_is_older_9) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_50 assert(clock, _T_838, UInt<1>(0h1), "") : assert_50 when searcher_is_older_9 : node _T_842 = or(ldq_executed[9], ldq_succeeded[9]) node _T_843 = eq(s1_executing_loads[9], UInt<1>(0h0)) node _T_844 = and(_T_842, _T_843) node _T_845 = and(_T_844, ldq_observed[9]) when _T_845 : node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_51 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_51 else : node _T_849 = neq(lcam_ldq_idx[0], UInt<4>(0h9)) when _T_849 : node _T_850 = or(ldq_succeeded[9], ldq_will_succeed[9]) node _T_851 = and(ldq_executed[9], _T_850) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_854 = bits(_T_853, 4, 0) connect s1_set_execute[_T_854], UInt<1>(0h0) node _T_855 = eq(s0_kills[0], UInt<1>(0h0)) node _T_856 = and(dmem_req_fire[0], _T_855) reg REG_10 : UInt<1>, clock connect REG_10, _T_856 node _T_857 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_858 = and(REG_10, _T_857) when _T_858 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_10, ldq_uop[10] node _block_addr_matches_T_30 = shr(lcam_addr[0], 6) node _block_addr_matches_T_31 = shr(ldq_addr[10].bits, 6) node _block_addr_matches_T_32 = eq(_block_addr_matches_T_30, _block_addr_matches_T_31) wire block_addr_matches_10 : UInt<1>[1] connect block_addr_matches_10[0], _block_addr_matches_T_32 node _dword_addr_matches_T_40 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_41 = bits(ldq_addr[10].bits, 5, 3) node _dword_addr_matches_T_42 = eq(_dword_addr_matches_T_40, _dword_addr_matches_T_41) node _dword_addr_matches_T_43 = and(block_addr_matches_10[0], _dword_addr_matches_T_42) wire dword_addr_matches_10 : UInt<1>[1] connect dword_addr_matches_10[0], _dword_addr_matches_T_43 node _mask_match_T_20 = and(ldq_ld_byte_mask[10], lcam_mask[0]) node _mask_match_T_21 = eq(_mask_match_T_20, ldq_ld_byte_mask[10]) wire mask_match_10 : UInt<1>[1] connect mask_match_10[0], _mask_match_T_21 node _mask_overlap_T_20 = and(ldq_ld_byte_mask[10], lcam_mask[0]) node _mask_overlap_T_21 = orr(_mask_overlap_T_20) wire mask_overlap_10 : UInt<1>[1] connect mask_overlap_10[0], _mask_overlap_T_21 node _T_859 = and(do_release_search[0], ldq_valid[10]) node _T_860 = and(_T_859, ldq_addr[10].valid) node _T_861 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_862 = and(_T_860, _T_861) node _T_863 = and(_T_862, block_addr_matches_10[0]) when _T_863 : connect ldq_observed[10], UInt<1>(0h1) node _T_864 = and(do_st_search[0], ldq_valid[10]) node _T_865 = and(_T_864, ldq_addr[10].valid) node _T_866 = or(ldq_executed[10], ldq_succeeded[10]) node _T_867 = and(_T_865, _T_866) node _T_868 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_869 = and(_T_867, _T_868) node _T_870 = dshr(ldq_st_dep_mask[10], lcam_stq_idx[0]) node _T_871 = bits(_T_870, 0, 0) node _T_872 = and(_T_869, _T_871) node _T_873 = and(_T_872, dword_addr_matches_10[0]) node _T_874 = and(_T_873, mask_overlap_10[0]) when _T_874 : node _forwarded_is_older_T_40 = lt(ldq_forward_stq_idx[10], lcam_stq_idx[0]) node _forwarded_is_older_T_41 = lt(ldq_forward_stq_idx[10], l_uop_10.stq_idx) node _forwarded_is_older_T_42 = xor(_forwarded_is_older_T_40, _forwarded_is_older_T_41) node _forwarded_is_older_T_43 = lt(lcam_stq_idx[0], l_uop_10.stq_idx) node forwarded_is_older_10 = xor(_forwarded_is_older_T_42, _forwarded_is_older_T_43) node _T_875 = eq(ldq_forward_std_val[10], UInt<1>(0h0)) node _T_876 = neq(ldq_forward_stq_idx[10], lcam_stq_idx[0]) node _T_877 = and(_T_876, forwarded_is_older_10) node _T_878 = or(_T_875, _T_877) when _T_878 : connect ldq_order_fail[10], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_879 = and(do_ld_search[0], ldq_valid[10]) node _T_880 = and(_T_879, ldq_addr[10].valid) node _T_881 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_882 = and(_T_880, _T_881) node _T_883 = and(_T_882, dword_addr_matches_10[0]) node _T_884 = and(_T_883, mask_overlap_10[0]) when _T_884 : node searcher_is_older_10 = bits(lcam_younger_load_mask[0], 10, 10) node _T_885 = lt(lcam_ldq_idx[0], UInt<4>(0ha)) node _T_886 = lt(lcam_ldq_idx[0], ldq_head) node _T_887 = xor(_T_885, _T_886) node _T_888 = lt(UInt<4>(0ha), ldq_head) node _T_889 = xor(_T_887, _T_888) node _T_890 = eq(_T_889, searcher_is_older_10) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_52 assert(clock, _T_890, UInt<1>(0h1), "") : assert_52 when searcher_is_older_10 : node _T_894 = or(ldq_executed[10], ldq_succeeded[10]) node _T_895 = eq(s1_executing_loads[10], UInt<1>(0h0)) node _T_896 = and(_T_894, _T_895) node _T_897 = and(_T_896, ldq_observed[10]) when _T_897 : node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_53 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_53 else : node _T_901 = neq(lcam_ldq_idx[0], UInt<4>(0ha)) when _T_901 : node _T_902 = or(ldq_succeeded[10], ldq_will_succeed[10]) node _T_903 = and(ldq_executed[10], _T_902) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_906 = bits(_T_905, 4, 0) connect s1_set_execute[_T_906], UInt<1>(0h0) node _T_907 = eq(s0_kills[0], UInt<1>(0h0)) node _T_908 = and(dmem_req_fire[0], _T_907) reg REG_11 : UInt<1>, clock connect REG_11, _T_908 node _T_909 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_910 = and(REG_11, _T_909) when _T_910 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_11, ldq_uop[11] node _block_addr_matches_T_33 = shr(lcam_addr[0], 6) node _block_addr_matches_T_34 = shr(ldq_addr[11].bits, 6) node _block_addr_matches_T_35 = eq(_block_addr_matches_T_33, _block_addr_matches_T_34) wire block_addr_matches_11 : UInt<1>[1] connect block_addr_matches_11[0], _block_addr_matches_T_35 node _dword_addr_matches_T_44 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_45 = bits(ldq_addr[11].bits, 5, 3) node _dword_addr_matches_T_46 = eq(_dword_addr_matches_T_44, _dword_addr_matches_T_45) node _dword_addr_matches_T_47 = and(block_addr_matches_11[0], _dword_addr_matches_T_46) wire dword_addr_matches_11 : UInt<1>[1] connect dword_addr_matches_11[0], _dword_addr_matches_T_47 node _mask_match_T_22 = and(ldq_ld_byte_mask[11], lcam_mask[0]) node _mask_match_T_23 = eq(_mask_match_T_22, ldq_ld_byte_mask[11]) wire mask_match_11 : UInt<1>[1] connect mask_match_11[0], _mask_match_T_23 node _mask_overlap_T_22 = and(ldq_ld_byte_mask[11], lcam_mask[0]) node _mask_overlap_T_23 = orr(_mask_overlap_T_22) wire mask_overlap_11 : UInt<1>[1] connect mask_overlap_11[0], _mask_overlap_T_23 node _T_911 = and(do_release_search[0], ldq_valid[11]) node _T_912 = and(_T_911, ldq_addr[11].valid) node _T_913 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_914 = and(_T_912, _T_913) node _T_915 = and(_T_914, block_addr_matches_11[0]) when _T_915 : connect ldq_observed[11], UInt<1>(0h1) node _T_916 = and(do_st_search[0], ldq_valid[11]) node _T_917 = and(_T_916, ldq_addr[11].valid) node _T_918 = or(ldq_executed[11], ldq_succeeded[11]) node _T_919 = and(_T_917, _T_918) node _T_920 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) node _T_922 = dshr(ldq_st_dep_mask[11], lcam_stq_idx[0]) node _T_923 = bits(_T_922, 0, 0) node _T_924 = and(_T_921, _T_923) node _T_925 = and(_T_924, dword_addr_matches_11[0]) node _T_926 = and(_T_925, mask_overlap_11[0]) when _T_926 : node _forwarded_is_older_T_44 = lt(ldq_forward_stq_idx[11], lcam_stq_idx[0]) node _forwarded_is_older_T_45 = lt(ldq_forward_stq_idx[11], l_uop_11.stq_idx) node _forwarded_is_older_T_46 = xor(_forwarded_is_older_T_44, _forwarded_is_older_T_45) node _forwarded_is_older_T_47 = lt(lcam_stq_idx[0], l_uop_11.stq_idx) node forwarded_is_older_11 = xor(_forwarded_is_older_T_46, _forwarded_is_older_T_47) node _T_927 = eq(ldq_forward_std_val[11], UInt<1>(0h0)) node _T_928 = neq(ldq_forward_stq_idx[11], lcam_stq_idx[0]) node _T_929 = and(_T_928, forwarded_is_older_11) node _T_930 = or(_T_927, _T_929) when _T_930 : connect ldq_order_fail[11], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_931 = and(do_ld_search[0], ldq_valid[11]) node _T_932 = and(_T_931, ldq_addr[11].valid) node _T_933 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_934 = and(_T_932, _T_933) node _T_935 = and(_T_934, dword_addr_matches_11[0]) node _T_936 = and(_T_935, mask_overlap_11[0]) when _T_936 : node searcher_is_older_11 = bits(lcam_younger_load_mask[0], 11, 11) node _T_937 = lt(lcam_ldq_idx[0], UInt<4>(0hb)) node _T_938 = lt(lcam_ldq_idx[0], ldq_head) node _T_939 = xor(_T_937, _T_938) node _T_940 = lt(UInt<4>(0hb), ldq_head) node _T_941 = xor(_T_939, _T_940) node _T_942 = eq(_T_941, searcher_is_older_11) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_54 assert(clock, _T_942, UInt<1>(0h1), "") : assert_54 when searcher_is_older_11 : node _T_946 = or(ldq_executed[11], ldq_succeeded[11]) node _T_947 = eq(s1_executing_loads[11], UInt<1>(0h0)) node _T_948 = and(_T_946, _T_947) node _T_949 = and(_T_948, ldq_observed[11]) when _T_949 : node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_55 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_55 else : node _T_953 = neq(lcam_ldq_idx[0], UInt<4>(0hb)) when _T_953 : node _T_954 = or(ldq_succeeded[11], ldq_will_succeed[11]) node _T_955 = and(ldq_executed[11], _T_954) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_958 = bits(_T_957, 4, 0) connect s1_set_execute[_T_958], UInt<1>(0h0) node _T_959 = eq(s0_kills[0], UInt<1>(0h0)) node _T_960 = and(dmem_req_fire[0], _T_959) reg REG_12 : UInt<1>, clock connect REG_12, _T_960 node _T_961 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_962 = and(REG_12, _T_961) when _T_962 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_12, ldq_uop[12] node _block_addr_matches_T_36 = shr(lcam_addr[0], 6) node _block_addr_matches_T_37 = shr(ldq_addr[12].bits, 6) node _block_addr_matches_T_38 = eq(_block_addr_matches_T_36, _block_addr_matches_T_37) wire block_addr_matches_12 : UInt<1>[1] connect block_addr_matches_12[0], _block_addr_matches_T_38 node _dword_addr_matches_T_48 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_49 = bits(ldq_addr[12].bits, 5, 3) node _dword_addr_matches_T_50 = eq(_dword_addr_matches_T_48, _dword_addr_matches_T_49) node _dword_addr_matches_T_51 = and(block_addr_matches_12[0], _dword_addr_matches_T_50) wire dword_addr_matches_12 : UInt<1>[1] connect dword_addr_matches_12[0], _dword_addr_matches_T_51 node _mask_match_T_24 = and(ldq_ld_byte_mask[12], lcam_mask[0]) node _mask_match_T_25 = eq(_mask_match_T_24, ldq_ld_byte_mask[12]) wire mask_match_12 : UInt<1>[1] connect mask_match_12[0], _mask_match_T_25 node _mask_overlap_T_24 = and(ldq_ld_byte_mask[12], lcam_mask[0]) node _mask_overlap_T_25 = orr(_mask_overlap_T_24) wire mask_overlap_12 : UInt<1>[1] connect mask_overlap_12[0], _mask_overlap_T_25 node _T_963 = and(do_release_search[0], ldq_valid[12]) node _T_964 = and(_T_963, ldq_addr[12].valid) node _T_965 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_966 = and(_T_964, _T_965) node _T_967 = and(_T_966, block_addr_matches_12[0]) when _T_967 : connect ldq_observed[12], UInt<1>(0h1) node _T_968 = and(do_st_search[0], ldq_valid[12]) node _T_969 = and(_T_968, ldq_addr[12].valid) node _T_970 = or(ldq_executed[12], ldq_succeeded[12]) node _T_971 = and(_T_969, _T_970) node _T_972 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_973 = and(_T_971, _T_972) node _T_974 = dshr(ldq_st_dep_mask[12], lcam_stq_idx[0]) node _T_975 = bits(_T_974, 0, 0) node _T_976 = and(_T_973, _T_975) node _T_977 = and(_T_976, dword_addr_matches_12[0]) node _T_978 = and(_T_977, mask_overlap_12[0]) when _T_978 : node _forwarded_is_older_T_48 = lt(ldq_forward_stq_idx[12], lcam_stq_idx[0]) node _forwarded_is_older_T_49 = lt(ldq_forward_stq_idx[12], l_uop_12.stq_idx) node _forwarded_is_older_T_50 = xor(_forwarded_is_older_T_48, _forwarded_is_older_T_49) node _forwarded_is_older_T_51 = lt(lcam_stq_idx[0], l_uop_12.stq_idx) node forwarded_is_older_12 = xor(_forwarded_is_older_T_50, _forwarded_is_older_T_51) node _T_979 = eq(ldq_forward_std_val[12], UInt<1>(0h0)) node _T_980 = neq(ldq_forward_stq_idx[12], lcam_stq_idx[0]) node _T_981 = and(_T_980, forwarded_is_older_12) node _T_982 = or(_T_979, _T_981) when _T_982 : connect ldq_order_fail[12], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_983 = and(do_ld_search[0], ldq_valid[12]) node _T_984 = and(_T_983, ldq_addr[12].valid) node _T_985 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_986 = and(_T_984, _T_985) node _T_987 = and(_T_986, dword_addr_matches_12[0]) node _T_988 = and(_T_987, mask_overlap_12[0]) when _T_988 : node searcher_is_older_12 = bits(lcam_younger_load_mask[0], 12, 12) node _T_989 = lt(lcam_ldq_idx[0], UInt<4>(0hc)) node _T_990 = lt(lcam_ldq_idx[0], ldq_head) node _T_991 = xor(_T_989, _T_990) node _T_992 = lt(UInt<4>(0hc), ldq_head) node _T_993 = xor(_T_991, _T_992) node _T_994 = eq(_T_993, searcher_is_older_12) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_56 assert(clock, _T_994, UInt<1>(0h1), "") : assert_56 when searcher_is_older_12 : node _T_998 = or(ldq_executed[12], ldq_succeeded[12]) node _T_999 = eq(s1_executing_loads[12], UInt<1>(0h0)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = and(_T_1000, ldq_observed[12]) when _T_1001 : node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_57 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_57 else : node _T_1005 = neq(lcam_ldq_idx[0], UInt<4>(0hc)) when _T_1005 : node _T_1006 = or(ldq_succeeded[12], ldq_will_succeed[12]) node _T_1007 = and(ldq_executed[12], _T_1006) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1010 = bits(_T_1009, 4, 0) connect s1_set_execute[_T_1010], UInt<1>(0h0) node _T_1011 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1012 = and(dmem_req_fire[0], _T_1011) reg REG_13 : UInt<1>, clock connect REG_13, _T_1012 node _T_1013 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1014 = and(REG_13, _T_1013) when _T_1014 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_13, ldq_uop[13] node _block_addr_matches_T_39 = shr(lcam_addr[0], 6) node _block_addr_matches_T_40 = shr(ldq_addr[13].bits, 6) node _block_addr_matches_T_41 = eq(_block_addr_matches_T_39, _block_addr_matches_T_40) wire block_addr_matches_13 : UInt<1>[1] connect block_addr_matches_13[0], _block_addr_matches_T_41 node _dword_addr_matches_T_52 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_53 = bits(ldq_addr[13].bits, 5, 3) node _dword_addr_matches_T_54 = eq(_dword_addr_matches_T_52, _dword_addr_matches_T_53) node _dword_addr_matches_T_55 = and(block_addr_matches_13[0], _dword_addr_matches_T_54) wire dword_addr_matches_13 : UInt<1>[1] connect dword_addr_matches_13[0], _dword_addr_matches_T_55 node _mask_match_T_26 = and(ldq_ld_byte_mask[13], lcam_mask[0]) node _mask_match_T_27 = eq(_mask_match_T_26, ldq_ld_byte_mask[13]) wire mask_match_13 : UInt<1>[1] connect mask_match_13[0], _mask_match_T_27 node _mask_overlap_T_26 = and(ldq_ld_byte_mask[13], lcam_mask[0]) node _mask_overlap_T_27 = orr(_mask_overlap_T_26) wire mask_overlap_13 : UInt<1>[1] connect mask_overlap_13[0], _mask_overlap_T_27 node _T_1015 = and(do_release_search[0], ldq_valid[13]) node _T_1016 = and(_T_1015, ldq_addr[13].valid) node _T_1017 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = and(_T_1018, block_addr_matches_13[0]) when _T_1019 : connect ldq_observed[13], UInt<1>(0h1) node _T_1020 = and(do_st_search[0], ldq_valid[13]) node _T_1021 = and(_T_1020, ldq_addr[13].valid) node _T_1022 = or(ldq_executed[13], ldq_succeeded[13]) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1025 = and(_T_1023, _T_1024) node _T_1026 = dshr(ldq_st_dep_mask[13], lcam_stq_idx[0]) node _T_1027 = bits(_T_1026, 0, 0) node _T_1028 = and(_T_1025, _T_1027) node _T_1029 = and(_T_1028, dword_addr_matches_13[0]) node _T_1030 = and(_T_1029, mask_overlap_13[0]) when _T_1030 : node _forwarded_is_older_T_52 = lt(ldq_forward_stq_idx[13], lcam_stq_idx[0]) node _forwarded_is_older_T_53 = lt(ldq_forward_stq_idx[13], l_uop_13.stq_idx) node _forwarded_is_older_T_54 = xor(_forwarded_is_older_T_52, _forwarded_is_older_T_53) node _forwarded_is_older_T_55 = lt(lcam_stq_idx[0], l_uop_13.stq_idx) node forwarded_is_older_13 = xor(_forwarded_is_older_T_54, _forwarded_is_older_T_55) node _T_1031 = eq(ldq_forward_std_val[13], UInt<1>(0h0)) node _T_1032 = neq(ldq_forward_stq_idx[13], lcam_stq_idx[0]) node _T_1033 = and(_T_1032, forwarded_is_older_13) node _T_1034 = or(_T_1031, _T_1033) when _T_1034 : connect ldq_order_fail[13], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1035 = and(do_ld_search[0], ldq_valid[13]) node _T_1036 = and(_T_1035, ldq_addr[13].valid) node _T_1037 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = and(_T_1038, dword_addr_matches_13[0]) node _T_1040 = and(_T_1039, mask_overlap_13[0]) when _T_1040 : node searcher_is_older_13 = bits(lcam_younger_load_mask[0], 13, 13) node _T_1041 = lt(lcam_ldq_idx[0], UInt<4>(0hd)) node _T_1042 = lt(lcam_ldq_idx[0], ldq_head) node _T_1043 = xor(_T_1041, _T_1042) node _T_1044 = lt(UInt<4>(0hd), ldq_head) node _T_1045 = xor(_T_1043, _T_1044) node _T_1046 = eq(_T_1045, searcher_is_older_13) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_58 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_58 when searcher_is_older_13 : node _T_1050 = or(ldq_executed[13], ldq_succeeded[13]) node _T_1051 = eq(s1_executing_loads[13], UInt<1>(0h0)) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = and(_T_1052, ldq_observed[13]) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_59 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_59 else : node _T_1057 = neq(lcam_ldq_idx[0], UInt<4>(0hd)) when _T_1057 : node _T_1058 = or(ldq_succeeded[13], ldq_will_succeed[13]) node _T_1059 = and(ldq_executed[13], _T_1058) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1062 = bits(_T_1061, 4, 0) connect s1_set_execute[_T_1062], UInt<1>(0h0) node _T_1063 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1064 = and(dmem_req_fire[0], _T_1063) reg REG_14 : UInt<1>, clock connect REG_14, _T_1064 node _T_1065 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1066 = and(REG_14, _T_1065) when _T_1066 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_14, ldq_uop[14] node _block_addr_matches_T_42 = shr(lcam_addr[0], 6) node _block_addr_matches_T_43 = shr(ldq_addr[14].bits, 6) node _block_addr_matches_T_44 = eq(_block_addr_matches_T_42, _block_addr_matches_T_43) wire block_addr_matches_14 : UInt<1>[1] connect block_addr_matches_14[0], _block_addr_matches_T_44 node _dword_addr_matches_T_56 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_57 = bits(ldq_addr[14].bits, 5, 3) node _dword_addr_matches_T_58 = eq(_dword_addr_matches_T_56, _dword_addr_matches_T_57) node _dword_addr_matches_T_59 = and(block_addr_matches_14[0], _dword_addr_matches_T_58) wire dword_addr_matches_14 : UInt<1>[1] connect dword_addr_matches_14[0], _dword_addr_matches_T_59 node _mask_match_T_28 = and(ldq_ld_byte_mask[14], lcam_mask[0]) node _mask_match_T_29 = eq(_mask_match_T_28, ldq_ld_byte_mask[14]) wire mask_match_14 : UInt<1>[1] connect mask_match_14[0], _mask_match_T_29 node _mask_overlap_T_28 = and(ldq_ld_byte_mask[14], lcam_mask[0]) node _mask_overlap_T_29 = orr(_mask_overlap_T_28) wire mask_overlap_14 : UInt<1>[1] connect mask_overlap_14[0], _mask_overlap_T_29 node _T_1067 = and(do_release_search[0], ldq_valid[14]) node _T_1068 = and(_T_1067, ldq_addr[14].valid) node _T_1069 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = and(_T_1070, block_addr_matches_14[0]) when _T_1071 : connect ldq_observed[14], UInt<1>(0h1) node _T_1072 = and(do_st_search[0], ldq_valid[14]) node _T_1073 = and(_T_1072, ldq_addr[14].valid) node _T_1074 = or(ldq_executed[14], ldq_succeeded[14]) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = dshr(ldq_st_dep_mask[14], lcam_stq_idx[0]) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = and(_T_1077, _T_1079) node _T_1081 = and(_T_1080, dword_addr_matches_14[0]) node _T_1082 = and(_T_1081, mask_overlap_14[0]) when _T_1082 : node _forwarded_is_older_T_56 = lt(ldq_forward_stq_idx[14], lcam_stq_idx[0]) node _forwarded_is_older_T_57 = lt(ldq_forward_stq_idx[14], l_uop_14.stq_idx) node _forwarded_is_older_T_58 = xor(_forwarded_is_older_T_56, _forwarded_is_older_T_57) node _forwarded_is_older_T_59 = lt(lcam_stq_idx[0], l_uop_14.stq_idx) node forwarded_is_older_14 = xor(_forwarded_is_older_T_58, _forwarded_is_older_T_59) node _T_1083 = eq(ldq_forward_std_val[14], UInt<1>(0h0)) node _T_1084 = neq(ldq_forward_stq_idx[14], lcam_stq_idx[0]) node _T_1085 = and(_T_1084, forwarded_is_older_14) node _T_1086 = or(_T_1083, _T_1085) when _T_1086 : connect ldq_order_fail[14], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1087 = and(do_ld_search[0], ldq_valid[14]) node _T_1088 = and(_T_1087, ldq_addr[14].valid) node _T_1089 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = and(_T_1090, dword_addr_matches_14[0]) node _T_1092 = and(_T_1091, mask_overlap_14[0]) when _T_1092 : node searcher_is_older_14 = bits(lcam_younger_load_mask[0], 14, 14) node _T_1093 = lt(lcam_ldq_idx[0], UInt<4>(0he)) node _T_1094 = lt(lcam_ldq_idx[0], ldq_head) node _T_1095 = xor(_T_1093, _T_1094) node _T_1096 = lt(UInt<4>(0he), ldq_head) node _T_1097 = xor(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, searcher_is_older_14) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_60 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_60 when searcher_is_older_14 : node _T_1102 = or(ldq_executed[14], ldq_succeeded[14]) node _T_1103 = eq(s1_executing_loads[14], UInt<1>(0h0)) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = and(_T_1104, ldq_observed[14]) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_61 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_61 else : node _T_1109 = neq(lcam_ldq_idx[0], UInt<4>(0he)) when _T_1109 : node _T_1110 = or(ldq_succeeded[14], ldq_will_succeed[14]) node _T_1111 = and(ldq_executed[14], _T_1110) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1114 = bits(_T_1113, 4, 0) connect s1_set_execute[_T_1114], UInt<1>(0h0) node _T_1115 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1116 = and(dmem_req_fire[0], _T_1115) reg REG_15 : UInt<1>, clock connect REG_15, _T_1116 node _T_1117 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1118 = and(REG_15, _T_1117) when _T_1118 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_15, ldq_uop[15] node _block_addr_matches_T_45 = shr(lcam_addr[0], 6) node _block_addr_matches_T_46 = shr(ldq_addr[15].bits, 6) node _block_addr_matches_T_47 = eq(_block_addr_matches_T_45, _block_addr_matches_T_46) wire block_addr_matches_15 : UInt<1>[1] connect block_addr_matches_15[0], _block_addr_matches_T_47 node _dword_addr_matches_T_60 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_61 = bits(ldq_addr[15].bits, 5, 3) node _dword_addr_matches_T_62 = eq(_dword_addr_matches_T_60, _dword_addr_matches_T_61) node _dword_addr_matches_T_63 = and(block_addr_matches_15[0], _dword_addr_matches_T_62) wire dword_addr_matches_15 : UInt<1>[1] connect dword_addr_matches_15[0], _dword_addr_matches_T_63 node _mask_match_T_30 = and(ldq_ld_byte_mask[15], lcam_mask[0]) node _mask_match_T_31 = eq(_mask_match_T_30, ldq_ld_byte_mask[15]) wire mask_match_15 : UInt<1>[1] connect mask_match_15[0], _mask_match_T_31 node _mask_overlap_T_30 = and(ldq_ld_byte_mask[15], lcam_mask[0]) node _mask_overlap_T_31 = orr(_mask_overlap_T_30) wire mask_overlap_15 : UInt<1>[1] connect mask_overlap_15[0], _mask_overlap_T_31 node _T_1119 = and(do_release_search[0], ldq_valid[15]) node _T_1120 = and(_T_1119, ldq_addr[15].valid) node _T_1121 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1122 = and(_T_1120, _T_1121) node _T_1123 = and(_T_1122, block_addr_matches_15[0]) when _T_1123 : connect ldq_observed[15], UInt<1>(0h1) node _T_1124 = and(do_st_search[0], ldq_valid[15]) node _T_1125 = and(_T_1124, ldq_addr[15].valid) node _T_1126 = or(ldq_executed[15], ldq_succeeded[15]) node _T_1127 = and(_T_1125, _T_1126) node _T_1128 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = dshr(ldq_st_dep_mask[15], lcam_stq_idx[0]) node _T_1131 = bits(_T_1130, 0, 0) node _T_1132 = and(_T_1129, _T_1131) node _T_1133 = and(_T_1132, dword_addr_matches_15[0]) node _T_1134 = and(_T_1133, mask_overlap_15[0]) when _T_1134 : node _forwarded_is_older_T_60 = lt(ldq_forward_stq_idx[15], lcam_stq_idx[0]) node _forwarded_is_older_T_61 = lt(ldq_forward_stq_idx[15], l_uop_15.stq_idx) node _forwarded_is_older_T_62 = xor(_forwarded_is_older_T_60, _forwarded_is_older_T_61) node _forwarded_is_older_T_63 = lt(lcam_stq_idx[0], l_uop_15.stq_idx) node forwarded_is_older_15 = xor(_forwarded_is_older_T_62, _forwarded_is_older_T_63) node _T_1135 = eq(ldq_forward_std_val[15], UInt<1>(0h0)) node _T_1136 = neq(ldq_forward_stq_idx[15], lcam_stq_idx[0]) node _T_1137 = and(_T_1136, forwarded_is_older_15) node _T_1138 = or(_T_1135, _T_1137) when _T_1138 : connect ldq_order_fail[15], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1139 = and(do_ld_search[0], ldq_valid[15]) node _T_1140 = and(_T_1139, ldq_addr[15].valid) node _T_1141 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, dword_addr_matches_15[0]) node _T_1144 = and(_T_1143, mask_overlap_15[0]) when _T_1144 : node searcher_is_older_15 = bits(lcam_younger_load_mask[0], 15, 15) node _T_1145 = lt(lcam_ldq_idx[0], UInt<4>(0hf)) node _T_1146 = lt(lcam_ldq_idx[0], ldq_head) node _T_1147 = xor(_T_1145, _T_1146) node _T_1148 = lt(UInt<4>(0hf), ldq_head) node _T_1149 = xor(_T_1147, _T_1148) node _T_1150 = eq(_T_1149, searcher_is_older_15) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_62 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_62 when searcher_is_older_15 : node _T_1154 = or(ldq_executed[15], ldq_succeeded[15]) node _T_1155 = eq(s1_executing_loads[15], UInt<1>(0h0)) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = and(_T_1156, ldq_observed[15]) when _T_1157 : node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_63 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_63 else : node _T_1161 = neq(lcam_ldq_idx[0], UInt<4>(0hf)) when _T_1161 : node _T_1162 = or(ldq_succeeded[15], ldq_will_succeed[15]) node _T_1163 = and(ldq_executed[15], _T_1162) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1166 = bits(_T_1165, 4, 0) connect s1_set_execute[_T_1166], UInt<1>(0h0) node _T_1167 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1168 = and(dmem_req_fire[0], _T_1167) reg REG_16 : UInt<1>, clock connect REG_16, _T_1168 node _T_1169 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1170 = and(REG_16, _T_1169) when _T_1170 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_16, ldq_uop[16] node _block_addr_matches_T_48 = shr(lcam_addr[0], 6) node _block_addr_matches_T_49 = shr(ldq_addr[16].bits, 6) node _block_addr_matches_T_50 = eq(_block_addr_matches_T_48, _block_addr_matches_T_49) wire block_addr_matches_16 : UInt<1>[1] connect block_addr_matches_16[0], _block_addr_matches_T_50 node _dword_addr_matches_T_64 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_65 = bits(ldq_addr[16].bits, 5, 3) node _dword_addr_matches_T_66 = eq(_dword_addr_matches_T_64, _dword_addr_matches_T_65) node _dword_addr_matches_T_67 = and(block_addr_matches_16[0], _dword_addr_matches_T_66) wire dword_addr_matches_16 : UInt<1>[1] connect dword_addr_matches_16[0], _dword_addr_matches_T_67 node _mask_match_T_32 = and(ldq_ld_byte_mask[16], lcam_mask[0]) node _mask_match_T_33 = eq(_mask_match_T_32, ldq_ld_byte_mask[16]) wire mask_match_16 : UInt<1>[1] connect mask_match_16[0], _mask_match_T_33 node _mask_overlap_T_32 = and(ldq_ld_byte_mask[16], lcam_mask[0]) node _mask_overlap_T_33 = orr(_mask_overlap_T_32) wire mask_overlap_16 : UInt<1>[1] connect mask_overlap_16[0], _mask_overlap_T_33 node _T_1171 = and(do_release_search[0], ldq_valid[16]) node _T_1172 = and(_T_1171, ldq_addr[16].valid) node _T_1173 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = and(_T_1174, block_addr_matches_16[0]) when _T_1175 : connect ldq_observed[16], UInt<1>(0h1) node _T_1176 = and(do_st_search[0], ldq_valid[16]) node _T_1177 = and(_T_1176, ldq_addr[16].valid) node _T_1178 = or(ldq_executed[16], ldq_succeeded[16]) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = dshr(ldq_st_dep_mask[16], lcam_stq_idx[0]) node _T_1183 = bits(_T_1182, 0, 0) node _T_1184 = and(_T_1181, _T_1183) node _T_1185 = and(_T_1184, dword_addr_matches_16[0]) node _T_1186 = and(_T_1185, mask_overlap_16[0]) when _T_1186 : node _forwarded_is_older_T_64 = lt(ldq_forward_stq_idx[16], lcam_stq_idx[0]) node _forwarded_is_older_T_65 = lt(ldq_forward_stq_idx[16], l_uop_16.stq_idx) node _forwarded_is_older_T_66 = xor(_forwarded_is_older_T_64, _forwarded_is_older_T_65) node _forwarded_is_older_T_67 = lt(lcam_stq_idx[0], l_uop_16.stq_idx) node forwarded_is_older_16 = xor(_forwarded_is_older_T_66, _forwarded_is_older_T_67) node _T_1187 = eq(ldq_forward_std_val[16], UInt<1>(0h0)) node _T_1188 = neq(ldq_forward_stq_idx[16], lcam_stq_idx[0]) node _T_1189 = and(_T_1188, forwarded_is_older_16) node _T_1190 = or(_T_1187, _T_1189) when _T_1190 : connect ldq_order_fail[16], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1191 = and(do_ld_search[0], ldq_valid[16]) node _T_1192 = and(_T_1191, ldq_addr[16].valid) node _T_1193 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = and(_T_1194, dword_addr_matches_16[0]) node _T_1196 = and(_T_1195, mask_overlap_16[0]) when _T_1196 : node searcher_is_older_16 = bits(lcam_younger_load_mask[0], 16, 16) node _T_1197 = lt(lcam_ldq_idx[0], UInt<5>(0h10)) node _T_1198 = lt(lcam_ldq_idx[0], ldq_head) node _T_1199 = xor(_T_1197, _T_1198) node _T_1200 = lt(UInt<5>(0h10), ldq_head) node _T_1201 = xor(_T_1199, _T_1200) node _T_1202 = eq(_T_1201, searcher_is_older_16) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_64 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_64 when searcher_is_older_16 : node _T_1206 = or(ldq_executed[16], ldq_succeeded[16]) node _T_1207 = eq(s1_executing_loads[16], UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = and(_T_1208, ldq_observed[16]) when _T_1209 : node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_65 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_65 else : node _T_1213 = neq(lcam_ldq_idx[0], UInt<5>(0h10)) when _T_1213 : node _T_1214 = or(ldq_succeeded[16], ldq_will_succeed[16]) node _T_1215 = and(ldq_executed[16], _T_1214) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1218 = bits(_T_1217, 4, 0) connect s1_set_execute[_T_1218], UInt<1>(0h0) node _T_1219 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1220 = and(dmem_req_fire[0], _T_1219) reg REG_17 : UInt<1>, clock connect REG_17, _T_1220 node _T_1221 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1222 = and(REG_17, _T_1221) when _T_1222 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_17, ldq_uop[17] node _block_addr_matches_T_51 = shr(lcam_addr[0], 6) node _block_addr_matches_T_52 = shr(ldq_addr[17].bits, 6) node _block_addr_matches_T_53 = eq(_block_addr_matches_T_51, _block_addr_matches_T_52) wire block_addr_matches_17 : UInt<1>[1] connect block_addr_matches_17[0], _block_addr_matches_T_53 node _dword_addr_matches_T_68 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_69 = bits(ldq_addr[17].bits, 5, 3) node _dword_addr_matches_T_70 = eq(_dword_addr_matches_T_68, _dword_addr_matches_T_69) node _dword_addr_matches_T_71 = and(block_addr_matches_17[0], _dword_addr_matches_T_70) wire dword_addr_matches_17 : UInt<1>[1] connect dword_addr_matches_17[0], _dword_addr_matches_T_71 node _mask_match_T_34 = and(ldq_ld_byte_mask[17], lcam_mask[0]) node _mask_match_T_35 = eq(_mask_match_T_34, ldq_ld_byte_mask[17]) wire mask_match_17 : UInt<1>[1] connect mask_match_17[0], _mask_match_T_35 node _mask_overlap_T_34 = and(ldq_ld_byte_mask[17], lcam_mask[0]) node _mask_overlap_T_35 = orr(_mask_overlap_T_34) wire mask_overlap_17 : UInt<1>[1] connect mask_overlap_17[0], _mask_overlap_T_35 node _T_1223 = and(do_release_search[0], ldq_valid[17]) node _T_1224 = and(_T_1223, ldq_addr[17].valid) node _T_1225 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = and(_T_1226, block_addr_matches_17[0]) when _T_1227 : connect ldq_observed[17], UInt<1>(0h1) node _T_1228 = and(do_st_search[0], ldq_valid[17]) node _T_1229 = and(_T_1228, ldq_addr[17].valid) node _T_1230 = or(ldq_executed[17], ldq_succeeded[17]) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = dshr(ldq_st_dep_mask[17], lcam_stq_idx[0]) node _T_1235 = bits(_T_1234, 0, 0) node _T_1236 = and(_T_1233, _T_1235) node _T_1237 = and(_T_1236, dword_addr_matches_17[0]) node _T_1238 = and(_T_1237, mask_overlap_17[0]) when _T_1238 : node _forwarded_is_older_T_68 = lt(ldq_forward_stq_idx[17], lcam_stq_idx[0]) node _forwarded_is_older_T_69 = lt(ldq_forward_stq_idx[17], l_uop_17.stq_idx) node _forwarded_is_older_T_70 = xor(_forwarded_is_older_T_68, _forwarded_is_older_T_69) node _forwarded_is_older_T_71 = lt(lcam_stq_idx[0], l_uop_17.stq_idx) node forwarded_is_older_17 = xor(_forwarded_is_older_T_70, _forwarded_is_older_T_71) node _T_1239 = eq(ldq_forward_std_val[17], UInt<1>(0h0)) node _T_1240 = neq(ldq_forward_stq_idx[17], lcam_stq_idx[0]) node _T_1241 = and(_T_1240, forwarded_is_older_17) node _T_1242 = or(_T_1239, _T_1241) when _T_1242 : connect ldq_order_fail[17], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1243 = and(do_ld_search[0], ldq_valid[17]) node _T_1244 = and(_T_1243, ldq_addr[17].valid) node _T_1245 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1246 = and(_T_1244, _T_1245) node _T_1247 = and(_T_1246, dword_addr_matches_17[0]) node _T_1248 = and(_T_1247, mask_overlap_17[0]) when _T_1248 : node searcher_is_older_17 = bits(lcam_younger_load_mask[0], 17, 17) node _T_1249 = lt(lcam_ldq_idx[0], UInt<5>(0h11)) node _T_1250 = lt(lcam_ldq_idx[0], ldq_head) node _T_1251 = xor(_T_1249, _T_1250) node _T_1252 = lt(UInt<5>(0h11), ldq_head) node _T_1253 = xor(_T_1251, _T_1252) node _T_1254 = eq(_T_1253, searcher_is_older_17) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_66 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_66 when searcher_is_older_17 : node _T_1258 = or(ldq_executed[17], ldq_succeeded[17]) node _T_1259 = eq(s1_executing_loads[17], UInt<1>(0h0)) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, ldq_observed[17]) when _T_1261 : node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_67 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_67 else : node _T_1265 = neq(lcam_ldq_idx[0], UInt<5>(0h11)) when _T_1265 : node _T_1266 = or(ldq_succeeded[17], ldq_will_succeed[17]) node _T_1267 = and(ldq_executed[17], _T_1266) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1270 = bits(_T_1269, 4, 0) connect s1_set_execute[_T_1270], UInt<1>(0h0) node _T_1271 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1272 = and(dmem_req_fire[0], _T_1271) reg REG_18 : UInt<1>, clock connect REG_18, _T_1272 node _T_1273 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1274 = and(REG_18, _T_1273) when _T_1274 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_18, ldq_uop[18] node _block_addr_matches_T_54 = shr(lcam_addr[0], 6) node _block_addr_matches_T_55 = shr(ldq_addr[18].bits, 6) node _block_addr_matches_T_56 = eq(_block_addr_matches_T_54, _block_addr_matches_T_55) wire block_addr_matches_18 : UInt<1>[1] connect block_addr_matches_18[0], _block_addr_matches_T_56 node _dword_addr_matches_T_72 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_73 = bits(ldq_addr[18].bits, 5, 3) node _dword_addr_matches_T_74 = eq(_dword_addr_matches_T_72, _dword_addr_matches_T_73) node _dword_addr_matches_T_75 = and(block_addr_matches_18[0], _dword_addr_matches_T_74) wire dword_addr_matches_18 : UInt<1>[1] connect dword_addr_matches_18[0], _dword_addr_matches_T_75 node _mask_match_T_36 = and(ldq_ld_byte_mask[18], lcam_mask[0]) node _mask_match_T_37 = eq(_mask_match_T_36, ldq_ld_byte_mask[18]) wire mask_match_18 : UInt<1>[1] connect mask_match_18[0], _mask_match_T_37 node _mask_overlap_T_36 = and(ldq_ld_byte_mask[18], lcam_mask[0]) node _mask_overlap_T_37 = orr(_mask_overlap_T_36) wire mask_overlap_18 : UInt<1>[1] connect mask_overlap_18[0], _mask_overlap_T_37 node _T_1275 = and(do_release_search[0], ldq_valid[18]) node _T_1276 = and(_T_1275, ldq_addr[18].valid) node _T_1277 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1278, block_addr_matches_18[0]) when _T_1279 : connect ldq_observed[18], UInt<1>(0h1) node _T_1280 = and(do_st_search[0], ldq_valid[18]) node _T_1281 = and(_T_1280, ldq_addr[18].valid) node _T_1282 = or(ldq_executed[18], ldq_succeeded[18]) node _T_1283 = and(_T_1281, _T_1282) node _T_1284 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1285 = and(_T_1283, _T_1284) node _T_1286 = dshr(ldq_st_dep_mask[18], lcam_stq_idx[0]) node _T_1287 = bits(_T_1286, 0, 0) node _T_1288 = and(_T_1285, _T_1287) node _T_1289 = and(_T_1288, dword_addr_matches_18[0]) node _T_1290 = and(_T_1289, mask_overlap_18[0]) when _T_1290 : node _forwarded_is_older_T_72 = lt(ldq_forward_stq_idx[18], lcam_stq_idx[0]) node _forwarded_is_older_T_73 = lt(ldq_forward_stq_idx[18], l_uop_18.stq_idx) node _forwarded_is_older_T_74 = xor(_forwarded_is_older_T_72, _forwarded_is_older_T_73) node _forwarded_is_older_T_75 = lt(lcam_stq_idx[0], l_uop_18.stq_idx) node forwarded_is_older_18 = xor(_forwarded_is_older_T_74, _forwarded_is_older_T_75) node _T_1291 = eq(ldq_forward_std_val[18], UInt<1>(0h0)) node _T_1292 = neq(ldq_forward_stq_idx[18], lcam_stq_idx[0]) node _T_1293 = and(_T_1292, forwarded_is_older_18) node _T_1294 = or(_T_1291, _T_1293) when _T_1294 : connect ldq_order_fail[18], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1295 = and(do_ld_search[0], ldq_valid[18]) node _T_1296 = and(_T_1295, ldq_addr[18].valid) node _T_1297 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = and(_T_1298, dword_addr_matches_18[0]) node _T_1300 = and(_T_1299, mask_overlap_18[0]) when _T_1300 : node searcher_is_older_18 = bits(lcam_younger_load_mask[0], 18, 18) node _T_1301 = lt(lcam_ldq_idx[0], UInt<5>(0h12)) node _T_1302 = lt(lcam_ldq_idx[0], ldq_head) node _T_1303 = xor(_T_1301, _T_1302) node _T_1304 = lt(UInt<5>(0h12), ldq_head) node _T_1305 = xor(_T_1303, _T_1304) node _T_1306 = eq(_T_1305, searcher_is_older_18) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_68 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_68 when searcher_is_older_18 : node _T_1310 = or(ldq_executed[18], ldq_succeeded[18]) node _T_1311 = eq(s1_executing_loads[18], UInt<1>(0h0)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = and(_T_1312, ldq_observed[18]) when _T_1313 : node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_69 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_69 else : node _T_1317 = neq(lcam_ldq_idx[0], UInt<5>(0h12)) when _T_1317 : node _T_1318 = or(ldq_succeeded[18], ldq_will_succeed[18]) node _T_1319 = and(ldq_executed[18], _T_1318) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1322 = bits(_T_1321, 4, 0) connect s1_set_execute[_T_1322], UInt<1>(0h0) node _T_1323 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1324 = and(dmem_req_fire[0], _T_1323) reg REG_19 : UInt<1>, clock connect REG_19, _T_1324 node _T_1325 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1326 = and(REG_19, _T_1325) when _T_1326 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_19, ldq_uop[19] node _block_addr_matches_T_57 = shr(lcam_addr[0], 6) node _block_addr_matches_T_58 = shr(ldq_addr[19].bits, 6) node _block_addr_matches_T_59 = eq(_block_addr_matches_T_57, _block_addr_matches_T_58) wire block_addr_matches_19 : UInt<1>[1] connect block_addr_matches_19[0], _block_addr_matches_T_59 node _dword_addr_matches_T_76 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_77 = bits(ldq_addr[19].bits, 5, 3) node _dword_addr_matches_T_78 = eq(_dword_addr_matches_T_76, _dword_addr_matches_T_77) node _dword_addr_matches_T_79 = and(block_addr_matches_19[0], _dword_addr_matches_T_78) wire dword_addr_matches_19 : UInt<1>[1] connect dword_addr_matches_19[0], _dword_addr_matches_T_79 node _mask_match_T_38 = and(ldq_ld_byte_mask[19], lcam_mask[0]) node _mask_match_T_39 = eq(_mask_match_T_38, ldq_ld_byte_mask[19]) wire mask_match_19 : UInt<1>[1] connect mask_match_19[0], _mask_match_T_39 node _mask_overlap_T_38 = and(ldq_ld_byte_mask[19], lcam_mask[0]) node _mask_overlap_T_39 = orr(_mask_overlap_T_38) wire mask_overlap_19 : UInt<1>[1] connect mask_overlap_19[0], _mask_overlap_T_39 node _T_1327 = and(do_release_search[0], ldq_valid[19]) node _T_1328 = and(_T_1327, ldq_addr[19].valid) node _T_1329 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = and(_T_1330, block_addr_matches_19[0]) when _T_1331 : connect ldq_observed[19], UInt<1>(0h1) node _T_1332 = and(do_st_search[0], ldq_valid[19]) node _T_1333 = and(_T_1332, ldq_addr[19].valid) node _T_1334 = or(ldq_executed[19], ldq_succeeded[19]) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1337 = and(_T_1335, _T_1336) node _T_1338 = dshr(ldq_st_dep_mask[19], lcam_stq_idx[0]) node _T_1339 = bits(_T_1338, 0, 0) node _T_1340 = and(_T_1337, _T_1339) node _T_1341 = and(_T_1340, dword_addr_matches_19[0]) node _T_1342 = and(_T_1341, mask_overlap_19[0]) when _T_1342 : node _forwarded_is_older_T_76 = lt(ldq_forward_stq_idx[19], lcam_stq_idx[0]) node _forwarded_is_older_T_77 = lt(ldq_forward_stq_idx[19], l_uop_19.stq_idx) node _forwarded_is_older_T_78 = xor(_forwarded_is_older_T_76, _forwarded_is_older_T_77) node _forwarded_is_older_T_79 = lt(lcam_stq_idx[0], l_uop_19.stq_idx) node forwarded_is_older_19 = xor(_forwarded_is_older_T_78, _forwarded_is_older_T_79) node _T_1343 = eq(ldq_forward_std_val[19], UInt<1>(0h0)) node _T_1344 = neq(ldq_forward_stq_idx[19], lcam_stq_idx[0]) node _T_1345 = and(_T_1344, forwarded_is_older_19) node _T_1346 = or(_T_1343, _T_1345) when _T_1346 : connect ldq_order_fail[19], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1347 = and(do_ld_search[0], ldq_valid[19]) node _T_1348 = and(_T_1347, ldq_addr[19].valid) node _T_1349 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = and(_T_1350, dword_addr_matches_19[0]) node _T_1352 = and(_T_1351, mask_overlap_19[0]) when _T_1352 : node searcher_is_older_19 = bits(lcam_younger_load_mask[0], 19, 19) node _T_1353 = lt(lcam_ldq_idx[0], UInt<5>(0h13)) node _T_1354 = lt(lcam_ldq_idx[0], ldq_head) node _T_1355 = xor(_T_1353, _T_1354) node _T_1356 = lt(UInt<5>(0h13), ldq_head) node _T_1357 = xor(_T_1355, _T_1356) node _T_1358 = eq(_T_1357, searcher_is_older_19) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_70 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_70 when searcher_is_older_19 : node _T_1362 = or(ldq_executed[19], ldq_succeeded[19]) node _T_1363 = eq(s1_executing_loads[19], UInt<1>(0h0)) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = and(_T_1364, ldq_observed[19]) when _T_1365 : node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_71 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_71 else : node _T_1369 = neq(lcam_ldq_idx[0], UInt<5>(0h13)) when _T_1369 : node _T_1370 = or(ldq_succeeded[19], ldq_will_succeed[19]) node _T_1371 = and(ldq_executed[19], _T_1370) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1374 = bits(_T_1373, 4, 0) connect s1_set_execute[_T_1374], UInt<1>(0h0) node _T_1375 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1376 = and(dmem_req_fire[0], _T_1375) reg REG_20 : UInt<1>, clock connect REG_20, _T_1376 node _T_1377 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1378 = and(REG_20, _T_1377) when _T_1378 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_20, ldq_uop[20] node _block_addr_matches_T_60 = shr(lcam_addr[0], 6) node _block_addr_matches_T_61 = shr(ldq_addr[20].bits, 6) node _block_addr_matches_T_62 = eq(_block_addr_matches_T_60, _block_addr_matches_T_61) wire block_addr_matches_20 : UInt<1>[1] connect block_addr_matches_20[0], _block_addr_matches_T_62 node _dword_addr_matches_T_80 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_81 = bits(ldq_addr[20].bits, 5, 3) node _dword_addr_matches_T_82 = eq(_dword_addr_matches_T_80, _dword_addr_matches_T_81) node _dword_addr_matches_T_83 = and(block_addr_matches_20[0], _dword_addr_matches_T_82) wire dword_addr_matches_20 : UInt<1>[1] connect dword_addr_matches_20[0], _dword_addr_matches_T_83 node _mask_match_T_40 = and(ldq_ld_byte_mask[20], lcam_mask[0]) node _mask_match_T_41 = eq(_mask_match_T_40, ldq_ld_byte_mask[20]) wire mask_match_20 : UInt<1>[1] connect mask_match_20[0], _mask_match_T_41 node _mask_overlap_T_40 = and(ldq_ld_byte_mask[20], lcam_mask[0]) node _mask_overlap_T_41 = orr(_mask_overlap_T_40) wire mask_overlap_20 : UInt<1>[1] connect mask_overlap_20[0], _mask_overlap_T_41 node _T_1379 = and(do_release_search[0], ldq_valid[20]) node _T_1380 = and(_T_1379, ldq_addr[20].valid) node _T_1381 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = and(_T_1382, block_addr_matches_20[0]) when _T_1383 : connect ldq_observed[20], UInt<1>(0h1) node _T_1384 = and(do_st_search[0], ldq_valid[20]) node _T_1385 = and(_T_1384, ldq_addr[20].valid) node _T_1386 = or(ldq_executed[20], ldq_succeeded[20]) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1389 = and(_T_1387, _T_1388) node _T_1390 = dshr(ldq_st_dep_mask[20], lcam_stq_idx[0]) node _T_1391 = bits(_T_1390, 0, 0) node _T_1392 = and(_T_1389, _T_1391) node _T_1393 = and(_T_1392, dword_addr_matches_20[0]) node _T_1394 = and(_T_1393, mask_overlap_20[0]) when _T_1394 : node _forwarded_is_older_T_80 = lt(ldq_forward_stq_idx[20], lcam_stq_idx[0]) node _forwarded_is_older_T_81 = lt(ldq_forward_stq_idx[20], l_uop_20.stq_idx) node _forwarded_is_older_T_82 = xor(_forwarded_is_older_T_80, _forwarded_is_older_T_81) node _forwarded_is_older_T_83 = lt(lcam_stq_idx[0], l_uop_20.stq_idx) node forwarded_is_older_20 = xor(_forwarded_is_older_T_82, _forwarded_is_older_T_83) node _T_1395 = eq(ldq_forward_std_val[20], UInt<1>(0h0)) node _T_1396 = neq(ldq_forward_stq_idx[20], lcam_stq_idx[0]) node _T_1397 = and(_T_1396, forwarded_is_older_20) node _T_1398 = or(_T_1395, _T_1397) when _T_1398 : connect ldq_order_fail[20], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1399 = and(do_ld_search[0], ldq_valid[20]) node _T_1400 = and(_T_1399, ldq_addr[20].valid) node _T_1401 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = and(_T_1402, dword_addr_matches_20[0]) node _T_1404 = and(_T_1403, mask_overlap_20[0]) when _T_1404 : node searcher_is_older_20 = bits(lcam_younger_load_mask[0], 20, 20) node _T_1405 = lt(lcam_ldq_idx[0], UInt<5>(0h14)) node _T_1406 = lt(lcam_ldq_idx[0], ldq_head) node _T_1407 = xor(_T_1405, _T_1406) node _T_1408 = lt(UInt<5>(0h14), ldq_head) node _T_1409 = xor(_T_1407, _T_1408) node _T_1410 = eq(_T_1409, searcher_is_older_20) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_72 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_72 when searcher_is_older_20 : node _T_1414 = or(ldq_executed[20], ldq_succeeded[20]) node _T_1415 = eq(s1_executing_loads[20], UInt<1>(0h0)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = and(_T_1416, ldq_observed[20]) when _T_1417 : node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_73 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_73 else : node _T_1421 = neq(lcam_ldq_idx[0], UInt<5>(0h14)) when _T_1421 : node _T_1422 = or(ldq_succeeded[20], ldq_will_succeed[20]) node _T_1423 = and(ldq_executed[20], _T_1422) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1426 = bits(_T_1425, 4, 0) connect s1_set_execute[_T_1426], UInt<1>(0h0) node _T_1427 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1428 = and(dmem_req_fire[0], _T_1427) reg REG_21 : UInt<1>, clock connect REG_21, _T_1428 node _T_1429 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1430 = and(REG_21, _T_1429) when _T_1430 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_21, ldq_uop[21] node _block_addr_matches_T_63 = shr(lcam_addr[0], 6) node _block_addr_matches_T_64 = shr(ldq_addr[21].bits, 6) node _block_addr_matches_T_65 = eq(_block_addr_matches_T_63, _block_addr_matches_T_64) wire block_addr_matches_21 : UInt<1>[1] connect block_addr_matches_21[0], _block_addr_matches_T_65 node _dword_addr_matches_T_84 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_85 = bits(ldq_addr[21].bits, 5, 3) node _dword_addr_matches_T_86 = eq(_dword_addr_matches_T_84, _dword_addr_matches_T_85) node _dword_addr_matches_T_87 = and(block_addr_matches_21[0], _dword_addr_matches_T_86) wire dword_addr_matches_21 : UInt<1>[1] connect dword_addr_matches_21[0], _dword_addr_matches_T_87 node _mask_match_T_42 = and(ldq_ld_byte_mask[21], lcam_mask[0]) node _mask_match_T_43 = eq(_mask_match_T_42, ldq_ld_byte_mask[21]) wire mask_match_21 : UInt<1>[1] connect mask_match_21[0], _mask_match_T_43 node _mask_overlap_T_42 = and(ldq_ld_byte_mask[21], lcam_mask[0]) node _mask_overlap_T_43 = orr(_mask_overlap_T_42) wire mask_overlap_21 : UInt<1>[1] connect mask_overlap_21[0], _mask_overlap_T_43 node _T_1431 = and(do_release_search[0], ldq_valid[21]) node _T_1432 = and(_T_1431, ldq_addr[21].valid) node _T_1433 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = and(_T_1434, block_addr_matches_21[0]) when _T_1435 : connect ldq_observed[21], UInt<1>(0h1) node _T_1436 = and(do_st_search[0], ldq_valid[21]) node _T_1437 = and(_T_1436, ldq_addr[21].valid) node _T_1438 = or(ldq_executed[21], ldq_succeeded[21]) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1441 = and(_T_1439, _T_1440) node _T_1442 = dshr(ldq_st_dep_mask[21], lcam_stq_idx[0]) node _T_1443 = bits(_T_1442, 0, 0) node _T_1444 = and(_T_1441, _T_1443) node _T_1445 = and(_T_1444, dword_addr_matches_21[0]) node _T_1446 = and(_T_1445, mask_overlap_21[0]) when _T_1446 : node _forwarded_is_older_T_84 = lt(ldq_forward_stq_idx[21], lcam_stq_idx[0]) node _forwarded_is_older_T_85 = lt(ldq_forward_stq_idx[21], l_uop_21.stq_idx) node _forwarded_is_older_T_86 = xor(_forwarded_is_older_T_84, _forwarded_is_older_T_85) node _forwarded_is_older_T_87 = lt(lcam_stq_idx[0], l_uop_21.stq_idx) node forwarded_is_older_21 = xor(_forwarded_is_older_T_86, _forwarded_is_older_T_87) node _T_1447 = eq(ldq_forward_std_val[21], UInt<1>(0h0)) node _T_1448 = neq(ldq_forward_stq_idx[21], lcam_stq_idx[0]) node _T_1449 = and(_T_1448, forwarded_is_older_21) node _T_1450 = or(_T_1447, _T_1449) when _T_1450 : connect ldq_order_fail[21], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1451 = and(do_ld_search[0], ldq_valid[21]) node _T_1452 = and(_T_1451, ldq_addr[21].valid) node _T_1453 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = and(_T_1454, dword_addr_matches_21[0]) node _T_1456 = and(_T_1455, mask_overlap_21[0]) when _T_1456 : node searcher_is_older_21 = bits(lcam_younger_load_mask[0], 21, 21) node _T_1457 = lt(lcam_ldq_idx[0], UInt<5>(0h15)) node _T_1458 = lt(lcam_ldq_idx[0], ldq_head) node _T_1459 = xor(_T_1457, _T_1458) node _T_1460 = lt(UInt<5>(0h15), ldq_head) node _T_1461 = xor(_T_1459, _T_1460) node _T_1462 = eq(_T_1461, searcher_is_older_21) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_74 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_74 when searcher_is_older_21 : node _T_1466 = or(ldq_executed[21], ldq_succeeded[21]) node _T_1467 = eq(s1_executing_loads[21], UInt<1>(0h0)) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = and(_T_1468, ldq_observed[21]) when _T_1469 : node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_75 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_75 else : node _T_1473 = neq(lcam_ldq_idx[0], UInt<5>(0h15)) when _T_1473 : node _T_1474 = or(ldq_succeeded[21], ldq_will_succeed[21]) node _T_1475 = and(ldq_executed[21], _T_1474) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1478 = bits(_T_1477, 4, 0) connect s1_set_execute[_T_1478], UInt<1>(0h0) node _T_1479 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1480 = and(dmem_req_fire[0], _T_1479) reg REG_22 : UInt<1>, clock connect REG_22, _T_1480 node _T_1481 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1482 = and(REG_22, _T_1481) when _T_1482 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_22, ldq_uop[22] node _block_addr_matches_T_66 = shr(lcam_addr[0], 6) node _block_addr_matches_T_67 = shr(ldq_addr[22].bits, 6) node _block_addr_matches_T_68 = eq(_block_addr_matches_T_66, _block_addr_matches_T_67) wire block_addr_matches_22 : UInt<1>[1] connect block_addr_matches_22[0], _block_addr_matches_T_68 node _dword_addr_matches_T_88 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_89 = bits(ldq_addr[22].bits, 5, 3) node _dword_addr_matches_T_90 = eq(_dword_addr_matches_T_88, _dword_addr_matches_T_89) node _dword_addr_matches_T_91 = and(block_addr_matches_22[0], _dword_addr_matches_T_90) wire dword_addr_matches_22 : UInt<1>[1] connect dword_addr_matches_22[0], _dword_addr_matches_T_91 node _mask_match_T_44 = and(ldq_ld_byte_mask[22], lcam_mask[0]) node _mask_match_T_45 = eq(_mask_match_T_44, ldq_ld_byte_mask[22]) wire mask_match_22 : UInt<1>[1] connect mask_match_22[0], _mask_match_T_45 node _mask_overlap_T_44 = and(ldq_ld_byte_mask[22], lcam_mask[0]) node _mask_overlap_T_45 = orr(_mask_overlap_T_44) wire mask_overlap_22 : UInt<1>[1] connect mask_overlap_22[0], _mask_overlap_T_45 node _T_1483 = and(do_release_search[0], ldq_valid[22]) node _T_1484 = and(_T_1483, ldq_addr[22].valid) node _T_1485 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1486 = and(_T_1484, _T_1485) node _T_1487 = and(_T_1486, block_addr_matches_22[0]) when _T_1487 : connect ldq_observed[22], UInt<1>(0h1) node _T_1488 = and(do_st_search[0], ldq_valid[22]) node _T_1489 = and(_T_1488, ldq_addr[22].valid) node _T_1490 = or(ldq_executed[22], ldq_succeeded[22]) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = dshr(ldq_st_dep_mask[22], lcam_stq_idx[0]) node _T_1495 = bits(_T_1494, 0, 0) node _T_1496 = and(_T_1493, _T_1495) node _T_1497 = and(_T_1496, dword_addr_matches_22[0]) node _T_1498 = and(_T_1497, mask_overlap_22[0]) when _T_1498 : node _forwarded_is_older_T_88 = lt(ldq_forward_stq_idx[22], lcam_stq_idx[0]) node _forwarded_is_older_T_89 = lt(ldq_forward_stq_idx[22], l_uop_22.stq_idx) node _forwarded_is_older_T_90 = xor(_forwarded_is_older_T_88, _forwarded_is_older_T_89) node _forwarded_is_older_T_91 = lt(lcam_stq_idx[0], l_uop_22.stq_idx) node forwarded_is_older_22 = xor(_forwarded_is_older_T_90, _forwarded_is_older_T_91) node _T_1499 = eq(ldq_forward_std_val[22], UInt<1>(0h0)) node _T_1500 = neq(ldq_forward_stq_idx[22], lcam_stq_idx[0]) node _T_1501 = and(_T_1500, forwarded_is_older_22) node _T_1502 = or(_T_1499, _T_1501) when _T_1502 : connect ldq_order_fail[22], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1503 = and(do_ld_search[0], ldq_valid[22]) node _T_1504 = and(_T_1503, ldq_addr[22].valid) node _T_1505 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = and(_T_1506, dword_addr_matches_22[0]) node _T_1508 = and(_T_1507, mask_overlap_22[0]) when _T_1508 : node searcher_is_older_22 = bits(lcam_younger_load_mask[0], 22, 22) node _T_1509 = lt(lcam_ldq_idx[0], UInt<5>(0h16)) node _T_1510 = lt(lcam_ldq_idx[0], ldq_head) node _T_1511 = xor(_T_1509, _T_1510) node _T_1512 = lt(UInt<5>(0h16), ldq_head) node _T_1513 = xor(_T_1511, _T_1512) node _T_1514 = eq(_T_1513, searcher_is_older_22) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_76 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_76 when searcher_is_older_22 : node _T_1518 = or(ldq_executed[22], ldq_succeeded[22]) node _T_1519 = eq(s1_executing_loads[22], UInt<1>(0h0)) node _T_1520 = and(_T_1518, _T_1519) node _T_1521 = and(_T_1520, ldq_observed[22]) when _T_1521 : node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_77 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_77 else : node _T_1525 = neq(lcam_ldq_idx[0], UInt<5>(0h16)) when _T_1525 : node _T_1526 = or(ldq_succeeded[22], ldq_will_succeed[22]) node _T_1527 = and(ldq_executed[22], _T_1526) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1530 = bits(_T_1529, 4, 0) connect s1_set_execute[_T_1530], UInt<1>(0h0) node _T_1531 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1532 = and(dmem_req_fire[0], _T_1531) reg REG_23 : UInt<1>, clock connect REG_23, _T_1532 node _T_1533 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1534 = and(REG_23, _T_1533) when _T_1534 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_23, ldq_uop[23] node _block_addr_matches_T_69 = shr(lcam_addr[0], 6) node _block_addr_matches_T_70 = shr(ldq_addr[23].bits, 6) node _block_addr_matches_T_71 = eq(_block_addr_matches_T_69, _block_addr_matches_T_70) wire block_addr_matches_23 : UInt<1>[1] connect block_addr_matches_23[0], _block_addr_matches_T_71 node _dword_addr_matches_T_92 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_93 = bits(ldq_addr[23].bits, 5, 3) node _dword_addr_matches_T_94 = eq(_dword_addr_matches_T_92, _dword_addr_matches_T_93) node _dword_addr_matches_T_95 = and(block_addr_matches_23[0], _dword_addr_matches_T_94) wire dword_addr_matches_23 : UInt<1>[1] connect dword_addr_matches_23[0], _dword_addr_matches_T_95 node _mask_match_T_46 = and(ldq_ld_byte_mask[23], lcam_mask[0]) node _mask_match_T_47 = eq(_mask_match_T_46, ldq_ld_byte_mask[23]) wire mask_match_23 : UInt<1>[1] connect mask_match_23[0], _mask_match_T_47 node _mask_overlap_T_46 = and(ldq_ld_byte_mask[23], lcam_mask[0]) node _mask_overlap_T_47 = orr(_mask_overlap_T_46) wire mask_overlap_23 : UInt<1>[1] connect mask_overlap_23[0], _mask_overlap_T_47 node _T_1535 = and(do_release_search[0], ldq_valid[23]) node _T_1536 = and(_T_1535, ldq_addr[23].valid) node _T_1537 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1538 = and(_T_1536, _T_1537) node _T_1539 = and(_T_1538, block_addr_matches_23[0]) when _T_1539 : connect ldq_observed[23], UInt<1>(0h1) node _T_1540 = and(do_st_search[0], ldq_valid[23]) node _T_1541 = and(_T_1540, ldq_addr[23].valid) node _T_1542 = or(ldq_executed[23], ldq_succeeded[23]) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = dshr(ldq_st_dep_mask[23], lcam_stq_idx[0]) node _T_1547 = bits(_T_1546, 0, 0) node _T_1548 = and(_T_1545, _T_1547) node _T_1549 = and(_T_1548, dword_addr_matches_23[0]) node _T_1550 = and(_T_1549, mask_overlap_23[0]) when _T_1550 : node _forwarded_is_older_T_92 = lt(ldq_forward_stq_idx[23], lcam_stq_idx[0]) node _forwarded_is_older_T_93 = lt(ldq_forward_stq_idx[23], l_uop_23.stq_idx) node _forwarded_is_older_T_94 = xor(_forwarded_is_older_T_92, _forwarded_is_older_T_93) node _forwarded_is_older_T_95 = lt(lcam_stq_idx[0], l_uop_23.stq_idx) node forwarded_is_older_23 = xor(_forwarded_is_older_T_94, _forwarded_is_older_T_95) node _T_1551 = eq(ldq_forward_std_val[23], UInt<1>(0h0)) node _T_1552 = neq(ldq_forward_stq_idx[23], lcam_stq_idx[0]) node _T_1553 = and(_T_1552, forwarded_is_older_23) node _T_1554 = or(_T_1551, _T_1553) when _T_1554 : connect ldq_order_fail[23], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1555 = and(do_ld_search[0], ldq_valid[23]) node _T_1556 = and(_T_1555, ldq_addr[23].valid) node _T_1557 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = and(_T_1558, dword_addr_matches_23[0]) node _T_1560 = and(_T_1559, mask_overlap_23[0]) when _T_1560 : node searcher_is_older_23 = bits(lcam_younger_load_mask[0], 23, 23) node _T_1561 = lt(lcam_ldq_idx[0], UInt<5>(0h17)) node _T_1562 = lt(lcam_ldq_idx[0], ldq_head) node _T_1563 = xor(_T_1561, _T_1562) node _T_1564 = lt(UInt<5>(0h17), ldq_head) node _T_1565 = xor(_T_1563, _T_1564) node _T_1566 = eq(_T_1565, searcher_is_older_23) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_78 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_78 when searcher_is_older_23 : node _T_1570 = or(ldq_executed[23], ldq_succeeded[23]) node _T_1571 = eq(s1_executing_loads[23], UInt<1>(0h0)) node _T_1572 = and(_T_1570, _T_1571) node _T_1573 = and(_T_1572, ldq_observed[23]) when _T_1573 : node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_79 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_79 else : node _T_1577 = neq(lcam_ldq_idx[0], UInt<5>(0h17)) when _T_1577 : node _T_1578 = or(ldq_succeeded[23], ldq_will_succeed[23]) node _T_1579 = and(ldq_executed[23], _T_1578) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1582 = bits(_T_1581, 4, 0) connect s1_set_execute[_T_1582], UInt<1>(0h0) node _T_1583 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1584 = and(dmem_req_fire[0], _T_1583) reg REG_24 : UInt<1>, clock connect REG_24, _T_1584 node _T_1585 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1586 = and(REG_24, _T_1585) when _T_1586 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) node _nack_dword_addr_matches_T = shr(lcam_addr[0], 3) node _nack_dword_addr_matches_T_1 = shr(io.dmem.nack[0].bits.addr, 3) node nack_dword_addr_matches = eq(_nack_dword_addr_matches_T, _nack_dword_addr_matches_T_1) wire nack_mask : UInt<8> node _nack_mask_mask_T = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<1>(0h0)) node _nack_mask_mask_T_1 = bits(io.dmem.nack[0].bits.addr, 2, 0) node _nack_mask_mask_T_2 = dshl(UInt<8>(0h1), _nack_mask_mask_T_1) node _nack_mask_mask_T_3 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<1>(0h1)) node _nack_mask_mask_T_4 = bits(io.dmem.nack[0].bits.addr, 2, 1) node _nack_mask_mask_T_5 = dshl(_nack_mask_mask_T_4, UInt<1>(0h1)) node _nack_mask_mask_T_6 = dshl(UInt<8>(0h3), _nack_mask_mask_T_5) node _nack_mask_mask_T_7 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<2>(0h2)) node _nack_mask_mask_T_8 = bits(io.dmem.nack[0].bits.addr, 2, 2) node _nack_mask_mask_T_9 = mux(_nack_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _nack_mask_mask_T_10 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<2>(0h3)) node _nack_mask_mask_T_11 = mux(_nack_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _nack_mask_mask_T_12 = mux(_nack_mask_mask_T_7, _nack_mask_mask_T_9, _nack_mask_mask_T_11) node _nack_mask_mask_T_13 = mux(_nack_mask_mask_T_3, _nack_mask_mask_T_6, _nack_mask_mask_T_12) node _nack_mask_mask_T_14 = mux(_nack_mask_mask_T, _nack_mask_mask_T_2, _nack_mask_mask_T_13) connect nack_mask, _nack_mask_mask_T_14 node _nack_mask_overlap_T = and(nack_mask, lcam_mask[0]) node nack_mask_overlap = neq(_nack_mask_overlap_T, UInt<1>(0h0)) node _T_1587 = and(do_ld_search[0], io.dmem.nack[0].valid) node _T_1588 = and(_T_1587, io.dmem.nack[0].bits.uop.uses_ldq) node _T_1589 = and(_T_1588, nack_dword_addr_matches) node _T_1590 = and(_T_1589, nack_mask_overlap) node _T_1591 = lt(io.dmem.nack[0].bits.uop.ldq_idx, lcam_ldq_idx[0]) node _T_1592 = lt(io.dmem.nack[0].bits.uop.ldq_idx, ldq_head) node _T_1593 = xor(_T_1591, _T_1592) node _T_1594 = lt(lcam_ldq_idx[0], ldq_head) node _T_1595 = xor(_T_1593, _T_1594) node _T_1596 = and(_T_1590, _T_1595) when _T_1596 : node _T_1597 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1598 = bits(_T_1597, 4, 0) connect s1_set_execute[_T_1598], UInt<1>(0h0) node _T_1599 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1600 = and(dmem_req_fire[0], _T_1599) reg REG_25 : UInt<1>, clock connect REG_25, _T_1600 node _T_1601 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1602 = and(REG_25, _T_1601) when _T_1602 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) node _forward_dword_addr_matches_T = shr(lcam_addr[0], 3) node _forward_dword_addr_matches_T_1 = shr(wb_ldst_forward_ld_addr[0], 3) node forward_dword_addr_matches = eq(_forward_dword_addr_matches_T, _forward_dword_addr_matches_T_1) wire forward_mask : UInt<8> node _forward_mask_mask_T = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<1>(0h0)) node _forward_mask_mask_T_1 = bits(wb_ldst_forward_ld_addr[0], 2, 0) node _forward_mask_mask_T_2 = dshl(UInt<8>(0h1), _forward_mask_mask_T_1) node _forward_mask_mask_T_3 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<1>(0h1)) node _forward_mask_mask_T_4 = bits(wb_ldst_forward_ld_addr[0], 2, 1) node _forward_mask_mask_T_5 = dshl(_forward_mask_mask_T_4, UInt<1>(0h1)) node _forward_mask_mask_T_6 = dshl(UInt<8>(0h3), _forward_mask_mask_T_5) node _forward_mask_mask_T_7 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<2>(0h2)) node _forward_mask_mask_T_8 = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _forward_mask_mask_T_9 = mux(_forward_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _forward_mask_mask_T_10 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<2>(0h3)) node _forward_mask_mask_T_11 = mux(_forward_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _forward_mask_mask_T_12 = mux(_forward_mask_mask_T_7, _forward_mask_mask_T_9, _forward_mask_mask_T_11) node _forward_mask_mask_T_13 = mux(_forward_mask_mask_T_3, _forward_mask_mask_T_6, _forward_mask_mask_T_12) node _forward_mask_mask_T_14 = mux(_forward_mask_mask_T, _forward_mask_mask_T_2, _forward_mask_mask_T_13) connect forward_mask, _forward_mask_mask_T_14 node _forward_mask_overlap_T = and(forward_mask, lcam_mask[0]) node forward_mask_overlap = neq(_forward_mask_overlap_T, UInt<1>(0h0)) node _T_1603 = and(do_ld_search[0], wb_ldst_forward_valid[0]) node _T_1604 = and(_T_1603, forward_dword_addr_matches) node _T_1605 = and(_T_1604, forward_mask_overlap) node _T_1606 = and(_T_1605, wb_ldst_forward_e[0].observed) node _T_1607 = lt(lcam_ldq_idx[0], wb_ldst_forward_ldq_idx[0]) node _T_1608 = lt(lcam_ldq_idx[0], ldq_head) node _T_1609 = xor(_T_1607, _T_1608) node _T_1610 = lt(wb_ldst_forward_ldq_idx[0], ldq_head) node _T_1611 = xor(_T_1609, _T_1610) node _T_1612 = and(_T_1606, _T_1611) when _T_1612 : node _T_1613 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1614 = bits(_T_1613, 4, 0) connect ldq_order_fail[_T_1614], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _forwarded_is_older_T_96 = lt(wb_ldst_forward_stq_idx[0], lcam_stq_idx[0]) node _forwarded_is_older_T_97 = lt(wb_ldst_forward_stq_idx[0], wb_ldst_forward_e[0].uop.stq_idx) node _forwarded_is_older_T_98 = xor(_forwarded_is_older_T_96, _forwarded_is_older_T_97) node _forwarded_is_older_T_99 = lt(lcam_stq_idx[0], wb_ldst_forward_e[0].uop.stq_idx) node forwarded_is_older_24 = xor(_forwarded_is_older_T_98, _forwarded_is_older_T_99) node _T_1615 = and(do_st_search[0], wb_ldst_forward_valid[0]) node _T_1616 = and(_T_1615, forward_dword_addr_matches) node _T_1617 = and(_T_1616, forward_mask_overlap) node _T_1618 = dshr(wb_ldst_forward_e[0].st_dep_mask, lcam_stq_idx[0]) node _T_1619 = bits(_T_1618, 0, 0) node _T_1620 = and(_T_1617, _T_1619) node _T_1621 = and(_T_1620, forwarded_is_older_24) when _T_1621 : node _T_1622 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1623 = bits(_T_1622, 4, 0) connect ldq_order_fail[_T_1623], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) wire addr_matches : UInt<1>[24][1] wire forward_matches : UInt<1>[24][1] wire prs2_matches : UInt<1>[24][1] wire s_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_3, stq_uop[0] wire write_mask : UInt<8> node _write_mask_mask_T = eq(s_uop_3.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_1 = bits(stq_addr[0].bits, 2, 0) node _write_mask_mask_T_2 = dshl(UInt<8>(0h1), _write_mask_mask_T_1) node _write_mask_mask_T_3 = eq(s_uop_3.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_4 = bits(stq_addr[0].bits, 2, 1) node _write_mask_mask_T_5 = dshl(_write_mask_mask_T_4, UInt<1>(0h1)) node _write_mask_mask_T_6 = dshl(UInt<8>(0h3), _write_mask_mask_T_5) node _write_mask_mask_T_7 = eq(s_uop_3.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_8 = bits(stq_addr[0].bits, 2, 2) node _write_mask_mask_T_9 = mux(_write_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_10 = eq(s_uop_3.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_11 = mux(_write_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_12 = mux(_write_mask_mask_T_7, _write_mask_mask_T_9, _write_mask_mask_T_11) node _write_mask_mask_T_13 = mux(_write_mask_mask_T_3, _write_mask_mask_T_6, _write_mask_mask_T_12) node _write_mask_mask_T_14 = mux(_write_mask_mask_T, _write_mask_mask_T_2, _write_mask_mask_T_13) connect write_mask, _write_mask_mask_T_14 node _dword_addr_matches_T_96 = eq(s_uop_3.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_97 = and(stq_addr[0].valid, _dword_addr_matches_T_96) node _dword_addr_matches_T_98 = eq(stq_addr_is_virtual[0], UInt<1>(0h0)) node _dword_addr_matches_T_99 = and(_dword_addr_matches_T_97, _dword_addr_matches_T_98) node _dword_addr_matches_T_100 = bits(stq_addr[0].bits, 31, 3) node _dword_addr_matches_T_101 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_102 = eq(_dword_addr_matches_T_100, _dword_addr_matches_T_101) node dword_addr_matches_24 = and(_dword_addr_matches_T_99, _dword_addr_matches_T_102) node mask_union = and(lcam_mask[0], write_mask) node _addr_matches_0_0_T = neq(mask_union, UInt<1>(0h0)) node _addr_matches_0_0_T_1 = and(_addr_matches_0_0_T, dword_addr_matches_24) connect addr_matches[0][0], _addr_matches_0_0_T_1 node _forward_matches_0_0_T = and(addr_matches[0][0], stq_data[0].valid) node _forward_matches_0_0_T_1 = eq(mask_union, lcam_mask[0]) node _forward_matches_0_0_T_2 = and(_forward_matches_0_0_T, _forward_matches_0_0_T_1) connect forward_matches[0][0], _forward_matches_0_0_T_2 node _prs2_matches_0_0_T = eq(s_uop_3.prs2, lcam_uop[0].pdst) node _prs2_matches_0_0_T_1 = eq(s_uop_3.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_0_T_2 = and(_prs2_matches_0_0_T, _prs2_matches_0_0_T_1) node _prs2_matches_0_0_T_3 = and(_prs2_matches_0_0_T_2, UInt<1>(0h1)) connect prs2_matches[0][0], _prs2_matches_0_0_T_3 wire s_uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_4, stq_uop[1] wire write_mask_1 : UInt<8> node _write_mask_mask_T_15 = eq(s_uop_4.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_16 = bits(stq_addr[1].bits, 2, 0) node _write_mask_mask_T_17 = dshl(UInt<8>(0h1), _write_mask_mask_T_16) node _write_mask_mask_T_18 = eq(s_uop_4.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_19 = bits(stq_addr[1].bits, 2, 1) node _write_mask_mask_T_20 = dshl(_write_mask_mask_T_19, UInt<1>(0h1)) node _write_mask_mask_T_21 = dshl(UInt<8>(0h3), _write_mask_mask_T_20) node _write_mask_mask_T_22 = eq(s_uop_4.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_23 = bits(stq_addr[1].bits, 2, 2) node _write_mask_mask_T_24 = mux(_write_mask_mask_T_23, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_25 = eq(s_uop_4.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_26 = mux(_write_mask_mask_T_25, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_27 = mux(_write_mask_mask_T_22, _write_mask_mask_T_24, _write_mask_mask_T_26) node _write_mask_mask_T_28 = mux(_write_mask_mask_T_18, _write_mask_mask_T_21, _write_mask_mask_T_27) node _write_mask_mask_T_29 = mux(_write_mask_mask_T_15, _write_mask_mask_T_17, _write_mask_mask_T_28) connect write_mask_1, _write_mask_mask_T_29 node _dword_addr_matches_T_103 = eq(s_uop_4.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_104 = and(stq_addr[1].valid, _dword_addr_matches_T_103) node _dword_addr_matches_T_105 = eq(stq_addr_is_virtual[1], UInt<1>(0h0)) node _dword_addr_matches_T_106 = and(_dword_addr_matches_T_104, _dword_addr_matches_T_105) node _dword_addr_matches_T_107 = bits(stq_addr[1].bits, 31, 3) node _dword_addr_matches_T_108 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_109 = eq(_dword_addr_matches_T_107, _dword_addr_matches_T_108) node dword_addr_matches_25 = and(_dword_addr_matches_T_106, _dword_addr_matches_T_109) node mask_union_1 = and(lcam_mask[0], write_mask_1) node _addr_matches_0_1_T = neq(mask_union_1, UInt<1>(0h0)) node _addr_matches_0_1_T_1 = and(_addr_matches_0_1_T, dword_addr_matches_25) connect addr_matches[0][1], _addr_matches_0_1_T_1 node _forward_matches_0_1_T = and(addr_matches[0][1], stq_data[1].valid) node _forward_matches_0_1_T_1 = eq(mask_union_1, lcam_mask[0]) node _forward_matches_0_1_T_2 = and(_forward_matches_0_1_T, _forward_matches_0_1_T_1) connect forward_matches[0][1], _forward_matches_0_1_T_2 node _prs2_matches_0_1_T = eq(s_uop_4.prs2, lcam_uop[0].pdst) node _prs2_matches_0_1_T_1 = eq(s_uop_4.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_1_T_2 = and(_prs2_matches_0_1_T, _prs2_matches_0_1_T_1) node _prs2_matches_0_1_T_3 = and(_prs2_matches_0_1_T_2, UInt<1>(0h1)) connect prs2_matches[0][1], _prs2_matches_0_1_T_3 wire s_uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_5, stq_uop[2] wire write_mask_2 : UInt<8> node _write_mask_mask_T_30 = eq(s_uop_5.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_31 = bits(stq_addr[2].bits, 2, 0) node _write_mask_mask_T_32 = dshl(UInt<8>(0h1), _write_mask_mask_T_31) node _write_mask_mask_T_33 = eq(s_uop_5.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_34 = bits(stq_addr[2].bits, 2, 1) node _write_mask_mask_T_35 = dshl(_write_mask_mask_T_34, UInt<1>(0h1)) node _write_mask_mask_T_36 = dshl(UInt<8>(0h3), _write_mask_mask_T_35) node _write_mask_mask_T_37 = eq(s_uop_5.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_38 = bits(stq_addr[2].bits, 2, 2) node _write_mask_mask_T_39 = mux(_write_mask_mask_T_38, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_40 = eq(s_uop_5.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_41 = mux(_write_mask_mask_T_40, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_42 = mux(_write_mask_mask_T_37, _write_mask_mask_T_39, _write_mask_mask_T_41) node _write_mask_mask_T_43 = mux(_write_mask_mask_T_33, _write_mask_mask_T_36, _write_mask_mask_T_42) node _write_mask_mask_T_44 = mux(_write_mask_mask_T_30, _write_mask_mask_T_32, _write_mask_mask_T_43) connect write_mask_2, _write_mask_mask_T_44 node _dword_addr_matches_T_110 = eq(s_uop_5.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_111 = and(stq_addr[2].valid, _dword_addr_matches_T_110) node _dword_addr_matches_T_112 = eq(stq_addr_is_virtual[2], UInt<1>(0h0)) node _dword_addr_matches_T_113 = and(_dword_addr_matches_T_111, _dword_addr_matches_T_112) node _dword_addr_matches_T_114 = bits(stq_addr[2].bits, 31, 3) node _dword_addr_matches_T_115 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_116 = eq(_dword_addr_matches_T_114, _dword_addr_matches_T_115) node dword_addr_matches_26 = and(_dword_addr_matches_T_113, _dword_addr_matches_T_116) node mask_union_2 = and(lcam_mask[0], write_mask_2) node _addr_matches_0_2_T = neq(mask_union_2, UInt<1>(0h0)) node _addr_matches_0_2_T_1 = and(_addr_matches_0_2_T, dword_addr_matches_26) connect addr_matches[0][2], _addr_matches_0_2_T_1 node _forward_matches_0_2_T = and(addr_matches[0][2], stq_data[2].valid) node _forward_matches_0_2_T_1 = eq(mask_union_2, lcam_mask[0]) node _forward_matches_0_2_T_2 = and(_forward_matches_0_2_T, _forward_matches_0_2_T_1) connect forward_matches[0][2], _forward_matches_0_2_T_2 node _prs2_matches_0_2_T = eq(s_uop_5.prs2, lcam_uop[0].pdst) node _prs2_matches_0_2_T_1 = eq(s_uop_5.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_2_T_2 = and(_prs2_matches_0_2_T, _prs2_matches_0_2_T_1) node _prs2_matches_0_2_T_3 = and(_prs2_matches_0_2_T_2, UInt<1>(0h1)) connect prs2_matches[0][2], _prs2_matches_0_2_T_3 wire s_uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_6, stq_uop[3] wire write_mask_3 : UInt<8> node _write_mask_mask_T_45 = eq(s_uop_6.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_46 = bits(stq_addr[3].bits, 2, 0) node _write_mask_mask_T_47 = dshl(UInt<8>(0h1), _write_mask_mask_T_46) node _write_mask_mask_T_48 = eq(s_uop_6.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_49 = bits(stq_addr[3].bits, 2, 1) node _write_mask_mask_T_50 = dshl(_write_mask_mask_T_49, UInt<1>(0h1)) node _write_mask_mask_T_51 = dshl(UInt<8>(0h3), _write_mask_mask_T_50) node _write_mask_mask_T_52 = eq(s_uop_6.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_53 = bits(stq_addr[3].bits, 2, 2) node _write_mask_mask_T_54 = mux(_write_mask_mask_T_53, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_55 = eq(s_uop_6.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_56 = mux(_write_mask_mask_T_55, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_57 = mux(_write_mask_mask_T_52, _write_mask_mask_T_54, _write_mask_mask_T_56) node _write_mask_mask_T_58 = mux(_write_mask_mask_T_48, _write_mask_mask_T_51, _write_mask_mask_T_57) node _write_mask_mask_T_59 = mux(_write_mask_mask_T_45, _write_mask_mask_T_47, _write_mask_mask_T_58) connect write_mask_3, _write_mask_mask_T_59 node _dword_addr_matches_T_117 = eq(s_uop_6.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_118 = and(stq_addr[3].valid, _dword_addr_matches_T_117) node _dword_addr_matches_T_119 = eq(stq_addr_is_virtual[3], UInt<1>(0h0)) node _dword_addr_matches_T_120 = and(_dword_addr_matches_T_118, _dword_addr_matches_T_119) node _dword_addr_matches_T_121 = bits(stq_addr[3].bits, 31, 3) node _dword_addr_matches_T_122 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_123 = eq(_dword_addr_matches_T_121, _dword_addr_matches_T_122) node dword_addr_matches_27 = and(_dword_addr_matches_T_120, _dword_addr_matches_T_123) node mask_union_3 = and(lcam_mask[0], write_mask_3) node _addr_matches_0_3_T = neq(mask_union_3, UInt<1>(0h0)) node _addr_matches_0_3_T_1 = and(_addr_matches_0_3_T, dword_addr_matches_27) connect addr_matches[0][3], _addr_matches_0_3_T_1 node _forward_matches_0_3_T = and(addr_matches[0][3], stq_data[3].valid) node _forward_matches_0_3_T_1 = eq(mask_union_3, lcam_mask[0]) node _forward_matches_0_3_T_2 = and(_forward_matches_0_3_T, _forward_matches_0_3_T_1) connect forward_matches[0][3], _forward_matches_0_3_T_2 node _prs2_matches_0_3_T = eq(s_uop_6.prs2, lcam_uop[0].pdst) node _prs2_matches_0_3_T_1 = eq(s_uop_6.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_3_T_2 = and(_prs2_matches_0_3_T, _prs2_matches_0_3_T_1) node _prs2_matches_0_3_T_3 = and(_prs2_matches_0_3_T_2, UInt<1>(0h1)) connect prs2_matches[0][3], _prs2_matches_0_3_T_3 wire s_uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_7, stq_uop[4] wire write_mask_4 : UInt<8> node _write_mask_mask_T_60 = eq(s_uop_7.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_61 = bits(stq_addr[4].bits, 2, 0) node _write_mask_mask_T_62 = dshl(UInt<8>(0h1), _write_mask_mask_T_61) node _write_mask_mask_T_63 = eq(s_uop_7.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_64 = bits(stq_addr[4].bits, 2, 1) node _write_mask_mask_T_65 = dshl(_write_mask_mask_T_64, UInt<1>(0h1)) node _write_mask_mask_T_66 = dshl(UInt<8>(0h3), _write_mask_mask_T_65) node _write_mask_mask_T_67 = eq(s_uop_7.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_68 = bits(stq_addr[4].bits, 2, 2) node _write_mask_mask_T_69 = mux(_write_mask_mask_T_68, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_70 = eq(s_uop_7.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_71 = mux(_write_mask_mask_T_70, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_72 = mux(_write_mask_mask_T_67, _write_mask_mask_T_69, _write_mask_mask_T_71) node _write_mask_mask_T_73 = mux(_write_mask_mask_T_63, _write_mask_mask_T_66, _write_mask_mask_T_72) node _write_mask_mask_T_74 = mux(_write_mask_mask_T_60, _write_mask_mask_T_62, _write_mask_mask_T_73) connect write_mask_4, _write_mask_mask_T_74 node _dword_addr_matches_T_124 = eq(s_uop_7.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_125 = and(stq_addr[4].valid, _dword_addr_matches_T_124) node _dword_addr_matches_T_126 = eq(stq_addr_is_virtual[4], UInt<1>(0h0)) node _dword_addr_matches_T_127 = and(_dword_addr_matches_T_125, _dword_addr_matches_T_126) node _dword_addr_matches_T_128 = bits(stq_addr[4].bits, 31, 3) node _dword_addr_matches_T_129 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_130 = eq(_dword_addr_matches_T_128, _dword_addr_matches_T_129) node dword_addr_matches_28 = and(_dword_addr_matches_T_127, _dword_addr_matches_T_130) node mask_union_4 = and(lcam_mask[0], write_mask_4) node _addr_matches_0_4_T = neq(mask_union_4, UInt<1>(0h0)) node _addr_matches_0_4_T_1 = and(_addr_matches_0_4_T, dword_addr_matches_28) connect addr_matches[0][4], _addr_matches_0_4_T_1 node _forward_matches_0_4_T = and(addr_matches[0][4], stq_data[4].valid) node _forward_matches_0_4_T_1 = eq(mask_union_4, lcam_mask[0]) node _forward_matches_0_4_T_2 = and(_forward_matches_0_4_T, _forward_matches_0_4_T_1) connect forward_matches[0][4], _forward_matches_0_4_T_2 node _prs2_matches_0_4_T = eq(s_uop_7.prs2, lcam_uop[0].pdst) node _prs2_matches_0_4_T_1 = eq(s_uop_7.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_4_T_2 = and(_prs2_matches_0_4_T, _prs2_matches_0_4_T_1) node _prs2_matches_0_4_T_3 = and(_prs2_matches_0_4_T_2, UInt<1>(0h1)) connect prs2_matches[0][4], _prs2_matches_0_4_T_3 wire s_uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_8, stq_uop[5] wire write_mask_5 : UInt<8> node _write_mask_mask_T_75 = eq(s_uop_8.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_76 = bits(stq_addr[5].bits, 2, 0) node _write_mask_mask_T_77 = dshl(UInt<8>(0h1), _write_mask_mask_T_76) node _write_mask_mask_T_78 = eq(s_uop_8.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_79 = bits(stq_addr[5].bits, 2, 1) node _write_mask_mask_T_80 = dshl(_write_mask_mask_T_79, UInt<1>(0h1)) node _write_mask_mask_T_81 = dshl(UInt<8>(0h3), _write_mask_mask_T_80) node _write_mask_mask_T_82 = eq(s_uop_8.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_83 = bits(stq_addr[5].bits, 2, 2) node _write_mask_mask_T_84 = mux(_write_mask_mask_T_83, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_85 = eq(s_uop_8.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_86 = mux(_write_mask_mask_T_85, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_87 = mux(_write_mask_mask_T_82, _write_mask_mask_T_84, _write_mask_mask_T_86) node _write_mask_mask_T_88 = mux(_write_mask_mask_T_78, _write_mask_mask_T_81, _write_mask_mask_T_87) node _write_mask_mask_T_89 = mux(_write_mask_mask_T_75, _write_mask_mask_T_77, _write_mask_mask_T_88) connect write_mask_5, _write_mask_mask_T_89 node _dword_addr_matches_T_131 = eq(s_uop_8.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_132 = and(stq_addr[5].valid, _dword_addr_matches_T_131) node _dword_addr_matches_T_133 = eq(stq_addr_is_virtual[5], UInt<1>(0h0)) node _dword_addr_matches_T_134 = and(_dword_addr_matches_T_132, _dword_addr_matches_T_133) node _dword_addr_matches_T_135 = bits(stq_addr[5].bits, 31, 3) node _dword_addr_matches_T_136 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_137 = eq(_dword_addr_matches_T_135, _dword_addr_matches_T_136) node dword_addr_matches_29 = and(_dword_addr_matches_T_134, _dword_addr_matches_T_137) node mask_union_5 = and(lcam_mask[0], write_mask_5) node _addr_matches_0_5_T = neq(mask_union_5, UInt<1>(0h0)) node _addr_matches_0_5_T_1 = and(_addr_matches_0_5_T, dword_addr_matches_29) connect addr_matches[0][5], _addr_matches_0_5_T_1 node _forward_matches_0_5_T = and(addr_matches[0][5], stq_data[5].valid) node _forward_matches_0_5_T_1 = eq(mask_union_5, lcam_mask[0]) node _forward_matches_0_5_T_2 = and(_forward_matches_0_5_T, _forward_matches_0_5_T_1) connect forward_matches[0][5], _forward_matches_0_5_T_2 node _prs2_matches_0_5_T = eq(s_uop_8.prs2, lcam_uop[0].pdst) node _prs2_matches_0_5_T_1 = eq(s_uop_8.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_5_T_2 = and(_prs2_matches_0_5_T, _prs2_matches_0_5_T_1) node _prs2_matches_0_5_T_3 = and(_prs2_matches_0_5_T_2, UInt<1>(0h1)) connect prs2_matches[0][5], _prs2_matches_0_5_T_3 wire s_uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_9, stq_uop[6] wire write_mask_6 : UInt<8> node _write_mask_mask_T_90 = eq(s_uop_9.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_91 = bits(stq_addr[6].bits, 2, 0) node _write_mask_mask_T_92 = dshl(UInt<8>(0h1), _write_mask_mask_T_91) node _write_mask_mask_T_93 = eq(s_uop_9.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_94 = bits(stq_addr[6].bits, 2, 1) node _write_mask_mask_T_95 = dshl(_write_mask_mask_T_94, UInt<1>(0h1)) node _write_mask_mask_T_96 = dshl(UInt<8>(0h3), _write_mask_mask_T_95) node _write_mask_mask_T_97 = eq(s_uop_9.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_98 = bits(stq_addr[6].bits, 2, 2) node _write_mask_mask_T_99 = mux(_write_mask_mask_T_98, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_100 = eq(s_uop_9.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_101 = mux(_write_mask_mask_T_100, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_102 = mux(_write_mask_mask_T_97, _write_mask_mask_T_99, _write_mask_mask_T_101) node _write_mask_mask_T_103 = mux(_write_mask_mask_T_93, _write_mask_mask_T_96, _write_mask_mask_T_102) node _write_mask_mask_T_104 = mux(_write_mask_mask_T_90, _write_mask_mask_T_92, _write_mask_mask_T_103) connect write_mask_6, _write_mask_mask_T_104 node _dword_addr_matches_T_138 = eq(s_uop_9.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_139 = and(stq_addr[6].valid, _dword_addr_matches_T_138) node _dword_addr_matches_T_140 = eq(stq_addr_is_virtual[6], UInt<1>(0h0)) node _dword_addr_matches_T_141 = and(_dword_addr_matches_T_139, _dword_addr_matches_T_140) node _dword_addr_matches_T_142 = bits(stq_addr[6].bits, 31, 3) node _dword_addr_matches_T_143 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_144 = eq(_dword_addr_matches_T_142, _dword_addr_matches_T_143) node dword_addr_matches_30 = and(_dword_addr_matches_T_141, _dword_addr_matches_T_144) node mask_union_6 = and(lcam_mask[0], write_mask_6) node _addr_matches_0_6_T = neq(mask_union_6, UInt<1>(0h0)) node _addr_matches_0_6_T_1 = and(_addr_matches_0_6_T, dword_addr_matches_30) connect addr_matches[0][6], _addr_matches_0_6_T_1 node _forward_matches_0_6_T = and(addr_matches[0][6], stq_data[6].valid) node _forward_matches_0_6_T_1 = eq(mask_union_6, lcam_mask[0]) node _forward_matches_0_6_T_2 = and(_forward_matches_0_6_T, _forward_matches_0_6_T_1) connect forward_matches[0][6], _forward_matches_0_6_T_2 node _prs2_matches_0_6_T = eq(s_uop_9.prs2, lcam_uop[0].pdst) node _prs2_matches_0_6_T_1 = eq(s_uop_9.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_6_T_2 = and(_prs2_matches_0_6_T, _prs2_matches_0_6_T_1) node _prs2_matches_0_6_T_3 = and(_prs2_matches_0_6_T_2, UInt<1>(0h1)) connect prs2_matches[0][6], _prs2_matches_0_6_T_3 wire s_uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_10, stq_uop[7] wire write_mask_7 : UInt<8> node _write_mask_mask_T_105 = eq(s_uop_10.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_106 = bits(stq_addr[7].bits, 2, 0) node _write_mask_mask_T_107 = dshl(UInt<8>(0h1), _write_mask_mask_T_106) node _write_mask_mask_T_108 = eq(s_uop_10.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_109 = bits(stq_addr[7].bits, 2, 1) node _write_mask_mask_T_110 = dshl(_write_mask_mask_T_109, UInt<1>(0h1)) node _write_mask_mask_T_111 = dshl(UInt<8>(0h3), _write_mask_mask_T_110) node _write_mask_mask_T_112 = eq(s_uop_10.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_113 = bits(stq_addr[7].bits, 2, 2) node _write_mask_mask_T_114 = mux(_write_mask_mask_T_113, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_115 = eq(s_uop_10.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_116 = mux(_write_mask_mask_T_115, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_117 = mux(_write_mask_mask_T_112, _write_mask_mask_T_114, _write_mask_mask_T_116) node _write_mask_mask_T_118 = mux(_write_mask_mask_T_108, _write_mask_mask_T_111, _write_mask_mask_T_117) node _write_mask_mask_T_119 = mux(_write_mask_mask_T_105, _write_mask_mask_T_107, _write_mask_mask_T_118) connect write_mask_7, _write_mask_mask_T_119 node _dword_addr_matches_T_145 = eq(s_uop_10.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_146 = and(stq_addr[7].valid, _dword_addr_matches_T_145) node _dword_addr_matches_T_147 = eq(stq_addr_is_virtual[7], UInt<1>(0h0)) node _dword_addr_matches_T_148 = and(_dword_addr_matches_T_146, _dword_addr_matches_T_147) node _dword_addr_matches_T_149 = bits(stq_addr[7].bits, 31, 3) node _dword_addr_matches_T_150 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_151 = eq(_dword_addr_matches_T_149, _dword_addr_matches_T_150) node dword_addr_matches_31 = and(_dword_addr_matches_T_148, _dword_addr_matches_T_151) node mask_union_7 = and(lcam_mask[0], write_mask_7) node _addr_matches_0_7_T = neq(mask_union_7, UInt<1>(0h0)) node _addr_matches_0_7_T_1 = and(_addr_matches_0_7_T, dword_addr_matches_31) connect addr_matches[0][7], _addr_matches_0_7_T_1 node _forward_matches_0_7_T = and(addr_matches[0][7], stq_data[7].valid) node _forward_matches_0_7_T_1 = eq(mask_union_7, lcam_mask[0]) node _forward_matches_0_7_T_2 = and(_forward_matches_0_7_T, _forward_matches_0_7_T_1) connect forward_matches[0][7], _forward_matches_0_7_T_2 node _prs2_matches_0_7_T = eq(s_uop_10.prs2, lcam_uop[0].pdst) node _prs2_matches_0_7_T_1 = eq(s_uop_10.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_7_T_2 = and(_prs2_matches_0_7_T, _prs2_matches_0_7_T_1) node _prs2_matches_0_7_T_3 = and(_prs2_matches_0_7_T_2, UInt<1>(0h1)) connect prs2_matches[0][7], _prs2_matches_0_7_T_3 wire s_uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_11, stq_uop[8] wire write_mask_8 : UInt<8> node _write_mask_mask_T_120 = eq(s_uop_11.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_121 = bits(stq_addr[8].bits, 2, 0) node _write_mask_mask_T_122 = dshl(UInt<8>(0h1), _write_mask_mask_T_121) node _write_mask_mask_T_123 = eq(s_uop_11.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_124 = bits(stq_addr[8].bits, 2, 1) node _write_mask_mask_T_125 = dshl(_write_mask_mask_T_124, UInt<1>(0h1)) node _write_mask_mask_T_126 = dshl(UInt<8>(0h3), _write_mask_mask_T_125) node _write_mask_mask_T_127 = eq(s_uop_11.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_128 = bits(stq_addr[8].bits, 2, 2) node _write_mask_mask_T_129 = mux(_write_mask_mask_T_128, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_130 = eq(s_uop_11.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_131 = mux(_write_mask_mask_T_130, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_132 = mux(_write_mask_mask_T_127, _write_mask_mask_T_129, _write_mask_mask_T_131) node _write_mask_mask_T_133 = mux(_write_mask_mask_T_123, _write_mask_mask_T_126, _write_mask_mask_T_132) node _write_mask_mask_T_134 = mux(_write_mask_mask_T_120, _write_mask_mask_T_122, _write_mask_mask_T_133) connect write_mask_8, _write_mask_mask_T_134 node _dword_addr_matches_T_152 = eq(s_uop_11.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_153 = and(stq_addr[8].valid, _dword_addr_matches_T_152) node _dword_addr_matches_T_154 = eq(stq_addr_is_virtual[8], UInt<1>(0h0)) node _dword_addr_matches_T_155 = and(_dword_addr_matches_T_153, _dword_addr_matches_T_154) node _dword_addr_matches_T_156 = bits(stq_addr[8].bits, 31, 3) node _dword_addr_matches_T_157 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_158 = eq(_dword_addr_matches_T_156, _dword_addr_matches_T_157) node dword_addr_matches_32 = and(_dword_addr_matches_T_155, _dword_addr_matches_T_158) node mask_union_8 = and(lcam_mask[0], write_mask_8) node _addr_matches_0_8_T = neq(mask_union_8, UInt<1>(0h0)) node _addr_matches_0_8_T_1 = and(_addr_matches_0_8_T, dword_addr_matches_32) connect addr_matches[0][8], _addr_matches_0_8_T_1 node _forward_matches_0_8_T = and(addr_matches[0][8], stq_data[8].valid) node _forward_matches_0_8_T_1 = eq(mask_union_8, lcam_mask[0]) node _forward_matches_0_8_T_2 = and(_forward_matches_0_8_T, _forward_matches_0_8_T_1) connect forward_matches[0][8], _forward_matches_0_8_T_2 node _prs2_matches_0_8_T = eq(s_uop_11.prs2, lcam_uop[0].pdst) node _prs2_matches_0_8_T_1 = eq(s_uop_11.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_8_T_2 = and(_prs2_matches_0_8_T, _prs2_matches_0_8_T_1) node _prs2_matches_0_8_T_3 = and(_prs2_matches_0_8_T_2, UInt<1>(0h1)) connect prs2_matches[0][8], _prs2_matches_0_8_T_3 wire s_uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_12, stq_uop[9] wire write_mask_9 : UInt<8> node _write_mask_mask_T_135 = eq(s_uop_12.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_136 = bits(stq_addr[9].bits, 2, 0) node _write_mask_mask_T_137 = dshl(UInt<8>(0h1), _write_mask_mask_T_136) node _write_mask_mask_T_138 = eq(s_uop_12.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_139 = bits(stq_addr[9].bits, 2, 1) node _write_mask_mask_T_140 = dshl(_write_mask_mask_T_139, UInt<1>(0h1)) node _write_mask_mask_T_141 = dshl(UInt<8>(0h3), _write_mask_mask_T_140) node _write_mask_mask_T_142 = eq(s_uop_12.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_143 = bits(stq_addr[9].bits, 2, 2) node _write_mask_mask_T_144 = mux(_write_mask_mask_T_143, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_145 = eq(s_uop_12.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_146 = mux(_write_mask_mask_T_145, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_147 = mux(_write_mask_mask_T_142, _write_mask_mask_T_144, _write_mask_mask_T_146) node _write_mask_mask_T_148 = mux(_write_mask_mask_T_138, _write_mask_mask_T_141, _write_mask_mask_T_147) node _write_mask_mask_T_149 = mux(_write_mask_mask_T_135, _write_mask_mask_T_137, _write_mask_mask_T_148) connect write_mask_9, _write_mask_mask_T_149 node _dword_addr_matches_T_159 = eq(s_uop_12.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_160 = and(stq_addr[9].valid, _dword_addr_matches_T_159) node _dword_addr_matches_T_161 = eq(stq_addr_is_virtual[9], UInt<1>(0h0)) node _dword_addr_matches_T_162 = and(_dword_addr_matches_T_160, _dword_addr_matches_T_161) node _dword_addr_matches_T_163 = bits(stq_addr[9].bits, 31, 3) node _dword_addr_matches_T_164 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_165 = eq(_dword_addr_matches_T_163, _dword_addr_matches_T_164) node dword_addr_matches_33 = and(_dword_addr_matches_T_162, _dword_addr_matches_T_165) node mask_union_9 = and(lcam_mask[0], write_mask_9) node _addr_matches_0_9_T = neq(mask_union_9, UInt<1>(0h0)) node _addr_matches_0_9_T_1 = and(_addr_matches_0_9_T, dword_addr_matches_33) connect addr_matches[0][9], _addr_matches_0_9_T_1 node _forward_matches_0_9_T = and(addr_matches[0][9], stq_data[9].valid) node _forward_matches_0_9_T_1 = eq(mask_union_9, lcam_mask[0]) node _forward_matches_0_9_T_2 = and(_forward_matches_0_9_T, _forward_matches_0_9_T_1) connect forward_matches[0][9], _forward_matches_0_9_T_2 node _prs2_matches_0_9_T = eq(s_uop_12.prs2, lcam_uop[0].pdst) node _prs2_matches_0_9_T_1 = eq(s_uop_12.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_9_T_2 = and(_prs2_matches_0_9_T, _prs2_matches_0_9_T_1) node _prs2_matches_0_9_T_3 = and(_prs2_matches_0_9_T_2, UInt<1>(0h1)) connect prs2_matches[0][9], _prs2_matches_0_9_T_3 wire s_uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_13, stq_uop[10] wire write_mask_10 : UInt<8> node _write_mask_mask_T_150 = eq(s_uop_13.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_151 = bits(stq_addr[10].bits, 2, 0) node _write_mask_mask_T_152 = dshl(UInt<8>(0h1), _write_mask_mask_T_151) node _write_mask_mask_T_153 = eq(s_uop_13.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_154 = bits(stq_addr[10].bits, 2, 1) node _write_mask_mask_T_155 = dshl(_write_mask_mask_T_154, UInt<1>(0h1)) node _write_mask_mask_T_156 = dshl(UInt<8>(0h3), _write_mask_mask_T_155) node _write_mask_mask_T_157 = eq(s_uop_13.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_158 = bits(stq_addr[10].bits, 2, 2) node _write_mask_mask_T_159 = mux(_write_mask_mask_T_158, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_160 = eq(s_uop_13.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_161 = mux(_write_mask_mask_T_160, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_162 = mux(_write_mask_mask_T_157, _write_mask_mask_T_159, _write_mask_mask_T_161) node _write_mask_mask_T_163 = mux(_write_mask_mask_T_153, _write_mask_mask_T_156, _write_mask_mask_T_162) node _write_mask_mask_T_164 = mux(_write_mask_mask_T_150, _write_mask_mask_T_152, _write_mask_mask_T_163) connect write_mask_10, _write_mask_mask_T_164 node _dword_addr_matches_T_166 = eq(s_uop_13.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_167 = and(stq_addr[10].valid, _dword_addr_matches_T_166) node _dword_addr_matches_T_168 = eq(stq_addr_is_virtual[10], UInt<1>(0h0)) node _dword_addr_matches_T_169 = and(_dword_addr_matches_T_167, _dword_addr_matches_T_168) node _dword_addr_matches_T_170 = bits(stq_addr[10].bits, 31, 3) node _dword_addr_matches_T_171 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_172 = eq(_dword_addr_matches_T_170, _dword_addr_matches_T_171) node dword_addr_matches_34 = and(_dword_addr_matches_T_169, _dword_addr_matches_T_172) node mask_union_10 = and(lcam_mask[0], write_mask_10) node _addr_matches_0_10_T = neq(mask_union_10, UInt<1>(0h0)) node _addr_matches_0_10_T_1 = and(_addr_matches_0_10_T, dword_addr_matches_34) connect addr_matches[0][10], _addr_matches_0_10_T_1 node _forward_matches_0_10_T = and(addr_matches[0][10], stq_data[10].valid) node _forward_matches_0_10_T_1 = eq(mask_union_10, lcam_mask[0]) node _forward_matches_0_10_T_2 = and(_forward_matches_0_10_T, _forward_matches_0_10_T_1) connect forward_matches[0][10], _forward_matches_0_10_T_2 node _prs2_matches_0_10_T = eq(s_uop_13.prs2, lcam_uop[0].pdst) node _prs2_matches_0_10_T_1 = eq(s_uop_13.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_10_T_2 = and(_prs2_matches_0_10_T, _prs2_matches_0_10_T_1) node _prs2_matches_0_10_T_3 = and(_prs2_matches_0_10_T_2, UInt<1>(0h1)) connect prs2_matches[0][10], _prs2_matches_0_10_T_3 wire s_uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_14, stq_uop[11] wire write_mask_11 : UInt<8> node _write_mask_mask_T_165 = eq(s_uop_14.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_166 = bits(stq_addr[11].bits, 2, 0) node _write_mask_mask_T_167 = dshl(UInt<8>(0h1), _write_mask_mask_T_166) node _write_mask_mask_T_168 = eq(s_uop_14.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_169 = bits(stq_addr[11].bits, 2, 1) node _write_mask_mask_T_170 = dshl(_write_mask_mask_T_169, UInt<1>(0h1)) node _write_mask_mask_T_171 = dshl(UInt<8>(0h3), _write_mask_mask_T_170) node _write_mask_mask_T_172 = eq(s_uop_14.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_173 = bits(stq_addr[11].bits, 2, 2) node _write_mask_mask_T_174 = mux(_write_mask_mask_T_173, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_175 = eq(s_uop_14.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_176 = mux(_write_mask_mask_T_175, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_177 = mux(_write_mask_mask_T_172, _write_mask_mask_T_174, _write_mask_mask_T_176) node _write_mask_mask_T_178 = mux(_write_mask_mask_T_168, _write_mask_mask_T_171, _write_mask_mask_T_177) node _write_mask_mask_T_179 = mux(_write_mask_mask_T_165, _write_mask_mask_T_167, _write_mask_mask_T_178) connect write_mask_11, _write_mask_mask_T_179 node _dword_addr_matches_T_173 = eq(s_uop_14.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_174 = and(stq_addr[11].valid, _dword_addr_matches_T_173) node _dword_addr_matches_T_175 = eq(stq_addr_is_virtual[11], UInt<1>(0h0)) node _dword_addr_matches_T_176 = and(_dword_addr_matches_T_174, _dword_addr_matches_T_175) node _dword_addr_matches_T_177 = bits(stq_addr[11].bits, 31, 3) node _dword_addr_matches_T_178 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_179 = eq(_dword_addr_matches_T_177, _dword_addr_matches_T_178) node dword_addr_matches_35 = and(_dword_addr_matches_T_176, _dword_addr_matches_T_179) node mask_union_11 = and(lcam_mask[0], write_mask_11) node _addr_matches_0_11_T = neq(mask_union_11, UInt<1>(0h0)) node _addr_matches_0_11_T_1 = and(_addr_matches_0_11_T, dword_addr_matches_35) connect addr_matches[0][11], _addr_matches_0_11_T_1 node _forward_matches_0_11_T = and(addr_matches[0][11], stq_data[11].valid) node _forward_matches_0_11_T_1 = eq(mask_union_11, lcam_mask[0]) node _forward_matches_0_11_T_2 = and(_forward_matches_0_11_T, _forward_matches_0_11_T_1) connect forward_matches[0][11], _forward_matches_0_11_T_2 node _prs2_matches_0_11_T = eq(s_uop_14.prs2, lcam_uop[0].pdst) node _prs2_matches_0_11_T_1 = eq(s_uop_14.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_11_T_2 = and(_prs2_matches_0_11_T, _prs2_matches_0_11_T_1) node _prs2_matches_0_11_T_3 = and(_prs2_matches_0_11_T_2, UInt<1>(0h1)) connect prs2_matches[0][11], _prs2_matches_0_11_T_3 wire s_uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_15, stq_uop[12] wire write_mask_12 : UInt<8> node _write_mask_mask_T_180 = eq(s_uop_15.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_181 = bits(stq_addr[12].bits, 2, 0) node _write_mask_mask_T_182 = dshl(UInt<8>(0h1), _write_mask_mask_T_181) node _write_mask_mask_T_183 = eq(s_uop_15.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_184 = bits(stq_addr[12].bits, 2, 1) node _write_mask_mask_T_185 = dshl(_write_mask_mask_T_184, UInt<1>(0h1)) node _write_mask_mask_T_186 = dshl(UInt<8>(0h3), _write_mask_mask_T_185) node _write_mask_mask_T_187 = eq(s_uop_15.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_188 = bits(stq_addr[12].bits, 2, 2) node _write_mask_mask_T_189 = mux(_write_mask_mask_T_188, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_190 = eq(s_uop_15.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_191 = mux(_write_mask_mask_T_190, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_192 = mux(_write_mask_mask_T_187, _write_mask_mask_T_189, _write_mask_mask_T_191) node _write_mask_mask_T_193 = mux(_write_mask_mask_T_183, _write_mask_mask_T_186, _write_mask_mask_T_192) node _write_mask_mask_T_194 = mux(_write_mask_mask_T_180, _write_mask_mask_T_182, _write_mask_mask_T_193) connect write_mask_12, _write_mask_mask_T_194 node _dword_addr_matches_T_180 = eq(s_uop_15.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_181 = and(stq_addr[12].valid, _dword_addr_matches_T_180) node _dword_addr_matches_T_182 = eq(stq_addr_is_virtual[12], UInt<1>(0h0)) node _dword_addr_matches_T_183 = and(_dword_addr_matches_T_181, _dword_addr_matches_T_182) node _dword_addr_matches_T_184 = bits(stq_addr[12].bits, 31, 3) node _dword_addr_matches_T_185 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_186 = eq(_dword_addr_matches_T_184, _dword_addr_matches_T_185) node dword_addr_matches_36 = and(_dword_addr_matches_T_183, _dword_addr_matches_T_186) node mask_union_12 = and(lcam_mask[0], write_mask_12) node _addr_matches_0_12_T = neq(mask_union_12, UInt<1>(0h0)) node _addr_matches_0_12_T_1 = and(_addr_matches_0_12_T, dword_addr_matches_36) connect addr_matches[0][12], _addr_matches_0_12_T_1 node _forward_matches_0_12_T = and(addr_matches[0][12], stq_data[12].valid) node _forward_matches_0_12_T_1 = eq(mask_union_12, lcam_mask[0]) node _forward_matches_0_12_T_2 = and(_forward_matches_0_12_T, _forward_matches_0_12_T_1) connect forward_matches[0][12], _forward_matches_0_12_T_2 node _prs2_matches_0_12_T = eq(s_uop_15.prs2, lcam_uop[0].pdst) node _prs2_matches_0_12_T_1 = eq(s_uop_15.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_12_T_2 = and(_prs2_matches_0_12_T, _prs2_matches_0_12_T_1) node _prs2_matches_0_12_T_3 = and(_prs2_matches_0_12_T_2, UInt<1>(0h1)) connect prs2_matches[0][12], _prs2_matches_0_12_T_3 wire s_uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_16, stq_uop[13] wire write_mask_13 : UInt<8> node _write_mask_mask_T_195 = eq(s_uop_16.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_196 = bits(stq_addr[13].bits, 2, 0) node _write_mask_mask_T_197 = dshl(UInt<8>(0h1), _write_mask_mask_T_196) node _write_mask_mask_T_198 = eq(s_uop_16.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_199 = bits(stq_addr[13].bits, 2, 1) node _write_mask_mask_T_200 = dshl(_write_mask_mask_T_199, UInt<1>(0h1)) node _write_mask_mask_T_201 = dshl(UInt<8>(0h3), _write_mask_mask_T_200) node _write_mask_mask_T_202 = eq(s_uop_16.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_203 = bits(stq_addr[13].bits, 2, 2) node _write_mask_mask_T_204 = mux(_write_mask_mask_T_203, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_205 = eq(s_uop_16.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_206 = mux(_write_mask_mask_T_205, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_207 = mux(_write_mask_mask_T_202, _write_mask_mask_T_204, _write_mask_mask_T_206) node _write_mask_mask_T_208 = mux(_write_mask_mask_T_198, _write_mask_mask_T_201, _write_mask_mask_T_207) node _write_mask_mask_T_209 = mux(_write_mask_mask_T_195, _write_mask_mask_T_197, _write_mask_mask_T_208) connect write_mask_13, _write_mask_mask_T_209 node _dword_addr_matches_T_187 = eq(s_uop_16.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_188 = and(stq_addr[13].valid, _dword_addr_matches_T_187) node _dword_addr_matches_T_189 = eq(stq_addr_is_virtual[13], UInt<1>(0h0)) node _dword_addr_matches_T_190 = and(_dword_addr_matches_T_188, _dword_addr_matches_T_189) node _dword_addr_matches_T_191 = bits(stq_addr[13].bits, 31, 3) node _dword_addr_matches_T_192 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_193 = eq(_dword_addr_matches_T_191, _dword_addr_matches_T_192) node dword_addr_matches_37 = and(_dword_addr_matches_T_190, _dword_addr_matches_T_193) node mask_union_13 = and(lcam_mask[0], write_mask_13) node _addr_matches_0_13_T = neq(mask_union_13, UInt<1>(0h0)) node _addr_matches_0_13_T_1 = and(_addr_matches_0_13_T, dword_addr_matches_37) connect addr_matches[0][13], _addr_matches_0_13_T_1 node _forward_matches_0_13_T = and(addr_matches[0][13], stq_data[13].valid) node _forward_matches_0_13_T_1 = eq(mask_union_13, lcam_mask[0]) node _forward_matches_0_13_T_2 = and(_forward_matches_0_13_T, _forward_matches_0_13_T_1) connect forward_matches[0][13], _forward_matches_0_13_T_2 node _prs2_matches_0_13_T = eq(s_uop_16.prs2, lcam_uop[0].pdst) node _prs2_matches_0_13_T_1 = eq(s_uop_16.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_13_T_2 = and(_prs2_matches_0_13_T, _prs2_matches_0_13_T_1) node _prs2_matches_0_13_T_3 = and(_prs2_matches_0_13_T_2, UInt<1>(0h1)) connect prs2_matches[0][13], _prs2_matches_0_13_T_3 wire s_uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_17, stq_uop[14] wire write_mask_14 : UInt<8> node _write_mask_mask_T_210 = eq(s_uop_17.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_211 = bits(stq_addr[14].bits, 2, 0) node _write_mask_mask_T_212 = dshl(UInt<8>(0h1), _write_mask_mask_T_211) node _write_mask_mask_T_213 = eq(s_uop_17.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_214 = bits(stq_addr[14].bits, 2, 1) node _write_mask_mask_T_215 = dshl(_write_mask_mask_T_214, UInt<1>(0h1)) node _write_mask_mask_T_216 = dshl(UInt<8>(0h3), _write_mask_mask_T_215) node _write_mask_mask_T_217 = eq(s_uop_17.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_218 = bits(stq_addr[14].bits, 2, 2) node _write_mask_mask_T_219 = mux(_write_mask_mask_T_218, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_220 = eq(s_uop_17.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_221 = mux(_write_mask_mask_T_220, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_222 = mux(_write_mask_mask_T_217, _write_mask_mask_T_219, _write_mask_mask_T_221) node _write_mask_mask_T_223 = mux(_write_mask_mask_T_213, _write_mask_mask_T_216, _write_mask_mask_T_222) node _write_mask_mask_T_224 = mux(_write_mask_mask_T_210, _write_mask_mask_T_212, _write_mask_mask_T_223) connect write_mask_14, _write_mask_mask_T_224 node _dword_addr_matches_T_194 = eq(s_uop_17.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_195 = and(stq_addr[14].valid, _dword_addr_matches_T_194) node _dword_addr_matches_T_196 = eq(stq_addr_is_virtual[14], UInt<1>(0h0)) node _dword_addr_matches_T_197 = and(_dword_addr_matches_T_195, _dword_addr_matches_T_196) node _dword_addr_matches_T_198 = bits(stq_addr[14].bits, 31, 3) node _dword_addr_matches_T_199 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_200 = eq(_dword_addr_matches_T_198, _dword_addr_matches_T_199) node dword_addr_matches_38 = and(_dword_addr_matches_T_197, _dword_addr_matches_T_200) node mask_union_14 = and(lcam_mask[0], write_mask_14) node _addr_matches_0_14_T = neq(mask_union_14, UInt<1>(0h0)) node _addr_matches_0_14_T_1 = and(_addr_matches_0_14_T, dword_addr_matches_38) connect addr_matches[0][14], _addr_matches_0_14_T_1 node _forward_matches_0_14_T = and(addr_matches[0][14], stq_data[14].valid) node _forward_matches_0_14_T_1 = eq(mask_union_14, lcam_mask[0]) node _forward_matches_0_14_T_2 = and(_forward_matches_0_14_T, _forward_matches_0_14_T_1) connect forward_matches[0][14], _forward_matches_0_14_T_2 node _prs2_matches_0_14_T = eq(s_uop_17.prs2, lcam_uop[0].pdst) node _prs2_matches_0_14_T_1 = eq(s_uop_17.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_14_T_2 = and(_prs2_matches_0_14_T, _prs2_matches_0_14_T_1) node _prs2_matches_0_14_T_3 = and(_prs2_matches_0_14_T_2, UInt<1>(0h1)) connect prs2_matches[0][14], _prs2_matches_0_14_T_3 wire s_uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_18, stq_uop[15] wire write_mask_15 : UInt<8> node _write_mask_mask_T_225 = eq(s_uop_18.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_226 = bits(stq_addr[15].bits, 2, 0) node _write_mask_mask_T_227 = dshl(UInt<8>(0h1), _write_mask_mask_T_226) node _write_mask_mask_T_228 = eq(s_uop_18.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_229 = bits(stq_addr[15].bits, 2, 1) node _write_mask_mask_T_230 = dshl(_write_mask_mask_T_229, UInt<1>(0h1)) node _write_mask_mask_T_231 = dshl(UInt<8>(0h3), _write_mask_mask_T_230) node _write_mask_mask_T_232 = eq(s_uop_18.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_233 = bits(stq_addr[15].bits, 2, 2) node _write_mask_mask_T_234 = mux(_write_mask_mask_T_233, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_235 = eq(s_uop_18.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_236 = mux(_write_mask_mask_T_235, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_237 = mux(_write_mask_mask_T_232, _write_mask_mask_T_234, _write_mask_mask_T_236) node _write_mask_mask_T_238 = mux(_write_mask_mask_T_228, _write_mask_mask_T_231, _write_mask_mask_T_237) node _write_mask_mask_T_239 = mux(_write_mask_mask_T_225, _write_mask_mask_T_227, _write_mask_mask_T_238) connect write_mask_15, _write_mask_mask_T_239 node _dword_addr_matches_T_201 = eq(s_uop_18.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_202 = and(stq_addr[15].valid, _dword_addr_matches_T_201) node _dword_addr_matches_T_203 = eq(stq_addr_is_virtual[15], UInt<1>(0h0)) node _dword_addr_matches_T_204 = and(_dword_addr_matches_T_202, _dword_addr_matches_T_203) node _dword_addr_matches_T_205 = bits(stq_addr[15].bits, 31, 3) node _dword_addr_matches_T_206 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_207 = eq(_dword_addr_matches_T_205, _dword_addr_matches_T_206) node dword_addr_matches_39 = and(_dword_addr_matches_T_204, _dword_addr_matches_T_207) node mask_union_15 = and(lcam_mask[0], write_mask_15) node _addr_matches_0_15_T = neq(mask_union_15, UInt<1>(0h0)) node _addr_matches_0_15_T_1 = and(_addr_matches_0_15_T, dword_addr_matches_39) connect addr_matches[0][15], _addr_matches_0_15_T_1 node _forward_matches_0_15_T = and(addr_matches[0][15], stq_data[15].valid) node _forward_matches_0_15_T_1 = eq(mask_union_15, lcam_mask[0]) node _forward_matches_0_15_T_2 = and(_forward_matches_0_15_T, _forward_matches_0_15_T_1) connect forward_matches[0][15], _forward_matches_0_15_T_2 node _prs2_matches_0_15_T = eq(s_uop_18.prs2, lcam_uop[0].pdst) node _prs2_matches_0_15_T_1 = eq(s_uop_18.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_15_T_2 = and(_prs2_matches_0_15_T, _prs2_matches_0_15_T_1) node _prs2_matches_0_15_T_3 = and(_prs2_matches_0_15_T_2, UInt<1>(0h1)) connect prs2_matches[0][15], _prs2_matches_0_15_T_3 wire s_uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_19, stq_uop[16] wire write_mask_16 : UInt<8> node _write_mask_mask_T_240 = eq(s_uop_19.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_241 = bits(stq_addr[16].bits, 2, 0) node _write_mask_mask_T_242 = dshl(UInt<8>(0h1), _write_mask_mask_T_241) node _write_mask_mask_T_243 = eq(s_uop_19.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_244 = bits(stq_addr[16].bits, 2, 1) node _write_mask_mask_T_245 = dshl(_write_mask_mask_T_244, UInt<1>(0h1)) node _write_mask_mask_T_246 = dshl(UInt<8>(0h3), _write_mask_mask_T_245) node _write_mask_mask_T_247 = eq(s_uop_19.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_248 = bits(stq_addr[16].bits, 2, 2) node _write_mask_mask_T_249 = mux(_write_mask_mask_T_248, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_250 = eq(s_uop_19.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_251 = mux(_write_mask_mask_T_250, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_252 = mux(_write_mask_mask_T_247, _write_mask_mask_T_249, _write_mask_mask_T_251) node _write_mask_mask_T_253 = mux(_write_mask_mask_T_243, _write_mask_mask_T_246, _write_mask_mask_T_252) node _write_mask_mask_T_254 = mux(_write_mask_mask_T_240, _write_mask_mask_T_242, _write_mask_mask_T_253) connect write_mask_16, _write_mask_mask_T_254 node _dword_addr_matches_T_208 = eq(s_uop_19.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_209 = and(stq_addr[16].valid, _dword_addr_matches_T_208) node _dword_addr_matches_T_210 = eq(stq_addr_is_virtual[16], UInt<1>(0h0)) node _dword_addr_matches_T_211 = and(_dword_addr_matches_T_209, _dword_addr_matches_T_210) node _dword_addr_matches_T_212 = bits(stq_addr[16].bits, 31, 3) node _dword_addr_matches_T_213 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_214 = eq(_dword_addr_matches_T_212, _dword_addr_matches_T_213) node dword_addr_matches_40 = and(_dword_addr_matches_T_211, _dword_addr_matches_T_214) node mask_union_16 = and(lcam_mask[0], write_mask_16) node _addr_matches_0_16_T = neq(mask_union_16, UInt<1>(0h0)) node _addr_matches_0_16_T_1 = and(_addr_matches_0_16_T, dword_addr_matches_40) connect addr_matches[0][16], _addr_matches_0_16_T_1 node _forward_matches_0_16_T = and(addr_matches[0][16], stq_data[16].valid) node _forward_matches_0_16_T_1 = eq(mask_union_16, lcam_mask[0]) node _forward_matches_0_16_T_2 = and(_forward_matches_0_16_T, _forward_matches_0_16_T_1) connect forward_matches[0][16], _forward_matches_0_16_T_2 node _prs2_matches_0_16_T = eq(s_uop_19.prs2, lcam_uop[0].pdst) node _prs2_matches_0_16_T_1 = eq(s_uop_19.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_16_T_2 = and(_prs2_matches_0_16_T, _prs2_matches_0_16_T_1) node _prs2_matches_0_16_T_3 = and(_prs2_matches_0_16_T_2, UInt<1>(0h1)) connect prs2_matches[0][16], _prs2_matches_0_16_T_3 wire s_uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_20, stq_uop[17] wire write_mask_17 : UInt<8> node _write_mask_mask_T_255 = eq(s_uop_20.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_256 = bits(stq_addr[17].bits, 2, 0) node _write_mask_mask_T_257 = dshl(UInt<8>(0h1), _write_mask_mask_T_256) node _write_mask_mask_T_258 = eq(s_uop_20.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_259 = bits(stq_addr[17].bits, 2, 1) node _write_mask_mask_T_260 = dshl(_write_mask_mask_T_259, UInt<1>(0h1)) node _write_mask_mask_T_261 = dshl(UInt<8>(0h3), _write_mask_mask_T_260) node _write_mask_mask_T_262 = eq(s_uop_20.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_263 = bits(stq_addr[17].bits, 2, 2) node _write_mask_mask_T_264 = mux(_write_mask_mask_T_263, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_265 = eq(s_uop_20.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_266 = mux(_write_mask_mask_T_265, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_267 = mux(_write_mask_mask_T_262, _write_mask_mask_T_264, _write_mask_mask_T_266) node _write_mask_mask_T_268 = mux(_write_mask_mask_T_258, _write_mask_mask_T_261, _write_mask_mask_T_267) node _write_mask_mask_T_269 = mux(_write_mask_mask_T_255, _write_mask_mask_T_257, _write_mask_mask_T_268) connect write_mask_17, _write_mask_mask_T_269 node _dword_addr_matches_T_215 = eq(s_uop_20.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_216 = and(stq_addr[17].valid, _dword_addr_matches_T_215) node _dword_addr_matches_T_217 = eq(stq_addr_is_virtual[17], UInt<1>(0h0)) node _dword_addr_matches_T_218 = and(_dword_addr_matches_T_216, _dword_addr_matches_T_217) node _dword_addr_matches_T_219 = bits(stq_addr[17].bits, 31, 3) node _dword_addr_matches_T_220 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_221 = eq(_dword_addr_matches_T_219, _dword_addr_matches_T_220) node dword_addr_matches_41 = and(_dword_addr_matches_T_218, _dword_addr_matches_T_221) node mask_union_17 = and(lcam_mask[0], write_mask_17) node _addr_matches_0_17_T = neq(mask_union_17, UInt<1>(0h0)) node _addr_matches_0_17_T_1 = and(_addr_matches_0_17_T, dword_addr_matches_41) connect addr_matches[0][17], _addr_matches_0_17_T_1 node _forward_matches_0_17_T = and(addr_matches[0][17], stq_data[17].valid) node _forward_matches_0_17_T_1 = eq(mask_union_17, lcam_mask[0]) node _forward_matches_0_17_T_2 = and(_forward_matches_0_17_T, _forward_matches_0_17_T_1) connect forward_matches[0][17], _forward_matches_0_17_T_2 node _prs2_matches_0_17_T = eq(s_uop_20.prs2, lcam_uop[0].pdst) node _prs2_matches_0_17_T_1 = eq(s_uop_20.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_17_T_2 = and(_prs2_matches_0_17_T, _prs2_matches_0_17_T_1) node _prs2_matches_0_17_T_3 = and(_prs2_matches_0_17_T_2, UInt<1>(0h1)) connect prs2_matches[0][17], _prs2_matches_0_17_T_3 wire s_uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_21, stq_uop[18] wire write_mask_18 : UInt<8> node _write_mask_mask_T_270 = eq(s_uop_21.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_271 = bits(stq_addr[18].bits, 2, 0) node _write_mask_mask_T_272 = dshl(UInt<8>(0h1), _write_mask_mask_T_271) node _write_mask_mask_T_273 = eq(s_uop_21.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_274 = bits(stq_addr[18].bits, 2, 1) node _write_mask_mask_T_275 = dshl(_write_mask_mask_T_274, UInt<1>(0h1)) node _write_mask_mask_T_276 = dshl(UInt<8>(0h3), _write_mask_mask_T_275) node _write_mask_mask_T_277 = eq(s_uop_21.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_278 = bits(stq_addr[18].bits, 2, 2) node _write_mask_mask_T_279 = mux(_write_mask_mask_T_278, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_280 = eq(s_uop_21.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_281 = mux(_write_mask_mask_T_280, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_282 = mux(_write_mask_mask_T_277, _write_mask_mask_T_279, _write_mask_mask_T_281) node _write_mask_mask_T_283 = mux(_write_mask_mask_T_273, _write_mask_mask_T_276, _write_mask_mask_T_282) node _write_mask_mask_T_284 = mux(_write_mask_mask_T_270, _write_mask_mask_T_272, _write_mask_mask_T_283) connect write_mask_18, _write_mask_mask_T_284 node _dword_addr_matches_T_222 = eq(s_uop_21.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_223 = and(stq_addr[18].valid, _dword_addr_matches_T_222) node _dword_addr_matches_T_224 = eq(stq_addr_is_virtual[18], UInt<1>(0h0)) node _dword_addr_matches_T_225 = and(_dword_addr_matches_T_223, _dword_addr_matches_T_224) node _dword_addr_matches_T_226 = bits(stq_addr[18].bits, 31, 3) node _dword_addr_matches_T_227 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_228 = eq(_dword_addr_matches_T_226, _dword_addr_matches_T_227) node dword_addr_matches_42 = and(_dword_addr_matches_T_225, _dword_addr_matches_T_228) node mask_union_18 = and(lcam_mask[0], write_mask_18) node _addr_matches_0_18_T = neq(mask_union_18, UInt<1>(0h0)) node _addr_matches_0_18_T_1 = and(_addr_matches_0_18_T, dword_addr_matches_42) connect addr_matches[0][18], _addr_matches_0_18_T_1 node _forward_matches_0_18_T = and(addr_matches[0][18], stq_data[18].valid) node _forward_matches_0_18_T_1 = eq(mask_union_18, lcam_mask[0]) node _forward_matches_0_18_T_2 = and(_forward_matches_0_18_T, _forward_matches_0_18_T_1) connect forward_matches[0][18], _forward_matches_0_18_T_2 node _prs2_matches_0_18_T = eq(s_uop_21.prs2, lcam_uop[0].pdst) node _prs2_matches_0_18_T_1 = eq(s_uop_21.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_18_T_2 = and(_prs2_matches_0_18_T, _prs2_matches_0_18_T_1) node _prs2_matches_0_18_T_3 = and(_prs2_matches_0_18_T_2, UInt<1>(0h1)) connect prs2_matches[0][18], _prs2_matches_0_18_T_3 wire s_uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_22, stq_uop[19] wire write_mask_19 : UInt<8> node _write_mask_mask_T_285 = eq(s_uop_22.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_286 = bits(stq_addr[19].bits, 2, 0) node _write_mask_mask_T_287 = dshl(UInt<8>(0h1), _write_mask_mask_T_286) node _write_mask_mask_T_288 = eq(s_uop_22.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_289 = bits(stq_addr[19].bits, 2, 1) node _write_mask_mask_T_290 = dshl(_write_mask_mask_T_289, UInt<1>(0h1)) node _write_mask_mask_T_291 = dshl(UInt<8>(0h3), _write_mask_mask_T_290) node _write_mask_mask_T_292 = eq(s_uop_22.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_293 = bits(stq_addr[19].bits, 2, 2) node _write_mask_mask_T_294 = mux(_write_mask_mask_T_293, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_295 = eq(s_uop_22.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_296 = mux(_write_mask_mask_T_295, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_297 = mux(_write_mask_mask_T_292, _write_mask_mask_T_294, _write_mask_mask_T_296) node _write_mask_mask_T_298 = mux(_write_mask_mask_T_288, _write_mask_mask_T_291, _write_mask_mask_T_297) node _write_mask_mask_T_299 = mux(_write_mask_mask_T_285, _write_mask_mask_T_287, _write_mask_mask_T_298) connect write_mask_19, _write_mask_mask_T_299 node _dword_addr_matches_T_229 = eq(s_uop_22.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_230 = and(stq_addr[19].valid, _dword_addr_matches_T_229) node _dword_addr_matches_T_231 = eq(stq_addr_is_virtual[19], UInt<1>(0h0)) node _dword_addr_matches_T_232 = and(_dword_addr_matches_T_230, _dword_addr_matches_T_231) node _dword_addr_matches_T_233 = bits(stq_addr[19].bits, 31, 3) node _dword_addr_matches_T_234 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_235 = eq(_dword_addr_matches_T_233, _dword_addr_matches_T_234) node dword_addr_matches_43 = and(_dword_addr_matches_T_232, _dword_addr_matches_T_235) node mask_union_19 = and(lcam_mask[0], write_mask_19) node _addr_matches_0_19_T = neq(mask_union_19, UInt<1>(0h0)) node _addr_matches_0_19_T_1 = and(_addr_matches_0_19_T, dword_addr_matches_43) connect addr_matches[0][19], _addr_matches_0_19_T_1 node _forward_matches_0_19_T = and(addr_matches[0][19], stq_data[19].valid) node _forward_matches_0_19_T_1 = eq(mask_union_19, lcam_mask[0]) node _forward_matches_0_19_T_2 = and(_forward_matches_0_19_T, _forward_matches_0_19_T_1) connect forward_matches[0][19], _forward_matches_0_19_T_2 node _prs2_matches_0_19_T = eq(s_uop_22.prs2, lcam_uop[0].pdst) node _prs2_matches_0_19_T_1 = eq(s_uop_22.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_19_T_2 = and(_prs2_matches_0_19_T, _prs2_matches_0_19_T_1) node _prs2_matches_0_19_T_3 = and(_prs2_matches_0_19_T_2, UInt<1>(0h1)) connect prs2_matches[0][19], _prs2_matches_0_19_T_3 wire s_uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_23, stq_uop[20] wire write_mask_20 : UInt<8> node _write_mask_mask_T_300 = eq(s_uop_23.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_301 = bits(stq_addr[20].bits, 2, 0) node _write_mask_mask_T_302 = dshl(UInt<8>(0h1), _write_mask_mask_T_301) node _write_mask_mask_T_303 = eq(s_uop_23.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_304 = bits(stq_addr[20].bits, 2, 1) node _write_mask_mask_T_305 = dshl(_write_mask_mask_T_304, UInt<1>(0h1)) node _write_mask_mask_T_306 = dshl(UInt<8>(0h3), _write_mask_mask_T_305) node _write_mask_mask_T_307 = eq(s_uop_23.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_308 = bits(stq_addr[20].bits, 2, 2) node _write_mask_mask_T_309 = mux(_write_mask_mask_T_308, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_310 = eq(s_uop_23.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_311 = mux(_write_mask_mask_T_310, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_312 = mux(_write_mask_mask_T_307, _write_mask_mask_T_309, _write_mask_mask_T_311) node _write_mask_mask_T_313 = mux(_write_mask_mask_T_303, _write_mask_mask_T_306, _write_mask_mask_T_312) node _write_mask_mask_T_314 = mux(_write_mask_mask_T_300, _write_mask_mask_T_302, _write_mask_mask_T_313) connect write_mask_20, _write_mask_mask_T_314 node _dword_addr_matches_T_236 = eq(s_uop_23.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_237 = and(stq_addr[20].valid, _dword_addr_matches_T_236) node _dword_addr_matches_T_238 = eq(stq_addr_is_virtual[20], UInt<1>(0h0)) node _dword_addr_matches_T_239 = and(_dword_addr_matches_T_237, _dword_addr_matches_T_238) node _dword_addr_matches_T_240 = bits(stq_addr[20].bits, 31, 3) node _dword_addr_matches_T_241 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_242 = eq(_dword_addr_matches_T_240, _dword_addr_matches_T_241) node dword_addr_matches_44 = and(_dword_addr_matches_T_239, _dword_addr_matches_T_242) node mask_union_20 = and(lcam_mask[0], write_mask_20) node _addr_matches_0_20_T = neq(mask_union_20, UInt<1>(0h0)) node _addr_matches_0_20_T_1 = and(_addr_matches_0_20_T, dword_addr_matches_44) connect addr_matches[0][20], _addr_matches_0_20_T_1 node _forward_matches_0_20_T = and(addr_matches[0][20], stq_data[20].valid) node _forward_matches_0_20_T_1 = eq(mask_union_20, lcam_mask[0]) node _forward_matches_0_20_T_2 = and(_forward_matches_0_20_T, _forward_matches_0_20_T_1) connect forward_matches[0][20], _forward_matches_0_20_T_2 node _prs2_matches_0_20_T = eq(s_uop_23.prs2, lcam_uop[0].pdst) node _prs2_matches_0_20_T_1 = eq(s_uop_23.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_20_T_2 = and(_prs2_matches_0_20_T, _prs2_matches_0_20_T_1) node _prs2_matches_0_20_T_3 = and(_prs2_matches_0_20_T_2, UInt<1>(0h1)) connect prs2_matches[0][20], _prs2_matches_0_20_T_3 wire s_uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_24, stq_uop[21] wire write_mask_21 : UInt<8> node _write_mask_mask_T_315 = eq(s_uop_24.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_316 = bits(stq_addr[21].bits, 2, 0) node _write_mask_mask_T_317 = dshl(UInt<8>(0h1), _write_mask_mask_T_316) node _write_mask_mask_T_318 = eq(s_uop_24.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_319 = bits(stq_addr[21].bits, 2, 1) node _write_mask_mask_T_320 = dshl(_write_mask_mask_T_319, UInt<1>(0h1)) node _write_mask_mask_T_321 = dshl(UInt<8>(0h3), _write_mask_mask_T_320) node _write_mask_mask_T_322 = eq(s_uop_24.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_323 = bits(stq_addr[21].bits, 2, 2) node _write_mask_mask_T_324 = mux(_write_mask_mask_T_323, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_325 = eq(s_uop_24.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_326 = mux(_write_mask_mask_T_325, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_327 = mux(_write_mask_mask_T_322, _write_mask_mask_T_324, _write_mask_mask_T_326) node _write_mask_mask_T_328 = mux(_write_mask_mask_T_318, _write_mask_mask_T_321, _write_mask_mask_T_327) node _write_mask_mask_T_329 = mux(_write_mask_mask_T_315, _write_mask_mask_T_317, _write_mask_mask_T_328) connect write_mask_21, _write_mask_mask_T_329 node _dword_addr_matches_T_243 = eq(s_uop_24.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_244 = and(stq_addr[21].valid, _dword_addr_matches_T_243) node _dword_addr_matches_T_245 = eq(stq_addr_is_virtual[21], UInt<1>(0h0)) node _dword_addr_matches_T_246 = and(_dword_addr_matches_T_244, _dword_addr_matches_T_245) node _dword_addr_matches_T_247 = bits(stq_addr[21].bits, 31, 3) node _dword_addr_matches_T_248 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_249 = eq(_dword_addr_matches_T_247, _dword_addr_matches_T_248) node dword_addr_matches_45 = and(_dword_addr_matches_T_246, _dword_addr_matches_T_249) node mask_union_21 = and(lcam_mask[0], write_mask_21) node _addr_matches_0_21_T = neq(mask_union_21, UInt<1>(0h0)) node _addr_matches_0_21_T_1 = and(_addr_matches_0_21_T, dword_addr_matches_45) connect addr_matches[0][21], _addr_matches_0_21_T_1 node _forward_matches_0_21_T = and(addr_matches[0][21], stq_data[21].valid) node _forward_matches_0_21_T_1 = eq(mask_union_21, lcam_mask[0]) node _forward_matches_0_21_T_2 = and(_forward_matches_0_21_T, _forward_matches_0_21_T_1) connect forward_matches[0][21], _forward_matches_0_21_T_2 node _prs2_matches_0_21_T = eq(s_uop_24.prs2, lcam_uop[0].pdst) node _prs2_matches_0_21_T_1 = eq(s_uop_24.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_21_T_2 = and(_prs2_matches_0_21_T, _prs2_matches_0_21_T_1) node _prs2_matches_0_21_T_3 = and(_prs2_matches_0_21_T_2, UInt<1>(0h1)) connect prs2_matches[0][21], _prs2_matches_0_21_T_3 wire s_uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_25, stq_uop[22] wire write_mask_22 : UInt<8> node _write_mask_mask_T_330 = eq(s_uop_25.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_331 = bits(stq_addr[22].bits, 2, 0) node _write_mask_mask_T_332 = dshl(UInt<8>(0h1), _write_mask_mask_T_331) node _write_mask_mask_T_333 = eq(s_uop_25.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_334 = bits(stq_addr[22].bits, 2, 1) node _write_mask_mask_T_335 = dshl(_write_mask_mask_T_334, UInt<1>(0h1)) node _write_mask_mask_T_336 = dshl(UInt<8>(0h3), _write_mask_mask_T_335) node _write_mask_mask_T_337 = eq(s_uop_25.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_338 = bits(stq_addr[22].bits, 2, 2) node _write_mask_mask_T_339 = mux(_write_mask_mask_T_338, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_340 = eq(s_uop_25.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_341 = mux(_write_mask_mask_T_340, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_342 = mux(_write_mask_mask_T_337, _write_mask_mask_T_339, _write_mask_mask_T_341) node _write_mask_mask_T_343 = mux(_write_mask_mask_T_333, _write_mask_mask_T_336, _write_mask_mask_T_342) node _write_mask_mask_T_344 = mux(_write_mask_mask_T_330, _write_mask_mask_T_332, _write_mask_mask_T_343) connect write_mask_22, _write_mask_mask_T_344 node _dword_addr_matches_T_250 = eq(s_uop_25.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_251 = and(stq_addr[22].valid, _dword_addr_matches_T_250) node _dword_addr_matches_T_252 = eq(stq_addr_is_virtual[22], UInt<1>(0h0)) node _dword_addr_matches_T_253 = and(_dword_addr_matches_T_251, _dword_addr_matches_T_252) node _dword_addr_matches_T_254 = bits(stq_addr[22].bits, 31, 3) node _dword_addr_matches_T_255 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_256 = eq(_dword_addr_matches_T_254, _dword_addr_matches_T_255) node dword_addr_matches_46 = and(_dword_addr_matches_T_253, _dword_addr_matches_T_256) node mask_union_22 = and(lcam_mask[0], write_mask_22) node _addr_matches_0_22_T = neq(mask_union_22, UInt<1>(0h0)) node _addr_matches_0_22_T_1 = and(_addr_matches_0_22_T, dword_addr_matches_46) connect addr_matches[0][22], _addr_matches_0_22_T_1 node _forward_matches_0_22_T = and(addr_matches[0][22], stq_data[22].valid) node _forward_matches_0_22_T_1 = eq(mask_union_22, lcam_mask[0]) node _forward_matches_0_22_T_2 = and(_forward_matches_0_22_T, _forward_matches_0_22_T_1) connect forward_matches[0][22], _forward_matches_0_22_T_2 node _prs2_matches_0_22_T = eq(s_uop_25.prs2, lcam_uop[0].pdst) node _prs2_matches_0_22_T_1 = eq(s_uop_25.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_22_T_2 = and(_prs2_matches_0_22_T, _prs2_matches_0_22_T_1) node _prs2_matches_0_22_T_3 = and(_prs2_matches_0_22_T_2, UInt<1>(0h1)) connect prs2_matches[0][22], _prs2_matches_0_22_T_3 wire s_uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_26, stq_uop[23] wire write_mask_23 : UInt<8> node _write_mask_mask_T_345 = eq(s_uop_26.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_346 = bits(stq_addr[23].bits, 2, 0) node _write_mask_mask_T_347 = dshl(UInt<8>(0h1), _write_mask_mask_T_346) node _write_mask_mask_T_348 = eq(s_uop_26.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_349 = bits(stq_addr[23].bits, 2, 1) node _write_mask_mask_T_350 = dshl(_write_mask_mask_T_349, UInt<1>(0h1)) node _write_mask_mask_T_351 = dshl(UInt<8>(0h3), _write_mask_mask_T_350) node _write_mask_mask_T_352 = eq(s_uop_26.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_353 = bits(stq_addr[23].bits, 2, 2) node _write_mask_mask_T_354 = mux(_write_mask_mask_T_353, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_355 = eq(s_uop_26.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_356 = mux(_write_mask_mask_T_355, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_357 = mux(_write_mask_mask_T_352, _write_mask_mask_T_354, _write_mask_mask_T_356) node _write_mask_mask_T_358 = mux(_write_mask_mask_T_348, _write_mask_mask_T_351, _write_mask_mask_T_357) node _write_mask_mask_T_359 = mux(_write_mask_mask_T_345, _write_mask_mask_T_347, _write_mask_mask_T_358) connect write_mask_23, _write_mask_mask_T_359 node _dword_addr_matches_T_257 = eq(s_uop_26.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_258 = and(stq_addr[23].valid, _dword_addr_matches_T_257) node _dword_addr_matches_T_259 = eq(stq_addr_is_virtual[23], UInt<1>(0h0)) node _dword_addr_matches_T_260 = and(_dword_addr_matches_T_258, _dword_addr_matches_T_259) node _dword_addr_matches_T_261 = bits(stq_addr[23].bits, 31, 3) node _dword_addr_matches_T_262 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_263 = eq(_dword_addr_matches_T_261, _dword_addr_matches_T_262) node dword_addr_matches_47 = and(_dword_addr_matches_T_260, _dword_addr_matches_T_263) node mask_union_23 = and(lcam_mask[0], write_mask_23) node _addr_matches_0_23_T = neq(mask_union_23, UInt<1>(0h0)) node _addr_matches_0_23_T_1 = and(_addr_matches_0_23_T, dword_addr_matches_47) connect addr_matches[0][23], _addr_matches_0_23_T_1 node _forward_matches_0_23_T = and(addr_matches[0][23], stq_data[23].valid) node _forward_matches_0_23_T_1 = eq(mask_union_23, lcam_mask[0]) node _forward_matches_0_23_T_2 = and(_forward_matches_0_23_T, _forward_matches_0_23_T_1) connect forward_matches[0][23], _forward_matches_0_23_T_2 node _prs2_matches_0_23_T = eq(s_uop_26.prs2, lcam_uop[0].pdst) node _prs2_matches_0_23_T_1 = eq(s_uop_26.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_23_T_2 = and(_prs2_matches_0_23_T, _prs2_matches_0_23_T_1) node _prs2_matches_0_23_T_3 = and(_prs2_matches_0_23_T_2, UInt<1>(0h1)) connect prs2_matches[0][23], _prs2_matches_0_23_T_3 node fast_stq_valids_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node fast_stq_valids_lo_lo_lo = cat(fast_stq_valids_lo_lo_lo_hi, stq_valid[0]) node fast_stq_valids_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node fast_stq_valids_lo_lo_hi = cat(fast_stq_valids_lo_lo_hi_hi, stq_valid[3]) node fast_stq_valids_lo_lo = cat(fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo) node fast_stq_valids_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node fast_stq_valids_lo_hi_lo = cat(fast_stq_valids_lo_hi_lo_hi, stq_valid[6]) node fast_stq_valids_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node fast_stq_valids_lo_hi_hi = cat(fast_stq_valids_lo_hi_hi_hi, stq_valid[9]) node fast_stq_valids_lo_hi = cat(fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo) node fast_stq_valids_lo = cat(fast_stq_valids_lo_hi, fast_stq_valids_lo_lo) node fast_stq_valids_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node fast_stq_valids_hi_lo_lo = cat(fast_stq_valids_hi_lo_lo_hi, stq_valid[12]) node fast_stq_valids_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node fast_stq_valids_hi_lo_hi = cat(fast_stq_valids_hi_lo_hi_hi, stq_valid[15]) node fast_stq_valids_hi_lo = cat(fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo) node fast_stq_valids_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node fast_stq_valids_hi_hi_lo = cat(fast_stq_valids_hi_hi_lo_hi, stq_valid[18]) node fast_stq_valids_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node fast_stq_valids_hi_hi_hi = cat(fast_stq_valids_hi_hi_hi_hi, stq_valid[21]) node fast_stq_valids_hi_hi = cat(fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo) node fast_stq_valids_hi = cat(fast_stq_valids_hi_hi, fast_stq_valids_hi_lo) node fast_stq_valids = cat(fast_stq_valids_hi, fast_stq_valids_lo) node ldst_addr_matches_0_lo_lo_lo_hi = cat(addr_matches[0][2], addr_matches[0][1]) node ldst_addr_matches_0_lo_lo_lo = cat(ldst_addr_matches_0_lo_lo_lo_hi, addr_matches[0][0]) node ldst_addr_matches_0_lo_lo_hi_hi = cat(addr_matches[0][5], addr_matches[0][4]) node ldst_addr_matches_0_lo_lo_hi = cat(ldst_addr_matches_0_lo_lo_hi_hi, addr_matches[0][3]) node ldst_addr_matches_0_lo_lo = cat(ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo) node ldst_addr_matches_0_lo_hi_lo_hi = cat(addr_matches[0][8], addr_matches[0][7]) node ldst_addr_matches_0_lo_hi_lo = cat(ldst_addr_matches_0_lo_hi_lo_hi, addr_matches[0][6]) node ldst_addr_matches_0_lo_hi_hi_hi = cat(addr_matches[0][11], addr_matches[0][10]) node ldst_addr_matches_0_lo_hi_hi = cat(ldst_addr_matches_0_lo_hi_hi_hi, addr_matches[0][9]) node ldst_addr_matches_0_lo_hi = cat(ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo) node ldst_addr_matches_0_lo = cat(ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo) node ldst_addr_matches_0_hi_lo_lo_hi = cat(addr_matches[0][14], addr_matches[0][13]) node ldst_addr_matches_0_hi_lo_lo = cat(ldst_addr_matches_0_hi_lo_lo_hi, addr_matches[0][12]) node ldst_addr_matches_0_hi_lo_hi_hi = cat(addr_matches[0][17], addr_matches[0][16]) node ldst_addr_matches_0_hi_lo_hi = cat(ldst_addr_matches_0_hi_lo_hi_hi, addr_matches[0][15]) node ldst_addr_matches_0_hi_lo = cat(ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo) node ldst_addr_matches_0_hi_hi_lo_hi = cat(addr_matches[0][20], addr_matches[0][19]) node ldst_addr_matches_0_hi_hi_lo = cat(ldst_addr_matches_0_hi_hi_lo_hi, addr_matches[0][18]) node ldst_addr_matches_0_hi_hi_hi_hi = cat(addr_matches[0][23], addr_matches[0][22]) node ldst_addr_matches_0_hi_hi_hi = cat(ldst_addr_matches_0_hi_hi_hi_hi, addr_matches[0][21]) node ldst_addr_matches_0_hi_hi = cat(ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo) node ldst_addr_matches_0_hi = cat(ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo) node _ldst_addr_matches_0_T = cat(ldst_addr_matches_0_hi, ldst_addr_matches_0_lo) node _ldst_addr_matches_0_T_1 = and(_ldst_addr_matches_0_T, lcam_st_dep_mask[0]) node _ldst_addr_matches_0_T_2 = and(_ldst_addr_matches_0_T_1, fast_stq_valids) connect ldst_addr_matches[0], _ldst_addr_matches_0_T_2 node ldst_forward_matches_0_lo_lo_lo_hi = cat(forward_matches[0][2], forward_matches[0][1]) node ldst_forward_matches_0_lo_lo_lo = cat(ldst_forward_matches_0_lo_lo_lo_hi, forward_matches[0][0]) node ldst_forward_matches_0_lo_lo_hi_hi = cat(forward_matches[0][5], forward_matches[0][4]) node ldst_forward_matches_0_lo_lo_hi = cat(ldst_forward_matches_0_lo_lo_hi_hi, forward_matches[0][3]) node ldst_forward_matches_0_lo_lo = cat(ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo) node ldst_forward_matches_0_lo_hi_lo_hi = cat(forward_matches[0][8], forward_matches[0][7]) node ldst_forward_matches_0_lo_hi_lo = cat(ldst_forward_matches_0_lo_hi_lo_hi, forward_matches[0][6]) node ldst_forward_matches_0_lo_hi_hi_hi = cat(forward_matches[0][11], forward_matches[0][10]) node ldst_forward_matches_0_lo_hi_hi = cat(ldst_forward_matches_0_lo_hi_hi_hi, forward_matches[0][9]) node ldst_forward_matches_0_lo_hi = cat(ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo) node ldst_forward_matches_0_lo = cat(ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo) node ldst_forward_matches_0_hi_lo_lo_hi = cat(forward_matches[0][14], forward_matches[0][13]) node ldst_forward_matches_0_hi_lo_lo = cat(ldst_forward_matches_0_hi_lo_lo_hi, forward_matches[0][12]) node ldst_forward_matches_0_hi_lo_hi_hi = cat(forward_matches[0][17], forward_matches[0][16]) node ldst_forward_matches_0_hi_lo_hi = cat(ldst_forward_matches_0_hi_lo_hi_hi, forward_matches[0][15]) node ldst_forward_matches_0_hi_lo = cat(ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo) node ldst_forward_matches_0_hi_hi_lo_hi = cat(forward_matches[0][20], forward_matches[0][19]) node ldst_forward_matches_0_hi_hi_lo = cat(ldst_forward_matches_0_hi_hi_lo_hi, forward_matches[0][18]) node ldst_forward_matches_0_hi_hi_hi_hi = cat(forward_matches[0][23], forward_matches[0][22]) node ldst_forward_matches_0_hi_hi_hi = cat(ldst_forward_matches_0_hi_hi_hi_hi, forward_matches[0][21]) node ldst_forward_matches_0_hi_hi = cat(ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo) node ldst_forward_matches_0_hi = cat(ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo) node _ldst_forward_matches_0_T = cat(ldst_forward_matches_0_hi, ldst_forward_matches_0_lo) node _ldst_forward_matches_0_T_1 = and(_ldst_forward_matches_0_T, lcam_st_dep_mask[0]) node _ldst_forward_matches_0_T_2 = and(_ldst_forward_matches_0_T_1, fast_stq_valids) connect ldst_forward_matches[0], _ldst_forward_matches_0_T_2 node stld_prs2_matches_0_lo_lo_lo_hi = cat(prs2_matches[0][2], prs2_matches[0][1]) node stld_prs2_matches_0_lo_lo_lo = cat(stld_prs2_matches_0_lo_lo_lo_hi, prs2_matches[0][0]) node stld_prs2_matches_0_lo_lo_hi_hi = cat(prs2_matches[0][5], prs2_matches[0][4]) node stld_prs2_matches_0_lo_lo_hi = cat(stld_prs2_matches_0_lo_lo_hi_hi, prs2_matches[0][3]) node stld_prs2_matches_0_lo_lo = cat(stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo) node stld_prs2_matches_0_lo_hi_lo_hi = cat(prs2_matches[0][8], prs2_matches[0][7]) node stld_prs2_matches_0_lo_hi_lo = cat(stld_prs2_matches_0_lo_hi_lo_hi, prs2_matches[0][6]) node stld_prs2_matches_0_lo_hi_hi_hi = cat(prs2_matches[0][11], prs2_matches[0][10]) node stld_prs2_matches_0_lo_hi_hi = cat(stld_prs2_matches_0_lo_hi_hi_hi, prs2_matches[0][9]) node stld_prs2_matches_0_lo_hi = cat(stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo) node stld_prs2_matches_0_lo = cat(stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo) node stld_prs2_matches_0_hi_lo_lo_hi = cat(prs2_matches[0][14], prs2_matches[0][13]) node stld_prs2_matches_0_hi_lo_lo = cat(stld_prs2_matches_0_hi_lo_lo_hi, prs2_matches[0][12]) node stld_prs2_matches_0_hi_lo_hi_hi = cat(prs2_matches[0][17], prs2_matches[0][16]) node stld_prs2_matches_0_hi_lo_hi = cat(stld_prs2_matches_0_hi_lo_hi_hi, prs2_matches[0][15]) node stld_prs2_matches_0_hi_lo = cat(stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo) node stld_prs2_matches_0_hi_hi_lo_hi = cat(prs2_matches[0][20], prs2_matches[0][19]) node stld_prs2_matches_0_hi_hi_lo = cat(stld_prs2_matches_0_hi_hi_lo_hi, prs2_matches[0][18]) node stld_prs2_matches_0_hi_hi_hi_hi = cat(prs2_matches[0][23], prs2_matches[0][22]) node stld_prs2_matches_0_hi_hi_hi = cat(stld_prs2_matches_0_hi_hi_hi_hi, prs2_matches[0][21]) node stld_prs2_matches_0_hi_hi = cat(stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo) node stld_prs2_matches_0_hi = cat(stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo) node _stld_prs2_matches_0_T = cat(stld_prs2_matches_0_hi, stld_prs2_matches_0_lo) node _stld_prs2_matches_0_T_1 = not(lcam_st_dep_mask[0]) node _stld_prs2_matches_0_T_2 = and(_stld_prs2_matches_0_T, _stld_prs2_matches_0_T_1) node _stld_prs2_matches_0_T_3 = and(_stld_prs2_matches_0_T_2, fast_stq_valids) connect stld_prs2_matches[0], _stld_prs2_matches_0_T_3 node _stq_amos_T = or(stq_uop[0].is_fence, stq_uop[0].is_amo) node _stq_amos_T_1 = or(stq_uop[1].is_fence, stq_uop[1].is_amo) node _stq_amos_T_2 = or(stq_uop[2].is_fence, stq_uop[2].is_amo) node _stq_amos_T_3 = or(stq_uop[3].is_fence, stq_uop[3].is_amo) node _stq_amos_T_4 = or(stq_uop[4].is_fence, stq_uop[4].is_amo) node _stq_amos_T_5 = or(stq_uop[5].is_fence, stq_uop[5].is_amo) node _stq_amos_T_6 = or(stq_uop[6].is_fence, stq_uop[6].is_amo) node _stq_amos_T_7 = or(stq_uop[7].is_fence, stq_uop[7].is_amo) node _stq_amos_T_8 = or(stq_uop[8].is_fence, stq_uop[8].is_amo) node _stq_amos_T_9 = or(stq_uop[9].is_fence, stq_uop[9].is_amo) node _stq_amos_T_10 = or(stq_uop[10].is_fence, stq_uop[10].is_amo) node _stq_amos_T_11 = or(stq_uop[11].is_fence, stq_uop[11].is_amo) node _stq_amos_T_12 = or(stq_uop[12].is_fence, stq_uop[12].is_amo) node _stq_amos_T_13 = or(stq_uop[13].is_fence, stq_uop[13].is_amo) node _stq_amos_T_14 = or(stq_uop[14].is_fence, stq_uop[14].is_amo) node _stq_amos_T_15 = or(stq_uop[15].is_fence, stq_uop[15].is_amo) node _stq_amos_T_16 = or(stq_uop[16].is_fence, stq_uop[16].is_amo) node _stq_amos_T_17 = or(stq_uop[17].is_fence, stq_uop[17].is_amo) node _stq_amos_T_18 = or(stq_uop[18].is_fence, stq_uop[18].is_amo) node _stq_amos_T_19 = or(stq_uop[19].is_fence, stq_uop[19].is_amo) node _stq_amos_T_20 = or(stq_uop[20].is_fence, stq_uop[20].is_amo) node _stq_amos_T_21 = or(stq_uop[21].is_fence, stq_uop[21].is_amo) node _stq_amos_T_22 = or(stq_uop[22].is_fence, stq_uop[22].is_amo) node _stq_amos_T_23 = or(stq_uop[23].is_fence, stq_uop[23].is_amo) wire stq_amos : UInt<1>[24] connect stq_amos[0], _stq_amos_T connect stq_amos[1], _stq_amos_T_1 connect stq_amos[2], _stq_amos_T_2 connect stq_amos[3], _stq_amos_T_3 connect stq_amos[4], _stq_amos_T_4 connect stq_amos[5], _stq_amos_T_5 connect stq_amos[6], _stq_amos_T_6 connect stq_amos[7], _stq_amos_T_7 connect stq_amos[8], _stq_amos_T_8 connect stq_amos[9], _stq_amos_T_9 connect stq_amos[10], _stq_amos_T_10 connect stq_amos[11], _stq_amos_T_11 connect stq_amos[12], _stq_amos_T_12 connect stq_amos[13], _stq_amos_T_13 connect stq_amos[14], _stq_amos_T_14 connect stq_amos[15], _stq_amos_T_15 connect stq_amos[16], _stq_amos_T_16 connect stq_amos[17], _stq_amos_T_17 connect stq_amos[18], _stq_amos_T_18 connect stq_amos[19], _stq_amos_T_19 connect stq_amos[20], _stq_amos_T_20 connect stq_amos[21], _stq_amos_T_21 connect stq_amos[22], _stq_amos_T_22 connect stq_amos[23], _stq_amos_T_23 node has_older_amo_lo_lo_lo_hi = cat(stq_amos[2], stq_amos[1]) node has_older_amo_lo_lo_lo = cat(has_older_amo_lo_lo_lo_hi, stq_amos[0]) node has_older_amo_lo_lo_hi_hi = cat(stq_amos[5], stq_amos[4]) node has_older_amo_lo_lo_hi = cat(has_older_amo_lo_lo_hi_hi, stq_amos[3]) node has_older_amo_lo_lo = cat(has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo) node has_older_amo_lo_hi_lo_hi = cat(stq_amos[8], stq_amos[7]) node has_older_amo_lo_hi_lo = cat(has_older_amo_lo_hi_lo_hi, stq_amos[6]) node has_older_amo_lo_hi_hi_hi = cat(stq_amos[11], stq_amos[10]) node has_older_amo_lo_hi_hi = cat(has_older_amo_lo_hi_hi_hi, stq_amos[9]) node has_older_amo_lo_hi = cat(has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo) node has_older_amo_lo = cat(has_older_amo_lo_hi, has_older_amo_lo_lo) node has_older_amo_hi_lo_lo_hi = cat(stq_amos[14], stq_amos[13]) node has_older_amo_hi_lo_lo = cat(has_older_amo_hi_lo_lo_hi, stq_amos[12]) node has_older_amo_hi_lo_hi_hi = cat(stq_amos[17], stq_amos[16]) node has_older_amo_hi_lo_hi = cat(has_older_amo_hi_lo_hi_hi, stq_amos[15]) node has_older_amo_hi_lo = cat(has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo) node has_older_amo_hi_hi_lo_hi = cat(stq_amos[20], stq_amos[19]) node has_older_amo_hi_hi_lo = cat(has_older_amo_hi_hi_lo_hi, stq_amos[18]) node has_older_amo_hi_hi_hi_hi = cat(stq_amos[23], stq_amos[22]) node has_older_amo_hi_hi_hi = cat(has_older_amo_hi_hi_hi_hi, stq_amos[21]) node has_older_amo_hi_hi = cat(has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo) node has_older_amo_hi = cat(has_older_amo_hi_hi, has_older_amo_hi_lo) node _has_older_amo_T = cat(has_older_amo_hi, has_older_amo_lo) node _has_older_amo_T_1 = and(_has_older_amo_T, lcam_st_dep_mask[0]) node has_older_amo = neq(_has_older_amo_T_1, UInt<1>(0h0)) node _T_1624 = neq(ldst_addr_matches[0], UInt<1>(0h0)) node _T_1625 = or(has_older_amo, _T_1624) node _T_1626 = and(do_ld_search[0], _T_1625) when _T_1626 : node _T_1627 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1628 = and(dmem_req_fire[0], _T_1627) reg REG_26 : UInt<1>, clock connect REG_26, _T_1628 node _T_1629 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1630 = and(REG_26, _T_1629) when _T_1630 : connect io.dmem.s1_kill[0], UInt<1>(0h1) node _T_1631 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1632 = bits(_T_1631, 4, 0) connect s1_set_execute[_T_1632], UInt<1>(0h0) when has_older_amo : connect kill_forward[0], UInt<1>(0h1) when s1_set_execute[0] : connect ldq_executed[0], UInt<1>(0h1) when s1_set_execute[1] : connect ldq_executed[1], UInt<1>(0h1) when s1_set_execute[2] : connect ldq_executed[2], UInt<1>(0h1) when s1_set_execute[3] : connect ldq_executed[3], UInt<1>(0h1) when s1_set_execute[4] : connect ldq_executed[4], UInt<1>(0h1) when s1_set_execute[5] : connect ldq_executed[5], UInt<1>(0h1) when s1_set_execute[6] : connect ldq_executed[6], UInt<1>(0h1) when s1_set_execute[7] : connect ldq_executed[7], UInt<1>(0h1) when s1_set_execute[8] : connect ldq_executed[8], UInt<1>(0h1) when s1_set_execute[9] : connect ldq_executed[9], UInt<1>(0h1) when s1_set_execute[10] : connect ldq_executed[10], UInt<1>(0h1) when s1_set_execute[11] : connect ldq_executed[11], UInt<1>(0h1) when s1_set_execute[12] : connect ldq_executed[12], UInt<1>(0h1) when s1_set_execute[13] : connect ldq_executed[13], UInt<1>(0h1) when s1_set_execute[14] : connect ldq_executed[14], UInt<1>(0h1) when s1_set_execute[15] : connect ldq_executed[15], UInt<1>(0h1) when s1_set_execute[16] : connect ldq_executed[16], UInt<1>(0h1) when s1_set_execute[17] : connect ldq_executed[17], UInt<1>(0h1) when s1_set_execute[18] : connect ldq_executed[18], UInt<1>(0h1) when s1_set_execute[19] : connect ldq_executed[19], UInt<1>(0h1) when s1_set_execute[20] : connect ldq_executed[20], UInt<1>(0h1) when s1_set_execute[21] : connect ldq_executed[21], UInt<1>(0h1) when s1_set_execute[22] : connect ldq_executed[22], UInt<1>(0h1) when s1_set_execute[23] : connect ldq_executed[23], UInt<1>(0h1) inst logic of ForwardingAgeLogic connect logic.clock, clock connect logic.reset, reset connect logic.io.matches, ldst_addr_matches[0] connect logic.io.youngest, lcam_uop[0].stq_idx inst logic_1 of ForwardingAgeLogic_1 connect logic_1.clock, clock connect logic_1.reset, reset connect logic_1.io.matches, ldst_forward_matches[0] connect logic_1.io.youngest, lcam_uop[0].stq_idx connect wb_ldst_forward_stq_idx[0], logic_1.io.found_idx node _wb_ldst_forward_valid_0_T = eq(logic.io.found_idx, logic_1.io.found_idx) node _wb_ldst_forward_valid_0_T_1 = and(_wb_ldst_forward_valid_0_T, logic.io.found) node _wb_ldst_forward_valid_0_T_2 = and(_wb_ldst_forward_valid_0_T_1, logic_1.io.found) node _wb_ldst_forward_valid_0_T_3 = eq(kill_forward[0], UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_4 = and(can_forward[0], _wb_ldst_forward_valid_0_T_3) node _wb_ldst_forward_valid_0_T_5 = and(_wb_ldst_forward_valid_0_T_4, do_ld_search[0]) reg wb_ldst_forward_valid_0_REG : UInt<1>, clock connect wb_ldst_forward_valid_0_REG, _wb_ldst_forward_valid_0_T_5 node _wb_ldst_forward_valid_0_T_6 = and(_wb_ldst_forward_valid_0_T_2, wb_ldst_forward_valid_0_REG) node _wb_ldst_forward_valid_0_T_7 = and(io.core.brupdate.b1.mispredict_mask, lcam_uop[0].br_mask) node _wb_ldst_forward_valid_0_T_8 = neq(_wb_ldst_forward_valid_0_T_7, UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_9 = or(_wb_ldst_forward_valid_0_T_8, io.core.exception) reg wb_ldst_forward_valid_0_REG_1 : UInt<1>, clock connect wb_ldst_forward_valid_0_REG_1, _wb_ldst_forward_valid_0_T_9 node _wb_ldst_forward_valid_0_T_10 = eq(wb_ldst_forward_valid_0_REG_1, UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_11 = and(_wb_ldst_forward_valid_0_T_6, _wb_ldst_forward_valid_0_T_10) connect wb_ldst_forward_valid[0], _wb_ldst_forward_valid_0_T_11 node _T_1633 = neq(ldst_addr_matches[0], UInt<1>(0h0)) reg REG_27 : UInt<1>, clock connect REG_27, _T_1633 node _T_1634 = eq(wb_ldst_forward_valid[0], UInt<1>(0h0)) node _T_1635 = and(REG_27, _T_1634) when _T_1635 : connect block_load_wakeup, UInt<1>(0h1) reg store_blocked_counter : UInt<4>, clock node _T_1636 = or(will_fire_store_commit_fast[0], will_fire_store_commit_slow[0]) node _T_1637 = eq(can_fire_store_commit_slow[0], UInt<1>(0h0)) node _T_1638 = or(_T_1636, _T_1637) when _T_1638 : connect store_blocked_counter, UInt<1>(0h0) else : node _T_1639 = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) node _T_1641 = and(can_fire_store_commit_slow[0], _T_1640) when _T_1641 : node _store_blocked_counter_T = eq(store_blocked_counter, UInt<4>(0hf)) node _store_blocked_counter_T_1 = add(store_blocked_counter, UInt<1>(0h1)) node _store_blocked_counter_T_2 = tail(_store_blocked_counter_T_1, 1) node _store_blocked_counter_T_3 = mux(_store_blocked_counter_T, UInt<4>(0hf), _store_blocked_counter_T_2) connect store_blocked_counter, _store_blocked_counter_T_3 node _T_1642 = eq(store_blocked_counter, UInt<4>(0hf)) when _T_1642 : connect block_load_wakeup, UInt<1>(0h1) node _mem_stld_forward_stq_idx_T = bits(stld_prs2_matches[0], 0, 0) node _mem_stld_forward_stq_idx_T_1 = bits(stld_prs2_matches[0], 1, 1) node _mem_stld_forward_stq_idx_T_2 = bits(stld_prs2_matches[0], 2, 2) node _mem_stld_forward_stq_idx_T_3 = bits(stld_prs2_matches[0], 3, 3) node _mem_stld_forward_stq_idx_T_4 = bits(stld_prs2_matches[0], 4, 4) node _mem_stld_forward_stq_idx_T_5 = bits(stld_prs2_matches[0], 5, 5) node _mem_stld_forward_stq_idx_T_6 = bits(stld_prs2_matches[0], 6, 6) node _mem_stld_forward_stq_idx_T_7 = bits(stld_prs2_matches[0], 7, 7) node _mem_stld_forward_stq_idx_T_8 = bits(stld_prs2_matches[0], 8, 8) node _mem_stld_forward_stq_idx_T_9 = bits(stld_prs2_matches[0], 9, 9) node _mem_stld_forward_stq_idx_T_10 = bits(stld_prs2_matches[0], 10, 10) node _mem_stld_forward_stq_idx_T_11 = bits(stld_prs2_matches[0], 11, 11) node _mem_stld_forward_stq_idx_T_12 = bits(stld_prs2_matches[0], 12, 12) node _mem_stld_forward_stq_idx_T_13 = bits(stld_prs2_matches[0], 13, 13) node _mem_stld_forward_stq_idx_T_14 = bits(stld_prs2_matches[0], 14, 14) node _mem_stld_forward_stq_idx_T_15 = bits(stld_prs2_matches[0], 15, 15) node _mem_stld_forward_stq_idx_T_16 = bits(stld_prs2_matches[0], 16, 16) node _mem_stld_forward_stq_idx_T_17 = bits(stld_prs2_matches[0], 17, 17) node _mem_stld_forward_stq_idx_T_18 = bits(stld_prs2_matches[0], 18, 18) node _mem_stld_forward_stq_idx_T_19 = bits(stld_prs2_matches[0], 19, 19) node _mem_stld_forward_stq_idx_T_20 = bits(stld_prs2_matches[0], 20, 20) node _mem_stld_forward_stq_idx_T_21 = bits(stld_prs2_matches[0], 21, 21) node _mem_stld_forward_stq_idx_T_22 = bits(stld_prs2_matches[0], 22, 22) node _mem_stld_forward_stq_idx_T_23 = bits(stld_prs2_matches[0], 23, 23) node _mem_stld_forward_stq_idx_temp_vec_T = geq(UInt<1>(0h0), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_0 = and(_mem_stld_forward_stq_idx_T, _mem_stld_forward_stq_idx_temp_vec_T) node _mem_stld_forward_stq_idx_temp_vec_T_1 = geq(UInt<1>(0h1), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_1 = and(_mem_stld_forward_stq_idx_T_1, _mem_stld_forward_stq_idx_temp_vec_T_1) node _mem_stld_forward_stq_idx_temp_vec_T_2 = geq(UInt<2>(0h2), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_2 = and(_mem_stld_forward_stq_idx_T_2, _mem_stld_forward_stq_idx_temp_vec_T_2) node _mem_stld_forward_stq_idx_temp_vec_T_3 = geq(UInt<2>(0h3), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_3 = and(_mem_stld_forward_stq_idx_T_3, _mem_stld_forward_stq_idx_temp_vec_T_3) node _mem_stld_forward_stq_idx_temp_vec_T_4 = geq(UInt<3>(0h4), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_4 = and(_mem_stld_forward_stq_idx_T_4, _mem_stld_forward_stq_idx_temp_vec_T_4) node _mem_stld_forward_stq_idx_temp_vec_T_5 = geq(UInt<3>(0h5), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_5 = and(_mem_stld_forward_stq_idx_T_5, _mem_stld_forward_stq_idx_temp_vec_T_5) node _mem_stld_forward_stq_idx_temp_vec_T_6 = geq(UInt<3>(0h6), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_6 = and(_mem_stld_forward_stq_idx_T_6, _mem_stld_forward_stq_idx_temp_vec_T_6) node _mem_stld_forward_stq_idx_temp_vec_T_7 = geq(UInt<3>(0h7), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_7 = and(_mem_stld_forward_stq_idx_T_7, _mem_stld_forward_stq_idx_temp_vec_T_7) node _mem_stld_forward_stq_idx_temp_vec_T_8 = geq(UInt<4>(0h8), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_8 = and(_mem_stld_forward_stq_idx_T_8, _mem_stld_forward_stq_idx_temp_vec_T_8) node _mem_stld_forward_stq_idx_temp_vec_T_9 = geq(UInt<4>(0h9), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_9 = and(_mem_stld_forward_stq_idx_T_9, _mem_stld_forward_stq_idx_temp_vec_T_9) node _mem_stld_forward_stq_idx_temp_vec_T_10 = geq(UInt<4>(0ha), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_10 = and(_mem_stld_forward_stq_idx_T_10, _mem_stld_forward_stq_idx_temp_vec_T_10) node _mem_stld_forward_stq_idx_temp_vec_T_11 = geq(UInt<4>(0hb), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_11 = and(_mem_stld_forward_stq_idx_T_11, _mem_stld_forward_stq_idx_temp_vec_T_11) node _mem_stld_forward_stq_idx_temp_vec_T_12 = geq(UInt<4>(0hc), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_12 = and(_mem_stld_forward_stq_idx_T_12, _mem_stld_forward_stq_idx_temp_vec_T_12) node _mem_stld_forward_stq_idx_temp_vec_T_13 = geq(UInt<4>(0hd), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_13 = and(_mem_stld_forward_stq_idx_T_13, _mem_stld_forward_stq_idx_temp_vec_T_13) node _mem_stld_forward_stq_idx_temp_vec_T_14 = geq(UInt<4>(0he), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_14 = and(_mem_stld_forward_stq_idx_T_14, _mem_stld_forward_stq_idx_temp_vec_T_14) node _mem_stld_forward_stq_idx_temp_vec_T_15 = geq(UInt<4>(0hf), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_15 = and(_mem_stld_forward_stq_idx_T_15, _mem_stld_forward_stq_idx_temp_vec_T_15) node _mem_stld_forward_stq_idx_temp_vec_T_16 = geq(UInt<5>(0h10), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_16 = and(_mem_stld_forward_stq_idx_T_16, _mem_stld_forward_stq_idx_temp_vec_T_16) node _mem_stld_forward_stq_idx_temp_vec_T_17 = geq(UInt<5>(0h11), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_17 = and(_mem_stld_forward_stq_idx_T_17, _mem_stld_forward_stq_idx_temp_vec_T_17) node _mem_stld_forward_stq_idx_temp_vec_T_18 = geq(UInt<5>(0h12), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_18 = and(_mem_stld_forward_stq_idx_T_18, _mem_stld_forward_stq_idx_temp_vec_T_18) node _mem_stld_forward_stq_idx_temp_vec_T_19 = geq(UInt<5>(0h13), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_19 = and(_mem_stld_forward_stq_idx_T_19, _mem_stld_forward_stq_idx_temp_vec_T_19) node _mem_stld_forward_stq_idx_temp_vec_T_20 = geq(UInt<5>(0h14), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_20 = and(_mem_stld_forward_stq_idx_T_20, _mem_stld_forward_stq_idx_temp_vec_T_20) node _mem_stld_forward_stq_idx_temp_vec_T_21 = geq(UInt<5>(0h15), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_21 = and(_mem_stld_forward_stq_idx_T_21, _mem_stld_forward_stq_idx_temp_vec_T_21) node _mem_stld_forward_stq_idx_temp_vec_T_22 = geq(UInt<5>(0h16), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_22 = and(_mem_stld_forward_stq_idx_T_22, _mem_stld_forward_stq_idx_temp_vec_T_22) node _mem_stld_forward_stq_idx_temp_vec_T_23 = geq(UInt<5>(0h17), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_23 = and(_mem_stld_forward_stq_idx_T_23, _mem_stld_forward_stq_idx_temp_vec_T_23) node _mem_stld_forward_stq_idx_idx_T = mux(_mem_stld_forward_stq_idx_T_22, UInt<6>(0h36), UInt<6>(0h37)) node _mem_stld_forward_stq_idx_idx_T_1 = mux(_mem_stld_forward_stq_idx_T_21, UInt<6>(0h35), _mem_stld_forward_stq_idx_idx_T) node _mem_stld_forward_stq_idx_idx_T_2 = mux(_mem_stld_forward_stq_idx_T_20, UInt<6>(0h34), _mem_stld_forward_stq_idx_idx_T_1) node _mem_stld_forward_stq_idx_idx_T_3 = mux(_mem_stld_forward_stq_idx_T_19, UInt<6>(0h33), _mem_stld_forward_stq_idx_idx_T_2) node _mem_stld_forward_stq_idx_idx_T_4 = mux(_mem_stld_forward_stq_idx_T_18, UInt<6>(0h32), _mem_stld_forward_stq_idx_idx_T_3) node _mem_stld_forward_stq_idx_idx_T_5 = mux(_mem_stld_forward_stq_idx_T_17, UInt<6>(0h31), _mem_stld_forward_stq_idx_idx_T_4) node _mem_stld_forward_stq_idx_idx_T_6 = mux(_mem_stld_forward_stq_idx_T_16, UInt<6>(0h30), _mem_stld_forward_stq_idx_idx_T_5) node _mem_stld_forward_stq_idx_idx_T_7 = mux(_mem_stld_forward_stq_idx_T_15, UInt<6>(0h2f), _mem_stld_forward_stq_idx_idx_T_6) node _mem_stld_forward_stq_idx_idx_T_8 = mux(_mem_stld_forward_stq_idx_T_14, UInt<6>(0h2e), _mem_stld_forward_stq_idx_idx_T_7) node _mem_stld_forward_stq_idx_idx_T_9 = mux(_mem_stld_forward_stq_idx_T_13, UInt<6>(0h2d), _mem_stld_forward_stq_idx_idx_T_8) node _mem_stld_forward_stq_idx_idx_T_10 = mux(_mem_stld_forward_stq_idx_T_12, UInt<6>(0h2c), _mem_stld_forward_stq_idx_idx_T_9) node _mem_stld_forward_stq_idx_idx_T_11 = mux(_mem_stld_forward_stq_idx_T_11, UInt<6>(0h2b), _mem_stld_forward_stq_idx_idx_T_10) node _mem_stld_forward_stq_idx_idx_T_12 = mux(_mem_stld_forward_stq_idx_T_10, UInt<6>(0h2a), _mem_stld_forward_stq_idx_idx_T_11) node _mem_stld_forward_stq_idx_idx_T_13 = mux(_mem_stld_forward_stq_idx_T_9, UInt<6>(0h29), _mem_stld_forward_stq_idx_idx_T_12) node _mem_stld_forward_stq_idx_idx_T_14 = mux(_mem_stld_forward_stq_idx_T_8, UInt<6>(0h28), _mem_stld_forward_stq_idx_idx_T_13) node _mem_stld_forward_stq_idx_idx_T_15 = mux(_mem_stld_forward_stq_idx_T_7, UInt<6>(0h27), _mem_stld_forward_stq_idx_idx_T_14) node _mem_stld_forward_stq_idx_idx_T_16 = mux(_mem_stld_forward_stq_idx_T_6, UInt<6>(0h26), _mem_stld_forward_stq_idx_idx_T_15) node _mem_stld_forward_stq_idx_idx_T_17 = mux(_mem_stld_forward_stq_idx_T_5, UInt<6>(0h25), _mem_stld_forward_stq_idx_idx_T_16) node _mem_stld_forward_stq_idx_idx_T_18 = mux(_mem_stld_forward_stq_idx_T_4, UInt<6>(0h24), _mem_stld_forward_stq_idx_idx_T_17) node _mem_stld_forward_stq_idx_idx_T_19 = mux(_mem_stld_forward_stq_idx_T_3, UInt<6>(0h23), _mem_stld_forward_stq_idx_idx_T_18) node _mem_stld_forward_stq_idx_idx_T_20 = mux(_mem_stld_forward_stq_idx_T_2, UInt<6>(0h22), _mem_stld_forward_stq_idx_idx_T_19) node _mem_stld_forward_stq_idx_idx_T_21 = mux(_mem_stld_forward_stq_idx_T_1, UInt<6>(0h21), _mem_stld_forward_stq_idx_idx_T_20) node _mem_stld_forward_stq_idx_idx_T_22 = mux(_mem_stld_forward_stq_idx_T, UInt<6>(0h20), _mem_stld_forward_stq_idx_idx_T_21) node _mem_stld_forward_stq_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _mem_stld_forward_stq_idx_idx_T_22) node _mem_stld_forward_stq_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _mem_stld_forward_stq_idx_idx_T_23) node _mem_stld_forward_stq_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _mem_stld_forward_stq_idx_idx_T_24) node _mem_stld_forward_stq_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _mem_stld_forward_stq_idx_idx_T_25) node _mem_stld_forward_stq_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _mem_stld_forward_stq_idx_idx_T_26) node _mem_stld_forward_stq_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _mem_stld_forward_stq_idx_idx_T_27) node _mem_stld_forward_stq_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _mem_stld_forward_stq_idx_idx_T_28) node _mem_stld_forward_stq_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _mem_stld_forward_stq_idx_idx_T_29) node _mem_stld_forward_stq_idx_idx_T_31 = mux(mem_stld_forward_stq_idx_temp_vec_23, UInt<5>(0h17), _mem_stld_forward_stq_idx_idx_T_30) node _mem_stld_forward_stq_idx_idx_T_32 = mux(mem_stld_forward_stq_idx_temp_vec_22, UInt<5>(0h16), _mem_stld_forward_stq_idx_idx_T_31) node _mem_stld_forward_stq_idx_idx_T_33 = mux(mem_stld_forward_stq_idx_temp_vec_21, UInt<5>(0h15), _mem_stld_forward_stq_idx_idx_T_32) node _mem_stld_forward_stq_idx_idx_T_34 = mux(mem_stld_forward_stq_idx_temp_vec_20, UInt<5>(0h14), _mem_stld_forward_stq_idx_idx_T_33) node _mem_stld_forward_stq_idx_idx_T_35 = mux(mem_stld_forward_stq_idx_temp_vec_19, UInt<5>(0h13), _mem_stld_forward_stq_idx_idx_T_34) node _mem_stld_forward_stq_idx_idx_T_36 = mux(mem_stld_forward_stq_idx_temp_vec_18, UInt<5>(0h12), _mem_stld_forward_stq_idx_idx_T_35) node _mem_stld_forward_stq_idx_idx_T_37 = mux(mem_stld_forward_stq_idx_temp_vec_17, UInt<5>(0h11), _mem_stld_forward_stq_idx_idx_T_36) node _mem_stld_forward_stq_idx_idx_T_38 = mux(mem_stld_forward_stq_idx_temp_vec_16, UInt<5>(0h10), _mem_stld_forward_stq_idx_idx_T_37) node _mem_stld_forward_stq_idx_idx_T_39 = mux(mem_stld_forward_stq_idx_temp_vec_15, UInt<4>(0hf), _mem_stld_forward_stq_idx_idx_T_38) node _mem_stld_forward_stq_idx_idx_T_40 = mux(mem_stld_forward_stq_idx_temp_vec_14, UInt<4>(0he), _mem_stld_forward_stq_idx_idx_T_39) node _mem_stld_forward_stq_idx_idx_T_41 = mux(mem_stld_forward_stq_idx_temp_vec_13, UInt<4>(0hd), _mem_stld_forward_stq_idx_idx_T_40) node _mem_stld_forward_stq_idx_idx_T_42 = mux(mem_stld_forward_stq_idx_temp_vec_12, UInt<4>(0hc), _mem_stld_forward_stq_idx_idx_T_41) node _mem_stld_forward_stq_idx_idx_T_43 = mux(mem_stld_forward_stq_idx_temp_vec_11, UInt<4>(0hb), _mem_stld_forward_stq_idx_idx_T_42) node _mem_stld_forward_stq_idx_idx_T_44 = mux(mem_stld_forward_stq_idx_temp_vec_10, UInt<4>(0ha), _mem_stld_forward_stq_idx_idx_T_43) node _mem_stld_forward_stq_idx_idx_T_45 = mux(mem_stld_forward_stq_idx_temp_vec_9, UInt<4>(0h9), _mem_stld_forward_stq_idx_idx_T_44) node _mem_stld_forward_stq_idx_idx_T_46 = mux(mem_stld_forward_stq_idx_temp_vec_8, UInt<4>(0h8), _mem_stld_forward_stq_idx_idx_T_45) node _mem_stld_forward_stq_idx_idx_T_47 = mux(mem_stld_forward_stq_idx_temp_vec_7, UInt<3>(0h7), _mem_stld_forward_stq_idx_idx_T_46) node _mem_stld_forward_stq_idx_idx_T_48 = mux(mem_stld_forward_stq_idx_temp_vec_6, UInt<3>(0h6), _mem_stld_forward_stq_idx_idx_T_47) node _mem_stld_forward_stq_idx_idx_T_49 = mux(mem_stld_forward_stq_idx_temp_vec_5, UInt<3>(0h5), _mem_stld_forward_stq_idx_idx_T_48) node _mem_stld_forward_stq_idx_idx_T_50 = mux(mem_stld_forward_stq_idx_temp_vec_4, UInt<3>(0h4), _mem_stld_forward_stq_idx_idx_T_49) node _mem_stld_forward_stq_idx_idx_T_51 = mux(mem_stld_forward_stq_idx_temp_vec_3, UInt<2>(0h3), _mem_stld_forward_stq_idx_idx_T_50) node _mem_stld_forward_stq_idx_idx_T_52 = mux(mem_stld_forward_stq_idx_temp_vec_2, UInt<2>(0h2), _mem_stld_forward_stq_idx_idx_T_51) node _mem_stld_forward_stq_idx_idx_T_53 = mux(mem_stld_forward_stq_idx_temp_vec_1, UInt<1>(0h1), _mem_stld_forward_stq_idx_idx_T_52) node mem_stld_forward_stq_idx_idx = mux(mem_stld_forward_stq_idx_temp_vec_0, UInt<1>(0h0), _mem_stld_forward_stq_idx_idx_T_53) node _mem_stld_forward_stq_idx_T_24 = bits(mem_stld_forward_stq_idx_idx, 4, 0) wire mem_stld_forward_stq_idx : UInt<5>[1] connect mem_stld_forward_stq_idx[0], _mem_stld_forward_stq_idx_T_24 node _mem_stld_forward_valid_T = dshr(stld_prs2_matches[0], mem_stld_forward_stq_idx[0]) node _mem_stld_forward_valid_T_1 = bits(_mem_stld_forward_valid_T, 0, 0) node _mem_stld_forward_valid_T_2 = and(do_ld_search[0], _mem_stld_forward_valid_T_1) wire mem_stld_forward_valid : UInt<1>[1] connect mem_stld_forward_valid[0], _mem_stld_forward_valid_T_2 reg io_core_clr_unsafe_0_valid_REG : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG, do_st_search[0] node _io_core_clr_unsafe_0_valid_T = eq(io.dmem.nack[0].valid, UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_1 = eq(fired_load_agen[0], UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_2 = and(do_ld_search[0], _io_core_clr_unsafe_0_valid_T_1) node _io_core_clr_unsafe_0_valid_T_3 = eq(io.dmem.s1_kill[0], UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_4 = and(_io_core_clr_unsafe_0_valid_T_2, _io_core_clr_unsafe_0_valid_T_3) reg io_core_clr_unsafe_0_valid_REG_1 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_1, dmem_req_fire[0] node _io_core_clr_unsafe_0_valid_T_5 = and(_io_core_clr_unsafe_0_valid_T_4, io_core_clr_unsafe_0_valid_REG_1) reg io_core_clr_unsafe_0_valid_REG_2 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_2, _io_core_clr_unsafe_0_valid_T_5 node _io_core_clr_unsafe_0_valid_T_6 = and(_io_core_clr_unsafe_0_valid_T, io_core_clr_unsafe_0_valid_REG_2) node _io_core_clr_unsafe_0_valid_T_7 = or(io_core_clr_unsafe_0_valid_REG, _io_core_clr_unsafe_0_valid_T_6) reg io_core_clr_unsafe_0_valid_REG_3 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_3, failed_load node _io_core_clr_unsafe_0_valid_T_8 = eq(io_core_clr_unsafe_0_valid_REG_3, UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_9 = and(_io_core_clr_unsafe_0_valid_T_7, _io_core_clr_unsafe_0_valid_T_8) connect io.core.clr_unsafe[0].valid, _io_core_clr_unsafe_0_valid_T_9 reg io_core_clr_unsafe_0_bits_REG : UInt, clock connect io_core_clr_unsafe_0_bits_REG, lcam_uop[0].rob_idx connect io.core.clr_unsafe[0].bits, io_core_clr_unsafe_0_bits_REG node _l_idx_T = and(ldq_valid[0], ldq_order_fail[0]) node _l_idx_T_1 = and(ldq_valid[1], ldq_order_fail[1]) node _l_idx_T_2 = and(ldq_valid[2], ldq_order_fail[2]) node _l_idx_T_3 = and(ldq_valid[3], ldq_order_fail[3]) node _l_idx_T_4 = and(ldq_valid[4], ldq_order_fail[4]) node _l_idx_T_5 = and(ldq_valid[5], ldq_order_fail[5]) node _l_idx_T_6 = and(ldq_valid[6], ldq_order_fail[6]) node _l_idx_T_7 = and(ldq_valid[7], ldq_order_fail[7]) node _l_idx_T_8 = and(ldq_valid[8], ldq_order_fail[8]) node _l_idx_T_9 = and(ldq_valid[9], ldq_order_fail[9]) node _l_idx_T_10 = and(ldq_valid[10], ldq_order_fail[10]) node _l_idx_T_11 = and(ldq_valid[11], ldq_order_fail[11]) node _l_idx_T_12 = and(ldq_valid[12], ldq_order_fail[12]) node _l_idx_T_13 = and(ldq_valid[13], ldq_order_fail[13]) node _l_idx_T_14 = and(ldq_valid[14], ldq_order_fail[14]) node _l_idx_T_15 = and(ldq_valid[15], ldq_order_fail[15]) node _l_idx_T_16 = and(ldq_valid[16], ldq_order_fail[16]) node _l_idx_T_17 = and(ldq_valid[17], ldq_order_fail[17]) node _l_idx_T_18 = and(ldq_valid[18], ldq_order_fail[18]) node _l_idx_T_19 = and(ldq_valid[19], ldq_order_fail[19]) node _l_idx_T_20 = and(ldq_valid[20], ldq_order_fail[20]) node _l_idx_T_21 = and(ldq_valid[21], ldq_order_fail[21]) node _l_idx_T_22 = and(ldq_valid[22], ldq_order_fail[22]) node _l_idx_T_23 = and(ldq_valid[23], ldq_order_fail[23]) node _l_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node l_idx_temp_vec_0 = and(_l_idx_T, _l_idx_temp_vec_T) node _l_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node l_idx_temp_vec_1 = and(_l_idx_T_1, _l_idx_temp_vec_T_1) node _l_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node l_idx_temp_vec_2 = and(_l_idx_T_2, _l_idx_temp_vec_T_2) node _l_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node l_idx_temp_vec_3 = and(_l_idx_T_3, _l_idx_temp_vec_T_3) node _l_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node l_idx_temp_vec_4 = and(_l_idx_T_4, _l_idx_temp_vec_T_4) node _l_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node l_idx_temp_vec_5 = and(_l_idx_T_5, _l_idx_temp_vec_T_5) node _l_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node l_idx_temp_vec_6 = and(_l_idx_T_6, _l_idx_temp_vec_T_6) node _l_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node l_idx_temp_vec_7 = and(_l_idx_T_7, _l_idx_temp_vec_T_7) node _l_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node l_idx_temp_vec_8 = and(_l_idx_T_8, _l_idx_temp_vec_T_8) node _l_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node l_idx_temp_vec_9 = and(_l_idx_T_9, _l_idx_temp_vec_T_9) node _l_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node l_idx_temp_vec_10 = and(_l_idx_T_10, _l_idx_temp_vec_T_10) node _l_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node l_idx_temp_vec_11 = and(_l_idx_T_11, _l_idx_temp_vec_T_11) node _l_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node l_idx_temp_vec_12 = and(_l_idx_T_12, _l_idx_temp_vec_T_12) node _l_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node l_idx_temp_vec_13 = and(_l_idx_T_13, _l_idx_temp_vec_T_13) node _l_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node l_idx_temp_vec_14 = and(_l_idx_T_14, _l_idx_temp_vec_T_14) node _l_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node l_idx_temp_vec_15 = and(_l_idx_T_15, _l_idx_temp_vec_T_15) node _l_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node l_idx_temp_vec_16 = and(_l_idx_T_16, _l_idx_temp_vec_T_16) node _l_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node l_idx_temp_vec_17 = and(_l_idx_T_17, _l_idx_temp_vec_T_17) node _l_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node l_idx_temp_vec_18 = and(_l_idx_T_18, _l_idx_temp_vec_T_18) node _l_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node l_idx_temp_vec_19 = and(_l_idx_T_19, _l_idx_temp_vec_T_19) node _l_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node l_idx_temp_vec_20 = and(_l_idx_T_20, _l_idx_temp_vec_T_20) node _l_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node l_idx_temp_vec_21 = and(_l_idx_T_21, _l_idx_temp_vec_T_21) node _l_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node l_idx_temp_vec_22 = and(_l_idx_T_22, _l_idx_temp_vec_T_22) node _l_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node l_idx_temp_vec_23 = and(_l_idx_T_23, _l_idx_temp_vec_T_23) node _l_idx_idx_T = mux(_l_idx_T_22, UInt<6>(0h36), UInt<6>(0h37)) node _l_idx_idx_T_1 = mux(_l_idx_T_21, UInt<6>(0h35), _l_idx_idx_T) node _l_idx_idx_T_2 = mux(_l_idx_T_20, UInt<6>(0h34), _l_idx_idx_T_1) node _l_idx_idx_T_3 = mux(_l_idx_T_19, UInt<6>(0h33), _l_idx_idx_T_2) node _l_idx_idx_T_4 = mux(_l_idx_T_18, UInt<6>(0h32), _l_idx_idx_T_3) node _l_idx_idx_T_5 = mux(_l_idx_T_17, UInt<6>(0h31), _l_idx_idx_T_4) node _l_idx_idx_T_6 = mux(_l_idx_T_16, UInt<6>(0h30), _l_idx_idx_T_5) node _l_idx_idx_T_7 = mux(_l_idx_T_15, UInt<6>(0h2f), _l_idx_idx_T_6) node _l_idx_idx_T_8 = mux(_l_idx_T_14, UInt<6>(0h2e), _l_idx_idx_T_7) node _l_idx_idx_T_9 = mux(_l_idx_T_13, UInt<6>(0h2d), _l_idx_idx_T_8) node _l_idx_idx_T_10 = mux(_l_idx_T_12, UInt<6>(0h2c), _l_idx_idx_T_9) node _l_idx_idx_T_11 = mux(_l_idx_T_11, UInt<6>(0h2b), _l_idx_idx_T_10) node _l_idx_idx_T_12 = mux(_l_idx_T_10, UInt<6>(0h2a), _l_idx_idx_T_11) node _l_idx_idx_T_13 = mux(_l_idx_T_9, UInt<6>(0h29), _l_idx_idx_T_12) node _l_idx_idx_T_14 = mux(_l_idx_T_8, UInt<6>(0h28), _l_idx_idx_T_13) node _l_idx_idx_T_15 = mux(_l_idx_T_7, UInt<6>(0h27), _l_idx_idx_T_14) node _l_idx_idx_T_16 = mux(_l_idx_T_6, UInt<6>(0h26), _l_idx_idx_T_15) node _l_idx_idx_T_17 = mux(_l_idx_T_5, UInt<6>(0h25), _l_idx_idx_T_16) node _l_idx_idx_T_18 = mux(_l_idx_T_4, UInt<6>(0h24), _l_idx_idx_T_17) node _l_idx_idx_T_19 = mux(_l_idx_T_3, UInt<6>(0h23), _l_idx_idx_T_18) node _l_idx_idx_T_20 = mux(_l_idx_T_2, UInt<6>(0h22), _l_idx_idx_T_19) node _l_idx_idx_T_21 = mux(_l_idx_T_1, UInt<6>(0h21), _l_idx_idx_T_20) node _l_idx_idx_T_22 = mux(_l_idx_T, UInt<6>(0h20), _l_idx_idx_T_21) node _l_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _l_idx_idx_T_22) node _l_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _l_idx_idx_T_23) node _l_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _l_idx_idx_T_24) node _l_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _l_idx_idx_T_25) node _l_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _l_idx_idx_T_26) node _l_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _l_idx_idx_T_27) node _l_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _l_idx_idx_T_28) node _l_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _l_idx_idx_T_29) node _l_idx_idx_T_31 = mux(l_idx_temp_vec_23, UInt<5>(0h17), _l_idx_idx_T_30) node _l_idx_idx_T_32 = mux(l_idx_temp_vec_22, UInt<5>(0h16), _l_idx_idx_T_31) node _l_idx_idx_T_33 = mux(l_idx_temp_vec_21, UInt<5>(0h15), _l_idx_idx_T_32) node _l_idx_idx_T_34 = mux(l_idx_temp_vec_20, UInt<5>(0h14), _l_idx_idx_T_33) node _l_idx_idx_T_35 = mux(l_idx_temp_vec_19, UInt<5>(0h13), _l_idx_idx_T_34) node _l_idx_idx_T_36 = mux(l_idx_temp_vec_18, UInt<5>(0h12), _l_idx_idx_T_35) node _l_idx_idx_T_37 = mux(l_idx_temp_vec_17, UInt<5>(0h11), _l_idx_idx_T_36) node _l_idx_idx_T_38 = mux(l_idx_temp_vec_16, UInt<5>(0h10), _l_idx_idx_T_37) node _l_idx_idx_T_39 = mux(l_idx_temp_vec_15, UInt<4>(0hf), _l_idx_idx_T_38) node _l_idx_idx_T_40 = mux(l_idx_temp_vec_14, UInt<4>(0he), _l_idx_idx_T_39) node _l_idx_idx_T_41 = mux(l_idx_temp_vec_13, UInt<4>(0hd), _l_idx_idx_T_40) node _l_idx_idx_T_42 = mux(l_idx_temp_vec_12, UInt<4>(0hc), _l_idx_idx_T_41) node _l_idx_idx_T_43 = mux(l_idx_temp_vec_11, UInt<4>(0hb), _l_idx_idx_T_42) node _l_idx_idx_T_44 = mux(l_idx_temp_vec_10, UInt<4>(0ha), _l_idx_idx_T_43) node _l_idx_idx_T_45 = mux(l_idx_temp_vec_9, UInt<4>(0h9), _l_idx_idx_T_44) node _l_idx_idx_T_46 = mux(l_idx_temp_vec_8, UInt<4>(0h8), _l_idx_idx_T_45) node _l_idx_idx_T_47 = mux(l_idx_temp_vec_7, UInt<3>(0h7), _l_idx_idx_T_46) node _l_idx_idx_T_48 = mux(l_idx_temp_vec_6, UInt<3>(0h6), _l_idx_idx_T_47) node _l_idx_idx_T_49 = mux(l_idx_temp_vec_5, UInt<3>(0h5), _l_idx_idx_T_48) node _l_idx_idx_T_50 = mux(l_idx_temp_vec_4, UInt<3>(0h4), _l_idx_idx_T_49) node _l_idx_idx_T_51 = mux(l_idx_temp_vec_3, UInt<2>(0h3), _l_idx_idx_T_50) node _l_idx_idx_T_52 = mux(l_idx_temp_vec_2, UInt<2>(0h2), _l_idx_idx_T_51) node _l_idx_idx_T_53 = mux(l_idx_temp_vec_1, UInt<1>(0h1), _l_idx_idx_T_52) node l_idx_idx = mux(l_idx_temp_vec_0, UInt<1>(0h0), _l_idx_idx_T_53) node l_idx = bits(l_idx_idx, 4, 0) regreset r_xcpt_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg r_xcpt : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, cause : UInt<5>, badvaddr : UInt<40>}, clock node ld_xcpt_valid_lo_lo_lo_hi = cat(ldq_order_fail[2], ldq_order_fail[1]) node ld_xcpt_valid_lo_lo_lo = cat(ld_xcpt_valid_lo_lo_lo_hi, ldq_order_fail[0]) node ld_xcpt_valid_lo_lo_hi_hi = cat(ldq_order_fail[5], ldq_order_fail[4]) node ld_xcpt_valid_lo_lo_hi = cat(ld_xcpt_valid_lo_lo_hi_hi, ldq_order_fail[3]) node ld_xcpt_valid_lo_lo = cat(ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo) node ld_xcpt_valid_lo_hi_lo_hi = cat(ldq_order_fail[8], ldq_order_fail[7]) node ld_xcpt_valid_lo_hi_lo = cat(ld_xcpt_valid_lo_hi_lo_hi, ldq_order_fail[6]) node ld_xcpt_valid_lo_hi_hi_hi = cat(ldq_order_fail[11], ldq_order_fail[10]) node ld_xcpt_valid_lo_hi_hi = cat(ld_xcpt_valid_lo_hi_hi_hi, ldq_order_fail[9]) node ld_xcpt_valid_lo_hi = cat(ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo) node ld_xcpt_valid_lo = cat(ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo) node ld_xcpt_valid_hi_lo_lo_hi = cat(ldq_order_fail[14], ldq_order_fail[13]) node ld_xcpt_valid_hi_lo_lo = cat(ld_xcpt_valid_hi_lo_lo_hi, ldq_order_fail[12]) node ld_xcpt_valid_hi_lo_hi_hi = cat(ldq_order_fail[17], ldq_order_fail[16]) node ld_xcpt_valid_hi_lo_hi = cat(ld_xcpt_valid_hi_lo_hi_hi, ldq_order_fail[15]) node ld_xcpt_valid_hi_lo = cat(ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo) node ld_xcpt_valid_hi_hi_lo_hi = cat(ldq_order_fail[20], ldq_order_fail[19]) node ld_xcpt_valid_hi_hi_lo = cat(ld_xcpt_valid_hi_hi_lo_hi, ldq_order_fail[18]) node ld_xcpt_valid_hi_hi_hi_hi = cat(ldq_order_fail[23], ldq_order_fail[22]) node ld_xcpt_valid_hi_hi_hi = cat(ld_xcpt_valid_hi_hi_hi_hi, ldq_order_fail[21]) node ld_xcpt_valid_hi_hi = cat(ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo) node ld_xcpt_valid_hi = cat(ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo) node _ld_xcpt_valid_T = cat(ld_xcpt_valid_hi, ld_xcpt_valid_lo) node ld_xcpt_valid_lo_lo_lo_hi_1 = cat(ldq_valid[2], ldq_valid[1]) node ld_xcpt_valid_lo_lo_lo_1 = cat(ld_xcpt_valid_lo_lo_lo_hi_1, ldq_valid[0]) node ld_xcpt_valid_lo_lo_hi_hi_1 = cat(ldq_valid[5], ldq_valid[4]) node ld_xcpt_valid_lo_lo_hi_1 = cat(ld_xcpt_valid_lo_lo_hi_hi_1, ldq_valid[3]) node ld_xcpt_valid_lo_lo_1 = cat(ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1) node ld_xcpt_valid_lo_hi_lo_hi_1 = cat(ldq_valid[8], ldq_valid[7]) node ld_xcpt_valid_lo_hi_lo_1 = cat(ld_xcpt_valid_lo_hi_lo_hi_1, ldq_valid[6]) node ld_xcpt_valid_lo_hi_hi_hi_1 = cat(ldq_valid[11], ldq_valid[10]) node ld_xcpt_valid_lo_hi_hi_1 = cat(ld_xcpt_valid_lo_hi_hi_hi_1, ldq_valid[9]) node ld_xcpt_valid_lo_hi_1 = cat(ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1) node ld_xcpt_valid_lo_1 = cat(ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1) node ld_xcpt_valid_hi_lo_lo_hi_1 = cat(ldq_valid[14], ldq_valid[13]) node ld_xcpt_valid_hi_lo_lo_1 = cat(ld_xcpt_valid_hi_lo_lo_hi_1, ldq_valid[12]) node ld_xcpt_valid_hi_lo_hi_hi_1 = cat(ldq_valid[17], ldq_valid[16]) node ld_xcpt_valid_hi_lo_hi_1 = cat(ld_xcpt_valid_hi_lo_hi_hi_1, ldq_valid[15]) node ld_xcpt_valid_hi_lo_1 = cat(ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1) node ld_xcpt_valid_hi_hi_lo_hi_1 = cat(ldq_valid[20], ldq_valid[19]) node ld_xcpt_valid_hi_hi_lo_1 = cat(ld_xcpt_valid_hi_hi_lo_hi_1, ldq_valid[18]) node ld_xcpt_valid_hi_hi_hi_hi_1 = cat(ldq_valid[23], ldq_valid[22]) node ld_xcpt_valid_hi_hi_hi_1 = cat(ld_xcpt_valid_hi_hi_hi_hi_1, ldq_valid[21]) node ld_xcpt_valid_hi_hi_1 = cat(ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1) node ld_xcpt_valid_hi_1 = cat(ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1) node _ld_xcpt_valid_T_1 = cat(ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1) node _ld_xcpt_valid_T_2 = and(_ld_xcpt_valid_T, _ld_xcpt_valid_T_1) node ld_xcpt_valid = neq(_ld_xcpt_valid_T_2, UInt<1>(0h0)) node _ld_xcpt_uop_T = geq(l_idx, UInt<5>(0h18)) node _ld_xcpt_uop_T_1 = sub(l_idx, UInt<5>(0h18)) node _ld_xcpt_uop_T_2 = tail(_ld_xcpt_uop_T_1, 1) node _ld_xcpt_uop_T_3 = mux(_ld_xcpt_uop_T, _ld_xcpt_uop_T_2, l_idx) wire ld_xcpt_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ld_xcpt_uop, ldq_uop[_ld_xcpt_uop_T_3] node _use_mem_xcpt_T = lt(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx) node _use_mem_xcpt_T_1 = lt(mem_xcpt_uop.rob_idx, io.core.rob_head_idx) node _use_mem_xcpt_T_2 = xor(_use_mem_xcpt_T, _use_mem_xcpt_T_1) node _use_mem_xcpt_T_3 = lt(ld_xcpt_uop.rob_idx, io.core.rob_head_idx) node _use_mem_xcpt_T_4 = xor(_use_mem_xcpt_T_2, _use_mem_xcpt_T_3) node _use_mem_xcpt_T_5 = and(mem_xcpt_valid, _use_mem_xcpt_T_4) node _use_mem_xcpt_T_6 = eq(ld_xcpt_valid, UInt<1>(0h0)) node use_mem_xcpt = or(_use_mem_xcpt_T_5, _use_mem_xcpt_T_6) node xcpt_uop = mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) node _r_xcpt_valid_T = or(ld_xcpt_valid, mem_xcpt_valid) node _r_xcpt_valid_T_1 = and(io.core.brupdate.b1.mispredict_mask, xcpt_uop.br_mask) node _r_xcpt_valid_T_2 = neq(_r_xcpt_valid_T_1, UInt<1>(0h0)) node _r_xcpt_valid_T_3 = or(_r_xcpt_valid_T_2, io.core.exception) node _r_xcpt_valid_T_4 = eq(_r_xcpt_valid_T_3, UInt<1>(0h0)) node _r_xcpt_valid_T_5 = and(_r_xcpt_valid_T, _r_xcpt_valid_T_4) connect r_xcpt_valid, _r_xcpt_valid_T_5 connect r_xcpt.uop, xcpt_uop node _r_xcpt_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _r_xcpt_uop_br_mask_T_1 = and(xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T) connect r_xcpt.uop.br_mask, _r_xcpt_uop_br_mask_T_1 node _r_xcpt_cause_T = mux(use_mem_xcpt, mem_xcpt_cause, UInt<5>(0h10)) connect r_xcpt.cause, _r_xcpt_cause_T connect r_xcpt.badvaddr, mem_xcpt_vaddr node _io_core_lxcpt_valid_T = and(io.core.brupdate.b1.mispredict_mask, r_xcpt.uop.br_mask) node _io_core_lxcpt_valid_T_1 = neq(_io_core_lxcpt_valid_T, UInt<1>(0h0)) node _io_core_lxcpt_valid_T_2 = or(_io_core_lxcpt_valid_T_1, io.core.exception) node _io_core_lxcpt_valid_T_3 = eq(_io_core_lxcpt_valid_T_2, UInt<1>(0h0)) node _io_core_lxcpt_valid_T_4 = and(r_xcpt_valid, _io_core_lxcpt_valid_T_3) connect io.core.lxcpt.valid, _io_core_lxcpt_valid_T_4 connect io.core.lxcpt.bits, r_xcpt reg wakeupArbs_0_io_in_1_valid_REG : UInt<1>, clock connect wakeupArbs_0_io_in_1_valid_REG, dmem_req_fire[0] node _wakeupArbs_0_io_in_1_valid_T = and(fired_load_agen_exec[0], wakeupArbs_0_io_in_1_valid_REG) node _wakeupArbs_0_io_in_1_valid_T_1 = eq(io.dmem.s1_nack_advisory[0], UInt<1>(0h0)) node _wakeupArbs_0_io_in_1_valid_T_2 = and(_wakeupArbs_0_io_in_1_valid_T, _wakeupArbs_0_io_in_1_valid_T_1) node _wakeupArbs_0_io_in_1_valid_T_3 = eq(mem_incoming_uop[0].fp_val, UInt<1>(0h0)) node _wakeupArbs_0_io_in_1_valid_T_4 = and(_wakeupArbs_0_io_in_1_valid_T_2, _wakeupArbs_0_io_in_1_valid_T_3) connect wakeupArbs_0.io.in[1].valid, _wakeupArbs_0_io_in_1_valid_T_4 connect wakeupArbs_0.io.in[1].bits.uop.debug_tsrc, mem_incoming_uop[0].debug_tsrc connect wakeupArbs_0.io.in[1].bits.uop.debug_fsrc, mem_incoming_uop[0].debug_fsrc connect wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if, mem_incoming_uop[0].bp_xcpt_if connect wakeupArbs_0.io.in[1].bits.uop.bp_debug_if, mem_incoming_uop[0].bp_debug_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if, mem_incoming_uop[0].xcpt_ma_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if, mem_incoming_uop[0].xcpt_ae_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if, mem_incoming_uop[0].xcpt_pf_if connect wakeupArbs_0.io.in[1].bits.uop.fp_typ, mem_incoming_uop[0].fp_typ connect wakeupArbs_0.io.in[1].bits.uop.fp_rm, mem_incoming_uop[0].fp_rm connect wakeupArbs_0.io.in[1].bits.uop.fp_val, mem_incoming_uop[0].fp_val connect wakeupArbs_0.io.in[1].bits.uop.fcn_op, mem_incoming_uop[0].fcn_op connect wakeupArbs_0.io.in[1].bits.uop.fcn_dw, mem_incoming_uop[0].fcn_dw connect wakeupArbs_0.io.in[1].bits.uop.frs3_en, mem_incoming_uop[0].frs3_en connect wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype, mem_incoming_uop[0].lrs2_rtype connect wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype, mem_incoming_uop[0].lrs1_rtype connect wakeupArbs_0.io.in[1].bits.uop.dst_rtype, mem_incoming_uop[0].dst_rtype connect wakeupArbs_0.io.in[1].bits.uop.lrs3, mem_incoming_uop[0].lrs3 connect wakeupArbs_0.io.in[1].bits.uop.lrs2, mem_incoming_uop[0].lrs2 connect wakeupArbs_0.io.in[1].bits.uop.lrs1, mem_incoming_uop[0].lrs1 connect wakeupArbs_0.io.in[1].bits.uop.ldst, mem_incoming_uop[0].ldst connect wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1, mem_incoming_uop[0].ldst_is_rs1 connect wakeupArbs_0.io.in[1].bits.uop.csr_cmd, mem_incoming_uop[0].csr_cmd connect wakeupArbs_0.io.in[1].bits.uop.flush_on_commit, mem_incoming_uop[0].flush_on_commit connect wakeupArbs_0.io.in[1].bits.uop.is_unique, mem_incoming_uop[0].is_unique connect wakeupArbs_0.io.in[1].bits.uop.uses_stq, mem_incoming_uop[0].uses_stq connect wakeupArbs_0.io.in[1].bits.uop.uses_ldq, mem_incoming_uop[0].uses_ldq connect wakeupArbs_0.io.in[1].bits.uop.mem_signed, mem_incoming_uop[0].mem_signed connect wakeupArbs_0.io.in[1].bits.uop.mem_size, mem_incoming_uop[0].mem_size connect wakeupArbs_0.io.in[1].bits.uop.mem_cmd, mem_incoming_uop[0].mem_cmd connect wakeupArbs_0.io.in[1].bits.uop.exc_cause, mem_incoming_uop[0].exc_cause connect wakeupArbs_0.io.in[1].bits.uop.exception, mem_incoming_uop[0].exception connect wakeupArbs_0.io.in[1].bits.uop.stale_pdst, mem_incoming_uop[0].stale_pdst connect wakeupArbs_0.io.in[1].bits.uop.ppred_busy, mem_incoming_uop[0].ppred_busy connect wakeupArbs_0.io.in[1].bits.uop.prs3_busy, mem_incoming_uop[0].prs3_busy connect wakeupArbs_0.io.in[1].bits.uop.prs2_busy, mem_incoming_uop[0].prs2_busy connect wakeupArbs_0.io.in[1].bits.uop.prs1_busy, mem_incoming_uop[0].prs1_busy connect wakeupArbs_0.io.in[1].bits.uop.ppred, mem_incoming_uop[0].ppred connect wakeupArbs_0.io.in[1].bits.uop.prs3, mem_incoming_uop[0].prs3 connect wakeupArbs_0.io.in[1].bits.uop.prs2, mem_incoming_uop[0].prs2 connect wakeupArbs_0.io.in[1].bits.uop.prs1, mem_incoming_uop[0].prs1 connect wakeupArbs_0.io.in[1].bits.uop.pdst, mem_incoming_uop[0].pdst connect wakeupArbs_0.io.in[1].bits.uop.rxq_idx, mem_incoming_uop[0].rxq_idx connect wakeupArbs_0.io.in[1].bits.uop.stq_idx, mem_incoming_uop[0].stq_idx connect wakeupArbs_0.io.in[1].bits.uop.ldq_idx, mem_incoming_uop[0].ldq_idx connect wakeupArbs_0.io.in[1].bits.uop.rob_idx, mem_incoming_uop[0].rob_idx connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec, mem_incoming_uop[0].fp_ctrl.vec connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags, mem_incoming_uop[0].fp_ctrl.wflags connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt, mem_incoming_uop[0].fp_ctrl.sqrt connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div, mem_incoming_uop[0].fp_ctrl.div connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma, mem_incoming_uop[0].fp_ctrl.fma connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe, mem_incoming_uop[0].fp_ctrl.fastpipe connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint, mem_incoming_uop[0].fp_ctrl.toint connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint, mem_incoming_uop[0].fp_ctrl.fromint connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut, mem_incoming_uop[0].fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn, mem_incoming_uop[0].fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23, mem_incoming_uop[0].fp_ctrl.swap23 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12, mem_incoming_uop[0].fp_ctrl.swap12 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3, mem_incoming_uop[0].fp_ctrl.ren3 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2, mem_incoming_uop[0].fp_ctrl.ren2 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1, mem_incoming_uop[0].fp_ctrl.ren1 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen, mem_incoming_uop[0].fp_ctrl.wen connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst, mem_incoming_uop[0].fp_ctrl.ldst connect wakeupArbs_0.io.in[1].bits.uop.op2_sel, mem_incoming_uop[0].op2_sel connect wakeupArbs_0.io.in[1].bits.uop.op1_sel, mem_incoming_uop[0].op1_sel connect wakeupArbs_0.io.in[1].bits.uop.imm_packed, mem_incoming_uop[0].imm_packed connect wakeupArbs_0.io.in[1].bits.uop.pimm, mem_incoming_uop[0].pimm connect wakeupArbs_0.io.in[1].bits.uop.imm_sel, mem_incoming_uop[0].imm_sel connect wakeupArbs_0.io.in[1].bits.uop.imm_rename, mem_incoming_uop[0].imm_rename connect wakeupArbs_0.io.in[1].bits.uop.taken, mem_incoming_uop[0].taken connect wakeupArbs_0.io.in[1].bits.uop.pc_lob, mem_incoming_uop[0].pc_lob connect wakeupArbs_0.io.in[1].bits.uop.edge_inst, mem_incoming_uop[0].edge_inst connect wakeupArbs_0.io.in[1].bits.uop.ftq_idx, mem_incoming_uop[0].ftq_idx connect wakeupArbs_0.io.in[1].bits.uop.is_mov, mem_incoming_uop[0].is_mov connect wakeupArbs_0.io.in[1].bits.uop.is_rocc, mem_incoming_uop[0].is_rocc connect wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc, mem_incoming_uop[0].is_sys_pc2epc connect wakeupArbs_0.io.in[1].bits.uop.is_eret, mem_incoming_uop[0].is_eret connect wakeupArbs_0.io.in[1].bits.uop.is_amo, mem_incoming_uop[0].is_amo connect wakeupArbs_0.io.in[1].bits.uop.is_sfence, mem_incoming_uop[0].is_sfence connect wakeupArbs_0.io.in[1].bits.uop.is_fencei, mem_incoming_uop[0].is_fencei connect wakeupArbs_0.io.in[1].bits.uop.is_fence, mem_incoming_uop[0].is_fence connect wakeupArbs_0.io.in[1].bits.uop.is_sfb, mem_incoming_uop[0].is_sfb connect wakeupArbs_0.io.in[1].bits.uop.br_type, mem_incoming_uop[0].br_type connect wakeupArbs_0.io.in[1].bits.uop.br_tag, mem_incoming_uop[0].br_tag connect wakeupArbs_0.io.in[1].bits.uop.br_mask, mem_incoming_uop[0].br_mask connect wakeupArbs_0.io.in[1].bits.uop.dis_col_sel, mem_incoming_uop[0].dis_col_sel connect wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint, mem_incoming_uop[0].iw_p3_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint, mem_incoming_uop[0].iw_p2_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint, mem_incoming_uop[0].iw_p1_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child, mem_incoming_uop[0].iw_p2_speculative_child connect wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child, mem_incoming_uop[0].iw_p1_speculative_child connect wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen, mem_incoming_uop[0].iw_issued_partial_dgen connect wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen, mem_incoming_uop[0].iw_issued_partial_agen connect wakeupArbs_0.io.in[1].bits.uop.iw_issued, mem_incoming_uop[0].iw_issued connect wakeupArbs_0.io.in[1].bits.uop.fu_code[0], mem_incoming_uop[0].fu_code[0] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[1], mem_incoming_uop[0].fu_code[1] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[2], mem_incoming_uop[0].fu_code[2] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[3], mem_incoming_uop[0].fu_code[3] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[4], mem_incoming_uop[0].fu_code[4] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[5], mem_incoming_uop[0].fu_code[5] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[6], mem_incoming_uop[0].fu_code[6] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[7], mem_incoming_uop[0].fu_code[7] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[8], mem_incoming_uop[0].fu_code[8] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[9], mem_incoming_uop[0].fu_code[9] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[0], mem_incoming_uop[0].iq_type[0] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[1], mem_incoming_uop[0].iq_type[1] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[2], mem_incoming_uop[0].iq_type[2] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[3], mem_incoming_uop[0].iq_type[3] connect wakeupArbs_0.io.in[1].bits.uop.debug_pc, mem_incoming_uop[0].debug_pc connect wakeupArbs_0.io.in[1].bits.uop.is_rvc, mem_incoming_uop[0].is_rvc connect wakeupArbs_0.io.in[1].bits.uop.debug_inst, mem_incoming_uop[0].debug_inst connect wakeupArbs_0.io.in[1].bits.uop.inst, mem_incoming_uop[0].inst connect wakeupArbs_0.io.in[1].bits.bypassable, UInt<1>(0h1) connect wakeupArbs_0.io.in[1].bits.speculative_mask, UInt<1>(0h0) connect wakeupArbs_0.io.in[1].bits.rebusy, UInt<1>(0h0) wire iresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1] wire fresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1] connect iresp[0].valid, UInt<1>(0h0) invalidate iresp[0].bits.fflags.bits invalidate iresp[0].bits.fflags.valid invalidate iresp[0].bits.predicated invalidate iresp[0].bits.data invalidate iresp[0].bits.uop.debug_tsrc invalidate iresp[0].bits.uop.debug_fsrc invalidate iresp[0].bits.uop.bp_xcpt_if invalidate iresp[0].bits.uop.bp_debug_if invalidate iresp[0].bits.uop.xcpt_ma_if invalidate iresp[0].bits.uop.xcpt_ae_if invalidate iresp[0].bits.uop.xcpt_pf_if invalidate iresp[0].bits.uop.fp_typ invalidate iresp[0].bits.uop.fp_rm invalidate iresp[0].bits.uop.fp_val invalidate iresp[0].bits.uop.fcn_op invalidate iresp[0].bits.uop.fcn_dw invalidate iresp[0].bits.uop.frs3_en invalidate iresp[0].bits.uop.lrs2_rtype invalidate iresp[0].bits.uop.lrs1_rtype invalidate iresp[0].bits.uop.dst_rtype invalidate iresp[0].bits.uop.lrs3 invalidate iresp[0].bits.uop.lrs2 invalidate iresp[0].bits.uop.lrs1 invalidate iresp[0].bits.uop.ldst invalidate iresp[0].bits.uop.ldst_is_rs1 invalidate iresp[0].bits.uop.csr_cmd invalidate iresp[0].bits.uop.flush_on_commit invalidate iresp[0].bits.uop.is_unique invalidate iresp[0].bits.uop.uses_stq invalidate iresp[0].bits.uop.uses_ldq invalidate iresp[0].bits.uop.mem_signed invalidate iresp[0].bits.uop.mem_size invalidate iresp[0].bits.uop.mem_cmd invalidate iresp[0].bits.uop.exc_cause invalidate iresp[0].bits.uop.exception invalidate iresp[0].bits.uop.stale_pdst invalidate iresp[0].bits.uop.ppred_busy invalidate iresp[0].bits.uop.prs3_busy invalidate iresp[0].bits.uop.prs2_busy invalidate iresp[0].bits.uop.prs1_busy invalidate iresp[0].bits.uop.ppred invalidate iresp[0].bits.uop.prs3 invalidate iresp[0].bits.uop.prs2 invalidate iresp[0].bits.uop.prs1 invalidate iresp[0].bits.uop.pdst invalidate iresp[0].bits.uop.rxq_idx invalidate iresp[0].bits.uop.stq_idx invalidate iresp[0].bits.uop.ldq_idx invalidate iresp[0].bits.uop.rob_idx invalidate iresp[0].bits.uop.fp_ctrl.vec invalidate iresp[0].bits.uop.fp_ctrl.wflags invalidate iresp[0].bits.uop.fp_ctrl.sqrt invalidate iresp[0].bits.uop.fp_ctrl.div invalidate iresp[0].bits.uop.fp_ctrl.fma invalidate iresp[0].bits.uop.fp_ctrl.fastpipe invalidate iresp[0].bits.uop.fp_ctrl.toint invalidate iresp[0].bits.uop.fp_ctrl.fromint invalidate iresp[0].bits.uop.fp_ctrl.typeTagOut invalidate iresp[0].bits.uop.fp_ctrl.typeTagIn invalidate iresp[0].bits.uop.fp_ctrl.swap23 invalidate iresp[0].bits.uop.fp_ctrl.swap12 invalidate iresp[0].bits.uop.fp_ctrl.ren3 invalidate iresp[0].bits.uop.fp_ctrl.ren2 invalidate iresp[0].bits.uop.fp_ctrl.ren1 invalidate iresp[0].bits.uop.fp_ctrl.wen invalidate iresp[0].bits.uop.fp_ctrl.ldst invalidate iresp[0].bits.uop.op2_sel invalidate iresp[0].bits.uop.op1_sel invalidate iresp[0].bits.uop.imm_packed invalidate iresp[0].bits.uop.pimm invalidate iresp[0].bits.uop.imm_sel invalidate iresp[0].bits.uop.imm_rename invalidate iresp[0].bits.uop.taken invalidate iresp[0].bits.uop.pc_lob invalidate iresp[0].bits.uop.edge_inst invalidate iresp[0].bits.uop.ftq_idx invalidate iresp[0].bits.uop.is_mov invalidate iresp[0].bits.uop.is_rocc invalidate iresp[0].bits.uop.is_sys_pc2epc invalidate iresp[0].bits.uop.is_eret invalidate iresp[0].bits.uop.is_amo invalidate iresp[0].bits.uop.is_sfence invalidate iresp[0].bits.uop.is_fencei invalidate iresp[0].bits.uop.is_fence invalidate iresp[0].bits.uop.is_sfb invalidate iresp[0].bits.uop.br_type invalidate iresp[0].bits.uop.br_tag invalidate iresp[0].bits.uop.br_mask invalidate iresp[0].bits.uop.dis_col_sel invalidate iresp[0].bits.uop.iw_p3_bypass_hint invalidate iresp[0].bits.uop.iw_p2_bypass_hint invalidate iresp[0].bits.uop.iw_p1_bypass_hint invalidate iresp[0].bits.uop.iw_p2_speculative_child invalidate iresp[0].bits.uop.iw_p1_speculative_child invalidate iresp[0].bits.uop.iw_issued_partial_dgen invalidate iresp[0].bits.uop.iw_issued_partial_agen invalidate iresp[0].bits.uop.iw_issued invalidate iresp[0].bits.uop.fu_code[0] invalidate iresp[0].bits.uop.fu_code[1] invalidate iresp[0].bits.uop.fu_code[2] invalidate iresp[0].bits.uop.fu_code[3] invalidate iresp[0].bits.uop.fu_code[4] invalidate iresp[0].bits.uop.fu_code[5] invalidate iresp[0].bits.uop.fu_code[6] invalidate iresp[0].bits.uop.fu_code[7] invalidate iresp[0].bits.uop.fu_code[8] invalidate iresp[0].bits.uop.fu_code[9] invalidate iresp[0].bits.uop.iq_type[0] invalidate iresp[0].bits.uop.iq_type[1] invalidate iresp[0].bits.uop.iq_type[2] invalidate iresp[0].bits.uop.iq_type[3] invalidate iresp[0].bits.uop.debug_pc invalidate iresp[0].bits.uop.is_rvc invalidate iresp[0].bits.uop.debug_inst invalidate iresp[0].bits.uop.inst connect fresp[0].valid, UInt<1>(0h0) invalidate fresp[0].bits.fflags.bits invalidate fresp[0].bits.fflags.valid invalidate fresp[0].bits.predicated invalidate fresp[0].bits.data invalidate fresp[0].bits.uop.debug_tsrc invalidate fresp[0].bits.uop.debug_fsrc invalidate fresp[0].bits.uop.bp_xcpt_if invalidate fresp[0].bits.uop.bp_debug_if invalidate fresp[0].bits.uop.xcpt_ma_if invalidate fresp[0].bits.uop.xcpt_ae_if invalidate fresp[0].bits.uop.xcpt_pf_if invalidate fresp[0].bits.uop.fp_typ invalidate fresp[0].bits.uop.fp_rm invalidate fresp[0].bits.uop.fp_val invalidate fresp[0].bits.uop.fcn_op invalidate fresp[0].bits.uop.fcn_dw invalidate fresp[0].bits.uop.frs3_en invalidate fresp[0].bits.uop.lrs2_rtype invalidate fresp[0].bits.uop.lrs1_rtype invalidate fresp[0].bits.uop.dst_rtype invalidate fresp[0].bits.uop.lrs3 invalidate fresp[0].bits.uop.lrs2 invalidate fresp[0].bits.uop.lrs1 invalidate fresp[0].bits.uop.ldst invalidate fresp[0].bits.uop.ldst_is_rs1 invalidate fresp[0].bits.uop.csr_cmd invalidate fresp[0].bits.uop.flush_on_commit invalidate fresp[0].bits.uop.is_unique invalidate fresp[0].bits.uop.uses_stq invalidate fresp[0].bits.uop.uses_ldq invalidate fresp[0].bits.uop.mem_signed invalidate fresp[0].bits.uop.mem_size invalidate fresp[0].bits.uop.mem_cmd invalidate fresp[0].bits.uop.exc_cause invalidate fresp[0].bits.uop.exception invalidate fresp[0].bits.uop.stale_pdst invalidate fresp[0].bits.uop.ppred_busy invalidate fresp[0].bits.uop.prs3_busy invalidate fresp[0].bits.uop.prs2_busy invalidate fresp[0].bits.uop.prs1_busy invalidate fresp[0].bits.uop.ppred invalidate fresp[0].bits.uop.prs3 invalidate fresp[0].bits.uop.prs2 invalidate fresp[0].bits.uop.prs1 invalidate fresp[0].bits.uop.pdst invalidate fresp[0].bits.uop.rxq_idx invalidate fresp[0].bits.uop.stq_idx invalidate fresp[0].bits.uop.ldq_idx invalidate fresp[0].bits.uop.rob_idx invalidate fresp[0].bits.uop.fp_ctrl.vec invalidate fresp[0].bits.uop.fp_ctrl.wflags invalidate fresp[0].bits.uop.fp_ctrl.sqrt invalidate fresp[0].bits.uop.fp_ctrl.div invalidate fresp[0].bits.uop.fp_ctrl.fma invalidate fresp[0].bits.uop.fp_ctrl.fastpipe invalidate fresp[0].bits.uop.fp_ctrl.toint invalidate fresp[0].bits.uop.fp_ctrl.fromint invalidate fresp[0].bits.uop.fp_ctrl.typeTagOut invalidate fresp[0].bits.uop.fp_ctrl.typeTagIn invalidate fresp[0].bits.uop.fp_ctrl.swap23 invalidate fresp[0].bits.uop.fp_ctrl.swap12 invalidate fresp[0].bits.uop.fp_ctrl.ren3 invalidate fresp[0].bits.uop.fp_ctrl.ren2 invalidate fresp[0].bits.uop.fp_ctrl.ren1 invalidate fresp[0].bits.uop.fp_ctrl.wen invalidate fresp[0].bits.uop.fp_ctrl.ldst invalidate fresp[0].bits.uop.op2_sel invalidate fresp[0].bits.uop.op1_sel invalidate fresp[0].bits.uop.imm_packed invalidate fresp[0].bits.uop.pimm invalidate fresp[0].bits.uop.imm_sel invalidate fresp[0].bits.uop.imm_rename invalidate fresp[0].bits.uop.taken invalidate fresp[0].bits.uop.pc_lob invalidate fresp[0].bits.uop.edge_inst invalidate fresp[0].bits.uop.ftq_idx invalidate fresp[0].bits.uop.is_mov invalidate fresp[0].bits.uop.is_rocc invalidate fresp[0].bits.uop.is_sys_pc2epc invalidate fresp[0].bits.uop.is_eret invalidate fresp[0].bits.uop.is_amo invalidate fresp[0].bits.uop.is_sfence invalidate fresp[0].bits.uop.is_fencei invalidate fresp[0].bits.uop.is_fence invalidate fresp[0].bits.uop.is_sfb invalidate fresp[0].bits.uop.br_type invalidate fresp[0].bits.uop.br_tag invalidate fresp[0].bits.uop.br_mask invalidate fresp[0].bits.uop.dis_col_sel invalidate fresp[0].bits.uop.iw_p3_bypass_hint invalidate fresp[0].bits.uop.iw_p2_bypass_hint invalidate fresp[0].bits.uop.iw_p1_bypass_hint invalidate fresp[0].bits.uop.iw_p2_speculative_child invalidate fresp[0].bits.uop.iw_p1_speculative_child invalidate fresp[0].bits.uop.iw_issued_partial_dgen invalidate fresp[0].bits.uop.iw_issued_partial_agen invalidate fresp[0].bits.uop.iw_issued invalidate fresp[0].bits.uop.fu_code[0] invalidate fresp[0].bits.uop.fu_code[1] invalidate fresp[0].bits.uop.fu_code[2] invalidate fresp[0].bits.uop.fu_code[3] invalidate fresp[0].bits.uop.fu_code[4] invalidate fresp[0].bits.uop.fu_code[5] invalidate fresp[0].bits.uop.fu_code[6] invalidate fresp[0].bits.uop.fu_code[7] invalidate fresp[0].bits.uop.fu_code[8] invalidate fresp[0].bits.uop.fu_code[9] invalidate fresp[0].bits.uop.iq_type[0] invalidate fresp[0].bits.uop.iq_type[1] invalidate fresp[0].bits.uop.iq_type[2] invalidate fresp[0].bits.uop.iq_type[3] invalidate fresp[0].bits.uop.debug_pc invalidate fresp[0].bits.uop.is_rvc invalidate fresp[0].bits.uop.debug_inst invalidate fresp[0].bits.uop.inst wire io_core_iresp_0_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}} connect io_core_iresp_0_out, iresp[0] node _io_core_iresp_0_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _io_core_iresp_0_out_bits_uop_br_mask_T_1 = and(iresp[0].bits.uop.br_mask, _io_core_iresp_0_out_bits_uop_br_mask_T) connect io_core_iresp_0_out.bits.uop.br_mask, _io_core_iresp_0_out_bits_uop_br_mask_T_1 node _io_core_iresp_0_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, iresp[0].bits.uop.br_mask) node _io_core_iresp_0_out_valid_T_1 = neq(_io_core_iresp_0_out_valid_T, UInt<1>(0h0)) node _io_core_iresp_0_out_valid_T_2 = or(_io_core_iresp_0_out_valid_T_1, io.core.exception) node _io_core_iresp_0_out_valid_T_3 = eq(_io_core_iresp_0_out_valid_T_2, UInt<1>(0h0)) node _io_core_iresp_0_out_valid_T_4 = and(iresp[0].valid, _io_core_iresp_0_out_valid_T_3) connect io_core_iresp_0_out.valid, _io_core_iresp_0_out_valid_T_4 reg io_core_iresp_0_REG : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, clock connect io_core_iresp_0_REG, io_core_iresp_0_out connect io.core.iresp[0], io_core_iresp_0_REG connect io.core.fresp[0], fresp[0] wire wb_spec_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire spec_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire wb_slow_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire slow_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire _dmem_resp_fired_WIRE : UInt<1>[1] connect _dmem_resp_fired_WIRE[0], UInt<1>(0h0) wire dmem_resp_fired : UInt<1>[1] connect dmem_resp_fired, _dmem_resp_fired_WIRE reg w1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock node _w1_valid_T = and(wakeupArbs_0.io.in[1].ready, wakeupArbs_0.io.in[1].valid) node _w1_valid_T_1 = and(io.core.brupdate.b1.mispredict_mask, wakeupArbs_0.io.in[1].bits.uop.br_mask) node _w1_valid_T_2 = neq(_w1_valid_T_1, UInt<1>(0h0)) node _w1_valid_T_3 = or(_w1_valid_T_2, io.core.exception) node _w1_valid_T_4 = eq(_w1_valid_T_3, UInt<1>(0h0)) node _w1_valid_T_5 = and(_w1_valid_T, _w1_valid_T_4) connect w1.valid, _w1_valid_T_5 wire w1_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>} connect w1_bits_out.rebusy, wakeupArbs_0.io.in[1].bits.rebusy connect w1_bits_out.speculative_mask, wakeupArbs_0.io.in[1].bits.speculative_mask connect w1_bits_out.bypassable, wakeupArbs_0.io.in[1].bits.bypassable connect w1_bits_out.uop.debug_tsrc, wakeupArbs_0.io.in[1].bits.uop.debug_tsrc connect w1_bits_out.uop.debug_fsrc, wakeupArbs_0.io.in[1].bits.uop.debug_fsrc connect w1_bits_out.uop.bp_xcpt_if, wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if connect w1_bits_out.uop.bp_debug_if, wakeupArbs_0.io.in[1].bits.uop.bp_debug_if connect w1_bits_out.uop.xcpt_ma_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if connect w1_bits_out.uop.xcpt_ae_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if connect w1_bits_out.uop.xcpt_pf_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if connect w1_bits_out.uop.fp_typ, wakeupArbs_0.io.in[1].bits.uop.fp_typ connect w1_bits_out.uop.fp_rm, wakeupArbs_0.io.in[1].bits.uop.fp_rm connect w1_bits_out.uop.fp_val, wakeupArbs_0.io.in[1].bits.uop.fp_val connect w1_bits_out.uop.fcn_op, wakeupArbs_0.io.in[1].bits.uop.fcn_op connect w1_bits_out.uop.fcn_dw, wakeupArbs_0.io.in[1].bits.uop.fcn_dw connect w1_bits_out.uop.frs3_en, wakeupArbs_0.io.in[1].bits.uop.frs3_en connect w1_bits_out.uop.lrs2_rtype, wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype connect w1_bits_out.uop.lrs1_rtype, wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype connect w1_bits_out.uop.dst_rtype, wakeupArbs_0.io.in[1].bits.uop.dst_rtype connect w1_bits_out.uop.lrs3, wakeupArbs_0.io.in[1].bits.uop.lrs3 connect w1_bits_out.uop.lrs2, wakeupArbs_0.io.in[1].bits.uop.lrs2 connect w1_bits_out.uop.lrs1, wakeupArbs_0.io.in[1].bits.uop.lrs1 connect w1_bits_out.uop.ldst, wakeupArbs_0.io.in[1].bits.uop.ldst connect w1_bits_out.uop.ldst_is_rs1, wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1 connect w1_bits_out.uop.csr_cmd, wakeupArbs_0.io.in[1].bits.uop.csr_cmd connect w1_bits_out.uop.flush_on_commit, wakeupArbs_0.io.in[1].bits.uop.flush_on_commit connect w1_bits_out.uop.is_unique, wakeupArbs_0.io.in[1].bits.uop.is_unique connect w1_bits_out.uop.uses_stq, wakeupArbs_0.io.in[1].bits.uop.uses_stq connect w1_bits_out.uop.uses_ldq, wakeupArbs_0.io.in[1].bits.uop.uses_ldq connect w1_bits_out.uop.mem_signed, wakeupArbs_0.io.in[1].bits.uop.mem_signed connect w1_bits_out.uop.mem_size, wakeupArbs_0.io.in[1].bits.uop.mem_size connect w1_bits_out.uop.mem_cmd, wakeupArbs_0.io.in[1].bits.uop.mem_cmd connect w1_bits_out.uop.exc_cause, wakeupArbs_0.io.in[1].bits.uop.exc_cause connect w1_bits_out.uop.exception, wakeupArbs_0.io.in[1].bits.uop.exception connect w1_bits_out.uop.stale_pdst, wakeupArbs_0.io.in[1].bits.uop.stale_pdst connect w1_bits_out.uop.ppred_busy, wakeupArbs_0.io.in[1].bits.uop.ppred_busy connect w1_bits_out.uop.prs3_busy, wakeupArbs_0.io.in[1].bits.uop.prs3_busy connect w1_bits_out.uop.prs2_busy, wakeupArbs_0.io.in[1].bits.uop.prs2_busy connect w1_bits_out.uop.prs1_busy, wakeupArbs_0.io.in[1].bits.uop.prs1_busy connect w1_bits_out.uop.ppred, wakeupArbs_0.io.in[1].bits.uop.ppred connect w1_bits_out.uop.prs3, wakeupArbs_0.io.in[1].bits.uop.prs3 connect w1_bits_out.uop.prs2, wakeupArbs_0.io.in[1].bits.uop.prs2 connect w1_bits_out.uop.prs1, wakeupArbs_0.io.in[1].bits.uop.prs1 connect w1_bits_out.uop.pdst, wakeupArbs_0.io.in[1].bits.uop.pdst connect w1_bits_out.uop.rxq_idx, wakeupArbs_0.io.in[1].bits.uop.rxq_idx connect w1_bits_out.uop.stq_idx, wakeupArbs_0.io.in[1].bits.uop.stq_idx connect w1_bits_out.uop.ldq_idx, wakeupArbs_0.io.in[1].bits.uop.ldq_idx connect w1_bits_out.uop.rob_idx, wakeupArbs_0.io.in[1].bits.uop.rob_idx connect w1_bits_out.uop.fp_ctrl.vec, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec connect w1_bits_out.uop.fp_ctrl.wflags, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags connect w1_bits_out.uop.fp_ctrl.sqrt, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt connect w1_bits_out.uop.fp_ctrl.div, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div connect w1_bits_out.uop.fp_ctrl.fma, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma connect w1_bits_out.uop.fp_ctrl.fastpipe, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe connect w1_bits_out.uop.fp_ctrl.toint, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint connect w1_bits_out.uop.fp_ctrl.fromint, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint connect w1_bits_out.uop.fp_ctrl.typeTagOut, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut connect w1_bits_out.uop.fp_ctrl.typeTagIn, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn connect w1_bits_out.uop.fp_ctrl.swap23, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23 connect w1_bits_out.uop.fp_ctrl.swap12, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12 connect w1_bits_out.uop.fp_ctrl.ren3, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3 connect w1_bits_out.uop.fp_ctrl.ren2, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2 connect w1_bits_out.uop.fp_ctrl.ren1, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1 connect w1_bits_out.uop.fp_ctrl.wen, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen connect w1_bits_out.uop.fp_ctrl.ldst, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst connect w1_bits_out.uop.op2_sel, wakeupArbs_0.io.in[1].bits.uop.op2_sel connect w1_bits_out.uop.op1_sel, wakeupArbs_0.io.in[1].bits.uop.op1_sel connect w1_bits_out.uop.imm_packed, wakeupArbs_0.io.in[1].bits.uop.imm_packed connect w1_bits_out.uop.pimm, wakeupArbs_0.io.in[1].bits.uop.pimm connect w1_bits_out.uop.imm_sel, wakeupArbs_0.io.in[1].bits.uop.imm_sel connect w1_bits_out.uop.imm_rename, wakeupArbs_0.io.in[1].bits.uop.imm_rename connect w1_bits_out.uop.taken, wakeupArbs_0.io.in[1].bits.uop.taken connect w1_bits_out.uop.pc_lob, wakeupArbs_0.io.in[1].bits.uop.pc_lob connect w1_bits_out.uop.edge_inst, wakeupArbs_0.io.in[1].bits.uop.edge_inst connect w1_bits_out.uop.ftq_idx, wakeupArbs_0.io.in[1].bits.uop.ftq_idx connect w1_bits_out.uop.is_mov, wakeupArbs_0.io.in[1].bits.uop.is_mov connect w1_bits_out.uop.is_rocc, wakeupArbs_0.io.in[1].bits.uop.is_rocc connect w1_bits_out.uop.is_sys_pc2epc, wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc connect w1_bits_out.uop.is_eret, wakeupArbs_0.io.in[1].bits.uop.is_eret connect w1_bits_out.uop.is_amo, wakeupArbs_0.io.in[1].bits.uop.is_amo connect w1_bits_out.uop.is_sfence, wakeupArbs_0.io.in[1].bits.uop.is_sfence connect w1_bits_out.uop.is_fencei, wakeupArbs_0.io.in[1].bits.uop.is_fencei connect w1_bits_out.uop.is_fence, wakeupArbs_0.io.in[1].bits.uop.is_fence connect w1_bits_out.uop.is_sfb, wakeupArbs_0.io.in[1].bits.uop.is_sfb connect w1_bits_out.uop.br_type, wakeupArbs_0.io.in[1].bits.uop.br_type connect w1_bits_out.uop.br_tag, wakeupArbs_0.io.in[1].bits.uop.br_tag connect w1_bits_out.uop.br_mask, wakeupArbs_0.io.in[1].bits.uop.br_mask connect w1_bits_out.uop.dis_col_sel, wakeupArbs_0.io.in[1].bits.uop.dis_col_sel connect w1_bits_out.uop.iw_p3_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint connect w1_bits_out.uop.iw_p2_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint connect w1_bits_out.uop.iw_p1_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint connect w1_bits_out.uop.iw_p2_speculative_child, wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child connect w1_bits_out.uop.iw_p1_speculative_child, wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child connect w1_bits_out.uop.iw_issued_partial_dgen, wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen connect w1_bits_out.uop.iw_issued_partial_agen, wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen connect w1_bits_out.uop.iw_issued, wakeupArbs_0.io.in[1].bits.uop.iw_issued connect w1_bits_out.uop.fu_code[0], wakeupArbs_0.io.in[1].bits.uop.fu_code[0] connect w1_bits_out.uop.fu_code[1], wakeupArbs_0.io.in[1].bits.uop.fu_code[1] connect w1_bits_out.uop.fu_code[2], wakeupArbs_0.io.in[1].bits.uop.fu_code[2] connect w1_bits_out.uop.fu_code[3], wakeupArbs_0.io.in[1].bits.uop.fu_code[3] connect w1_bits_out.uop.fu_code[4], wakeupArbs_0.io.in[1].bits.uop.fu_code[4] connect w1_bits_out.uop.fu_code[5], wakeupArbs_0.io.in[1].bits.uop.fu_code[5] connect w1_bits_out.uop.fu_code[6], wakeupArbs_0.io.in[1].bits.uop.fu_code[6] connect w1_bits_out.uop.fu_code[7], wakeupArbs_0.io.in[1].bits.uop.fu_code[7] connect w1_bits_out.uop.fu_code[8], wakeupArbs_0.io.in[1].bits.uop.fu_code[8] connect w1_bits_out.uop.fu_code[9], wakeupArbs_0.io.in[1].bits.uop.fu_code[9] connect w1_bits_out.uop.iq_type[0], wakeupArbs_0.io.in[1].bits.uop.iq_type[0] connect w1_bits_out.uop.iq_type[1], wakeupArbs_0.io.in[1].bits.uop.iq_type[1] connect w1_bits_out.uop.iq_type[2], wakeupArbs_0.io.in[1].bits.uop.iq_type[2] connect w1_bits_out.uop.iq_type[3], wakeupArbs_0.io.in[1].bits.uop.iq_type[3] connect w1_bits_out.uop.debug_pc, wakeupArbs_0.io.in[1].bits.uop.debug_pc connect w1_bits_out.uop.is_rvc, wakeupArbs_0.io.in[1].bits.uop.is_rvc connect w1_bits_out.uop.debug_inst, wakeupArbs_0.io.in[1].bits.uop.debug_inst connect w1_bits_out.uop.inst, wakeupArbs_0.io.in[1].bits.uop.inst node _w1_bits_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _w1_bits_out_uop_br_mask_T_1 = and(wakeupArbs_0.io.in[1].bits.uop.br_mask, _w1_bits_out_uop_br_mask_T) connect w1_bits_out.uop.br_mask, _w1_bits_out_uop_br_mask_T_1 connect w1.bits, w1_bits_out reg w2 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock node _w2_valid_T = and(io.core.brupdate.b1.mispredict_mask, w1.bits.uop.br_mask) node _w2_valid_T_1 = neq(_w2_valid_T, UInt<1>(0h0)) node _w2_valid_T_2 = or(_w2_valid_T_1, io.core.exception) node _w2_valid_T_3 = eq(_w2_valid_T_2, UInt<1>(0h0)) node _w2_valid_T_4 = and(w1.valid, _w2_valid_T_3) connect w2.valid, _w2_valid_T_4 wire w2_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>} connect w2_bits_out, w1.bits node _w2_bits_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _w2_bits_out_uop_br_mask_T_1 = and(w1.bits.uop.br_mask, _w2_bits_out_uop_br_mask_T) connect w2_bits_out.uop.br_mask, _w2_bits_out_uop_br_mask_T_1 connect w2.bits, w2_bits_out connect spec_wakeups[0].valid, w2.valid connect spec_wakeups[0].bits, w2.bits connect wb_spec_wakeups[0], w1 connect wb_slow_wakeups[0].valid, UInt<1>(0h0) invalidate wb_slow_wakeups[0].bits.rebusy invalidate wb_slow_wakeups[0].bits.speculative_mask invalidate wb_slow_wakeups[0].bits.bypassable invalidate wb_slow_wakeups[0].bits.uop.debug_tsrc invalidate wb_slow_wakeups[0].bits.uop.debug_fsrc invalidate wb_slow_wakeups[0].bits.uop.bp_xcpt_if invalidate wb_slow_wakeups[0].bits.uop.bp_debug_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_ma_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_ae_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_pf_if invalidate wb_slow_wakeups[0].bits.uop.fp_typ invalidate wb_slow_wakeups[0].bits.uop.fp_rm invalidate wb_slow_wakeups[0].bits.uop.fp_val invalidate wb_slow_wakeups[0].bits.uop.fcn_op invalidate wb_slow_wakeups[0].bits.uop.fcn_dw invalidate wb_slow_wakeups[0].bits.uop.frs3_en invalidate wb_slow_wakeups[0].bits.uop.lrs2_rtype invalidate wb_slow_wakeups[0].bits.uop.lrs1_rtype invalidate wb_slow_wakeups[0].bits.uop.dst_rtype invalidate wb_slow_wakeups[0].bits.uop.lrs3 invalidate wb_slow_wakeups[0].bits.uop.lrs2 invalidate wb_slow_wakeups[0].bits.uop.lrs1 invalidate wb_slow_wakeups[0].bits.uop.ldst invalidate wb_slow_wakeups[0].bits.uop.ldst_is_rs1 invalidate wb_slow_wakeups[0].bits.uop.csr_cmd invalidate wb_slow_wakeups[0].bits.uop.flush_on_commit invalidate wb_slow_wakeups[0].bits.uop.is_unique invalidate wb_slow_wakeups[0].bits.uop.uses_stq invalidate wb_slow_wakeups[0].bits.uop.uses_ldq invalidate wb_slow_wakeups[0].bits.uop.mem_signed invalidate wb_slow_wakeups[0].bits.uop.mem_size invalidate wb_slow_wakeups[0].bits.uop.mem_cmd invalidate wb_slow_wakeups[0].bits.uop.exc_cause invalidate wb_slow_wakeups[0].bits.uop.exception invalidate wb_slow_wakeups[0].bits.uop.stale_pdst invalidate wb_slow_wakeups[0].bits.uop.ppred_busy invalidate wb_slow_wakeups[0].bits.uop.prs3_busy invalidate wb_slow_wakeups[0].bits.uop.prs2_busy invalidate wb_slow_wakeups[0].bits.uop.prs1_busy invalidate wb_slow_wakeups[0].bits.uop.ppred invalidate wb_slow_wakeups[0].bits.uop.prs3 invalidate wb_slow_wakeups[0].bits.uop.prs2 invalidate wb_slow_wakeups[0].bits.uop.prs1 invalidate wb_slow_wakeups[0].bits.uop.pdst invalidate wb_slow_wakeups[0].bits.uop.rxq_idx invalidate wb_slow_wakeups[0].bits.uop.stq_idx invalidate wb_slow_wakeups[0].bits.uop.ldq_idx invalidate wb_slow_wakeups[0].bits.uop.rob_idx invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.vec invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.wflags invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.sqrt invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.div invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fma invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fastpipe invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.toint invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fromint invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.typeTagOut invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.typeTagIn invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.swap23 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.swap12 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren3 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren2 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren1 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.wen invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ldst invalidate wb_slow_wakeups[0].bits.uop.op2_sel invalidate wb_slow_wakeups[0].bits.uop.op1_sel invalidate wb_slow_wakeups[0].bits.uop.imm_packed invalidate wb_slow_wakeups[0].bits.uop.pimm invalidate wb_slow_wakeups[0].bits.uop.imm_sel invalidate wb_slow_wakeups[0].bits.uop.imm_rename invalidate wb_slow_wakeups[0].bits.uop.taken invalidate wb_slow_wakeups[0].bits.uop.pc_lob invalidate wb_slow_wakeups[0].bits.uop.edge_inst invalidate wb_slow_wakeups[0].bits.uop.ftq_idx invalidate wb_slow_wakeups[0].bits.uop.is_mov invalidate wb_slow_wakeups[0].bits.uop.is_rocc invalidate wb_slow_wakeups[0].bits.uop.is_sys_pc2epc invalidate wb_slow_wakeups[0].bits.uop.is_eret invalidate wb_slow_wakeups[0].bits.uop.is_amo invalidate wb_slow_wakeups[0].bits.uop.is_sfence invalidate wb_slow_wakeups[0].bits.uop.is_fencei invalidate wb_slow_wakeups[0].bits.uop.is_fence invalidate wb_slow_wakeups[0].bits.uop.is_sfb invalidate wb_slow_wakeups[0].bits.uop.br_type invalidate wb_slow_wakeups[0].bits.uop.br_tag invalidate wb_slow_wakeups[0].bits.uop.br_mask invalidate wb_slow_wakeups[0].bits.uop.dis_col_sel invalidate wb_slow_wakeups[0].bits.uop.iw_p3_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p2_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p1_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p2_speculative_child invalidate wb_slow_wakeups[0].bits.uop.iw_p1_speculative_child invalidate wb_slow_wakeups[0].bits.uop.iw_issued_partial_dgen invalidate wb_slow_wakeups[0].bits.uop.iw_issued_partial_agen invalidate wb_slow_wakeups[0].bits.uop.iw_issued invalidate wb_slow_wakeups[0].bits.uop.fu_code[0] invalidate wb_slow_wakeups[0].bits.uop.fu_code[1] invalidate wb_slow_wakeups[0].bits.uop.fu_code[2] invalidate wb_slow_wakeups[0].bits.uop.fu_code[3] invalidate wb_slow_wakeups[0].bits.uop.fu_code[4] invalidate wb_slow_wakeups[0].bits.uop.fu_code[5] invalidate wb_slow_wakeups[0].bits.uop.fu_code[6] invalidate wb_slow_wakeups[0].bits.uop.fu_code[7] invalidate wb_slow_wakeups[0].bits.uop.fu_code[8] invalidate wb_slow_wakeups[0].bits.uop.fu_code[9] invalidate wb_slow_wakeups[0].bits.uop.iq_type[0] invalidate wb_slow_wakeups[0].bits.uop.iq_type[1] invalidate wb_slow_wakeups[0].bits.uop.iq_type[2] invalidate wb_slow_wakeups[0].bits.uop.iq_type[3] invalidate wb_slow_wakeups[0].bits.uop.debug_pc invalidate wb_slow_wakeups[0].bits.uop.is_rvc invalidate wb_slow_wakeups[0].bits.uop.debug_inst invalidate wb_slow_wakeups[0].bits.uop.inst when io.dmem.nack[0].valid : when io.dmem.nack[0].bits.is_hella : node _T_1643 = eq(hella_state, UInt<3>(0h4)) node _T_1644 = eq(hella_state, UInt<3>(0h6)) node _T_1645 = or(_T_1643, _T_1644) node _T_1646 = asUInt(reset) node _T_1647 = eq(_T_1646, UInt<1>(0h0)) when _T_1647 : node _T_1648 = eq(_T_1645, UInt<1>(0h0)) when _T_1648 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1521 assert(hella_state === h_wait \|\| hella_state === h_dead)\n") : printf_80 assert(clock, _T_1645, UInt<1>(0h1), "") : assert_80 else : when io.dmem.nack[0].bits.uop.uses_ldq : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1523 assert(ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx))\n") : printf_81 assert(clock, ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h1), "") : assert_81 connect ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h0) else : node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1526 assert(io.dmem.nack(w).bits.uop.uses_stq)\n") : printf_82 assert(clock, io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h1), "") : assert_82 node _T_1655 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_execute_head) node _T_1656 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_head) node _T_1657 = xor(_T_1655, _T_1656) node _T_1658 = lt(stq_execute_head, stq_head) node _T_1659 = xor(_T_1657, _T_1658) when _T_1659 : connect stq_execute_queue_flush, UInt<1>(0h1) connect stq_execute_head, io.dmem.nack[0].bits.uop.stq_idx node _resp_T = eq(io.dmem.resp[0].valid, UInt<1>(0h0)) node _resp_T_1 = and(_resp_T, UInt<1>(0h1)) node resp = mux(_resp_T_1, io.dmem.ll_resp.bits, io.dmem.resp[0].bits) node _io_dmem_ll_resp_ready_T = eq(io.dmem.resp[0].valid, UInt<1>(0h0)) node _io_dmem_ll_resp_ready_T_1 = eq(wb_spec_wakeups[0].valid, UInt<1>(0h0)) node _io_dmem_ll_resp_ready_T_2 = and(_io_dmem_ll_resp_ready_T, _io_dmem_ll_resp_ready_T_1) connect io.dmem.ll_resp.ready, _io_dmem_ll_resp_ready_T_2 node _T_1660 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_1661 = and(UInt<1>(0h1), _T_1660) node _T_1662 = or(io.dmem.resp[0].valid, _T_1661) when _T_1662 : when resp.uop.uses_ldq : node _T_1663 = eq(resp.is_hella, UInt<1>(0h0)) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1541 assert(!resp.is_hella)\n") : printf_83 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_83 wire uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop, ldq_uop[resp.uop.ldq_idx] node send_iresp = eq(uop.dst_rtype, UInt<2>(0h0)) node send_fresp = eq(uop.dst_rtype, UInt<2>(0h1)) connect iresp[0].bits.uop, uop connect fresp[0].bits.uop, uop connect iresp[0].valid, send_iresp connect iresp[0].bits.data, resp.data connect fresp[0].valid, send_fresp connect fresp[0].bits.data, resp.data node _T_1667 = xor(send_iresp, send_fresp) node _T_1668 = asUInt(reset) node _T_1669 = eq(_T_1668, UInt<1>(0h0)) when _T_1669 : node _T_1670 = eq(_T_1667, UInt<1>(0h0)) when _T_1670 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1557 assert(send_iresp ^ send_fresp)\n") : printf_84 assert(clock, _T_1667, UInt<1>(0h1), "") : assert_84 connect dmem_resp_fired[0], UInt<1>(0h1) node _ldq_will_succeed_T = or(iresp[0].valid, fresp[0].valid) connect ldq_will_succeed[resp.uop.ldq_idx], _ldq_will_succeed_T connect ldq_debug_wb_data[resp.uop.ldq_idx], resp.data connect wb_slow_wakeups[0].valid, send_iresp connect wb_slow_wakeups[0].bits.uop, uop connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) when resp.uop.uses_stq : node _T_1671 = eq(resp.is_hella, UInt<1>(0h0)) node _T_1672 = and(_T_1671, resp.uop.is_amo) node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(_T_1672, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1573 assert(!resp.is_hella && resp.uop.is_amo)\n") : printf_85 assert(clock, _T_1672, UInt<1>(0h1), "") : assert_85 connect dmem_resp_fired[0], UInt<1>(0h1) connect iresp[0].valid, UInt<1>(0h1) connect iresp[0].bits.uop, stq_uop[resp.uop.stq_idx] connect iresp[0].bits.data, resp.data connect wb_slow_wakeups[0].valid, UInt<1>(0h1) connect wb_slow_wakeups[0].bits.uop, stq_uop[resp.uop.stq_idx] connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) connect stq_debug_wb_data[resp.uop.stq_idx], resp.data when io.dmem.store_ack[0].valid : connect stq_succeeded[io.dmem.store_ack[0].bits.uop.stq_idx], UInt<1>(0h1) node _T_1676 = and(dmem_resp_fired[0], wb_ldst_forward_valid[0]) when _T_1676 : skip else : node _T_1677 = eq(dmem_resp_fired[0], UInt<1>(0h0)) node _T_1678 = and(_T_1677, wb_ldst_forward_valid[0]) when _T_1678 : wire size : UInt<2> connect size, stq_uop[wb_ldst_forward_stq_idx[0]].mem_size node _T_1679 = eq(size, UInt<1>(0h0)) node _T_1680 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 7, 0) node _T_1681 = cat(_T_1680, _T_1680) node _T_1682 = cat(_T_1681, _T_1681) node _T_1683 = cat(_T_1682, _T_1682) node _T_1684 = eq(size, UInt<1>(0h1)) node _T_1685 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 15, 0) node _T_1686 = cat(_T_1685, _T_1685) node _T_1687 = cat(_T_1686, _T_1686) node _T_1688 = eq(size, UInt<2>(0h2)) node _T_1689 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 31, 0) node _T_1690 = cat(_T_1689, _T_1689) node _T_1691 = mux(_T_1688, _T_1690, stq_data[wb_ldst_forward_stq_idx[0]].bits) node _T_1692 = mux(_T_1684, _T_1687, _T_1691) node _T_1693 = mux(_T_1679, _T_1683, _T_1692) wire size_1 : UInt<2> connect size_1, wb_ldst_forward_e[0].uop.mem_size node _wb_slow_wakeups_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h0)) connect wb_slow_wakeups[0].valid, _wb_slow_wakeups_0_valid_T connect wb_slow_wakeups[0].bits.uop, wb_ldst_forward_e[0].uop connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) node _iresp_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h0)) connect iresp[0].valid, _iresp_0_valid_T node _fresp_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h1)) connect fresp[0].valid, _fresp_0_valid_T connect iresp[0].bits.uop, wb_ldst_forward_e[0].uop connect fresp[0].bits.uop, wb_ldst_forward_e[0].uop node _iresp_0_bits_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _iresp_0_bits_data_shifted_T_1 = bits(_T_1693, 63, 32) node _iresp_0_bits_data_shifted_T_2 = bits(_T_1693, 31, 0) node iresp_0_bits_data_shifted = mux(_iresp_0_bits_data_shifted_T, _iresp_0_bits_data_shifted_T_1, _iresp_0_bits_data_shifted_T_2) node iresp_0_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node iresp_0_bits_data_zeroed = mux(iresp_0_bits_data_doZero, UInt<1>(0h0), iresp_0_bits_data_shifted) node _iresp_0_bits_data_T = eq(size_1, UInt<2>(0h2)) node _iresp_0_bits_data_T_1 = or(_iresp_0_bits_data_T, iresp_0_bits_data_doZero) node _iresp_0_bits_data_T_2 = bits(iresp_0_bits_data_zeroed, 31, 31) node _iresp_0_bits_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_2) node _iresp_0_bits_data_T_4 = mux(_iresp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _iresp_0_bits_data_T_5 = bits(_T_1693, 63, 32) node _iresp_0_bits_data_T_6 = mux(_iresp_0_bits_data_T_1, _iresp_0_bits_data_T_4, _iresp_0_bits_data_T_5) node _iresp_0_bits_data_T_7 = cat(_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed) node _iresp_0_bits_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _iresp_0_bits_data_shifted_T_4 = bits(_iresp_0_bits_data_T_7, 31, 16) node _iresp_0_bits_data_shifted_T_5 = bits(_iresp_0_bits_data_T_7, 15, 0) node iresp_0_bits_data_shifted_1 = mux(_iresp_0_bits_data_shifted_T_3, _iresp_0_bits_data_shifted_T_4, _iresp_0_bits_data_shifted_T_5) node iresp_0_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node iresp_0_bits_data_zeroed_1 = mux(iresp_0_bits_data_doZero_1, UInt<1>(0h0), iresp_0_bits_data_shifted_1) node _iresp_0_bits_data_T_8 = eq(size_1, UInt<1>(0h1)) node _iresp_0_bits_data_T_9 = or(_iresp_0_bits_data_T_8, iresp_0_bits_data_doZero_1) node _iresp_0_bits_data_T_10 = bits(iresp_0_bits_data_zeroed_1, 15, 15) node _iresp_0_bits_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_10) node _iresp_0_bits_data_T_12 = mux(_iresp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _iresp_0_bits_data_T_13 = bits(_iresp_0_bits_data_T_7, 63, 16) node _iresp_0_bits_data_T_14 = mux(_iresp_0_bits_data_T_9, _iresp_0_bits_data_T_12, _iresp_0_bits_data_T_13) node _iresp_0_bits_data_T_15 = cat(_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1) node _iresp_0_bits_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _iresp_0_bits_data_shifted_T_7 = bits(_iresp_0_bits_data_T_15, 15, 8) node _iresp_0_bits_data_shifted_T_8 = bits(_iresp_0_bits_data_T_15, 7, 0) node iresp_0_bits_data_shifted_2 = mux(_iresp_0_bits_data_shifted_T_6, _iresp_0_bits_data_shifted_T_7, _iresp_0_bits_data_shifted_T_8) node iresp_0_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node iresp_0_bits_data_zeroed_2 = mux(iresp_0_bits_data_doZero_2, UInt<1>(0h0), iresp_0_bits_data_shifted_2) node _iresp_0_bits_data_T_16 = eq(size_1, UInt<1>(0h0)) node _iresp_0_bits_data_T_17 = or(_iresp_0_bits_data_T_16, iresp_0_bits_data_doZero_2) node _iresp_0_bits_data_T_18 = bits(iresp_0_bits_data_zeroed_2, 7, 7) node _iresp_0_bits_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_18) node _iresp_0_bits_data_T_20 = mux(_iresp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _iresp_0_bits_data_T_21 = bits(_iresp_0_bits_data_T_15, 63, 8) node _iresp_0_bits_data_T_22 = mux(_iresp_0_bits_data_T_17, _iresp_0_bits_data_T_20, _iresp_0_bits_data_T_21) node _iresp_0_bits_data_T_23 = cat(_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2) connect iresp[0].bits.data, _iresp_0_bits_data_T_23 node _fresp_0_bits_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _fresp_0_bits_data_shifted_T_1 = bits(_T_1693, 63, 32) node _fresp_0_bits_data_shifted_T_2 = bits(_T_1693, 31, 0) node fresp_0_bits_data_shifted = mux(_fresp_0_bits_data_shifted_T, _fresp_0_bits_data_shifted_T_1, _fresp_0_bits_data_shifted_T_2) node fresp_0_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node fresp_0_bits_data_zeroed = mux(fresp_0_bits_data_doZero, UInt<1>(0h0), fresp_0_bits_data_shifted) node _fresp_0_bits_data_T = eq(size_1, UInt<2>(0h2)) node _fresp_0_bits_data_T_1 = or(_fresp_0_bits_data_T, fresp_0_bits_data_doZero) node _fresp_0_bits_data_T_2 = bits(fresp_0_bits_data_zeroed, 31, 31) node _fresp_0_bits_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_2) node _fresp_0_bits_data_T_4 = mux(_fresp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _fresp_0_bits_data_T_5 = bits(_T_1693, 63, 32) node _fresp_0_bits_data_T_6 = mux(_fresp_0_bits_data_T_1, _fresp_0_bits_data_T_4, _fresp_0_bits_data_T_5) node _fresp_0_bits_data_T_7 = cat(_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed) node _fresp_0_bits_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _fresp_0_bits_data_shifted_T_4 = bits(_fresp_0_bits_data_T_7, 31, 16) node _fresp_0_bits_data_shifted_T_5 = bits(_fresp_0_bits_data_T_7, 15, 0) node fresp_0_bits_data_shifted_1 = mux(_fresp_0_bits_data_shifted_T_3, _fresp_0_bits_data_shifted_T_4, _fresp_0_bits_data_shifted_T_5) node fresp_0_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node fresp_0_bits_data_zeroed_1 = mux(fresp_0_bits_data_doZero_1, UInt<1>(0h0), fresp_0_bits_data_shifted_1) node _fresp_0_bits_data_T_8 = eq(size_1, UInt<1>(0h1)) node _fresp_0_bits_data_T_9 = or(_fresp_0_bits_data_T_8, fresp_0_bits_data_doZero_1) node _fresp_0_bits_data_T_10 = bits(fresp_0_bits_data_zeroed_1, 15, 15) node _fresp_0_bits_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_10) node _fresp_0_bits_data_T_12 = mux(_fresp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _fresp_0_bits_data_T_13 = bits(_fresp_0_bits_data_T_7, 63, 16) node _fresp_0_bits_data_T_14 = mux(_fresp_0_bits_data_T_9, _fresp_0_bits_data_T_12, _fresp_0_bits_data_T_13) node _fresp_0_bits_data_T_15 = cat(_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1) node _fresp_0_bits_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _fresp_0_bits_data_shifted_T_7 = bits(_fresp_0_bits_data_T_15, 15, 8) node _fresp_0_bits_data_shifted_T_8 = bits(_fresp_0_bits_data_T_15, 7, 0) node fresp_0_bits_data_shifted_2 = mux(_fresp_0_bits_data_shifted_T_6, _fresp_0_bits_data_shifted_T_7, _fresp_0_bits_data_shifted_T_8) node fresp_0_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node fresp_0_bits_data_zeroed_2 = mux(fresp_0_bits_data_doZero_2, UInt<1>(0h0), fresp_0_bits_data_shifted_2) node _fresp_0_bits_data_T_16 = eq(size_1, UInt<1>(0h0)) node _fresp_0_bits_data_T_17 = or(_fresp_0_bits_data_T_16, fresp_0_bits_data_doZero_2) node _fresp_0_bits_data_T_18 = bits(fresp_0_bits_data_zeroed_2, 7, 7) node _fresp_0_bits_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_18) node _fresp_0_bits_data_T_20 = mux(_fresp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _fresp_0_bits_data_T_21 = bits(_fresp_0_bits_data_T_15, 63, 8) node _fresp_0_bits_data_T_22 = mux(_fresp_0_bits_data_T_17, _fresp_0_bits_data_T_20, _fresp_0_bits_data_T_21) node _fresp_0_bits_data_T_23 = cat(_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2) connect fresp[0].bits.data, _fresp_0_bits_data_T_23 node _T_1694 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1695 = bits(_T_1694, 4, 0) connect ldq_will_succeed[_T_1695], UInt<1>(0h1) node _T_1696 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1697 = bits(_T_1696, 4, 0) connect ldq_forward_std_val[_T_1697], UInt<1>(0h1) node _T_1698 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1699 = bits(_T_1698, 4, 0) connect ldq_forward_stq_idx[_T_1699], wb_ldst_forward_stq_idx[0] node _T_1700 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1701 = bits(_T_1700, 4, 0) node _ldq_debug_wb_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _ldq_debug_wb_data_shifted_T_1 = bits(_T_1693, 63, 32) node _ldq_debug_wb_data_shifted_T_2 = bits(_T_1693, 31, 0) node ldq_debug_wb_data_shifted = mux(_ldq_debug_wb_data_shifted_T, _ldq_debug_wb_data_shifted_T_1, _ldq_debug_wb_data_shifted_T_2) node ldq_debug_wb_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed = mux(ldq_debug_wb_data_doZero, UInt<1>(0h0), ldq_debug_wb_data_shifted) node _ldq_debug_wb_data_T = eq(size_1, UInt<2>(0h2)) node _ldq_debug_wb_data_T_1 = or(_ldq_debug_wb_data_T, ldq_debug_wb_data_doZero) node _ldq_debug_wb_data_T_2 = bits(ldq_debug_wb_data_zeroed, 31, 31) node _ldq_debug_wb_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_2) node _ldq_debug_wb_data_T_4 = mux(_ldq_debug_wb_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _ldq_debug_wb_data_T_5 = bits(_T_1693, 63, 32) node _ldq_debug_wb_data_T_6 = mux(_ldq_debug_wb_data_T_1, _ldq_debug_wb_data_T_4, _ldq_debug_wb_data_T_5) node _ldq_debug_wb_data_T_7 = cat(_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed) node _ldq_debug_wb_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _ldq_debug_wb_data_shifted_T_4 = bits(_ldq_debug_wb_data_T_7, 31, 16) node _ldq_debug_wb_data_shifted_T_5 = bits(_ldq_debug_wb_data_T_7, 15, 0) node ldq_debug_wb_data_shifted_1 = mux(_ldq_debug_wb_data_shifted_T_3, _ldq_debug_wb_data_shifted_T_4, _ldq_debug_wb_data_shifted_T_5) node ldq_debug_wb_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed_1 = mux(ldq_debug_wb_data_doZero_1, UInt<1>(0h0), ldq_debug_wb_data_shifted_1) node _ldq_debug_wb_data_T_8 = eq(size_1, UInt<1>(0h1)) node _ldq_debug_wb_data_T_9 = or(_ldq_debug_wb_data_T_8, ldq_debug_wb_data_doZero_1) node _ldq_debug_wb_data_T_10 = bits(ldq_debug_wb_data_zeroed_1, 15, 15) node _ldq_debug_wb_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_10) node _ldq_debug_wb_data_T_12 = mux(_ldq_debug_wb_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _ldq_debug_wb_data_T_13 = bits(_ldq_debug_wb_data_T_7, 63, 16) node _ldq_debug_wb_data_T_14 = mux(_ldq_debug_wb_data_T_9, _ldq_debug_wb_data_T_12, _ldq_debug_wb_data_T_13) node _ldq_debug_wb_data_T_15 = cat(_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1) node _ldq_debug_wb_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _ldq_debug_wb_data_shifted_T_7 = bits(_ldq_debug_wb_data_T_15, 15, 8) node _ldq_debug_wb_data_shifted_T_8 = bits(_ldq_debug_wb_data_T_15, 7, 0) node ldq_debug_wb_data_shifted_2 = mux(_ldq_debug_wb_data_shifted_T_6, _ldq_debug_wb_data_shifted_T_7, _ldq_debug_wb_data_shifted_T_8) node ldq_debug_wb_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed_2 = mux(ldq_debug_wb_data_doZero_2, UInt<1>(0h0), ldq_debug_wb_data_shifted_2) node _ldq_debug_wb_data_T_16 = eq(size_1, UInt<1>(0h0)) node _ldq_debug_wb_data_T_17 = or(_ldq_debug_wb_data_T_16, ldq_debug_wb_data_doZero_2) node _ldq_debug_wb_data_T_18 = bits(ldq_debug_wb_data_zeroed_2, 7, 7) node _ldq_debug_wb_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_18) node _ldq_debug_wb_data_T_20 = mux(_ldq_debug_wb_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _ldq_debug_wb_data_T_21 = bits(_ldq_debug_wb_data_T_15, 63, 8) node _ldq_debug_wb_data_T_22 = mux(_ldq_debug_wb_data_T_17, _ldq_debug_wb_data_T_20, _ldq_debug_wb_data_T_21) node _ldq_debug_wb_data_T_23 = cat(_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2) connect ldq_debug_wb_data[_T_1701], _ldq_debug_wb_data_T_23 connect wakeupArbs_0.io.in[0].valid, UInt<1>(0h0) invalidate wakeupArbs_0.io.in[0].bits.rebusy invalidate wakeupArbs_0.io.in[0].bits.speculative_mask invalidate wakeupArbs_0.io.in[0].bits.bypassable invalidate wakeupArbs_0.io.in[0].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[0].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[0].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[0].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[0].bits.uop.fp_val invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[0].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[0].bits.uop.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[0].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[0].bits.uop.is_unique invalidate wakeupArbs_0.io.in[0].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[0].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[0].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[0].bits.uop.mem_size invalidate wakeupArbs_0.io.in[0].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[0].bits.uop.exception invalidate wakeupArbs_0.io.in[0].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[0].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[0].bits.uop.ppred invalidate wakeupArbs_0.io.in[0].bits.uop.prs3 invalidate wakeupArbs_0.io.in[0].bits.uop.prs2 invalidate wakeupArbs_0.io.in[0].bits.uop.prs1 invalidate wakeupArbs_0.io.in[0].bits.uop.pdst invalidate wakeupArbs_0.io.in[0].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[0].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[0].bits.uop.pimm invalidate wakeupArbs_0.io.in[0].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[0].bits.uop.taken invalidate wakeupArbs_0.io.in[0].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[0].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[0].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.is_mov invalidate wakeupArbs_0.io.in[0].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[0].bits.uop.is_eret invalidate wakeupArbs_0.io.in[0].bits.uop.is_amo invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[0].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[0].bits.uop.is_fence invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[0].bits.uop.br_type invalidate wakeupArbs_0.io.in[0].bits.uop.br_tag invalidate wakeupArbs_0.io.in[0].bits.uop.br_mask invalidate wakeupArbs_0.io.in[0].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[0].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[0].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[0].bits.uop.inst wire slow_wakeups_0_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}} connect slow_wakeups_0_out, wb_slow_wakeups[0] node _slow_wakeups_0_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _slow_wakeups_0_out_bits_uop_br_mask_T_1 = and(wb_slow_wakeups[0].bits.uop.br_mask, _slow_wakeups_0_out_bits_uop_br_mask_T) connect slow_wakeups_0_out.bits.uop.br_mask, _slow_wakeups_0_out_bits_uop_br_mask_T_1 node _slow_wakeups_0_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, wb_slow_wakeups[0].bits.uop.br_mask) node _slow_wakeups_0_out_valid_T_1 = neq(_slow_wakeups_0_out_valid_T, UInt<1>(0h0)) node _slow_wakeups_0_out_valid_T_2 = or(_slow_wakeups_0_out_valid_T_1, io.core.exception) node _slow_wakeups_0_out_valid_T_3 = eq(_slow_wakeups_0_out_valid_T_2, UInt<1>(0h0)) node _slow_wakeups_0_out_valid_T_4 = and(wb_slow_wakeups[0].valid, _slow_wakeups_0_out_valid_T_3) connect slow_wakeups_0_out.valid, _slow_wakeups_0_out_valid_T_4 reg slow_wakeups_0_REG : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock connect slow_wakeups_0_REG, slow_wakeups_0_out connect slow_wakeups[0], slow_wakeups_0_REG when slow_wakeups[0].valid : when spec_wakeups[0].valid : node _T_1702 = eq(slow_wakeups[0].bits.uop.ldq_idx, spec_wakeups[0].bits.uop.ldq_idx) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1651 assert(slow_wakeups(w).bits.uop.ldq_idx === spec_wakeups(w).bits.uop.ldq_idx)\n") : printf_86 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_86 else : connect wakeupArbs_0.io.in[0].valid, slow_wakeups[0].valid connect wakeupArbs_0.io.in[0].bits.rebusy, slow_wakeups[0].bits.rebusy connect wakeupArbs_0.io.in[0].bits.speculative_mask, slow_wakeups[0].bits.speculative_mask connect wakeupArbs_0.io.in[0].bits.bypassable, slow_wakeups[0].bits.bypassable connect wakeupArbs_0.io.in[0].bits.uop.debug_tsrc, slow_wakeups[0].bits.uop.debug_tsrc connect wakeupArbs_0.io.in[0].bits.uop.debug_fsrc, slow_wakeups[0].bits.uop.debug_fsrc connect wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if, slow_wakeups[0].bits.uop.bp_xcpt_if connect wakeupArbs_0.io.in[0].bits.uop.bp_debug_if, slow_wakeups[0].bits.uop.bp_debug_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if, slow_wakeups[0].bits.uop.xcpt_ma_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if, slow_wakeups[0].bits.uop.xcpt_ae_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if, slow_wakeups[0].bits.uop.xcpt_pf_if connect wakeupArbs_0.io.in[0].bits.uop.fp_typ, slow_wakeups[0].bits.uop.fp_typ connect wakeupArbs_0.io.in[0].bits.uop.fp_rm, slow_wakeups[0].bits.uop.fp_rm connect wakeupArbs_0.io.in[0].bits.uop.fp_val, slow_wakeups[0].bits.uop.fp_val connect wakeupArbs_0.io.in[0].bits.uop.fcn_op, slow_wakeups[0].bits.uop.fcn_op connect wakeupArbs_0.io.in[0].bits.uop.fcn_dw, slow_wakeups[0].bits.uop.fcn_dw connect wakeupArbs_0.io.in[0].bits.uop.frs3_en, slow_wakeups[0].bits.uop.frs3_en connect wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype, slow_wakeups[0].bits.uop.lrs2_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype, slow_wakeups[0].bits.uop.lrs1_rtype connect wakeupArbs_0.io.in[0].bits.uop.dst_rtype, slow_wakeups[0].bits.uop.dst_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs3, slow_wakeups[0].bits.uop.lrs3 connect wakeupArbs_0.io.in[0].bits.uop.lrs2, slow_wakeups[0].bits.uop.lrs2 connect wakeupArbs_0.io.in[0].bits.uop.lrs1, slow_wakeups[0].bits.uop.lrs1 connect wakeupArbs_0.io.in[0].bits.uop.ldst, slow_wakeups[0].bits.uop.ldst connect wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1, slow_wakeups[0].bits.uop.ldst_is_rs1 connect wakeupArbs_0.io.in[0].bits.uop.csr_cmd, slow_wakeups[0].bits.uop.csr_cmd connect wakeupArbs_0.io.in[0].bits.uop.flush_on_commit, slow_wakeups[0].bits.uop.flush_on_commit connect wakeupArbs_0.io.in[0].bits.uop.is_unique, slow_wakeups[0].bits.uop.is_unique connect wakeupArbs_0.io.in[0].bits.uop.uses_stq, slow_wakeups[0].bits.uop.uses_stq connect wakeupArbs_0.io.in[0].bits.uop.uses_ldq, slow_wakeups[0].bits.uop.uses_ldq connect wakeupArbs_0.io.in[0].bits.uop.mem_signed, slow_wakeups[0].bits.uop.mem_signed connect wakeupArbs_0.io.in[0].bits.uop.mem_size, slow_wakeups[0].bits.uop.mem_size connect wakeupArbs_0.io.in[0].bits.uop.mem_cmd, slow_wakeups[0].bits.uop.mem_cmd connect wakeupArbs_0.io.in[0].bits.uop.exc_cause, slow_wakeups[0].bits.uop.exc_cause connect wakeupArbs_0.io.in[0].bits.uop.exception, slow_wakeups[0].bits.uop.exception connect wakeupArbs_0.io.in[0].bits.uop.stale_pdst, slow_wakeups[0].bits.uop.stale_pdst connect wakeupArbs_0.io.in[0].bits.uop.ppred_busy, slow_wakeups[0].bits.uop.ppred_busy connect wakeupArbs_0.io.in[0].bits.uop.prs3_busy, slow_wakeups[0].bits.uop.prs3_busy connect wakeupArbs_0.io.in[0].bits.uop.prs2_busy, slow_wakeups[0].bits.uop.prs2_busy connect wakeupArbs_0.io.in[0].bits.uop.prs1_busy, slow_wakeups[0].bits.uop.prs1_busy connect wakeupArbs_0.io.in[0].bits.uop.ppred, slow_wakeups[0].bits.uop.ppred connect wakeupArbs_0.io.in[0].bits.uop.prs3, slow_wakeups[0].bits.uop.prs3 connect wakeupArbs_0.io.in[0].bits.uop.prs2, slow_wakeups[0].bits.uop.prs2 connect wakeupArbs_0.io.in[0].bits.uop.prs1, slow_wakeups[0].bits.uop.prs1 connect wakeupArbs_0.io.in[0].bits.uop.pdst, slow_wakeups[0].bits.uop.pdst connect wakeupArbs_0.io.in[0].bits.uop.rxq_idx, slow_wakeups[0].bits.uop.rxq_idx connect wakeupArbs_0.io.in[0].bits.uop.stq_idx, slow_wakeups[0].bits.uop.stq_idx connect wakeupArbs_0.io.in[0].bits.uop.ldq_idx, slow_wakeups[0].bits.uop.ldq_idx connect wakeupArbs_0.io.in[0].bits.uop.rob_idx, slow_wakeups[0].bits.uop.rob_idx connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec, slow_wakeups[0].bits.uop.fp_ctrl.vec connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags, slow_wakeups[0].bits.uop.fp_ctrl.wflags connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt, slow_wakeups[0].bits.uop.fp_ctrl.sqrt connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div, slow_wakeups[0].bits.uop.fp_ctrl.div connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma, slow_wakeups[0].bits.uop.fp_ctrl.fma connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe, slow_wakeups[0].bits.uop.fp_ctrl.fastpipe connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint, slow_wakeups[0].bits.uop.fp_ctrl.toint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint, slow_wakeups[0].bits.uop.fp_ctrl.fromint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut, slow_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn, slow_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23, slow_wakeups[0].bits.uop.fp_ctrl.swap23 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12, slow_wakeups[0].bits.uop.fp_ctrl.swap12 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3, slow_wakeups[0].bits.uop.fp_ctrl.ren3 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2, slow_wakeups[0].bits.uop.fp_ctrl.ren2 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1, slow_wakeups[0].bits.uop.fp_ctrl.ren1 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen, slow_wakeups[0].bits.uop.fp_ctrl.wen connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst, slow_wakeups[0].bits.uop.fp_ctrl.ldst connect wakeupArbs_0.io.in[0].bits.uop.op2_sel, slow_wakeups[0].bits.uop.op2_sel connect wakeupArbs_0.io.in[0].bits.uop.op1_sel, slow_wakeups[0].bits.uop.op1_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_packed, slow_wakeups[0].bits.uop.imm_packed connect wakeupArbs_0.io.in[0].bits.uop.pimm, slow_wakeups[0].bits.uop.pimm connect wakeupArbs_0.io.in[0].bits.uop.imm_sel, slow_wakeups[0].bits.uop.imm_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_rename, slow_wakeups[0].bits.uop.imm_rename connect wakeupArbs_0.io.in[0].bits.uop.taken, slow_wakeups[0].bits.uop.taken connect wakeupArbs_0.io.in[0].bits.uop.pc_lob, slow_wakeups[0].bits.uop.pc_lob connect wakeupArbs_0.io.in[0].bits.uop.edge_inst, slow_wakeups[0].bits.uop.edge_inst connect wakeupArbs_0.io.in[0].bits.uop.ftq_idx, slow_wakeups[0].bits.uop.ftq_idx connect wakeupArbs_0.io.in[0].bits.uop.is_mov, slow_wakeups[0].bits.uop.is_mov connect wakeupArbs_0.io.in[0].bits.uop.is_rocc, slow_wakeups[0].bits.uop.is_rocc connect wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc, slow_wakeups[0].bits.uop.is_sys_pc2epc connect wakeupArbs_0.io.in[0].bits.uop.is_eret, slow_wakeups[0].bits.uop.is_eret connect wakeupArbs_0.io.in[0].bits.uop.is_amo, slow_wakeups[0].bits.uop.is_amo connect wakeupArbs_0.io.in[0].bits.uop.is_sfence, slow_wakeups[0].bits.uop.is_sfence connect wakeupArbs_0.io.in[0].bits.uop.is_fencei, slow_wakeups[0].bits.uop.is_fencei connect wakeupArbs_0.io.in[0].bits.uop.is_fence, slow_wakeups[0].bits.uop.is_fence connect wakeupArbs_0.io.in[0].bits.uop.is_sfb, slow_wakeups[0].bits.uop.is_sfb connect wakeupArbs_0.io.in[0].bits.uop.br_type, slow_wakeups[0].bits.uop.br_type connect wakeupArbs_0.io.in[0].bits.uop.br_tag, slow_wakeups[0].bits.uop.br_tag connect wakeupArbs_0.io.in[0].bits.uop.br_mask, slow_wakeups[0].bits.uop.br_mask connect wakeupArbs_0.io.in[0].bits.uop.dis_col_sel, slow_wakeups[0].bits.uop.dis_col_sel connect wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint, slow_wakeups[0].bits.uop.iw_p3_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint, slow_wakeups[0].bits.uop.iw_p2_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint, slow_wakeups[0].bits.uop.iw_p1_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child, slow_wakeups[0].bits.uop.iw_p2_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child, slow_wakeups[0].bits.uop.iw_p1_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen, slow_wakeups[0].bits.uop.iw_issued_partial_dgen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen, slow_wakeups[0].bits.uop.iw_issued_partial_agen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued, slow_wakeups[0].bits.uop.iw_issued connect wakeupArbs_0.io.in[0].bits.uop.fu_code[0], slow_wakeups[0].bits.uop.fu_code[0] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[1], slow_wakeups[0].bits.uop.fu_code[1] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[2], slow_wakeups[0].bits.uop.fu_code[2] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[3], slow_wakeups[0].bits.uop.fu_code[3] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[4], slow_wakeups[0].bits.uop.fu_code[4] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[5], slow_wakeups[0].bits.uop.fu_code[5] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[6], slow_wakeups[0].bits.uop.fu_code[6] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[7], slow_wakeups[0].bits.uop.fu_code[7] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[8], slow_wakeups[0].bits.uop.fu_code[8] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[9], slow_wakeups[0].bits.uop.fu_code[9] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[0], slow_wakeups[0].bits.uop.iq_type[0] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[1], slow_wakeups[0].bits.uop.iq_type[1] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[2], slow_wakeups[0].bits.uop.iq_type[2] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[3], slow_wakeups[0].bits.uop.iq_type[3] connect wakeupArbs_0.io.in[0].bits.uop.debug_pc, slow_wakeups[0].bits.uop.debug_pc connect wakeupArbs_0.io.in[0].bits.uop.is_rvc, slow_wakeups[0].bits.uop.is_rvc connect wakeupArbs_0.io.in[0].bits.uop.debug_inst, slow_wakeups[0].bits.uop.debug_inst connect wakeupArbs_0.io.in[0].bits.uop.inst, slow_wakeups[0].bits.uop.inst else : when spec_wakeups[0].valid : connect wakeupArbs_0.io.in[0].valid, spec_wakeups[0].valid connect wakeupArbs_0.io.in[0].bits.rebusy, spec_wakeups[0].bits.rebusy connect wakeupArbs_0.io.in[0].bits.speculative_mask, spec_wakeups[0].bits.speculative_mask connect wakeupArbs_0.io.in[0].bits.bypassable, spec_wakeups[0].bits.bypassable connect wakeupArbs_0.io.in[0].bits.uop.debug_tsrc, spec_wakeups[0].bits.uop.debug_tsrc connect wakeupArbs_0.io.in[0].bits.uop.debug_fsrc, spec_wakeups[0].bits.uop.debug_fsrc connect wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if, spec_wakeups[0].bits.uop.bp_xcpt_if connect wakeupArbs_0.io.in[0].bits.uop.bp_debug_if, spec_wakeups[0].bits.uop.bp_debug_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if, spec_wakeups[0].bits.uop.xcpt_ma_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if, spec_wakeups[0].bits.uop.xcpt_ae_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if, spec_wakeups[0].bits.uop.xcpt_pf_if connect wakeupArbs_0.io.in[0].bits.uop.fp_typ, spec_wakeups[0].bits.uop.fp_typ connect wakeupArbs_0.io.in[0].bits.uop.fp_rm, spec_wakeups[0].bits.uop.fp_rm connect wakeupArbs_0.io.in[0].bits.uop.fp_val, spec_wakeups[0].bits.uop.fp_val connect wakeupArbs_0.io.in[0].bits.uop.fcn_op, spec_wakeups[0].bits.uop.fcn_op connect wakeupArbs_0.io.in[0].bits.uop.fcn_dw, spec_wakeups[0].bits.uop.fcn_dw connect wakeupArbs_0.io.in[0].bits.uop.frs3_en, spec_wakeups[0].bits.uop.frs3_en connect wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype, spec_wakeups[0].bits.uop.lrs2_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype, spec_wakeups[0].bits.uop.lrs1_rtype connect wakeupArbs_0.io.in[0].bits.uop.dst_rtype, spec_wakeups[0].bits.uop.dst_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs3, spec_wakeups[0].bits.uop.lrs3 connect wakeupArbs_0.io.in[0].bits.uop.lrs2, spec_wakeups[0].bits.uop.lrs2 connect wakeupArbs_0.io.in[0].bits.uop.lrs1, spec_wakeups[0].bits.uop.lrs1 connect wakeupArbs_0.io.in[0].bits.uop.ldst, spec_wakeups[0].bits.uop.ldst connect wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1, spec_wakeups[0].bits.uop.ldst_is_rs1 connect wakeupArbs_0.io.in[0].bits.uop.csr_cmd, spec_wakeups[0].bits.uop.csr_cmd connect wakeupArbs_0.io.in[0].bits.uop.flush_on_commit, spec_wakeups[0].bits.uop.flush_on_commit connect wakeupArbs_0.io.in[0].bits.uop.is_unique, spec_wakeups[0].bits.uop.is_unique connect wakeupArbs_0.io.in[0].bits.uop.uses_stq, spec_wakeups[0].bits.uop.uses_stq connect wakeupArbs_0.io.in[0].bits.uop.uses_ldq, spec_wakeups[0].bits.uop.uses_ldq connect wakeupArbs_0.io.in[0].bits.uop.mem_signed, spec_wakeups[0].bits.uop.mem_signed connect wakeupArbs_0.io.in[0].bits.uop.mem_size, spec_wakeups[0].bits.uop.mem_size connect wakeupArbs_0.io.in[0].bits.uop.mem_cmd, spec_wakeups[0].bits.uop.mem_cmd connect wakeupArbs_0.io.in[0].bits.uop.exc_cause, spec_wakeups[0].bits.uop.exc_cause connect wakeupArbs_0.io.in[0].bits.uop.exception, spec_wakeups[0].bits.uop.exception connect wakeupArbs_0.io.in[0].bits.uop.stale_pdst, spec_wakeups[0].bits.uop.stale_pdst connect wakeupArbs_0.io.in[0].bits.uop.ppred_busy, spec_wakeups[0].bits.uop.ppred_busy connect wakeupArbs_0.io.in[0].bits.uop.prs3_busy, spec_wakeups[0].bits.uop.prs3_busy connect wakeupArbs_0.io.in[0].bits.uop.prs2_busy, spec_wakeups[0].bits.uop.prs2_busy connect wakeupArbs_0.io.in[0].bits.uop.prs1_busy, spec_wakeups[0].bits.uop.prs1_busy connect wakeupArbs_0.io.in[0].bits.uop.ppred, spec_wakeups[0].bits.uop.ppred connect wakeupArbs_0.io.in[0].bits.uop.prs3, spec_wakeups[0].bits.uop.prs3 connect wakeupArbs_0.io.in[0].bits.uop.prs2, spec_wakeups[0].bits.uop.prs2 connect wakeupArbs_0.io.in[0].bits.uop.prs1, spec_wakeups[0].bits.uop.prs1 connect wakeupArbs_0.io.in[0].bits.uop.pdst, spec_wakeups[0].bits.uop.pdst connect wakeupArbs_0.io.in[0].bits.uop.rxq_idx, spec_wakeups[0].bits.uop.rxq_idx connect wakeupArbs_0.io.in[0].bits.uop.stq_idx, spec_wakeups[0].bits.uop.stq_idx connect wakeupArbs_0.io.in[0].bits.uop.ldq_idx, spec_wakeups[0].bits.uop.ldq_idx connect wakeupArbs_0.io.in[0].bits.uop.rob_idx, spec_wakeups[0].bits.uop.rob_idx connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec, spec_wakeups[0].bits.uop.fp_ctrl.vec connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags, spec_wakeups[0].bits.uop.fp_ctrl.wflags connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt, spec_wakeups[0].bits.uop.fp_ctrl.sqrt connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div, spec_wakeups[0].bits.uop.fp_ctrl.div connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma, spec_wakeups[0].bits.uop.fp_ctrl.fma connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe, spec_wakeups[0].bits.uop.fp_ctrl.fastpipe connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint, spec_wakeups[0].bits.uop.fp_ctrl.toint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint, spec_wakeups[0].bits.uop.fp_ctrl.fromint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut, spec_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn, spec_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23, spec_wakeups[0].bits.uop.fp_ctrl.swap23 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12, spec_wakeups[0].bits.uop.fp_ctrl.swap12 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3, spec_wakeups[0].bits.uop.fp_ctrl.ren3 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2, spec_wakeups[0].bits.uop.fp_ctrl.ren2 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1, spec_wakeups[0].bits.uop.fp_ctrl.ren1 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen, spec_wakeups[0].bits.uop.fp_ctrl.wen connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst, spec_wakeups[0].bits.uop.fp_ctrl.ldst connect wakeupArbs_0.io.in[0].bits.uop.op2_sel, spec_wakeups[0].bits.uop.op2_sel connect wakeupArbs_0.io.in[0].bits.uop.op1_sel, spec_wakeups[0].bits.uop.op1_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_packed, spec_wakeups[0].bits.uop.imm_packed connect wakeupArbs_0.io.in[0].bits.uop.pimm, spec_wakeups[0].bits.uop.pimm connect wakeupArbs_0.io.in[0].bits.uop.imm_sel, spec_wakeups[0].bits.uop.imm_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_rename, spec_wakeups[0].bits.uop.imm_rename connect wakeupArbs_0.io.in[0].bits.uop.taken, spec_wakeups[0].bits.uop.taken connect wakeupArbs_0.io.in[0].bits.uop.pc_lob, spec_wakeups[0].bits.uop.pc_lob connect wakeupArbs_0.io.in[0].bits.uop.edge_inst, spec_wakeups[0].bits.uop.edge_inst connect wakeupArbs_0.io.in[0].bits.uop.ftq_idx, spec_wakeups[0].bits.uop.ftq_idx connect wakeupArbs_0.io.in[0].bits.uop.is_mov, spec_wakeups[0].bits.uop.is_mov connect wakeupArbs_0.io.in[0].bits.uop.is_rocc, spec_wakeups[0].bits.uop.is_rocc connect wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc, spec_wakeups[0].bits.uop.is_sys_pc2epc connect wakeupArbs_0.io.in[0].bits.uop.is_eret, spec_wakeups[0].bits.uop.is_eret connect wakeupArbs_0.io.in[0].bits.uop.is_amo, spec_wakeups[0].bits.uop.is_amo connect wakeupArbs_0.io.in[0].bits.uop.is_sfence, spec_wakeups[0].bits.uop.is_sfence connect wakeupArbs_0.io.in[0].bits.uop.is_fencei, spec_wakeups[0].bits.uop.is_fencei connect wakeupArbs_0.io.in[0].bits.uop.is_fence, spec_wakeups[0].bits.uop.is_fence connect wakeupArbs_0.io.in[0].bits.uop.is_sfb, spec_wakeups[0].bits.uop.is_sfb connect wakeupArbs_0.io.in[0].bits.uop.br_type, spec_wakeups[0].bits.uop.br_type connect wakeupArbs_0.io.in[0].bits.uop.br_tag, spec_wakeups[0].bits.uop.br_tag connect wakeupArbs_0.io.in[0].bits.uop.br_mask, spec_wakeups[0].bits.uop.br_mask connect wakeupArbs_0.io.in[0].bits.uop.dis_col_sel, spec_wakeups[0].bits.uop.dis_col_sel connect wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint, spec_wakeups[0].bits.uop.iw_p3_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint, spec_wakeups[0].bits.uop.iw_p2_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint, spec_wakeups[0].bits.uop.iw_p1_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child, spec_wakeups[0].bits.uop.iw_p2_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child, spec_wakeups[0].bits.uop.iw_p1_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen, spec_wakeups[0].bits.uop.iw_issued_partial_dgen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen, spec_wakeups[0].bits.uop.iw_issued_partial_agen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued, spec_wakeups[0].bits.uop.iw_issued connect wakeupArbs_0.io.in[0].bits.uop.fu_code[0], spec_wakeups[0].bits.uop.fu_code[0] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[1], spec_wakeups[0].bits.uop.fu_code[1] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[2], spec_wakeups[0].bits.uop.fu_code[2] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[3], spec_wakeups[0].bits.uop.fu_code[3] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[4], spec_wakeups[0].bits.uop.fu_code[4] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[5], spec_wakeups[0].bits.uop.fu_code[5] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[6], spec_wakeups[0].bits.uop.fu_code[6] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[7], spec_wakeups[0].bits.uop.fu_code[7] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[8], spec_wakeups[0].bits.uop.fu_code[8] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[9], spec_wakeups[0].bits.uop.fu_code[9] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[0], spec_wakeups[0].bits.uop.iq_type[0] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[1], spec_wakeups[0].bits.uop.iq_type[1] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[2], spec_wakeups[0].bits.uop.iq_type[2] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[3], spec_wakeups[0].bits.uop.iq_type[3] connect wakeupArbs_0.io.in[0].bits.uop.debug_pc, spec_wakeups[0].bits.uop.debug_pc connect wakeupArbs_0.io.in[0].bits.uop.is_rvc, spec_wakeups[0].bits.uop.is_rvc connect wakeupArbs_0.io.in[0].bits.uop.debug_inst, spec_wakeups[0].bits.uop.debug_inst connect wakeupArbs_0.io.in[0].bits.uop.inst, spec_wakeups[0].bits.uop.inst connect wakeupArbs_0.io.in[0].bits.rebusy, UInt<1>(0h1) when stq_valid[0] : wire uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_1, stq_uop[0] node _stq_uop_0_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_0_br_mask_T_1 = and(uop_1.br_mask, _stq_uop_0_br_mask_T) connect stq_uop[0].br_mask, _stq_uop_0_br_mask_T_1 node _T_1706 = and(io.core.brupdate.b1.mispredict_mask, uop_1.br_mask) node _T_1707 = neq(_T_1706, UInt<1>(0h0)) node _T_1708 = or(_T_1707, UInt<1>(0h0)) when _T_1708 : connect stq_valid[0], UInt<1>(0h0) connect stq_addr[0].valid, UInt<1>(0h0) connect stq_data[0].valid, UInt<1>(0h0) node _T_1709 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[0].br_mask) node _T_1710 = neq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1710, UInt<1>(0h0)) node _T_1712 = and(_T_1711, stq_valid[0]) node _T_1713 = and(_T_1712, stq_committed[0]) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_87 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_87 when stq_valid[1] : wire uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_2, stq_uop[1] node _stq_uop_1_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_1_br_mask_T_1 = and(uop_2.br_mask, _stq_uop_1_br_mask_T) connect stq_uop[1].br_mask, _stq_uop_1_br_mask_T_1 node _T_1718 = and(io.core.brupdate.b1.mispredict_mask, uop_2.br_mask) node _T_1719 = neq(_T_1718, UInt<1>(0h0)) node _T_1720 = or(_T_1719, UInt<1>(0h0)) when _T_1720 : connect stq_valid[1], UInt<1>(0h0) connect stq_addr[1].valid, UInt<1>(0h0) connect stq_data[1].valid, UInt<1>(0h0) node _T_1721 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[1].br_mask) node _T_1722 = neq(_T_1721, UInt<1>(0h0)) node _T_1723 = or(_T_1722, UInt<1>(0h0)) node _T_1724 = and(_T_1723, stq_valid[1]) node _T_1725 = and(_T_1724, stq_committed[1]) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_88 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_88 when stq_valid[2] : wire uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_3, stq_uop[2] node _stq_uop_2_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_2_br_mask_T_1 = and(uop_3.br_mask, _stq_uop_2_br_mask_T) connect stq_uop[2].br_mask, _stq_uop_2_br_mask_T_1 node _T_1730 = and(io.core.brupdate.b1.mispredict_mask, uop_3.br_mask) node _T_1731 = neq(_T_1730, UInt<1>(0h0)) node _T_1732 = or(_T_1731, UInt<1>(0h0)) when _T_1732 : connect stq_valid[2], UInt<1>(0h0) connect stq_addr[2].valid, UInt<1>(0h0) connect stq_data[2].valid, UInt<1>(0h0) node _T_1733 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[2].br_mask) node _T_1734 = neq(_T_1733, UInt<1>(0h0)) node _T_1735 = or(_T_1734, UInt<1>(0h0)) node _T_1736 = and(_T_1735, stq_valid[2]) node _T_1737 = and(_T_1736, stq_committed[2]) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_89 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_89 when stq_valid[3] : wire uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_4, stq_uop[3] node _stq_uop_3_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_3_br_mask_T_1 = and(uop_4.br_mask, _stq_uop_3_br_mask_T) connect stq_uop[3].br_mask, _stq_uop_3_br_mask_T_1 node _T_1742 = and(io.core.brupdate.b1.mispredict_mask, uop_4.br_mask) node _T_1743 = neq(_T_1742, UInt<1>(0h0)) node _T_1744 = or(_T_1743, UInt<1>(0h0)) when _T_1744 : connect stq_valid[3], UInt<1>(0h0) connect stq_addr[3].valid, UInt<1>(0h0) connect stq_data[3].valid, UInt<1>(0h0) node _T_1745 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[3].br_mask) node _T_1746 = neq(_T_1745, UInt<1>(0h0)) node _T_1747 = or(_T_1746, UInt<1>(0h0)) node _T_1748 = and(_T_1747, stq_valid[3]) node _T_1749 = and(_T_1748, stq_committed[3]) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) node _T_1751 = asUInt(reset) node _T_1752 = eq(_T_1751, UInt<1>(0h0)) when _T_1752 : node _T_1753 = eq(_T_1750, UInt<1>(0h0)) when _T_1753 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_90 assert(clock, _T_1750, UInt<1>(0h1), "") : assert_90 when stq_valid[4] : wire uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_5, stq_uop[4] node _stq_uop_4_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_4_br_mask_T_1 = and(uop_5.br_mask, _stq_uop_4_br_mask_T) connect stq_uop[4].br_mask, _stq_uop_4_br_mask_T_1 node _T_1754 = and(io.core.brupdate.b1.mispredict_mask, uop_5.br_mask) node _T_1755 = neq(_T_1754, UInt<1>(0h0)) node _T_1756 = or(_T_1755, UInt<1>(0h0)) when _T_1756 : connect stq_valid[4], UInt<1>(0h0) connect stq_addr[4].valid, UInt<1>(0h0) connect stq_data[4].valid, UInt<1>(0h0) node _T_1757 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[4].br_mask) node _T_1758 = neq(_T_1757, UInt<1>(0h0)) node _T_1759 = or(_T_1758, UInt<1>(0h0)) node _T_1760 = and(_T_1759, stq_valid[4]) node _T_1761 = and(_T_1760, stq_committed[4]) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_91 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_91 when stq_valid[5] : wire uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_6, stq_uop[5] node _stq_uop_5_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_5_br_mask_T_1 = and(uop_6.br_mask, _stq_uop_5_br_mask_T) connect stq_uop[5].br_mask, _stq_uop_5_br_mask_T_1 node _T_1766 = and(io.core.brupdate.b1.mispredict_mask, uop_6.br_mask) node _T_1767 = neq(_T_1766, UInt<1>(0h0)) node _T_1768 = or(_T_1767, UInt<1>(0h0)) when _T_1768 : connect stq_valid[5], UInt<1>(0h0) connect stq_addr[5].valid, UInt<1>(0h0) connect stq_data[5].valid, UInt<1>(0h0) node _T_1769 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[5].br_mask) node _T_1770 = neq(_T_1769, UInt<1>(0h0)) node _T_1771 = or(_T_1770, UInt<1>(0h0)) node _T_1772 = and(_T_1771, stq_valid[5]) node _T_1773 = and(_T_1772, stq_committed[5]) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = asUInt(reset) node _T_1776 = eq(_T_1775, UInt<1>(0h0)) when _T_1776 : node _T_1777 = eq(_T_1774, UInt<1>(0h0)) when _T_1777 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_92 assert(clock, _T_1774, UInt<1>(0h1), "") : assert_92 when stq_valid[6] : wire uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_7, stq_uop[6] node _stq_uop_6_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_6_br_mask_T_1 = and(uop_7.br_mask, _stq_uop_6_br_mask_T) connect stq_uop[6].br_mask, _stq_uop_6_br_mask_T_1 node _T_1778 = and(io.core.brupdate.b1.mispredict_mask, uop_7.br_mask) node _T_1779 = neq(_T_1778, UInt<1>(0h0)) node _T_1780 = or(_T_1779, UInt<1>(0h0)) when _T_1780 : connect stq_valid[6], UInt<1>(0h0) connect stq_addr[6].valid, UInt<1>(0h0) connect stq_data[6].valid, UInt<1>(0h0) node _T_1781 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[6].br_mask) node _T_1782 = neq(_T_1781, UInt<1>(0h0)) node _T_1783 = or(_T_1782, UInt<1>(0h0)) node _T_1784 = and(_T_1783, stq_valid[6]) node _T_1785 = and(_T_1784, stq_committed[6]) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) node _T_1787 = asUInt(reset) node _T_1788 = eq(_T_1787, UInt<1>(0h0)) when _T_1788 : node _T_1789 = eq(_T_1786, UInt<1>(0h0)) when _T_1789 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_93 assert(clock, _T_1786, UInt<1>(0h1), "") : assert_93 when stq_valid[7] : wire uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_8, stq_uop[7] node _stq_uop_7_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_7_br_mask_T_1 = and(uop_8.br_mask, _stq_uop_7_br_mask_T) connect stq_uop[7].br_mask, _stq_uop_7_br_mask_T_1 node _T_1790 = and(io.core.brupdate.b1.mispredict_mask, uop_8.br_mask) node _T_1791 = neq(_T_1790, UInt<1>(0h0)) node _T_1792 = or(_T_1791, UInt<1>(0h0)) when _T_1792 : connect stq_valid[7], UInt<1>(0h0) connect stq_addr[7].valid, UInt<1>(0h0) connect stq_data[7].valid, UInt<1>(0h0) node _T_1793 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[7].br_mask) node _T_1794 = neq(_T_1793, UInt<1>(0h0)) node _T_1795 = or(_T_1794, UInt<1>(0h0)) node _T_1796 = and(_T_1795, stq_valid[7]) node _T_1797 = and(_T_1796, stq_committed[7]) node _T_1798 = eq(_T_1797, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_94 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_94 when stq_valid[8] : wire uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_9, stq_uop[8] node _stq_uop_8_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_8_br_mask_T_1 = and(uop_9.br_mask, _stq_uop_8_br_mask_T) connect stq_uop[8].br_mask, _stq_uop_8_br_mask_T_1 node _T_1802 = and(io.core.brupdate.b1.mispredict_mask, uop_9.br_mask) node _T_1803 = neq(_T_1802, UInt<1>(0h0)) node _T_1804 = or(_T_1803, UInt<1>(0h0)) when _T_1804 : connect stq_valid[8], UInt<1>(0h0) connect stq_addr[8].valid, UInt<1>(0h0) connect stq_data[8].valid, UInt<1>(0h0) node _T_1805 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[8].br_mask) node _T_1806 = neq(_T_1805, UInt<1>(0h0)) node _T_1807 = or(_T_1806, UInt<1>(0h0)) node _T_1808 = and(_T_1807, stq_valid[8]) node _T_1809 = and(_T_1808, stq_committed[8]) node _T_1810 = eq(_T_1809, UInt<1>(0h0)) node _T_1811 = asUInt(reset) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) when _T_1812 : node _T_1813 = eq(_T_1810, UInt<1>(0h0)) when _T_1813 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_95 assert(clock, _T_1810, UInt<1>(0h1), "") : assert_95 when stq_valid[9] : wire uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_10, stq_uop[9] node _stq_uop_9_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_9_br_mask_T_1 = and(uop_10.br_mask, _stq_uop_9_br_mask_T) connect stq_uop[9].br_mask, _stq_uop_9_br_mask_T_1 node _T_1814 = and(io.core.brupdate.b1.mispredict_mask, uop_10.br_mask) node _T_1815 = neq(_T_1814, UInt<1>(0h0)) node _T_1816 = or(_T_1815, UInt<1>(0h0)) when _T_1816 : connect stq_valid[9], UInt<1>(0h0) connect stq_addr[9].valid, UInt<1>(0h0) connect stq_data[9].valid, UInt<1>(0h0) node _T_1817 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[9].br_mask) node _T_1818 = neq(_T_1817, UInt<1>(0h0)) node _T_1819 = or(_T_1818, UInt<1>(0h0)) node _T_1820 = and(_T_1819, stq_valid[9]) node _T_1821 = and(_T_1820, stq_committed[9]) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(_T_1822, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_96 assert(clock, _T_1822, UInt<1>(0h1), "") : assert_96 when stq_valid[10] : wire uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_11, stq_uop[10] node _stq_uop_10_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_10_br_mask_T_1 = and(uop_11.br_mask, _stq_uop_10_br_mask_T) connect stq_uop[10].br_mask, _stq_uop_10_br_mask_T_1 node _T_1826 = and(io.core.brupdate.b1.mispredict_mask, uop_11.br_mask) node _T_1827 = neq(_T_1826, UInt<1>(0h0)) node _T_1828 = or(_T_1827, UInt<1>(0h0)) when _T_1828 : connect stq_valid[10], UInt<1>(0h0) connect stq_addr[10].valid, UInt<1>(0h0) connect stq_data[10].valid, UInt<1>(0h0) node _T_1829 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[10].br_mask) node _T_1830 = neq(_T_1829, UInt<1>(0h0)) node _T_1831 = or(_T_1830, UInt<1>(0h0)) node _T_1832 = and(_T_1831, stq_valid[10]) node _T_1833 = and(_T_1832, stq_committed[10]) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_97 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_97 when stq_valid[11] : wire uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_12, stq_uop[11] node _stq_uop_11_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_11_br_mask_T_1 = and(uop_12.br_mask, _stq_uop_11_br_mask_T) connect stq_uop[11].br_mask, _stq_uop_11_br_mask_T_1 node _T_1838 = and(io.core.brupdate.b1.mispredict_mask, uop_12.br_mask) node _T_1839 = neq(_T_1838, UInt<1>(0h0)) node _T_1840 = or(_T_1839, UInt<1>(0h0)) when _T_1840 : connect stq_valid[11], UInt<1>(0h0) connect stq_addr[11].valid, UInt<1>(0h0) connect stq_data[11].valid, UInt<1>(0h0) node _T_1841 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[11].br_mask) node _T_1842 = neq(_T_1841, UInt<1>(0h0)) node _T_1843 = or(_T_1842, UInt<1>(0h0)) node _T_1844 = and(_T_1843, stq_valid[11]) node _T_1845 = and(_T_1844, stq_committed[11]) node _T_1846 = eq(_T_1845, UInt<1>(0h0)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_98 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_98 when stq_valid[12] : wire uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_13, stq_uop[12] node _stq_uop_12_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_12_br_mask_T_1 = and(uop_13.br_mask, _stq_uop_12_br_mask_T) connect stq_uop[12].br_mask, _stq_uop_12_br_mask_T_1 node _T_1850 = and(io.core.brupdate.b1.mispredict_mask, uop_13.br_mask) node _T_1851 = neq(_T_1850, UInt<1>(0h0)) node _T_1852 = or(_T_1851, UInt<1>(0h0)) when _T_1852 : connect stq_valid[12], UInt<1>(0h0) connect stq_addr[12].valid, UInt<1>(0h0) connect stq_data[12].valid, UInt<1>(0h0) node _T_1853 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[12].br_mask) node _T_1854 = neq(_T_1853, UInt<1>(0h0)) node _T_1855 = or(_T_1854, UInt<1>(0h0)) node _T_1856 = and(_T_1855, stq_valid[12]) node _T_1857 = and(_T_1856, stq_committed[12]) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(_T_1858, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_99 assert(clock, _T_1858, UInt<1>(0h1), "") : assert_99 when stq_valid[13] : wire uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_14, stq_uop[13] node _stq_uop_13_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_13_br_mask_T_1 = and(uop_14.br_mask, _stq_uop_13_br_mask_T) connect stq_uop[13].br_mask, _stq_uop_13_br_mask_T_1 node _T_1862 = and(io.core.brupdate.b1.mispredict_mask, uop_14.br_mask) node _T_1863 = neq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(_T_1863, UInt<1>(0h0)) when _T_1864 : connect stq_valid[13], UInt<1>(0h0) connect stq_addr[13].valid, UInt<1>(0h0) connect stq_data[13].valid, UInt<1>(0h0) node _T_1865 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[13].br_mask) node _T_1866 = neq(_T_1865, UInt<1>(0h0)) node _T_1867 = or(_T_1866, UInt<1>(0h0)) node _T_1868 = and(_T_1867, stq_valid[13]) node _T_1869 = and(_T_1868, stq_committed[13]) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_100 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_100 when stq_valid[14] : wire uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_15, stq_uop[14] node _stq_uop_14_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_14_br_mask_T_1 = and(uop_15.br_mask, _stq_uop_14_br_mask_T) connect stq_uop[14].br_mask, _stq_uop_14_br_mask_T_1 node _T_1874 = and(io.core.brupdate.b1.mispredict_mask, uop_15.br_mask) node _T_1875 = neq(_T_1874, UInt<1>(0h0)) node _T_1876 = or(_T_1875, UInt<1>(0h0)) when _T_1876 : connect stq_valid[14], UInt<1>(0h0) connect stq_addr[14].valid, UInt<1>(0h0) connect stq_data[14].valid, UInt<1>(0h0) node _T_1877 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[14].br_mask) node _T_1878 = neq(_T_1877, UInt<1>(0h0)) node _T_1879 = or(_T_1878, UInt<1>(0h0)) node _T_1880 = and(_T_1879, stq_valid[14]) node _T_1881 = and(_T_1880, stq_committed[14]) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(_T_1882, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_101 assert(clock, _T_1882, UInt<1>(0h1), "") : assert_101 when stq_valid[15] : wire uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_16, stq_uop[15] node _stq_uop_15_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_15_br_mask_T_1 = and(uop_16.br_mask, _stq_uop_15_br_mask_T) connect stq_uop[15].br_mask, _stq_uop_15_br_mask_T_1 node _T_1886 = and(io.core.brupdate.b1.mispredict_mask, uop_16.br_mask) node _T_1887 = neq(_T_1886, UInt<1>(0h0)) node _T_1888 = or(_T_1887, UInt<1>(0h0)) when _T_1888 : connect stq_valid[15], UInt<1>(0h0) connect stq_addr[15].valid, UInt<1>(0h0) connect stq_data[15].valid, UInt<1>(0h0) node _T_1889 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[15].br_mask) node _T_1890 = neq(_T_1889, UInt<1>(0h0)) node _T_1891 = or(_T_1890, UInt<1>(0h0)) node _T_1892 = and(_T_1891, stq_valid[15]) node _T_1893 = and(_T_1892, stq_committed[15]) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_102 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_102 when stq_valid[16] : wire uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_17, stq_uop[16] node _stq_uop_16_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_16_br_mask_T_1 = and(uop_17.br_mask, _stq_uop_16_br_mask_T) connect stq_uop[16].br_mask, _stq_uop_16_br_mask_T_1 node _T_1898 = and(io.core.brupdate.b1.mispredict_mask, uop_17.br_mask) node _T_1899 = neq(_T_1898, UInt<1>(0h0)) node _T_1900 = or(_T_1899, UInt<1>(0h0)) when _T_1900 : connect stq_valid[16], UInt<1>(0h0) connect stq_addr[16].valid, UInt<1>(0h0) connect stq_data[16].valid, UInt<1>(0h0) node _T_1901 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[16].br_mask) node _T_1902 = neq(_T_1901, UInt<1>(0h0)) node _T_1903 = or(_T_1902, UInt<1>(0h0)) node _T_1904 = and(_T_1903, stq_valid[16]) node _T_1905 = and(_T_1904, stq_committed[16]) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_103 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_103 when stq_valid[17] : wire uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_18, stq_uop[17] node _stq_uop_17_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_17_br_mask_T_1 = and(uop_18.br_mask, _stq_uop_17_br_mask_T) connect stq_uop[17].br_mask, _stq_uop_17_br_mask_T_1 node _T_1910 = and(io.core.brupdate.b1.mispredict_mask, uop_18.br_mask) node _T_1911 = neq(_T_1910, UInt<1>(0h0)) node _T_1912 = or(_T_1911, UInt<1>(0h0)) when _T_1912 : connect stq_valid[17], UInt<1>(0h0) connect stq_addr[17].valid, UInt<1>(0h0) connect stq_data[17].valid, UInt<1>(0h0) node _T_1913 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[17].br_mask) node _T_1914 = neq(_T_1913, UInt<1>(0h0)) node _T_1915 = or(_T_1914, UInt<1>(0h0)) node _T_1916 = and(_T_1915, stq_valid[17]) node _T_1917 = and(_T_1916, stq_committed[17]) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_104 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_104 when stq_valid[18] : wire uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_19, stq_uop[18] node _stq_uop_18_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_18_br_mask_T_1 = and(uop_19.br_mask, _stq_uop_18_br_mask_T) connect stq_uop[18].br_mask, _stq_uop_18_br_mask_T_1 node _T_1922 = and(io.core.brupdate.b1.mispredict_mask, uop_19.br_mask) node _T_1923 = neq(_T_1922, UInt<1>(0h0)) node _T_1924 = or(_T_1923, UInt<1>(0h0)) when _T_1924 : connect stq_valid[18], UInt<1>(0h0) connect stq_addr[18].valid, UInt<1>(0h0) connect stq_data[18].valid, UInt<1>(0h0) node _T_1925 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[18].br_mask) node _T_1926 = neq(_T_1925, UInt<1>(0h0)) node _T_1927 = or(_T_1926, UInt<1>(0h0)) node _T_1928 = and(_T_1927, stq_valid[18]) node _T_1929 = and(_T_1928, stq_committed[18]) node _T_1930 = eq(_T_1929, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_105 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_105 when stq_valid[19] : wire uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_20, stq_uop[19] node _stq_uop_19_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_19_br_mask_T_1 = and(uop_20.br_mask, _stq_uop_19_br_mask_T) connect stq_uop[19].br_mask, _stq_uop_19_br_mask_T_1 node _T_1934 = and(io.core.brupdate.b1.mispredict_mask, uop_20.br_mask) node _T_1935 = neq(_T_1934, UInt<1>(0h0)) node _T_1936 = or(_T_1935, UInt<1>(0h0)) when _T_1936 : connect stq_valid[19], UInt<1>(0h0) connect stq_addr[19].valid, UInt<1>(0h0) connect stq_data[19].valid, UInt<1>(0h0) node _T_1937 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[19].br_mask) node _T_1938 = neq(_T_1937, UInt<1>(0h0)) node _T_1939 = or(_T_1938, UInt<1>(0h0)) node _T_1940 = and(_T_1939, stq_valid[19]) node _T_1941 = and(_T_1940, stq_committed[19]) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) node _T_1943 = asUInt(reset) node _T_1944 = eq(_T_1943, UInt<1>(0h0)) when _T_1944 : node _T_1945 = eq(_T_1942, UInt<1>(0h0)) when _T_1945 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_106 assert(clock, _T_1942, UInt<1>(0h1), "") : assert_106 when stq_valid[20] : wire uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_21, stq_uop[20] node _stq_uop_20_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_20_br_mask_T_1 = and(uop_21.br_mask, _stq_uop_20_br_mask_T) connect stq_uop[20].br_mask, _stq_uop_20_br_mask_T_1 node _T_1946 = and(io.core.brupdate.b1.mispredict_mask, uop_21.br_mask) node _T_1947 = neq(_T_1946, UInt<1>(0h0)) node _T_1948 = or(_T_1947, UInt<1>(0h0)) when _T_1948 : connect stq_valid[20], UInt<1>(0h0) connect stq_addr[20].valid, UInt<1>(0h0) connect stq_data[20].valid, UInt<1>(0h0) node _T_1949 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[20].br_mask) node _T_1950 = neq(_T_1949, UInt<1>(0h0)) node _T_1951 = or(_T_1950, UInt<1>(0h0)) node _T_1952 = and(_T_1951, stq_valid[20]) node _T_1953 = and(_T_1952, stq_committed[20]) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_107 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_107 when stq_valid[21] : wire uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_22, stq_uop[21] node _stq_uop_21_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_21_br_mask_T_1 = and(uop_22.br_mask, _stq_uop_21_br_mask_T) connect stq_uop[21].br_mask, _stq_uop_21_br_mask_T_1 node _T_1958 = and(io.core.brupdate.b1.mispredict_mask, uop_22.br_mask) node _T_1959 = neq(_T_1958, UInt<1>(0h0)) node _T_1960 = or(_T_1959, UInt<1>(0h0)) when _T_1960 : connect stq_valid[21], UInt<1>(0h0) connect stq_addr[21].valid, UInt<1>(0h0) connect stq_data[21].valid, UInt<1>(0h0) node _T_1961 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[21].br_mask) node _T_1962 = neq(_T_1961, UInt<1>(0h0)) node _T_1963 = or(_T_1962, UInt<1>(0h0)) node _T_1964 = and(_T_1963, stq_valid[21]) node _T_1965 = and(_T_1964, stq_committed[21]) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_108 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_108 when stq_valid[22] : wire uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_23, stq_uop[22] node _stq_uop_22_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_22_br_mask_T_1 = and(uop_23.br_mask, _stq_uop_22_br_mask_T) connect stq_uop[22].br_mask, _stq_uop_22_br_mask_T_1 node _T_1970 = and(io.core.brupdate.b1.mispredict_mask, uop_23.br_mask) node _T_1971 = neq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(_T_1971, UInt<1>(0h0)) when _T_1972 : connect stq_valid[22], UInt<1>(0h0) connect stq_addr[22].valid, UInt<1>(0h0) connect stq_data[22].valid, UInt<1>(0h0) node _T_1973 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[22].br_mask) node _T_1974 = neq(_T_1973, UInt<1>(0h0)) node _T_1975 = or(_T_1974, UInt<1>(0h0)) node _T_1976 = and(_T_1975, stq_valid[22]) node _T_1977 = and(_T_1976, stq_committed[22]) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_109 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_109 when stq_valid[23] : wire uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_24, stq_uop[23] node _stq_uop_23_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_23_br_mask_T_1 = and(uop_24.br_mask, _stq_uop_23_br_mask_T) connect stq_uop[23].br_mask, _stq_uop_23_br_mask_T_1 node _T_1982 = and(io.core.brupdate.b1.mispredict_mask, uop_24.br_mask) node _T_1983 = neq(_T_1982, UInt<1>(0h0)) node _T_1984 = or(_T_1983, UInt<1>(0h0)) when _T_1984 : connect stq_valid[23], UInt<1>(0h0) connect stq_addr[23].valid, UInt<1>(0h0) connect stq_data[23].valid, UInt<1>(0h0) node _T_1985 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[23].br_mask) node _T_1986 = neq(_T_1985, UInt<1>(0h0)) node _T_1987 = or(_T_1986, UInt<1>(0h0)) node _T_1988 = and(_T_1987, stq_valid[23]) node _T_1989 = and(_T_1988, stq_committed[23]) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_110 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_110 when ldq_valid[0] : wire uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_25, ldq_uop[0] node _ldq_uop_0_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_0_br_mask_T_1 = and(uop_25.br_mask, _ldq_uop_0_br_mask_T) connect ldq_uop[0].br_mask, _ldq_uop_0_br_mask_T_1 node _T_1994 = and(io.core.brupdate.b1.mispredict_mask, uop_25.br_mask) node _T_1995 = neq(_T_1994, UInt<1>(0h0)) node _T_1996 = or(_T_1995, io.core.exception) when _T_1996 : connect ldq_valid[0], UInt<1>(0h0) connect ldq_addr[0].valid, UInt<1>(0h0) when ldq_valid[1] : wire uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_26, ldq_uop[1] node _ldq_uop_1_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_1_br_mask_T_1 = and(uop_26.br_mask, _ldq_uop_1_br_mask_T) connect ldq_uop[1].br_mask, _ldq_uop_1_br_mask_T_1 node _T_1997 = and(io.core.brupdate.b1.mispredict_mask, uop_26.br_mask) node _T_1998 = neq(_T_1997, UInt<1>(0h0)) node _T_1999 = or(_T_1998, io.core.exception) when _T_1999 : connect ldq_valid[1], UInt<1>(0h0) connect ldq_addr[1].valid, UInt<1>(0h0) when ldq_valid[2] : wire uop_27 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_27, ldq_uop[2] node _ldq_uop_2_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_2_br_mask_T_1 = and(uop_27.br_mask, _ldq_uop_2_br_mask_T) connect ldq_uop[2].br_mask, _ldq_uop_2_br_mask_T_1 node _T_2000 = and(io.core.brupdate.b1.mispredict_mask, uop_27.br_mask) node _T_2001 = neq(_T_2000, UInt<1>(0h0)) node _T_2002 = or(_T_2001, io.core.exception) when _T_2002 : connect ldq_valid[2], UInt<1>(0h0) connect ldq_addr[2].valid, UInt<1>(0h0) when ldq_valid[3] : wire uop_28 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_28, ldq_uop[3] node _ldq_uop_3_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_3_br_mask_T_1 = and(uop_28.br_mask, _ldq_uop_3_br_mask_T) connect ldq_uop[3].br_mask, _ldq_uop_3_br_mask_T_1 node _T_2003 = and(io.core.brupdate.b1.mispredict_mask, uop_28.br_mask) node _T_2004 = neq(_T_2003, UInt<1>(0h0)) node _T_2005 = or(_T_2004, io.core.exception) when _T_2005 : connect ldq_valid[3], UInt<1>(0h0) connect ldq_addr[3].valid, UInt<1>(0h0) when ldq_valid[4] : wire uop_29 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_29, ldq_uop[4] node _ldq_uop_4_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_4_br_mask_T_1 = and(uop_29.br_mask, _ldq_uop_4_br_mask_T) connect ldq_uop[4].br_mask, _ldq_uop_4_br_mask_T_1 node _T_2006 = and(io.core.brupdate.b1.mispredict_mask, uop_29.br_mask) node _T_2007 = neq(_T_2006, UInt<1>(0h0)) node _T_2008 = or(_T_2007, io.core.exception) when _T_2008 : connect ldq_valid[4], UInt<1>(0h0) connect ldq_addr[4].valid, UInt<1>(0h0) when ldq_valid[5] : wire uop_30 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_30, ldq_uop[5] node _ldq_uop_5_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_5_br_mask_T_1 = and(uop_30.br_mask, _ldq_uop_5_br_mask_T) connect ldq_uop[5].br_mask, _ldq_uop_5_br_mask_T_1 node _T_2009 = and(io.core.brupdate.b1.mispredict_mask, uop_30.br_mask) node _T_2010 = neq(_T_2009, UInt<1>(0h0)) node _T_2011 = or(_T_2010, io.core.exception) when _T_2011 : connect ldq_valid[5], UInt<1>(0h0) connect ldq_addr[5].valid, UInt<1>(0h0) when ldq_valid[6] : wire uop_31 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_31, ldq_uop[6] node _ldq_uop_6_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_6_br_mask_T_1 = and(uop_31.br_mask, _ldq_uop_6_br_mask_T) connect ldq_uop[6].br_mask, _ldq_uop_6_br_mask_T_1 node _T_2012 = and(io.core.brupdate.b1.mispredict_mask, uop_31.br_mask) node _T_2013 = neq(_T_2012, UInt<1>(0h0)) node _T_2014 = or(_T_2013, io.core.exception) when _T_2014 : connect ldq_valid[6], UInt<1>(0h0) connect ldq_addr[6].valid, UInt<1>(0h0) when ldq_valid[7] : wire uop_32 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_32, ldq_uop[7] node _ldq_uop_7_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_7_br_mask_T_1 = and(uop_32.br_mask, _ldq_uop_7_br_mask_T) connect ldq_uop[7].br_mask, _ldq_uop_7_br_mask_T_1 node _T_2015 = and(io.core.brupdate.b1.mispredict_mask, uop_32.br_mask) node _T_2016 = neq(_T_2015, UInt<1>(0h0)) node _T_2017 = or(_T_2016, io.core.exception) when _T_2017 : connect ldq_valid[7], UInt<1>(0h0) connect ldq_addr[7].valid, UInt<1>(0h0) when ldq_valid[8] : wire uop_33 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_33, ldq_uop[8] node _ldq_uop_8_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_8_br_mask_T_1 = and(uop_33.br_mask, _ldq_uop_8_br_mask_T) connect ldq_uop[8].br_mask, _ldq_uop_8_br_mask_T_1 node _T_2018 = and(io.core.brupdate.b1.mispredict_mask, uop_33.br_mask) node _T_2019 = neq(_T_2018, UInt<1>(0h0)) node _T_2020 = or(_T_2019, io.core.exception) when _T_2020 : connect ldq_valid[8], UInt<1>(0h0) connect ldq_addr[8].valid, UInt<1>(0h0) when ldq_valid[9] : wire uop_34 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_34, ldq_uop[9] node _ldq_uop_9_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_9_br_mask_T_1 = and(uop_34.br_mask, _ldq_uop_9_br_mask_T) connect ldq_uop[9].br_mask, _ldq_uop_9_br_mask_T_1 node _T_2021 = and(io.core.brupdate.b1.mispredict_mask, uop_34.br_mask) node _T_2022 = neq(_T_2021, UInt<1>(0h0)) node _T_2023 = or(_T_2022, io.core.exception) when _T_2023 : connect ldq_valid[9], UInt<1>(0h0) connect ldq_addr[9].valid, UInt<1>(0h0) when ldq_valid[10] : wire uop_35 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_35, ldq_uop[10] node _ldq_uop_10_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_10_br_mask_T_1 = and(uop_35.br_mask, _ldq_uop_10_br_mask_T) connect ldq_uop[10].br_mask, _ldq_uop_10_br_mask_T_1 node _T_2024 = and(io.core.brupdate.b1.mispredict_mask, uop_35.br_mask) node _T_2025 = neq(_T_2024, UInt<1>(0h0)) node _T_2026 = or(_T_2025, io.core.exception) when _T_2026 : connect ldq_valid[10], UInt<1>(0h0) connect ldq_addr[10].valid, UInt<1>(0h0) when ldq_valid[11] : wire uop_36 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_36, ldq_uop[11] node _ldq_uop_11_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_11_br_mask_T_1 = and(uop_36.br_mask, _ldq_uop_11_br_mask_T) connect ldq_uop[11].br_mask, _ldq_uop_11_br_mask_T_1 node _T_2027 = and(io.core.brupdate.b1.mispredict_mask, uop_36.br_mask) node _T_2028 = neq(_T_2027, UInt<1>(0h0)) node _T_2029 = or(_T_2028, io.core.exception) when _T_2029 : connect ldq_valid[11], UInt<1>(0h0) connect ldq_addr[11].valid, UInt<1>(0h0) when ldq_valid[12] : wire uop_37 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_37, ldq_uop[12] node _ldq_uop_12_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_12_br_mask_T_1 = and(uop_37.br_mask, _ldq_uop_12_br_mask_T) connect ldq_uop[12].br_mask, _ldq_uop_12_br_mask_T_1 node _T_2030 = and(io.core.brupdate.b1.mispredict_mask, uop_37.br_mask) node _T_2031 = neq(_T_2030, UInt<1>(0h0)) node _T_2032 = or(_T_2031, io.core.exception) when _T_2032 : connect ldq_valid[12], UInt<1>(0h0) connect ldq_addr[12].valid, UInt<1>(0h0) when ldq_valid[13] : wire uop_38 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_38, ldq_uop[13] node _ldq_uop_13_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_13_br_mask_T_1 = and(uop_38.br_mask, _ldq_uop_13_br_mask_T) connect ldq_uop[13].br_mask, _ldq_uop_13_br_mask_T_1 node _T_2033 = and(io.core.brupdate.b1.mispredict_mask, uop_38.br_mask) node _T_2034 = neq(_T_2033, UInt<1>(0h0)) node _T_2035 = or(_T_2034, io.core.exception) when _T_2035 : connect ldq_valid[13], UInt<1>(0h0) connect ldq_addr[13].valid, UInt<1>(0h0) when ldq_valid[14] : wire uop_39 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_39, ldq_uop[14] node _ldq_uop_14_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_14_br_mask_T_1 = and(uop_39.br_mask, _ldq_uop_14_br_mask_T) connect ldq_uop[14].br_mask, _ldq_uop_14_br_mask_T_1 node _T_2036 = and(io.core.brupdate.b1.mispredict_mask, uop_39.br_mask) node _T_2037 = neq(_T_2036, UInt<1>(0h0)) node _T_2038 = or(_T_2037, io.core.exception) when _T_2038 : connect ldq_valid[14], UInt<1>(0h0) connect ldq_addr[14].valid, UInt<1>(0h0) when ldq_valid[15] : wire uop_40 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_40, ldq_uop[15] node _ldq_uop_15_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_15_br_mask_T_1 = and(uop_40.br_mask, _ldq_uop_15_br_mask_T) connect ldq_uop[15].br_mask, _ldq_uop_15_br_mask_T_1 node _T_2039 = and(io.core.brupdate.b1.mispredict_mask, uop_40.br_mask) node _T_2040 = neq(_T_2039, UInt<1>(0h0)) node _T_2041 = or(_T_2040, io.core.exception) when _T_2041 : connect ldq_valid[15], UInt<1>(0h0) connect ldq_addr[15].valid, UInt<1>(0h0) when ldq_valid[16] : wire uop_41 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_41, ldq_uop[16] node _ldq_uop_16_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_16_br_mask_T_1 = and(uop_41.br_mask, _ldq_uop_16_br_mask_T) connect ldq_uop[16].br_mask, _ldq_uop_16_br_mask_T_1 node _T_2042 = and(io.core.brupdate.b1.mispredict_mask, uop_41.br_mask) node _T_2043 = neq(_T_2042, UInt<1>(0h0)) node _T_2044 = or(_T_2043, io.core.exception) when _T_2044 : connect ldq_valid[16], UInt<1>(0h0) connect ldq_addr[16].valid, UInt<1>(0h0) when ldq_valid[17] : wire uop_42 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_42, ldq_uop[17] node _ldq_uop_17_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_17_br_mask_T_1 = and(uop_42.br_mask, _ldq_uop_17_br_mask_T) connect ldq_uop[17].br_mask, _ldq_uop_17_br_mask_T_1 node _T_2045 = and(io.core.brupdate.b1.mispredict_mask, uop_42.br_mask) node _T_2046 = neq(_T_2045, UInt<1>(0h0)) node _T_2047 = or(_T_2046, io.core.exception) when _T_2047 : connect ldq_valid[17], UInt<1>(0h0) connect ldq_addr[17].valid, UInt<1>(0h0) when ldq_valid[18] : wire uop_43 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_43, ldq_uop[18] node _ldq_uop_18_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_18_br_mask_T_1 = and(uop_43.br_mask, _ldq_uop_18_br_mask_T) connect ldq_uop[18].br_mask, _ldq_uop_18_br_mask_T_1 node _T_2048 = and(io.core.brupdate.b1.mispredict_mask, uop_43.br_mask) node _T_2049 = neq(_T_2048, UInt<1>(0h0)) node _T_2050 = or(_T_2049, io.core.exception) when _T_2050 : connect ldq_valid[18], UInt<1>(0h0) connect ldq_addr[18].valid, UInt<1>(0h0) when ldq_valid[19] : wire uop_44 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_44, ldq_uop[19] node _ldq_uop_19_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_19_br_mask_T_1 = and(uop_44.br_mask, _ldq_uop_19_br_mask_T) connect ldq_uop[19].br_mask, _ldq_uop_19_br_mask_T_1 node _T_2051 = and(io.core.brupdate.b1.mispredict_mask, uop_44.br_mask) node _T_2052 = neq(_T_2051, UInt<1>(0h0)) node _T_2053 = or(_T_2052, io.core.exception) when _T_2053 : connect ldq_valid[19], UInt<1>(0h0) connect ldq_addr[19].valid, UInt<1>(0h0) when ldq_valid[20] : wire uop_45 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_45, ldq_uop[20] node _ldq_uop_20_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_20_br_mask_T_1 = and(uop_45.br_mask, _ldq_uop_20_br_mask_T) connect ldq_uop[20].br_mask, _ldq_uop_20_br_mask_T_1 node _T_2054 = and(io.core.brupdate.b1.mispredict_mask, uop_45.br_mask) node _T_2055 = neq(_T_2054, UInt<1>(0h0)) node _T_2056 = or(_T_2055, io.core.exception) when _T_2056 : connect ldq_valid[20], UInt<1>(0h0) connect ldq_addr[20].valid, UInt<1>(0h0) when ldq_valid[21] : wire uop_46 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_46, ldq_uop[21] node _ldq_uop_21_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_21_br_mask_T_1 = and(uop_46.br_mask, _ldq_uop_21_br_mask_T) connect ldq_uop[21].br_mask, _ldq_uop_21_br_mask_T_1 node _T_2057 = and(io.core.brupdate.b1.mispredict_mask, uop_46.br_mask) node _T_2058 = neq(_T_2057, UInt<1>(0h0)) node _T_2059 = or(_T_2058, io.core.exception) when _T_2059 : connect ldq_valid[21], UInt<1>(0h0) connect ldq_addr[21].valid, UInt<1>(0h0) when ldq_valid[22] : wire uop_47 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_47, ldq_uop[22] node _ldq_uop_22_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_22_br_mask_T_1 = and(uop_47.br_mask, _ldq_uop_22_br_mask_T) connect ldq_uop[22].br_mask, _ldq_uop_22_br_mask_T_1 node _T_2060 = and(io.core.brupdate.b1.mispredict_mask, uop_47.br_mask) node _T_2061 = neq(_T_2060, UInt<1>(0h0)) node _T_2062 = or(_T_2061, io.core.exception) when _T_2062 : connect ldq_valid[22], UInt<1>(0h0) connect ldq_addr[22].valid, UInt<1>(0h0) when ldq_valid[23] : wire uop_48 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_48, ldq_uop[23] node _ldq_uop_23_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_23_br_mask_T_1 = and(uop_48.br_mask, _ldq_uop_23_br_mask_T) connect ldq_uop[23].br_mask, _ldq_uop_23_br_mask_T_1 node _T_2063 = and(io.core.brupdate.b1.mispredict_mask, uop_48.br_mask) node _T_2064 = neq(_T_2063, UInt<1>(0h0)) node _T_2065 = or(_T_2064, io.core.exception) when _T_2065 : connect ldq_valid[23], UInt<1>(0h0) connect ldq_addr[23].valid, UInt<1>(0h0) node _T_2066 = eq(io.core.exception, UInt<1>(0h0)) node _T_2067 = and(io.core.brupdate.b2.mispredict, _T_2066) when _T_2067 : connect stq_tail, io.core.brupdate.b2.uop.stq_idx connect ldq_tail, io.core.brupdate.b2.uop.ldq_idx node commit_store = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_stq) node commit_load = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_ldq) wire l_uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_24, ldq_uop[ldq_head] wire s_uop_27 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_27, stq_uop[stq_commit_head] when commit_store : connect stq_committed[stq_commit_head], UInt<1>(0h1) connect stq_can_execute[stq_commit_head], UInt<1>(0h1) else : when commit_load : node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(ldq_valid[ldq_head], UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_111 assert(clock, ldq_valid[ldq_head], UInt<1>(0h1), "") : assert_111 node _T_2071 = or(ldq_executed[ldq_head], ldq_forward_std_val[ldq_head]) node _T_2072 = and(_T_2071, ldq_succeeded[ldq_head]) node _T_2073 = asUInt(reset) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) when _T_2074 : node _T_2075 = eq(_T_2072, UInt<1>(0h0)) when _T_2075 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) \|\| ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_112 assert(clock, _T_2072, UInt<1>(0h1), "") : assert_112 connect ldq_valid[ldq_head], UInt<1>(0h0) node wrap_9 = eq(stq_commit_head, UInt<5>(0h17)) node _T_2076 = add(stq_commit_head, UInt<1>(0h1)) node _T_2077 = tail(_T_2076, 1) node _T_2078 = mux(wrap_9, UInt<1>(0h0), _T_2077) node _T_2079 = mux(commit_store, _T_2078, stq_commit_head) node wrap_10 = eq(ldq_head, UInt<5>(0h17)) node _T_2080 = add(ldq_head, UInt<1>(0h1)) node _T_2081 = tail(_T_2080, 1) node _T_2082 = mux(wrap_10, UInt<1>(0h0), _T_2081) node _T_2083 = mux(commit_load, _T_2082, ldq_head) node commit_store_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_stq) node commit_load_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_ldq) wire l_uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_25, ldq_uop[_T_2083] wire s_uop_28 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_28, stq_uop[_T_2079] when commit_store_1 : connect stq_committed[_T_2079], UInt<1>(0h1) connect stq_can_execute[_T_2079], UInt<1>(0h1) else : when commit_load_1 : node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(ldq_valid[_T_2083], UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_113 assert(clock, ldq_valid[_T_2083], UInt<1>(0h1), "") : assert_113 node _T_2087 = or(ldq_executed[_T_2083], ldq_forward_std_val[_T_2083]) node _T_2088 = and(_T_2087, ldq_succeeded[_T_2083]) node _T_2089 = asUInt(reset) node _T_2090 = eq(_T_2089, UInt<1>(0h0)) when _T_2090 : node _T_2091 = eq(_T_2088, UInt<1>(0h0)) when _T_2091 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) \|\| ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_114 assert(clock, _T_2088, UInt<1>(0h1), "") : assert_114 connect ldq_valid[_T_2083], UInt<1>(0h0) node wrap_11 = eq(_T_2079, UInt<5>(0h17)) node _T_2092 = add(_T_2079, UInt<1>(0h1)) node _T_2093 = tail(_T_2092, 1) node _T_2094 = mux(wrap_11, UInt<1>(0h0), _T_2093) node _T_2095 = mux(commit_store_1, _T_2094, _T_2079) node wrap_12 = eq(_T_2083, UInt<5>(0h17)) node _T_2096 = add(_T_2083, UInt<1>(0h1)) node _T_2097 = tail(_T_2096, 1) node _T_2098 = mux(wrap_12, UInt<1>(0h0), _T_2097) node _T_2099 = mux(commit_load_1, _T_2098, _T_2083) node commit_store_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_stq) node commit_load_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_ldq) wire l_uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_26, ldq_uop[_T_2099] wire s_uop_29 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_29, stq_uop[_T_2095] when commit_store_2 : connect stq_committed[_T_2095], UInt<1>(0h1) connect stq_can_execute[_T_2095], UInt<1>(0h1) else : when commit_load_2 : node _T_2100 = asUInt(reset) node _T_2101 = eq(_T_2100, UInt<1>(0h0)) when _T_2101 : node _T_2102 = eq(ldq_valid[_T_2099], UInt<1>(0h0)) when _T_2102 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_115 assert(clock, ldq_valid[_T_2099], UInt<1>(0h1), "") : assert_115 node _T_2103 = or(ldq_executed[_T_2099], ldq_forward_std_val[_T_2099]) node _T_2104 = and(_T_2103, ldq_succeeded[_T_2099]) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) \|\| ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_116 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_116 connect ldq_valid[_T_2099], UInt<1>(0h0) node wrap_13 = eq(_T_2095, UInt<5>(0h17)) node _T_2108 = add(_T_2095, UInt<1>(0h1)) node _T_2109 = tail(_T_2108, 1) node _T_2110 = mux(wrap_13, UInt<1>(0h0), _T_2109) node _T_2111 = mux(commit_store_2, _T_2110, _T_2095) node wrap_14 = eq(_T_2099, UInt<5>(0h17)) node _T_2112 = add(_T_2099, UInt<1>(0h1)) node _T_2113 = tail(_T_2112, 1) node _T_2114 = mux(wrap_14, UInt<1>(0h0), _T_2113) node _T_2115 = mux(commit_load_2, _T_2114, _T_2099) connect stq_commit_head, _T_2111 connect ldq_head, _T_2115 node _T_2116 = and(stq_valid[stq_head], stq_committed[stq_head]) when _T_2116 : node _T_2117 = eq(io.dmem.ordered, UInt<1>(0h0)) node _T_2118 = and(stq_uop[stq_head].is_fence, _T_2117) when _T_2118 : connect io.dmem.force_order, UInt<1>(0h1) connect store_needs_order, UInt<1>(0h1) node _clear_store_T = mux(stq_uop[stq_head].is_fence, io.dmem.ordered, stq_succeeded[stq_head]) connect clear_store, _clear_store_T when clear_store : connect stq_valid[stq_head], UInt<1>(0h0) node stq_head_wrap = eq(stq_head, UInt<5>(0h17)) node _stq_head_T = add(stq_head, UInt<1>(0h1)) node _stq_head_T_1 = tail(_stq_head_T, 1) node _stq_head_T_2 = mux(stq_head_wrap, UInt<1>(0h0), _stq_head_T_1) connect stq_head, _stq_head_T_2 when stq_uop[stq_head].is_fence : node stq_execute_head_wrap_1 = eq(stq_execute_head, UInt<5>(0h17)) node _stq_execute_head_T_3 = add(stq_execute_head, UInt<1>(0h1)) node _stq_execute_head_T_4 = tail(_stq_execute_head_T_3, 1) node _stq_execute_head_T_5 = mux(stq_execute_head_wrap_1, UInt<1>(0h0), _stq_execute_head_T_4) connect stq_execute_head, _stq_execute_head_T_5 connect io.hellacache.req.ready, UInt<1>(0h0) connect io.hellacache.s2_nack, UInt<1>(0h0) connect io.hellacache.s2_nack_cause_raw, UInt<1>(0h0) invalidate io.hellacache.s2_uncached invalidate io.hellacache.s2_paddr wire _io_hellacache_s2_xcpt_WIRE : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}} connect _io_hellacache_s2_xcpt_WIRE.ae.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.gf.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.pf.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ma.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0) connect io.hellacache.s2_xcpt, _io_hellacache_s2_xcpt_WIRE connect io.hellacache.replay_next, UInt<1>(0h0) invalidate io.hellacache.s2_gpa invalidate io.hellacache.s2_gpa_is_pte invalidate io.hellacache.ordered invalidate io.hellacache.perf.storeBufferEmptyAfterStore invalidate io.hellacache.perf.storeBufferEmptyAfterLoad invalidate io.hellacache.perf.canAcceptLoadThenLoad invalidate io.hellacache.perf.canAcceptStoreThenRMW invalidate io.hellacache.perf.canAcceptStoreThenLoad invalidate io.hellacache.perf.blocked invalidate io.hellacache.perf.tlbMiss invalidate io.hellacache.perf.grant invalidate io.hellacache.perf.release invalidate io.hellacache.perf.acquire connect io.hellacache.clock_enabled, UInt<1>(0h1) node _io_hellacache_store_pending_T = or(stq_valid[0], stq_valid[1]) node _io_hellacache_store_pending_T_1 = or(_io_hellacache_store_pending_T, stq_valid[2]) node _io_hellacache_store_pending_T_2 = or(_io_hellacache_store_pending_T_1, stq_valid[3]) node _io_hellacache_store_pending_T_3 = or(_io_hellacache_store_pending_T_2, stq_valid[4]) node _io_hellacache_store_pending_T_4 = or(_io_hellacache_store_pending_T_3, stq_valid[5]) node _io_hellacache_store_pending_T_5 = or(_io_hellacache_store_pending_T_4, stq_valid[6]) node _io_hellacache_store_pending_T_6 = or(_io_hellacache_store_pending_T_5, stq_valid[7]) node _io_hellacache_store_pending_T_7 = or(_io_hellacache_store_pending_T_6, stq_valid[8]) node _io_hellacache_store_pending_T_8 = or(_io_hellacache_store_pending_T_7, stq_valid[9]) node _io_hellacache_store_pending_T_9 = or(_io_hellacache_store_pending_T_8, stq_valid[10]) node _io_hellacache_store_pending_T_10 = or(_io_hellacache_store_pending_T_9, stq_valid[11]) node _io_hellacache_store_pending_T_11 = or(_io_hellacache_store_pending_T_10, stq_valid[12]) node _io_hellacache_store_pending_T_12 = or(_io_hellacache_store_pending_T_11, stq_valid[13]) node _io_hellacache_store_pending_T_13 = or(_io_hellacache_store_pending_T_12, stq_valid[14]) node _io_hellacache_store_pending_T_14 = or(_io_hellacache_store_pending_T_13, stq_valid[15]) node _io_hellacache_store_pending_T_15 = or(_io_hellacache_store_pending_T_14, stq_valid[16]) node _io_hellacache_store_pending_T_16 = or(_io_hellacache_store_pending_T_15, stq_valid[17]) node _io_hellacache_store_pending_T_17 = or(_io_hellacache_store_pending_T_16, stq_valid[18]) node _io_hellacache_store_pending_T_18 = or(_io_hellacache_store_pending_T_17, stq_valid[19]) node _io_hellacache_store_pending_T_19 = or(_io_hellacache_store_pending_T_18, stq_valid[20]) node _io_hellacache_store_pending_T_20 = or(_io_hellacache_store_pending_T_19, stq_valid[21]) node _io_hellacache_store_pending_T_21 = or(_io_hellacache_store_pending_T_20, stq_valid[22]) node _io_hellacache_store_pending_T_22 = or(_io_hellacache_store_pending_T_21, stq_valid[23]) connect io.hellacache.store_pending, _io_hellacache_store_pending_T_22 connect io.hellacache.resp.valid, UInt<1>(0h0) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.mask, hella_req.mask connect io.hellacache.resp.bits.replay, UInt<1>(0h0) connect io.hellacache.resp.bits.has_data, UInt<1>(0h1) connect io.hellacache.resp.bits.data_word_bypass, io.dmem.ll_resp.bits.data connect io.hellacache.resp.bits.data_raw, io.dmem.ll_resp.bits.data connect io.hellacache.resp.bits.store_data, hella_req.data connect io.hellacache.resp.bits.dprv, io.ptw.status.prv connect io.hellacache.resp.bits.dv, io.ptw.status.v connect io.hellacache.resp.bits.data, io.dmem.ll_resp.bits.data node _T_2119 = eq(hella_state, UInt<3>(0h0)) when _T_2119 : connect io.hellacache.req.ready, UInt<1>(0h1) node _T_2120 = and(io.hellacache.req.ready, io.hellacache.req.valid) when _T_2120 : connect hella_req, io.hellacache.req.bits connect hella_state, UInt<3>(0h1) else : node _T_2121 = eq(hella_state, UInt<3>(0h1)) when _T_2121 : connect can_fire_hella_incoming[0], UInt<1>(0h1) connect hella_data, io.hellacache.s1_data connect hella_xcpt.ae.st, dtlb.io.resp[0].ae.st connect hella_xcpt.ae.ld, dtlb.io.resp[0].ae.ld connect hella_xcpt.gf.st, dtlb.io.resp[0].gf.st connect hella_xcpt.gf.ld, dtlb.io.resp[0].gf.ld connect hella_xcpt.pf.st, dtlb.io.resp[0].pf.st connect hella_xcpt.pf.ld, dtlb.io.resp[0].pf.ld connect hella_xcpt.ma.st, dtlb.io.resp[0].ma.st connect hella_xcpt.ma.ld, dtlb.io.resp[0].ma.ld when io.hellacache.s1_kill : node _T_2122 = and(will_fire_hella_incoming[0], dmem_req_fire[0]) when _T_2122 : connect hella_state, UInt<3>(0h6) else : connect hella_state, UInt<3>(0h0) else : node _T_2123 = and(will_fire_hella_incoming[0], dmem_req_fire[0]) when _T_2123 : connect hella_state, UInt<3>(0h2) else : connect hella_state, UInt<3>(0h3) else : node _T_2124 = eq(hella_state, UInt<3>(0h3)) when _T_2124 : connect io.hellacache.s2_nack, UInt<1>(0h1) connect hella_state, UInt<3>(0h0) else : node _T_2125 = eq(hella_state, UInt<3>(0h2)) when _T_2125 : connect io.hellacache.s2_xcpt, hella_xcpt node _T_2126 = cat(hella_xcpt.ae.ld, hella_xcpt.ae.st) node _T_2127 = cat(hella_xcpt.gf.ld, hella_xcpt.gf.st) node _T_2128 = cat(hella_xcpt.pf.ld, hella_xcpt.pf.st) node _T_2129 = cat(hella_xcpt.ma.ld, hella_xcpt.ma.st) node lo = cat(_T_2127, _T_2126) node hi = cat(_T_2129, _T_2128) node _T_2130 = cat(hi, lo) node _T_2131 = neq(_T_2130, UInt<1>(0h0)) node _T_2132 = or(io.hellacache.s2_kill, _T_2131) when _T_2132 : connect hella_state, UInt<3>(0h6) else : connect hella_state, UInt<3>(0h4) else : node _T_2133 = eq(hella_state, UInt<3>(0h4)) when _T_2133 : node _T_2134 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_2135 = and(_T_2134, io.dmem.ll_resp.bits.is_hella) when _T_2135 : connect hella_state, UInt<3>(0h0) connect io.hellacache.resp.valid, UInt<1>(0h1) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.data, io.dmem.ll_resp.bits.data node _T_2136 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella) node _T_2137 = and(io.dmem.store_ack[0].valid, io.dmem.store_ack[0].bits.is_hella) node _T_2138 = or(_T_2136, _T_2137) when _T_2138 : connect hella_state, UInt<3>(0h0) connect io.hellacache.resp.valid, UInt<1>(0h1) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.data, io.dmem.resp[0].bits.data node _T_2139 = and(io.dmem.nack[0].valid, io.dmem.nack[0].bits.is_hella) when _T_2139 : connect hella_state, UInt<3>(0h5) else : node _T_2140 = eq(hella_state, UInt<3>(0h5)) when _T_2140 : connect can_fire_hella_wakeup[0], UInt<1>(0h1) node _T_2141 = and(will_fire_hella_wakeup[0], dmem_req_fire[0]) when _T_2141 : connect hella_state, UInt<3>(0h4) else : node _T_2142 = eq(hella_state, UInt<3>(0h6)) when _T_2142 : node _T_2143 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_2144 = and(_T_2143, io.dmem.ll_resp.bits.is_hella) when _T_2144 : connect hella_state, UInt<3>(0h0) node _T_2145 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella) when _T_2145 : connect hella_state, UInt<3>(0h0) node _T_2146 = asUInt(reset) node _T_2147 = or(_T_2146, io.core.exception) when _T_2147 : connect ldq_head, UInt<1>(0h0) connect ldq_tail, UInt<1>(0h0) node _T_2148 = asUInt(reset) when _T_2148 : connect stq_head, UInt<1>(0h0) connect stq_tail, UInt<1>(0h0) connect stq_commit_head, UInt<1>(0h0) connect stq_execute_head, UInt<1>(0h0) connect stq_valid[0], UInt<1>(0h0) connect stq_valid[1], UInt<1>(0h0) connect stq_valid[2], UInt<1>(0h0) connect stq_valid[3], UInt<1>(0h0) connect stq_valid[4], UInt<1>(0h0) connect stq_valid[5], UInt<1>(0h0) connect stq_valid[6], UInt<1>(0h0) connect stq_valid[7], UInt<1>(0h0) connect stq_valid[8], UInt<1>(0h0) connect stq_valid[9], UInt<1>(0h0) connect stq_valid[10], UInt<1>(0h0) connect stq_valid[11], UInt<1>(0h0) connect stq_valid[12], UInt<1>(0h0) connect stq_valid[13], UInt<1>(0h0) connect stq_valid[14], UInt<1>(0h0) connect stq_valid[15], UInt<1>(0h0) connect stq_valid[16], UInt<1>(0h0) connect stq_valid[17], UInt<1>(0h0) connect stq_valid[18], UInt<1>(0h0) connect stq_valid[19], UInt<1>(0h0) connect stq_valid[20], UInt<1>(0h0) connect stq_valid[21], UInt<1>(0h0) connect stq_valid[22], UInt<1>(0h0) connect stq_valid[23], UInt<1>(0h0) else : connect stq_tail, stq_commit_head node _T_2149 = eq(stq_committed[0], UInt<1>(0h0)) node _T_2150 = eq(stq_succeeded[0], UInt<1>(0h0)) node _T_2151 = and(_T_2149, _T_2150) when _T_2151 : connect stq_valid[0], UInt<1>(0h0) node _T_2152 = eq(stq_committed[1], UInt<1>(0h0)) node _T_2153 = eq(stq_succeeded[1], UInt<1>(0h0)) node _T_2154 = and(_T_2152, _T_2153) when _T_2154 : connect stq_valid[1], UInt<1>(0h0) node _T_2155 = eq(stq_committed[2], UInt<1>(0h0)) node _T_2156 = eq(stq_succeeded[2], UInt<1>(0h0)) node _T_2157 = and(_T_2155, _T_2156) when _T_2157 : connect stq_valid[2], UInt<1>(0h0) node _T_2158 = eq(stq_committed[3], UInt<1>(0h0)) node _T_2159 = eq(stq_succeeded[3], UInt<1>(0h0)) node _T_2160 = and(_T_2158, _T_2159) when _T_2160 : connect stq_valid[3], UInt<1>(0h0) node _T_2161 = eq(stq_committed[4], UInt<1>(0h0)) node _T_2162 = eq(stq_succeeded[4], UInt<1>(0h0)) node _T_2163 = and(_T_2161, _T_2162) when _T_2163 : connect stq_valid[4], UInt<1>(0h0) node _T_2164 = eq(stq_committed[5], UInt<1>(0h0)) node _T_2165 = eq(stq_succeeded[5], UInt<1>(0h0)) node _T_2166 = and(_T_2164, _T_2165) when _T_2166 : connect stq_valid[5], UInt<1>(0h0) node _T_2167 = eq(stq_committed[6], UInt<1>(0h0)) node _T_2168 = eq(stq_succeeded[6], UInt<1>(0h0)) node _T_2169 = and(_T_2167, _T_2168) when _T_2169 : connect stq_valid[6], UInt<1>(0h0) node _T_2170 = eq(stq_committed[7], UInt<1>(0h0)) node _T_2171 = eq(stq_succeeded[7], UInt<1>(0h0)) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : connect stq_valid[7], UInt<1>(0h0) node _T_2173 = eq(stq_committed[8], UInt<1>(0h0)) node _T_2174 = eq(stq_succeeded[8], UInt<1>(0h0)) node _T_2175 = and(_T_2173, _T_2174) when _T_2175 : connect stq_valid[8], UInt<1>(0h0) node _T_2176 = eq(stq_committed[9], UInt<1>(0h0)) node _T_2177 = eq(stq_succeeded[9], UInt<1>(0h0)) node _T_2178 = and(_T_2176, _T_2177) when _T_2178 : connect stq_valid[9], UInt<1>(0h0) node _T_2179 = eq(stq_committed[10], UInt<1>(0h0)) node _T_2180 = eq(stq_succeeded[10], UInt<1>(0h0)) node _T_2181 = and(_T_2179, _T_2180) when _T_2181 : connect stq_valid[10], UInt<1>(0h0) node _T_2182 = eq(stq_committed[11], UInt<1>(0h0)) node _T_2183 = eq(stq_succeeded[11], UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : connect stq_valid[11], UInt<1>(0h0) node _T_2185 = eq(stq_committed[12], UInt<1>(0h0)) node _T_2186 = eq(stq_succeeded[12], UInt<1>(0h0)) node _T_2187 = and(_T_2185, _T_2186) when _T_2187 : connect stq_valid[12], UInt<1>(0h0) node _T_2188 = eq(stq_committed[13], UInt<1>(0h0)) node _T_2189 = eq(stq_succeeded[13], UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : connect stq_valid[13], UInt<1>(0h0) node _T_2191 = eq(stq_committed[14], UInt<1>(0h0)) node _T_2192 = eq(stq_succeeded[14], UInt<1>(0h0)) node _T_2193 = and(_T_2191, _T_2192) when _T_2193 : connect stq_valid[14], UInt<1>(0h0) node _T_2194 = eq(stq_committed[15], UInt<1>(0h0)) node _T_2195 = eq(stq_succeeded[15], UInt<1>(0h0)) node _T_2196 = and(_T_2194, _T_2195) when _T_2196 : connect stq_valid[15], UInt<1>(0h0) node _T_2197 = eq(stq_committed[16], UInt<1>(0h0)) node _T_2198 = eq(stq_succeeded[16], UInt<1>(0h0)) node _T_2199 = and(_T_2197, _T_2198) when _T_2199 : connect stq_valid[16], UInt<1>(0h0) node _T_2200 = eq(stq_committed[17], UInt<1>(0h0)) node _T_2201 = eq(stq_succeeded[17], UInt<1>(0h0)) node _T_2202 = and(_T_2200, _T_2201) when _T_2202 : connect stq_valid[17], UInt<1>(0h0) node _T_2203 = eq(stq_committed[18], UInt<1>(0h0)) node _T_2204 = eq(stq_succeeded[18], UInt<1>(0h0)) node _T_2205 = and(_T_2203, _T_2204) when _T_2205 : connect stq_valid[18], UInt<1>(0h0) node _T_2206 = eq(stq_committed[19], UInt<1>(0h0)) node _T_2207 = eq(stq_succeeded[19], UInt<1>(0h0)) node _T_2208 = and(_T_2206, _T_2207) when _T_2208 : connect stq_valid[19], UInt<1>(0h0) node _T_2209 = eq(stq_committed[20], UInt<1>(0h0)) node _T_2210 = eq(stq_succeeded[20], UInt<1>(0h0)) node _T_2211 = and(_T_2209, _T_2210) when _T_2211 : connect stq_valid[20], UInt<1>(0h0) node _T_2212 = eq(stq_committed[21], UInt<1>(0h0)) node _T_2213 = eq(stq_succeeded[21], UInt<1>(0h0)) node _T_2214 = and(_T_2212, _T_2213) when _T_2214 : connect stq_valid[21], UInt<1>(0h0) node _T_2215 = eq(stq_committed[22], UInt<1>(0h0)) node _T_2216 = eq(stq_succeeded[22], UInt<1>(0h0)) node _T_2217 = and(_T_2215, _T_2216) when _T_2217 : connect stq_valid[22], UInt<1>(0h0) node _T_2218 = eq(stq_committed[23], UInt<1>(0h0)) node _T_2219 = eq(stq_succeeded[23], UInt<1>(0h0)) node _T_2220 = and(_T_2218, _T_2219) when _T_2220 : connect stq_valid[23], UInt<1>(0h0) connect ldq_valid[0], UInt<1>(0h0) connect ldq_valid[1], UInt<1>(0h0) connect ldq_valid[2], UInt<1>(0h0) connect ldq_valid[3], UInt<1>(0h0) connect ldq_valid[4], UInt<1>(0h0) connect ldq_valid[5], UInt<1>(0h0) connect ldq_valid[6], UInt<1>(0h0) connect ldq_valid[7], UInt<1>(0h0) connect ldq_valid[8], UInt<1>(0h0) connect ldq_valid[9], UInt<1>(0h0) connect ldq_valid[10], UInt<1>(0h0) connect ldq_valid[11], UInt<1>(0h0) connect ldq_valid[12], UInt<1>(0h0) connect ldq_valid[13], UInt<1>(0h0) connect ldq_valid[14], UInt<1>(0h0) connect ldq_valid[15], UInt<1>(0h0) connect ldq_valid[16], UInt<1>(0h0) connect ldq_valid[17], UInt<1>(0h0) connect ldq_valid[18], UInt<1>(0h0) connect ldq_valid[19], UInt<1>(0h0) connect ldq_valid[20], UInt<1>(0h0) connect ldq_valid[21], UInt<1>(0h0) connect ldq_valid[22], UInt<1>(0h0) connect ldq_valid[23], UInt<1>(0h0)	module LSU( // @[lsu.scala:211:7] input clock, // @[lsu.scala:211:7] input reset, // @[lsu.scala:211:7] input io_ptw_req_ready, // @[lsu.scala:214:14] output io_ptw_req_valid, // @[lsu.scala:214:14] output io_ptw_req_bits_valid, // @[lsu.scala:214:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:214:14] input io_ptw_resp_valid, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:214:14] input io_ptw_resp_bits_pf, // @[lsu.scala:214:14] input io_ptw_resp_bits_gf, // @[lsu.scala:214:14] input io_ptw_resp_bits_hr, // @[lsu.scala:214:14] input io_ptw_resp_bits_hw, // @[lsu.scala:214:14] input io_ptw_resp_bits_hx, // @[lsu.scala:214:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:214:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:214:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:214:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:214:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:214:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:214:14] input io_ptw_status_debug, // @[lsu.scala:214:14] input io_ptw_status_cease, // @[lsu.scala:214:14] input io_ptw_status_wfi, // @[lsu.scala:214:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:214:14] input io_ptw_status_dv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:214:14] input io_ptw_status_v, // @[lsu.scala:214:14] input io_ptw_status_sd, // @[lsu.scala:214:14] input io_ptw_status_mpv, // @[lsu.scala:214:14] input io_ptw_status_gva, // @[lsu.scala:214:14] input io_ptw_status_tsr, // @[lsu.scala:214:14] input io_ptw_status_tw, // @[lsu.scala:214:14] input io_ptw_status_tvm, // @[lsu.scala:214:14] input io_ptw_status_mxr, // @[lsu.scala:214:14] input io_ptw_status_sum, // @[lsu.scala:214:14] input io_ptw_status_mprv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:214:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:214:14] input io_ptw_status_spp, // @[lsu.scala:214:14] input io_ptw_status_mpie, // @[lsu.scala:214:14] input io_ptw_status_spie, // @[lsu.scala:214:14] input io_ptw_status_mie, // @[lsu.scala:214:14] input io_ptw_status_sie, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:214:14] input io_core_agen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_agen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_agen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_agen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_1_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_1_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_1_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_data, // @[lsu.scala:214:14] input io_core_dgen_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_2_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_2_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_2_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_data, // @[lsu.scala:214:14] output io_core_iwakeups_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iwakeups_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_iwakeups_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iwakeups_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iwakeups_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_bypassable, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_speculative_mask, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_rebusy, // @[lsu.scala:214:14] output io_core_iresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_iresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_data, // @[lsu.scala:214:14] output io_core_fresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_fresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_fresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_fresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_data, // @[lsu.scala:214:14] input io_core_sfence_valid, // @[lsu.scala:214:14] input io_core_sfence_bits_rs1, // @[lsu.scala:214:14] input io_core_sfence_bits_rs2, // @[lsu.scala:214:14] input [38:0] io_core_sfence_bits_addr, // @[lsu.scala:214:14] input io_core_sfence_bits_asid, // @[lsu.scala:214:14] input io_core_sfence_bits_hv, // @[lsu.scala:214:14] input io_core_sfence_bits_hg, // @[lsu.scala:214:14] input io_core_dis_uops_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_2_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_2_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_2_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_2_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_2_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_2_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_2_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_2_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_0, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_1, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_2, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_0, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_1, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_2, // @[lsu.scala:214:14] output io_core_ldq_full_0, // @[lsu.scala:214:14] output io_core_ldq_full_1, // @[lsu.scala:214:14] output io_core_ldq_full_2, // @[lsu.scala:214:14] output io_core_stq_full_0, // @[lsu.scala:214:14] output io_core_stq_full_1, // @[lsu.scala:214:14] output io_core_stq_full_2, // @[lsu.scala:214:14] input io_core_commit_valids_0, // @[lsu.scala:214:14] input io_core_commit_valids_1, // @[lsu.scala:214:14] input io_core_commit_valids_2, // @[lsu.scala:214:14] input io_core_commit_arch_valids_0, // @[lsu.scala:214:14] input io_core_commit_arch_valids_1, // @[lsu.scala:214:14] input io_core_commit_arch_valids_2, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_0_taken, // @[lsu.scala:214:14] input io_core_commit_uops_0_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_0_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_0_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_1_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_1_taken, // @[lsu.scala:214:14] input io_core_commit_uops_1_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_1_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_1_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_1_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_1_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_2_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_2_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_2_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_2_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_2_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_2_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_2_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_2_taken, // @[lsu.scala:214:14] input io_core_commit_uops_2_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_2_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_2_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_2_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_2_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_2_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_2_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_2_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_2_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_2_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_2_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_debug_tsrc, // @[lsu.scala:214:14] input io_core_commit_fflags_valid, // @[lsu.scala:214:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_2, // @[lsu.scala:214:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:214:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_0_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_1_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_2_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_2_bits, // @[lsu.scala:214:14] output io_core_clr_unsafe_0_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:214:14] input io_core_fence_dmem, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:214:14] input io_core_brupdate_b2_taken, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:214:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:214:14] input [6:0] io_core_rob_pnr_idx, // @[lsu.scala:214:14] input [6:0] io_core_rob_head_idx, // @[lsu.scala:214:14] input io_core_exception, // @[lsu.scala:214:14] output io_core_fencei_rdy, // @[lsu.scala:214:14] output io_core_lxcpt_valid, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:214:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:214:14] input io_core_status_debug, // @[lsu.scala:214:14] input io_core_status_cease, // @[lsu.scala:214:14] input io_core_status_wfi, // @[lsu.scala:214:14] input [1:0] io_core_status_dprv, // @[lsu.scala:214:14] input io_core_status_dv, // @[lsu.scala:214:14] input [1:0] io_core_status_prv, // @[lsu.scala:214:14] input io_core_status_v, // @[lsu.scala:214:14] input io_core_status_sd, // @[lsu.scala:214:14] input io_core_status_mpv, // @[lsu.scala:214:14] input io_core_status_gva, // @[lsu.scala:214:14] input io_core_status_tsr, // @[lsu.scala:214:14] input io_core_status_tw, // @[lsu.scala:214:14] input io_core_status_tvm, // @[lsu.scala:214:14] input io_core_status_mxr, // @[lsu.scala:214:14] input io_core_status_sum, // @[lsu.scala:214:14] input io_core_status_mprv, // @[lsu.scala:214:14] input [1:0] io_core_status_fs, // @[lsu.scala:214:14] input [1:0] io_core_status_mpp, // @[lsu.scala:214:14] input io_core_status_spp, // @[lsu.scala:214:14] input io_core_status_mpie, // @[lsu.scala:214:14] input io_core_status_spie, // @[lsu.scala:214:14] input io_core_status_mie, // @[lsu.scala:214:14] input io_core_status_sie, // @[lsu.scala:214:14] output io_core_perf_acquire, // @[lsu.scala:214:14] output io_core_perf_release, // @[lsu.scala:214:14] output io_core_perf_tlbMiss, // @[lsu.scala:214:14] input io_dmem_req_ready, // @[lsu.scala:214:14] output io_dmem_req_valid, // @[lsu.scala:214:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_s1_kill_0, // @[lsu.scala:214:14] input io_dmem_resp_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_store_ack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_store_ack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_store_ack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_nack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_ll_resp_ready, // @[lsu.scala:214:14] input io_dmem_ll_resp_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_ll_resp_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_ll_resp_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_ll_resp_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_data, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_is_hella, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:214:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:214:14] output io_dmem_exception, // @[lsu.scala:214:14] output [6:0] io_dmem_rob_pnr_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_rob_head_idx, // @[lsu.scala:214:14] output io_dmem_release_ready, // @[lsu.scala:214:14] input io_dmem_release_valid, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:214:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_source, // @[lsu.scala:214:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:214:14] input [127:0] io_dmem_release_bits_data, // @[lsu.scala:214:14] output io_dmem_force_order, // @[lsu.scala:214:14] input io_dmem_ordered, // @[lsu.scala:214:14] input io_dmem_perf_acquire, // @[lsu.scala:214:14] input io_dmem_perf_release, // @[lsu.scala:214:14] output io_hellacache_req_ready, // @[lsu.scala:214:14] input io_hellacache_req_valid, // @[lsu.scala:214:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:214:14] input io_hellacache_req_bits_dv, // @[lsu.scala:214:14] input io_hellacache_s1_kill, // @[lsu.scala:214:14] output io_hellacache_s2_nack, // @[lsu.scala:214:14] output io_hellacache_resp_valid, // @[lsu.scala:214:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:214:14] output [1:0] io_hellacache_resp_bits_dprv, // @[lsu.scala:214:14] output io_hellacache_resp_bits_dv, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_word_bypass, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_raw, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:214:14] output io_hellacache_store_pending // @[lsu.scala:214:14] ); wire [2:0] wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1494:29] wire [63:0] wb_slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1494:29] wire [19:0] wb_slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1494:29] wire [39:0] wb_slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1494:29] wire [63:0] iresp_0_bits_data; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_typ; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_fp_rm; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_val; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_fcn_op; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fcn_dw; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_frs3_en; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dst_rtype; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs3; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs2; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs1; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_csr_cmd; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_unique; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_stq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_ldq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_mem_signed; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_mem_size; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_mem_cmd; // @[lsu.scala:1477:19] wire [63:0] iresp_0_bits_uop_exc_cause; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_exception; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_stale_pdst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ppred_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs3_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs2_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs1_busy; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ppred; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs3; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs2; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs1; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_pdst; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_rxq_idx; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_stq_idx; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ldq_idx; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_rob_idx; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_op2_sel; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_op1_sel; // @[lsu.scala:1477:19] wire [19:0] iresp_0_bits_uop_imm_packed; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_pimm; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_imm_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_imm_rename; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_taken; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_pc_lob; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_edge_inst; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ftq_idx; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_mov; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rocc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_eret; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_amo; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fencei; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfb; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_type; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_tag; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued; // @[lsu.scala:1477:19] wire [39:0] iresp_0_bits_uop_debug_pc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rvc; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_debug_inst; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_inst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_9; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_8; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_7; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_6; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_5; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_4; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_0; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_0; // @[lsu.scala:1477:19] wire [63:0] wb_ldst_forward_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] wb_ldst_forward_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] wb_ldst_forward_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_observed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_order_fail; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_succeeded; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_executed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] wb_ldst_forward_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] wb_ldst_forward_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire [2:0] s_uop_2_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_2_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_2_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_fp_rm; // @[lsu.scala:1093:25] wire s_uop_2_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_fcn_op; // @[lsu.scala:1093:25] wire s_uop_2_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_2_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_ldst; // @[lsu.scala:1093:25] wire s_uop_2_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_2_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_2_is_unique; // @[lsu.scala:1093:25] wire s_uop_2_uses_stq; // @[lsu.scala:1093:25] wire s_uop_2_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_2_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_2_exc_cause; // @[lsu.scala:1093:25] wire s_uop_2_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_2_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_2_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_imm_sel; // @[lsu.scala:1093:25] wire s_uop_2_imm_rename; // @[lsu.scala:1093:25] wire s_uop_2_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_pc_lob; // @[lsu.scala:1093:25] wire s_uop_2_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_2_is_mov; // @[lsu.scala:1093:25] wire s_uop_2_is_rocc; // @[lsu.scala:1093:25] wire s_uop_2_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_2_is_eret; // @[lsu.scala:1093:25] wire s_uop_2_is_amo; // @[lsu.scala:1093:25] wire s_uop_2_is_sfence; // @[lsu.scala:1093:25] wire s_uop_2_is_fencei; // @[lsu.scala:1093:25] wire s_uop_2_is_fence; // @[lsu.scala:1093:25] wire s_uop_2_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_2_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_2_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_2_debug_pc; // @[lsu.scala:1093:25] wire s_uop_2_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_2_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_2_inst; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_1_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_1_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_fp_rm; // @[lsu.scala:1093:25] wire s_uop_1_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_fcn_op; // @[lsu.scala:1093:25] wire s_uop_1_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_1_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_ldst; // @[lsu.scala:1093:25] wire s_uop_1_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_1_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_1_is_unique; // @[lsu.scala:1093:25] wire s_uop_1_uses_stq; // @[lsu.scala:1093:25] wire s_uop_1_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_1_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_1_exc_cause; // @[lsu.scala:1093:25] wire s_uop_1_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_1_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_1_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_imm_sel; // @[lsu.scala:1093:25] wire s_uop_1_imm_rename; // @[lsu.scala:1093:25] wire s_uop_1_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_pc_lob; // @[lsu.scala:1093:25] wire s_uop_1_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_1_is_mov; // @[lsu.scala:1093:25] wire s_uop_1_is_rocc; // @[lsu.scala:1093:25] wire s_uop_1_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_1_is_eret; // @[lsu.scala:1093:25] wire s_uop_1_is_amo; // @[lsu.scala:1093:25] wire s_uop_1_is_sfence; // @[lsu.scala:1093:25] wire s_uop_1_is_fencei; // @[lsu.scala:1093:25] wire s_uop_1_is_fence; // @[lsu.scala:1093:25] wire s_uop_1_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_1_debug_pc; // @[lsu.scala:1093:25] wire s_uop_1_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_inst; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_fp_rm; // @[lsu.scala:1093:25] wire s_uop_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_fcn_op; // @[lsu.scala:1093:25] wire s_uop_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_ldst; // @[lsu.scala:1093:25] wire s_uop_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_is_unique; // @[lsu.scala:1093:25] wire s_uop_uses_stq; // @[lsu.scala:1093:25] wire s_uop_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_exc_cause; // @[lsu.scala:1093:25] wire s_uop_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_imm_sel; // @[lsu.scala:1093:25] wire s_uop_imm_rename; // @[lsu.scala:1093:25] wire s_uop_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_pc_lob; // @[lsu.scala:1093:25] wire s_uop_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_is_mov; // @[lsu.scala:1093:25] wire s_uop_is_rocc; // @[lsu.scala:1093:25] wire s_uop_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_is_eret; // @[lsu.scala:1093:25] wire s_uop_is_amo; // @[lsu.scala:1093:25] wire s_uop_is_sfence; // @[lsu.scala:1093:25] wire s_uop_is_fencei; // @[lsu.scala:1093:25] wire s_uop_is_fence; // @[lsu.scala:1093:25] wire s_uop_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_debug_pc; // @[lsu.scala:1093:25] wire s_uop_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_inst; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_iq_type_0; // @[lsu.scala:1093:25] wire [63:0] mem_stq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] mem_stq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire [63:0] mem_ldq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] mem_ldq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] mem_ldq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] mem_ldq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] mem_ldq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [15:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [15:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [15:0] mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [63:0] stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire stq_incoming_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_incoming_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire _logic_1_io_found; // @[lsu.scala:1965:23] wire [4:0] _logic_1_io_found_idx; // @[lsu.scala:1965:23] wire _logic_io_found; // @[lsu.scala:1965:23] wire [4:0] _logic_io_found_idx; // @[lsu.scala:1965:23] wire _wakeupArbs_0_io_in_1_ready; // @[lsu.scala:1016:47] wire _stq_execute_queue_io_enq_ready; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_valid; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_inst; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:558:11] wire [15:0] _stq_execute_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_type; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_taken; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_pimm; // @[lsu.scala:558:11] wire [19:0] _stq_execute_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_pdst; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs1; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs2; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs3; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ppred; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_exception; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_ldst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_addr_bits; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_data_bits; // @[lsu.scala:558:11] wire _retry_queue_io_enq_ready; // @[lsu.scala:533:27] wire _retry_queue_io_deq_valid; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_inst; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27] wire [39:0] _retry_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:533:27] wire [15:0] _retry_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_type; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_pimm; // @[lsu.scala:533:27] wire [19:0] _retry_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_pdst; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs1; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs2; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs3; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ppred; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_ldst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_data; // @[lsu.scala:533:27] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:211:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:211:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:211:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:211:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:211:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:211:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:211:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:211:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:211:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:211:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:211:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:211:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:211:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:211:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:211:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:211:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:211:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:211:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:211:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:211:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:211:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:211:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:211:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:211:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:211:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:211:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:211:7] wire io_core_agen_0_valid_0 = io_core_agen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_inst_0 = io_core_agen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_debug_inst_0 = io_core_agen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rvc_0 = io_core_agen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_agen_0_bits_uop_debug_pc_0 = io_core_agen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_0_0 = io_core_agen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_1_0 = io_core_agen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_2_0 = io_core_agen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_3_0 = io_core_agen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_0_0 = io_core_agen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_1_0 = io_core_agen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_2_0 = io_core_agen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_3_0 = io_core_agen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_4_0 = io_core_agen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_5_0 = io_core_agen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_6_0 = io_core_agen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_7_0 = io_core_agen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_8_0 = io_core_agen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_9_0 = io_core_agen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_0 = io_core_agen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_agen_0 = io_core_agen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_agen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_iw_p1_speculative_child_0 = io_core_agen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_iw_p2_speculative_child_0 = io_core_agen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_dis_col_sel_0 = io_core_agen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_agen_0_bits_uop_br_mask_0 = io_core_agen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_tag_0 = io_core_agen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_type_0 = io_core_agen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfb_0 = io_core_agen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fence_0 = io_core_agen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fencei_0 = io_core_agen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfence_0 = io_core_agen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_amo_0 = io_core_agen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_eret_0 = io_core_agen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sys_pc2epc_0 = io_core_agen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rocc_0 = io_core_agen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_mov_0 = io_core_agen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ftq_idx_0 = io_core_agen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_edge_inst_0 = io_core_agen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_pc_lob_0 = io_core_agen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_taken_0 = io_core_agen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_imm_rename_0 = io_core_agen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_imm_sel_0 = io_core_agen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_pimm_0 = io_core_agen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_agen_0_bits_uop_imm_packed_0 = io_core_agen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_op1_sel_0 = io_core_agen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_op2_sel_0 = io_core_agen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ldst_0 = io_core_agen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wen_0 = io_core_agen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren1_0 = io_core_agen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren2_0 = io_core_agen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren3_0 = io_core_agen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap12_0 = io_core_agen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap23_0 = io_core_agen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fromint_0 = io_core_agen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_toint_0 = io_core_agen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_agen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fma_0 = io_core_agen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_div_0 = io_core_agen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_agen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wflags_0 = io_core_agen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_vec_0 = io_core_agen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_rob_idx_0 = io_core_agen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ldq_idx_0 = io_core_agen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_stq_idx_0 = io_core_agen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_rxq_idx_0 = io_core_agen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_pdst_0 = io_core_agen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs1_0 = io_core_agen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs2_0 = io_core_agen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs3_0 = io_core_agen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ppred_0 = io_core_agen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs1_busy_0 = io_core_agen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs2_busy_0 = io_core_agen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs3_busy_0 = io_core_agen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ppred_busy_0 = io_core_agen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_stale_pdst_0 = io_core_agen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_exception_0 = io_core_agen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_uop_exc_cause_0 = io_core_agen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_mem_cmd_0 = io_core_agen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_mem_size_0 = io_core_agen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_mem_signed_0 = io_core_agen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_ldq_0 = io_core_agen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_stq_0 = io_core_agen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_unique_0 = io_core_agen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_flush_on_commit_0 = io_core_agen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_csr_cmd_0 = io_core_agen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ldst_is_rs1_0 = io_core_agen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_ldst_0 = io_core_agen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs1_0 = io_core_agen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs2_0 = io_core_agen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs3_0 = io_core_agen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dst_rtype_0 = io_core_agen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs1_rtype_0 = io_core_agen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs2_rtype_0 = io_core_agen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_frs3_en_0 = io_core_agen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fcn_dw_0 = io_core_agen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_fcn_op_0 = io_core_agen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_val_0 = io_core_agen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_fp_rm_0 = io_core_agen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_typ_0 = io_core_agen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_pf_if_0 = io_core_agen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ae_if_0 = io_core_agen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ma_if_0 = io_core_agen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_debug_if_0 = io_core_agen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_xcpt_if_0 = io_core_agen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_fsrc_0 = io_core_agen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_tsrc_0 = io_core_agen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_data_0 = io_core_agen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_0_valid_0 = io_core_dgen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_inst_0 = io_core_dgen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_debug_inst_0 = io_core_dgen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rvc_0 = io_core_dgen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_0_bits_uop_debug_pc_0 = io_core_dgen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_0_0 = io_core_dgen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_1_0 = io_core_dgen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_2_0 = io_core_dgen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_3_0 = io_core_dgen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_0_0 = io_core_dgen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_1_0 = io_core_dgen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_2_0 = io_core_dgen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_3_0 = io_core_dgen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_4_0 = io_core_dgen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_5_0 = io_core_dgen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_6_0 = io_core_dgen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_7_0 = io_core_dgen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_8_0 = io_core_dgen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_9_0 = io_core_dgen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_0 = io_core_dgen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_dis_col_sel_0 = io_core_dgen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_0_bits_uop_br_mask_0 = io_core_dgen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_tag_0 = io_core_dgen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_type_0 = io_core_dgen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfb_0 = io_core_dgen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fence_0 = io_core_dgen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fencei_0 = io_core_dgen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfence_0 = io_core_dgen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_amo_0 = io_core_dgen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_eret_0 = io_core_dgen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sys_pc2epc_0 = io_core_dgen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rocc_0 = io_core_dgen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_mov_0 = io_core_dgen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ftq_idx_0 = io_core_dgen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_edge_inst_0 = io_core_dgen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_pc_lob_0 = io_core_dgen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_taken_0 = io_core_dgen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_imm_rename_0 = io_core_dgen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_imm_sel_0 = io_core_dgen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_pimm_0 = io_core_dgen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_0_bits_uop_imm_packed_0 = io_core_dgen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_op1_sel_0 = io_core_dgen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_op2_sel_0 = io_core_dgen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wen_0 = io_core_dgen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_toint_0 = io_core_dgen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fma_0 = io_core_dgen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_div_0 = io_core_dgen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_vec_0 = io_core_dgen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_rob_idx_0 = io_core_dgen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ldq_idx_0 = io_core_dgen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_stq_idx_0 = io_core_dgen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_rxq_idx_0 = io_core_dgen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_pdst_0 = io_core_dgen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs1_0 = io_core_dgen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs2_0 = io_core_dgen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs3_0 = io_core_dgen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ppred_0 = io_core_dgen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs1_busy_0 = io_core_dgen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs2_busy_0 = io_core_dgen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs3_busy_0 = io_core_dgen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ppred_busy_0 = io_core_dgen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_stale_pdst_0 = io_core_dgen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_exception_0 = io_core_dgen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_uop_exc_cause_0 = io_core_dgen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_mem_cmd_0 = io_core_dgen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_mem_size_0 = io_core_dgen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_mem_signed_0 = io_core_dgen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_ldq_0 = io_core_dgen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_stq_0 = io_core_dgen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_unique_0 = io_core_dgen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_flush_on_commit_0 = io_core_dgen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_csr_cmd_0 = io_core_dgen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ldst_is_rs1_0 = io_core_dgen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_ldst_0 = io_core_dgen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs1_0 = io_core_dgen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs2_0 = io_core_dgen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs3_0 = io_core_dgen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dst_rtype_0 = io_core_dgen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs1_rtype_0 = io_core_dgen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs2_rtype_0 = io_core_dgen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_frs3_en_0 = io_core_dgen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fcn_dw_0 = io_core_dgen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_fcn_op_0 = io_core_dgen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_val_0 = io_core_dgen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_fp_rm_0 = io_core_dgen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_typ_0 = io_core_dgen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_pf_if_0 = io_core_dgen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ae_if_0 = io_core_dgen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ma_if_0 = io_core_dgen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_debug_if_0 = io_core_dgen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_xcpt_if_0 = io_core_dgen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_fsrc_0 = io_core_dgen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_tsrc_0 = io_core_dgen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_data_0 = io_core_dgen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_1_valid_0 = io_core_dgen_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_inst_0 = io_core_dgen_1_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_debug_inst_0 = io_core_dgen_1_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rvc_0 = io_core_dgen_1_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_1_bits_uop_debug_pc_0 = io_core_dgen_1_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_0_0 = io_core_dgen_1_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_1_0 = io_core_dgen_1_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_2_0 = io_core_dgen_1_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_3_0 = io_core_dgen_1_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_0_0 = io_core_dgen_1_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_1_0 = io_core_dgen_1_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_2_0 = io_core_dgen_1_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_3_0 = io_core_dgen_1_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_4_0 = io_core_dgen_1_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_5_0 = io_core_dgen_1_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_6_0 = io_core_dgen_1_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_7_0 = io_core_dgen_1_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_8_0 = io_core_dgen_1_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_9_0 = io_core_dgen_1_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_0 = io_core_dgen_1_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_dis_col_sel_0 = io_core_dgen_1_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_1_bits_uop_br_mask_0 = io_core_dgen_1_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_tag_0 = io_core_dgen_1_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_type_0 = io_core_dgen_1_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfb_0 = io_core_dgen_1_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fence_0 = io_core_dgen_1_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fencei_0 = io_core_dgen_1_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfence_0 = io_core_dgen_1_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_amo_0 = io_core_dgen_1_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_eret_0 = io_core_dgen_1_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sys_pc2epc_0 = io_core_dgen_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rocc_0 = io_core_dgen_1_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_mov_0 = io_core_dgen_1_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ftq_idx_0 = io_core_dgen_1_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_edge_inst_0 = io_core_dgen_1_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_pc_lob_0 = io_core_dgen_1_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_taken_0 = io_core_dgen_1_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_imm_rename_0 = io_core_dgen_1_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_imm_sel_0 = io_core_dgen_1_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_pimm_0 = io_core_dgen_1_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_1_bits_uop_imm_packed_0 = io_core_dgen_1_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_op1_sel_0 = io_core_dgen_1_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_op2_sel_0 = io_core_dgen_1_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wen_0 = io_core_dgen_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_toint_0 = io_core_dgen_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fma_0 = io_core_dgen_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_div_0 = io_core_dgen_1_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_vec_0 = io_core_dgen_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_rob_idx_0 = io_core_dgen_1_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ldq_idx_0 = io_core_dgen_1_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_stq_idx_0 = io_core_dgen_1_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_rxq_idx_0 = io_core_dgen_1_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_pdst_0 = io_core_dgen_1_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs1_0 = io_core_dgen_1_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs2_0 = io_core_dgen_1_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs3_0 = io_core_dgen_1_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ppred_0 = io_core_dgen_1_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs1_busy_0 = io_core_dgen_1_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs2_busy_0 = io_core_dgen_1_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs3_busy_0 = io_core_dgen_1_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ppred_busy_0 = io_core_dgen_1_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_stale_pdst_0 = io_core_dgen_1_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_exception_0 = io_core_dgen_1_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_uop_exc_cause_0 = io_core_dgen_1_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_mem_cmd_0 = io_core_dgen_1_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_mem_size_0 = io_core_dgen_1_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_mem_signed_0 = io_core_dgen_1_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_ldq_0 = io_core_dgen_1_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_stq_0 = io_core_dgen_1_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_unique_0 = io_core_dgen_1_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_flush_on_commit_0 = io_core_dgen_1_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_csr_cmd_0 = io_core_dgen_1_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ldst_is_rs1_0 = io_core_dgen_1_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_ldst_0 = io_core_dgen_1_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs1_0 = io_core_dgen_1_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs2_0 = io_core_dgen_1_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs3_0 = io_core_dgen_1_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dst_rtype_0 = io_core_dgen_1_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs1_rtype_0 = io_core_dgen_1_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs2_rtype_0 = io_core_dgen_1_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_frs3_en_0 = io_core_dgen_1_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fcn_dw_0 = io_core_dgen_1_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_fcn_op_0 = io_core_dgen_1_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_val_0 = io_core_dgen_1_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_fp_rm_0 = io_core_dgen_1_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_typ_0 = io_core_dgen_1_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_pf_if_0 = io_core_dgen_1_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ae_if_0 = io_core_dgen_1_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ma_if_0 = io_core_dgen_1_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_debug_if_0 = io_core_dgen_1_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_xcpt_if_0 = io_core_dgen_1_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_fsrc_0 = io_core_dgen_1_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_tsrc_0 = io_core_dgen_1_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_data_0 = io_core_dgen_1_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_2_valid_0 = io_core_dgen_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_inst_0 = io_core_dgen_2_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_debug_inst_0 = io_core_dgen_2_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rvc_0 = io_core_dgen_2_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_2_bits_uop_debug_pc_0 = io_core_dgen_2_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_0_0 = io_core_dgen_2_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_1_0 = io_core_dgen_2_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_2_0 = io_core_dgen_2_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_3_0 = io_core_dgen_2_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_0_0 = io_core_dgen_2_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_1_0 = io_core_dgen_2_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_2_0 = io_core_dgen_2_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_3_0 = io_core_dgen_2_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_4_0 = io_core_dgen_2_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_5_0 = io_core_dgen_2_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_6_0 = io_core_dgen_2_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_7_0 = io_core_dgen_2_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_8_0 = io_core_dgen_2_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_9_0 = io_core_dgen_2_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_0 = io_core_dgen_2_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_dis_col_sel_0 = io_core_dgen_2_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_2_bits_uop_br_mask_0 = io_core_dgen_2_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_tag_0 = io_core_dgen_2_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_type_0 = io_core_dgen_2_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfb_0 = io_core_dgen_2_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fence_0 = io_core_dgen_2_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fencei_0 = io_core_dgen_2_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfence_0 = io_core_dgen_2_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_amo_0 = io_core_dgen_2_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_eret_0 = io_core_dgen_2_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sys_pc2epc_0 = io_core_dgen_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rocc_0 = io_core_dgen_2_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_mov_0 = io_core_dgen_2_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ftq_idx_0 = io_core_dgen_2_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_edge_inst_0 = io_core_dgen_2_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_pc_lob_0 = io_core_dgen_2_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_taken_0 = io_core_dgen_2_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_imm_rename_0 = io_core_dgen_2_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_imm_sel_0 = io_core_dgen_2_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_pimm_0 = io_core_dgen_2_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_2_bits_uop_imm_packed_0 = io_core_dgen_2_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_op1_sel_0 = io_core_dgen_2_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_op2_sel_0 = io_core_dgen_2_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wen_0 = io_core_dgen_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_toint_0 = io_core_dgen_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fma_0 = io_core_dgen_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_div_0 = io_core_dgen_2_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_vec_0 = io_core_dgen_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_rob_idx_0 = io_core_dgen_2_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ldq_idx_0 = io_core_dgen_2_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_stq_idx_0 = io_core_dgen_2_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_rxq_idx_0 = io_core_dgen_2_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_pdst_0 = io_core_dgen_2_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs1_0 = io_core_dgen_2_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs2_0 = io_core_dgen_2_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs3_0 = io_core_dgen_2_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ppred_0 = io_core_dgen_2_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs1_busy_0 = io_core_dgen_2_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs2_busy_0 = io_core_dgen_2_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs3_busy_0 = io_core_dgen_2_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ppred_busy_0 = io_core_dgen_2_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_stale_pdst_0 = io_core_dgen_2_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_exception_0 = io_core_dgen_2_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_uop_exc_cause_0 = io_core_dgen_2_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_mem_cmd_0 = io_core_dgen_2_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_mem_size_0 = io_core_dgen_2_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_mem_signed_0 = io_core_dgen_2_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_ldq_0 = io_core_dgen_2_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_stq_0 = io_core_dgen_2_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_unique_0 = io_core_dgen_2_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_flush_on_commit_0 = io_core_dgen_2_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_csr_cmd_0 = io_core_dgen_2_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ldst_is_rs1_0 = io_core_dgen_2_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_ldst_0 = io_core_dgen_2_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs1_0 = io_core_dgen_2_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs2_0 = io_core_dgen_2_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs3_0 = io_core_dgen_2_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dst_rtype_0 = io_core_dgen_2_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs1_rtype_0 = io_core_dgen_2_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs2_rtype_0 = io_core_dgen_2_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_frs3_en_0 = io_core_dgen_2_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fcn_dw_0 = io_core_dgen_2_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_fcn_op_0 = io_core_dgen_2_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_val_0 = io_core_dgen_2_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_fp_rm_0 = io_core_dgen_2_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_typ_0 = io_core_dgen_2_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_pf_if_0 = io_core_dgen_2_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ae_if_0 = io_core_dgen_2_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ma_if_0 = io_core_dgen_2_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_debug_if_0 = io_core_dgen_2_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_xcpt_if_0 = io_core_dgen_2_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_fsrc_0 = io_core_dgen_2_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_tsrc_0 = io_core_dgen_2_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_data_0 = io_core_dgen_2_bits_data; // @[lsu.scala:211:7] wire io_core_sfence_valid_0 = io_core_sfence_valid; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs1_0 = io_core_sfence_bits_rs1; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs2_0 = io_core_sfence_bits_rs2; // @[lsu.scala:211:7] wire [38:0] io_core_sfence_bits_addr_0 = io_core_sfence_bits_addr; // @[lsu.scala:211:7] wire io_core_sfence_bits_asid_0 = io_core_sfence_bits_asid; // @[lsu.scala:211:7] wire io_core_sfence_bits_hv_0 = io_core_sfence_bits_hv; // @[lsu.scala:211:7] wire io_core_sfence_bits_hg_0 = io_core_sfence_bits_hg; // @[lsu.scala:211:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_0_0 = io_core_dis_uops_0_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_1_0 = io_core_dis_uops_0_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_2_0 = io_core_dis_uops_0_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_3_0 = io_core_dis_uops_0_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_0_0 = io_core_dis_uops_0_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_1_0 = io_core_dis_uops_0_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_2_0 = io_core_dis_uops_0_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_3_0 = io_core_dis_uops_0_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_4_0 = io_core_dis_uops_0_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_5_0 = io_core_dis_uops_0_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_6_0 = io_core_dis_uops_0_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_7_0 = io_core_dis_uops_0_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_8_0 = io_core_dis_uops_0_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_9_0 = io_core_dis_uops_0_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_0 = io_core_dis_uops_0_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_agen_0 = io_core_dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_iw_p1_speculative_child_0 = io_core_dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_iw_p2_speculative_child_0 = io_core_dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_dis_col_sel_0 = io_core_dis_uops_0_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_type_0 = io_core_dis_uops_0_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfence_0 = io_core_dis_uops_0_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_eret_0 = io_core_dis_uops_0_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rocc_0 = io_core_dis_uops_0_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_mov_0 = io_core_dis_uops_0_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_imm_rename_0 = io_core_dis_uops_0_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_imm_sel_0 = io_core_dis_uops_0_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_pimm_0 = io_core_dis_uops_0_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_op1_sel_0 = io_core_dis_uops_0_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_op2_sel_0 = io_core_dis_uops_0_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ldst_0 = io_core_dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wen_0 = io_core_dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren1_0 = io_core_dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren2_0 = io_core_dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren3_0 = io_core_dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap12_0 = io_core_dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap23_0 = io_core_dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fromint_0 = io_core_dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_toint_0 = io_core_dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fma_0 = io_core_dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_div_0 = io_core_dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wflags_0 = io_core_dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_vec_0 = io_core_dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ppred_0 = io_core_dis_uops_0_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ppred_busy_0 = io_core_dis_uops_0_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_csr_cmd_0 = io_core_dis_uops_0_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fcn_dw_0 = io_core_dis_uops_0_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_fcn_op_0 = io_core_dis_uops_0_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_fp_rm_0 = io_core_dis_uops_0_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_typ_0 = io_core_dis_uops_0_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_0_0 = io_core_dis_uops_1_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_1_0 = io_core_dis_uops_1_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_2_0 = io_core_dis_uops_1_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_3_0 = io_core_dis_uops_1_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_0_0 = io_core_dis_uops_1_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_1_0 = io_core_dis_uops_1_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_2_0 = io_core_dis_uops_1_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_3_0 = io_core_dis_uops_1_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_4_0 = io_core_dis_uops_1_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_5_0 = io_core_dis_uops_1_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_6_0 = io_core_dis_uops_1_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_7_0 = io_core_dis_uops_1_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_8_0 = io_core_dis_uops_1_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_9_0 = io_core_dis_uops_1_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_0 = io_core_dis_uops_1_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_agen_0 = io_core_dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_iw_p1_speculative_child_0 = io_core_dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_iw_p2_speculative_child_0 = io_core_dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_dis_col_sel_0 = io_core_dis_uops_1_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_type_0 = io_core_dis_uops_1_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfence_0 = io_core_dis_uops_1_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_eret_0 = io_core_dis_uops_1_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rocc_0 = io_core_dis_uops_1_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_mov_0 = io_core_dis_uops_1_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_imm_rename_0 = io_core_dis_uops_1_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_imm_sel_0 = io_core_dis_uops_1_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_pimm_0 = io_core_dis_uops_1_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_op1_sel_0 = io_core_dis_uops_1_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_op2_sel_0 = io_core_dis_uops_1_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ldst_0 = io_core_dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wen_0 = io_core_dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren1_0 = io_core_dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren2_0 = io_core_dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren3_0 = io_core_dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap12_0 = io_core_dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap23_0 = io_core_dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fromint_0 = io_core_dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_toint_0 = io_core_dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fma_0 = io_core_dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_div_0 = io_core_dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wflags_0 = io_core_dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_vec_0 = io_core_dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ppred_0 = io_core_dis_uops_1_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ppred_busy_0 = io_core_dis_uops_1_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_csr_cmd_0 = io_core_dis_uops_1_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fcn_dw_0 = io_core_dis_uops_1_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_fcn_op_0 = io_core_dis_uops_1_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_fp_rm_0 = io_core_dis_uops_1_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_typ_0 = io_core_dis_uops_1_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_valid_0 = io_core_dis_uops_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_2_bits_inst_0 = io_core_dis_uops_2_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_2_bits_debug_inst_0 = io_core_dis_uops_2_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_rvc_0 = io_core_dis_uops_2_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_2_bits_debug_pc_0 = io_core_dis_uops_2_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_0_0 = io_core_dis_uops_2_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_1_0 = io_core_dis_uops_2_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_2_0 = io_core_dis_uops_2_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_3_0 = io_core_dis_uops_2_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_0_0 = io_core_dis_uops_2_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_1_0 = io_core_dis_uops_2_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_2_0 = io_core_dis_uops_2_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_3_0 = io_core_dis_uops_2_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_4_0 = io_core_dis_uops_2_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_5_0 = io_core_dis_uops_2_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_6_0 = io_core_dis_uops_2_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_7_0 = io_core_dis_uops_2_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_8_0 = io_core_dis_uops_2_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_9_0 = io_core_dis_uops_2_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_0 = io_core_dis_uops_2_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_partial_agen_0 = io_core_dis_uops_2_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_2_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_iw_p1_speculative_child_0 = io_core_dis_uops_2_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_iw_p2_speculative_child_0 = io_core_dis_uops_2_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_dis_col_sel_0 = io_core_dis_uops_2_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_2_bits_br_mask_0 = io_core_dis_uops_2_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_2_bits_br_tag_0 = io_core_dis_uops_2_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_2_bits_br_type_0 = io_core_dis_uops_2_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sfb_0 = io_core_dis_uops_2_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_fence_0 = io_core_dis_uops_2_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_fencei_0 = io_core_dis_uops_2_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sfence_0 = io_core_dis_uops_2_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_amo_0 = io_core_dis_uops_2_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_eret_0 = io_core_dis_uops_2_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sys_pc2epc_0 = io_core_dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_rocc_0 = io_core_dis_uops_2_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_mov_0 = io_core_dis_uops_2_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ftq_idx_0 = io_core_dis_uops_2_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_edge_inst_0 = io_core_dis_uops_2_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_pc_lob_0 = io_core_dis_uops_2_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_taken_0 = io_core_dis_uops_2_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_imm_rename_0 = io_core_dis_uops_2_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_imm_sel_0 = io_core_dis_uops_2_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_pimm_0 = io_core_dis_uops_2_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_2_bits_imm_packed_0 = io_core_dis_uops_2_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_op1_sel_0 = io_core_dis_uops_2_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_op2_sel_0 = io_core_dis_uops_2_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ldst_0 = io_core_dis_uops_2_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_wen_0 = io_core_dis_uops_2_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren1_0 = io_core_dis_uops_2_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren2_0 = io_core_dis_uops_2_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren3_0 = io_core_dis_uops_2_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_swap12_0 = io_core_dis_uops_2_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_swap23_0 = io_core_dis_uops_2_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fromint_0 = io_core_dis_uops_2_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_toint_0 = io_core_dis_uops_2_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_2_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fma_0 = io_core_dis_uops_2_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_div_0 = io_core_dis_uops_2_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_2_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_wflags_0 = io_core_dis_uops_2_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_vec_0 = io_core_dis_uops_2_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_rob_idx_0 = io_core_dis_uops_2_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ldq_idx_0 = io_core_dis_uops_2_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_stq_idx_0 = io_core_dis_uops_2_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_rxq_idx_0 = io_core_dis_uops_2_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_pdst_0 = io_core_dis_uops_2_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs1_0 = io_core_dis_uops_2_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs2_0 = io_core_dis_uops_2_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs3_0 = io_core_dis_uops_2_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ppred_0 = io_core_dis_uops_2_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs1_busy_0 = io_core_dis_uops_2_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs2_busy_0 = io_core_dis_uops_2_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs3_busy_0 = io_core_dis_uops_2_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_ppred_busy_0 = io_core_dis_uops_2_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_stale_pdst_0 = io_core_dis_uops_2_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_exception_0 = io_core_dis_uops_2_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_2_bits_exc_cause_0 = io_core_dis_uops_2_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_mem_cmd_0 = io_core_dis_uops_2_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_mem_size_0 = io_core_dis_uops_2_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_mem_signed_0 = io_core_dis_uops_2_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_uses_ldq_0 = io_core_dis_uops_2_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_uses_stq_0 = io_core_dis_uops_2_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_unique_0 = io_core_dis_uops_2_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_flush_on_commit_0 = io_core_dis_uops_2_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_csr_cmd_0 = io_core_dis_uops_2_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_ldst_is_rs1_0 = io_core_dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_ldst_0 = io_core_dis_uops_2_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs1_0 = io_core_dis_uops_2_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs2_0 = io_core_dis_uops_2_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs3_0 = io_core_dis_uops_2_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_dst_rtype_0 = io_core_dis_uops_2_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_lrs1_rtype_0 = io_core_dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_lrs2_rtype_0 = io_core_dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_frs3_en_0 = io_core_dis_uops_2_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fcn_dw_0 = io_core_dis_uops_2_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_fcn_op_0 = io_core_dis_uops_2_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_val_0 = io_core_dis_uops_2_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_fp_rm_0 = io_core_dis_uops_2_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_typ_0 = io_core_dis_uops_2_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_pf_if_0 = io_core_dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_ae_if_0 = io_core_dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_ma_if_0 = io_core_dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_bp_debug_if_0 = io_core_dis_uops_2_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_bp_xcpt_if_0 = io_core_dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_debug_fsrc_0 = io_core_dis_uops_2_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_debug_tsrc_0 = io_core_dis_uops_2_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:211:7] wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:211:7] wire io_core_commit_valids_2_0 = io_core_commit_valids_2; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_2_0 = io_core_commit_arch_valids_2; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_0_0 = io_core_commit_uops_0_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_1_0 = io_core_commit_uops_0_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_2_0 = io_core_commit_uops_0_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_3_0 = io_core_commit_uops_0_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_0_0 = io_core_commit_uops_0_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_1_0 = io_core_commit_uops_0_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_2_0 = io_core_commit_uops_0_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_3_0 = io_core_commit_uops_0_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_4_0 = io_core_commit_uops_0_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_5_0 = io_core_commit_uops_0_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_6_0 = io_core_commit_uops_0_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_7_0 = io_core_commit_uops_0_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_8_0 = io_core_commit_uops_0_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_9_0 = io_core_commit_uops_0_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_0 = io_core_commit_uops_0_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_agen_0 = io_core_commit_uops_0_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_dgen_0 = io_core_commit_uops_0_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_iw_p1_speculative_child_0 = io_core_commit_uops_0_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_iw_p2_speculative_child_0 = io_core_commit_uops_0_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p1_bypass_hint_0 = io_core_commit_uops_0_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p2_bypass_hint_0 = io_core_commit_uops_0_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p3_bypass_hint_0 = io_core_commit_uops_0_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_dis_col_sel_0 = io_core_commit_uops_0_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_type_0 = io_core_commit_uops_0_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfence_0 = io_core_commit_uops_0_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_eret_0 = io_core_commit_uops_0_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rocc_0 = io_core_commit_uops_0_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_mov_0 = io_core_commit_uops_0_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_0_imm_rename_0 = io_core_commit_uops_0_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_imm_sel_0 = io_core_commit_uops_0_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_pimm_0 = io_core_commit_uops_0_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_op1_sel_0 = io_core_commit_uops_0_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_op2_sel_0 = io_core_commit_uops_0_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ldst_0 = io_core_commit_uops_0_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wen_0 = io_core_commit_uops_0_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren1_0 = io_core_commit_uops_0_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren2_0 = io_core_commit_uops_0_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren3_0 = io_core_commit_uops_0_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap12_0 = io_core_commit_uops_0_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap23_0 = io_core_commit_uops_0_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn_0 = io_core_commit_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut_0 = io_core_commit_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fromint_0 = io_core_commit_uops_0_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_toint_0 = io_core_commit_uops_0_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fastpipe_0 = io_core_commit_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fma_0 = io_core_commit_uops_0_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_div_0 = io_core_commit_uops_0_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_sqrt_0 = io_core_commit_uops_0_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wflags_0 = io_core_commit_uops_0_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_vec_0 = io_core_commit_uops_0_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_csr_cmd_0 = io_core_commit_uops_0_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fcn_dw_0 = io_core_commit_uops_0_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_fcn_op_0 = io_core_commit_uops_0_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_fp_rm_0 = io_core_commit_uops_0_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_typ_0 = io_core_commit_uops_0_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_0_0 = io_core_commit_uops_1_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_1_0 = io_core_commit_uops_1_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_2_0 = io_core_commit_uops_1_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_3_0 = io_core_commit_uops_1_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_0_0 = io_core_commit_uops_1_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_1_0 = io_core_commit_uops_1_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_2_0 = io_core_commit_uops_1_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_3_0 = io_core_commit_uops_1_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_4_0 = io_core_commit_uops_1_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_5_0 = io_core_commit_uops_1_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_6_0 = io_core_commit_uops_1_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_7_0 = io_core_commit_uops_1_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_8_0 = io_core_commit_uops_1_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_9_0 = io_core_commit_uops_1_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_0 = io_core_commit_uops_1_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_agen_0 = io_core_commit_uops_1_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_dgen_0 = io_core_commit_uops_1_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_iw_p1_speculative_child_0 = io_core_commit_uops_1_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_iw_p2_speculative_child_0 = io_core_commit_uops_1_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p1_bypass_hint_0 = io_core_commit_uops_1_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p2_bypass_hint_0 = io_core_commit_uops_1_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p3_bypass_hint_0 = io_core_commit_uops_1_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_dis_col_sel_0 = io_core_commit_uops_1_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_type_0 = io_core_commit_uops_1_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfence_0 = io_core_commit_uops_1_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_eret_0 = io_core_commit_uops_1_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rocc_0 = io_core_commit_uops_1_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_mov_0 = io_core_commit_uops_1_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_1_imm_rename_0 = io_core_commit_uops_1_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_imm_sel_0 = io_core_commit_uops_1_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_pimm_0 = io_core_commit_uops_1_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_op1_sel_0 = io_core_commit_uops_1_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_op2_sel_0 = io_core_commit_uops_1_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ldst_0 = io_core_commit_uops_1_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wen_0 = io_core_commit_uops_1_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren1_0 = io_core_commit_uops_1_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren2_0 = io_core_commit_uops_1_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren3_0 = io_core_commit_uops_1_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap12_0 = io_core_commit_uops_1_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap23_0 = io_core_commit_uops_1_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn_0 = io_core_commit_uops_1_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut_0 = io_core_commit_uops_1_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fromint_0 = io_core_commit_uops_1_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_toint_0 = io_core_commit_uops_1_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fastpipe_0 = io_core_commit_uops_1_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fma_0 = io_core_commit_uops_1_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_div_0 = io_core_commit_uops_1_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_sqrt_0 = io_core_commit_uops_1_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wflags_0 = io_core_commit_uops_1_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_vec_0 = io_core_commit_uops_1_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_csr_cmd_0 = io_core_commit_uops_1_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fcn_dw_0 = io_core_commit_uops_1_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_fcn_op_0 = io_core_commit_uops_1_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_fp_rm_0 = io_core_commit_uops_1_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_typ_0 = io_core_commit_uops_1_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_2_inst_0 = io_core_commit_uops_2_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_2_debug_inst_0 = io_core_commit_uops_2_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_rvc_0 = io_core_commit_uops_2_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_2_debug_pc_0 = io_core_commit_uops_2_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_0_0 = io_core_commit_uops_2_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_1_0 = io_core_commit_uops_2_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_2_0 = io_core_commit_uops_2_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_3_0 = io_core_commit_uops_2_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_0_0 = io_core_commit_uops_2_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_1_0 = io_core_commit_uops_2_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_2_0 = io_core_commit_uops_2_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_3_0 = io_core_commit_uops_2_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_4_0 = io_core_commit_uops_2_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_5_0 = io_core_commit_uops_2_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_6_0 = io_core_commit_uops_2_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_7_0 = io_core_commit_uops_2_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_8_0 = io_core_commit_uops_2_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_9_0 = io_core_commit_uops_2_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_0 = io_core_commit_uops_2_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_partial_agen_0 = io_core_commit_uops_2_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_partial_dgen_0 = io_core_commit_uops_2_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_iw_p1_speculative_child_0 = io_core_commit_uops_2_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_iw_p2_speculative_child_0 = io_core_commit_uops_2_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p1_bypass_hint_0 = io_core_commit_uops_2_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p2_bypass_hint_0 = io_core_commit_uops_2_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p3_bypass_hint_0 = io_core_commit_uops_2_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_dis_col_sel_0 = io_core_commit_uops_2_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_2_br_mask_0 = io_core_commit_uops_2_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_2_br_tag_0 = io_core_commit_uops_2_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_2_br_type_0 = io_core_commit_uops_2_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sfb_0 = io_core_commit_uops_2_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_fence_0 = io_core_commit_uops_2_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_fencei_0 = io_core_commit_uops_2_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sfence_0 = io_core_commit_uops_2_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_amo_0 = io_core_commit_uops_2_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_eret_0 = io_core_commit_uops_2_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sys_pc2epc_0 = io_core_commit_uops_2_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_rocc_0 = io_core_commit_uops_2_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_mov_0 = io_core_commit_uops_2_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ftq_idx_0 = io_core_commit_uops_2_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_2_edge_inst_0 = io_core_commit_uops_2_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_pc_lob_0 = io_core_commit_uops_2_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_2_taken_0 = io_core_commit_uops_2_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_2_imm_rename_0 = io_core_commit_uops_2_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_imm_sel_0 = io_core_commit_uops_2_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_pimm_0 = io_core_commit_uops_2_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_2_imm_packed_0 = io_core_commit_uops_2_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_op1_sel_0 = io_core_commit_uops_2_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_op2_sel_0 = io_core_commit_uops_2_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ldst_0 = io_core_commit_uops_2_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_wen_0 = io_core_commit_uops_2_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren1_0 = io_core_commit_uops_2_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren2_0 = io_core_commit_uops_2_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren3_0 = io_core_commit_uops_2_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_swap12_0 = io_core_commit_uops_2_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_swap23_0 = io_core_commit_uops_2_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_ctrl_typeTagIn_0 = io_core_commit_uops_2_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_ctrl_typeTagOut_0 = io_core_commit_uops_2_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fromint_0 = io_core_commit_uops_2_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_toint_0 = io_core_commit_uops_2_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fastpipe_0 = io_core_commit_uops_2_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fma_0 = io_core_commit_uops_2_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_div_0 = io_core_commit_uops_2_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_sqrt_0 = io_core_commit_uops_2_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_wflags_0 = io_core_commit_uops_2_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_vec_0 = io_core_commit_uops_2_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_rob_idx_0 = io_core_commit_uops_2_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ldq_idx_0 = io_core_commit_uops_2_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_stq_idx_0 = io_core_commit_uops_2_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_rxq_idx_0 = io_core_commit_uops_2_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_pdst_0 = io_core_commit_uops_2_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs1_0 = io_core_commit_uops_2_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs2_0 = io_core_commit_uops_2_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs3_0 = io_core_commit_uops_2_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ppred_0 = io_core_commit_uops_2_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs1_busy_0 = io_core_commit_uops_2_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs2_busy_0 = io_core_commit_uops_2_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs3_busy_0 = io_core_commit_uops_2_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_ppred_busy_0 = io_core_commit_uops_2_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_stale_pdst_0 = io_core_commit_uops_2_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_exception_0 = io_core_commit_uops_2_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_2_exc_cause_0 = io_core_commit_uops_2_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_mem_cmd_0 = io_core_commit_uops_2_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_mem_size_0 = io_core_commit_uops_2_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_2_mem_signed_0 = io_core_commit_uops_2_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_2_uses_ldq_0 = io_core_commit_uops_2_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_2_uses_stq_0 = io_core_commit_uops_2_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_unique_0 = io_core_commit_uops_2_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_2_flush_on_commit_0 = io_core_commit_uops_2_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_csr_cmd_0 = io_core_commit_uops_2_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_2_ldst_is_rs1_0 = io_core_commit_uops_2_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_ldst_0 = io_core_commit_uops_2_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs1_0 = io_core_commit_uops_2_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs2_0 = io_core_commit_uops_2_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs3_0 = io_core_commit_uops_2_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_dst_rtype_0 = io_core_commit_uops_2_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_lrs1_rtype_0 = io_core_commit_uops_2_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_lrs2_rtype_0 = io_core_commit_uops_2_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_2_frs3_en_0 = io_core_commit_uops_2_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fcn_dw_0 = io_core_commit_uops_2_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_fcn_op_0 = io_core_commit_uops_2_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_val_0 = io_core_commit_uops_2_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_fp_rm_0 = io_core_commit_uops_2_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_typ_0 = io_core_commit_uops_2_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_pf_if_0 = io_core_commit_uops_2_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_ae_if_0 = io_core_commit_uops_2_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_ma_if_0 = io_core_commit_uops_2_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_bp_debug_if_0 = io_core_commit_uops_2_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_bp_xcpt_if_0 = io_core_commit_uops_2_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_debug_fsrc_0 = io_core_commit_uops_2_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_debug_tsrc_0 = io_core_commit_uops_2_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:211:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_2_0 = io_core_commit_debug_wdata_2; // @[lsu.scala:211:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:211:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:211:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:211:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:211:7] wire [6:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:211:7] wire [6:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:211:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:211:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:211:7] wire io_core_status_debug_0 = io_core_status_debug; // @[lsu.scala:211:7] wire io_core_status_cease_0 = io_core_status_cease; // @[lsu.scala:211:7] wire io_core_status_wfi_0 = io_core_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_core_status_dprv_0 = io_core_status_dprv; // @[lsu.scala:211:7] wire io_core_status_dv_0 = io_core_status_dv; // @[lsu.scala:211:7] wire [1:0] io_core_status_prv_0 = io_core_status_prv; // @[lsu.scala:211:7] wire io_core_status_v_0 = io_core_status_v; // @[lsu.scala:211:7] wire io_core_status_sd_0 = io_core_status_sd; // @[lsu.scala:211:7] wire io_core_status_mpv_0 = io_core_status_mpv; // @[lsu.scala:211:7] wire io_core_status_gva_0 = io_core_status_gva; // @[lsu.scala:211:7] wire io_core_status_tsr_0 = io_core_status_tsr; // @[lsu.scala:211:7] wire io_core_status_tw_0 = io_core_status_tw; // @[lsu.scala:211:7] wire io_core_status_tvm_0 = io_core_status_tvm; // @[lsu.scala:211:7] wire io_core_status_mxr_0 = io_core_status_mxr; // @[lsu.scala:211:7] wire io_core_status_sum_0 = io_core_status_sum; // @[lsu.scala:211:7] wire io_core_status_mprv_0 = io_core_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_core_status_fs_0 = io_core_status_fs; // @[lsu.scala:211:7] wire [1:0] io_core_status_mpp_0 = io_core_status_mpp; // @[lsu.scala:211:7] wire io_core_status_spp_0 = io_core_status_spp; // @[lsu.scala:211:7] wire io_core_status_mpie_0 = io_core_status_mpie; // @[lsu.scala:211:7] wire io_core_status_spie_0 = io_core_status_spie; // @[lsu.scala:211:7] wire io_core_status_mie_0 = io_core_status_mie; // @[lsu.scala:211:7] wire io_core_status_sie_0 = io_core_status_sie; // @[lsu.scala:211:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:211:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_0_0 = io_dmem_resp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_1_0 = io_dmem_resp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_2_0 = io_dmem_resp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_3_0 = io_dmem_resp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_0_0 = io_dmem_resp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_1_0 = io_dmem_resp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_2_0 = io_dmem_resp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_3_0 = io_dmem_resp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_4_0 = io_dmem_resp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_5_0 = io_dmem_resp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_6_0 = io_dmem_resp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_7_0 = io_dmem_resp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_8_0 = io_dmem_resp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_9_0 = io_dmem_resp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_0 = io_dmem_resp_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_dis_col_sel_0 = io_dmem_resp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_type_0 = io_dmem_resp_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfence_0 = io_dmem_resp_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_eret_0 = io_dmem_resp_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rocc_0 = io_dmem_resp_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_mov_0 = io_dmem_resp_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_imm_rename_0 = io_dmem_resp_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_imm_sel_0 = io_dmem_resp_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_pimm_0 = io_dmem_resp_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_op1_sel_0 = io_dmem_resp_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_op2_sel_0 = io_dmem_resp_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wen_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_toint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fma_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_div_0 = io_dmem_resp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_resp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_vec_0 = io_dmem_resp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_csr_cmd_0 = io_dmem_resp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fcn_dw_0 = io_dmem_resp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_fcn_op_0 = io_dmem_resp_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_fp_rm_0 = io_dmem_resp_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_typ_0 = io_dmem_resp_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_valid_0 = io_dmem_store_ack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_inst_0 = io_dmem_store_ack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_debug_inst_0 = io_dmem_store_ack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rvc_0 = io_dmem_store_ack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_uop_debug_pc_0 = io_dmem_store_ack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_0_0 = io_dmem_store_ack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_1_0 = io_dmem_store_ack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_2_0 = io_dmem_store_ack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_3_0 = io_dmem_store_ack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_0_0 = io_dmem_store_ack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_1_0 = io_dmem_store_ack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_2_0 = io_dmem_store_ack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_3_0 = io_dmem_store_ack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_4_0 = io_dmem_store_ack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_5_0 = io_dmem_store_ack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_6_0 = io_dmem_store_ack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_7_0 = io_dmem_store_ack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_8_0 = io_dmem_store_ack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_9_0 = io_dmem_store_ack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_0 = io_dmem_store_ack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_dis_col_sel_0 = io_dmem_store_ack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_store_ack_0_bits_uop_br_mask_0 = io_dmem_store_ack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_tag_0 = io_dmem_store_ack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_type_0 = io_dmem_store_ack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfb_0 = io_dmem_store_ack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fence_0 = io_dmem_store_ack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fencei_0 = io_dmem_store_ack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfence_0 = io_dmem_store_ack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_amo_0 = io_dmem_store_ack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_eret_0 = io_dmem_store_ack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_store_ack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rocc_0 = io_dmem_store_ack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_mov_0 = io_dmem_store_ack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx_0 = io_dmem_store_ack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_edge_inst_0 = io_dmem_store_ack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_pc_lob_0 = io_dmem_store_ack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_taken_0 = io_dmem_store_ack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_imm_rename_0 = io_dmem_store_ack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_imm_sel_0 = io_dmem_store_ack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_pimm_0 = io_dmem_store_ack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_store_ack_0_bits_uop_imm_packed_0 = io_dmem_store_ack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_op1_sel_0 = io_dmem_store_ack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_op2_sel_0 = io_dmem_store_ack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_div_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_rob_idx_0 = io_dmem_store_ack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ldq_idx_0 = io_dmem_store_ack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_stq_idx_0 = io_dmem_store_ack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx_0 = io_dmem_store_ack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_pdst_0 = io_dmem_store_ack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs1_0 = io_dmem_store_ack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs2_0 = io_dmem_store_ack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs3_0 = io_dmem_store_ack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ppred_0 = io_dmem_store_ack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs1_busy_0 = io_dmem_store_ack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs2_busy_0 = io_dmem_store_ack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs3_busy_0 = io_dmem_store_ack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ppred_busy_0 = io_dmem_store_ack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst_0 = io_dmem_store_ack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_exception_0 = io_dmem_store_ack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_uop_exc_cause_0 = io_dmem_store_ack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd_0 = io_dmem_store_ack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_mem_size_0 = io_dmem_store_ack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_mem_signed_0 = io_dmem_store_ack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_ldq_0 = io_dmem_store_ack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_stq_0 = io_dmem_store_ack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_unique_0 = io_dmem_store_ack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_flush_on_commit_0 = io_dmem_store_ack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd_0 = io_dmem_store_ack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ldst_is_rs1_0 = io_dmem_store_ack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_ldst_0 = io_dmem_store_ack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs1_0 = io_dmem_store_ack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs2_0 = io_dmem_store_ack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs3_0 = io_dmem_store_ack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype_0 = io_dmem_store_ack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_frs3_en_0 = io_dmem_store_ack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fcn_dw_0 = io_dmem_store_ack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_fcn_op_0 = io_dmem_store_ack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_val_0 = io_dmem_store_ack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_fp_rm_0 = io_dmem_store_ack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_typ_0 = io_dmem_store_ack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_pf_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ae_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ma_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_debug_if_0 = io_dmem_store_ack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_xcpt_if_0 = io_dmem_store_ack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc_0 = io_dmem_store_ack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc_0 = io_dmem_store_ack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_addr_0 = io_dmem_store_ack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_data_0 = io_dmem_store_ack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_is_hella_0 = io_dmem_store_ack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_0_0 = io_dmem_nack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_1_0 = io_dmem_nack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_2_0 = io_dmem_nack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_3_0 = io_dmem_nack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_0_0 = io_dmem_nack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_1_0 = io_dmem_nack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_2_0 = io_dmem_nack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_3_0 = io_dmem_nack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_4_0 = io_dmem_nack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_5_0 = io_dmem_nack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_6_0 = io_dmem_nack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_7_0 = io_dmem_nack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_8_0 = io_dmem_nack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_9_0 = io_dmem_nack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_0 = io_dmem_nack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_dis_col_sel_0 = io_dmem_nack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_type_0 = io_dmem_nack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfence_0 = io_dmem_nack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_eret_0 = io_dmem_nack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rocc_0 = io_dmem_nack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_mov_0 = io_dmem_nack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_imm_rename_0 = io_dmem_nack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_imm_sel_0 = io_dmem_nack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_pimm_0 = io_dmem_nack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_op1_sel_0 = io_dmem_nack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_op2_sel_0 = io_dmem_nack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_div_0 = io_dmem_nack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_nack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_nack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_csr_cmd_0 = io_dmem_nack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fcn_dw_0 = io_dmem_nack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_fcn_op_0 = io_dmem_nack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_fp_rm_0 = io_dmem_nack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_typ_0 = io_dmem_nack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_ll_resp_valid_0 = io_dmem_ll_resp_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_inst_0 = io_dmem_ll_resp_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_debug_inst_0 = io_dmem_ll_resp_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rvc_0 = io_dmem_ll_resp_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_ll_resp_bits_uop_debug_pc_0 = io_dmem_ll_resp_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_0_0 = io_dmem_ll_resp_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_1_0 = io_dmem_ll_resp_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_2_0 = io_dmem_ll_resp_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_3_0 = io_dmem_ll_resp_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_0_0 = io_dmem_ll_resp_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_1_0 = io_dmem_ll_resp_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_2_0 = io_dmem_ll_resp_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_3_0 = io_dmem_ll_resp_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_4_0 = io_dmem_ll_resp_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_5_0 = io_dmem_ll_resp_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_6_0 = io_dmem_ll_resp_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_7_0 = io_dmem_ll_resp_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_8_0 = io_dmem_ll_resp_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_9_0 = io_dmem_ll_resp_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_0 = io_dmem_ll_resp_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_dis_col_sel_0 = io_dmem_ll_resp_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_ll_resp_bits_uop_br_mask_0 = io_dmem_ll_resp_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_tag_0 = io_dmem_ll_resp_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_type_0 = io_dmem_ll_resp_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfb_0 = io_dmem_ll_resp_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fence_0 = io_dmem_ll_resp_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fencei_0 = io_dmem_ll_resp_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfence_0 = io_dmem_ll_resp_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_amo_0 = io_dmem_ll_resp_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_eret_0 = io_dmem_ll_resp_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 = io_dmem_ll_resp_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rocc_0 = io_dmem_ll_resp_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_mov_0 = io_dmem_ll_resp_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ftq_idx_0 = io_dmem_ll_resp_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_edge_inst_0 = io_dmem_ll_resp_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_pc_lob_0 = io_dmem_ll_resp_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_taken_0 = io_dmem_ll_resp_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_imm_rename_0 = io_dmem_ll_resp_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_imm_sel_0 = io_dmem_ll_resp_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_pimm_0 = io_dmem_ll_resp_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_ll_resp_bits_uop_imm_packed_0 = io_dmem_ll_resp_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_op1_sel_0 = io_dmem_ll_resp_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_op2_sel_0 = io_dmem_ll_resp_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_rob_idx_0 = io_dmem_ll_resp_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ldq_idx_0 = io_dmem_ll_resp_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_stq_idx_0 = io_dmem_ll_resp_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_rxq_idx_0 = io_dmem_ll_resp_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_pdst_0 = io_dmem_ll_resp_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs1_0 = io_dmem_ll_resp_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs2_0 = io_dmem_ll_resp_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs3_0 = io_dmem_ll_resp_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ppred_0 = io_dmem_ll_resp_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs1_busy_0 = io_dmem_ll_resp_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs2_busy_0 = io_dmem_ll_resp_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs3_busy_0 = io_dmem_ll_resp_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ppred_busy_0 = io_dmem_ll_resp_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_stale_pdst_0 = io_dmem_ll_resp_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_exception_0 = io_dmem_ll_resp_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_uop_exc_cause_0 = io_dmem_ll_resp_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_mem_cmd_0 = io_dmem_ll_resp_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_mem_size_0 = io_dmem_ll_resp_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_mem_signed_0 = io_dmem_ll_resp_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_ldq_0 = io_dmem_ll_resp_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_stq_0 = io_dmem_ll_resp_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_unique_0 = io_dmem_ll_resp_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_flush_on_commit_0 = io_dmem_ll_resp_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_csr_cmd_0 = io_dmem_ll_resp_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 = io_dmem_ll_resp_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_ldst_0 = io_dmem_ll_resp_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs1_0 = io_dmem_ll_resp_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs2_0 = io_dmem_ll_resp_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs3_0 = io_dmem_ll_resp_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dst_rtype_0 = io_dmem_ll_resp_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype_0 = io_dmem_ll_resp_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype_0 = io_dmem_ll_resp_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_frs3_en_0 = io_dmem_ll_resp_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fcn_dw_0 = io_dmem_ll_resp_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_fcn_op_0 = io_dmem_ll_resp_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_val_0 = io_dmem_ll_resp_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_fp_rm_0 = io_dmem_ll_resp_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_typ_0 = io_dmem_ll_resp_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 = io_dmem_ll_resp_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_debug_if_0 = io_dmem_ll_resp_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 = io_dmem_ll_resp_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc_0 = io_dmem_ll_resp_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc_0 = io_dmem_ll_resp_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_data_0 = io_dmem_ll_resp_bits_data; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_is_hella_0 = io_dmem_ll_resp_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:211:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:211:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:211:7] wire [127:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:211:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:211:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:211:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:211:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:211:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:211:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:211:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:211:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] _exe_tlb_uop_WIRE_br_mask = 16'h0; // @[lsu.scala:722:68] wire [15:0] _exe_tlb_uop_WIRE_1_br_mask = 16'h0; // @[lsu.scala:723:68] wire [15:0] _exe_tlb_uop_T_2_br_mask = 16'h0; // @[lsu.scala:722:24] wire [15:0] _dmem_req_0_bits_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [15:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:1064:73] wire [15:0] _mem_stq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:1067:87] wire [15:0] _lcam_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [31:0] io_core_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_core_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_core_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_core_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_dmem_s1_nack_advisory_0 = 1'h0; // @[lsu.scala:211:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:211:7] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_16 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_17 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_18 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_19 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_20 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_21 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_22 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_23 = 1'h0; // @[lsu.scala:488:44] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _will_fire_sfence_0_will_fire_T = 1'h0; // @[lsu.scala:656:51] wire _will_fire_sfence_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_sfence_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_sfence_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_commit_fast_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_fast_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_store_commit_fast_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_fast_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_store_commit_fast_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_commit_fast_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_fast_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_load_agen_exec_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_load_agen_exec_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_load_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_load_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_store_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_retry_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_slow_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_slow_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _exe_tlb_uop_WIRE_is_rvc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_4 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_5 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_6 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_7 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_8 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_9 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfb = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fencei = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_amo = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_eret = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_rocc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_mov = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_edge_inst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_taken = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_imm_rename = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_div = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs1_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs2_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs3_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ppred_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_exception = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_mem_signed = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_ldq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_stq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_unique = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_flush_on_commit = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_frs3_en = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fcn_dw = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_val = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_pf_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ae_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ma_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_debug_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_xcpt_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_1_is_rvc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_4 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_5 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_6 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_7 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_8 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_9 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_agen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfb = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fencei = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_amo = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_eret = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sys_pc2epc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_rocc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_mov = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_edge_inst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_taken = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_imm_rename = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ldst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fromint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_toint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fma = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_div = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wflags = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_vec = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs1_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs2_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs3_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ppred_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_exception = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_mem_signed = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_ldq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_stq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_unique = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_flush_on_commit = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ldst_is_rs1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_frs3_en = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fcn_dw = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_val = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_pf_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ae_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ma_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_debug_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_xcpt_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_T_2_is_rvc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_4 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_5 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_6 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_7 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_8 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_9 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfb = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fencei = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_amo = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_eret = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_rocc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_mov = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_edge_inst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_taken = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_imm_rename = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_div = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs1_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs2_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs3_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ppred_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_exception = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_mem_signed = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_ldq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_stq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_unique = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_flush_on_commit = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_frs3_en = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fcn_dw = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_val = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_pf_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ae_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ma_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_debug_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_xcpt_if = 1'h0; // @[lsu.scala:722:24] wire _dbg_bp_T = 1'h0; // @[lsu.scala:788:80] wire _dbg_bp_T_1 = 1'h0; // @[lsu.scala:789:80] wire _dbg_bp_T_3 = 1'h0; // @[lsu.scala:789:104] wire _dbg_bp_T_4 = 1'h0; // @[lsu.scala:788:105] wire _dbg_bp_T_5 = 1'h0; // @[lsu.scala:788:51] wire dbg_bp_0 = 1'h0; // @[lsu.scala:321:49] wire _bp_T = 1'h0; // @[lsu.scala:790:80] wire _bp_T_1 = 1'h0; // @[lsu.scala:791:80] wire _bp_T_3 = 1'h0; // @[lsu.scala:791:103] wire _bp_T_4 = 1'h0; // @[lsu.scala:790:104] wire _bp_T_5 = 1'h0; // @[lsu.scala:790:51] wire bp_0 = 1'h0; // @[lsu.scala:321:49] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:835:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_16 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_17 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_18 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_19 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_20 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_21 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_22 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_23 = 1'h0; // @[lsu.scala:882:44] wire _dmem_req_0_bits_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_can_execute = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_cleared = 1'h0; // @[lsu.scala:1067:87] wire _lcam_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _kill_forward_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire iresp_0_bits_predicated = 1'h0; // @[lsu.scala:1477:19] wire iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1477:19] wire fresp_0_bits_predicated = 1'h0; // @[lsu.scala:1478:19] wire fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1478:19] wire io_core_iresp_0_out_bits_predicated = 1'h0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_fflags_valid = 1'h0; // @[util.scala:114:23] wire wb_spec_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1491:29] wire wb_slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1495:26] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire w1_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire w2_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire iresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire slow_wakeups_0_out_bits_bypassable = 1'h0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_rebusy = 1'h0; // @[util.scala:114:23] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1797:44] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_core_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_ld_byte_mask = 8'h0; // @[lsu.scala:1064:73] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] _exe_tlb_uop_WIRE_op1_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_rxq_idx = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_mem_size = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dst_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs1_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs2_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_typ = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_1_op1_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_rxq_idx = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_mem_size = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dst_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs1_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs2_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_typ = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_T_2_op1_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_rxq_idx = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_mem_size = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dst_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs1_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs2_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_typ = 2'h0; // @[lsu.scala:722:24] wire [1:0] _dmem_req_0_bits_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] _mem_ldq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_stq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _lcam_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] _exe_tlb_uop_WIRE_ftq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_pimm = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ldq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_stq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ppred = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_mem_cmd = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_fcn_op = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_1_ftq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_pimm = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ldq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_stq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ppred = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_mem_cmd = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_fcn_op = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_T_2_ftq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_pimm = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ldq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_stq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ppred = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_mem_cmd = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_fcn_op = 5'h0; // @[lsu.scala:722:24] wire [4:0] _dmem_req_0_bits_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _lcam_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1477:19] wire [4:0] fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1478:19] wire [4:0] io_core_iresp_0_out_bits_fflags_bits = 5'h0; // @[util.scala:114:23] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] _exe_tlb_uop_WIRE_rob_idx = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs1 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs2 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs3 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_stale_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_1_rob_idx = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs1 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs2 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs3 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_stale_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_T_2_rob_idx = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs1 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs2 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs3 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_stale_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _dmem_req_0_bits_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _lcam_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] _exe_tlb_uop_WIRE_exc_cause = 64'h0; // @[lsu.scala:722:68] wire [63:0] _exe_tlb_uop_WIRE_1_exc_cause = 64'h0; // @[lsu.scala:723:68] wire [63:0] _exe_tlb_uop_T_2_exc_cause = 64'h0; // @[lsu.scala:722:24] wire [63:0] _dmem_req_0_bits_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _lcam_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [2:0] _exe_tlb_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_dis_col_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_imm_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_op2_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_csr_cmd = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_fp_rm = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_fsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_tsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_1_iw_p1_speculative_child = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_iw_p2_speculative_child = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_dis_col_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_imm_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_op2_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_csr_cmd = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_fp_rm = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_fsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_tsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_T_2_iw_p1_speculative_child = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_iw_p2_speculative_child = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_dis_col_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_imm_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_op2_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_csr_cmd = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_fp_rm = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_fsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_tsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _dmem_req_0_bits_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iw_p1_speculative_child = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iw_p2_speculative_child = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_dis_col_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_stq_e_WIRE_bits_uop_iw_p1_speculative_child = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_iw_p2_speculative_child = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_dis_col_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _lcam_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] wb_spec_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1491:29] wire [2:0] wb_slow_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1494:29] wire [2:0] slow_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1495:26] wire [2:0] w1_bits_out_speculative_mask = 3'h0; // @[util.scala:109:23] wire [2:0] w2_bits_out_speculative_mask = 3'h0; // @[util.scala:109:23] wire [2:0] slow_wakeups_0_out_bits_speculative_mask = 3'h0; // @[util.scala:114:23] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_has_data = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_clock_enabled = 1'h1; // @[lsu.scala:211:7] wire _will_fire_sfence_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_sfence_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_sfence_0_T_8 = 1'h1; // @[lsu.scala:661:31] wire _will_fire_store_commit_fast_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_fast_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_fast_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_commit_fast_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_fast_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_commit_fast_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_load_agen_exec_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_load_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_load_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_store_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_retry_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_slow_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_slow_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _dmem_req_0_valid_T_2 = 1'h1; // @[lsu.scala:937:86] wire _wakeupArbs_0_io_in_1_valid_T_1 = 1'h1; // @[lsu.scala:1459:40] wire wb_spec_wakeups_0_bits_bypassable = 1'h1; // @[lsu.scala:1491:29] wire w1_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire w2_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:211:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] _exe_tlb_uop_WIRE_br_tag = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_br_type = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_tag = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_type = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_T_2_br_tag = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_br_type = 4'h0; // @[lsu.scala:722:24] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _lcam_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:211:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:211:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:211:7] wire [5:0] _exe_tlb_uop_WIRE_pc_lob = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_ldst = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs1 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs2 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs3 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_1_pc_lob = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_ldst = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs1 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs2 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs3 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_T_2_pc_lob = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_ldst = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs1 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs2 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs3 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _dmem_req_0_bits_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _lcam_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_0 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_1 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_2 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:211:7] wire [31:0] _exe_tlb_uop_WIRE_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_debug_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_1_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_WIRE_1_debug_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_T_2_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _exe_tlb_uop_T_2_debug_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _dmem_req_0_bits_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _lcam_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _lcam_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:211:7] wire [39:0] _exe_tlb_uop_WIRE_debug_pc = 40'h0; // @[lsu.scala:722:68] wire [39:0] _exe_tlb_uop_WIRE_1_debug_pc = 40'h0; // @[lsu.scala:723:68] wire [39:0] _exe_tlb_uop_T_2_debug_pc = 40'h0; // @[lsu.scala:722:24] wire [39:0] _dmem_req_0_bits_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _lcam_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [7:0] _ldq_ld_byte_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _nack_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _forward_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16] wire [19:0] _exe_tlb_uop_WIRE_imm_packed = 20'h0; // @[lsu.scala:722:68] wire [19:0] _exe_tlb_uop_WIRE_1_imm_packed = 20'h0; // @[lsu.scala:723:68] wire [19:0] _exe_tlb_uop_T_2_imm_packed = 20'h0; // @[lsu.scala:722:24] wire [19:0] _dmem_req_0_bits_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1064:73] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1067:87] wire [19:0] _lcam_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [23:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 24'h0; // @[lsu.scala:1064:73] wire [3:0] _stq_tail_plus_sum_T_1 = 4'h6; // @[util.scala:174:43] wire [1:0] io_hellacache_resp_bits_dprv_0 = io_ptw_status_prv_0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_dv_0 = io_ptw_status_v_0; // @[lsu.scala:211:7] wire [31:0] mem_incoming_uop_out_inst = io_core_agen_0_bits_uop_inst_0; // @[util.scala:104:23] wire [31:0] mem_incoming_uop_out_debug_inst = io_core_agen_0_bits_uop_debug_inst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rvc = io_core_agen_0_bits_uop_is_rvc_0; // @[util.scala:104:23] wire [39:0] mem_incoming_uop_out_debug_pc = io_core_agen_0_bits_uop_debug_pc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_0 = io_core_agen_0_bits_uop_iq_type_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_1 = io_core_agen_0_bits_uop_iq_type_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_2 = io_core_agen_0_bits_uop_iq_type_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_3 = io_core_agen_0_bits_uop_iq_type_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_0 = io_core_agen_0_bits_uop_fu_code_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_1 = io_core_agen_0_bits_uop_fu_code_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_2 = io_core_agen_0_bits_uop_fu_code_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_3 = io_core_agen_0_bits_uop_fu_code_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_4 = io_core_agen_0_bits_uop_fu_code_4_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_5 = io_core_agen_0_bits_uop_fu_code_5_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_6 = io_core_agen_0_bits_uop_fu_code_6_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_7 = io_core_agen_0_bits_uop_fu_code_7_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_8 = io_core_agen_0_bits_uop_fu_code_8_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_9 = io_core_agen_0_bits_uop_fu_code_9_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued = io_core_agen_0_bits_uop_iw_issued_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_agen = io_core_agen_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_dgen = io_core_agen_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_iw_p1_speculative_child = io_core_agen_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_iw_p2_speculative_child = io_core_agen_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p1_bypass_hint = io_core_agen_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p2_bypass_hint = io_core_agen_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p3_bypass_hint = io_core_agen_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_dis_col_sel = io_core_agen_0_bits_uop_dis_col_sel_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_tag = io_core_agen_0_bits_uop_br_tag_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_type = io_core_agen_0_bits_uop_br_type_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfb = io_core_agen_0_bits_uop_is_sfb_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fence = io_core_agen_0_bits_uop_is_fence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fencei = io_core_agen_0_bits_uop_is_fencei_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfence = io_core_agen_0_bits_uop_is_sfence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_amo = io_core_agen_0_bits_uop_is_amo_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_eret = io_core_agen_0_bits_uop_is_eret_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sys_pc2epc = io_core_agen_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rocc = io_core_agen_0_bits_uop_is_rocc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_mov = io_core_agen_0_bits_uop_is_mov_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ftq_idx = io_core_agen_0_bits_uop_ftq_idx_0; // @[util.scala:104:23] wire mem_incoming_uop_out_edge_inst = io_core_agen_0_bits_uop_edge_inst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_pc_lob = io_core_agen_0_bits_uop_pc_lob_0; // @[util.scala:104:23] wire mem_incoming_uop_out_taken = io_core_agen_0_bits_uop_taken_0; // @[util.scala:104:23] wire mem_incoming_uop_out_imm_rename = io_core_agen_0_bits_uop_imm_rename_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_imm_sel = io_core_agen_0_bits_uop_imm_sel_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_pimm = io_core_agen_0_bits_uop_pimm_0; // @[util.scala:104:23] wire [19:0] mem_incoming_uop_out_imm_packed = io_core_agen_0_bits_uop_imm_packed_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_op1_sel = io_core_agen_0_bits_uop_op1_sel_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_op2_sel = io_core_agen_0_bits_uop_op2_sel_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ldst = io_core_agen_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wen = io_core_agen_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren1 = io_core_agen_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren2 = io_core_agen_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren3 = io_core_agen_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap12 = io_core_agen_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap23 = io_core_agen_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagIn = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagOut = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fromint = io_core_agen_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_toint = io_core_agen_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fastpipe = io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fma = io_core_agen_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_div = io_core_agen_0_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_sqrt = io_core_agen_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wflags = io_core_agen_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_vec = io_core_agen_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_rob_idx = io_core_agen_0_bits_uop_rob_idx_0; // @[util.scala:104:23] wire [4:0] ldq_incoming_idx_0 = io_core_agen_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :321:49] wire [4:0] mem_incoming_uop_out_ldq_idx = io_core_agen_0_bits_uop_ldq_idx_0; // @[util.scala:104:23] wire [4:0] stq_incoming_idx_0 = io_core_agen_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :321:49] wire [4:0] mem_incoming_uop_out_stq_idx = io_core_agen_0_bits_uop_stq_idx_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_rxq_idx = io_core_agen_0_bits_uop_rxq_idx_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_pdst = io_core_agen_0_bits_uop_pdst_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs1 = io_core_agen_0_bits_uop_prs1_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs2 = io_core_agen_0_bits_uop_prs2_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs3 = io_core_agen_0_bits_uop_prs3_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ppred = io_core_agen_0_bits_uop_ppred_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs1_busy = io_core_agen_0_bits_uop_prs1_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs2_busy = io_core_agen_0_bits_uop_prs2_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs3_busy = io_core_agen_0_bits_uop_prs3_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ppred_busy = io_core_agen_0_bits_uop_ppred_busy_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_stale_pdst = io_core_agen_0_bits_uop_stale_pdst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_exception = io_core_agen_0_bits_uop_exception_0; // @[util.scala:104:23] wire [63:0] mem_incoming_uop_out_exc_cause = io_core_agen_0_bits_uop_exc_cause_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_mem_cmd = io_core_agen_0_bits_uop_mem_cmd_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_mem_size = io_core_agen_0_bits_uop_mem_size_0; // @[util.scala:104:23] wire mem_incoming_uop_out_mem_signed = io_core_agen_0_bits_uop_mem_signed_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_ldq = io_core_agen_0_bits_uop_uses_ldq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_stq = io_core_agen_0_bits_uop_uses_stq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_unique = io_core_agen_0_bits_uop_is_unique_0; // @[util.scala:104:23] wire mem_incoming_uop_out_flush_on_commit = io_core_agen_0_bits_uop_flush_on_commit_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_csr_cmd = io_core_agen_0_bits_uop_csr_cmd_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ldst_is_rs1 = io_core_agen_0_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_ldst = io_core_agen_0_bits_uop_ldst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs1 = io_core_agen_0_bits_uop_lrs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs2 = io_core_agen_0_bits_uop_lrs2_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs3 = io_core_agen_0_bits_uop_lrs3_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dst_rtype = io_core_agen_0_bits_uop_dst_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = io_core_agen_0_bits_uop_lrs1_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = io_core_agen_0_bits_uop_lrs2_rtype_0; // @[util.scala:104:23] wire mem_incoming_uop_out_frs3_en = io_core_agen_0_bits_uop_frs3_en_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fcn_dw = io_core_agen_0_bits_uop_fcn_dw_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_fcn_op = io_core_agen_0_bits_uop_fcn_op_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_val = io_core_agen_0_bits_uop_fp_val_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_fp_rm = io_core_agen_0_bits_uop_fp_rm_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_typ = io_core_agen_0_bits_uop_fp_typ_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_pf_if = io_core_agen_0_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ae_if = io_core_agen_0_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ma_if = io_core_agen_0_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_debug_if = io_core_agen_0_bits_uop_bp_debug_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_xcpt_if = io_core_agen_0_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_fsrc = io_core_agen_0_bits_uop_debug_fsrc_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_tsrc = io_core_agen_0_bits_uop_debug_tsrc_0; // @[util.scala:104:23] wire fresp_0_valid; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_inst; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_debug_inst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rvc; // @[lsu.scala:1478:19] wire [39:0] fresp_0_bits_uop_debug_pc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_4; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_5; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_6; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_7; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_8; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_9; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1478:19] wire [15:0] fresp_0_bits_uop_br_mask; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_tag; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_type; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfb; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fencei; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_amo; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_eret; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rocc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_mov; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ftq_idx; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_edge_inst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_pc_lob; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_taken; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_imm_rename; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_imm_sel; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_pimm; // @[lsu.scala:1478:19] wire [19:0] fresp_0_bits_uop_imm_packed; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_op1_sel; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_op2_sel; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_rob_idx; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ldq_idx; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_stq_idx; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_rxq_idx; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_pdst; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs1; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs2; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs3; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ppred; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs1_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs2_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs3_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ppred_busy; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_stale_pdst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_exception; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_uop_exc_cause; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_mem_cmd; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_mem_size; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_mem_signed; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_ldq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_stq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_unique; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_csr_cmd; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_ldst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs2; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs3; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dst_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_frs3_en; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fcn_dw; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_fcn_op; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_val; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_fp_rm; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_typ; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_data; // @[lsu.scala:1478:19] wire can_fire_sfence_0 = io_core_sfence_valid_0; // @[lsu.scala:211:7, :321:49] wire ldq_full; // @[lsu.scala:369:47] wire ldq_full_1; // @[lsu.scala:369:47] wire ldq_full_2; // @[lsu.scala:369:47] wire stq_full; // @[lsu.scala:373:47] wire stq_full_1; // @[lsu.scala:373:47] wire stq_full_2; // @[lsu.scala:373:47] wire _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_2_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:1423:7] wire [15:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:211:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:211:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:211:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:446:42] wire _io_core_lxcpt_valid_T_4; // @[lsu.scala:1450:39] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:877:22] wire [15:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_type; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_eret; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_mov; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_pimm; // @[lsu.scala:877:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:877:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:877:22] wire _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:1537:55] wire [63:0] io_hellacache_resp_bits_data_word_bypass_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_raw_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire will_fire_release_0; // @[lsu.scala:475:41] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:211:7, :598:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:211:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:211:7] wire _io_hellacache_store_pending_T_22; // @[lsu.scala:1804:52] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:211:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:211:7] wire io_ptw_req_valid_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iwakeups_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_iwakeups_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iwakeups_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iwakeups_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_bypassable_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_speculative_mask_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_rebusy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_valid_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_iresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_iresp_0_valid_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_fresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_fresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_fresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_fresp_0_valid_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_2_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_2_0; // @[lsu.scala:211:7] wire io_core_ldq_full_0_0; // @[lsu.scala:211:7] wire io_core_ldq_full_1_0; // @[lsu.scala:211:7] wire io_core_ldq_full_2_0; // @[lsu.scala:211:7] wire io_core_stq_full_0_0; // @[lsu.scala:211:7] wire io_core_stq_full_1_0; // @[lsu.scala:211:7] wire io_core_stq_full_2_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_2_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_2_bits_0; // @[lsu.scala:211:7] wire io_core_clr_unsafe_0_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:211:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:211:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:211:7] wire io_core_fencei_rdy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:211:7] wire io_dmem_req_valid_0; // @[lsu.scala:211:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_ready_0; // @[lsu.scala:211:7] wire io_dmem_release_ready_0; // @[lsu.scala:211:7] wire io_dmem_force_order_0; // @[lsu.scala:211:7] wire io_hellacache_req_ready_0; // @[lsu.scala:211:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_0; // @[lsu.scala:211:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:211:7] wire io_hellacache_store_pending_0; // @[lsu.scala:211:7] reg ldq_valid_0; // @[lsu.scala:218:36] reg ldq_valid_1; // @[lsu.scala:218:36] reg ldq_valid_2; // @[lsu.scala:218:36] reg ldq_valid_3; // @[lsu.scala:218:36] reg ldq_valid_4; // @[lsu.scala:218:36] reg ldq_valid_5; // @[lsu.scala:218:36] reg ldq_valid_6; // @[lsu.scala:218:36] reg ldq_valid_7; // @[lsu.scala:218:36] reg ldq_valid_8; // @[lsu.scala:218:36] reg ldq_valid_9; // @[lsu.scala:218:36] reg ldq_valid_10; // @[lsu.scala:218:36] reg ldq_valid_11; // @[lsu.scala:218:36] reg ldq_valid_12; // @[lsu.scala:218:36] reg ldq_valid_13; // @[lsu.scala:218:36] reg ldq_valid_14; // @[lsu.scala:218:36] reg ldq_valid_15; // @[lsu.scala:218:36] reg ldq_valid_16; // @[lsu.scala:218:36] reg ldq_valid_17; // @[lsu.scala:218:36] reg ldq_valid_18; // @[lsu.scala:218:36] reg ldq_valid_19; // @[lsu.scala:218:36] reg ldq_valid_20; // @[lsu.scala:218:36] reg ldq_valid_21; // @[lsu.scala:218:36] reg ldq_valid_22; // @[lsu.scala:218:36] reg ldq_valid_23; // @[lsu.scala:218:36] reg [31:0] ldq_uop_0_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_0_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rvc; // @[lsu.scala:219:36] wire l_uop_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_0_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_25_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_0; // @[lsu.scala:219:36] wire l_uop_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_1; // @[lsu.scala:219:36] wire l_uop_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_2; // @[lsu.scala:219:36] wire l_uop_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_3; // @[lsu.scala:219:36] wire l_uop_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_0; // @[lsu.scala:219:36] wire l_uop_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_1; // @[lsu.scala:219:36] wire l_uop_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_2; // @[lsu.scala:219:36] wire l_uop_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_3; // @[lsu.scala:219:36] wire l_uop_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_4; // @[lsu.scala:219:36] wire l_uop_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_5; // @[lsu.scala:219:36] wire l_uop_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_6; // @[lsu.scala:219:36] wire l_uop_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_7; // @[lsu.scala:219:36] wire l_uop_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_8; // @[lsu.scala:219:36] wire l_uop_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_9; // @[lsu.scala:219:36] wire l_uop_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued; // @[lsu.scala:219:36] wire l_uop_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_0_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_25_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfb; // @[lsu.scala:219:36] wire l_uop_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fence; // @[lsu.scala:219:36] wire l_uop_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fencei; // @[lsu.scala:219:36] wire l_uop_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfence; // @[lsu.scala:219:36] wire l_uop_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_amo; // @[lsu.scala:219:36] wire l_uop_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_eret; // @[lsu.scala:219:36] wire l_uop_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rocc; // @[lsu.scala:219:36] wire l_uop_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_mov; // @[lsu.scala:219:36] wire l_uop_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_edge_inst; // @[lsu.scala:219:36] wire l_uop_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_25_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_taken; // @[lsu.scala:219:36] wire l_uop_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1191:37] wire uop_25_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_imm_rename; // @[lsu.scala:219:36] wire l_uop_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_25_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_0_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_25_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs1_busy; // @[lsu.scala:219:36] wire l_uop_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs2_busy; // @[lsu.scala:219:36] wire l_uop_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs3_busy; // @[lsu.scala:219:36] wire l_uop_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ppred_busy; // @[lsu.scala:219:36] wire l_uop_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_exception; // @[lsu.scala:219:36] wire l_uop_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1191:37] wire uop_25_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_0_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_25_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_mem_signed; // @[lsu.scala:219:36] wire l_uop_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_25_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_ldq; // @[lsu.scala:219:36] wire l_uop_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_stq; // @[lsu.scala:219:36] wire l_uop_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_unique; // @[lsu.scala:219:36] wire l_uop_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_25_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_25_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_frs3_en; // @[lsu.scala:219:36] wire l_uop_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_25_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fcn_dw; // @[lsu.scala:219:36] wire l_uop_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_25_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_val; // @[lsu.scala:219:36] wire l_uop_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rvc; // @[lsu.scala:219:36] wire l_uop_1_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_1_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_1_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_26_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_0; // @[lsu.scala:219:36] wire l_uop_1_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_1; // @[lsu.scala:219:36] wire l_uop_1_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_2; // @[lsu.scala:219:36] wire l_uop_1_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_3; // @[lsu.scala:219:36] wire l_uop_1_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_0; // @[lsu.scala:219:36] wire l_uop_1_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_1; // @[lsu.scala:219:36] wire l_uop_1_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_2; // @[lsu.scala:219:36] wire l_uop_1_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_3; // @[lsu.scala:219:36] wire l_uop_1_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_4; // @[lsu.scala:219:36] wire l_uop_1_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_5; // @[lsu.scala:219:36] wire l_uop_1_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_6; // @[lsu.scala:219:36] wire l_uop_1_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_7; // @[lsu.scala:219:36] wire l_uop_1_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_8; // @[lsu.scala:219:36] wire l_uop_1_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_9; // @[lsu.scala:219:36] wire l_uop_1_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued; // @[lsu.scala:219:36] wire l_uop_1_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_1_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_1_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_1_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_1_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_26_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfb; // @[lsu.scala:219:36] wire l_uop_1_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fence; // @[lsu.scala:219:36] wire l_uop_1_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fencei; // @[lsu.scala:219:36] wire l_uop_1_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfence; // @[lsu.scala:219:36] wire l_uop_1_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_amo; // @[lsu.scala:219:36] wire l_uop_1_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_eret; // @[lsu.scala:219:36] wire l_uop_1_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_1_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rocc; // @[lsu.scala:219:36] wire l_uop_1_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_mov; // @[lsu.scala:219:36] wire l_uop_1_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_edge_inst; // @[lsu.scala:219:36] wire l_uop_1_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_26_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_1_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_taken; // @[lsu.scala:219:36] wire l_uop_1_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1191:37] wire uop_26_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_imm_rename; // @[lsu.scala:219:36] wire l_uop_1_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_26_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_1_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_1_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_1_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_26_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_1_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_1_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs1_busy; // @[lsu.scala:219:36] wire l_uop_1_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs2_busy; // @[lsu.scala:219:36] wire l_uop_1_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs3_busy; // @[lsu.scala:219:36] wire l_uop_1_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ppred_busy; // @[lsu.scala:219:36] wire l_uop_1_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_exception; // @[lsu.scala:219:36] wire l_uop_1_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1191:37] wire uop_26_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_1_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_1_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_26_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_1_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_1_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_mem_signed; // @[lsu.scala:219:36] wire l_uop_1_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_26_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_ldq; // @[lsu.scala:219:36] wire l_uop_1_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_stq; // @[lsu.scala:219:36] wire l_uop_1_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_unique; // @[lsu.scala:219:36] wire l_uop_1_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_1_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_26_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_1_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_1_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_26_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_1_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_frs3_en; // @[lsu.scala:219:36] wire l_uop_1_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_26_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fcn_dw; // @[lsu.scala:219:36] wire l_uop_1_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_26_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_1_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_val; // @[lsu.scala:219:36] wire l_uop_1_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_1_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_1_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_1_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rvc; // @[lsu.scala:219:36] wire l_uop_2_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_2_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_2_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_27_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_0; // @[lsu.scala:219:36] wire l_uop_2_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_1; // @[lsu.scala:219:36] wire l_uop_2_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_2; // @[lsu.scala:219:36] wire l_uop_2_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_3; // @[lsu.scala:219:36] wire l_uop_2_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_0; // @[lsu.scala:219:36] wire l_uop_2_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_1; // @[lsu.scala:219:36] wire l_uop_2_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_2; // @[lsu.scala:219:36] wire l_uop_2_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_3; // @[lsu.scala:219:36] wire l_uop_2_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_4; // @[lsu.scala:219:36] wire l_uop_2_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_5; // @[lsu.scala:219:36] wire l_uop_2_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_6; // @[lsu.scala:219:36] wire l_uop_2_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_7; // @[lsu.scala:219:36] wire l_uop_2_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_8; // @[lsu.scala:219:36] wire l_uop_2_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_9; // @[lsu.scala:219:36] wire l_uop_2_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued; // @[lsu.scala:219:36] wire l_uop_2_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_2_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_2_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_2_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_2_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_27_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfb; // @[lsu.scala:219:36] wire l_uop_2_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fence; // @[lsu.scala:219:36] wire l_uop_2_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fencei; // @[lsu.scala:219:36] wire l_uop_2_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfence; // @[lsu.scala:219:36] wire l_uop_2_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_amo; // @[lsu.scala:219:36] wire l_uop_2_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_eret; // @[lsu.scala:219:36] wire l_uop_2_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_2_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rocc; // @[lsu.scala:219:36] wire l_uop_2_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_mov; // @[lsu.scala:219:36] wire l_uop_2_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_edge_inst; // @[lsu.scala:219:36] wire l_uop_2_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_27_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_2_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_taken; // @[lsu.scala:219:36] wire l_uop_2_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1191:37] wire uop_27_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_imm_rename; // @[lsu.scala:219:36] wire l_uop_2_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_27_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_2_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_2_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_2_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_27_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_2_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_2_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs1_busy; // @[lsu.scala:219:36] wire l_uop_2_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs2_busy; // @[lsu.scala:219:36] wire l_uop_2_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs3_busy; // @[lsu.scala:219:36] wire l_uop_2_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ppred_busy; // @[lsu.scala:219:36] wire l_uop_2_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_exception; // @[lsu.scala:219:36] wire l_uop_2_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1191:37] wire uop_27_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_2_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_2_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_27_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_2_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_2_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_mem_signed; // @[lsu.scala:219:36] wire l_uop_2_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_27_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_ldq; // @[lsu.scala:219:36] wire l_uop_2_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_stq; // @[lsu.scala:219:36] wire l_uop_2_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_unique; // @[lsu.scala:219:36] wire l_uop_2_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_2_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_27_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_2_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_2_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_27_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_2_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_frs3_en; // @[lsu.scala:219:36] wire l_uop_2_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_27_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fcn_dw; // @[lsu.scala:219:36] wire l_uop_2_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_27_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_2_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_val; // @[lsu.scala:219:36] wire l_uop_2_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_2_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_2_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_2_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rvc; // @[lsu.scala:219:36] wire l_uop_3_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_3_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_3_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_28_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_0; // @[lsu.scala:219:36] wire l_uop_3_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_1; // @[lsu.scala:219:36] wire l_uop_3_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_2; // @[lsu.scala:219:36] wire l_uop_3_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_3; // @[lsu.scala:219:36] wire l_uop_3_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_0; // @[lsu.scala:219:36] wire l_uop_3_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_1; // @[lsu.scala:219:36] wire l_uop_3_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_2; // @[lsu.scala:219:36] wire l_uop_3_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_3; // @[lsu.scala:219:36] wire l_uop_3_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_4; // @[lsu.scala:219:36] wire l_uop_3_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_5; // @[lsu.scala:219:36] wire l_uop_3_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_6; // @[lsu.scala:219:36] wire l_uop_3_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_7; // @[lsu.scala:219:36] wire l_uop_3_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_8; // @[lsu.scala:219:36] wire l_uop_3_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_9; // @[lsu.scala:219:36] wire l_uop_3_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued; // @[lsu.scala:219:36] wire l_uop_3_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_3_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_3_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_3_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_3_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_28_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfb; // @[lsu.scala:219:36] wire l_uop_3_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fence; // @[lsu.scala:219:36] wire l_uop_3_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fencei; // @[lsu.scala:219:36] wire l_uop_3_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfence; // @[lsu.scala:219:36] wire l_uop_3_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_amo; // @[lsu.scala:219:36] wire l_uop_3_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_eret; // @[lsu.scala:219:36] wire l_uop_3_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_3_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rocc; // @[lsu.scala:219:36] wire l_uop_3_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_mov; // @[lsu.scala:219:36] wire l_uop_3_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_edge_inst; // @[lsu.scala:219:36] wire l_uop_3_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_28_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_3_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_taken; // @[lsu.scala:219:36] wire l_uop_3_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1191:37] wire uop_28_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_imm_rename; // @[lsu.scala:219:36] wire l_uop_3_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_28_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_3_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_3_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_3_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_28_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_3_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_3_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs1_busy; // @[lsu.scala:219:36] wire l_uop_3_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs2_busy; // @[lsu.scala:219:36] wire l_uop_3_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs3_busy; // @[lsu.scala:219:36] wire l_uop_3_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ppred_busy; // @[lsu.scala:219:36] wire l_uop_3_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_exception; // @[lsu.scala:219:36] wire l_uop_3_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1191:37] wire uop_28_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_3_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_3_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_28_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_3_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_3_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_mem_signed; // @[lsu.scala:219:36] wire l_uop_3_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_28_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_ldq; // @[lsu.scala:219:36] wire l_uop_3_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_stq; // @[lsu.scala:219:36] wire l_uop_3_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_unique; // @[lsu.scala:219:36] wire l_uop_3_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_3_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_28_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_3_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_3_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_28_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_3_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_frs3_en; // @[lsu.scala:219:36] wire l_uop_3_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_28_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fcn_dw; // @[lsu.scala:219:36] wire l_uop_3_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_28_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_3_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_val; // @[lsu.scala:219:36] wire l_uop_3_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_3_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_3_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_3_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rvc; // @[lsu.scala:219:36] wire l_uop_4_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_4_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_4_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_29_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_0; // @[lsu.scala:219:36] wire l_uop_4_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_1; // @[lsu.scala:219:36] wire l_uop_4_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_2; // @[lsu.scala:219:36] wire l_uop_4_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_3; // @[lsu.scala:219:36] wire l_uop_4_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_0; // @[lsu.scala:219:36] wire l_uop_4_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_1; // @[lsu.scala:219:36] wire l_uop_4_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_2; // @[lsu.scala:219:36] wire l_uop_4_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_3; // @[lsu.scala:219:36] wire l_uop_4_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_4; // @[lsu.scala:219:36] wire l_uop_4_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_5; // @[lsu.scala:219:36] wire l_uop_4_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_6; // @[lsu.scala:219:36] wire l_uop_4_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_7; // @[lsu.scala:219:36] wire l_uop_4_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_8; // @[lsu.scala:219:36] wire l_uop_4_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_9; // @[lsu.scala:219:36] wire l_uop_4_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued; // @[lsu.scala:219:36] wire l_uop_4_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_4_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_4_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_4_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_4_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_29_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfb; // @[lsu.scala:219:36] wire l_uop_4_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fence; // @[lsu.scala:219:36] wire l_uop_4_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fencei; // @[lsu.scala:219:36] wire l_uop_4_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfence; // @[lsu.scala:219:36] wire l_uop_4_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_amo; // @[lsu.scala:219:36] wire l_uop_4_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_eret; // @[lsu.scala:219:36] wire l_uop_4_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_4_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rocc; // @[lsu.scala:219:36] wire l_uop_4_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_mov; // @[lsu.scala:219:36] wire l_uop_4_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_edge_inst; // @[lsu.scala:219:36] wire l_uop_4_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_29_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_4_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_taken; // @[lsu.scala:219:36] wire l_uop_4_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1191:37] wire uop_29_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_imm_rename; // @[lsu.scala:219:36] wire l_uop_4_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_29_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_4_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_4_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_4_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_29_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_4_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_4_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs1_busy; // @[lsu.scala:219:36] wire l_uop_4_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs2_busy; // @[lsu.scala:219:36] wire l_uop_4_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs3_busy; // @[lsu.scala:219:36] wire l_uop_4_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ppred_busy; // @[lsu.scala:219:36] wire l_uop_4_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_exception; // @[lsu.scala:219:36] wire l_uop_4_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1191:37] wire uop_29_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_4_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_4_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_29_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_4_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_4_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_mem_signed; // @[lsu.scala:219:36] wire l_uop_4_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_29_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_ldq; // @[lsu.scala:219:36] wire l_uop_4_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_stq; // @[lsu.scala:219:36] wire l_uop_4_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_unique; // @[lsu.scala:219:36] wire l_uop_4_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_4_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_29_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_4_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_4_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_29_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_4_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_frs3_en; // @[lsu.scala:219:36] wire l_uop_4_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_29_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fcn_dw; // @[lsu.scala:219:36] wire l_uop_4_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_29_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_4_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_val; // @[lsu.scala:219:36] wire l_uop_4_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_4_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_4_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_4_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rvc; // @[lsu.scala:219:36] wire l_uop_5_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_5_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_5_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_30_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_0; // @[lsu.scala:219:36] wire l_uop_5_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_1; // @[lsu.scala:219:36] wire l_uop_5_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_2; // @[lsu.scala:219:36] wire l_uop_5_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_3; // @[lsu.scala:219:36] wire l_uop_5_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_0; // @[lsu.scala:219:36] wire l_uop_5_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_1; // @[lsu.scala:219:36] wire l_uop_5_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_2; // @[lsu.scala:219:36] wire l_uop_5_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_3; // @[lsu.scala:219:36] wire l_uop_5_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_4; // @[lsu.scala:219:36] wire l_uop_5_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_5; // @[lsu.scala:219:36] wire l_uop_5_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_6; // @[lsu.scala:219:36] wire l_uop_5_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_7; // @[lsu.scala:219:36] wire l_uop_5_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_8; // @[lsu.scala:219:36] wire l_uop_5_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_9; // @[lsu.scala:219:36] wire l_uop_5_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued; // @[lsu.scala:219:36] wire l_uop_5_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_5_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_5_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_5_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_5_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_30_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfb; // @[lsu.scala:219:36] wire l_uop_5_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fence; // @[lsu.scala:219:36] wire l_uop_5_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fencei; // @[lsu.scala:219:36] wire l_uop_5_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfence; // @[lsu.scala:219:36] wire l_uop_5_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_amo; // @[lsu.scala:219:36] wire l_uop_5_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_eret; // @[lsu.scala:219:36] wire l_uop_5_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_5_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rocc; // @[lsu.scala:219:36] wire l_uop_5_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_mov; // @[lsu.scala:219:36] wire l_uop_5_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_edge_inst; // @[lsu.scala:219:36] wire l_uop_5_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_30_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_5_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_taken; // @[lsu.scala:219:36] wire l_uop_5_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1191:37] wire uop_30_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_imm_rename; // @[lsu.scala:219:36] wire l_uop_5_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_30_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_5_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_5_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_5_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_30_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_5_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_5_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs1_busy; // @[lsu.scala:219:36] wire l_uop_5_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs2_busy; // @[lsu.scala:219:36] wire l_uop_5_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs3_busy; // @[lsu.scala:219:36] wire l_uop_5_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ppred_busy; // @[lsu.scala:219:36] wire l_uop_5_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_exception; // @[lsu.scala:219:36] wire l_uop_5_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1191:37] wire uop_30_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_5_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_5_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_30_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_5_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_5_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_mem_signed; // @[lsu.scala:219:36] wire l_uop_5_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_30_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_ldq; // @[lsu.scala:219:36] wire l_uop_5_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_stq; // @[lsu.scala:219:36] wire l_uop_5_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_unique; // @[lsu.scala:219:36] wire l_uop_5_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_5_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_30_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_5_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_5_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_30_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_5_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_frs3_en; // @[lsu.scala:219:36] wire l_uop_5_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_30_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fcn_dw; // @[lsu.scala:219:36] wire l_uop_5_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_30_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_5_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_val; // @[lsu.scala:219:36] wire l_uop_5_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_5_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_5_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_5_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rvc; // @[lsu.scala:219:36] wire l_uop_6_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_6_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_6_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_31_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_0; // @[lsu.scala:219:36] wire l_uop_6_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_1; // @[lsu.scala:219:36] wire l_uop_6_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_2; // @[lsu.scala:219:36] wire l_uop_6_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_3; // @[lsu.scala:219:36] wire l_uop_6_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_0; // @[lsu.scala:219:36] wire l_uop_6_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_1; // @[lsu.scala:219:36] wire l_uop_6_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_2; // @[lsu.scala:219:36] wire l_uop_6_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_3; // @[lsu.scala:219:36] wire l_uop_6_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_4; // @[lsu.scala:219:36] wire l_uop_6_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_5; // @[lsu.scala:219:36] wire l_uop_6_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_6; // @[lsu.scala:219:36] wire l_uop_6_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_7; // @[lsu.scala:219:36] wire l_uop_6_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_8; // @[lsu.scala:219:36] wire l_uop_6_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_9; // @[lsu.scala:219:36] wire l_uop_6_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued; // @[lsu.scala:219:36] wire l_uop_6_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_6_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_6_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_6_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_6_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_31_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfb; // @[lsu.scala:219:36] wire l_uop_6_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fence; // @[lsu.scala:219:36] wire l_uop_6_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fencei; // @[lsu.scala:219:36] wire l_uop_6_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfence; // @[lsu.scala:219:36] wire l_uop_6_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_amo; // @[lsu.scala:219:36] wire l_uop_6_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_eret; // @[lsu.scala:219:36] wire l_uop_6_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_6_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rocc; // @[lsu.scala:219:36] wire l_uop_6_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_mov; // @[lsu.scala:219:36] wire l_uop_6_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_edge_inst; // @[lsu.scala:219:36] wire l_uop_6_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_31_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_6_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_taken; // @[lsu.scala:219:36] wire l_uop_6_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1191:37] wire uop_31_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_imm_rename; // @[lsu.scala:219:36] wire l_uop_6_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_31_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_6_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_6_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_6_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_31_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_6_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_6_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs1_busy; // @[lsu.scala:219:36] wire l_uop_6_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs2_busy; // @[lsu.scala:219:36] wire l_uop_6_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs3_busy; // @[lsu.scala:219:36] wire l_uop_6_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ppred_busy; // @[lsu.scala:219:36] wire l_uop_6_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_exception; // @[lsu.scala:219:36] wire l_uop_6_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1191:37] wire uop_31_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_6_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_6_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_31_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_6_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_6_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_mem_signed; // @[lsu.scala:219:36] wire l_uop_6_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_31_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_ldq; // @[lsu.scala:219:36] wire l_uop_6_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_stq; // @[lsu.scala:219:36] wire l_uop_6_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_unique; // @[lsu.scala:219:36] wire l_uop_6_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_6_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_31_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_6_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_6_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_31_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_6_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_frs3_en; // @[lsu.scala:219:36] wire l_uop_6_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_31_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fcn_dw; // @[lsu.scala:219:36] wire l_uop_6_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_31_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_6_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_val; // @[lsu.scala:219:36] wire l_uop_6_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_6_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_6_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_6_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rvc; // @[lsu.scala:219:36] wire l_uop_7_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_7_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_7_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_32_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_0; // @[lsu.scala:219:36] wire l_uop_7_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_1; // @[lsu.scala:219:36] wire l_uop_7_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_2; // @[lsu.scala:219:36] wire l_uop_7_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_3; // @[lsu.scala:219:36] wire l_uop_7_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_0; // @[lsu.scala:219:36] wire l_uop_7_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_1; // @[lsu.scala:219:36] wire l_uop_7_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_2; // @[lsu.scala:219:36] wire l_uop_7_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_3; // @[lsu.scala:219:36] wire l_uop_7_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_4; // @[lsu.scala:219:36] wire l_uop_7_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_5; // @[lsu.scala:219:36] wire l_uop_7_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_6; // @[lsu.scala:219:36] wire l_uop_7_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_7; // @[lsu.scala:219:36] wire l_uop_7_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_8; // @[lsu.scala:219:36] wire l_uop_7_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_9; // @[lsu.scala:219:36] wire l_uop_7_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued; // @[lsu.scala:219:36] wire l_uop_7_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_7_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_7_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_7_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_7_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_32_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfb; // @[lsu.scala:219:36] wire l_uop_7_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fence; // @[lsu.scala:219:36] wire l_uop_7_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fencei; // @[lsu.scala:219:36] wire l_uop_7_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfence; // @[lsu.scala:219:36] wire l_uop_7_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_amo; // @[lsu.scala:219:36] wire l_uop_7_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_eret; // @[lsu.scala:219:36] wire l_uop_7_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_7_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rocc; // @[lsu.scala:219:36] wire l_uop_7_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_mov; // @[lsu.scala:219:36] wire l_uop_7_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_edge_inst; // @[lsu.scala:219:36] wire l_uop_7_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_32_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_7_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_taken; // @[lsu.scala:219:36] wire l_uop_7_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1191:37] wire uop_32_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_imm_rename; // @[lsu.scala:219:36] wire l_uop_7_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_32_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_7_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_7_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_7_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_32_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_7_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_7_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs1_busy; // @[lsu.scala:219:36] wire l_uop_7_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs2_busy; // @[lsu.scala:219:36] wire l_uop_7_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs3_busy; // @[lsu.scala:219:36] wire l_uop_7_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ppred_busy; // @[lsu.scala:219:36] wire l_uop_7_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_exception; // @[lsu.scala:219:36] wire l_uop_7_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1191:37] wire uop_32_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_7_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_7_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_32_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_7_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_7_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_mem_signed; // @[lsu.scala:219:36] wire l_uop_7_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_32_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_ldq; // @[lsu.scala:219:36] wire l_uop_7_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_stq; // @[lsu.scala:219:36] wire l_uop_7_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_unique; // @[lsu.scala:219:36] wire l_uop_7_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_7_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_32_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_7_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_7_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_32_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_7_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_frs3_en; // @[lsu.scala:219:36] wire l_uop_7_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_32_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fcn_dw; // @[lsu.scala:219:36] wire l_uop_7_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_32_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_7_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_val; // @[lsu.scala:219:36] wire l_uop_7_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_7_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_7_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_7_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_33_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_33_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rvc; // @[lsu.scala:219:36] wire l_uop_8_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_8_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_8_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_33_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_0; // @[lsu.scala:219:36] wire l_uop_8_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_1; // @[lsu.scala:219:36] wire l_uop_8_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_2; // @[lsu.scala:219:36] wire l_uop_8_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_3; // @[lsu.scala:219:36] wire l_uop_8_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_0; // @[lsu.scala:219:36] wire l_uop_8_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_1; // @[lsu.scala:219:36] wire l_uop_8_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_2; // @[lsu.scala:219:36] wire l_uop_8_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_3; // @[lsu.scala:219:36] wire l_uop_8_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_4; // @[lsu.scala:219:36] wire l_uop_8_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_5; // @[lsu.scala:219:36] wire l_uop_8_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_6; // @[lsu.scala:219:36] wire l_uop_8_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_7; // @[lsu.scala:219:36] wire l_uop_8_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_8; // @[lsu.scala:219:36] wire l_uop_8_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_9; // @[lsu.scala:219:36] wire l_uop_8_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued; // @[lsu.scala:219:36] wire l_uop_8_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_8_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_8_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_8_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_8_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_33_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_33_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_33_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfb; // @[lsu.scala:219:36] wire l_uop_8_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fence; // @[lsu.scala:219:36] wire l_uop_8_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fencei; // @[lsu.scala:219:36] wire l_uop_8_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfence; // @[lsu.scala:219:36] wire l_uop_8_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_amo; // @[lsu.scala:219:36] wire l_uop_8_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_eret; // @[lsu.scala:219:36] wire l_uop_8_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_8_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rocc; // @[lsu.scala:219:36] wire l_uop_8_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_mov; // @[lsu.scala:219:36] wire l_uop_8_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_edge_inst; // @[lsu.scala:219:36] wire l_uop_8_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_33_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_8_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_taken; // @[lsu.scala:219:36] wire l_uop_8_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1191:37] wire uop_33_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_imm_rename; // @[lsu.scala:219:36] wire l_uop_8_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_33_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_8_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_8_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_8_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_33_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_8_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_8_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs1_busy; // @[lsu.scala:219:36] wire l_uop_8_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs2_busy; // @[lsu.scala:219:36] wire l_uop_8_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs3_busy; // @[lsu.scala:219:36] wire l_uop_8_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ppred_busy; // @[lsu.scala:219:36] wire l_uop_8_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_exception; // @[lsu.scala:219:36] wire l_uop_8_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1191:37] wire uop_33_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_8_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_8_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_33_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_8_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_8_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_mem_signed; // @[lsu.scala:219:36] wire l_uop_8_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_33_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_ldq; // @[lsu.scala:219:36] wire l_uop_8_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_33_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_stq; // @[lsu.scala:219:36] wire l_uop_8_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_33_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_unique; // @[lsu.scala:219:36] wire l_uop_8_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_8_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_33_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_8_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_8_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_33_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_8_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_frs3_en; // @[lsu.scala:219:36] wire l_uop_8_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_33_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fcn_dw; // @[lsu.scala:219:36] wire l_uop_8_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_33_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_8_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_val; // @[lsu.scala:219:36] wire l_uop_8_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_8_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_8_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_8_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_34_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_34_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rvc; // @[lsu.scala:219:36] wire l_uop_9_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_9_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_9_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_34_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_0; // @[lsu.scala:219:36] wire l_uop_9_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_1; // @[lsu.scala:219:36] wire l_uop_9_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_2; // @[lsu.scala:219:36] wire l_uop_9_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_3; // @[lsu.scala:219:36] wire l_uop_9_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_0; // @[lsu.scala:219:36] wire l_uop_9_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_1; // @[lsu.scala:219:36] wire l_uop_9_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_2; // @[lsu.scala:219:36] wire l_uop_9_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_3; // @[lsu.scala:219:36] wire l_uop_9_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_4; // @[lsu.scala:219:36] wire l_uop_9_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_5; // @[lsu.scala:219:36] wire l_uop_9_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_6; // @[lsu.scala:219:36] wire l_uop_9_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_7; // @[lsu.scala:219:36] wire l_uop_9_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_8; // @[lsu.scala:219:36] wire l_uop_9_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_9; // @[lsu.scala:219:36] wire l_uop_9_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued; // @[lsu.scala:219:36] wire l_uop_9_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_9_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_9_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_9_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_9_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_34_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_34_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_34_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfb; // @[lsu.scala:219:36] wire l_uop_9_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fence; // @[lsu.scala:219:36] wire l_uop_9_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fencei; // @[lsu.scala:219:36] wire l_uop_9_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfence; // @[lsu.scala:219:36] wire l_uop_9_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_amo; // @[lsu.scala:219:36] wire l_uop_9_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_eret; // @[lsu.scala:219:36] wire l_uop_9_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_9_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rocc; // @[lsu.scala:219:36] wire l_uop_9_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_mov; // @[lsu.scala:219:36] wire l_uop_9_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_edge_inst; // @[lsu.scala:219:36] wire l_uop_9_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_34_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_9_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_taken; // @[lsu.scala:219:36] wire l_uop_9_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1191:37] wire uop_34_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_imm_rename; // @[lsu.scala:219:36] wire l_uop_9_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_34_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_9_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_9_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_9_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_34_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_9_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_9_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs1_busy; // @[lsu.scala:219:36] wire l_uop_9_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs2_busy; // @[lsu.scala:219:36] wire l_uop_9_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs3_busy; // @[lsu.scala:219:36] wire l_uop_9_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ppred_busy; // @[lsu.scala:219:36] wire l_uop_9_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_exception; // @[lsu.scala:219:36] wire l_uop_9_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1191:37] wire uop_34_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_9_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_9_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_34_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_9_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_9_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_mem_signed; // @[lsu.scala:219:36] wire l_uop_9_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_34_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_ldq; // @[lsu.scala:219:36] wire l_uop_9_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_34_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_stq; // @[lsu.scala:219:36] wire l_uop_9_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_34_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_unique; // @[lsu.scala:219:36] wire l_uop_9_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_9_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_34_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_9_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_9_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_34_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_9_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_frs3_en; // @[lsu.scala:219:36] wire l_uop_9_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_34_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fcn_dw; // @[lsu.scala:219:36] wire l_uop_9_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_34_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_9_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_val; // @[lsu.scala:219:36] wire l_uop_9_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_9_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_9_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_9_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_35_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_35_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rvc; // @[lsu.scala:219:36] wire l_uop_10_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_10_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_10_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_35_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_0; // @[lsu.scala:219:36] wire l_uop_10_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_1; // @[lsu.scala:219:36] wire l_uop_10_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_2; // @[lsu.scala:219:36] wire l_uop_10_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_3; // @[lsu.scala:219:36] wire l_uop_10_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_0; // @[lsu.scala:219:36] wire l_uop_10_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_1; // @[lsu.scala:219:36] wire l_uop_10_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_2; // @[lsu.scala:219:36] wire l_uop_10_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_3; // @[lsu.scala:219:36] wire l_uop_10_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_4; // @[lsu.scala:219:36] wire l_uop_10_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_5; // @[lsu.scala:219:36] wire l_uop_10_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_6; // @[lsu.scala:219:36] wire l_uop_10_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_7; // @[lsu.scala:219:36] wire l_uop_10_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_8; // @[lsu.scala:219:36] wire l_uop_10_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_9; // @[lsu.scala:219:36] wire l_uop_10_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued; // @[lsu.scala:219:36] wire l_uop_10_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_10_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_10_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_10_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_10_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_35_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_35_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_35_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfb; // @[lsu.scala:219:36] wire l_uop_10_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fence; // @[lsu.scala:219:36] wire l_uop_10_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fencei; // @[lsu.scala:219:36] wire l_uop_10_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfence; // @[lsu.scala:219:36] wire l_uop_10_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_amo; // @[lsu.scala:219:36] wire l_uop_10_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_eret; // @[lsu.scala:219:36] wire l_uop_10_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_10_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rocc; // @[lsu.scala:219:36] wire l_uop_10_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_mov; // @[lsu.scala:219:36] wire l_uop_10_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_edge_inst; // @[lsu.scala:219:36] wire l_uop_10_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_35_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_10_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_taken; // @[lsu.scala:219:36] wire l_uop_10_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1191:37] wire uop_35_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_imm_rename; // @[lsu.scala:219:36] wire l_uop_10_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_35_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_10_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_10_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_10_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_35_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_10_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_10_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs1_busy; // @[lsu.scala:219:36] wire l_uop_10_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs2_busy; // @[lsu.scala:219:36] wire l_uop_10_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs3_busy; // @[lsu.scala:219:36] wire l_uop_10_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ppred_busy; // @[lsu.scala:219:36] wire l_uop_10_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_exception; // @[lsu.scala:219:36] wire l_uop_10_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1191:37] wire uop_35_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_10_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_10_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_35_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_10_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_10_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_mem_signed; // @[lsu.scala:219:36] wire l_uop_10_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_35_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_ldq; // @[lsu.scala:219:36] wire l_uop_10_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_35_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_stq; // @[lsu.scala:219:36] wire l_uop_10_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_35_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_unique; // @[lsu.scala:219:36] wire l_uop_10_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_10_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_35_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_10_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_10_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_35_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_10_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_frs3_en; // @[lsu.scala:219:36] wire l_uop_10_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_35_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fcn_dw; // @[lsu.scala:219:36] wire l_uop_10_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_35_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_10_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_val; // @[lsu.scala:219:36] wire l_uop_10_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_10_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_10_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_10_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_36_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_36_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rvc; // @[lsu.scala:219:36] wire l_uop_11_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_11_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_11_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_36_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_0; // @[lsu.scala:219:36] wire l_uop_11_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_1; // @[lsu.scala:219:36] wire l_uop_11_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_2; // @[lsu.scala:219:36] wire l_uop_11_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_3; // @[lsu.scala:219:36] wire l_uop_11_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_0; // @[lsu.scala:219:36] wire l_uop_11_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_1; // @[lsu.scala:219:36] wire l_uop_11_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_2; // @[lsu.scala:219:36] wire l_uop_11_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_3; // @[lsu.scala:219:36] wire l_uop_11_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_4; // @[lsu.scala:219:36] wire l_uop_11_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_5; // @[lsu.scala:219:36] wire l_uop_11_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_6; // @[lsu.scala:219:36] wire l_uop_11_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_7; // @[lsu.scala:219:36] wire l_uop_11_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_8; // @[lsu.scala:219:36] wire l_uop_11_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_9; // @[lsu.scala:219:36] wire l_uop_11_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued; // @[lsu.scala:219:36] wire l_uop_11_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_11_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_11_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_11_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_11_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_36_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_36_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_36_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfb; // @[lsu.scala:219:36] wire l_uop_11_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fence; // @[lsu.scala:219:36] wire l_uop_11_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fencei; // @[lsu.scala:219:36] wire l_uop_11_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfence; // @[lsu.scala:219:36] wire l_uop_11_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_amo; // @[lsu.scala:219:36] wire l_uop_11_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_eret; // @[lsu.scala:219:36] wire l_uop_11_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_11_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rocc; // @[lsu.scala:219:36] wire l_uop_11_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_mov; // @[lsu.scala:219:36] wire l_uop_11_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_edge_inst; // @[lsu.scala:219:36] wire l_uop_11_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_36_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_11_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_taken; // @[lsu.scala:219:36] wire l_uop_11_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1191:37] wire uop_36_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_imm_rename; // @[lsu.scala:219:36] wire l_uop_11_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_36_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_11_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_11_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_11_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_36_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_11_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_11_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs1_busy; // @[lsu.scala:219:36] wire l_uop_11_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs2_busy; // @[lsu.scala:219:36] wire l_uop_11_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs3_busy; // @[lsu.scala:219:36] wire l_uop_11_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ppred_busy; // @[lsu.scala:219:36] wire l_uop_11_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_exception; // @[lsu.scala:219:36] wire l_uop_11_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1191:37] wire uop_36_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_11_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_11_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_36_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_11_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_11_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_mem_signed; // @[lsu.scala:219:36] wire l_uop_11_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_36_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_ldq; // @[lsu.scala:219:36] wire l_uop_11_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_36_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_stq; // @[lsu.scala:219:36] wire l_uop_11_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_36_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_unique; // @[lsu.scala:219:36] wire l_uop_11_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_11_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_36_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_11_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_11_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_36_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_11_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_frs3_en; // @[lsu.scala:219:36] wire l_uop_11_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_36_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fcn_dw; // @[lsu.scala:219:36] wire l_uop_11_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_36_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_11_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_val; // @[lsu.scala:219:36] wire l_uop_11_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_11_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_11_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_11_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_37_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_37_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rvc; // @[lsu.scala:219:36] wire l_uop_12_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_12_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_12_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_37_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_0; // @[lsu.scala:219:36] wire l_uop_12_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_1; // @[lsu.scala:219:36] wire l_uop_12_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_2; // @[lsu.scala:219:36] wire l_uop_12_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_3; // @[lsu.scala:219:36] wire l_uop_12_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_0; // @[lsu.scala:219:36] wire l_uop_12_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_1; // @[lsu.scala:219:36] wire l_uop_12_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_2; // @[lsu.scala:219:36] wire l_uop_12_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_3; // @[lsu.scala:219:36] wire l_uop_12_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_4; // @[lsu.scala:219:36] wire l_uop_12_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_5; // @[lsu.scala:219:36] wire l_uop_12_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_6; // @[lsu.scala:219:36] wire l_uop_12_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_7; // @[lsu.scala:219:36] wire l_uop_12_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_8; // @[lsu.scala:219:36] wire l_uop_12_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_9; // @[lsu.scala:219:36] wire l_uop_12_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued; // @[lsu.scala:219:36] wire l_uop_12_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_12_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_12_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_12_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_12_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_37_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_37_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_37_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfb; // @[lsu.scala:219:36] wire l_uop_12_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fence; // @[lsu.scala:219:36] wire l_uop_12_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fencei; // @[lsu.scala:219:36] wire l_uop_12_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfence; // @[lsu.scala:219:36] wire l_uop_12_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_amo; // @[lsu.scala:219:36] wire l_uop_12_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_eret; // @[lsu.scala:219:36] wire l_uop_12_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_12_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rocc; // @[lsu.scala:219:36] wire l_uop_12_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_mov; // @[lsu.scala:219:36] wire l_uop_12_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_edge_inst; // @[lsu.scala:219:36] wire l_uop_12_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_37_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_12_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_taken; // @[lsu.scala:219:36] wire l_uop_12_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1191:37] wire uop_37_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_imm_rename; // @[lsu.scala:219:36] wire l_uop_12_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_37_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_12_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_12_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_12_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_37_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_12_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_12_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs1_busy; // @[lsu.scala:219:36] wire l_uop_12_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs2_busy; // @[lsu.scala:219:36] wire l_uop_12_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs3_busy; // @[lsu.scala:219:36] wire l_uop_12_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ppred_busy; // @[lsu.scala:219:36] wire l_uop_12_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_exception; // @[lsu.scala:219:36] wire l_uop_12_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1191:37] wire uop_37_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_12_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_12_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_37_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_12_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_12_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_mem_signed; // @[lsu.scala:219:36] wire l_uop_12_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_37_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_ldq; // @[lsu.scala:219:36] wire l_uop_12_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_37_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_stq; // @[lsu.scala:219:36] wire l_uop_12_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_37_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_unique; // @[lsu.scala:219:36] wire l_uop_12_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_12_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_37_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_12_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_12_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_37_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_12_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_frs3_en; // @[lsu.scala:219:36] wire l_uop_12_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_37_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fcn_dw; // @[lsu.scala:219:36] wire l_uop_12_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_37_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_12_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_val; // @[lsu.scala:219:36] wire l_uop_12_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_12_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_12_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_12_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_38_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_38_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rvc; // @[lsu.scala:219:36] wire l_uop_13_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_13_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_13_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_38_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_0; // @[lsu.scala:219:36] wire l_uop_13_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_1; // @[lsu.scala:219:36] wire l_uop_13_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_2; // @[lsu.scala:219:36] wire l_uop_13_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_3; // @[lsu.scala:219:36] wire l_uop_13_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_0; // @[lsu.scala:219:36] wire l_uop_13_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_1; // @[lsu.scala:219:36] wire l_uop_13_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_2; // @[lsu.scala:219:36] wire l_uop_13_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_3; // @[lsu.scala:219:36] wire l_uop_13_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_4; // @[lsu.scala:219:36] wire l_uop_13_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_5; // @[lsu.scala:219:36] wire l_uop_13_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_6; // @[lsu.scala:219:36] wire l_uop_13_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_7; // @[lsu.scala:219:36] wire l_uop_13_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_8; // @[lsu.scala:219:36] wire l_uop_13_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_9; // @[lsu.scala:219:36] wire l_uop_13_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued; // @[lsu.scala:219:36] wire l_uop_13_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_13_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_13_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_13_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_13_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_38_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_38_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_38_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfb; // @[lsu.scala:219:36] wire l_uop_13_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fence; // @[lsu.scala:219:36] wire l_uop_13_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fencei; // @[lsu.scala:219:36] wire l_uop_13_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfence; // @[lsu.scala:219:36] wire l_uop_13_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_amo; // @[lsu.scala:219:36] wire l_uop_13_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_eret; // @[lsu.scala:219:36] wire l_uop_13_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_13_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rocc; // @[lsu.scala:219:36] wire l_uop_13_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_mov; // @[lsu.scala:219:36] wire l_uop_13_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_edge_inst; // @[lsu.scala:219:36] wire l_uop_13_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_38_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_13_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_taken; // @[lsu.scala:219:36] wire l_uop_13_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1191:37] wire uop_38_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_imm_rename; // @[lsu.scala:219:36] wire l_uop_13_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_38_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_13_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_13_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_13_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_38_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_13_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_13_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs1_busy; // @[lsu.scala:219:36] wire l_uop_13_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs2_busy; // @[lsu.scala:219:36] wire l_uop_13_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs3_busy; // @[lsu.scala:219:36] wire l_uop_13_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ppred_busy; // @[lsu.scala:219:36] wire l_uop_13_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_exception; // @[lsu.scala:219:36] wire l_uop_13_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1191:37] wire uop_38_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_13_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_13_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_38_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_13_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_13_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_mem_signed; // @[lsu.scala:219:36] wire l_uop_13_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_38_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_ldq; // @[lsu.scala:219:36] wire l_uop_13_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_38_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_stq; // @[lsu.scala:219:36] wire l_uop_13_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_38_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_unique; // @[lsu.scala:219:36] wire l_uop_13_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_13_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_38_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_13_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_13_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_38_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_13_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_frs3_en; // @[lsu.scala:219:36] wire l_uop_13_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_38_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fcn_dw; // @[lsu.scala:219:36] wire l_uop_13_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_38_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_13_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_val; // @[lsu.scala:219:36] wire l_uop_13_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_13_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_13_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_13_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_39_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_39_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rvc; // @[lsu.scala:219:36] wire l_uop_14_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_14_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_14_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_39_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_0; // @[lsu.scala:219:36] wire l_uop_14_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_1; // @[lsu.scala:219:36] wire l_uop_14_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_2; // @[lsu.scala:219:36] wire l_uop_14_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_3; // @[lsu.scala:219:36] wire l_uop_14_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_0; // @[lsu.scala:219:36] wire l_uop_14_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_1; // @[lsu.scala:219:36] wire l_uop_14_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_2; // @[lsu.scala:219:36] wire l_uop_14_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_3; // @[lsu.scala:219:36] wire l_uop_14_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_4; // @[lsu.scala:219:36] wire l_uop_14_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_5; // @[lsu.scala:219:36] wire l_uop_14_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_6; // @[lsu.scala:219:36] wire l_uop_14_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_7; // @[lsu.scala:219:36] wire l_uop_14_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_8; // @[lsu.scala:219:36] wire l_uop_14_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_9; // @[lsu.scala:219:36] wire l_uop_14_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued; // @[lsu.scala:219:36] wire l_uop_14_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_14_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_14_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_14_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_14_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_39_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_39_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_39_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfb; // @[lsu.scala:219:36] wire l_uop_14_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fence; // @[lsu.scala:219:36] wire l_uop_14_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fencei; // @[lsu.scala:219:36] wire l_uop_14_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfence; // @[lsu.scala:219:36] wire l_uop_14_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_amo; // @[lsu.scala:219:36] wire l_uop_14_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_eret; // @[lsu.scala:219:36] wire l_uop_14_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_14_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rocc; // @[lsu.scala:219:36] wire l_uop_14_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_mov; // @[lsu.scala:219:36] wire l_uop_14_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_edge_inst; // @[lsu.scala:219:36] wire l_uop_14_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_39_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_14_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_taken; // @[lsu.scala:219:36] wire l_uop_14_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1191:37] wire uop_39_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_imm_rename; // @[lsu.scala:219:36] wire l_uop_14_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_39_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_14_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_14_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_14_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_39_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_14_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_14_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs1_busy; // @[lsu.scala:219:36] wire l_uop_14_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs2_busy; // @[lsu.scala:219:36] wire l_uop_14_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs3_busy; // @[lsu.scala:219:36] wire l_uop_14_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ppred_busy; // @[lsu.scala:219:36] wire l_uop_14_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_exception; // @[lsu.scala:219:36] wire l_uop_14_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1191:37] wire uop_39_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_14_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_14_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_39_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_14_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_14_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_mem_signed; // @[lsu.scala:219:36] wire l_uop_14_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_39_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_ldq; // @[lsu.scala:219:36] wire l_uop_14_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_39_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_stq; // @[lsu.scala:219:36] wire l_uop_14_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_39_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_unique; // @[lsu.scala:219:36] wire l_uop_14_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_14_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_39_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_14_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_14_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_39_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_14_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_frs3_en; // @[lsu.scala:219:36] wire l_uop_14_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_39_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fcn_dw; // @[lsu.scala:219:36] wire l_uop_14_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_39_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_14_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_val; // @[lsu.scala:219:36] wire l_uop_14_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_14_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_14_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_14_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_40_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_40_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rvc; // @[lsu.scala:219:36] wire l_uop_15_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_15_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_15_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_40_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_0; // @[lsu.scala:219:36] wire l_uop_15_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_1; // @[lsu.scala:219:36] wire l_uop_15_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_2; // @[lsu.scala:219:36] wire l_uop_15_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_3; // @[lsu.scala:219:36] wire l_uop_15_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_0; // @[lsu.scala:219:36] wire l_uop_15_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_1; // @[lsu.scala:219:36] wire l_uop_15_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_2; // @[lsu.scala:219:36] wire l_uop_15_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_3; // @[lsu.scala:219:36] wire l_uop_15_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_4; // @[lsu.scala:219:36] wire l_uop_15_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_5; // @[lsu.scala:219:36] wire l_uop_15_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_6; // @[lsu.scala:219:36] wire l_uop_15_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_7; // @[lsu.scala:219:36] wire l_uop_15_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_8; // @[lsu.scala:219:36] wire l_uop_15_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_9; // @[lsu.scala:219:36] wire l_uop_15_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued; // @[lsu.scala:219:36] wire l_uop_15_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_15_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_15_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_15_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_15_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_40_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_40_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_40_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfb; // @[lsu.scala:219:36] wire l_uop_15_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fence; // @[lsu.scala:219:36] wire l_uop_15_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fencei; // @[lsu.scala:219:36] wire l_uop_15_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfence; // @[lsu.scala:219:36] wire l_uop_15_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_amo; // @[lsu.scala:219:36] wire l_uop_15_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_eret; // @[lsu.scala:219:36] wire l_uop_15_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_15_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rocc; // @[lsu.scala:219:36] wire l_uop_15_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_mov; // @[lsu.scala:219:36] wire l_uop_15_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_edge_inst; // @[lsu.scala:219:36] wire l_uop_15_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_40_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_15_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_taken; // @[lsu.scala:219:36] wire l_uop_15_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1191:37] wire uop_40_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_imm_rename; // @[lsu.scala:219:36] wire l_uop_15_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_40_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_15_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_15_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_15_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_40_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_15_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_15_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs1_busy; // @[lsu.scala:219:36] wire l_uop_15_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs2_busy; // @[lsu.scala:219:36] wire l_uop_15_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs3_busy; // @[lsu.scala:219:36] wire l_uop_15_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ppred_busy; // @[lsu.scala:219:36] wire l_uop_15_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_exception; // @[lsu.scala:219:36] wire l_uop_15_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1191:37] wire uop_40_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_15_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_15_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_40_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_15_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_15_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_mem_signed; // @[lsu.scala:219:36] wire l_uop_15_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_40_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_ldq; // @[lsu.scala:219:36] wire l_uop_15_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_40_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_stq; // @[lsu.scala:219:36] wire l_uop_15_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_40_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_unique; // @[lsu.scala:219:36] wire l_uop_15_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_15_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_40_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_15_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_15_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_40_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_15_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_frs3_en; // @[lsu.scala:219:36] wire l_uop_15_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_40_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fcn_dw; // @[lsu.scala:219:36] wire l_uop_15_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_40_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_15_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_val; // @[lsu.scala:219:36] wire l_uop_15_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_15_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_15_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_15_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_16_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_16_inst = ldq_uop_16_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_41_inst = ldq_uop_16_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_16_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_16_debug_inst = ldq_uop_16_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_41_debug_inst = ldq_uop_16_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_rvc; // @[lsu.scala:219:36] wire l_uop_16_is_rvc = ldq_uop_16_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_rvc = ldq_uop_16_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_16_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_16_debug_pc = ldq_uop_16_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_41_debug_pc = ldq_uop_16_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_0; // @[lsu.scala:219:36] wire l_uop_16_iq_type_0 = ldq_uop_16_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_0 = ldq_uop_16_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_1; // @[lsu.scala:219:36] wire l_uop_16_iq_type_1 = ldq_uop_16_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_1 = ldq_uop_16_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_2; // @[lsu.scala:219:36] wire l_uop_16_iq_type_2 = ldq_uop_16_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_2 = ldq_uop_16_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_3; // @[lsu.scala:219:36] wire l_uop_16_iq_type_3 = ldq_uop_16_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_3 = ldq_uop_16_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_0; // @[lsu.scala:219:36] wire l_uop_16_fu_code_0 = ldq_uop_16_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_0 = ldq_uop_16_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_1; // @[lsu.scala:219:36] wire l_uop_16_fu_code_1 = ldq_uop_16_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_1 = ldq_uop_16_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_2; // @[lsu.scala:219:36] wire l_uop_16_fu_code_2 = ldq_uop_16_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_2 = ldq_uop_16_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_3; // @[lsu.scala:219:36] wire l_uop_16_fu_code_3 = ldq_uop_16_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_3 = ldq_uop_16_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_4; // @[lsu.scala:219:36] wire l_uop_16_fu_code_4 = ldq_uop_16_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_4 = ldq_uop_16_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_5; // @[lsu.scala:219:36] wire l_uop_16_fu_code_5 = ldq_uop_16_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_5 = ldq_uop_16_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_6; // @[lsu.scala:219:36] wire l_uop_16_fu_code_6 = ldq_uop_16_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_6 = ldq_uop_16_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_7; // @[lsu.scala:219:36] wire l_uop_16_fu_code_7 = ldq_uop_16_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_7 = ldq_uop_16_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_8; // @[lsu.scala:219:36] wire l_uop_16_fu_code_8 = ldq_uop_16_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_8 = ldq_uop_16_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_9; // @[lsu.scala:219:36] wire l_uop_16_fu_code_9 = ldq_uop_16_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_9 = ldq_uop_16_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued; // @[lsu.scala:219:36] wire l_uop_16_iw_issued = ldq_uop_16_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued = ldq_uop_16_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_16_iw_issued_partial_agen = ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued_partial_agen = ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_16_iw_issued_partial_dgen = ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued_partial_dgen = ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_16_iw_p1_speculative_child = ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_iw_p1_speculative_child = ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_16_iw_p2_speculative_child = ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_iw_p2_speculative_child = ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p1_bypass_hint = ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p1_bypass_hint = ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p2_bypass_hint = ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p2_bypass_hint = ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p3_bypass_hint = ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p3_bypass_hint = ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_dis_col_sel = ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_dis_col_sel = ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_16_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_16_br_mask = ldq_uop_16_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_41_br_mask = ldq_uop_16_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_16_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_16_br_tag = ldq_uop_16_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_41_br_tag = ldq_uop_16_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_16_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_16_br_type = ldq_uop_16_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_41_br_type = ldq_uop_16_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sfb; // @[lsu.scala:219:36] wire l_uop_16_is_sfb = ldq_uop_16_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sfb = ldq_uop_16_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_fence; // @[lsu.scala:219:36] wire l_uop_16_is_fence = ldq_uop_16_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_fence = ldq_uop_16_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_fencei; // @[lsu.scala:219:36] wire l_uop_16_is_fencei = ldq_uop_16_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_fencei = ldq_uop_16_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sfence; // @[lsu.scala:219:36] wire l_uop_16_is_sfence = ldq_uop_16_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sfence = ldq_uop_16_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_amo; // @[lsu.scala:219:36] wire l_uop_16_is_amo = ldq_uop_16_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_amo = ldq_uop_16_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_eret; // @[lsu.scala:219:36] wire l_uop_16_is_eret = ldq_uop_16_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_eret = ldq_uop_16_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_16_is_sys_pc2epc = ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sys_pc2epc = ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_rocc; // @[lsu.scala:219:36] wire l_uop_16_is_rocc = ldq_uop_16_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_rocc = ldq_uop_16_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_mov; // @[lsu.scala:219:36] wire l_uop_16_is_mov = ldq_uop_16_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_mov = ldq_uop_16_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ftq_idx = ldq_uop_16_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ftq_idx = ldq_uop_16_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_edge_inst; // @[lsu.scala:219:36] wire l_uop_16_edge_inst = ldq_uop_16_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_41_edge_inst = ldq_uop_16_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_16_pc_lob = ldq_uop_16_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_pc_lob = ldq_uop_16_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_taken; // @[lsu.scala:219:36] wire l_uop_16_taken = ldq_uop_16_taken; // @[lsu.scala:219:36, :1191:37] wire uop_41_taken = ldq_uop_16_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_imm_rename; // @[lsu.scala:219:36] wire l_uop_16_imm_rename = ldq_uop_16_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_41_imm_rename = ldq_uop_16_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_imm_sel = ldq_uop_16_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_imm_sel = ldq_uop_16_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_16_pimm = ldq_uop_16_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_pimm = ldq_uop_16_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_16_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_16_imm_packed = ldq_uop_16_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_41_imm_packed = ldq_uop_16_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_16_op1_sel = ldq_uop_16_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_op1_sel = ldq_uop_16_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_op2_sel = ldq_uop_16_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_op2_sel = ldq_uop_16_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ldst = ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ldst = ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_wen = ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_wen = ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren1 = ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren1 = ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren2 = ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren2 = ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren3 = ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren3 = ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_swap12 = ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_swap12 = ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_swap23 = ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_swap23 = ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_ctrl_typeTagIn = ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_ctrl_typeTagIn = ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_ctrl_typeTagOut = ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_ctrl_typeTagOut = ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fromint = ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fromint = ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_toint = ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_toint = ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fastpipe = ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fastpipe = ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fma = ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fma = ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_div = ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_div = ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_sqrt = ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_sqrt = ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_wflags = ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_wflags = ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_vec = ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_vec = ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_16_rob_idx = ldq_uop_16_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_rob_idx = ldq_uop_16_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ldq_idx = ldq_uop_16_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ldq_idx = ldq_uop_16_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_stq_idx = ldq_uop_16_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_stq_idx = ldq_uop_16_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_16_rxq_idx = ldq_uop_16_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_rxq_idx = ldq_uop_16_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_16_pdst = ldq_uop_16_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_pdst = ldq_uop_16_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs1 = ldq_uop_16_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs1 = ldq_uop_16_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs2 = ldq_uop_16_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs2 = ldq_uop_16_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs3 = ldq_uop_16_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs3 = ldq_uop_16_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ppred = ldq_uop_16_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ppred = ldq_uop_16_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs1_busy; // @[lsu.scala:219:36] wire l_uop_16_prs1_busy = ldq_uop_16_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs1_busy = ldq_uop_16_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs2_busy; // @[lsu.scala:219:36] wire l_uop_16_prs2_busy = ldq_uop_16_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs2_busy = ldq_uop_16_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs3_busy; // @[lsu.scala:219:36] wire l_uop_16_prs3_busy = ldq_uop_16_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs3_busy = ldq_uop_16_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_ppred_busy; // @[lsu.scala:219:36] wire l_uop_16_ppred_busy = ldq_uop_16_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_ppred_busy = ldq_uop_16_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_16_stale_pdst = ldq_uop_16_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_stale_pdst = ldq_uop_16_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_exception; // @[lsu.scala:219:36] wire l_uop_16_exception = ldq_uop_16_exception; // @[lsu.scala:219:36, :1191:37] wire uop_41_exception = ldq_uop_16_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_16_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_16_exc_cause = ldq_uop_16_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_41_exc_cause = ldq_uop_16_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_16_mem_cmd = ldq_uop_16_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_mem_cmd = ldq_uop_16_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_16_mem_size = ldq_uop_16_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_mem_size = ldq_uop_16_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_mem_signed; // @[lsu.scala:219:36] wire l_uop_16_mem_signed = ldq_uop_16_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_41_mem_signed = ldq_uop_16_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_uses_ldq; // @[lsu.scala:219:36] wire l_uop_16_uses_ldq = ldq_uop_16_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_41_uses_ldq = ldq_uop_16_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_uses_stq; // @[lsu.scala:219:36] wire l_uop_16_uses_stq = ldq_uop_16_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_41_uses_stq = ldq_uop_16_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_unique; // @[lsu.scala:219:36] wire l_uop_16_is_unique = ldq_uop_16_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_unique = ldq_uop_16_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_16_flush_on_commit = ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_41_flush_on_commit = ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_16_csr_cmd = ldq_uop_16_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_csr_cmd = ldq_uop_16_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_16_ldst_is_rs1 = ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_41_ldst_is_rs1 = ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_16_ldst = ldq_uop_16_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_ldst = ldq_uop_16_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs1 = ldq_uop_16_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs1 = ldq_uop_16_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs2 = ldq_uop_16_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs2 = ldq_uop_16_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs3 = ldq_uop_16_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs3 = ldq_uop_16_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_dst_rtype = ldq_uop_16_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_dst_rtype = ldq_uop_16_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_lrs1_rtype = ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_lrs1_rtype = ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_lrs2_rtype = ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_lrs2_rtype = ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_frs3_en; // @[lsu.scala:219:36] wire l_uop_16_frs3_en = ldq_uop_16_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_41_frs3_en = ldq_uop_16_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fcn_dw; // @[lsu.scala:219:36] wire l_uop_16_fcn_dw = ldq_uop_16_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_41_fcn_dw = ldq_uop_16_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_16_fcn_op = ldq_uop_16_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_fcn_op = ldq_uop_16_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_val; // @[lsu.scala:219:36] wire l_uop_16_fp_val = ldq_uop_16_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_val = ldq_uop_16_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_16_fp_rm = ldq_uop_16_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_fp_rm = ldq_uop_16_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_typ = ldq_uop_16_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_typ = ldq_uop_16_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_pf_if = ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_pf_if = ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_ae_if = ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_ae_if = ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_ma_if = ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_ma_if = ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_16_bp_debug_if = ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_bp_debug_if = ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_16_bp_xcpt_if = ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_bp_xcpt_if = ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_16_debug_fsrc = ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_debug_fsrc = ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_16_debug_tsrc = ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_debug_tsrc = ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_17_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_17_inst = ldq_uop_17_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_42_inst = ldq_uop_17_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_17_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_17_debug_inst = ldq_uop_17_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_42_debug_inst = ldq_uop_17_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_rvc; // @[lsu.scala:219:36] wire l_uop_17_is_rvc = ldq_uop_17_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_rvc = ldq_uop_17_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_17_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_17_debug_pc = ldq_uop_17_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_42_debug_pc = ldq_uop_17_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_0; // @[lsu.scala:219:36] wire l_uop_17_iq_type_0 = ldq_uop_17_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_0 = ldq_uop_17_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_1; // @[lsu.scala:219:36] wire l_uop_17_iq_type_1 = ldq_uop_17_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_1 = ldq_uop_17_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_2; // @[lsu.scala:219:36] wire l_uop_17_iq_type_2 = ldq_uop_17_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_2 = ldq_uop_17_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_3; // @[lsu.scala:219:36] wire l_uop_17_iq_type_3 = ldq_uop_17_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_3 = ldq_uop_17_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_0; // @[lsu.scala:219:36] wire l_uop_17_fu_code_0 = ldq_uop_17_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_0 = ldq_uop_17_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_1; // @[lsu.scala:219:36] wire l_uop_17_fu_code_1 = ldq_uop_17_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_1 = ldq_uop_17_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_2; // @[lsu.scala:219:36] wire l_uop_17_fu_code_2 = ldq_uop_17_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_2 = ldq_uop_17_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_3; // @[lsu.scala:219:36] wire l_uop_17_fu_code_3 = ldq_uop_17_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_3 = ldq_uop_17_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_4; // @[lsu.scala:219:36] wire l_uop_17_fu_code_4 = ldq_uop_17_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_4 = ldq_uop_17_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_5; // @[lsu.scala:219:36] wire l_uop_17_fu_code_5 = ldq_uop_17_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_5 = ldq_uop_17_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_6; // @[lsu.scala:219:36] wire l_uop_17_fu_code_6 = ldq_uop_17_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_6 = ldq_uop_17_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_7; // @[lsu.scala:219:36] wire l_uop_17_fu_code_7 = ldq_uop_17_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_7 = ldq_uop_17_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_8; // @[lsu.scala:219:36] wire l_uop_17_fu_code_8 = ldq_uop_17_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_8 = ldq_uop_17_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_9; // @[lsu.scala:219:36] wire l_uop_17_fu_code_9 = ldq_uop_17_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_9 = ldq_uop_17_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued; // @[lsu.scala:219:36] wire l_uop_17_iw_issued = ldq_uop_17_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued = ldq_uop_17_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_17_iw_issued_partial_agen = ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued_partial_agen = ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_17_iw_issued_partial_dgen = ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued_partial_dgen = ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_17_iw_p1_speculative_child = ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_iw_p1_speculative_child = ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_17_iw_p2_speculative_child = ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_iw_p2_speculative_child = ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p1_bypass_hint = ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p1_bypass_hint = ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p2_bypass_hint = ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p2_bypass_hint = ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p3_bypass_hint = ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p3_bypass_hint = ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_dis_col_sel = ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_dis_col_sel = ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_17_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_17_br_mask = ldq_uop_17_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_42_br_mask = ldq_uop_17_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_17_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_17_br_tag = ldq_uop_17_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_42_br_tag = ldq_uop_17_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_17_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_17_br_type = ldq_uop_17_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_42_br_type = ldq_uop_17_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sfb; // @[lsu.scala:219:36] wire l_uop_17_is_sfb = ldq_uop_17_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sfb = ldq_uop_17_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_fence; // @[lsu.scala:219:36] wire l_uop_17_is_fence = ldq_uop_17_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_fence = ldq_uop_17_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_fencei; // @[lsu.scala:219:36] wire l_uop_17_is_fencei = ldq_uop_17_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_fencei = ldq_uop_17_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sfence; // @[lsu.scala:219:36] wire l_uop_17_is_sfence = ldq_uop_17_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sfence = ldq_uop_17_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_amo; // @[lsu.scala:219:36] wire l_uop_17_is_amo = ldq_uop_17_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_amo = ldq_uop_17_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_eret; // @[lsu.scala:219:36] wire l_uop_17_is_eret = ldq_uop_17_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_eret = ldq_uop_17_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_17_is_sys_pc2epc = ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sys_pc2epc = ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_rocc; // @[lsu.scala:219:36] wire l_uop_17_is_rocc = ldq_uop_17_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_rocc = ldq_uop_17_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_mov; // @[lsu.scala:219:36] wire l_uop_17_is_mov = ldq_uop_17_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_mov = ldq_uop_17_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ftq_idx = ldq_uop_17_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ftq_idx = ldq_uop_17_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_edge_inst; // @[lsu.scala:219:36] wire l_uop_17_edge_inst = ldq_uop_17_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_42_edge_inst = ldq_uop_17_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_17_pc_lob = ldq_uop_17_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_pc_lob = ldq_uop_17_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_taken; // @[lsu.scala:219:36] wire l_uop_17_taken = ldq_uop_17_taken; // @[lsu.scala:219:36, :1191:37] wire uop_42_taken = ldq_uop_17_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_imm_rename; // @[lsu.scala:219:36] wire l_uop_17_imm_rename = ldq_uop_17_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_42_imm_rename = ldq_uop_17_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_imm_sel = ldq_uop_17_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_imm_sel = ldq_uop_17_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_17_pimm = ldq_uop_17_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_pimm = ldq_uop_17_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_17_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_17_imm_packed = ldq_uop_17_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_42_imm_packed = ldq_uop_17_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_17_op1_sel = ldq_uop_17_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_op1_sel = ldq_uop_17_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_op2_sel = ldq_uop_17_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_op2_sel = ldq_uop_17_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ldst = ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ldst = ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_wen = ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_wen = ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren1 = ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren1 = ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren2 = ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren2 = ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren3 = ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren3 = ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_swap12 = ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_swap12 = ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_swap23 = ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_swap23 = ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_ctrl_typeTagIn = ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_ctrl_typeTagIn = ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_ctrl_typeTagOut = ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_ctrl_typeTagOut = ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fromint = ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fromint = ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_toint = ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_toint = ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fastpipe = ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fastpipe = ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fma = ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fma = ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_div = ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_div = ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_sqrt = ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_sqrt = ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_wflags = ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_wflags = ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_vec = ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_vec = ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_17_rob_idx = ldq_uop_17_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_rob_idx = ldq_uop_17_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ldq_idx = ldq_uop_17_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ldq_idx = ldq_uop_17_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_stq_idx = ldq_uop_17_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_stq_idx = ldq_uop_17_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_17_rxq_idx = ldq_uop_17_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_rxq_idx = ldq_uop_17_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_17_pdst = ldq_uop_17_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_pdst = ldq_uop_17_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs1 = ldq_uop_17_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs1 = ldq_uop_17_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs2 = ldq_uop_17_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs2 = ldq_uop_17_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs3 = ldq_uop_17_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs3 = ldq_uop_17_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ppred = ldq_uop_17_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ppred = ldq_uop_17_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs1_busy; // @[lsu.scala:219:36] wire l_uop_17_prs1_busy = ldq_uop_17_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs1_busy = ldq_uop_17_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs2_busy; // @[lsu.scala:219:36] wire l_uop_17_prs2_busy = ldq_uop_17_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs2_busy = ldq_uop_17_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs3_busy; // @[lsu.scala:219:36] wire l_uop_17_prs3_busy = ldq_uop_17_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs3_busy = ldq_uop_17_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_ppred_busy; // @[lsu.scala:219:36] wire l_uop_17_ppred_busy = ldq_uop_17_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_ppred_busy = ldq_uop_17_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_17_stale_pdst = ldq_uop_17_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_stale_pdst = ldq_uop_17_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_exception; // @[lsu.scala:219:36] wire l_uop_17_exception = ldq_uop_17_exception; // @[lsu.scala:219:36, :1191:37] wire uop_42_exception = ldq_uop_17_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_17_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_17_exc_cause = ldq_uop_17_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_42_exc_cause = ldq_uop_17_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_17_mem_cmd = ldq_uop_17_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_mem_cmd = ldq_uop_17_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_17_mem_size = ldq_uop_17_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_mem_size = ldq_uop_17_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_mem_signed; // @[lsu.scala:219:36] wire l_uop_17_mem_signed = ldq_uop_17_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_42_mem_signed = ldq_uop_17_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_uses_ldq; // @[lsu.scala:219:36] wire l_uop_17_uses_ldq = ldq_uop_17_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_42_uses_ldq = ldq_uop_17_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_uses_stq; // @[lsu.scala:219:36] wire l_uop_17_uses_stq = ldq_uop_17_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_42_uses_stq = ldq_uop_17_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_unique; // @[lsu.scala:219:36] wire l_uop_17_is_unique = ldq_uop_17_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_unique = ldq_uop_17_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_17_flush_on_commit = ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_42_flush_on_commit = ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_17_csr_cmd = ldq_uop_17_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_csr_cmd = ldq_uop_17_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_17_ldst_is_rs1 = ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_42_ldst_is_rs1 = ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_17_ldst = ldq_uop_17_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_ldst = ldq_uop_17_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs1 = ldq_uop_17_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs1 = ldq_uop_17_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs2 = ldq_uop_17_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs2 = ldq_uop_17_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs3 = ldq_uop_17_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs3 = ldq_uop_17_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_dst_rtype = ldq_uop_17_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_dst_rtype = ldq_uop_17_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_lrs1_rtype = ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_lrs1_rtype = ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_lrs2_rtype = ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_lrs2_rtype = ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_frs3_en; // @[lsu.scala:219:36] wire l_uop_17_frs3_en = ldq_uop_17_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_42_frs3_en = ldq_uop_17_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fcn_dw; // @[lsu.scala:219:36] wire l_uop_17_fcn_dw = ldq_uop_17_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_42_fcn_dw = ldq_uop_17_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_17_fcn_op = ldq_uop_17_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_fcn_op = ldq_uop_17_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_val; // @[lsu.scala:219:36] wire l_uop_17_fp_val = ldq_uop_17_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_val = ldq_uop_17_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_17_fp_rm = ldq_uop_17_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_fp_rm = ldq_uop_17_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_typ = ldq_uop_17_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_typ = ldq_uop_17_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_pf_if = ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_pf_if = ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_ae_if = ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_ae_if = ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_ma_if = ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_ma_if = ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_17_bp_debug_if = ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_bp_debug_if = ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_17_bp_xcpt_if = ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_bp_xcpt_if = ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_17_debug_fsrc = ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_debug_fsrc = ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_17_debug_tsrc = ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_debug_tsrc = ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_18_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_18_inst = ldq_uop_18_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_43_inst = ldq_uop_18_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_18_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_18_debug_inst = ldq_uop_18_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_43_debug_inst = ldq_uop_18_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_rvc; // @[lsu.scala:219:36] wire l_uop_18_is_rvc = ldq_uop_18_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_rvc = ldq_uop_18_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_18_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_18_debug_pc = ldq_uop_18_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_43_debug_pc = ldq_uop_18_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_0; // @[lsu.scala:219:36] wire l_uop_18_iq_type_0 = ldq_uop_18_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_0 = ldq_uop_18_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_1; // @[lsu.scala:219:36] wire l_uop_18_iq_type_1 = ldq_uop_18_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_1 = ldq_uop_18_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_2; // @[lsu.scala:219:36] wire l_uop_18_iq_type_2 = ldq_uop_18_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_2 = ldq_uop_18_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_3; // @[lsu.scala:219:36] wire l_uop_18_iq_type_3 = ldq_uop_18_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_3 = ldq_uop_18_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_0; // @[lsu.scala:219:36] wire l_uop_18_fu_code_0 = ldq_uop_18_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_0 = ldq_uop_18_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_1; // @[lsu.scala:219:36] wire l_uop_18_fu_code_1 = ldq_uop_18_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_1 = ldq_uop_18_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_2; // @[lsu.scala:219:36] wire l_uop_18_fu_code_2 = ldq_uop_18_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_2 = ldq_uop_18_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_3; // @[lsu.scala:219:36] wire l_uop_18_fu_code_3 = ldq_uop_18_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_3 = ldq_uop_18_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_4; // @[lsu.scala:219:36] wire l_uop_18_fu_code_4 = ldq_uop_18_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_4 = ldq_uop_18_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_5; // @[lsu.scala:219:36] wire l_uop_18_fu_code_5 = ldq_uop_18_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_5 = ldq_uop_18_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_6; // @[lsu.scala:219:36] wire l_uop_18_fu_code_6 = ldq_uop_18_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_6 = ldq_uop_18_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_7; // @[lsu.scala:219:36] wire l_uop_18_fu_code_7 = ldq_uop_18_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_7 = ldq_uop_18_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_8; // @[lsu.scala:219:36] wire l_uop_18_fu_code_8 = ldq_uop_18_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_8 = ldq_uop_18_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_9; // @[lsu.scala:219:36] wire l_uop_18_fu_code_9 = ldq_uop_18_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_9 = ldq_uop_18_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued; // @[lsu.scala:219:36] wire l_uop_18_iw_issued = ldq_uop_18_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued = ldq_uop_18_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_18_iw_issued_partial_agen = ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued_partial_agen = ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_18_iw_issued_partial_dgen = ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued_partial_dgen = ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_18_iw_p1_speculative_child = ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_iw_p1_speculative_child = ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_18_iw_p2_speculative_child = ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_iw_p2_speculative_child = ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p1_bypass_hint = ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p1_bypass_hint = ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p2_bypass_hint = ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p2_bypass_hint = ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p3_bypass_hint = ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p3_bypass_hint = ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_dis_col_sel = ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_dis_col_sel = ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_18_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_18_br_mask = ldq_uop_18_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_43_br_mask = ldq_uop_18_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_18_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_18_br_tag = ldq_uop_18_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_43_br_tag = ldq_uop_18_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_18_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_18_br_type = ldq_uop_18_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_43_br_type = ldq_uop_18_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sfb; // @[lsu.scala:219:36] wire l_uop_18_is_sfb = ldq_uop_18_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sfb = ldq_uop_18_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_fence; // @[lsu.scala:219:36] wire l_uop_18_is_fence = ldq_uop_18_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_fence = ldq_uop_18_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_fencei; // @[lsu.scala:219:36] wire l_uop_18_is_fencei = ldq_uop_18_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_fencei = ldq_uop_18_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sfence; // @[lsu.scala:219:36] wire l_uop_18_is_sfence = ldq_uop_18_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sfence = ldq_uop_18_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_amo; // @[lsu.scala:219:36] wire l_uop_18_is_amo = ldq_uop_18_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_amo = ldq_uop_18_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_eret; // @[lsu.scala:219:36] wire l_uop_18_is_eret = ldq_uop_18_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_eret = ldq_uop_18_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_18_is_sys_pc2epc = ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sys_pc2epc = ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_rocc; // @[lsu.scala:219:36] wire l_uop_18_is_rocc = ldq_uop_18_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_rocc = ldq_uop_18_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_mov; // @[lsu.scala:219:36] wire l_uop_18_is_mov = ldq_uop_18_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_mov = ldq_uop_18_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ftq_idx = ldq_uop_18_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ftq_idx = ldq_uop_18_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_edge_inst; // @[lsu.scala:219:36] wire l_uop_18_edge_inst = ldq_uop_18_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_43_edge_inst = ldq_uop_18_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_18_pc_lob = ldq_uop_18_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_pc_lob = ldq_uop_18_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_taken; // @[lsu.scala:219:36] wire l_uop_18_taken = ldq_uop_18_taken; // @[lsu.scala:219:36, :1191:37] wire uop_43_taken = ldq_uop_18_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_imm_rename; // @[lsu.scala:219:36] wire l_uop_18_imm_rename = ldq_uop_18_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_43_imm_rename = ldq_uop_18_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_imm_sel = ldq_uop_18_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_imm_sel = ldq_uop_18_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_18_pimm = ldq_uop_18_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_pimm = ldq_uop_18_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_18_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_18_imm_packed = ldq_uop_18_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_43_imm_packed = ldq_uop_18_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_18_op1_sel = ldq_uop_18_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_op1_sel = ldq_uop_18_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_op2_sel = ldq_uop_18_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_op2_sel = ldq_uop_18_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ldst = ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ldst = ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_wen = ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_wen = ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren1 = ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren1 = ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren2 = ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren2 = ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren3 = ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren3 = ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_swap12 = ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_swap12 = ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_swap23 = ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_swap23 = ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_ctrl_typeTagIn = ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_ctrl_typeTagIn = ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_ctrl_typeTagOut = ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_ctrl_typeTagOut = ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fromint = ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fromint = ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_toint = ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_toint = ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fastpipe = ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fastpipe = ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fma = ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fma = ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_div = ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_div = ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_sqrt = ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_sqrt = ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_wflags = ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_wflags = ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_vec = ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_vec = ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_18_rob_idx = ldq_uop_18_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_rob_idx = ldq_uop_18_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ldq_idx = ldq_uop_18_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ldq_idx = ldq_uop_18_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_stq_idx = ldq_uop_18_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_stq_idx = ldq_uop_18_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_18_rxq_idx = ldq_uop_18_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_rxq_idx = ldq_uop_18_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_18_pdst = ldq_uop_18_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_pdst = ldq_uop_18_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs1 = ldq_uop_18_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs1 = ldq_uop_18_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs2 = ldq_uop_18_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs2 = ldq_uop_18_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs3 = ldq_uop_18_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs3 = ldq_uop_18_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ppred = ldq_uop_18_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ppred = ldq_uop_18_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs1_busy; // @[lsu.scala:219:36] wire l_uop_18_prs1_busy = ldq_uop_18_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs1_busy = ldq_uop_18_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs2_busy; // @[lsu.scala:219:36] wire l_uop_18_prs2_busy = ldq_uop_18_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs2_busy = ldq_uop_18_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs3_busy; // @[lsu.scala:219:36] wire l_uop_18_prs3_busy = ldq_uop_18_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs3_busy = ldq_uop_18_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_ppred_busy; // @[lsu.scala:219:36] wire l_uop_18_ppred_busy = ldq_uop_18_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_ppred_busy = ldq_uop_18_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_18_stale_pdst = ldq_uop_18_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_stale_pdst = ldq_uop_18_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_exception; // @[lsu.scala:219:36] wire l_uop_18_exception = ldq_uop_18_exception; // @[lsu.scala:219:36, :1191:37] wire uop_43_exception = ldq_uop_18_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_18_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_18_exc_cause = ldq_uop_18_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_43_exc_cause = ldq_uop_18_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_18_mem_cmd = ldq_uop_18_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_mem_cmd = ldq_uop_18_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_18_mem_size = ldq_uop_18_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_mem_size = ldq_uop_18_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_mem_signed; // @[lsu.scala:219:36] wire l_uop_18_mem_signed = ldq_uop_18_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_43_mem_signed = ldq_uop_18_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_uses_ldq; // @[lsu.scala:219:36] wire l_uop_18_uses_ldq = ldq_uop_18_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_43_uses_ldq = ldq_uop_18_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_uses_stq; // @[lsu.scala:219:36] wire l_uop_18_uses_stq = ldq_uop_18_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_43_uses_stq = ldq_uop_18_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_unique; // @[lsu.scala:219:36] wire l_uop_18_is_unique = ldq_uop_18_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_unique = ldq_uop_18_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_18_flush_on_commit = ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_43_flush_on_commit = ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_18_csr_cmd = ldq_uop_18_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_csr_cmd = ldq_uop_18_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_18_ldst_is_rs1 = ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_43_ldst_is_rs1 = ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_18_ldst = ldq_uop_18_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_ldst = ldq_uop_18_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs1 = ldq_uop_18_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs1 = ldq_uop_18_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs2 = ldq_uop_18_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs2 = ldq_uop_18_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs3 = ldq_uop_18_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs3 = ldq_uop_18_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_dst_rtype = ldq_uop_18_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_dst_rtype = ldq_uop_18_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_lrs1_rtype = ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_lrs1_rtype = ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_lrs2_rtype = ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_lrs2_rtype = ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_frs3_en; // @[lsu.scala:219:36] wire l_uop_18_frs3_en = ldq_uop_18_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_43_frs3_en = ldq_uop_18_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fcn_dw; // @[lsu.scala:219:36] wire l_uop_18_fcn_dw = ldq_uop_18_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_43_fcn_dw = ldq_uop_18_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_18_fcn_op = ldq_uop_18_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_fcn_op = ldq_uop_18_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_val; // @[lsu.scala:219:36] wire l_uop_18_fp_val = ldq_uop_18_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_val = ldq_uop_18_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_18_fp_rm = ldq_uop_18_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_fp_rm = ldq_uop_18_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_typ = ldq_uop_18_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_typ = ldq_uop_18_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_pf_if = ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_pf_if = ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_ae_if = ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_ae_if = ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_ma_if = ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_ma_if = ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_18_bp_debug_if = ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_bp_debug_if = ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_18_bp_xcpt_if = ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_bp_xcpt_if = ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_18_debug_fsrc = ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_debug_fsrc = ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_18_debug_tsrc = ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_debug_tsrc = ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_19_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_19_inst = ldq_uop_19_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_44_inst = ldq_uop_19_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_19_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_19_debug_inst = ldq_uop_19_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_44_debug_inst = ldq_uop_19_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_rvc; // @[lsu.scala:219:36] wire l_uop_19_is_rvc = ldq_uop_19_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_rvc = ldq_uop_19_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_19_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_19_debug_pc = ldq_uop_19_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_44_debug_pc = ldq_uop_19_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_0; // @[lsu.scala:219:36] wire l_uop_19_iq_type_0 = ldq_uop_19_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_0 = ldq_uop_19_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_1; // @[lsu.scala:219:36] wire l_uop_19_iq_type_1 = ldq_uop_19_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_1 = ldq_uop_19_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_2; // @[lsu.scala:219:36] wire l_uop_19_iq_type_2 = ldq_uop_19_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_2 = ldq_uop_19_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_3; // @[lsu.scala:219:36] wire l_uop_19_iq_type_3 = ldq_uop_19_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_3 = ldq_uop_19_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_0; // @[lsu.scala:219:36] wire l_uop_19_fu_code_0 = ldq_uop_19_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_0 = ldq_uop_19_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_1; // @[lsu.scala:219:36] wire l_uop_19_fu_code_1 = ldq_uop_19_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_1 = ldq_uop_19_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_2; // @[lsu.scala:219:36] wire l_uop_19_fu_code_2 = ldq_uop_19_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_2 = ldq_uop_19_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_3; // @[lsu.scala:219:36] wire l_uop_19_fu_code_3 = ldq_uop_19_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_3 = ldq_uop_19_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_4; // @[lsu.scala:219:36] wire l_uop_19_fu_code_4 = ldq_uop_19_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_4 = ldq_uop_19_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_5; // @[lsu.scala:219:36] wire l_uop_19_fu_code_5 = ldq_uop_19_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_5 = ldq_uop_19_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_6; // @[lsu.scala:219:36] wire l_uop_19_fu_code_6 = ldq_uop_19_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_6 = ldq_uop_19_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_7; // @[lsu.scala:219:36] wire l_uop_19_fu_code_7 = ldq_uop_19_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_7 = ldq_uop_19_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_8; // @[lsu.scala:219:36] wire l_uop_19_fu_code_8 = ldq_uop_19_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_8 = ldq_uop_19_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_9; // @[lsu.scala:219:36] wire l_uop_19_fu_code_9 = ldq_uop_19_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_9 = ldq_uop_19_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued; // @[lsu.scala:219:36] wire l_uop_19_iw_issued = ldq_uop_19_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued = ldq_uop_19_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_19_iw_issued_partial_agen = ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued_partial_agen = ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_19_iw_issued_partial_dgen = ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued_partial_dgen = ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_19_iw_p1_speculative_child = ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_iw_p1_speculative_child = ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_19_iw_p2_speculative_child = ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_iw_p2_speculative_child = ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p1_bypass_hint = ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p1_bypass_hint = ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p2_bypass_hint = ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p2_bypass_hint = ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p3_bypass_hint = ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p3_bypass_hint = ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_dis_col_sel = ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_dis_col_sel = ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_19_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_19_br_mask = ldq_uop_19_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_44_br_mask = ldq_uop_19_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_19_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_19_br_tag = ldq_uop_19_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_44_br_tag = ldq_uop_19_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_19_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_19_br_type = ldq_uop_19_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_44_br_type = ldq_uop_19_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sfb; // @[lsu.scala:219:36] wire l_uop_19_is_sfb = ldq_uop_19_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sfb = ldq_uop_19_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_fence; // @[lsu.scala:219:36] wire l_uop_19_is_fence = ldq_uop_19_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_fence = ldq_uop_19_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_fencei; // @[lsu.scala:219:36] wire l_uop_19_is_fencei = ldq_uop_19_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_fencei = ldq_uop_19_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sfence; // @[lsu.scala:219:36] wire l_uop_19_is_sfence = ldq_uop_19_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sfence = ldq_uop_19_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_amo; // @[lsu.scala:219:36] wire l_uop_19_is_amo = ldq_uop_19_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_amo = ldq_uop_19_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_eret; // @[lsu.scala:219:36] wire l_uop_19_is_eret = ldq_uop_19_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_eret = ldq_uop_19_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_19_is_sys_pc2epc = ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sys_pc2epc = ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_rocc; // @[lsu.scala:219:36] wire l_uop_19_is_rocc = ldq_uop_19_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_rocc = ldq_uop_19_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_mov; // @[lsu.scala:219:36] wire l_uop_19_is_mov = ldq_uop_19_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_mov = ldq_uop_19_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ftq_idx = ldq_uop_19_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ftq_idx = ldq_uop_19_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_edge_inst; // @[lsu.scala:219:36] wire l_uop_19_edge_inst = ldq_uop_19_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_44_edge_inst = ldq_uop_19_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_19_pc_lob = ldq_uop_19_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_pc_lob = ldq_uop_19_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_taken; // @[lsu.scala:219:36] wire l_uop_19_taken = ldq_uop_19_taken; // @[lsu.scala:219:36, :1191:37] wire uop_44_taken = ldq_uop_19_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_imm_rename; // @[lsu.scala:219:36] wire l_uop_19_imm_rename = ldq_uop_19_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_44_imm_rename = ldq_uop_19_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_imm_sel = ldq_uop_19_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_imm_sel = ldq_uop_19_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_19_pimm = ldq_uop_19_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_pimm = ldq_uop_19_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_19_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_19_imm_packed = ldq_uop_19_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_44_imm_packed = ldq_uop_19_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_19_op1_sel = ldq_uop_19_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_op1_sel = ldq_uop_19_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_op2_sel = ldq_uop_19_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_op2_sel = ldq_uop_19_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ldst = ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ldst = ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_wen = ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_wen = ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren1 = ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren1 = ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren2 = ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren2 = ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren3 = ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren3 = ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_swap12 = ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_swap12 = ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_swap23 = ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_swap23 = ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_ctrl_typeTagIn = ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_ctrl_typeTagIn = ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_ctrl_typeTagOut = ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_ctrl_typeTagOut = ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fromint = ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fromint = ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_toint = ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_toint = ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fastpipe = ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fastpipe = ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fma = ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fma = ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_div = ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_div = ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_sqrt = ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_sqrt = ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_wflags = ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_wflags = ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_vec = ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_vec = ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_19_rob_idx = ldq_uop_19_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_rob_idx = ldq_uop_19_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ldq_idx = ldq_uop_19_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ldq_idx = ldq_uop_19_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_stq_idx = ldq_uop_19_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_stq_idx = ldq_uop_19_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_19_rxq_idx = ldq_uop_19_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_rxq_idx = ldq_uop_19_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_19_pdst = ldq_uop_19_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_pdst = ldq_uop_19_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs1 = ldq_uop_19_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs1 = ldq_uop_19_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs2 = ldq_uop_19_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs2 = ldq_uop_19_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs3 = ldq_uop_19_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs3 = ldq_uop_19_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ppred = ldq_uop_19_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ppred = ldq_uop_19_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs1_busy; // @[lsu.scala:219:36] wire l_uop_19_prs1_busy = ldq_uop_19_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs1_busy = ldq_uop_19_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs2_busy; // @[lsu.scala:219:36] wire l_uop_19_prs2_busy = ldq_uop_19_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs2_busy = ldq_uop_19_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs3_busy; // @[lsu.scala:219:36] wire l_uop_19_prs3_busy = ldq_uop_19_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs3_busy = ldq_uop_19_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_ppred_busy; // @[lsu.scala:219:36] wire l_uop_19_ppred_busy = ldq_uop_19_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_ppred_busy = ldq_uop_19_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_19_stale_pdst = ldq_uop_19_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_stale_pdst = ldq_uop_19_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_exception; // @[lsu.scala:219:36] wire l_uop_19_exception = ldq_uop_19_exception; // @[lsu.scala:219:36, :1191:37] wire uop_44_exception = ldq_uop_19_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_19_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_19_exc_cause = ldq_uop_19_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_44_exc_cause = ldq_uop_19_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_19_mem_cmd = ldq_uop_19_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_mem_cmd = ldq_uop_19_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_19_mem_size = ldq_uop_19_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_mem_size = ldq_uop_19_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_mem_signed; // @[lsu.scala:219:36] wire l_uop_19_mem_signed = ldq_uop_19_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_44_mem_signed = ldq_uop_19_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_uses_ldq; // @[lsu.scala:219:36] wire l_uop_19_uses_ldq = ldq_uop_19_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_44_uses_ldq = ldq_uop_19_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_uses_stq; // @[lsu.scala:219:36] wire l_uop_19_uses_stq = ldq_uop_19_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_44_uses_stq = ldq_uop_19_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_unique; // @[lsu.scala:219:36] wire l_uop_19_is_unique = ldq_uop_19_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_unique = ldq_uop_19_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_19_flush_on_commit = ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_44_flush_on_commit = ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_19_csr_cmd = ldq_uop_19_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_csr_cmd = ldq_uop_19_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_19_ldst_is_rs1 = ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_44_ldst_is_rs1 = ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_19_ldst = ldq_uop_19_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_ldst = ldq_uop_19_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs1 = ldq_uop_19_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs1 = ldq_uop_19_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs2 = ldq_uop_19_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs2 = ldq_uop_19_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs3 = ldq_uop_19_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs3 = ldq_uop_19_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_dst_rtype = ldq_uop_19_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_dst_rtype = ldq_uop_19_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_lrs1_rtype = ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_lrs1_rtype = ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_lrs2_rtype = ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_lrs2_rtype = ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_frs3_en; // @[lsu.scala:219:36] wire l_uop_19_frs3_en = ldq_uop_19_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_44_frs3_en = ldq_uop_19_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fcn_dw; // @[lsu.scala:219:36] wire l_uop_19_fcn_dw = ldq_uop_19_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_44_fcn_dw = ldq_uop_19_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_19_fcn_op = ldq_uop_19_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_fcn_op = ldq_uop_19_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_val; // @[lsu.scala:219:36] wire l_uop_19_fp_val = ldq_uop_19_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_val = ldq_uop_19_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_19_fp_rm = ldq_uop_19_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_fp_rm = ldq_uop_19_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_typ = ldq_uop_19_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_typ = ldq_uop_19_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_pf_if = ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_pf_if = ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_ae_if = ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_ae_if = ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_ma_if = ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_ma_if = ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_19_bp_debug_if = ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_bp_debug_if = ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_19_bp_xcpt_if = ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_bp_xcpt_if = ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_19_debug_fsrc = ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_debug_fsrc = ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_19_debug_tsrc = ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_debug_tsrc = ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_20_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_20_inst = ldq_uop_20_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_45_inst = ldq_uop_20_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_20_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_20_debug_inst = ldq_uop_20_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_45_debug_inst = ldq_uop_20_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_rvc; // @[lsu.scala:219:36] wire l_uop_20_is_rvc = ldq_uop_20_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_rvc = ldq_uop_20_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_20_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_20_debug_pc = ldq_uop_20_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_45_debug_pc = ldq_uop_20_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_0; // @[lsu.scala:219:36] wire l_uop_20_iq_type_0 = ldq_uop_20_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_0 = ldq_uop_20_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_1; // @[lsu.scala:219:36] wire l_uop_20_iq_type_1 = ldq_uop_20_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_1 = ldq_uop_20_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_2; // @[lsu.scala:219:36] wire l_uop_20_iq_type_2 = ldq_uop_20_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_2 = ldq_uop_20_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_3; // @[lsu.scala:219:36] wire l_uop_20_iq_type_3 = ldq_uop_20_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_3 = ldq_uop_20_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_0; // @[lsu.scala:219:36] wire l_uop_20_fu_code_0 = ldq_uop_20_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_0 = ldq_uop_20_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_1; // @[lsu.scala:219:36] wire l_uop_20_fu_code_1 = ldq_uop_20_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_1 = ldq_uop_20_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_2; // @[lsu.scala:219:36] wire l_uop_20_fu_code_2 = ldq_uop_20_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_2 = ldq_uop_20_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_3; // @[lsu.scala:219:36] wire l_uop_20_fu_code_3 = ldq_uop_20_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_3 = ldq_uop_20_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_4; // @[lsu.scala:219:36] wire l_uop_20_fu_code_4 = ldq_uop_20_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_4 = ldq_uop_20_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_5; // @[lsu.scala:219:36] wire l_uop_20_fu_code_5 = ldq_uop_20_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_5 = ldq_uop_20_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_6; // @[lsu.scala:219:36] wire l_uop_20_fu_code_6 = ldq_uop_20_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_6 = ldq_uop_20_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_7; // @[lsu.scala:219:36] wire l_uop_20_fu_code_7 = ldq_uop_20_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_7 = ldq_uop_20_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_8; // @[lsu.scala:219:36] wire l_uop_20_fu_code_8 = ldq_uop_20_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_8 = ldq_uop_20_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_9; // @[lsu.scala:219:36] wire l_uop_20_fu_code_9 = ldq_uop_20_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_9 = ldq_uop_20_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued; // @[lsu.scala:219:36] wire l_uop_20_iw_issued = ldq_uop_20_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued = ldq_uop_20_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_20_iw_issued_partial_agen = ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued_partial_agen = ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_20_iw_issued_partial_dgen = ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued_partial_dgen = ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_20_iw_p1_speculative_child = ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_iw_p1_speculative_child = ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_20_iw_p2_speculative_child = ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_iw_p2_speculative_child = ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p1_bypass_hint = ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p1_bypass_hint = ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p2_bypass_hint = ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p2_bypass_hint = ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p3_bypass_hint = ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p3_bypass_hint = ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_dis_col_sel = ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_dis_col_sel = ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_20_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_20_br_mask = ldq_uop_20_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_45_br_mask = ldq_uop_20_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_20_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_20_br_tag = ldq_uop_20_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_45_br_tag = ldq_uop_20_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_20_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_20_br_type = ldq_uop_20_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_45_br_type = ldq_uop_20_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sfb; // @[lsu.scala:219:36] wire l_uop_20_is_sfb = ldq_uop_20_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sfb = ldq_uop_20_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_fence; // @[lsu.scala:219:36] wire l_uop_20_is_fence = ldq_uop_20_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_fence = ldq_uop_20_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_fencei; // @[lsu.scala:219:36] wire l_uop_20_is_fencei = ldq_uop_20_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_fencei = ldq_uop_20_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sfence; // @[lsu.scala:219:36] wire l_uop_20_is_sfence = ldq_uop_20_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sfence = ldq_uop_20_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_amo; // @[lsu.scala:219:36] wire l_uop_20_is_amo = ldq_uop_20_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_amo = ldq_uop_20_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_eret; // @[lsu.scala:219:36] wire l_uop_20_is_eret = ldq_uop_20_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_eret = ldq_uop_20_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_20_is_sys_pc2epc = ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sys_pc2epc = ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_rocc; // @[lsu.scala:219:36] wire l_uop_20_is_rocc = ldq_uop_20_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_rocc = ldq_uop_20_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_mov; // @[lsu.scala:219:36] wire l_uop_20_is_mov = ldq_uop_20_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_mov = ldq_uop_20_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ftq_idx = ldq_uop_20_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ftq_idx = ldq_uop_20_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_edge_inst; // @[lsu.scala:219:36] wire l_uop_20_edge_inst = ldq_uop_20_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_45_edge_inst = ldq_uop_20_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_20_pc_lob = ldq_uop_20_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_pc_lob = ldq_uop_20_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_taken; // @[lsu.scala:219:36] wire l_uop_20_taken = ldq_uop_20_taken; // @[lsu.scala:219:36, :1191:37] wire uop_45_taken = ldq_uop_20_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_imm_rename; // @[lsu.scala:219:36] wire l_uop_20_imm_rename = ldq_uop_20_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_45_imm_rename = ldq_uop_20_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_imm_sel = ldq_uop_20_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_imm_sel = ldq_uop_20_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_20_pimm = ldq_uop_20_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_pimm = ldq_uop_20_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_20_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_20_imm_packed = ldq_uop_20_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_45_imm_packed = ldq_uop_20_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_20_op1_sel = ldq_uop_20_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_op1_sel = ldq_uop_20_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_op2_sel = ldq_uop_20_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_op2_sel = ldq_uop_20_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ldst = ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ldst = ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_wen = ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_wen = ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren1 = ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren1 = ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren2 = ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren2 = ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren3 = ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren3 = ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_swap12 = ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_swap12 = ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_swap23 = ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_swap23 = ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_ctrl_typeTagIn = ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_ctrl_typeTagIn = ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_ctrl_typeTagOut = ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_ctrl_typeTagOut = ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fromint = ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fromint = ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_toint = ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_toint = ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fastpipe = ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fastpipe = ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fma = ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fma = ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_div = ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_div = ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_sqrt = ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_sqrt = ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_wflags = ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_wflags = ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_vec = ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_vec = ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_20_rob_idx = ldq_uop_20_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_rob_idx = ldq_uop_20_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ldq_idx = ldq_uop_20_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ldq_idx = ldq_uop_20_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_stq_idx = ldq_uop_20_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_stq_idx = ldq_uop_20_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_20_rxq_idx = ldq_uop_20_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_rxq_idx = ldq_uop_20_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_20_pdst = ldq_uop_20_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_pdst = ldq_uop_20_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs1 = ldq_uop_20_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs1 = ldq_uop_20_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs2 = ldq_uop_20_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs2 = ldq_uop_20_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs3 = ldq_uop_20_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs3 = ldq_uop_20_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ppred = ldq_uop_20_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ppred = ldq_uop_20_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs1_busy; // @[lsu.scala:219:36] wire l_uop_20_prs1_busy = ldq_uop_20_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs1_busy = ldq_uop_20_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs2_busy; // @[lsu.scala:219:36] wire l_uop_20_prs2_busy = ldq_uop_20_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs2_busy = ldq_uop_20_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs3_busy; // @[lsu.scala:219:36] wire l_uop_20_prs3_busy = ldq_uop_20_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs3_busy = ldq_uop_20_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_ppred_busy; // @[lsu.scala:219:36] wire l_uop_20_ppred_busy = ldq_uop_20_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_ppred_busy = ldq_uop_20_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_20_stale_pdst = ldq_uop_20_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_stale_pdst = ldq_uop_20_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_exception; // @[lsu.scala:219:36] wire l_uop_20_exception = ldq_uop_20_exception; // @[lsu.scala:219:36, :1191:37] wire uop_45_exception = ldq_uop_20_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_20_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_20_exc_cause = ldq_uop_20_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_45_exc_cause = ldq_uop_20_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_20_mem_cmd = ldq_uop_20_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_mem_cmd = ldq_uop_20_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_20_mem_size = ldq_uop_20_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_mem_size = ldq_uop_20_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_mem_signed; // @[lsu.scala:219:36] wire l_uop_20_mem_signed = ldq_uop_20_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_45_mem_signed = ldq_uop_20_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_uses_ldq; // @[lsu.scala:219:36] wire l_uop_20_uses_ldq = ldq_uop_20_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_45_uses_ldq = ldq_uop_20_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_uses_stq; // @[lsu.scala:219:36] wire l_uop_20_uses_stq = ldq_uop_20_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_45_uses_stq = ldq_uop_20_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_unique; // @[lsu.scala:219:36] wire l_uop_20_is_unique = ldq_uop_20_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_unique = ldq_uop_20_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_20_flush_on_commit = ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_45_flush_on_commit = ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_20_csr_cmd = ldq_uop_20_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_csr_cmd = ldq_uop_20_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_20_ldst_is_rs1 = ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_45_ldst_is_rs1 = ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_20_ldst = ldq_uop_20_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_ldst = ldq_uop_20_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs1 = ldq_uop_20_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs1 = ldq_uop_20_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs2 = ldq_uop_20_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs2 = ldq_uop_20_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs3 = ldq_uop_20_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs3 = ldq_uop_20_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_dst_rtype = ldq_uop_20_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_dst_rtype = ldq_uop_20_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_lrs1_rtype = ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_lrs1_rtype = ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_lrs2_rtype = ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_lrs2_rtype = ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_frs3_en; // @[lsu.scala:219:36] wire l_uop_20_frs3_en = ldq_uop_20_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_45_frs3_en = ldq_uop_20_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fcn_dw; // @[lsu.scala:219:36] wire l_uop_20_fcn_dw = ldq_uop_20_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_45_fcn_dw = ldq_uop_20_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_20_fcn_op = ldq_uop_20_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_fcn_op = ldq_uop_20_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_val; // @[lsu.scala:219:36] wire l_uop_20_fp_val = ldq_uop_20_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_val = ldq_uop_20_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_20_fp_rm = ldq_uop_20_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_fp_rm = ldq_uop_20_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_typ = ldq_uop_20_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_typ = ldq_uop_20_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_pf_if = ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_pf_if = ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_ae_if = ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_ae_if = ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_ma_if = ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_ma_if = ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_20_bp_debug_if = ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_bp_debug_if = ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_20_bp_xcpt_if = ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_bp_xcpt_if = ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_20_debug_fsrc = ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_debug_fsrc = ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_20_debug_tsrc = ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_debug_tsrc = ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_21_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_21_inst = ldq_uop_21_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_46_inst = ldq_uop_21_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_21_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_21_debug_inst = ldq_uop_21_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_46_debug_inst = ldq_uop_21_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_rvc; // @[lsu.scala:219:36] wire l_uop_21_is_rvc = ldq_uop_21_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_rvc = ldq_uop_21_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_21_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_21_debug_pc = ldq_uop_21_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_46_debug_pc = ldq_uop_21_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_0; // @[lsu.scala:219:36] wire l_uop_21_iq_type_0 = ldq_uop_21_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_0 = ldq_uop_21_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_1; // @[lsu.scala:219:36] wire l_uop_21_iq_type_1 = ldq_uop_21_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_1 = ldq_uop_21_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_2; // @[lsu.scala:219:36] wire l_uop_21_iq_type_2 = ldq_uop_21_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_2 = ldq_uop_21_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_3; // @[lsu.scala:219:36] wire l_uop_21_iq_type_3 = ldq_uop_21_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_3 = ldq_uop_21_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_0; // @[lsu.scala:219:36] wire l_uop_21_fu_code_0 = ldq_uop_21_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_0 = ldq_uop_21_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_1; // @[lsu.scala:219:36] wire l_uop_21_fu_code_1 = ldq_uop_21_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_1 = ldq_uop_21_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_2; // @[lsu.scala:219:36] wire l_uop_21_fu_code_2 = ldq_uop_21_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_2 = ldq_uop_21_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_3; // @[lsu.scala:219:36] wire l_uop_21_fu_code_3 = ldq_uop_21_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_3 = ldq_uop_21_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_4; // @[lsu.scala:219:36] wire l_uop_21_fu_code_4 = ldq_uop_21_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_4 = ldq_uop_21_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_5; // @[lsu.scala:219:36] wire l_uop_21_fu_code_5 = ldq_uop_21_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_5 = ldq_uop_21_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_6; // @[lsu.scala:219:36] wire l_uop_21_fu_code_6 = ldq_uop_21_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_6 = ldq_uop_21_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_7; // @[lsu.scala:219:36] wire l_uop_21_fu_code_7 = ldq_uop_21_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_7 = ldq_uop_21_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_8; // @[lsu.scala:219:36] wire l_uop_21_fu_code_8 = ldq_uop_21_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_8 = ldq_uop_21_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_9; // @[lsu.scala:219:36] wire l_uop_21_fu_code_9 = ldq_uop_21_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_9 = ldq_uop_21_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued; // @[lsu.scala:219:36] wire l_uop_21_iw_issued = ldq_uop_21_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued = ldq_uop_21_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_21_iw_issued_partial_agen = ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued_partial_agen = ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_21_iw_issued_partial_dgen = ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued_partial_dgen = ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_21_iw_p1_speculative_child = ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_iw_p1_speculative_child = ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_21_iw_p2_speculative_child = ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_iw_p2_speculative_child = ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p1_bypass_hint = ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p1_bypass_hint = ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p2_bypass_hint = ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p2_bypass_hint = ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p3_bypass_hint = ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p3_bypass_hint = ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_dis_col_sel = ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_dis_col_sel = ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_21_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_21_br_mask = ldq_uop_21_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_46_br_mask = ldq_uop_21_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_21_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_21_br_tag = ldq_uop_21_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_46_br_tag = ldq_uop_21_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_21_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_21_br_type = ldq_uop_21_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_46_br_type = ldq_uop_21_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sfb; // @[lsu.scala:219:36] wire l_uop_21_is_sfb = ldq_uop_21_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sfb = ldq_uop_21_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_fence; // @[lsu.scala:219:36] wire l_uop_21_is_fence = ldq_uop_21_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_fence = ldq_uop_21_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_fencei; // @[lsu.scala:219:36] wire l_uop_21_is_fencei = ldq_uop_21_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_fencei = ldq_uop_21_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sfence; // @[lsu.scala:219:36] wire l_uop_21_is_sfence = ldq_uop_21_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sfence = ldq_uop_21_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_amo; // @[lsu.scala:219:36] wire l_uop_21_is_amo = ldq_uop_21_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_amo = ldq_uop_21_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_eret; // @[lsu.scala:219:36] wire l_uop_21_is_eret = ldq_uop_21_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_eret = ldq_uop_21_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_21_is_sys_pc2epc = ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sys_pc2epc = ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_rocc; // @[lsu.scala:219:36] wire l_uop_21_is_rocc = ldq_uop_21_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_rocc = ldq_uop_21_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_mov; // @[lsu.scala:219:36] wire l_uop_21_is_mov = ldq_uop_21_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_mov = ldq_uop_21_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ftq_idx = ldq_uop_21_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ftq_idx = ldq_uop_21_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_edge_inst; // @[lsu.scala:219:36] wire l_uop_21_edge_inst = ldq_uop_21_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_46_edge_inst = ldq_uop_21_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_21_pc_lob = ldq_uop_21_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_pc_lob = ldq_uop_21_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_taken; // @[lsu.scala:219:36] wire l_uop_21_taken = ldq_uop_21_taken; // @[lsu.scala:219:36, :1191:37] wire uop_46_taken = ldq_uop_21_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_imm_rename; // @[lsu.scala:219:36] wire l_uop_21_imm_rename = ldq_uop_21_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_46_imm_rename = ldq_uop_21_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_imm_sel = ldq_uop_21_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_imm_sel = ldq_uop_21_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_21_pimm = ldq_uop_21_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_pimm = ldq_uop_21_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_21_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_21_imm_packed = ldq_uop_21_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_46_imm_packed = ldq_uop_21_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_21_op1_sel = ldq_uop_21_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_op1_sel = ldq_uop_21_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_op2_sel = ldq_uop_21_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_op2_sel = ldq_uop_21_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ldst = ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ldst = ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_wen = ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_wen = ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren1 = ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren1 = ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren2 = ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren2 = ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren3 = ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren3 = ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_swap12 = ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_swap12 = ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_swap23 = ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_swap23 = ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_ctrl_typeTagIn = ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_ctrl_typeTagIn = ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_ctrl_typeTagOut = ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_ctrl_typeTagOut = ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fromint = ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fromint = ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_toint = ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_toint = ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fastpipe = ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fastpipe = ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fma = ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fma = ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_div = ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_div = ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_sqrt = ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_sqrt = ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_wflags = ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_wflags = ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_vec = ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_vec = ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_21_rob_idx = ldq_uop_21_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_rob_idx = ldq_uop_21_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ldq_idx = ldq_uop_21_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ldq_idx = ldq_uop_21_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_stq_idx = ldq_uop_21_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_stq_idx = ldq_uop_21_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_21_rxq_idx = ldq_uop_21_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_rxq_idx = ldq_uop_21_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_21_pdst = ldq_uop_21_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_pdst = ldq_uop_21_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs1 = ldq_uop_21_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs1 = ldq_uop_21_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs2 = ldq_uop_21_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs2 = ldq_uop_21_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs3 = ldq_uop_21_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs3 = ldq_uop_21_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ppred = ldq_uop_21_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ppred = ldq_uop_21_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs1_busy; // @[lsu.scala:219:36] wire l_uop_21_prs1_busy = ldq_uop_21_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs1_busy = ldq_uop_21_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs2_busy; // @[lsu.scala:219:36] wire l_uop_21_prs2_busy = ldq_uop_21_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs2_busy = ldq_uop_21_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs3_busy; // @[lsu.scala:219:36] wire l_uop_21_prs3_busy = ldq_uop_21_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs3_busy = ldq_uop_21_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_ppred_busy; // @[lsu.scala:219:36] wire l_uop_21_ppred_busy = ldq_uop_21_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_ppred_busy = ldq_uop_21_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_21_stale_pdst = ldq_uop_21_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_stale_pdst = ldq_uop_21_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_exception; // @[lsu.scala:219:36] wire l_uop_21_exception = ldq_uop_21_exception; // @[lsu.scala:219:36, :1191:37] wire uop_46_exception = ldq_uop_21_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_21_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_21_exc_cause = ldq_uop_21_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_46_exc_cause = ldq_uop_21_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_21_mem_cmd = ldq_uop_21_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_mem_cmd = ldq_uop_21_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_21_mem_size = ldq_uop_21_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_mem_size = ldq_uop_21_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_mem_signed; // @[lsu.scala:219:36] wire l_uop_21_mem_signed = ldq_uop_21_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_46_mem_signed = ldq_uop_21_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_uses_ldq; // @[lsu.scala:219:36] wire l_uop_21_uses_ldq = ldq_uop_21_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_46_uses_ldq = ldq_uop_21_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_uses_stq; // @[lsu.scala:219:36] wire l_uop_21_uses_stq = ldq_uop_21_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_46_uses_stq = ldq_uop_21_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_unique; // @[lsu.scala:219:36] wire l_uop_21_is_unique = ldq_uop_21_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_unique = ldq_uop_21_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_21_flush_on_commit = ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_46_flush_on_commit = ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_21_csr_cmd = ldq_uop_21_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_csr_cmd = ldq_uop_21_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_21_ldst_is_rs1 = ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_46_ldst_is_rs1 = ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_21_ldst = ldq_uop_21_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_ldst = ldq_uop_21_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs1 = ldq_uop_21_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs1 = ldq_uop_21_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs2 = ldq_uop_21_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs2 = ldq_uop_21_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs3 = ldq_uop_21_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs3 = ldq_uop_21_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_dst_rtype = ldq_uop_21_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_dst_rtype = ldq_uop_21_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_lrs1_rtype = ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_lrs1_rtype = ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_lrs2_rtype = ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_lrs2_rtype = ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_frs3_en; // @[lsu.scala:219:36] wire l_uop_21_frs3_en = ldq_uop_21_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_46_frs3_en = ldq_uop_21_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fcn_dw; // @[lsu.scala:219:36] wire l_uop_21_fcn_dw = ldq_uop_21_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_46_fcn_dw = ldq_uop_21_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_21_fcn_op = ldq_uop_21_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_fcn_op = ldq_uop_21_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_val; // @[lsu.scala:219:36] wire l_uop_21_fp_val = ldq_uop_21_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_val = ldq_uop_21_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_21_fp_rm = ldq_uop_21_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_fp_rm = ldq_uop_21_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_typ = ldq_uop_21_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_typ = ldq_uop_21_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_pf_if = ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_pf_if = ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_ae_if = ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_ae_if = ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_ma_if = ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_ma_if = ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_21_bp_debug_if = ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_bp_debug_if = ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_21_bp_xcpt_if = ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_bp_xcpt_if = ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_21_debug_fsrc = ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_debug_fsrc = ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_21_debug_tsrc = ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_debug_tsrc = ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_22_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_22_inst = ldq_uop_22_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_47_inst = ldq_uop_22_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_22_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_22_debug_inst = ldq_uop_22_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_47_debug_inst = ldq_uop_22_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_rvc; // @[lsu.scala:219:36] wire l_uop_22_is_rvc = ldq_uop_22_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_rvc = ldq_uop_22_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_22_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_22_debug_pc = ldq_uop_22_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_47_debug_pc = ldq_uop_22_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_0; // @[lsu.scala:219:36] wire l_uop_22_iq_type_0 = ldq_uop_22_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_0 = ldq_uop_22_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_1; // @[lsu.scala:219:36] wire l_uop_22_iq_type_1 = ldq_uop_22_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_1 = ldq_uop_22_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_2; // @[lsu.scala:219:36] wire l_uop_22_iq_type_2 = ldq_uop_22_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_2 = ldq_uop_22_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_3; // @[lsu.scala:219:36] wire l_uop_22_iq_type_3 = ldq_uop_22_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_3 = ldq_uop_22_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_0; // @[lsu.scala:219:36] wire l_uop_22_fu_code_0 = ldq_uop_22_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_0 = ldq_uop_22_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_1; // @[lsu.scala:219:36] wire l_uop_22_fu_code_1 = ldq_uop_22_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_1 = ldq_uop_22_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_2; // @[lsu.scala:219:36] wire l_uop_22_fu_code_2 = ldq_uop_22_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_2 = ldq_uop_22_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_3; // @[lsu.scala:219:36] wire l_uop_22_fu_code_3 = ldq_uop_22_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_3 = ldq_uop_22_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_4; // @[lsu.scala:219:36] wire l_uop_22_fu_code_4 = ldq_uop_22_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_4 = ldq_uop_22_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_5; // @[lsu.scala:219:36] wire l_uop_22_fu_code_5 = ldq_uop_22_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_5 = ldq_uop_22_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_6; // @[lsu.scala:219:36] wire l_uop_22_fu_code_6 = ldq_uop_22_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_6 = ldq_uop_22_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_7; // @[lsu.scala:219:36] wire l_uop_22_fu_code_7 = ldq_uop_22_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_7 = ldq_uop_22_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_8; // @[lsu.scala:219:36] wire l_uop_22_fu_code_8 = ldq_uop_22_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_8 = ldq_uop_22_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_9; // @[lsu.scala:219:36] wire l_uop_22_fu_code_9 = ldq_uop_22_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_9 = ldq_uop_22_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued; // @[lsu.scala:219:36] wire l_uop_22_iw_issued = ldq_uop_22_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued = ldq_uop_22_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_22_iw_issued_partial_agen = ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued_partial_agen = ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_22_iw_issued_partial_dgen = ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued_partial_dgen = ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_22_iw_p1_speculative_child = ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_iw_p1_speculative_child = ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_22_iw_p2_speculative_child = ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_iw_p2_speculative_child = ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p1_bypass_hint = ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p1_bypass_hint = ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p2_bypass_hint = ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p2_bypass_hint = ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p3_bypass_hint = ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p3_bypass_hint = ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_dis_col_sel = ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_dis_col_sel = ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_22_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_22_br_mask = ldq_uop_22_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_47_br_mask = ldq_uop_22_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_22_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_22_br_tag = ldq_uop_22_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_47_br_tag = ldq_uop_22_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_22_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_22_br_type = ldq_uop_22_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_47_br_type = ldq_uop_22_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sfb; // @[lsu.scala:219:36] wire l_uop_22_is_sfb = ldq_uop_22_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sfb = ldq_uop_22_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_fence; // @[lsu.scala:219:36] wire l_uop_22_is_fence = ldq_uop_22_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_fence = ldq_uop_22_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_fencei; // @[lsu.scala:219:36] wire l_uop_22_is_fencei = ldq_uop_22_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_fencei = ldq_uop_22_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sfence; // @[lsu.scala:219:36] wire l_uop_22_is_sfence = ldq_uop_22_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sfence = ldq_uop_22_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_amo; // @[lsu.scala:219:36] wire l_uop_22_is_amo = ldq_uop_22_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_amo = ldq_uop_22_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_eret; // @[lsu.scala:219:36] wire l_uop_22_is_eret = ldq_uop_22_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_eret = ldq_uop_22_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_22_is_sys_pc2epc = ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sys_pc2epc = ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_rocc; // @[lsu.scala:219:36] wire l_uop_22_is_rocc = ldq_uop_22_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_rocc = ldq_uop_22_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_mov; // @[lsu.scala:219:36] wire l_uop_22_is_mov = ldq_uop_22_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_mov = ldq_uop_22_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ftq_idx = ldq_uop_22_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ftq_idx = ldq_uop_22_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_edge_inst; // @[lsu.scala:219:36] wire l_uop_22_edge_inst = ldq_uop_22_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_47_edge_inst = ldq_uop_22_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_22_pc_lob = ldq_uop_22_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_pc_lob = ldq_uop_22_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_taken; // @[lsu.scala:219:36] wire l_uop_22_taken = ldq_uop_22_taken; // @[lsu.scala:219:36, :1191:37] wire uop_47_taken = ldq_uop_22_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_imm_rename; // @[lsu.scala:219:36] wire l_uop_22_imm_rename = ldq_uop_22_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_47_imm_rename = ldq_uop_22_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_imm_sel = ldq_uop_22_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_imm_sel = ldq_uop_22_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_22_pimm = ldq_uop_22_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_pimm = ldq_uop_22_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_22_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_22_imm_packed = ldq_uop_22_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_47_imm_packed = ldq_uop_22_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_22_op1_sel = ldq_uop_22_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_op1_sel = ldq_uop_22_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_op2_sel = ldq_uop_22_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_op2_sel = ldq_uop_22_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ldst = ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ldst = ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_wen = ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_wen = ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren1 = ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren1 = ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren2 = ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren2 = ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren3 = ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren3 = ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_swap12 = ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_swap12 = ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_swap23 = ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_swap23 = ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_ctrl_typeTagIn = ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_ctrl_typeTagIn = ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_ctrl_typeTagOut = ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_ctrl_typeTagOut = ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fromint = ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fromint = ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_toint = ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_toint = ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fastpipe = ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fastpipe = ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fma = ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fma = ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_div = ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_div = ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_sqrt = ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_sqrt = ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_wflags = ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_wflags = ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_vec = ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_vec = ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_22_rob_idx = ldq_uop_22_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_rob_idx = ldq_uop_22_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ldq_idx = ldq_uop_22_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ldq_idx = ldq_uop_22_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_stq_idx = ldq_uop_22_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_stq_idx = ldq_uop_22_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_22_rxq_idx = ldq_uop_22_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_rxq_idx = ldq_uop_22_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_22_pdst = ldq_uop_22_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_pdst = ldq_uop_22_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs1 = ldq_uop_22_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs1 = ldq_uop_22_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs2 = ldq_uop_22_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs2 = ldq_uop_22_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs3 = ldq_uop_22_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs3 = ldq_uop_22_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ppred = ldq_uop_22_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ppred = ldq_uop_22_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs1_busy; // @[lsu.scala:219:36] wire l_uop_22_prs1_busy = ldq_uop_22_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs1_busy = ldq_uop_22_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs2_busy; // @[lsu.scala:219:36] wire l_uop_22_prs2_busy = ldq_uop_22_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs2_busy = ldq_uop_22_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs3_busy; // @[lsu.scala:219:36] wire l_uop_22_prs3_busy = ldq_uop_22_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs3_busy = ldq_uop_22_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_ppred_busy; // @[lsu.scala:219:36] wire l_uop_22_ppred_busy = ldq_uop_22_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_ppred_busy = ldq_uop_22_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_22_stale_pdst = ldq_uop_22_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_stale_pdst = ldq_uop_22_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_exception; // @[lsu.scala:219:36] wire l_uop_22_exception = ldq_uop_22_exception; // @[lsu.scala:219:36, :1191:37] wire uop_47_exception = ldq_uop_22_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_22_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_22_exc_cause = ldq_uop_22_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_47_exc_cause = ldq_uop_22_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_22_mem_cmd = ldq_uop_22_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_mem_cmd = ldq_uop_22_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_22_mem_size = ldq_uop_22_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_mem_size = ldq_uop_22_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_mem_signed; // @[lsu.scala:219:36] wire l_uop_22_mem_signed = ldq_uop_22_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_47_mem_signed = ldq_uop_22_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_uses_ldq; // @[lsu.scala:219:36] wire l_uop_22_uses_ldq = ldq_uop_22_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_47_uses_ldq = ldq_uop_22_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_uses_stq; // @[lsu.scala:219:36] wire l_uop_22_uses_stq = ldq_uop_22_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_47_uses_stq = ldq_uop_22_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_unique; // @[lsu.scala:219:36] wire l_uop_22_is_unique = ldq_uop_22_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_unique = ldq_uop_22_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_22_flush_on_commit = ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_47_flush_on_commit = ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_22_csr_cmd = ldq_uop_22_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_csr_cmd = ldq_uop_22_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_22_ldst_is_rs1 = ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_47_ldst_is_rs1 = ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_22_ldst = ldq_uop_22_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_ldst = ldq_uop_22_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs1 = ldq_uop_22_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs1 = ldq_uop_22_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs2 = ldq_uop_22_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs2 = ldq_uop_22_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs3 = ldq_uop_22_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs3 = ldq_uop_22_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_dst_rtype = ldq_uop_22_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_dst_rtype = ldq_uop_22_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_lrs1_rtype = ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_lrs1_rtype = ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_lrs2_rtype = ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_lrs2_rtype = ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_frs3_en; // @[lsu.scala:219:36] wire l_uop_22_frs3_en = ldq_uop_22_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_47_frs3_en = ldq_uop_22_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fcn_dw; // @[lsu.scala:219:36] wire l_uop_22_fcn_dw = ldq_uop_22_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_47_fcn_dw = ldq_uop_22_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_22_fcn_op = ldq_uop_22_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_fcn_op = ldq_uop_22_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_val; // @[lsu.scala:219:36] wire l_uop_22_fp_val = ldq_uop_22_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_val = ldq_uop_22_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_22_fp_rm = ldq_uop_22_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_fp_rm = ldq_uop_22_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_typ = ldq_uop_22_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_typ = ldq_uop_22_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_pf_if = ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_pf_if = ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_ae_if = ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_ae_if = ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_ma_if = ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_ma_if = ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_22_bp_debug_if = ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_bp_debug_if = ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_22_bp_xcpt_if = ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_bp_xcpt_if = ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_22_debug_fsrc = ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_debug_fsrc = ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_22_debug_tsrc = ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_debug_tsrc = ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_23_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_23_inst = ldq_uop_23_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_48_inst = ldq_uop_23_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_23_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_23_debug_inst = ldq_uop_23_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_48_debug_inst = ldq_uop_23_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_rvc; // @[lsu.scala:219:36] wire l_uop_23_is_rvc = ldq_uop_23_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_rvc = ldq_uop_23_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_23_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_23_debug_pc = ldq_uop_23_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_48_debug_pc = ldq_uop_23_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_0; // @[lsu.scala:219:36] wire l_uop_23_iq_type_0 = ldq_uop_23_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_0 = ldq_uop_23_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_1; // @[lsu.scala:219:36] wire l_uop_23_iq_type_1 = ldq_uop_23_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_1 = ldq_uop_23_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_2; // @[lsu.scala:219:36] wire l_uop_23_iq_type_2 = ldq_uop_23_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_2 = ldq_uop_23_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_3; // @[lsu.scala:219:36] wire l_uop_23_iq_type_3 = ldq_uop_23_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_3 = ldq_uop_23_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_0; // @[lsu.scala:219:36] wire l_uop_23_fu_code_0 = ldq_uop_23_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_0 = ldq_uop_23_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_1; // @[lsu.scala:219:36] wire l_uop_23_fu_code_1 = ldq_uop_23_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_1 = ldq_uop_23_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_2; // @[lsu.scala:219:36] wire l_uop_23_fu_code_2 = ldq_uop_23_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_2 = ldq_uop_23_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_3; // @[lsu.scala:219:36] wire l_uop_23_fu_code_3 = ldq_uop_23_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_3 = ldq_uop_23_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_4; // @[lsu.scala:219:36] wire l_uop_23_fu_code_4 = ldq_uop_23_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_4 = ldq_uop_23_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_5; // @[lsu.scala:219:36] wire l_uop_23_fu_code_5 = ldq_uop_23_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_5 = ldq_uop_23_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_6; // @[lsu.scala:219:36] wire l_uop_23_fu_code_6 = ldq_uop_23_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_6 = ldq_uop_23_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_7; // @[lsu.scala:219:36] wire l_uop_23_fu_code_7 = ldq_uop_23_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_7 = ldq_uop_23_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_8; // @[lsu.scala:219:36] wire l_uop_23_fu_code_8 = ldq_uop_23_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_8 = ldq_uop_23_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_9; // @[lsu.scala:219:36] wire l_uop_23_fu_code_9 = ldq_uop_23_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_9 = ldq_uop_23_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued; // @[lsu.scala:219:36] wire l_uop_23_iw_issued = ldq_uop_23_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued = ldq_uop_23_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_23_iw_issued_partial_agen = ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued_partial_agen = ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_23_iw_issued_partial_dgen = ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued_partial_dgen = ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_23_iw_p1_speculative_child = ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_iw_p1_speculative_child = ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_23_iw_p2_speculative_child = ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_iw_p2_speculative_child = ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p1_bypass_hint = ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p1_bypass_hint = ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p2_bypass_hint = ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p2_bypass_hint = ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p3_bypass_hint = ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p3_bypass_hint = ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_dis_col_sel = ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_dis_col_sel = ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_23_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_23_br_mask = ldq_uop_23_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_48_br_mask = ldq_uop_23_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_23_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_23_br_tag = ldq_uop_23_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_48_br_tag = ldq_uop_23_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_23_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_23_br_type = ldq_uop_23_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_48_br_type = ldq_uop_23_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sfb; // @[lsu.scala:219:36] wire l_uop_23_is_sfb = ldq_uop_23_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sfb = ldq_uop_23_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_fence; // @[lsu.scala:219:36] wire l_uop_23_is_fence = ldq_uop_23_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_fence = ldq_uop_23_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_fencei; // @[lsu.scala:219:36] wire l_uop_23_is_fencei = ldq_uop_23_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_fencei = ldq_uop_23_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sfence; // @[lsu.scala:219:36] wire l_uop_23_is_sfence = ldq_uop_23_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sfence = ldq_uop_23_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_amo; // @[lsu.scala:219:36] wire l_uop_23_is_amo = ldq_uop_23_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_amo = ldq_uop_23_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_eret; // @[lsu.scala:219:36] wire l_uop_23_is_eret = ldq_uop_23_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_eret = ldq_uop_23_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_23_is_sys_pc2epc = ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sys_pc2epc = ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_rocc; // @[lsu.scala:219:36] wire l_uop_23_is_rocc = ldq_uop_23_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_rocc = ldq_uop_23_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_mov; // @[lsu.scala:219:36] wire l_uop_23_is_mov = ldq_uop_23_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_mov = ldq_uop_23_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ftq_idx = ldq_uop_23_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ftq_idx = ldq_uop_23_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_edge_inst; // @[lsu.scala:219:36] wire l_uop_23_edge_inst = ldq_uop_23_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_48_edge_inst = ldq_uop_23_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_23_pc_lob = ldq_uop_23_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_pc_lob = ldq_uop_23_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_taken; // @[lsu.scala:219:36] wire l_uop_23_taken = ldq_uop_23_taken; // @[lsu.scala:219:36, :1191:37] wire uop_48_taken = ldq_uop_23_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_imm_rename; // @[lsu.scala:219:36] wire l_uop_23_imm_rename = ldq_uop_23_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_48_imm_rename = ldq_uop_23_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_imm_sel = ldq_uop_23_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_imm_sel = ldq_uop_23_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_23_pimm = ldq_uop_23_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_pimm = ldq_uop_23_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_23_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_23_imm_packed = ldq_uop_23_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_48_imm_packed = ldq_uop_23_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_23_op1_sel = ldq_uop_23_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_op1_sel = ldq_uop_23_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_op2_sel = ldq_uop_23_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_op2_sel = ldq_uop_23_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ldst = ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ldst = ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_wen = ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_wen = ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren1 = ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren1 = ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren2 = ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren2 = ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren3 = ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren3 = ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_swap12 = ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_swap12 = ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_swap23 = ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_swap23 = ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_ctrl_typeTagIn = ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_ctrl_typeTagIn = ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_ctrl_typeTagOut = ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_ctrl_typeTagOut = ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fromint = ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fromint = ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_toint = ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_toint = ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fastpipe = ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fastpipe = ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fma = ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fma = ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_div = ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_div = ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_sqrt = ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_sqrt = ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_wflags = ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_wflags = ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_vec = ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_vec = ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_23_rob_idx = ldq_uop_23_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_rob_idx = ldq_uop_23_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ldq_idx = ldq_uop_23_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ldq_idx = ldq_uop_23_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_stq_idx = ldq_uop_23_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_stq_idx = ldq_uop_23_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_23_rxq_idx = ldq_uop_23_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_rxq_idx = ldq_uop_23_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_23_pdst = ldq_uop_23_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_pdst = ldq_uop_23_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs1 = ldq_uop_23_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs1 = ldq_uop_23_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs2 = ldq_uop_23_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs2 = ldq_uop_23_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs3 = ldq_uop_23_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs3 = ldq_uop_23_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ppred = ldq_uop_23_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ppred = ldq_uop_23_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs1_busy; // @[lsu.scala:219:36] wire l_uop_23_prs1_busy = ldq_uop_23_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs1_busy = ldq_uop_23_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs2_busy; // @[lsu.scala:219:36] wire l_uop_23_prs2_busy = ldq_uop_23_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs2_busy = ldq_uop_23_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs3_busy; // @[lsu.scala:219:36] wire l_uop_23_prs3_busy = ldq_uop_23_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs3_busy = ldq_uop_23_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_ppred_busy; // @[lsu.scala:219:36] wire l_uop_23_ppred_busy = ldq_uop_23_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_ppred_busy = ldq_uop_23_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_23_stale_pdst = ldq_uop_23_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_stale_pdst = ldq_uop_23_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_exception; // @[lsu.scala:219:36] wire l_uop_23_exception = ldq_uop_23_exception; // @[lsu.scala:219:36, :1191:37] wire uop_48_exception = ldq_uop_23_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_23_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_23_exc_cause = ldq_uop_23_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_48_exc_cause = ldq_uop_23_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_23_mem_cmd = ldq_uop_23_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_mem_cmd = ldq_uop_23_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_23_mem_size = ldq_uop_23_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_mem_size = ldq_uop_23_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_mem_signed; // @[lsu.scala:219:36] wire l_uop_23_mem_signed = ldq_uop_23_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_48_mem_signed = ldq_uop_23_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_uses_ldq; // @[lsu.scala:219:36] wire l_uop_23_uses_ldq = ldq_uop_23_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_48_uses_ldq = ldq_uop_23_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_uses_stq; // @[lsu.scala:219:36] wire l_uop_23_uses_stq = ldq_uop_23_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_48_uses_stq = ldq_uop_23_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_unique; // @[lsu.scala:219:36] wire l_uop_23_is_unique = ldq_uop_23_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_unique = ldq_uop_23_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_23_flush_on_commit = ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_48_flush_on_commit = ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_23_csr_cmd = ldq_uop_23_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_csr_cmd = ldq_uop_23_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_23_ldst_is_rs1 = ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_48_ldst_is_rs1 = ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_23_ldst = ldq_uop_23_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_ldst = ldq_uop_23_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs1 = ldq_uop_23_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs1 = ldq_uop_23_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs2 = ldq_uop_23_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs2 = ldq_uop_23_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs3 = ldq_uop_23_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs3 = ldq_uop_23_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_dst_rtype = ldq_uop_23_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_dst_rtype = ldq_uop_23_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_lrs1_rtype = ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_lrs1_rtype = ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_lrs2_rtype = ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_lrs2_rtype = ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_frs3_en; // @[lsu.scala:219:36] wire l_uop_23_frs3_en = ldq_uop_23_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_48_frs3_en = ldq_uop_23_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fcn_dw; // @[lsu.scala:219:36] wire l_uop_23_fcn_dw = ldq_uop_23_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_48_fcn_dw = ldq_uop_23_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_23_fcn_op = ldq_uop_23_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_fcn_op = ldq_uop_23_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_val; // @[lsu.scala:219:36] wire l_uop_23_fp_val = ldq_uop_23_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_val = ldq_uop_23_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_23_fp_rm = ldq_uop_23_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_fp_rm = ldq_uop_23_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_typ = ldq_uop_23_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_typ = ldq_uop_23_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_pf_if = ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_pf_if = ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_ae_if = ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_ae_if = ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_ma_if = ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_ma_if = ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_23_bp_debug_if = ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_bp_debug_if = ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_23_bp_xcpt_if = ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_bp_xcpt_if = ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_23_debug_fsrc = ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_debug_fsrc = ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_23_debug_tsrc = ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_debug_tsrc = ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg ldq_addr_0_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_0_bits; // @[lsu.scala:220:36] reg ldq_addr_1_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_1_bits; // @[lsu.scala:220:36] reg ldq_addr_2_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_2_bits; // @[lsu.scala:220:36] reg ldq_addr_3_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_3_bits; // @[lsu.scala:220:36] reg ldq_addr_4_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_4_bits; // @[lsu.scala:220:36] reg ldq_addr_5_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_5_bits; // @[lsu.scala:220:36] reg ldq_addr_6_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_6_bits; // @[lsu.scala:220:36] reg ldq_addr_7_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_7_bits; // @[lsu.scala:220:36] reg ldq_addr_8_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_8_bits; // @[lsu.scala:220:36] reg ldq_addr_9_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_9_bits; // @[lsu.scala:220:36] reg ldq_addr_10_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_10_bits; // @[lsu.scala:220:36] reg ldq_addr_11_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_11_bits; // @[lsu.scala:220:36] reg ldq_addr_12_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_12_bits; // @[lsu.scala:220:36] reg ldq_addr_13_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_13_bits; // @[lsu.scala:220:36] reg ldq_addr_14_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_14_bits; // @[lsu.scala:220:36] reg ldq_addr_15_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_15_bits; // @[lsu.scala:220:36] reg ldq_addr_16_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_16_bits; // @[lsu.scala:220:36] reg ldq_addr_17_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_17_bits; // @[lsu.scala:220:36] reg ldq_addr_18_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_18_bits; // @[lsu.scala:220:36] reg ldq_addr_19_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_19_bits; // @[lsu.scala:220:36] reg ldq_addr_20_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_20_bits; // @[lsu.scala:220:36] reg ldq_addr_21_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_21_bits; // @[lsu.scala:220:36] reg ldq_addr_22_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_22_bits; // @[lsu.scala:220:36] reg ldq_addr_23_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_23_bits; // @[lsu.scala:220:36] reg ldq_addr_is_virtual_0; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_1; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_2; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_3; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_4; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_5; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_6; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_7; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_8; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_9; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_10; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_11; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_12; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_13; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_14; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_15; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_16; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_17; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_18; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_19; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_20; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_21; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_22; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_23; // @[lsu.scala:221:36] reg ldq_addr_is_uncacheable_0; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_1; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_2; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_3; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_4; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_5; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_6; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_7; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_8; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_9; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_10; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_11; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_12; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_13; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_14; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_15; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_16; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_17; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_18; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_19; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_20; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_21; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_22; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_23; // @[lsu.scala:222:36] reg ldq_executed_0; // @[lsu.scala:223:36] reg ldq_executed_1; // @[lsu.scala:223:36] reg ldq_executed_2; // @[lsu.scala:223:36] reg ldq_executed_3; // @[lsu.scala:223:36] reg ldq_executed_4; // @[lsu.scala:223:36] reg ldq_executed_5; // @[lsu.scala:223:36] reg ldq_executed_6; // @[lsu.scala:223:36] reg ldq_executed_7; // @[lsu.scala:223:36] reg ldq_executed_8; // @[lsu.scala:223:36] reg ldq_executed_9; // @[lsu.scala:223:36] reg ldq_executed_10; // @[lsu.scala:223:36] reg ldq_executed_11; // @[lsu.scala:223:36] reg ldq_executed_12; // @[lsu.scala:223:36] reg ldq_executed_13; // @[lsu.scala:223:36] reg ldq_executed_14; // @[lsu.scala:223:36] reg ldq_executed_15; // @[lsu.scala:223:36] reg ldq_executed_16; // @[lsu.scala:223:36] reg ldq_executed_17; // @[lsu.scala:223:36] reg ldq_executed_18; // @[lsu.scala:223:36] reg ldq_executed_19; // @[lsu.scala:223:36] reg ldq_executed_20; // @[lsu.scala:223:36] reg ldq_executed_21; // @[lsu.scala:223:36] reg ldq_executed_22; // @[lsu.scala:223:36] reg ldq_executed_23; // @[lsu.scala:223:36] reg ldq_succeeded_0; // @[lsu.scala:224:36] reg ldq_succeeded_1; // @[lsu.scala:224:36] reg ldq_succeeded_2; // @[lsu.scala:224:36] reg ldq_succeeded_3; // @[lsu.scala:224:36] reg ldq_succeeded_4; // @[lsu.scala:224:36] reg ldq_succeeded_5; // @[lsu.scala:224:36] reg ldq_succeeded_6; // @[lsu.scala:224:36] reg ldq_succeeded_7; // @[lsu.scala:224:36] reg ldq_succeeded_8; // @[lsu.scala:224:36] reg ldq_succeeded_9; // @[lsu.scala:224:36] reg ldq_succeeded_10; // @[lsu.scala:224:36] reg ldq_succeeded_11; // @[lsu.scala:224:36] reg ldq_succeeded_12; // @[lsu.scala:224:36] reg ldq_succeeded_13; // @[lsu.scala:224:36] reg ldq_succeeded_14; // @[lsu.scala:224:36] reg ldq_succeeded_15; // @[lsu.scala:224:36] reg ldq_succeeded_16; // @[lsu.scala:224:36] reg ldq_succeeded_17; // @[lsu.scala:224:36] reg ldq_succeeded_18; // @[lsu.scala:224:36] reg ldq_succeeded_19; // @[lsu.scala:224:36] reg ldq_succeeded_20; // @[lsu.scala:224:36] reg ldq_succeeded_21; // @[lsu.scala:224:36] reg ldq_succeeded_22; // @[lsu.scala:224:36] reg ldq_succeeded_23; // @[lsu.scala:224:36] reg ldq_order_fail_0; // @[lsu.scala:225:36] reg ldq_order_fail_1; // @[lsu.scala:225:36] reg ldq_order_fail_2; // @[lsu.scala:225:36] reg ldq_order_fail_3; // @[lsu.scala:225:36] reg ldq_order_fail_4; // @[lsu.scala:225:36] reg ldq_order_fail_5; // @[lsu.scala:225:36] reg ldq_order_fail_6; // @[lsu.scala:225:36] reg ldq_order_fail_7; // @[lsu.scala:225:36] reg ldq_order_fail_8; // @[lsu.scala:225:36] reg ldq_order_fail_9; // @[lsu.scala:225:36] reg ldq_order_fail_10; // @[lsu.scala:225:36] reg ldq_order_fail_11; // @[lsu.scala:225:36] reg ldq_order_fail_12; // @[lsu.scala:225:36] reg ldq_order_fail_13; // @[lsu.scala:225:36] reg ldq_order_fail_14; // @[lsu.scala:225:36] reg ldq_order_fail_15; // @[lsu.scala:225:36] reg ldq_order_fail_16; // @[lsu.scala:225:36] reg ldq_order_fail_17; // @[lsu.scala:225:36] reg ldq_order_fail_18; // @[lsu.scala:225:36] reg ldq_order_fail_19; // @[lsu.scala:225:36] reg ldq_order_fail_20; // @[lsu.scala:225:36] reg ldq_order_fail_21; // @[lsu.scala:225:36] reg ldq_order_fail_22; // @[lsu.scala:225:36] reg ldq_order_fail_23; // @[lsu.scala:225:36] reg ldq_observed_0; // @[lsu.scala:226:36] reg ldq_observed_1; // @[lsu.scala:226:36] reg ldq_observed_2; // @[lsu.scala:226:36] reg ldq_observed_3; // @[lsu.scala:226:36] reg ldq_observed_4; // @[lsu.scala:226:36] reg ldq_observed_5; // @[lsu.scala:226:36] reg ldq_observed_6; // @[lsu.scala:226:36] reg ldq_observed_7; // @[lsu.scala:226:36] reg ldq_observed_8; // @[lsu.scala:226:36] reg ldq_observed_9; // @[lsu.scala:226:36] reg ldq_observed_10; // @[lsu.scala:226:36] reg ldq_observed_11; // @[lsu.scala:226:36] reg ldq_observed_12; // @[lsu.scala:226:36] reg ldq_observed_13; // @[lsu.scala:226:36] reg ldq_observed_14; // @[lsu.scala:226:36] reg ldq_observed_15; // @[lsu.scala:226:36] reg ldq_observed_16; // @[lsu.scala:226:36] reg ldq_observed_17; // @[lsu.scala:226:36] reg ldq_observed_18; // @[lsu.scala:226:36] reg ldq_observed_19; // @[lsu.scala:226:36] reg ldq_observed_20; // @[lsu.scala:226:36] reg ldq_observed_21; // @[lsu.scala:226:36] reg ldq_observed_22; // @[lsu.scala:226:36] reg ldq_observed_23; // @[lsu.scala:226:36] reg [23:0] ldq_st_dep_mask_0; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_1; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_2; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_3; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_4; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_5; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_6; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_7; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_8; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_9; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_10; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_11; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_12; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_13; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_14; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_15; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_16; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_17; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_18; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_19; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_20; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_21; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_22; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_23; // @[lsu.scala:227:36] reg [7:0] ldq_ld_byte_mask_0; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_1; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_2; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_3; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_4; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_5; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_6; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_7; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_8; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_9; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_10; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_11; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_12; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_13; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_14; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_15; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_16; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_17; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_18; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_19; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_20; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_21; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_22; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_23; // @[lsu.scala:228:36] reg ldq_forward_std_val_0; // @[lsu.scala:229:36] reg ldq_forward_std_val_1; // @[lsu.scala:229:36] reg ldq_forward_std_val_2; // @[lsu.scala:229:36] reg ldq_forward_std_val_3; // @[lsu.scala:229:36] reg ldq_forward_std_val_4; // @[lsu.scala:229:36] reg ldq_forward_std_val_5; // @[lsu.scala:229:36] reg ldq_forward_std_val_6; // @[lsu.scala:229:36] reg ldq_forward_std_val_7; // @[lsu.scala:229:36] reg ldq_forward_std_val_8; // @[lsu.scala:229:36] reg ldq_forward_std_val_9; // @[lsu.scala:229:36] reg ldq_forward_std_val_10; // @[lsu.scala:229:36] reg ldq_forward_std_val_11; // @[lsu.scala:229:36] reg ldq_forward_std_val_12; // @[lsu.scala:229:36] reg ldq_forward_std_val_13; // @[lsu.scala:229:36] reg ldq_forward_std_val_14; // @[lsu.scala:229:36] reg ldq_forward_std_val_15; // @[lsu.scala:229:36] reg ldq_forward_std_val_16; // @[lsu.scala:229:36] reg ldq_forward_std_val_17; // @[lsu.scala:229:36] reg ldq_forward_std_val_18; // @[lsu.scala:229:36] reg ldq_forward_std_val_19; // @[lsu.scala:229:36] reg ldq_forward_std_val_20; // @[lsu.scala:229:36] reg ldq_forward_std_val_21; // @[lsu.scala:229:36] reg ldq_forward_std_val_22; // @[lsu.scala:229:36] reg ldq_forward_std_val_23; // @[lsu.scala:229:36] reg [4:0] ldq_forward_stq_idx_0; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_1; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_2; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_3; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_4; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_5; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_6; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_7; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_8; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_9; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_10; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_11; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_12; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_13; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_14; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_15; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_16; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_17; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_18; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_19; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_20; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_21; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_22; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_23; // @[lsu.scala:230:36] reg [63:0] ldq_debug_wb_data_0; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_1; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_2; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_3; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_4; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_5; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_6; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_7; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_8; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_9; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_10; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_11; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_12; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_13; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_14; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_15; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_16; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_17; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_18; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_19; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_20; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_21; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_22; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_23; // @[lsu.scala:231:36] reg stq_valid_0; // @[lsu.scala:251:32] reg stq_valid_1; // @[lsu.scala:251:32] reg stq_valid_2; // @[lsu.scala:251:32] reg stq_valid_3; // @[lsu.scala:251:32] reg stq_valid_4; // @[lsu.scala:251:32] reg stq_valid_5; // @[lsu.scala:251:32] reg stq_valid_6; // @[lsu.scala:251:32] reg stq_valid_7; // @[lsu.scala:251:32] reg stq_valid_8; // @[lsu.scala:251:32] reg stq_valid_9; // @[lsu.scala:251:32] reg stq_valid_10; // @[lsu.scala:251:32] reg stq_valid_11; // @[lsu.scala:251:32] reg stq_valid_12; // @[lsu.scala:251:32] reg stq_valid_13; // @[lsu.scala:251:32] reg stq_valid_14; // @[lsu.scala:251:32] reg stq_valid_15; // @[lsu.scala:251:32] reg stq_valid_16; // @[lsu.scala:251:32] reg stq_valid_17; // @[lsu.scala:251:32] reg stq_valid_18; // @[lsu.scala:251:32] reg stq_valid_19; // @[lsu.scala:251:32] reg stq_valid_20; // @[lsu.scala:251:32] reg stq_valid_21; // @[lsu.scala:251:32] reg stq_valid_22; // @[lsu.scala:251:32] reg stq_valid_23; // @[lsu.scala:251:32] reg [31:0] stq_uop_0_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_0_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rvc; // @[lsu.scala:252:32] wire s_uop_3_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_0_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_3_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_1_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_0; // @[lsu.scala:252:32] wire s_uop_3_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_1; // @[lsu.scala:252:32] wire s_uop_3_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_2; // @[lsu.scala:252:32] wire s_uop_3_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_3; // @[lsu.scala:252:32] wire s_uop_3_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_0; // @[lsu.scala:252:32] wire s_uop_3_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_1; // @[lsu.scala:252:32] wire s_uop_3_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_2; // @[lsu.scala:252:32] wire s_uop_3_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_3; // @[lsu.scala:252:32] wire s_uop_3_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_4; // @[lsu.scala:252:32] wire s_uop_3_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_5; // @[lsu.scala:252:32] wire s_uop_3_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_6; // @[lsu.scala:252:32] wire s_uop_3_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_7; // @[lsu.scala:252:32] wire s_uop_3_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_8; // @[lsu.scala:252:32] wire s_uop_3_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_9; // @[lsu.scala:252:32] wire s_uop_3_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued; // @[lsu.scala:252:32] wire s_uop_3_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_3_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_3_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_0_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_3_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_1_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfb; // @[lsu.scala:252:32] wire s_uop_3_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fence; // @[lsu.scala:252:32] wire s_uop_3_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fencei; // @[lsu.scala:252:32] wire s_uop_3_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfence; // @[lsu.scala:252:32] wire s_uop_3_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_amo; // @[lsu.scala:252:32] wire s_uop_3_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_eret; // @[lsu.scala:252:32] wire s_uop_3_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_3_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rocc; // @[lsu.scala:252:32] wire s_uop_3_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_mov; // @[lsu.scala:252:32] wire s_uop_3_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_edge_inst; // @[lsu.scala:252:32] wire s_uop_3_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_1_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_3_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_taken; // @[lsu.scala:252:32] wire s_uop_3_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1324:37] wire uop_1_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_imm_rename; // @[lsu.scala:252:32] wire s_uop_3_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_1_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_3_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_0_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_3_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_1_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_3_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_3_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs1_busy; // @[lsu.scala:252:32] wire s_uop_3_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs2_busy; // @[lsu.scala:252:32] wire s_uop_3_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs3_busy; // @[lsu.scala:252:32] wire s_uop_3_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ppred_busy; // @[lsu.scala:252:32] wire s_uop_3_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_exception; // @[lsu.scala:252:32] wire s_uop_3_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1324:37] wire uop_1_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_0_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_3_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_1_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_3_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_3_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_mem_signed; // @[lsu.scala:252:32] wire s_uop_3_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_1_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_ldq; // @[lsu.scala:252:32] wire s_uop_3_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_stq; // @[lsu.scala:252:32] wire s_uop_3_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_unique; // @[lsu.scala:252:32] wire s_uop_3_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_3_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_1_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_3_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_3_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_1_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_3_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_frs3_en; // @[lsu.scala:252:32] wire s_uop_3_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_1_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fcn_dw; // @[lsu.scala:252:32] wire s_uop_3_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_1_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_3_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_val; // @[lsu.scala:252:32] wire s_uop_3_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_3_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_3_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_3_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rvc; // @[lsu.scala:252:32] wire s_uop_4_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_1_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_4_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_2_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_0; // @[lsu.scala:252:32] wire s_uop_4_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_1; // @[lsu.scala:252:32] wire s_uop_4_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_2; // @[lsu.scala:252:32] wire s_uop_4_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_3; // @[lsu.scala:252:32] wire s_uop_4_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_0; // @[lsu.scala:252:32] wire s_uop_4_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_1; // @[lsu.scala:252:32] wire s_uop_4_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_2; // @[lsu.scala:252:32] wire s_uop_4_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_3; // @[lsu.scala:252:32] wire s_uop_4_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_4; // @[lsu.scala:252:32] wire s_uop_4_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_5; // @[lsu.scala:252:32] wire s_uop_4_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_6; // @[lsu.scala:252:32] wire s_uop_4_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_7; // @[lsu.scala:252:32] wire s_uop_4_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_8; // @[lsu.scala:252:32] wire s_uop_4_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_9; // @[lsu.scala:252:32] wire s_uop_4_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued; // @[lsu.scala:252:32] wire s_uop_4_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_4_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_4_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_1_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_4_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_2_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfb; // @[lsu.scala:252:32] wire s_uop_4_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fence; // @[lsu.scala:252:32] wire s_uop_4_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fencei; // @[lsu.scala:252:32] wire s_uop_4_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfence; // @[lsu.scala:252:32] wire s_uop_4_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_amo; // @[lsu.scala:252:32] wire s_uop_4_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_eret; // @[lsu.scala:252:32] wire s_uop_4_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_4_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rocc; // @[lsu.scala:252:32] wire s_uop_4_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_mov; // @[lsu.scala:252:32] wire s_uop_4_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_edge_inst; // @[lsu.scala:252:32] wire s_uop_4_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_2_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_4_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_taken; // @[lsu.scala:252:32] wire s_uop_4_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1324:37] wire uop_2_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_imm_rename; // @[lsu.scala:252:32] wire s_uop_4_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_2_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_4_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_1_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_4_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_2_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_4_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_4_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs1_busy; // @[lsu.scala:252:32] wire s_uop_4_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs2_busy; // @[lsu.scala:252:32] wire s_uop_4_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs3_busy; // @[lsu.scala:252:32] wire s_uop_4_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ppred_busy; // @[lsu.scala:252:32] wire s_uop_4_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_exception; // @[lsu.scala:252:32] wire s_uop_4_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1324:37] wire uop_2_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_1_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_4_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_2_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_4_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_4_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_mem_signed; // @[lsu.scala:252:32] wire s_uop_4_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_2_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_ldq; // @[lsu.scala:252:32] wire s_uop_4_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_stq; // @[lsu.scala:252:32] wire s_uop_4_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_unique; // @[lsu.scala:252:32] wire s_uop_4_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_4_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_2_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_4_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_4_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_2_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_4_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_frs3_en; // @[lsu.scala:252:32] wire s_uop_4_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_2_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fcn_dw; // @[lsu.scala:252:32] wire s_uop_4_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_2_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_4_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_val; // @[lsu.scala:252:32] wire s_uop_4_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_4_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_4_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_4_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rvc; // @[lsu.scala:252:32] wire s_uop_5_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_2_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_5_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_3_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_0; // @[lsu.scala:252:32] wire s_uop_5_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_1; // @[lsu.scala:252:32] wire s_uop_5_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_2; // @[lsu.scala:252:32] wire s_uop_5_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_3; // @[lsu.scala:252:32] wire s_uop_5_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_0; // @[lsu.scala:252:32] wire s_uop_5_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_1; // @[lsu.scala:252:32] wire s_uop_5_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_2; // @[lsu.scala:252:32] wire s_uop_5_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_3; // @[lsu.scala:252:32] wire s_uop_5_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_4; // @[lsu.scala:252:32] wire s_uop_5_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_5; // @[lsu.scala:252:32] wire s_uop_5_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_6; // @[lsu.scala:252:32] wire s_uop_5_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_7; // @[lsu.scala:252:32] wire s_uop_5_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_8; // @[lsu.scala:252:32] wire s_uop_5_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_9; // @[lsu.scala:252:32] wire s_uop_5_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued; // @[lsu.scala:252:32] wire s_uop_5_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_5_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_5_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_2_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_5_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_3_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfb; // @[lsu.scala:252:32] wire s_uop_5_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fence; // @[lsu.scala:252:32] wire s_uop_5_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fencei; // @[lsu.scala:252:32] wire s_uop_5_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfence; // @[lsu.scala:252:32] wire s_uop_5_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_amo; // @[lsu.scala:252:32] wire s_uop_5_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_eret; // @[lsu.scala:252:32] wire s_uop_5_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_5_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rocc; // @[lsu.scala:252:32] wire s_uop_5_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_mov; // @[lsu.scala:252:32] wire s_uop_5_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_edge_inst; // @[lsu.scala:252:32] wire s_uop_5_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_3_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_5_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_taken; // @[lsu.scala:252:32] wire s_uop_5_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1324:37] wire uop_3_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_imm_rename; // @[lsu.scala:252:32] wire s_uop_5_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_3_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_5_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_2_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_5_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_3_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_5_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_5_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs1_busy; // @[lsu.scala:252:32] wire s_uop_5_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs2_busy; // @[lsu.scala:252:32] wire s_uop_5_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs3_busy; // @[lsu.scala:252:32] wire s_uop_5_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ppred_busy; // @[lsu.scala:252:32] wire s_uop_5_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_exception; // @[lsu.scala:252:32] wire s_uop_5_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1324:37] wire uop_3_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_2_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_5_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_3_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_5_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_5_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_mem_signed; // @[lsu.scala:252:32] wire s_uop_5_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_3_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_ldq; // @[lsu.scala:252:32] wire s_uop_5_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_stq; // @[lsu.scala:252:32] wire s_uop_5_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_unique; // @[lsu.scala:252:32] wire s_uop_5_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_5_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_3_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_5_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_5_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_3_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_5_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_frs3_en; // @[lsu.scala:252:32] wire s_uop_5_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_3_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fcn_dw; // @[lsu.scala:252:32] wire s_uop_5_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_3_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_5_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_val; // @[lsu.scala:252:32] wire s_uop_5_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_5_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_5_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_5_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rvc; // @[lsu.scala:252:32] wire s_uop_6_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_3_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_6_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_4_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_0; // @[lsu.scala:252:32] wire s_uop_6_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_1; // @[lsu.scala:252:32] wire s_uop_6_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_2; // @[lsu.scala:252:32] wire s_uop_6_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_3; // @[lsu.scala:252:32] wire s_uop_6_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_0; // @[lsu.scala:252:32] wire s_uop_6_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_1; // @[lsu.scala:252:32] wire s_uop_6_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_2; // @[lsu.scala:252:32] wire s_uop_6_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_3; // @[lsu.scala:252:32] wire s_uop_6_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_4; // @[lsu.scala:252:32] wire s_uop_6_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_5; // @[lsu.scala:252:32] wire s_uop_6_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_6; // @[lsu.scala:252:32] wire s_uop_6_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_7; // @[lsu.scala:252:32] wire s_uop_6_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_8; // @[lsu.scala:252:32] wire s_uop_6_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_9; // @[lsu.scala:252:32] wire s_uop_6_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued; // @[lsu.scala:252:32] wire s_uop_6_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_6_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_6_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_3_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_6_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_4_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfb; // @[lsu.scala:252:32] wire s_uop_6_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fence; // @[lsu.scala:252:32] wire s_uop_6_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fencei; // @[lsu.scala:252:32] wire s_uop_6_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfence; // @[lsu.scala:252:32] wire s_uop_6_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_amo; // @[lsu.scala:252:32] wire s_uop_6_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_eret; // @[lsu.scala:252:32] wire s_uop_6_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_6_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rocc; // @[lsu.scala:252:32] wire s_uop_6_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_mov; // @[lsu.scala:252:32] wire s_uop_6_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_edge_inst; // @[lsu.scala:252:32] wire s_uop_6_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_4_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_6_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_taken; // @[lsu.scala:252:32] wire s_uop_6_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1324:37] wire uop_4_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_imm_rename; // @[lsu.scala:252:32] wire s_uop_6_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_4_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_6_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_3_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_6_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_4_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_6_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_6_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs1_busy; // @[lsu.scala:252:32] wire s_uop_6_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs2_busy; // @[lsu.scala:252:32] wire s_uop_6_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs3_busy; // @[lsu.scala:252:32] wire s_uop_6_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ppred_busy; // @[lsu.scala:252:32] wire s_uop_6_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_exception; // @[lsu.scala:252:32] wire s_uop_6_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1324:37] wire uop_4_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_3_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_6_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_4_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_6_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_6_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_mem_signed; // @[lsu.scala:252:32] wire s_uop_6_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_4_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_ldq; // @[lsu.scala:252:32] wire s_uop_6_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_stq; // @[lsu.scala:252:32] wire s_uop_6_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_unique; // @[lsu.scala:252:32] wire s_uop_6_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_6_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_4_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_6_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_6_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_4_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_6_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_frs3_en; // @[lsu.scala:252:32] wire s_uop_6_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_4_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fcn_dw; // @[lsu.scala:252:32] wire s_uop_6_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_4_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_6_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_val; // @[lsu.scala:252:32] wire s_uop_6_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_6_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_6_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_6_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rvc; // @[lsu.scala:252:32] wire s_uop_7_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_4_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_7_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_5_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_0; // @[lsu.scala:252:32] wire s_uop_7_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_1; // @[lsu.scala:252:32] wire s_uop_7_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_2; // @[lsu.scala:252:32] wire s_uop_7_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_3; // @[lsu.scala:252:32] wire s_uop_7_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_0; // @[lsu.scala:252:32] wire s_uop_7_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_1; // @[lsu.scala:252:32] wire s_uop_7_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_2; // @[lsu.scala:252:32] wire s_uop_7_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_3; // @[lsu.scala:252:32] wire s_uop_7_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_4; // @[lsu.scala:252:32] wire s_uop_7_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_5; // @[lsu.scala:252:32] wire s_uop_7_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_6; // @[lsu.scala:252:32] wire s_uop_7_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_7; // @[lsu.scala:252:32] wire s_uop_7_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_8; // @[lsu.scala:252:32] wire s_uop_7_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_9; // @[lsu.scala:252:32] wire s_uop_7_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued; // @[lsu.scala:252:32] wire s_uop_7_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_7_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_7_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_4_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_7_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_5_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfb; // @[lsu.scala:252:32] wire s_uop_7_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fence; // @[lsu.scala:252:32] wire s_uop_7_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fencei; // @[lsu.scala:252:32] wire s_uop_7_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfence; // @[lsu.scala:252:32] wire s_uop_7_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_amo; // @[lsu.scala:252:32] wire s_uop_7_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_eret; // @[lsu.scala:252:32] wire s_uop_7_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_7_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rocc; // @[lsu.scala:252:32] wire s_uop_7_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_mov; // @[lsu.scala:252:32] wire s_uop_7_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_edge_inst; // @[lsu.scala:252:32] wire s_uop_7_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_5_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_7_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_taken; // @[lsu.scala:252:32] wire s_uop_7_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1324:37] wire uop_5_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_imm_rename; // @[lsu.scala:252:32] wire s_uop_7_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_5_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_7_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_4_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_7_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_5_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_7_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_7_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs1_busy; // @[lsu.scala:252:32] wire s_uop_7_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs2_busy; // @[lsu.scala:252:32] wire s_uop_7_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs3_busy; // @[lsu.scala:252:32] wire s_uop_7_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ppred_busy; // @[lsu.scala:252:32] wire s_uop_7_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_exception; // @[lsu.scala:252:32] wire s_uop_7_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1324:37] wire uop_5_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_4_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_7_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_5_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_7_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_7_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_mem_signed; // @[lsu.scala:252:32] wire s_uop_7_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_5_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_ldq; // @[lsu.scala:252:32] wire s_uop_7_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_stq; // @[lsu.scala:252:32] wire s_uop_7_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_unique; // @[lsu.scala:252:32] wire s_uop_7_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_7_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_5_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_7_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_7_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_5_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_7_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_frs3_en; // @[lsu.scala:252:32] wire s_uop_7_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_5_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fcn_dw; // @[lsu.scala:252:32] wire s_uop_7_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_5_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_7_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_val; // @[lsu.scala:252:32] wire s_uop_7_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_7_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_7_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_7_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rvc; // @[lsu.scala:252:32] wire s_uop_8_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_5_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_8_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_6_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_0; // @[lsu.scala:252:32] wire s_uop_8_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_1; // @[lsu.scala:252:32] wire s_uop_8_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_2; // @[lsu.scala:252:32] wire s_uop_8_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_3; // @[lsu.scala:252:32] wire s_uop_8_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_0; // @[lsu.scala:252:32] wire s_uop_8_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_1; // @[lsu.scala:252:32] wire s_uop_8_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_2; // @[lsu.scala:252:32] wire s_uop_8_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_3; // @[lsu.scala:252:32] wire s_uop_8_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_4; // @[lsu.scala:252:32] wire s_uop_8_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_5; // @[lsu.scala:252:32] wire s_uop_8_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_6; // @[lsu.scala:252:32] wire s_uop_8_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_7; // @[lsu.scala:252:32] wire s_uop_8_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_8; // @[lsu.scala:252:32] wire s_uop_8_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_9; // @[lsu.scala:252:32] wire s_uop_8_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued; // @[lsu.scala:252:32] wire s_uop_8_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_8_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_8_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_5_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_8_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_6_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfb; // @[lsu.scala:252:32] wire s_uop_8_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fence; // @[lsu.scala:252:32] wire s_uop_8_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fencei; // @[lsu.scala:252:32] wire s_uop_8_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfence; // @[lsu.scala:252:32] wire s_uop_8_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_amo; // @[lsu.scala:252:32] wire s_uop_8_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_eret; // @[lsu.scala:252:32] wire s_uop_8_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_8_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rocc; // @[lsu.scala:252:32] wire s_uop_8_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_mov; // @[lsu.scala:252:32] wire s_uop_8_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_edge_inst; // @[lsu.scala:252:32] wire s_uop_8_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_6_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_8_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_taken; // @[lsu.scala:252:32] wire s_uop_8_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1324:37] wire uop_6_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_imm_rename; // @[lsu.scala:252:32] wire s_uop_8_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_6_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_8_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_5_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_8_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_6_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_8_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_8_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs1_busy; // @[lsu.scala:252:32] wire s_uop_8_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs2_busy; // @[lsu.scala:252:32] wire s_uop_8_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs3_busy; // @[lsu.scala:252:32] wire s_uop_8_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ppred_busy; // @[lsu.scala:252:32] wire s_uop_8_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_exception; // @[lsu.scala:252:32] wire s_uop_8_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1324:37] wire uop_6_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_5_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_8_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_6_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_8_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_8_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_mem_signed; // @[lsu.scala:252:32] wire s_uop_8_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_6_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_ldq; // @[lsu.scala:252:32] wire s_uop_8_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_stq; // @[lsu.scala:252:32] wire s_uop_8_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_unique; // @[lsu.scala:252:32] wire s_uop_8_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_8_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_6_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_8_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_8_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_6_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_8_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_frs3_en; // @[lsu.scala:252:32] wire s_uop_8_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_6_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fcn_dw; // @[lsu.scala:252:32] wire s_uop_8_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_6_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_8_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_val; // @[lsu.scala:252:32] wire s_uop_8_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_8_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_8_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_8_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rvc; // @[lsu.scala:252:32] wire s_uop_9_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_6_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_9_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_7_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_0; // @[lsu.scala:252:32] wire s_uop_9_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_1; // @[lsu.scala:252:32] wire s_uop_9_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_2; // @[lsu.scala:252:32] wire s_uop_9_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_3; // @[lsu.scala:252:32] wire s_uop_9_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_0; // @[lsu.scala:252:32] wire s_uop_9_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_1; // @[lsu.scala:252:32] wire s_uop_9_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_2; // @[lsu.scala:252:32] wire s_uop_9_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_3; // @[lsu.scala:252:32] wire s_uop_9_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_4; // @[lsu.scala:252:32] wire s_uop_9_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_5; // @[lsu.scala:252:32] wire s_uop_9_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_6; // @[lsu.scala:252:32] wire s_uop_9_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_7; // @[lsu.scala:252:32] wire s_uop_9_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_8; // @[lsu.scala:252:32] wire s_uop_9_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_9; // @[lsu.scala:252:32] wire s_uop_9_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued; // @[lsu.scala:252:32] wire s_uop_9_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_9_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_9_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_6_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_9_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_7_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfb; // @[lsu.scala:252:32] wire s_uop_9_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fence; // @[lsu.scala:252:32] wire s_uop_9_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fencei; // @[lsu.scala:252:32] wire s_uop_9_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfence; // @[lsu.scala:252:32] wire s_uop_9_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_amo; // @[lsu.scala:252:32] wire s_uop_9_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_eret; // @[lsu.scala:252:32] wire s_uop_9_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_9_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rocc; // @[lsu.scala:252:32] wire s_uop_9_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_mov; // @[lsu.scala:252:32] wire s_uop_9_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_edge_inst; // @[lsu.scala:252:32] wire s_uop_9_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_7_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_9_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_taken; // @[lsu.scala:252:32] wire s_uop_9_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1324:37] wire uop_7_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_imm_rename; // @[lsu.scala:252:32] wire s_uop_9_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_7_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_9_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_6_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_9_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_7_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_9_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_9_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs1_busy; // @[lsu.scala:252:32] wire s_uop_9_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs2_busy; // @[lsu.scala:252:32] wire s_uop_9_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs3_busy; // @[lsu.scala:252:32] wire s_uop_9_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ppred_busy; // @[lsu.scala:252:32] wire s_uop_9_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_exception; // @[lsu.scala:252:32] wire s_uop_9_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1324:37] wire uop_7_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_6_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_9_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_7_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_9_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_9_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_mem_signed; // @[lsu.scala:252:32] wire s_uop_9_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_7_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_ldq; // @[lsu.scala:252:32] wire s_uop_9_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_stq; // @[lsu.scala:252:32] wire s_uop_9_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_unique; // @[lsu.scala:252:32] wire s_uop_9_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_9_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_7_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_9_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_9_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_7_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_9_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_frs3_en; // @[lsu.scala:252:32] wire s_uop_9_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_7_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fcn_dw; // @[lsu.scala:252:32] wire s_uop_9_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_7_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_9_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_val; // @[lsu.scala:252:32] wire s_uop_9_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_9_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_9_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_9_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rvc; // @[lsu.scala:252:32] wire s_uop_10_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_7_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_10_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_8_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_0; // @[lsu.scala:252:32] wire s_uop_10_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_1; // @[lsu.scala:252:32] wire s_uop_10_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_2; // @[lsu.scala:252:32] wire s_uop_10_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_3; // @[lsu.scala:252:32] wire s_uop_10_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_0; // @[lsu.scala:252:32] wire s_uop_10_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_1; // @[lsu.scala:252:32] wire s_uop_10_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_2; // @[lsu.scala:252:32] wire s_uop_10_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_3; // @[lsu.scala:252:32] wire s_uop_10_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_4; // @[lsu.scala:252:32] wire s_uop_10_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_5; // @[lsu.scala:252:32] wire s_uop_10_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_6; // @[lsu.scala:252:32] wire s_uop_10_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_7; // @[lsu.scala:252:32] wire s_uop_10_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_8; // @[lsu.scala:252:32] wire s_uop_10_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_9; // @[lsu.scala:252:32] wire s_uop_10_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued; // @[lsu.scala:252:32] wire s_uop_10_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_10_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_10_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_7_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_10_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_8_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfb; // @[lsu.scala:252:32] wire s_uop_10_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fence; // @[lsu.scala:252:32] wire s_uop_10_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fencei; // @[lsu.scala:252:32] wire s_uop_10_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfence; // @[lsu.scala:252:32] wire s_uop_10_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_amo; // @[lsu.scala:252:32] wire s_uop_10_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_eret; // @[lsu.scala:252:32] wire s_uop_10_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_10_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rocc; // @[lsu.scala:252:32] wire s_uop_10_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_mov; // @[lsu.scala:252:32] wire s_uop_10_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_edge_inst; // @[lsu.scala:252:32] wire s_uop_10_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_8_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_10_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_taken; // @[lsu.scala:252:32] wire s_uop_10_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1324:37] wire uop_8_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_imm_rename; // @[lsu.scala:252:32] wire s_uop_10_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_8_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_10_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_7_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_10_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_8_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_10_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_10_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs1_busy; // @[lsu.scala:252:32] wire s_uop_10_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs2_busy; // @[lsu.scala:252:32] wire s_uop_10_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs3_busy; // @[lsu.scala:252:32] wire s_uop_10_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ppred_busy; // @[lsu.scala:252:32] wire s_uop_10_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_exception; // @[lsu.scala:252:32] wire s_uop_10_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1324:37] wire uop_8_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_7_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_10_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_8_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_10_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_10_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_mem_signed; // @[lsu.scala:252:32] wire s_uop_10_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_8_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_ldq; // @[lsu.scala:252:32] wire s_uop_10_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_stq; // @[lsu.scala:252:32] wire s_uop_10_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_unique; // @[lsu.scala:252:32] wire s_uop_10_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_10_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_8_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_10_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_10_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_8_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_10_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_frs3_en; // @[lsu.scala:252:32] wire s_uop_10_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_8_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fcn_dw; // @[lsu.scala:252:32] wire s_uop_10_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_8_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_10_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_val; // @[lsu.scala:252:32] wire s_uop_10_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_10_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_10_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_10_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rvc; // @[lsu.scala:252:32] wire s_uop_11_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_8_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_11_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_9_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_0; // @[lsu.scala:252:32] wire s_uop_11_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_1; // @[lsu.scala:252:32] wire s_uop_11_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_2; // @[lsu.scala:252:32] wire s_uop_11_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_3; // @[lsu.scala:252:32] wire s_uop_11_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_0; // @[lsu.scala:252:32] wire s_uop_11_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_1; // @[lsu.scala:252:32] wire s_uop_11_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_2; // @[lsu.scala:252:32] wire s_uop_11_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_3; // @[lsu.scala:252:32] wire s_uop_11_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_4; // @[lsu.scala:252:32] wire s_uop_11_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_5; // @[lsu.scala:252:32] wire s_uop_11_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_6; // @[lsu.scala:252:32] wire s_uop_11_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_7; // @[lsu.scala:252:32] wire s_uop_11_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_8; // @[lsu.scala:252:32] wire s_uop_11_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_9; // @[lsu.scala:252:32] wire s_uop_11_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued; // @[lsu.scala:252:32] wire s_uop_11_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_11_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_11_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_8_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_11_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_9_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfb; // @[lsu.scala:252:32] wire s_uop_11_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fence; // @[lsu.scala:252:32] wire s_uop_11_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fencei; // @[lsu.scala:252:32] wire s_uop_11_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfence; // @[lsu.scala:252:32] wire s_uop_11_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_amo; // @[lsu.scala:252:32] wire s_uop_11_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_eret; // @[lsu.scala:252:32] wire s_uop_11_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_11_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rocc; // @[lsu.scala:252:32] wire s_uop_11_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_mov; // @[lsu.scala:252:32] wire s_uop_11_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_edge_inst; // @[lsu.scala:252:32] wire s_uop_11_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_9_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_11_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_taken; // @[lsu.scala:252:32] wire s_uop_11_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1324:37] wire uop_9_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_imm_rename; // @[lsu.scala:252:32] wire s_uop_11_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_9_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_11_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_8_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_11_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_9_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_11_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_11_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs1_busy; // @[lsu.scala:252:32] wire s_uop_11_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs2_busy; // @[lsu.scala:252:32] wire s_uop_11_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs3_busy; // @[lsu.scala:252:32] wire s_uop_11_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ppred_busy; // @[lsu.scala:252:32] wire s_uop_11_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_exception; // @[lsu.scala:252:32] wire s_uop_11_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1324:37] wire uop_9_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_8_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_11_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_9_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_11_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_11_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_mem_signed; // @[lsu.scala:252:32] wire s_uop_11_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_9_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_ldq; // @[lsu.scala:252:32] wire s_uop_11_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_stq; // @[lsu.scala:252:32] wire s_uop_11_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_unique; // @[lsu.scala:252:32] wire s_uop_11_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_11_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_9_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_11_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_11_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_9_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_11_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_frs3_en; // @[lsu.scala:252:32] wire s_uop_11_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_9_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fcn_dw; // @[lsu.scala:252:32] wire s_uop_11_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_9_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_11_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_val; // @[lsu.scala:252:32] wire s_uop_11_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_11_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_11_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_11_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rvc; // @[lsu.scala:252:32] wire s_uop_12_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_9_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_12_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_10_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_0; // @[lsu.scala:252:32] wire s_uop_12_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_1; // @[lsu.scala:252:32] wire s_uop_12_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_2; // @[lsu.scala:252:32] wire s_uop_12_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_3; // @[lsu.scala:252:32] wire s_uop_12_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_0; // @[lsu.scala:252:32] wire s_uop_12_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_1; // @[lsu.scala:252:32] wire s_uop_12_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_2; // @[lsu.scala:252:32] wire s_uop_12_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_3; // @[lsu.scala:252:32] wire s_uop_12_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_4; // @[lsu.scala:252:32] wire s_uop_12_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_5; // @[lsu.scala:252:32] wire s_uop_12_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_6; // @[lsu.scala:252:32] wire s_uop_12_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_7; // @[lsu.scala:252:32] wire s_uop_12_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_8; // @[lsu.scala:252:32] wire s_uop_12_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_9; // @[lsu.scala:252:32] wire s_uop_12_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued; // @[lsu.scala:252:32] wire s_uop_12_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_12_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_12_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_9_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_12_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_10_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfb; // @[lsu.scala:252:32] wire s_uop_12_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fence; // @[lsu.scala:252:32] wire s_uop_12_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fencei; // @[lsu.scala:252:32] wire s_uop_12_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfence; // @[lsu.scala:252:32] wire s_uop_12_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_amo; // @[lsu.scala:252:32] wire s_uop_12_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_eret; // @[lsu.scala:252:32] wire s_uop_12_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_12_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rocc; // @[lsu.scala:252:32] wire s_uop_12_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_mov; // @[lsu.scala:252:32] wire s_uop_12_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_edge_inst; // @[lsu.scala:252:32] wire s_uop_12_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_10_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_12_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_taken; // @[lsu.scala:252:32] wire s_uop_12_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1324:37] wire uop_10_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_imm_rename; // @[lsu.scala:252:32] wire s_uop_12_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_10_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_12_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_9_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_12_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_10_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_12_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_12_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs1_busy; // @[lsu.scala:252:32] wire s_uop_12_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs2_busy; // @[lsu.scala:252:32] wire s_uop_12_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs3_busy; // @[lsu.scala:252:32] wire s_uop_12_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ppred_busy; // @[lsu.scala:252:32] wire s_uop_12_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_exception; // @[lsu.scala:252:32] wire s_uop_12_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1324:37] wire uop_10_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_9_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_12_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_10_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_12_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_12_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_mem_signed; // @[lsu.scala:252:32] wire s_uop_12_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_10_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_ldq; // @[lsu.scala:252:32] wire s_uop_12_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_stq; // @[lsu.scala:252:32] wire s_uop_12_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_unique; // @[lsu.scala:252:32] wire s_uop_12_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_12_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_10_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_12_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_12_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_10_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_12_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_frs3_en; // @[lsu.scala:252:32] wire s_uop_12_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_10_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fcn_dw; // @[lsu.scala:252:32] wire s_uop_12_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_10_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_12_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_val; // @[lsu.scala:252:32] wire s_uop_12_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_12_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_12_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_12_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rvc; // @[lsu.scala:252:32] wire s_uop_13_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_10_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_13_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_11_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_0; // @[lsu.scala:252:32] wire s_uop_13_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_1; // @[lsu.scala:252:32] wire s_uop_13_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_2; // @[lsu.scala:252:32] wire s_uop_13_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_3; // @[lsu.scala:252:32] wire s_uop_13_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_0; // @[lsu.scala:252:32] wire s_uop_13_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_1; // @[lsu.scala:252:32] wire s_uop_13_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_2; // @[lsu.scala:252:32] wire s_uop_13_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_3; // @[lsu.scala:252:32] wire s_uop_13_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_4; // @[lsu.scala:252:32] wire s_uop_13_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_5; // @[lsu.scala:252:32] wire s_uop_13_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_6; // @[lsu.scala:252:32] wire s_uop_13_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_7; // @[lsu.scala:252:32] wire s_uop_13_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_8; // @[lsu.scala:252:32] wire s_uop_13_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_9; // @[lsu.scala:252:32] wire s_uop_13_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued; // @[lsu.scala:252:32] wire s_uop_13_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_13_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_13_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_10_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_13_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_11_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfb; // @[lsu.scala:252:32] wire s_uop_13_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fence; // @[lsu.scala:252:32] wire s_uop_13_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fencei; // @[lsu.scala:252:32] wire s_uop_13_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfence; // @[lsu.scala:252:32] wire s_uop_13_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_amo; // @[lsu.scala:252:32] wire s_uop_13_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_eret; // @[lsu.scala:252:32] wire s_uop_13_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_13_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rocc; // @[lsu.scala:252:32] wire s_uop_13_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_mov; // @[lsu.scala:252:32] wire s_uop_13_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_edge_inst; // @[lsu.scala:252:32] wire s_uop_13_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_11_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_13_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_taken; // @[lsu.scala:252:32] wire s_uop_13_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1324:37] wire uop_11_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_imm_rename; // @[lsu.scala:252:32] wire s_uop_13_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_11_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_13_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_10_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_13_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_11_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_13_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_13_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs1_busy; // @[lsu.scala:252:32] wire s_uop_13_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs2_busy; // @[lsu.scala:252:32] wire s_uop_13_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs3_busy; // @[lsu.scala:252:32] wire s_uop_13_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ppred_busy; // @[lsu.scala:252:32] wire s_uop_13_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_exception; // @[lsu.scala:252:32] wire s_uop_13_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1324:37] wire uop_11_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_10_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_13_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_11_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_13_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_13_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_mem_signed; // @[lsu.scala:252:32] wire s_uop_13_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_11_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_ldq; // @[lsu.scala:252:32] wire s_uop_13_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_stq; // @[lsu.scala:252:32] wire s_uop_13_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_unique; // @[lsu.scala:252:32] wire s_uop_13_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_13_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_11_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_13_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_13_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_11_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_13_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_frs3_en; // @[lsu.scala:252:32] wire s_uop_13_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_11_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fcn_dw; // @[lsu.scala:252:32] wire s_uop_13_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_11_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_13_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_val; // @[lsu.scala:252:32] wire s_uop_13_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_13_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_13_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_13_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rvc; // @[lsu.scala:252:32] wire s_uop_14_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_11_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_14_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_12_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_0; // @[lsu.scala:252:32] wire s_uop_14_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_1; // @[lsu.scala:252:32] wire s_uop_14_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_2; // @[lsu.scala:252:32] wire s_uop_14_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_3; // @[lsu.scala:252:32] wire s_uop_14_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_0; // @[lsu.scala:252:32] wire s_uop_14_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_1; // @[lsu.scala:252:32] wire s_uop_14_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_2; // @[lsu.scala:252:32] wire s_uop_14_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_3; // @[lsu.scala:252:32] wire s_uop_14_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_4; // @[lsu.scala:252:32] wire s_uop_14_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_5; // @[lsu.scala:252:32] wire s_uop_14_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_6; // @[lsu.scala:252:32] wire s_uop_14_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_7; // @[lsu.scala:252:32] wire s_uop_14_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_8; // @[lsu.scala:252:32] wire s_uop_14_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_9; // @[lsu.scala:252:32] wire s_uop_14_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued; // @[lsu.scala:252:32] wire s_uop_14_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_14_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_14_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_11_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_14_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_12_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfb; // @[lsu.scala:252:32] wire s_uop_14_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fence; // @[lsu.scala:252:32] wire s_uop_14_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fencei; // @[lsu.scala:252:32] wire s_uop_14_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfence; // @[lsu.scala:252:32] wire s_uop_14_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_amo; // @[lsu.scala:252:32] wire s_uop_14_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_eret; // @[lsu.scala:252:32] wire s_uop_14_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_14_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rocc; // @[lsu.scala:252:32] wire s_uop_14_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_mov; // @[lsu.scala:252:32] wire s_uop_14_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_edge_inst; // @[lsu.scala:252:32] wire s_uop_14_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_12_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_14_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_taken; // @[lsu.scala:252:32] wire s_uop_14_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1324:37] wire uop_12_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_imm_rename; // @[lsu.scala:252:32] wire s_uop_14_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_12_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_14_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_11_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_14_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_12_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_14_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_14_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs1_busy; // @[lsu.scala:252:32] wire s_uop_14_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs2_busy; // @[lsu.scala:252:32] wire s_uop_14_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs3_busy; // @[lsu.scala:252:32] wire s_uop_14_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ppred_busy; // @[lsu.scala:252:32] wire s_uop_14_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_exception; // @[lsu.scala:252:32] wire s_uop_14_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1324:37] wire uop_12_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_11_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_14_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_12_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_14_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_14_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_mem_signed; // @[lsu.scala:252:32] wire s_uop_14_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_12_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_ldq; // @[lsu.scala:252:32] wire s_uop_14_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_stq; // @[lsu.scala:252:32] wire s_uop_14_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_unique; // @[lsu.scala:252:32] wire s_uop_14_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_14_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_12_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_14_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_14_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_12_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_14_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_frs3_en; // @[lsu.scala:252:32] wire s_uop_14_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_12_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fcn_dw; // @[lsu.scala:252:32] wire s_uop_14_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_12_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_14_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_val; // @[lsu.scala:252:32] wire s_uop_14_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_14_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_14_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_14_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rvc; // @[lsu.scala:252:32] wire s_uop_15_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_12_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_15_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_13_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_0; // @[lsu.scala:252:32] wire s_uop_15_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_1; // @[lsu.scala:252:32] wire s_uop_15_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_2; // @[lsu.scala:252:32] wire s_uop_15_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_3; // @[lsu.scala:252:32] wire s_uop_15_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_0; // @[lsu.scala:252:32] wire s_uop_15_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_1; // @[lsu.scala:252:32] wire s_uop_15_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_2; // @[lsu.scala:252:32] wire s_uop_15_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_3; // @[lsu.scala:252:32] wire s_uop_15_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_4; // @[lsu.scala:252:32] wire s_uop_15_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_5; // @[lsu.scala:252:32] wire s_uop_15_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_6; // @[lsu.scala:252:32] wire s_uop_15_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_7; // @[lsu.scala:252:32] wire s_uop_15_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_8; // @[lsu.scala:252:32] wire s_uop_15_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_9; // @[lsu.scala:252:32] wire s_uop_15_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued; // @[lsu.scala:252:32] wire s_uop_15_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_15_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_15_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_12_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_15_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_13_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfb; // @[lsu.scala:252:32] wire s_uop_15_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fence; // @[lsu.scala:252:32] wire s_uop_15_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fencei; // @[lsu.scala:252:32] wire s_uop_15_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfence; // @[lsu.scala:252:32] wire s_uop_15_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_amo; // @[lsu.scala:252:32] wire s_uop_15_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_eret; // @[lsu.scala:252:32] wire s_uop_15_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_15_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rocc; // @[lsu.scala:252:32] wire s_uop_15_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_mov; // @[lsu.scala:252:32] wire s_uop_15_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_edge_inst; // @[lsu.scala:252:32] wire s_uop_15_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_13_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_15_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_taken; // @[lsu.scala:252:32] wire s_uop_15_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1324:37] wire uop_13_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_imm_rename; // @[lsu.scala:252:32] wire s_uop_15_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_13_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_15_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_12_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_15_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_13_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_15_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_15_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs1_busy; // @[lsu.scala:252:32] wire s_uop_15_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs2_busy; // @[lsu.scala:252:32] wire s_uop_15_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs3_busy; // @[lsu.scala:252:32] wire s_uop_15_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ppred_busy; // @[lsu.scala:252:32] wire s_uop_15_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_exception; // @[lsu.scala:252:32] wire s_uop_15_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1324:37] wire uop_13_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_12_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_15_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_13_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_15_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_15_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_mem_signed; // @[lsu.scala:252:32] wire s_uop_15_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_13_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_ldq; // @[lsu.scala:252:32] wire s_uop_15_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_stq; // @[lsu.scala:252:32] wire s_uop_15_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_unique; // @[lsu.scala:252:32] wire s_uop_15_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_15_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_13_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_15_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_15_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_13_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_15_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_frs3_en; // @[lsu.scala:252:32] wire s_uop_15_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_13_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fcn_dw; // @[lsu.scala:252:32] wire s_uop_15_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_13_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_15_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_val; // @[lsu.scala:252:32] wire s_uop_15_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_15_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_15_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_15_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rvc; // @[lsu.scala:252:32] wire s_uop_16_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_13_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_16_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_14_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_0; // @[lsu.scala:252:32] wire s_uop_16_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_1; // @[lsu.scala:252:32] wire s_uop_16_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_2; // @[lsu.scala:252:32] wire s_uop_16_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_3; // @[lsu.scala:252:32] wire s_uop_16_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_0; // @[lsu.scala:252:32] wire s_uop_16_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_1; // @[lsu.scala:252:32] wire s_uop_16_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_2; // @[lsu.scala:252:32] wire s_uop_16_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_3; // @[lsu.scala:252:32] wire s_uop_16_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_4; // @[lsu.scala:252:32] wire s_uop_16_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_5; // @[lsu.scala:252:32] wire s_uop_16_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_6; // @[lsu.scala:252:32] wire s_uop_16_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_7; // @[lsu.scala:252:32] wire s_uop_16_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_8; // @[lsu.scala:252:32] wire s_uop_16_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_9; // @[lsu.scala:252:32] wire s_uop_16_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued; // @[lsu.scala:252:32] wire s_uop_16_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_16_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_16_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_13_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_16_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_14_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfb; // @[lsu.scala:252:32] wire s_uop_16_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fence; // @[lsu.scala:252:32] wire s_uop_16_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fencei; // @[lsu.scala:252:32] wire s_uop_16_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfence; // @[lsu.scala:252:32] wire s_uop_16_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_amo; // @[lsu.scala:252:32] wire s_uop_16_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_eret; // @[lsu.scala:252:32] wire s_uop_16_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_16_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rocc; // @[lsu.scala:252:32] wire s_uop_16_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_mov; // @[lsu.scala:252:32] wire s_uop_16_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_edge_inst; // @[lsu.scala:252:32] wire s_uop_16_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_14_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_16_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_taken; // @[lsu.scala:252:32] wire s_uop_16_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1324:37] wire uop_14_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_imm_rename; // @[lsu.scala:252:32] wire s_uop_16_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_14_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_16_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_13_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_16_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_14_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_16_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_16_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs1_busy; // @[lsu.scala:252:32] wire s_uop_16_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs2_busy; // @[lsu.scala:252:32] wire s_uop_16_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs3_busy; // @[lsu.scala:252:32] wire s_uop_16_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ppred_busy; // @[lsu.scala:252:32] wire s_uop_16_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_exception; // @[lsu.scala:252:32] wire s_uop_16_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1324:37] wire uop_14_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_13_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_16_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_14_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_16_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_16_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_mem_signed; // @[lsu.scala:252:32] wire s_uop_16_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_14_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_ldq; // @[lsu.scala:252:32] wire s_uop_16_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_stq; // @[lsu.scala:252:32] wire s_uop_16_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_unique; // @[lsu.scala:252:32] wire s_uop_16_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_16_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_14_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_16_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_16_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_14_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_16_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_frs3_en; // @[lsu.scala:252:32] wire s_uop_16_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_14_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fcn_dw; // @[lsu.scala:252:32] wire s_uop_16_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_14_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_16_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_val; // @[lsu.scala:252:32] wire s_uop_16_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_16_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_16_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_16_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rvc; // @[lsu.scala:252:32] wire s_uop_17_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_14_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_17_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_15_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_0; // @[lsu.scala:252:32] wire s_uop_17_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_1; // @[lsu.scala:252:32] wire s_uop_17_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_2; // @[lsu.scala:252:32] wire s_uop_17_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_3; // @[lsu.scala:252:32] wire s_uop_17_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_0; // @[lsu.scala:252:32] wire s_uop_17_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_1; // @[lsu.scala:252:32] wire s_uop_17_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_2; // @[lsu.scala:252:32] wire s_uop_17_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_3; // @[lsu.scala:252:32] wire s_uop_17_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_4; // @[lsu.scala:252:32] wire s_uop_17_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_5; // @[lsu.scala:252:32] wire s_uop_17_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_6; // @[lsu.scala:252:32] wire s_uop_17_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_7; // @[lsu.scala:252:32] wire s_uop_17_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_8; // @[lsu.scala:252:32] wire s_uop_17_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_9; // @[lsu.scala:252:32] wire s_uop_17_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued; // @[lsu.scala:252:32] wire s_uop_17_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_17_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_17_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_14_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_17_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_15_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfb; // @[lsu.scala:252:32] wire s_uop_17_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fence; // @[lsu.scala:252:32] wire s_uop_17_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fencei; // @[lsu.scala:252:32] wire s_uop_17_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfence; // @[lsu.scala:252:32] wire s_uop_17_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_amo; // @[lsu.scala:252:32] wire s_uop_17_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_eret; // @[lsu.scala:252:32] wire s_uop_17_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_17_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rocc; // @[lsu.scala:252:32] wire s_uop_17_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_mov; // @[lsu.scala:252:32] wire s_uop_17_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_edge_inst; // @[lsu.scala:252:32] wire s_uop_17_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_15_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_17_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_taken; // @[lsu.scala:252:32] wire s_uop_17_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1324:37] wire uop_15_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_imm_rename; // @[lsu.scala:252:32] wire s_uop_17_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_15_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_17_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_14_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_17_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_15_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_17_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_17_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs1_busy; // @[lsu.scala:252:32] wire s_uop_17_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs2_busy; // @[lsu.scala:252:32] wire s_uop_17_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs3_busy; // @[lsu.scala:252:32] wire s_uop_17_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ppred_busy; // @[lsu.scala:252:32] wire s_uop_17_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_exception; // @[lsu.scala:252:32] wire s_uop_17_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1324:37] wire uop_15_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_14_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_17_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_15_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_17_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_17_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_mem_signed; // @[lsu.scala:252:32] wire s_uop_17_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_15_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_ldq; // @[lsu.scala:252:32] wire s_uop_17_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_stq; // @[lsu.scala:252:32] wire s_uop_17_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_unique; // @[lsu.scala:252:32] wire s_uop_17_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_17_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_15_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_17_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_17_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_15_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_17_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_frs3_en; // @[lsu.scala:252:32] wire s_uop_17_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_15_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fcn_dw; // @[lsu.scala:252:32] wire s_uop_17_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_15_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_17_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_val; // @[lsu.scala:252:32] wire s_uop_17_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_17_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_17_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_17_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_18_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_18_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rvc; // @[lsu.scala:252:32] wire s_uop_18_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_15_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_18_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_16_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_0; // @[lsu.scala:252:32] wire s_uop_18_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_1; // @[lsu.scala:252:32] wire s_uop_18_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_2; // @[lsu.scala:252:32] wire s_uop_18_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_3; // @[lsu.scala:252:32] wire s_uop_18_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_0; // @[lsu.scala:252:32] wire s_uop_18_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_1; // @[lsu.scala:252:32] wire s_uop_18_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_2; // @[lsu.scala:252:32] wire s_uop_18_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_3; // @[lsu.scala:252:32] wire s_uop_18_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_4; // @[lsu.scala:252:32] wire s_uop_18_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_5; // @[lsu.scala:252:32] wire s_uop_18_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_6; // @[lsu.scala:252:32] wire s_uop_18_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_7; // @[lsu.scala:252:32] wire s_uop_18_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_8; // @[lsu.scala:252:32] wire s_uop_18_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_9; // @[lsu.scala:252:32] wire s_uop_18_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued; // @[lsu.scala:252:32] wire s_uop_18_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_18_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_18_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_18_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_18_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_15_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_18_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_16_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_18_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_18_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfb; // @[lsu.scala:252:32] wire s_uop_18_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fence; // @[lsu.scala:252:32] wire s_uop_18_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fencei; // @[lsu.scala:252:32] wire s_uop_18_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfence; // @[lsu.scala:252:32] wire s_uop_18_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_amo; // @[lsu.scala:252:32] wire s_uop_18_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_eret; // @[lsu.scala:252:32] wire s_uop_18_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_18_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rocc; // @[lsu.scala:252:32] wire s_uop_18_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_mov; // @[lsu.scala:252:32] wire s_uop_18_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_edge_inst; // @[lsu.scala:252:32] wire s_uop_18_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_16_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_18_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_taken; // @[lsu.scala:252:32] wire s_uop_18_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1324:37] wire uop_16_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_imm_rename; // @[lsu.scala:252:32] wire s_uop_18_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_16_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_18_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_15_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_18_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_16_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_18_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_18_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_18_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_18_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs1_busy; // @[lsu.scala:252:32] wire s_uop_18_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs2_busy; // @[lsu.scala:252:32] wire s_uop_18_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs3_busy; // @[lsu.scala:252:32] wire s_uop_18_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ppred_busy; // @[lsu.scala:252:32] wire s_uop_18_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_18_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_exception; // @[lsu.scala:252:32] wire s_uop_18_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1324:37] wire uop_16_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_15_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_18_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_16_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_18_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_18_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_mem_signed; // @[lsu.scala:252:32] wire s_uop_18_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_16_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_ldq; // @[lsu.scala:252:32] wire s_uop_18_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_stq; // @[lsu.scala:252:32] wire s_uop_18_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_unique; // @[lsu.scala:252:32] wire s_uop_18_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_18_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_16_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_18_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_18_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_16_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_18_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_frs3_en; // @[lsu.scala:252:32] wire s_uop_18_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_16_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fcn_dw; // @[lsu.scala:252:32] wire s_uop_18_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_16_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_18_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_val; // @[lsu.scala:252:32] wire s_uop_18_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_18_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_18_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_18_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_18_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_18_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_16_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_19_inst = stq_uop_16_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_17_inst = stq_uop_16_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_16_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_19_debug_inst = stq_uop_16_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_17_debug_inst = stq_uop_16_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_rvc; // @[lsu.scala:252:32] wire s_uop_19_is_rvc = stq_uop_16_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_rvc = stq_uop_16_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_16_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_19_debug_pc = stq_uop_16_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_17_debug_pc = stq_uop_16_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_0; // @[lsu.scala:252:32] wire s_uop_19_iq_type_0 = stq_uop_16_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_0 = stq_uop_16_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_1; // @[lsu.scala:252:32] wire s_uop_19_iq_type_1 = stq_uop_16_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_1 = stq_uop_16_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_2; // @[lsu.scala:252:32] wire s_uop_19_iq_type_2 = stq_uop_16_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_2 = stq_uop_16_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_3; // @[lsu.scala:252:32] wire s_uop_19_iq_type_3 = stq_uop_16_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_3 = stq_uop_16_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_0; // @[lsu.scala:252:32] wire s_uop_19_fu_code_0 = stq_uop_16_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_0 = stq_uop_16_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_1; // @[lsu.scala:252:32] wire s_uop_19_fu_code_1 = stq_uop_16_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_1 = stq_uop_16_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_2; // @[lsu.scala:252:32] wire s_uop_19_fu_code_2 = stq_uop_16_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_2 = stq_uop_16_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_3; // @[lsu.scala:252:32] wire s_uop_19_fu_code_3 = stq_uop_16_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_3 = stq_uop_16_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_4; // @[lsu.scala:252:32] wire s_uop_19_fu_code_4 = stq_uop_16_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_4 = stq_uop_16_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_5; // @[lsu.scala:252:32] wire s_uop_19_fu_code_5 = stq_uop_16_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_5 = stq_uop_16_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_6; // @[lsu.scala:252:32] wire s_uop_19_fu_code_6 = stq_uop_16_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_6 = stq_uop_16_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_7; // @[lsu.scala:252:32] wire s_uop_19_fu_code_7 = stq_uop_16_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_7 = stq_uop_16_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_8; // @[lsu.scala:252:32] wire s_uop_19_fu_code_8 = stq_uop_16_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_8 = stq_uop_16_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_9; // @[lsu.scala:252:32] wire s_uop_19_fu_code_9 = stq_uop_16_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_9 = stq_uop_16_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued; // @[lsu.scala:252:32] wire s_uop_19_iw_issued = stq_uop_16_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued = stq_uop_16_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_19_iw_issued_partial_agen = stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued_partial_agen = stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_19_iw_issued_partial_dgen = stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued_partial_dgen = stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_19_iw_p1_speculative_child = stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_iw_p1_speculative_child = stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_19_iw_p2_speculative_child = stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_iw_p2_speculative_child = stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p1_bypass_hint = stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p1_bypass_hint = stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p2_bypass_hint = stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p2_bypass_hint = stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p3_bypass_hint = stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p3_bypass_hint = stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_dis_col_sel = stq_uop_16_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_dis_col_sel = stq_uop_16_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_16_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_19_br_mask = stq_uop_16_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_17_br_mask = stq_uop_16_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_16_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_19_br_tag = stq_uop_16_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_17_br_tag = stq_uop_16_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_16_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_19_br_type = stq_uop_16_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_17_br_type = stq_uop_16_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sfb; // @[lsu.scala:252:32] wire s_uop_19_is_sfb = stq_uop_16_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sfb = stq_uop_16_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_fence; // @[lsu.scala:252:32] wire s_uop_19_is_fence = stq_uop_16_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_fence = stq_uop_16_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_fencei; // @[lsu.scala:252:32] wire s_uop_19_is_fencei = stq_uop_16_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_fencei = stq_uop_16_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sfence; // @[lsu.scala:252:32] wire s_uop_19_is_sfence = stq_uop_16_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sfence = stq_uop_16_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_amo; // @[lsu.scala:252:32] wire s_uop_19_is_amo = stq_uop_16_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_amo = stq_uop_16_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_eret; // @[lsu.scala:252:32] wire s_uop_19_is_eret = stq_uop_16_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_eret = stq_uop_16_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_19_is_sys_pc2epc = stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sys_pc2epc = stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_rocc; // @[lsu.scala:252:32] wire s_uop_19_is_rocc = stq_uop_16_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_rocc = stq_uop_16_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_mov; // @[lsu.scala:252:32] wire s_uop_19_is_mov = stq_uop_16_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_mov = stq_uop_16_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ftq_idx = stq_uop_16_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ftq_idx = stq_uop_16_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_edge_inst; // @[lsu.scala:252:32] wire s_uop_19_edge_inst = stq_uop_16_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_17_edge_inst = stq_uop_16_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_19_pc_lob = stq_uop_16_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_pc_lob = stq_uop_16_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_taken; // @[lsu.scala:252:32] wire s_uop_19_taken = stq_uop_16_taken; // @[lsu.scala:252:32, :1324:37] wire uop_17_taken = stq_uop_16_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_imm_rename; // @[lsu.scala:252:32] wire s_uop_19_imm_rename = stq_uop_16_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_17_imm_rename = stq_uop_16_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_imm_sel = stq_uop_16_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_imm_sel = stq_uop_16_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_19_pimm = stq_uop_16_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_pimm = stq_uop_16_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_16_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_19_imm_packed = stq_uop_16_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_17_imm_packed = stq_uop_16_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_19_op1_sel = stq_uop_16_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_op1_sel = stq_uop_16_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_op2_sel = stq_uop_16_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_op2_sel = stq_uop_16_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ldst = stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ldst = stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_wen = stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_wen = stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren1 = stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren1 = stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren2 = stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren2 = stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren3 = stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren3 = stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_swap12 = stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_swap12 = stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_swap23 = stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_swap23 = stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_ctrl_typeTagIn = stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_ctrl_typeTagIn = stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_ctrl_typeTagOut = stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_ctrl_typeTagOut = stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fromint = stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fromint = stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_toint = stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_toint = stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fastpipe = stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fastpipe = stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fma = stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fma = stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_div = stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_div = stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_sqrt = stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_sqrt = stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_wflags = stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_wflags = stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_vec = stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_vec = stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_19_rob_idx = stq_uop_16_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_rob_idx = stq_uop_16_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ldq_idx = stq_uop_16_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ldq_idx = stq_uop_16_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_stq_idx = stq_uop_16_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_stq_idx = stq_uop_16_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_19_rxq_idx = stq_uop_16_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_rxq_idx = stq_uop_16_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_19_pdst = stq_uop_16_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_pdst = stq_uop_16_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs1 = stq_uop_16_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs1 = stq_uop_16_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs2 = stq_uop_16_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs2 = stq_uop_16_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs3 = stq_uop_16_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs3 = stq_uop_16_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ppred = stq_uop_16_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ppred = stq_uop_16_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs1_busy; // @[lsu.scala:252:32] wire s_uop_19_prs1_busy = stq_uop_16_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs1_busy = stq_uop_16_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs2_busy; // @[lsu.scala:252:32] wire s_uop_19_prs2_busy = stq_uop_16_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs2_busy = stq_uop_16_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs3_busy; // @[lsu.scala:252:32] wire s_uop_19_prs3_busy = stq_uop_16_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs3_busy = stq_uop_16_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_ppred_busy; // @[lsu.scala:252:32] wire s_uop_19_ppred_busy = stq_uop_16_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_ppred_busy = stq_uop_16_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_19_stale_pdst = stq_uop_16_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_stale_pdst = stq_uop_16_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_exception; // @[lsu.scala:252:32] wire s_uop_19_exception = stq_uop_16_exception; // @[lsu.scala:252:32, :1324:37] wire uop_17_exception = stq_uop_16_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_16_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_19_exc_cause = stq_uop_16_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_17_exc_cause = stq_uop_16_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_19_mem_cmd = stq_uop_16_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_mem_cmd = stq_uop_16_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_19_mem_size = stq_uop_16_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_mem_size = stq_uop_16_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_mem_signed; // @[lsu.scala:252:32] wire s_uop_19_mem_signed = stq_uop_16_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_17_mem_signed = stq_uop_16_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_uses_ldq; // @[lsu.scala:252:32] wire s_uop_19_uses_ldq = stq_uop_16_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_17_uses_ldq = stq_uop_16_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_uses_stq; // @[lsu.scala:252:32] wire s_uop_19_uses_stq = stq_uop_16_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_17_uses_stq = stq_uop_16_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_unique; // @[lsu.scala:252:32] wire s_uop_19_is_unique = stq_uop_16_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_unique = stq_uop_16_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_19_flush_on_commit = stq_uop_16_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_17_flush_on_commit = stq_uop_16_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_19_csr_cmd = stq_uop_16_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_csr_cmd = stq_uop_16_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_19_ldst_is_rs1 = stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_17_ldst_is_rs1 = stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_19_ldst = stq_uop_16_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_ldst = stq_uop_16_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs1 = stq_uop_16_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs1 = stq_uop_16_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs2 = stq_uop_16_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs2 = stq_uop_16_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs3 = stq_uop_16_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs3 = stq_uop_16_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_dst_rtype = stq_uop_16_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_dst_rtype = stq_uop_16_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_lrs1_rtype = stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_lrs1_rtype = stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_lrs2_rtype = stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_lrs2_rtype = stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_frs3_en; // @[lsu.scala:252:32] wire s_uop_19_frs3_en = stq_uop_16_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_17_frs3_en = stq_uop_16_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fcn_dw; // @[lsu.scala:252:32] wire s_uop_19_fcn_dw = stq_uop_16_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_17_fcn_dw = stq_uop_16_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_19_fcn_op = stq_uop_16_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_fcn_op = stq_uop_16_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_val; // @[lsu.scala:252:32] wire s_uop_19_fp_val = stq_uop_16_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_val = stq_uop_16_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_19_fp_rm = stq_uop_16_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_fp_rm = stq_uop_16_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_typ = stq_uop_16_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_typ = stq_uop_16_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_pf_if = stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_pf_if = stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_ae_if = stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_ae_if = stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_ma_if = stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_ma_if = stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_19_bp_debug_if = stq_uop_16_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_bp_debug_if = stq_uop_16_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_19_bp_xcpt_if = stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_bp_xcpt_if = stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_19_debug_fsrc = stq_uop_16_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_debug_fsrc = stq_uop_16_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_19_debug_tsrc = stq_uop_16_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_debug_tsrc = stq_uop_16_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_17_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_20_inst = stq_uop_17_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_18_inst = stq_uop_17_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_17_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_20_debug_inst = stq_uop_17_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_18_debug_inst = stq_uop_17_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_rvc; // @[lsu.scala:252:32] wire s_uop_20_is_rvc = stq_uop_17_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_rvc = stq_uop_17_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_17_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_20_debug_pc = stq_uop_17_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_18_debug_pc = stq_uop_17_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_0; // @[lsu.scala:252:32] wire s_uop_20_iq_type_0 = stq_uop_17_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_0 = stq_uop_17_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_1; // @[lsu.scala:252:32] wire s_uop_20_iq_type_1 = stq_uop_17_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_1 = stq_uop_17_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_2; // @[lsu.scala:252:32] wire s_uop_20_iq_type_2 = stq_uop_17_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_2 = stq_uop_17_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_3; // @[lsu.scala:252:32] wire s_uop_20_iq_type_3 = stq_uop_17_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_3 = stq_uop_17_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_0; // @[lsu.scala:252:32] wire s_uop_20_fu_code_0 = stq_uop_17_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_0 = stq_uop_17_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_1; // @[lsu.scala:252:32] wire s_uop_20_fu_code_1 = stq_uop_17_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_1 = stq_uop_17_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_2; // @[lsu.scala:252:32] wire s_uop_20_fu_code_2 = stq_uop_17_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_2 = stq_uop_17_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_3; // @[lsu.scala:252:32] wire s_uop_20_fu_code_3 = stq_uop_17_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_3 = stq_uop_17_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_4; // @[lsu.scala:252:32] wire s_uop_20_fu_code_4 = stq_uop_17_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_4 = stq_uop_17_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_5; // @[lsu.scala:252:32] wire s_uop_20_fu_code_5 = stq_uop_17_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_5 = stq_uop_17_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_6; // @[lsu.scala:252:32] wire s_uop_20_fu_code_6 = stq_uop_17_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_6 = stq_uop_17_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_7; // @[lsu.scala:252:32] wire s_uop_20_fu_code_7 = stq_uop_17_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_7 = stq_uop_17_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_8; // @[lsu.scala:252:32] wire s_uop_20_fu_code_8 = stq_uop_17_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_8 = stq_uop_17_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_9; // @[lsu.scala:252:32] wire s_uop_20_fu_code_9 = stq_uop_17_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_9 = stq_uop_17_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued; // @[lsu.scala:252:32] wire s_uop_20_iw_issued = stq_uop_17_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued = stq_uop_17_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_20_iw_issued_partial_agen = stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued_partial_agen = stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_20_iw_issued_partial_dgen = stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued_partial_dgen = stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_20_iw_p1_speculative_child = stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_iw_p1_speculative_child = stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_20_iw_p2_speculative_child = stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_iw_p2_speculative_child = stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p1_bypass_hint = stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p1_bypass_hint = stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p2_bypass_hint = stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p2_bypass_hint = stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p3_bypass_hint = stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p3_bypass_hint = stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_dis_col_sel = stq_uop_17_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_dis_col_sel = stq_uop_17_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_17_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_20_br_mask = stq_uop_17_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_18_br_mask = stq_uop_17_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_17_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_20_br_tag = stq_uop_17_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_18_br_tag = stq_uop_17_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_17_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_20_br_type = stq_uop_17_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_18_br_type = stq_uop_17_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sfb; // @[lsu.scala:252:32] wire s_uop_20_is_sfb = stq_uop_17_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sfb = stq_uop_17_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_fence; // @[lsu.scala:252:32] wire s_uop_20_is_fence = stq_uop_17_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_fence = stq_uop_17_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_fencei; // @[lsu.scala:252:32] wire s_uop_20_is_fencei = stq_uop_17_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_fencei = stq_uop_17_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sfence; // @[lsu.scala:252:32] wire s_uop_20_is_sfence = stq_uop_17_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sfence = stq_uop_17_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_amo; // @[lsu.scala:252:32] wire s_uop_20_is_amo = stq_uop_17_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_amo = stq_uop_17_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_eret; // @[lsu.scala:252:32] wire s_uop_20_is_eret = stq_uop_17_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_eret = stq_uop_17_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_20_is_sys_pc2epc = stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sys_pc2epc = stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_rocc; // @[lsu.scala:252:32] wire s_uop_20_is_rocc = stq_uop_17_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_rocc = stq_uop_17_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_mov; // @[lsu.scala:252:32] wire s_uop_20_is_mov = stq_uop_17_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_mov = stq_uop_17_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ftq_idx = stq_uop_17_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ftq_idx = stq_uop_17_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_edge_inst; // @[lsu.scala:252:32] wire s_uop_20_edge_inst = stq_uop_17_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_18_edge_inst = stq_uop_17_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_20_pc_lob = stq_uop_17_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_pc_lob = stq_uop_17_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_taken; // @[lsu.scala:252:32] wire s_uop_20_taken = stq_uop_17_taken; // @[lsu.scala:252:32, :1324:37] wire uop_18_taken = stq_uop_17_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_imm_rename; // @[lsu.scala:252:32] wire s_uop_20_imm_rename = stq_uop_17_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_18_imm_rename = stq_uop_17_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_imm_sel = stq_uop_17_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_imm_sel = stq_uop_17_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_20_pimm = stq_uop_17_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_pimm = stq_uop_17_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_17_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_20_imm_packed = stq_uop_17_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_18_imm_packed = stq_uop_17_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_20_op1_sel = stq_uop_17_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_op1_sel = stq_uop_17_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_op2_sel = stq_uop_17_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_op2_sel = stq_uop_17_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ldst = stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ldst = stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_wen = stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_wen = stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren1 = stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren1 = stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren2 = stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren2 = stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren3 = stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren3 = stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_swap12 = stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_swap12 = stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_swap23 = stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_swap23 = stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_ctrl_typeTagIn = stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_ctrl_typeTagIn = stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_ctrl_typeTagOut = stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_ctrl_typeTagOut = stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fromint = stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fromint = stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_toint = stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_toint = stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fastpipe = stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fastpipe = stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fma = stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fma = stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_div = stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_div = stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_sqrt = stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_sqrt = stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_wflags = stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_wflags = stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_vec = stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_vec = stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_20_rob_idx = stq_uop_17_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_rob_idx = stq_uop_17_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ldq_idx = stq_uop_17_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ldq_idx = stq_uop_17_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_stq_idx = stq_uop_17_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_stq_idx = stq_uop_17_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_20_rxq_idx = stq_uop_17_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_rxq_idx = stq_uop_17_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_20_pdst = stq_uop_17_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_pdst = stq_uop_17_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs1 = stq_uop_17_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs1 = stq_uop_17_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs2 = stq_uop_17_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs2 = stq_uop_17_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs3 = stq_uop_17_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs3 = stq_uop_17_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ppred = stq_uop_17_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ppred = stq_uop_17_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs1_busy; // @[lsu.scala:252:32] wire s_uop_20_prs1_busy = stq_uop_17_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs1_busy = stq_uop_17_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs2_busy; // @[lsu.scala:252:32] wire s_uop_20_prs2_busy = stq_uop_17_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs2_busy = stq_uop_17_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs3_busy; // @[lsu.scala:252:32] wire s_uop_20_prs3_busy = stq_uop_17_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs3_busy = stq_uop_17_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_ppred_busy; // @[lsu.scala:252:32] wire s_uop_20_ppred_busy = stq_uop_17_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_ppred_busy = stq_uop_17_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_20_stale_pdst = stq_uop_17_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_stale_pdst = stq_uop_17_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_exception; // @[lsu.scala:252:32] wire s_uop_20_exception = stq_uop_17_exception; // @[lsu.scala:252:32, :1324:37] wire uop_18_exception = stq_uop_17_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_17_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_20_exc_cause = stq_uop_17_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_18_exc_cause = stq_uop_17_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_20_mem_cmd = stq_uop_17_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_mem_cmd = stq_uop_17_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_20_mem_size = stq_uop_17_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_mem_size = stq_uop_17_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_mem_signed; // @[lsu.scala:252:32] wire s_uop_20_mem_signed = stq_uop_17_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_18_mem_signed = stq_uop_17_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_uses_ldq; // @[lsu.scala:252:32] wire s_uop_20_uses_ldq = stq_uop_17_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_18_uses_ldq = stq_uop_17_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_uses_stq; // @[lsu.scala:252:32] wire s_uop_20_uses_stq = stq_uop_17_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_18_uses_stq = stq_uop_17_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_unique; // @[lsu.scala:252:32] wire s_uop_20_is_unique = stq_uop_17_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_unique = stq_uop_17_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_20_flush_on_commit = stq_uop_17_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_18_flush_on_commit = stq_uop_17_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_20_csr_cmd = stq_uop_17_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_csr_cmd = stq_uop_17_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_20_ldst_is_rs1 = stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_18_ldst_is_rs1 = stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_20_ldst = stq_uop_17_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_ldst = stq_uop_17_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs1 = stq_uop_17_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs1 = stq_uop_17_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs2 = stq_uop_17_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs2 = stq_uop_17_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs3 = stq_uop_17_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs3 = stq_uop_17_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_dst_rtype = stq_uop_17_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_dst_rtype = stq_uop_17_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_lrs1_rtype = stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_lrs1_rtype = stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_lrs2_rtype = stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_lrs2_rtype = stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_frs3_en; // @[lsu.scala:252:32] wire s_uop_20_frs3_en = stq_uop_17_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_18_frs3_en = stq_uop_17_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fcn_dw; // @[lsu.scala:252:32] wire s_uop_20_fcn_dw = stq_uop_17_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_18_fcn_dw = stq_uop_17_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_20_fcn_op = stq_uop_17_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_fcn_op = stq_uop_17_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_val; // @[lsu.scala:252:32] wire s_uop_20_fp_val = stq_uop_17_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_val = stq_uop_17_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_20_fp_rm = stq_uop_17_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_fp_rm = stq_uop_17_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_typ = stq_uop_17_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_typ = stq_uop_17_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_pf_if = stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_pf_if = stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_ae_if = stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_ae_if = stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_ma_if = stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_ma_if = stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_20_bp_debug_if = stq_uop_17_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_bp_debug_if = stq_uop_17_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_20_bp_xcpt_if = stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_bp_xcpt_if = stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_20_debug_fsrc = stq_uop_17_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_debug_fsrc = stq_uop_17_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_20_debug_tsrc = stq_uop_17_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_debug_tsrc = stq_uop_17_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_18_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_21_inst = stq_uop_18_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_19_inst = stq_uop_18_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_18_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_21_debug_inst = stq_uop_18_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_19_debug_inst = stq_uop_18_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_rvc; // @[lsu.scala:252:32] wire s_uop_21_is_rvc = stq_uop_18_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_rvc = stq_uop_18_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_18_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_21_debug_pc = stq_uop_18_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_19_debug_pc = stq_uop_18_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_0; // @[lsu.scala:252:32] wire s_uop_21_iq_type_0 = stq_uop_18_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_0 = stq_uop_18_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_1; // @[lsu.scala:252:32] wire s_uop_21_iq_type_1 = stq_uop_18_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_1 = stq_uop_18_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_2; // @[lsu.scala:252:32] wire s_uop_21_iq_type_2 = stq_uop_18_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_2 = stq_uop_18_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_3; // @[lsu.scala:252:32] wire s_uop_21_iq_type_3 = stq_uop_18_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_3 = stq_uop_18_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_0; // @[lsu.scala:252:32] wire s_uop_21_fu_code_0 = stq_uop_18_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_0 = stq_uop_18_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_1; // @[lsu.scala:252:32] wire s_uop_21_fu_code_1 = stq_uop_18_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_1 = stq_uop_18_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_2; // @[lsu.scala:252:32] wire s_uop_21_fu_code_2 = stq_uop_18_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_2 = stq_uop_18_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_3; // @[lsu.scala:252:32] wire s_uop_21_fu_code_3 = stq_uop_18_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_3 = stq_uop_18_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_4; // @[lsu.scala:252:32] wire s_uop_21_fu_code_4 = stq_uop_18_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_4 = stq_uop_18_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_5; // @[lsu.scala:252:32] wire s_uop_21_fu_code_5 = stq_uop_18_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_5 = stq_uop_18_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_6; // @[lsu.scala:252:32] wire s_uop_21_fu_code_6 = stq_uop_18_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_6 = stq_uop_18_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_7; // @[lsu.scala:252:32] wire s_uop_21_fu_code_7 = stq_uop_18_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_7 = stq_uop_18_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_8; // @[lsu.scala:252:32] wire s_uop_21_fu_code_8 = stq_uop_18_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_8 = stq_uop_18_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_9; // @[lsu.scala:252:32] wire s_uop_21_fu_code_9 = stq_uop_18_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_9 = stq_uop_18_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued; // @[lsu.scala:252:32] wire s_uop_21_iw_issued = stq_uop_18_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued = stq_uop_18_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_21_iw_issued_partial_agen = stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued_partial_agen = stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_21_iw_issued_partial_dgen = stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued_partial_dgen = stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_21_iw_p1_speculative_child = stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_iw_p1_speculative_child = stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_21_iw_p2_speculative_child = stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_iw_p2_speculative_child = stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p1_bypass_hint = stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p1_bypass_hint = stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p2_bypass_hint = stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p2_bypass_hint = stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p3_bypass_hint = stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p3_bypass_hint = stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_dis_col_sel = stq_uop_18_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_dis_col_sel = stq_uop_18_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_18_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_21_br_mask = stq_uop_18_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_19_br_mask = stq_uop_18_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_18_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_21_br_tag = stq_uop_18_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_19_br_tag = stq_uop_18_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_18_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_21_br_type = stq_uop_18_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_19_br_type = stq_uop_18_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sfb; // @[lsu.scala:252:32] wire s_uop_21_is_sfb = stq_uop_18_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sfb = stq_uop_18_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_fence; // @[lsu.scala:252:32] wire s_uop_21_is_fence = stq_uop_18_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_fence = stq_uop_18_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_fencei; // @[lsu.scala:252:32] wire s_uop_21_is_fencei = stq_uop_18_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_fencei = stq_uop_18_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sfence; // @[lsu.scala:252:32] wire s_uop_21_is_sfence = stq_uop_18_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sfence = stq_uop_18_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_amo; // @[lsu.scala:252:32] wire s_uop_21_is_amo = stq_uop_18_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_amo = stq_uop_18_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_eret; // @[lsu.scala:252:32] wire s_uop_21_is_eret = stq_uop_18_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_eret = stq_uop_18_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_21_is_sys_pc2epc = stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sys_pc2epc = stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_rocc; // @[lsu.scala:252:32] wire s_uop_21_is_rocc = stq_uop_18_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_rocc = stq_uop_18_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_mov; // @[lsu.scala:252:32] wire s_uop_21_is_mov = stq_uop_18_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_mov = stq_uop_18_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ftq_idx = stq_uop_18_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ftq_idx = stq_uop_18_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_edge_inst; // @[lsu.scala:252:32] wire s_uop_21_edge_inst = stq_uop_18_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_19_edge_inst = stq_uop_18_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_21_pc_lob = stq_uop_18_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_pc_lob = stq_uop_18_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_taken; // @[lsu.scala:252:32] wire s_uop_21_taken = stq_uop_18_taken; // @[lsu.scala:252:32, :1324:37] wire uop_19_taken = stq_uop_18_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_imm_rename; // @[lsu.scala:252:32] wire s_uop_21_imm_rename = stq_uop_18_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_19_imm_rename = stq_uop_18_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_imm_sel = stq_uop_18_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_imm_sel = stq_uop_18_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_21_pimm = stq_uop_18_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_pimm = stq_uop_18_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_18_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_21_imm_packed = stq_uop_18_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_19_imm_packed = stq_uop_18_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_21_op1_sel = stq_uop_18_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_op1_sel = stq_uop_18_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_op2_sel = stq_uop_18_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_op2_sel = stq_uop_18_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ldst = stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ldst = stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_wen = stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_wen = stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren1 = stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren1 = stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren2 = stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren2 = stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren3 = stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren3 = stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_swap12 = stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_swap12 = stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_swap23 = stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_swap23 = stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_ctrl_typeTagIn = stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_ctrl_typeTagIn = stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_ctrl_typeTagOut = stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_ctrl_typeTagOut = stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fromint = stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fromint = stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_toint = stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_toint = stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fastpipe = stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fastpipe = stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fma = stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fma = stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_div = stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_div = stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_sqrt = stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_sqrt = stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_wflags = stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_wflags = stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_vec = stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_vec = stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_21_rob_idx = stq_uop_18_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_rob_idx = stq_uop_18_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ldq_idx = stq_uop_18_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ldq_idx = stq_uop_18_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_stq_idx = stq_uop_18_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_stq_idx = stq_uop_18_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_21_rxq_idx = stq_uop_18_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_rxq_idx = stq_uop_18_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_21_pdst = stq_uop_18_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_pdst = stq_uop_18_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs1 = stq_uop_18_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs1 = stq_uop_18_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs2 = stq_uop_18_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs2 = stq_uop_18_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs3 = stq_uop_18_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs3 = stq_uop_18_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ppred = stq_uop_18_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ppred = stq_uop_18_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs1_busy; // @[lsu.scala:252:32] wire s_uop_21_prs1_busy = stq_uop_18_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs1_busy = stq_uop_18_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs2_busy; // @[lsu.scala:252:32] wire s_uop_21_prs2_busy = stq_uop_18_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs2_busy = stq_uop_18_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs3_busy; // @[lsu.scala:252:32] wire s_uop_21_prs3_busy = stq_uop_18_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs3_busy = stq_uop_18_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_ppred_busy; // @[lsu.scala:252:32] wire s_uop_21_ppred_busy = stq_uop_18_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_ppred_busy = stq_uop_18_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_21_stale_pdst = stq_uop_18_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_stale_pdst = stq_uop_18_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_exception; // @[lsu.scala:252:32] wire s_uop_21_exception = stq_uop_18_exception; // @[lsu.scala:252:32, :1324:37] wire uop_19_exception = stq_uop_18_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_18_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_21_exc_cause = stq_uop_18_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_19_exc_cause = stq_uop_18_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_21_mem_cmd = stq_uop_18_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_mem_cmd = stq_uop_18_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_21_mem_size = stq_uop_18_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_mem_size = stq_uop_18_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_mem_signed; // @[lsu.scala:252:32] wire s_uop_21_mem_signed = stq_uop_18_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_19_mem_signed = stq_uop_18_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_uses_ldq; // @[lsu.scala:252:32] wire s_uop_21_uses_ldq = stq_uop_18_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_19_uses_ldq = stq_uop_18_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_uses_stq; // @[lsu.scala:252:32] wire s_uop_21_uses_stq = stq_uop_18_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_19_uses_stq = stq_uop_18_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_unique; // @[lsu.scala:252:32] wire s_uop_21_is_unique = stq_uop_18_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_unique = stq_uop_18_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_21_flush_on_commit = stq_uop_18_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_19_flush_on_commit = stq_uop_18_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_21_csr_cmd = stq_uop_18_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_csr_cmd = stq_uop_18_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_21_ldst_is_rs1 = stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_19_ldst_is_rs1 = stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_21_ldst = stq_uop_18_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_ldst = stq_uop_18_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs1 = stq_uop_18_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs1 = stq_uop_18_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs2 = stq_uop_18_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs2 = stq_uop_18_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs3 = stq_uop_18_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs3 = stq_uop_18_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_dst_rtype = stq_uop_18_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_dst_rtype = stq_uop_18_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_lrs1_rtype = stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_lrs1_rtype = stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_lrs2_rtype = stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_lrs2_rtype = stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_frs3_en; // @[lsu.scala:252:32] wire s_uop_21_frs3_en = stq_uop_18_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_19_frs3_en = stq_uop_18_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fcn_dw; // @[lsu.scala:252:32] wire s_uop_21_fcn_dw = stq_uop_18_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_19_fcn_dw = stq_uop_18_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_21_fcn_op = stq_uop_18_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_fcn_op = stq_uop_18_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_val; // @[lsu.scala:252:32] wire s_uop_21_fp_val = stq_uop_18_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_val = stq_uop_18_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_21_fp_rm = stq_uop_18_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_fp_rm = stq_uop_18_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_typ = stq_uop_18_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_typ = stq_uop_18_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_pf_if = stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_pf_if = stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_ae_if = stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_ae_if = stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_ma_if = stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_ma_if = stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_21_bp_debug_if = stq_uop_18_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_bp_debug_if = stq_uop_18_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_21_bp_xcpt_if = stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_bp_xcpt_if = stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_21_debug_fsrc = stq_uop_18_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_debug_fsrc = stq_uop_18_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_21_debug_tsrc = stq_uop_18_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_debug_tsrc = stq_uop_18_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_19_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_22_inst = stq_uop_19_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_20_inst = stq_uop_19_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_19_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_22_debug_inst = stq_uop_19_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_20_debug_inst = stq_uop_19_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_rvc; // @[lsu.scala:252:32] wire s_uop_22_is_rvc = stq_uop_19_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_rvc = stq_uop_19_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_19_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_22_debug_pc = stq_uop_19_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_20_debug_pc = stq_uop_19_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_0; // @[lsu.scala:252:32] wire s_uop_22_iq_type_0 = stq_uop_19_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_0 = stq_uop_19_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_1; // @[lsu.scala:252:32] wire s_uop_22_iq_type_1 = stq_uop_19_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_1 = stq_uop_19_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_2; // @[lsu.scala:252:32] wire s_uop_22_iq_type_2 = stq_uop_19_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_2 = stq_uop_19_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_3; // @[lsu.scala:252:32] wire s_uop_22_iq_type_3 = stq_uop_19_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_3 = stq_uop_19_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_0; // @[lsu.scala:252:32] wire s_uop_22_fu_code_0 = stq_uop_19_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_0 = stq_uop_19_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_1; // @[lsu.scala:252:32] wire s_uop_22_fu_code_1 = stq_uop_19_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_1 = stq_uop_19_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_2; // @[lsu.scala:252:32] wire s_uop_22_fu_code_2 = stq_uop_19_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_2 = stq_uop_19_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_3; // @[lsu.scala:252:32] wire s_uop_22_fu_code_3 = stq_uop_19_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_3 = stq_uop_19_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_4; // @[lsu.scala:252:32] wire s_uop_22_fu_code_4 = stq_uop_19_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_4 = stq_uop_19_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_5; // @[lsu.scala:252:32] wire s_uop_22_fu_code_5 = stq_uop_19_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_5 = stq_uop_19_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_6; // @[lsu.scala:252:32] wire s_uop_22_fu_code_6 = stq_uop_19_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_6 = stq_uop_19_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_7; // @[lsu.scala:252:32] wire s_uop_22_fu_code_7 = stq_uop_19_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_7 = stq_uop_19_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_8; // @[lsu.scala:252:32] wire s_uop_22_fu_code_8 = stq_uop_19_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_8 = stq_uop_19_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_9; // @[lsu.scala:252:32] wire s_uop_22_fu_code_9 = stq_uop_19_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_9 = stq_uop_19_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued; // @[lsu.scala:252:32] wire s_uop_22_iw_issued = stq_uop_19_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued = stq_uop_19_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_22_iw_issued_partial_agen = stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued_partial_agen = stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_22_iw_issued_partial_dgen = stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued_partial_dgen = stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_22_iw_p1_speculative_child = stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_iw_p1_speculative_child = stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_22_iw_p2_speculative_child = stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_iw_p2_speculative_child = stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p1_bypass_hint = stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p1_bypass_hint = stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p2_bypass_hint = stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p2_bypass_hint = stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p3_bypass_hint = stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p3_bypass_hint = stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_dis_col_sel = stq_uop_19_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_dis_col_sel = stq_uop_19_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_19_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_22_br_mask = stq_uop_19_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_20_br_mask = stq_uop_19_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_19_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_22_br_tag = stq_uop_19_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_20_br_tag = stq_uop_19_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_19_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_22_br_type = stq_uop_19_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_20_br_type = stq_uop_19_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sfb; // @[lsu.scala:252:32] wire s_uop_22_is_sfb = stq_uop_19_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sfb = stq_uop_19_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_fence; // @[lsu.scala:252:32] wire s_uop_22_is_fence = stq_uop_19_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_fence = stq_uop_19_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_fencei; // @[lsu.scala:252:32] wire s_uop_22_is_fencei = stq_uop_19_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_fencei = stq_uop_19_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sfence; // @[lsu.scala:252:32] wire s_uop_22_is_sfence = stq_uop_19_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sfence = stq_uop_19_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_amo; // @[lsu.scala:252:32] wire s_uop_22_is_amo = stq_uop_19_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_amo = stq_uop_19_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_eret; // @[lsu.scala:252:32] wire s_uop_22_is_eret = stq_uop_19_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_eret = stq_uop_19_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_22_is_sys_pc2epc = stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sys_pc2epc = stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_rocc; // @[lsu.scala:252:32] wire s_uop_22_is_rocc = stq_uop_19_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_rocc = stq_uop_19_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_mov; // @[lsu.scala:252:32] wire s_uop_22_is_mov = stq_uop_19_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_mov = stq_uop_19_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ftq_idx = stq_uop_19_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ftq_idx = stq_uop_19_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_edge_inst; // @[lsu.scala:252:32] wire s_uop_22_edge_inst = stq_uop_19_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_20_edge_inst = stq_uop_19_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_22_pc_lob = stq_uop_19_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_pc_lob = stq_uop_19_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_taken; // @[lsu.scala:252:32] wire s_uop_22_taken = stq_uop_19_taken; // @[lsu.scala:252:32, :1324:37] wire uop_20_taken = stq_uop_19_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_imm_rename; // @[lsu.scala:252:32] wire s_uop_22_imm_rename = stq_uop_19_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_20_imm_rename = stq_uop_19_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_imm_sel = stq_uop_19_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_imm_sel = stq_uop_19_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_22_pimm = stq_uop_19_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_pimm = stq_uop_19_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_19_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_22_imm_packed = stq_uop_19_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_20_imm_packed = stq_uop_19_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_22_op1_sel = stq_uop_19_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_op1_sel = stq_uop_19_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_op2_sel = stq_uop_19_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_op2_sel = stq_uop_19_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ldst = stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ldst = stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_wen = stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_wen = stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren1 = stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren1 = stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren2 = stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren2 = stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren3 = stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren3 = stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_swap12 = stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_swap12 = stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_swap23 = stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_swap23 = stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_ctrl_typeTagIn = stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_ctrl_typeTagIn = stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_ctrl_typeTagOut = stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_ctrl_typeTagOut = stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fromint = stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fromint = stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_toint = stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_toint = stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fastpipe = stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fastpipe = stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fma = stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fma = stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_div = stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_div = stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_sqrt = stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_sqrt = stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_wflags = stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_wflags = stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_vec = stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_vec = stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_22_rob_idx = stq_uop_19_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_rob_idx = stq_uop_19_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ldq_idx = stq_uop_19_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ldq_idx = stq_uop_19_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_stq_idx = stq_uop_19_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_stq_idx = stq_uop_19_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_22_rxq_idx = stq_uop_19_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_rxq_idx = stq_uop_19_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_22_pdst = stq_uop_19_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_pdst = stq_uop_19_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs1 = stq_uop_19_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs1 = stq_uop_19_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs2 = stq_uop_19_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs2 = stq_uop_19_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs3 = stq_uop_19_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs3 = stq_uop_19_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ppred = stq_uop_19_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ppred = stq_uop_19_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs1_busy; // @[lsu.scala:252:32] wire s_uop_22_prs1_busy = stq_uop_19_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs1_busy = stq_uop_19_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs2_busy; // @[lsu.scala:252:32] wire s_uop_22_prs2_busy = stq_uop_19_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs2_busy = stq_uop_19_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs3_busy; // @[lsu.scala:252:32] wire s_uop_22_prs3_busy = stq_uop_19_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs3_busy = stq_uop_19_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_ppred_busy; // @[lsu.scala:252:32] wire s_uop_22_ppred_busy = stq_uop_19_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_ppred_busy = stq_uop_19_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_22_stale_pdst = stq_uop_19_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_stale_pdst = stq_uop_19_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_exception; // @[lsu.scala:252:32] wire s_uop_22_exception = stq_uop_19_exception; // @[lsu.scala:252:32, :1324:37] wire uop_20_exception = stq_uop_19_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_19_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_22_exc_cause = stq_uop_19_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_20_exc_cause = stq_uop_19_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_22_mem_cmd = stq_uop_19_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_mem_cmd = stq_uop_19_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_22_mem_size = stq_uop_19_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_mem_size = stq_uop_19_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_mem_signed; // @[lsu.scala:252:32] wire s_uop_22_mem_signed = stq_uop_19_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_20_mem_signed = stq_uop_19_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_uses_ldq; // @[lsu.scala:252:32] wire s_uop_22_uses_ldq = stq_uop_19_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_20_uses_ldq = stq_uop_19_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_uses_stq; // @[lsu.scala:252:32] wire s_uop_22_uses_stq = stq_uop_19_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_20_uses_stq = stq_uop_19_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_unique; // @[lsu.scala:252:32] wire s_uop_22_is_unique = stq_uop_19_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_unique = stq_uop_19_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_22_flush_on_commit = stq_uop_19_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_20_flush_on_commit = stq_uop_19_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_22_csr_cmd = stq_uop_19_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_csr_cmd = stq_uop_19_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_22_ldst_is_rs1 = stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_20_ldst_is_rs1 = stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_22_ldst = stq_uop_19_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_ldst = stq_uop_19_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs1 = stq_uop_19_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs1 = stq_uop_19_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs2 = stq_uop_19_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs2 = stq_uop_19_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs3 = stq_uop_19_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs3 = stq_uop_19_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_dst_rtype = stq_uop_19_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_dst_rtype = stq_uop_19_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_lrs1_rtype = stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_lrs1_rtype = stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_lrs2_rtype = stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_lrs2_rtype = stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_frs3_en; // @[lsu.scala:252:32] wire s_uop_22_frs3_en = stq_uop_19_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_20_frs3_en = stq_uop_19_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fcn_dw; // @[lsu.scala:252:32] wire s_uop_22_fcn_dw = stq_uop_19_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_20_fcn_dw = stq_uop_19_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_22_fcn_op = stq_uop_19_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_fcn_op = stq_uop_19_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_val; // @[lsu.scala:252:32] wire s_uop_22_fp_val = stq_uop_19_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_val = stq_uop_19_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_22_fp_rm = stq_uop_19_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_fp_rm = stq_uop_19_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_typ = stq_uop_19_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_typ = stq_uop_19_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_pf_if = stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_pf_if = stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_ae_if = stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_ae_if = stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_ma_if = stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_ma_if = stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_22_bp_debug_if = stq_uop_19_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_bp_debug_if = stq_uop_19_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_22_bp_xcpt_if = stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_bp_xcpt_if = stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_22_debug_fsrc = stq_uop_19_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_debug_fsrc = stq_uop_19_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_22_debug_tsrc = stq_uop_19_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_debug_tsrc = stq_uop_19_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_20_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_23_inst = stq_uop_20_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_21_inst = stq_uop_20_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_20_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_23_debug_inst = stq_uop_20_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_21_debug_inst = stq_uop_20_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_rvc; // @[lsu.scala:252:32] wire s_uop_23_is_rvc = stq_uop_20_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_rvc = stq_uop_20_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_20_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_23_debug_pc = stq_uop_20_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_21_debug_pc = stq_uop_20_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_0; // @[lsu.scala:252:32] wire s_uop_23_iq_type_0 = stq_uop_20_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_0 = stq_uop_20_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_1; // @[lsu.scala:252:32] wire s_uop_23_iq_type_1 = stq_uop_20_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_1 = stq_uop_20_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_2; // @[lsu.scala:252:32] wire s_uop_23_iq_type_2 = stq_uop_20_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_2 = stq_uop_20_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_3; // @[lsu.scala:252:32] wire s_uop_23_iq_type_3 = stq_uop_20_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_3 = stq_uop_20_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_0; // @[lsu.scala:252:32] wire s_uop_23_fu_code_0 = stq_uop_20_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_0 = stq_uop_20_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_1; // @[lsu.scala:252:32] wire s_uop_23_fu_code_1 = stq_uop_20_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_1 = stq_uop_20_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_2; // @[lsu.scala:252:32] wire s_uop_23_fu_code_2 = stq_uop_20_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_2 = stq_uop_20_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_3; // @[lsu.scala:252:32] wire s_uop_23_fu_code_3 = stq_uop_20_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_3 = stq_uop_20_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_4; // @[lsu.scala:252:32] wire s_uop_23_fu_code_4 = stq_uop_20_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_4 = stq_uop_20_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_5; // @[lsu.scala:252:32] wire s_uop_23_fu_code_5 = stq_uop_20_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_5 = stq_uop_20_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_6; // @[lsu.scala:252:32] wire s_uop_23_fu_code_6 = stq_uop_20_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_6 = stq_uop_20_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_7; // @[lsu.scala:252:32] wire s_uop_23_fu_code_7 = stq_uop_20_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_7 = stq_uop_20_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_8; // @[lsu.scala:252:32] wire s_uop_23_fu_code_8 = stq_uop_20_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_8 = stq_uop_20_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_9; // @[lsu.scala:252:32] wire s_uop_23_fu_code_9 = stq_uop_20_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_9 = stq_uop_20_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued; // @[lsu.scala:252:32] wire s_uop_23_iw_issued = stq_uop_20_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued = stq_uop_20_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_23_iw_issued_partial_agen = stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued_partial_agen = stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_23_iw_issued_partial_dgen = stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued_partial_dgen = stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_23_iw_p1_speculative_child = stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_iw_p1_speculative_child = stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_23_iw_p2_speculative_child = stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_iw_p2_speculative_child = stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p1_bypass_hint = stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p1_bypass_hint = stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p2_bypass_hint = stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p2_bypass_hint = stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p3_bypass_hint = stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p3_bypass_hint = stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_dis_col_sel = stq_uop_20_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_dis_col_sel = stq_uop_20_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_20_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_23_br_mask = stq_uop_20_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_21_br_mask = stq_uop_20_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_20_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_23_br_tag = stq_uop_20_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_21_br_tag = stq_uop_20_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_20_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_23_br_type = stq_uop_20_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_21_br_type = stq_uop_20_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sfb; // @[lsu.scala:252:32] wire s_uop_23_is_sfb = stq_uop_20_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sfb = stq_uop_20_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_fence; // @[lsu.scala:252:32] wire s_uop_23_is_fence = stq_uop_20_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_fence = stq_uop_20_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_fencei; // @[lsu.scala:252:32] wire s_uop_23_is_fencei = stq_uop_20_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_fencei = stq_uop_20_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sfence; // @[lsu.scala:252:32] wire s_uop_23_is_sfence = stq_uop_20_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sfence = stq_uop_20_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_amo; // @[lsu.scala:252:32] wire s_uop_23_is_amo = stq_uop_20_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_amo = stq_uop_20_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_eret; // @[lsu.scala:252:32] wire s_uop_23_is_eret = stq_uop_20_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_eret = stq_uop_20_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_23_is_sys_pc2epc = stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sys_pc2epc = stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_rocc; // @[lsu.scala:252:32] wire s_uop_23_is_rocc = stq_uop_20_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_rocc = stq_uop_20_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_mov; // @[lsu.scala:252:32] wire s_uop_23_is_mov = stq_uop_20_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_mov = stq_uop_20_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ftq_idx = stq_uop_20_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ftq_idx = stq_uop_20_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_edge_inst; // @[lsu.scala:252:32] wire s_uop_23_edge_inst = stq_uop_20_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_21_edge_inst = stq_uop_20_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_23_pc_lob = stq_uop_20_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_pc_lob = stq_uop_20_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_taken; // @[lsu.scala:252:32] wire s_uop_23_taken = stq_uop_20_taken; // @[lsu.scala:252:32, :1324:37] wire uop_21_taken = stq_uop_20_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_imm_rename; // @[lsu.scala:252:32] wire s_uop_23_imm_rename = stq_uop_20_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_21_imm_rename = stq_uop_20_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_imm_sel = stq_uop_20_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_imm_sel = stq_uop_20_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_23_pimm = stq_uop_20_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_pimm = stq_uop_20_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_20_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_23_imm_packed = stq_uop_20_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_21_imm_packed = stq_uop_20_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_23_op1_sel = stq_uop_20_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_op1_sel = stq_uop_20_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_op2_sel = stq_uop_20_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_op2_sel = stq_uop_20_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ldst = stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ldst = stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_wen = stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_wen = stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren1 = stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren1 = stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren2 = stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren2 = stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren3 = stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren3 = stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_swap12 = stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_swap12 = stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_swap23 = stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_swap23 = stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_ctrl_typeTagIn = stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_ctrl_typeTagIn = stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_ctrl_typeTagOut = stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_ctrl_typeTagOut = stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fromint = stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fromint = stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_toint = stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_toint = stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fastpipe = stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fastpipe = stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fma = stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fma = stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_div = stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_div = stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_sqrt = stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_sqrt = stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_wflags = stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_wflags = stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_vec = stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_vec = stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_23_rob_idx = stq_uop_20_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_rob_idx = stq_uop_20_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ldq_idx = stq_uop_20_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ldq_idx = stq_uop_20_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_stq_idx = stq_uop_20_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_stq_idx = stq_uop_20_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_23_rxq_idx = stq_uop_20_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_rxq_idx = stq_uop_20_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_23_pdst = stq_uop_20_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_pdst = stq_uop_20_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs1 = stq_uop_20_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs1 = stq_uop_20_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs2 = stq_uop_20_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs2 = stq_uop_20_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs3 = stq_uop_20_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs3 = stq_uop_20_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ppred = stq_uop_20_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ppred = stq_uop_20_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs1_busy; // @[lsu.scala:252:32] wire s_uop_23_prs1_busy = stq_uop_20_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs1_busy = stq_uop_20_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs2_busy; // @[lsu.scala:252:32] wire s_uop_23_prs2_busy = stq_uop_20_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs2_busy = stq_uop_20_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs3_busy; // @[lsu.scala:252:32] wire s_uop_23_prs3_busy = stq_uop_20_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs3_busy = stq_uop_20_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_ppred_busy; // @[lsu.scala:252:32] wire s_uop_23_ppred_busy = stq_uop_20_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_ppred_busy = stq_uop_20_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_23_stale_pdst = stq_uop_20_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_stale_pdst = stq_uop_20_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_exception; // @[lsu.scala:252:32] wire s_uop_23_exception = stq_uop_20_exception; // @[lsu.scala:252:32, :1324:37] wire uop_21_exception = stq_uop_20_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_20_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_23_exc_cause = stq_uop_20_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_21_exc_cause = stq_uop_20_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_23_mem_cmd = stq_uop_20_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_mem_cmd = stq_uop_20_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_23_mem_size = stq_uop_20_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_mem_size = stq_uop_20_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_mem_signed; // @[lsu.scala:252:32] wire s_uop_23_mem_signed = stq_uop_20_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_21_mem_signed = stq_uop_20_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_uses_ldq; // @[lsu.scala:252:32] wire s_uop_23_uses_ldq = stq_uop_20_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_21_uses_ldq = stq_uop_20_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_uses_stq; // @[lsu.scala:252:32] wire s_uop_23_uses_stq = stq_uop_20_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_21_uses_stq = stq_uop_20_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_unique; // @[lsu.scala:252:32] wire s_uop_23_is_unique = stq_uop_20_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_unique = stq_uop_20_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_23_flush_on_commit = stq_uop_20_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_21_flush_on_commit = stq_uop_20_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_23_csr_cmd = stq_uop_20_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_csr_cmd = stq_uop_20_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_23_ldst_is_rs1 = stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_21_ldst_is_rs1 = stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_23_ldst = stq_uop_20_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_ldst = stq_uop_20_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs1 = stq_uop_20_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs1 = stq_uop_20_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs2 = stq_uop_20_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs2 = stq_uop_20_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs3 = stq_uop_20_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs3 = stq_uop_20_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_dst_rtype = stq_uop_20_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_dst_rtype = stq_uop_20_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_lrs1_rtype = stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_lrs1_rtype = stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_lrs2_rtype = stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_lrs2_rtype = stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_frs3_en; // @[lsu.scala:252:32] wire s_uop_23_frs3_en = stq_uop_20_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_21_frs3_en = stq_uop_20_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fcn_dw; // @[lsu.scala:252:32] wire s_uop_23_fcn_dw = stq_uop_20_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_21_fcn_dw = stq_uop_20_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_23_fcn_op = stq_uop_20_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_fcn_op = stq_uop_20_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_val; // @[lsu.scala:252:32] wire s_uop_23_fp_val = stq_uop_20_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_val = stq_uop_20_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_23_fp_rm = stq_uop_20_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_fp_rm = stq_uop_20_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_typ = stq_uop_20_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_typ = stq_uop_20_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_pf_if = stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_pf_if = stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_ae_if = stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_ae_if = stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_ma_if = stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_ma_if = stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_23_bp_debug_if = stq_uop_20_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_bp_debug_if = stq_uop_20_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_23_bp_xcpt_if = stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_bp_xcpt_if = stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_23_debug_fsrc = stq_uop_20_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_debug_fsrc = stq_uop_20_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_23_debug_tsrc = stq_uop_20_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_debug_tsrc = stq_uop_20_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_21_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_24_inst = stq_uop_21_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_22_inst = stq_uop_21_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_21_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_24_debug_inst = stq_uop_21_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_22_debug_inst = stq_uop_21_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_rvc; // @[lsu.scala:252:32] wire s_uop_24_is_rvc = stq_uop_21_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_rvc = stq_uop_21_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_21_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_24_debug_pc = stq_uop_21_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_22_debug_pc = stq_uop_21_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_0; // @[lsu.scala:252:32] wire s_uop_24_iq_type_0 = stq_uop_21_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_0 = stq_uop_21_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_1; // @[lsu.scala:252:32] wire s_uop_24_iq_type_1 = stq_uop_21_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_1 = stq_uop_21_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_2; // @[lsu.scala:252:32] wire s_uop_24_iq_type_2 = stq_uop_21_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_2 = stq_uop_21_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_3; // @[lsu.scala:252:32] wire s_uop_24_iq_type_3 = stq_uop_21_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_3 = stq_uop_21_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_0; // @[lsu.scala:252:32] wire s_uop_24_fu_code_0 = stq_uop_21_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_0 = stq_uop_21_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_1; // @[lsu.scala:252:32] wire s_uop_24_fu_code_1 = stq_uop_21_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_1 = stq_uop_21_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_2; // @[lsu.scala:252:32] wire s_uop_24_fu_code_2 = stq_uop_21_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_2 = stq_uop_21_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_3; // @[lsu.scala:252:32] wire s_uop_24_fu_code_3 = stq_uop_21_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_3 = stq_uop_21_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_4; // @[lsu.scala:252:32] wire s_uop_24_fu_code_4 = stq_uop_21_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_4 = stq_uop_21_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_5; // @[lsu.scala:252:32] wire s_uop_24_fu_code_5 = stq_uop_21_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_5 = stq_uop_21_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_6; // @[lsu.scala:252:32] wire s_uop_24_fu_code_6 = stq_uop_21_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_6 = stq_uop_21_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_7; // @[lsu.scala:252:32] wire s_uop_24_fu_code_7 = stq_uop_21_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_7 = stq_uop_21_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_8; // @[lsu.scala:252:32] wire s_uop_24_fu_code_8 = stq_uop_21_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_8 = stq_uop_21_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_9; // @[lsu.scala:252:32] wire s_uop_24_fu_code_9 = stq_uop_21_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_9 = stq_uop_21_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued; // @[lsu.scala:252:32] wire s_uop_24_iw_issued = stq_uop_21_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued = stq_uop_21_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_24_iw_issued_partial_agen = stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued_partial_agen = stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_24_iw_issued_partial_dgen = stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued_partial_dgen = stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_24_iw_p1_speculative_child = stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_iw_p1_speculative_child = stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_24_iw_p2_speculative_child = stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_iw_p2_speculative_child = stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p1_bypass_hint = stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p1_bypass_hint = stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p2_bypass_hint = stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p2_bypass_hint = stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p3_bypass_hint = stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p3_bypass_hint = stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_dis_col_sel = stq_uop_21_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_dis_col_sel = stq_uop_21_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_21_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_24_br_mask = stq_uop_21_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_22_br_mask = stq_uop_21_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_21_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_24_br_tag = stq_uop_21_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_22_br_tag = stq_uop_21_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_21_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_24_br_type = stq_uop_21_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_22_br_type = stq_uop_21_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sfb; // @[lsu.scala:252:32] wire s_uop_24_is_sfb = stq_uop_21_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sfb = stq_uop_21_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_fence; // @[lsu.scala:252:32] wire s_uop_24_is_fence = stq_uop_21_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_fence = stq_uop_21_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_fencei; // @[lsu.scala:252:32] wire s_uop_24_is_fencei = stq_uop_21_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_fencei = stq_uop_21_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sfence; // @[lsu.scala:252:32] wire s_uop_24_is_sfence = stq_uop_21_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sfence = stq_uop_21_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_amo; // @[lsu.scala:252:32] wire s_uop_24_is_amo = stq_uop_21_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_amo = stq_uop_21_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_eret; // @[lsu.scala:252:32] wire s_uop_24_is_eret = stq_uop_21_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_eret = stq_uop_21_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_24_is_sys_pc2epc = stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sys_pc2epc = stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_rocc; // @[lsu.scala:252:32] wire s_uop_24_is_rocc = stq_uop_21_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_rocc = stq_uop_21_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_mov; // @[lsu.scala:252:32] wire s_uop_24_is_mov = stq_uop_21_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_mov = stq_uop_21_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ftq_idx = stq_uop_21_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ftq_idx = stq_uop_21_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_edge_inst; // @[lsu.scala:252:32] wire s_uop_24_edge_inst = stq_uop_21_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_22_edge_inst = stq_uop_21_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_24_pc_lob = stq_uop_21_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_pc_lob = stq_uop_21_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_taken; // @[lsu.scala:252:32] wire s_uop_24_taken = stq_uop_21_taken; // @[lsu.scala:252:32, :1324:37] wire uop_22_taken = stq_uop_21_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_imm_rename; // @[lsu.scala:252:32] wire s_uop_24_imm_rename = stq_uop_21_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_22_imm_rename = stq_uop_21_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_imm_sel = stq_uop_21_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_imm_sel = stq_uop_21_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_24_pimm = stq_uop_21_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_pimm = stq_uop_21_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_21_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_24_imm_packed = stq_uop_21_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_22_imm_packed = stq_uop_21_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_24_op1_sel = stq_uop_21_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_op1_sel = stq_uop_21_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_op2_sel = stq_uop_21_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_op2_sel = stq_uop_21_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ldst = stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ldst = stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_wen = stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_wen = stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren1 = stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren1 = stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren2 = stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren2 = stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren3 = stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren3 = stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_swap12 = stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_swap12 = stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_swap23 = stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_swap23 = stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_ctrl_typeTagIn = stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_ctrl_typeTagIn = stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_ctrl_typeTagOut = stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_ctrl_typeTagOut = stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fromint = stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fromint = stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_toint = stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_toint = stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fastpipe = stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fastpipe = stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fma = stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fma = stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_div = stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_div = stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_sqrt = stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_sqrt = stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_wflags = stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_wflags = stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_vec = stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_vec = stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_24_rob_idx = stq_uop_21_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_rob_idx = stq_uop_21_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ldq_idx = stq_uop_21_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ldq_idx = stq_uop_21_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_stq_idx = stq_uop_21_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_stq_idx = stq_uop_21_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_24_rxq_idx = stq_uop_21_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_rxq_idx = stq_uop_21_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_24_pdst = stq_uop_21_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_pdst = stq_uop_21_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs1 = stq_uop_21_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs1 = stq_uop_21_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs2 = stq_uop_21_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs2 = stq_uop_21_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs3 = stq_uop_21_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs3 = stq_uop_21_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ppred = stq_uop_21_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ppred = stq_uop_21_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs1_busy; // @[lsu.scala:252:32] wire s_uop_24_prs1_busy = stq_uop_21_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs1_busy = stq_uop_21_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs2_busy; // @[lsu.scala:252:32] wire s_uop_24_prs2_busy = stq_uop_21_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs2_busy = stq_uop_21_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs3_busy; // @[lsu.scala:252:32] wire s_uop_24_prs3_busy = stq_uop_21_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs3_busy = stq_uop_21_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_ppred_busy; // @[lsu.scala:252:32] wire s_uop_24_ppred_busy = stq_uop_21_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_ppred_busy = stq_uop_21_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_24_stale_pdst = stq_uop_21_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_stale_pdst = stq_uop_21_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_exception; // @[lsu.scala:252:32] wire s_uop_24_exception = stq_uop_21_exception; // @[lsu.scala:252:32, :1324:37] wire uop_22_exception = stq_uop_21_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_21_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_24_exc_cause = stq_uop_21_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_22_exc_cause = stq_uop_21_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_24_mem_cmd = stq_uop_21_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_mem_cmd = stq_uop_21_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_24_mem_size = stq_uop_21_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_mem_size = stq_uop_21_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_mem_signed; // @[lsu.scala:252:32] wire s_uop_24_mem_signed = stq_uop_21_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_22_mem_signed = stq_uop_21_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_uses_ldq; // @[lsu.scala:252:32] wire s_uop_24_uses_ldq = stq_uop_21_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_22_uses_ldq = stq_uop_21_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_uses_stq; // @[lsu.scala:252:32] wire s_uop_24_uses_stq = stq_uop_21_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_22_uses_stq = stq_uop_21_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_unique; // @[lsu.scala:252:32] wire s_uop_24_is_unique = stq_uop_21_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_unique = stq_uop_21_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_24_flush_on_commit = stq_uop_21_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_22_flush_on_commit = stq_uop_21_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_24_csr_cmd = stq_uop_21_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_csr_cmd = stq_uop_21_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_24_ldst_is_rs1 = stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_22_ldst_is_rs1 = stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_24_ldst = stq_uop_21_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_ldst = stq_uop_21_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs1 = stq_uop_21_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs1 = stq_uop_21_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs2 = stq_uop_21_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs2 = stq_uop_21_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs3 = stq_uop_21_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs3 = stq_uop_21_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_dst_rtype = stq_uop_21_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_dst_rtype = stq_uop_21_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_lrs1_rtype = stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_lrs1_rtype = stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_lrs2_rtype = stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_lrs2_rtype = stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_frs3_en; // @[lsu.scala:252:32] wire s_uop_24_frs3_en = stq_uop_21_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_22_frs3_en = stq_uop_21_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fcn_dw; // @[lsu.scala:252:32] wire s_uop_24_fcn_dw = stq_uop_21_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_22_fcn_dw = stq_uop_21_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_24_fcn_op = stq_uop_21_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_fcn_op = stq_uop_21_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_val; // @[lsu.scala:252:32] wire s_uop_24_fp_val = stq_uop_21_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_val = stq_uop_21_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_24_fp_rm = stq_uop_21_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_fp_rm = stq_uop_21_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_typ = stq_uop_21_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_typ = stq_uop_21_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_pf_if = stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_pf_if = stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_ae_if = stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_ae_if = stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_ma_if = stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_ma_if = stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_24_bp_debug_if = stq_uop_21_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_bp_debug_if = stq_uop_21_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_24_bp_xcpt_if = stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_bp_xcpt_if = stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_24_debug_fsrc = stq_uop_21_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_debug_fsrc = stq_uop_21_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_24_debug_tsrc = stq_uop_21_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_debug_tsrc = stq_uop_21_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_22_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_25_inst = stq_uop_22_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_23_inst = stq_uop_22_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_22_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_25_debug_inst = stq_uop_22_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_23_debug_inst = stq_uop_22_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_rvc; // @[lsu.scala:252:32] wire s_uop_25_is_rvc = stq_uop_22_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_rvc = stq_uop_22_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_22_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_25_debug_pc = stq_uop_22_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_23_debug_pc = stq_uop_22_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_0; // @[lsu.scala:252:32] wire s_uop_25_iq_type_0 = stq_uop_22_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_0 = stq_uop_22_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_1; // @[lsu.scala:252:32] wire s_uop_25_iq_type_1 = stq_uop_22_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_1 = stq_uop_22_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_2; // @[lsu.scala:252:32] wire s_uop_25_iq_type_2 = stq_uop_22_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_2 = stq_uop_22_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_3; // @[lsu.scala:252:32] wire s_uop_25_iq_type_3 = stq_uop_22_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_3 = stq_uop_22_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_0; // @[lsu.scala:252:32] wire s_uop_25_fu_code_0 = stq_uop_22_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_0 = stq_uop_22_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_1; // @[lsu.scala:252:32] wire s_uop_25_fu_code_1 = stq_uop_22_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_1 = stq_uop_22_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_2; // @[lsu.scala:252:32] wire s_uop_25_fu_code_2 = stq_uop_22_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_2 = stq_uop_22_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_3; // @[lsu.scala:252:32] wire s_uop_25_fu_code_3 = stq_uop_22_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_3 = stq_uop_22_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_4; // @[lsu.scala:252:32] wire s_uop_25_fu_code_4 = stq_uop_22_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_4 = stq_uop_22_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_5; // @[lsu.scala:252:32] wire s_uop_25_fu_code_5 = stq_uop_22_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_5 = stq_uop_22_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_6; // @[lsu.scala:252:32] wire s_uop_25_fu_code_6 = stq_uop_22_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_6 = stq_uop_22_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_7; // @[lsu.scala:252:32] wire s_uop_25_fu_code_7 = stq_uop_22_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_7 = stq_uop_22_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_8; // @[lsu.scala:252:32] wire s_uop_25_fu_code_8 = stq_uop_22_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_8 = stq_uop_22_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_9; // @[lsu.scala:252:32] wire s_uop_25_fu_code_9 = stq_uop_22_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_9 = stq_uop_22_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued; // @[lsu.scala:252:32] wire s_uop_25_iw_issued = stq_uop_22_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued = stq_uop_22_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_25_iw_issued_partial_agen = stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued_partial_agen = stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_25_iw_issued_partial_dgen = stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued_partial_dgen = stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_25_iw_p1_speculative_child = stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_iw_p1_speculative_child = stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_25_iw_p2_speculative_child = stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_iw_p2_speculative_child = stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p1_bypass_hint = stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p1_bypass_hint = stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p2_bypass_hint = stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p2_bypass_hint = stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p3_bypass_hint = stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p3_bypass_hint = stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_dis_col_sel = stq_uop_22_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_dis_col_sel = stq_uop_22_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_22_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_25_br_mask = stq_uop_22_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_23_br_mask = stq_uop_22_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_22_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_25_br_tag = stq_uop_22_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_23_br_tag = stq_uop_22_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_22_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_25_br_type = stq_uop_22_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_23_br_type = stq_uop_22_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sfb; // @[lsu.scala:252:32] wire s_uop_25_is_sfb = stq_uop_22_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sfb = stq_uop_22_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_fence; // @[lsu.scala:252:32] wire s_uop_25_is_fence = stq_uop_22_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_fence = stq_uop_22_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_fencei; // @[lsu.scala:252:32] wire s_uop_25_is_fencei = stq_uop_22_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_fencei = stq_uop_22_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sfence; // @[lsu.scala:252:32] wire s_uop_25_is_sfence = stq_uop_22_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sfence = stq_uop_22_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_amo; // @[lsu.scala:252:32] wire s_uop_25_is_amo = stq_uop_22_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_amo = stq_uop_22_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_eret; // @[lsu.scala:252:32] wire s_uop_25_is_eret = stq_uop_22_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_eret = stq_uop_22_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_25_is_sys_pc2epc = stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sys_pc2epc = stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_rocc; // @[lsu.scala:252:32] wire s_uop_25_is_rocc = stq_uop_22_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_rocc = stq_uop_22_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_mov; // @[lsu.scala:252:32] wire s_uop_25_is_mov = stq_uop_22_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_mov = stq_uop_22_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ftq_idx = stq_uop_22_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ftq_idx = stq_uop_22_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_edge_inst; // @[lsu.scala:252:32] wire s_uop_25_edge_inst = stq_uop_22_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_23_edge_inst = stq_uop_22_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_25_pc_lob = stq_uop_22_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_pc_lob = stq_uop_22_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_taken; // @[lsu.scala:252:32] wire s_uop_25_taken = stq_uop_22_taken; // @[lsu.scala:252:32, :1324:37] wire uop_23_taken = stq_uop_22_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_imm_rename; // @[lsu.scala:252:32] wire s_uop_25_imm_rename = stq_uop_22_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_23_imm_rename = stq_uop_22_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_imm_sel = stq_uop_22_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_imm_sel = stq_uop_22_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_25_pimm = stq_uop_22_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_pimm = stq_uop_22_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_22_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_25_imm_packed = stq_uop_22_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_23_imm_packed = stq_uop_22_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_25_op1_sel = stq_uop_22_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_op1_sel = stq_uop_22_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_op2_sel = stq_uop_22_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_op2_sel = stq_uop_22_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ldst = stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ldst = stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_wen = stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_wen = stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren1 = stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren1 = stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren2 = stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren2 = stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren3 = stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren3 = stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_swap12 = stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_swap12 = stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_swap23 = stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_swap23 = stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_ctrl_typeTagIn = stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_ctrl_typeTagIn = stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_ctrl_typeTagOut = stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_ctrl_typeTagOut = stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fromint = stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fromint = stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_toint = stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_toint = stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fastpipe = stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fastpipe = stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fma = stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fma = stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_div = stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_div = stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_sqrt = stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_sqrt = stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_wflags = stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_wflags = stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_vec = stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_vec = stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_25_rob_idx = stq_uop_22_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_rob_idx = stq_uop_22_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ldq_idx = stq_uop_22_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ldq_idx = stq_uop_22_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_stq_idx = stq_uop_22_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_stq_idx = stq_uop_22_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_25_rxq_idx = stq_uop_22_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_rxq_idx = stq_uop_22_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_25_pdst = stq_uop_22_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_pdst = stq_uop_22_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs1 = stq_uop_22_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs1 = stq_uop_22_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs2 = stq_uop_22_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs2 = stq_uop_22_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs3 = stq_uop_22_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs3 = stq_uop_22_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ppred = stq_uop_22_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ppred = stq_uop_22_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs1_busy; // @[lsu.scala:252:32] wire s_uop_25_prs1_busy = stq_uop_22_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs1_busy = stq_uop_22_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs2_busy; // @[lsu.scala:252:32] wire s_uop_25_prs2_busy = stq_uop_22_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs2_busy = stq_uop_22_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs3_busy; // @[lsu.scala:252:32] wire s_uop_25_prs3_busy = stq_uop_22_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs3_busy = stq_uop_22_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_ppred_busy; // @[lsu.scala:252:32] wire s_uop_25_ppred_busy = stq_uop_22_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_ppred_busy = stq_uop_22_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_25_stale_pdst = stq_uop_22_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_stale_pdst = stq_uop_22_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_exception; // @[lsu.scala:252:32] wire s_uop_25_exception = stq_uop_22_exception; // @[lsu.scala:252:32, :1324:37] wire uop_23_exception = stq_uop_22_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_22_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_25_exc_cause = stq_uop_22_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_23_exc_cause = stq_uop_22_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_25_mem_cmd = stq_uop_22_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_mem_cmd = stq_uop_22_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_25_mem_size = stq_uop_22_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_mem_size = stq_uop_22_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_mem_signed; // @[lsu.scala:252:32] wire s_uop_25_mem_signed = stq_uop_22_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_23_mem_signed = stq_uop_22_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_uses_ldq; // @[lsu.scala:252:32] wire s_uop_25_uses_ldq = stq_uop_22_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_23_uses_ldq = stq_uop_22_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_uses_stq; // @[lsu.scala:252:32] wire s_uop_25_uses_stq = stq_uop_22_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_23_uses_stq = stq_uop_22_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_unique; // @[lsu.scala:252:32] wire s_uop_25_is_unique = stq_uop_22_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_unique = stq_uop_22_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_25_flush_on_commit = stq_uop_22_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_23_flush_on_commit = stq_uop_22_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_25_csr_cmd = stq_uop_22_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_csr_cmd = stq_uop_22_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_25_ldst_is_rs1 = stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_23_ldst_is_rs1 = stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_25_ldst = stq_uop_22_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_ldst = stq_uop_22_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs1 = stq_uop_22_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs1 = stq_uop_22_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs2 = stq_uop_22_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs2 = stq_uop_22_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs3 = stq_uop_22_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs3 = stq_uop_22_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_dst_rtype = stq_uop_22_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_dst_rtype = stq_uop_22_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_lrs1_rtype = stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_lrs1_rtype = stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_lrs2_rtype = stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_lrs2_rtype = stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_frs3_en; // @[lsu.scala:252:32] wire s_uop_25_frs3_en = stq_uop_22_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_23_frs3_en = stq_uop_22_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fcn_dw; // @[lsu.scala:252:32] wire s_uop_25_fcn_dw = stq_uop_22_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_23_fcn_dw = stq_uop_22_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_25_fcn_op = stq_uop_22_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_fcn_op = stq_uop_22_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_val; // @[lsu.scala:252:32] wire s_uop_25_fp_val = stq_uop_22_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_val = stq_uop_22_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_25_fp_rm = stq_uop_22_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_fp_rm = stq_uop_22_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_typ = stq_uop_22_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_typ = stq_uop_22_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_pf_if = stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_pf_if = stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_ae_if = stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_ae_if = stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_ma_if = stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_ma_if = stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_25_bp_debug_if = stq_uop_22_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_bp_debug_if = stq_uop_22_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_25_bp_xcpt_if = stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_bp_xcpt_if = stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_25_debug_fsrc = stq_uop_22_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_debug_fsrc = stq_uop_22_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_25_debug_tsrc = stq_uop_22_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_debug_tsrc = stq_uop_22_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_23_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_26_inst = stq_uop_23_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_24_inst = stq_uop_23_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_23_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_26_debug_inst = stq_uop_23_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_24_debug_inst = stq_uop_23_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_rvc; // @[lsu.scala:252:32] wire s_uop_26_is_rvc = stq_uop_23_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_rvc = stq_uop_23_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_23_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_26_debug_pc = stq_uop_23_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_24_debug_pc = stq_uop_23_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_0; // @[lsu.scala:252:32] wire s_uop_26_iq_type_0 = stq_uop_23_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_0 = stq_uop_23_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_1; // @[lsu.scala:252:32] wire s_uop_26_iq_type_1 = stq_uop_23_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_1 = stq_uop_23_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_2; // @[lsu.scala:252:32] wire s_uop_26_iq_type_2 = stq_uop_23_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_2 = stq_uop_23_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_3; // @[lsu.scala:252:32] wire s_uop_26_iq_type_3 = stq_uop_23_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_3 = stq_uop_23_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_0; // @[lsu.scala:252:32] wire s_uop_26_fu_code_0 = stq_uop_23_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_0 = stq_uop_23_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_1; // @[lsu.scala:252:32] wire s_uop_26_fu_code_1 = stq_uop_23_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_1 = stq_uop_23_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_2; // @[lsu.scala:252:32] wire s_uop_26_fu_code_2 = stq_uop_23_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_2 = stq_uop_23_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_3; // @[lsu.scala:252:32] wire s_uop_26_fu_code_3 = stq_uop_23_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_3 = stq_uop_23_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_4; // @[lsu.scala:252:32] wire s_uop_26_fu_code_4 = stq_uop_23_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_4 = stq_uop_23_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_5; // @[lsu.scala:252:32] wire s_uop_26_fu_code_5 = stq_uop_23_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_5 = stq_uop_23_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_6; // @[lsu.scala:252:32] wire s_uop_26_fu_code_6 = stq_uop_23_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_6 = stq_uop_23_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_7; // @[lsu.scala:252:32] wire s_uop_26_fu_code_7 = stq_uop_23_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_7 = stq_uop_23_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_8; // @[lsu.scala:252:32] wire s_uop_26_fu_code_8 = stq_uop_23_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_8 = stq_uop_23_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_9; // @[lsu.scala:252:32] wire s_uop_26_fu_code_9 = stq_uop_23_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_9 = stq_uop_23_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued; // @[lsu.scala:252:32] wire s_uop_26_iw_issued = stq_uop_23_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued = stq_uop_23_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_26_iw_issued_partial_agen = stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued_partial_agen = stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_26_iw_issued_partial_dgen = stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued_partial_dgen = stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_26_iw_p1_speculative_child = stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_iw_p1_speculative_child = stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_26_iw_p2_speculative_child = stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_iw_p2_speculative_child = stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p1_bypass_hint = stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p1_bypass_hint = stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p2_bypass_hint = stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p2_bypass_hint = stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p3_bypass_hint = stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p3_bypass_hint = stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_dis_col_sel = stq_uop_23_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_dis_col_sel = stq_uop_23_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_23_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_26_br_mask = stq_uop_23_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_24_br_mask = stq_uop_23_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_23_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_26_br_tag = stq_uop_23_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_24_br_tag = stq_uop_23_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_23_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_26_br_type = stq_uop_23_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_24_br_type = stq_uop_23_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sfb; // @[lsu.scala:252:32] wire s_uop_26_is_sfb = stq_uop_23_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sfb = stq_uop_23_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_fence; // @[lsu.scala:252:32] wire s_uop_26_is_fence = stq_uop_23_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_fence = stq_uop_23_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_fencei; // @[lsu.scala:252:32] wire s_uop_26_is_fencei = stq_uop_23_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_fencei = stq_uop_23_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sfence; // @[lsu.scala:252:32] wire s_uop_26_is_sfence = stq_uop_23_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sfence = stq_uop_23_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_amo; // @[lsu.scala:252:32] wire s_uop_26_is_amo = stq_uop_23_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_amo = stq_uop_23_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_eret; // @[lsu.scala:252:32] wire s_uop_26_is_eret = stq_uop_23_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_eret = stq_uop_23_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_26_is_sys_pc2epc = stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sys_pc2epc = stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_rocc; // @[lsu.scala:252:32] wire s_uop_26_is_rocc = stq_uop_23_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_rocc = stq_uop_23_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_mov; // @[lsu.scala:252:32] wire s_uop_26_is_mov = stq_uop_23_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_mov = stq_uop_23_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ftq_idx = stq_uop_23_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ftq_idx = stq_uop_23_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_edge_inst; // @[lsu.scala:252:32] wire s_uop_26_edge_inst = stq_uop_23_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_24_edge_inst = stq_uop_23_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_26_pc_lob = stq_uop_23_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_pc_lob = stq_uop_23_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_taken; // @[lsu.scala:252:32] wire s_uop_26_taken = stq_uop_23_taken; // @[lsu.scala:252:32, :1324:37] wire uop_24_taken = stq_uop_23_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_imm_rename; // @[lsu.scala:252:32] wire s_uop_26_imm_rename = stq_uop_23_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_24_imm_rename = stq_uop_23_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_imm_sel = stq_uop_23_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_imm_sel = stq_uop_23_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_26_pimm = stq_uop_23_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_pimm = stq_uop_23_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_23_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_26_imm_packed = stq_uop_23_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_24_imm_packed = stq_uop_23_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_26_op1_sel = stq_uop_23_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_op1_sel = stq_uop_23_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_op2_sel = stq_uop_23_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_op2_sel = stq_uop_23_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ldst = stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ldst = stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_wen = stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_wen = stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren1 = stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren1 = stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren2 = stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren2 = stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren3 = stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren3 = stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_swap12 = stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_swap12 = stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_swap23 = stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_swap23 = stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_ctrl_typeTagIn = stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_ctrl_typeTagIn = stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_ctrl_typeTagOut = stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_ctrl_typeTagOut = stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fromint = stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fromint = stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_toint = stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_toint = stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fastpipe = stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fastpipe = stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fma = stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fma = stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_div = stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_div = stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_sqrt = stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_sqrt = stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_wflags = stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_wflags = stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_vec = stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_vec = stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_26_rob_idx = stq_uop_23_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_rob_idx = stq_uop_23_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ldq_idx = stq_uop_23_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ldq_idx = stq_uop_23_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_stq_idx = stq_uop_23_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_stq_idx = stq_uop_23_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_26_rxq_idx = stq_uop_23_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_rxq_idx = stq_uop_23_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_26_pdst = stq_uop_23_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_pdst = stq_uop_23_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs1 = stq_uop_23_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs1 = stq_uop_23_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs2 = stq_uop_23_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs2 = stq_uop_23_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs3 = stq_uop_23_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs3 = stq_uop_23_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ppred = stq_uop_23_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ppred = stq_uop_23_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs1_busy; // @[lsu.scala:252:32] wire s_uop_26_prs1_busy = stq_uop_23_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs1_busy = stq_uop_23_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs2_busy; // @[lsu.scala:252:32] wire s_uop_26_prs2_busy = stq_uop_23_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs2_busy = stq_uop_23_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs3_busy; // @[lsu.scala:252:32] wire s_uop_26_prs3_busy = stq_uop_23_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs3_busy = stq_uop_23_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_ppred_busy; // @[lsu.scala:252:32] wire s_uop_26_ppred_busy = stq_uop_23_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_ppred_busy = stq_uop_23_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_26_stale_pdst = stq_uop_23_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_stale_pdst = stq_uop_23_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_exception; // @[lsu.scala:252:32] wire s_uop_26_exception = stq_uop_23_exception; // @[lsu.scala:252:32, :1324:37] wire uop_24_exception = stq_uop_23_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_23_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_26_exc_cause = stq_uop_23_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_24_exc_cause = stq_uop_23_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_26_mem_cmd = stq_uop_23_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_mem_cmd = stq_uop_23_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_26_mem_size = stq_uop_23_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_mem_size = stq_uop_23_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_mem_signed; // @[lsu.scala:252:32] wire s_uop_26_mem_signed = stq_uop_23_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_24_mem_signed = stq_uop_23_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_uses_ldq; // @[lsu.scala:252:32] wire s_uop_26_uses_ldq = stq_uop_23_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_24_uses_ldq = stq_uop_23_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_uses_stq; // @[lsu.scala:252:32] wire s_uop_26_uses_stq = stq_uop_23_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_24_uses_stq = stq_uop_23_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_unique; // @[lsu.scala:252:32] wire s_uop_26_is_unique = stq_uop_23_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_unique = stq_uop_23_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_26_flush_on_commit = stq_uop_23_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_24_flush_on_commit = stq_uop_23_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_26_csr_cmd = stq_uop_23_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_csr_cmd = stq_uop_23_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_26_ldst_is_rs1 = stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_24_ldst_is_rs1 = stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_26_ldst = stq_uop_23_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_ldst = stq_uop_23_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs1 = stq_uop_23_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs1 = stq_uop_23_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs2 = stq_uop_23_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs2 = stq_uop_23_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs3 = stq_uop_23_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs3 = stq_uop_23_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_dst_rtype = stq_uop_23_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_dst_rtype = stq_uop_23_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_lrs1_rtype = stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_lrs1_rtype = stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_lrs2_rtype = stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_lrs2_rtype = stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_frs3_en; // @[lsu.scala:252:32] wire s_uop_26_frs3_en = stq_uop_23_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_24_frs3_en = stq_uop_23_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fcn_dw; // @[lsu.scala:252:32] wire s_uop_26_fcn_dw = stq_uop_23_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_24_fcn_dw = stq_uop_23_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_26_fcn_op = stq_uop_23_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_fcn_op = stq_uop_23_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_val; // @[lsu.scala:252:32] wire s_uop_26_fp_val = stq_uop_23_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_val = stq_uop_23_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_26_fp_rm = stq_uop_23_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_fp_rm = stq_uop_23_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_typ = stq_uop_23_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_typ = stq_uop_23_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_pf_if = stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_pf_if = stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_ae_if = stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_ae_if = stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_ma_if = stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_ma_if = stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_26_bp_debug_if = stq_uop_23_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_bp_debug_if = stq_uop_23_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_26_bp_xcpt_if = stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_bp_xcpt_if = stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_26_debug_fsrc = stq_uop_23_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_debug_fsrc = stq_uop_23_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_26_debug_tsrc = stq_uop_23_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_debug_tsrc = stq_uop_23_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg stq_addr_0_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_0_bits; // @[lsu.scala:253:32] reg stq_addr_1_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_1_bits; // @[lsu.scala:253:32] reg stq_addr_2_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_2_bits; // @[lsu.scala:253:32] reg stq_addr_3_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_3_bits; // @[lsu.scala:253:32] reg stq_addr_4_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_4_bits; // @[lsu.scala:253:32] reg stq_addr_5_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_5_bits; // @[lsu.scala:253:32] reg stq_addr_6_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_6_bits; // @[lsu.scala:253:32] reg stq_addr_7_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_7_bits; // @[lsu.scala:253:32] reg stq_addr_8_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_8_bits; // @[lsu.scala:253:32] reg stq_addr_9_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_9_bits; // @[lsu.scala:253:32] reg stq_addr_10_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_10_bits; // @[lsu.scala:253:32] reg stq_addr_11_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_11_bits; // @[lsu.scala:253:32] reg stq_addr_12_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_12_bits; // @[lsu.scala:253:32] reg stq_addr_13_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_13_bits; // @[lsu.scala:253:32] reg stq_addr_14_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_14_bits; // @[lsu.scala:253:32] reg stq_addr_15_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_15_bits; // @[lsu.scala:253:32] reg stq_addr_16_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_16_bits; // @[lsu.scala:253:32] reg stq_addr_17_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_17_bits; // @[lsu.scala:253:32] reg stq_addr_18_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_18_bits; // @[lsu.scala:253:32] reg stq_addr_19_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_19_bits; // @[lsu.scala:253:32] reg stq_addr_20_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_20_bits; // @[lsu.scala:253:32] reg stq_addr_21_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_21_bits; // @[lsu.scala:253:32] reg stq_addr_22_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_22_bits; // @[lsu.scala:253:32] reg stq_addr_23_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_23_bits; // @[lsu.scala:253:32] reg stq_addr_is_virtual_0; // @[lsu.scala:254:32] reg stq_addr_is_virtual_1; // @[lsu.scala:254:32] reg stq_addr_is_virtual_2; // @[lsu.scala:254:32] reg stq_addr_is_virtual_3; // @[lsu.scala:254:32] reg stq_addr_is_virtual_4; // @[lsu.scala:254:32] reg stq_addr_is_virtual_5; // @[lsu.scala:254:32] reg stq_addr_is_virtual_6; // @[lsu.scala:254:32] reg stq_addr_is_virtual_7; // @[lsu.scala:254:32] reg stq_addr_is_virtual_8; // @[lsu.scala:254:32] reg stq_addr_is_virtual_9; // @[lsu.scala:254:32] reg stq_addr_is_virtual_10; // @[lsu.scala:254:32] reg stq_addr_is_virtual_11; // @[lsu.scala:254:32] reg stq_addr_is_virtual_12; // @[lsu.scala:254:32] reg stq_addr_is_virtual_13; // @[lsu.scala:254:32] reg stq_addr_is_virtual_14; // @[lsu.scala:254:32] reg stq_addr_is_virtual_15; // @[lsu.scala:254:32] reg stq_addr_is_virtual_16; // @[lsu.scala:254:32] reg stq_addr_is_virtual_17; // @[lsu.scala:254:32] reg stq_addr_is_virtual_18; // @[lsu.scala:254:32] reg stq_addr_is_virtual_19; // @[lsu.scala:254:32] reg stq_addr_is_virtual_20; // @[lsu.scala:254:32] reg stq_addr_is_virtual_21; // @[lsu.scala:254:32] reg stq_addr_is_virtual_22; // @[lsu.scala:254:32] reg stq_addr_is_virtual_23; // @[lsu.scala:254:32] reg stq_data_0_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_0_bits; // @[lsu.scala:255:32] reg stq_data_1_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_1_bits; // @[lsu.scala:255:32] reg stq_data_2_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_2_bits; // @[lsu.scala:255:32] reg stq_data_3_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_3_bits; // @[lsu.scala:255:32] reg stq_data_4_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_4_bits; // @[lsu.scala:255:32] reg stq_data_5_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_5_bits; // @[lsu.scala:255:32] reg stq_data_6_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_6_bits; // @[lsu.scala:255:32] reg stq_data_7_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_7_bits; // @[lsu.scala:255:32] reg stq_data_8_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_8_bits; // @[lsu.scala:255:32] reg stq_data_9_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_9_bits; // @[lsu.scala:255:32] reg stq_data_10_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_10_bits; // @[lsu.scala:255:32] reg stq_data_11_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_11_bits; // @[lsu.scala:255:32] reg stq_data_12_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_12_bits; // @[lsu.scala:255:32] reg stq_data_13_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_13_bits; // @[lsu.scala:255:32] reg stq_data_14_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_14_bits; // @[lsu.scala:255:32] reg stq_data_15_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_15_bits; // @[lsu.scala:255:32] reg stq_data_16_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_16_bits; // @[lsu.scala:255:32] reg stq_data_17_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_17_bits; // @[lsu.scala:255:32] reg stq_data_18_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_18_bits; // @[lsu.scala:255:32] reg stq_data_19_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_19_bits; // @[lsu.scala:255:32] reg stq_data_20_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_20_bits; // @[lsu.scala:255:32] reg stq_data_21_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_21_bits; // @[lsu.scala:255:32] reg stq_data_22_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_22_bits; // @[lsu.scala:255:32] reg stq_data_23_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_23_bits; // @[lsu.scala:255:32] reg stq_committed_0; // @[lsu.scala:256:32] reg stq_committed_1; // @[lsu.scala:256:32] reg stq_committed_2; // @[lsu.scala:256:32] reg stq_committed_3; // @[lsu.scala:256:32] reg stq_committed_4; // @[lsu.scala:256:32] reg stq_committed_5; // @[lsu.scala:256:32] reg stq_committed_6; // @[lsu.scala:256:32] reg stq_committed_7; // @[lsu.scala:256:32] reg stq_committed_8; // @[lsu.scala:256:32] reg stq_committed_9; // @[lsu.scala:256:32] reg stq_committed_10; // @[lsu.scala:256:32] reg stq_committed_11; // @[lsu.scala:256:32] reg stq_committed_12; // @[lsu.scala:256:32] reg stq_committed_13; // @[lsu.scala:256:32] reg stq_committed_14; // @[lsu.scala:256:32] reg stq_committed_15; // @[lsu.scala:256:32] reg stq_committed_16; // @[lsu.scala:256:32] reg stq_committed_17; // @[lsu.scala:256:32] reg stq_committed_18; // @[lsu.scala:256:32] reg stq_committed_19; // @[lsu.scala:256:32] reg stq_committed_20; // @[lsu.scala:256:32] reg stq_committed_21; // @[lsu.scala:256:32] reg stq_committed_22; // @[lsu.scala:256:32] reg stq_committed_23; // @[lsu.scala:256:32] reg stq_succeeded_0; // @[lsu.scala:257:32] reg stq_succeeded_1; // @[lsu.scala:257:32] reg stq_succeeded_2; // @[lsu.scala:257:32] reg stq_succeeded_3; // @[lsu.scala:257:32] reg stq_succeeded_4; // @[lsu.scala:257:32] reg stq_succeeded_5; // @[lsu.scala:257:32] reg stq_succeeded_6; // @[lsu.scala:257:32] reg stq_succeeded_7; // @[lsu.scala:257:32] reg stq_succeeded_8; // @[lsu.scala:257:32] reg stq_succeeded_9; // @[lsu.scala:257:32] reg stq_succeeded_10; // @[lsu.scala:257:32] reg stq_succeeded_11; // @[lsu.scala:257:32] reg stq_succeeded_12; // @[lsu.scala:257:32] reg stq_succeeded_13; // @[lsu.scala:257:32] reg stq_succeeded_14; // @[lsu.scala:257:32] reg stq_succeeded_15; // @[lsu.scala:257:32] reg stq_succeeded_16; // @[lsu.scala:257:32] reg stq_succeeded_17; // @[lsu.scala:257:32] reg stq_succeeded_18; // @[lsu.scala:257:32] reg stq_succeeded_19; // @[lsu.scala:257:32] reg stq_succeeded_20; // @[lsu.scala:257:32] reg stq_succeeded_21; // @[lsu.scala:257:32] reg stq_succeeded_22; // @[lsu.scala:257:32] reg stq_succeeded_23; // @[lsu.scala:257:32] reg stq_can_execute_0; // @[lsu.scala:258:32] reg stq_can_execute_1; // @[lsu.scala:258:32] reg stq_can_execute_2; // @[lsu.scala:258:32] reg stq_can_execute_3; // @[lsu.scala:258:32] reg stq_can_execute_4; // @[lsu.scala:258:32] reg stq_can_execute_5; // @[lsu.scala:258:32] reg stq_can_execute_6; // @[lsu.scala:258:32] reg stq_can_execute_7; // @[lsu.scala:258:32] reg stq_can_execute_8; // @[lsu.scala:258:32] reg stq_can_execute_9; // @[lsu.scala:258:32] reg stq_can_execute_10; // @[lsu.scala:258:32] reg stq_can_execute_11; // @[lsu.scala:258:32] reg stq_can_execute_12; // @[lsu.scala:258:32] reg stq_can_execute_13; // @[lsu.scala:258:32] reg stq_can_execute_14; // @[lsu.scala:258:32] reg stq_can_execute_15; // @[lsu.scala:258:32] reg stq_can_execute_16; // @[lsu.scala:258:32] reg stq_can_execute_17; // @[lsu.scala:258:32] reg stq_can_execute_18; // @[lsu.scala:258:32] reg stq_can_execute_19; // @[lsu.scala:258:32] reg stq_can_execute_20; // @[lsu.scala:258:32] reg stq_can_execute_21; // @[lsu.scala:258:32] reg stq_can_execute_22; // @[lsu.scala:258:32] reg stq_can_execute_23; // @[lsu.scala:258:32] reg stq_cleared_0; // @[lsu.scala:259:32] reg stq_cleared_1; // @[lsu.scala:259:32] reg stq_cleared_2; // @[lsu.scala:259:32] reg stq_cleared_3; // @[lsu.scala:259:32] reg stq_cleared_4; // @[lsu.scala:259:32] reg stq_cleared_5; // @[lsu.scala:259:32] reg stq_cleared_6; // @[lsu.scala:259:32] reg stq_cleared_7; // @[lsu.scala:259:32] reg stq_cleared_8; // @[lsu.scala:259:32] reg stq_cleared_9; // @[lsu.scala:259:32] reg stq_cleared_10; // @[lsu.scala:259:32] reg stq_cleared_11; // @[lsu.scala:259:32] reg stq_cleared_12; // @[lsu.scala:259:32] reg stq_cleared_13; // @[lsu.scala:259:32] reg stq_cleared_14; // @[lsu.scala:259:32] reg stq_cleared_15; // @[lsu.scala:259:32] reg stq_cleared_16; // @[lsu.scala:259:32] reg stq_cleared_17; // @[lsu.scala:259:32] reg stq_cleared_18; // @[lsu.scala:259:32] reg stq_cleared_19; // @[lsu.scala:259:32] reg stq_cleared_20; // @[lsu.scala:259:32] reg stq_cleared_21; // @[lsu.scala:259:32] reg stq_cleared_22; // @[lsu.scala:259:32] reg stq_cleared_23; // @[lsu.scala:259:32] reg [63:0] stq_debug_wb_data_0; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_1; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_2; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_3; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_4; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_5; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_6; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_7; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_8; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_9; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_10; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_11; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_12; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_13; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_14; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_15; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_16; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_17; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_18; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_19; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_20; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_21; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_22; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_23; // @[lsu.scala:260:32] reg [4:0] ldq_head; // @[lsu.scala:278:29] reg [4:0] ldq_tail; // @[lsu.scala:279:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:211:7, :279:29] reg [4:0] stq_head; // @[lsu.scala:280:29] reg [4:0] stq_tail; // @[lsu.scala:281:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:211:7, :281:29] reg [4:0] stq_commit_head; // @[lsu.scala:282:29] reg [4:0] stq_execute_head; // @[lsu.scala:283:29] reg [2:0] hella_state; // @[lsu.scala:301:38] reg [39:0] hella_req_addr; // @[lsu.scala:302:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:211:7, :302:34] reg hella_req_dv; // @[lsu.scala:302:34] reg [63:0] hella_data_data; // @[lsu.scala:303:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:303:34] reg [31:0] hella_paddr; // @[lsu.scala:304:34] reg hella_xcpt_ma_ld; // @[lsu.scala:305:34] reg hella_xcpt_ma_st; // @[lsu.scala:305:34] reg hella_xcpt_pf_ld; // @[lsu.scala:305:34] reg hella_xcpt_pf_st; // @[lsu.scala:305:34] reg hella_xcpt_gf_ld; // @[lsu.scala:305:34] reg hella_xcpt_gf_st; // @[lsu.scala:305:34] reg hella_xcpt_ae_ld; // @[lsu.scala:305:34] reg hella_xcpt_ae_st; // @[lsu.scala:305:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:318:33] wire ldq_will_succeed_0; // @[lsu.scala:325:44] wire ldq_will_succeed_1; // @[lsu.scala:325:44] wire ldq_will_succeed_2; // @[lsu.scala:325:44] wire ldq_will_succeed_3; // @[lsu.scala:325:44] wire ldq_will_succeed_4; // @[lsu.scala:325:44] wire ldq_will_succeed_5; // @[lsu.scala:325:44] wire ldq_will_succeed_6; // @[lsu.scala:325:44] wire ldq_will_succeed_7; // @[lsu.scala:325:44] wire ldq_will_succeed_8; // @[lsu.scala:325:44] wire ldq_will_succeed_9; // @[lsu.scala:325:44] wire ldq_will_succeed_10; // @[lsu.scala:325:44] wire ldq_will_succeed_11; // @[lsu.scala:325:44] wire ldq_will_succeed_12; // @[lsu.scala:325:44] wire ldq_will_succeed_13; // @[lsu.scala:325:44] wire ldq_will_succeed_14; // @[lsu.scala:325:44] wire ldq_will_succeed_15; // @[lsu.scala:325:44] wire ldq_will_succeed_16; // @[lsu.scala:325:44] wire ldq_will_succeed_17; // @[lsu.scala:325:44] wire ldq_will_succeed_18; // @[lsu.scala:325:44] wire ldq_will_succeed_19; // @[lsu.scala:325:44] wire ldq_will_succeed_20; // @[lsu.scala:325:44] wire ldq_will_succeed_21; // @[lsu.scala:325:44] wire ldq_will_succeed_22; // @[lsu.scala:325:44] wire ldq_will_succeed_23; // @[lsu.scala:325:44] wire [31:0] _GEN = 32'h1 << stq_head; // @[lsu.scala:280:29, :340:56] wire [31:0] _ldq_st_dep_mask_0_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_0_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_1_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_1_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_2_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_2_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_3_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_3_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_4_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_4_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_5_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_5_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_6_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_6_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_7_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_7_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_8_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_8_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_9_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_9_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_10_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_10_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_11_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_11_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_12_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_12_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_13_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_13_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_14_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_14_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_15_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_15_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_16_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_16_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_17_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_17_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_18_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_18_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_19_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_19_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_20_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_20_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_21_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_21_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_22_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_22_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_23_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_23_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _next_live_store_mask_T; // @[lsu.scala:355:71] assign _next_live_store_mask_T = _GEN; // @[lsu.scala:340:56, :355:71] wire [31:0] _ldq_st_dep_mask_0_T_1 = ~_ldq_st_dep_mask_0_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_0_T_2 = {8'h0, _ldq_st_dep_mask_0_T_1[23:0] & ldq_st_dep_mask_0}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_1_T_1 = ~_ldq_st_dep_mask_1_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_1_T_2 = {8'h0, _ldq_st_dep_mask_1_T_1[23:0] & ldq_st_dep_mask_1}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_2_T_1 = ~_ldq_st_dep_mask_2_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_2_T_2 = {8'h0, _ldq_st_dep_mask_2_T_1[23:0] & ldq_st_dep_mask_2}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_3_T_1 = ~_ldq_st_dep_mask_3_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_3_T_2 = {8'h0, _ldq_st_dep_mask_3_T_1[23:0] & ldq_st_dep_mask_3}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_4_T_1 = ~_ldq_st_dep_mask_4_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_4_T_2 = {8'h0, _ldq_st_dep_mask_4_T_1[23:0] & ldq_st_dep_mask_4}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_5_T_1 = ~_ldq_st_dep_mask_5_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_5_T_2 = {8'h0, _ldq_st_dep_mask_5_T_1[23:0] & ldq_st_dep_mask_5}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_6_T_1 = ~_ldq_st_dep_mask_6_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_6_T_2 = {8'h0, _ldq_st_dep_mask_6_T_1[23:0] & ldq_st_dep_mask_6}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_7_T_1 = ~_ldq_st_dep_mask_7_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_7_T_2 = {8'h0, _ldq_st_dep_mask_7_T_1[23:0] & ldq_st_dep_mask_7}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_8_T_1 = ~_ldq_st_dep_mask_8_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_8_T_2 = {8'h0, _ldq_st_dep_mask_8_T_1[23:0] & ldq_st_dep_mask_8}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_9_T_1 = ~_ldq_st_dep_mask_9_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_9_T_2 = {8'h0, _ldq_st_dep_mask_9_T_1[23:0] & ldq_st_dep_mask_9}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_10_T_1 = ~_ldq_st_dep_mask_10_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_10_T_2 = {8'h0, _ldq_st_dep_mask_10_T_1[23:0] & ldq_st_dep_mask_10}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_11_T_1 = ~_ldq_st_dep_mask_11_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_11_T_2 = {8'h0, _ldq_st_dep_mask_11_T_1[23:0] & ldq_st_dep_mask_11}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_12_T_1 = ~_ldq_st_dep_mask_12_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_12_T_2 = {8'h0, _ldq_st_dep_mask_12_T_1[23:0] & ldq_st_dep_mask_12}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_13_T_1 = ~_ldq_st_dep_mask_13_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_13_T_2 = {8'h0, _ldq_st_dep_mask_13_T_1[23:0] & ldq_st_dep_mask_13}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_14_T_1 = ~_ldq_st_dep_mask_14_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_14_T_2 = {8'h0, _ldq_st_dep_mask_14_T_1[23:0] & ldq_st_dep_mask_14}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_15_T_1 = ~_ldq_st_dep_mask_15_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_15_T_2 = {8'h0, _ldq_st_dep_mask_15_T_1[23:0] & ldq_st_dep_mask_15}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_16_T_1 = ~_ldq_st_dep_mask_16_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_16_T_2 = {8'h0, _ldq_st_dep_mask_16_T_1[23:0] & ldq_st_dep_mask_16}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_17_T_1 = ~_ldq_st_dep_mask_17_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_17_T_2 = {8'h0, _ldq_st_dep_mask_17_T_1[23:0] & ldq_st_dep_mask_17}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_18_T_1 = ~_ldq_st_dep_mask_18_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_18_T_2 = {8'h0, _ldq_st_dep_mask_18_T_1[23:0] & ldq_st_dep_mask_18}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_19_T_1 = ~_ldq_st_dep_mask_19_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_19_T_2 = {8'h0, _ldq_st_dep_mask_19_T_1[23:0] & ldq_st_dep_mask_19}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_20_T_1 = ~_ldq_st_dep_mask_20_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_20_T_2 = {8'h0, _ldq_st_dep_mask_20_T_1[23:0] & ldq_st_dep_mask_20}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_21_T_1 = ~_ldq_st_dep_mask_21_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_21_T_2 = {8'h0, _ldq_st_dep_mask_21_T_1[23:0] & ldq_st_dep_mask_21}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_22_T_1 = ~_ldq_st_dep_mask_22_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_22_T_2 = {8'h0, _ldq_st_dep_mask_22_T_1[23:0] & ldq_st_dep_mask_22}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_23_T_1 = ~_ldq_st_dep_mask_23_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_23_T_2 = {8'h0, _ldq_st_dep_mask_23_T_1[23:0] & ldq_st_dep_mask_23}; // @[lsu.scala:227:36, :340:{48,50}] reg dis_ldq_oh_0; // @[lsu.scala:348:23] reg dis_ldq_oh_1; // @[lsu.scala:348:23] reg dis_ldq_oh_2; // @[lsu.scala:348:23] reg dis_ldq_oh_3; // @[lsu.scala:348:23] reg dis_ldq_oh_4; // @[lsu.scala:348:23] reg dis_ldq_oh_5; // @[lsu.scala:348:23] reg dis_ldq_oh_6; // @[lsu.scala:348:23] reg dis_ldq_oh_7; // @[lsu.scala:348:23] reg dis_ldq_oh_8; // @[lsu.scala:348:23] reg dis_ldq_oh_9; // @[lsu.scala:348:23] reg dis_ldq_oh_10; // @[lsu.scala:348:23] reg dis_ldq_oh_11; // @[lsu.scala:348:23] reg dis_ldq_oh_12; // @[lsu.scala:348:23] reg dis_ldq_oh_13; // @[lsu.scala:348:23] reg dis_ldq_oh_14; // @[lsu.scala:348:23] reg dis_ldq_oh_15; // @[lsu.scala:348:23] reg dis_ldq_oh_16; // @[lsu.scala:348:23] reg dis_ldq_oh_17; // @[lsu.scala:348:23] reg dis_ldq_oh_18; // @[lsu.scala:348:23] reg dis_ldq_oh_19; // @[lsu.scala:348:23] reg dis_ldq_oh_20; // @[lsu.scala:348:23] reg dis_ldq_oh_21; // @[lsu.scala:348:23] reg dis_ldq_oh_22; // @[lsu.scala:348:23] reg dis_ldq_oh_23; // @[lsu.scala:348:23] reg dis_stq_oh_0; // @[lsu.scala:349:23] reg dis_stq_oh_1; // @[lsu.scala:349:23] reg dis_stq_oh_2; // @[lsu.scala:349:23] reg dis_stq_oh_3; // @[lsu.scala:349:23] reg dis_stq_oh_4; // @[lsu.scala:349:23] reg dis_stq_oh_5; // @[lsu.scala:349:23] reg dis_stq_oh_6; // @[lsu.scala:349:23] reg dis_stq_oh_7; // @[lsu.scala:349:23] reg dis_stq_oh_8; // @[lsu.scala:349:23] reg dis_stq_oh_9; // @[lsu.scala:349:23] reg dis_stq_oh_10; // @[lsu.scala:349:23] reg dis_stq_oh_11; // @[lsu.scala:349:23] reg dis_stq_oh_12; // @[lsu.scala:349:23] reg dis_stq_oh_13; // @[lsu.scala:349:23] reg dis_stq_oh_14; // @[lsu.scala:349:23] reg dis_stq_oh_15; // @[lsu.scala:349:23] reg dis_stq_oh_16; // @[lsu.scala:349:23] reg dis_stq_oh_17; // @[lsu.scala:349:23] reg dis_stq_oh_18; // @[lsu.scala:349:23] reg dis_stq_oh_19; // @[lsu.scala:349:23] reg dis_stq_oh_20; // @[lsu.scala:349:23] reg dis_stq_oh_21; // @[lsu.scala:349:23] reg dis_stq_oh_22; // @[lsu.scala:349:23] reg dis_stq_oh_23; // @[lsu.scala:349:23] reg dis_uops_0_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_0_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_0_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_0_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_0_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_0_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_0_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_0_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] reg dis_uops_0_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_0_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] reg dis_uops_0_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] reg dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_0_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_0_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_0_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_0_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] wire stq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] reg dis_uops_0_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_0_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] reg dis_uops_0_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_0_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_0_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] wire stq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_0_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] reg dis_uops_0_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_0_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_0_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] reg dis_uops_0_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_0_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_0_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_0_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_1_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_1_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_1_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_1_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_1_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_1_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_1_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_1_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] reg dis_uops_1_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_1_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] reg dis_uops_1_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] reg dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_1_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_1_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_1_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_1_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] wire stq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] reg dis_uops_1_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_1_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] reg dis_uops_1_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_1_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_1_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] wire stq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_1_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] reg dis_uops_1_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_1_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_1_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] reg dis_uops_1_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_1_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_1_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_1_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_2_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_2_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_2_inst = dis_uops_2_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_2_inst = dis_uops_2_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_2_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_2_debug_inst = dis_uops_2_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_2_debug_inst = dis_uops_2_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_2_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_rvc = dis_uops_2_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_2_is_rvc = dis_uops_2_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_2_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_2_debug_pc = dis_uops_2_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_2_debug_pc = dis_uops_2_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_0 = dis_uops_2_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_0 = dis_uops_2_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_1 = dis_uops_2_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_1 = dis_uops_2_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_2 = dis_uops_2_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_2 = dis_uops_2_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_3 = dis_uops_2_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_3 = dis_uops_2_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_0 = dis_uops_2_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_0 = dis_uops_2_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_1 = dis_uops_2_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_1 = dis_uops_2_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_2 = dis_uops_2_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_2 = dis_uops_2_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_3 = dis_uops_2_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_3 = dis_uops_2_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_4 = dis_uops_2_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_4 = dis_uops_2_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_5 = dis_uops_2_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_5 = dis_uops_2_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_6 = dis_uops_2_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_6 = dis_uops_2_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_7 = dis_uops_2_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_7 = dis_uops_2_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_8 = dis_uops_2_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_8 = dis_uops_2_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_9 = dis_uops_2_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_9 = dis_uops_2_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued = dis_uops_2_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued = dis_uops_2_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued_partial_agen = dis_uops_2_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued_partial_agen = dis_uops_2_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued_partial_dgen = dis_uops_2_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued_partial_dgen = dis_uops_2_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_iw_p1_speculative_child = dis_uops_2_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_iw_p1_speculative_child = dis_uops_2_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_iw_p2_speculative_child = dis_uops_2_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_iw_p2_speculative_child = dis_uops_2_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p1_bypass_hint = dis_uops_2_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p1_bypass_hint = dis_uops_2_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p2_bypass_hint = dis_uops_2_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p2_bypass_hint = dis_uops_2_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p3_bypass_hint = dis_uops_2_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p3_bypass_hint = dis_uops_2_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_dis_col_sel = dis_uops_2_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_dis_col_sel = dis_uops_2_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_2_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_2_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_2_br_tag = dis_uops_2_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_2_br_tag = dis_uops_2_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_2_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_2_br_type = dis_uops_2_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_2_br_type = dis_uops_2_bits_br_type; // @[util.scala:104:23] reg dis_uops_2_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sfb = dis_uops_2_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_2_is_sfb = dis_uops_2_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_2_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_fence = dis_uops_2_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_2_is_fence = dis_uops_2_bits_is_fence; // @[util.scala:104:23] reg dis_uops_2_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_fencei = dis_uops_2_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_2_is_fencei = dis_uops_2_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_2_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sfence = dis_uops_2_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_2_is_sfence = dis_uops_2_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_2_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_amo = dis_uops_2_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_2_is_amo = dis_uops_2_bits_is_amo; // @[util.scala:104:23] reg dis_uops_2_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_eret = dis_uops_2_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_2_is_eret = dis_uops_2_bits_is_eret; // @[util.scala:104:23] reg dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sys_pc2epc = dis_uops_2_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_2_is_sys_pc2epc = dis_uops_2_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_2_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_rocc = dis_uops_2_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_2_is_rocc = dis_uops_2_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_2_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_mov = dis_uops_2_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_2_is_mov = dis_uops_2_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ftq_idx = dis_uops_2_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ftq_idx = dis_uops_2_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_2_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_2_edge_inst = dis_uops_2_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_2_edge_inst = dis_uops_2_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_pc_lob = dis_uops_2_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_pc_lob = dis_uops_2_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_2_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_2_taken = dis_uops_2_bits_taken; // @[util.scala:104:23] wire stq_uop_out_2_taken = dis_uops_2_bits_taken; // @[util.scala:104:23] reg dis_uops_2_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_2_imm_rename = dis_uops_2_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_2_imm_rename = dis_uops_2_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_imm_sel = dis_uops_2_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_imm_sel = dis_uops_2_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_pimm = dis_uops_2_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_pimm = dis_uops_2_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_2_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_2_imm_packed = dis_uops_2_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_2_imm_packed = dis_uops_2_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_op1_sel = dis_uops_2_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_op1_sel = dis_uops_2_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_op2_sel = dis_uops_2_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_op2_sel = dis_uops_2_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ldst = dis_uops_2_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ldst = dis_uops_2_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_wen = dis_uops_2_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_wen = dis_uops_2_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren1 = dis_uops_2_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren1 = dis_uops_2_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren2 = dis_uops_2_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren2 = dis_uops_2_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren3 = dis_uops_2_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren3 = dis_uops_2_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_swap12 = dis_uops_2_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_swap12 = dis_uops_2_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_swap23 = dis_uops_2_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_swap23 = dis_uops_2_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_ctrl_typeTagIn = dis_uops_2_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_ctrl_typeTagIn = dis_uops_2_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_ctrl_typeTagOut = dis_uops_2_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_ctrl_typeTagOut = dis_uops_2_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fromint = dis_uops_2_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fromint = dis_uops_2_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_toint = dis_uops_2_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_toint = dis_uops_2_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fastpipe = dis_uops_2_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fastpipe = dis_uops_2_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fma = dis_uops_2_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fma = dis_uops_2_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_div = dis_uops_2_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_div = dis_uops_2_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_sqrt = dis_uops_2_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_sqrt = dis_uops_2_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_wflags = dis_uops_2_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_wflags = dis_uops_2_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_vec = dis_uops_2_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_vec = dis_uops_2_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_rob_idx = dis_uops_2_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_rob_idx = dis_uops_2_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ldq_idx = dis_uops_2_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ldq_idx = dis_uops_2_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_stq_idx = dis_uops_2_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_stq_idx = dis_uops_2_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_rxq_idx = dis_uops_2_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_rxq_idx = dis_uops_2_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_pdst = dis_uops_2_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_pdst = dis_uops_2_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs1 = dis_uops_2_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs1 = dis_uops_2_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs2 = dis_uops_2_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs2 = dis_uops_2_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs3 = dis_uops_2_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs3 = dis_uops_2_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ppred = dis_uops_2_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ppred = dis_uops_2_bits_ppred; // @[util.scala:104:23] reg dis_uops_2_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs1_busy = dis_uops_2_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs1_busy = dis_uops_2_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_2_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs2_busy = dis_uops_2_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs2_busy = dis_uops_2_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_2_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs3_busy = dis_uops_2_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs3_busy = dis_uops_2_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_2_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_ppred_busy = dis_uops_2_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_2_ppred_busy = dis_uops_2_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_stale_pdst = dis_uops_2_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_stale_pdst = dis_uops_2_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_2_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_2_exception = dis_uops_2_bits_exception; // @[util.scala:104:23] wire stq_uop_out_2_exception = dis_uops_2_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_2_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_2_exc_cause = dis_uops_2_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_2_exc_cause = dis_uops_2_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_mem_cmd = dis_uops_2_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_mem_cmd = dis_uops_2_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_mem_size = dis_uops_2_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_mem_size = dis_uops_2_bits_mem_size; // @[util.scala:104:23] reg dis_uops_2_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_2_mem_signed = dis_uops_2_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_2_mem_signed = dis_uops_2_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_2_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_2_uses_ldq = dis_uops_2_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_2_uses_ldq = dis_uops_2_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_2_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_2_uses_stq = dis_uops_2_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_2_uses_stq = dis_uops_2_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_2_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_unique = dis_uops_2_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_2_is_unique = dis_uops_2_bits_is_unique; // @[util.scala:104:23] reg dis_uops_2_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_2_flush_on_commit = dis_uops_2_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_2_flush_on_commit = dis_uops_2_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_csr_cmd = dis_uops_2_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_csr_cmd = dis_uops_2_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_2_ldst_is_rs1 = dis_uops_2_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_2_ldst_is_rs1 = dis_uops_2_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_ldst = dis_uops_2_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_ldst = dis_uops_2_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs1 = dis_uops_2_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs1 = dis_uops_2_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs2 = dis_uops_2_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs2 = dis_uops_2_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs3 = dis_uops_2_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs3 = dis_uops_2_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_dst_rtype = dis_uops_2_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_dst_rtype = dis_uops_2_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_lrs1_rtype = dis_uops_2_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_lrs1_rtype = dis_uops_2_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_lrs2_rtype = dis_uops_2_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_lrs2_rtype = dis_uops_2_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_2_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_2_frs3_en = dis_uops_2_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_2_frs3_en = dis_uops_2_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_2_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_2_fcn_dw = dis_uops_2_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_2_fcn_dw = dis_uops_2_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_fcn_op = dis_uops_2_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_fcn_op = dis_uops_2_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_2_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_val = dis_uops_2_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_2_fp_val = dis_uops_2_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_fp_rm = dis_uops_2_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_fp_rm = dis_uops_2_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_typ = dis_uops_2_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_typ = dis_uops_2_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_pf_if = dis_uops_2_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_pf_if = dis_uops_2_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_ae_if = dis_uops_2_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_ae_if = dis_uops_2_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_ma_if = dis_uops_2_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_ma_if = dis_uops_2_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_2_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_bp_debug_if = dis_uops_2_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_2_bp_debug_if = dis_uops_2_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_bp_xcpt_if = dis_uops_2_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_2_bp_xcpt_if = dis_uops_2_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_debug_fsrc = dis_uops_2_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_debug_fsrc = dis_uops_2_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_debug_tsrc = dis_uops_2_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_debug_tsrc = dis_uops_2_bits_debug_tsrc; // @[util.scala:104:23] wire [1:0] _GEN_0 = {stq_valid_2, stq_valid_1}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_lo_lo = {live_store_mask_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_1 = {stq_valid_5, stq_valid_4}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_lo_hi = {live_store_mask_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_lo_lo = {live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_2 = {stq_valid_8, stq_valid_7}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_hi_lo = {live_store_mask_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_3 = {stq_valid_11, stq_valid_10}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_hi_hi = {live_store_mask_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_lo_hi = {live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo}; // @[lsu.scala:354:35] wire [11:0] live_store_mask_lo = {live_store_mask_lo_hi, live_store_mask_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_4 = {stq_valid_14, stq_valid_13}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_lo_lo = {live_store_mask_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_5 = {stq_valid_17, stq_valid_16}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_lo_hi = {live_store_mask_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_hi_lo = {live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_6 = {stq_valid_20, stq_valid_19}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_hi_lo = {live_store_mask_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_7 = {stq_valid_23, stq_valid_22}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_hi_hi = {live_store_mask_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_hi_hi = {live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo}; // @[lsu.scala:354:35] wire [11:0] live_store_mask_hi = {live_store_mask_hi_hi, live_store_mask_hi_lo}; // @[lsu.scala:354:35] wire [23:0] _live_store_mask_T = {live_store_mask_hi, live_store_mask_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_8 = {dis_stq_oh_2, dis_stq_oh_1}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_lo_hi_1 = _GEN_8; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_lo_hi_1 = _GEN_8; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_lo_lo_1 = {live_store_mask_lo_lo_lo_hi_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_9 = {dis_stq_oh_5, dis_stq_oh_4}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_hi_hi_1 = _GEN_9; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_hi_hi_1 = _GEN_9; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_lo_hi_1 = {live_store_mask_lo_lo_hi_hi_1, dis_stq_oh_3}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_lo_lo_1 = {live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_10 = {dis_stq_oh_8, dis_stq_oh_7}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_lo_hi_1 = _GEN_10; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_lo_hi_1 = _GEN_10; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_hi_lo_1 = {live_store_mask_lo_hi_lo_hi_1, dis_stq_oh_6}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_11 = {dis_stq_oh_11, dis_stq_oh_10}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_hi_hi_1 = {live_store_mask_lo_hi_hi_hi_1, dis_stq_oh_9}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_lo_hi_1 = {live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1}; // @[lsu.scala:354:55] wire [11:0] live_store_mask_lo_1 = {live_store_mask_lo_hi_1, live_store_mask_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_12 = {dis_stq_oh_14, dis_stq_oh_13}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_lo_hi_1 = _GEN_12; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_lo_hi_1 = _GEN_12; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_lo_lo_1 = {live_store_mask_hi_lo_lo_hi_1, dis_stq_oh_12}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_13 = {dis_stq_oh_17, dis_stq_oh_16}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_hi_hi_1 = _GEN_13; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_hi_hi_1 = _GEN_13; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_lo_hi_1 = {live_store_mask_hi_lo_hi_hi_1, dis_stq_oh_15}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_hi_lo_1 = {live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_14 = {dis_stq_oh_20, dis_stq_oh_19}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_lo_hi_1 = _GEN_14; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_lo_hi_1 = _GEN_14; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_hi_lo_1 = {live_store_mask_hi_hi_lo_hi_1, dis_stq_oh_18}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_15 = {dis_stq_oh_23, dis_stq_oh_22}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_hi_hi_1 = {live_store_mask_hi_hi_hi_hi_1, dis_stq_oh_21}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_hi_hi_1 = {live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1}; // @[lsu.scala:354:55] wire [11:0] live_store_mask_hi_1 = {live_store_mask_hi_hi_1, live_store_mask_hi_lo_1}; // @[lsu.scala:354:55] wire [23:0] _live_store_mask_T_1 = {live_store_mask_hi_1, live_store_mask_lo_1}; // @[lsu.scala:354:55] wire [23:0] live_store_mask = _live_store_mask_T \| _live_store_mask_T_1; // @[lsu.scala:354:{35,42,55}] wire [31:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:355:{65,71}] wire [31:0] _next_live_store_mask_T_2 = {8'h0, _next_live_store_mask_T_1[23:0] & live_store_mask}; // @[lsu.scala:354:42, :355:{63,65}] wire [31:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : {8'h0, live_store_mask}; // @[lsu.scala:318:33, :354:42, :355:{33,63}] wire [31:0] _ldq_tail_oh_T = 32'h1 << ldq_tail; // @[OneHot.scala:58:35] wire [23:0] ldq_tail_oh = _ldq_tail_oh_T[23:0]; // @[OneHot.scala:58:35] wire [1:0] _GEN_16 = {ldq_valid_2, ldq_valid_1}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_lo_hi = _GEN_16; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_lo_hi_1 = _GEN_16; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_lo_lo = {ldq_valids_lo_lo_lo_hi, ldq_valid_0}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_17 = {ldq_valid_5, ldq_valid_4}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_hi_hi = _GEN_17; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_hi_hi_1 = _GEN_17; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_lo_hi = {ldq_valids_lo_lo_hi_hi, ldq_valid_3}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_lo_lo = {ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_18 = {ldq_valid_8, ldq_valid_7}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_lo_hi = _GEN_18; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_lo_hi_1 = _GEN_18; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_hi_lo = {ldq_valids_lo_hi_lo_hi, ldq_valid_6}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_19 = {ldq_valid_11, ldq_valid_10}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_hi_hi = _GEN_19; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_hi_hi_1 = _GEN_19; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_hi_hi = {ldq_valids_lo_hi_hi_hi, ldq_valid_9}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_lo_hi = {ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo}; // @[lsu.scala:360:31] wire [11:0] ldq_valids_lo = {ldq_valids_lo_hi, ldq_valids_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_20 = {ldq_valid_14, ldq_valid_13}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_lo_hi = _GEN_20; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_lo_hi_1 = _GEN_20; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_lo_lo = {ldq_valids_hi_lo_lo_hi, ldq_valid_12}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_21 = {ldq_valid_17, ldq_valid_16}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_hi_hi = _GEN_21; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_hi_hi_1 = _GEN_21; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_lo_hi = {ldq_valids_hi_lo_hi_hi, ldq_valid_15}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_hi_lo = {ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_22 = {ldq_valid_20, ldq_valid_19}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_lo_hi = _GEN_22; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_lo_hi_1 = _GEN_22; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_hi_lo = {ldq_valids_hi_hi_lo_hi, ldq_valid_18}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_23 = {ldq_valid_23, ldq_valid_22}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_hi_hi = _GEN_23; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_hi_hi_1 = _GEN_23; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_hi_hi = {ldq_valids_hi_hi_hi_hi, ldq_valid_21}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_hi_hi = {ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo}; // @[lsu.scala:360:31] wire [11:0] ldq_valids_hi = {ldq_valids_hi_hi, ldq_valids_hi_lo}; // @[lsu.scala:360:31] wire [23:0] _ldq_valids_T = {ldq_valids_hi, ldq_valids_lo}; // @[lsu.scala:360:31] wire [1:0] ldq_valids_lo_lo_lo_hi_1 = {dis_ldq_oh_2, dis_ldq_oh_1}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_lo_lo_1 = {ldq_valids_lo_lo_lo_hi_1, dis_ldq_oh_0}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_lo_hi_hi_1 = {dis_ldq_oh_5, dis_ldq_oh_4}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_lo_hi_1 = {ldq_valids_lo_lo_hi_hi_1, dis_ldq_oh_3}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_lo_lo_1 = {ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_lo_hi_lo_hi_1 = {dis_ldq_oh_8, dis_ldq_oh_7}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_hi_lo_1 = {ldq_valids_lo_hi_lo_hi_1, dis_ldq_oh_6}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_hi_hi_hi_1 = {dis_ldq_oh_11, dis_ldq_oh_10}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_hi_hi_1 = {ldq_valids_lo_hi_hi_hi_1, dis_ldq_oh_9}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_lo_hi_1 = {ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1}; // @[lsu.scala:360:51] wire [11:0] ldq_valids_lo_1 = {ldq_valids_lo_hi_1, ldq_valids_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_lo_lo_hi_1 = {dis_ldq_oh_14, dis_ldq_oh_13}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_lo_lo_1 = {ldq_valids_hi_lo_lo_hi_1, dis_ldq_oh_12}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_lo_hi_hi_1 = {dis_ldq_oh_17, dis_ldq_oh_16}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_lo_hi_1 = {ldq_valids_hi_lo_hi_hi_1, dis_ldq_oh_15}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_hi_lo_1 = {ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_hi_lo_hi_1 = {dis_ldq_oh_20, dis_ldq_oh_19}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_hi_lo_1 = {ldq_valids_hi_hi_lo_hi_1, dis_ldq_oh_18}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_hi_hi_hi_1 = {dis_ldq_oh_23, dis_ldq_oh_22}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_hi_hi_1 = {ldq_valids_hi_hi_hi_hi_1, dis_ldq_oh_21}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_hi_hi_1 = {ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1}; // @[lsu.scala:360:51] wire [11:0] ldq_valids_hi_1 = {ldq_valids_hi_hi_1, ldq_valids_hi_lo_1}; // @[lsu.scala:360:51] wire [23:0] _ldq_valids_T_1 = {ldq_valids_hi_1, ldq_valids_lo_1}; // @[lsu.scala:360:51] wire [23:0] ldq_valids = _ldq_valids_T \| _ldq_valids_T_1; // @[lsu.scala:360:{31,38,51}] wire [31:0] _stq_tail_oh_T = 32'h1 << stq_tail; // @[OneHot.scala:58:35] wire [23:0] stq_tail_oh = _stq_tail_oh_T[23:0]; // @[OneHot.scala:58:35] wire [2:0] stq_valids_lo_lo_lo = {stq_valids_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_lo_lo_hi = {stq_valids_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_lo_lo = {stq_valids_lo_lo_hi, stq_valids_lo_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_lo_hi_lo = {stq_valids_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_lo_hi_hi = {stq_valids_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_lo_hi = {stq_valids_lo_hi_hi, stq_valids_lo_hi_lo}; // @[lsu.scala:362:31] wire [11:0] stq_valids_lo = {stq_valids_lo_hi, stq_valids_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_hi_lo_lo = {stq_valids_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_hi_lo_hi = {stq_valids_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_hi_lo = {stq_valids_hi_lo_hi, stq_valids_hi_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_hi_hi_lo = {stq_valids_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_hi_hi_hi = {stq_valids_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_hi_hi = {stq_valids_hi_hi_hi, stq_valids_hi_hi_lo}; // @[lsu.scala:362:31] wire [11:0] stq_valids_hi = {stq_valids_hi_hi, stq_valids_hi_lo}; // @[lsu.scala:362:31] wire [23:0] _stq_valids_T = {stq_valids_hi, stq_valids_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_lo_lo_lo_1 = {stq_valids_lo_lo_lo_hi_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_lo_lo_hi_1 = {stq_valids_lo_lo_hi_hi_1, dis_stq_oh_3}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_lo_lo_1 = {stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_lo_hi_lo_1 = {stq_valids_lo_hi_lo_hi_1, dis_stq_oh_6}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_lo_hi_hi_1 = {stq_valids_lo_hi_hi_hi_1, dis_stq_oh_9}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_lo_hi_1 = {stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1}; // @[lsu.scala:362:51] wire [11:0] stq_valids_lo_1 = {stq_valids_lo_hi_1, stq_valids_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_hi_lo_lo_1 = {stq_valids_hi_lo_lo_hi_1, dis_stq_oh_12}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_hi_lo_hi_1 = {stq_valids_hi_lo_hi_hi_1, dis_stq_oh_15}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_hi_lo_1 = {stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_hi_hi_lo_1 = {stq_valids_hi_hi_lo_hi_1, dis_stq_oh_18}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_hi_hi_hi_1 = {stq_valids_hi_hi_hi_hi_1, dis_stq_oh_21}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_hi_hi_1 = {stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1}; // @[lsu.scala:362:51] wire [11:0] stq_valids_hi_1 = {stq_valids_hi_hi_1, stq_valids_hi_lo_1}; // @[lsu.scala:362:51] wire [23:0] _stq_valids_T_1 = {stq_valids_hi_1, stq_valids_lo_1}; // @[lsu.scala:362:51] wire [23:0] stq_valids = _stq_valids_T \| _stq_valids_T_1; // @[lsu.scala:362:{31,38,51}] wire _GEN_24 = stq_valid_0 \| stq_valid_1; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T; // @[lsu.scala:364:40] assign _stq_nonempty_T = _GEN_24; // @[lsu.scala:364:40] wire _io_hellacache_store_pending_T; // @[lsu.scala:1804:52] assign _io_hellacache_store_pending_T = _GEN_24; // @[lsu.scala:364:40, :1804:52] wire _stq_nonempty_T_1 = _stq_nonempty_T \| stq_valid_2; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 \| stq_valid_3; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 \| stq_valid_4; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 \| stq_valid_5; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 \| stq_valid_6; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 \| stq_valid_7; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_7 = _stq_nonempty_T_6 \| stq_valid_8; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_8 = _stq_nonempty_T_7 \| stq_valid_9; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_9 = _stq_nonempty_T_8 \| stq_valid_10; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_10 = _stq_nonempty_T_9 \| stq_valid_11; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_11 = _stq_nonempty_T_10 \| stq_valid_12; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_12 = _stq_nonempty_T_11 \| stq_valid_13; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_13 = _stq_nonempty_T_12 \| stq_valid_14; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_14 = _stq_nonempty_T_13 \| stq_valid_15; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_15 = _stq_nonempty_T_14 \| stq_valid_16; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_16 = _stq_nonempty_T_15 \| stq_valid_17; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_17 = _stq_nonempty_T_16 \| stq_valid_18; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_18 = _stq_nonempty_T_17 \| stq_valid_19; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_19 = _stq_nonempty_T_18 \| stq_valid_20; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_20 = _stq_nonempty_T_19 \| stq_valid_21; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_21 = _stq_nonempty_T_20 \| stq_valid_22; // @[lsu.scala:251:32, :364:40] wire stq_nonempty = _stq_nonempty_T_21 \| stq_valid_23; // @[lsu.scala:251:32, :364:40] wire [23:0] _ldq_full_T = ldq_tail_oh & ldq_valids; // @[lsu.scala:359:39, :360:38, :369:33] assign ldq_full = \|_ldq_full_T; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_0_0 = ldq_full; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T = stq_tail_oh & stq_valids; // @[lsu.scala:361:39, :362:38, :373:33] assign stq_full = \|_stq_full_T; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_0_0 = stq_full; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_0_valid_T = dis_ld_val \| dis_st_val; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap = ldq_tail == 5'h17; // @[util.scala:213:25] wire [31:0] _GEN_25 = {{ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_23}, {ldq_valid_22}, {ldq_valid_21}, {ldq_valid_20}, {ldq_valid_19}, {ldq_valid_18}, {ldq_valid_17}, {ldq_valid_16}, {ldq_valid_15}, {ldq_valid_14}, {ldq_valid_13}, {ldq_valid_12}, {ldq_valid_11}, {ldq_valid_10}, {ldq_valid_9}, {ldq_valid_8}, {ldq_valid_7}, {ldq_valid_6}, {ldq_valid_5}, {ldq_valid_4}, {ldq_valid_3}, {ldq_valid_2}, {ldq_valid_1}, {ldq_valid_0}}; // @[lsu.scala:218:36, :387:15] wire wrap_1 = stq_tail == 5'h17; // @[util.scala:213:25] wire [31:0] _GEN_26 = {{stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_23}, {stq_valid_22}, {stq_valid_21}, {stq_valid_20}, {stq_valid_19}, {stq_valid_18}, {stq_valid_17}, {stq_valid_16}, {stq_valid_15}, {stq_valid_14}, {stq_valid_13}, {stq_valid_12}, {stq_valid_11}, {stq_valid_10}, {stq_valid_9}, {stq_valid_8}, {stq_valid_7}, {stq_valid_6}, {stq_valid_5}, {stq_valid_4}, {stq_valid_3}, {stq_valid_2}, {stq_valid_1}, {stq_valid_0}}; // @[lsu.scala:251:32, :392:15] wire _T_16 = dis_uops_0_valid & dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_27 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_0_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T; // @[util.scala:126:51] assign _ldq_valid_T = _GEN_27; // @[util.scala:126:51] wire [15:0] _stq_valid_T; // @[util.scala:126:51] assign _stq_valid_T = _GEN_27; // @[util.scala:126:51] wire _ldq_valid_T_1 = \|_ldq_valid_T; // @[util.scala:126:{51,59}] wire _ldq_valid_T_2 = _ldq_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_3 = ~_ldq_valid_T_2; // @[util.scala:61:61] wire _GEN_28 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h0; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_29 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h1; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_30 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h2; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_31 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h3; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_32 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h4; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_33 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h5; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_34 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h6; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_35 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h7; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_36 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h8; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_37 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h9; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_38 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hA; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_39 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hB; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_40 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hC; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_41 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hD; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_42 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hE; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_43 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hF; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_44 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h10; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_45 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h11; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_46 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h12; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_47 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h13; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_48 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h14; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_49 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h15; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_50 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h16; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_51 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h17; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] ldq_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _ldq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign ldq_uop_out_br_mask = _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _stq_valid_T_1 = \|_stq_valid_T; // @[util.scala:126:{51,59}] wire _stq_valid_T_2 = _stq_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_3 = ~_stq_valid_T_2; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] stq_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _stq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign stq_uop_out_br_mask = _stq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [4:0] _T_20 = wrap ? 5'h0 : ldq_tail + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_20 : ldq_tail; // @[util.scala:214:10] wire [5:0] _stq_tail_plus_sum_T = {1'h0, stq_tail}; // @[util.scala:174:20, :214:28] wire [4:0] _T_27 = wrap_1 ? 5'h0 : stq_tail + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_27 : stq_tail; // @[util.scala:214:10] wire [22:0] _out_T = ldq_tail_oh[22:0]; // @[util.scala:256:25] wire _out_T_1 = ldq_tail_oh[23]; // @[util.scala:256:40] wire [23:0] out = {_out_T, _out_T_1}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_38 = io_core_dis_uops_0_bits_uses_ldq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out : ldq_tail_oh; // @[util.scala:256:18] wire [22:0] _out_T_2 = stq_tail_oh[22:0]; // @[util.scala:256:25] wire _out_T_3 = stq_tail_oh[23]; // @[util.scala:256:40] wire [23:0] out_1 = {_out_T_2, _out_T_3}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_43 = io_core_dis_uops_0_bits_uses_stq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out_1 : stq_tail_oh; // @[util.scala:256:18] wire [23:0] _ldq_full_T_1 = _T_38 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_1 = \|_ldq_full_T_1; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_1_0 = ldq_full_1; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T_1 = _T_43 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_1 = \|_stq_full_T_1; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_1_0 = stq_full_1; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_1_valid_T = dis_ld_val_1 \| dis_st_val_1; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap_2 = io_core_dis_ldq_idx_1_0 == 5'h17; // @[util.scala:213:25] wire wrap_3 = io_core_dis_stq_idx_1_0 == 5'h17; // @[util.scala:213:25] wire _T_60 = dis_uops_1_valid & dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_52 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_1_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T_4; // @[util.scala:126:51] assign _ldq_valid_T_4 = _GEN_52; // @[util.scala:126:51] wire [15:0] _stq_valid_T_4; // @[util.scala:126:51] assign _stq_valid_T_4 = _GEN_52; // @[util.scala:126:51] wire _ldq_valid_T_5 = \|_ldq_valid_T_4; // @[util.scala:126:{51,59}] wire _ldq_valid_T_6 = _ldq_valid_T_5 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_7 = ~_ldq_valid_T_6; // @[util.scala:61:61] wire _GEN_53 = dis_uops_1_bits_ldq_idx == 5'h0; // @[lsu.scala:352:23, :396:42] wire _GEN_54 = dis_uops_1_bits_ldq_idx == 5'h1; // @[lsu.scala:352:23, :396:42] wire _GEN_55 = dis_uops_1_bits_ldq_idx == 5'h2; // @[lsu.scala:352:23, :396:42] wire _GEN_56 = dis_uops_1_bits_ldq_idx == 5'h3; // @[lsu.scala:352:23, :396:42] wire _GEN_57 = dis_uops_1_bits_ldq_idx == 5'h4; // @[lsu.scala:352:23, :396:42] wire _GEN_58 = dis_uops_1_bits_ldq_idx == 5'h5; // @[lsu.scala:352:23, :396:42] wire _GEN_59 = dis_uops_1_bits_ldq_idx == 5'h6; // @[lsu.scala:352:23, :396:42] wire _GEN_60 = dis_uops_1_bits_ldq_idx == 5'h7; // @[lsu.scala:352:23, :396:42] wire _GEN_61 = dis_uops_1_bits_ldq_idx == 5'h8; // @[lsu.scala:352:23, :396:42] wire _GEN_62 = dis_uops_1_bits_ldq_idx == 5'h9; // @[lsu.scala:352:23, :396:42] wire _GEN_63 = dis_uops_1_bits_ldq_idx == 5'hA; // @[lsu.scala:352:23, :396:42] wire _GEN_64 = dis_uops_1_bits_ldq_idx == 5'hB; // @[lsu.scala:352:23, :396:42] wire _GEN_65 = dis_uops_1_bits_ldq_idx == 5'hC; // @[lsu.scala:352:23, :396:42] wire _GEN_66 = dis_uops_1_bits_ldq_idx == 5'hD; // @[lsu.scala:352:23, :396:42] wire _GEN_67 = dis_uops_1_bits_ldq_idx == 5'hE; // @[lsu.scala:352:23, :396:42] wire _GEN_68 = dis_uops_1_bits_ldq_idx == 5'hF; // @[lsu.scala:352:23, :396:42] wire _GEN_69 = dis_uops_1_bits_ldq_idx == 5'h10; // @[lsu.scala:352:23, :396:42] wire _GEN_70 = dis_uops_1_bits_ldq_idx == 5'h11; // @[lsu.scala:352:23, :396:42] wire _GEN_71 = dis_uops_1_bits_ldq_idx == 5'h12; // @[lsu.scala:352:23, :396:42] wire _GEN_72 = dis_uops_1_bits_ldq_idx == 5'h13; // @[lsu.scala:352:23, :396:42] wire _GEN_73 = dis_uops_1_bits_ldq_idx == 5'h14; // @[lsu.scala:352:23, :396:42] wire _GEN_74 = dis_uops_1_bits_ldq_idx == 5'h15; // @[lsu.scala:352:23, :396:42] wire _GEN_75 = dis_uops_1_bits_ldq_idx == 5'h16; // @[lsu.scala:352:23, :396:42] wire _GEN_76 = dis_uops_1_bits_ldq_idx == 5'h17; // @[lsu.scala:352:23, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] ldq_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _ldq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign ldq_uop_out_1_br_mask = _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _GEN_77 = _GEN_53 \| _GEN_28; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_78 = _GEN_54 \| _GEN_29; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_79 = _GEN_55 \| _GEN_30; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_80 = _GEN_56 \| _GEN_31; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_81 = _GEN_57 \| _GEN_32; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_82 = _GEN_58 \| _GEN_33; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_83 = _GEN_59 \| _GEN_34; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_84 = _GEN_60 \| _GEN_35; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_85 = _GEN_61 \| _GEN_36; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_86 = _GEN_62 \| _GEN_37; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_87 = _GEN_63 \| _GEN_38; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_88 = _GEN_64 \| _GEN_39; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_89 = _GEN_65 \| _GEN_40; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_90 = _GEN_66 \| _GEN_41; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_91 = _GEN_67 \| _GEN_42; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_92 = _GEN_68 \| _GEN_43; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_93 = _GEN_69 \| _GEN_44; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_94 = _GEN_70 \| _GEN_45; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_95 = _GEN_71 \| _GEN_46; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_96 = _GEN_72 \| _GEN_47; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_97 = _GEN_73 \| _GEN_48; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_98 = _GEN_74 \| _GEN_49; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_99 = _GEN_75 \| _GEN_50; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_100 = _GEN_76 \| _GEN_51; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _stq_valid_T_5 = \|_stq_valid_T_4; // @[util.scala:126:{51,59}] wire _stq_valid_T_6 = _stq_valid_T_5 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_7 = ~_stq_valid_T_6; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] stq_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _stq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign stq_uop_out_1_br_mask = _stq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [4:0] _T_64 = wrap_2 ? 5'h0 : io_core_dis_ldq_idx_1_0 + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_ldq_idx_2_0 = dis_ld_val_1 ? _T_64 : io_core_dis_ldq_idx_1_0; // @[util.scala:214:10] wire [4:0] _T_71 = wrap_3 ? 5'h0 : io_core_dis_stq_idx_1_0 + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_stq_idx_2_0 = dis_st_val_1 ? _T_71 : io_core_dis_stq_idx_1_0; // @[util.scala:214:10] wire [22:0] _out_T_4 = _T_38[22:0]; // @[util.scala:256:25] wire _out_T_5 = _T_38[23]; // @[util.scala:256:40] wire [23:0] out_2 = {_out_T_4, _out_T_5}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_82 = io_core_dis_uops_1_bits_uses_ldq_0 & ~io_core_dis_uops_1_bits_exception_0 ? out_2 : _T_38; // @[util.scala:256:18] wire [22:0] _out_T_6 = _T_43[22:0]; // @[util.scala:256:25] wire _out_T_7 = _T_43[23]; // @[util.scala:256:40] wire [23:0] out_3 = {_out_T_6, _out_T_7}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_87 = io_core_dis_uops_1_bits_uses_stq_0 & ~io_core_dis_uops_1_bits_exception_0 ? out_3 : _T_43; // @[util.scala:256:18] wire [23:0] _ldq_full_T_2 = _T_82 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_2 = \|_ldq_full_T_2; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_2_0 = ldq_full_2; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T_2 = _T_87 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_2 = \|_stq_full_T_2; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_2_0 = stq_full_2; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_2 = _dis_ld_val_T_4 & _dis_ld_val_T_5; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_2 = _dis_st_val_T_4 & _dis_st_val_T_5; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_2_valid_T = dis_ld_val_2 \| dis_st_val_2; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap_4 = io_core_dis_ldq_idx_2_0 == 5'h17; // @[util.scala:213:25] wire wrap_5 = io_core_dis_stq_idx_2_0 == 5'h17; // @[util.scala:213:25] wire _T_104 = dis_uops_2_valid & dis_uops_2_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_101 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_2_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T_8; // @[util.scala:126:51] assign _ldq_valid_T_8 = _GEN_101; // @[util.scala:126:51] wire [15:0] _stq_valid_T_8; // @[util.scala:126:51] assign _stq_valid_T_8 = _GEN_101; // @[util.scala:126:51] wire _ldq_valid_T_9 = \|_ldq_valid_T_8; // @[util.scala:126:{51,59}] wire _ldq_valid_T_10 = _ldq_valid_T_9 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_11 = ~_ldq_valid_T_10; // @[util.scala:61:61] wire _GEN_102 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h0; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_103 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h1; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_104 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h2; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_105 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h3; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_106 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h4; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_107 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h5; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_108 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h6; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_109 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h7; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_110 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h8; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_111 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h9; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_112 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hA; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_113 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hB; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_114 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hC; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_115 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hD; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_116 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hE; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_117 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hF; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_118 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h10; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_119 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h11; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_120 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h12; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_121 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h13; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_122 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h14; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_123 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h15; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_124 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h16; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_125 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h17; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] ldq_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_5 = dis_uops_2_bits_br_mask & _ldq_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign ldq_uop_out_2_br_mask = _ldq_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire _stq_valid_T_9 = \|_stq_valid_T_8; // @[util.scala:126:{51,59}] wire _stq_valid_T_10 = _stq_valid_T_9 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_11 = ~_stq_valid_T_10; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] stq_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_5 = dis_uops_2_bits_br_mask & _stq_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign stq_uop_out_2_br_mask = _stq_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire [22:0] _out_T_8 = _T_82[22:0]; // @[util.scala:256:25] wire _out_T_9 = _T_82[23]; // @[util.scala:256:40] wire [23:0] out_4 = {_out_T_8, _out_T_9}; // @[util.scala:256:{18,25,40}] wire [22:0] _out_T_10 = _T_87[22:0]; // @[util.scala:256:25] wire _out_T_11 = _T_87[23]; // @[util.scala:256:40] wire [23:0] out_5 = {_out_T_10, _out_T_11}; // @[util.scala:256:{18,25,40}] wire stq_enq_e_e_valid = _GEN_26[stq_execute_head]; // @[lsu.scala:262:17, :283:29, :392:15, :438:42] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:364:40, :446:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:211:7, :446:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:211:7, :446:42] wire mem_xcpt_valid; // @[lsu.scala:457:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:458:29] wire mem_xcpt_uop_iq_type_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_4; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_5; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_6; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_7; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_8; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_9; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:459:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29] wire [15:0] mem_xcpt_uop_br_mask; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_type; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_eret; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rocc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_mov; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:459:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:459:29] wire mem_xcpt_uop_taken; // @[lsu.scala:459:29] wire mem_xcpt_uop_imm_rename; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_imm_sel; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_pimm; // @[lsu.scala:459:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_op1_sel; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_op2_sel; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:459:29] wire mem_xcpt_uop_exception; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:459:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:459:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_csr_cmd; // @[lsu.scala:459:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:459:29] wire mem_xcpt_uop_fcn_dw; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_fcn_op; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_fp_rm; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_typ; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_vaddr; // @[lsu.scala:460:29] wire will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_exec_0; // @[lsu.scala:469:39] wire will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_0; // @[lsu.scala:470:41] wire will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_agen_0; // @[lsu.scala:471:41] wire will_fire_sfence_0_will_fire; // @[lsu.scala:657:65] wire will_fire_sfence_0; // @[lsu.scala:472:41] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_incoming_0; // @[lsu.scala:473:41] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:473:41, :756:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_wakeup_0; // @[lsu.scala:474:41] wire will_fire_release_0_will_fire; // @[lsu.scala:657:65] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:211:7, :475:41] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_retry_0; // @[lsu.scala:476:41] wire will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_retry_0; // @[lsu.scala:477:41] wire will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_fast_0; // @[lsu.scala:478:41] wire will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_slow_0; // @[lsu.scala:479:41] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_wakeup_0; // @[lsu.scala:480:41] wire block_load_mask_0; // @[lsu.scala:488:36] wire block_load_mask_1; // @[lsu.scala:488:36] wire block_load_mask_2; // @[lsu.scala:488:36] wire block_load_mask_3; // @[lsu.scala:488:36] wire block_load_mask_4; // @[lsu.scala:488:36] wire block_load_mask_5; // @[lsu.scala:488:36] wire block_load_mask_6; // @[lsu.scala:488:36] wire block_load_mask_7; // @[lsu.scala:488:36] wire block_load_mask_8; // @[lsu.scala:488:36] wire block_load_mask_9; // @[lsu.scala:488:36] wire block_load_mask_10; // @[lsu.scala:488:36] wire block_load_mask_11; // @[lsu.scala:488:36] wire block_load_mask_12; // @[lsu.scala:488:36] wire block_load_mask_13; // @[lsu.scala:488:36] wire block_load_mask_14; // @[lsu.scala:488:36] wire block_load_mask_15; // @[lsu.scala:488:36] wire block_load_mask_16; // @[lsu.scala:488:36] wire block_load_mask_17; // @[lsu.scala:488:36] wire block_load_mask_18; // @[lsu.scala:488:36] wire block_load_mask_19; // @[lsu.scala:488:36] wire block_load_mask_20; // @[lsu.scala:488:36] wire block_load_mask_21; // @[lsu.scala:488:36] wire block_load_mask_22; // @[lsu.scala:488:36] wire block_load_mask_23; // @[lsu.scala:488:36] reg p1_block_load_mask_0; // @[lsu.scala:489:35] reg p1_block_load_mask_1; // @[lsu.scala:489:35] reg p1_block_load_mask_2; // @[lsu.scala:489:35] reg p1_block_load_mask_3; // @[lsu.scala:489:35] reg p1_block_load_mask_4; // @[lsu.scala:489:35] reg p1_block_load_mask_5; // @[lsu.scala:489:35] reg p1_block_load_mask_6; // @[lsu.scala:489:35] reg p1_block_load_mask_7; // @[lsu.scala:489:35] reg p1_block_load_mask_8; // @[lsu.scala:489:35] reg p1_block_load_mask_9; // @[lsu.scala:489:35] reg p1_block_load_mask_10; // @[lsu.scala:489:35] reg p1_block_load_mask_11; // @[lsu.scala:489:35] reg p1_block_load_mask_12; // @[lsu.scala:489:35] reg p1_block_load_mask_13; // @[lsu.scala:489:35] reg p1_block_load_mask_14; // @[lsu.scala:489:35] reg p1_block_load_mask_15; // @[lsu.scala:489:35] reg p1_block_load_mask_16; // @[lsu.scala:489:35] reg p1_block_load_mask_17; // @[lsu.scala:489:35] reg p1_block_load_mask_18; // @[lsu.scala:489:35] reg p1_block_load_mask_19; // @[lsu.scala:489:35] reg p1_block_load_mask_20; // @[lsu.scala:489:35] reg p1_block_load_mask_21; // @[lsu.scala:489:35] reg p1_block_load_mask_22; // @[lsu.scala:489:35] reg p1_block_load_mask_23; // @[lsu.scala:489:35] reg p2_block_load_mask_0; // @[lsu.scala:490:35] reg p2_block_load_mask_1; // @[lsu.scala:490:35] reg p2_block_load_mask_2; // @[lsu.scala:490:35] reg p2_block_load_mask_3; // @[lsu.scala:490:35] reg p2_block_load_mask_4; // @[lsu.scala:490:35] reg p2_block_load_mask_5; // @[lsu.scala:490:35] reg p2_block_load_mask_6; // @[lsu.scala:490:35] reg p2_block_load_mask_7; // @[lsu.scala:490:35] reg p2_block_load_mask_8; // @[lsu.scala:490:35] reg p2_block_load_mask_9; // @[lsu.scala:490:35] reg p2_block_load_mask_10; // @[lsu.scala:490:35] reg p2_block_load_mask_11; // @[lsu.scala:490:35] reg p2_block_load_mask_12; // @[lsu.scala:490:35] reg p2_block_load_mask_13; // @[lsu.scala:490:35] reg p2_block_load_mask_14; // @[lsu.scala:490:35] reg p2_block_load_mask_15; // @[lsu.scala:490:35] reg p2_block_load_mask_16; // @[lsu.scala:490:35] reg p2_block_load_mask_17; // @[lsu.scala:490:35] reg p2_block_load_mask_18; // @[lsu.scala:490:35] reg p2_block_load_mask_19; // @[lsu.scala:490:35] reg p2_block_load_mask_20; // @[lsu.scala:490:35] reg p2_block_load_mask_21; // @[lsu.scala:490:35] reg p2_block_load_mask_22; // @[lsu.scala:490:35] reg p2_block_load_mask_23; // @[lsu.scala:490:35] wire [6:0] _stq_tail_plus_sum_T_2 = {1'h0, _stq_tail_plus_sum_T} + 7'h6; // @[util.scala:174:{20,38}] wire [5:0] stq_tail_plus_sum = _stq_tail_plus_sum_T_2[5:0]; // @[util.scala:174:38] wire _stq_tail_plus_T = stq_tail_plus_sum > 6'h17; // @[util.scala:174:38, :175:15] wire [6:0] _stq_tail_plus_T_1 = {1'h0, stq_tail_plus_sum} - 7'h18; // @[util.scala:174:38, :176:15] wire [5:0] _stq_tail_plus_T_2 = _stq_tail_plus_T_1[5:0]; // @[util.scala:176:15] wire [5:0] stq_tail_plus = _stq_tail_plus_T ? _stq_tail_plus_T_2 : stq_tail_plus_sum; // @[util.scala:174:38, :175:{10,15}, :176:15] wire [5:0] _GEN_126 = {1'h0, stq_head}; // @[util.scala:364:52] wire _stq_almost_full_T = _GEN_126 < stq_tail_plus; // @[util.scala:175:10, :364:52] wire _stq_almost_full_T_1 = stq_head < stq_tail; // @[util.scala:364:64] wire _stq_almost_full_T_2 = _stq_almost_full_T ^ _stq_almost_full_T_1; // @[util.scala:364:{52,58,64}] wire _stq_almost_full_T_3 = stq_tail_plus < _stq_tail_plus_sum_T; // @[util.scala:174:20, :175:10, :364:78] wire _stq_almost_full_T_4 = _stq_almost_full_T_2 ^ _stq_almost_full_T_3; // @[util.scala:364:{58,72,78}] reg stq_almost_full; // @[lsu.scala:494:32] wire store_needs_order; // @[lsu.scala:498:35] wire _ldq_incoming_e_WIRE_valid = ldq_incoming_e_e_valid; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_inst = ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_debug_inst = ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rvc = ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_uop_debug_pc = ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_0 = ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_1 = ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_2 = ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_3 = ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_0 = ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_1 = ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_2 = ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_3 = ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_4 = ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_5 = ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_6 = ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_7 = ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_8 = ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_9 = ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued = ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_dis_col_sel = ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :501:48] wire [15:0] _ldq_incoming_e_WIRE_bits_uop_br_mask = ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_tag = ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_type = ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfb = ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fence = ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fencei = ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfence = ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_amo = ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_eret = ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rocc = ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_mov = ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ftq_idx = ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_edge_inst = ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_pc_lob = ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_taken = ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_imm_rename = ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_imm_sel = ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_pimm = ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :501:48] wire [19:0] _ldq_incoming_e_WIRE_bits_uop_imm_packed = ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_op1_sel = ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_op2_sel = ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div = ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_rob_idx = ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ldq_idx = ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_stq_idx = ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_rxq_idx = ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_pdst = ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs1 = ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs2 = ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs3 = ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ppred = ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs1_busy = ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs2_busy = ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs3_busy = ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ppred_busy = ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_stale_pdst = ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_exception = ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_uop_exc_cause = ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_mem_cmd = ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_mem_size = ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_mem_signed = ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_ldq = ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_stq = ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_unique = ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_flush_on_commit = ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_csr_cmd = ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_ldst = ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs1 = ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs2 = ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs3 = ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dst_rtype = ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype = ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype = ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_frs3_en = ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fcn_dw = ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_fcn_op = ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_val = ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_fp_rm = ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_typ = ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if = ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if = ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if = ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_debug_if = ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if = ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_fsrc = ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_tsrc = ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_valid = ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_addr_bits = ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_virtual = ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_uncacheable = ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_executed = ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_succeeded = ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_order_fail = ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_observed = ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17, :501:48] wire [23:0] _ldq_incoming_e_WIRE_bits_st_dep_mask = ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :501:48] wire [7:0] _ldq_incoming_e_WIRE_bits_ld_byte_mask = ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_forward_std_val = ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_forward_stq_idx = ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_debug_wb_data = ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :501:48] assign ldq_incoming_e_e_valid = _GEN_25[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :234:32, :321:49, :387:15] wire [31:0][31:0] _GEN_127 = {{ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_23_inst}, {ldq_uop_22_inst}, {ldq_uop_21_inst}, {ldq_uop_20_inst}, {ldq_uop_19_inst}, {ldq_uop_18_inst}, {ldq_uop_17_inst}, {ldq_uop_16_inst}, {ldq_uop_15_inst}, {ldq_uop_14_inst}, {ldq_uop_13_inst}, {ldq_uop_12_inst}, {ldq_uop_11_inst}, {ldq_uop_10_inst}, {ldq_uop_9_inst}, {ldq_uop_8_inst}, {ldq_uop_7_inst}, {ldq_uop_6_inst}, {ldq_uop_5_inst}, {ldq_uop_4_inst}, {ldq_uop_3_inst}, {ldq_uop_2_inst}, {ldq_uop_1_inst}, {ldq_uop_0_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_inst = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][31:0] _GEN_128 = {{ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_23_debug_inst}, {ldq_uop_22_debug_inst}, {ldq_uop_21_debug_inst}, {ldq_uop_20_debug_inst}, {ldq_uop_19_debug_inst}, {ldq_uop_18_debug_inst}, {ldq_uop_17_debug_inst}, {ldq_uop_16_debug_inst}, {ldq_uop_15_debug_inst}, {ldq_uop_14_debug_inst}, {ldq_uop_13_debug_inst}, {ldq_uop_12_debug_inst}, {ldq_uop_11_debug_inst}, {ldq_uop_10_debug_inst}, {ldq_uop_9_debug_inst}, {ldq_uop_8_debug_inst}, {ldq_uop_7_debug_inst}, {ldq_uop_6_debug_inst}, {ldq_uop_5_debug_inst}, {ldq_uop_4_debug_inst}, {ldq_uop_3_debug_inst}, {ldq_uop_2_debug_inst}, {ldq_uop_1_debug_inst}, {ldq_uop_0_debug_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_inst = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_129 = {{ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_23_is_rvc}, {ldq_uop_22_is_rvc}, {ldq_uop_21_is_rvc}, {ldq_uop_20_is_rvc}, {ldq_uop_19_is_rvc}, {ldq_uop_18_is_rvc}, {ldq_uop_17_is_rvc}, {ldq_uop_16_is_rvc}, {ldq_uop_15_is_rvc}, {ldq_uop_14_is_rvc}, {ldq_uop_13_is_rvc}, {ldq_uop_12_is_rvc}, {ldq_uop_11_is_rvc}, {ldq_uop_10_is_rvc}, {ldq_uop_9_is_rvc}, {ldq_uop_8_is_rvc}, {ldq_uop_7_is_rvc}, {ldq_uop_6_is_rvc}, {ldq_uop_5_is_rvc}, {ldq_uop_4_is_rvc}, {ldq_uop_3_is_rvc}, {ldq_uop_2_is_rvc}, {ldq_uop_1_is_rvc}, {ldq_uop_0_is_rvc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rvc = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][39:0] _GEN_130 = {{ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_23_debug_pc}, {ldq_uop_22_debug_pc}, {ldq_uop_21_debug_pc}, {ldq_uop_20_debug_pc}, {ldq_uop_19_debug_pc}, {ldq_uop_18_debug_pc}, {ldq_uop_17_debug_pc}, {ldq_uop_16_debug_pc}, {ldq_uop_15_debug_pc}, {ldq_uop_14_debug_pc}, {ldq_uop_13_debug_pc}, {ldq_uop_12_debug_pc}, {ldq_uop_11_debug_pc}, {ldq_uop_10_debug_pc}, {ldq_uop_9_debug_pc}, {ldq_uop_8_debug_pc}, {ldq_uop_7_debug_pc}, {ldq_uop_6_debug_pc}, {ldq_uop_5_debug_pc}, {ldq_uop_4_debug_pc}, {ldq_uop_3_debug_pc}, {ldq_uop_2_debug_pc}, {ldq_uop_1_debug_pc}, {ldq_uop_0_debug_pc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_pc = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_131 = {{ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_23_iq_type_0}, {ldq_uop_22_iq_type_0}, {ldq_uop_21_iq_type_0}, {ldq_uop_20_iq_type_0}, {ldq_uop_19_iq_type_0}, {ldq_uop_18_iq_type_0}, {ldq_uop_17_iq_type_0}, {ldq_uop_16_iq_type_0}, {ldq_uop_15_iq_type_0}, {ldq_uop_14_iq_type_0}, {ldq_uop_13_iq_type_0}, {ldq_uop_12_iq_type_0}, {ldq_uop_11_iq_type_0}, {ldq_uop_10_iq_type_0}, {ldq_uop_9_iq_type_0}, {ldq_uop_8_iq_type_0}, {ldq_uop_7_iq_type_0}, {ldq_uop_6_iq_type_0}, {ldq_uop_5_iq_type_0}, {ldq_uop_4_iq_type_0}, {ldq_uop_3_iq_type_0}, {ldq_uop_2_iq_type_0}, {ldq_uop_1_iq_type_0}, {ldq_uop_0_iq_type_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_0 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_132 = {{ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_23_iq_type_1}, {ldq_uop_22_iq_type_1}, {ldq_uop_21_iq_type_1}, {ldq_uop_20_iq_type_1}, {ldq_uop_19_iq_type_1}, {ldq_uop_18_iq_type_1}, {ldq_uop_17_iq_type_1}, {ldq_uop_16_iq_type_1}, {ldq_uop_15_iq_type_1}, {ldq_uop_14_iq_type_1}, {ldq_uop_13_iq_type_1}, {ldq_uop_12_iq_type_1}, {ldq_uop_11_iq_type_1}, {ldq_uop_10_iq_type_1}, {ldq_uop_9_iq_type_1}, {ldq_uop_8_iq_type_1}, {ldq_uop_7_iq_type_1}, {ldq_uop_6_iq_type_1}, {ldq_uop_5_iq_type_1}, {ldq_uop_4_iq_type_1}, {ldq_uop_3_iq_type_1}, {ldq_uop_2_iq_type_1}, {ldq_uop_1_iq_type_1}, {ldq_uop_0_iq_type_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_1 = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_133 = {{ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_23_iq_type_2}, {ldq_uop_22_iq_type_2}, {ldq_uop_21_iq_type_2}, {ldq_uop_20_iq_type_2}, {ldq_uop_19_iq_type_2}, {ldq_uop_18_iq_type_2}, {ldq_uop_17_iq_type_2}, {ldq_uop_16_iq_type_2}, {ldq_uop_15_iq_type_2}, {ldq_uop_14_iq_type_2}, {ldq_uop_13_iq_type_2}, {ldq_uop_12_iq_type_2}, {ldq_uop_11_iq_type_2}, {ldq_uop_10_iq_type_2}, {ldq_uop_9_iq_type_2}, {ldq_uop_8_iq_type_2}, {ldq_uop_7_iq_type_2}, {ldq_uop_6_iq_type_2}, {ldq_uop_5_iq_type_2}, {ldq_uop_4_iq_type_2}, {ldq_uop_3_iq_type_2}, {ldq_uop_2_iq_type_2}, {ldq_uop_1_iq_type_2}, {ldq_uop_0_iq_type_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_2 = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_134 = {{ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_23_iq_type_3}, {ldq_uop_22_iq_type_3}, {ldq_uop_21_iq_type_3}, {ldq_uop_20_iq_type_3}, {ldq_uop_19_iq_type_3}, {ldq_uop_18_iq_type_3}, {ldq_uop_17_iq_type_3}, {ldq_uop_16_iq_type_3}, {ldq_uop_15_iq_type_3}, {ldq_uop_14_iq_type_3}, {ldq_uop_13_iq_type_3}, {ldq_uop_12_iq_type_3}, {ldq_uop_11_iq_type_3}, {ldq_uop_10_iq_type_3}, {ldq_uop_9_iq_type_3}, {ldq_uop_8_iq_type_3}, {ldq_uop_7_iq_type_3}, {ldq_uop_6_iq_type_3}, {ldq_uop_5_iq_type_3}, {ldq_uop_4_iq_type_3}, {ldq_uop_3_iq_type_3}, {ldq_uop_2_iq_type_3}, {ldq_uop_1_iq_type_3}, {ldq_uop_0_iq_type_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_3 = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_135 = {{ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_23_fu_code_0}, {ldq_uop_22_fu_code_0}, {ldq_uop_21_fu_code_0}, {ldq_uop_20_fu_code_0}, {ldq_uop_19_fu_code_0}, {ldq_uop_18_fu_code_0}, {ldq_uop_17_fu_code_0}, {ldq_uop_16_fu_code_0}, {ldq_uop_15_fu_code_0}, {ldq_uop_14_fu_code_0}, {ldq_uop_13_fu_code_0}, {ldq_uop_12_fu_code_0}, {ldq_uop_11_fu_code_0}, {ldq_uop_10_fu_code_0}, {ldq_uop_9_fu_code_0}, {ldq_uop_8_fu_code_0}, {ldq_uop_7_fu_code_0}, {ldq_uop_6_fu_code_0}, {ldq_uop_5_fu_code_0}, {ldq_uop_4_fu_code_0}, {ldq_uop_3_fu_code_0}, {ldq_uop_2_fu_code_0}, {ldq_uop_1_fu_code_0}, {ldq_uop_0_fu_code_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_0 = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_136 = {{ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_23_fu_code_1}, {ldq_uop_22_fu_code_1}, {ldq_uop_21_fu_code_1}, {ldq_uop_20_fu_code_1}, {ldq_uop_19_fu_code_1}, {ldq_uop_18_fu_code_1}, {ldq_uop_17_fu_code_1}, {ldq_uop_16_fu_code_1}, {ldq_uop_15_fu_code_1}, {ldq_uop_14_fu_code_1}, {ldq_uop_13_fu_code_1}, {ldq_uop_12_fu_code_1}, {ldq_uop_11_fu_code_1}, {ldq_uop_10_fu_code_1}, {ldq_uop_9_fu_code_1}, {ldq_uop_8_fu_code_1}, {ldq_uop_7_fu_code_1}, {ldq_uop_6_fu_code_1}, {ldq_uop_5_fu_code_1}, {ldq_uop_4_fu_code_1}, {ldq_uop_3_fu_code_1}, {ldq_uop_2_fu_code_1}, {ldq_uop_1_fu_code_1}, {ldq_uop_0_fu_code_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_1 = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_137 = {{ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_23_fu_code_2}, {ldq_uop_22_fu_code_2}, {ldq_uop_21_fu_code_2}, {ldq_uop_20_fu_code_2}, {ldq_uop_19_fu_code_2}, {ldq_uop_18_fu_code_2}, {ldq_uop_17_fu_code_2}, {ldq_uop_16_fu_code_2}, {ldq_uop_15_fu_code_2}, {ldq_uop_14_fu_code_2}, {ldq_uop_13_fu_code_2}, {ldq_uop_12_fu_code_2}, {ldq_uop_11_fu_code_2}, {ldq_uop_10_fu_code_2}, {ldq_uop_9_fu_code_2}, {ldq_uop_8_fu_code_2}, {ldq_uop_7_fu_code_2}, {ldq_uop_6_fu_code_2}, {ldq_uop_5_fu_code_2}, {ldq_uop_4_fu_code_2}, {ldq_uop_3_fu_code_2}, {ldq_uop_2_fu_code_2}, {ldq_uop_1_fu_code_2}, {ldq_uop_0_fu_code_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_2 = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_138 = {{ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_23_fu_code_3}, {ldq_uop_22_fu_code_3}, {ldq_uop_21_fu_code_3}, {ldq_uop_20_fu_code_3}, {ldq_uop_19_fu_code_3}, {ldq_uop_18_fu_code_3}, {ldq_uop_17_fu_code_3}, {ldq_uop_16_fu_code_3}, {ldq_uop_15_fu_code_3}, {ldq_uop_14_fu_code_3}, {ldq_uop_13_fu_code_3}, {ldq_uop_12_fu_code_3}, {ldq_uop_11_fu_code_3}, {ldq_uop_10_fu_code_3}, {ldq_uop_9_fu_code_3}, {ldq_uop_8_fu_code_3}, {ldq_uop_7_fu_code_3}, {ldq_uop_6_fu_code_3}, {ldq_uop_5_fu_code_3}, {ldq_uop_4_fu_code_3}, {ldq_uop_3_fu_code_3}, {ldq_uop_2_fu_code_3}, {ldq_uop_1_fu_code_3}, {ldq_uop_0_fu_code_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_3 = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_139 = {{ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_23_fu_code_4}, {ldq_uop_22_fu_code_4}, {ldq_uop_21_fu_code_4}, {ldq_uop_20_fu_code_4}, {ldq_uop_19_fu_code_4}, {ldq_uop_18_fu_code_4}, {ldq_uop_17_fu_code_4}, {ldq_uop_16_fu_code_4}, {ldq_uop_15_fu_code_4}, {ldq_uop_14_fu_code_4}, {ldq_uop_13_fu_code_4}, {ldq_uop_12_fu_code_4}, {ldq_uop_11_fu_code_4}, {ldq_uop_10_fu_code_4}, {ldq_uop_9_fu_code_4}, {ldq_uop_8_fu_code_4}, {ldq_uop_7_fu_code_4}, {ldq_uop_6_fu_code_4}, {ldq_uop_5_fu_code_4}, {ldq_uop_4_fu_code_4}, {ldq_uop_3_fu_code_4}, {ldq_uop_2_fu_code_4}, {ldq_uop_1_fu_code_4}, {ldq_uop_0_fu_code_4}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_4 = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_140 = {{ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_23_fu_code_5}, {ldq_uop_22_fu_code_5}, {ldq_uop_21_fu_code_5}, {ldq_uop_20_fu_code_5}, {ldq_uop_19_fu_code_5}, {ldq_uop_18_fu_code_5}, {ldq_uop_17_fu_code_5}, {ldq_uop_16_fu_code_5}, {ldq_uop_15_fu_code_5}, {ldq_uop_14_fu_code_5}, {ldq_uop_13_fu_code_5}, {ldq_uop_12_fu_code_5}, {ldq_uop_11_fu_code_5}, {ldq_uop_10_fu_code_5}, {ldq_uop_9_fu_code_5}, {ldq_uop_8_fu_code_5}, {ldq_uop_7_fu_code_5}, {ldq_uop_6_fu_code_5}, {ldq_uop_5_fu_code_5}, {ldq_uop_4_fu_code_5}, {ldq_uop_3_fu_code_5}, {ldq_uop_2_fu_code_5}, {ldq_uop_1_fu_code_5}, {ldq_uop_0_fu_code_5}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_5 = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_141 = {{ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_23_fu_code_6}, {ldq_uop_22_fu_code_6}, {ldq_uop_21_fu_code_6}, {ldq_uop_20_fu_code_6}, {ldq_uop_19_fu_code_6}, {ldq_uop_18_fu_code_6}, {ldq_uop_17_fu_code_6}, {ldq_uop_16_fu_code_6}, {ldq_uop_15_fu_code_6}, {ldq_uop_14_fu_code_6}, {ldq_uop_13_fu_code_6}, {ldq_uop_12_fu_code_6}, {ldq_uop_11_fu_code_6}, {ldq_uop_10_fu_code_6}, {ldq_uop_9_fu_code_6}, {ldq_uop_8_fu_code_6}, {ldq_uop_7_fu_code_6}, {ldq_uop_6_fu_code_6}, {ldq_uop_5_fu_code_6}, {ldq_uop_4_fu_code_6}, {ldq_uop_3_fu_code_6}, {ldq_uop_2_fu_code_6}, {ldq_uop_1_fu_code_6}, {ldq_uop_0_fu_code_6}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_6 = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_142 = {{ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_23_fu_code_7}, {ldq_uop_22_fu_code_7}, {ldq_uop_21_fu_code_7}, {ldq_uop_20_fu_code_7}, {ldq_uop_19_fu_code_7}, {ldq_uop_18_fu_code_7}, {ldq_uop_17_fu_code_7}, {ldq_uop_16_fu_code_7}, {ldq_uop_15_fu_code_7}, {ldq_uop_14_fu_code_7}, {ldq_uop_13_fu_code_7}, {ldq_uop_12_fu_code_7}, {ldq_uop_11_fu_code_7}, {ldq_uop_10_fu_code_7}, {ldq_uop_9_fu_code_7}, {ldq_uop_8_fu_code_7}, {ldq_uop_7_fu_code_7}, {ldq_uop_6_fu_code_7}, {ldq_uop_5_fu_code_7}, {ldq_uop_4_fu_code_7}, {ldq_uop_3_fu_code_7}, {ldq_uop_2_fu_code_7}, {ldq_uop_1_fu_code_7}, {ldq_uop_0_fu_code_7}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_7 = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_143 = {{ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_23_fu_code_8}, {ldq_uop_22_fu_code_8}, {ldq_uop_21_fu_code_8}, {ldq_uop_20_fu_code_8}, {ldq_uop_19_fu_code_8}, {ldq_uop_18_fu_code_8}, {ldq_uop_17_fu_code_8}, {ldq_uop_16_fu_code_8}, {ldq_uop_15_fu_code_8}, {ldq_uop_14_fu_code_8}, {ldq_uop_13_fu_code_8}, {ldq_uop_12_fu_code_8}, {ldq_uop_11_fu_code_8}, {ldq_uop_10_fu_code_8}, {ldq_uop_9_fu_code_8}, {ldq_uop_8_fu_code_8}, {ldq_uop_7_fu_code_8}, {ldq_uop_6_fu_code_8}, {ldq_uop_5_fu_code_8}, {ldq_uop_4_fu_code_8}, {ldq_uop_3_fu_code_8}, {ldq_uop_2_fu_code_8}, {ldq_uop_1_fu_code_8}, {ldq_uop_0_fu_code_8}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_8 = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_144 = {{ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_23_fu_code_9}, {ldq_uop_22_fu_code_9}, {ldq_uop_21_fu_code_9}, {ldq_uop_20_fu_code_9}, {ldq_uop_19_fu_code_9}, {ldq_uop_18_fu_code_9}, {ldq_uop_17_fu_code_9}, {ldq_uop_16_fu_code_9}, {ldq_uop_15_fu_code_9}, {ldq_uop_14_fu_code_9}, {ldq_uop_13_fu_code_9}, {ldq_uop_12_fu_code_9}, {ldq_uop_11_fu_code_9}, {ldq_uop_10_fu_code_9}, {ldq_uop_9_fu_code_9}, {ldq_uop_8_fu_code_9}, {ldq_uop_7_fu_code_9}, {ldq_uop_6_fu_code_9}, {ldq_uop_5_fu_code_9}, {ldq_uop_4_fu_code_9}, {ldq_uop_3_fu_code_9}, {ldq_uop_2_fu_code_9}, {ldq_uop_1_fu_code_9}, {ldq_uop_0_fu_code_9}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_9 = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_145 = {{ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_23_iw_issued}, {ldq_uop_22_iw_issued}, {ldq_uop_21_iw_issued}, {ldq_uop_20_iw_issued}, {ldq_uop_19_iw_issued}, {ldq_uop_18_iw_issued}, {ldq_uop_17_iw_issued}, {ldq_uop_16_iw_issued}, {ldq_uop_15_iw_issued}, {ldq_uop_14_iw_issued}, {ldq_uop_13_iw_issued}, {ldq_uop_12_iw_issued}, {ldq_uop_11_iw_issued}, {ldq_uop_10_iw_issued}, {ldq_uop_9_iw_issued}, {ldq_uop_8_iw_issued}, {ldq_uop_7_iw_issued}, {ldq_uop_6_iw_issued}, {ldq_uop_5_iw_issued}, {ldq_uop_4_iw_issued}, {ldq_uop_3_iw_issued}, {ldq_uop_2_iw_issued}, {ldq_uop_1_iw_issued}, {ldq_uop_0_iw_issued}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_146 = {{ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_23_iw_issued_partial_agen}, {ldq_uop_22_iw_issued_partial_agen}, {ldq_uop_21_iw_issued_partial_agen}, {ldq_uop_20_iw_issued_partial_agen}, {ldq_uop_19_iw_issued_partial_agen}, {ldq_uop_18_iw_issued_partial_agen}, {ldq_uop_17_iw_issued_partial_agen}, {ldq_uop_16_iw_issued_partial_agen}, {ldq_uop_15_iw_issued_partial_agen}, {ldq_uop_14_iw_issued_partial_agen}, {ldq_uop_13_iw_issued_partial_agen}, {ldq_uop_12_iw_issued_partial_agen}, {ldq_uop_11_iw_issued_partial_agen}, {ldq_uop_10_iw_issued_partial_agen}, {ldq_uop_9_iw_issued_partial_agen}, {ldq_uop_8_iw_issued_partial_agen}, {ldq_uop_7_iw_issued_partial_agen}, {ldq_uop_6_iw_issued_partial_agen}, {ldq_uop_5_iw_issued_partial_agen}, {ldq_uop_4_iw_issued_partial_agen}, {ldq_uop_3_iw_issued_partial_agen}, {ldq_uop_2_iw_issued_partial_agen}, {ldq_uop_1_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_147 = {{ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_23_iw_issued_partial_dgen}, {ldq_uop_22_iw_issued_partial_dgen}, {ldq_uop_21_iw_issued_partial_dgen}, {ldq_uop_20_iw_issued_partial_dgen}, {ldq_uop_19_iw_issued_partial_dgen}, {ldq_uop_18_iw_issued_partial_dgen}, {ldq_uop_17_iw_issued_partial_dgen}, {ldq_uop_16_iw_issued_partial_dgen}, {ldq_uop_15_iw_issued_partial_dgen}, {ldq_uop_14_iw_issued_partial_dgen}, {ldq_uop_13_iw_issued_partial_dgen}, {ldq_uop_12_iw_issued_partial_dgen}, {ldq_uop_11_iw_issued_partial_dgen}, {ldq_uop_10_iw_issued_partial_dgen}, {ldq_uop_9_iw_issued_partial_dgen}, {ldq_uop_8_iw_issued_partial_dgen}, {ldq_uop_7_iw_issued_partial_dgen}, {ldq_uop_6_iw_issued_partial_dgen}, {ldq_uop_5_iw_issued_partial_dgen}, {ldq_uop_4_iw_issued_partial_dgen}, {ldq_uop_3_iw_issued_partial_dgen}, {ldq_uop_2_iw_issued_partial_dgen}, {ldq_uop_1_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_148 = {{ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_23_iw_p1_speculative_child}, {ldq_uop_22_iw_p1_speculative_child}, {ldq_uop_21_iw_p1_speculative_child}, {ldq_uop_20_iw_p1_speculative_child}, {ldq_uop_19_iw_p1_speculative_child}, {ldq_uop_18_iw_p1_speculative_child}, {ldq_uop_17_iw_p1_speculative_child}, {ldq_uop_16_iw_p1_speculative_child}, {ldq_uop_15_iw_p1_speculative_child}, {ldq_uop_14_iw_p1_speculative_child}, {ldq_uop_13_iw_p1_speculative_child}, {ldq_uop_12_iw_p1_speculative_child}, {ldq_uop_11_iw_p1_speculative_child}, {ldq_uop_10_iw_p1_speculative_child}, {ldq_uop_9_iw_p1_speculative_child}, {ldq_uop_8_iw_p1_speculative_child}, {ldq_uop_7_iw_p1_speculative_child}, {ldq_uop_6_iw_p1_speculative_child}, {ldq_uop_5_iw_p1_speculative_child}, {ldq_uop_4_iw_p1_speculative_child}, {ldq_uop_3_iw_p1_speculative_child}, {ldq_uop_2_iw_p1_speculative_child}, {ldq_uop_1_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_149 = {{ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_23_iw_p2_speculative_child}, {ldq_uop_22_iw_p2_speculative_child}, {ldq_uop_21_iw_p2_speculative_child}, {ldq_uop_20_iw_p2_speculative_child}, {ldq_uop_19_iw_p2_speculative_child}, {ldq_uop_18_iw_p2_speculative_child}, {ldq_uop_17_iw_p2_speculative_child}, {ldq_uop_16_iw_p2_speculative_child}, {ldq_uop_15_iw_p2_speculative_child}, {ldq_uop_14_iw_p2_speculative_child}, {ldq_uop_13_iw_p2_speculative_child}, {ldq_uop_12_iw_p2_speculative_child}, {ldq_uop_11_iw_p2_speculative_child}, {ldq_uop_10_iw_p2_speculative_child}, {ldq_uop_9_iw_p2_speculative_child}, {ldq_uop_8_iw_p2_speculative_child}, {ldq_uop_7_iw_p2_speculative_child}, {ldq_uop_6_iw_p2_speculative_child}, {ldq_uop_5_iw_p2_speculative_child}, {ldq_uop_4_iw_p2_speculative_child}, {ldq_uop_3_iw_p2_speculative_child}, {ldq_uop_2_iw_p2_speculative_child}, {ldq_uop_1_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_150 = {{ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_23_iw_p1_bypass_hint}, {ldq_uop_22_iw_p1_bypass_hint}, {ldq_uop_21_iw_p1_bypass_hint}, {ldq_uop_20_iw_p1_bypass_hint}, {ldq_uop_19_iw_p1_bypass_hint}, {ldq_uop_18_iw_p1_bypass_hint}, {ldq_uop_17_iw_p1_bypass_hint}, {ldq_uop_16_iw_p1_bypass_hint}, {ldq_uop_15_iw_p1_bypass_hint}, {ldq_uop_14_iw_p1_bypass_hint}, {ldq_uop_13_iw_p1_bypass_hint}, {ldq_uop_12_iw_p1_bypass_hint}, {ldq_uop_11_iw_p1_bypass_hint}, {ldq_uop_10_iw_p1_bypass_hint}, {ldq_uop_9_iw_p1_bypass_hint}, {ldq_uop_8_iw_p1_bypass_hint}, {ldq_uop_7_iw_p1_bypass_hint}, {ldq_uop_6_iw_p1_bypass_hint}, {ldq_uop_5_iw_p1_bypass_hint}, {ldq_uop_4_iw_p1_bypass_hint}, {ldq_uop_3_iw_p1_bypass_hint}, {ldq_uop_2_iw_p1_bypass_hint}, {ldq_uop_1_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_151 = {{ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_23_iw_p2_bypass_hint}, {ldq_uop_22_iw_p2_bypass_hint}, {ldq_uop_21_iw_p2_bypass_hint}, {ldq_uop_20_iw_p2_bypass_hint}, {ldq_uop_19_iw_p2_bypass_hint}, {ldq_uop_18_iw_p2_bypass_hint}, {ldq_uop_17_iw_p2_bypass_hint}, {ldq_uop_16_iw_p2_bypass_hint}, {ldq_uop_15_iw_p2_bypass_hint}, {ldq_uop_14_iw_p2_bypass_hint}, {ldq_uop_13_iw_p2_bypass_hint}, {ldq_uop_12_iw_p2_bypass_hint}, {ldq_uop_11_iw_p2_bypass_hint}, {ldq_uop_10_iw_p2_bypass_hint}, {ldq_uop_9_iw_p2_bypass_hint}, {ldq_uop_8_iw_p2_bypass_hint}, {ldq_uop_7_iw_p2_bypass_hint}, {ldq_uop_6_iw_p2_bypass_hint}, {ldq_uop_5_iw_p2_bypass_hint}, {ldq_uop_4_iw_p2_bypass_hint}, {ldq_uop_3_iw_p2_bypass_hint}, {ldq_uop_2_iw_p2_bypass_hint}, {ldq_uop_1_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_152 = {{ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_23_iw_p3_bypass_hint}, {ldq_uop_22_iw_p3_bypass_hint}, {ldq_uop_21_iw_p3_bypass_hint}, {ldq_uop_20_iw_p3_bypass_hint}, {ldq_uop_19_iw_p3_bypass_hint}, {ldq_uop_18_iw_p3_bypass_hint}, {ldq_uop_17_iw_p3_bypass_hint}, {ldq_uop_16_iw_p3_bypass_hint}, {ldq_uop_15_iw_p3_bypass_hint}, {ldq_uop_14_iw_p3_bypass_hint}, {ldq_uop_13_iw_p3_bypass_hint}, {ldq_uop_12_iw_p3_bypass_hint}, {ldq_uop_11_iw_p3_bypass_hint}, {ldq_uop_10_iw_p3_bypass_hint}, {ldq_uop_9_iw_p3_bypass_hint}, {ldq_uop_8_iw_p3_bypass_hint}, {ldq_uop_7_iw_p3_bypass_hint}, {ldq_uop_6_iw_p3_bypass_hint}, {ldq_uop_5_iw_p3_bypass_hint}, {ldq_uop_4_iw_p3_bypass_hint}, {ldq_uop_3_iw_p3_bypass_hint}, {ldq_uop_2_iw_p3_bypass_hint}, {ldq_uop_1_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_153 = {{ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_23_dis_col_sel}, {ldq_uop_22_dis_col_sel}, {ldq_uop_21_dis_col_sel}, {ldq_uop_20_dis_col_sel}, {ldq_uop_19_dis_col_sel}, {ldq_uop_18_dis_col_sel}, {ldq_uop_17_dis_col_sel}, {ldq_uop_16_dis_col_sel}, {ldq_uop_15_dis_col_sel}, {ldq_uop_14_dis_col_sel}, {ldq_uop_13_dis_col_sel}, {ldq_uop_12_dis_col_sel}, {ldq_uop_11_dis_col_sel}, {ldq_uop_10_dis_col_sel}, {ldq_uop_9_dis_col_sel}, {ldq_uop_8_dis_col_sel}, {ldq_uop_7_dis_col_sel}, {ldq_uop_6_dis_col_sel}, {ldq_uop_5_dis_col_sel}, {ldq_uop_4_dis_col_sel}, {ldq_uop_3_dis_col_sel}, {ldq_uop_2_dis_col_sel}, {ldq_uop_1_dis_col_sel}, {ldq_uop_0_dis_col_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dis_col_sel = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][15:0] _GEN_154 = {{ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_23_br_mask}, {ldq_uop_22_br_mask}, {ldq_uop_21_br_mask}, {ldq_uop_20_br_mask}, {ldq_uop_19_br_mask}, {ldq_uop_18_br_mask}, {ldq_uop_17_br_mask}, {ldq_uop_16_br_mask}, {ldq_uop_15_br_mask}, {ldq_uop_14_br_mask}, {ldq_uop_13_br_mask}, {ldq_uop_12_br_mask}, {ldq_uop_11_br_mask}, {ldq_uop_10_br_mask}, {ldq_uop_9_br_mask}, {ldq_uop_8_br_mask}, {ldq_uop_7_br_mask}, {ldq_uop_6_br_mask}, {ldq_uop_5_br_mask}, {ldq_uop_4_br_mask}, {ldq_uop_3_br_mask}, {ldq_uop_2_br_mask}, {ldq_uop_1_br_mask}, {ldq_uop_0_br_mask}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_mask = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][3:0] _GEN_155 = {{ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_23_br_tag}, {ldq_uop_22_br_tag}, {ldq_uop_21_br_tag}, {ldq_uop_20_br_tag}, {ldq_uop_19_br_tag}, {ldq_uop_18_br_tag}, {ldq_uop_17_br_tag}, {ldq_uop_16_br_tag}, {ldq_uop_15_br_tag}, {ldq_uop_14_br_tag}, {ldq_uop_13_br_tag}, {ldq_uop_12_br_tag}, {ldq_uop_11_br_tag}, {ldq_uop_10_br_tag}, {ldq_uop_9_br_tag}, {ldq_uop_8_br_tag}, {ldq_uop_7_br_tag}, {ldq_uop_6_br_tag}, {ldq_uop_5_br_tag}, {ldq_uop_4_br_tag}, {ldq_uop_3_br_tag}, {ldq_uop_2_br_tag}, {ldq_uop_1_br_tag}, {ldq_uop_0_br_tag}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_tag = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][3:0] _GEN_156 = {{ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_23_br_type}, {ldq_uop_22_br_type}, {ldq_uop_21_br_type}, {ldq_uop_20_br_type}, {ldq_uop_19_br_type}, {ldq_uop_18_br_type}, {ldq_uop_17_br_type}, {ldq_uop_16_br_type}, {ldq_uop_15_br_type}, {ldq_uop_14_br_type}, {ldq_uop_13_br_type}, {ldq_uop_12_br_type}, {ldq_uop_11_br_type}, {ldq_uop_10_br_type}, {ldq_uop_9_br_type}, {ldq_uop_8_br_type}, {ldq_uop_7_br_type}, {ldq_uop_6_br_type}, {ldq_uop_5_br_type}, {ldq_uop_4_br_type}, {ldq_uop_3_br_type}, {ldq_uop_2_br_type}, {ldq_uop_1_br_type}, {ldq_uop_0_br_type}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_type = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_157 = {{ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_23_is_sfb}, {ldq_uop_22_is_sfb}, {ldq_uop_21_is_sfb}, {ldq_uop_20_is_sfb}, {ldq_uop_19_is_sfb}, {ldq_uop_18_is_sfb}, {ldq_uop_17_is_sfb}, {ldq_uop_16_is_sfb}, {ldq_uop_15_is_sfb}, {ldq_uop_14_is_sfb}, {ldq_uop_13_is_sfb}, {ldq_uop_12_is_sfb}, {ldq_uop_11_is_sfb}, {ldq_uop_10_is_sfb}, {ldq_uop_9_is_sfb}, {ldq_uop_8_is_sfb}, {ldq_uop_7_is_sfb}, {ldq_uop_6_is_sfb}, {ldq_uop_5_is_sfb}, {ldq_uop_4_is_sfb}, {ldq_uop_3_is_sfb}, {ldq_uop_2_is_sfb}, {ldq_uop_1_is_sfb}, {ldq_uop_0_is_sfb}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfb = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_158 = {{ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_23_is_fence}, {ldq_uop_22_is_fence}, {ldq_uop_21_is_fence}, {ldq_uop_20_is_fence}, {ldq_uop_19_is_fence}, {ldq_uop_18_is_fence}, {ldq_uop_17_is_fence}, {ldq_uop_16_is_fence}, {ldq_uop_15_is_fence}, {ldq_uop_14_is_fence}, {ldq_uop_13_is_fence}, {ldq_uop_12_is_fence}, {ldq_uop_11_is_fence}, {ldq_uop_10_is_fence}, {ldq_uop_9_is_fence}, {ldq_uop_8_is_fence}, {ldq_uop_7_is_fence}, {ldq_uop_6_is_fence}, {ldq_uop_5_is_fence}, {ldq_uop_4_is_fence}, {ldq_uop_3_is_fence}, {ldq_uop_2_is_fence}, {ldq_uop_1_is_fence}, {ldq_uop_0_is_fence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fence = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_159 = {{ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_23_is_fencei}, {ldq_uop_22_is_fencei}, {ldq_uop_21_is_fencei}, {ldq_uop_20_is_fencei}, {ldq_uop_19_is_fencei}, {ldq_uop_18_is_fencei}, {ldq_uop_17_is_fencei}, {ldq_uop_16_is_fencei}, {ldq_uop_15_is_fencei}, {ldq_uop_14_is_fencei}, {ldq_uop_13_is_fencei}, {ldq_uop_12_is_fencei}, {ldq_uop_11_is_fencei}, {ldq_uop_10_is_fencei}, {ldq_uop_9_is_fencei}, {ldq_uop_8_is_fencei}, {ldq_uop_7_is_fencei}, {ldq_uop_6_is_fencei}, {ldq_uop_5_is_fencei}, {ldq_uop_4_is_fencei}, {ldq_uop_3_is_fencei}, {ldq_uop_2_is_fencei}, {ldq_uop_1_is_fencei}, {ldq_uop_0_is_fencei}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fencei = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_160 = {{ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_23_is_sfence}, {ldq_uop_22_is_sfence}, {ldq_uop_21_is_sfence}, {ldq_uop_20_is_sfence}, {ldq_uop_19_is_sfence}, {ldq_uop_18_is_sfence}, {ldq_uop_17_is_sfence}, {ldq_uop_16_is_sfence}, {ldq_uop_15_is_sfence}, {ldq_uop_14_is_sfence}, {ldq_uop_13_is_sfence}, {ldq_uop_12_is_sfence}, {ldq_uop_11_is_sfence}, {ldq_uop_10_is_sfence}, {ldq_uop_9_is_sfence}, {ldq_uop_8_is_sfence}, {ldq_uop_7_is_sfence}, {ldq_uop_6_is_sfence}, {ldq_uop_5_is_sfence}, {ldq_uop_4_is_sfence}, {ldq_uop_3_is_sfence}, {ldq_uop_2_is_sfence}, {ldq_uop_1_is_sfence}, {ldq_uop_0_is_sfence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfence = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_161 = {{ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_23_is_amo}, {ldq_uop_22_is_amo}, {ldq_uop_21_is_amo}, {ldq_uop_20_is_amo}, {ldq_uop_19_is_amo}, {ldq_uop_18_is_amo}, {ldq_uop_17_is_amo}, {ldq_uop_16_is_amo}, {ldq_uop_15_is_amo}, {ldq_uop_14_is_amo}, {ldq_uop_13_is_amo}, {ldq_uop_12_is_amo}, {ldq_uop_11_is_amo}, {ldq_uop_10_is_amo}, {ldq_uop_9_is_amo}, {ldq_uop_8_is_amo}, {ldq_uop_7_is_amo}, {ldq_uop_6_is_amo}, {ldq_uop_5_is_amo}, {ldq_uop_4_is_amo}, {ldq_uop_3_is_amo}, {ldq_uop_2_is_amo}, {ldq_uop_1_is_amo}, {ldq_uop_0_is_amo}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_amo = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_162 = {{ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_23_is_eret}, {ldq_uop_22_is_eret}, {ldq_uop_21_is_eret}, {ldq_uop_20_is_eret}, {ldq_uop_19_is_eret}, {ldq_uop_18_is_eret}, {ldq_uop_17_is_eret}, {ldq_uop_16_is_eret}, {ldq_uop_15_is_eret}, {ldq_uop_14_is_eret}, {ldq_uop_13_is_eret}, {ldq_uop_12_is_eret}, {ldq_uop_11_is_eret}, {ldq_uop_10_is_eret}, {ldq_uop_9_is_eret}, {ldq_uop_8_is_eret}, {ldq_uop_7_is_eret}, {ldq_uop_6_is_eret}, {ldq_uop_5_is_eret}, {ldq_uop_4_is_eret}, {ldq_uop_3_is_eret}, {ldq_uop_2_is_eret}, {ldq_uop_1_is_eret}, {ldq_uop_0_is_eret}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_eret = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_163 = {{ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_23_is_sys_pc2epc}, {ldq_uop_22_is_sys_pc2epc}, {ldq_uop_21_is_sys_pc2epc}, {ldq_uop_20_is_sys_pc2epc}, {ldq_uop_19_is_sys_pc2epc}, {ldq_uop_18_is_sys_pc2epc}, {ldq_uop_17_is_sys_pc2epc}, {ldq_uop_16_is_sys_pc2epc}, {ldq_uop_15_is_sys_pc2epc}, {ldq_uop_14_is_sys_pc2epc}, {ldq_uop_13_is_sys_pc2epc}, {ldq_uop_12_is_sys_pc2epc}, {ldq_uop_11_is_sys_pc2epc}, {ldq_uop_10_is_sys_pc2epc}, {ldq_uop_9_is_sys_pc2epc}, {ldq_uop_8_is_sys_pc2epc}, {ldq_uop_7_is_sys_pc2epc}, {ldq_uop_6_is_sys_pc2epc}, {ldq_uop_5_is_sys_pc2epc}, {ldq_uop_4_is_sys_pc2epc}, {ldq_uop_3_is_sys_pc2epc}, {ldq_uop_2_is_sys_pc2epc}, {ldq_uop_1_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_164 = {{ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_23_is_rocc}, {ldq_uop_22_is_rocc}, {ldq_uop_21_is_rocc}, {ldq_uop_20_is_rocc}, {ldq_uop_19_is_rocc}, {ldq_uop_18_is_rocc}, {ldq_uop_17_is_rocc}, {ldq_uop_16_is_rocc}, {ldq_uop_15_is_rocc}, {ldq_uop_14_is_rocc}, {ldq_uop_13_is_rocc}, {ldq_uop_12_is_rocc}, {ldq_uop_11_is_rocc}, {ldq_uop_10_is_rocc}, {ldq_uop_9_is_rocc}, {ldq_uop_8_is_rocc}, {ldq_uop_7_is_rocc}, {ldq_uop_6_is_rocc}, {ldq_uop_5_is_rocc}, {ldq_uop_4_is_rocc}, {ldq_uop_3_is_rocc}, {ldq_uop_2_is_rocc}, {ldq_uop_1_is_rocc}, {ldq_uop_0_is_rocc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rocc = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_165 = {{ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_23_is_mov}, {ldq_uop_22_is_mov}, {ldq_uop_21_is_mov}, {ldq_uop_20_is_mov}, {ldq_uop_19_is_mov}, {ldq_uop_18_is_mov}, {ldq_uop_17_is_mov}, {ldq_uop_16_is_mov}, {ldq_uop_15_is_mov}, {ldq_uop_14_is_mov}, {ldq_uop_13_is_mov}, {ldq_uop_12_is_mov}, {ldq_uop_11_is_mov}, {ldq_uop_10_is_mov}, {ldq_uop_9_is_mov}, {ldq_uop_8_is_mov}, {ldq_uop_7_is_mov}, {ldq_uop_6_is_mov}, {ldq_uop_5_is_mov}, {ldq_uop_4_is_mov}, {ldq_uop_3_is_mov}, {ldq_uop_2_is_mov}, {ldq_uop_1_is_mov}, {ldq_uop_0_is_mov}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_mov = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_166 = {{ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_23_ftq_idx}, {ldq_uop_22_ftq_idx}, {ldq_uop_21_ftq_idx}, {ldq_uop_20_ftq_idx}, {ldq_uop_19_ftq_idx}, {ldq_uop_18_ftq_idx}, {ldq_uop_17_ftq_idx}, {ldq_uop_16_ftq_idx}, {ldq_uop_15_ftq_idx}, {ldq_uop_14_ftq_idx}, {ldq_uop_13_ftq_idx}, {ldq_uop_12_ftq_idx}, {ldq_uop_11_ftq_idx}, {ldq_uop_10_ftq_idx}, {ldq_uop_9_ftq_idx}, {ldq_uop_8_ftq_idx}, {ldq_uop_7_ftq_idx}, {ldq_uop_6_ftq_idx}, {ldq_uop_5_ftq_idx}, {ldq_uop_4_ftq_idx}, {ldq_uop_3_ftq_idx}, {ldq_uop_2_ftq_idx}, {ldq_uop_1_ftq_idx}, {ldq_uop_0_ftq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ftq_idx = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_167 = {{ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_23_edge_inst}, {ldq_uop_22_edge_inst}, {ldq_uop_21_edge_inst}, {ldq_uop_20_edge_inst}, {ldq_uop_19_edge_inst}, {ldq_uop_18_edge_inst}, {ldq_uop_17_edge_inst}, {ldq_uop_16_edge_inst}, {ldq_uop_15_edge_inst}, {ldq_uop_14_edge_inst}, {ldq_uop_13_edge_inst}, {ldq_uop_12_edge_inst}, {ldq_uop_11_edge_inst}, {ldq_uop_10_edge_inst}, {ldq_uop_9_edge_inst}, {ldq_uop_8_edge_inst}, {ldq_uop_7_edge_inst}, {ldq_uop_6_edge_inst}, {ldq_uop_5_edge_inst}, {ldq_uop_4_edge_inst}, {ldq_uop_3_edge_inst}, {ldq_uop_2_edge_inst}, {ldq_uop_1_edge_inst}, {ldq_uop_0_edge_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_edge_inst = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_168 = {{ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_23_pc_lob}, {ldq_uop_22_pc_lob}, {ldq_uop_21_pc_lob}, {ldq_uop_20_pc_lob}, {ldq_uop_19_pc_lob}, {ldq_uop_18_pc_lob}, {ldq_uop_17_pc_lob}, {ldq_uop_16_pc_lob}, {ldq_uop_15_pc_lob}, {ldq_uop_14_pc_lob}, {ldq_uop_13_pc_lob}, {ldq_uop_12_pc_lob}, {ldq_uop_11_pc_lob}, {ldq_uop_10_pc_lob}, {ldq_uop_9_pc_lob}, {ldq_uop_8_pc_lob}, {ldq_uop_7_pc_lob}, {ldq_uop_6_pc_lob}, {ldq_uop_5_pc_lob}, {ldq_uop_4_pc_lob}, {ldq_uop_3_pc_lob}, {ldq_uop_2_pc_lob}, {ldq_uop_1_pc_lob}, {ldq_uop_0_pc_lob}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pc_lob = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_169 = {{ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_23_taken}, {ldq_uop_22_taken}, {ldq_uop_21_taken}, {ldq_uop_20_taken}, {ldq_uop_19_taken}, {ldq_uop_18_taken}, {ldq_uop_17_taken}, {ldq_uop_16_taken}, {ldq_uop_15_taken}, {ldq_uop_14_taken}, {ldq_uop_13_taken}, {ldq_uop_12_taken}, {ldq_uop_11_taken}, {ldq_uop_10_taken}, {ldq_uop_9_taken}, {ldq_uop_8_taken}, {ldq_uop_7_taken}, {ldq_uop_6_taken}, {ldq_uop_5_taken}, {ldq_uop_4_taken}, {ldq_uop_3_taken}, {ldq_uop_2_taken}, {ldq_uop_1_taken}, {ldq_uop_0_taken}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_taken = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_170 = {{ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_23_imm_rename}, {ldq_uop_22_imm_rename}, {ldq_uop_21_imm_rename}, {ldq_uop_20_imm_rename}, {ldq_uop_19_imm_rename}, {ldq_uop_18_imm_rename}, {ldq_uop_17_imm_rename}, {ldq_uop_16_imm_rename}, {ldq_uop_15_imm_rename}, {ldq_uop_14_imm_rename}, {ldq_uop_13_imm_rename}, {ldq_uop_12_imm_rename}, {ldq_uop_11_imm_rename}, {ldq_uop_10_imm_rename}, {ldq_uop_9_imm_rename}, {ldq_uop_8_imm_rename}, {ldq_uop_7_imm_rename}, {ldq_uop_6_imm_rename}, {ldq_uop_5_imm_rename}, {ldq_uop_4_imm_rename}, {ldq_uop_3_imm_rename}, {ldq_uop_2_imm_rename}, {ldq_uop_1_imm_rename}, {ldq_uop_0_imm_rename}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_rename = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_171 = {{ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_23_imm_sel}, {ldq_uop_22_imm_sel}, {ldq_uop_21_imm_sel}, {ldq_uop_20_imm_sel}, {ldq_uop_19_imm_sel}, {ldq_uop_18_imm_sel}, {ldq_uop_17_imm_sel}, {ldq_uop_16_imm_sel}, {ldq_uop_15_imm_sel}, {ldq_uop_14_imm_sel}, {ldq_uop_13_imm_sel}, {ldq_uop_12_imm_sel}, {ldq_uop_11_imm_sel}, {ldq_uop_10_imm_sel}, {ldq_uop_9_imm_sel}, {ldq_uop_8_imm_sel}, {ldq_uop_7_imm_sel}, {ldq_uop_6_imm_sel}, {ldq_uop_5_imm_sel}, {ldq_uop_4_imm_sel}, {ldq_uop_3_imm_sel}, {ldq_uop_2_imm_sel}, {ldq_uop_1_imm_sel}, {ldq_uop_0_imm_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_sel = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_172 = {{ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_23_pimm}, {ldq_uop_22_pimm}, {ldq_uop_21_pimm}, {ldq_uop_20_pimm}, {ldq_uop_19_pimm}, {ldq_uop_18_pimm}, {ldq_uop_17_pimm}, {ldq_uop_16_pimm}, {ldq_uop_15_pimm}, {ldq_uop_14_pimm}, {ldq_uop_13_pimm}, {ldq_uop_12_pimm}, {ldq_uop_11_pimm}, {ldq_uop_10_pimm}, {ldq_uop_9_pimm}, {ldq_uop_8_pimm}, {ldq_uop_7_pimm}, {ldq_uop_6_pimm}, {ldq_uop_5_pimm}, {ldq_uop_4_pimm}, {ldq_uop_3_pimm}, {ldq_uop_2_pimm}, {ldq_uop_1_pimm}, {ldq_uop_0_pimm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pimm = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][19:0] _GEN_173 = {{ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_23_imm_packed}, {ldq_uop_22_imm_packed}, {ldq_uop_21_imm_packed}, {ldq_uop_20_imm_packed}, {ldq_uop_19_imm_packed}, {ldq_uop_18_imm_packed}, {ldq_uop_17_imm_packed}, {ldq_uop_16_imm_packed}, {ldq_uop_15_imm_packed}, {ldq_uop_14_imm_packed}, {ldq_uop_13_imm_packed}, {ldq_uop_12_imm_packed}, {ldq_uop_11_imm_packed}, {ldq_uop_10_imm_packed}, {ldq_uop_9_imm_packed}, {ldq_uop_8_imm_packed}, {ldq_uop_7_imm_packed}, {ldq_uop_6_imm_packed}, {ldq_uop_5_imm_packed}, {ldq_uop_4_imm_packed}, {ldq_uop_3_imm_packed}, {ldq_uop_2_imm_packed}, {ldq_uop_1_imm_packed}, {ldq_uop_0_imm_packed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_packed = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_174 = {{ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_23_op1_sel}, {ldq_uop_22_op1_sel}, {ldq_uop_21_op1_sel}, {ldq_uop_20_op1_sel}, {ldq_uop_19_op1_sel}, {ldq_uop_18_op1_sel}, {ldq_uop_17_op1_sel}, {ldq_uop_16_op1_sel}, {ldq_uop_15_op1_sel}, {ldq_uop_14_op1_sel}, {ldq_uop_13_op1_sel}, {ldq_uop_12_op1_sel}, {ldq_uop_11_op1_sel}, {ldq_uop_10_op1_sel}, {ldq_uop_9_op1_sel}, {ldq_uop_8_op1_sel}, {ldq_uop_7_op1_sel}, {ldq_uop_6_op1_sel}, {ldq_uop_5_op1_sel}, {ldq_uop_4_op1_sel}, {ldq_uop_3_op1_sel}, {ldq_uop_2_op1_sel}, {ldq_uop_1_op1_sel}, {ldq_uop_0_op1_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op1_sel = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_175 = {{ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_23_op2_sel}, {ldq_uop_22_op2_sel}, {ldq_uop_21_op2_sel}, {ldq_uop_20_op2_sel}, {ldq_uop_19_op2_sel}, {ldq_uop_18_op2_sel}, {ldq_uop_17_op2_sel}, {ldq_uop_16_op2_sel}, {ldq_uop_15_op2_sel}, {ldq_uop_14_op2_sel}, {ldq_uop_13_op2_sel}, {ldq_uop_12_op2_sel}, {ldq_uop_11_op2_sel}, {ldq_uop_10_op2_sel}, {ldq_uop_9_op2_sel}, {ldq_uop_8_op2_sel}, {ldq_uop_7_op2_sel}, {ldq_uop_6_op2_sel}, {ldq_uop_5_op2_sel}, {ldq_uop_4_op2_sel}, {ldq_uop_3_op2_sel}, {ldq_uop_2_op2_sel}, {ldq_uop_1_op2_sel}, {ldq_uop_0_op2_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op2_sel = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_176 = {{ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_23_fp_ctrl_ldst}, {ldq_uop_22_fp_ctrl_ldst}, {ldq_uop_21_fp_ctrl_ldst}, {ldq_uop_20_fp_ctrl_ldst}, {ldq_uop_19_fp_ctrl_ldst}, {ldq_uop_18_fp_ctrl_ldst}, {ldq_uop_17_fp_ctrl_ldst}, {ldq_uop_16_fp_ctrl_ldst}, {ldq_uop_15_fp_ctrl_ldst}, {ldq_uop_14_fp_ctrl_ldst}, {ldq_uop_13_fp_ctrl_ldst}, {ldq_uop_12_fp_ctrl_ldst}, {ldq_uop_11_fp_ctrl_ldst}, {ldq_uop_10_fp_ctrl_ldst}, {ldq_uop_9_fp_ctrl_ldst}, {ldq_uop_8_fp_ctrl_ldst}, {ldq_uop_7_fp_ctrl_ldst}, {ldq_uop_6_fp_ctrl_ldst}, {ldq_uop_5_fp_ctrl_ldst}, {ldq_uop_4_fp_ctrl_ldst}, {ldq_uop_3_fp_ctrl_ldst}, {ldq_uop_2_fp_ctrl_ldst}, {ldq_uop_1_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_177 = {{ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_23_fp_ctrl_wen}, {ldq_uop_22_fp_ctrl_wen}, {ldq_uop_21_fp_ctrl_wen}, {ldq_uop_20_fp_ctrl_wen}, {ldq_uop_19_fp_ctrl_wen}, {ldq_uop_18_fp_ctrl_wen}, {ldq_uop_17_fp_ctrl_wen}, {ldq_uop_16_fp_ctrl_wen}, {ldq_uop_15_fp_ctrl_wen}, {ldq_uop_14_fp_ctrl_wen}, {ldq_uop_13_fp_ctrl_wen}, {ldq_uop_12_fp_ctrl_wen}, {ldq_uop_11_fp_ctrl_wen}, {ldq_uop_10_fp_ctrl_wen}, {ldq_uop_9_fp_ctrl_wen}, {ldq_uop_8_fp_ctrl_wen}, {ldq_uop_7_fp_ctrl_wen}, {ldq_uop_6_fp_ctrl_wen}, {ldq_uop_5_fp_ctrl_wen}, {ldq_uop_4_fp_ctrl_wen}, {ldq_uop_3_fp_ctrl_wen}, {ldq_uop_2_fp_ctrl_wen}, {ldq_uop_1_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_178 = {{ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_23_fp_ctrl_ren1}, {ldq_uop_22_fp_ctrl_ren1}, {ldq_uop_21_fp_ctrl_ren1}, {ldq_uop_20_fp_ctrl_ren1}, {ldq_uop_19_fp_ctrl_ren1}, {ldq_uop_18_fp_ctrl_ren1}, {ldq_uop_17_fp_ctrl_ren1}, {ldq_uop_16_fp_ctrl_ren1}, {ldq_uop_15_fp_ctrl_ren1}, {ldq_uop_14_fp_ctrl_ren1}, {ldq_uop_13_fp_ctrl_ren1}, {ldq_uop_12_fp_ctrl_ren1}, {ldq_uop_11_fp_ctrl_ren1}, {ldq_uop_10_fp_ctrl_ren1}, {ldq_uop_9_fp_ctrl_ren1}, {ldq_uop_8_fp_ctrl_ren1}, {ldq_uop_7_fp_ctrl_ren1}, {ldq_uop_6_fp_ctrl_ren1}, {ldq_uop_5_fp_ctrl_ren1}, {ldq_uop_4_fp_ctrl_ren1}, {ldq_uop_3_fp_ctrl_ren1}, {ldq_uop_2_fp_ctrl_ren1}, {ldq_uop_1_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_179 = {{ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_23_fp_ctrl_ren2}, {ldq_uop_22_fp_ctrl_ren2}, {ldq_uop_21_fp_ctrl_ren2}, {ldq_uop_20_fp_ctrl_ren2}, {ldq_uop_19_fp_ctrl_ren2}, {ldq_uop_18_fp_ctrl_ren2}, {ldq_uop_17_fp_ctrl_ren2}, {ldq_uop_16_fp_ctrl_ren2}, {ldq_uop_15_fp_ctrl_ren2}, {ldq_uop_14_fp_ctrl_ren2}, {ldq_uop_13_fp_ctrl_ren2}, {ldq_uop_12_fp_ctrl_ren2}, {ldq_uop_11_fp_ctrl_ren2}, {ldq_uop_10_fp_ctrl_ren2}, {ldq_uop_9_fp_ctrl_ren2}, {ldq_uop_8_fp_ctrl_ren2}, {ldq_uop_7_fp_ctrl_ren2}, {ldq_uop_6_fp_ctrl_ren2}, {ldq_uop_5_fp_ctrl_ren2}, {ldq_uop_4_fp_ctrl_ren2}, {ldq_uop_3_fp_ctrl_ren2}, {ldq_uop_2_fp_ctrl_ren2}, {ldq_uop_1_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_180 = {{ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_23_fp_ctrl_ren3}, {ldq_uop_22_fp_ctrl_ren3}, {ldq_uop_21_fp_ctrl_ren3}, {ldq_uop_20_fp_ctrl_ren3}, {ldq_uop_19_fp_ctrl_ren3}, {ldq_uop_18_fp_ctrl_ren3}, {ldq_uop_17_fp_ctrl_ren3}, {ldq_uop_16_fp_ctrl_ren3}, {ldq_uop_15_fp_ctrl_ren3}, {ldq_uop_14_fp_ctrl_ren3}, {ldq_uop_13_fp_ctrl_ren3}, {ldq_uop_12_fp_ctrl_ren3}, {ldq_uop_11_fp_ctrl_ren3}, {ldq_uop_10_fp_ctrl_ren3}, {ldq_uop_9_fp_ctrl_ren3}, {ldq_uop_8_fp_ctrl_ren3}, {ldq_uop_7_fp_ctrl_ren3}, {ldq_uop_6_fp_ctrl_ren3}, {ldq_uop_5_fp_ctrl_ren3}, {ldq_uop_4_fp_ctrl_ren3}, {ldq_uop_3_fp_ctrl_ren3}, {ldq_uop_2_fp_ctrl_ren3}, {ldq_uop_1_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_181 = {{ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_23_fp_ctrl_swap12}, {ldq_uop_22_fp_ctrl_swap12}, {ldq_uop_21_fp_ctrl_swap12}, {ldq_uop_20_fp_ctrl_swap12}, {ldq_uop_19_fp_ctrl_swap12}, {ldq_uop_18_fp_ctrl_swap12}, {ldq_uop_17_fp_ctrl_swap12}, {ldq_uop_16_fp_ctrl_swap12}, {ldq_uop_15_fp_ctrl_swap12}, {ldq_uop_14_fp_ctrl_swap12}, {ldq_uop_13_fp_ctrl_swap12}, {ldq_uop_12_fp_ctrl_swap12}, {ldq_uop_11_fp_ctrl_swap12}, {ldq_uop_10_fp_ctrl_swap12}, {ldq_uop_9_fp_ctrl_swap12}, {ldq_uop_8_fp_ctrl_swap12}, {ldq_uop_7_fp_ctrl_swap12}, {ldq_uop_6_fp_ctrl_swap12}, {ldq_uop_5_fp_ctrl_swap12}, {ldq_uop_4_fp_ctrl_swap12}, {ldq_uop_3_fp_ctrl_swap12}, {ldq_uop_2_fp_ctrl_swap12}, {ldq_uop_1_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_182 = {{ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_23_fp_ctrl_swap23}, {ldq_uop_22_fp_ctrl_swap23}, {ldq_uop_21_fp_ctrl_swap23}, {ldq_uop_20_fp_ctrl_swap23}, {ldq_uop_19_fp_ctrl_swap23}, {ldq_uop_18_fp_ctrl_swap23}, {ldq_uop_17_fp_ctrl_swap23}, {ldq_uop_16_fp_ctrl_swap23}, {ldq_uop_15_fp_ctrl_swap23}, {ldq_uop_14_fp_ctrl_swap23}, {ldq_uop_13_fp_ctrl_swap23}, {ldq_uop_12_fp_ctrl_swap23}, {ldq_uop_11_fp_ctrl_swap23}, {ldq_uop_10_fp_ctrl_swap23}, {ldq_uop_9_fp_ctrl_swap23}, {ldq_uop_8_fp_ctrl_swap23}, {ldq_uop_7_fp_ctrl_swap23}, {ldq_uop_6_fp_ctrl_swap23}, {ldq_uop_5_fp_ctrl_swap23}, {ldq_uop_4_fp_ctrl_swap23}, {ldq_uop_3_fp_ctrl_swap23}, {ldq_uop_2_fp_ctrl_swap23}, {ldq_uop_1_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_183 = {{ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_23_fp_ctrl_typeTagIn}, {ldq_uop_22_fp_ctrl_typeTagIn}, {ldq_uop_21_fp_ctrl_typeTagIn}, {ldq_uop_20_fp_ctrl_typeTagIn}, {ldq_uop_19_fp_ctrl_typeTagIn}, {ldq_uop_18_fp_ctrl_typeTagIn}, {ldq_uop_17_fp_ctrl_typeTagIn}, {ldq_uop_16_fp_ctrl_typeTagIn}, {ldq_uop_15_fp_ctrl_typeTagIn}, {ldq_uop_14_fp_ctrl_typeTagIn}, {ldq_uop_13_fp_ctrl_typeTagIn}, {ldq_uop_12_fp_ctrl_typeTagIn}, {ldq_uop_11_fp_ctrl_typeTagIn}, {ldq_uop_10_fp_ctrl_typeTagIn}, {ldq_uop_9_fp_ctrl_typeTagIn}, {ldq_uop_8_fp_ctrl_typeTagIn}, {ldq_uop_7_fp_ctrl_typeTagIn}, {ldq_uop_6_fp_ctrl_typeTagIn}, {ldq_uop_5_fp_ctrl_typeTagIn}, {ldq_uop_4_fp_ctrl_typeTagIn}, {ldq_uop_3_fp_ctrl_typeTagIn}, {ldq_uop_2_fp_ctrl_typeTagIn}, {ldq_uop_1_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_184 = {{ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_23_fp_ctrl_typeTagOut}, {ldq_uop_22_fp_ctrl_typeTagOut}, {ldq_uop_21_fp_ctrl_typeTagOut}, {ldq_uop_20_fp_ctrl_typeTagOut}, {ldq_uop_19_fp_ctrl_typeTagOut}, {ldq_uop_18_fp_ctrl_typeTagOut}, {ldq_uop_17_fp_ctrl_typeTagOut}, {ldq_uop_16_fp_ctrl_typeTagOut}, {ldq_uop_15_fp_ctrl_typeTagOut}, {ldq_uop_14_fp_ctrl_typeTagOut}, {ldq_uop_13_fp_ctrl_typeTagOut}, {ldq_uop_12_fp_ctrl_typeTagOut}, {ldq_uop_11_fp_ctrl_typeTagOut}, {ldq_uop_10_fp_ctrl_typeTagOut}, {ldq_uop_9_fp_ctrl_typeTagOut}, {ldq_uop_8_fp_ctrl_typeTagOut}, {ldq_uop_7_fp_ctrl_typeTagOut}, {ldq_uop_6_fp_ctrl_typeTagOut}, {ldq_uop_5_fp_ctrl_typeTagOut}, {ldq_uop_4_fp_ctrl_typeTagOut}, {ldq_uop_3_fp_ctrl_typeTagOut}, {ldq_uop_2_fp_ctrl_typeTagOut}, {ldq_uop_1_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_185 = {{ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_23_fp_ctrl_fromint}, {ldq_uop_22_fp_ctrl_fromint}, {ldq_uop_21_fp_ctrl_fromint}, {ldq_uop_20_fp_ctrl_fromint}, {ldq_uop_19_fp_ctrl_fromint}, {ldq_uop_18_fp_ctrl_fromint}, {ldq_uop_17_fp_ctrl_fromint}, {ldq_uop_16_fp_ctrl_fromint}, {ldq_uop_15_fp_ctrl_fromint}, {ldq_uop_14_fp_ctrl_fromint}, {ldq_uop_13_fp_ctrl_fromint}, {ldq_uop_12_fp_ctrl_fromint}, {ldq_uop_11_fp_ctrl_fromint}, {ldq_uop_10_fp_ctrl_fromint}, {ldq_uop_9_fp_ctrl_fromint}, {ldq_uop_8_fp_ctrl_fromint}, {ldq_uop_7_fp_ctrl_fromint}, {ldq_uop_6_fp_ctrl_fromint}, {ldq_uop_5_fp_ctrl_fromint}, {ldq_uop_4_fp_ctrl_fromint}, {ldq_uop_3_fp_ctrl_fromint}, {ldq_uop_2_fp_ctrl_fromint}, {ldq_uop_1_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_186 = {{ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_23_fp_ctrl_toint}, {ldq_uop_22_fp_ctrl_toint}, {ldq_uop_21_fp_ctrl_toint}, {ldq_uop_20_fp_ctrl_toint}, {ldq_uop_19_fp_ctrl_toint}, {ldq_uop_18_fp_ctrl_toint}, {ldq_uop_17_fp_ctrl_toint}, {ldq_uop_16_fp_ctrl_toint}, {ldq_uop_15_fp_ctrl_toint}, {ldq_uop_14_fp_ctrl_toint}, {ldq_uop_13_fp_ctrl_toint}, {ldq_uop_12_fp_ctrl_toint}, {ldq_uop_11_fp_ctrl_toint}, {ldq_uop_10_fp_ctrl_toint}, {ldq_uop_9_fp_ctrl_toint}, {ldq_uop_8_fp_ctrl_toint}, {ldq_uop_7_fp_ctrl_toint}, {ldq_uop_6_fp_ctrl_toint}, {ldq_uop_5_fp_ctrl_toint}, {ldq_uop_4_fp_ctrl_toint}, {ldq_uop_3_fp_ctrl_toint}, {ldq_uop_2_fp_ctrl_toint}, {ldq_uop_1_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_187 = {{ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_23_fp_ctrl_fastpipe}, {ldq_uop_22_fp_ctrl_fastpipe}, {ldq_uop_21_fp_ctrl_fastpipe}, {ldq_uop_20_fp_ctrl_fastpipe}, {ldq_uop_19_fp_ctrl_fastpipe}, {ldq_uop_18_fp_ctrl_fastpipe}, {ldq_uop_17_fp_ctrl_fastpipe}, {ldq_uop_16_fp_ctrl_fastpipe}, {ldq_uop_15_fp_ctrl_fastpipe}, {ldq_uop_14_fp_ctrl_fastpipe}, {ldq_uop_13_fp_ctrl_fastpipe}, {ldq_uop_12_fp_ctrl_fastpipe}, {ldq_uop_11_fp_ctrl_fastpipe}, {ldq_uop_10_fp_ctrl_fastpipe}, {ldq_uop_9_fp_ctrl_fastpipe}, {ldq_uop_8_fp_ctrl_fastpipe}, {ldq_uop_7_fp_ctrl_fastpipe}, {ldq_uop_6_fp_ctrl_fastpipe}, {ldq_uop_5_fp_ctrl_fastpipe}, {ldq_uop_4_fp_ctrl_fastpipe}, {ldq_uop_3_fp_ctrl_fastpipe}, {ldq_uop_2_fp_ctrl_fastpipe}, {ldq_uop_1_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_188 = {{ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_23_fp_ctrl_fma}, {ldq_uop_22_fp_ctrl_fma}, {ldq_uop_21_fp_ctrl_fma}, {ldq_uop_20_fp_ctrl_fma}, {ldq_uop_19_fp_ctrl_fma}, {ldq_uop_18_fp_ctrl_fma}, {ldq_uop_17_fp_ctrl_fma}, {ldq_uop_16_fp_ctrl_fma}, {ldq_uop_15_fp_ctrl_fma}, {ldq_uop_14_fp_ctrl_fma}, {ldq_uop_13_fp_ctrl_fma}, {ldq_uop_12_fp_ctrl_fma}, {ldq_uop_11_fp_ctrl_fma}, {ldq_uop_10_fp_ctrl_fma}, {ldq_uop_9_fp_ctrl_fma}, {ldq_uop_8_fp_ctrl_fma}, {ldq_uop_7_fp_ctrl_fma}, {ldq_uop_6_fp_ctrl_fma}, {ldq_uop_5_fp_ctrl_fma}, {ldq_uop_4_fp_ctrl_fma}, {ldq_uop_3_fp_ctrl_fma}, {ldq_uop_2_fp_ctrl_fma}, {ldq_uop_1_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_189 = {{ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_23_fp_ctrl_div}, {ldq_uop_22_fp_ctrl_div}, {ldq_uop_21_fp_ctrl_div}, {ldq_uop_20_fp_ctrl_div}, {ldq_uop_19_fp_ctrl_div}, {ldq_uop_18_fp_ctrl_div}, {ldq_uop_17_fp_ctrl_div}, {ldq_uop_16_fp_ctrl_div}, {ldq_uop_15_fp_ctrl_div}, {ldq_uop_14_fp_ctrl_div}, {ldq_uop_13_fp_ctrl_div}, {ldq_uop_12_fp_ctrl_div}, {ldq_uop_11_fp_ctrl_div}, {ldq_uop_10_fp_ctrl_div}, {ldq_uop_9_fp_ctrl_div}, {ldq_uop_8_fp_ctrl_div}, {ldq_uop_7_fp_ctrl_div}, {ldq_uop_6_fp_ctrl_div}, {ldq_uop_5_fp_ctrl_div}, {ldq_uop_4_fp_ctrl_div}, {ldq_uop_3_fp_ctrl_div}, {ldq_uop_2_fp_ctrl_div}, {ldq_uop_1_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_190 = {{ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_23_fp_ctrl_sqrt}, {ldq_uop_22_fp_ctrl_sqrt}, {ldq_uop_21_fp_ctrl_sqrt}, {ldq_uop_20_fp_ctrl_sqrt}, {ldq_uop_19_fp_ctrl_sqrt}, {ldq_uop_18_fp_ctrl_sqrt}, {ldq_uop_17_fp_ctrl_sqrt}, {ldq_uop_16_fp_ctrl_sqrt}, {ldq_uop_15_fp_ctrl_sqrt}, {ldq_uop_14_fp_ctrl_sqrt}, {ldq_uop_13_fp_ctrl_sqrt}, {ldq_uop_12_fp_ctrl_sqrt}, {ldq_uop_11_fp_ctrl_sqrt}, {ldq_uop_10_fp_ctrl_sqrt}, {ldq_uop_9_fp_ctrl_sqrt}, {ldq_uop_8_fp_ctrl_sqrt}, {ldq_uop_7_fp_ctrl_sqrt}, {ldq_uop_6_fp_ctrl_sqrt}, {ldq_uop_5_fp_ctrl_sqrt}, {ldq_uop_4_fp_ctrl_sqrt}, {ldq_uop_3_fp_ctrl_sqrt}, {ldq_uop_2_fp_ctrl_sqrt}, {ldq_uop_1_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_191 = {{ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_23_fp_ctrl_wflags}, {ldq_uop_22_fp_ctrl_wflags}, {ldq_uop_21_fp_ctrl_wflags}, {ldq_uop_20_fp_ctrl_wflags}, {ldq_uop_19_fp_ctrl_wflags}, {ldq_uop_18_fp_ctrl_wflags}, {ldq_uop_17_fp_ctrl_wflags}, {ldq_uop_16_fp_ctrl_wflags}, {ldq_uop_15_fp_ctrl_wflags}, {ldq_uop_14_fp_ctrl_wflags}, {ldq_uop_13_fp_ctrl_wflags}, {ldq_uop_12_fp_ctrl_wflags}, {ldq_uop_11_fp_ctrl_wflags}, {ldq_uop_10_fp_ctrl_wflags}, {ldq_uop_9_fp_ctrl_wflags}, {ldq_uop_8_fp_ctrl_wflags}, {ldq_uop_7_fp_ctrl_wflags}, {ldq_uop_6_fp_ctrl_wflags}, {ldq_uop_5_fp_ctrl_wflags}, {ldq_uop_4_fp_ctrl_wflags}, {ldq_uop_3_fp_ctrl_wflags}, {ldq_uop_2_fp_ctrl_wflags}, {ldq_uop_1_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_192 = {{ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_23_fp_ctrl_vec}, {ldq_uop_22_fp_ctrl_vec}, {ldq_uop_21_fp_ctrl_vec}, {ldq_uop_20_fp_ctrl_vec}, {ldq_uop_19_fp_ctrl_vec}, {ldq_uop_18_fp_ctrl_vec}, {ldq_uop_17_fp_ctrl_vec}, {ldq_uop_16_fp_ctrl_vec}, {ldq_uop_15_fp_ctrl_vec}, {ldq_uop_14_fp_ctrl_vec}, {ldq_uop_13_fp_ctrl_vec}, {ldq_uop_12_fp_ctrl_vec}, {ldq_uop_11_fp_ctrl_vec}, {ldq_uop_10_fp_ctrl_vec}, {ldq_uop_9_fp_ctrl_vec}, {ldq_uop_8_fp_ctrl_vec}, {ldq_uop_7_fp_ctrl_vec}, {ldq_uop_6_fp_ctrl_vec}, {ldq_uop_5_fp_ctrl_vec}, {ldq_uop_4_fp_ctrl_vec}, {ldq_uop_3_fp_ctrl_vec}, {ldq_uop_2_fp_ctrl_vec}, {ldq_uop_1_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_192[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_193 = {{ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_23_rob_idx}, {ldq_uop_22_rob_idx}, {ldq_uop_21_rob_idx}, {ldq_uop_20_rob_idx}, {ldq_uop_19_rob_idx}, {ldq_uop_18_rob_idx}, {ldq_uop_17_rob_idx}, {ldq_uop_16_rob_idx}, {ldq_uop_15_rob_idx}, {ldq_uop_14_rob_idx}, {ldq_uop_13_rob_idx}, {ldq_uop_12_rob_idx}, {ldq_uop_11_rob_idx}, {ldq_uop_10_rob_idx}, {ldq_uop_9_rob_idx}, {ldq_uop_8_rob_idx}, {ldq_uop_7_rob_idx}, {ldq_uop_6_rob_idx}, {ldq_uop_5_rob_idx}, {ldq_uop_4_rob_idx}, {ldq_uop_3_rob_idx}, {ldq_uop_2_rob_idx}, {ldq_uop_1_rob_idx}, {ldq_uop_0_rob_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rob_idx = _GEN_193[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_194 = {{ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_23_ldq_idx}, {ldq_uop_22_ldq_idx}, {ldq_uop_21_ldq_idx}, {ldq_uop_20_ldq_idx}, {ldq_uop_19_ldq_idx}, {ldq_uop_18_ldq_idx}, {ldq_uop_17_ldq_idx}, {ldq_uop_16_ldq_idx}, {ldq_uop_15_ldq_idx}, {ldq_uop_14_ldq_idx}, {ldq_uop_13_ldq_idx}, {ldq_uop_12_ldq_idx}, {ldq_uop_11_ldq_idx}, {ldq_uop_10_ldq_idx}, {ldq_uop_9_ldq_idx}, {ldq_uop_8_ldq_idx}, {ldq_uop_7_ldq_idx}, {ldq_uop_6_ldq_idx}, {ldq_uop_5_ldq_idx}, {ldq_uop_4_ldq_idx}, {ldq_uop_3_ldq_idx}, {ldq_uop_2_ldq_idx}, {ldq_uop_1_ldq_idx}, {ldq_uop_0_ldq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldq_idx = _GEN_194[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_195 = {{ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_23_stq_idx}, {ldq_uop_22_stq_idx}, {ldq_uop_21_stq_idx}, {ldq_uop_20_stq_idx}, {ldq_uop_19_stq_idx}, {ldq_uop_18_stq_idx}, {ldq_uop_17_stq_idx}, {ldq_uop_16_stq_idx}, {ldq_uop_15_stq_idx}, {ldq_uop_14_stq_idx}, {ldq_uop_13_stq_idx}, {ldq_uop_12_stq_idx}, {ldq_uop_11_stq_idx}, {ldq_uop_10_stq_idx}, {ldq_uop_9_stq_idx}, {ldq_uop_8_stq_idx}, {ldq_uop_7_stq_idx}, {ldq_uop_6_stq_idx}, {ldq_uop_5_stq_idx}, {ldq_uop_4_stq_idx}, {ldq_uop_3_stq_idx}, {ldq_uop_2_stq_idx}, {ldq_uop_1_stq_idx}, {ldq_uop_0_stq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stq_idx = _GEN_195[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_196 = {{ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_23_rxq_idx}, {ldq_uop_22_rxq_idx}, {ldq_uop_21_rxq_idx}, {ldq_uop_20_rxq_idx}, {ldq_uop_19_rxq_idx}, {ldq_uop_18_rxq_idx}, {ldq_uop_17_rxq_idx}, {ldq_uop_16_rxq_idx}, {ldq_uop_15_rxq_idx}, {ldq_uop_14_rxq_idx}, {ldq_uop_13_rxq_idx}, {ldq_uop_12_rxq_idx}, {ldq_uop_11_rxq_idx}, {ldq_uop_10_rxq_idx}, {ldq_uop_9_rxq_idx}, {ldq_uop_8_rxq_idx}, {ldq_uop_7_rxq_idx}, {ldq_uop_6_rxq_idx}, {ldq_uop_5_rxq_idx}, {ldq_uop_4_rxq_idx}, {ldq_uop_3_rxq_idx}, {ldq_uop_2_rxq_idx}, {ldq_uop_1_rxq_idx}, {ldq_uop_0_rxq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rxq_idx = _GEN_196[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_197 = {{ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_23_pdst}, {ldq_uop_22_pdst}, {ldq_uop_21_pdst}, {ldq_uop_20_pdst}, {ldq_uop_19_pdst}, {ldq_uop_18_pdst}, {ldq_uop_17_pdst}, {ldq_uop_16_pdst}, {ldq_uop_15_pdst}, {ldq_uop_14_pdst}, {ldq_uop_13_pdst}, {ldq_uop_12_pdst}, {ldq_uop_11_pdst}, {ldq_uop_10_pdst}, {ldq_uop_9_pdst}, {ldq_uop_8_pdst}, {ldq_uop_7_pdst}, {ldq_uop_6_pdst}, {ldq_uop_5_pdst}, {ldq_uop_4_pdst}, {ldq_uop_3_pdst}, {ldq_uop_2_pdst}, {ldq_uop_1_pdst}, {ldq_uop_0_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pdst = _GEN_197[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_198 = {{ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_23_prs1}, {ldq_uop_22_prs1}, {ldq_uop_21_prs1}, {ldq_uop_20_prs1}, {ldq_uop_19_prs1}, {ldq_uop_18_prs1}, {ldq_uop_17_prs1}, {ldq_uop_16_prs1}, {ldq_uop_15_prs1}, {ldq_uop_14_prs1}, {ldq_uop_13_prs1}, {ldq_uop_12_prs1}, {ldq_uop_11_prs1}, {ldq_uop_10_prs1}, {ldq_uop_9_prs1}, {ldq_uop_8_prs1}, {ldq_uop_7_prs1}, {ldq_uop_6_prs1}, {ldq_uop_5_prs1}, {ldq_uop_4_prs1}, {ldq_uop_3_prs1}, {ldq_uop_2_prs1}, {ldq_uop_1_prs1}, {ldq_uop_0_prs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1 = _GEN_198[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_199 = {{ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_23_prs2}, {ldq_uop_22_prs2}, {ldq_uop_21_prs2}, {ldq_uop_20_prs2}, {ldq_uop_19_prs2}, {ldq_uop_18_prs2}, {ldq_uop_17_prs2}, {ldq_uop_16_prs2}, {ldq_uop_15_prs2}, {ldq_uop_14_prs2}, {ldq_uop_13_prs2}, {ldq_uop_12_prs2}, {ldq_uop_11_prs2}, {ldq_uop_10_prs2}, {ldq_uop_9_prs2}, {ldq_uop_8_prs2}, {ldq_uop_7_prs2}, {ldq_uop_6_prs2}, {ldq_uop_5_prs2}, {ldq_uop_4_prs2}, {ldq_uop_3_prs2}, {ldq_uop_2_prs2}, {ldq_uop_1_prs2}, {ldq_uop_0_prs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2 = _GEN_199[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_200 = {{ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_23_prs3}, {ldq_uop_22_prs3}, {ldq_uop_21_prs3}, {ldq_uop_20_prs3}, {ldq_uop_19_prs3}, {ldq_uop_18_prs3}, {ldq_uop_17_prs3}, {ldq_uop_16_prs3}, {ldq_uop_15_prs3}, {ldq_uop_14_prs3}, {ldq_uop_13_prs3}, {ldq_uop_12_prs3}, {ldq_uop_11_prs3}, {ldq_uop_10_prs3}, {ldq_uop_9_prs3}, {ldq_uop_8_prs3}, {ldq_uop_7_prs3}, {ldq_uop_6_prs3}, {ldq_uop_5_prs3}, {ldq_uop_4_prs3}, {ldq_uop_3_prs3}, {ldq_uop_2_prs3}, {ldq_uop_1_prs3}, {ldq_uop_0_prs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3 = _GEN_200[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_201 = {{ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_23_ppred}, {ldq_uop_22_ppred}, {ldq_uop_21_ppred}, {ldq_uop_20_ppred}, {ldq_uop_19_ppred}, {ldq_uop_18_ppred}, {ldq_uop_17_ppred}, {ldq_uop_16_ppred}, {ldq_uop_15_ppred}, {ldq_uop_14_ppred}, {ldq_uop_13_ppred}, {ldq_uop_12_ppred}, {ldq_uop_11_ppred}, {ldq_uop_10_ppred}, {ldq_uop_9_ppred}, {ldq_uop_8_ppred}, {ldq_uop_7_ppred}, {ldq_uop_6_ppred}, {ldq_uop_5_ppred}, {ldq_uop_4_ppred}, {ldq_uop_3_ppred}, {ldq_uop_2_ppred}, {ldq_uop_1_ppred}, {ldq_uop_0_ppred}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred = _GEN_201[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_202 = {{ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_23_prs1_busy}, {ldq_uop_22_prs1_busy}, {ldq_uop_21_prs1_busy}, {ldq_uop_20_prs1_busy}, {ldq_uop_19_prs1_busy}, {ldq_uop_18_prs1_busy}, {ldq_uop_17_prs1_busy}, {ldq_uop_16_prs1_busy}, {ldq_uop_15_prs1_busy}, {ldq_uop_14_prs1_busy}, {ldq_uop_13_prs1_busy}, {ldq_uop_12_prs1_busy}, {ldq_uop_11_prs1_busy}, {ldq_uop_10_prs1_busy}, {ldq_uop_9_prs1_busy}, {ldq_uop_8_prs1_busy}, {ldq_uop_7_prs1_busy}, {ldq_uop_6_prs1_busy}, {ldq_uop_5_prs1_busy}, {ldq_uop_4_prs1_busy}, {ldq_uop_3_prs1_busy}, {ldq_uop_2_prs1_busy}, {ldq_uop_1_prs1_busy}, {ldq_uop_0_prs1_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1_busy = _GEN_202[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_203 = {{ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_23_prs2_busy}, {ldq_uop_22_prs2_busy}, {ldq_uop_21_prs2_busy}, {ldq_uop_20_prs2_busy}, {ldq_uop_19_prs2_busy}, {ldq_uop_18_prs2_busy}, {ldq_uop_17_prs2_busy}, {ldq_uop_16_prs2_busy}, {ldq_uop_15_prs2_busy}, {ldq_uop_14_prs2_busy}, {ldq_uop_13_prs2_busy}, {ldq_uop_12_prs2_busy}, {ldq_uop_11_prs2_busy}, {ldq_uop_10_prs2_busy}, {ldq_uop_9_prs2_busy}, {ldq_uop_8_prs2_busy}, {ldq_uop_7_prs2_busy}, {ldq_uop_6_prs2_busy}, {ldq_uop_5_prs2_busy}, {ldq_uop_4_prs2_busy}, {ldq_uop_3_prs2_busy}, {ldq_uop_2_prs2_busy}, {ldq_uop_1_prs2_busy}, {ldq_uop_0_prs2_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2_busy = _GEN_203[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_204 = {{ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_23_prs3_busy}, {ldq_uop_22_prs3_busy}, {ldq_uop_21_prs3_busy}, {ldq_uop_20_prs3_busy}, {ldq_uop_19_prs3_busy}, {ldq_uop_18_prs3_busy}, {ldq_uop_17_prs3_busy}, {ldq_uop_16_prs3_busy}, {ldq_uop_15_prs3_busy}, {ldq_uop_14_prs3_busy}, {ldq_uop_13_prs3_busy}, {ldq_uop_12_prs3_busy}, {ldq_uop_11_prs3_busy}, {ldq_uop_10_prs3_busy}, {ldq_uop_9_prs3_busy}, {ldq_uop_8_prs3_busy}, {ldq_uop_7_prs3_busy}, {ldq_uop_6_prs3_busy}, {ldq_uop_5_prs3_busy}, {ldq_uop_4_prs3_busy}, {ldq_uop_3_prs3_busy}, {ldq_uop_2_prs3_busy}, {ldq_uop_1_prs3_busy}, {ldq_uop_0_prs3_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3_busy = _GEN_204[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_205 = {{ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_23_ppred_busy}, {ldq_uop_22_ppred_busy}, {ldq_uop_21_ppred_busy}, {ldq_uop_20_ppred_busy}, {ldq_uop_19_ppred_busy}, {ldq_uop_18_ppred_busy}, {ldq_uop_17_ppred_busy}, {ldq_uop_16_ppred_busy}, {ldq_uop_15_ppred_busy}, {ldq_uop_14_ppred_busy}, {ldq_uop_13_ppred_busy}, {ldq_uop_12_ppred_busy}, {ldq_uop_11_ppred_busy}, {ldq_uop_10_ppred_busy}, {ldq_uop_9_ppred_busy}, {ldq_uop_8_ppred_busy}, {ldq_uop_7_ppred_busy}, {ldq_uop_6_ppred_busy}, {ldq_uop_5_ppred_busy}, {ldq_uop_4_ppred_busy}, {ldq_uop_3_ppred_busy}, {ldq_uop_2_ppred_busy}, {ldq_uop_1_ppred_busy}, {ldq_uop_0_ppred_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred_busy = _GEN_205[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_206 = {{ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_23_stale_pdst}, {ldq_uop_22_stale_pdst}, {ldq_uop_21_stale_pdst}, {ldq_uop_20_stale_pdst}, {ldq_uop_19_stale_pdst}, {ldq_uop_18_stale_pdst}, {ldq_uop_17_stale_pdst}, {ldq_uop_16_stale_pdst}, {ldq_uop_15_stale_pdst}, {ldq_uop_14_stale_pdst}, {ldq_uop_13_stale_pdst}, {ldq_uop_12_stale_pdst}, {ldq_uop_11_stale_pdst}, {ldq_uop_10_stale_pdst}, {ldq_uop_9_stale_pdst}, {ldq_uop_8_stale_pdst}, {ldq_uop_7_stale_pdst}, {ldq_uop_6_stale_pdst}, {ldq_uop_5_stale_pdst}, {ldq_uop_4_stale_pdst}, {ldq_uop_3_stale_pdst}, {ldq_uop_2_stale_pdst}, {ldq_uop_1_stale_pdst}, {ldq_uop_0_stale_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stale_pdst = _GEN_206[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_207 = {{ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_23_exception}, {ldq_uop_22_exception}, {ldq_uop_21_exception}, {ldq_uop_20_exception}, {ldq_uop_19_exception}, {ldq_uop_18_exception}, {ldq_uop_17_exception}, {ldq_uop_16_exception}, {ldq_uop_15_exception}, {ldq_uop_14_exception}, {ldq_uop_13_exception}, {ldq_uop_12_exception}, {ldq_uop_11_exception}, {ldq_uop_10_exception}, {ldq_uop_9_exception}, {ldq_uop_8_exception}, {ldq_uop_7_exception}, {ldq_uop_6_exception}, {ldq_uop_5_exception}, {ldq_uop_4_exception}, {ldq_uop_3_exception}, {ldq_uop_2_exception}, {ldq_uop_1_exception}, {ldq_uop_0_exception}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exception = _GEN_207[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][63:0] _GEN_208 = {{ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_23_exc_cause}, {ldq_uop_22_exc_cause}, {ldq_uop_21_exc_cause}, {ldq_uop_20_exc_cause}, {ldq_uop_19_exc_cause}, {ldq_uop_18_exc_cause}, {ldq_uop_17_exc_cause}, {ldq_uop_16_exc_cause}, {ldq_uop_15_exc_cause}, {ldq_uop_14_exc_cause}, {ldq_uop_13_exc_cause}, {ldq_uop_12_exc_cause}, {ldq_uop_11_exc_cause}, {ldq_uop_10_exc_cause}, {ldq_uop_9_exc_cause}, {ldq_uop_8_exc_cause}, {ldq_uop_7_exc_cause}, {ldq_uop_6_exc_cause}, {ldq_uop_5_exc_cause}, {ldq_uop_4_exc_cause}, {ldq_uop_3_exc_cause}, {ldq_uop_2_exc_cause}, {ldq_uop_1_exc_cause}, {ldq_uop_0_exc_cause}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exc_cause = _GEN_208[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_209 = {{ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_23_mem_cmd}, {ldq_uop_22_mem_cmd}, {ldq_uop_21_mem_cmd}, {ldq_uop_20_mem_cmd}, {ldq_uop_19_mem_cmd}, {ldq_uop_18_mem_cmd}, {ldq_uop_17_mem_cmd}, {ldq_uop_16_mem_cmd}, {ldq_uop_15_mem_cmd}, {ldq_uop_14_mem_cmd}, {ldq_uop_13_mem_cmd}, {ldq_uop_12_mem_cmd}, {ldq_uop_11_mem_cmd}, {ldq_uop_10_mem_cmd}, {ldq_uop_9_mem_cmd}, {ldq_uop_8_mem_cmd}, {ldq_uop_7_mem_cmd}, {ldq_uop_6_mem_cmd}, {ldq_uop_5_mem_cmd}, {ldq_uop_4_mem_cmd}, {ldq_uop_3_mem_cmd}, {ldq_uop_2_mem_cmd}, {ldq_uop_1_mem_cmd}, {ldq_uop_0_mem_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_cmd = _GEN_209[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_210 = {{ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_23_mem_size}, {ldq_uop_22_mem_size}, {ldq_uop_21_mem_size}, {ldq_uop_20_mem_size}, {ldq_uop_19_mem_size}, {ldq_uop_18_mem_size}, {ldq_uop_17_mem_size}, {ldq_uop_16_mem_size}, {ldq_uop_15_mem_size}, {ldq_uop_14_mem_size}, {ldq_uop_13_mem_size}, {ldq_uop_12_mem_size}, {ldq_uop_11_mem_size}, {ldq_uop_10_mem_size}, {ldq_uop_9_mem_size}, {ldq_uop_8_mem_size}, {ldq_uop_7_mem_size}, {ldq_uop_6_mem_size}, {ldq_uop_5_mem_size}, {ldq_uop_4_mem_size}, {ldq_uop_3_mem_size}, {ldq_uop_2_mem_size}, {ldq_uop_1_mem_size}, {ldq_uop_0_mem_size}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_size = _GEN_210[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_211 = {{ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_23_mem_signed}, {ldq_uop_22_mem_signed}, {ldq_uop_21_mem_signed}, {ldq_uop_20_mem_signed}, {ldq_uop_19_mem_signed}, {ldq_uop_18_mem_signed}, {ldq_uop_17_mem_signed}, {ldq_uop_16_mem_signed}, {ldq_uop_15_mem_signed}, {ldq_uop_14_mem_signed}, {ldq_uop_13_mem_signed}, {ldq_uop_12_mem_signed}, {ldq_uop_11_mem_signed}, {ldq_uop_10_mem_signed}, {ldq_uop_9_mem_signed}, {ldq_uop_8_mem_signed}, {ldq_uop_7_mem_signed}, {ldq_uop_6_mem_signed}, {ldq_uop_5_mem_signed}, {ldq_uop_4_mem_signed}, {ldq_uop_3_mem_signed}, {ldq_uop_2_mem_signed}, {ldq_uop_1_mem_signed}, {ldq_uop_0_mem_signed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_signed = _GEN_211[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_212 = {{ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_23_uses_ldq}, {ldq_uop_22_uses_ldq}, {ldq_uop_21_uses_ldq}, {ldq_uop_20_uses_ldq}, {ldq_uop_19_uses_ldq}, {ldq_uop_18_uses_ldq}, {ldq_uop_17_uses_ldq}, {ldq_uop_16_uses_ldq}, {ldq_uop_15_uses_ldq}, {ldq_uop_14_uses_ldq}, {ldq_uop_13_uses_ldq}, {ldq_uop_12_uses_ldq}, {ldq_uop_11_uses_ldq}, {ldq_uop_10_uses_ldq}, {ldq_uop_9_uses_ldq}, {ldq_uop_8_uses_ldq}, {ldq_uop_7_uses_ldq}, {ldq_uop_6_uses_ldq}, {ldq_uop_5_uses_ldq}, {ldq_uop_4_uses_ldq}, {ldq_uop_3_uses_ldq}, {ldq_uop_2_uses_ldq}, {ldq_uop_1_uses_ldq}, {ldq_uop_0_uses_ldq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_ldq = _GEN_212[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_213 = {{ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_23_uses_stq}, {ldq_uop_22_uses_stq}, {ldq_uop_21_uses_stq}, {ldq_uop_20_uses_stq}, {ldq_uop_19_uses_stq}, {ldq_uop_18_uses_stq}, {ldq_uop_17_uses_stq}, {ldq_uop_16_uses_stq}, {ldq_uop_15_uses_stq}, {ldq_uop_14_uses_stq}, {ldq_uop_13_uses_stq}, {ldq_uop_12_uses_stq}, {ldq_uop_11_uses_stq}, {ldq_uop_10_uses_stq}, {ldq_uop_9_uses_stq}, {ldq_uop_8_uses_stq}, {ldq_uop_7_uses_stq}, {ldq_uop_6_uses_stq}, {ldq_uop_5_uses_stq}, {ldq_uop_4_uses_stq}, {ldq_uop_3_uses_stq}, {ldq_uop_2_uses_stq}, {ldq_uop_1_uses_stq}, {ldq_uop_0_uses_stq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_stq = _GEN_213[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_214 = {{ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_23_is_unique}, {ldq_uop_22_is_unique}, {ldq_uop_21_is_unique}, {ldq_uop_20_is_unique}, {ldq_uop_19_is_unique}, {ldq_uop_18_is_unique}, {ldq_uop_17_is_unique}, {ldq_uop_16_is_unique}, {ldq_uop_15_is_unique}, {ldq_uop_14_is_unique}, {ldq_uop_13_is_unique}, {ldq_uop_12_is_unique}, {ldq_uop_11_is_unique}, {ldq_uop_10_is_unique}, {ldq_uop_9_is_unique}, {ldq_uop_8_is_unique}, {ldq_uop_7_is_unique}, {ldq_uop_6_is_unique}, {ldq_uop_5_is_unique}, {ldq_uop_4_is_unique}, {ldq_uop_3_is_unique}, {ldq_uop_2_is_unique}, {ldq_uop_1_is_unique}, {ldq_uop_0_is_unique}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_unique = _GEN_214[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_215 = {{ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_23_flush_on_commit}, {ldq_uop_22_flush_on_commit}, {ldq_uop_21_flush_on_commit}, {ldq_uop_20_flush_on_commit}, {ldq_uop_19_flush_on_commit}, {ldq_uop_18_flush_on_commit}, {ldq_uop_17_flush_on_commit}, {ldq_uop_16_flush_on_commit}, {ldq_uop_15_flush_on_commit}, {ldq_uop_14_flush_on_commit}, {ldq_uop_13_flush_on_commit}, {ldq_uop_12_flush_on_commit}, {ldq_uop_11_flush_on_commit}, {ldq_uop_10_flush_on_commit}, {ldq_uop_9_flush_on_commit}, {ldq_uop_8_flush_on_commit}, {ldq_uop_7_flush_on_commit}, {ldq_uop_6_flush_on_commit}, {ldq_uop_5_flush_on_commit}, {ldq_uop_4_flush_on_commit}, {ldq_uop_3_flush_on_commit}, {ldq_uop_2_flush_on_commit}, {ldq_uop_1_flush_on_commit}, {ldq_uop_0_flush_on_commit}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_flush_on_commit = _GEN_215[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_216 = {{ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_23_csr_cmd}, {ldq_uop_22_csr_cmd}, {ldq_uop_21_csr_cmd}, {ldq_uop_20_csr_cmd}, {ldq_uop_19_csr_cmd}, {ldq_uop_18_csr_cmd}, {ldq_uop_17_csr_cmd}, {ldq_uop_16_csr_cmd}, {ldq_uop_15_csr_cmd}, {ldq_uop_14_csr_cmd}, {ldq_uop_13_csr_cmd}, {ldq_uop_12_csr_cmd}, {ldq_uop_11_csr_cmd}, {ldq_uop_10_csr_cmd}, {ldq_uop_9_csr_cmd}, {ldq_uop_8_csr_cmd}, {ldq_uop_7_csr_cmd}, {ldq_uop_6_csr_cmd}, {ldq_uop_5_csr_cmd}, {ldq_uop_4_csr_cmd}, {ldq_uop_3_csr_cmd}, {ldq_uop_2_csr_cmd}, {ldq_uop_1_csr_cmd}, {ldq_uop_0_csr_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_csr_cmd = _GEN_216[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_217 = {{ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_23_ldst_is_rs1}, {ldq_uop_22_ldst_is_rs1}, {ldq_uop_21_ldst_is_rs1}, {ldq_uop_20_ldst_is_rs1}, {ldq_uop_19_ldst_is_rs1}, {ldq_uop_18_ldst_is_rs1}, {ldq_uop_17_ldst_is_rs1}, {ldq_uop_16_ldst_is_rs1}, {ldq_uop_15_ldst_is_rs1}, {ldq_uop_14_ldst_is_rs1}, {ldq_uop_13_ldst_is_rs1}, {ldq_uop_12_ldst_is_rs1}, {ldq_uop_11_ldst_is_rs1}, {ldq_uop_10_ldst_is_rs1}, {ldq_uop_9_ldst_is_rs1}, {ldq_uop_8_ldst_is_rs1}, {ldq_uop_7_ldst_is_rs1}, {ldq_uop_6_ldst_is_rs1}, {ldq_uop_5_ldst_is_rs1}, {ldq_uop_4_ldst_is_rs1}, {ldq_uop_3_ldst_is_rs1}, {ldq_uop_2_ldst_is_rs1}, {ldq_uop_1_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_217[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_218 = {{ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_23_ldst}, {ldq_uop_22_ldst}, {ldq_uop_21_ldst}, {ldq_uop_20_ldst}, {ldq_uop_19_ldst}, {ldq_uop_18_ldst}, {ldq_uop_17_ldst}, {ldq_uop_16_ldst}, {ldq_uop_15_ldst}, {ldq_uop_14_ldst}, {ldq_uop_13_ldst}, {ldq_uop_12_ldst}, {ldq_uop_11_ldst}, {ldq_uop_10_ldst}, {ldq_uop_9_ldst}, {ldq_uop_8_ldst}, {ldq_uop_7_ldst}, {ldq_uop_6_ldst}, {ldq_uop_5_ldst}, {ldq_uop_4_ldst}, {ldq_uop_3_ldst}, {ldq_uop_2_ldst}, {ldq_uop_1_ldst}, {ldq_uop_0_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst = _GEN_218[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_219 = {{ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_23_lrs1}, {ldq_uop_22_lrs1}, {ldq_uop_21_lrs1}, {ldq_uop_20_lrs1}, {ldq_uop_19_lrs1}, {ldq_uop_18_lrs1}, {ldq_uop_17_lrs1}, {ldq_uop_16_lrs1}, {ldq_uop_15_lrs1}, {ldq_uop_14_lrs1}, {ldq_uop_13_lrs1}, {ldq_uop_12_lrs1}, {ldq_uop_11_lrs1}, {ldq_uop_10_lrs1}, {ldq_uop_9_lrs1}, {ldq_uop_8_lrs1}, {ldq_uop_7_lrs1}, {ldq_uop_6_lrs1}, {ldq_uop_5_lrs1}, {ldq_uop_4_lrs1}, {ldq_uop_3_lrs1}, {ldq_uop_2_lrs1}, {ldq_uop_1_lrs1}, {ldq_uop_0_lrs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1 = _GEN_219[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_220 = {{ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_23_lrs2}, {ldq_uop_22_lrs2}, {ldq_uop_21_lrs2}, {ldq_uop_20_lrs2}, {ldq_uop_19_lrs2}, {ldq_uop_18_lrs2}, {ldq_uop_17_lrs2}, {ldq_uop_16_lrs2}, {ldq_uop_15_lrs2}, {ldq_uop_14_lrs2}, {ldq_uop_13_lrs2}, {ldq_uop_12_lrs2}, {ldq_uop_11_lrs2}, {ldq_uop_10_lrs2}, {ldq_uop_9_lrs2}, {ldq_uop_8_lrs2}, {ldq_uop_7_lrs2}, {ldq_uop_6_lrs2}, {ldq_uop_5_lrs2}, {ldq_uop_4_lrs2}, {ldq_uop_3_lrs2}, {ldq_uop_2_lrs2}, {ldq_uop_1_lrs2}, {ldq_uop_0_lrs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2 = _GEN_220[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_221 = {{ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_23_lrs3}, {ldq_uop_22_lrs3}, {ldq_uop_21_lrs3}, {ldq_uop_20_lrs3}, {ldq_uop_19_lrs3}, {ldq_uop_18_lrs3}, {ldq_uop_17_lrs3}, {ldq_uop_16_lrs3}, {ldq_uop_15_lrs3}, {ldq_uop_14_lrs3}, {ldq_uop_13_lrs3}, {ldq_uop_12_lrs3}, {ldq_uop_11_lrs3}, {ldq_uop_10_lrs3}, {ldq_uop_9_lrs3}, {ldq_uop_8_lrs3}, {ldq_uop_7_lrs3}, {ldq_uop_6_lrs3}, {ldq_uop_5_lrs3}, {ldq_uop_4_lrs3}, {ldq_uop_3_lrs3}, {ldq_uop_2_lrs3}, {ldq_uop_1_lrs3}, {ldq_uop_0_lrs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs3 = _GEN_221[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_222 = {{ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_23_dst_rtype}, {ldq_uop_22_dst_rtype}, {ldq_uop_21_dst_rtype}, {ldq_uop_20_dst_rtype}, {ldq_uop_19_dst_rtype}, {ldq_uop_18_dst_rtype}, {ldq_uop_17_dst_rtype}, {ldq_uop_16_dst_rtype}, {ldq_uop_15_dst_rtype}, {ldq_uop_14_dst_rtype}, {ldq_uop_13_dst_rtype}, {ldq_uop_12_dst_rtype}, {ldq_uop_11_dst_rtype}, {ldq_uop_10_dst_rtype}, {ldq_uop_9_dst_rtype}, {ldq_uop_8_dst_rtype}, {ldq_uop_7_dst_rtype}, {ldq_uop_6_dst_rtype}, {ldq_uop_5_dst_rtype}, {ldq_uop_4_dst_rtype}, {ldq_uop_3_dst_rtype}, {ldq_uop_2_dst_rtype}, {ldq_uop_1_dst_rtype}, {ldq_uop_0_dst_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dst_rtype = _GEN_222[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_223 = {{ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_23_lrs1_rtype}, {ldq_uop_22_lrs1_rtype}, {ldq_uop_21_lrs1_rtype}, {ldq_uop_20_lrs1_rtype}, {ldq_uop_19_lrs1_rtype}, {ldq_uop_18_lrs1_rtype}, {ldq_uop_17_lrs1_rtype}, {ldq_uop_16_lrs1_rtype}, {ldq_uop_15_lrs1_rtype}, {ldq_uop_14_lrs1_rtype}, {ldq_uop_13_lrs1_rtype}, {ldq_uop_12_lrs1_rtype}, {ldq_uop_11_lrs1_rtype}, {ldq_uop_10_lrs1_rtype}, {ldq_uop_9_lrs1_rtype}, {ldq_uop_8_lrs1_rtype}, {ldq_uop_7_lrs1_rtype}, {ldq_uop_6_lrs1_rtype}, {ldq_uop_5_lrs1_rtype}, {ldq_uop_4_lrs1_rtype}, {ldq_uop_3_lrs1_rtype}, {ldq_uop_2_lrs1_rtype}, {ldq_uop_1_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_223[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_224 = {{ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_23_lrs2_rtype}, {ldq_uop_22_lrs2_rtype}, {ldq_uop_21_lrs2_rtype}, {ldq_uop_20_lrs2_rtype}, {ldq_uop_19_lrs2_rtype}, {ldq_uop_18_lrs2_rtype}, {ldq_uop_17_lrs2_rtype}, {ldq_uop_16_lrs2_rtype}, {ldq_uop_15_lrs2_rtype}, {ldq_uop_14_lrs2_rtype}, {ldq_uop_13_lrs2_rtype}, {ldq_uop_12_lrs2_rtype}, {ldq_uop_11_lrs2_rtype}, {ldq_uop_10_lrs2_rtype}, {ldq_uop_9_lrs2_rtype}, {ldq_uop_8_lrs2_rtype}, {ldq_uop_7_lrs2_rtype}, {ldq_uop_6_lrs2_rtype}, {ldq_uop_5_lrs2_rtype}, {ldq_uop_4_lrs2_rtype}, {ldq_uop_3_lrs2_rtype}, {ldq_uop_2_lrs2_rtype}, {ldq_uop_1_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_224[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_225 = {{ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_23_frs3_en}, {ldq_uop_22_frs3_en}, {ldq_uop_21_frs3_en}, {ldq_uop_20_frs3_en}, {ldq_uop_19_frs3_en}, {ldq_uop_18_frs3_en}, {ldq_uop_17_frs3_en}, {ldq_uop_16_frs3_en}, {ldq_uop_15_frs3_en}, {ldq_uop_14_frs3_en}, {ldq_uop_13_frs3_en}, {ldq_uop_12_frs3_en}, {ldq_uop_11_frs3_en}, {ldq_uop_10_frs3_en}, {ldq_uop_9_frs3_en}, {ldq_uop_8_frs3_en}, {ldq_uop_7_frs3_en}, {ldq_uop_6_frs3_en}, {ldq_uop_5_frs3_en}, {ldq_uop_4_frs3_en}, {ldq_uop_3_frs3_en}, {ldq_uop_2_frs3_en}, {ldq_uop_1_frs3_en}, {ldq_uop_0_frs3_en}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_frs3_en = _GEN_225[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_226 = {{ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_23_fcn_dw}, {ldq_uop_22_fcn_dw}, {ldq_uop_21_fcn_dw}, {ldq_uop_20_fcn_dw}, {ldq_uop_19_fcn_dw}, {ldq_uop_18_fcn_dw}, {ldq_uop_17_fcn_dw}, {ldq_uop_16_fcn_dw}, {ldq_uop_15_fcn_dw}, {ldq_uop_14_fcn_dw}, {ldq_uop_13_fcn_dw}, {ldq_uop_12_fcn_dw}, {ldq_uop_11_fcn_dw}, {ldq_uop_10_fcn_dw}, {ldq_uop_9_fcn_dw}, {ldq_uop_8_fcn_dw}, {ldq_uop_7_fcn_dw}, {ldq_uop_6_fcn_dw}, {ldq_uop_5_fcn_dw}, {ldq_uop_4_fcn_dw}, {ldq_uop_3_fcn_dw}, {ldq_uop_2_fcn_dw}, {ldq_uop_1_fcn_dw}, {ldq_uop_0_fcn_dw}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_dw = _GEN_226[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_227 = {{ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_23_fcn_op}, {ldq_uop_22_fcn_op}, {ldq_uop_21_fcn_op}, {ldq_uop_20_fcn_op}, {ldq_uop_19_fcn_op}, {ldq_uop_18_fcn_op}, {ldq_uop_17_fcn_op}, {ldq_uop_16_fcn_op}, {ldq_uop_15_fcn_op}, {ldq_uop_14_fcn_op}, {ldq_uop_13_fcn_op}, {ldq_uop_12_fcn_op}, {ldq_uop_11_fcn_op}, {ldq_uop_10_fcn_op}, {ldq_uop_9_fcn_op}, {ldq_uop_8_fcn_op}, {ldq_uop_7_fcn_op}, {ldq_uop_6_fcn_op}, {ldq_uop_5_fcn_op}, {ldq_uop_4_fcn_op}, {ldq_uop_3_fcn_op}, {ldq_uop_2_fcn_op}, {ldq_uop_1_fcn_op}, {ldq_uop_0_fcn_op}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_op = _GEN_227[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_228 = {{ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_23_fp_val}, {ldq_uop_22_fp_val}, {ldq_uop_21_fp_val}, {ldq_uop_20_fp_val}, {ldq_uop_19_fp_val}, {ldq_uop_18_fp_val}, {ldq_uop_17_fp_val}, {ldq_uop_16_fp_val}, {ldq_uop_15_fp_val}, {ldq_uop_14_fp_val}, {ldq_uop_13_fp_val}, {ldq_uop_12_fp_val}, {ldq_uop_11_fp_val}, {ldq_uop_10_fp_val}, {ldq_uop_9_fp_val}, {ldq_uop_8_fp_val}, {ldq_uop_7_fp_val}, {ldq_uop_6_fp_val}, {ldq_uop_5_fp_val}, {ldq_uop_4_fp_val}, {ldq_uop_3_fp_val}, {ldq_uop_2_fp_val}, {ldq_uop_1_fp_val}, {ldq_uop_0_fp_val}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_val = _GEN_228[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_229 = {{ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_23_fp_rm}, {ldq_uop_22_fp_rm}, {ldq_uop_21_fp_rm}, {ldq_uop_20_fp_rm}, {ldq_uop_19_fp_rm}, {ldq_uop_18_fp_rm}, {ldq_uop_17_fp_rm}, {ldq_uop_16_fp_rm}, {ldq_uop_15_fp_rm}, {ldq_uop_14_fp_rm}, {ldq_uop_13_fp_rm}, {ldq_uop_12_fp_rm}, {ldq_uop_11_fp_rm}, {ldq_uop_10_fp_rm}, {ldq_uop_9_fp_rm}, {ldq_uop_8_fp_rm}, {ldq_uop_7_fp_rm}, {ldq_uop_6_fp_rm}, {ldq_uop_5_fp_rm}, {ldq_uop_4_fp_rm}, {ldq_uop_3_fp_rm}, {ldq_uop_2_fp_rm}, {ldq_uop_1_fp_rm}, {ldq_uop_0_fp_rm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_rm = _GEN_229[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_230 = {{ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_23_fp_typ}, {ldq_uop_22_fp_typ}, {ldq_uop_21_fp_typ}, {ldq_uop_20_fp_typ}, {ldq_uop_19_fp_typ}, {ldq_uop_18_fp_typ}, {ldq_uop_17_fp_typ}, {ldq_uop_16_fp_typ}, {ldq_uop_15_fp_typ}, {ldq_uop_14_fp_typ}, {ldq_uop_13_fp_typ}, {ldq_uop_12_fp_typ}, {ldq_uop_11_fp_typ}, {ldq_uop_10_fp_typ}, {ldq_uop_9_fp_typ}, {ldq_uop_8_fp_typ}, {ldq_uop_7_fp_typ}, {ldq_uop_6_fp_typ}, {ldq_uop_5_fp_typ}, {ldq_uop_4_fp_typ}, {ldq_uop_3_fp_typ}, {ldq_uop_2_fp_typ}, {ldq_uop_1_fp_typ}, {ldq_uop_0_fp_typ}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_typ = _GEN_230[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_231 = {{ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_23_xcpt_pf_if}, {ldq_uop_22_xcpt_pf_if}, {ldq_uop_21_xcpt_pf_if}, {ldq_uop_20_xcpt_pf_if}, {ldq_uop_19_xcpt_pf_if}, {ldq_uop_18_xcpt_pf_if}, {ldq_uop_17_xcpt_pf_if}, {ldq_uop_16_xcpt_pf_if}, {ldq_uop_15_xcpt_pf_if}, {ldq_uop_14_xcpt_pf_if}, {ldq_uop_13_xcpt_pf_if}, {ldq_uop_12_xcpt_pf_if}, {ldq_uop_11_xcpt_pf_if}, {ldq_uop_10_xcpt_pf_if}, {ldq_uop_9_xcpt_pf_if}, {ldq_uop_8_xcpt_pf_if}, {ldq_uop_7_xcpt_pf_if}, {ldq_uop_6_xcpt_pf_if}, {ldq_uop_5_xcpt_pf_if}, {ldq_uop_4_xcpt_pf_if}, {ldq_uop_3_xcpt_pf_if}, {ldq_uop_2_xcpt_pf_if}, {ldq_uop_1_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_231[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_232 = {{ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_23_xcpt_ae_if}, {ldq_uop_22_xcpt_ae_if}, {ldq_uop_21_xcpt_ae_if}, {ldq_uop_20_xcpt_ae_if}, {ldq_uop_19_xcpt_ae_if}, {ldq_uop_18_xcpt_ae_if}, {ldq_uop_17_xcpt_ae_if}, {ldq_uop_16_xcpt_ae_if}, {ldq_uop_15_xcpt_ae_if}, {ldq_uop_14_xcpt_ae_if}, {ldq_uop_13_xcpt_ae_if}, {ldq_uop_12_xcpt_ae_if}, {ldq_uop_11_xcpt_ae_if}, {ldq_uop_10_xcpt_ae_if}, {ldq_uop_9_xcpt_ae_if}, {ldq_uop_8_xcpt_ae_if}, {ldq_uop_7_xcpt_ae_if}, {ldq_uop_6_xcpt_ae_if}, {ldq_uop_5_xcpt_ae_if}, {ldq_uop_4_xcpt_ae_if}, {ldq_uop_3_xcpt_ae_if}, {ldq_uop_2_xcpt_ae_if}, {ldq_uop_1_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_232[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_233 = {{ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_23_xcpt_ma_if}, {ldq_uop_22_xcpt_ma_if}, {ldq_uop_21_xcpt_ma_if}, {ldq_uop_20_xcpt_ma_if}, {ldq_uop_19_xcpt_ma_if}, {ldq_uop_18_xcpt_ma_if}, {ldq_uop_17_xcpt_ma_if}, {ldq_uop_16_xcpt_ma_if}, {ldq_uop_15_xcpt_ma_if}, {ldq_uop_14_xcpt_ma_if}, {ldq_uop_13_xcpt_ma_if}, {ldq_uop_12_xcpt_ma_if}, {ldq_uop_11_xcpt_ma_if}, {ldq_uop_10_xcpt_ma_if}, {ldq_uop_9_xcpt_ma_if}, {ldq_uop_8_xcpt_ma_if}, {ldq_uop_7_xcpt_ma_if}, {ldq_uop_6_xcpt_ma_if}, {ldq_uop_5_xcpt_ma_if}, {ldq_uop_4_xcpt_ma_if}, {ldq_uop_3_xcpt_ma_if}, {ldq_uop_2_xcpt_ma_if}, {ldq_uop_1_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_233[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_234 = {{ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_23_bp_debug_if}, {ldq_uop_22_bp_debug_if}, {ldq_uop_21_bp_debug_if}, {ldq_uop_20_bp_debug_if}, {ldq_uop_19_bp_debug_if}, {ldq_uop_18_bp_debug_if}, {ldq_uop_17_bp_debug_if}, {ldq_uop_16_bp_debug_if}, {ldq_uop_15_bp_debug_if}, {ldq_uop_14_bp_debug_if}, {ldq_uop_13_bp_debug_if}, {ldq_uop_12_bp_debug_if}, {ldq_uop_11_bp_debug_if}, {ldq_uop_10_bp_debug_if}, {ldq_uop_9_bp_debug_if}, {ldq_uop_8_bp_debug_if}, {ldq_uop_7_bp_debug_if}, {ldq_uop_6_bp_debug_if}, {ldq_uop_5_bp_debug_if}, {ldq_uop_4_bp_debug_if}, {ldq_uop_3_bp_debug_if}, {ldq_uop_2_bp_debug_if}, {ldq_uop_1_bp_debug_if}, {ldq_uop_0_bp_debug_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_debug_if = _GEN_234[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_235 = {{ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_23_bp_xcpt_if}, {ldq_uop_22_bp_xcpt_if}, {ldq_uop_21_bp_xcpt_if}, {ldq_uop_20_bp_xcpt_if}, {ldq_uop_19_bp_xcpt_if}, {ldq_uop_18_bp_xcpt_if}, {ldq_uop_17_bp_xcpt_if}, {ldq_uop_16_bp_xcpt_if}, {ldq_uop_15_bp_xcpt_if}, {ldq_uop_14_bp_xcpt_if}, {ldq_uop_13_bp_xcpt_if}, {ldq_uop_12_bp_xcpt_if}, {ldq_uop_11_bp_xcpt_if}, {ldq_uop_10_bp_xcpt_if}, {ldq_uop_9_bp_xcpt_if}, {ldq_uop_8_bp_xcpt_if}, {ldq_uop_7_bp_xcpt_if}, {ldq_uop_6_bp_xcpt_if}, {ldq_uop_5_bp_xcpt_if}, {ldq_uop_4_bp_xcpt_if}, {ldq_uop_3_bp_xcpt_if}, {ldq_uop_2_bp_xcpt_if}, {ldq_uop_1_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_235[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_236 = {{ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_23_debug_fsrc}, {ldq_uop_22_debug_fsrc}, {ldq_uop_21_debug_fsrc}, {ldq_uop_20_debug_fsrc}, {ldq_uop_19_debug_fsrc}, {ldq_uop_18_debug_fsrc}, {ldq_uop_17_debug_fsrc}, {ldq_uop_16_debug_fsrc}, {ldq_uop_15_debug_fsrc}, {ldq_uop_14_debug_fsrc}, {ldq_uop_13_debug_fsrc}, {ldq_uop_12_debug_fsrc}, {ldq_uop_11_debug_fsrc}, {ldq_uop_10_debug_fsrc}, {ldq_uop_9_debug_fsrc}, {ldq_uop_8_debug_fsrc}, {ldq_uop_7_debug_fsrc}, {ldq_uop_6_debug_fsrc}, {ldq_uop_5_debug_fsrc}, {ldq_uop_4_debug_fsrc}, {ldq_uop_3_debug_fsrc}, {ldq_uop_2_debug_fsrc}, {ldq_uop_1_debug_fsrc}, {ldq_uop_0_debug_fsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_fsrc = _GEN_236[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_237 = {{ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_23_debug_tsrc}, {ldq_uop_22_debug_tsrc}, {ldq_uop_21_debug_tsrc}, {ldq_uop_20_debug_tsrc}, {ldq_uop_19_debug_tsrc}, {ldq_uop_18_debug_tsrc}, {ldq_uop_17_debug_tsrc}, {ldq_uop_16_debug_tsrc}, {ldq_uop_15_debug_tsrc}, {ldq_uop_14_debug_tsrc}, {ldq_uop_13_debug_tsrc}, {ldq_uop_12_debug_tsrc}, {ldq_uop_11_debug_tsrc}, {ldq_uop_10_debug_tsrc}, {ldq_uop_9_debug_tsrc}, {ldq_uop_8_debug_tsrc}, {ldq_uop_7_debug_tsrc}, {ldq_uop_6_debug_tsrc}, {ldq_uop_5_debug_tsrc}, {ldq_uop_4_debug_tsrc}, {ldq_uop_3_debug_tsrc}, {ldq_uop_2_debug_tsrc}, {ldq_uop_1_debug_tsrc}, {ldq_uop_0_debug_tsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_tsrc = _GEN_237[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_238 = {{ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_23_valid}, {ldq_addr_22_valid}, {ldq_addr_21_valid}, {ldq_addr_20_valid}, {ldq_addr_19_valid}, {ldq_addr_18_valid}, {ldq_addr_17_valid}, {ldq_addr_16_valid}, {ldq_addr_15_valid}, {ldq_addr_14_valid}, {ldq_addr_13_valid}, {ldq_addr_12_valid}, {ldq_addr_11_valid}, {ldq_addr_10_valid}, {ldq_addr_9_valid}, {ldq_addr_8_valid}, {ldq_addr_7_valid}, {ldq_addr_6_valid}, {ldq_addr_5_valid}, {ldq_addr_4_valid}, {ldq_addr_3_valid}, {ldq_addr_2_valid}, {ldq_addr_1_valid}, {ldq_addr_0_valid}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_valid = _GEN_238[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [31:0][39:0] _GEN_239 = {{ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_23_bits}, {ldq_addr_22_bits}, {ldq_addr_21_bits}, {ldq_addr_20_bits}, {ldq_addr_19_bits}, {ldq_addr_18_bits}, {ldq_addr_17_bits}, {ldq_addr_16_bits}, {ldq_addr_15_bits}, {ldq_addr_14_bits}, {ldq_addr_13_bits}, {ldq_addr_12_bits}, {ldq_addr_11_bits}, {ldq_addr_10_bits}, {ldq_addr_9_bits}, {ldq_addr_8_bits}, {ldq_addr_7_bits}, {ldq_addr_6_bits}, {ldq_addr_5_bits}, {ldq_addr_4_bits}, {ldq_addr_3_bits}, {ldq_addr_2_bits}, {ldq_addr_1_bits}, {ldq_addr_0_bits}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_bits = _GEN_239[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [31:0] _GEN_240 = {{ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_23}, {ldq_addr_is_virtual_22}, {ldq_addr_is_virtual_21}, {ldq_addr_is_virtual_20}, {ldq_addr_is_virtual_19}, {ldq_addr_is_virtual_18}, {ldq_addr_is_virtual_17}, {ldq_addr_is_virtual_16}, {ldq_addr_is_virtual_15}, {ldq_addr_is_virtual_14}, {ldq_addr_is_virtual_13}, {ldq_addr_is_virtual_12}, {ldq_addr_is_virtual_11}, {ldq_addr_is_virtual_10}, {ldq_addr_is_virtual_9}, {ldq_addr_is_virtual_8}, {ldq_addr_is_virtual_7}, {ldq_addr_is_virtual_6}, {ldq_addr_is_virtual_5}, {ldq_addr_is_virtual_4}, {ldq_addr_is_virtual_3}, {ldq_addr_is_virtual_2}, {ldq_addr_is_virtual_1}, {ldq_addr_is_virtual_0}}; // @[lsu.scala:221:36, :237:32] assign ldq_incoming_e_e_bits_addr_is_virtual = _GEN_240[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :237:32, :321:49] wire [31:0] _GEN_241 = {{ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_23}, {ldq_addr_is_uncacheable_22}, {ldq_addr_is_uncacheable_21}, {ldq_addr_is_uncacheable_20}, {ldq_addr_is_uncacheable_19}, {ldq_addr_is_uncacheable_18}, {ldq_addr_is_uncacheable_17}, {ldq_addr_is_uncacheable_16}, {ldq_addr_is_uncacheable_15}, {ldq_addr_is_uncacheable_14}, {ldq_addr_is_uncacheable_13}, {ldq_addr_is_uncacheable_12}, {ldq_addr_is_uncacheable_11}, {ldq_addr_is_uncacheable_10}, {ldq_addr_is_uncacheable_9}, {ldq_addr_is_uncacheable_8}, {ldq_addr_is_uncacheable_7}, {ldq_addr_is_uncacheable_6}, {ldq_addr_is_uncacheable_5}, {ldq_addr_is_uncacheable_4}, {ldq_addr_is_uncacheable_3}, {ldq_addr_is_uncacheable_2}, {ldq_addr_is_uncacheable_1}, {ldq_addr_is_uncacheable_0}}; // @[lsu.scala:222:36, :238:32] assign ldq_incoming_e_e_bits_addr_is_uncacheable = _GEN_241[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :238:32, :321:49] wire [31:0] _GEN_242 = {{ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_23}, {ldq_executed_22}, {ldq_executed_21}, {ldq_executed_20}, {ldq_executed_19}, {ldq_executed_18}, {ldq_executed_17}, {ldq_executed_16}, {ldq_executed_15}, {ldq_executed_14}, {ldq_executed_13}, {ldq_executed_12}, {ldq_executed_11}, {ldq_executed_10}, {ldq_executed_9}, {ldq_executed_8}, {ldq_executed_7}, {ldq_executed_6}, {ldq_executed_5}, {ldq_executed_4}, {ldq_executed_3}, {ldq_executed_2}, {ldq_executed_1}, {ldq_executed_0}}; // @[lsu.scala:223:36, :239:32] assign ldq_incoming_e_e_bits_executed = _GEN_242[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :239:32, :321:49] wire [31:0] _GEN_243 = {{ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_23}, {ldq_succeeded_22}, {ldq_succeeded_21}, {ldq_succeeded_20}, {ldq_succeeded_19}, {ldq_succeeded_18}, {ldq_succeeded_17}, {ldq_succeeded_16}, {ldq_succeeded_15}, {ldq_succeeded_14}, {ldq_succeeded_13}, {ldq_succeeded_12}, {ldq_succeeded_11}, {ldq_succeeded_10}, {ldq_succeeded_9}, {ldq_succeeded_8}, {ldq_succeeded_7}, {ldq_succeeded_6}, {ldq_succeeded_5}, {ldq_succeeded_4}, {ldq_succeeded_3}, {ldq_succeeded_2}, {ldq_succeeded_1}, {ldq_succeeded_0}}; // @[lsu.scala:224:36, :240:32] assign ldq_incoming_e_e_bits_succeeded = _GEN_243[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :240:32, :321:49] wire [31:0] _GEN_244 = {{ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_23}, {ldq_order_fail_22}, {ldq_order_fail_21}, {ldq_order_fail_20}, {ldq_order_fail_19}, {ldq_order_fail_18}, {ldq_order_fail_17}, {ldq_order_fail_16}, {ldq_order_fail_15}, {ldq_order_fail_14}, {ldq_order_fail_13}, {ldq_order_fail_12}, {ldq_order_fail_11}, {ldq_order_fail_10}, {ldq_order_fail_9}, {ldq_order_fail_8}, {ldq_order_fail_7}, {ldq_order_fail_6}, {ldq_order_fail_5}, {ldq_order_fail_4}, {ldq_order_fail_3}, {ldq_order_fail_2}, {ldq_order_fail_1}, {ldq_order_fail_0}}; // @[lsu.scala:225:36, :241:32] assign ldq_incoming_e_e_bits_order_fail = _GEN_244[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :241:32, :321:49] wire [31:0] _GEN_245 = {{ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_23}, {ldq_observed_22}, {ldq_observed_21}, {ldq_observed_20}, {ldq_observed_19}, {ldq_observed_18}, {ldq_observed_17}, {ldq_observed_16}, {ldq_observed_15}, {ldq_observed_14}, {ldq_observed_13}, {ldq_observed_12}, {ldq_observed_11}, {ldq_observed_10}, {ldq_observed_9}, {ldq_observed_8}, {ldq_observed_7}, {ldq_observed_6}, {ldq_observed_5}, {ldq_observed_4}, {ldq_observed_3}, {ldq_observed_2}, {ldq_observed_1}, {ldq_observed_0}}; // @[lsu.scala:226:36, :242:32] assign ldq_incoming_e_e_bits_observed = _GEN_245[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :242:32, :321:49] wire [31:0][23:0] _GEN_246 = {{ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_23}, {ldq_st_dep_mask_22}, {ldq_st_dep_mask_21}, {ldq_st_dep_mask_20}, {ldq_st_dep_mask_19}, {ldq_st_dep_mask_18}, {ldq_st_dep_mask_17}, {ldq_st_dep_mask_16}, {ldq_st_dep_mask_15}, {ldq_st_dep_mask_14}, {ldq_st_dep_mask_13}, {ldq_st_dep_mask_12}, {ldq_st_dep_mask_11}, {ldq_st_dep_mask_10}, {ldq_st_dep_mask_9}, {ldq_st_dep_mask_8}, {ldq_st_dep_mask_7}, {ldq_st_dep_mask_6}, {ldq_st_dep_mask_5}, {ldq_st_dep_mask_4}, {ldq_st_dep_mask_3}, {ldq_st_dep_mask_2}, {ldq_st_dep_mask_1}, {ldq_st_dep_mask_0}}; // @[lsu.scala:227:36, :243:32] assign ldq_incoming_e_e_bits_st_dep_mask = _GEN_246[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :243:32, :321:49] wire [31:0][7:0] _GEN_247 = {{ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_23}, {ldq_ld_byte_mask_22}, {ldq_ld_byte_mask_21}, {ldq_ld_byte_mask_20}, {ldq_ld_byte_mask_19}, {ldq_ld_byte_mask_18}, {ldq_ld_byte_mask_17}, {ldq_ld_byte_mask_16}, {ldq_ld_byte_mask_15}, {ldq_ld_byte_mask_14}, {ldq_ld_byte_mask_13}, {ldq_ld_byte_mask_12}, {ldq_ld_byte_mask_11}, {ldq_ld_byte_mask_10}, {ldq_ld_byte_mask_9}, {ldq_ld_byte_mask_8}, {ldq_ld_byte_mask_7}, {ldq_ld_byte_mask_6}, {ldq_ld_byte_mask_5}, {ldq_ld_byte_mask_4}, {ldq_ld_byte_mask_3}, {ldq_ld_byte_mask_2}, {ldq_ld_byte_mask_1}, {ldq_ld_byte_mask_0}}; // @[lsu.scala:228:36, :244:32] assign ldq_incoming_e_e_bits_ld_byte_mask = _GEN_247[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :244:32, :321:49] wire [31:0] _GEN_248 = {{ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_23}, {ldq_forward_std_val_22}, {ldq_forward_std_val_21}, {ldq_forward_std_val_20}, {ldq_forward_std_val_19}, {ldq_forward_std_val_18}, {ldq_forward_std_val_17}, {ldq_forward_std_val_16}, {ldq_forward_std_val_15}, {ldq_forward_std_val_14}, {ldq_forward_std_val_13}, {ldq_forward_std_val_12}, {ldq_forward_std_val_11}, {ldq_forward_std_val_10}, {ldq_forward_std_val_9}, {ldq_forward_std_val_8}, {ldq_forward_std_val_7}, {ldq_forward_std_val_6}, {ldq_forward_std_val_5}, {ldq_forward_std_val_4}, {ldq_forward_std_val_3}, {ldq_forward_std_val_2}, {ldq_forward_std_val_1}, {ldq_forward_std_val_0}}; // @[lsu.scala:229:36, :245:32] assign ldq_incoming_e_e_bits_forward_std_val = _GEN_248[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :245:32, :321:49] wire [31:0][4:0] _GEN_249 = {{ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_23}, {ldq_forward_stq_idx_22}, {ldq_forward_stq_idx_21}, {ldq_forward_stq_idx_20}, {ldq_forward_stq_idx_19}, {ldq_forward_stq_idx_18}, {ldq_forward_stq_idx_17}, {ldq_forward_stq_idx_16}, {ldq_forward_stq_idx_15}, {ldq_forward_stq_idx_14}, {ldq_forward_stq_idx_13}, {ldq_forward_stq_idx_12}, {ldq_forward_stq_idx_11}, {ldq_forward_stq_idx_10}, {ldq_forward_stq_idx_9}, {ldq_forward_stq_idx_8}, {ldq_forward_stq_idx_7}, {ldq_forward_stq_idx_6}, {ldq_forward_stq_idx_5}, {ldq_forward_stq_idx_4}, {ldq_forward_stq_idx_3}, {ldq_forward_stq_idx_2}, {ldq_forward_stq_idx_1}, {ldq_forward_stq_idx_0}}; // @[lsu.scala:230:36, :246:32] assign ldq_incoming_e_e_bits_forward_stq_idx = _GEN_249[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :246:32, :321:49] wire [31:0][63:0] _GEN_250 = {{ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_23}, {ldq_debug_wb_data_22}, {ldq_debug_wb_data_21}, {ldq_debug_wb_data_20}, {ldq_debug_wb_data_19}, {ldq_debug_wb_data_18}, {ldq_debug_wb_data_17}, {ldq_debug_wb_data_16}, {ldq_debug_wb_data_15}, {ldq_debug_wb_data_14}, {ldq_debug_wb_data_13}, {ldq_debug_wb_data_12}, {ldq_debug_wb_data_11}, {ldq_debug_wb_data_10}, {ldq_debug_wb_data_9}, {ldq_debug_wb_data_8}, {ldq_debug_wb_data_7}, {ldq_debug_wb_data_6}, {ldq_debug_wb_data_5}, {ldq_debug_wb_data_4}, {ldq_debug_wb_data_3}, {ldq_debug_wb_data_2}, {ldq_debug_wb_data_1}, {ldq_debug_wb_data_0}}; // @[lsu.scala:231:36, :247:32] assign ldq_incoming_e_e_bits_debug_wb_data = _GEN_250[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :247:32, :321:49] wire ldq_incoming_e_0_valid = _ldq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_inst = _ldq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst = _ldq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rvc = _ldq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc = _ldq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_0 = _ldq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_1 = _ldq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_2 = _ldq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_3 = _ldq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_0 = _ldq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_1 = _ldq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_2 = _ldq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_3 = _ldq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_4 = _ldq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_5 = _ldq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_6 = _ldq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_7 = _ldq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_8 = _ldq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_9 = _ldq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued = _ldq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_agen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_iw_p1_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_iw_p2_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_dis_col_sel = _ldq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :501:48] wire [15:0] ldq_incoming_e_0_bits_uop_br_mask = _ldq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_tag = _ldq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_type = _ldq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfb = _ldq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fence = _ldq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fencei = _ldq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfence = _ldq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_amo = _ldq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_eret = _ldq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rocc = _ldq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_mov = _ldq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx = _ldq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_edge_inst = _ldq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob = _ldq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_taken = _ldq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_imm_rename = _ldq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_imm_sel = _ldq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_pimm = _ldq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :501:48] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed = _ldq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_op1_sel = _ldq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_op2_sel = _ldq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ldst = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wen = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fromint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_toint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fma = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_div = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wflags = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_vec = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_rob_idx = _ldq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ldq_idx = _ldq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_stq_idx = _ldq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx = _ldq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_pdst = _ldq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs1 = _ldq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs2 = _ldq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs3 = _ldq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ppred = _ldq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs1_busy = _ldq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs2_busy = _ldq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs3_busy = _ldq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ppred_busy = _ldq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst = _ldq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_exception = _ldq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause = _ldq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd = _ldq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size = _ldq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_mem_signed = _ldq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_ldq = _ldq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_stq = _ldq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_unique = _ldq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_flush_on_commit = _ldq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_csr_cmd = _ldq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_ldst = _ldq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1 = _ldq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2 = _ldq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3 = _ldq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype = _ldq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_frs3_en = _ldq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fcn_dw = _ldq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_fcn_op = _ldq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_val = _ldq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_fp_rm = _ldq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_typ = _ldq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_debug_if = _ldq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if = _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_fsrc = _ldq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_tsrc = _ldq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_valid = _ldq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_addr_bits = _ldq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_virtual = _ldq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_uncacheable = _ldq_incoming_e_WIRE_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_executed = _ldq_incoming_e_WIRE_bits_executed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_succeeded = _ldq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_order_fail = _ldq_incoming_e_WIRE_bits_order_fail; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_observed = _ldq_incoming_e_WIRE_bits_observed; // @[lsu.scala:321:49, :501:48] wire [23:0] ldq_incoming_e_0_bits_st_dep_mask = _ldq_incoming_e_WIRE_bits_st_dep_mask; // @[lsu.scala:321:49, :501:48] wire [7:0] ldq_incoming_e_0_bits_ld_byte_mask = _ldq_incoming_e_WIRE_bits_ld_byte_mask; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_forward_std_val = _ldq_incoming_e_WIRE_bits_forward_std_val; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_forward_stq_idx = _ldq_incoming_e_WIRE_bits_forward_stq_idx; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data = _ldq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :501:48] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_0 = ldq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_1 = ldq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_2 = ldq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_3 = ldq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_0 = ldq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_1 = ldq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_2 = ldq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_3 = ldq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_4 = ldq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_5 = ldq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_6 = ldq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_7 = ldq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_8 = ldq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_9 = ldq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued = ldq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen = ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child = ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child = ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_dis_col_sel = ldq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_type = ldq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfence = ldq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_eret = ldq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rocc = ldq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_mov = ldq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_imm_rename = ldq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_imm_sel = ldq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_pimm = ldq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_op1_sel = ldq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_op2_sel = ldq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst = ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen = ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint = ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint = ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma = ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div = ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags = ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec = ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_csr_cmd = ldq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fcn_dw = ldq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_fcn_op = ldq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_fp_rm = ldq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_typ = ldq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_incoming_e_out_bits_ld_byte_mask = ldq_incoming_e_0_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire _stq_incoming_e_WIRE_valid = stq_incoming_e_e_valid; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_inst = stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_debug_inst = stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rvc = stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_uop_debug_pc = stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_0 = stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_1 = stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_2 = stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_3 = stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_0 = stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_1 = stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_2 = stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_3 = stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_4 = stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_5 = stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_6 = stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_7 = stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_8 = stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_9 = stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued = stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_dis_col_sel = stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :504:48] wire [15:0] _stq_incoming_e_WIRE_bits_uop_br_mask = stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_tag = stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_type = stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfb = stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fence = stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fencei = stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfence = stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_amo = stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_eret = stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rocc = stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_mov = stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ftq_idx = stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_edge_inst = stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_pc_lob = stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_taken = stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_imm_rename = stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_imm_sel = stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_pimm = stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :504:48] wire [19:0] _stq_incoming_e_WIRE_bits_uop_imm_packed = stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_op1_sel = stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_op2_sel = stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div = stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_rob_idx = stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ldq_idx = stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_stq_idx = stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_rxq_idx = stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_pdst = stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs1 = stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs2 = stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs3 = stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ppred = stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs1_busy = stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs2_busy = stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs3_busy = stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ppred_busy = stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_stale_pdst = stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_exception = stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_uop_exc_cause = stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_mem_cmd = stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_mem_size = stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_mem_signed = stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_ldq = stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_stq = stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_unique = stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_flush_on_commit = stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_csr_cmd = stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_ldst = stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs1 = stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs2 = stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs3 = stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dst_rtype = stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs1_rtype = stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs2_rtype = stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_frs3_en = stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fcn_dw = stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_fcn_op = stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_val = stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_fp_rm = stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_typ = stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if = stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if = stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if = stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_debug_if = stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if = stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_fsrc = stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_tsrc = stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_valid = stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_addr_bits = stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_is_virtual = stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_data_valid = stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_data_bits = stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_committed = stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_succeeded = stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_can_execute = stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_cleared = stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_debug_wb_data = stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :504:48] assign stq_incoming_e_e_valid = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:262:17, :263:32, :321:49, :392:15] wire [31:0][31:0] _GEN_251 = {{stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_23_inst}, {stq_uop_22_inst}, {stq_uop_21_inst}, {stq_uop_20_inst}, {stq_uop_19_inst}, {stq_uop_18_inst}, {stq_uop_17_inst}, {stq_uop_16_inst}, {stq_uop_15_inst}, {stq_uop_14_inst}, {stq_uop_13_inst}, {stq_uop_12_inst}, {stq_uop_11_inst}, {stq_uop_10_inst}, {stq_uop_9_inst}, {stq_uop_8_inst}, {stq_uop_7_inst}, {stq_uop_6_inst}, {stq_uop_5_inst}, {stq_uop_4_inst}, {stq_uop_3_inst}, {stq_uop_2_inst}, {stq_uop_1_inst}, {stq_uop_0_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_inst = _GEN_251[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][31:0] _GEN_252 = {{stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_23_debug_inst}, {stq_uop_22_debug_inst}, {stq_uop_21_debug_inst}, {stq_uop_20_debug_inst}, {stq_uop_19_debug_inst}, {stq_uop_18_debug_inst}, {stq_uop_17_debug_inst}, {stq_uop_16_debug_inst}, {stq_uop_15_debug_inst}, {stq_uop_14_debug_inst}, {stq_uop_13_debug_inst}, {stq_uop_12_debug_inst}, {stq_uop_11_debug_inst}, {stq_uop_10_debug_inst}, {stq_uop_9_debug_inst}, {stq_uop_8_debug_inst}, {stq_uop_7_debug_inst}, {stq_uop_6_debug_inst}, {stq_uop_5_debug_inst}, {stq_uop_4_debug_inst}, {stq_uop_3_debug_inst}, {stq_uop_2_debug_inst}, {stq_uop_1_debug_inst}, {stq_uop_0_debug_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_inst = _GEN_252[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_253 = {{stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_23_is_rvc}, {stq_uop_22_is_rvc}, {stq_uop_21_is_rvc}, {stq_uop_20_is_rvc}, {stq_uop_19_is_rvc}, {stq_uop_18_is_rvc}, {stq_uop_17_is_rvc}, {stq_uop_16_is_rvc}, {stq_uop_15_is_rvc}, {stq_uop_14_is_rvc}, {stq_uop_13_is_rvc}, {stq_uop_12_is_rvc}, {stq_uop_11_is_rvc}, {stq_uop_10_is_rvc}, {stq_uop_9_is_rvc}, {stq_uop_8_is_rvc}, {stq_uop_7_is_rvc}, {stq_uop_6_is_rvc}, {stq_uop_5_is_rvc}, {stq_uop_4_is_rvc}, {stq_uop_3_is_rvc}, {stq_uop_2_is_rvc}, {stq_uop_1_is_rvc}, {stq_uop_0_is_rvc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rvc = _GEN_253[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][39:0] _GEN_254 = {{stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_23_debug_pc}, {stq_uop_22_debug_pc}, {stq_uop_21_debug_pc}, {stq_uop_20_debug_pc}, {stq_uop_19_debug_pc}, {stq_uop_18_debug_pc}, {stq_uop_17_debug_pc}, {stq_uop_16_debug_pc}, {stq_uop_15_debug_pc}, {stq_uop_14_debug_pc}, {stq_uop_13_debug_pc}, {stq_uop_12_debug_pc}, {stq_uop_11_debug_pc}, {stq_uop_10_debug_pc}, {stq_uop_9_debug_pc}, {stq_uop_8_debug_pc}, {stq_uop_7_debug_pc}, {stq_uop_6_debug_pc}, {stq_uop_5_debug_pc}, {stq_uop_4_debug_pc}, {stq_uop_3_debug_pc}, {stq_uop_2_debug_pc}, {stq_uop_1_debug_pc}, {stq_uop_0_debug_pc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_pc = _GEN_254[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_255 = {{stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_23_iq_type_0}, {stq_uop_22_iq_type_0}, {stq_uop_21_iq_type_0}, {stq_uop_20_iq_type_0}, {stq_uop_19_iq_type_0}, {stq_uop_18_iq_type_0}, {stq_uop_17_iq_type_0}, {stq_uop_16_iq_type_0}, {stq_uop_15_iq_type_0}, {stq_uop_14_iq_type_0}, {stq_uop_13_iq_type_0}, {stq_uop_12_iq_type_0}, {stq_uop_11_iq_type_0}, {stq_uop_10_iq_type_0}, {stq_uop_9_iq_type_0}, {stq_uop_8_iq_type_0}, {stq_uop_7_iq_type_0}, {stq_uop_6_iq_type_0}, {stq_uop_5_iq_type_0}, {stq_uop_4_iq_type_0}, {stq_uop_3_iq_type_0}, {stq_uop_2_iq_type_0}, {stq_uop_1_iq_type_0}, {stq_uop_0_iq_type_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_0 = _GEN_255[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_256 = {{stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_23_iq_type_1}, {stq_uop_22_iq_type_1}, {stq_uop_21_iq_type_1}, {stq_uop_20_iq_type_1}, {stq_uop_19_iq_type_1}, {stq_uop_18_iq_type_1}, {stq_uop_17_iq_type_1}, {stq_uop_16_iq_type_1}, {stq_uop_15_iq_type_1}, {stq_uop_14_iq_type_1}, {stq_uop_13_iq_type_1}, {stq_uop_12_iq_type_1}, {stq_uop_11_iq_type_1}, {stq_uop_10_iq_type_1}, {stq_uop_9_iq_type_1}, {stq_uop_8_iq_type_1}, {stq_uop_7_iq_type_1}, {stq_uop_6_iq_type_1}, {stq_uop_5_iq_type_1}, {stq_uop_4_iq_type_1}, {stq_uop_3_iq_type_1}, {stq_uop_2_iq_type_1}, {stq_uop_1_iq_type_1}, {stq_uop_0_iq_type_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_1 = _GEN_256[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_257 = {{stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_23_iq_type_2}, {stq_uop_22_iq_type_2}, {stq_uop_21_iq_type_2}, {stq_uop_20_iq_type_2}, {stq_uop_19_iq_type_2}, {stq_uop_18_iq_type_2}, {stq_uop_17_iq_type_2}, {stq_uop_16_iq_type_2}, {stq_uop_15_iq_type_2}, {stq_uop_14_iq_type_2}, {stq_uop_13_iq_type_2}, {stq_uop_12_iq_type_2}, {stq_uop_11_iq_type_2}, {stq_uop_10_iq_type_2}, {stq_uop_9_iq_type_2}, {stq_uop_8_iq_type_2}, {stq_uop_7_iq_type_2}, {stq_uop_6_iq_type_2}, {stq_uop_5_iq_type_2}, {stq_uop_4_iq_type_2}, {stq_uop_3_iq_type_2}, {stq_uop_2_iq_type_2}, {stq_uop_1_iq_type_2}, {stq_uop_0_iq_type_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_2 = _GEN_257[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_258 = {{stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_23_iq_type_3}, {stq_uop_22_iq_type_3}, {stq_uop_21_iq_type_3}, {stq_uop_20_iq_type_3}, {stq_uop_19_iq_type_3}, {stq_uop_18_iq_type_3}, {stq_uop_17_iq_type_3}, {stq_uop_16_iq_type_3}, {stq_uop_15_iq_type_3}, {stq_uop_14_iq_type_3}, {stq_uop_13_iq_type_3}, {stq_uop_12_iq_type_3}, {stq_uop_11_iq_type_3}, {stq_uop_10_iq_type_3}, {stq_uop_9_iq_type_3}, {stq_uop_8_iq_type_3}, {stq_uop_7_iq_type_3}, {stq_uop_6_iq_type_3}, {stq_uop_5_iq_type_3}, {stq_uop_4_iq_type_3}, {stq_uop_3_iq_type_3}, {stq_uop_2_iq_type_3}, {stq_uop_1_iq_type_3}, {stq_uop_0_iq_type_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_3 = _GEN_258[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_259 = {{stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_23_fu_code_0}, {stq_uop_22_fu_code_0}, {stq_uop_21_fu_code_0}, {stq_uop_20_fu_code_0}, {stq_uop_19_fu_code_0}, {stq_uop_18_fu_code_0}, {stq_uop_17_fu_code_0}, {stq_uop_16_fu_code_0}, {stq_uop_15_fu_code_0}, {stq_uop_14_fu_code_0}, {stq_uop_13_fu_code_0}, {stq_uop_12_fu_code_0}, {stq_uop_11_fu_code_0}, {stq_uop_10_fu_code_0}, {stq_uop_9_fu_code_0}, {stq_uop_8_fu_code_0}, {stq_uop_7_fu_code_0}, {stq_uop_6_fu_code_0}, {stq_uop_5_fu_code_0}, {stq_uop_4_fu_code_0}, {stq_uop_3_fu_code_0}, {stq_uop_2_fu_code_0}, {stq_uop_1_fu_code_0}, {stq_uop_0_fu_code_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_0 = _GEN_259[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_260 = {{stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_23_fu_code_1}, {stq_uop_22_fu_code_1}, {stq_uop_21_fu_code_1}, {stq_uop_20_fu_code_1}, {stq_uop_19_fu_code_1}, {stq_uop_18_fu_code_1}, {stq_uop_17_fu_code_1}, {stq_uop_16_fu_code_1}, {stq_uop_15_fu_code_1}, {stq_uop_14_fu_code_1}, {stq_uop_13_fu_code_1}, {stq_uop_12_fu_code_1}, {stq_uop_11_fu_code_1}, {stq_uop_10_fu_code_1}, {stq_uop_9_fu_code_1}, {stq_uop_8_fu_code_1}, {stq_uop_7_fu_code_1}, {stq_uop_6_fu_code_1}, {stq_uop_5_fu_code_1}, {stq_uop_4_fu_code_1}, {stq_uop_3_fu_code_1}, {stq_uop_2_fu_code_1}, {stq_uop_1_fu_code_1}, {stq_uop_0_fu_code_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_1 = _GEN_260[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_261 = {{stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_23_fu_code_2}, {stq_uop_22_fu_code_2}, {stq_uop_21_fu_code_2}, {stq_uop_20_fu_code_2}, {stq_uop_19_fu_code_2}, {stq_uop_18_fu_code_2}, {stq_uop_17_fu_code_2}, {stq_uop_16_fu_code_2}, {stq_uop_15_fu_code_2}, {stq_uop_14_fu_code_2}, {stq_uop_13_fu_code_2}, {stq_uop_12_fu_code_2}, {stq_uop_11_fu_code_2}, {stq_uop_10_fu_code_2}, {stq_uop_9_fu_code_2}, {stq_uop_8_fu_code_2}, {stq_uop_7_fu_code_2}, {stq_uop_6_fu_code_2}, {stq_uop_5_fu_code_2}, {stq_uop_4_fu_code_2}, {stq_uop_3_fu_code_2}, {stq_uop_2_fu_code_2}, {stq_uop_1_fu_code_2}, {stq_uop_0_fu_code_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_2 = _GEN_261[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_262 = {{stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_23_fu_code_3}, {stq_uop_22_fu_code_3}, {stq_uop_21_fu_code_3}, {stq_uop_20_fu_code_3}, {stq_uop_19_fu_code_3}, {stq_uop_18_fu_code_3}, {stq_uop_17_fu_code_3}, {stq_uop_16_fu_code_3}, {stq_uop_15_fu_code_3}, {stq_uop_14_fu_code_3}, {stq_uop_13_fu_code_3}, {stq_uop_12_fu_code_3}, {stq_uop_11_fu_code_3}, {stq_uop_10_fu_code_3}, {stq_uop_9_fu_code_3}, {stq_uop_8_fu_code_3}, {stq_uop_7_fu_code_3}, {stq_uop_6_fu_code_3}, {stq_uop_5_fu_code_3}, {stq_uop_4_fu_code_3}, {stq_uop_3_fu_code_3}, {stq_uop_2_fu_code_3}, {stq_uop_1_fu_code_3}, {stq_uop_0_fu_code_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_3 = _GEN_262[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_263 = {{stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_23_fu_code_4}, {stq_uop_22_fu_code_4}, {stq_uop_21_fu_code_4}, {stq_uop_20_fu_code_4}, {stq_uop_19_fu_code_4}, {stq_uop_18_fu_code_4}, {stq_uop_17_fu_code_4}, {stq_uop_16_fu_code_4}, {stq_uop_15_fu_code_4}, {stq_uop_14_fu_code_4}, {stq_uop_13_fu_code_4}, {stq_uop_12_fu_code_4}, {stq_uop_11_fu_code_4}, {stq_uop_10_fu_code_4}, {stq_uop_9_fu_code_4}, {stq_uop_8_fu_code_4}, {stq_uop_7_fu_code_4}, {stq_uop_6_fu_code_4}, {stq_uop_5_fu_code_4}, {stq_uop_4_fu_code_4}, {stq_uop_3_fu_code_4}, {stq_uop_2_fu_code_4}, {stq_uop_1_fu_code_4}, {stq_uop_0_fu_code_4}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_4 = _GEN_263[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_264 = {{stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_23_fu_code_5}, {stq_uop_22_fu_code_5}, {stq_uop_21_fu_code_5}, {stq_uop_20_fu_code_5}, {stq_uop_19_fu_code_5}, {stq_uop_18_fu_code_5}, {stq_uop_17_fu_code_5}, {stq_uop_16_fu_code_5}, {stq_uop_15_fu_code_5}, {stq_uop_14_fu_code_5}, {stq_uop_13_fu_code_5}, {stq_uop_12_fu_code_5}, {stq_uop_11_fu_code_5}, {stq_uop_10_fu_code_5}, {stq_uop_9_fu_code_5}, {stq_uop_8_fu_code_5}, {stq_uop_7_fu_code_5}, {stq_uop_6_fu_code_5}, {stq_uop_5_fu_code_5}, {stq_uop_4_fu_code_5}, {stq_uop_3_fu_code_5}, {stq_uop_2_fu_code_5}, {stq_uop_1_fu_code_5}, {stq_uop_0_fu_code_5}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_5 = _GEN_264[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_265 = {{stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_23_fu_code_6}, {stq_uop_22_fu_code_6}, {stq_uop_21_fu_code_6}, {stq_uop_20_fu_code_6}, {stq_uop_19_fu_code_6}, {stq_uop_18_fu_code_6}, {stq_uop_17_fu_code_6}, {stq_uop_16_fu_code_6}, {stq_uop_15_fu_code_6}, {stq_uop_14_fu_code_6}, {stq_uop_13_fu_code_6}, {stq_uop_12_fu_code_6}, {stq_uop_11_fu_code_6}, {stq_uop_10_fu_code_6}, {stq_uop_9_fu_code_6}, {stq_uop_8_fu_code_6}, {stq_uop_7_fu_code_6}, {stq_uop_6_fu_code_6}, {stq_uop_5_fu_code_6}, {stq_uop_4_fu_code_6}, {stq_uop_3_fu_code_6}, {stq_uop_2_fu_code_6}, {stq_uop_1_fu_code_6}, {stq_uop_0_fu_code_6}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_6 = _GEN_265[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_266 = {{stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_23_fu_code_7}, {stq_uop_22_fu_code_7}, {stq_uop_21_fu_code_7}, {stq_uop_20_fu_code_7}, {stq_uop_19_fu_code_7}, {stq_uop_18_fu_code_7}, {stq_uop_17_fu_code_7}, {stq_uop_16_fu_code_7}, {stq_uop_15_fu_code_7}, {stq_uop_14_fu_code_7}, {stq_uop_13_fu_code_7}, {stq_uop_12_fu_code_7}, {stq_uop_11_fu_code_7}, {stq_uop_10_fu_code_7}, {stq_uop_9_fu_code_7}, {stq_uop_8_fu_code_7}, {stq_uop_7_fu_code_7}, {stq_uop_6_fu_code_7}, {stq_uop_5_fu_code_7}, {stq_uop_4_fu_code_7}, {stq_uop_3_fu_code_7}, {stq_uop_2_fu_code_7}, {stq_uop_1_fu_code_7}, {stq_uop_0_fu_code_7}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_7 = _GEN_266[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_267 = {{stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_23_fu_code_8}, {stq_uop_22_fu_code_8}, {stq_uop_21_fu_code_8}, {stq_uop_20_fu_code_8}, {stq_uop_19_fu_code_8}, {stq_uop_18_fu_code_8}, {stq_uop_17_fu_code_8}, {stq_uop_16_fu_code_8}, {stq_uop_15_fu_code_8}, {stq_uop_14_fu_code_8}, {stq_uop_13_fu_code_8}, {stq_uop_12_fu_code_8}, {stq_uop_11_fu_code_8}, {stq_uop_10_fu_code_8}, {stq_uop_9_fu_code_8}, {stq_uop_8_fu_code_8}, {stq_uop_7_fu_code_8}, {stq_uop_6_fu_code_8}, {stq_uop_5_fu_code_8}, {stq_uop_4_fu_code_8}, {stq_uop_3_fu_code_8}, {stq_uop_2_fu_code_8}, {stq_uop_1_fu_code_8}, {stq_uop_0_fu_code_8}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_8 = _GEN_267[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_268 = {{stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_23_fu_code_9}, {stq_uop_22_fu_code_9}, {stq_uop_21_fu_code_9}, {stq_uop_20_fu_code_9}, {stq_uop_19_fu_code_9}, {stq_uop_18_fu_code_9}, {stq_uop_17_fu_code_9}, {stq_uop_16_fu_code_9}, {stq_uop_15_fu_code_9}, {stq_uop_14_fu_code_9}, {stq_uop_13_fu_code_9}, {stq_uop_12_fu_code_9}, {stq_uop_11_fu_code_9}, {stq_uop_10_fu_code_9}, {stq_uop_9_fu_code_9}, {stq_uop_8_fu_code_9}, {stq_uop_7_fu_code_9}, {stq_uop_6_fu_code_9}, {stq_uop_5_fu_code_9}, {stq_uop_4_fu_code_9}, {stq_uop_3_fu_code_9}, {stq_uop_2_fu_code_9}, {stq_uop_1_fu_code_9}, {stq_uop_0_fu_code_9}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_9 = _GEN_268[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_269 = {{stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_23_iw_issued}, {stq_uop_22_iw_issued}, {stq_uop_21_iw_issued}, {stq_uop_20_iw_issued}, {stq_uop_19_iw_issued}, {stq_uop_18_iw_issued}, {stq_uop_17_iw_issued}, {stq_uop_16_iw_issued}, {stq_uop_15_iw_issued}, {stq_uop_14_iw_issued}, {stq_uop_13_iw_issued}, {stq_uop_12_iw_issued}, {stq_uop_11_iw_issued}, {stq_uop_10_iw_issued}, {stq_uop_9_iw_issued}, {stq_uop_8_iw_issued}, {stq_uop_7_iw_issued}, {stq_uop_6_iw_issued}, {stq_uop_5_iw_issued}, {stq_uop_4_iw_issued}, {stq_uop_3_iw_issued}, {stq_uop_2_iw_issued}, {stq_uop_1_iw_issued}, {stq_uop_0_iw_issued}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued = _GEN_269[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_270 = {{stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_23_iw_issued_partial_agen}, {stq_uop_22_iw_issued_partial_agen}, {stq_uop_21_iw_issued_partial_agen}, {stq_uop_20_iw_issued_partial_agen}, {stq_uop_19_iw_issued_partial_agen}, {stq_uop_18_iw_issued_partial_agen}, {stq_uop_17_iw_issued_partial_agen}, {stq_uop_16_iw_issued_partial_agen}, {stq_uop_15_iw_issued_partial_agen}, {stq_uop_14_iw_issued_partial_agen}, {stq_uop_13_iw_issued_partial_agen}, {stq_uop_12_iw_issued_partial_agen}, {stq_uop_11_iw_issued_partial_agen}, {stq_uop_10_iw_issued_partial_agen}, {stq_uop_9_iw_issued_partial_agen}, {stq_uop_8_iw_issued_partial_agen}, {stq_uop_7_iw_issued_partial_agen}, {stq_uop_6_iw_issued_partial_agen}, {stq_uop_5_iw_issued_partial_agen}, {stq_uop_4_iw_issued_partial_agen}, {stq_uop_3_iw_issued_partial_agen}, {stq_uop_2_iw_issued_partial_agen}, {stq_uop_1_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_271 = {{stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_23_iw_issued_partial_dgen}, {stq_uop_22_iw_issued_partial_dgen}, {stq_uop_21_iw_issued_partial_dgen}, {stq_uop_20_iw_issued_partial_dgen}, {stq_uop_19_iw_issued_partial_dgen}, {stq_uop_18_iw_issued_partial_dgen}, {stq_uop_17_iw_issued_partial_dgen}, {stq_uop_16_iw_issued_partial_dgen}, {stq_uop_15_iw_issued_partial_dgen}, {stq_uop_14_iw_issued_partial_dgen}, {stq_uop_13_iw_issued_partial_dgen}, {stq_uop_12_iw_issued_partial_dgen}, {stq_uop_11_iw_issued_partial_dgen}, {stq_uop_10_iw_issued_partial_dgen}, {stq_uop_9_iw_issued_partial_dgen}, {stq_uop_8_iw_issued_partial_dgen}, {stq_uop_7_iw_issued_partial_dgen}, {stq_uop_6_iw_issued_partial_dgen}, {stq_uop_5_iw_issued_partial_dgen}, {stq_uop_4_iw_issued_partial_dgen}, {stq_uop_3_iw_issued_partial_dgen}, {stq_uop_2_iw_issued_partial_dgen}, {stq_uop_1_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_272 = {{stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_23_iw_p1_speculative_child}, {stq_uop_22_iw_p1_speculative_child}, {stq_uop_21_iw_p1_speculative_child}, {stq_uop_20_iw_p1_speculative_child}, {stq_uop_19_iw_p1_speculative_child}, {stq_uop_18_iw_p1_speculative_child}, {stq_uop_17_iw_p1_speculative_child}, {stq_uop_16_iw_p1_speculative_child}, {stq_uop_15_iw_p1_speculative_child}, {stq_uop_14_iw_p1_speculative_child}, {stq_uop_13_iw_p1_speculative_child}, {stq_uop_12_iw_p1_speculative_child}, {stq_uop_11_iw_p1_speculative_child}, {stq_uop_10_iw_p1_speculative_child}, {stq_uop_9_iw_p1_speculative_child}, {stq_uop_8_iw_p1_speculative_child}, {stq_uop_7_iw_p1_speculative_child}, {stq_uop_6_iw_p1_speculative_child}, {stq_uop_5_iw_p1_speculative_child}, {stq_uop_4_iw_p1_speculative_child}, {stq_uop_3_iw_p1_speculative_child}, {stq_uop_2_iw_p1_speculative_child}, {stq_uop_1_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_273 = {{stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_23_iw_p2_speculative_child}, {stq_uop_22_iw_p2_speculative_child}, {stq_uop_21_iw_p2_speculative_child}, {stq_uop_20_iw_p2_speculative_child}, {stq_uop_19_iw_p2_speculative_child}, {stq_uop_18_iw_p2_speculative_child}, {stq_uop_17_iw_p2_speculative_child}, {stq_uop_16_iw_p2_speculative_child}, {stq_uop_15_iw_p2_speculative_child}, {stq_uop_14_iw_p2_speculative_child}, {stq_uop_13_iw_p2_speculative_child}, {stq_uop_12_iw_p2_speculative_child}, {stq_uop_11_iw_p2_speculative_child}, {stq_uop_10_iw_p2_speculative_child}, {stq_uop_9_iw_p2_speculative_child}, {stq_uop_8_iw_p2_speculative_child}, {stq_uop_7_iw_p2_speculative_child}, {stq_uop_6_iw_p2_speculative_child}, {stq_uop_5_iw_p2_speculative_child}, {stq_uop_4_iw_p2_speculative_child}, {stq_uop_3_iw_p2_speculative_child}, {stq_uop_2_iw_p2_speculative_child}, {stq_uop_1_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_274 = {{stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_23_iw_p1_bypass_hint}, {stq_uop_22_iw_p1_bypass_hint}, {stq_uop_21_iw_p1_bypass_hint}, {stq_uop_20_iw_p1_bypass_hint}, {stq_uop_19_iw_p1_bypass_hint}, {stq_uop_18_iw_p1_bypass_hint}, {stq_uop_17_iw_p1_bypass_hint}, {stq_uop_16_iw_p1_bypass_hint}, {stq_uop_15_iw_p1_bypass_hint}, {stq_uop_14_iw_p1_bypass_hint}, {stq_uop_13_iw_p1_bypass_hint}, {stq_uop_12_iw_p1_bypass_hint}, {stq_uop_11_iw_p1_bypass_hint}, {stq_uop_10_iw_p1_bypass_hint}, {stq_uop_9_iw_p1_bypass_hint}, {stq_uop_8_iw_p1_bypass_hint}, {stq_uop_7_iw_p1_bypass_hint}, {stq_uop_6_iw_p1_bypass_hint}, {stq_uop_5_iw_p1_bypass_hint}, {stq_uop_4_iw_p1_bypass_hint}, {stq_uop_3_iw_p1_bypass_hint}, {stq_uop_2_iw_p1_bypass_hint}, {stq_uop_1_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_275 = {{stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_23_iw_p2_bypass_hint}, {stq_uop_22_iw_p2_bypass_hint}, {stq_uop_21_iw_p2_bypass_hint}, {stq_uop_20_iw_p2_bypass_hint}, {stq_uop_19_iw_p2_bypass_hint}, {stq_uop_18_iw_p2_bypass_hint}, {stq_uop_17_iw_p2_bypass_hint}, {stq_uop_16_iw_p2_bypass_hint}, {stq_uop_15_iw_p2_bypass_hint}, {stq_uop_14_iw_p2_bypass_hint}, {stq_uop_13_iw_p2_bypass_hint}, {stq_uop_12_iw_p2_bypass_hint}, {stq_uop_11_iw_p2_bypass_hint}, {stq_uop_10_iw_p2_bypass_hint}, {stq_uop_9_iw_p2_bypass_hint}, {stq_uop_8_iw_p2_bypass_hint}, {stq_uop_7_iw_p2_bypass_hint}, {stq_uop_6_iw_p2_bypass_hint}, {stq_uop_5_iw_p2_bypass_hint}, {stq_uop_4_iw_p2_bypass_hint}, {stq_uop_3_iw_p2_bypass_hint}, {stq_uop_2_iw_p2_bypass_hint}, {stq_uop_1_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_276 = {{stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_23_iw_p3_bypass_hint}, {stq_uop_22_iw_p3_bypass_hint}, {stq_uop_21_iw_p3_bypass_hint}, {stq_uop_20_iw_p3_bypass_hint}, {stq_uop_19_iw_p3_bypass_hint}, {stq_uop_18_iw_p3_bypass_hint}, {stq_uop_17_iw_p3_bypass_hint}, {stq_uop_16_iw_p3_bypass_hint}, {stq_uop_15_iw_p3_bypass_hint}, {stq_uop_14_iw_p3_bypass_hint}, {stq_uop_13_iw_p3_bypass_hint}, {stq_uop_12_iw_p3_bypass_hint}, {stq_uop_11_iw_p3_bypass_hint}, {stq_uop_10_iw_p3_bypass_hint}, {stq_uop_9_iw_p3_bypass_hint}, {stq_uop_8_iw_p3_bypass_hint}, {stq_uop_7_iw_p3_bypass_hint}, {stq_uop_6_iw_p3_bypass_hint}, {stq_uop_5_iw_p3_bypass_hint}, {stq_uop_4_iw_p3_bypass_hint}, {stq_uop_3_iw_p3_bypass_hint}, {stq_uop_2_iw_p3_bypass_hint}, {stq_uop_1_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_277 = {{stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_23_dis_col_sel}, {stq_uop_22_dis_col_sel}, {stq_uop_21_dis_col_sel}, {stq_uop_20_dis_col_sel}, {stq_uop_19_dis_col_sel}, {stq_uop_18_dis_col_sel}, {stq_uop_17_dis_col_sel}, {stq_uop_16_dis_col_sel}, {stq_uop_15_dis_col_sel}, {stq_uop_14_dis_col_sel}, {stq_uop_13_dis_col_sel}, {stq_uop_12_dis_col_sel}, {stq_uop_11_dis_col_sel}, {stq_uop_10_dis_col_sel}, {stq_uop_9_dis_col_sel}, {stq_uop_8_dis_col_sel}, {stq_uop_7_dis_col_sel}, {stq_uop_6_dis_col_sel}, {stq_uop_5_dis_col_sel}, {stq_uop_4_dis_col_sel}, {stq_uop_3_dis_col_sel}, {stq_uop_2_dis_col_sel}, {stq_uop_1_dis_col_sel}, {stq_uop_0_dis_col_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dis_col_sel = _GEN_277[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][15:0] _GEN_278 = {{stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_23_br_mask}, {stq_uop_22_br_mask}, {stq_uop_21_br_mask}, {stq_uop_20_br_mask}, {stq_uop_19_br_mask}, {stq_uop_18_br_mask}, {stq_uop_17_br_mask}, {stq_uop_16_br_mask}, {stq_uop_15_br_mask}, {stq_uop_14_br_mask}, {stq_uop_13_br_mask}, {stq_uop_12_br_mask}, {stq_uop_11_br_mask}, {stq_uop_10_br_mask}, {stq_uop_9_br_mask}, {stq_uop_8_br_mask}, {stq_uop_7_br_mask}, {stq_uop_6_br_mask}, {stq_uop_5_br_mask}, {stq_uop_4_br_mask}, {stq_uop_3_br_mask}, {stq_uop_2_br_mask}, {stq_uop_1_br_mask}, {stq_uop_0_br_mask}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_mask = _GEN_278[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][3:0] _GEN_279 = {{stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_23_br_tag}, {stq_uop_22_br_tag}, {stq_uop_21_br_tag}, {stq_uop_20_br_tag}, {stq_uop_19_br_tag}, {stq_uop_18_br_tag}, {stq_uop_17_br_tag}, {stq_uop_16_br_tag}, {stq_uop_15_br_tag}, {stq_uop_14_br_tag}, {stq_uop_13_br_tag}, {stq_uop_12_br_tag}, {stq_uop_11_br_tag}, {stq_uop_10_br_tag}, {stq_uop_9_br_tag}, {stq_uop_8_br_tag}, {stq_uop_7_br_tag}, {stq_uop_6_br_tag}, {stq_uop_5_br_tag}, {stq_uop_4_br_tag}, {stq_uop_3_br_tag}, {stq_uop_2_br_tag}, {stq_uop_1_br_tag}, {stq_uop_0_br_tag}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_tag = _GEN_279[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][3:0] _GEN_280 = {{stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_23_br_type}, {stq_uop_22_br_type}, {stq_uop_21_br_type}, {stq_uop_20_br_type}, {stq_uop_19_br_type}, {stq_uop_18_br_type}, {stq_uop_17_br_type}, {stq_uop_16_br_type}, {stq_uop_15_br_type}, {stq_uop_14_br_type}, {stq_uop_13_br_type}, {stq_uop_12_br_type}, {stq_uop_11_br_type}, {stq_uop_10_br_type}, {stq_uop_9_br_type}, {stq_uop_8_br_type}, {stq_uop_7_br_type}, {stq_uop_6_br_type}, {stq_uop_5_br_type}, {stq_uop_4_br_type}, {stq_uop_3_br_type}, {stq_uop_2_br_type}, {stq_uop_1_br_type}, {stq_uop_0_br_type}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_type = _GEN_280[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_281 = {{stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_23_is_sfb}, {stq_uop_22_is_sfb}, {stq_uop_21_is_sfb}, {stq_uop_20_is_sfb}, {stq_uop_19_is_sfb}, {stq_uop_18_is_sfb}, {stq_uop_17_is_sfb}, {stq_uop_16_is_sfb}, {stq_uop_15_is_sfb}, {stq_uop_14_is_sfb}, {stq_uop_13_is_sfb}, {stq_uop_12_is_sfb}, {stq_uop_11_is_sfb}, {stq_uop_10_is_sfb}, {stq_uop_9_is_sfb}, {stq_uop_8_is_sfb}, {stq_uop_7_is_sfb}, {stq_uop_6_is_sfb}, {stq_uop_5_is_sfb}, {stq_uop_4_is_sfb}, {stq_uop_3_is_sfb}, {stq_uop_2_is_sfb}, {stq_uop_1_is_sfb}, {stq_uop_0_is_sfb}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfb = _GEN_281[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_282 = {{stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_23_is_fence}, {stq_uop_22_is_fence}, {stq_uop_21_is_fence}, {stq_uop_20_is_fence}, {stq_uop_19_is_fence}, {stq_uop_18_is_fence}, {stq_uop_17_is_fence}, {stq_uop_16_is_fence}, {stq_uop_15_is_fence}, {stq_uop_14_is_fence}, {stq_uop_13_is_fence}, {stq_uop_12_is_fence}, {stq_uop_11_is_fence}, {stq_uop_10_is_fence}, {stq_uop_9_is_fence}, {stq_uop_8_is_fence}, {stq_uop_7_is_fence}, {stq_uop_6_is_fence}, {stq_uop_5_is_fence}, {stq_uop_4_is_fence}, {stq_uop_3_is_fence}, {stq_uop_2_is_fence}, {stq_uop_1_is_fence}, {stq_uop_0_is_fence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fence = _GEN_282[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_283 = {{stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_23_is_fencei}, {stq_uop_22_is_fencei}, {stq_uop_21_is_fencei}, {stq_uop_20_is_fencei}, {stq_uop_19_is_fencei}, {stq_uop_18_is_fencei}, {stq_uop_17_is_fencei}, {stq_uop_16_is_fencei}, {stq_uop_15_is_fencei}, {stq_uop_14_is_fencei}, {stq_uop_13_is_fencei}, {stq_uop_12_is_fencei}, {stq_uop_11_is_fencei}, {stq_uop_10_is_fencei}, {stq_uop_9_is_fencei}, {stq_uop_8_is_fencei}, {stq_uop_7_is_fencei}, {stq_uop_6_is_fencei}, {stq_uop_5_is_fencei}, {stq_uop_4_is_fencei}, {stq_uop_3_is_fencei}, {stq_uop_2_is_fencei}, {stq_uop_1_is_fencei}, {stq_uop_0_is_fencei}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fencei = _GEN_283[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_284 = {{stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_23_is_sfence}, {stq_uop_22_is_sfence}, {stq_uop_21_is_sfence}, {stq_uop_20_is_sfence}, {stq_uop_19_is_sfence}, {stq_uop_18_is_sfence}, {stq_uop_17_is_sfence}, {stq_uop_16_is_sfence}, {stq_uop_15_is_sfence}, {stq_uop_14_is_sfence}, {stq_uop_13_is_sfence}, {stq_uop_12_is_sfence}, {stq_uop_11_is_sfence}, {stq_uop_10_is_sfence}, {stq_uop_9_is_sfence}, {stq_uop_8_is_sfence}, {stq_uop_7_is_sfence}, {stq_uop_6_is_sfence}, {stq_uop_5_is_sfence}, {stq_uop_4_is_sfence}, {stq_uop_3_is_sfence}, {stq_uop_2_is_sfence}, {stq_uop_1_is_sfence}, {stq_uop_0_is_sfence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfence = _GEN_284[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_285 = {{stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_23_is_amo}, {stq_uop_22_is_amo}, {stq_uop_21_is_amo}, {stq_uop_20_is_amo}, {stq_uop_19_is_amo}, {stq_uop_18_is_amo}, {stq_uop_17_is_amo}, {stq_uop_16_is_amo}, {stq_uop_15_is_amo}, {stq_uop_14_is_amo}, {stq_uop_13_is_amo}, {stq_uop_12_is_amo}, {stq_uop_11_is_amo}, {stq_uop_10_is_amo}, {stq_uop_9_is_amo}, {stq_uop_8_is_amo}, {stq_uop_7_is_amo}, {stq_uop_6_is_amo}, {stq_uop_5_is_amo}, {stq_uop_4_is_amo}, {stq_uop_3_is_amo}, {stq_uop_2_is_amo}, {stq_uop_1_is_amo}, {stq_uop_0_is_amo}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_amo = _GEN_285[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_286 = {{stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_23_is_eret}, {stq_uop_22_is_eret}, {stq_uop_21_is_eret}, {stq_uop_20_is_eret}, {stq_uop_19_is_eret}, {stq_uop_18_is_eret}, {stq_uop_17_is_eret}, {stq_uop_16_is_eret}, {stq_uop_15_is_eret}, {stq_uop_14_is_eret}, {stq_uop_13_is_eret}, {stq_uop_12_is_eret}, {stq_uop_11_is_eret}, {stq_uop_10_is_eret}, {stq_uop_9_is_eret}, {stq_uop_8_is_eret}, {stq_uop_7_is_eret}, {stq_uop_6_is_eret}, {stq_uop_5_is_eret}, {stq_uop_4_is_eret}, {stq_uop_3_is_eret}, {stq_uop_2_is_eret}, {stq_uop_1_is_eret}, {stq_uop_0_is_eret}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_eret = _GEN_286[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_287 = {{stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_23_is_sys_pc2epc}, {stq_uop_22_is_sys_pc2epc}, {stq_uop_21_is_sys_pc2epc}, {stq_uop_20_is_sys_pc2epc}, {stq_uop_19_is_sys_pc2epc}, {stq_uop_18_is_sys_pc2epc}, {stq_uop_17_is_sys_pc2epc}, {stq_uop_16_is_sys_pc2epc}, {stq_uop_15_is_sys_pc2epc}, {stq_uop_14_is_sys_pc2epc}, {stq_uop_13_is_sys_pc2epc}, {stq_uop_12_is_sys_pc2epc}, {stq_uop_11_is_sys_pc2epc}, {stq_uop_10_is_sys_pc2epc}, {stq_uop_9_is_sys_pc2epc}, {stq_uop_8_is_sys_pc2epc}, {stq_uop_7_is_sys_pc2epc}, {stq_uop_6_is_sys_pc2epc}, {stq_uop_5_is_sys_pc2epc}, {stq_uop_4_is_sys_pc2epc}, {stq_uop_3_is_sys_pc2epc}, {stq_uop_2_is_sys_pc2epc}, {stq_uop_1_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_288 = {{stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_23_is_rocc}, {stq_uop_22_is_rocc}, {stq_uop_21_is_rocc}, {stq_uop_20_is_rocc}, {stq_uop_19_is_rocc}, {stq_uop_18_is_rocc}, {stq_uop_17_is_rocc}, {stq_uop_16_is_rocc}, {stq_uop_15_is_rocc}, {stq_uop_14_is_rocc}, {stq_uop_13_is_rocc}, {stq_uop_12_is_rocc}, {stq_uop_11_is_rocc}, {stq_uop_10_is_rocc}, {stq_uop_9_is_rocc}, {stq_uop_8_is_rocc}, {stq_uop_7_is_rocc}, {stq_uop_6_is_rocc}, {stq_uop_5_is_rocc}, {stq_uop_4_is_rocc}, {stq_uop_3_is_rocc}, {stq_uop_2_is_rocc}, {stq_uop_1_is_rocc}, {stq_uop_0_is_rocc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rocc = _GEN_288[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_289 = {{stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_23_is_mov}, {stq_uop_22_is_mov}, {stq_uop_21_is_mov}, {stq_uop_20_is_mov}, {stq_uop_19_is_mov}, {stq_uop_18_is_mov}, {stq_uop_17_is_mov}, {stq_uop_16_is_mov}, {stq_uop_15_is_mov}, {stq_uop_14_is_mov}, {stq_uop_13_is_mov}, {stq_uop_12_is_mov}, {stq_uop_11_is_mov}, {stq_uop_10_is_mov}, {stq_uop_9_is_mov}, {stq_uop_8_is_mov}, {stq_uop_7_is_mov}, {stq_uop_6_is_mov}, {stq_uop_5_is_mov}, {stq_uop_4_is_mov}, {stq_uop_3_is_mov}, {stq_uop_2_is_mov}, {stq_uop_1_is_mov}, {stq_uop_0_is_mov}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_mov = _GEN_289[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_290 = {{stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_23_ftq_idx}, {stq_uop_22_ftq_idx}, {stq_uop_21_ftq_idx}, {stq_uop_20_ftq_idx}, {stq_uop_19_ftq_idx}, {stq_uop_18_ftq_idx}, {stq_uop_17_ftq_idx}, {stq_uop_16_ftq_idx}, {stq_uop_15_ftq_idx}, {stq_uop_14_ftq_idx}, {stq_uop_13_ftq_idx}, {stq_uop_12_ftq_idx}, {stq_uop_11_ftq_idx}, {stq_uop_10_ftq_idx}, {stq_uop_9_ftq_idx}, {stq_uop_8_ftq_idx}, {stq_uop_7_ftq_idx}, {stq_uop_6_ftq_idx}, {stq_uop_5_ftq_idx}, {stq_uop_4_ftq_idx}, {stq_uop_3_ftq_idx}, {stq_uop_2_ftq_idx}, {stq_uop_1_ftq_idx}, {stq_uop_0_ftq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ftq_idx = _GEN_290[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_291 = {{stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_23_edge_inst}, {stq_uop_22_edge_inst}, {stq_uop_21_edge_inst}, {stq_uop_20_edge_inst}, {stq_uop_19_edge_inst}, {stq_uop_18_edge_inst}, {stq_uop_17_edge_inst}, {stq_uop_16_edge_inst}, {stq_uop_15_edge_inst}, {stq_uop_14_edge_inst}, {stq_uop_13_edge_inst}, {stq_uop_12_edge_inst}, {stq_uop_11_edge_inst}, {stq_uop_10_edge_inst}, {stq_uop_9_edge_inst}, {stq_uop_8_edge_inst}, {stq_uop_7_edge_inst}, {stq_uop_6_edge_inst}, {stq_uop_5_edge_inst}, {stq_uop_4_edge_inst}, {stq_uop_3_edge_inst}, {stq_uop_2_edge_inst}, {stq_uop_1_edge_inst}, {stq_uop_0_edge_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_edge_inst = _GEN_291[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_292 = {{stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_23_pc_lob}, {stq_uop_22_pc_lob}, {stq_uop_21_pc_lob}, {stq_uop_20_pc_lob}, {stq_uop_19_pc_lob}, {stq_uop_18_pc_lob}, {stq_uop_17_pc_lob}, {stq_uop_16_pc_lob}, {stq_uop_15_pc_lob}, {stq_uop_14_pc_lob}, {stq_uop_13_pc_lob}, {stq_uop_12_pc_lob}, {stq_uop_11_pc_lob}, {stq_uop_10_pc_lob}, {stq_uop_9_pc_lob}, {stq_uop_8_pc_lob}, {stq_uop_7_pc_lob}, {stq_uop_6_pc_lob}, {stq_uop_5_pc_lob}, {stq_uop_4_pc_lob}, {stq_uop_3_pc_lob}, {stq_uop_2_pc_lob}, {stq_uop_1_pc_lob}, {stq_uop_0_pc_lob}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pc_lob = _GEN_292[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_293 = {{stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_23_taken}, {stq_uop_22_taken}, {stq_uop_21_taken}, {stq_uop_20_taken}, {stq_uop_19_taken}, {stq_uop_18_taken}, {stq_uop_17_taken}, {stq_uop_16_taken}, {stq_uop_15_taken}, {stq_uop_14_taken}, {stq_uop_13_taken}, {stq_uop_12_taken}, {stq_uop_11_taken}, {stq_uop_10_taken}, {stq_uop_9_taken}, {stq_uop_8_taken}, {stq_uop_7_taken}, {stq_uop_6_taken}, {stq_uop_5_taken}, {stq_uop_4_taken}, {stq_uop_3_taken}, {stq_uop_2_taken}, {stq_uop_1_taken}, {stq_uop_0_taken}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_taken = _GEN_293[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_294 = {{stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_23_imm_rename}, {stq_uop_22_imm_rename}, {stq_uop_21_imm_rename}, {stq_uop_20_imm_rename}, {stq_uop_19_imm_rename}, {stq_uop_18_imm_rename}, {stq_uop_17_imm_rename}, {stq_uop_16_imm_rename}, {stq_uop_15_imm_rename}, {stq_uop_14_imm_rename}, {stq_uop_13_imm_rename}, {stq_uop_12_imm_rename}, {stq_uop_11_imm_rename}, {stq_uop_10_imm_rename}, {stq_uop_9_imm_rename}, {stq_uop_8_imm_rename}, {stq_uop_7_imm_rename}, {stq_uop_6_imm_rename}, {stq_uop_5_imm_rename}, {stq_uop_4_imm_rename}, {stq_uop_3_imm_rename}, {stq_uop_2_imm_rename}, {stq_uop_1_imm_rename}, {stq_uop_0_imm_rename}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_rename = _GEN_294[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_295 = {{stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_23_imm_sel}, {stq_uop_22_imm_sel}, {stq_uop_21_imm_sel}, {stq_uop_20_imm_sel}, {stq_uop_19_imm_sel}, {stq_uop_18_imm_sel}, {stq_uop_17_imm_sel}, {stq_uop_16_imm_sel}, {stq_uop_15_imm_sel}, {stq_uop_14_imm_sel}, {stq_uop_13_imm_sel}, {stq_uop_12_imm_sel}, {stq_uop_11_imm_sel}, {stq_uop_10_imm_sel}, {stq_uop_9_imm_sel}, {stq_uop_8_imm_sel}, {stq_uop_7_imm_sel}, {stq_uop_6_imm_sel}, {stq_uop_5_imm_sel}, {stq_uop_4_imm_sel}, {stq_uop_3_imm_sel}, {stq_uop_2_imm_sel}, {stq_uop_1_imm_sel}, {stq_uop_0_imm_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_sel = _GEN_295[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_296 = {{stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_23_pimm}, {stq_uop_22_pimm}, {stq_uop_21_pimm}, {stq_uop_20_pimm}, {stq_uop_19_pimm}, {stq_uop_18_pimm}, {stq_uop_17_pimm}, {stq_uop_16_pimm}, {stq_uop_15_pimm}, {stq_uop_14_pimm}, {stq_uop_13_pimm}, {stq_uop_12_pimm}, {stq_uop_11_pimm}, {stq_uop_10_pimm}, {stq_uop_9_pimm}, {stq_uop_8_pimm}, {stq_uop_7_pimm}, {stq_uop_6_pimm}, {stq_uop_5_pimm}, {stq_uop_4_pimm}, {stq_uop_3_pimm}, {stq_uop_2_pimm}, {stq_uop_1_pimm}, {stq_uop_0_pimm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pimm = _GEN_296[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][19:0] _GEN_297 = {{stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_23_imm_packed}, {stq_uop_22_imm_packed}, {stq_uop_21_imm_packed}, {stq_uop_20_imm_packed}, {stq_uop_19_imm_packed}, {stq_uop_18_imm_packed}, {stq_uop_17_imm_packed}, {stq_uop_16_imm_packed}, {stq_uop_15_imm_packed}, {stq_uop_14_imm_packed}, {stq_uop_13_imm_packed}, {stq_uop_12_imm_packed}, {stq_uop_11_imm_packed}, {stq_uop_10_imm_packed}, {stq_uop_9_imm_packed}, {stq_uop_8_imm_packed}, {stq_uop_7_imm_packed}, {stq_uop_6_imm_packed}, {stq_uop_5_imm_packed}, {stq_uop_4_imm_packed}, {stq_uop_3_imm_packed}, {stq_uop_2_imm_packed}, {stq_uop_1_imm_packed}, {stq_uop_0_imm_packed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_packed = _GEN_297[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_298 = {{stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_23_op1_sel}, {stq_uop_22_op1_sel}, {stq_uop_21_op1_sel}, {stq_uop_20_op1_sel}, {stq_uop_19_op1_sel}, {stq_uop_18_op1_sel}, {stq_uop_17_op1_sel}, {stq_uop_16_op1_sel}, {stq_uop_15_op1_sel}, {stq_uop_14_op1_sel}, {stq_uop_13_op1_sel}, {stq_uop_12_op1_sel}, {stq_uop_11_op1_sel}, {stq_uop_10_op1_sel}, {stq_uop_9_op1_sel}, {stq_uop_8_op1_sel}, {stq_uop_7_op1_sel}, {stq_uop_6_op1_sel}, {stq_uop_5_op1_sel}, {stq_uop_4_op1_sel}, {stq_uop_3_op1_sel}, {stq_uop_2_op1_sel}, {stq_uop_1_op1_sel}, {stq_uop_0_op1_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op1_sel = _GEN_298[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_299 = {{stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_23_op2_sel}, {stq_uop_22_op2_sel}, {stq_uop_21_op2_sel}, {stq_uop_20_op2_sel}, {stq_uop_19_op2_sel}, {stq_uop_18_op2_sel}, {stq_uop_17_op2_sel}, {stq_uop_16_op2_sel}, {stq_uop_15_op2_sel}, {stq_uop_14_op2_sel}, {stq_uop_13_op2_sel}, {stq_uop_12_op2_sel}, {stq_uop_11_op2_sel}, {stq_uop_10_op2_sel}, {stq_uop_9_op2_sel}, {stq_uop_8_op2_sel}, {stq_uop_7_op2_sel}, {stq_uop_6_op2_sel}, {stq_uop_5_op2_sel}, {stq_uop_4_op2_sel}, {stq_uop_3_op2_sel}, {stq_uop_2_op2_sel}, {stq_uop_1_op2_sel}, {stq_uop_0_op2_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op2_sel = _GEN_299[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_300 = {{stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_23_fp_ctrl_ldst}, {stq_uop_22_fp_ctrl_ldst}, {stq_uop_21_fp_ctrl_ldst}, {stq_uop_20_fp_ctrl_ldst}, {stq_uop_19_fp_ctrl_ldst}, {stq_uop_18_fp_ctrl_ldst}, {stq_uop_17_fp_ctrl_ldst}, {stq_uop_16_fp_ctrl_ldst}, {stq_uop_15_fp_ctrl_ldst}, {stq_uop_14_fp_ctrl_ldst}, {stq_uop_13_fp_ctrl_ldst}, {stq_uop_12_fp_ctrl_ldst}, {stq_uop_11_fp_ctrl_ldst}, {stq_uop_10_fp_ctrl_ldst}, {stq_uop_9_fp_ctrl_ldst}, {stq_uop_8_fp_ctrl_ldst}, {stq_uop_7_fp_ctrl_ldst}, {stq_uop_6_fp_ctrl_ldst}, {stq_uop_5_fp_ctrl_ldst}, {stq_uop_4_fp_ctrl_ldst}, {stq_uop_3_fp_ctrl_ldst}, {stq_uop_2_fp_ctrl_ldst}, {stq_uop_1_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_301 = {{stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_23_fp_ctrl_wen}, {stq_uop_22_fp_ctrl_wen}, {stq_uop_21_fp_ctrl_wen}, {stq_uop_20_fp_ctrl_wen}, {stq_uop_19_fp_ctrl_wen}, {stq_uop_18_fp_ctrl_wen}, {stq_uop_17_fp_ctrl_wen}, {stq_uop_16_fp_ctrl_wen}, {stq_uop_15_fp_ctrl_wen}, {stq_uop_14_fp_ctrl_wen}, {stq_uop_13_fp_ctrl_wen}, {stq_uop_12_fp_ctrl_wen}, {stq_uop_11_fp_ctrl_wen}, {stq_uop_10_fp_ctrl_wen}, {stq_uop_9_fp_ctrl_wen}, {stq_uop_8_fp_ctrl_wen}, {stq_uop_7_fp_ctrl_wen}, {stq_uop_6_fp_ctrl_wen}, {stq_uop_5_fp_ctrl_wen}, {stq_uop_4_fp_ctrl_wen}, {stq_uop_3_fp_ctrl_wen}, {stq_uop_2_fp_ctrl_wen}, {stq_uop_1_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_302 = {{stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_23_fp_ctrl_ren1}, {stq_uop_22_fp_ctrl_ren1}, {stq_uop_21_fp_ctrl_ren1}, {stq_uop_20_fp_ctrl_ren1}, {stq_uop_19_fp_ctrl_ren1}, {stq_uop_18_fp_ctrl_ren1}, {stq_uop_17_fp_ctrl_ren1}, {stq_uop_16_fp_ctrl_ren1}, {stq_uop_15_fp_ctrl_ren1}, {stq_uop_14_fp_ctrl_ren1}, {stq_uop_13_fp_ctrl_ren1}, {stq_uop_12_fp_ctrl_ren1}, {stq_uop_11_fp_ctrl_ren1}, {stq_uop_10_fp_ctrl_ren1}, {stq_uop_9_fp_ctrl_ren1}, {stq_uop_8_fp_ctrl_ren1}, {stq_uop_7_fp_ctrl_ren1}, {stq_uop_6_fp_ctrl_ren1}, {stq_uop_5_fp_ctrl_ren1}, {stq_uop_4_fp_ctrl_ren1}, {stq_uop_3_fp_ctrl_ren1}, {stq_uop_2_fp_ctrl_ren1}, {stq_uop_1_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_303 = {{stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_23_fp_ctrl_ren2}, {stq_uop_22_fp_ctrl_ren2}, {stq_uop_21_fp_ctrl_ren2}, {stq_uop_20_fp_ctrl_ren2}, {stq_uop_19_fp_ctrl_ren2}, {stq_uop_18_fp_ctrl_ren2}, {stq_uop_17_fp_ctrl_ren2}, {stq_uop_16_fp_ctrl_ren2}, {stq_uop_15_fp_ctrl_ren2}, {stq_uop_14_fp_ctrl_ren2}, {stq_uop_13_fp_ctrl_ren2}, {stq_uop_12_fp_ctrl_ren2}, {stq_uop_11_fp_ctrl_ren2}, {stq_uop_10_fp_ctrl_ren2}, {stq_uop_9_fp_ctrl_ren2}, {stq_uop_8_fp_ctrl_ren2}, {stq_uop_7_fp_ctrl_ren2}, {stq_uop_6_fp_ctrl_ren2}, {stq_uop_5_fp_ctrl_ren2}, {stq_uop_4_fp_ctrl_ren2}, {stq_uop_3_fp_ctrl_ren2}, {stq_uop_2_fp_ctrl_ren2}, {stq_uop_1_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_304 = {{stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_23_fp_ctrl_ren3}, {stq_uop_22_fp_ctrl_ren3}, {stq_uop_21_fp_ctrl_ren3}, {stq_uop_20_fp_ctrl_ren3}, {stq_uop_19_fp_ctrl_ren3}, {stq_uop_18_fp_ctrl_ren3}, {stq_uop_17_fp_ctrl_ren3}, {stq_uop_16_fp_ctrl_ren3}, {stq_uop_15_fp_ctrl_ren3}, {stq_uop_14_fp_ctrl_ren3}, {stq_uop_13_fp_ctrl_ren3}, {stq_uop_12_fp_ctrl_ren3}, {stq_uop_11_fp_ctrl_ren3}, {stq_uop_10_fp_ctrl_ren3}, {stq_uop_9_fp_ctrl_ren3}, {stq_uop_8_fp_ctrl_ren3}, {stq_uop_7_fp_ctrl_ren3}, {stq_uop_6_fp_ctrl_ren3}, {stq_uop_5_fp_ctrl_ren3}, {stq_uop_4_fp_ctrl_ren3}, {stq_uop_3_fp_ctrl_ren3}, {stq_uop_2_fp_ctrl_ren3}, {stq_uop_1_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_305 = {{stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_23_fp_ctrl_swap12}, {stq_uop_22_fp_ctrl_swap12}, {stq_uop_21_fp_ctrl_swap12}, {stq_uop_20_fp_ctrl_swap12}, {stq_uop_19_fp_ctrl_swap12}, {stq_uop_18_fp_ctrl_swap12}, {stq_uop_17_fp_ctrl_swap12}, {stq_uop_16_fp_ctrl_swap12}, {stq_uop_15_fp_ctrl_swap12}, {stq_uop_14_fp_ctrl_swap12}, {stq_uop_13_fp_ctrl_swap12}, {stq_uop_12_fp_ctrl_swap12}, {stq_uop_11_fp_ctrl_swap12}, {stq_uop_10_fp_ctrl_swap12}, {stq_uop_9_fp_ctrl_swap12}, {stq_uop_8_fp_ctrl_swap12}, {stq_uop_7_fp_ctrl_swap12}, {stq_uop_6_fp_ctrl_swap12}, {stq_uop_5_fp_ctrl_swap12}, {stq_uop_4_fp_ctrl_swap12}, {stq_uop_3_fp_ctrl_swap12}, {stq_uop_2_fp_ctrl_swap12}, {stq_uop_1_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_306 = {{stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_23_fp_ctrl_swap23}, {stq_uop_22_fp_ctrl_swap23}, {stq_uop_21_fp_ctrl_swap23}, {stq_uop_20_fp_ctrl_swap23}, {stq_uop_19_fp_ctrl_swap23}, {stq_uop_18_fp_ctrl_swap23}, {stq_uop_17_fp_ctrl_swap23}, {stq_uop_16_fp_ctrl_swap23}, {stq_uop_15_fp_ctrl_swap23}, {stq_uop_14_fp_ctrl_swap23}, {stq_uop_13_fp_ctrl_swap23}, {stq_uop_12_fp_ctrl_swap23}, {stq_uop_11_fp_ctrl_swap23}, {stq_uop_10_fp_ctrl_swap23}, {stq_uop_9_fp_ctrl_swap23}, {stq_uop_8_fp_ctrl_swap23}, {stq_uop_7_fp_ctrl_swap23}, {stq_uop_6_fp_ctrl_swap23}, {stq_uop_5_fp_ctrl_swap23}, {stq_uop_4_fp_ctrl_swap23}, {stq_uop_3_fp_ctrl_swap23}, {stq_uop_2_fp_ctrl_swap23}, {stq_uop_1_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_307 = {{stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_23_fp_ctrl_typeTagIn}, {stq_uop_22_fp_ctrl_typeTagIn}, {stq_uop_21_fp_ctrl_typeTagIn}, {stq_uop_20_fp_ctrl_typeTagIn}, {stq_uop_19_fp_ctrl_typeTagIn}, {stq_uop_18_fp_ctrl_typeTagIn}, {stq_uop_17_fp_ctrl_typeTagIn}, {stq_uop_16_fp_ctrl_typeTagIn}, {stq_uop_15_fp_ctrl_typeTagIn}, {stq_uop_14_fp_ctrl_typeTagIn}, {stq_uop_13_fp_ctrl_typeTagIn}, {stq_uop_12_fp_ctrl_typeTagIn}, {stq_uop_11_fp_ctrl_typeTagIn}, {stq_uop_10_fp_ctrl_typeTagIn}, {stq_uop_9_fp_ctrl_typeTagIn}, {stq_uop_8_fp_ctrl_typeTagIn}, {stq_uop_7_fp_ctrl_typeTagIn}, {stq_uop_6_fp_ctrl_typeTagIn}, {stq_uop_5_fp_ctrl_typeTagIn}, {stq_uop_4_fp_ctrl_typeTagIn}, {stq_uop_3_fp_ctrl_typeTagIn}, {stq_uop_2_fp_ctrl_typeTagIn}, {stq_uop_1_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_308 = {{stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_23_fp_ctrl_typeTagOut}, {stq_uop_22_fp_ctrl_typeTagOut}, {stq_uop_21_fp_ctrl_typeTagOut}, {stq_uop_20_fp_ctrl_typeTagOut}, {stq_uop_19_fp_ctrl_typeTagOut}, {stq_uop_18_fp_ctrl_typeTagOut}, {stq_uop_17_fp_ctrl_typeTagOut}, {stq_uop_16_fp_ctrl_typeTagOut}, {stq_uop_15_fp_ctrl_typeTagOut}, {stq_uop_14_fp_ctrl_typeTagOut}, {stq_uop_13_fp_ctrl_typeTagOut}, {stq_uop_12_fp_ctrl_typeTagOut}, {stq_uop_11_fp_ctrl_typeTagOut}, {stq_uop_10_fp_ctrl_typeTagOut}, {stq_uop_9_fp_ctrl_typeTagOut}, {stq_uop_8_fp_ctrl_typeTagOut}, {stq_uop_7_fp_ctrl_typeTagOut}, {stq_uop_6_fp_ctrl_typeTagOut}, {stq_uop_5_fp_ctrl_typeTagOut}, {stq_uop_4_fp_ctrl_typeTagOut}, {stq_uop_3_fp_ctrl_typeTagOut}, {stq_uop_2_fp_ctrl_typeTagOut}, {stq_uop_1_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_309 = {{stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_23_fp_ctrl_fromint}, {stq_uop_22_fp_ctrl_fromint}, {stq_uop_21_fp_ctrl_fromint}, {stq_uop_20_fp_ctrl_fromint}, {stq_uop_19_fp_ctrl_fromint}, {stq_uop_18_fp_ctrl_fromint}, {stq_uop_17_fp_ctrl_fromint}, {stq_uop_16_fp_ctrl_fromint}, {stq_uop_15_fp_ctrl_fromint}, {stq_uop_14_fp_ctrl_fromint}, {stq_uop_13_fp_ctrl_fromint}, {stq_uop_12_fp_ctrl_fromint}, {stq_uop_11_fp_ctrl_fromint}, {stq_uop_10_fp_ctrl_fromint}, {stq_uop_9_fp_ctrl_fromint}, {stq_uop_8_fp_ctrl_fromint}, {stq_uop_7_fp_ctrl_fromint}, {stq_uop_6_fp_ctrl_fromint}, {stq_uop_5_fp_ctrl_fromint}, {stq_uop_4_fp_ctrl_fromint}, {stq_uop_3_fp_ctrl_fromint}, {stq_uop_2_fp_ctrl_fromint}, {stq_uop_1_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_310 = {{stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_23_fp_ctrl_toint}, {stq_uop_22_fp_ctrl_toint}, {stq_uop_21_fp_ctrl_toint}, {stq_uop_20_fp_ctrl_toint}, {stq_uop_19_fp_ctrl_toint}, {stq_uop_18_fp_ctrl_toint}, {stq_uop_17_fp_ctrl_toint}, {stq_uop_16_fp_ctrl_toint}, {stq_uop_15_fp_ctrl_toint}, {stq_uop_14_fp_ctrl_toint}, {stq_uop_13_fp_ctrl_toint}, {stq_uop_12_fp_ctrl_toint}, {stq_uop_11_fp_ctrl_toint}, {stq_uop_10_fp_ctrl_toint}, {stq_uop_9_fp_ctrl_toint}, {stq_uop_8_fp_ctrl_toint}, {stq_uop_7_fp_ctrl_toint}, {stq_uop_6_fp_ctrl_toint}, {stq_uop_5_fp_ctrl_toint}, {stq_uop_4_fp_ctrl_toint}, {stq_uop_3_fp_ctrl_toint}, {stq_uop_2_fp_ctrl_toint}, {stq_uop_1_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_311 = {{stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_23_fp_ctrl_fastpipe}, {stq_uop_22_fp_ctrl_fastpipe}, {stq_uop_21_fp_ctrl_fastpipe}, {stq_uop_20_fp_ctrl_fastpipe}, {stq_uop_19_fp_ctrl_fastpipe}, {stq_uop_18_fp_ctrl_fastpipe}, {stq_uop_17_fp_ctrl_fastpipe}, {stq_uop_16_fp_ctrl_fastpipe}, {stq_uop_15_fp_ctrl_fastpipe}, {stq_uop_14_fp_ctrl_fastpipe}, {stq_uop_13_fp_ctrl_fastpipe}, {stq_uop_12_fp_ctrl_fastpipe}, {stq_uop_11_fp_ctrl_fastpipe}, {stq_uop_10_fp_ctrl_fastpipe}, {stq_uop_9_fp_ctrl_fastpipe}, {stq_uop_8_fp_ctrl_fastpipe}, {stq_uop_7_fp_ctrl_fastpipe}, {stq_uop_6_fp_ctrl_fastpipe}, {stq_uop_5_fp_ctrl_fastpipe}, {stq_uop_4_fp_ctrl_fastpipe}, {stq_uop_3_fp_ctrl_fastpipe}, {stq_uop_2_fp_ctrl_fastpipe}, {stq_uop_1_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_312 = {{stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_23_fp_ctrl_fma}, {stq_uop_22_fp_ctrl_fma}, {stq_uop_21_fp_ctrl_fma}, {stq_uop_20_fp_ctrl_fma}, {stq_uop_19_fp_ctrl_fma}, {stq_uop_18_fp_ctrl_fma}, {stq_uop_17_fp_ctrl_fma}, {stq_uop_16_fp_ctrl_fma}, {stq_uop_15_fp_ctrl_fma}, {stq_uop_14_fp_ctrl_fma}, {stq_uop_13_fp_ctrl_fma}, {stq_uop_12_fp_ctrl_fma}, {stq_uop_11_fp_ctrl_fma}, {stq_uop_10_fp_ctrl_fma}, {stq_uop_9_fp_ctrl_fma}, {stq_uop_8_fp_ctrl_fma}, {stq_uop_7_fp_ctrl_fma}, {stq_uop_6_fp_ctrl_fma}, {stq_uop_5_fp_ctrl_fma}, {stq_uop_4_fp_ctrl_fma}, {stq_uop_3_fp_ctrl_fma}, {stq_uop_2_fp_ctrl_fma}, {stq_uop_1_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_313 = {{stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_23_fp_ctrl_div}, {stq_uop_22_fp_ctrl_div}, {stq_uop_21_fp_ctrl_div}, {stq_uop_20_fp_ctrl_div}, {stq_uop_19_fp_ctrl_div}, {stq_uop_18_fp_ctrl_div}, {stq_uop_17_fp_ctrl_div}, {stq_uop_16_fp_ctrl_div}, {stq_uop_15_fp_ctrl_div}, {stq_uop_14_fp_ctrl_div}, {stq_uop_13_fp_ctrl_div}, {stq_uop_12_fp_ctrl_div}, {stq_uop_11_fp_ctrl_div}, {stq_uop_10_fp_ctrl_div}, {stq_uop_9_fp_ctrl_div}, {stq_uop_8_fp_ctrl_div}, {stq_uop_7_fp_ctrl_div}, {stq_uop_6_fp_ctrl_div}, {stq_uop_5_fp_ctrl_div}, {stq_uop_4_fp_ctrl_div}, {stq_uop_3_fp_ctrl_div}, {stq_uop_2_fp_ctrl_div}, {stq_uop_1_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_314 = {{stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_23_fp_ctrl_sqrt}, {stq_uop_22_fp_ctrl_sqrt}, {stq_uop_21_fp_ctrl_sqrt}, {stq_uop_20_fp_ctrl_sqrt}, {stq_uop_19_fp_ctrl_sqrt}, {stq_uop_18_fp_ctrl_sqrt}, {stq_uop_17_fp_ctrl_sqrt}, {stq_uop_16_fp_ctrl_sqrt}, {stq_uop_15_fp_ctrl_sqrt}, {stq_uop_14_fp_ctrl_sqrt}, {stq_uop_13_fp_ctrl_sqrt}, {stq_uop_12_fp_ctrl_sqrt}, {stq_uop_11_fp_ctrl_sqrt}, {stq_uop_10_fp_ctrl_sqrt}, {stq_uop_9_fp_ctrl_sqrt}, {stq_uop_8_fp_ctrl_sqrt}, {stq_uop_7_fp_ctrl_sqrt}, {stq_uop_6_fp_ctrl_sqrt}, {stq_uop_5_fp_ctrl_sqrt}, {stq_uop_4_fp_ctrl_sqrt}, {stq_uop_3_fp_ctrl_sqrt}, {stq_uop_2_fp_ctrl_sqrt}, {stq_uop_1_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_315 = {{stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_23_fp_ctrl_wflags}, {stq_uop_22_fp_ctrl_wflags}, {stq_uop_21_fp_ctrl_wflags}, {stq_uop_20_fp_ctrl_wflags}, {stq_uop_19_fp_ctrl_wflags}, {stq_uop_18_fp_ctrl_wflags}, {stq_uop_17_fp_ctrl_wflags}, {stq_uop_16_fp_ctrl_wflags}, {stq_uop_15_fp_ctrl_wflags}, {stq_uop_14_fp_ctrl_wflags}, {stq_uop_13_fp_ctrl_wflags}, {stq_uop_12_fp_ctrl_wflags}, {stq_uop_11_fp_ctrl_wflags}, {stq_uop_10_fp_ctrl_wflags}, {stq_uop_9_fp_ctrl_wflags}, {stq_uop_8_fp_ctrl_wflags}, {stq_uop_7_fp_ctrl_wflags}, {stq_uop_6_fp_ctrl_wflags}, {stq_uop_5_fp_ctrl_wflags}, {stq_uop_4_fp_ctrl_wflags}, {stq_uop_3_fp_ctrl_wflags}, {stq_uop_2_fp_ctrl_wflags}, {stq_uop_1_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_316 = {{stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_23_fp_ctrl_vec}, {stq_uop_22_fp_ctrl_vec}, {stq_uop_21_fp_ctrl_vec}, {stq_uop_20_fp_ctrl_vec}, {stq_uop_19_fp_ctrl_vec}, {stq_uop_18_fp_ctrl_vec}, {stq_uop_17_fp_ctrl_vec}, {stq_uop_16_fp_ctrl_vec}, {stq_uop_15_fp_ctrl_vec}, {stq_uop_14_fp_ctrl_vec}, {stq_uop_13_fp_ctrl_vec}, {stq_uop_12_fp_ctrl_vec}, {stq_uop_11_fp_ctrl_vec}, {stq_uop_10_fp_ctrl_vec}, {stq_uop_9_fp_ctrl_vec}, {stq_uop_8_fp_ctrl_vec}, {stq_uop_7_fp_ctrl_vec}, {stq_uop_6_fp_ctrl_vec}, {stq_uop_5_fp_ctrl_vec}, {stq_uop_4_fp_ctrl_vec}, {stq_uop_3_fp_ctrl_vec}, {stq_uop_2_fp_ctrl_vec}, {stq_uop_1_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_317 = {{stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_23_rob_idx}, {stq_uop_22_rob_idx}, {stq_uop_21_rob_idx}, {stq_uop_20_rob_idx}, {stq_uop_19_rob_idx}, {stq_uop_18_rob_idx}, {stq_uop_17_rob_idx}, {stq_uop_16_rob_idx}, {stq_uop_15_rob_idx}, {stq_uop_14_rob_idx}, {stq_uop_13_rob_idx}, {stq_uop_12_rob_idx}, {stq_uop_11_rob_idx}, {stq_uop_10_rob_idx}, {stq_uop_9_rob_idx}, {stq_uop_8_rob_idx}, {stq_uop_7_rob_idx}, {stq_uop_6_rob_idx}, {stq_uop_5_rob_idx}, {stq_uop_4_rob_idx}, {stq_uop_3_rob_idx}, {stq_uop_2_rob_idx}, {stq_uop_1_rob_idx}, {stq_uop_0_rob_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rob_idx = _GEN_317[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_318 = {{stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_23_ldq_idx}, {stq_uop_22_ldq_idx}, {stq_uop_21_ldq_idx}, {stq_uop_20_ldq_idx}, {stq_uop_19_ldq_idx}, {stq_uop_18_ldq_idx}, {stq_uop_17_ldq_idx}, {stq_uop_16_ldq_idx}, {stq_uop_15_ldq_idx}, {stq_uop_14_ldq_idx}, {stq_uop_13_ldq_idx}, {stq_uop_12_ldq_idx}, {stq_uop_11_ldq_idx}, {stq_uop_10_ldq_idx}, {stq_uop_9_ldq_idx}, {stq_uop_8_ldq_idx}, {stq_uop_7_ldq_idx}, {stq_uop_6_ldq_idx}, {stq_uop_5_ldq_idx}, {stq_uop_4_ldq_idx}, {stq_uop_3_ldq_idx}, {stq_uop_2_ldq_idx}, {stq_uop_1_ldq_idx}, {stq_uop_0_ldq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldq_idx = _GEN_318[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_319 = {{stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_23_stq_idx}, {stq_uop_22_stq_idx}, {stq_uop_21_stq_idx}, {stq_uop_20_stq_idx}, {stq_uop_19_stq_idx}, {stq_uop_18_stq_idx}, {stq_uop_17_stq_idx}, {stq_uop_16_stq_idx}, {stq_uop_15_stq_idx}, {stq_uop_14_stq_idx}, {stq_uop_13_stq_idx}, {stq_uop_12_stq_idx}, {stq_uop_11_stq_idx}, {stq_uop_10_stq_idx}, {stq_uop_9_stq_idx}, {stq_uop_8_stq_idx}, {stq_uop_7_stq_idx}, {stq_uop_6_stq_idx}, {stq_uop_5_stq_idx}, {stq_uop_4_stq_idx}, {stq_uop_3_stq_idx}, {stq_uop_2_stq_idx}, {stq_uop_1_stq_idx}, {stq_uop_0_stq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stq_idx = _GEN_319[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_320 = {{stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_23_rxq_idx}, {stq_uop_22_rxq_idx}, {stq_uop_21_rxq_idx}, {stq_uop_20_rxq_idx}, {stq_uop_19_rxq_idx}, {stq_uop_18_rxq_idx}, {stq_uop_17_rxq_idx}, {stq_uop_16_rxq_idx}, {stq_uop_15_rxq_idx}, {stq_uop_14_rxq_idx}, {stq_uop_13_rxq_idx}, {stq_uop_12_rxq_idx}, {stq_uop_11_rxq_idx}, {stq_uop_10_rxq_idx}, {stq_uop_9_rxq_idx}, {stq_uop_8_rxq_idx}, {stq_uop_7_rxq_idx}, {stq_uop_6_rxq_idx}, {stq_uop_5_rxq_idx}, {stq_uop_4_rxq_idx}, {stq_uop_3_rxq_idx}, {stq_uop_2_rxq_idx}, {stq_uop_1_rxq_idx}, {stq_uop_0_rxq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rxq_idx = _GEN_320[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_321 = {{stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_23_pdst}, {stq_uop_22_pdst}, {stq_uop_21_pdst}, {stq_uop_20_pdst}, {stq_uop_19_pdst}, {stq_uop_18_pdst}, {stq_uop_17_pdst}, {stq_uop_16_pdst}, {stq_uop_15_pdst}, {stq_uop_14_pdst}, {stq_uop_13_pdst}, {stq_uop_12_pdst}, {stq_uop_11_pdst}, {stq_uop_10_pdst}, {stq_uop_9_pdst}, {stq_uop_8_pdst}, {stq_uop_7_pdst}, {stq_uop_6_pdst}, {stq_uop_5_pdst}, {stq_uop_4_pdst}, {stq_uop_3_pdst}, {stq_uop_2_pdst}, {stq_uop_1_pdst}, {stq_uop_0_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pdst = _GEN_321[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_322 = {{stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_23_prs1}, {stq_uop_22_prs1}, {stq_uop_21_prs1}, {stq_uop_20_prs1}, {stq_uop_19_prs1}, {stq_uop_18_prs1}, {stq_uop_17_prs1}, {stq_uop_16_prs1}, {stq_uop_15_prs1}, {stq_uop_14_prs1}, {stq_uop_13_prs1}, {stq_uop_12_prs1}, {stq_uop_11_prs1}, {stq_uop_10_prs1}, {stq_uop_9_prs1}, {stq_uop_8_prs1}, {stq_uop_7_prs1}, {stq_uop_6_prs1}, {stq_uop_5_prs1}, {stq_uop_4_prs1}, {stq_uop_3_prs1}, {stq_uop_2_prs1}, {stq_uop_1_prs1}, {stq_uop_0_prs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1 = _GEN_322[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_323 = {{stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_23_prs2}, {stq_uop_22_prs2}, {stq_uop_21_prs2}, {stq_uop_20_prs2}, {stq_uop_19_prs2}, {stq_uop_18_prs2}, {stq_uop_17_prs2}, {stq_uop_16_prs2}, {stq_uop_15_prs2}, {stq_uop_14_prs2}, {stq_uop_13_prs2}, {stq_uop_12_prs2}, {stq_uop_11_prs2}, {stq_uop_10_prs2}, {stq_uop_9_prs2}, {stq_uop_8_prs2}, {stq_uop_7_prs2}, {stq_uop_6_prs2}, {stq_uop_5_prs2}, {stq_uop_4_prs2}, {stq_uop_3_prs2}, {stq_uop_2_prs2}, {stq_uop_1_prs2}, {stq_uop_0_prs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2 = _GEN_323[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_324 = {{stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_23_prs3}, {stq_uop_22_prs3}, {stq_uop_21_prs3}, {stq_uop_20_prs3}, {stq_uop_19_prs3}, {stq_uop_18_prs3}, {stq_uop_17_prs3}, {stq_uop_16_prs3}, {stq_uop_15_prs3}, {stq_uop_14_prs3}, {stq_uop_13_prs3}, {stq_uop_12_prs3}, {stq_uop_11_prs3}, {stq_uop_10_prs3}, {stq_uop_9_prs3}, {stq_uop_8_prs3}, {stq_uop_7_prs3}, {stq_uop_6_prs3}, {stq_uop_5_prs3}, {stq_uop_4_prs3}, {stq_uop_3_prs3}, {stq_uop_2_prs3}, {stq_uop_1_prs3}, {stq_uop_0_prs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3 = _GEN_324[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_325 = {{stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_23_ppred}, {stq_uop_22_ppred}, {stq_uop_21_ppred}, {stq_uop_20_ppred}, {stq_uop_19_ppred}, {stq_uop_18_ppred}, {stq_uop_17_ppred}, {stq_uop_16_ppred}, {stq_uop_15_ppred}, {stq_uop_14_ppred}, {stq_uop_13_ppred}, {stq_uop_12_ppred}, {stq_uop_11_ppred}, {stq_uop_10_ppred}, {stq_uop_9_ppred}, {stq_uop_8_ppred}, {stq_uop_7_ppred}, {stq_uop_6_ppred}, {stq_uop_5_ppred}, {stq_uop_4_ppred}, {stq_uop_3_ppred}, {stq_uop_2_ppred}, {stq_uop_1_ppred}, {stq_uop_0_ppred}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred = _GEN_325[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_326 = {{stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_23_prs1_busy}, {stq_uop_22_prs1_busy}, {stq_uop_21_prs1_busy}, {stq_uop_20_prs1_busy}, {stq_uop_19_prs1_busy}, {stq_uop_18_prs1_busy}, {stq_uop_17_prs1_busy}, {stq_uop_16_prs1_busy}, {stq_uop_15_prs1_busy}, {stq_uop_14_prs1_busy}, {stq_uop_13_prs1_busy}, {stq_uop_12_prs1_busy}, {stq_uop_11_prs1_busy}, {stq_uop_10_prs1_busy}, {stq_uop_9_prs1_busy}, {stq_uop_8_prs1_busy}, {stq_uop_7_prs1_busy}, {stq_uop_6_prs1_busy}, {stq_uop_5_prs1_busy}, {stq_uop_4_prs1_busy}, {stq_uop_3_prs1_busy}, {stq_uop_2_prs1_busy}, {stq_uop_1_prs1_busy}, {stq_uop_0_prs1_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1_busy = _GEN_326[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_327 = {{stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_23_prs2_busy}, {stq_uop_22_prs2_busy}, {stq_uop_21_prs2_busy}, {stq_uop_20_prs2_busy}, {stq_uop_19_prs2_busy}, {stq_uop_18_prs2_busy}, {stq_uop_17_prs2_busy}, {stq_uop_16_prs2_busy}, {stq_uop_15_prs2_busy}, {stq_uop_14_prs2_busy}, {stq_uop_13_prs2_busy}, {stq_uop_12_prs2_busy}, {stq_uop_11_prs2_busy}, {stq_uop_10_prs2_busy}, {stq_uop_9_prs2_busy}, {stq_uop_8_prs2_busy}, {stq_uop_7_prs2_busy}, {stq_uop_6_prs2_busy}, {stq_uop_5_prs2_busy}, {stq_uop_4_prs2_busy}, {stq_uop_3_prs2_busy}, {stq_uop_2_prs2_busy}, {stq_uop_1_prs2_busy}, {stq_uop_0_prs2_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2_busy = _GEN_327[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_328 = {{stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_23_prs3_busy}, {stq_uop_22_prs3_busy}, {stq_uop_21_prs3_busy}, {stq_uop_20_prs3_busy}, {stq_uop_19_prs3_busy}, {stq_uop_18_prs3_busy}, {stq_uop_17_prs3_busy}, {stq_uop_16_prs3_busy}, {stq_uop_15_prs3_busy}, {stq_uop_14_prs3_busy}, {stq_uop_13_prs3_busy}, {stq_uop_12_prs3_busy}, {stq_uop_11_prs3_busy}, {stq_uop_10_prs3_busy}, {stq_uop_9_prs3_busy}, {stq_uop_8_prs3_busy}, {stq_uop_7_prs3_busy}, {stq_uop_6_prs3_busy}, {stq_uop_5_prs3_busy}, {stq_uop_4_prs3_busy}, {stq_uop_3_prs3_busy}, {stq_uop_2_prs3_busy}, {stq_uop_1_prs3_busy}, {stq_uop_0_prs3_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3_busy = _GEN_328[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_329 = {{stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_23_ppred_busy}, {stq_uop_22_ppred_busy}, {stq_uop_21_ppred_busy}, {stq_uop_20_ppred_busy}, {stq_uop_19_ppred_busy}, {stq_uop_18_ppred_busy}, {stq_uop_17_ppred_busy}, {stq_uop_16_ppred_busy}, {stq_uop_15_ppred_busy}, {stq_uop_14_ppred_busy}, {stq_uop_13_ppred_busy}, {stq_uop_12_ppred_busy}, {stq_uop_11_ppred_busy}, {stq_uop_10_ppred_busy}, {stq_uop_9_ppred_busy}, {stq_uop_8_ppred_busy}, {stq_uop_7_ppred_busy}, {stq_uop_6_ppred_busy}, {stq_uop_5_ppred_busy}, {stq_uop_4_ppred_busy}, {stq_uop_3_ppred_busy}, {stq_uop_2_ppred_busy}, {stq_uop_1_ppred_busy}, {stq_uop_0_ppred_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred_busy = _GEN_329[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_330 = {{stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_23_stale_pdst}, {stq_uop_22_stale_pdst}, {stq_uop_21_stale_pdst}, {stq_uop_20_stale_pdst}, {stq_uop_19_stale_pdst}, {stq_uop_18_stale_pdst}, {stq_uop_17_stale_pdst}, {stq_uop_16_stale_pdst}, {stq_uop_15_stale_pdst}, {stq_uop_14_stale_pdst}, {stq_uop_13_stale_pdst}, {stq_uop_12_stale_pdst}, {stq_uop_11_stale_pdst}, {stq_uop_10_stale_pdst}, {stq_uop_9_stale_pdst}, {stq_uop_8_stale_pdst}, {stq_uop_7_stale_pdst}, {stq_uop_6_stale_pdst}, {stq_uop_5_stale_pdst}, {stq_uop_4_stale_pdst}, {stq_uop_3_stale_pdst}, {stq_uop_2_stale_pdst}, {stq_uop_1_stale_pdst}, {stq_uop_0_stale_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stale_pdst = _GEN_330[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_331 = {{stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_23_exception}, {stq_uop_22_exception}, {stq_uop_21_exception}, {stq_uop_20_exception}, {stq_uop_19_exception}, {stq_uop_18_exception}, {stq_uop_17_exception}, {stq_uop_16_exception}, {stq_uop_15_exception}, {stq_uop_14_exception}, {stq_uop_13_exception}, {stq_uop_12_exception}, {stq_uop_11_exception}, {stq_uop_10_exception}, {stq_uop_9_exception}, {stq_uop_8_exception}, {stq_uop_7_exception}, {stq_uop_6_exception}, {stq_uop_5_exception}, {stq_uop_4_exception}, {stq_uop_3_exception}, {stq_uop_2_exception}, {stq_uop_1_exception}, {stq_uop_0_exception}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exception = _GEN_331[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][63:0] _GEN_332 = {{stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_23_exc_cause}, {stq_uop_22_exc_cause}, {stq_uop_21_exc_cause}, {stq_uop_20_exc_cause}, {stq_uop_19_exc_cause}, {stq_uop_18_exc_cause}, {stq_uop_17_exc_cause}, {stq_uop_16_exc_cause}, {stq_uop_15_exc_cause}, {stq_uop_14_exc_cause}, {stq_uop_13_exc_cause}, {stq_uop_12_exc_cause}, {stq_uop_11_exc_cause}, {stq_uop_10_exc_cause}, {stq_uop_9_exc_cause}, {stq_uop_8_exc_cause}, {stq_uop_7_exc_cause}, {stq_uop_6_exc_cause}, {stq_uop_5_exc_cause}, {stq_uop_4_exc_cause}, {stq_uop_3_exc_cause}, {stq_uop_2_exc_cause}, {stq_uop_1_exc_cause}, {stq_uop_0_exc_cause}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exc_cause = _GEN_332[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_333 = {{stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_23_mem_cmd}, {stq_uop_22_mem_cmd}, {stq_uop_21_mem_cmd}, {stq_uop_20_mem_cmd}, {stq_uop_19_mem_cmd}, {stq_uop_18_mem_cmd}, {stq_uop_17_mem_cmd}, {stq_uop_16_mem_cmd}, {stq_uop_15_mem_cmd}, {stq_uop_14_mem_cmd}, {stq_uop_13_mem_cmd}, {stq_uop_12_mem_cmd}, {stq_uop_11_mem_cmd}, {stq_uop_10_mem_cmd}, {stq_uop_9_mem_cmd}, {stq_uop_8_mem_cmd}, {stq_uop_7_mem_cmd}, {stq_uop_6_mem_cmd}, {stq_uop_5_mem_cmd}, {stq_uop_4_mem_cmd}, {stq_uop_3_mem_cmd}, {stq_uop_2_mem_cmd}, {stq_uop_1_mem_cmd}, {stq_uop_0_mem_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_cmd = _GEN_333[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_334 = {{stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_23_mem_size}, {stq_uop_22_mem_size}, {stq_uop_21_mem_size}, {stq_uop_20_mem_size}, {stq_uop_19_mem_size}, {stq_uop_18_mem_size}, {stq_uop_17_mem_size}, {stq_uop_16_mem_size}, {stq_uop_15_mem_size}, {stq_uop_14_mem_size}, {stq_uop_13_mem_size}, {stq_uop_12_mem_size}, {stq_uop_11_mem_size}, {stq_uop_10_mem_size}, {stq_uop_9_mem_size}, {stq_uop_8_mem_size}, {stq_uop_7_mem_size}, {stq_uop_6_mem_size}, {stq_uop_5_mem_size}, {stq_uop_4_mem_size}, {stq_uop_3_mem_size}, {stq_uop_2_mem_size}, {stq_uop_1_mem_size}, {stq_uop_0_mem_size}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_size = _GEN_334[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_335 = {{stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_23_mem_signed}, {stq_uop_22_mem_signed}, {stq_uop_21_mem_signed}, {stq_uop_20_mem_signed}, {stq_uop_19_mem_signed}, {stq_uop_18_mem_signed}, {stq_uop_17_mem_signed}, {stq_uop_16_mem_signed}, {stq_uop_15_mem_signed}, {stq_uop_14_mem_signed}, {stq_uop_13_mem_signed}, {stq_uop_12_mem_signed}, {stq_uop_11_mem_signed}, {stq_uop_10_mem_signed}, {stq_uop_9_mem_signed}, {stq_uop_8_mem_signed}, {stq_uop_7_mem_signed}, {stq_uop_6_mem_signed}, {stq_uop_5_mem_signed}, {stq_uop_4_mem_signed}, {stq_uop_3_mem_signed}, {stq_uop_2_mem_signed}, {stq_uop_1_mem_signed}, {stq_uop_0_mem_signed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_signed = _GEN_335[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_336 = {{stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_23_uses_ldq}, {stq_uop_22_uses_ldq}, {stq_uop_21_uses_ldq}, {stq_uop_20_uses_ldq}, {stq_uop_19_uses_ldq}, {stq_uop_18_uses_ldq}, {stq_uop_17_uses_ldq}, {stq_uop_16_uses_ldq}, {stq_uop_15_uses_ldq}, {stq_uop_14_uses_ldq}, {stq_uop_13_uses_ldq}, {stq_uop_12_uses_ldq}, {stq_uop_11_uses_ldq}, {stq_uop_10_uses_ldq}, {stq_uop_9_uses_ldq}, {stq_uop_8_uses_ldq}, {stq_uop_7_uses_ldq}, {stq_uop_6_uses_ldq}, {stq_uop_5_uses_ldq}, {stq_uop_4_uses_ldq}, {stq_uop_3_uses_ldq}, {stq_uop_2_uses_ldq}, {stq_uop_1_uses_ldq}, {stq_uop_0_uses_ldq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_ldq = _GEN_336[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_337 = {{stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_23_uses_stq}, {stq_uop_22_uses_stq}, {stq_uop_21_uses_stq}, {stq_uop_20_uses_stq}, {stq_uop_19_uses_stq}, {stq_uop_18_uses_stq}, {stq_uop_17_uses_stq}, {stq_uop_16_uses_stq}, {stq_uop_15_uses_stq}, {stq_uop_14_uses_stq}, {stq_uop_13_uses_stq}, {stq_uop_12_uses_stq}, {stq_uop_11_uses_stq}, {stq_uop_10_uses_stq}, {stq_uop_9_uses_stq}, {stq_uop_8_uses_stq}, {stq_uop_7_uses_stq}, {stq_uop_6_uses_stq}, {stq_uop_5_uses_stq}, {stq_uop_4_uses_stq}, {stq_uop_3_uses_stq}, {stq_uop_2_uses_stq}, {stq_uop_1_uses_stq}, {stq_uop_0_uses_stq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_stq = _GEN_337[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_338 = {{stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_23_is_unique}, {stq_uop_22_is_unique}, {stq_uop_21_is_unique}, {stq_uop_20_is_unique}, {stq_uop_19_is_unique}, {stq_uop_18_is_unique}, {stq_uop_17_is_unique}, {stq_uop_16_is_unique}, {stq_uop_15_is_unique}, {stq_uop_14_is_unique}, {stq_uop_13_is_unique}, {stq_uop_12_is_unique}, {stq_uop_11_is_unique}, {stq_uop_10_is_unique}, {stq_uop_9_is_unique}, {stq_uop_8_is_unique}, {stq_uop_7_is_unique}, {stq_uop_6_is_unique}, {stq_uop_5_is_unique}, {stq_uop_4_is_unique}, {stq_uop_3_is_unique}, {stq_uop_2_is_unique}, {stq_uop_1_is_unique}, {stq_uop_0_is_unique}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_unique = _GEN_338[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_339 = {{stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_23_flush_on_commit}, {stq_uop_22_flush_on_commit}, {stq_uop_21_flush_on_commit}, {stq_uop_20_flush_on_commit}, {stq_uop_19_flush_on_commit}, {stq_uop_18_flush_on_commit}, {stq_uop_17_flush_on_commit}, {stq_uop_16_flush_on_commit}, {stq_uop_15_flush_on_commit}, {stq_uop_14_flush_on_commit}, {stq_uop_13_flush_on_commit}, {stq_uop_12_flush_on_commit}, {stq_uop_11_flush_on_commit}, {stq_uop_10_flush_on_commit}, {stq_uop_9_flush_on_commit}, {stq_uop_8_flush_on_commit}, {stq_uop_7_flush_on_commit}, {stq_uop_6_flush_on_commit}, {stq_uop_5_flush_on_commit}, {stq_uop_4_flush_on_commit}, {stq_uop_3_flush_on_commit}, {stq_uop_2_flush_on_commit}, {stq_uop_1_flush_on_commit}, {stq_uop_0_flush_on_commit}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_flush_on_commit = _GEN_339[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_340 = {{stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_23_csr_cmd}, {stq_uop_22_csr_cmd}, {stq_uop_21_csr_cmd}, {stq_uop_20_csr_cmd}, {stq_uop_19_csr_cmd}, {stq_uop_18_csr_cmd}, {stq_uop_17_csr_cmd}, {stq_uop_16_csr_cmd}, {stq_uop_15_csr_cmd}, {stq_uop_14_csr_cmd}, {stq_uop_13_csr_cmd}, {stq_uop_12_csr_cmd}, {stq_uop_11_csr_cmd}, {stq_uop_10_csr_cmd}, {stq_uop_9_csr_cmd}, {stq_uop_8_csr_cmd}, {stq_uop_7_csr_cmd}, {stq_uop_6_csr_cmd}, {stq_uop_5_csr_cmd}, {stq_uop_4_csr_cmd}, {stq_uop_3_csr_cmd}, {stq_uop_2_csr_cmd}, {stq_uop_1_csr_cmd}, {stq_uop_0_csr_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_csr_cmd = _GEN_340[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_341 = {{stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_23_ldst_is_rs1}, {stq_uop_22_ldst_is_rs1}, {stq_uop_21_ldst_is_rs1}, {stq_uop_20_ldst_is_rs1}, {stq_uop_19_ldst_is_rs1}, {stq_uop_18_ldst_is_rs1}, {stq_uop_17_ldst_is_rs1}, {stq_uop_16_ldst_is_rs1}, {stq_uop_15_ldst_is_rs1}, {stq_uop_14_ldst_is_rs1}, {stq_uop_13_ldst_is_rs1}, {stq_uop_12_ldst_is_rs1}, {stq_uop_11_ldst_is_rs1}, {stq_uop_10_ldst_is_rs1}, {stq_uop_9_ldst_is_rs1}, {stq_uop_8_ldst_is_rs1}, {stq_uop_7_ldst_is_rs1}, {stq_uop_6_ldst_is_rs1}, {stq_uop_5_ldst_is_rs1}, {stq_uop_4_ldst_is_rs1}, {stq_uop_3_ldst_is_rs1}, {stq_uop_2_ldst_is_rs1}, {stq_uop_1_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_342 = {{stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_23_ldst}, {stq_uop_22_ldst}, {stq_uop_21_ldst}, {stq_uop_20_ldst}, {stq_uop_19_ldst}, {stq_uop_18_ldst}, {stq_uop_17_ldst}, {stq_uop_16_ldst}, {stq_uop_15_ldst}, {stq_uop_14_ldst}, {stq_uop_13_ldst}, {stq_uop_12_ldst}, {stq_uop_11_ldst}, {stq_uop_10_ldst}, {stq_uop_9_ldst}, {stq_uop_8_ldst}, {stq_uop_7_ldst}, {stq_uop_6_ldst}, {stq_uop_5_ldst}, {stq_uop_4_ldst}, {stq_uop_3_ldst}, {stq_uop_2_ldst}, {stq_uop_1_ldst}, {stq_uop_0_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst = _GEN_342[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_343 = {{stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_23_lrs1}, {stq_uop_22_lrs1}, {stq_uop_21_lrs1}, {stq_uop_20_lrs1}, {stq_uop_19_lrs1}, {stq_uop_18_lrs1}, {stq_uop_17_lrs1}, {stq_uop_16_lrs1}, {stq_uop_15_lrs1}, {stq_uop_14_lrs1}, {stq_uop_13_lrs1}, {stq_uop_12_lrs1}, {stq_uop_11_lrs1}, {stq_uop_10_lrs1}, {stq_uop_9_lrs1}, {stq_uop_8_lrs1}, {stq_uop_7_lrs1}, {stq_uop_6_lrs1}, {stq_uop_5_lrs1}, {stq_uop_4_lrs1}, {stq_uop_3_lrs1}, {stq_uop_2_lrs1}, {stq_uop_1_lrs1}, {stq_uop_0_lrs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1 = _GEN_343[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_344 = {{stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_23_lrs2}, {stq_uop_22_lrs2}, {stq_uop_21_lrs2}, {stq_uop_20_lrs2}, {stq_uop_19_lrs2}, {stq_uop_18_lrs2}, {stq_uop_17_lrs2}, {stq_uop_16_lrs2}, {stq_uop_15_lrs2}, {stq_uop_14_lrs2}, {stq_uop_13_lrs2}, {stq_uop_12_lrs2}, {stq_uop_11_lrs2}, {stq_uop_10_lrs2}, {stq_uop_9_lrs2}, {stq_uop_8_lrs2}, {stq_uop_7_lrs2}, {stq_uop_6_lrs2}, {stq_uop_5_lrs2}, {stq_uop_4_lrs2}, {stq_uop_3_lrs2}, {stq_uop_2_lrs2}, {stq_uop_1_lrs2}, {stq_uop_0_lrs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2 = _GEN_344[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_345 = {{stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_23_lrs3}, {stq_uop_22_lrs3}, {stq_uop_21_lrs3}, {stq_uop_20_lrs3}, {stq_uop_19_lrs3}, {stq_uop_18_lrs3}, {stq_uop_17_lrs3}, {stq_uop_16_lrs3}, {stq_uop_15_lrs3}, {stq_uop_14_lrs3}, {stq_uop_13_lrs3}, {stq_uop_12_lrs3}, {stq_uop_11_lrs3}, {stq_uop_10_lrs3}, {stq_uop_9_lrs3}, {stq_uop_8_lrs3}, {stq_uop_7_lrs3}, {stq_uop_6_lrs3}, {stq_uop_5_lrs3}, {stq_uop_4_lrs3}, {stq_uop_3_lrs3}, {stq_uop_2_lrs3}, {stq_uop_1_lrs3}, {stq_uop_0_lrs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs3 = _GEN_345[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_346 = {{stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_23_dst_rtype}, {stq_uop_22_dst_rtype}, {stq_uop_21_dst_rtype}, {stq_uop_20_dst_rtype}, {stq_uop_19_dst_rtype}, {stq_uop_18_dst_rtype}, {stq_uop_17_dst_rtype}, {stq_uop_16_dst_rtype}, {stq_uop_15_dst_rtype}, {stq_uop_14_dst_rtype}, {stq_uop_13_dst_rtype}, {stq_uop_12_dst_rtype}, {stq_uop_11_dst_rtype}, {stq_uop_10_dst_rtype}, {stq_uop_9_dst_rtype}, {stq_uop_8_dst_rtype}, {stq_uop_7_dst_rtype}, {stq_uop_6_dst_rtype}, {stq_uop_5_dst_rtype}, {stq_uop_4_dst_rtype}, {stq_uop_3_dst_rtype}, {stq_uop_2_dst_rtype}, {stq_uop_1_dst_rtype}, {stq_uop_0_dst_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dst_rtype = _GEN_346[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_347 = {{stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_23_lrs1_rtype}, {stq_uop_22_lrs1_rtype}, {stq_uop_21_lrs1_rtype}, {stq_uop_20_lrs1_rtype}, {stq_uop_19_lrs1_rtype}, {stq_uop_18_lrs1_rtype}, {stq_uop_17_lrs1_rtype}, {stq_uop_16_lrs1_rtype}, {stq_uop_15_lrs1_rtype}, {stq_uop_14_lrs1_rtype}, {stq_uop_13_lrs1_rtype}, {stq_uop_12_lrs1_rtype}, {stq_uop_11_lrs1_rtype}, {stq_uop_10_lrs1_rtype}, {stq_uop_9_lrs1_rtype}, {stq_uop_8_lrs1_rtype}, {stq_uop_7_lrs1_rtype}, {stq_uop_6_lrs1_rtype}, {stq_uop_5_lrs1_rtype}, {stq_uop_4_lrs1_rtype}, {stq_uop_3_lrs1_rtype}, {stq_uop_2_lrs1_rtype}, {stq_uop_1_lrs1_rtype}, {stq_uop_0_lrs1_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_348 = {{stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_23_lrs2_rtype}, {stq_uop_22_lrs2_rtype}, {stq_uop_21_lrs2_rtype}, {stq_uop_20_lrs2_rtype}, {stq_uop_19_lrs2_rtype}, {stq_uop_18_lrs2_rtype}, {stq_uop_17_lrs2_rtype}, {stq_uop_16_lrs2_rtype}, {stq_uop_15_lrs2_rtype}, {stq_uop_14_lrs2_rtype}, {stq_uop_13_lrs2_rtype}, {stq_uop_12_lrs2_rtype}, {stq_uop_11_lrs2_rtype}, {stq_uop_10_lrs2_rtype}, {stq_uop_9_lrs2_rtype}, {stq_uop_8_lrs2_rtype}, {stq_uop_7_lrs2_rtype}, {stq_uop_6_lrs2_rtype}, {stq_uop_5_lrs2_rtype}, {stq_uop_4_lrs2_rtype}, {stq_uop_3_lrs2_rtype}, {stq_uop_2_lrs2_rtype}, {stq_uop_1_lrs2_rtype}, {stq_uop_0_lrs2_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_349 = {{stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_23_frs3_en}, {stq_uop_22_frs3_en}, {stq_uop_21_frs3_en}, {stq_uop_20_frs3_en}, {stq_uop_19_frs3_en}, {stq_uop_18_frs3_en}, {stq_uop_17_frs3_en}, {stq_uop_16_frs3_en}, {stq_uop_15_frs3_en}, {stq_uop_14_frs3_en}, {stq_uop_13_frs3_en}, {stq_uop_12_frs3_en}, {stq_uop_11_frs3_en}, {stq_uop_10_frs3_en}, {stq_uop_9_frs3_en}, {stq_uop_8_frs3_en}, {stq_uop_7_frs3_en}, {stq_uop_6_frs3_en}, {stq_uop_5_frs3_en}, {stq_uop_4_frs3_en}, {stq_uop_3_frs3_en}, {stq_uop_2_frs3_en}, {stq_uop_1_frs3_en}, {stq_uop_0_frs3_en}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_frs3_en = _GEN_349[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_350 = {{stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_23_fcn_dw}, {stq_uop_22_fcn_dw}, {stq_uop_21_fcn_dw}, {stq_uop_20_fcn_dw}, {stq_uop_19_fcn_dw}, {stq_uop_18_fcn_dw}, {stq_uop_17_fcn_dw}, {stq_uop_16_fcn_dw}, {stq_uop_15_fcn_dw}, {stq_uop_14_fcn_dw}, {stq_uop_13_fcn_dw}, {stq_uop_12_fcn_dw}, {stq_uop_11_fcn_dw}, {stq_uop_10_fcn_dw}, {stq_uop_9_fcn_dw}, {stq_uop_8_fcn_dw}, {stq_uop_7_fcn_dw}, {stq_uop_6_fcn_dw}, {stq_uop_5_fcn_dw}, {stq_uop_4_fcn_dw}, {stq_uop_3_fcn_dw}, {stq_uop_2_fcn_dw}, {stq_uop_1_fcn_dw}, {stq_uop_0_fcn_dw}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_dw = _GEN_350[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_351 = {{stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_23_fcn_op}, {stq_uop_22_fcn_op}, {stq_uop_21_fcn_op}, {stq_uop_20_fcn_op}, {stq_uop_19_fcn_op}, {stq_uop_18_fcn_op}, {stq_uop_17_fcn_op}, {stq_uop_16_fcn_op}, {stq_uop_15_fcn_op}, {stq_uop_14_fcn_op}, {stq_uop_13_fcn_op}, {stq_uop_12_fcn_op}, {stq_uop_11_fcn_op}, {stq_uop_10_fcn_op}, {stq_uop_9_fcn_op}, {stq_uop_8_fcn_op}, {stq_uop_7_fcn_op}, {stq_uop_6_fcn_op}, {stq_uop_5_fcn_op}, {stq_uop_4_fcn_op}, {stq_uop_3_fcn_op}, {stq_uop_2_fcn_op}, {stq_uop_1_fcn_op}, {stq_uop_0_fcn_op}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_op = _GEN_351[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_352 = {{stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_23_fp_val}, {stq_uop_22_fp_val}, {stq_uop_21_fp_val}, {stq_uop_20_fp_val}, {stq_uop_19_fp_val}, {stq_uop_18_fp_val}, {stq_uop_17_fp_val}, {stq_uop_16_fp_val}, {stq_uop_15_fp_val}, {stq_uop_14_fp_val}, {stq_uop_13_fp_val}, {stq_uop_12_fp_val}, {stq_uop_11_fp_val}, {stq_uop_10_fp_val}, {stq_uop_9_fp_val}, {stq_uop_8_fp_val}, {stq_uop_7_fp_val}, {stq_uop_6_fp_val}, {stq_uop_5_fp_val}, {stq_uop_4_fp_val}, {stq_uop_3_fp_val}, {stq_uop_2_fp_val}, {stq_uop_1_fp_val}, {stq_uop_0_fp_val}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_val = _GEN_352[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_353 = {{stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_23_fp_rm}, {stq_uop_22_fp_rm}, {stq_uop_21_fp_rm}, {stq_uop_20_fp_rm}, {stq_uop_19_fp_rm}, {stq_uop_18_fp_rm}, {stq_uop_17_fp_rm}, {stq_uop_16_fp_rm}, {stq_uop_15_fp_rm}, {stq_uop_14_fp_rm}, {stq_uop_13_fp_rm}, {stq_uop_12_fp_rm}, {stq_uop_11_fp_rm}, {stq_uop_10_fp_rm}, {stq_uop_9_fp_rm}, {stq_uop_8_fp_rm}, {stq_uop_7_fp_rm}, {stq_uop_6_fp_rm}, {stq_uop_5_fp_rm}, {stq_uop_4_fp_rm}, {stq_uop_3_fp_rm}, {stq_uop_2_fp_rm}, {stq_uop_1_fp_rm}, {stq_uop_0_fp_rm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_rm = _GEN_353[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_354 = {{stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_23_fp_typ}, {stq_uop_22_fp_typ}, {stq_uop_21_fp_typ}, {stq_uop_20_fp_typ}, {stq_uop_19_fp_typ}, {stq_uop_18_fp_typ}, {stq_uop_17_fp_typ}, {stq_uop_16_fp_typ}, {stq_uop_15_fp_typ}, {stq_uop_14_fp_typ}, {stq_uop_13_fp_typ}, {stq_uop_12_fp_typ}, {stq_uop_11_fp_typ}, {stq_uop_10_fp_typ}, {stq_uop_9_fp_typ}, {stq_uop_8_fp_typ}, {stq_uop_7_fp_typ}, {stq_uop_6_fp_typ}, {stq_uop_5_fp_typ}, {stq_uop_4_fp_typ}, {stq_uop_3_fp_typ}, {stq_uop_2_fp_typ}, {stq_uop_1_fp_typ}, {stq_uop_0_fp_typ}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_typ = _GEN_354[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_355 = {{stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_23_xcpt_pf_if}, {stq_uop_22_xcpt_pf_if}, {stq_uop_21_xcpt_pf_if}, {stq_uop_20_xcpt_pf_if}, {stq_uop_19_xcpt_pf_if}, {stq_uop_18_xcpt_pf_if}, {stq_uop_17_xcpt_pf_if}, {stq_uop_16_xcpt_pf_if}, {stq_uop_15_xcpt_pf_if}, {stq_uop_14_xcpt_pf_if}, {stq_uop_13_xcpt_pf_if}, {stq_uop_12_xcpt_pf_if}, {stq_uop_11_xcpt_pf_if}, {stq_uop_10_xcpt_pf_if}, {stq_uop_9_xcpt_pf_if}, {stq_uop_8_xcpt_pf_if}, {stq_uop_7_xcpt_pf_if}, {stq_uop_6_xcpt_pf_if}, {stq_uop_5_xcpt_pf_if}, {stq_uop_4_xcpt_pf_if}, {stq_uop_3_xcpt_pf_if}, {stq_uop_2_xcpt_pf_if}, {stq_uop_1_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_356 = {{stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_23_xcpt_ae_if}, {stq_uop_22_xcpt_ae_if}, {stq_uop_21_xcpt_ae_if}, {stq_uop_20_xcpt_ae_if}, {stq_uop_19_xcpt_ae_if}, {stq_uop_18_xcpt_ae_if}, {stq_uop_17_xcpt_ae_if}, {stq_uop_16_xcpt_ae_if}, {stq_uop_15_xcpt_ae_if}, {stq_uop_14_xcpt_ae_if}, {stq_uop_13_xcpt_ae_if}, {stq_uop_12_xcpt_ae_if}, {stq_uop_11_xcpt_ae_if}, {stq_uop_10_xcpt_ae_if}, {stq_uop_9_xcpt_ae_if}, {stq_uop_8_xcpt_ae_if}, {stq_uop_7_xcpt_ae_if}, {stq_uop_6_xcpt_ae_if}, {stq_uop_5_xcpt_ae_if}, {stq_uop_4_xcpt_ae_if}, {stq_uop_3_xcpt_ae_if}, {stq_uop_2_xcpt_ae_if}, {stq_uop_1_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_357 = {{stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_23_xcpt_ma_if}, {stq_uop_22_xcpt_ma_if}, {stq_uop_21_xcpt_ma_if}, {stq_uop_20_xcpt_ma_if}, {stq_uop_19_xcpt_ma_if}, {stq_uop_18_xcpt_ma_if}, {stq_uop_17_xcpt_ma_if}, {stq_uop_16_xcpt_ma_if}, {stq_uop_15_xcpt_ma_if}, {stq_uop_14_xcpt_ma_if}, {stq_uop_13_xcpt_ma_if}, {stq_uop_12_xcpt_ma_if}, {stq_uop_11_xcpt_ma_if}, {stq_uop_10_xcpt_ma_if}, {stq_uop_9_xcpt_ma_if}, {stq_uop_8_xcpt_ma_if}, {stq_uop_7_xcpt_ma_if}, {stq_uop_6_xcpt_ma_if}, {stq_uop_5_xcpt_ma_if}, {stq_uop_4_xcpt_ma_if}, {stq_uop_3_xcpt_ma_if}, {stq_uop_2_xcpt_ma_if}, {stq_uop_1_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_358 = {{stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_23_bp_debug_if}, {stq_uop_22_bp_debug_if}, {stq_uop_21_bp_debug_if}, {stq_uop_20_bp_debug_if}, {stq_uop_19_bp_debug_if}, {stq_uop_18_bp_debug_if}, {stq_uop_17_bp_debug_if}, {stq_uop_16_bp_debug_if}, {stq_uop_15_bp_debug_if}, {stq_uop_14_bp_debug_if}, {stq_uop_13_bp_debug_if}, {stq_uop_12_bp_debug_if}, {stq_uop_11_bp_debug_if}, {stq_uop_10_bp_debug_if}, {stq_uop_9_bp_debug_if}, {stq_uop_8_bp_debug_if}, {stq_uop_7_bp_debug_if}, {stq_uop_6_bp_debug_if}, {stq_uop_5_bp_debug_if}, {stq_uop_4_bp_debug_if}, {stq_uop_3_bp_debug_if}, {stq_uop_2_bp_debug_if}, {stq_uop_1_bp_debug_if}, {stq_uop_0_bp_debug_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_debug_if = _GEN_358[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_359 = {{stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_23_bp_xcpt_if}, {stq_uop_22_bp_xcpt_if}, {stq_uop_21_bp_xcpt_if}, {stq_uop_20_bp_xcpt_if}, {stq_uop_19_bp_xcpt_if}, {stq_uop_18_bp_xcpt_if}, {stq_uop_17_bp_xcpt_if}, {stq_uop_16_bp_xcpt_if}, {stq_uop_15_bp_xcpt_if}, {stq_uop_14_bp_xcpt_if}, {stq_uop_13_bp_xcpt_if}, {stq_uop_12_bp_xcpt_if}, {stq_uop_11_bp_xcpt_if}, {stq_uop_10_bp_xcpt_if}, {stq_uop_9_bp_xcpt_if}, {stq_uop_8_bp_xcpt_if}, {stq_uop_7_bp_xcpt_if}, {stq_uop_6_bp_xcpt_if}, {stq_uop_5_bp_xcpt_if}, {stq_uop_4_bp_xcpt_if}, {stq_uop_3_bp_xcpt_if}, {stq_uop_2_bp_xcpt_if}, {stq_uop_1_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_360 = {{stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_23_debug_fsrc}, {stq_uop_22_debug_fsrc}, {stq_uop_21_debug_fsrc}, {stq_uop_20_debug_fsrc}, {stq_uop_19_debug_fsrc}, {stq_uop_18_debug_fsrc}, {stq_uop_17_debug_fsrc}, {stq_uop_16_debug_fsrc}, {stq_uop_15_debug_fsrc}, {stq_uop_14_debug_fsrc}, {stq_uop_13_debug_fsrc}, {stq_uop_12_debug_fsrc}, {stq_uop_11_debug_fsrc}, {stq_uop_10_debug_fsrc}, {stq_uop_9_debug_fsrc}, {stq_uop_8_debug_fsrc}, {stq_uop_7_debug_fsrc}, {stq_uop_6_debug_fsrc}, {stq_uop_5_debug_fsrc}, {stq_uop_4_debug_fsrc}, {stq_uop_3_debug_fsrc}, {stq_uop_2_debug_fsrc}, {stq_uop_1_debug_fsrc}, {stq_uop_0_debug_fsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_fsrc = _GEN_360[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_361 = {{stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_23_debug_tsrc}, {stq_uop_22_debug_tsrc}, {stq_uop_21_debug_tsrc}, {stq_uop_20_debug_tsrc}, {stq_uop_19_debug_tsrc}, {stq_uop_18_debug_tsrc}, {stq_uop_17_debug_tsrc}, {stq_uop_16_debug_tsrc}, {stq_uop_15_debug_tsrc}, {stq_uop_14_debug_tsrc}, {stq_uop_13_debug_tsrc}, {stq_uop_12_debug_tsrc}, {stq_uop_11_debug_tsrc}, {stq_uop_10_debug_tsrc}, {stq_uop_9_debug_tsrc}, {stq_uop_8_debug_tsrc}, {stq_uop_7_debug_tsrc}, {stq_uop_6_debug_tsrc}, {stq_uop_5_debug_tsrc}, {stq_uop_4_debug_tsrc}, {stq_uop_3_debug_tsrc}, {stq_uop_2_debug_tsrc}, {stq_uop_1_debug_tsrc}, {stq_uop_0_debug_tsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_tsrc = _GEN_361[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_362 = {{stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_23_valid}, {stq_addr_22_valid}, {stq_addr_21_valid}, {stq_addr_20_valid}, {stq_addr_19_valid}, {stq_addr_18_valid}, {stq_addr_17_valid}, {stq_addr_16_valid}, {stq_addr_15_valid}, {stq_addr_14_valid}, {stq_addr_13_valid}, {stq_addr_12_valid}, {stq_addr_11_valid}, {stq_addr_10_valid}, {stq_addr_9_valid}, {stq_addr_8_valid}, {stq_addr_7_valid}, {stq_addr_6_valid}, {stq_addr_5_valid}, {stq_addr_4_valid}, {stq_addr_3_valid}, {stq_addr_2_valid}, {stq_addr_1_valid}, {stq_addr_0_valid}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_valid = _GEN_362[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [31:0][39:0] _GEN_363 = {{stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_23_bits}, {stq_addr_22_bits}, {stq_addr_21_bits}, {stq_addr_20_bits}, {stq_addr_19_bits}, {stq_addr_18_bits}, {stq_addr_17_bits}, {stq_addr_16_bits}, {stq_addr_15_bits}, {stq_addr_14_bits}, {stq_addr_13_bits}, {stq_addr_12_bits}, {stq_addr_11_bits}, {stq_addr_10_bits}, {stq_addr_9_bits}, {stq_addr_8_bits}, {stq_addr_7_bits}, {stq_addr_6_bits}, {stq_addr_5_bits}, {stq_addr_4_bits}, {stq_addr_3_bits}, {stq_addr_2_bits}, {stq_addr_1_bits}, {stq_addr_0_bits}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_bits = _GEN_363[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [31:0] _GEN_364 = {{stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_23}, {stq_addr_is_virtual_22}, {stq_addr_is_virtual_21}, {stq_addr_is_virtual_20}, {stq_addr_is_virtual_19}, {stq_addr_is_virtual_18}, {stq_addr_is_virtual_17}, {stq_addr_is_virtual_16}, {stq_addr_is_virtual_15}, {stq_addr_is_virtual_14}, {stq_addr_is_virtual_13}, {stq_addr_is_virtual_12}, {stq_addr_is_virtual_11}, {stq_addr_is_virtual_10}, {stq_addr_is_virtual_9}, {stq_addr_is_virtual_8}, {stq_addr_is_virtual_7}, {stq_addr_is_virtual_6}, {stq_addr_is_virtual_5}, {stq_addr_is_virtual_4}, {stq_addr_is_virtual_3}, {stq_addr_is_virtual_2}, {stq_addr_is_virtual_1}, {stq_addr_is_virtual_0}}; // @[lsu.scala:254:32, :266:32] assign stq_incoming_e_e_bits_addr_is_virtual = _GEN_364[stq_incoming_idx_0]; // @[lsu.scala:262:17, :266:32, :321:49] wire [31:0] _GEN_365 = {{stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_23_valid}, {stq_data_22_valid}, {stq_data_21_valid}, {stq_data_20_valid}, {stq_data_19_valid}, {stq_data_18_valid}, {stq_data_17_valid}, {stq_data_16_valid}, {stq_data_15_valid}, {stq_data_14_valid}, {stq_data_13_valid}, {stq_data_12_valid}, {stq_data_11_valid}, {stq_data_10_valid}, {stq_data_9_valid}, {stq_data_8_valid}, {stq_data_7_valid}, {stq_data_6_valid}, {stq_data_5_valid}, {stq_data_4_valid}, {stq_data_3_valid}, {stq_data_2_valid}, {stq_data_1_valid}, {stq_data_0_valid}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_valid = _GEN_365[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [31:0][63:0] _GEN_366 = {{stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_23_bits}, {stq_data_22_bits}, {stq_data_21_bits}, {stq_data_20_bits}, {stq_data_19_bits}, {stq_data_18_bits}, {stq_data_17_bits}, {stq_data_16_bits}, {stq_data_15_bits}, {stq_data_14_bits}, {stq_data_13_bits}, {stq_data_12_bits}, {stq_data_11_bits}, {stq_data_10_bits}, {stq_data_9_bits}, {stq_data_8_bits}, {stq_data_7_bits}, {stq_data_6_bits}, {stq_data_5_bits}, {stq_data_4_bits}, {stq_data_3_bits}, {stq_data_2_bits}, {stq_data_1_bits}, {stq_data_0_bits}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_bits = _GEN_366[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [31:0] _GEN_367 = {{stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_23}, {stq_committed_22}, {stq_committed_21}, {stq_committed_20}, {stq_committed_19}, {stq_committed_18}, {stq_committed_17}, {stq_committed_16}, {stq_committed_15}, {stq_committed_14}, {stq_committed_13}, {stq_committed_12}, {stq_committed_11}, {stq_committed_10}, {stq_committed_9}, {stq_committed_8}, {stq_committed_7}, {stq_committed_6}, {stq_committed_5}, {stq_committed_4}, {stq_committed_3}, {stq_committed_2}, {stq_committed_1}, {stq_committed_0}}; // @[lsu.scala:256:32, :268:32] assign stq_incoming_e_e_bits_committed = _GEN_367[stq_incoming_idx_0]; // @[lsu.scala:262:17, :268:32, :321:49] wire [31:0] _GEN_368 = {{stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_23}, {stq_succeeded_22}, {stq_succeeded_21}, {stq_succeeded_20}, {stq_succeeded_19}, {stq_succeeded_18}, {stq_succeeded_17}, {stq_succeeded_16}, {stq_succeeded_15}, {stq_succeeded_14}, {stq_succeeded_13}, {stq_succeeded_12}, {stq_succeeded_11}, {stq_succeeded_10}, {stq_succeeded_9}, {stq_succeeded_8}, {stq_succeeded_7}, {stq_succeeded_6}, {stq_succeeded_5}, {stq_succeeded_4}, {stq_succeeded_3}, {stq_succeeded_2}, {stq_succeeded_1}, {stq_succeeded_0}}; // @[lsu.scala:257:32, :269:32] assign stq_incoming_e_e_bits_succeeded = _GEN_368[stq_incoming_idx_0]; // @[lsu.scala:262:17, :269:32, :321:49] wire [31:0] _GEN_369 = {{stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_23}, {stq_can_execute_22}, {stq_can_execute_21}, {stq_can_execute_20}, {stq_can_execute_19}, {stq_can_execute_18}, {stq_can_execute_17}, {stq_can_execute_16}, {stq_can_execute_15}, {stq_can_execute_14}, {stq_can_execute_13}, {stq_can_execute_12}, {stq_can_execute_11}, {stq_can_execute_10}, {stq_can_execute_9}, {stq_can_execute_8}, {stq_can_execute_7}, {stq_can_execute_6}, {stq_can_execute_5}, {stq_can_execute_4}, {stq_can_execute_3}, {stq_can_execute_2}, {stq_can_execute_1}, {stq_can_execute_0}}; // @[lsu.scala:258:32, :270:32] assign stq_incoming_e_e_bits_can_execute = _GEN_369[stq_incoming_idx_0]; // @[lsu.scala:262:17, :270:32, :321:49] wire [31:0] _GEN_370 = {{stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_23}, {stq_cleared_22}, {stq_cleared_21}, {stq_cleared_20}, {stq_cleared_19}, {stq_cleared_18}, {stq_cleared_17}, {stq_cleared_16}, {stq_cleared_15}, {stq_cleared_14}, {stq_cleared_13}, {stq_cleared_12}, {stq_cleared_11}, {stq_cleared_10}, {stq_cleared_9}, {stq_cleared_8}, {stq_cleared_7}, {stq_cleared_6}, {stq_cleared_5}, {stq_cleared_4}, {stq_cleared_3}, {stq_cleared_2}, {stq_cleared_1}, {stq_cleared_0}}; // @[lsu.scala:259:32, :271:32] assign stq_incoming_e_e_bits_cleared = _GEN_370[stq_incoming_idx_0]; // @[lsu.scala:262:17, :271:32, :321:49] wire [31:0][63:0] _GEN_371 = {{stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_23}, {stq_debug_wb_data_22}, {stq_debug_wb_data_21}, {stq_debug_wb_data_20}, {stq_debug_wb_data_19}, {stq_debug_wb_data_18}, {stq_debug_wb_data_17}, {stq_debug_wb_data_16}, {stq_debug_wb_data_15}, {stq_debug_wb_data_14}, {stq_debug_wb_data_13}, {stq_debug_wb_data_12}, {stq_debug_wb_data_11}, {stq_debug_wb_data_10}, {stq_debug_wb_data_9}, {stq_debug_wb_data_8}, {stq_debug_wb_data_7}, {stq_debug_wb_data_6}, {stq_debug_wb_data_5}, {stq_debug_wb_data_4}, {stq_debug_wb_data_3}, {stq_debug_wb_data_2}, {stq_debug_wb_data_1}, {stq_debug_wb_data_0}}; // @[lsu.scala:260:32, :272:32] assign stq_incoming_e_e_bits_debug_wb_data = _GEN_371[stq_incoming_idx_0]; // @[lsu.scala:262:17, :272:32, :321:49] wire stq_incoming_e_0_valid = _stq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_inst = _stq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst = _stq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rvc = _stq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc = _stq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_0 = _stq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_1 = _stq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_2 = _stq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_3 = _stq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_0 = _stq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_1 = _stq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_2 = _stq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_3 = _stq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_4 = _stq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_5 = _stq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_6 = _stq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_7 = _stq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_8 = _stq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_9 = _stq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued = _stq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_agen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_iw_p1_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_iw_p2_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_dis_col_sel = _stq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :504:48] wire [15:0] stq_incoming_e_0_bits_uop_br_mask = _stq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_tag = _stq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_type = _stq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfb = _stq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fence = _stq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fencei = _stq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfence = _stq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_amo = _stq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_eret = _stq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc = _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rocc = _stq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_mov = _stq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx = _stq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_edge_inst = _stq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob = _stq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_taken = _stq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_imm_rename = _stq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_imm_sel = _stq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_pimm = _stq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :504:48] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed = _stq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_op1_sel = _stq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_op2_sel = _stq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ldst = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wen = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fromint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_toint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fma = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_div = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wflags = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_vec = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_rob_idx = _stq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ldq_idx = _stq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_stq_idx = _stq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx = _stq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_pdst = _stq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs1 = _stq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs2 = _stq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs3 = _stq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ppred = _stq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs1_busy = _stq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs2_busy = _stq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs3_busy = _stq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ppred_busy = _stq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst = _stq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_exception = _stq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause = _stq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd = _stq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_mem_size = _stq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_mem_signed = _stq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_ldq = _stq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_stq = _stq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_unique = _stq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_flush_on_commit = _stq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_csr_cmd = _stq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ldst_is_rs1 = _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_ldst = _stq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs1 = _stq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs2 = _stq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs3 = _stq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype = _stq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype = _stq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype = _stq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_frs3_en = _stq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fcn_dw = _stq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_fcn_op = _stq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_val = _stq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_fp_rm = _stq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_typ = _stq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_pf_if = _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ae_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ma_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_debug_if = _stq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_xcpt_if = _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_fsrc = _stq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_tsrc = _stq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_valid = _stq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_addr_bits = _stq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_is_virtual = _stq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_data_valid = _stq_incoming_e_WIRE_bits_data_valid; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_data_bits = _stq_incoming_e_WIRE_bits_data_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_committed = _stq_incoming_e_WIRE_bits_committed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_succeeded = _stq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_can_execute = _stq_incoming_e_WIRE_bits_can_execute; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_cleared = _stq_incoming_e_WIRE_bits_cleared; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_debug_wb_data = _stq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :504:48] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_0 = stq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_1 = stq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_2 = stq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_3 = stq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_0 = stq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_1 = stq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_2 = stq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_3 = stq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_4 = stq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_5 = stq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_6 = stq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_7 = stq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_8 = stq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_9 = stq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued = stq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen = stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen = stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child = stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child = stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint = stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint = stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint = stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_dis_col_sel = stq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_type = stq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfence = stq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_eret = stq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rocc = stq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_mov = stq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_imm_rename = stq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_imm_sel = stq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_pimm = stq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_op1_sel = stq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_op2_sel = stq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst = stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen = stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1 = stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2 = stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3 = stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12 = stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23 = stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint = stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint = stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma = stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_div = stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt = stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags = stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec = stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_csr_cmd = stq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fcn_dw = stq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_fcn_op = stq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_fp_rm = stq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_typ = stq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_can_execute = stq_incoming_e_0_bits_can_execute; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_cleared = stq_incoming_e_0_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire ldq_wakeup_idx_block = block_load_mask_0 \| p1_block_load_mask_0; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T = ~ldq_executed_0; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_1 = ldq_addr_0_valid & _ldq_wakeup_idx_T; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_2 = ~ldq_succeeded_0; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_4 = ~ldq_addr_is_virtual_0; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_1 = block_load_mask_1 \| p1_block_load_mask_1; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_8 = ~ldq_executed_1; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_9 = ldq_addr_1_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_10 = ~ldq_succeeded_1; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_12 = ~ldq_addr_is_virtual_1; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_2 = block_load_mask_2 \| p1_block_load_mask_2; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_16 = ~ldq_executed_2; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_17 = ldq_addr_2_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_18 = ~ldq_succeeded_2; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_20 = ~ldq_addr_is_virtual_2; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_3 = block_load_mask_3 \| p1_block_load_mask_3; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_24 = ~ldq_executed_3; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_25 = ldq_addr_3_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_26 = ~ldq_succeeded_3; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_28 = ~ldq_addr_is_virtual_3; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_4 = block_load_mask_4 \| p1_block_load_mask_4; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_32 = ~ldq_executed_4; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_33 = ldq_addr_4_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_34 = ~ldq_succeeded_4; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_36 = ~ldq_addr_is_virtual_4; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_5 = block_load_mask_5 \| p1_block_load_mask_5; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_40 = ~ldq_executed_5; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_41 = ldq_addr_5_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_42 = ~ldq_succeeded_5; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_44 = ~ldq_addr_is_virtual_5; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_6 = block_load_mask_6 \| p1_block_load_mask_6; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_48 = ~ldq_executed_6; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_49 = ldq_addr_6_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_50 = ~ldq_succeeded_6; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_52 = ~ldq_addr_is_virtual_6; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_7 = block_load_mask_7 \| p1_block_load_mask_7; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_56 = ~ldq_executed_7; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_57 = ldq_addr_7_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_58 = ~ldq_succeeded_7; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_60 = ~ldq_addr_is_virtual_7; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_8 = block_load_mask_8 \| p1_block_load_mask_8; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_64 = ~ldq_executed_8; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_65 = ldq_addr_8_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_66 = ~ldq_succeeded_8; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_68 = ~ldq_addr_is_virtual_8; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_9 = block_load_mask_9 \| p1_block_load_mask_9; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_72 = ~ldq_executed_9; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_73 = ldq_addr_9_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_74 = ~ldq_succeeded_9; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_76 = ~ldq_addr_is_virtual_9; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_10 = block_load_mask_10 \| p1_block_load_mask_10; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_80 = ~ldq_executed_10; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_81 = ldq_addr_10_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_82 = ~ldq_succeeded_10; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_84 = ~ldq_addr_is_virtual_10; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_11 = block_load_mask_11 \| p1_block_load_mask_11; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_88 = ~ldq_executed_11; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_89 = ldq_addr_11_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_90 = ~ldq_succeeded_11; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_92 = ~ldq_addr_is_virtual_11; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_12 = block_load_mask_12 \| p1_block_load_mask_12; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_96 = ~ldq_executed_12; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_97 = ldq_addr_12_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_98 = ~ldq_succeeded_12; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_100 = ~ldq_addr_is_virtual_12; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_13 = block_load_mask_13 \| p1_block_load_mask_13; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_104 = ~ldq_executed_13; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_105 = ldq_addr_13_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_106 = ~ldq_succeeded_13; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_108 = ~ldq_addr_is_virtual_13; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_14 = block_load_mask_14 \| p1_block_load_mask_14; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_112 = ~ldq_executed_14; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_113 = ldq_addr_14_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_114 = ~ldq_succeeded_14; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_116 = ~ldq_addr_is_virtual_14; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_15 = block_load_mask_15 \| p1_block_load_mask_15; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_120 = ~ldq_executed_15; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_121 = ldq_addr_15_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_122 = ~ldq_succeeded_15; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_124 = ~ldq_addr_is_virtual_15; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_16 = block_load_mask_16 \| p1_block_load_mask_16; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_128 = ~ldq_executed_16; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_129 = ldq_addr_16_valid & _ldq_wakeup_idx_T_128; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_130 = ~ldq_succeeded_16; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_131 = _ldq_wakeup_idx_T_129 & _ldq_wakeup_idx_T_130; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_132 = ~ldq_addr_is_virtual_16; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_133 = _ldq_wakeup_idx_T_131 & _ldq_wakeup_idx_T_132; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_134 = ~ldq_wakeup_idx_block_16; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_135 = _ldq_wakeup_idx_T_133 & _ldq_wakeup_idx_T_134; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_17 = block_load_mask_17 \| p1_block_load_mask_17; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_136 = ~ldq_executed_17; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_137 = ldq_addr_17_valid & _ldq_wakeup_idx_T_136; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_138 = ~ldq_succeeded_17; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_139 = _ldq_wakeup_idx_T_137 & _ldq_wakeup_idx_T_138; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_140 = ~ldq_addr_is_virtual_17; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_141 = _ldq_wakeup_idx_T_139 & _ldq_wakeup_idx_T_140; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_142 = ~ldq_wakeup_idx_block_17; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_143 = _ldq_wakeup_idx_T_141 & _ldq_wakeup_idx_T_142; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_18 = block_load_mask_18 \| p1_block_load_mask_18; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_144 = ~ldq_executed_18; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_145 = ldq_addr_18_valid & _ldq_wakeup_idx_T_144; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_146 = ~ldq_succeeded_18; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_147 = _ldq_wakeup_idx_T_145 & _ldq_wakeup_idx_T_146; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_148 = ~ldq_addr_is_virtual_18; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_149 = _ldq_wakeup_idx_T_147 & _ldq_wakeup_idx_T_148; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_150 = ~ldq_wakeup_idx_block_18; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_151 = _ldq_wakeup_idx_T_149 & _ldq_wakeup_idx_T_150; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_19 = block_load_mask_19 \| p1_block_load_mask_19; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_152 = ~ldq_executed_19; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_153 = ldq_addr_19_valid & _ldq_wakeup_idx_T_152; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_154 = ~ldq_succeeded_19; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_155 = _ldq_wakeup_idx_T_153 & _ldq_wakeup_idx_T_154; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_156 = ~ldq_addr_is_virtual_19; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_157 = _ldq_wakeup_idx_T_155 & _ldq_wakeup_idx_T_156; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_158 = ~ldq_wakeup_idx_block_19; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_159 = _ldq_wakeup_idx_T_157 & _ldq_wakeup_idx_T_158; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_20 = block_load_mask_20 \| p1_block_load_mask_20; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_160 = ~ldq_executed_20; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_161 = ldq_addr_20_valid & _ldq_wakeup_idx_T_160; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_162 = ~ldq_succeeded_20; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_163 = _ldq_wakeup_idx_T_161 & _ldq_wakeup_idx_T_162; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_164 = ~ldq_addr_is_virtual_20; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_165 = _ldq_wakeup_idx_T_163 & _ldq_wakeup_idx_T_164; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_166 = ~ldq_wakeup_idx_block_20; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_167 = _ldq_wakeup_idx_T_165 & _ldq_wakeup_idx_T_166; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_21 = block_load_mask_21 \| p1_block_load_mask_21; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_168 = ~ldq_executed_21; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_169 = ldq_addr_21_valid & _ldq_wakeup_idx_T_168; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_170 = ~ldq_succeeded_21; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_171 = _ldq_wakeup_idx_T_169 & _ldq_wakeup_idx_T_170; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_172 = ~ldq_addr_is_virtual_21; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_173 = _ldq_wakeup_idx_T_171 & _ldq_wakeup_idx_T_172; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_174 = ~ldq_wakeup_idx_block_21; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_175 = _ldq_wakeup_idx_T_173 & _ldq_wakeup_idx_T_174; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_22 = block_load_mask_22 \| p1_block_load_mask_22; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_176 = ~ldq_executed_22; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_177 = ldq_addr_22_valid & _ldq_wakeup_idx_T_176; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_178 = ~ldq_succeeded_22; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_179 = _ldq_wakeup_idx_T_177 & _ldq_wakeup_idx_T_178; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_180 = ~ldq_addr_is_virtual_22; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_181 = _ldq_wakeup_idx_T_179 & _ldq_wakeup_idx_T_180; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_182 = ~ldq_wakeup_idx_block_22; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_183 = _ldq_wakeup_idx_T_181 & _ldq_wakeup_idx_T_182; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_23 = block_load_mask_23 \| p1_block_load_mask_23; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_184 = ~ldq_executed_23; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_185 = ldq_addr_23_valid & _ldq_wakeup_idx_T_184; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_186 = ~ldq_succeeded_23; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_187 = _ldq_wakeup_idx_T_185 & _ldq_wakeup_idx_T_186; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_188 = ~ldq_addr_is_virtual_23; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_189 = _ldq_wakeup_idx_T_187 & _ldq_wakeup_idx_T_188; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_190 = ~ldq_wakeup_idx_block_23; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_191 = _ldq_wakeup_idx_T_189 & _ldq_wakeup_idx_T_190; // @[lsu.scala:508:{64,91,94}] wire _GEN_372 = ldq_head == 5'h0; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire _l_idx_temp_vec_T; // @[util.scala:352:72] assign _l_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_373 = ldq_head < 5'h2; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire _l_idx_temp_vec_T_1; // @[util.scala:352:72] assign _l_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_374 = ldq_head < 5'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire _l_idx_temp_vec_T_2; // @[util.scala:352:72] assign _l_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_375 = ldq_head < 5'h4; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire _l_idx_temp_vec_T_3; // @[util.scala:352:72] assign _l_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_376 = ldq_head < 5'h5; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire _l_idx_temp_vec_T_4; // @[util.scala:352:72] assign _l_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_377 = ldq_head < 5'h6; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire _l_idx_temp_vec_T_5; // @[util.scala:352:72] assign _l_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_378 = ldq_head < 5'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire _l_idx_temp_vec_T_6; // @[util.scala:352:72] assign _l_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _GEN_379 = ldq_head < 5'h8; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire _l_idx_temp_vec_T_7; // @[util.scala:352:72] assign _l_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_380 = ldq_head < 5'h9; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire _l_idx_temp_vec_T_8; // @[util.scala:352:72] assign _l_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_381 = ldq_head < 5'hA; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire _l_idx_temp_vec_T_9; // @[util.scala:352:72] assign _l_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_382 = ldq_head < 5'hB; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire _l_idx_temp_vec_T_10; // @[util.scala:352:72] assign _l_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_383 = ldq_head < 5'hC; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire _l_idx_temp_vec_T_11; // @[util.scala:352:72] assign _l_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_384 = ldq_head < 5'hD; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire _l_idx_temp_vec_T_12; // @[util.scala:352:72] assign _l_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_385 = ldq_head < 5'hE; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire _l_idx_temp_vec_T_13; // @[util.scala:352:72] assign _l_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_386 = ldq_head < 5'hF; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire _l_idx_temp_vec_T_14; // @[util.scala:352:72] assign _l_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127 & _ldq_wakeup_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _GEN_387 = ldq_head < 5'h11; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire _l_idx_temp_vec_T_16; // @[util.scala:352:72] assign _l_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_16 = _ldq_wakeup_idx_T_135 & _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _GEN_388 = ldq_head < 5'h12; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire _l_idx_temp_vec_T_17; // @[util.scala:352:72] assign _l_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_17 = _ldq_wakeup_idx_T_143 & _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _GEN_389 = ldq_head < 5'h13; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire _l_idx_temp_vec_T_18; // @[util.scala:352:72] assign _l_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_18 = _ldq_wakeup_idx_T_151 & _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _GEN_390 = ldq_head < 5'h14; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire _l_idx_temp_vec_T_19; // @[util.scala:352:72] assign _l_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_19 = _ldq_wakeup_idx_T_159 & _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _GEN_391 = ldq_head < 5'h15; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire _l_idx_temp_vec_T_20; // @[util.scala:352:72] assign _l_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_20 = _ldq_wakeup_idx_T_167 & _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _GEN_392 = ldq_head < 5'h16; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire _l_idx_temp_vec_T_21; // @[util.scala:352:72] assign _l_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_21 = _ldq_wakeup_idx_T_175 & _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _GEN_393 = ldq_head < 5'h17; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire _l_idx_temp_vec_T_22; // @[util.scala:352:72] assign _l_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_22 = _ldq_wakeup_idx_T_183 & _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _GEN_394 = ldq_head[4:3] != 2'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire _l_idx_temp_vec_T_23; // @[util.scala:352:72] assign _l_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_23 = _ldq_wakeup_idx_T_191 & _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _ldq_wakeup_idx_idx_T = {5'h1B, ~_ldq_wakeup_idx_T_183}; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_175 ? 6'h35 : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_167 ? 6'h34 : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_159 ? 6'h33 : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_151 ? 6'h32 : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_143 ? 6'h31 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_135 ? 6'h30 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_127 ? 6'h2F : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_119 ? 6'h2E : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_111 ? 6'h2D : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_103 ? 6'h2C : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_95 ? 6'h2B : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_87 ? 6'h2A : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_79 ? 6'h29 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_71 ? 6'h28 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_15 = _ldq_wakeup_idx_T_63 ? 6'h27 : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_16 = _ldq_wakeup_idx_T_55 ? 6'h26 : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_17 = _ldq_wakeup_idx_T_47 ? 6'h25 : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_18 = _ldq_wakeup_idx_T_39 ? 6'h24 : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_19 = _ldq_wakeup_idx_T_31 ? 6'h23 : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_20 = _ldq_wakeup_idx_T_23 ? 6'h22 : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_21 = _ldq_wakeup_idx_T_15 ? 6'h21 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_22 = _ldq_wakeup_idx_T_7 ? 6'h20 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_23 = _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_24 = _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_25 = _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_26 = _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_27 = _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_28 = _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_29 = _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_30 = _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_31 = ldq_wakeup_idx_temp_vec_23 ? 6'h17 : _ldq_wakeup_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_32 = ldq_wakeup_idx_temp_vec_22 ? 6'h16 : _ldq_wakeup_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_33 = ldq_wakeup_idx_temp_vec_21 ? 6'h15 : _ldq_wakeup_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_34 = ldq_wakeup_idx_temp_vec_20 ? 6'h14 : _ldq_wakeup_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_35 = ldq_wakeup_idx_temp_vec_19 ? 6'h13 : _ldq_wakeup_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_36 = ldq_wakeup_idx_temp_vec_18 ? 6'h12 : _ldq_wakeup_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_37 = ldq_wakeup_idx_temp_vec_17 ? 6'h11 : _ldq_wakeup_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_38 = ldq_wakeup_idx_temp_vec_16 ? 6'h10 : _ldq_wakeup_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_39 = ldq_wakeup_idx_temp_vec_15 ? 6'hF : _ldq_wakeup_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_40 = ldq_wakeup_idx_temp_vec_14 ? 6'hE : _ldq_wakeup_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_41 = ldq_wakeup_idx_temp_vec_13 ? 6'hD : _ldq_wakeup_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_42 = ldq_wakeup_idx_temp_vec_12 ? 6'hC : _ldq_wakeup_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_43 = ldq_wakeup_idx_temp_vec_11 ? 6'hB : _ldq_wakeup_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_44 = ldq_wakeup_idx_temp_vec_10 ? 6'hA : _ldq_wakeup_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_45 = ldq_wakeup_idx_temp_vec_9 ? 6'h9 : _ldq_wakeup_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_46 = ldq_wakeup_idx_temp_vec_8 ? 6'h8 : _ldq_wakeup_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_47 = ldq_wakeup_idx_temp_vec_7 ? 6'h7 : _ldq_wakeup_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_48 = ldq_wakeup_idx_temp_vec_6 ? 6'h6 : _ldq_wakeup_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_49 = ldq_wakeup_idx_temp_vec_5 ? 6'h5 : _ldq_wakeup_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_50 = ldq_wakeup_idx_temp_vec_4 ? 6'h4 : _ldq_wakeup_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_51 = ldq_wakeup_idx_temp_vec_3 ? 6'h3 : _ldq_wakeup_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_52 = ldq_wakeup_idx_temp_vec_2 ? 6'h2 : _ldq_wakeup_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_53 = ldq_wakeup_idx_temp_vec_1 ? 6'h1 : _ldq_wakeup_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 6'h0 : _ldq_wakeup_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_T_192 = ldq_wakeup_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_valid_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_uop_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_executed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_succeeded_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_order_fail_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_observed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_st_dep_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_forward_std_val_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_debug_wb_data_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire ldq_wakeup_e_valid = ldq_wakeup_e_e_valid; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_inst = ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_debug_inst = ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rvc = ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_uop_debug_pc = ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_0 = ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_1 = ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_2 = ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_3 = ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_0 = ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_1 = ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_2 = ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_3 = ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_4 = ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_5 = ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_6 = ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_7 = ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_8 = ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_9 = ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued = ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_dis_col_sel = ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :510:32] wire [15:0] ldq_wakeup_e_bits_uop_br_mask = ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_tag = ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_type = ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfb = ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fence = ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fencei = ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfence = ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_amo = ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_eret = ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sys_pc2epc = ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rocc = ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_mov = ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ftq_idx = ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_edge_inst = ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_pc_lob = ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_taken = ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_imm_rename = ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_imm_sel = ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_pimm = ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :510:32] wire [19:0] ldq_wakeup_e_bits_uop_imm_packed = ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_op1_sel = ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_op2_sel = ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wen = ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_toint = ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fma = ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_div = ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_vec = ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_rob_idx = ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ldq_idx = ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_stq_idx = ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_rxq_idx = ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_pdst = ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs1 = ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs2 = ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs3 = ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ppred = ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs1_busy = ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs2_busy = ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs3_busy = ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ppred_busy = ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_stale_pdst = ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_exception = ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_uop_exc_cause = ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_mem_cmd = ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_mem_size = ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_mem_signed = ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_ldq = ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_stq = ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_unique = ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_flush_on_commit = ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_csr_cmd = ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ldst_is_rs1 = ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_ldst = ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs1 = ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs2 = ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs3 = ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dst_rtype = ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs1_rtype = ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs2_rtype = ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_frs3_en = ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fcn_dw = ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_fcn_op = ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_val = ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_fp_rm = ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_typ = ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_pf_if = ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ae_if = ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ma_if = ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_debug_if = ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_xcpt_if = ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_fsrc = ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_tsrc = ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_valid = ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_addr_bits = ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_virtual = ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_uncacheable = ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_executed = ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_succeeded = ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_order_fail = ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_observed = ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17, :510:32] wire [23:0] ldq_wakeup_e_bits_st_dep_mask = ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :510:32] wire [7:0] ldq_wakeup_e_bits_ld_byte_mask = ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_forward_std_val = ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_forward_stq_idx = ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_debug_wb_data = ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :510:32] wire [4:0] _ldq_wakeup_e_e_valid_T_1 = _ldq_wakeup_e_e_valid_T; assign ldq_wakeup_e_e_valid = _GEN_25[_ldq_wakeup_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [4:0] _ldq_wakeup_e_e_bits_uop_T_1 = _ldq_wakeup_e_e_bits_uop_T; assign ldq_wakeup_e_e_bits_uop_inst = _GEN_127[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_inst = _GEN_128[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rvc = _GEN_129[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_pc = _GEN_130[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_0 = _GEN_131[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_1 = _GEN_132[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_2 = _GEN_133[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_3 = _GEN_134[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_0 = _GEN_135[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_1 = _GEN_136[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_2 = _GEN_137[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_3 = _GEN_138[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_4 = _GEN_139[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_5 = _GEN_140[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_6 = _GEN_141[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_7 = _GEN_142[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_8 = _GEN_143[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_9 = _GEN_144[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued = _GEN_145[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dis_col_sel = _GEN_153[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_mask = _GEN_154[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_tag = _GEN_155[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_type = _GEN_156[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfb = _GEN_157[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fence = _GEN_158[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fencei = _GEN_159[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfence = _GEN_160[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_amo = _GEN_161[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_eret = _GEN_162[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rocc = _GEN_164[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_mov = _GEN_165[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ftq_idx = _GEN_166[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_edge_inst = _GEN_167[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pc_lob = _GEN_168[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_taken = _GEN_169[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_rename = _GEN_170[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_sel = _GEN_171[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pimm = _GEN_172[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_packed = _GEN_173[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op1_sel = _GEN_174[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op2_sel = _GEN_175[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_div = _GEN_189[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rob_idx = _GEN_193[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldq_idx = _GEN_194[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stq_idx = _GEN_195[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rxq_idx = _GEN_196[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pdst = _GEN_197[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1 = _GEN_198[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2 = _GEN_199[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3 = _GEN_200[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred = _GEN_201[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1_busy = _GEN_202[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2_busy = _GEN_203[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3_busy = _GEN_204[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred_busy = _GEN_205[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stale_pdst = _GEN_206[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exception = _GEN_207[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exc_cause = _GEN_208[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_cmd = _GEN_209[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_size = _GEN_210[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_signed = _GEN_211[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_ldq = _GEN_212[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_stq = _GEN_213[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_unique = _GEN_214[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_flush_on_commit = _GEN_215[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_csr_cmd = _GEN_216[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst = _GEN_218[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1 = _GEN_219[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2 = _GEN_220[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs3 = _GEN_221[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dst_rtype = _GEN_222[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1_rtype = _GEN_223[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2_rtype = _GEN_224[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_frs3_en = _GEN_225[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_dw = _GEN_226[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_op = _GEN_227[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_val = _GEN_228[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_rm = _GEN_229[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_typ = _GEN_230[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_pf_if = _GEN_231[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ae_if = _GEN_232[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ma_if = _GEN_233[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_debug_if = _GEN_234[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_xcpt_if = _GEN_235[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_fsrc = _GEN_236[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_tsrc = _GEN_237[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_T_1 = _ldq_wakeup_e_e_bits_addr_T; assign ldq_wakeup_e_e_bits_addr_valid = _GEN_238[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign ldq_wakeup_e_e_bits_addr_bits = _GEN_239[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = _ldq_wakeup_e_e_bits_addr_is_virtual_T; assign ldq_wakeup_e_e_bits_addr_is_virtual = _GEN_240[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = _ldq_wakeup_e_e_bits_addr_is_uncacheable_T; assign ldq_wakeup_e_e_bits_addr_is_uncacheable = _GEN_241[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [4:0] _ldq_wakeup_e_e_bits_executed_T_1 = _ldq_wakeup_e_e_bits_executed_T; assign ldq_wakeup_e_e_bits_executed = _GEN_242[_ldq_wakeup_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [4:0] _ldq_wakeup_e_e_bits_succeeded_T_1 = _ldq_wakeup_e_e_bits_succeeded_T; assign ldq_wakeup_e_e_bits_succeeded = _GEN_243[_ldq_wakeup_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [4:0] _ldq_wakeup_e_e_bits_order_fail_T_1 = _ldq_wakeup_e_e_bits_order_fail_T; assign ldq_wakeup_e_e_bits_order_fail = _GEN_244[_ldq_wakeup_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [4:0] _ldq_wakeup_e_e_bits_observed_T_1 = _ldq_wakeup_e_e_bits_observed_T; assign ldq_wakeup_e_e_bits_observed = _GEN_245[_ldq_wakeup_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [4:0] _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = _ldq_wakeup_e_e_bits_st_dep_mask_T; assign ldq_wakeup_e_e_bits_st_dep_mask = _GEN_246[_ldq_wakeup_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [4:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = _ldq_wakeup_e_e_bits_ld_byte_mask_T; assign ldq_wakeup_e_e_bits_ld_byte_mask = _GEN_247[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [4:0] _ldq_wakeup_e_e_bits_forward_std_val_T_1 = _ldq_wakeup_e_e_bits_forward_std_val_T; assign ldq_wakeup_e_e_bits_forward_std_val = _GEN_248[_ldq_wakeup_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [4:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = _ldq_wakeup_e_e_bits_forward_stq_idx_T; assign ldq_wakeup_e_e_bits_forward_stq_idx = _GEN_249[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [4:0] _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = _ldq_wakeup_e_e_bits_debug_wb_data_T; assign ldq_wakeup_e_e_bits_debug_wb_data = _GEN_250[_ldq_wakeup_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = ldq_wakeup_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = ldq_wakeup_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = ldq_wakeup_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = ldq_wakeup_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_0 = ldq_wakeup_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_1 = ldq_wakeup_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_2 = ldq_wakeup_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_3 = ldq_wakeup_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_0 = ldq_wakeup_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_1 = ldq_wakeup_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_2 = ldq_wakeup_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_3 = ldq_wakeup_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_4 = ldq_wakeup_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_5 = ldq_wakeup_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_6 = ldq_wakeup_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_7 = ldq_wakeup_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_8 = ldq_wakeup_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_9 = ldq_wakeup_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued = ldq_wakeup_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_dis_col_sel = ldq_wakeup_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = ldq_wakeup_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_type = ldq_wakeup_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = ldq_wakeup_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = ldq_wakeup_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = ldq_wakeup_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfence = ldq_wakeup_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = ldq_wakeup_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_eret = ldq_wakeup_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rocc = ldq_wakeup_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_mov = ldq_wakeup_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = ldq_wakeup_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = ldq_wakeup_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = ldq_wakeup_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = ldq_wakeup_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_imm_rename = ldq_wakeup_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_imm_sel = ldq_wakeup_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_pimm = ldq_wakeup_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = ldq_wakeup_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_op1_sel = ldq_wakeup_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_op2_sel = ldq_wakeup_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wen = ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_toint = ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fma = ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_div = ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_vec = ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = ldq_wakeup_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = ldq_wakeup_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = ldq_wakeup_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = ldq_wakeup_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = ldq_wakeup_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = ldq_wakeup_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = ldq_wakeup_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = ldq_wakeup_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = ldq_wakeup_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = ldq_wakeup_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = ldq_wakeup_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = ldq_wakeup_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = ldq_wakeup_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = ldq_wakeup_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = ldq_wakeup_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = ldq_wakeup_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = ldq_wakeup_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = ldq_wakeup_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = ldq_wakeup_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = ldq_wakeup_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = ldq_wakeup_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = ldq_wakeup_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = ldq_wakeup_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_csr_cmd = ldq_wakeup_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = ldq_wakeup_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = ldq_wakeup_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = ldq_wakeup_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = ldq_wakeup_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = ldq_wakeup_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = ldq_wakeup_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = ldq_wakeup_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = ldq_wakeup_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fcn_dw = ldq_wakeup_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_fcn_op = ldq_wakeup_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = ldq_wakeup_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_fp_rm = ldq_wakeup_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_typ = ldq_wakeup_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = ldq_wakeup_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = ldq_wakeup_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = ldq_wakeup_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = ldq_wakeup_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = ldq_wakeup_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = ldq_wakeup_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = ldq_wakeup_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_executed = ldq_wakeup_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_succeeded = ldq_wakeup_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_order_fail = ldq_wakeup_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_observed = ldq_wakeup_e_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = ldq_wakeup_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_wakeup_e_out_bits_ld_byte_mask = ldq_wakeup_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = ldq_wakeup_e_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = ldq_wakeup_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = ldq_wakeup_e_bits_debug_wb_data; // @[util.scala:114:23] reg [4:0] ldq_enq_retry_idx; // @[lsu.scala:514:30] wire _ldq_enq_retry_idx_T = ldq_addr_0_valid & ldq_addr_is_virtual_0; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_1 = \|ldq_enq_retry_idx; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_2 = _ldq_enq_retry_idx_T & _ldq_enq_retry_idx_T_1; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_3 = ldq_addr_1_valid & ldq_addr_is_virtual_1; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_4 = ldq_enq_retry_idx != 5'h1; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_5 = _ldq_enq_retry_idx_T_3 & _ldq_enq_retry_idx_T_4; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_6 = ldq_addr_2_valid & ldq_addr_is_virtual_2; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_7 = ldq_enq_retry_idx != 5'h2; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_8 = _ldq_enq_retry_idx_T_6 & _ldq_enq_retry_idx_T_7; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_9 = ldq_addr_3_valid & ldq_addr_is_virtual_3; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_10 = ldq_enq_retry_idx != 5'h3; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_11 = _ldq_enq_retry_idx_T_9 & _ldq_enq_retry_idx_T_10; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_12 = ldq_addr_4_valid & ldq_addr_is_virtual_4; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_13 = ldq_enq_retry_idx != 5'h4; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_14 = _ldq_enq_retry_idx_T_12 & _ldq_enq_retry_idx_T_13; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_15 = ldq_addr_5_valid & ldq_addr_is_virtual_5; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_16 = ldq_enq_retry_idx != 5'h5; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_17 = _ldq_enq_retry_idx_T_15 & _ldq_enq_retry_idx_T_16; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_18 = ldq_addr_6_valid & ldq_addr_is_virtual_6; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_19 = ldq_enq_retry_idx != 5'h6; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_20 = _ldq_enq_retry_idx_T_18 & _ldq_enq_retry_idx_T_19; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_21 = ldq_addr_7_valid & ldq_addr_is_virtual_7; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_22 = ldq_enq_retry_idx != 5'h7; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_23 = _ldq_enq_retry_idx_T_21 & _ldq_enq_retry_idx_T_22; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_24 = ldq_addr_8_valid & ldq_addr_is_virtual_8; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_25 = ldq_enq_retry_idx != 5'h8; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_26 = _ldq_enq_retry_idx_T_24 & _ldq_enq_retry_idx_T_25; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_27 = ldq_addr_9_valid & ldq_addr_is_virtual_9; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_28 = ldq_enq_retry_idx != 5'h9; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_29 = _ldq_enq_retry_idx_T_27 & _ldq_enq_retry_idx_T_28; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_30 = ldq_addr_10_valid & ldq_addr_is_virtual_10; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_31 = ldq_enq_retry_idx != 5'hA; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_32 = _ldq_enq_retry_idx_T_30 & _ldq_enq_retry_idx_T_31; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_33 = ldq_addr_11_valid & ldq_addr_is_virtual_11; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_34 = ldq_enq_retry_idx != 5'hB; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_35 = _ldq_enq_retry_idx_T_33 & _ldq_enq_retry_idx_T_34; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_36 = ldq_addr_12_valid & ldq_addr_is_virtual_12; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_37 = ldq_enq_retry_idx != 5'hC; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_38 = _ldq_enq_retry_idx_T_36 & _ldq_enq_retry_idx_T_37; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_39 = ldq_addr_13_valid & ldq_addr_is_virtual_13; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_40 = ldq_enq_retry_idx != 5'hD; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_41 = _ldq_enq_retry_idx_T_39 & _ldq_enq_retry_idx_T_40; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_42 = ldq_addr_14_valid & ldq_addr_is_virtual_14; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_43 = ldq_enq_retry_idx != 5'hE; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_44 = _ldq_enq_retry_idx_T_42 & _ldq_enq_retry_idx_T_43; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_45 = ldq_addr_15_valid & ldq_addr_is_virtual_15; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_46 = ldq_enq_retry_idx != 5'hF; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_47 = _ldq_enq_retry_idx_T_45 & _ldq_enq_retry_idx_T_46; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_48 = ldq_addr_16_valid & ldq_addr_is_virtual_16; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_49 = ldq_enq_retry_idx != 5'h10; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_50 = _ldq_enq_retry_idx_T_48 & _ldq_enq_retry_idx_T_49; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_51 = ldq_addr_17_valid & ldq_addr_is_virtual_17; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_52 = ldq_enq_retry_idx != 5'h11; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_53 = _ldq_enq_retry_idx_T_51 & _ldq_enq_retry_idx_T_52; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_54 = ldq_addr_18_valid & ldq_addr_is_virtual_18; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_55 = ldq_enq_retry_idx != 5'h12; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_56 = _ldq_enq_retry_idx_T_54 & _ldq_enq_retry_idx_T_55; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_57 = ldq_addr_19_valid & ldq_addr_is_virtual_19; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_58 = ldq_enq_retry_idx != 5'h13; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_59 = _ldq_enq_retry_idx_T_57 & _ldq_enq_retry_idx_T_58; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_60 = ldq_addr_20_valid & ldq_addr_is_virtual_20; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_61 = ldq_enq_retry_idx != 5'h14; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_62 = _ldq_enq_retry_idx_T_60 & _ldq_enq_retry_idx_T_61; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_63 = ldq_addr_21_valid & ldq_addr_is_virtual_21; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_64 = ldq_enq_retry_idx != 5'h15; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_65 = _ldq_enq_retry_idx_T_63 & _ldq_enq_retry_idx_T_64; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_66 = ldq_addr_22_valid & ldq_addr_is_virtual_22; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_67 = ldq_enq_retry_idx != 5'h16; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_68 = _ldq_enq_retry_idx_T_66 & _ldq_enq_retry_idx_T_67; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_69 = ldq_addr_23_valid & ldq_addr_is_virtual_23; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_70 = ldq_enq_retry_idx != 5'h17; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_71 = _ldq_enq_retry_idx_T_69 & _ldq_enq_retry_idx_T_70; // @[lsu.scala:516:{23,49,57}] wire ldq_enq_retry_idx_temp_vec_0 = _ldq_enq_retry_idx_T_2 & _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_1 = _ldq_enq_retry_idx_T_5 & _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_2 = _ldq_enq_retry_idx_T_8 & _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_3 = _ldq_enq_retry_idx_T_11 & _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_4 = _ldq_enq_retry_idx_T_14 & _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_5 = _ldq_enq_retry_idx_T_17 & _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_6 = _ldq_enq_retry_idx_T_20 & _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_7 = _ldq_enq_retry_idx_T_23 & _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_8 = _ldq_enq_retry_idx_T_26 & _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_9 = _ldq_enq_retry_idx_T_29 & _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_10 = _ldq_enq_retry_idx_T_32 & _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_11 = _ldq_enq_retry_idx_T_35 & _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_12 = _ldq_enq_retry_idx_T_38 & _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_13 = _ldq_enq_retry_idx_T_41 & _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_14 = _ldq_enq_retry_idx_T_44 & _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _ldq_enq_retry_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire ldq_enq_retry_idx_temp_vec_15 = _ldq_enq_retry_idx_T_47 & _ldq_enq_retry_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_16 = _ldq_enq_retry_idx_T_50 & _ldq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_17 = _ldq_enq_retry_idx_T_53 & _ldq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_18 = _ldq_enq_retry_idx_T_56 & _ldq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_19 = _ldq_enq_retry_idx_T_59 & _ldq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_20 = _ldq_enq_retry_idx_T_62 & _ldq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_21 = _ldq_enq_retry_idx_T_65 & _ldq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_22 = _ldq_enq_retry_idx_T_68 & _ldq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_23 = _ldq_enq_retry_idx_T_71 & _ldq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _ldq_enq_retry_idx_idx_T = {5'h1B, ~_ldq_enq_retry_idx_T_68}; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_1 = _ldq_enq_retry_idx_T_65 ? 6'h35 : _ldq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_2 = _ldq_enq_retry_idx_T_62 ? 6'h34 : _ldq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_3 = _ldq_enq_retry_idx_T_59 ? 6'h33 : _ldq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_4 = _ldq_enq_retry_idx_T_56 ? 6'h32 : _ldq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_5 = _ldq_enq_retry_idx_T_53 ? 6'h31 : _ldq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_6 = _ldq_enq_retry_idx_T_50 ? 6'h30 : _ldq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_7 = _ldq_enq_retry_idx_T_47 ? 6'h2F : _ldq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_8 = _ldq_enq_retry_idx_T_44 ? 6'h2E : _ldq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_9 = _ldq_enq_retry_idx_T_41 ? 6'h2D : _ldq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_10 = _ldq_enq_retry_idx_T_38 ? 6'h2C : _ldq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_11 = _ldq_enq_retry_idx_T_35 ? 6'h2B : _ldq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_12 = _ldq_enq_retry_idx_T_32 ? 6'h2A : _ldq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_13 = _ldq_enq_retry_idx_T_29 ? 6'h29 : _ldq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_14 = _ldq_enq_retry_idx_T_26 ? 6'h28 : _ldq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_15 = _ldq_enq_retry_idx_T_23 ? 6'h27 : _ldq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_16 = _ldq_enq_retry_idx_T_20 ? 6'h26 : _ldq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_17 = _ldq_enq_retry_idx_T_17 ? 6'h25 : _ldq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_18 = _ldq_enq_retry_idx_T_14 ? 6'h24 : _ldq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_19 = _ldq_enq_retry_idx_T_11 ? 6'h23 : _ldq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_20 = _ldq_enq_retry_idx_T_8 ? 6'h22 : _ldq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_21 = _ldq_enq_retry_idx_T_5 ? 6'h21 : _ldq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_22 = _ldq_enq_retry_idx_T_2 ? 6'h20 : _ldq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_23 = _ldq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_24 = _ldq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_25 = _ldq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_26 = _ldq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_27 = _ldq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_28 = _ldq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_29 = _ldq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_30 = _ldq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_31 = ldq_enq_retry_idx_temp_vec_23 ? 6'h17 : _ldq_enq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_32 = ldq_enq_retry_idx_temp_vec_22 ? 6'h16 : _ldq_enq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_33 = ldq_enq_retry_idx_temp_vec_21 ? 6'h15 : _ldq_enq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_34 = ldq_enq_retry_idx_temp_vec_20 ? 6'h14 : _ldq_enq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_35 = ldq_enq_retry_idx_temp_vec_19 ? 6'h13 : _ldq_enq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_36 = ldq_enq_retry_idx_temp_vec_18 ? 6'h12 : _ldq_enq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_37 = ldq_enq_retry_idx_temp_vec_17 ? 6'h11 : _ldq_enq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_38 = ldq_enq_retry_idx_temp_vec_16 ? 6'h10 : _ldq_enq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_39 = ldq_enq_retry_idx_temp_vec_15 ? 6'hF : _ldq_enq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_40 = ldq_enq_retry_idx_temp_vec_14 ? 6'hE : _ldq_enq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_41 = ldq_enq_retry_idx_temp_vec_13 ? 6'hD : _ldq_enq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_42 = ldq_enq_retry_idx_temp_vec_12 ? 6'hC : _ldq_enq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_43 = ldq_enq_retry_idx_temp_vec_11 ? 6'hB : _ldq_enq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_44 = ldq_enq_retry_idx_temp_vec_10 ? 6'hA : _ldq_enq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_45 = ldq_enq_retry_idx_temp_vec_9 ? 6'h9 : _ldq_enq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_46 = ldq_enq_retry_idx_temp_vec_8 ? 6'h8 : _ldq_enq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_47 = ldq_enq_retry_idx_temp_vec_7 ? 6'h7 : _ldq_enq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_48 = ldq_enq_retry_idx_temp_vec_6 ? 6'h6 : _ldq_enq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_49 = ldq_enq_retry_idx_temp_vec_5 ? 6'h5 : _ldq_enq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_50 = ldq_enq_retry_idx_temp_vec_4 ? 6'h4 : _ldq_enq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_51 = ldq_enq_retry_idx_temp_vec_3 ? 6'h3 : _ldq_enq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_52 = ldq_enq_retry_idx_temp_vec_2 ? 6'h2 : _ldq_enq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_53 = ldq_enq_retry_idx_temp_vec_1 ? 6'h1 : _ldq_enq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_enq_retry_idx_idx = ldq_enq_retry_idx_temp_vec_0 ? 6'h0 : _ldq_enq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_T_72 = ldq_enq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] wire ldq_enq_retry_e_valid = ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_inst = ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_debug_inst = ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rvc = ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_uop_debug_pc = ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_0 = ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_1 = ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_2 = ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_3 = ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_0 = ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_1 = ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_2 = ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_3 = ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_4 = ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_5 = ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_6 = ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_7 = ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_8 = ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_9 = ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued = ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_agen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_iw_p1_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_iw_p2_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_dis_col_sel = ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :518:33] wire [15:0] ldq_enq_retry_e_bits_uop_br_mask = ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_tag = ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_type = ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfb = ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fence = ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fencei = ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfence = ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_amo = ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_eret = ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sys_pc2epc = ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rocc = ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_mov = ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ftq_idx = ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_edge_inst = ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_pc_lob = ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_taken = ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_imm_rename = ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_imm_sel = ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_pimm = ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :518:33] wire [19:0] ldq_enq_retry_e_bits_uop_imm_packed = ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_op1_sel = ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_op2_sel = ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ldst = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wen = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren1 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren2 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren3 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap12 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap23 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fromint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_toint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fma = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_div = ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt = ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wflags = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_vec = ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_rob_idx = ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ldq_idx = ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_stq_idx = ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_rxq_idx = ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_pdst = ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs1 = ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs2 = ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs3 = ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ppred = ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs1_busy = ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs2_busy = ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs3_busy = ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ppred_busy = ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_stale_pdst = ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_exception = ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_uop_exc_cause = ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_mem_cmd = ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_mem_size = ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_mem_signed = ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_ldq = ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_stq = ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_unique = ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_flush_on_commit = ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_csr_cmd = ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ldst_is_rs1 = ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_ldst = ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs1 = ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs2 = ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs3 = ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dst_rtype = ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs1_rtype = ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs2_rtype = ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_frs3_en = ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fcn_dw = ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_fcn_op = ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_val = ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_fp_rm = ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_typ = ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_pf_if = ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ae_if = ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ma_if = ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_debug_if = ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_xcpt_if = ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_fsrc = ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_tsrc = ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_valid = ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_addr_bits = ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_virtual = ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_uncacheable = ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_executed = ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_succeeded = ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_order_fail = ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_observed = ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17, :518:33] wire [23:0] ldq_enq_retry_e_bits_st_dep_mask = ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :518:33] wire [7:0] ldq_enq_retry_e_bits_ld_byte_mask = ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_forward_std_val = ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_forward_stq_idx = ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_debug_wb_data = ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :518:33] assign ldq_enq_retry_e_e_valid = _GEN_25[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :514:30] assign ldq_enq_retry_e_e_bits_uop_inst = _GEN_127[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_inst = _GEN_128[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rvc = _GEN_129[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_pc = _GEN_130[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_131[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_132[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_133[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_134[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_135[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_136[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_137[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_138[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_139[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_140[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_141[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_142[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_143[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_144[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued = _GEN_145[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_153[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_mask = _GEN_154[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_tag = _GEN_155[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_type = _GEN_156[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfb = _GEN_157[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fence = _GEN_158[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fencei = _GEN_159[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfence = _GEN_160[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_amo = _GEN_161[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_eret = _GEN_162[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_163[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rocc = _GEN_164[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_mov = _GEN_165[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_166[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_edge_inst = _GEN_167[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pc_lob = _GEN_168[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_taken = _GEN_169[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_rename = _GEN_170[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_sel = _GEN_171[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pimm = _GEN_172[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_packed = _GEN_173[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op1_sel = _GEN_174[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op2_sel = _GEN_175[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_177[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_186[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_188[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_189[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_192[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rob_idx = _GEN_193[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_194[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stq_idx = _GEN_195[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_196[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pdst = _GEN_197[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1 = _GEN_198[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2 = _GEN_199[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3 = _GEN_200[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred = _GEN_201[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_202[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_203[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_204[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_205[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_206[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exception = _GEN_207[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exc_cause = _GEN_208[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_209[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_size = _GEN_210[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_signed = _GEN_211[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_212[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_stq = _GEN_213[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_unique = _GEN_214[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_215[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_216[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_217[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst = _GEN_218[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1 = _GEN_219[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2 = _GEN_220[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs3 = _GEN_221[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_222[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_223[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_224[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_frs3_en = _GEN_225[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_226[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_op = _GEN_227[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_val = _GEN_228[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_rm = _GEN_229[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_typ = _GEN_230[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_231[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_232[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_233[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_234[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_235[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_236[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_237[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_valid = _GEN_238[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_bits = _GEN_239[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_virtual = _GEN_240[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :237:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_uncacheable = _GEN_241[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :238:32, :514:30] assign ldq_enq_retry_e_e_bits_executed = _GEN_242[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :239:32, :514:30] assign ldq_enq_retry_e_e_bits_succeeded = _GEN_243[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :240:32, :514:30] assign ldq_enq_retry_e_e_bits_order_fail = _GEN_244[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :241:32, :514:30] assign ldq_enq_retry_e_e_bits_observed = _GEN_245[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :242:32, :514:30] assign ldq_enq_retry_e_e_bits_st_dep_mask = _GEN_246[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :243:32, :514:30] assign ldq_enq_retry_e_e_bits_ld_byte_mask = _GEN_247[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :244:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_std_val = _GEN_248[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :245:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_stq_idx = _GEN_249[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :246:32, :514:30] assign ldq_enq_retry_e_e_bits_debug_wb_data = _GEN_250[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :247:32, :514:30] reg [4:0] stq_enq_retry_idx; // @[lsu.scala:520:30] wire _stq_enq_retry_idx_T = stq_addr_0_valid & stq_addr_is_virtual_0; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_1 = \|stq_enq_retry_idx; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_2 = _stq_enq_retry_idx_T & _stq_enq_retry_idx_T_1; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_3 = stq_addr_1_valid & stq_addr_is_virtual_1; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_4 = stq_enq_retry_idx != 5'h1; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_5 = _stq_enq_retry_idx_T_3 & _stq_enq_retry_idx_T_4; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_6 = stq_addr_2_valid & stq_addr_is_virtual_2; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_7 = stq_enq_retry_idx != 5'h2; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_8 = _stq_enq_retry_idx_T_6 & _stq_enq_retry_idx_T_7; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_9 = stq_addr_3_valid & stq_addr_is_virtual_3; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_10 = stq_enq_retry_idx != 5'h3; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_11 = _stq_enq_retry_idx_T_9 & _stq_enq_retry_idx_T_10; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_12 = stq_addr_4_valid & stq_addr_is_virtual_4; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_13 = stq_enq_retry_idx != 5'h4; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_14 = _stq_enq_retry_idx_T_12 & _stq_enq_retry_idx_T_13; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_15 = stq_addr_5_valid & stq_addr_is_virtual_5; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_16 = stq_enq_retry_idx != 5'h5; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_17 = _stq_enq_retry_idx_T_15 & _stq_enq_retry_idx_T_16; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_18 = stq_addr_6_valid & stq_addr_is_virtual_6; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_19 = stq_enq_retry_idx != 5'h6; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_20 = _stq_enq_retry_idx_T_18 & _stq_enq_retry_idx_T_19; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_21 = stq_addr_7_valid & stq_addr_is_virtual_7; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_22 = stq_enq_retry_idx != 5'h7; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_23 = _stq_enq_retry_idx_T_21 & _stq_enq_retry_idx_T_22; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_24 = stq_addr_8_valid & stq_addr_is_virtual_8; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_25 = stq_enq_retry_idx != 5'h8; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_26 = _stq_enq_retry_idx_T_24 & _stq_enq_retry_idx_T_25; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_27 = stq_addr_9_valid & stq_addr_is_virtual_9; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_28 = stq_enq_retry_idx != 5'h9; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_29 = _stq_enq_retry_idx_T_27 & _stq_enq_retry_idx_T_28; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_30 = stq_addr_10_valid & stq_addr_is_virtual_10; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_31 = stq_enq_retry_idx != 5'hA; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_32 = _stq_enq_retry_idx_T_30 & _stq_enq_retry_idx_T_31; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_33 = stq_addr_11_valid & stq_addr_is_virtual_11; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_34 = stq_enq_retry_idx != 5'hB; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_35 = _stq_enq_retry_idx_T_33 & _stq_enq_retry_idx_T_34; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_36 = stq_addr_12_valid & stq_addr_is_virtual_12; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_37 = stq_enq_retry_idx != 5'hC; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_38 = _stq_enq_retry_idx_T_36 & _stq_enq_retry_idx_T_37; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_39 = stq_addr_13_valid & stq_addr_is_virtual_13; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_40 = stq_enq_retry_idx != 5'hD; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_41 = _stq_enq_retry_idx_T_39 & _stq_enq_retry_idx_T_40; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_42 = stq_addr_14_valid & stq_addr_is_virtual_14; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_43 = stq_enq_retry_idx != 5'hE; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_44 = _stq_enq_retry_idx_T_42 & _stq_enq_retry_idx_T_43; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_45 = stq_addr_15_valid & stq_addr_is_virtual_15; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_46 = stq_enq_retry_idx != 5'hF; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_47 = _stq_enq_retry_idx_T_45 & _stq_enq_retry_idx_T_46; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_48 = stq_addr_16_valid & stq_addr_is_virtual_16; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_49 = stq_enq_retry_idx != 5'h10; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_50 = _stq_enq_retry_idx_T_48 & _stq_enq_retry_idx_T_49; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_51 = stq_addr_17_valid & stq_addr_is_virtual_17; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_52 = stq_enq_retry_idx != 5'h11; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_53 = _stq_enq_retry_idx_T_51 & _stq_enq_retry_idx_T_52; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_54 = stq_addr_18_valid & stq_addr_is_virtual_18; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_55 = stq_enq_retry_idx != 5'h12; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_56 = _stq_enq_retry_idx_T_54 & _stq_enq_retry_idx_T_55; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_57 = stq_addr_19_valid & stq_addr_is_virtual_19; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_58 = stq_enq_retry_idx != 5'h13; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_59 = _stq_enq_retry_idx_T_57 & _stq_enq_retry_idx_T_58; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_60 = stq_addr_20_valid & stq_addr_is_virtual_20; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_61 = stq_enq_retry_idx != 5'h14; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_62 = _stq_enq_retry_idx_T_60 & _stq_enq_retry_idx_T_61; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_63 = stq_addr_21_valid & stq_addr_is_virtual_21; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_64 = stq_enq_retry_idx != 5'h15; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_65 = _stq_enq_retry_idx_T_63 & _stq_enq_retry_idx_T_64; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_66 = stq_addr_22_valid & stq_addr_is_virtual_22; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_67 = stq_enq_retry_idx != 5'h16; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_68 = _stq_enq_retry_idx_T_66 & _stq_enq_retry_idx_T_67; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_69 = stq_addr_23_valid & stq_addr_is_virtual_23; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_70 = stq_enq_retry_idx != 5'h17; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_71 = _stq_enq_retry_idx_T_69 & _stq_enq_retry_idx_T_70; // @[lsu.scala:522:{23,49,57}] wire _GEN_395 = stq_commit_head == 5'h0; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T = _GEN_395; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T = _GEN_395; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_0 = _stq_enq_retry_idx_T_2 & _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_396 = stq_commit_head < 5'h2; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_1 = _GEN_396; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_1 = _GEN_396; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_1 = _stq_enq_retry_idx_T_5 & _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_397 = stq_commit_head < 5'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_2 = _GEN_397; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_2 = _GEN_397; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_2 = _stq_enq_retry_idx_T_8 & _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_398 = stq_commit_head < 5'h4; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_3 = _GEN_398; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_3 = _GEN_398; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_3 = _stq_enq_retry_idx_T_11 & _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_399 = stq_commit_head < 5'h5; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_4 = _GEN_399; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_4 = _GEN_399; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_4 = _stq_enq_retry_idx_T_14 & _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_400 = stq_commit_head < 5'h6; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_5 = _GEN_400; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_5 = _GEN_400; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_5 = _stq_enq_retry_idx_T_17 & _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_401 = stq_commit_head < 5'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_6 = _GEN_401; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_6 = _GEN_401; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_6 = _stq_enq_retry_idx_T_20 & _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _GEN_402 = stq_commit_head < 5'h8; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_7 = _GEN_402; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_7 = _GEN_402; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_7 = _stq_enq_retry_idx_T_23 & _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_403 = stq_commit_head < 5'h9; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_8 = _GEN_403; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_8 = _GEN_403; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_8 = _stq_enq_retry_idx_T_26 & _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_404 = stq_commit_head < 5'hA; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_9 = _GEN_404; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_9 = _GEN_404; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_9 = _stq_enq_retry_idx_T_29 & _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_405 = stq_commit_head < 5'hB; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_10 = _GEN_405; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_10 = _GEN_405; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_10 = _stq_enq_retry_idx_T_32 & _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_406 = stq_commit_head < 5'hC; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_11 = _GEN_406; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_11 = _GEN_406; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_11 = _stq_enq_retry_idx_T_35 & _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_407 = stq_commit_head < 5'hD; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_12 = _GEN_407; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_12 = _GEN_407; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_12 = _stq_enq_retry_idx_T_38 & _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_408 = stq_commit_head < 5'hE; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_13 = _GEN_408; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_13 = _GEN_408; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_13 = _stq_enq_retry_idx_T_41 & _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_409 = stq_commit_head < 5'hF; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_14 = _GEN_409; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_14 = _GEN_409; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_14 = _stq_enq_retry_idx_T_44 & _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _stq_enq_retry_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_15 = _stq_enq_retry_idx_T_47 & _stq_enq_retry_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _GEN_410 = stq_commit_head < 5'h11; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_16 = _GEN_410; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_16; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_16 = _GEN_410; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_16 = _stq_enq_retry_idx_T_50 & _stq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _GEN_411 = stq_commit_head < 5'h12; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_17 = _GEN_411; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_17; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_17 = _GEN_411; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_17 = _stq_enq_retry_idx_T_53 & _stq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _GEN_412 = stq_commit_head < 5'h13; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_18 = _GEN_412; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_18; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_18 = _GEN_412; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_18 = _stq_enq_retry_idx_T_56 & _stq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _GEN_413 = stq_commit_head < 5'h14; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_19 = _GEN_413; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_19; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_19 = _GEN_413; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_19 = _stq_enq_retry_idx_T_59 & _stq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _GEN_414 = stq_commit_head < 5'h15; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_20 = _GEN_414; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_20; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_20 = _GEN_414; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_20 = _stq_enq_retry_idx_T_62 & _stq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _GEN_415 = stq_commit_head < 5'h16; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_21 = _GEN_415; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_21; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_21 = _GEN_415; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_21 = _stq_enq_retry_idx_T_65 & _stq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _GEN_416 = stq_commit_head < 5'h17; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_22 = _GEN_416; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_22; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_22 = _GEN_416; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_22 = _stq_enq_retry_idx_T_68 & _stq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _GEN_417 = stq_commit_head[4:3] != 2'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_23 = _GEN_417; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_23; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_23 = _GEN_417; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_23 = _stq_enq_retry_idx_T_71 & _stq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _stq_enq_retry_idx_idx_T = {5'h1B, ~_stq_enq_retry_idx_T_68}; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_1 = _stq_enq_retry_idx_T_65 ? 6'h35 : _stq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_2 = _stq_enq_retry_idx_T_62 ? 6'h34 : _stq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_3 = _stq_enq_retry_idx_T_59 ? 6'h33 : _stq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_4 = _stq_enq_retry_idx_T_56 ? 6'h32 : _stq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_5 = _stq_enq_retry_idx_T_53 ? 6'h31 : _stq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_6 = _stq_enq_retry_idx_T_50 ? 6'h30 : _stq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_7 = _stq_enq_retry_idx_T_47 ? 6'h2F : _stq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_8 = _stq_enq_retry_idx_T_44 ? 6'h2E : _stq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_9 = _stq_enq_retry_idx_T_41 ? 6'h2D : _stq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_10 = _stq_enq_retry_idx_T_38 ? 6'h2C : _stq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_11 = _stq_enq_retry_idx_T_35 ? 6'h2B : _stq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_12 = _stq_enq_retry_idx_T_32 ? 6'h2A : _stq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_13 = _stq_enq_retry_idx_T_29 ? 6'h29 : _stq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_14 = _stq_enq_retry_idx_T_26 ? 6'h28 : _stq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_15 = _stq_enq_retry_idx_T_23 ? 6'h27 : _stq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_16 = _stq_enq_retry_idx_T_20 ? 6'h26 : _stq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_17 = _stq_enq_retry_idx_T_17 ? 6'h25 : _stq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_18 = _stq_enq_retry_idx_T_14 ? 6'h24 : _stq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_19 = _stq_enq_retry_idx_T_11 ? 6'h23 : _stq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_20 = _stq_enq_retry_idx_T_8 ? 6'h22 : _stq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_21 = _stq_enq_retry_idx_T_5 ? 6'h21 : _stq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_22 = _stq_enq_retry_idx_T_2 ? 6'h20 : _stq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_23 = _stq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_24 = _stq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_25 = _stq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_26 = _stq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_27 = _stq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_28 = _stq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_29 = _stq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_30 = _stq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_31 = stq_enq_retry_idx_temp_vec_23 ? 6'h17 : _stq_enq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_32 = stq_enq_retry_idx_temp_vec_22 ? 6'h16 : _stq_enq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_33 = stq_enq_retry_idx_temp_vec_21 ? 6'h15 : _stq_enq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_34 = stq_enq_retry_idx_temp_vec_20 ? 6'h14 : _stq_enq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_35 = stq_enq_retry_idx_temp_vec_19 ? 6'h13 : _stq_enq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_36 = stq_enq_retry_idx_temp_vec_18 ? 6'h12 : _stq_enq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_37 = stq_enq_retry_idx_temp_vec_17 ? 6'h11 : _stq_enq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_38 = stq_enq_retry_idx_temp_vec_16 ? 6'h10 : _stq_enq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_39 = stq_enq_retry_idx_temp_vec_15 ? 6'hF : _stq_enq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_40 = stq_enq_retry_idx_temp_vec_14 ? 6'hE : _stq_enq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_41 = stq_enq_retry_idx_temp_vec_13 ? 6'hD : _stq_enq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_42 = stq_enq_retry_idx_temp_vec_12 ? 6'hC : _stq_enq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_43 = stq_enq_retry_idx_temp_vec_11 ? 6'hB : _stq_enq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_44 = stq_enq_retry_idx_temp_vec_10 ? 6'hA : _stq_enq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_45 = stq_enq_retry_idx_temp_vec_9 ? 6'h9 : _stq_enq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_46 = stq_enq_retry_idx_temp_vec_8 ? 6'h8 : _stq_enq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_47 = stq_enq_retry_idx_temp_vec_7 ? 6'h7 : _stq_enq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_48 = stq_enq_retry_idx_temp_vec_6 ? 6'h6 : _stq_enq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_49 = stq_enq_retry_idx_temp_vec_5 ? 6'h5 : _stq_enq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_50 = stq_enq_retry_idx_temp_vec_4 ? 6'h4 : _stq_enq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_51 = stq_enq_retry_idx_temp_vec_3 ? 6'h3 : _stq_enq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_52 = stq_enq_retry_idx_temp_vec_2 ? 6'h2 : _stq_enq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_53 = stq_enq_retry_idx_temp_vec_1 ? 6'h1 : _stq_enq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] stq_enq_retry_idx_idx = stq_enq_retry_idx_temp_vec_0 ? 6'h0 : _stq_enq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_T_72 = stq_enq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] wire stq_enq_retry_e_valid = stq_enq_retry_e_e_valid; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_inst = stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_debug_inst = stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rvc = stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_uop_debug_pc = stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_0 = stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_1 = stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_2 = stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_3 = stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_0 = stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_1 = stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_2 = stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_3 = stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_4 = stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_5 = stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_6 = stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_7 = stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_8 = stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_9 = stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued = stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_agen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_dgen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_iw_p1_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_iw_p2_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p1_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p2_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p3_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_dis_col_sel = stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :524:35] wire [15:0] stq_enq_retry_e_bits_uop_br_mask = stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_tag = stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_type = stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfb = stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fence = stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fencei = stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfence = stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_amo = stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_eret = stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sys_pc2epc = stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rocc = stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_mov = stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ftq_idx = stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_edge_inst = stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_pc_lob = stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_taken = stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_imm_rename = stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_imm_sel = stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_pimm = stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :524:35] wire [19:0] stq_enq_retry_e_bits_uop_imm_packed = stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_op1_sel = stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_op2_sel = stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ldst = stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wen = stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren1 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren2 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren3 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap12 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap23 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fromint = stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_toint = stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fma = stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_div = stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_sqrt = stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wflags = stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_vec = stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_rob_idx = stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ldq_idx = stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_stq_idx = stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_rxq_idx = stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_pdst = stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs1 = stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs2 = stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs3 = stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ppred = stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs1_busy = stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs2_busy = stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs3_busy = stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ppred_busy = stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_stale_pdst = stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_exception = stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_uop_exc_cause = stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_mem_cmd = stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_mem_size = stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_mem_signed = stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_ldq = stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_stq = stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_unique = stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_flush_on_commit = stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_csr_cmd = stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ldst_is_rs1 = stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_ldst = stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs1 = stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs2 = stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs3 = stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dst_rtype = stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs1_rtype = stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs2_rtype = stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_frs3_en = stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fcn_dw = stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_fcn_op = stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_val = stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_fp_rm = stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_typ = stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_pf_if = stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ae_if = stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ma_if = stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_debug_if = stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_xcpt_if = stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_fsrc = stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_tsrc = stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_valid = stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_addr_bits = stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_is_virtual = stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_data_valid = stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_data_bits = stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_committed = stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_succeeded = stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_can_execute = stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_cleared = stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_debug_wb_data = stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :524:35] assign stq_enq_retry_e_e_valid = _GEN_26[stq_enq_retry_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :520:30] assign stq_enq_retry_e_e_bits_uop_inst = _GEN_251[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_inst = _GEN_252[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rvc = _GEN_253[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_pc = _GEN_254[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_255[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_256[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_257[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_258[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_259[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_260[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_261[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_262[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_263[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_264[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_265[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_266[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_267[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_268[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued = _GEN_269[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_277[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_mask = _GEN_278[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_tag = _GEN_279[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_type = _GEN_280[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfb = _GEN_281[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fence = _GEN_282[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fencei = _GEN_283[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfence = _GEN_284[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_amo = _GEN_285[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_eret = _GEN_286[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rocc = _GEN_288[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_mov = _GEN_289[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_290[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_edge_inst = _GEN_291[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pc_lob = _GEN_292[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_taken = _GEN_293[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_rename = _GEN_294[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_sel = _GEN_295[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pimm = _GEN_296[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_packed = _GEN_297[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op1_sel = _GEN_298[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op2_sel = _GEN_299[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rob_idx = _GEN_317[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_318[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stq_idx = _GEN_319[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_320[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pdst = _GEN_321[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1 = _GEN_322[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2 = _GEN_323[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3 = _GEN_324[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred = _GEN_325[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_326[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_327[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_328[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_329[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_330[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exception = _GEN_331[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exc_cause = _GEN_332[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_333[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_size = _GEN_334[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_signed = _GEN_335[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_336[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_stq = _GEN_337[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_unique = _GEN_338[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_339[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_340[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst = _GEN_342[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1 = _GEN_343[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2 = _GEN_344[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs3 = _GEN_345[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_346[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_frs3_en = _GEN_349[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_350[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_op = _GEN_351[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_val = _GEN_352[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_rm = _GEN_353[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_typ = _GEN_354[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_358[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_360[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_361[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_addr_valid = _GEN_362[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_bits = _GEN_363[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_is_virtual = _GEN_364[stq_enq_retry_idx]; // @[lsu.scala:262:17, :266:32, :520:30] assign stq_enq_retry_e_e_bits_data_valid = _GEN_365[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_data_bits = _GEN_366[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_committed = _GEN_367[stq_enq_retry_idx]; // @[lsu.scala:262:17, :268:32, :520:30] assign stq_enq_retry_e_e_bits_succeeded = _GEN_368[stq_enq_retry_idx]; // @[lsu.scala:262:17, :269:32, :520:30] assign stq_enq_retry_e_e_bits_can_execute = _GEN_369[stq_enq_retry_idx]; // @[lsu.scala:262:17, :270:32, :520:30] assign stq_enq_retry_e_e_bits_cleared = _GEN_370[stq_enq_retry_idx]; // @[lsu.scala:262:17, :271:32, :520:30] assign stq_enq_retry_e_e_bits_debug_wb_data = _GEN_371[stq_enq_retry_idx]; // @[lsu.scala:262:17, :272:32, :520:30] wire _can_enq_load_retry_T = ldq_enq_retry_e_valid & ldq_enq_retry_e_bits_addr_valid; // @[lsu.scala:518:33, :526:81] wire can_enq_load_retry = _can_enq_load_retry_T & ldq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:518:33, :526:81, :527:81] wire _can_enq_store_retry_T = stq_enq_retry_e_valid & stq_enq_retry_e_bits_addr_valid; // @[lsu.scala:524:35, :529:81] wire can_enq_store_retry = _can_enq_store_retry_T & stq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:524:35, :529:81, :530:81] wire _retry_queue_io_enq_valid_T = can_enq_store_retry \| can_enq_load_retry; // @[lsu.scala:527:81, :530:81, :537:55] wire [39:0] _retry_queue_io_enq_bits_data_T = can_enq_store_retry ? stq_enq_retry_e_bits_addr_bits : ldq_enq_retry_e_bits_addr_bits; // @[lsu.scala:518:33, :524:35, :530:81, :539:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_inst : ldq_enq_retry_e_bits_uop_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_debug_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_inst : ldq_enq_retry_e_bits_uop_debug_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rvc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rvc : ldq_enq_retry_e_bits_uop_is_rvc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [39:0] _retry_queue_io_enq_bits_uop_T_debug_pc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_pc : ldq_enq_retry_e_bits_uop_debug_pc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_0 : ldq_enq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_1 : ldq_enq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_2 : ldq_enq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_3 : ldq_enq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_0 : ldq_enq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_1 : ldq_enq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_2 : ldq_enq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_3 : ldq_enq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_4 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_4 : ldq_enq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_5 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_5 : ldq_enq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_6 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_6 : ldq_enq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_7 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_7 : ldq_enq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_8 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_8 : ldq_enq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_9 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_9 : ldq_enq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued : ldq_enq_retry_e_bits_uop_iw_issued; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_agen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_agen : ldq_enq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_dgen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_dgen : ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_iw_p1_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_speculative_child : ldq_enq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_iw_p2_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_speculative_child : ldq_enq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p1_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p2_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p3_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p3_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_dis_col_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dis_col_sel : ldq_enq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [15:0] _retry_queue_io_enq_bits_uop_T_br_mask = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_mask : ldq_enq_retry_e_bits_uop_br_mask; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_tag = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_tag : ldq_enq_retry_e_bits_uop_br_tag; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_type = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_type : ldq_enq_retry_e_bits_uop_br_type; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfb = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfb : ldq_enq_retry_e_bits_uop_is_sfb; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fence : ldq_enq_retry_e_bits_uop_is_fence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fencei = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fencei : ldq_enq_retry_e_bits_uop_is_fencei; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfence : ldq_enq_retry_e_bits_uop_is_sfence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_amo = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_amo : ldq_enq_retry_e_bits_uop_is_amo; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_eret = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_eret : ldq_enq_retry_e_bits_uop_is_eret; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sys_pc2epc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sys_pc2epc : ldq_enq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rocc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rocc : ldq_enq_retry_e_bits_uop_is_rocc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_mov = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_mov : ldq_enq_retry_e_bits_uop_is_mov; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ftq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ftq_idx : ldq_enq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_edge_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_edge_inst : ldq_enq_retry_e_bits_uop_edge_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_pc_lob = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pc_lob : ldq_enq_retry_e_bits_uop_pc_lob; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_taken = can_enq_store_retry ? stq_enq_retry_e_bits_uop_taken : ldq_enq_retry_e_bits_uop_taken; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_imm_rename = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_rename : ldq_enq_retry_e_bits_uop_imm_rename; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_imm_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_sel : ldq_enq_retry_e_bits_uop_imm_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_pimm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pimm : ldq_enq_retry_e_bits_uop_pimm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [19:0] _retry_queue_io_enq_bits_uop_T_imm_packed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_packed : ldq_enq_retry_e_bits_uop_imm_packed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_op1_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op1_sel : ldq_enq_retry_e_bits_uop_op1_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_op2_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op2_sel : ldq_enq_retry_e_bits_uop_op2_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ldst : ldq_enq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wen : ldq_enq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren1 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren2 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren3 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap12 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap12 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap23 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap23 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagIn = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagOut = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fromint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fromint : ldq_enq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_toint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_toint : ldq_enq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fastpipe = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe : ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fma = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fma : ldq_enq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_div = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_div : ldq_enq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_sqrt = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_sqrt : ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wflags = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wflags : ldq_enq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_vec = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_vec : ldq_enq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_rob_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rob_idx : ldq_enq_retry_e_bits_uop_rob_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ldq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldq_idx : ldq_enq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_stq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stq_idx : ldq_enq_retry_e_bits_uop_stq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_rxq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rxq_idx : ldq_enq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pdst : ldq_enq_retry_e_bits_uop_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1 : ldq_enq_retry_e_bits_uop_prs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2 : ldq_enq_retry_e_bits_uop_prs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3 : ldq_enq_retry_e_bits_uop_prs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ppred = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred : ldq_enq_retry_e_bits_uop_ppred; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs1_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1_busy : ldq_enq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs2_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2_busy : ldq_enq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs3_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3_busy : ldq_enq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ppred_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred_busy : ldq_enq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_stale_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stale_pdst : ldq_enq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_exception = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exception : ldq_enq_retry_e_bits_uop_exception; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [63:0] _retry_queue_io_enq_bits_uop_T_exc_cause = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exc_cause : ldq_enq_retry_e_bits_uop_exc_cause; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_mem_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_cmd : ldq_enq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_mem_size = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_size : ldq_enq_retry_e_bits_uop_mem_size; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_mem_signed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_signed : ldq_enq_retry_e_bits_uop_mem_signed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_ldq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_ldq : ldq_enq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_stq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_stq : ldq_enq_retry_e_bits_uop_uses_stq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_unique = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_unique : ldq_enq_retry_e_bits_uop_is_unique; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_flush_on_commit = can_enq_store_retry ? stq_enq_retry_e_bits_uop_flush_on_commit : ldq_enq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_csr_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_csr_cmd : ldq_enq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ldst_is_rs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst_is_rs1 : ldq_enq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst : ldq_enq_retry_e_bits_uop_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1 : ldq_enq_retry_e_bits_uop_lrs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2 : ldq_enq_retry_e_bits_uop_lrs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs3 : ldq_enq_retry_e_bits_uop_lrs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dst_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dst_rtype : ldq_enq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs1_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1_rtype : ldq_enq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs2_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2_rtype : ldq_enq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_frs3_en = can_enq_store_retry ? stq_enq_retry_e_bits_uop_frs3_en : ldq_enq_retry_e_bits_uop_frs3_en; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fcn_dw = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_dw : ldq_enq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_fcn_op = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_op : ldq_enq_retry_e_bits_uop_fcn_op; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_val = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_val : ldq_enq_retry_e_bits_uop_fp_val; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_fp_rm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_rm : ldq_enq_retry_e_bits_uop_fp_rm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_typ = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_typ : ldq_enq_retry_e_bits_uop_fp_typ; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_pf_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_pf_if : ldq_enq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ae_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ae_if : ldq_enq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ma_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ma_if : ldq_enq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_debug_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_debug_if : ldq_enq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_xcpt_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_xcpt_if : ldq_enq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_fsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_fsrc : ldq_enq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_tsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_tsrc : ldq_enq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_uses_ldq_T = ~can_enq_store_retry; // @[lsu.scala:530:81, :541:65] wire _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = can_enq_load_retry & _retry_queue_io_enq_bits_uop_uses_ldq_T; // @[lsu.scala:527:81, :541:{62,65}] wire _GEN_418 = will_fire_load_retry_0 \| will_fire_store_retry_0; // @[lsu.scala:476:41, :477:41, :554:65] wire _retry_queue_io_deq_ready_T; // @[lsu.scala:554:65] assign _retry_queue_io_deq_ready_T = _GEN_418; // @[lsu.scala:554:65] wire _exe_tlb_uop_T_1; // @[lsu.scala:720:53] assign _exe_tlb_uop_T_1 = _GEN_418; // @[lsu.scala:554:65, :720:53] wire _exe_tlb_vaddr_T_2; // @[lsu.scala:730:53] assign _exe_tlb_vaddr_T_2 = _GEN_418; // @[lsu.scala:554:65, :730:53] wire stq_execute_queue_flush; // @[lsu.scala:556:41] wire stq_enq_e_valid = stq_enq_e_e_valid; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_inst = stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_debug_inst = stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rvc = stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_uop_debug_pc = stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_0 = stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_1 = stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_2 = stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_3 = stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_0 = stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_1 = stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_2 = stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_3 = stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_4 = stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_5 = stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_6 = stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_7 = stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_8 = stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_9 = stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued = stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_agen = stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_dgen = stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_iw_p1_speculative_child = stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_iw_p2_speculative_child = stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p1_bypass_hint = stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p2_bypass_hint = stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p3_bypass_hint = stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_dis_col_sel = stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :561:27] wire [15:0] stq_enq_e_bits_uop_br_mask = stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_tag = stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_type = stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfb = stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fence = stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fencei = stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfence = stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_amo = stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_eret = stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sys_pc2epc = stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rocc = stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_mov = stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ftq_idx = stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_edge_inst = stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_pc_lob = stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_taken = stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_imm_rename = stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_imm_sel = stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_pimm = stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :561:27] wire [19:0] stq_enq_e_bits_uop_imm_packed = stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_op1_sel = stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_op2_sel = stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ldst = stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wen = stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren1 = stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren2 = stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren3 = stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap12 = stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap23 = stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fromint = stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_toint = stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fastpipe = stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fma = stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_div = stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_sqrt = stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wflags = stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_vec = stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_rob_idx = stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ldq_idx = stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_stq_idx = stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_rxq_idx = stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_pdst = stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs1 = stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs2 = stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs3 = stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ppred = stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs1_busy = stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs2_busy = stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs3_busy = stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ppred_busy = stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_stale_pdst = stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_exception = stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_uop_exc_cause = stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_mem_cmd = stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_mem_size = stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_mem_signed = stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_ldq = stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_stq = stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_unique = stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_flush_on_commit = stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_csr_cmd = stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ldst_is_rs1 = stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_ldst = stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs1 = stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs2 = stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs3 = stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dst_rtype = stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs1_rtype = stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs2_rtype = stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_frs3_en = stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fcn_dw = stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_fcn_op = stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_val = stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_fp_rm = stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_typ = stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_pf_if = stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ae_if = stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ma_if = stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_debug_if = stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_xcpt_if = stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_fsrc = stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_tsrc = stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_valid = stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_addr_bits = stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_is_virtual = stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_data_valid = stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_data_bits = stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_committed = stq_enq_e_e_bits_committed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_succeeded = stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_can_execute = stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_cleared = stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_debug_wb_data = stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :561:27] assign stq_enq_e_e_bits_uop_inst = _GEN_251[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_inst = _GEN_252[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rvc = _GEN_253[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_pc = _GEN_254[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_0 = _GEN_255[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_1 = _GEN_256[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_2 = _GEN_257[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_3 = _GEN_258[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_0 = _GEN_259[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_1 = _GEN_260[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_2 = _GEN_261[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_3 = _GEN_262[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_4 = _GEN_263[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_5 = _GEN_264[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_6 = _GEN_265[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_7 = _GEN_266[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_8 = _GEN_267[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_9 = _GEN_268[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued = _GEN_269[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dis_col_sel = _GEN_277[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_mask = _GEN_278[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_tag = _GEN_279[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_type = _GEN_280[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfb = _GEN_281[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fence = _GEN_282[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fencei = _GEN_283[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfence = _GEN_284[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_amo = _GEN_285[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_eret = _GEN_286[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rocc = _GEN_288[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_mov = _GEN_289[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ftq_idx = _GEN_290[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_edge_inst = _GEN_291[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pc_lob = _GEN_292[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_taken = _GEN_293[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_rename = _GEN_294[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_sel = _GEN_295[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pimm = _GEN_296[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_packed = _GEN_297[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op1_sel = _GEN_298[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op2_sel = _GEN_299[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rob_idx = _GEN_317[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldq_idx = _GEN_318[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stq_idx = _GEN_319[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rxq_idx = _GEN_320[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pdst = _GEN_321[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1 = _GEN_322[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2 = _GEN_323[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3 = _GEN_324[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred = _GEN_325[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1_busy = _GEN_326[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2_busy = _GEN_327[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3_busy = _GEN_328[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred_busy = _GEN_329[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stale_pdst = _GEN_330[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exception = _GEN_331[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exc_cause = _GEN_332[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_cmd = _GEN_333[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_size = _GEN_334[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_signed = _GEN_335[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_ldq = _GEN_336[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_stq = _GEN_337[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_unique = _GEN_338[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_flush_on_commit = _GEN_339[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_csr_cmd = _GEN_340[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst = _GEN_342[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1 = _GEN_343[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2 = _GEN_344[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs3 = _GEN_345[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dst_rtype = _GEN_346[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_frs3_en = _GEN_349[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_dw = _GEN_350[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_op = _GEN_351[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_val = _GEN_352[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_rm = _GEN_353[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_typ = _GEN_354[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_debug_if = _GEN_358[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_fsrc = _GEN_360[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_tsrc = _GEN_361[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_addr_valid = _GEN_362[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_bits = _GEN_363[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_is_virtual = _GEN_364[stq_execute_head]; // @[lsu.scala:262:17, :266:32, :283:29] assign stq_enq_e_e_bits_data_valid = _GEN_365[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_data_bits = _GEN_366[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_committed = _GEN_367[stq_execute_head]; // @[lsu.scala:262:17, :268:32, :283:29] assign stq_enq_e_e_bits_succeeded = _GEN_368[stq_execute_head]; // @[lsu.scala:262:17, :269:32, :283:29] assign stq_enq_e_e_bits_can_execute = _GEN_369[stq_execute_head]; // @[lsu.scala:262:17, :270:32, :283:29] assign stq_enq_e_e_bits_cleared = _GEN_370[stq_execute_head]; // @[lsu.scala:262:17, :271:32, :283:29] assign stq_enq_e_e_bits_debug_wb_data = _GEN_371[stq_execute_head]; // @[lsu.scala:262:17, :272:32, :283:29] wire _T_1639 = will_fire_store_commit_fast_0 \| will_fire_store_commit_slow_0; // @[lsu.scala:478:41, :479:41, :565:78] wire _stq_execute_queue_io_deq_ready_T; // @[lsu.scala:565:78] assign _stq_execute_queue_io_deq_ready_T = _T_1639; // @[lsu.scala:565:78] wire _fired_store_commit_T; // @[lsu.scala:1048:83] assign _fired_store_commit_T = _T_1639; // @[lsu.scala:565:78, :1048:83] wire _can_enq_store_execute_T = stq_enq_e_valid & stq_enq_e_bits_addr_valid; // @[lsu.scala:561:27, :568:21] wire _can_enq_store_execute_T_1 = _can_enq_store_execute_T & stq_enq_e_bits_data_valid; // @[lsu.scala:561:27, :568:21, :569:31] wire _can_enq_store_execute_T_2 = ~stq_enq_e_bits_addr_is_virtual; // @[lsu.scala:561:27, :571:4] wire _can_enq_store_execute_T_3 = _can_enq_store_execute_T_1 & _can_enq_store_execute_T_2; // @[lsu.scala:569:31, :570:31, :571:4] wire _can_enq_store_execute_T_4 = ~stq_enq_e_bits_uop_exception; // @[lsu.scala:561:27, :572:4] wire _can_enq_store_execute_T_5 = _can_enq_store_execute_T_3 & _can_enq_store_execute_T_4; // @[lsu.scala:570:31, :571:36, :572:4] wire _can_enq_store_execute_T_6 = ~stq_enq_e_bits_uop_is_fence; // @[lsu.scala:561:27, :573:4] wire _can_enq_store_execute_T_7 = _can_enq_store_execute_T_5 & _can_enq_store_execute_T_6; // @[lsu.scala:571:36, :572:34, :573:4] wire _can_enq_store_execute_T_8 = stq_enq_e_bits_committed \| stq_enq_e_bits_uop_is_amo; // @[lsu.scala:561:27, :574:30] wire can_enq_store_execute = _can_enq_store_execute_T_7 & _can_enq_store_execute_T_8; // @[lsu.scala:572:34, :573:33, :574:30] wire _GEN_419 = stq_execute_head == 5'h17; // @[util.scala:213:25] wire stq_execute_head_wrap; // @[util.scala:213:25] assign stq_execute_head_wrap = _GEN_419; // @[util.scala:213:25] wire stq_execute_head_wrap_1; // @[util.scala:213:25] assign stq_execute_head_wrap_1 = _GEN_419; // @[util.scala:213:25] wire [5:0] _GEN_420 = {1'h0, stq_execute_head} + 6'h1; // @[util.scala:214:28] wire [5:0] _stq_execute_head_T; // @[util.scala:214:28] assign _stq_execute_head_T = _GEN_420; // @[util.scala:214:28] wire [5:0] _stq_execute_head_T_3; // @[util.scala:214:28] assign _stq_execute_head_T_3 = _GEN_420; // @[util.scala:214:28] wire [4:0] _stq_execute_head_T_1 = _stq_execute_head_T[4:0]; // @[util.scala:214:28] wire [4:0] _stq_execute_head_T_2 = stq_execute_head_wrap ? 5'h0 : _stq_execute_head_T_1; // @[util.scala:213:25, :214:{10,28}] wire _can_fire_load_agen_exec_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :586:61] wire can_fire_load_agen_exec_0 = _can_fire_load_agen_exec_T; // @[lsu.scala:321:49, :586:61] wire _can_fire_store_agen_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :590:61] wire can_fire_store_agen_0 = _can_fire_store_agen_T; // @[lsu.scala:321:49, :590:61] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0; // @[lsu.scala:321:49, :656:32] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:321:49, :598:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_load_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :603:79] reg can_fire_load_retry_REG; // @[lsu.scala:605:41] wire _can_fire_load_retry_T_1 = ~can_fire_load_retry_REG; // @[lsu.scala:605:{33,41}] wire _can_fire_load_retry_T_2 = _can_fire_load_retry_T & _can_fire_load_retry_T_1; // @[lsu.scala:603:79, :604:79, :605:33] wire _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; // @[lsu.scala:604:79, :605:79] wire can_fire_load_retry_0 = _can_fire_load_retry_T_3; // @[lsu.scala:321:49, :605:79] wire _can_fire_store_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :610:79] wire _can_fire_store_retry_T_1 = _can_fire_store_retry_T; // @[lsu.scala:610:79, :611:79] wire can_fire_store_retry_0 = _can_fire_store_retry_T_1; // @[lsu.scala:321:49, :611:79] wire _can_fire_store_commit_slow_T = ~mem_xcpt_valid; // @[lsu.scala:457:29, :617:38] wire _can_fire_store_commit_slow_T_1 = _stq_execute_queue_io_deq_valid & _can_fire_store_commit_slow_T; // @[lsu.scala:558:11, :616:84, :617:38] wire _can_fire_store_commit_slow_T_2 = _can_fire_store_commit_slow_T_1; // @[lsu.scala:616:84, :617:84] wire can_fire_store_commit_slow_0 = _can_fire_store_commit_slow_T_2; // @[lsu.scala:321:49, :617:84] wire _will_fire_store_commit_slow_0_will_fire_T_3 = can_fire_store_commit_slow_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_store_commit_fast_T = can_fire_store_commit_slow_0 & stq_almost_full; // @[lsu.scala:321:49, :494:32, :620:80] wire can_fire_store_commit_fast_0 = _can_fire_store_commit_fast_T; // @[lsu.scala:321:49, :620:80] wire _will_fire_store_commit_fast_0_will_fire_T_3 = can_fire_store_commit_fast_0; // @[lsu.scala:321:49, :656:32] wire block_load_wakeup; // @[lsu.scala:623:35] wire _can_fire_load_wakeup_T = ldq_wakeup_e_valid & ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:510:32, :625:88] wire _can_fire_load_wakeup_T_1 = ~ldq_wakeup_e_bits_succeeded; // @[lsu.scala:510:32, :627:31] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:625:88, :626:88, :627:31] wire _can_fire_load_wakeup_T_3 = ~ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:510:32, :628:31] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:626:88, :627:88, :628:31] wire _can_fire_load_wakeup_T_5 = ~ldq_wakeup_e_bits_executed; // @[lsu.scala:510:32, :629:31] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:627:88, :628:88, :629:31] wire _can_fire_load_wakeup_T_7 = ~ldq_wakeup_e_bits_order_fail; // @[lsu.scala:510:32, :630:31] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:628:88, :629:88, :630:31] wire [4:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire [31:0] _GEN_421 = {{p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_23}, {p1_block_load_mask_22}, {p1_block_load_mask_21}, {p1_block_load_mask_20}, {p1_block_load_mask_19}, {p1_block_load_mask_18}, {p1_block_load_mask_17}, {p1_block_load_mask_16}, {p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:489:35, :631:31] wire _can_fire_load_wakeup_T_11 = ~_GEN_421[_can_fire_load_wakeup_T_10]; // @[lsu.scala:631:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:629:88, :630:88, :631:31] wire [4:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire [31:0] _GEN_422 = {{p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_23}, {p2_block_load_mask_22}, {p2_block_load_mask_21}, {p2_block_load_mask_20}, {p2_block_load_mask_19}, {p2_block_load_mask_18}, {p2_block_load_mask_17}, {p2_block_load_mask_16}, {p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:490:35, :632:31] wire _can_fire_load_wakeup_T_15 = ~_GEN_422[_can_fire_load_wakeup_T_14]; // @[lsu.scala:632:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:630:88, :631:88, :632:31] reg can_fire_load_wakeup_REG; // @[lsu.scala:633:39] wire _can_fire_load_wakeup_T_17 = ~can_fire_load_wakeup_REG; // @[lsu.scala:633:{31,39}] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:631:88, :632:88, :633:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:623:35, :634:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:632:88, :633:88, :634:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:633:88, :634:88] wire _can_fire_load_wakeup_T_22 = ~ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:510:32, :636:32] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:278:29, :506:31, :637:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:211:7, :636:107, :637:84] wire _can_fire_load_wakeup_T_25 = ldq_wakeup_e_bits_st_dep_mask == 24'h0; // @[lsu.scala:510:32, :638:112] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:636:107, :637:103, :638:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 \| _can_fire_load_wakeup_T_26; // @[lsu.scala:636:{32,71}, :637:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:634:88, :635:88, :636:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:321:49, :635:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:321:49, :656:32] wire can_fire_hella_incoming_0; // @[lsu.scala:641:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:644:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:644:42, :656:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:696:25] wire exe_tlb_valid_0; // @[lsu.scala:649:27] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:472:41, :657:65] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_sfence_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_commit_fast_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_commit_fast_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_fast_0_will_fire_T_7 = _will_fire_store_commit_fast_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_store_commit_fast_0_will_fire = _will_fire_store_commit_fast_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_store_commit_fast_0 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:478:41, :657:65] wire _will_fire_store_commit_fast_0_T_6 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_fast_0_T_7 = ~_will_fire_store_commit_fast_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_fast_0_T_8 = _will_fire_store_commit_fast_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_exec_0_will_fire_T = ~_will_fire_store_commit_fast_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_exec_0_will_fire_T_1 = _will_fire_load_agen_exec_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_exec_0_will_fire_T_2 = ~_will_fire_load_agen_exec_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_exec_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_exec_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_exec_0_will_fire_T_7 = _will_fire_load_agen_exec_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_load_agen_exec_0_will_fire_T_8 = ~_will_fire_store_commit_fast_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_agen_exec_0_will_fire_T_9 = _will_fire_load_agen_exec_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_agen_exec_0_will_fire_T_10 = ~_will_fire_load_agen_exec_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_agen_exec_0_will_fire = _will_fire_load_agen_exec_0_will_fire_T_7 & _will_fire_load_agen_exec_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_agen_exec_0 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:469:39, :657:65] wire _will_fire_load_agen_exec_0_T = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_exec_0_T_3 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_exec_0_T_6 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_agen_exec_0_T_1 = ~_will_fire_load_agen_exec_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_exec_0_T_2 = _will_fire_store_commit_fast_0_T_2 & _will_fire_load_agen_exec_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_exec_0_T_4 = ~_will_fire_load_agen_exec_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_exec_0_T_5 = _will_fire_load_agen_exec_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_agen_exec_0_T_7 = ~_will_fire_load_agen_exec_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_agen_exec_0_T_8 = _will_fire_store_commit_fast_0_T_8 & _will_fire_load_agen_exec_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_0_T_8 = _will_fire_load_agen_exec_0_T_8; // @[lsu.scala:661:31] wire _will_fire_load_agen_0_will_fire_T = ~_will_fire_load_agen_exec_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_0_will_fire_T_1 = _will_fire_load_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_0_will_fire_T_2 = ~_will_fire_load_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_0_will_fire_T_4 = ~_will_fire_load_agen_exec_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_agen_0_will_fire_T_5 = _will_fire_load_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_agen_0_will_fire_T_6 = ~_will_fire_load_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_agen_0_will_fire_T_7 = _will_fire_load_agen_0_will_fire_T_3 & _will_fire_load_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_load_agen_0_will_fire = _will_fire_load_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_load_agen_0_will_fire_T_8 = ~_will_fire_load_agen_exec_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_load_agen_0 = will_fire_load_agen_0_will_fire; // @[lsu.scala:470:41, :657:65] wire _will_fire_load_agen_0_T = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_0_T_3 = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_0_T_1 = ~_will_fire_load_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_0_T_2 = _will_fire_load_agen_exec_0_T_2 & _will_fire_load_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_0_T_4 = ~_will_fire_load_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_0_T_5 = _will_fire_load_agen_exec_0_T_5 & _will_fire_load_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_agen_0_T_8 = _will_fire_load_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_agen_0_will_fire_T = ~_will_fire_load_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_agen_0_will_fire_T_1 = _will_fire_store_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_agen_0_will_fire_T_2 = ~_will_fire_store_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_agen_0_will_fire_T_3 = can_fire_store_agen_0 & _will_fire_store_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_agen_0_will_fire_T_4 = ~_will_fire_load_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_agen_0_will_fire_T_5 = _will_fire_store_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_agen_0_will_fire_T_6 = ~_will_fire_store_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_agen_0_will_fire_T_7 = _will_fire_store_agen_0_will_fire_T_3 & _will_fire_store_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_agen_0_will_fire = _will_fire_store_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_agen_0_will_fire_T_8 = ~_will_fire_load_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_agen_0 = will_fire_store_agen_0_will_fire; // @[lsu.scala:471:41, :657:65] wire _will_fire_store_agen_0_T = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_agen_0_T_3 = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_agen_0_T_1 = ~_will_fire_store_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_agen_0_T_2 = _will_fire_load_agen_0_T_2 & _will_fire_store_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_store_agen_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_agen_0_T_4 = ~_will_fire_store_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_agen_0_T_5 = _will_fire_load_agen_0_T_5 & _will_fire_store_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_release_0_T_8 = _will_fire_store_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_store_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_store_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_store_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:475:41, :657:65] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_store_agen_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:641:42, :656:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:473:41, :657:65] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:659:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:474:41, :657:65] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_retry_0_will_fire_T_1 = _will_fire_store_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_retry_0_will_fire_T_2 = ~_will_fire_store_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_retry_0_will_fire_T_3 = can_fire_store_retry_0 & _will_fire_store_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_retry_0_will_fire_T_5 = _will_fire_store_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_retry_0_will_fire_T_6 = ~_will_fire_store_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_retry_0_will_fire_T_7 = _will_fire_store_retry_0_will_fire_T_3 & _will_fire_store_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_retry_0_will_fire = _will_fire_store_retry_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_retry_0 = will_fire_store_retry_0_will_fire; // @[lsu.scala:477:41, :657:65] wire _will_fire_store_retry_0_T = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_retry_0_T_3 = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_retry_0_T_1 = ~_will_fire_store_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_store_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_retry_0_T_4 = ~_will_fire_store_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_store_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_store_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_store_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_store_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:476:41, :657:65] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_store_retry_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_load_retry_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_store_retry_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_store_retry_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:480:41, :657:65] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_commit_slow_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:660:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_load_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_commit_slow_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_slow_0_will_fire_T_7 = _will_fire_store_commit_slow_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_store_commit_slow_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_commit_slow_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_store_commit_slow_0_will_fire_T_9 = _will_fire_store_commit_slow_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_store_commit_slow_0_will_fire_T_10 = ~_will_fire_store_commit_slow_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_store_commit_slow_0_will_fire = _will_fire_store_commit_slow_0_will_fire_T_7 & _will_fire_store_commit_slow_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_store_commit_slow_0 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:479:41, :657:65] wire _will_fire_store_commit_slow_0_T_6 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_7 = ~_will_fire_store_commit_slow_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_slow_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_slow_0_T_7; // @[lsu.scala:661:{31,34}] wire _T_226 = will_fire_load_agen_exec_0 \| will_fire_load_agen_0; // @[lsu.scala:469:39, :470:41, :687:61] wire _exe_tlb_uop_T; // @[lsu.scala:717:53] assign _exe_tlb_uop_T = _T_226; // @[lsu.scala:687:61, :717:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:726:53] assign _exe_tlb_vaddr_T = _T_226; // @[lsu.scala:687:61, :726:53] wire _exe_size_T; // @[lsu.scala:738:52] assign _exe_size_T = _T_226; // @[lsu.scala:687:61, :738:52] wire _exe_cmd_T; // @[lsu.scala:746:52] assign _exe_cmd_T = _T_226; // @[lsu.scala:687:61, :746:52] wire _ldq_idx_T; // @[lsu.scala:969:48] assign _ldq_idx_T = _T_226; // @[lsu.scala:687:61, :969:48] wire _GEN_423 = ldq_wakeup_idx == 5'h0; // @[lsu.scala:506:31, :690:49] wire _GEN_424 = ldq_wakeup_idx == 5'h1; // @[lsu.scala:506:31, :690:49] wire _GEN_425 = ldq_wakeup_idx == 5'h2; // @[lsu.scala:506:31, :690:49] wire _GEN_426 = ldq_wakeup_idx == 5'h3; // @[lsu.scala:506:31, :690:49] wire _GEN_427 = ldq_wakeup_idx == 5'h4; // @[lsu.scala:506:31, :690:49] wire _GEN_428 = ldq_wakeup_idx == 5'h5; // @[lsu.scala:506:31, :690:49] wire _GEN_429 = ldq_wakeup_idx == 5'h6; // @[lsu.scala:506:31, :690:49] wire _GEN_430 = ldq_wakeup_idx == 5'h7; // @[lsu.scala:506:31, :690:49] wire _GEN_431 = ldq_wakeup_idx == 5'h8; // @[lsu.scala:506:31, :690:49] wire _GEN_432 = ldq_wakeup_idx == 5'h9; // @[lsu.scala:506:31, :690:49] wire _GEN_433 = ldq_wakeup_idx == 5'hA; // @[lsu.scala:506:31, :690:49] wire _GEN_434 = ldq_wakeup_idx == 5'hB; // @[lsu.scala:506:31, :690:49] wire _GEN_435 = ldq_wakeup_idx == 5'hC; // @[lsu.scala:506:31, :690:49] wire _GEN_436 = ldq_wakeup_idx == 5'hD; // @[lsu.scala:506:31, :690:49] wire _GEN_437 = ldq_wakeup_idx == 5'hE; // @[lsu.scala:506:31, :690:49] wire _GEN_438 = ldq_wakeup_idx == 5'hF; // @[lsu.scala:506:31, :690:49] wire _GEN_439 = ldq_wakeup_idx == 5'h10; // @[lsu.scala:506:31, :690:49] wire _GEN_440 = ldq_wakeup_idx == 5'h11; // @[lsu.scala:506:31, :690:49] wire _GEN_441 = ldq_wakeup_idx == 5'h12; // @[lsu.scala:506:31, :690:49] wire _GEN_442 = ldq_wakeup_idx == 5'h13; // @[lsu.scala:506:31, :690:49] wire _GEN_443 = ldq_wakeup_idx == 5'h14; // @[lsu.scala:506:31, :690:49] wire _GEN_444 = ldq_wakeup_idx == 5'h15; // @[lsu.scala:506:31, :690:49] wire _GEN_445 = ldq_wakeup_idx == 5'h16; // @[lsu.scala:506:31, :690:49] wire _GEN_446 = ldq_wakeup_idx == 5'h17; // @[lsu.scala:506:31, :690:49] wire _GEN_447 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h0; // @[lsu.scala:533:27, :694:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_423 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h0 : will_fire_load_retry_0 & _GEN_447; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_448 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h1; // @[lsu.scala:533:27, :694:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_424 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h1 : will_fire_load_retry_0 & _GEN_448; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_449 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h2; // @[lsu.scala:533:27, :694:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_425 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h2 : will_fire_load_retry_0 & _GEN_449; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_450 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h3; // @[lsu.scala:533:27, :694:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_426 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h3 : will_fire_load_retry_0 & _GEN_450; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_451 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h4; // @[lsu.scala:533:27, :694:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_427 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h4 : will_fire_load_retry_0 & _GEN_451; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_452 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h5; // @[lsu.scala:533:27, :694:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_428 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h5 : will_fire_load_retry_0 & _GEN_452; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_453 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h6; // @[lsu.scala:533:27, :694:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_429 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h6 : will_fire_load_retry_0 & _GEN_453; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_454 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h7; // @[lsu.scala:533:27, :694:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_430 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h7 : will_fire_load_retry_0 & _GEN_454; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_455 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h8; // @[lsu.scala:533:27, :694:49] assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_431 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h8 : will_fire_load_retry_0 & _GEN_455; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_456 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h9; // @[lsu.scala:533:27, :694:49] assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_432 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h9 : will_fire_load_retry_0 & _GEN_456; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_457 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hA; // @[lsu.scala:533:27, :694:49] assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_433 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hA : will_fire_load_retry_0 & _GEN_457; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_458 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hB; // @[lsu.scala:533:27, :694:49] assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_434 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hB : will_fire_load_retry_0 & _GEN_458; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_459 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hC; // @[lsu.scala:533:27, :694:49] assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_435 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hC : will_fire_load_retry_0 & _GEN_459; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_460 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hD; // @[lsu.scala:533:27, :694:49] assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_436 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hD : will_fire_load_retry_0 & _GEN_460; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_461 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hE; // @[lsu.scala:533:27, :694:49] assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_437 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hE : will_fire_load_retry_0 & _GEN_461; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_462 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hF; // @[lsu.scala:533:27, :694:49] assign block_load_mask_15 = will_fire_load_wakeup_0 ? _GEN_438 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hF : will_fire_load_retry_0 & _GEN_462; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_463 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h10; // @[lsu.scala:533:27, :694:49] assign block_load_mask_16 = will_fire_load_wakeup_0 ? _GEN_439 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h10 : will_fire_load_retry_0 & _GEN_463; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_464 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h11; // @[lsu.scala:533:27, :694:49] assign block_load_mask_17 = will_fire_load_wakeup_0 ? _GEN_440 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h11 : will_fire_load_retry_0 & _GEN_464; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_465 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h12; // @[lsu.scala:533:27, :694:49] assign block_load_mask_18 = will_fire_load_wakeup_0 ? _GEN_441 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h12 : will_fire_load_retry_0 & _GEN_465; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_466 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h13; // @[lsu.scala:533:27, :694:49] assign block_load_mask_19 = will_fire_load_wakeup_0 ? _GEN_442 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h13 : will_fire_load_retry_0 & _GEN_466; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_467 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h14; // @[lsu.scala:533:27, :694:49] assign block_load_mask_20 = will_fire_load_wakeup_0 ? _GEN_443 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h14 : will_fire_load_retry_0 & _GEN_467; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_468 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h15; // @[lsu.scala:533:27, :694:49] assign block_load_mask_21 = will_fire_load_wakeup_0 ? _GEN_444 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h15 : will_fire_load_retry_0 & _GEN_468; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_469 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h16; // @[lsu.scala:533:27, :694:49] assign block_load_mask_22 = will_fire_load_wakeup_0 ? _GEN_445 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h16 : will_fire_load_retry_0 & _GEN_469; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_470 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h17; // @[lsu.scala:533:27, :694:49] assign block_load_mask_23 = will_fire_load_wakeup_0 ? _GEN_446 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h17 : will_fire_load_retry_0 & _GEN_470; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_slow_0_T_2; // @[lsu.scala:659:31, :696:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:649:27, :696:25] wire [31:0] _exe_tlb_uop_T_3_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_3_debug_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rvc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27, :720:{24,53}] wire [39:0] _exe_tlb_uop_T_3_debug_pc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_pc : 40'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_4 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_5 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_6 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_7 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_8 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_9 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_agen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_dgen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_iw_p1_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_iw_p2_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p1_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p2_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p3_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_dis_col_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [15:0] _exe_tlb_uop_T_3_br_mask = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_mask : 16'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_tag = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_tag : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_type = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_type : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfb = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fencei = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_amo = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_eret = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sys_pc2epc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rocc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_mov = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ftq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_edge_inst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_pc_lob = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pc_lob : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_taken = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_imm_rename = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_imm_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_pimm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pimm : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [19:0] _exe_tlb_uop_T_3_imm_packed = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_packed : 20'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_op1_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op1_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_op2_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op2_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ldst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap12 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap23 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagIn = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagOut = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fromint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_toint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fastpipe = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fma = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_div = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_sqrt = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wflags = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_vec = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_rob_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rob_idx : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ldq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_stq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs1 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs2 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs3 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ppred = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ppred : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs1_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs2_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs3_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ppred_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_stale_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_exception = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27, :720:{24,53}] wire [63:0] _exe_tlb_uop_T_3_exc_cause = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_exc_cause : 64'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_mem_size = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_size : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_mem_signed = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_ldq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_stq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_unique = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_flush_on_commit = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_csr_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ldst_is_rs1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_ldst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldst : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs3 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_frs3_en = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fcn_dw = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_fcn_op = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fcn_op : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_val = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_fp_rm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_rm : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_typ = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_typ : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_pf_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ae_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ma_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_debug_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_xcpt_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_fsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_tsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_3_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_3_debug_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rvc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_3_is_rvc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_3_debug_pc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_3_iq_type_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_3_iq_type_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_3_iq_type_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_3_iq_type_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_3_fu_code_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_3_fu_code_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_3_fu_code_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_3_fu_code_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_4 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_3_fu_code_4; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_5 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_3_fu_code_5; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_6 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_3_fu_code_6; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_7 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_3_fu_code_7; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_8 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_3_fu_code_8; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_9 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_3_fu_code_9; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_3_iw_issued; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_agen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_3_iw_issued_partial_agen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_dgen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_3_iw_issued_partial_dgen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_iw_p1_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_3_iw_p1_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_iw_p2_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_3_iw_p2_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p1_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_3_iw_p1_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p2_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_3_iw_p2_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p3_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_3_iw_p3_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_dis_col_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_3_dis_col_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [15:0] _exe_tlb_uop_T_4_br_mask = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_3_br_mask; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_3_br_tag; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_type = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_3_br_type; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfb = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_3_is_sfb; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_3_is_fence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fencei = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_3_is_fencei; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_3_is_sfence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_amo = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_3_is_amo; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_eret = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_3_is_eret; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_3_is_sys_pc2epc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rocc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_3_is_rocc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_mov = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_3_is_mov; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_3_ftq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_edge_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_3_edge_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_3_pc_lob; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_taken = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_3_taken; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_imm_rename = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_3_imm_rename; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_imm_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_3_imm_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_pimm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_3_pimm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_3_imm_packed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_op1_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_3_op1_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_op2_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_3_op2_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_3_fp_ctrl_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_3_fp_ctrl_wen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_3_fp_ctrl_ren1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_3_fp_ctrl_ren2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_3_fp_ctrl_ren3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap12 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_3_fp_ctrl_swap12; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap23 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_3_fp_ctrl_swap23; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagIn = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_3_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagOut = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_3_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fromint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_3_fp_ctrl_fromint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_toint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_3_fp_ctrl_toint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fastpipe = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_3_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fma = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_3_fp_ctrl_fma; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_div = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_3_fp_ctrl_div; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_sqrt = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_3_fp_ctrl_sqrt; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wflags = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_3_fp_ctrl_wflags; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_vec = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_3_fp_ctrl_vec; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_rob_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_3_rob_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_3_ldq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_stq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_3_stq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_3_rxq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_3_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_3_prs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_3_prs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_3_prs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_3_ppred; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_3_prs1_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_3_prs2_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_3_prs3_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_3_ppred_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_3_stale_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_exception = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_3_exception; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_3_exc_cause; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_3_mem_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_3_mem_size; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_mem_signed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_3_mem_signed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_3_uses_ldq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_stq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_3_uses_stq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_unique = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_3_is_unique; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_3_flush_on_commit; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_csr_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_3_csr_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_3_ldst_is_rs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_3_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_3_lrs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_3_lrs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_3_lrs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_3_dst_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_3_lrs1_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_3_lrs2_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_frs3_en = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_3_frs3_en; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fcn_dw = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_3_fcn_dw; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_fcn_op = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_3_fcn_op; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_val = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_3_fp_val; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_fp_rm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_3_fp_rm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_typ = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_3_fp_typ; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_3_xcpt_pf_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_3_xcpt_ae_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_3_xcpt_ma_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_3_bp_debug_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_3_bp_xcpt_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_3_debug_fsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_3_debug_tsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_5_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] _exe_tlb_uop_T_5_debug_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rvc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [39:0] _exe_tlb_uop_T_5_debug_pc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_4_iq_type_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_4_iq_type_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_4_iq_type_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_4_iq_type_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_4_fu_code_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_4_fu_code_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_4_fu_code_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_4_fu_code_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_4 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_4_fu_code_4; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_5 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_4_fu_code_5; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_6 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_4_fu_code_6; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_7 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_4_fu_code_7; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_8 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_4_fu_code_8; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_9 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_4_fu_code_9; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_4_iw_issued; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_agen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_4_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_dgen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_4_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_iw_p1_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_4_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_iw_p2_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_4_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p1_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_4_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p2_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_4_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p3_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_4_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_dis_col_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_4_dis_col_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [15:0] _exe_tlb_uop_T_5_br_mask = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_tag = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_type = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_4_br_type; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfb = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fencei = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_4_is_sfence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_amo = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_eret = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_4_is_eret; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sys_pc2epc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rocc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_4_is_rocc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_mov = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_4_is_mov; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ftq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_edge_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_pc_lob = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_taken = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_imm_rename = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_4_imm_rename; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_imm_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_4_imm_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_pimm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_4_pimm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [19:0] _exe_tlb_uop_T_5_imm_packed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_op1_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_4_op1_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_op2_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_4_op2_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_4_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_4_fp_ctrl_wen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_4_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_4_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_4_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap12 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_4_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap23 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_4_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagIn = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_4_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagOut = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_4_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fromint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_4_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_toint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_4_fp_ctrl_toint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fastpipe = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_4_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fma = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_4_fp_ctrl_fma; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_div = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_4_fp_ctrl_div; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_sqrt = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_4_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wflags = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_4_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_vec = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_4_fp_ctrl_vec; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_rob_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ldq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_stq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ppred = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs1_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs2_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs3_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ppred_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_stale_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_exception = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [63:0] _exe_tlb_uop_T_5_exc_cause = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_mem_size = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_mem_signed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_ldq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_stq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_unique = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_flush_on_commit = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_csr_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_4_csr_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ldst_is_rs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_frs3_en = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fcn_dw = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_4_fcn_dw; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_fcn_op = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_4_fcn_op; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_val = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_fp_rm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_4_fp_rm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_typ = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_4_fp_typ; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_pf_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ae_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ma_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_debug_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_xcpt_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_fsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_tsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_5_inst; // @[lsu.scala:321:49, :717:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:321:49, :717:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_0 = _exe_tlb_uop_T_5_iq_type_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_1 = _exe_tlb_uop_T_5_iq_type_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_2 = _exe_tlb_uop_T_5_iq_type_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_3 = _exe_tlb_uop_T_5_iq_type_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_0 = _exe_tlb_uop_T_5_fu_code_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_1 = _exe_tlb_uop_T_5_fu_code_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_2 = _exe_tlb_uop_T_5_fu_code_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_3 = _exe_tlb_uop_T_5_fu_code_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_4 = _exe_tlb_uop_T_5_fu_code_4; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_5 = _exe_tlb_uop_T_5_fu_code_5; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_6 = _exe_tlb_uop_T_5_fu_code_6; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_7 = _exe_tlb_uop_T_5_fu_code_7; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_8 = _exe_tlb_uop_T_5_fu_code_8; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_9 = _exe_tlb_uop_T_5_fu_code_9; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued = _exe_tlb_uop_T_5_iw_issued; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_agen = _exe_tlb_uop_T_5_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_dgen = _exe_tlb_uop_T_5_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_iw_p1_speculative_child = _exe_tlb_uop_T_5_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_iw_p2_speculative_child = _exe_tlb_uop_T_5_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p1_bypass_hint = _exe_tlb_uop_T_5_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p2_bypass_hint = _exe_tlb_uop_T_5_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p3_bypass_hint = _exe_tlb_uop_T_5_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_dis_col_sel = _exe_tlb_uop_T_5_dis_col_sel; // @[lsu.scala:321:49, :717:24] wire [15:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_type = _exe_tlb_uop_T_5_br_type; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfence = _exe_tlb_uop_T_5_is_sfence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_eret = _exe_tlb_uop_T_5_is_eret; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rocc = _exe_tlb_uop_T_5_is_rocc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_mov = _exe_tlb_uop_T_5_is_mov; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_5_taken; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_imm_rename = _exe_tlb_uop_T_5_imm_rename; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_imm_sel = _exe_tlb_uop_T_5_imm_sel; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_pimm = _exe_tlb_uop_T_5_pimm; // @[lsu.scala:321:49, :717:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_op1_sel = _exe_tlb_uop_T_5_op1_sel; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_op2_sel = _exe_tlb_uop_T_5_op2_sel; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ldst = _exe_tlb_uop_T_5_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wen = _exe_tlb_uop_T_5_fp_ctrl_wen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren1 = _exe_tlb_uop_T_5_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren2 = _exe_tlb_uop_T_5_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren3 = _exe_tlb_uop_T_5_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap12 = _exe_tlb_uop_T_5_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap23 = _exe_tlb_uop_T_5_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagIn = _exe_tlb_uop_T_5_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagOut = _exe_tlb_uop_T_5_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fromint = _exe_tlb_uop_T_5_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_toint = _exe_tlb_uop_T_5_fp_ctrl_toint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fastpipe = _exe_tlb_uop_T_5_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fma = _exe_tlb_uop_T_5_fp_ctrl_fma; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_div = _exe_tlb_uop_T_5_fp_ctrl_div; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_sqrt = _exe_tlb_uop_T_5_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wflags = _exe_tlb_uop_T_5_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_vec = _exe_tlb_uop_T_5_fp_ctrl_vec; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_5_pdst; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_5_prs1; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_5_prs2; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_5_prs3; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_5_ppred; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_5_exception; // @[lsu.scala:321:49, :717:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_csr_cmd = _exe_tlb_uop_T_5_csr_cmd; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_5_ldst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fcn_dw = _exe_tlb_uop_T_5_fcn_dw; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_fcn_op = _exe_tlb_uop_T_5_fcn_op; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_fp_rm = _exe_tlb_uop_T_5_fp_rm; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_typ = _exe_tlb_uop_T_5_fp_typ; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:321:49, :717:24] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:104:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:104:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_0 = exe_tlb_uop_0_iq_type_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_1 = exe_tlb_uop_0_iq_type_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_2 = exe_tlb_uop_0_iq_type_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_3 = exe_tlb_uop_0_iq_type_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_0 = exe_tlb_uop_0_fu_code_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_1 = exe_tlb_uop_0_fu_code_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_2 = exe_tlb_uop_0_fu_code_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_3 = exe_tlb_uop_0_fu_code_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_4 = exe_tlb_uop_0_fu_code_4; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_5 = exe_tlb_uop_0_fu_code_5; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_6 = exe_tlb_uop_0_fu_code_6; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_7 = exe_tlb_uop_0_fu_code_7; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_8 = exe_tlb_uop_0_fu_code_8; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_9 = exe_tlb_uop_0_fu_code_9; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued = exe_tlb_uop_0_iw_issued; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_agen = exe_tlb_uop_0_iw_issued_partial_agen; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_dgen = exe_tlb_uop_0_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_iw_p1_speculative_child = exe_tlb_uop_0_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_iw_p2_speculative_child = exe_tlb_uop_0_iw_p2_speculative_child; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p1_bypass_hint = exe_tlb_uop_0_iw_p1_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p2_bypass_hint = exe_tlb_uop_0_iw_p2_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p3_bypass_hint = exe_tlb_uop_0_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_dis_col_sel = exe_tlb_uop_0_dis_col_sel; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_type = exe_tlb_uop_0_br_type; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfence = exe_tlb_uop_0_is_sfence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_eret = exe_tlb_uop_0_is_eret; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rocc = exe_tlb_uop_0_is_rocc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_mov = exe_tlb_uop_0_is_mov; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:104:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:104:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:104:23] wire mem_xcpt_uops_out_imm_rename = exe_tlb_uop_0_imm_rename; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_imm_sel = exe_tlb_uop_0_imm_sel; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_pimm = exe_tlb_uop_0_pimm; // @[util.scala:104:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_op1_sel = exe_tlb_uop_0_op1_sel; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_op2_sel = exe_tlb_uop_0_op2_sel; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ldst = exe_tlb_uop_0_fp_ctrl_ldst; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wen = exe_tlb_uop_0_fp_ctrl_wen; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren1 = exe_tlb_uop_0_fp_ctrl_ren1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren2 = exe_tlb_uop_0_fp_ctrl_ren2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren3 = exe_tlb_uop_0_fp_ctrl_ren3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap12 = exe_tlb_uop_0_fp_ctrl_swap12; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap23 = exe_tlb_uop_0_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagIn = exe_tlb_uop_0_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagOut = exe_tlb_uop_0_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fromint = exe_tlb_uop_0_fp_ctrl_fromint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_toint = exe_tlb_uop_0_fp_ctrl_toint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fastpipe = exe_tlb_uop_0_fp_ctrl_fastpipe; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fma = exe_tlb_uop_0_fp_ctrl_fma; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_div = exe_tlb_uop_0_fp_ctrl_div; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_sqrt = exe_tlb_uop_0_fp_ctrl_sqrt; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wflags = exe_tlb_uop_0_fp_ctrl_wflags; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_vec = exe_tlb_uop_0_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:104:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:104:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:104:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:104:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_csr_cmd = exe_tlb_uop_0_csr_cmd; // @[util.scala:104:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:104:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:104:23] wire mem_xcpt_uops_out_fcn_dw = exe_tlb_uop_0_fcn_dw; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_fcn_op = exe_tlb_uop_0_fcn_op; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_fp_rm = exe_tlb_uop_0_fp_rm; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_typ = exe_tlb_uop_0_fp_typ; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:104:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :726:53, :727:53] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:302:34, :473:41, :732:24] wire [63:0] _exe_tlb_vaddr_T_4 = _exe_tlb_vaddr_T_2 ? _retry_queue_io_deq_bits_data : {24'h0, _exe_tlb_vaddr_T_3}; // @[lsu.scala:533:27, :730:{24,53}, :732:24] wire [63:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {25'h0, io_core_sfence_bits_addr_0} : _exe_tlb_vaddr_T_4; // @[lsu.scala:211:7, :472:41, :729:24, :730:24] wire [63:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? io_core_agen_0_bits_data_0 : _exe_tlb_vaddr_T_5; // @[lsu.scala:211:7, :726:24, :727:53, :729:24] wire [63:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:321:49, :726:24] wire _exe_size_T_1 = _exe_size_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :738:52, :739:52] wire _exe_size_T_2 = _exe_size_T_1 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :739:52, :740:52] wire _exe_size_T_3 = _exe_size_T_2 \| will_fire_store_retry_0; // @[lsu.scala:477:41, :740:52, :741:52] wire [1:0] _exe_size_T_4 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:473:41, :743:23] wire [1:0] _exe_size_T_5 = _exe_size_T_3 ? exe_tlb_uop_0_mem_size : _exe_size_T_4; // @[lsu.scala:321:49, :738:23, :741:52, :743:23] wire [1:0] exe_size_0 = _exe_size_T_5; // @[lsu.scala:321:49, :738:23] wire _exe_cmd_T_1 = _exe_cmd_T \| will_fire_store_agen_0; // @[lsu.scala:471:41, :746:52, :747:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :747:52, :748:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 \| will_fire_store_retry_0; // @[lsu.scala:477:41, :748:52, :749:52] wire [4:0] _exe_cmd_T_4 = will_fire_sfence_0 ? 5'h14 : 5'h0; // @[lsu.scala:472:41, :752:23] wire [4:0] _exe_cmd_T_5 = will_fire_hella_incoming_0 ? 5'h0 : _exe_cmd_T_4; // @[lsu.scala:473:41, :751:23, :752:23] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_3 ? exe_tlb_uop_0_mem_cmd : _exe_cmd_T_5; // @[lsu.scala:321:49, :746:23, :749:52, :751:23] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:321:49, :746:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:321:49, :756:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :473:41, :759:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:321:49, :759:23] wire _ma_ld_T = _dtlb_io_resp_0_ma_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :782:52] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:321:49, :782:52] wire _ma_st_T = _dtlb_io_resp_0_ma_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :783:52] wire _ma_st_T_1 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82] wire _ma_st_T_2 = _ma_st_T & _ma_st_T_1; // @[lsu.scala:783:{52,79,82}] wire ma_st_0 = _ma_st_T_2; // @[lsu.scala:321:49, :783:79] wire _pf_ld_T = _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :784:52] wire pf_ld_0 = _pf_ld_T; // @[lsu.scala:321:49, :784:52] wire _pf_st_T = _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :785:52] wire pf_st_0 = _pf_st_T; // @[lsu.scala:321:49, :785:52] wire _ae_ld_T = _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :786:52] wire ae_ld_0 = _ae_ld_T; // @[lsu.scala:321:49, :786:52] wire _ae_st_T = _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :787:52] wire ae_st_0 = _ae_st_T; // @[lsu.scala:321:49, :787:52] wire _dbg_bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :789:107] wire _bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :791:106] wire _mem_xcpt_valids_T = pf_ld_0 \| pf_st_0; // @[lsu.scala:321:49, :797:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T \| ae_ld_0; // @[lsu.scala:321:49, :797:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 \| ae_st_0; // @[lsu.scala:321:49, :797:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 \| ma_ld_0; // @[lsu.scala:321:49, :797:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 \| ma_st_0; // @[lsu.scala:321:49, :797:{68,80}] wire _mem_xcpt_valids_T_5 = _mem_xcpt_valids_T_4; // @[lsu.scala:797:{80,92}] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_5; // @[lsu.scala:797:{92,105}] wire _mem_xcpt_valids_T_7 = exe_tlb_valid_0 & _mem_xcpt_valids_T_6; // @[lsu.scala:649:27, :796:39, :797:105] wire [15:0] _mem_xcpt_valids_T_8 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:126:51] wire _mem_xcpt_valids_T_9 = \|_mem_xcpt_valids_T_8; // @[util.scala:126:{51,59}] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_9 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_xcpt_valids_T_11 = ~_mem_xcpt_valids_T_10; // @[util.scala:61:61] wire _mem_xcpt_valids_T_12 = _mem_xcpt_valids_T_7 & _mem_xcpt_valids_T_11; // @[lsu.scala:796:39, :797:115, :798:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_12; // @[lsu.scala:321:49, :797:115] reg mem_xcpt_valids_0; // @[lsu.scala:795:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:457:29, :795:32] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:104:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_0 = mem_xcpt_uops_out_iq_type_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_1 = mem_xcpt_uops_out_iq_type_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_2 = mem_xcpt_uops_out_iq_type_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_3 = mem_xcpt_uops_out_iq_type_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_0 = mem_xcpt_uops_out_fu_code_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_1 = mem_xcpt_uops_out_fu_code_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_2 = mem_xcpt_uops_out_fu_code_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_3 = mem_xcpt_uops_out_fu_code_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_4 = mem_xcpt_uops_out_fu_code_4; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_5 = mem_xcpt_uops_out_fu_code_5; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_6 = mem_xcpt_uops_out_fu_code_6; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_7 = mem_xcpt_uops_out_fu_code_7; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_8 = mem_xcpt_uops_out_fu_code_8; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_9 = mem_xcpt_uops_out_fu_code_9; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued = mem_xcpt_uops_out_iw_issued; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_agen = mem_xcpt_uops_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_dgen = mem_xcpt_uops_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iw_p1_speculative_child = mem_xcpt_uops_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iw_p2_speculative_child = mem_xcpt_uops_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_bypass_hint = mem_xcpt_uops_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_bypass_hint = mem_xcpt_uops_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p3_bypass_hint = mem_xcpt_uops_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25] wire [2:0] _mem_xcpt_uops_WIRE_0_dis_col_sel = mem_xcpt_uops_out_dis_col_sel; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_type = mem_xcpt_uops_out_br_type; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfence = mem_xcpt_uops_out_is_sfence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_eret = mem_xcpt_uops_out_is_eret; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rocc = mem_xcpt_uops_out_is_rocc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_mov = mem_xcpt_uops_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_imm_rename = mem_xcpt_uops_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_imm_sel = mem_xcpt_uops_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_pimm = mem_xcpt_uops_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_op1_sel = mem_xcpt_uops_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_op2_sel = mem_xcpt_uops_out_op2_sel; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ldst = mem_xcpt_uops_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wen = mem_xcpt_uops_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren1 = mem_xcpt_uops_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren2 = mem_xcpt_uops_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren3 = mem_xcpt_uops_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap12 = mem_xcpt_uops_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap23 = mem_xcpt_uops_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagIn = mem_xcpt_uops_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagOut = mem_xcpt_uops_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fromint = mem_xcpt_uops_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_toint = mem_xcpt_uops_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fastpipe = mem_xcpt_uops_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fma = mem_xcpt_uops_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_div = mem_xcpt_uops_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_sqrt = mem_xcpt_uops_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wflags = mem_xcpt_uops_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_vec = mem_xcpt_uops_out_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:104:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_csr_cmd = mem_xcpt_uops_out_csr_cmd; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fcn_dw = mem_xcpt_uops_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_fcn_op = mem_xcpt_uops_out_fcn_op; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_fp_rm = mem_xcpt_uops_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_typ = mem_xcpt_uops_out_fp_typ; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:459:29, :799:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:459:29, :799:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_0 = mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_1 = mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_2 = mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_3 = mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_0 = mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_1 = mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_2 = mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_3 = mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_4 = mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_5 = mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_6 = mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_7 = mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_8 = mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_9 = mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued = mem_xcpt_uops_0_iw_issued; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_agen = mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_dgen = mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_speculative_child = mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_speculative_child = mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_bypass_hint = mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_bypass_hint = mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p3_bypass_hint = mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_dis_col_sel = mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:459:29, :799:32] reg [15:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_type; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_type = mem_xcpt_uops_0_br_type; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfence = mem_xcpt_uops_0_is_sfence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_eret; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_eret = mem_xcpt_uops_0_is_eret; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rocc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rocc = mem_xcpt_uops_0_is_rocc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_mov; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_mov = mem_xcpt_uops_0_is_mov; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:799:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:799:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_imm_rename; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_rename = mem_xcpt_uops_0_imm_rename; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_imm_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_sel = mem_xcpt_uops_0_imm_sel; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_pimm; // @[lsu.scala:799:32] assign mem_xcpt_uop_pimm = mem_xcpt_uops_0_pimm; // @[lsu.scala:459:29, :799:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_op1_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op1_sel = mem_xcpt_uops_0_op1_sel; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_op2_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op2_sel = mem_xcpt_uops_0_op2_sel; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ldst = mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wen = mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren1 = mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren2 = mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren3 = mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap12 = mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap23 = mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagIn = mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagOut = mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fromint = mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_toint = mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fastpipe = mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fma = mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_div = mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_sqrt = mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wflags = mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_vec = mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:799:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:459:29, :799:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:799:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:799:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_csr_cmd = mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:799:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_dw = mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_fcn_op; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_op = mem_xcpt_uops_0_fcn_op; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_fp_rm; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_rm = mem_xcpt_uops_0_fp_rm; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_typ; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_typ = mem_xcpt_uops_0_fp_typ; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:459:29, :799:32] wire [2:0] _mem_xcpt_causes_T = ae_ld_0 ? 3'h5 : 3'h0; // @[lsu.scala:321:49, :808:8] wire [2:0] _mem_xcpt_causes_T_1 = ae_st_0 ? 3'h7 : _mem_xcpt_causes_T; // @[lsu.scala:321:49, :807:8, :808:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : {1'h0, _mem_xcpt_causes_T_1}; // @[lsu.scala:321:49, :806:8, :807:8] wire [3:0] _mem_xcpt_causes_T_3 = pf_st_0 ? 4'hF : _mem_xcpt_causes_T_2; // @[lsu.scala:321:49, :805:8, :806:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:321:49, :804:8, :805:8] wire [3:0] _mem_xcpt_causes_T_5 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_4; // @[lsu.scala:321:49, :803:8, :804:8] wire [3:0] _mem_xcpt_causes_T_6 = _mem_xcpt_causes_T_5; // @[lsu.scala:802:8, :803:8] wire [3:0] _mem_xcpt_causes_T_7 = _mem_xcpt_causes_T_6; // @[lsu.scala:801:8, :802:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_7; // @[lsu.scala:321:49, :801:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:800:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:458:29, :800:32] reg [63:0] mem_xcpt_vaddrs_0; // @[lsu.scala:810:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:460:29, :810:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:835:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:649:27, :835:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:321:49, :835:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:308:20, :836:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:321:49, :837:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:836:{40,62}, :837:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:321:49, :836:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20, :838:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:321:49, :838:43] reg REG; // @[lsu.scala:845:21] wire [15:0] _exe_agen_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_agen_0_bits_uop_br_mask_0; // @[util.scala:126:51] wire _exe_agen_killed_T_1 = \|_exe_agen_killed_T; // @[util.scala:126:{51,59}] wire _exe_agen_killed_T_2 = _exe_agen_killed_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire exe_agen_killed_0 = _exe_agen_killed_T_2; // @[util.scala:61:61] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0_0 = dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_1_0 = dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_2_0 = dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_3_0 = dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0_0 = dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_1_0 = dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_2_0 = dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_3_0 = dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_4_0 = dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_5_0 = dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_6_0 = dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_7_0 = dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_8_0 = dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_9_0 = dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_0 = dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0 = dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0 = dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0 = dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dis_col_sel_0 = dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_type_0 = dmem_req_0_bits_uop_br_type; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfence_0 = dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_eret_0 = dmem_req_0_bits_uop_is_eret; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rocc_0 = dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_mov_0 = dmem_req_0_bits_uop_is_mov; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_rename_0 = dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_sel_0 = dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pimm_0 = dmem_req_0_bits_uop_pimm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op1_sel_0 = dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op2_sel_0 = dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0 = dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0 = dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0 = dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0 = dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0 = dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0 = dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0 = dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0 = dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0 = dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0 = dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0 = dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0 = dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0 = dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_csr_cmd_0 = dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_dw_0 = dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_op_0 = dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_rm_0 = dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_typ_0 = dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:211:7, :877:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:321:49, :877:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:211:7, :877:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:321:49, :880:55] wire s0_executing_loads_0; // @[lsu.scala:882:36] wire s0_executing_loads_1; // @[lsu.scala:882:36] wire s0_executing_loads_2; // @[lsu.scala:882:36] wire s0_executing_loads_3; // @[lsu.scala:882:36] wire s0_executing_loads_4; // @[lsu.scala:882:36] wire s0_executing_loads_5; // @[lsu.scala:882:36] wire s0_executing_loads_6; // @[lsu.scala:882:36] wire s0_executing_loads_7; // @[lsu.scala:882:36] wire s0_executing_loads_8; // @[lsu.scala:882:36] wire s0_executing_loads_9; // @[lsu.scala:882:36] wire s0_executing_loads_10; // @[lsu.scala:882:36] wire s0_executing_loads_11; // @[lsu.scala:882:36] wire s0_executing_loads_12; // @[lsu.scala:882:36] wire s0_executing_loads_13; // @[lsu.scala:882:36] wire s0_executing_loads_14; // @[lsu.scala:882:36] wire s0_executing_loads_15; // @[lsu.scala:882:36] wire s0_executing_loads_16; // @[lsu.scala:882:36] wire s0_executing_loads_17; // @[lsu.scala:882:36] wire s0_executing_loads_18; // @[lsu.scala:882:36] wire s0_executing_loads_19; // @[lsu.scala:882:36] wire s0_executing_loads_20; // @[lsu.scala:882:36] wire s0_executing_loads_21; // @[lsu.scala:882:36] wire s0_executing_loads_22; // @[lsu.scala:882:36] wire s0_executing_loads_23; // @[lsu.scala:882:36] wire s0_kills_0; // @[lsu.scala:883:22] wire _io_dmem_s1_kill_0_T = s0_kills_0 & dmem_req_fire_0; // @[lsu.scala:321:49, :883:22, :893:47] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:893:34] wire [39:0] _GEN_471 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :897:30] wire _GEN_472 = exe_tlb_miss_0 \| exe_tlb_uncacheable_0; // @[lsu.scala:321:49, :900:49] wire _s0_kills_0_T; // @[lsu.scala:900:49] assign _s0_kills_0_T = _GEN_472; // @[lsu.scala:900:49] wire _s0_kills_0_T_4; // @[lsu.scala:909:38] assign _s0_kills_0_T_4 = _GEN_472; // @[lsu.scala:900:49, :909:38] wire _s0_kills_0_T_1 = _s0_kills_0_T \| ma_ld_0; // @[lsu.scala:321:49, :900:{49,75}] wire _s0_kills_0_T_2 = _s0_kills_0_T_1 \| ae_ld_0; // @[lsu.scala:321:49, :900:{75,87}] wire _s0_kills_0_T_3 = _s0_kills_0_T_2 \| pf_ld_0; // @[lsu.scala:321:49, :900:{87,99}] wire _s0_executing_loads_T = ~s0_kills_0; // @[lsu.scala:883:22, :901:70] wire _s0_executing_loads_T_1 = dmem_req_fire_0 & _s0_executing_loads_T; // @[lsu.scala:321:49, :901:{67,70}] wire _s0_kills_0_T_5 = _s0_kills_0_T_4 \| ma_ld_0; // @[lsu.scala:321:49, :909:{38,64}] wire _s0_kills_0_T_6 = _s0_kills_0_T_5 \| ae_ld_0; // @[lsu.scala:321:49, :909:{64,76}] wire _s0_kills_0_T_7 = _s0_kills_0_T_6 \| pf_ld_0; // @[lsu.scala:321:49, :909:{76,88}] assign s0_kills_0 = will_fire_load_agen_exec_0 ? _s0_kills_0_T_3 : will_fire_load_retry_0 & _s0_kills_0_T_7; // @[lsu.scala:469:39, :476:41, :883:22, :892:17, :895:40, :900:{30,99}, :904:43, :909:{19,88}] wire _s0_executing_loads_T_2 = ~s0_kills_0; // @[lsu.scala:883:22, :901:70, :910:64] wire _s0_executing_loads_T_3 = dmem_req_fire_0 & _s0_executing_loads_T_2; // @[lsu.scala:321:49, :910:{61,64}] wire [1:0] dmem_req_0_bits_data_size; // @[AMOALU.scala:11:18] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _stq_execute_queue_io_deq_bits_data_bits[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _stq_execute_queue_io_deq_bits_data_bits[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _stq_execute_queue_io_deq_bits_data_bits[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _stq_execute_queue_io_deq_bits_data_bits; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_473 = will_fire_load_agen_exec_0 \| will_fire_load_retry_0; // @[lsu.scala:469:39, :476:41, :556:41, :895:40, :904:43, :911:84] assign dmem_req_0_bits_uop_inst = _GEN_473 ? exe_tlb_uop_0_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_inst = _GEN_473 ? exe_tlb_uop_0_debug_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rvc = _GEN_473 ? exe_tlb_uop_0_is_rvc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_rvc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_pc = _GEN_473 ? exe_tlb_uop_0_debug_pc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_pc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_0 = _GEN_473 ? exe_tlb_uop_0_iq_type_0 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_1 = _GEN_473 ? exe_tlb_uop_0_iq_type_1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_2 = _GEN_473 ? exe_tlb_uop_0_iq_type_2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_3 = _GEN_473 ? exe_tlb_uop_0_iq_type_3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_0 = _GEN_473 ? exe_tlb_uop_0_fu_code_0 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_1 = _GEN_473 ? exe_tlb_uop_0_fu_code_1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_2 = _GEN_473 ? exe_tlb_uop_0_fu_code_2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_3 = _GEN_473 ? exe_tlb_uop_0_fu_code_3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_4 = _GEN_473 ? exe_tlb_uop_0_fu_code_4 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_4 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_5 = _GEN_473 ? exe_tlb_uop_0_fu_code_5 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_5 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_6 = _GEN_473 ? exe_tlb_uop_0_fu_code_6 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_6 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_7 = _GEN_473 ? exe_tlb_uop_0_fu_code_7 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_7 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_8 = _GEN_473 ? exe_tlb_uop_0_fu_code_8 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_8 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_9 = _GEN_473 ? exe_tlb_uop_0_fu_code_9 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_9 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued = _GEN_473 ? exe_tlb_uop_0_iw_issued : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_agen = _GEN_473 ? exe_tlb_uop_0_iw_issued_partial_agen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_dgen = _GEN_473 ? exe_tlb_uop_0_iw_issued_partial_dgen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_speculative_child = _GEN_473 ? exe_tlb_uop_0_iw_p1_speculative_child : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_speculative_child = _GEN_473 ? exe_tlb_uop_0_iw_p2_speculative_child : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p1_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p2_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p3_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p3_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dis_col_sel = _GEN_473 ? exe_tlb_uop_0_dis_col_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_dis_col_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_mask = _GEN_473 ? exe_tlb_uop_0_br_mask : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_mask : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_tag = _GEN_473 ? exe_tlb_uop_0_br_tag : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_tag : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_type = _GEN_473 ? exe_tlb_uop_0_br_type : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_type : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfb = _GEN_473 ? exe_tlb_uop_0_is_sfb : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sfb : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fence = _GEN_473 ? exe_tlb_uop_0_is_fence : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_fence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fencei = _GEN_473 ? exe_tlb_uop_0_is_fencei : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_fencei : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfence = _GEN_473 ? exe_tlb_uop_0_is_sfence : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sfence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_amo = _GEN_473 ? exe_tlb_uop_0_is_amo : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_amo : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_eret = _GEN_473 ? exe_tlb_uop_0_is_eret : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_eret : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_473 ? exe_tlb_uop_0_is_sys_pc2epc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rocc = _GEN_473 ? exe_tlb_uop_0_is_rocc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_rocc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_mov = _GEN_473 ? exe_tlb_uop_0_is_mov : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_mov : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ftq_idx = _GEN_473 ? exe_tlb_uop_0_ftq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ftq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_edge_inst = _GEN_473 ? exe_tlb_uop_0_edge_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_edge_inst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pc_lob = _GEN_473 ? exe_tlb_uop_0_pc_lob : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pc_lob : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_taken = _GEN_473 ? exe_tlb_uop_0_taken : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_taken : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_rename = _GEN_473 ? exe_tlb_uop_0_imm_rename : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_rename : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_sel = _GEN_473 ? exe_tlb_uop_0_imm_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pimm = _GEN_473 ? exe_tlb_uop_0_pimm : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pimm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_packed = _GEN_473 ? exe_tlb_uop_0_imm_packed : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_packed : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op1_sel = _GEN_473 ? exe_tlb_uop_0_op1_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_op1_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op2_sel = _GEN_473 ? exe_tlb_uop_0_op2_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_op2_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ldst = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ldst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wen = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_wen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren1 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren2 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren3 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap12 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_swap12 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap23 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_swap23 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagIn = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_typeTagIn : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagOut = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_typeTagOut : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fromint = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fromint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_toint = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_toint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fastpipe = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fastpipe : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fma = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fma : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_div = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_div : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_sqrt = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_sqrt : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wflags = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_wflags : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_vec = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_vec : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rob_idx = _GEN_473 ? exe_tlb_uop_0_rob_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_rob_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldq_idx = _GEN_473 ? exe_tlb_uop_0_ldq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stq_idx = _GEN_473 ? exe_tlb_uop_0_stq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_stq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rxq_idx = _GEN_473 ? exe_tlb_uop_0_rxq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_rxq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pdst = _GEN_473 ? exe_tlb_uop_0_pdst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1 = _GEN_473 ? exe_tlb_uop_0_prs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2 = _GEN_473 ? exe_tlb_uop_0_prs2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3 = _GEN_473 ? exe_tlb_uop_0_prs3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred = _GEN_473 ? exe_tlb_uop_0_ppred : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ppred : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1_busy = _GEN_473 ? exe_tlb_uop_0_prs1_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs1_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2_busy = _GEN_473 ? exe_tlb_uop_0_prs2_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs2_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3_busy = _GEN_473 ? exe_tlb_uop_0_prs3_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs3_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred_busy = _GEN_473 ? exe_tlb_uop_0_ppred_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ppred_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stale_pdst = _GEN_473 ? exe_tlb_uop_0_stale_pdst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_stale_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exception = _GEN_473 ? exe_tlb_uop_0_exception : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_exception : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exc_cause = _GEN_473 ? exe_tlb_uop_0_exc_cause : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_exc_cause : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_ldq = _GEN_473 ? exe_tlb_uop_0_uses_ldq : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_uses_ldq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_stq = _GEN_473 ? exe_tlb_uop_0_uses_stq : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_uses_stq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_unique = _GEN_473 ? exe_tlb_uop_0_is_unique : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_unique : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_473 ? exe_tlb_uop_0_flush_on_commit : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_flush_on_commit : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_csr_cmd = _GEN_473 ? exe_tlb_uop_0_csr_cmd : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_csr_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_473 ? exe_tlb_uop_0_ldst_is_rs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst = _GEN_473 ? exe_tlb_uop_0_ldst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1 = _GEN_473 ? exe_tlb_uop_0_lrs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2 = _GEN_473 ? exe_tlb_uop_0_lrs2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs3 = _GEN_473 ? exe_tlb_uop_0_lrs3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dst_rtype = _GEN_473 ? exe_tlb_uop_0_dst_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_dst_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_473 ? exe_tlb_uop_0_lrs1_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs1_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_473 ? exe_tlb_uop_0_lrs2_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs2_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_frs3_en = _GEN_473 ? exe_tlb_uop_0_frs3_en : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_frs3_en : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_dw = _GEN_473 ? exe_tlb_uop_0_fcn_dw : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fcn_dw : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_op = _GEN_473 ? exe_tlb_uop_0_fcn_op : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fcn_op : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_val = _GEN_473 ? exe_tlb_uop_0_fp_val : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_val : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_rm = _GEN_473 ? exe_tlb_uop_0_fp_rm : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_rm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_typ = _GEN_473 ? exe_tlb_uop_0_fp_typ : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_typ : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_473 ? exe_tlb_uop_0_xcpt_pf_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_473 ? exe_tlb_uop_0_xcpt_ae_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_473 ? exe_tlb_uop_0_xcpt_ma_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_473 ? exe_tlb_uop_0_bp_debug_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_bp_debug_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_473 ? exe_tlb_uop_0_bp_xcpt_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_473 ? exe_tlb_uop_0_debug_fsrc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_fsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_473 ? exe_tlb_uop_0_debug_tsrc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_tsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign s0_executing_loads_0 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h0 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_447 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_423 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_1 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h1 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_448 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_424 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_2 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h2 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_449 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_425 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_3 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h3 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_450 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_426 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_4 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h4 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_451 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_427 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_5 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h5 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_452 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_428 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_6 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h6 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_453 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_429 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_7 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h7 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_454 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_430 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_8 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h8 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_455 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_431 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_9 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h9 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_456 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_432 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_10 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hA & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_457 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_433 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_11 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hB & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_458 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_434 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_12 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hC & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_459 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_435 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_13 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hD & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_460 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_436 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_14 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hE & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_461 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_437 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_15 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hF & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_462 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_438 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_16 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h10 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_463 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_439 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_17 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h11 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_464 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_440 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_18 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h12 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_465 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_441 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_19 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h13 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_466 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_442 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_20 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h14 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_467 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_443 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_21 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h15 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_468 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_444 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_22 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h16 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_469 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_445 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_23 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h17 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_470 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_446 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] wire _dmem_req_0_valid_T = ~io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :937:42] wire _dmem_req_0_valid_T_3 = _dmem_req_0_valid_T; // @[lsu.scala:937:{42,65}] wire _dmem_req_0_valid_T_1 = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69] wire _GEN_474 = will_fire_load_agen_exec_0 \| will_fire_load_retry_0 \| _T_1639 \| will_fire_load_wakeup_0; // @[lsu.scala:304:34, :469:39, :476:41, :480:41, :565:78, :895:40, :904:43, :911:84, :926:44, :934:47] assign dmem_req_0_valid = _GEN_474 \| (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_3 : will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :895:40, :896:30, :904:43, :905:30, :911:84, :912:33, :926:44, :927:30, :934:47, :937:{39,65}, :951:5] assign dmem_req_0_bits_addr = will_fire_load_agen_exec_0 \| will_fire_load_retry_0 ? _GEN_471 : _T_1639 ? _stq_execute_queue_io_deq_bits_addr_bits : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_471 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[lsu.scala:304:34, :469:39, :473:41, :474:41, :476:41, :480:41, :510:32, :558:11, :565:78, :877:22, :888:28, :895:40, :897:30, :904:43, :911:84, :913:33, :926:44, :928:30, :934:47, :938:39, :951:5, :954:39] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_473 ? 64'h0 : _T_1639 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 \| will_fire_hella_incoming_0 \| ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_473 ? exe_tlb_uop_0_mem_cmd : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_uop_mem_size = _GEN_473 ? exe_tlb_uop_0_mem_size : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_size : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_size : {2{will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0}}; // @[lsu.scala:321:49, :473:41, :474:41, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47, :944:39, :951:5, :960:39] assign dmem_req_0_bits_uop_mem_signed = _GEN_473 ? exe_tlb_uop_0_mem_signed : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_signed : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_is_hella = ~_GEN_474 & (will_fire_hella_incoming_0 \| will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :890:31, :895:40, :904:43, :911:84, :926:44, :934:47, :946:39, :951:5] wire _T_227 = _T_226 \| will_fire_load_retry_0; // @[lsu.scala:476:41, :687:61, :967:65] wire [4:0] ldq_idx = _ldq_idx_T ? ldq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:321:49, :533:27, :969:{24,48}] wire _ldq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50] wire _ldq_addr_valid_T_1 = _ldq_addr_valid_T \| will_fire_load_retry_0; // @[lsu.scala:476:41, :970:{50,70}] wire [63:0] _GEN_475 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : {32'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :971:53] wire [63:0] _ldq_addr_bits_T; // @[lsu.scala:971:53] assign _ldq_addr_bits_T = _GEN_475; // @[lsu.scala:971:53] wire [63:0] _stq_addr_bits_T; // @[lsu.scala:987:48] assign _stq_addr_bits_T = _GEN_475; // @[lsu.scala:971:53, :987:48] wire [7:0] ldq_ld_byte_mask_mask; // @[lsu.scala:1951:22] wire _ldq_ld_byte_mask_mask_T = exe_tlb_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _ldq_ld_byte_mask_mask_T_1 = exe_tlb_vaddr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _ldq_ld_byte_mask_mask_T_2 = 15'h1 << _ldq_ld_byte_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _ldq_ld_byte_mask_mask_T_3 = exe_tlb_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _ldq_ld_byte_mask_mask_T_4 = exe_tlb_vaddr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _ldq_ld_byte_mask_mask_T_5 = {_ldq_ld_byte_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _ldq_ld_byte_mask_mask_T_6 = 15'h3 << _ldq_ld_byte_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _ldq_ld_byte_mask_mask_T_7 = exe_tlb_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _ldq_ld_byte_mask_mask_T_8 = exe_tlb_vaddr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _ldq_ld_byte_mask_mask_T_9 = _ldq_ld_byte_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _ldq_ld_byte_mask_mask_T_10 = &exe_tlb_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _ldq_ld_byte_mask_mask_T_12 = _ldq_ld_byte_mask_mask_T_7 ? _ldq_ld_byte_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_13 = _ldq_ld_byte_mask_mask_T_3 ? _ldq_ld_byte_mask_mask_T_6 : {7'h0, _ldq_ld_byte_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_14 = _ldq_ld_byte_mask_mask_T ? _ldq_ld_byte_mask_mask_T_2 : _ldq_ld_byte_mask_mask_T_13; // @[Mux.scala:126:16] assign ldq_ld_byte_mask_mask = _ldq_ld_byte_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _ldq_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69, :975:76] wire _ldq_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_addr_is_uncacheable_T; // @[lsu.scala:321:49, :975:{73,76}] wire _T_232 = will_fire_store_agen_0 \| will_fire_store_retry_0; // @[lsu.scala:471:41, :477:41, :981:35] wire [4:0] stq_idx = will_fire_store_agen_0 ? stq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:321:49, :471:41, :533:27, :983:24] wire _stq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :986:46] wire _stq_addr_valid_T_1 = _stq_addr_valid_T \| will_fire_store_retry_0; // @[lsu.scala:477:41, :986:{46,66}] wire _stq_addr_valid_T_2 = ~pf_st_0; // @[lsu.scala:321:49, :986:98] wire _stq_addr_valid_T_3 = _stq_addr_valid_T_1 & _stq_addr_valid_T_2; // @[lsu.scala:986:{66,95,98}] wire slow_wakeups_0_valid; // @[lsu.scala:1495:26] wire _fired_load_agen_exec_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1041:83] wire _fired_load_agen_exec_T_1 = will_fire_load_agen_exec_0 & _fired_load_agen_exec_T; // @[lsu.scala:469:39, :1041:{80,83}] reg fired_load_agen_exec_REG; // @[lsu.scala:1041:51] wire fired_load_agen_exec_0 = fired_load_agen_exec_REG; // @[lsu.scala:321:49, :1041:51] wire _fired_load_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1042:83] wire _fired_load_agen_T_1 = will_fire_load_agen_0 & _fired_load_agen_T; // @[lsu.scala:470:41, :1042:{80,83}] reg fired_load_agen_REG; // @[lsu.scala:1042:51] wire fired_load_agen_0 = fired_load_agen_REG; // @[lsu.scala:321:49, :1042:51] wire _fired_store_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1043:83] wire _fired_store_agen_T_1 = will_fire_store_agen_0 & _fired_store_agen_T; // @[lsu.scala:471:41, :1043:{80,83}] reg fired_store_agen_REG; // @[lsu.scala:1043:51] wire fired_store_agen_0 = fired_store_agen_REG; // @[lsu.scala:321:49, :1043:51] reg fired_sfence_0; // @[lsu.scala:1044:37] reg fired_release_0; // @[lsu.scala:1045:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire [15:0] _GEN_476 = io_core_brupdate_b1_mispredict_mask_0 & _retry_queue_io_deq_bits_uop_br_mask; // @[util.scala:126:51] wire [15:0] _fired_load_retry_T; // @[util.scala:126:51] assign _fired_load_retry_T = _GEN_476; // @[util.scala:126:51] wire [15:0] _fired_store_retry_T; // @[util.scala:126:51] assign _fired_store_retry_T = _GEN_476; // @[util.scala:126:51] wire _fired_load_retry_T_1 = \|_fired_load_retry_T; // @[util.scala:126:{51,59}] wire _fired_load_retry_T_2 = _fired_load_retry_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_retry_T_3 = ~_fired_load_retry_T_2; // @[util.scala:61:61] wire _fired_load_retry_T_4 = will_fire_load_retry_0 & _fired_load_retry_T_3; // @[lsu.scala:476:41, :1046:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:1046:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:321:49, :1046:51] wire _fired_store_retry_T_1 = \|_fired_store_retry_T; // @[util.scala:126:{51,59}] wire _fired_store_retry_T_2 = _fired_store_retry_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_store_retry_T_3 = ~_fired_store_retry_T_2; // @[util.scala:61:61] wire _fired_store_retry_T_4 = will_fire_store_retry_0 & _fired_store_retry_T_3; // @[lsu.scala:477:41, :1047:{79,82}] reg fired_store_retry_REG; // @[lsu.scala:1047:51] wire fired_store_retry_0 = fired_store_retry_REG; // @[lsu.scala:321:49, :1047:51] reg fired_store_commit_REG; // @[lsu.scala:1048:51] wire fired_store_commit_0 = fired_store_commit_REG; // @[lsu.scala:321:49, :1048:51] wire [15:0] _GEN_477 = io_core_brupdate_b1_mispredict_mask_0 & ldq_wakeup_e_bits_uop_br_mask; // @[util.scala:126:51] wire [15:0] _fired_load_wakeup_T; // @[util.scala:126:51] assign _fired_load_wakeup_T = _GEN_477; // @[util.scala:126:51] wire [15:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_477; // @[util.scala:126:51] wire _fired_load_wakeup_T_1 = \|_fired_load_wakeup_T; // @[util.scala:126:{51,59}] wire _fired_load_wakeup_T_2 = _fired_load_wakeup_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_wakeup_T_3 = ~_fired_load_wakeup_T_2; // @[util.scala:61:61] wire _fired_load_wakeup_T_4 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_3; // @[lsu.scala:480:41, :1049:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:1049:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:321:49, :1049:51] reg fired_hella_incoming_0; // @[lsu.scala:1050:37] reg fired_hella_wakeup_0; // @[lsu.scala:1051:37] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:104:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_0 = mem_incoming_uop_out_iq_type_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_1 = mem_incoming_uop_out_iq_type_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_2 = mem_incoming_uop_out_iq_type_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_3 = mem_incoming_uop_out_iq_type_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_0 = mem_incoming_uop_out_fu_code_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_1 = mem_incoming_uop_out_fu_code_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_2 = mem_incoming_uop_out_fu_code_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_3 = mem_incoming_uop_out_fu_code_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_4 = mem_incoming_uop_out_fu_code_4; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_5 = mem_incoming_uop_out_fu_code_5; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_6 = mem_incoming_uop_out_fu_code_6; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_7 = mem_incoming_uop_out_fu_code_7; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_8 = mem_incoming_uop_out_fu_code_8; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_9 = mem_incoming_uop_out_fu_code_9; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued = mem_incoming_uop_out_iw_issued; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_agen = mem_incoming_uop_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_dgen = mem_incoming_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_iw_p1_speculative_child = mem_incoming_uop_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_iw_p2_speculative_child = mem_incoming_uop_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p1_bypass_hint = mem_incoming_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p2_bypass_hint = mem_incoming_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p3_bypass_hint = mem_incoming_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [2:0] _mem_incoming_uop_WIRE_0_dis_col_sel = mem_incoming_uop_out_dis_col_sel; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_type = mem_incoming_uop_out_br_type; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfence = mem_incoming_uop_out_is_sfence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_eret = mem_incoming_uop_out_is_eret; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rocc = mem_incoming_uop_out_is_rocc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_mov = mem_incoming_uop_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_imm_rename = mem_incoming_uop_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_imm_sel = mem_incoming_uop_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_pimm = mem_incoming_uop_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_op1_sel = mem_incoming_uop_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_op2_sel = mem_incoming_uop_out_op2_sel; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ldst = mem_incoming_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wen = mem_incoming_uop_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren1 = mem_incoming_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren2 = mem_incoming_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren3 = mem_incoming_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap12 = mem_incoming_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap23 = mem_incoming_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagIn = mem_incoming_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagOut = mem_incoming_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fromint = mem_incoming_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_toint = mem_incoming_uop_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fastpipe = mem_incoming_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fma = mem_incoming_uop_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_div = mem_incoming_uop_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_sqrt = mem_incoming_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wflags = mem_incoming_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_vec = mem_incoming_uop_out_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:104:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_csr_cmd = mem_incoming_uop_out_csr_cmd; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fcn_dw = mem_incoming_uop_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_fcn_op = mem_incoming_uop_out_fcn_op; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_fp_rm = mem_incoming_uop_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_typ = mem_incoming_uop_out_fp_typ; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_incoming_uop_out_br_mask_T_1 = io_core_agen_0_bits_uop_br_mask_0 & _mem_incoming_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_inst = mem_incoming_uop_0_inst; // @[util.scala:109:23] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_debug_inst = mem_incoming_uop_0_debug_inst; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rvc = mem_incoming_uop_0_is_rvc; // @[util.scala:109:23] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:1053:37] wire [39:0] w1_bits_out_uop_debug_pc = mem_incoming_uop_0_debug_pc; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_0 = mem_incoming_uop_0_iq_type_0; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_1 = mem_incoming_uop_0_iq_type_1; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_2 = mem_incoming_uop_0_iq_type_2; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_3 = mem_incoming_uop_0_iq_type_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_0 = mem_incoming_uop_0_fu_code_0; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_1 = mem_incoming_uop_0_fu_code_1; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_2 = mem_incoming_uop_0_fu_code_2; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_3 = mem_incoming_uop_0_fu_code_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_4; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_4 = mem_incoming_uop_0_fu_code_4; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_5; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_5 = mem_incoming_uop_0_fu_code_5; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_6; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_6 = mem_incoming_uop_0_fu_code_6; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_7; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_7 = mem_incoming_uop_0_fu_code_7; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_8; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_8 = mem_incoming_uop_0_fu_code_8; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_9; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_9 = mem_incoming_uop_0_fu_code_9; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued = mem_incoming_uop_0_iw_issued; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_agen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_agen = mem_incoming_uop_0_iw_issued_partial_agen; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_dgen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_dgen = mem_incoming_uop_0_iw_issued_partial_dgen; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_iw_p1_speculative_child; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_iw_p1_speculative_child = mem_incoming_uop_0_iw_p1_speculative_child; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_iw_p2_speculative_child; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_iw_p2_speculative_child = mem_incoming_uop_0_iw_p2_speculative_child; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p1_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p1_bypass_hint = mem_incoming_uop_0_iw_p1_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p2_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p2_bypass_hint = mem_incoming_uop_0_iw_p2_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p3_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p3_bypass_hint = mem_incoming_uop_0_iw_p3_bypass_hint; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_dis_col_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_dis_col_sel = mem_incoming_uop_0_dis_col_sel; // @[util.scala:109:23] reg [15:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:1053:37] reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_tag = mem_incoming_uop_0_br_tag; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_br_type; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_type = mem_incoming_uop_0_br_type; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfb = mem_incoming_uop_0_is_sfb; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fence = mem_incoming_uop_0_is_fence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fencei = mem_incoming_uop_0_is_fencei; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfence = mem_incoming_uop_0_is_sfence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_amo = mem_incoming_uop_0_is_amo; // @[util.scala:109:23] reg mem_incoming_uop_0_is_eret; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_eret = mem_incoming_uop_0_is_eret; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sys_pc2epc = mem_incoming_uop_0_is_sys_pc2epc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rocc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rocc = mem_incoming_uop_0_is_rocc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_mov; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_mov = mem_incoming_uop_0_is_mov; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ftq_idx = mem_incoming_uop_0_ftq_idx; // @[util.scala:109:23] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_edge_inst = mem_incoming_uop_0_edge_inst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_pc_lob = mem_incoming_uop_0_pc_lob; // @[util.scala:109:23] reg mem_incoming_uop_0_taken; // @[lsu.scala:1053:37] wire w1_bits_out_uop_taken = mem_incoming_uop_0_taken; // @[util.scala:109:23] reg mem_incoming_uop_0_imm_rename; // @[lsu.scala:1053:37] wire w1_bits_out_uop_imm_rename = mem_incoming_uop_0_imm_rename; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_imm_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_imm_sel = mem_incoming_uop_0_imm_sel; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_pimm; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_pimm = mem_incoming_uop_0_pimm; // @[util.scala:109:23] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:1053:37] wire [19:0] w1_bits_out_uop_imm_packed = mem_incoming_uop_0_imm_packed; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_op1_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_op1_sel = mem_incoming_uop_0_op1_sel; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_op2_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_op2_sel = mem_incoming_uop_0_op2_sel; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ldst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ldst = mem_incoming_uop_0_fp_ctrl_ldst; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wen = mem_incoming_uop_0_fp_ctrl_wen; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren1 = mem_incoming_uop_0_fp_ctrl_ren1; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren2 = mem_incoming_uop_0_fp_ctrl_ren2; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren3 = mem_incoming_uop_0_fp_ctrl_ren3; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap12; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap12 = mem_incoming_uop_0_fp_ctrl_swap12; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap23; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap23 = mem_incoming_uop_0_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagIn = mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagOut = mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fromint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fromint = mem_incoming_uop_0_fp_ctrl_fromint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_toint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_toint = mem_incoming_uop_0_fp_ctrl_toint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fastpipe = mem_incoming_uop_0_fp_ctrl_fastpipe; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fma; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fma = mem_incoming_uop_0_fp_ctrl_fma; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_div; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_div = mem_incoming_uop_0_fp_ctrl_div; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_sqrt; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_sqrt = mem_incoming_uop_0_fp_ctrl_sqrt; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wflags; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wflags = mem_incoming_uop_0_fp_ctrl_wflags; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_vec; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_vec = mem_incoming_uop_0_fp_ctrl_vec; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_rob_idx = mem_incoming_uop_0_rob_idx; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ldq_idx = mem_incoming_uop_0_ldq_idx; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_stq_idx = mem_incoming_uop_0_stq_idx; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_rxq_idx = mem_incoming_uop_0_rxq_idx; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_pdst = mem_incoming_uop_0_pdst; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs1 = mem_incoming_uop_0_prs1; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs2 = mem_incoming_uop_0_prs2; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs3 = mem_incoming_uop_0_prs3; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ppred = mem_incoming_uop_0_ppred; // @[util.scala:109:23] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs1_busy = mem_incoming_uop_0_prs1_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs2_busy = mem_incoming_uop_0_prs2_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs3_busy = mem_incoming_uop_0_prs3_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ppred_busy = mem_incoming_uop_0_ppred_busy; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_stale_pdst = mem_incoming_uop_0_stale_pdst; // @[util.scala:109:23] reg mem_incoming_uop_0_exception; // @[lsu.scala:1053:37] wire w1_bits_out_uop_exception = mem_incoming_uop_0_exception; // @[util.scala:109:23] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:1053:37] wire [63:0] w1_bits_out_uop_exc_cause = mem_incoming_uop_0_exc_cause; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_mem_cmd = mem_incoming_uop_0_mem_cmd; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_mem_size = mem_incoming_uop_0_mem_size; // @[util.scala:109:23] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:1053:37] wire w1_bits_out_uop_mem_signed = mem_incoming_uop_0_mem_signed; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_ldq = mem_incoming_uop_0_uses_ldq; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_stq = mem_incoming_uop_0_uses_stq; // @[util.scala:109:23] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_unique = mem_incoming_uop_0_is_unique; // @[util.scala:109:23] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:1053:37] wire w1_bits_out_uop_flush_on_commit = mem_incoming_uop_0_flush_on_commit; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_csr_cmd; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_csr_cmd = mem_incoming_uop_0_csr_cmd; // @[util.scala:109:23] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ldst_is_rs1 = mem_incoming_uop_0_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_ldst = mem_incoming_uop_0_ldst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs1 = mem_incoming_uop_0_lrs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs2 = mem_incoming_uop_0_lrs2; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs3 = mem_incoming_uop_0_lrs3; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dst_rtype = mem_incoming_uop_0_dst_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs1_rtype = mem_incoming_uop_0_lrs1_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs2_rtype = mem_incoming_uop_0_lrs2_rtype; // @[util.scala:109:23] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:1053:37] wire w1_bits_out_uop_frs3_en = mem_incoming_uop_0_frs3_en; // @[util.scala:109:23] reg mem_incoming_uop_0_fcn_dw; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fcn_dw = mem_incoming_uop_0_fcn_dw; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_fcn_op; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_fcn_op = mem_incoming_uop_0_fcn_op; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_val = mem_incoming_uop_0_fp_val; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_fp_rm; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_fp_rm = mem_incoming_uop_0_fp_rm; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_typ; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_typ = mem_incoming_uop_0_fp_typ; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_pf_if = mem_incoming_uop_0_xcpt_pf_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ae_if = mem_incoming_uop_0_xcpt_ae_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ma_if = mem_incoming_uop_0_xcpt_ma_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_debug_if = mem_incoming_uop_0_bp_debug_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_xcpt_if = mem_incoming_uop_0_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_fsrc = mem_incoming_uop_0_debug_fsrc; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_tsrc = mem_incoming_uop_0_debug_tsrc; // @[util.scala:109:23] wire _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_ldq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_ldq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_ldq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_ldq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_ldq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_ldq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_ldq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_ldq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_ldq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_ldq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_ldq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_ldq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_ldq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_ldq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_ldq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_ldq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_type = mem_ldq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_ldq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_eret = mem_ldq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_ldq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_mov = mem_ldq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_ldq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_ldq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pimm = mem_ldq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_ldq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_ldq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_ldq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_ldq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_ldq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_ldq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_ldq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:114:23] wire [23:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_ld_byte_mask = mem_ldq_incoming_e_out_bits_ld_byte_mask; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_incoming_e_out_valid_T_1 = \|_mem_ldq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = _mem_ldq_incoming_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_incoming_e_out_valid_T_3 = ~_mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_incoming_e_out_valid_T_4 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1054:37] reg [15:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1054:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:1054:37] reg [23:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:1054:37] reg [7:0] mem_ldq_incoming_e_0_bits_ld_byte_mask; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1054:37] wire _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_stq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_stq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_stq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_stq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_stq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_stq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_stq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_stq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_stq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_stq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_stq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_stq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_stq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_stq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_stq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_stq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_type = mem_stq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_stq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_eret = mem_stq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_stq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_mov = mem_stq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_stq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_stq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pimm = mem_stq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_stq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_stq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_stq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_stq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_stq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_stq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_stq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_stq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_can_execute = mem_stq_incoming_e_out_bits_can_execute; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_cleared = mem_stq_incoming_e_out_bits_cleared; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_incoming_e_out_valid_T_1 = \|_mem_stq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = _mem_stq_incoming_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_incoming_e_out_valid_T_3 = ~_mem_stq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_incoming_e_out_valid_T_4 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1055:37] reg [15:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1055:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_can_execute; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_cleared; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1055:37] wire _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = ldq_wakeup_e_bits_uop_br_mask & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = \|_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = _mem_ldq_wakeup_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_wakeup_e_out_valid_T_3 = ~_mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_wakeup_e_out_valid_T_4 = ldq_wakeup_e_valid & _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_dis_col_sel; // @[lsu.scala:1056:37] reg [15:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_type; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_imm_sel; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_pimm; // @[lsu.scala:1056:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_op1_sel; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_op2_sel; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_csr_cmd; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_fcn_op; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_fp_rm; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_typ; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:1056:37] reg [23:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:1056:37] reg [7:0] mem_ldq_wakeup_e_bits_ld_byte_mask; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:1056:37] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = mem_ldq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = mem_ldq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = mem_ldq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = mem_ldq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_0 = mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_1 = mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_2 = mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_3 = mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_0 = mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_1 = mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_2 = mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_3 = mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_4 = mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_5 = mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_6 = mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_7 = mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_8 = mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_9 = mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued = mem_ldq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_dis_col_sel = mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = mem_ldq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_type = mem_ldq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = mem_ldq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = mem_ldq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = mem_ldq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfence = mem_ldq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = mem_ldq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_eret = mem_ldq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rocc = mem_ldq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_mov = mem_ldq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = mem_ldq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = mem_ldq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_taken = mem_ldq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_imm_rename = mem_ldq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_imm_sel = mem_ldq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_pimm = mem_ldq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = mem_ldq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_op1_sel = mem_ldq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_op2_sel = mem_ldq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wen = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_toint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fma = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_div = mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_vec = mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_rob_idx = mem_ldq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_stq_idx = mem_ldq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = mem_ldq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = mem_ldq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = mem_ldq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = mem_ldq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = mem_ldq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_exception = mem_ldq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = mem_ldq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = mem_ldq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = mem_ldq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = mem_ldq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = mem_ldq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_csr_cmd = mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = mem_ldq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = mem_ldq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = mem_ldq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = mem_ldq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = mem_ldq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fcn_dw = mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_fcn_op = mem_ldq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = mem_ldq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_fp_rm = mem_ldq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_typ = mem_ldq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_valid = mem_ldq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = mem_ldq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = mem_ldq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_executed = mem_ldq_retry_e_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_succeeded = mem_ldq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_order_fail = mem_ldq_retry_e_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_observed = mem_ldq_retry_e_e_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_retry_e_out_bits_st_dep_mask = mem_ldq_retry_e_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_retry_e_out_bits_ld_byte_mask = mem_ldq_retry_e_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_forward_std_val = mem_ldq_retry_e_e_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_forward_stq_idx = mem_ldq_retry_e_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = mem_ldq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] mem_ldq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_valid; // @[lsu.scala:233:17] assign mem_ldq_retry_e_e_valid = _GEN_25[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :533:27] assign mem_ldq_retry_e_e_bits_uop_inst = _GEN_127[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_inst = _GEN_128[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rvc = _GEN_129[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_pc = _GEN_130[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_0 = _GEN_131[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_1 = _GEN_132[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_2 = _GEN_133[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_3 = _GEN_134[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_0 = _GEN_135[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_1 = _GEN_136[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_2 = _GEN_137[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_3 = _GEN_138[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_4 = _GEN_139[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_5 = _GEN_140[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_6 = _GEN_141[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_7 = _GEN_142[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_8 = _GEN_143[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_9 = _GEN_144[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued = _GEN_145[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dis_col_sel = _GEN_153[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_mask = _GEN_154[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_tag = _GEN_155[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_type = _GEN_156[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfb = _GEN_157[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fence = _GEN_158[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fencei = _GEN_159[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfence = _GEN_160[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_amo = _GEN_161[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_eret = _GEN_162[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rocc = _GEN_164[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_mov = _GEN_165[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ftq_idx = _GEN_166[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_edge_inst = _GEN_167[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pc_lob = _GEN_168[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_taken = _GEN_169[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_rename = _GEN_170[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_sel = _GEN_171[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pimm = _GEN_172[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_packed = _GEN_173[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op1_sel = _GEN_174[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op2_sel = _GEN_175[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_189[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rob_idx = _GEN_193[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldq_idx = _GEN_194[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stq_idx = _GEN_195[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rxq_idx = _GEN_196[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pdst = _GEN_197[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1 = _GEN_198[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2 = _GEN_199[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3 = _GEN_200[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred = _GEN_201[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1_busy = _GEN_202[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2_busy = _GEN_203[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3_busy = _GEN_204[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred_busy = _GEN_205[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stale_pdst = _GEN_206[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exception = _GEN_207[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exc_cause = _GEN_208[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_cmd = _GEN_209[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_size = _GEN_210[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_signed = _GEN_211[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_ldq = _GEN_212[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_stq = _GEN_213[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_unique = _GEN_214[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_flush_on_commit = _GEN_215[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_csr_cmd = _GEN_216[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst = _GEN_218[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1 = _GEN_219[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2 = _GEN_220[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs3 = _GEN_221[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dst_rtype = _GEN_222[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1_rtype = _GEN_223[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2_rtype = _GEN_224[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_frs3_en = _GEN_225[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_dw = _GEN_226[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_op = _GEN_227[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_val = _GEN_228[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_rm = _GEN_229[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_typ = _GEN_230[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_231[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_232[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_233[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_debug_if = _GEN_234[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_235[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_fsrc = _GEN_236[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_tsrc = _GEN_237[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_valid = _GEN_238[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_bits = _GEN_239[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_virtual = _GEN_240[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :237:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_uncacheable = _GEN_241[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :238:32, :533:27] assign mem_ldq_retry_e_e_bits_executed = _GEN_242[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :239:32, :533:27] assign mem_ldq_retry_e_e_bits_succeeded = _GEN_243[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :240:32, :533:27] assign mem_ldq_retry_e_e_bits_order_fail = _GEN_244[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :241:32, :533:27] assign mem_ldq_retry_e_e_bits_observed = _GEN_245[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :242:32, :533:27] assign mem_ldq_retry_e_e_bits_st_dep_mask = _GEN_246[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :243:32, :533:27] assign mem_ldq_retry_e_e_bits_ld_byte_mask = _GEN_247[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :244:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_std_val = _GEN_248[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :245:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_stq_idx = _GEN_249[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :246:32, :533:27] assign mem_ldq_retry_e_e_bits_debug_wb_data = _GEN_250[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :247:32, :533:27] wire _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = mem_ldq_retry_e_e_bits_uop_br_mask & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_ldq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_ldq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_retry_e_out_valid_T_1 = \|_mem_ldq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = _mem_ldq_retry_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_retry_e_out_valid_T_3 = ~_mem_ldq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_retry_e_out_valid_T_4 = mem_ldq_retry_e_e_valid & _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1057:37] reg [15:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_type; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_eret; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_mov; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_pimm; // @[lsu.scala:1057:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:1057:37] reg [23:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:1057:37] reg [7:0] mem_ldq_retry_e_bits_ld_byte_mask; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:1057:37] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = mem_stq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = mem_stq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = mem_stq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = mem_stq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_0 = mem_stq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_1 = mem_stq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_2 = mem_stq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_3 = mem_stq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_0 = mem_stq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_1 = mem_stq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_2 = mem_stq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_3 = mem_stq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_4 = mem_stq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_5 = mem_stq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_6 = mem_stq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_7 = mem_stq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_8 = mem_stq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_9 = mem_stq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued = mem_stq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_dis_col_sel = mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = mem_stq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_type = mem_stq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = mem_stq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fence = mem_stq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = mem_stq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfence = mem_stq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_amo = mem_stq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_eret = mem_stq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rocc = mem_stq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_mov = mem_stq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = mem_stq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = mem_stq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = mem_stq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_taken = mem_stq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_imm_rename = mem_stq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_imm_sel = mem_stq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_pimm = mem_stq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = mem_stq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_op1_sel = mem_stq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_op2_sel = mem_stq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wen = mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_toint = mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fma = mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_div = mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_vec = mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_rob_idx = mem_stq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ldq_idx = mem_stq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_stq_idx = mem_stq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = mem_stq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = mem_stq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = mem_stq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = mem_stq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = mem_stq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = mem_stq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = mem_stq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = mem_stq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = mem_stq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = mem_stq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = mem_stq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_exception = mem_stq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = mem_stq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = mem_stq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = mem_stq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = mem_stq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = mem_stq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = mem_stq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_unique = mem_stq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_csr_cmd = mem_stq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = mem_stq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = mem_stq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = mem_stq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = mem_stq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = mem_stq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = mem_stq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fcn_dw = mem_stq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_fcn_op = mem_stq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_val = mem_stq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_fp_rm = mem_stq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_typ = mem_stq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_valid = mem_stq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = mem_stq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = mem_stq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_data_valid = mem_stq_retry_e_e_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = mem_stq_retry_e_e_bits_data_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_committed = mem_stq_retry_e_e_bits_committed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_succeeded = mem_stq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_can_execute = mem_stq_retry_e_e_bits_can_execute; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_cleared = mem_stq_retry_e_e_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = mem_stq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] mem_stq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_valid; // @[lsu.scala:262:17] assign mem_stq_retry_e_e_valid = _GEN_26[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :533:27] assign mem_stq_retry_e_e_bits_uop_inst = _GEN_251[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_inst = _GEN_252[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rvc = _GEN_253[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_pc = _GEN_254[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_0 = _GEN_255[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_1 = _GEN_256[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_2 = _GEN_257[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_3 = _GEN_258[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_0 = _GEN_259[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_1 = _GEN_260[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_2 = _GEN_261[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_3 = _GEN_262[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_4 = _GEN_263[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_5 = _GEN_264[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_6 = _GEN_265[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_7 = _GEN_266[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_8 = _GEN_267[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_9 = _GEN_268[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued = _GEN_269[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dis_col_sel = _GEN_277[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_mask = _GEN_278[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_tag = _GEN_279[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_type = _GEN_280[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfb = _GEN_281[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fence = _GEN_282[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fencei = _GEN_283[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfence = _GEN_284[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_amo = _GEN_285[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_eret = _GEN_286[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_287[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rocc = _GEN_288[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_mov = _GEN_289[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ftq_idx = _GEN_290[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_edge_inst = _GEN_291[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pc_lob = _GEN_292[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_taken = _GEN_293[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_rename = _GEN_294[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_sel = _GEN_295[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pimm = _GEN_296[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_packed = _GEN_297[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op1_sel = _GEN_298[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op2_sel = _GEN_299[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_301[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_310[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_312[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_313[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_316[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rob_idx = _GEN_317[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldq_idx = _GEN_318[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stq_idx = _GEN_319[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rxq_idx = _GEN_320[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pdst = _GEN_321[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1 = _GEN_322[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2 = _GEN_323[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3 = _GEN_324[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred = _GEN_325[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1_busy = _GEN_326[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2_busy = _GEN_327[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3_busy = _GEN_328[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred_busy = _GEN_329[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stale_pdst = _GEN_330[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exception = _GEN_331[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exc_cause = _GEN_332[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_cmd = _GEN_333[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_size = _GEN_334[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_signed = _GEN_335[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_ldq = _GEN_336[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_stq = _GEN_337[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_unique = _GEN_338[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_flush_on_commit = _GEN_339[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_csr_cmd = _GEN_340[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_341[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst = _GEN_342[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1 = _GEN_343[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2 = _GEN_344[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs3 = _GEN_345[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dst_rtype = _GEN_346[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1_rtype = _GEN_347[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2_rtype = _GEN_348[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_frs3_en = _GEN_349[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_dw = _GEN_350[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_op = _GEN_351[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_val = _GEN_352[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_rm = _GEN_353[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_typ = _GEN_354[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_355[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_356[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_357[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_debug_if = _GEN_358[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_359[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_fsrc = _GEN_360[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_tsrc = _GEN_361[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_addr_valid = _GEN_362[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_bits = _GEN_363[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_is_virtual = _GEN_364[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :266:32, :533:27] assign mem_stq_retry_e_e_bits_data_valid = _GEN_365[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_data_bits = _GEN_366[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_committed = _GEN_367[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :268:32, :533:27] assign mem_stq_retry_e_e_bits_succeeded = _GEN_368[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :269:32, :533:27] assign mem_stq_retry_e_e_bits_can_execute = _GEN_369[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :270:32, :533:27] assign mem_stq_retry_e_e_bits_cleared = _GEN_370[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :271:32, :533:27] assign mem_stq_retry_e_e_bits_debug_wb_data = _GEN_371[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :272:32, :533:27] wire _mem_stq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_stq_retry_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = mem_stq_retry_e_e_bits_uop_br_mask & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_retry_e_out_valid_T_1 = \|_mem_stq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = _mem_stq_retry_e_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_retry_e_out_valid_T_3 = ~_mem_stq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_retry_e_out_valid_T_4 = mem_stq_retry_e_e_valid & _mem_stq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_retry_e_valid; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1058:37] reg [15:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_type; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_pimm; // @[lsu.scala:1058:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_can_execute; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_cleared; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:1058:37] wire _GEN_478 = fired_load_agen_0 \| fired_load_agen_exec_0; // @[lsu.scala:321:49, :1060:58] wire _mem_ldq_e_T; // @[lsu.scala:1060:58] assign _mem_ldq_e_T = _GEN_478; // @[lsu.scala:1060:58] wire _do_ld_search_T; // @[lsu.scala:1124:57] assign _do_ld_search_T = _GEN_478; // @[lsu.scala:1060:58, :1124:57] wire _lcam_ldq_idx_T; // @[lsu.scala:1144:51] assign _lcam_ldq_idx_T = _GEN_478; // @[lsu.scala:1060:58, :1144:51] wire _can_forward_T; // @[lsu.scala:1154:58] assign _can_forward_T = _GEN_478; // @[lsu.scala:1060:58, :1154:58] wire _mem_ldq_e_T_1_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_4 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_5 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_6 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_7 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_8 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_9 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_dis_col_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [15:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_eret = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rocc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_mov = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_imm_rename = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_pimm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_div = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_fcn_op = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_fp_rm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_typ = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [23:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 24'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [7:0] _mem_ldq_e_T_1_bits_ld_byte_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_ld_byte_mask : 8'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_2_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_0 : _mem_ldq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_1 : _mem_ldq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_2 : _mem_ldq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_3 : _mem_ldq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_0 : _mem_ldq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_1 : _mem_ldq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_2 : _mem_ldq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_3 : _mem_ldq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_4 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_4 : _mem_ldq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_5 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_5 : _mem_ldq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_6 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_6 : _mem_ldq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_7 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_7 : _mem_ldq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_8 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_8 : _mem_ldq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_9 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_9 : _mem_ldq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued : _mem_ldq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_dis_col_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dis_col_sel : _mem_ldq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [15:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_type : _mem_ldq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfence : _mem_ldq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_eret = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_eret : _mem_ldq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rocc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rocc : _mem_ldq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_mov = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_mov : _mem_ldq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_imm_rename = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_rename : _mem_ldq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_sel : _mem_ldq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_pimm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pimm : _mem_ldq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op1_sel : _mem_ldq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op2_sel : _mem_ldq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_div = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_div : _mem_ldq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_cmd : _mem_ldq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_dw : _mem_ldq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_fcn_op = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_op : _mem_ldq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_fp_rm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_rm : _mem_ldq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_typ = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_typ : _mem_ldq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [23:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [7:0] _mem_ldq_e_T_2_bits_ld_byte_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_ld_byte_mask : _mem_ldq_e_T_1_bits_ld_byte_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_3_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_2_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_debug_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rvc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_uop_debug_pc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_0 : _mem_ldq_e_T_2_bits_uop_iq_type_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_1 : _mem_ldq_e_T_2_bits_uop_iq_type_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_2 : _mem_ldq_e_T_2_bits_uop_iq_type_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_3 : _mem_ldq_e_T_2_bits_uop_iq_type_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_0 : _mem_ldq_e_T_2_bits_uop_fu_code_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_1 : _mem_ldq_e_T_2_bits_uop_fu_code_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_2 : _mem_ldq_e_T_2_bits_uop_fu_code_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_3 : _mem_ldq_e_T_2_bits_uop_fu_code_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_4 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_4 : _mem_ldq_e_T_2_bits_uop_fu_code_4; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_5 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_5 : _mem_ldq_e_T_2_bits_uop_fu_code_5; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_6 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_6 : _mem_ldq_e_T_2_bits_uop_fu_code_6; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_7 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_7 : _mem_ldq_e_T_2_bits_uop_fu_code_7; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_8 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_8 : _mem_ldq_e_T_2_bits_uop_fu_code_8; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_9 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_9 : _mem_ldq_e_T_2_bits_uop_fu_code_9; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued : _mem_ldq_e_T_2_bits_uop_iw_issued; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_dis_col_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dis_col_sel : _mem_ldq_e_T_2_bits_uop_dis_col_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [15:0] _mem_ldq_e_T_3_bits_uop_br_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_tag = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_type = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_type : _mem_ldq_e_T_2_bits_uop_br_type; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfb = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fencei = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfence : _mem_ldq_e_T_2_bits_uop_is_sfence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_amo = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_eret = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_eret : _mem_ldq_e_T_2_bits_uop_is_eret; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rocc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rocc : _mem_ldq_e_T_2_bits_uop_is_rocc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_mov = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_mov : _mem_ldq_e_T_2_bits_uop_is_mov; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ftq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_edge_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_pc_lob = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_taken = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_imm_rename = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_rename : _mem_ldq_e_T_2_bits_uop_imm_rename; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_imm_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_sel : _mem_ldq_e_T_2_bits_uop_imm_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_pimm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pimm : _mem_ldq_e_T_2_bits_uop_pimm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [19:0] _mem_ldq_e_T_3_bits_uop_imm_packed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_op1_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op1_sel : _mem_ldq_e_T_2_bits_uop_op1_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_op2_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op2_sel : _mem_ldq_e_T_2_bits_uop_op2_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_div = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_ldq_e_T_2_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_rob_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ldq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_rxq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ppred = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs1_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs2_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs3_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ppred_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_stale_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_exception = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_uop_exc_cause = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_mem_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_mem_size = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_mem_signed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_ldq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_stq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_unique = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_flush_on_commit = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_csr_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_csr_cmd : _mem_ldq_e_T_2_bits_uop_csr_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ldst_is_rs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dst_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs1_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs2_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_frs3_en = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fcn_dw = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_dw : _mem_ldq_e_T_2_bits_uop_fcn_dw; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_fcn_op = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_op : _mem_ldq_e_T_2_bits_uop_fcn_op; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_fp_rm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_rm : _mem_ldq_e_T_2_bits_uop_fp_rm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_typ = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_typ : _mem_ldq_e_T_2_bits_uop_fp_typ; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_pf_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ae_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ma_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_debug_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_xcpt_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_fsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_tsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_addr_bits = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_virtual = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_uncacheable = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_executed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_succeeded = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_order_fail = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_observed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [23:0] _mem_ldq_e_T_3_bits_st_dep_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [7:0] _mem_ldq_e_T_3_bits_ld_byte_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_ld_byte_mask : _mem_ldq_e_T_2_bits_ld_byte_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_forward_std_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_forward_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_debug_wb_data = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_3_valid; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_3_bits_uop_inst; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_3_bits_uop_debug_inst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_3_bits_uop_is_rvc; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_3_bits_uop_debug_pc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_0 = _mem_ldq_e_T_3_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_1 = _mem_ldq_e_T_3_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_2 = _mem_ldq_e_T_3_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_3 = _mem_ldq_e_T_3_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_0 = _mem_ldq_e_T_3_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_1 = _mem_ldq_e_T_3_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_2 = _mem_ldq_e_T_3_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_3 = _mem_ldq_e_T_3_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_4 = _mem_ldq_e_T_3_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_5 = _mem_ldq_e_T_3_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_6 = _mem_ldq_e_T_3_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_7 = _mem_ldq_e_T_3_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_8 = _mem_ldq_e_T_3_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_9 = _mem_ldq_e_T_3_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued = _mem_ldq_e_T_3_bits_uop_iw_issued; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_dis_col_sel = _mem_ldq_e_T_3_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1060:33] wire [15:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_3_bits_uop_br_mask; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_3_bits_uop_br_tag; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_type = _mem_ldq_e_T_3_bits_uop_br_type; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_3_bits_uop_is_sfb; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_3_bits_uop_is_fence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_3_bits_uop_is_fencei; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfence = _mem_ldq_e_T_3_bits_uop_is_sfence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_3_bits_uop_is_amo; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_eret = _mem_ldq_e_T_3_bits_uop_is_eret; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rocc = _mem_ldq_e_T_3_bits_uop_is_rocc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_mov = _mem_ldq_e_T_3_bits_uop_is_mov; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_3_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_3_bits_uop_edge_inst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_3_bits_uop_pc_lob; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_3_bits_uop_taken; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_imm_rename = _mem_ldq_e_T_3_bits_uop_imm_rename; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_imm_sel = _mem_ldq_e_T_3_bits_uop_imm_sel; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_pimm = _mem_ldq_e_T_3_bits_uop_pimm; // @[lsu.scala:321:49, :1060:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_3_bits_uop_imm_packed; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_op1_sel = _mem_ldq_e_T_3_bits_uop_op1_sel; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_op2_sel = _mem_ldq_e_T_3_bits_uop_op2_sel; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wen = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_toint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fma = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_div = _mem_ldq_e_T_3_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_vec = _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_3_bits_uop_rob_idx; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_3_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_3_bits_uop_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_3_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_3_bits_uop_pdst; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_3_bits_uop_prs1; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_3_bits_uop_prs2; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_3_bits_uop_prs3; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_3_bits_uop_ppred; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_3_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_3_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_3_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_3_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_3_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_3_bits_uop_exception; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_3_bits_uop_exc_cause; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_3_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_3_bits_uop_mem_size; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_3_bits_uop_mem_signed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_3_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_3_bits_uop_uses_stq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_3_bits_uop_is_unique; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_3_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_csr_cmd = _mem_ldq_e_T_3_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_3_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_3_bits_uop_ldst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_3_bits_uop_lrs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_3_bits_uop_lrs2; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_3_bits_uop_lrs3; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_3_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_3_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_3_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_3_bits_uop_frs3_en; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fcn_dw = _mem_ldq_e_T_3_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_fcn_op = _mem_ldq_e_T_3_bits_uop_fcn_op; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_3_bits_uop_fp_val; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_fp_rm = _mem_ldq_e_T_3_bits_uop_fp_rm; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_typ = _mem_ldq_e_T_3_bits_uop_fp_typ; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_3_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_3_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_3_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_3_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_3_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_3_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_3_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_3_bits_addr_valid; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_3_bits_addr_bits; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_3_bits_addr_is_virtual; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_3_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_3_bits_executed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_3_bits_succeeded; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_3_bits_order_fail; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_3_bits_observed; // @[lsu.scala:321:49, :1060:33] wire [23:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_3_bits_st_dep_mask; // @[lsu.scala:321:49, :1060:33] wire [7:0] mem_ldq_e_0_bits_ld_byte_mask = _mem_ldq_e_T_3_bits_ld_byte_mask; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_3_bits_forward_std_val; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_3_bits_forward_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_3_bits_debug_wb_data; // @[lsu.scala:321:49, :1060:33] wire [23:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:321:49] wire _mem_stq_e_T_valid = fired_store_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_debug_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rvc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_uop_debug_pc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_4 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_5 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_6 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_7 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_8 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_9 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_agen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_dgen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_iw_p1_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_iw_p2_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p1_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p2_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p3_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_dis_col_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [15:0] _mem_stq_e_T_bits_uop_br_mask = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_tag = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_type = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfb = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fencei = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_amo = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_eret = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sys_pc2epc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rocc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_mov = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ftq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_edge_inst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_pc_lob = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_taken = fired_store_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_imm_rename = fired_store_retry_0 & mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_imm_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_pimm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [19:0] _mem_stq_e_T_bits_uop_imm_packed = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_op1_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_op2_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ldst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap12 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap23 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fromint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_toint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fma = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_div = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_sqrt = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wflags = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_vec = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_rob_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ldq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_stq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_rxq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ppred = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs1_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs2_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs3_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ppred_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_stale_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_exception = fired_store_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_uop_exc_cause = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_mem_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_mem_size = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_mem_signed = fired_store_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_ldq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_stq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_unique = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_flush_on_commit = fired_store_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_csr_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ldst_is_rs1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_ldst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dst_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs1_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs2_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_frs3_en = fired_store_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fcn_dw = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_fcn_op = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_val = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_fp_rm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_typ = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_pf_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ae_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ma_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_debug_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_xcpt_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_fsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_tsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_valid = fired_store_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_addr_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_is_virtual = fired_store_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_data_valid = fired_store_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_data_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_committed = fired_store_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_succeeded = fired_store_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_can_execute = fired_store_retry_0 & mem_stq_retry_e_bits_can_execute; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_cleared = fired_store_retry_0 & mem_stq_retry_e_bits_cleared; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_debug_wb_data = fired_store_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_1_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_bits_uop_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_bits_uop_debug_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_bits_uop_is_rvc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_bits_uop_debug_pc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_0 : _mem_stq_e_T_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_1 : _mem_stq_e_T_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_2 : _mem_stq_e_T_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_3 : _mem_stq_e_T_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_0 : _mem_stq_e_T_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_1 : _mem_stq_e_T_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_2 : _mem_stq_e_T_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_3 : _mem_stq_e_T_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_4 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_4 : _mem_stq_e_T_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_5 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_5 : _mem_stq_e_T_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_6 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_6 : _mem_stq_e_T_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_7 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_7 : _mem_stq_e_T_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_8 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_8 : _mem_stq_e_T_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_9 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_9 : _mem_stq_e_T_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued : _mem_stq_e_T_bits_uop_iw_issued; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_stq_e_T_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_stq_e_T_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_stq_e_T_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_stq_e_T_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_stq_e_T_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_stq_e_T_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_stq_e_T_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_dis_col_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dis_col_sel : _mem_stq_e_T_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [15:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_bits_uop_br_mask; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_bits_uop_br_tag; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_type = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_type : _mem_stq_e_T_bits_uop_br_type; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_bits_uop_is_sfb; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_bits_uop_is_fence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_bits_uop_is_fencei; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfence : _mem_stq_e_T_bits_uop_is_sfence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_bits_uop_is_amo; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_eret = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_eret : _mem_stq_e_T_bits_uop_is_eret; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rocc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rocc : _mem_stq_e_T_bits_uop_is_rocc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_mov = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_mov : _mem_stq_e_T_bits_uop_is_mov; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_bits_uop_edge_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_bits_uop_pc_lob; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_bits_uop_taken; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_imm_rename = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_rename : _mem_stq_e_T_bits_uop_imm_rename; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_imm_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_sel : _mem_stq_e_T_bits_uop_imm_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_pimm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pimm : _mem_stq_e_T_bits_uop_pimm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_bits_uop_imm_packed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_op1_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op1_sel : _mem_stq_e_T_bits_uop_op1_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_op2_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op2_sel : _mem_stq_e_T_bits_uop_op2_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_stq_e_T_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_stq_e_T_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_stq_e_T_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_stq_e_T_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_stq_e_T_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_stq_e_T_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_stq_e_T_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_stq_e_T_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_toint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_stq_e_T_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fma = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_stq_e_T_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_div = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_stq_e_T_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_stq_e_T_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_stq_e_T_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_vec = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_stq_e_T_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_bits_uop_rob_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_bits_uop_stq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_bits_uop_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_bits_uop_prs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_bits_uop_prs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_bits_uop_prs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_bits_uop_ppred; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_bits_uop_exception; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_bits_uop_exc_cause; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_bits_uop_mem_size; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_bits_uop_mem_signed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_bits_uop_uses_stq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_bits_uop_is_unique; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_csr_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_csr_cmd : _mem_stq_e_T_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_bits_uop_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_bits_uop_lrs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_bits_uop_lrs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_bits_uop_lrs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_bits_uop_frs3_en; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fcn_dw = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_dw : _mem_stq_e_T_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_fcn_op = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_op : _mem_stq_e_T_bits_uop_fcn_op; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_bits_uop_fp_val; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_fp_rm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_rm : _mem_stq_e_T_bits_uop_fp_rm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_typ = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_typ : _mem_stq_e_T_bits_uop_fp_typ; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_bits_addr_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_bits_addr_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_bits_addr_is_virtual; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_data_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_bits_data_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_bits_data_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_committed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_bits_committed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_succeeded = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_bits_succeeded; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_can_execute = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_can_execute : _mem_stq_e_T_bits_can_execute; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_cleared = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_cleared : _mem_stq_e_T_bits_cleared; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_bits_debug_wb_data; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire mem_stq_e_0_valid = _mem_stq_e_T_1_valid; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_0 = _mem_stq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_1 = _mem_stq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_2 = _mem_stq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_3 = _mem_stq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_0 = _mem_stq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_1 = _mem_stq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_2 = _mem_stq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_3 = _mem_stq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_4 = _mem_stq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_5 = _mem_stq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_6 = _mem_stq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_7 = _mem_stq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_8 = _mem_stq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_9 = _mem_stq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued = _mem_stq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_agen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_dgen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_iw_p1_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_iw_p2_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p1_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p2_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p3_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_dis_col_sel = _mem_stq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1066:33] wire [15:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_type = _mem_stq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfence = _mem_stq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_eret = _mem_stq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rocc = _mem_stq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_mov = _mem_stq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_imm_rename = _mem_stq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_imm_sel = _mem_stq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_pimm = _mem_stq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1066:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_op1_sel = _mem_stq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_op2_sel = _mem_stq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ldst = _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wen = _mem_stq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren1 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren2 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren3 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap12 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap23 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fromint = _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_toint = _mem_stq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fma = _mem_stq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_div = _mem_stq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_sqrt = _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wflags = _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_vec = _mem_stq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_csr_cmd = _mem_stq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fcn_dw = _mem_stq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_fcn_op = _mem_stq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_fp_rm = _mem_stq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_typ = _mem_stq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_1_bits_committed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_can_execute = _mem_stq_e_T_1_bits_can_execute; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_cleared = _mem_stq_e_T_1_bits_cleared; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1066:33] reg mem_tlb_miss_0; // @[lsu.scala:1070:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:1071:41] reg [39:0] mem_paddr_0; // @[lsu.scala:1072:41] wire _stq_clr_head_idx_T = ~stq_cleared_0; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_1 = stq_valid_0 & _stq_clr_head_idx_T; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_2 = ~stq_cleared_1; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_3 = stq_valid_1 & _stq_clr_head_idx_T_2; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_4 = ~stq_cleared_2; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_5 = stq_valid_2 & _stq_clr_head_idx_T_4; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_6 = ~stq_cleared_3; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_7 = stq_valid_3 & _stq_clr_head_idx_T_6; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_8 = ~stq_cleared_4; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_9 = stq_valid_4 & _stq_clr_head_idx_T_8; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_10 = ~stq_cleared_5; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_11 = stq_valid_5 & _stq_clr_head_idx_T_10; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_12 = ~stq_cleared_6; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_13 = stq_valid_6 & _stq_clr_head_idx_T_12; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_14 = ~stq_cleared_7; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_15 = stq_valid_7 & _stq_clr_head_idx_T_14; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_16 = ~stq_cleared_8; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_17 = stq_valid_8 & _stq_clr_head_idx_T_16; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_18 = ~stq_cleared_9; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_19 = stq_valid_9 & _stq_clr_head_idx_T_18; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_20 = ~stq_cleared_10; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_21 = stq_valid_10 & _stq_clr_head_idx_T_20; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_22 = ~stq_cleared_11; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_23 = stq_valid_11 & _stq_clr_head_idx_T_22; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_24 = ~stq_cleared_12; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_25 = stq_valid_12 & _stq_clr_head_idx_T_24; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_26 = ~stq_cleared_13; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_27 = stq_valid_13 & _stq_clr_head_idx_T_26; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_28 = ~stq_cleared_14; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_29 = stq_valid_14 & _stq_clr_head_idx_T_28; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_30 = ~stq_cleared_15; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_31 = stq_valid_15 & _stq_clr_head_idx_T_30; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_32 = ~stq_cleared_16; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_33 = stq_valid_16 & _stq_clr_head_idx_T_32; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_34 = ~stq_cleared_17; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_35 = stq_valid_17 & _stq_clr_head_idx_T_34; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_36 = ~stq_cleared_18; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_37 = stq_valid_18 & _stq_clr_head_idx_T_36; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_38 = ~stq_cleared_19; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_39 = stq_valid_19 & _stq_clr_head_idx_T_38; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_40 = ~stq_cleared_20; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_41 = stq_valid_20 & _stq_clr_head_idx_T_40; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_42 = ~stq_cleared_21; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_43 = stq_valid_21 & _stq_clr_head_idx_T_42; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_44 = ~stq_cleared_22; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_45 = stq_valid_22 & _stq_clr_head_idx_T_44; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_46 = ~stq_cleared_23; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_47 = stq_valid_23 & _stq_clr_head_idx_T_46; // @[lsu.scala:251:32, :1077:{18,21}] wire stq_clr_head_idx_temp_vec_0 = _stq_clr_head_idx_T_1 & _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_1 = _stq_clr_head_idx_T_3 & _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_2 = _stq_clr_head_idx_T_5 & _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_3 = _stq_clr_head_idx_T_7 & _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_4 = _stq_clr_head_idx_T_9 & _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_5 = _stq_clr_head_idx_T_11 & _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_6 = _stq_clr_head_idx_T_13 & _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_7 = _stq_clr_head_idx_T_15 & _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_8 = _stq_clr_head_idx_T_17 & _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_9 = _stq_clr_head_idx_T_19 & _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_10 = _stq_clr_head_idx_T_21 & _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_11 = _stq_clr_head_idx_T_23 & _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_12 = _stq_clr_head_idx_T_25 & _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_13 = _stq_clr_head_idx_T_27 & _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_14 = _stq_clr_head_idx_T_29 & _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _stq_clr_head_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:352:72] wire stq_clr_head_idx_temp_vec_15 = _stq_clr_head_idx_T_31 & _stq_clr_head_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_16 = _stq_clr_head_idx_T_33 & _stq_clr_head_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_17 = _stq_clr_head_idx_T_35 & _stq_clr_head_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_18 = _stq_clr_head_idx_T_37 & _stq_clr_head_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_19 = _stq_clr_head_idx_T_39 & _stq_clr_head_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_20 = _stq_clr_head_idx_T_41 & _stq_clr_head_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_21 = _stq_clr_head_idx_T_43 & _stq_clr_head_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_22 = _stq_clr_head_idx_T_45 & _stq_clr_head_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_23 = _stq_clr_head_idx_T_47 & _stq_clr_head_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _stq_clr_head_idx_idx_T = {5'h1B, ~_stq_clr_head_idx_T_45}; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_1 = _stq_clr_head_idx_T_43 ? 6'h35 : _stq_clr_head_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_2 = _stq_clr_head_idx_T_41 ? 6'h34 : _stq_clr_head_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_3 = _stq_clr_head_idx_T_39 ? 6'h33 : _stq_clr_head_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_4 = _stq_clr_head_idx_T_37 ? 6'h32 : _stq_clr_head_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_5 = _stq_clr_head_idx_T_35 ? 6'h31 : _stq_clr_head_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_6 = _stq_clr_head_idx_T_33 ? 6'h30 : _stq_clr_head_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_7 = _stq_clr_head_idx_T_31 ? 6'h2F : _stq_clr_head_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_8 = _stq_clr_head_idx_T_29 ? 6'h2E : _stq_clr_head_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_9 = _stq_clr_head_idx_T_27 ? 6'h2D : _stq_clr_head_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_10 = _stq_clr_head_idx_T_25 ? 6'h2C : _stq_clr_head_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_11 = _stq_clr_head_idx_T_23 ? 6'h2B : _stq_clr_head_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_12 = _stq_clr_head_idx_T_21 ? 6'h2A : _stq_clr_head_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_13 = _stq_clr_head_idx_T_19 ? 6'h29 : _stq_clr_head_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_14 = _stq_clr_head_idx_T_17 ? 6'h28 : _stq_clr_head_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_15 = _stq_clr_head_idx_T_15 ? 6'h27 : _stq_clr_head_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_16 = _stq_clr_head_idx_T_13 ? 6'h26 : _stq_clr_head_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_17 = _stq_clr_head_idx_T_11 ? 6'h25 : _stq_clr_head_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_18 = _stq_clr_head_idx_T_9 ? 6'h24 : _stq_clr_head_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_19 = _stq_clr_head_idx_T_7 ? 6'h23 : _stq_clr_head_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_20 = _stq_clr_head_idx_T_5 ? 6'h22 : _stq_clr_head_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_21 = _stq_clr_head_idx_T_3 ? 6'h21 : _stq_clr_head_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_22 = _stq_clr_head_idx_T_1 ? 6'h20 : _stq_clr_head_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_23 = _stq_clr_head_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_24 = _stq_clr_head_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_25 = _stq_clr_head_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_26 = _stq_clr_head_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_27 = _stq_clr_head_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_28 = _stq_clr_head_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_29 = _stq_clr_head_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_30 = _stq_clr_head_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_31 = stq_clr_head_idx_temp_vec_23 ? 6'h17 : _stq_clr_head_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_32 = stq_clr_head_idx_temp_vec_22 ? 6'h16 : _stq_clr_head_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_33 = stq_clr_head_idx_temp_vec_21 ? 6'h15 : _stq_clr_head_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_34 = stq_clr_head_idx_temp_vec_20 ? 6'h14 : _stq_clr_head_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_35 = stq_clr_head_idx_temp_vec_19 ? 6'h13 : _stq_clr_head_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_36 = stq_clr_head_idx_temp_vec_18 ? 6'h12 : _stq_clr_head_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_37 = stq_clr_head_idx_temp_vec_17 ? 6'h11 : _stq_clr_head_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_38 = stq_clr_head_idx_temp_vec_16 ? 6'h10 : _stq_clr_head_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_39 = stq_clr_head_idx_temp_vec_15 ? 6'hF : _stq_clr_head_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_40 = stq_clr_head_idx_temp_vec_14 ? 6'hE : _stq_clr_head_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_41 = stq_clr_head_idx_temp_vec_13 ? 6'hD : _stq_clr_head_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_42 = stq_clr_head_idx_temp_vec_12 ? 6'hC : _stq_clr_head_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_43 = stq_clr_head_idx_temp_vec_11 ? 6'hB : _stq_clr_head_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_44 = stq_clr_head_idx_temp_vec_10 ? 6'hA : _stq_clr_head_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_45 = stq_clr_head_idx_temp_vec_9 ? 6'h9 : _stq_clr_head_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_46 = stq_clr_head_idx_temp_vec_8 ? 6'h8 : _stq_clr_head_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_47 = stq_clr_head_idx_temp_vec_7 ? 6'h7 : _stq_clr_head_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_48 = stq_clr_head_idx_temp_vec_6 ? 6'h6 : _stq_clr_head_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_49 = stq_clr_head_idx_temp_vec_5 ? 6'h5 : _stq_clr_head_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_50 = stq_clr_head_idx_temp_vec_4 ? 6'h4 : _stq_clr_head_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_51 = stq_clr_head_idx_temp_vec_3 ? 6'h3 : _stq_clr_head_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_52 = stq_clr_head_idx_temp_vec_2 ? 6'h2 : _stq_clr_head_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_53 = stq_clr_head_idx_temp_vec_1 ? 6'h1 : _stq_clr_head_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] stq_clr_head_idx_idx = stq_clr_head_idx_temp_vec_0 ? 6'h0 : _stq_clr_head_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_T_48 = stq_clr_head_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] stq_clr_head_idx; // @[lsu.scala:1076:33] wire [4:0] _s_uop_T = stq_clr_head_idx; // @[lsu.scala:1076:33] reg clr_valid; // @[lsu.scala:1084:24] reg [31:0] clr_uop_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_inst = clr_uop_inst; // @[util.scala:104:23] reg [31:0] clr_uop_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_debug_inst = clr_uop_debug_inst; // @[util.scala:104:23] reg clr_uop_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rvc = clr_uop_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_debug_pc = clr_uop_debug_pc; // @[util.scala:104:23] reg clr_uop_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_0 = clr_uop_iq_type_0; // @[util.scala:104:23] reg clr_uop_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_1 = clr_uop_iq_type_1; // @[util.scala:104:23] reg clr_uop_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_2 = clr_uop_iq_type_2; // @[util.scala:104:23] reg clr_uop_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_3 = clr_uop_iq_type_3; // @[util.scala:104:23] reg clr_uop_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_0 = clr_uop_fu_code_0; // @[util.scala:104:23] reg clr_uop_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_1 = clr_uop_fu_code_1; // @[util.scala:104:23] reg clr_uop_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_2 = clr_uop_fu_code_2; // @[util.scala:104:23] reg clr_uop_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_3 = clr_uop_fu_code_3; // @[util.scala:104:23] reg clr_uop_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_4 = clr_uop_fu_code_4; // @[util.scala:104:23] reg clr_uop_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_5 = clr_uop_fu_code_5; // @[util.scala:104:23] reg clr_uop_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_6 = clr_uop_fu_code_6; // @[util.scala:104:23] reg clr_uop_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_7 = clr_uop_fu_code_7; // @[util.scala:104:23] reg clr_uop_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_8 = clr_uop_fu_code_8; // @[util.scala:104:23] reg clr_uop_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_9 = clr_uop_fu_code_9; // @[util.scala:104:23] reg clr_uop_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued = clr_uop_iw_issued; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_agen = clr_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_dgen = clr_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_iw_p1_speculative_child = clr_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_iw_p2_speculative_child = clr_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p1_bypass_hint = clr_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p2_bypass_hint = clr_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p3_bypass_hint = clr_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_dis_col_sel = clr_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_tag = clr_uop_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_type = clr_uop_br_type; // @[util.scala:104:23] reg clr_uop_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfb = clr_uop_is_sfb; // @[util.scala:104:23] reg clr_uop_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fence = clr_uop_is_fence; // @[util.scala:104:23] reg clr_uop_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fencei = clr_uop_is_fencei; // @[util.scala:104:23] reg clr_uop_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfence = clr_uop_is_sfence; // @[util.scala:104:23] reg clr_uop_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_amo = clr_uop_is_amo; // @[util.scala:104:23] reg clr_uop_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_eret = clr_uop_is_eret; // @[util.scala:104:23] reg clr_uop_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sys_pc2epc = clr_uop_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rocc = clr_uop_is_rocc; // @[util.scala:104:23] reg clr_uop_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_mov = clr_uop_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ftq_idx = clr_uop_ftq_idx; // @[util.scala:104:23] reg clr_uop_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_edge_inst = clr_uop_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_pc_lob = clr_uop_pc_lob; // @[util.scala:104:23] reg clr_uop_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_taken = clr_uop_taken; // @[util.scala:104:23] reg clr_uop_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_imm_rename = clr_uop_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_imm_sel = clr_uop_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_pimm = clr_uop_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_imm_packed = clr_uop_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_op1_sel = clr_uop_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_op2_sel = clr_uop_op2_sel; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ldst = clr_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wen = clr_uop_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren1 = clr_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren2 = clr_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren3 = clr_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap12 = clr_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap23 = clr_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagIn = clr_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagOut = clr_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fromint = clr_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_toint = clr_uop_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fastpipe = clr_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fma = clr_uop_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_div = clr_uop_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_sqrt = clr_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wflags = clr_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_vec = clr_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_rob_idx = clr_uop_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ldq_idx = clr_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_stq_idx = clr_uop_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_rxq_idx = clr_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_pdst = clr_uop_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs1 = clr_uop_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs2 = clr_uop_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs3 = clr_uop_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ppred = clr_uop_ppred; // @[util.scala:104:23] reg clr_uop_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs1_busy = clr_uop_prs1_busy; // @[util.scala:104:23] reg clr_uop_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs2_busy = clr_uop_prs2_busy; // @[util.scala:104:23] reg clr_uop_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs3_busy = clr_uop_prs3_busy; // @[util.scala:104:23] reg clr_uop_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_ppred_busy = clr_uop_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_stale_pdst = clr_uop_stale_pdst; // @[util.scala:104:23] reg clr_uop_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_exception = clr_uop_exception; // @[util.scala:104:23] reg [63:0] clr_uop_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_exc_cause = clr_uop_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_mem_cmd = clr_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_mem_size = clr_uop_mem_size; // @[util.scala:104:23] reg clr_uop_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_mem_signed = clr_uop_mem_signed; // @[util.scala:104:23] reg clr_uop_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_ldq = clr_uop_uses_ldq; // @[util.scala:104:23] reg clr_uop_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_stq = clr_uop_uses_stq; // @[util.scala:104:23] reg clr_uop_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_unique = clr_uop_is_unique; // @[util.scala:104:23] reg clr_uop_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_flush_on_commit = clr_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_csr_cmd = clr_uop_csr_cmd; // @[util.scala:104:23] reg clr_uop_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_ldst_is_rs1 = clr_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_ldst = clr_uop_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs1 = clr_uop_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs2 = clr_uop_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs3 = clr_uop_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dst_rtype = clr_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs1_rtype = clr_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs2_rtype = clr_uop_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_frs3_en = clr_uop_frs3_en; // @[util.scala:104:23] reg clr_uop_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_fcn_dw = clr_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_fcn_op = clr_uop_fcn_op; // @[util.scala:104:23] reg clr_uop_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_val = clr_uop_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_fp_rm = clr_uop_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_typ = clr_uop_fp_typ; // @[util.scala:104:23] reg clr_uop_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_pf_if = clr_uop_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ae_if = clr_uop_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ma_if = clr_uop_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_debug_if = clr_uop_bp_debug_if; // @[util.scala:104:23] reg clr_uop_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_xcpt_if = clr_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_fsrc = clr_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_tsrc = clr_uop_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_1 = \|_clr_valid_1_T; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_2 = _clr_valid_1_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_3 = ~_clr_valid_1_T_2; // @[util.scala:61:61] wire _clr_valid_1_T_4 = clr_valid & _clr_valid_1_T_3; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_1 = clr_uop_br_mask & _clr_uop_1_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_1_out_br_mask = _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_0_bits_0 = clr_uop_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_1 = _s_uop_T; wire [31:0] clr_uop_out_inst = s_uop_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_debug_inst = s_uop_debug_inst; // @[util.scala:104:23] wire clr_uop_out_is_rvc = s_uop_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_debug_pc = s_uop_debug_pc; // @[util.scala:104:23] wire clr_uop_out_iq_type_0 = s_uop_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_iq_type_1 = s_uop_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_iq_type_2 = s_uop_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_iq_type_3 = s_uop_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_0 = s_uop_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_fu_code_1 = s_uop_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_fu_code_2 = s_uop_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_fu_code_3 = s_uop_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_4 = s_uop_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_fu_code_5 = s_uop_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_fu_code_6 = s_uop_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_fu_code_7 = s_uop_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_fu_code_8 = s_uop_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_fu_code_9 = s_uop_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_iw_issued = s_uop_iw_issued; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_agen = s_uop_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_dgen = s_uop_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_iw_p1_speculative_child = s_uop_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_iw_p2_speculative_child = s_uop_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_iw_p1_bypass_hint = s_uop_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p2_bypass_hint = s_uop_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p3_bypass_hint = s_uop_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_dis_col_sel = s_uop_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_tag = s_uop_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_type = s_uop_br_type; // @[util.scala:104:23] wire clr_uop_out_is_sfb = s_uop_is_sfb; // @[util.scala:104:23] wire clr_uop_out_is_fence = s_uop_is_fence; // @[util.scala:104:23] wire clr_uop_out_is_fencei = s_uop_is_fencei; // @[util.scala:104:23] wire clr_uop_out_is_sfence = s_uop_is_sfence; // @[util.scala:104:23] wire clr_uop_out_is_amo = s_uop_is_amo; // @[util.scala:104:23] wire clr_uop_out_is_eret = s_uop_is_eret; // @[util.scala:104:23] wire clr_uop_out_is_sys_pc2epc = s_uop_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_is_rocc = s_uop_is_rocc; // @[util.scala:104:23] wire clr_uop_out_is_mov = s_uop_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_ftq_idx = s_uop_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_edge_inst = s_uop_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_pc_lob = s_uop_pc_lob; // @[util.scala:104:23] wire clr_uop_out_taken = s_uop_taken; // @[util.scala:104:23] wire clr_uop_out_imm_rename = s_uop_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_imm_sel = s_uop_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_pimm = s_uop_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_imm_packed = s_uop_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_op1_sel = s_uop_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_op2_sel = s_uop_op2_sel; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ldst = s_uop_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wen = s_uop_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren1 = s_uop_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren2 = s_uop_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren3 = s_uop_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap12 = s_uop_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap23 = s_uop_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagIn = s_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagOut = s_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fromint = s_uop_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_toint = s_uop_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fastpipe = s_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fma = s_uop_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_div = s_uop_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_sqrt = s_uop_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wflags = s_uop_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_vec = s_uop_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_rob_idx = s_uop_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_ldq_idx = s_uop_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_stq_idx = s_uop_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_rxq_idx = s_uop_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_pdst = s_uop_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs1 = s_uop_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs2 = s_uop_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs3 = s_uop_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_ppred = s_uop_ppred; // @[util.scala:104:23] wire clr_uop_out_prs1_busy = s_uop_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_prs2_busy = s_uop_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_prs3_busy = s_uop_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_ppred_busy = s_uop_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_stale_pdst = s_uop_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_exception = s_uop_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_exc_cause = s_uop_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_mem_cmd = s_uop_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_mem_size = s_uop_mem_size; // @[util.scala:104:23] wire clr_uop_out_mem_signed = s_uop_mem_signed; // @[util.scala:104:23] wire clr_uop_out_uses_ldq = s_uop_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_uses_stq = s_uop_uses_stq; // @[util.scala:104:23] wire clr_uop_out_is_unique = s_uop_is_unique; // @[util.scala:104:23] wire clr_uop_out_flush_on_commit = s_uop_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_csr_cmd = s_uop_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_ldst_is_rs1 = s_uop_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_ldst = s_uop_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs1 = s_uop_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs2 = s_uop_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs3 = s_uop_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_dst_rtype = s_uop_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs1_rtype = s_uop_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs2_rtype = s_uop_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_frs3_en = s_uop_frs3_en; // @[util.scala:104:23] wire clr_uop_out_fcn_dw = s_uop_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_fcn_op = s_uop_fcn_op; // @[util.scala:104:23] wire clr_uop_out_fp_val = s_uop_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_fp_rm = s_uop_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_typ = s_uop_fp_typ; // @[util.scala:104:23] wire clr_uop_out_xcpt_pf_if = s_uop_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ae_if = s_uop_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ma_if = s_uop_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_bp_debug_if = s_uop_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_bp_xcpt_if = s_uop_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_fsrc = s_uop_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_tsrc = s_uop_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_br_mask; // @[lsu.scala:1093:25] assign s_uop_inst = _GEN_251[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_inst = _GEN_252[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rvc = _GEN_253[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_pc = _GEN_254[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_0 = _GEN_255[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_1 = _GEN_256[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_2 = _GEN_257[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_3 = _GEN_258[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_0 = _GEN_259[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_1 = _GEN_260[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_2 = _GEN_261[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_3 = _GEN_262[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_4 = _GEN_263[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_5 = _GEN_264[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_6 = _GEN_265[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_7 = _GEN_266[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_8 = _GEN_267[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_9 = _GEN_268[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued = _GEN_269[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_agen = _GEN_270[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_dgen = _GEN_271[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_speculative_child = _GEN_272[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_speculative_child = _GEN_273[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_bypass_hint = _GEN_274[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_bypass_hint = _GEN_275[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p3_bypass_hint = _GEN_276[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dis_col_sel = _GEN_277[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_mask = _GEN_278[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_tag = _GEN_279[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_type = _GEN_280[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfb = _GEN_281[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fence = _GEN_282[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fencei = _GEN_283[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfence = _GEN_284[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_amo = _GEN_285[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_eret = _GEN_286[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sys_pc2epc = _GEN_287[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rocc = _GEN_288[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_mov = _GEN_289[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ftq_idx = _GEN_290[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_edge_inst = _GEN_291[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pc_lob = _GEN_292[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_taken = _GEN_293[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_rename = _GEN_294[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_sel = _GEN_295[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pimm = _GEN_296[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_packed = _GEN_297[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op1_sel = _GEN_298[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op2_sel = _GEN_299[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ldst = _GEN_300[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wen = _GEN_301[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren1 = _GEN_302[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren2 = _GEN_303[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren3 = _GEN_304[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap12 = _GEN_305[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap23 = _GEN_306[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fromint = _GEN_309[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_toint = _GEN_310[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fma = _GEN_312[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_div = _GEN_313[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_sqrt = _GEN_314[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wflags = _GEN_315[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_vec = _GEN_316[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rob_idx = _GEN_317[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldq_idx = _GEN_318[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stq_idx = _GEN_319[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rxq_idx = _GEN_320[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pdst = _GEN_321[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1 = _GEN_322[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2 = _GEN_323[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3 = _GEN_324[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred = _GEN_325[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1_busy = _GEN_326[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2_busy = _GEN_327[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3_busy = _GEN_328[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred_busy = _GEN_329[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stale_pdst = _GEN_330[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exception = _GEN_331[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exc_cause = _GEN_332[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_cmd = _GEN_333[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_size = _GEN_334[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_signed = _GEN_335[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_ldq = _GEN_336[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_stq = _GEN_337[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_unique = _GEN_338[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_flush_on_commit = _GEN_339[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_csr_cmd = _GEN_340[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst_is_rs1 = _GEN_341[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst = _GEN_342[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1 = _GEN_343[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2 = _GEN_344[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs3 = _GEN_345[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dst_rtype = _GEN_346[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1_rtype = _GEN_347[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2_rtype = _GEN_348[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_frs3_en = _GEN_349[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_dw = _GEN_350[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_op = _GEN_351[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_val = _GEN_352[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_rm = _GEN_353[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_typ = _GEN_354[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_pf_if = _GEN_355[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ae_if = _GEN_356[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ma_if = _GEN_357[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_debug_if = _GEN_358[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_xcpt_if = _GEN_359[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_fsrc = _GEN_360[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_tsrc = _GEN_361[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] clr_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_1 = s_uop_br_mask & _clr_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_out_br_mask = _clr_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire wrap_6 = stq_clr_head_idx == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_0_valid_T_1 = \|_io_core_clr_bsy_0_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = _io_core_clr_bsy_0_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_0_valid_T_3 = ~_io_core_clr_bsy_0_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_0_valid_T_4 = clr_valid_1 & _io_core_clr_bsy_0_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [4:0] _s_uop_T_2 = wrap_6 ? 5'h0 : stq_clr_head_idx + 5'h1; // @[util.scala:213:25, :214:{10,28}] reg clr_valid_2; // @[lsu.scala:1084:24] reg [31:0] clr_uop_2_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_inst = clr_uop_2_inst; // @[util.scala:104:23] reg [31:0] clr_uop_2_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_debug_inst = clr_uop_2_debug_inst; // @[util.scala:104:23] reg clr_uop_2_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rvc = clr_uop_2_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_2_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_1_debug_pc = clr_uop_2_debug_pc; // @[util.scala:104:23] reg clr_uop_2_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_0 = clr_uop_2_iq_type_0; // @[util.scala:104:23] reg clr_uop_2_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_1 = clr_uop_2_iq_type_1; // @[util.scala:104:23] reg clr_uop_2_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_2 = clr_uop_2_iq_type_2; // @[util.scala:104:23] reg clr_uop_2_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_3 = clr_uop_2_iq_type_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_0 = clr_uop_2_fu_code_0; // @[util.scala:104:23] reg clr_uop_2_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_1 = clr_uop_2_fu_code_1; // @[util.scala:104:23] reg clr_uop_2_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_2 = clr_uop_2_fu_code_2; // @[util.scala:104:23] reg clr_uop_2_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_3 = clr_uop_2_fu_code_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_4 = clr_uop_2_fu_code_4; // @[util.scala:104:23] reg clr_uop_2_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_5 = clr_uop_2_fu_code_5; // @[util.scala:104:23] reg clr_uop_2_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_6 = clr_uop_2_fu_code_6; // @[util.scala:104:23] reg clr_uop_2_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_7 = clr_uop_2_fu_code_7; // @[util.scala:104:23] reg clr_uop_2_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_8 = clr_uop_2_fu_code_8; // @[util.scala:104:23] reg clr_uop_2_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_9 = clr_uop_2_fu_code_9; // @[util.scala:104:23] reg clr_uop_2_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued = clr_uop_2_iw_issued; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_agen = clr_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_dgen = clr_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_2_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_iw_p1_speculative_child = clr_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_2_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_iw_p2_speculative_child = clr_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p1_bypass_hint = clr_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p2_bypass_hint = clr_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p3_bypass_hint = clr_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_2_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_dis_col_sel = clr_uop_2_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_2_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_2_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_tag = clr_uop_2_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_2_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_type = clr_uop_2_br_type; // @[util.scala:104:23] reg clr_uop_2_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfb = clr_uop_2_is_sfb; // @[util.scala:104:23] reg clr_uop_2_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fence = clr_uop_2_is_fence; // @[util.scala:104:23] reg clr_uop_2_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fencei = clr_uop_2_is_fencei; // @[util.scala:104:23] reg clr_uop_2_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfence = clr_uop_2_is_sfence; // @[util.scala:104:23] reg clr_uop_2_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_amo = clr_uop_2_is_amo; // @[util.scala:104:23] reg clr_uop_2_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_eret = clr_uop_2_is_eret; // @[util.scala:104:23] reg clr_uop_2_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sys_pc2epc = clr_uop_2_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_2_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rocc = clr_uop_2_is_rocc; // @[util.scala:104:23] reg clr_uop_2_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_mov = clr_uop_2_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_2_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ftq_idx = clr_uop_2_ftq_idx; // @[util.scala:104:23] reg clr_uop_2_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_edge_inst = clr_uop_2_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_2_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_pc_lob = clr_uop_2_pc_lob; // @[util.scala:104:23] reg clr_uop_2_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_taken = clr_uop_2_taken; // @[util.scala:104:23] reg clr_uop_2_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_imm_rename = clr_uop_2_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_2_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_imm_sel = clr_uop_2_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_2_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_pimm = clr_uop_2_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_2_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_1_imm_packed = clr_uop_2_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_2_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_op1_sel = clr_uop_2_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_2_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_op2_sel = clr_uop_2_op2_sel; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ldst = clr_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wen = clr_uop_2_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren1 = clr_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren2 = clr_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren3 = clr_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap12 = clr_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap23 = clr_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagIn = clr_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagOut = clr_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fromint = clr_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_toint = clr_uop_2_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fastpipe = clr_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fma = clr_uop_2_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_div = clr_uop_2_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_sqrt = clr_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wflags = clr_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_vec = clr_uop_2_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_2_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_rob_idx = clr_uop_2_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_2_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ldq_idx = clr_uop_2_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_2_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_stq_idx = clr_uop_2_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_2_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_rxq_idx = clr_uop_2_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_2_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_pdst = clr_uop_2_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs1 = clr_uop_2_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs2 = clr_uop_2_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs3 = clr_uop_2_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_2_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ppred = clr_uop_2_ppred; // @[util.scala:104:23] reg clr_uop_2_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs1_busy = clr_uop_2_prs1_busy; // @[util.scala:104:23] reg clr_uop_2_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs2_busy = clr_uop_2_prs2_busy; // @[util.scala:104:23] reg clr_uop_2_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs3_busy = clr_uop_2_prs3_busy; // @[util.scala:104:23] reg clr_uop_2_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ppred_busy = clr_uop_2_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_2_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_stale_pdst = clr_uop_2_stale_pdst; // @[util.scala:104:23] reg clr_uop_2_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_exception = clr_uop_2_exception; // @[util.scala:104:23] reg [63:0] clr_uop_2_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_1_exc_cause = clr_uop_2_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_2_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_mem_cmd = clr_uop_2_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_2_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_mem_size = clr_uop_2_mem_size; // @[util.scala:104:23] reg clr_uop_2_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_mem_signed = clr_uop_2_mem_signed; // @[util.scala:104:23] reg clr_uop_2_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_ldq = clr_uop_2_uses_ldq; // @[util.scala:104:23] reg clr_uop_2_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_stq = clr_uop_2_uses_stq; // @[util.scala:104:23] reg clr_uop_2_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_unique = clr_uop_2_is_unique; // @[util.scala:104:23] reg clr_uop_2_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_flush_on_commit = clr_uop_2_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_2_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_csr_cmd = clr_uop_2_csr_cmd; // @[util.scala:104:23] reg clr_uop_2_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ldst_is_rs1 = clr_uop_2_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_ldst = clr_uop_2_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs1 = clr_uop_2_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs2 = clr_uop_2_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs3 = clr_uop_2_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_2_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dst_rtype = clr_uop_2_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs1_rtype = clr_uop_2_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs2_rtype = clr_uop_2_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_2_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_frs3_en = clr_uop_2_frs3_en; // @[util.scala:104:23] reg clr_uop_2_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fcn_dw = clr_uop_2_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_2_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_fcn_op = clr_uop_2_fcn_op; // @[util.scala:104:23] reg clr_uop_2_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_val = clr_uop_2_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_2_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_fp_rm = clr_uop_2_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_typ = clr_uop_2_fp_typ; // @[util.scala:104:23] reg clr_uop_2_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_pf_if = clr_uop_2_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ae_if = clr_uop_2_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ma_if = clr_uop_2_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_2_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_debug_if = clr_uop_2_bp_debug_if; // @[util.scala:104:23] reg clr_uop_2_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_xcpt_if = clr_uop_2_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_fsrc = clr_uop_2_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_tsrc = clr_uop_2_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T_5 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_2_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_6 = \|_clr_valid_1_T_5; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_7 = _clr_valid_1_T_6 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_8 = ~_clr_valid_1_T_7; // @[util.scala:61:61] wire _clr_valid_1_T_9 = clr_valid_2 & _clr_valid_1_T_8; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_1; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_3 = clr_uop_2_br_mask & _clr_uop_1_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_1_out_1_br_mask = _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_1_bits_0 = clr_uop_1_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_1_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_3 = _s_uop_T_2; wire [31:0] clr_uop_out_1_inst = s_uop_1_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_1_debug_inst = s_uop_1_debug_inst; // @[util.scala:104:23] wire clr_uop_out_1_is_rvc = s_uop_1_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_1_debug_pc = s_uop_1_debug_pc; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_0 = s_uop_1_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_1 = s_uop_1_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_2 = s_uop_1_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_3 = s_uop_1_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_0 = s_uop_1_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_1 = s_uop_1_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_2 = s_uop_1_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_3 = s_uop_1_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_4 = s_uop_1_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_5 = s_uop_1_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_6 = s_uop_1_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_7 = s_uop_1_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_8 = s_uop_1_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_9 = s_uop_1_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued = s_uop_1_iw_issued; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_agen = s_uop_1_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_dgen = s_uop_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_iw_p1_speculative_child = s_uop_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_iw_p2_speculative_child = s_uop_1_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_1_iw_p1_bypass_hint = s_uop_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p2_bypass_hint = s_uop_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p3_bypass_hint = s_uop_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_dis_col_sel = s_uop_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_tag = s_uop_1_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_type = s_uop_1_br_type; // @[util.scala:104:23] wire clr_uop_out_1_is_sfb = s_uop_1_is_sfb; // @[util.scala:104:23] wire clr_uop_out_1_is_fence = s_uop_1_is_fence; // @[util.scala:104:23] wire clr_uop_out_1_is_fencei = s_uop_1_is_fencei; // @[util.scala:104:23] wire clr_uop_out_1_is_sfence = s_uop_1_is_sfence; // @[util.scala:104:23] wire clr_uop_out_1_is_amo = s_uop_1_is_amo; // @[util.scala:104:23] wire clr_uop_out_1_is_eret = s_uop_1_is_eret; // @[util.scala:104:23] wire clr_uop_out_1_is_sys_pc2epc = s_uop_1_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_1_is_rocc = s_uop_1_is_rocc; // @[util.scala:104:23] wire clr_uop_out_1_is_mov = s_uop_1_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ftq_idx = s_uop_1_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_1_edge_inst = s_uop_1_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_pc_lob = s_uop_1_pc_lob; // @[util.scala:104:23] wire clr_uop_out_1_taken = s_uop_1_taken; // @[util.scala:104:23] wire clr_uop_out_1_imm_rename = s_uop_1_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_imm_sel = s_uop_1_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_pimm = s_uop_1_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_1_imm_packed = s_uop_1_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_op1_sel = s_uop_1_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_op2_sel = s_uop_1_op2_sel; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ldst = s_uop_1_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wen = s_uop_1_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren1 = s_uop_1_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren2 = s_uop_1_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren3 = s_uop_1_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap12 = s_uop_1_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap23 = s_uop_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagIn = s_uop_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagOut = s_uop_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fromint = s_uop_1_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_toint = s_uop_1_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fastpipe = s_uop_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fma = s_uop_1_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_div = s_uop_1_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_sqrt = s_uop_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wflags = s_uop_1_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_vec = s_uop_1_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_rob_idx = s_uop_1_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ldq_idx = s_uop_1_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_stq_idx = s_uop_1_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_rxq_idx = s_uop_1_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_pdst = s_uop_1_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs1 = s_uop_1_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs2 = s_uop_1_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs3 = s_uop_1_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ppred = s_uop_1_ppred; // @[util.scala:104:23] wire clr_uop_out_1_prs1_busy = s_uop_1_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs2_busy = s_uop_1_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs3_busy = s_uop_1_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_1_ppred_busy = s_uop_1_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_stale_pdst = s_uop_1_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_1_exception = s_uop_1_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_1_exc_cause = s_uop_1_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_mem_cmd = s_uop_1_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_mem_size = s_uop_1_mem_size; // @[util.scala:104:23] wire clr_uop_out_1_mem_signed = s_uop_1_mem_signed; // @[util.scala:104:23] wire clr_uop_out_1_uses_ldq = s_uop_1_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_1_uses_stq = s_uop_1_uses_stq; // @[util.scala:104:23] wire clr_uop_out_1_is_unique = s_uop_1_is_unique; // @[util.scala:104:23] wire clr_uop_out_1_flush_on_commit = s_uop_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_csr_cmd = s_uop_1_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_1_ldst_is_rs1 = s_uop_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_ldst = s_uop_1_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs1 = s_uop_1_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs2 = s_uop_1_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs3 = s_uop_1_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dst_rtype = s_uop_1_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs1_rtype = s_uop_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs2_rtype = s_uop_1_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_1_frs3_en = s_uop_1_frs3_en; // @[util.scala:104:23] wire clr_uop_out_1_fcn_dw = s_uop_1_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_fcn_op = s_uop_1_fcn_op; // @[util.scala:104:23] wire clr_uop_out_1_fp_val = s_uop_1_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_fp_rm = s_uop_1_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_typ = s_uop_1_fp_typ; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_pf_if = s_uop_1_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ae_if = s_uop_1_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ma_if = s_uop_1_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_debug_if = s_uop_1_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_xcpt_if = s_uop_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_fsrc = s_uop_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_tsrc = s_uop_1_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_1_br_mask; // @[lsu.scala:1093:25] assign s_uop_1_inst = _GEN_251[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_inst = _GEN_252[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_rvc = _GEN_253[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_pc = _GEN_254[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_0 = _GEN_255[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_1 = _GEN_256[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_2 = _GEN_257[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_3 = _GEN_258[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_0 = _GEN_259[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_1 = _GEN_260[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_2 = _GEN_261[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_3 = _GEN_262[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_4 = _GEN_263[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_5 = _GEN_264[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_6 = _GEN_265[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_7 = _GEN_266[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_8 = _GEN_267[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_9 = _GEN_268[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued = _GEN_269[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued_partial_agen = _GEN_270[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued_partial_dgen = _GEN_271[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p1_speculative_child = _GEN_272[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p2_speculative_child = _GEN_273[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p1_bypass_hint = _GEN_274[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p2_bypass_hint = _GEN_275[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p3_bypass_hint = _GEN_276[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_dis_col_sel = _GEN_277[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_mask = _GEN_278[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_tag = _GEN_279[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_type = _GEN_280[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sfb = _GEN_281[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_fence = _GEN_282[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_fencei = _GEN_283[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sfence = _GEN_284[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_amo = _GEN_285[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_eret = _GEN_286[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sys_pc2epc = _GEN_287[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_rocc = _GEN_288[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_mov = _GEN_289[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ftq_idx = _GEN_290[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_edge_inst = _GEN_291[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pc_lob = _GEN_292[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_taken = _GEN_293[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_rename = _GEN_294[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_sel = _GEN_295[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pimm = _GEN_296[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_packed = _GEN_297[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_op1_sel = _GEN_298[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_op2_sel = _GEN_299[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ldst = _GEN_300[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_wen = _GEN_301[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren1 = _GEN_302[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren2 = _GEN_303[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren3 = _GEN_304[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_swap12 = _GEN_305[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_swap23 = _GEN_306[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fromint = _GEN_309[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_toint = _GEN_310[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fma = _GEN_312[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_div = _GEN_313[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_sqrt = _GEN_314[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_wflags = _GEN_315[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_vec = _GEN_316[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_rob_idx = _GEN_317[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldq_idx = _GEN_318[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_stq_idx = _GEN_319[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_rxq_idx = _GEN_320[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pdst = _GEN_321[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs1 = _GEN_322[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs2 = _GEN_323[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs3 = _GEN_324[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ppred = _GEN_325[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs1_busy = _GEN_326[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs2_busy = _GEN_327[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs3_busy = _GEN_328[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ppred_busy = _GEN_329[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_stale_pdst = _GEN_330[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_exception = _GEN_331[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_exc_cause = _GEN_332[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_cmd = _GEN_333[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_size = _GEN_334[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_signed = _GEN_335[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_uses_ldq = _GEN_336[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_uses_stq = _GEN_337[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_unique = _GEN_338[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_flush_on_commit = _GEN_339[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_csr_cmd = _GEN_340[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldst_is_rs1 = _GEN_341[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldst = _GEN_342[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs1 = _GEN_343[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs2 = _GEN_344[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs3 = _GEN_345[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_dst_rtype = _GEN_346[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs1_rtype = _GEN_347[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs2_rtype = _GEN_348[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_frs3_en = _GEN_349[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fcn_dw = _GEN_350[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fcn_op = _GEN_351[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_val = _GEN_352[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_rm = _GEN_353[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_typ = _GEN_354[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_pf_if = _GEN_355[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_ae_if = _GEN_356[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_ma_if = _GEN_357[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_bp_debug_if = _GEN_358[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_bp_xcpt_if = _GEN_359[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_fsrc = _GEN_360[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_tsrc = _GEN_361[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] clr_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_3 = s_uop_1_br_mask & _clr_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_out_1_br_mask = _clr_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire wrap_7 = _s_uop_T_2 == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_1_valid_T_1 = \|_io_core_clr_bsy_1_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = _io_core_clr_bsy_1_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_1_valid_T_3 = ~_io_core_clr_bsy_1_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_1_valid_T_4 = clr_valid_1_1 & _io_core_clr_bsy_1_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [4:0] _s_uop_T_4 = wrap_7 ? 5'h0 : _s_uop_T_2 + 5'h1; // @[util.scala:213:25, :214:{10,28}] reg clr_valid_3; // @[lsu.scala:1084:24] reg [31:0] clr_uop_3_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_2_inst = clr_uop_3_inst; // @[util.scala:104:23] reg [31:0] clr_uop_3_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_2_debug_inst = clr_uop_3_debug_inst; // @[util.scala:104:23] reg clr_uop_3_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_rvc = clr_uop_3_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_3_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_2_debug_pc = clr_uop_3_debug_pc; // @[util.scala:104:23] reg clr_uop_3_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_0 = clr_uop_3_iq_type_0; // @[util.scala:104:23] reg clr_uop_3_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_1 = clr_uop_3_iq_type_1; // @[util.scala:104:23] reg clr_uop_3_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_2 = clr_uop_3_iq_type_2; // @[util.scala:104:23] reg clr_uop_3_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_3 = clr_uop_3_iq_type_3; // @[util.scala:104:23] reg clr_uop_3_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_0 = clr_uop_3_fu_code_0; // @[util.scala:104:23] reg clr_uop_3_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_1 = clr_uop_3_fu_code_1; // @[util.scala:104:23] reg clr_uop_3_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_2 = clr_uop_3_fu_code_2; // @[util.scala:104:23] reg clr_uop_3_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_3 = clr_uop_3_fu_code_3; // @[util.scala:104:23] reg clr_uop_3_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_4 = clr_uop_3_fu_code_4; // @[util.scala:104:23] reg clr_uop_3_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_5 = clr_uop_3_fu_code_5; // @[util.scala:104:23] reg clr_uop_3_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_6 = clr_uop_3_fu_code_6; // @[util.scala:104:23] reg clr_uop_3_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_7 = clr_uop_3_fu_code_7; // @[util.scala:104:23] reg clr_uop_3_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_8 = clr_uop_3_fu_code_8; // @[util.scala:104:23] reg clr_uop_3_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_9 = clr_uop_3_fu_code_9; // @[util.scala:104:23] reg clr_uop_3_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued = clr_uop_3_iw_issued; // @[util.scala:104:23] reg clr_uop_3_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued_partial_agen = clr_uop_3_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_3_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued_partial_dgen = clr_uop_3_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_3_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_iw_p1_speculative_child = clr_uop_3_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_3_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_iw_p2_speculative_child = clr_uop_3_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_3_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p1_bypass_hint = clr_uop_3_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_3_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p2_bypass_hint = clr_uop_3_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_3_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p3_bypass_hint = clr_uop_3_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_3_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_dis_col_sel = clr_uop_3_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_3_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_3_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_2_br_tag = clr_uop_3_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_3_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_2_br_type = clr_uop_3_br_type; // @[util.scala:104:23] reg clr_uop_3_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sfb = clr_uop_3_is_sfb; // @[util.scala:104:23] reg clr_uop_3_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_fence = clr_uop_3_is_fence; // @[util.scala:104:23] reg clr_uop_3_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_fencei = clr_uop_3_is_fencei; // @[util.scala:104:23] reg clr_uop_3_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sfence = clr_uop_3_is_sfence; // @[util.scala:104:23] reg clr_uop_3_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_amo = clr_uop_3_is_amo; // @[util.scala:104:23] reg clr_uop_3_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_eret = clr_uop_3_is_eret; // @[util.scala:104:23] reg clr_uop_3_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sys_pc2epc = clr_uop_3_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_3_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_rocc = clr_uop_3_is_rocc; // @[util.scala:104:23] reg clr_uop_3_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_mov = clr_uop_3_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_3_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ftq_idx = clr_uop_3_ftq_idx; // @[util.scala:104:23] reg clr_uop_3_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_edge_inst = clr_uop_3_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_3_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_pc_lob = clr_uop_3_pc_lob; // @[util.scala:104:23] reg clr_uop_3_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_taken = clr_uop_3_taken; // @[util.scala:104:23] reg clr_uop_3_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_imm_rename = clr_uop_3_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_3_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_imm_sel = clr_uop_3_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_3_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_pimm = clr_uop_3_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_3_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_2_imm_packed = clr_uop_3_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_3_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_op1_sel = clr_uop_3_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_3_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_op2_sel = clr_uop_3_op2_sel; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ldst = clr_uop_3_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_wen = clr_uop_3_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren1 = clr_uop_3_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren2 = clr_uop_3_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren3 = clr_uop_3_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_swap12 = clr_uop_3_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_swap23 = clr_uop_3_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_ctrl_typeTagIn = clr_uop_3_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_ctrl_typeTagOut = clr_uop_3_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fromint = clr_uop_3_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_toint = clr_uop_3_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fastpipe = clr_uop_3_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fma = clr_uop_3_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_div = clr_uop_3_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_sqrt = clr_uop_3_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_wflags = clr_uop_3_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_vec = clr_uop_3_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_3_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_rob_idx = clr_uop_3_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_3_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ldq_idx = clr_uop_3_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_3_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_stq_idx = clr_uop_3_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_3_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_rxq_idx = clr_uop_3_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_3_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_pdst = clr_uop_3_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs1 = clr_uop_3_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs2 = clr_uop_3_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs3 = clr_uop_3_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_3_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ppred = clr_uop_3_ppred; // @[util.scala:104:23] reg clr_uop_3_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs1_busy = clr_uop_3_prs1_busy; // @[util.scala:104:23] reg clr_uop_3_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs2_busy = clr_uop_3_prs2_busy; // @[util.scala:104:23] reg clr_uop_3_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs3_busy = clr_uop_3_prs3_busy; // @[util.scala:104:23] reg clr_uop_3_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_ppred_busy = clr_uop_3_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_3_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_stale_pdst = clr_uop_3_stale_pdst; // @[util.scala:104:23] reg clr_uop_3_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_exception = clr_uop_3_exception; // @[util.scala:104:23] reg [63:0] clr_uop_3_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_2_exc_cause = clr_uop_3_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_3_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_mem_cmd = clr_uop_3_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_3_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_mem_size = clr_uop_3_mem_size; // @[util.scala:104:23] reg clr_uop_3_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_mem_signed = clr_uop_3_mem_signed; // @[util.scala:104:23] reg clr_uop_3_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_uses_ldq = clr_uop_3_uses_ldq; // @[util.scala:104:23] reg clr_uop_3_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_uses_stq = clr_uop_3_uses_stq; // @[util.scala:104:23] reg clr_uop_3_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_unique = clr_uop_3_is_unique; // @[util.scala:104:23] reg clr_uop_3_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_flush_on_commit = clr_uop_3_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_3_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_csr_cmd = clr_uop_3_csr_cmd; // @[util.scala:104:23] reg clr_uop_3_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_ldst_is_rs1 = clr_uop_3_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_3_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_ldst = clr_uop_3_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs1 = clr_uop_3_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs2 = clr_uop_3_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs3 = clr_uop_3_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_3_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_dst_rtype = clr_uop_3_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_3_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_lrs1_rtype = clr_uop_3_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_3_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_lrs2_rtype = clr_uop_3_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_3_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_frs3_en = clr_uop_3_frs3_en; // @[util.scala:104:23] reg clr_uop_3_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fcn_dw = clr_uop_3_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_3_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_fcn_op = clr_uop_3_fcn_op; // @[util.scala:104:23] reg clr_uop_3_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_val = clr_uop_3_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_3_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_fp_rm = clr_uop_3_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_typ = clr_uop_3_fp_typ; // @[util.scala:104:23] reg clr_uop_3_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_pf_if = clr_uop_3_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_3_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_ae_if = clr_uop_3_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_3_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_ma_if = clr_uop_3_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_3_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_bp_debug_if = clr_uop_3_bp_debug_if; // @[util.scala:104:23] reg clr_uop_3_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_bp_xcpt_if = clr_uop_3_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_3_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_debug_fsrc = clr_uop_3_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_3_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_debug_tsrc = clr_uop_3_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T_10 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_3_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_11 = \|_clr_valid_1_T_10; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_12 = _clr_valid_1_T_11 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_13 = ~_clr_valid_1_T_12; // @[util.scala:61:61] wire _clr_valid_1_T_14 = clr_valid_3 & _clr_valid_1_T_13; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_2; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_5 = clr_uop_3_br_mask & _clr_uop_1_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign clr_uop_1_out_2_br_mask = _clr_uop_1_out_br_mask_T_5; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_2_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_2_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_2_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_2_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_2_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_2_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_2_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_2_taken; // @[lsu.scala:1089:30] reg clr_uop_1_2_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_2_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_2_bits_0 = clr_uop_1_2_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_2_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_2_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_2_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_2_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_2_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_2_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_2_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_2_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_2_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_2_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_5 = _s_uop_T_4; wire [31:0] clr_uop_out_2_inst = s_uop_2_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_2_debug_inst = s_uop_2_debug_inst; // @[util.scala:104:23] wire clr_uop_out_2_is_rvc = s_uop_2_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_2_debug_pc = s_uop_2_debug_pc; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_0 = s_uop_2_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_1 = s_uop_2_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_2 = s_uop_2_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_3 = s_uop_2_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_0 = s_uop_2_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_1 = s_uop_2_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_2 = s_uop_2_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_3 = s_uop_2_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_4 = s_uop_2_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_5 = s_uop_2_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_6 = s_uop_2_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_7 = s_uop_2_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_8 = s_uop_2_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_9 = s_uop_2_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued = s_uop_2_iw_issued; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued_partial_agen = s_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued_partial_dgen = s_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_iw_p1_speculative_child = s_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_iw_p2_speculative_child = s_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_2_iw_p1_bypass_hint = s_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_2_iw_p2_bypass_hint = s_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_2_iw_p3_bypass_hint = s_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_dis_col_sel = s_uop_2_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_2_br_tag = s_uop_2_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_2_br_type = s_uop_2_br_type; // @[util.scala:104:23] wire clr_uop_out_2_is_sfb = s_uop_2_is_sfb; // @[util.scala:104:23] wire clr_uop_out_2_is_fence = s_uop_2_is_fence; // @[util.scala:104:23] wire clr_uop_out_2_is_fencei = s_uop_2_is_fencei; // @[util.scala:104:23] wire clr_uop_out_2_is_sfence = s_uop_2_is_sfence; // @[util.scala:104:23] wire clr_uop_out_2_is_amo = s_uop_2_is_amo; // @[util.scala:104:23] wire clr_uop_out_2_is_eret = s_uop_2_is_eret; // @[util.scala:104:23] wire clr_uop_out_2_is_sys_pc2epc = s_uop_2_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_2_is_rocc = s_uop_2_is_rocc; // @[util.scala:104:23] wire clr_uop_out_2_is_mov = s_uop_2_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ftq_idx = s_uop_2_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_2_edge_inst = s_uop_2_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_pc_lob = s_uop_2_pc_lob; // @[util.scala:104:23] wire clr_uop_out_2_taken = s_uop_2_taken; // @[util.scala:104:23] wire clr_uop_out_2_imm_rename = s_uop_2_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_imm_sel = s_uop_2_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_pimm = s_uop_2_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_2_imm_packed = s_uop_2_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_op1_sel = s_uop_2_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_op2_sel = s_uop_2_op2_sel; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ldst = s_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_wen = s_uop_2_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren1 = s_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren2 = s_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren3 = s_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_swap12 = s_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_swap23 = s_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_ctrl_typeTagIn = s_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_ctrl_typeTagOut = s_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fromint = s_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_toint = s_uop_2_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fastpipe = s_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fma = s_uop_2_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_div = s_uop_2_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_sqrt = s_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_wflags = s_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_vec = s_uop_2_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_rob_idx = s_uop_2_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ldq_idx = s_uop_2_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_stq_idx = s_uop_2_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_rxq_idx = s_uop_2_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_pdst = s_uop_2_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs1 = s_uop_2_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs2 = s_uop_2_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs3 = s_uop_2_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ppred = s_uop_2_ppred; // @[util.scala:104:23] wire clr_uop_out_2_prs1_busy = s_uop_2_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_2_prs2_busy = s_uop_2_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_2_prs3_busy = s_uop_2_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_2_ppred_busy = s_uop_2_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_stale_pdst = s_uop_2_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_2_exception = s_uop_2_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_2_exc_cause = s_uop_2_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_mem_cmd = s_uop_2_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_mem_size = s_uop_2_mem_size; // @[util.scala:104:23] wire clr_uop_out_2_mem_signed = s_uop_2_mem_signed; // @[util.scala:104:23] wire clr_uop_out_2_uses_ldq = s_uop_2_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_2_uses_stq = s_uop_2_uses_stq; // @[util.scala:104:23] wire clr_uop_out_2_is_unique = s_uop_2_is_unique; // @[util.scala:104:23] wire clr_uop_out_2_flush_on_commit = s_uop_2_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_csr_cmd = s_uop_2_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_2_ldst_is_rs1 = s_uop_2_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_ldst = s_uop_2_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs1 = s_uop_2_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs2 = s_uop_2_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs3 = s_uop_2_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_dst_rtype = s_uop_2_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_lrs1_rtype = s_uop_2_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_lrs2_rtype = s_uop_2_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_2_frs3_en = s_uop_2_frs3_en; // @[util.scala:104:23] wire clr_uop_out_2_fcn_dw = s_uop_2_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_fcn_op = s_uop_2_fcn_op; // @[util.scala:104:23] wire clr_uop_out_2_fp_val = s_uop_2_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_fp_rm = s_uop_2_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_typ = s_uop_2_fp_typ; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_pf_if = s_uop_2_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_ae_if = s_uop_2_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_ma_if = s_uop_2_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_2_bp_debug_if = s_uop_2_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_2_bp_xcpt_if = s_uop_2_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_debug_fsrc = s_uop_2_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_debug_tsrc = s_uop_2_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_2_br_mask; // @[lsu.scala:1093:25] assign s_uop_2_inst = _GEN_251[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_inst = _GEN_252[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_rvc = _GEN_253[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_pc = _GEN_254[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_0 = _GEN_255[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_1 = _GEN_256[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_2 = _GEN_257[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_3 = _GEN_258[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_0 = _GEN_259[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_1 = _GEN_260[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_2 = _GEN_261[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_3 = _GEN_262[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_4 = _GEN_263[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_5 = _GEN_264[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_6 = _GEN_265[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_7 = _GEN_266[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_8 = _GEN_267[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_9 = _GEN_268[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued = _GEN_269[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued_partial_agen = _GEN_270[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued_partial_dgen = _GEN_271[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p1_speculative_child = _GEN_272[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p2_speculative_child = _GEN_273[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p1_bypass_hint = _GEN_274[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p2_bypass_hint = _GEN_275[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p3_bypass_hint = _GEN_276[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_dis_col_sel = _GEN_277[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_mask = _GEN_278[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_tag = _GEN_279[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_type = _GEN_280[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sfb = _GEN_281[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_fence = _GEN_282[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_fencei = _GEN_283[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sfence = _GEN_284[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_amo = _GEN_285[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_eret = _GEN_286[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sys_pc2epc = _GEN_287[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_rocc = _GEN_288[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_mov = _GEN_289[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ftq_idx = _GEN_290[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_edge_inst = _GEN_291[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pc_lob = _GEN_292[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_taken = _GEN_293[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_rename = _GEN_294[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_sel = _GEN_295[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pimm = _GEN_296[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_packed = _GEN_297[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_op1_sel = _GEN_298[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_op2_sel = _GEN_299[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ldst = _GEN_300[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_wen = _GEN_301[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren1 = _GEN_302[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren2 = _GEN_303[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren3 = _GEN_304[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_swap12 = _GEN_305[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_swap23 = _GEN_306[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fromint = _GEN_309[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_toint = _GEN_310[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fma = _GEN_312[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_div = _GEN_313[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_sqrt = _GEN_314[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_wflags = _GEN_315[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_vec = _GEN_316[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_rob_idx = _GEN_317[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldq_idx = _GEN_318[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_stq_idx = _GEN_319[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_rxq_idx = _GEN_320[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pdst = _GEN_321[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs1 = _GEN_322[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs2 = _GEN_323[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs3 = _GEN_324[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ppred = _GEN_325[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs1_busy = _GEN_326[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs2_busy = _GEN_327[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs3_busy = _GEN_328[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ppred_busy = _GEN_329[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_stale_pdst = _GEN_330[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_exception = _GEN_331[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_exc_cause = _GEN_332[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_cmd = _GEN_333[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_size = _GEN_334[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_signed = _GEN_335[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_uses_ldq = _GEN_336[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_uses_stq = _GEN_337[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_unique = _GEN_338[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_flush_on_commit = _GEN_339[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_csr_cmd = _GEN_340[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldst_is_rs1 = _GEN_341[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldst = _GEN_342[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs1 = _GEN_343[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs2 = _GEN_344[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs3 = _GEN_345[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_dst_rtype = _GEN_346[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs1_rtype = _GEN_347[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs2_rtype = _GEN_348[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_frs3_en = _GEN_349[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fcn_dw = _GEN_350[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fcn_op = _GEN_351[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_val = _GEN_352[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_rm = _GEN_353[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_typ = _GEN_354[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_pf_if = _GEN_355[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_ae_if = _GEN_356[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_ma_if = _GEN_357[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_bp_debug_if = _GEN_358[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_bp_xcpt_if = _GEN_359[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_fsrc = _GEN_360[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_tsrc = _GEN_361[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] clr_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_5 = s_uop_2_br_mask & _clr_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign clr_uop_out_2_br_mask = _clr_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire wrap_8 = _s_uop_T_4 == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_2_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_2_valid_T_1 = \|_io_core_clr_bsy_2_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_2_valid_T_2 = _io_core_clr_bsy_2_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_2_valid_T_3 = ~_io_core_clr_bsy_2_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_2_valid_T_4 = clr_valid_1_2 & _io_core_clr_bsy_2_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_2_valid_0 = _io_core_clr_bsy_2_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire _GEN_479 = fired_store_agen_0 \| fired_store_retry_0; // @[lsu.scala:321:49, :1122:57] wire _do_st_search_T; // @[lsu.scala:1122:57] assign _do_st_search_T = _GEN_479; // @[lsu.scala:1122:57] wire _lcam_addr_T; // @[lsu.scala:1133:58] assign _lcam_addr_T = _GEN_479; // @[lsu.scala:1122:57, :1133:58] wire _do_st_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85] wire _do_st_search_T_2 = _do_st_search_T & _do_st_search_T_1; // @[lsu.scala:1122:{57,82,85}] wire do_st_search_0 = _do_st_search_T_2; // @[lsu.scala:321:49, :1122:82] wire _do_ld_search_T_1 = _do_ld_search_T \| fired_load_retry_0; // @[lsu.scala:321:49, :1124:{57,84}] wire _do_ld_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85, :1124:111] wire _do_ld_search_T_3 = _do_ld_search_T_1 & _do_ld_search_T_2; // @[lsu.scala:1124:{84,108,111}] wire _do_ld_search_T_4 = _do_ld_search_T_3 \| fired_load_wakeup_0; // @[lsu.scala:321:49, :1124:{108,129}] wire do_ld_search_0 = _do_ld_search_T_4; // @[lsu.scala:321:49, :1124:129] wire _lcam_addr_T_1 = _lcam_addr_T \| fired_load_agen_0; // @[lsu.scala:321:49, :1133:{58,82}] wire _lcam_addr_T_2 = _lcam_addr_T_1 \| fired_load_agen_exec_0; // @[lsu.scala:321:49, :1133:{82,104}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1134:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1135:67] wire [39:0] _lcam_addr_T_3 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:1045:37, :1072:41, :1135:{41,67}] wire [39:0] _lcam_addr_T_4 = _lcam_addr_T_2 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_3; // @[lsu.scala:1133:{37,104}, :1134:45, :1135:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_4; // @[lsu.scala:321:49, :1133:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:321:49, :1138:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_4 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_5 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_6 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_7 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_8 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_9 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_agen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_dgen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_iw_p1_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_iw_p2_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p1_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p2_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p3_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_dis_col_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [15:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_eret = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_eret; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rocc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rocc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_mov = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_mov; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_imm_rename = do_ld_search_0 & mem_ldq_e_0_bits_uop_imm_rename; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_pimm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ldst = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wen = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap12 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap23 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagIn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagOut = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fromint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_toint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fastpipe = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fma = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_div = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_sqrt = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wflags = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_vec = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:321:49, :1138:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_fcn_op = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_fp_rm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_typ = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_0 : _lcam_uop_T_iq_type_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_1 : _lcam_uop_T_iq_type_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_2 : _lcam_uop_T_iq_type_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_3 : _lcam_uop_T_iq_type_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_0 : _lcam_uop_T_fu_code_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_1 : _lcam_uop_T_fu_code_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_2 : _lcam_uop_T_fu_code_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_3 : _lcam_uop_T_fu_code_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_4 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_4 : _lcam_uop_T_fu_code_4; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_5 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_5 : _lcam_uop_T_fu_code_5; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_6 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_6 : _lcam_uop_T_fu_code_6; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_7 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_7 : _lcam_uop_T_fu_code_7; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_8 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_8 : _lcam_uop_T_fu_code_8; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_9 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_9 : _lcam_uop_T_fu_code_9; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued : _lcam_uop_T_iw_issued; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_agen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_agen : _lcam_uop_T_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_dgen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_dgen : _lcam_uop_T_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_iw_p1_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_speculative_child : _lcam_uop_T_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_iw_p2_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_speculative_child : _lcam_uop_T_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p1_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_bypass_hint : _lcam_uop_T_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p2_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_bypass_hint : _lcam_uop_T_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p3_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p3_bypass_hint : _lcam_uop_T_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_dis_col_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_dis_col_sel : _lcam_uop_T_dis_col_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [15:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_br_type : _lcam_uop_T_br_type; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfence : _lcam_uop_T_is_sfence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_eret = do_st_search_0 ? mem_stq_e_0_bits_uop_is_eret : _lcam_uop_T_is_eret; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rocc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rocc : _lcam_uop_T_is_rocc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_mov = do_st_search_0 ? mem_stq_e_0_bits_uop_is_mov : _lcam_uop_T_is_mov; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_imm_rename = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_rename : _lcam_uop_T_imm_rename; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_sel : _lcam_uop_T_imm_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_pimm = do_st_search_0 ? mem_stq_e_0_bits_uop_pimm : _lcam_uop_T_pimm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op1_sel : _lcam_uop_T_op1_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op2_sel : _lcam_uop_T_op2_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ldst : _lcam_uop_T_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wen = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wen : _lcam_uop_T_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren1 : _lcam_uop_T_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren2 : _lcam_uop_T_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren3 : _lcam_uop_T_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap12 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap12 : _lcam_uop_T_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap23 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap23 : _lcam_uop_T_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagIn = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn : _lcam_uop_T_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagOut = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut : _lcam_uop_T_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fromint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fromint : _lcam_uop_T_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_toint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_toint : _lcam_uop_T_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fastpipe = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fastpipe : _lcam_uop_T_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fma = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fma : _lcam_uop_T_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_div = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_div : _lcam_uop_T_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_sqrt = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_sqrt : _lcam_uop_T_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wflags = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wflags : _lcam_uop_T_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_vec = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_vec : _lcam_uop_T_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_cmd : _lcam_uop_T_csr_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_dw : _lcam_uop_T_fcn_dw; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_fcn_op = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_op : _lcam_uop_T_fcn_op; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_fp_rm = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_rm : _lcam_uop_T_fp_rm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_typ = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_typ : _lcam_uop_T_fp_typ; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:321:49, :1137:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:321:49, :1137:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_0 = _lcam_uop_T_1_iq_type_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_1 = _lcam_uop_T_1_iq_type_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_2 = _lcam_uop_T_1_iq_type_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_3 = _lcam_uop_T_1_iq_type_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_0 = _lcam_uop_T_1_fu_code_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_1 = _lcam_uop_T_1_fu_code_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_2 = _lcam_uop_T_1_fu_code_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_3 = _lcam_uop_T_1_fu_code_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_4 = _lcam_uop_T_1_fu_code_4; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_5 = _lcam_uop_T_1_fu_code_5; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_6 = _lcam_uop_T_1_fu_code_6; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_7 = _lcam_uop_T_1_fu_code_7; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_8 = _lcam_uop_T_1_fu_code_8; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_9 = _lcam_uop_T_1_fu_code_9; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued = _lcam_uop_T_1_iw_issued; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_agen = _lcam_uop_T_1_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_dgen = _lcam_uop_T_1_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_iw_p1_speculative_child = _lcam_uop_T_1_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_iw_p2_speculative_child = _lcam_uop_T_1_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p1_bypass_hint = _lcam_uop_T_1_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p2_bypass_hint = _lcam_uop_T_1_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p3_bypass_hint = _lcam_uop_T_1_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_dis_col_sel = _lcam_uop_T_1_dis_col_sel; // @[lsu.scala:321:49, :1137:37] wire [15:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_type = _lcam_uop_T_1_br_type; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfence = _lcam_uop_T_1_is_sfence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_eret = _lcam_uop_T_1_is_eret; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rocc = _lcam_uop_T_1_is_rocc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_mov = _lcam_uop_T_1_is_mov; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_imm_rename = _lcam_uop_T_1_imm_rename; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_imm_sel = _lcam_uop_T_1_imm_sel; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_pimm = _lcam_uop_T_1_pimm; // @[lsu.scala:321:49, :1137:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_op1_sel = _lcam_uop_T_1_op1_sel; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_op2_sel = _lcam_uop_T_1_op2_sel; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ldst = _lcam_uop_T_1_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wen = _lcam_uop_T_1_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren1 = _lcam_uop_T_1_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren2 = _lcam_uop_T_1_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren3 = _lcam_uop_T_1_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap12 = _lcam_uop_T_1_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap23 = _lcam_uop_T_1_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagIn = _lcam_uop_T_1_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagOut = _lcam_uop_T_1_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fromint = _lcam_uop_T_1_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_toint = _lcam_uop_T_1_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fastpipe = _lcam_uop_T_1_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fma = _lcam_uop_T_1_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_div = _lcam_uop_T_1_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_sqrt = _lcam_uop_T_1_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wflags = _lcam_uop_T_1_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_vec = _lcam_uop_T_1_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:321:49, :1137:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_csr_cmd = _lcam_uop_T_1_csr_cmd; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fcn_dw = _lcam_uop_T_1_fcn_dw; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_fcn_op = _lcam_uop_T_1_fcn_op; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_fp_rm = _lcam_uop_T_1_fp_rm; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_typ = _lcam_uop_T_1_fp_typ; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:321:49, :1137:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1951:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:321:49, :1951:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [4:0] lcam_ldq_idx_REG; // @[lsu.scala:1146:58] reg [4:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1147:58] wire [4:0] _lcam_ldq_idx_T_1 = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 5'h0; // @[lsu.scala:321:49, :1147:{26,58}] wire [4:0] _lcam_ldq_idx_T_2 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T_1; // @[lsu.scala:321:49, :1146:{26,58}, :1147:26] wire [4:0] _lcam_ldq_idx_T_3 = _lcam_ldq_idx_T ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_2; // @[lsu.scala:1053:37, :1144:{26,51}, :1146:26] wire [4:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_3; // @[lsu.scala:321:49, :1144:26] wire [4:0] _wb_ldst_forward_e_e_valid_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_uop_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_executed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_succeeded_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_order_fail_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_observed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_forward_std_val_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] reg [4:0] lcam_stq_idx_REG; // @[lsu.scala:1150:56] wire [4:0] _lcam_stq_idx_T = fired_store_retry_0 ? lcam_stq_idx_REG : 5'h0; // @[lsu.scala:321:49, :1150:{26,56}] wire [4:0] _lcam_stq_idx_T_1 = fired_store_agen_0 ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T; // @[lsu.scala:321:49, :1053:37, :1149:26, :1150:26] wire [4:0] lcam_stq_idx_0 = _lcam_stq_idx_T_1; // @[lsu.scala:321:49, :1149:26] wire [31:0] _lcam_younger_load_mask_hi_mask_T = 32'h1 << lcam_ldq_idx_0; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_hi_mask_T_1 = _lcam_younger_load_mask_hi_mask_T[23:0]; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_hi_mask_T_2 = _lcam_younger_load_mask_hi_mask_T_1; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_3 = {1'h0, _lcam_younger_load_mask_hi_mask_T_1[23:1]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_4 = {2'h0, _lcam_younger_load_mask_hi_mask_T_1[23:2]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_5 = {3'h0, _lcam_younger_load_mask_hi_mask_T_1[23:3]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_6 = {4'h0, _lcam_younger_load_mask_hi_mask_T_1[23:4]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_7 = {5'h0, _lcam_younger_load_mask_hi_mask_T_1[23:5]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_8 = {6'h0, _lcam_younger_load_mask_hi_mask_T_1[23:6]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_9 = {7'h0, _lcam_younger_load_mask_hi_mask_T_1[23:7]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_10 = {8'h0, _lcam_younger_load_mask_hi_mask_T_1[23:8]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_11 = {9'h0, _lcam_younger_load_mask_hi_mask_T_1[23:9]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_12 = {10'h0, _lcam_younger_load_mask_hi_mask_T_1[23:10]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_13 = {11'h0, _lcam_younger_load_mask_hi_mask_T_1[23:11]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_14 = {12'h0, _lcam_younger_load_mask_hi_mask_T_1[23:12]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_15 = {13'h0, _lcam_younger_load_mask_hi_mask_T_1[23:13]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_16 = {14'h0, _lcam_younger_load_mask_hi_mask_T_1[23:14]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_17 = {15'h0, _lcam_younger_load_mask_hi_mask_T_1[23:15]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_18 = {16'h0, _lcam_younger_load_mask_hi_mask_T_1[23:16]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_19 = {17'h0, _lcam_younger_load_mask_hi_mask_T_1[23:17]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_20 = {18'h0, _lcam_younger_load_mask_hi_mask_T_1[23:18]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_21 = {19'h0, _lcam_younger_load_mask_hi_mask_T_1[23:19]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_22 = {20'h0, _lcam_younger_load_mask_hi_mask_T_1[23:20]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_23 = {21'h0, _lcam_younger_load_mask_hi_mask_T_1[23:21]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_24 = {22'h0, _lcam_younger_load_mask_hi_mask_T_1[23:22]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_25 = {23'h0, _lcam_younger_load_mask_hi_mask_T_1[23]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_26 = _lcam_younger_load_mask_hi_mask_T_2 \| _lcam_younger_load_mask_hi_mask_T_3; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_27 = _lcam_younger_load_mask_hi_mask_T_26 \| _lcam_younger_load_mask_hi_mask_T_4; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_28 = _lcam_younger_load_mask_hi_mask_T_27 \| _lcam_younger_load_mask_hi_mask_T_5; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_29 = _lcam_younger_load_mask_hi_mask_T_28 \| _lcam_younger_load_mask_hi_mask_T_6; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_30 = _lcam_younger_load_mask_hi_mask_T_29 \| _lcam_younger_load_mask_hi_mask_T_7; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_31 = _lcam_younger_load_mask_hi_mask_T_30 \| _lcam_younger_load_mask_hi_mask_T_8; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_32 = _lcam_younger_load_mask_hi_mask_T_31 \| _lcam_younger_load_mask_hi_mask_T_9; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_33 = _lcam_younger_load_mask_hi_mask_T_32 \| _lcam_younger_load_mask_hi_mask_T_10; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_34 = _lcam_younger_load_mask_hi_mask_T_33 \| _lcam_younger_load_mask_hi_mask_T_11; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_35 = _lcam_younger_load_mask_hi_mask_T_34 \| _lcam_younger_load_mask_hi_mask_T_12; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_36 = _lcam_younger_load_mask_hi_mask_T_35 \| _lcam_younger_load_mask_hi_mask_T_13; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_37 = _lcam_younger_load_mask_hi_mask_T_36 \| _lcam_younger_load_mask_hi_mask_T_14; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_38 = _lcam_younger_load_mask_hi_mask_T_37 \| _lcam_younger_load_mask_hi_mask_T_15; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_39 = _lcam_younger_load_mask_hi_mask_T_38 \| _lcam_younger_load_mask_hi_mask_T_16; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_40 = _lcam_younger_load_mask_hi_mask_T_39 \| _lcam_younger_load_mask_hi_mask_T_17; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_41 = _lcam_younger_load_mask_hi_mask_T_40 \| _lcam_younger_load_mask_hi_mask_T_18; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_42 = _lcam_younger_load_mask_hi_mask_T_41 \| _lcam_younger_load_mask_hi_mask_T_19; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_43 = _lcam_younger_load_mask_hi_mask_T_42 \| _lcam_younger_load_mask_hi_mask_T_20; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_44 = _lcam_younger_load_mask_hi_mask_T_43 \| _lcam_younger_load_mask_hi_mask_T_21; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_45 = _lcam_younger_load_mask_hi_mask_T_44 \| _lcam_younger_load_mask_hi_mask_T_22; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_46 = _lcam_younger_load_mask_hi_mask_T_45 \| _lcam_younger_load_mask_hi_mask_T_23; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_47 = _lcam_younger_load_mask_hi_mask_T_46 \| _lcam_younger_load_mask_hi_mask_T_24; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_48 = _lcam_younger_load_mask_hi_mask_T_47 \| _lcam_younger_load_mask_hi_mask_T_25; // @[util.scala:383:{29,45}] wire [23:0] lcam_younger_load_mask_hi_mask = ~_lcam_younger_load_mask_hi_mask_T_48; // @[util.scala:370:19, :383:45] wire [31:0] _lcam_younger_load_mask_lo_mask_T = 32'h1 << ldq_head; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_lo_mask_T_1 = _lcam_younger_load_mask_lo_mask_T[23:0]; // @[OneHot.scala:58:35] wire [24:0] _lcam_younger_load_mask_lo_mask_T_2 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_3 = _lcam_younger_load_mask_lo_mask_T_2[23:0]; // @[util.scala:394:{30,37}] wire [24:0] _lcam_younger_load_mask_lo_mask_T_4 = {_lcam_younger_load_mask_lo_mask_T_1, 1'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_5 = _lcam_younger_load_mask_lo_mask_T_4[23:0]; // @[util.scala:394:{30,37}] wire [26:0] _lcam_younger_load_mask_lo_mask_T_6 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 2'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_7 = _lcam_younger_load_mask_lo_mask_T_6[23:0]; // @[util.scala:394:{30,37}] wire [26:0] _lcam_younger_load_mask_lo_mask_T_8 = {_lcam_younger_load_mask_lo_mask_T_1, 3'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_9 = _lcam_younger_load_mask_lo_mask_T_8[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_10 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 4'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_11 = _lcam_younger_load_mask_lo_mask_T_10[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_12 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 5'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_13 = _lcam_younger_load_mask_lo_mask_T_12[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_14 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 6'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_15 = _lcam_younger_load_mask_lo_mask_T_14[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_16 = {_lcam_younger_load_mask_lo_mask_T_1, 7'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_17 = _lcam_younger_load_mask_lo_mask_T_16[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_18 = {7'h0, _lcam_younger_load_mask_lo_mask_T_1, 8'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_19 = _lcam_younger_load_mask_lo_mask_T_18[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_20 = {6'h0, _lcam_younger_load_mask_lo_mask_T_1, 9'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_21 = _lcam_younger_load_mask_lo_mask_T_20[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_22 = {5'h0, _lcam_younger_load_mask_lo_mask_T_1, 10'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_23 = _lcam_younger_load_mask_lo_mask_T_22[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_24 = {4'h0, _lcam_younger_load_mask_lo_mask_T_1, 11'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_25 = _lcam_younger_load_mask_lo_mask_T_24[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_26 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 12'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_27 = _lcam_younger_load_mask_lo_mask_T_26[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_28 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 13'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_29 = _lcam_younger_load_mask_lo_mask_T_28[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_30 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 14'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_31 = _lcam_younger_load_mask_lo_mask_T_30[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_32 = {_lcam_younger_load_mask_lo_mask_T_1, 15'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_33 = _lcam_younger_load_mask_lo_mask_T_32[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_34 = {15'h0, _lcam_younger_load_mask_lo_mask_T_1, 16'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_35 = _lcam_younger_load_mask_lo_mask_T_34[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_36 = {14'h0, _lcam_younger_load_mask_lo_mask_T_1, 17'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_37 = _lcam_younger_load_mask_lo_mask_T_36[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_38 = {13'h0, _lcam_younger_load_mask_lo_mask_T_1, 18'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_39 = _lcam_younger_load_mask_lo_mask_T_38[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_40 = {12'h0, _lcam_younger_load_mask_lo_mask_T_1, 19'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_41 = _lcam_younger_load_mask_lo_mask_T_40[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_42 = {11'h0, _lcam_younger_load_mask_lo_mask_T_1, 20'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_43 = _lcam_younger_load_mask_lo_mask_T_42[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_44 = {10'h0, _lcam_younger_load_mask_lo_mask_T_1, 21'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_45 = _lcam_younger_load_mask_lo_mask_T_44[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_46 = {9'h0, _lcam_younger_load_mask_lo_mask_T_1, 22'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_47 = _lcam_younger_load_mask_lo_mask_T_46[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_48 = {8'h0, _lcam_younger_load_mask_lo_mask_T_1, 23'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_49 = _lcam_younger_load_mask_lo_mask_T_48[23:0]; // @[util.scala:394:{30,37}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_50 = _lcam_younger_load_mask_lo_mask_T_3 \| _lcam_younger_load_mask_lo_mask_T_5; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_51 = _lcam_younger_load_mask_lo_mask_T_50 \| _lcam_younger_load_mask_lo_mask_T_7; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_52 = _lcam_younger_load_mask_lo_mask_T_51 \| _lcam_younger_load_mask_lo_mask_T_9; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_53 = _lcam_younger_load_mask_lo_mask_T_52 \| _lcam_younger_load_mask_lo_mask_T_11; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_54 = _lcam_younger_load_mask_lo_mask_T_53 \| _lcam_younger_load_mask_lo_mask_T_13; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_55 = _lcam_younger_load_mask_lo_mask_T_54 \| _lcam_younger_load_mask_lo_mask_T_15; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_56 = _lcam_younger_load_mask_lo_mask_T_55 \| _lcam_younger_load_mask_lo_mask_T_17; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_57 = _lcam_younger_load_mask_lo_mask_T_56 \| _lcam_younger_load_mask_lo_mask_T_19; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_58 = _lcam_younger_load_mask_lo_mask_T_57 \| _lcam_younger_load_mask_lo_mask_T_21; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_59 = _lcam_younger_load_mask_lo_mask_T_58 \| _lcam_younger_load_mask_lo_mask_T_23; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_60 = _lcam_younger_load_mask_lo_mask_T_59 \| _lcam_younger_load_mask_lo_mask_T_25; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_61 = _lcam_younger_load_mask_lo_mask_T_60 \| _lcam_younger_load_mask_lo_mask_T_27; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_62 = _lcam_younger_load_mask_lo_mask_T_61 \| _lcam_younger_load_mask_lo_mask_T_29; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_63 = _lcam_younger_load_mask_lo_mask_T_62 \| _lcam_younger_load_mask_lo_mask_T_31; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_64 = _lcam_younger_load_mask_lo_mask_T_63 \| _lcam_younger_load_mask_lo_mask_T_33; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_65 = _lcam_younger_load_mask_lo_mask_T_64 \| _lcam_younger_load_mask_lo_mask_T_35; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_66 = _lcam_younger_load_mask_lo_mask_T_65 \| _lcam_younger_load_mask_lo_mask_T_37; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_67 = _lcam_younger_load_mask_lo_mask_T_66 \| _lcam_younger_load_mask_lo_mask_T_39; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_68 = _lcam_younger_load_mask_lo_mask_T_67 \| _lcam_younger_load_mask_lo_mask_T_41; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_69 = _lcam_younger_load_mask_lo_mask_T_68 \| _lcam_younger_load_mask_lo_mask_T_43; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_70 = _lcam_younger_load_mask_lo_mask_T_69 \| _lcam_younger_load_mask_lo_mask_T_45; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_71 = _lcam_younger_load_mask_lo_mask_T_70 \| _lcam_younger_load_mask_lo_mask_T_47; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_72 = _lcam_younger_load_mask_lo_mask_T_71 \| _lcam_younger_load_mask_lo_mask_T_49; // @[util.scala:394:{37,54}] wire [23:0] lcam_younger_load_mask_lo_mask = ~_lcam_younger_load_mask_lo_mask_T_72; // @[util.scala:371:19, :394:54] wire _lcam_younger_load_mask_T = lcam_ldq_idx_0 < ldq_head; // @[util.scala:372:11] wire [23:0] _lcam_younger_load_mask_T_1 = lcam_younger_load_mask_hi_mask & lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:27] wire [23:0] _lcam_younger_load_mask_T_2 = lcam_younger_load_mask_hi_mask \| lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:46] wire [23:0] _lcam_younger_load_mask_T_3 = _lcam_younger_load_mask_T ? _lcam_younger_load_mask_T_1 : _lcam_younger_load_mask_T_2; // @[util.scala:372:{8,11,27,46}] wire [23:0] _lcam_younger_load_mask_T_4 = _lcam_younger_load_mask_T_3; // @[util.scala:372:{8,56}] wire [23:0] lcam_younger_load_mask_0 = _lcam_younger_load_mask_T_4; // @[util.scala:372:56] wire _can_forward_T_1 = _can_forward_T \| fired_load_retry_0; // @[lsu.scala:321:49, :1154:{58,85}] wire _can_forward_T_2 = ~mem_tlb_uncacheable_0; // @[lsu.scala:1071:41, :1155:5] wire _can_forward_T_3 = ~mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37, :1156:5] wire _can_forward_T_4 = _can_forward_T_1 ? _can_forward_T_2 : _can_forward_T_3; // @[lsu.scala:1154:{38,85}, :1155:5, :1156:5] wire can_forward_0 = _can_forward_T_4; // @[lsu.scala:321:49, :1154:38] wire kill_forward_0; // @[lsu.scala:1159:30] wire [23:0] _ldst_addr_matches_0_T_2; // @[lsu.scala:1344:79] wire [23:0] ldst_addr_matches_0; // @[lsu.scala:1162:34] wire [23:0] _ldst_forward_matches_0_T_2; // @[lsu.scala:1345:82] wire [23:0] ldst_forward_matches_0; // @[lsu.scala:1164:34] wire [23:0] _stld_prs2_matches_0_T_3; // @[lsu.scala:1346:80] wire [23:0] stld_prs2_matches_0; // @[lsu.scala:1166:34] reg s1_executing_loads_0; // @[lsu.scala:1168:35] reg s1_executing_loads_1; // @[lsu.scala:1168:35] reg s1_executing_loads_2; // @[lsu.scala:1168:35] reg s1_executing_loads_3; // @[lsu.scala:1168:35] reg s1_executing_loads_4; // @[lsu.scala:1168:35] reg s1_executing_loads_5; // @[lsu.scala:1168:35] reg s1_executing_loads_6; // @[lsu.scala:1168:35] reg s1_executing_loads_7; // @[lsu.scala:1168:35] reg s1_executing_loads_8; // @[lsu.scala:1168:35] reg s1_executing_loads_9; // @[lsu.scala:1168:35] reg s1_executing_loads_10; // @[lsu.scala:1168:35] reg s1_executing_loads_11; // @[lsu.scala:1168:35] reg s1_executing_loads_12; // @[lsu.scala:1168:35] reg s1_executing_loads_13; // @[lsu.scala:1168:35] reg s1_executing_loads_14; // @[lsu.scala:1168:35] reg s1_executing_loads_15; // @[lsu.scala:1168:35] reg s1_executing_loads_16; // @[lsu.scala:1168:35] reg s1_executing_loads_17; // @[lsu.scala:1168:35] reg s1_executing_loads_18; // @[lsu.scala:1168:35] reg s1_executing_loads_19; // @[lsu.scala:1168:35] reg s1_executing_loads_20; // @[lsu.scala:1168:35] reg s1_executing_loads_21; // @[lsu.scala:1168:35] reg s1_executing_loads_22; // @[lsu.scala:1168:35] reg s1_executing_loads_23; // @[lsu.scala:1168:35] wire s1_set_execute_0; // @[lsu.scala:1169:36] wire s1_set_execute_1; // @[lsu.scala:1169:36] wire s1_set_execute_2; // @[lsu.scala:1169:36] wire s1_set_execute_3; // @[lsu.scala:1169:36] wire s1_set_execute_4; // @[lsu.scala:1169:36] wire s1_set_execute_5; // @[lsu.scala:1169:36] wire s1_set_execute_6; // @[lsu.scala:1169:36] wire s1_set_execute_7; // @[lsu.scala:1169:36] wire s1_set_execute_8; // @[lsu.scala:1169:36] wire s1_set_execute_9; // @[lsu.scala:1169:36] wire s1_set_execute_10; // @[lsu.scala:1169:36] wire s1_set_execute_11; // @[lsu.scala:1169:36] wire s1_set_execute_12; // @[lsu.scala:1169:36] wire s1_set_execute_13; // @[lsu.scala:1169:36] wire s1_set_execute_14; // @[lsu.scala:1169:36] wire s1_set_execute_15; // @[lsu.scala:1169:36] wire s1_set_execute_16; // @[lsu.scala:1169:36] wire s1_set_execute_17; // @[lsu.scala:1169:36] wire s1_set_execute_18; // @[lsu.scala:1169:36] wire s1_set_execute_19; // @[lsu.scala:1169:36] wire s1_set_execute_20; // @[lsu.scala:1169:36] wire s1_set_execute_21; // @[lsu.scala:1169:36] wire s1_set_execute_22; // @[lsu.scala:1169:36] wire s1_set_execute_23; // @[lsu.scala:1169:36] reg [23:0] wb_ldst_forward_matches_0; // @[lsu.scala:1171:41] wire _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1380:100] wire wb_ldst_forward_valid_0; // @[lsu.scala:1172:38] wire [31:0] wb_ldst_forward_e_out_uop_inst = wb_ldst_forward_e_e_bits_uop_inst; // @[util.scala:109:23] wire [31:0] wb_ldst_forward_e_out_uop_debug_inst = wb_ldst_forward_e_e_bits_uop_debug_inst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rvc = wb_ldst_forward_e_e_bits_uop_is_rvc; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_uop_debug_pc = wb_ldst_forward_e_e_bits_uop_debug_pc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_0 = wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_1 = wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_2 = wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_3 = wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_0 = wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_1 = wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_2 = wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_3 = wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_4 = wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_5 = wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_6 = wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_7 = wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_8 = wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_9 = wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued = wb_ldst_forward_e_e_bits_uop_iw_issued; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_agen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_dgen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_iw_p1_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_iw_p2_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p1_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p2_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p3_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_dis_col_sel = wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_tag = wb_ldst_forward_e_e_bits_uop_br_tag; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_type = wb_ldst_forward_e_e_bits_uop_br_type; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfb = wb_ldst_forward_e_e_bits_uop_is_sfb; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fence = wb_ldst_forward_e_e_bits_uop_is_fence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fencei = wb_ldst_forward_e_e_bits_uop_is_fencei; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfence = wb_ldst_forward_e_e_bits_uop_is_sfence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_amo = wb_ldst_forward_e_e_bits_uop_is_amo; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_eret = wb_ldst_forward_e_e_bits_uop_is_eret; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sys_pc2epc = wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rocc = wb_ldst_forward_e_e_bits_uop_is_rocc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_mov = wb_ldst_forward_e_e_bits_uop_is_mov; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ftq_idx = wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_edge_inst = wb_ldst_forward_e_e_bits_uop_edge_inst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_pc_lob = wb_ldst_forward_e_e_bits_uop_pc_lob; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_taken = wb_ldst_forward_e_e_bits_uop_taken; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_imm_rename = wb_ldst_forward_e_e_bits_uop_imm_rename; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_imm_sel = wb_ldst_forward_e_e_bits_uop_imm_sel; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_pimm = wb_ldst_forward_e_e_bits_uop_pimm; // @[util.scala:109:23] wire [19:0] wb_ldst_forward_e_out_uop_imm_packed = wb_ldst_forward_e_e_bits_uop_imm_packed; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_op1_sel = wb_ldst_forward_e_e_bits_uop_op1_sel; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_op2_sel = wb_ldst_forward_e_e_bits_uop_op2_sel; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ldst = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wen = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren1 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren2 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren3 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap12 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap23 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fromint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_toint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fma = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_div = wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_sqrt = wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wflags = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_vec = wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_rob_idx = wb_ldst_forward_e_e_bits_uop_rob_idx; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ldq_idx = wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_stq_idx = wb_ldst_forward_e_e_bits_uop_stq_idx; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_rxq_idx = wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_pdst = wb_ldst_forward_e_e_bits_uop_pdst; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs1 = wb_ldst_forward_e_e_bits_uop_prs1; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs2 = wb_ldst_forward_e_e_bits_uop_prs2; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs3 = wb_ldst_forward_e_e_bits_uop_prs3; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ppred = wb_ldst_forward_e_e_bits_uop_ppred; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs1_busy = wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs2_busy = wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs3_busy = wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ppred_busy = wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_stale_pdst = wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_exception = wb_ldst_forward_e_e_bits_uop_exception; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_uop_exc_cause = wb_ldst_forward_e_e_bits_uop_exc_cause; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_mem_cmd = wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_mem_size = wb_ldst_forward_e_e_bits_uop_mem_size; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_mem_signed = wb_ldst_forward_e_e_bits_uop_mem_signed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_ldq = wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_stq = wb_ldst_forward_e_e_bits_uop_uses_stq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_unique = wb_ldst_forward_e_e_bits_uop_is_unique; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_flush_on_commit = wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_csr_cmd = wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ldst_is_rs1 = wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_ldst = wb_ldst_forward_e_e_bits_uop_ldst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs1 = wb_ldst_forward_e_e_bits_uop_lrs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs2 = wb_ldst_forward_e_e_bits_uop_lrs2; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs3 = wb_ldst_forward_e_e_bits_uop_lrs3; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dst_rtype = wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs1_rtype = wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs2_rtype = wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_frs3_en = wb_ldst_forward_e_e_bits_uop_frs3_en; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fcn_dw = wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_fcn_op = wb_ldst_forward_e_e_bits_uop_fcn_op; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_val = wb_ldst_forward_e_e_bits_uop_fp_val; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_fp_rm = wb_ldst_forward_e_e_bits_uop_fp_rm; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_typ = wb_ldst_forward_e_e_bits_uop_fp_typ; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_pf_if = wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ae_if = wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ma_if = wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_debug_if = wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_xcpt_if = wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_fsrc = wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_tsrc = wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_valid = wb_ldst_forward_e_e_bits_addr_valid; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_addr_bits = wb_ldst_forward_e_e_bits_addr_bits; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_virtual = wb_ldst_forward_e_e_bits_addr_is_virtual; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_uncacheable = wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[util.scala:109:23] wire wb_ldst_forward_e_out_executed = wb_ldst_forward_e_e_bits_executed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_succeeded = wb_ldst_forward_e_e_bits_succeeded; // @[util.scala:109:23] wire wb_ldst_forward_e_out_order_fail = wb_ldst_forward_e_e_bits_order_fail; // @[util.scala:109:23] wire wb_ldst_forward_e_out_observed = wb_ldst_forward_e_e_bits_observed; // @[util.scala:109:23] wire [23:0] wb_ldst_forward_e_out_st_dep_mask = wb_ldst_forward_e_e_bits_st_dep_mask; // @[util.scala:109:23] wire [7:0] wb_ldst_forward_e_out_ld_byte_mask = wb_ldst_forward_e_e_bits_ld_byte_mask; // @[util.scala:109:23] wire wb_ldst_forward_e_out_forward_std_val = wb_ldst_forward_e_e_bits_forward_std_val; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_forward_stq_idx = wb_ldst_forward_e_e_bits_forward_stq_idx; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_debug_wb_data = wb_ldst_forward_e_e_bits_debug_wb_data; // @[util.scala:109:23] wire [15:0] wb_ldst_forward_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_valid; // @[lsu.scala:233:17] wire [4:0] _wb_ldst_forward_e_e_valid_T_1 = _wb_ldst_forward_e_e_valid_T; assign wb_ldst_forward_e_e_valid = _GEN_25[_wb_ldst_forward_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [4:0] _wb_ldst_forward_e_e_bits_uop_T_1 = _wb_ldst_forward_e_e_bits_uop_T; assign wb_ldst_forward_e_e_bits_uop_inst = _GEN_127[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_inst = _GEN_128[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rvc = _GEN_129[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_pc = _GEN_130[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_0 = _GEN_131[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_1 = _GEN_132[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_2 = _GEN_133[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_3 = _GEN_134[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_0 = _GEN_135[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_1 = _GEN_136[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_2 = _GEN_137[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_3 = _GEN_138[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_4 = _GEN_139[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_5 = _GEN_140[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_6 = _GEN_141[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_7 = _GEN_142[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_8 = _GEN_143[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_9 = _GEN_144[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued = _GEN_145[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dis_col_sel = _GEN_153[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_mask = _GEN_154[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_tag = _GEN_155[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_type = _GEN_156[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfb = _GEN_157[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fence = _GEN_158[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fencei = _GEN_159[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfence = _GEN_160[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_amo = _GEN_161[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_eret = _GEN_162[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rocc = _GEN_164[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_mov = _GEN_165[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ftq_idx = _GEN_166[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_edge_inst = _GEN_167[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pc_lob = _GEN_168[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_taken = _GEN_169[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_rename = _GEN_170[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_sel = _GEN_171[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pimm = _GEN_172[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_packed = _GEN_173[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op1_sel = _GEN_174[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op2_sel = _GEN_175[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_div = _GEN_189[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rob_idx = _GEN_193[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldq_idx = _GEN_194[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stq_idx = _GEN_195[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rxq_idx = _GEN_196[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pdst = _GEN_197[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1 = _GEN_198[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2 = _GEN_199[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3 = _GEN_200[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred = _GEN_201[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1_busy = _GEN_202[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2_busy = _GEN_203[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3_busy = _GEN_204[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred_busy = _GEN_205[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stale_pdst = _GEN_206[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exception = _GEN_207[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exc_cause = _GEN_208[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_cmd = _GEN_209[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_size = _GEN_210[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_signed = _GEN_211[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_ldq = _GEN_212[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_stq = _GEN_213[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_unique = _GEN_214[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_flush_on_commit = _GEN_215[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_csr_cmd = _GEN_216[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst = _GEN_218[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1 = _GEN_219[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2 = _GEN_220[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs3 = _GEN_221[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dst_rtype = _GEN_222[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1_rtype = _GEN_223[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2_rtype = _GEN_224[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_frs3_en = _GEN_225[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_dw = _GEN_226[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_op = _GEN_227[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_val = _GEN_228[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_rm = _GEN_229[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_typ = _GEN_230[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_pf_if = _GEN_231[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ae_if = _GEN_232[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ma_if = _GEN_233[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_debug_if = _GEN_234[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_xcpt_if = _GEN_235[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_fsrc = _GEN_236[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_tsrc = _GEN_237[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_T_1 = _wb_ldst_forward_e_e_bits_addr_T; assign wb_ldst_forward_e_e_bits_addr_valid = _GEN_238[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign wb_ldst_forward_e_e_bits_addr_bits = _GEN_239[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = _wb_ldst_forward_e_e_bits_addr_is_virtual_T; assign wb_ldst_forward_e_e_bits_addr_is_virtual = _GEN_240[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T; assign wb_ldst_forward_e_e_bits_addr_is_uncacheable = _GEN_241[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [4:0] _wb_ldst_forward_e_e_bits_executed_T_1 = _wb_ldst_forward_e_e_bits_executed_T; assign wb_ldst_forward_e_e_bits_executed = _GEN_242[_wb_ldst_forward_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [4:0] _wb_ldst_forward_e_e_bits_succeeded_T_1 = _wb_ldst_forward_e_e_bits_succeeded_T; assign wb_ldst_forward_e_e_bits_succeeded = _GEN_243[_wb_ldst_forward_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [4:0] _wb_ldst_forward_e_e_bits_order_fail_T_1 = _wb_ldst_forward_e_e_bits_order_fail_T; assign wb_ldst_forward_e_e_bits_order_fail = _GEN_244[_wb_ldst_forward_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [4:0] _wb_ldst_forward_e_e_bits_observed_T_1 = _wb_ldst_forward_e_e_bits_observed_T; assign wb_ldst_forward_e_e_bits_observed = _GEN_245[_wb_ldst_forward_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [4:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = _wb_ldst_forward_e_e_bits_st_dep_mask_T; assign wb_ldst_forward_e_e_bits_st_dep_mask = _GEN_246[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [4:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = _wb_ldst_forward_e_e_bits_ld_byte_mask_T; assign wb_ldst_forward_e_e_bits_ld_byte_mask = _GEN_247[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [4:0] _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = _wb_ldst_forward_e_e_bits_forward_std_val_T; assign wb_ldst_forward_e_e_bits_forward_std_val = _GEN_248[_wb_ldst_forward_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [4:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = _wb_ldst_forward_e_e_bits_forward_stq_idx_T; assign wb_ldst_forward_e_e_bits_forward_stq_idx = _GEN_249[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [4:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = _wb_ldst_forward_e_e_bits_debug_wb_data_T; assign wb_ldst_forward_e_e_bits_debug_wb_data = _GEN_250[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [15:0] _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] wb_ldst_forward_e_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _wb_ldst_forward_e_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _wb_ldst_forward_e_out_uop_br_mask_T_1 = wb_ldst_forward_e_e_bits_uop_br_mask & _wb_ldst_forward_e_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign wb_ldst_forward_e_out_uop_br_mask = _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg [31:0] wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_inst = wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:321:49, :1173:55] reg [31:0] wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_debug_inst = wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rvc = wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_uop_debug_pc = wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_0 = wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_1 = wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_2 = wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_3 = wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_0 = wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_1 = wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_2 = wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_3 = wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_4 = wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_5 = wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_6 = wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_7 = wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_8 = wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_9 = wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued = wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_agen = wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_dgen = wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_iw_p1_speculative_child = wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_iw_p2_speculative_child = wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p1_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p2_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p3_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_dis_col_sel = wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:321:49, :1173:55] reg [15:0] wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:1173:55] wire [15:0] wb_ldst_forward_e_0_uop_br_mask = wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_tag = wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_type = wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfb = wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fence = wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fencei = wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfence = wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_amo = wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_eret = wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sys_pc2epc = wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rocc = wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_mov = wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ftq_idx = wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_edge_inst = wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_pc_lob = wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_taken = wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_imm_rename = wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_imm_sel = wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_pimm = wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:321:49, :1173:55] reg [19:0] wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:1173:55] wire [19:0] wb_ldst_forward_e_0_uop_imm_packed = wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_op1_sel = wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_op2_sel = wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ldst = wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wen = wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren1 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren2 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren3 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap12 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap23 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fromint = wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_toint = wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fma = wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_div = wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_sqrt = wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wflags = wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_vec = wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_rob_idx = wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ldq_idx = wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_stq_idx = wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_rxq_idx = wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_pdst = wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs1 = wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs2 = wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs3 = wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ppred = wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs1_busy = wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs2_busy = wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs3_busy = wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ppred_busy = wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_stale_pdst = wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_exception = wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_uop_exc_cause = wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_mem_cmd = wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_mem_size = wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_mem_signed = wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_ldq = wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_stq = wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_unique = wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_flush_on_commit = wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_csr_cmd = wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ldst_is_rs1 = wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_ldst = wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs1 = wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs2 = wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs3 = wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dst_rtype = wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs1_rtype = wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs2_rtype = wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_frs3_en = wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fcn_dw = wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_fcn_op = wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_val = wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_fp_rm = wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_typ = wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_pf_if = wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ae_if = wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ma_if = wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_debug_if = wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_xcpt_if = wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_fsrc = wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_tsrc = wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_valid = wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_addr_bits = wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_virtual = wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_uncacheable = wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_executed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_executed = wb_ldst_forward_e_REG_executed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_succeeded = wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_order_fail = wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_observed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_observed = wb_ldst_forward_e_REG_observed; // @[lsu.scala:321:49, :1173:55] reg [23:0] wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:1173:55] wire [23:0] wb_ldst_forward_e_0_st_dep_mask = wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:321:49, :1173:55] reg [7:0] wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:1173:55] wire [7:0] wb_ldst_forward_e_0_ld_byte_mask = wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_forward_std_val = wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_forward_stq_idx = wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_debug_wb_data = wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:321:49, :1173:55] wire [1:0] size_1 = wb_ldst_forward_e_0_uop_mem_size; // @[AMOALU.scala:11:18] reg [4:0] wb_ldst_forward_ldq_idx_0; // @[lsu.scala:1174:41] reg [39:0] wb_ldst_forward_ld_addr_0; // @[lsu.scala:1175:41] wire [4:0] wb_ldst_forward_stq_idx_0; // @[lsu.scala:1176:38] wire failed_load; // @[lsu.scala:1178:29] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_48 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_51 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_54 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_57 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_60 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_63 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_66 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_69 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_1 = ldq_addr_0_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_64 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_68 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_72 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_76 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_80 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_84 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_88 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_92 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_1 = ldq_addr_0_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_480 = ldq_ld_byte_mask_0 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T; // @[lsu.scala:1197:46] assign _mask_match_T = _GEN_480; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1198:46] assign _mask_overlap_T = _GEN_480; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_1 = _mask_match_T == ldq_ld_byte_mask_0; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_1 = \|_mask_overlap_T; // @[lsu.scala:1198:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:321:49, :1198:62] wire _T_374 = ldq_executed_0 \| ldq_succeeded_0; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _GEN_481 = {19'h0, lcam_stq_idx_0}; // @[util.scala:383:29] wire [23:0] _T_350 = ldq_st_dep_mask_0 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_354 = do_st_search_0 & ldq_valid_0 & ldq_addr_0_valid & _T_374 & ~ldq_addr_is_virtual_0 & _T_350[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T = ldq_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_1 = ldq_forward_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:364:{58,72,78}] wire _T_358 = ~ldq_forward_std_val_0 \| ldq_forward_stq_idx_0 != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:364:72] wire _GEN_482 = _T_354 & _T_358; // @[lsu.scala:1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76] wire _T_364 = do_ld_search_0 & ldq_valid_0 & ldq_addr_0_valid & ~ldq_addr_is_virtual_0 & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older = lcam_younger_load_mask_0[0]; // @[lsu.scala:321:49, :1237:58] wire _T_383 = ldq_executed_0 & (ldq_succeeded_0 \| ldq_will_succeed_0); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_483 = lcam_ldq_idx_0 == 5'h0; // @[lsu.scala:321:49, :1254:48] wire _GEN_484 = lcam_ldq_idx_0 == 5'h1; // @[lsu.scala:321:49, :1254:48] wire _GEN_485 = lcam_ldq_idx_0 == 5'h2; // @[lsu.scala:321:49, :1254:48] wire _GEN_486 = lcam_ldq_idx_0 == 5'h3; // @[lsu.scala:321:49, :1254:48] wire _GEN_487 = lcam_ldq_idx_0 == 5'h4; // @[lsu.scala:321:49, :1254:48] wire _GEN_488 = lcam_ldq_idx_0 == 5'h5; // @[lsu.scala:321:49, :1254:48] wire _GEN_489 = lcam_ldq_idx_0 == 5'h6; // @[lsu.scala:321:49, :1254:48] wire _GEN_490 = lcam_ldq_idx_0 == 5'h7; // @[lsu.scala:321:49, :1254:48] wire _GEN_491 = lcam_ldq_idx_0 == 5'h8; // @[lsu.scala:321:49, :1254:48] wire _GEN_492 = lcam_ldq_idx_0 == 5'h9; // @[lsu.scala:321:49, :1254:48] wire _GEN_493 = lcam_ldq_idx_0 == 5'hA; // @[lsu.scala:321:49, :1254:48] wire _GEN_494 = lcam_ldq_idx_0 == 5'hB; // @[lsu.scala:321:49, :1254:48] wire _GEN_495 = lcam_ldq_idx_0 == 5'hC; // @[lsu.scala:321:49, :1254:48] wire _GEN_496 = lcam_ldq_idx_0 == 5'hD; // @[lsu.scala:321:49, :1254:48] wire _GEN_497 = lcam_ldq_idx_0 == 5'hE; // @[lsu.scala:321:49, :1254:48] wire _GEN_498 = lcam_ldq_idx_0 == 5'hF; // @[lsu.scala:321:49, :1254:48] wire _GEN_499 = lcam_ldq_idx_0 == 5'h10; // @[lsu.scala:321:49, :1254:48] wire _GEN_500 = lcam_ldq_idx_0 == 5'h11; // @[lsu.scala:321:49, :1254:48] wire _GEN_501 = lcam_ldq_idx_0 == 5'h12; // @[lsu.scala:321:49, :1254:48] wire _GEN_502 = lcam_ldq_idx_0 == 5'h13; // @[lsu.scala:321:49, :1254:48] wire _GEN_503 = lcam_ldq_idx_0 == 5'h14; // @[lsu.scala:321:49, :1254:48] wire _GEN_504 = lcam_ldq_idx_0 == 5'h15; // @[lsu.scala:321:49, :1254:48] wire _GEN_505 = lcam_ldq_idx_0 == 5'h16; // @[lsu.scala:321:49, :1254:48] wire _GEN_506 = lcam_ldq_idx_0 == 5'h17; // @[lsu.scala:321:49, :1254:48] reg REG_1; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_4 = ldq_addr_1_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_5 = ldq_addr_1_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_507 = ldq_ld_byte_mask_1 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_2; // @[lsu.scala:1197:46] assign _mask_match_T_2 = _GEN_507; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1198:46] assign _mask_overlap_T_2 = _GEN_507; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_3 = _mask_match_T_2 == ldq_ld_byte_mask_1; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_3 = \|_mask_overlap_T_2; // @[lsu.scala:1198:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:321:49, :1198:62] wire _T_426 = ldq_executed_1 \| ldq_succeeded_1; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_402 = ldq_st_dep_mask_1 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_4 = ldq_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_5 = ldq_forward_stq_idx_1 < l_uop_1_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < l_uop_1_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:364:{58,72,78}] wire _GEN_508 = do_st_search_0 & ldq_valid_1 & ldq_addr_1_valid & _T_426 & ~ldq_addr_is_virtual_1 & _T_402[0] & dword_addr_matches_1_0 & mask_overlap_1_0 & (~ldq_forward_std_val_1 \| ldq_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1); // @[util.scala:364:72] wire _T_416 = do_ld_search_0 & ldq_valid_1 & ldq_addr_1_valid & ~ldq_addr_is_virtual_1 & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_1 = lcam_younger_load_mask_0[1]; // @[lsu.scala:321:49, :1237:58] wire _T_435 = ldq_executed_1 & (ldq_succeeded_1 \| ldq_will_succeed_1); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_509 = searcher_is_older_1 \| _GEN_484; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_2; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_7 = ldq_addr_2_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_9 = ldq_addr_2_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_510 = ldq_ld_byte_mask_2 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_4; // @[lsu.scala:1197:46] assign _mask_match_T_4 = _GEN_510; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1198:46] assign _mask_overlap_T_4 = _GEN_510; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_5 = _mask_match_T_4 == ldq_ld_byte_mask_2; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_5 = \|_mask_overlap_T_4; // @[lsu.scala:1198:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:321:49, :1198:62] wire _T_478 = ldq_executed_2 \| ldq_succeeded_2; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_454 = ldq_st_dep_mask_2 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_458 = do_st_search_0 & ldq_valid_2 & ldq_addr_2_valid & _T_478 & ~ldq_addr_is_virtual_2 & _T_454[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_8 = ldq_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_9 = ldq_forward_stq_idx_2 < l_uop_2_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < l_uop_2_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:364:{58,72,78}] wire _T_462 = ~ldq_forward_std_val_2 \| ldq_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:364:72] wire _GEN_511 = _T_458 ? _T_462 \| _GEN_508 \| _GEN_482 : _GEN_508 \| _GEN_482; // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_468 = do_ld_search_0 & ldq_valid_2 & ldq_addr_2_valid & ~ldq_addr_is_virtual_2 & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_2 = lcam_younger_load_mask_0[2]; // @[lsu.scala:321:49, :1237:58] wire _T_487 = ldq_executed_2 & (ldq_succeeded_2 \| ldq_will_succeed_2); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_512 = searcher_is_older_2 \| _GEN_485; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_3; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_10 = ldq_addr_3_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_13 = ldq_addr_3_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_513 = ldq_ld_byte_mask_3 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_6; // @[lsu.scala:1197:46] assign _mask_match_T_6 = _GEN_513; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1198:46] assign _mask_overlap_T_6 = _GEN_513; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_7 = _mask_match_T_6 == ldq_ld_byte_mask_3; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_7 = \|_mask_overlap_T_6; // @[lsu.scala:1198:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:321:49, :1198:62] wire _T_530 = ldq_executed_3 \| ldq_succeeded_3; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_506 = ldq_st_dep_mask_3 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_12 = ldq_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_13 = ldq_forward_stq_idx_3 < l_uop_3_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < l_uop_3_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:364:{58,72,78}] wire _GEN_514 = do_st_search_0 & ldq_valid_3 & ldq_addr_3_valid & _T_530 & ~ldq_addr_is_virtual_3 & _T_506[0] & dword_addr_matches_3_0 & mask_overlap_3_0 & (~ldq_forward_std_val_3 \| ldq_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3); // @[util.scala:364:72] wire _T_520 = do_ld_search_0 & ldq_valid_3 & ldq_addr_3_valid & ~ldq_addr_is_virtual_3 & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_3 = lcam_younger_load_mask_0[3]; // @[lsu.scala:321:49, :1237:58] wire _T_539 = ldq_executed_3 & (ldq_succeeded_3 \| ldq_will_succeed_3); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_515 = searcher_is_older_3 \| _GEN_486; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_4; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_13 = ldq_addr_4_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_17 = ldq_addr_4_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_516 = ldq_ld_byte_mask_4 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_8; // @[lsu.scala:1197:46] assign _mask_match_T_8 = _GEN_516; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1198:46] assign _mask_overlap_T_8 = _GEN_516; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_9 = _mask_match_T_8 == ldq_ld_byte_mask_4; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_9 = \|_mask_overlap_T_8; // @[lsu.scala:1198:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:321:49, :1198:62] wire _T_582 = ldq_executed_4 \| ldq_succeeded_4; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_558 = ldq_st_dep_mask_4 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_562 = do_st_search_0 & ldq_valid_4 & ldq_addr_4_valid & _T_582 & ~ldq_addr_is_virtual_4 & _T_558[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_16 = ldq_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_17 = ldq_forward_stq_idx_4 < l_uop_4_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < l_uop_4_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:364:{58,72,78}] wire _T_566 = ~ldq_forward_std_val_4 \| ldq_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:364:72] wire _GEN_517 = _T_562 ? _T_566 \| _GEN_514 \| _GEN_511 : _GEN_514 \| _GEN_511; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_572 = do_ld_search_0 & ldq_valid_4 & ldq_addr_4_valid & ~ldq_addr_is_virtual_4 & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_4 = lcam_younger_load_mask_0[4]; // @[lsu.scala:321:49, :1237:58] wire _T_591 = ldq_executed_4 & (ldq_succeeded_4 \| ldq_will_succeed_4); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_518 = searcher_is_older_4 \| _GEN_487; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_5; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_16 = ldq_addr_5_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_21 = ldq_addr_5_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_519 = ldq_ld_byte_mask_5 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_10; // @[lsu.scala:1197:46] assign _mask_match_T_10 = _GEN_519; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1198:46] assign _mask_overlap_T_10 = _GEN_519; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_11 = _mask_match_T_10 == ldq_ld_byte_mask_5; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_11 = \|_mask_overlap_T_10; // @[lsu.scala:1198:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:321:49, :1198:62] wire _T_634 = ldq_executed_5 \| ldq_succeeded_5; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_610 = ldq_st_dep_mask_5 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_20 = ldq_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_21 = ldq_forward_stq_idx_5 < l_uop_5_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < l_uop_5_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:364:{58,72,78}] wire _GEN_520 = do_st_search_0 & ldq_valid_5 & ldq_addr_5_valid & _T_634 & ~ldq_addr_is_virtual_5 & _T_610[0] & dword_addr_matches_5_0 & mask_overlap_5_0 & (~ldq_forward_std_val_5 \| ldq_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5); // @[util.scala:364:72] wire _T_624 = do_ld_search_0 & ldq_valid_5 & ldq_addr_5_valid & ~ldq_addr_is_virtual_5 & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_5 = lcam_younger_load_mask_0[5]; // @[lsu.scala:321:49, :1237:58] wire _T_643 = ldq_executed_5 & (ldq_succeeded_5 \| ldq_will_succeed_5); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_521 = searcher_is_older_5 \| _GEN_488; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_6; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_19 = ldq_addr_6_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_25 = ldq_addr_6_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_522 = ldq_ld_byte_mask_6 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_12; // @[lsu.scala:1197:46] assign _mask_match_T_12 = _GEN_522; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1198:46] assign _mask_overlap_T_12 = _GEN_522; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_13 = _mask_match_T_12 == ldq_ld_byte_mask_6; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_13 = \|_mask_overlap_T_12; // @[lsu.scala:1198:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:321:49, :1198:62] wire _T_686 = ldq_executed_6 \| ldq_succeeded_6; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_662 = ldq_st_dep_mask_6 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_666 = do_st_search_0 & ldq_valid_6 & ldq_addr_6_valid & _T_686 & ~ldq_addr_is_virtual_6 & _T_662[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_24 = ldq_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_25 = ldq_forward_stq_idx_6 < l_uop_6_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < l_uop_6_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:364:{58,72,78}] wire _T_670 = ~ldq_forward_std_val_6 \| ldq_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:364:72] wire _GEN_523 = _T_666 ? _T_670 \| _GEN_520 \| _GEN_517 : _GEN_520 \| _GEN_517; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_676 = do_ld_search_0 & ldq_valid_6 & ldq_addr_6_valid & ~ldq_addr_is_virtual_6 & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_6 = lcam_younger_load_mask_0[6]; // @[lsu.scala:321:49, :1237:58] wire _T_695 = ldq_executed_6 & (ldq_succeeded_6 \| ldq_will_succeed_6); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_524 = searcher_is_older_6 \| _GEN_489; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_7; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_22 = ldq_addr_7_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_29 = ldq_addr_7_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_525 = ldq_ld_byte_mask_7 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_14; // @[lsu.scala:1197:46] assign _mask_match_T_14 = _GEN_525; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1198:46] assign _mask_overlap_T_14 = _GEN_525; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_15 = _mask_match_T_14 == ldq_ld_byte_mask_7; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_15 = \|_mask_overlap_T_14; // @[lsu.scala:1198:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:321:49, :1198:62] wire _T_738 = ldq_executed_7 \| ldq_succeeded_7; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_714 = ldq_st_dep_mask_7 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_28 = ldq_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_29 = ldq_forward_stq_idx_7 < l_uop_7_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < l_uop_7_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:364:{58,72,78}] wire _GEN_526 = do_st_search_0 & ldq_valid_7 & ldq_addr_7_valid & _T_738 & ~ldq_addr_is_virtual_7 & _T_714[0] & dword_addr_matches_7_0 & mask_overlap_7_0 & (~ldq_forward_std_val_7 \| ldq_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7); // @[util.scala:364:72] wire _T_728 = do_ld_search_0 & ldq_valid_7 & ldq_addr_7_valid & ~ldq_addr_is_virtual_7 & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_7 = lcam_younger_load_mask_0[7]; // @[lsu.scala:321:49, :1237:58] wire _T_747 = ldq_executed_7 & (ldq_succeeded_7 \| ldq_will_succeed_7); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_527 = searcher_is_older_7 \| _GEN_490; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_8; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_25 = ldq_addr_8_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_33 = ldq_addr_8_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_528 = ldq_ld_byte_mask_8 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_16; // @[lsu.scala:1197:46] assign _mask_match_T_16 = _GEN_528; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1198:46] assign _mask_overlap_T_16 = _GEN_528; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_17 = _mask_match_T_16 == ldq_ld_byte_mask_8; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_17 = \|_mask_overlap_T_16; // @[lsu.scala:1198:{46,62}] wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:321:49, :1198:62] wire _T_790 = ldq_executed_8 \| ldq_succeeded_8; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_766 = ldq_st_dep_mask_8 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_770 = do_st_search_0 & ldq_valid_8 & ldq_addr_8_valid & _T_790 & ~ldq_addr_is_virtual_8 & _T_766[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_32 = ldq_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_33 = ldq_forward_stq_idx_8 < l_uop_8_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < l_uop_8_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:364:{58,72,78}] wire _T_774 = ~ldq_forward_std_val_8 \| ldq_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:364:72] wire _GEN_529 = _T_770 ? _T_774 \| _GEN_526 \| _GEN_523 : _GEN_526 \| _GEN_523; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_780 = do_ld_search_0 & ldq_valid_8 & ldq_addr_8_valid & ~ldq_addr_is_virtual_8 & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_8 = lcam_younger_load_mask_0[8]; // @[lsu.scala:321:49, :1237:58] wire _T_799 = ldq_executed_8 & (ldq_succeeded_8 \| ldq_will_succeed_8); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_530 = searcher_is_older_8 \| _GEN_491; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_9; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_28 = ldq_addr_9_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_37 = ldq_addr_9_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_531 = ldq_ld_byte_mask_9 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_18; // @[lsu.scala:1197:46] assign _mask_match_T_18 = _GEN_531; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1198:46] assign _mask_overlap_T_18 = _GEN_531; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_19 = _mask_match_T_18 == ldq_ld_byte_mask_9; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_19 = \|_mask_overlap_T_18; // @[lsu.scala:1198:{46,62}] wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:321:49, :1198:62] wire _T_842 = ldq_executed_9 \| ldq_succeeded_9; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_818 = ldq_st_dep_mask_9 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_36 = ldq_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_37 = ldq_forward_stq_idx_9 < l_uop_9_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < l_uop_9_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:364:{58,72,78}] wire _GEN_532 = do_st_search_0 & ldq_valid_9 & ldq_addr_9_valid & _T_842 & ~ldq_addr_is_virtual_9 & _T_818[0] & dword_addr_matches_9_0 & mask_overlap_9_0 & (~ldq_forward_std_val_9 \| ldq_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9); // @[util.scala:364:72] wire _T_832 = do_ld_search_0 & ldq_valid_9 & ldq_addr_9_valid & ~ldq_addr_is_virtual_9 & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_9 = lcam_younger_load_mask_0[9]; // @[lsu.scala:321:49, :1237:58] wire _T_851 = ldq_executed_9 & (ldq_succeeded_9 \| ldq_will_succeed_9); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_533 = searcher_is_older_9 \| _GEN_492; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_10; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_31 = ldq_addr_10_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_41 = ldq_addr_10_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_534 = ldq_ld_byte_mask_10 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_20; // @[lsu.scala:1197:46] assign _mask_match_T_20 = _GEN_534; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1198:46] assign _mask_overlap_T_20 = _GEN_534; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_21 = _mask_match_T_20 == ldq_ld_byte_mask_10; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_21 = \|_mask_overlap_T_20; // @[lsu.scala:1198:{46,62}] wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:321:49, :1198:62] wire _T_894 = ldq_executed_10 \| ldq_succeeded_10; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_870 = ldq_st_dep_mask_10 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_874 = do_st_search_0 & ldq_valid_10 & ldq_addr_10_valid & _T_894 & ~ldq_addr_is_virtual_10 & _T_870[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_40 = ldq_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_41 = ldq_forward_stq_idx_10 < l_uop_10_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < l_uop_10_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:364:{58,72,78}] wire _T_878 = ~ldq_forward_std_val_10 \| ldq_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:364:72] wire _GEN_535 = _T_874 ? _T_878 \| _GEN_532 \| _GEN_529 : _GEN_532 \| _GEN_529; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_884 = do_ld_search_0 & ldq_valid_10 & ldq_addr_10_valid & ~ldq_addr_is_virtual_10 & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_10 = lcam_younger_load_mask_0[10]; // @[lsu.scala:321:49, :1237:58] wire _T_903 = ldq_executed_10 & (ldq_succeeded_10 \| ldq_will_succeed_10); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_536 = searcher_is_older_10 \| _GEN_493; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_11; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_34 = ldq_addr_11_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_45 = ldq_addr_11_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_537 = ldq_ld_byte_mask_11 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_22; // @[lsu.scala:1197:46] assign _mask_match_T_22 = _GEN_537; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1198:46] assign _mask_overlap_T_22 = _GEN_537; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_23 = _mask_match_T_22 == ldq_ld_byte_mask_11; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_23 = \|_mask_overlap_T_22; // @[lsu.scala:1198:{46,62}] wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:321:49, :1198:62] wire _T_946 = ldq_executed_11 \| ldq_succeeded_11; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_922 = ldq_st_dep_mask_11 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_44 = ldq_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_45 = ldq_forward_stq_idx_11 < l_uop_11_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < l_uop_11_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:364:{58,72,78}] wire _GEN_538 = do_st_search_0 & ldq_valid_11 & ldq_addr_11_valid & _T_946 & ~ldq_addr_is_virtual_11 & _T_922[0] & dword_addr_matches_11_0 & mask_overlap_11_0 & (~ldq_forward_std_val_11 \| ldq_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11); // @[util.scala:364:72] wire _T_936 = do_ld_search_0 & ldq_valid_11 & ldq_addr_11_valid & ~ldq_addr_is_virtual_11 & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_11 = lcam_younger_load_mask_0[11]; // @[lsu.scala:321:49, :1237:58] wire _T_955 = ldq_executed_11 & (ldq_succeeded_11 \| ldq_will_succeed_11); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_539 = searcher_is_older_11 \| _GEN_494; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_12; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_37 = ldq_addr_12_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_49 = ldq_addr_12_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_540 = ldq_ld_byte_mask_12 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_24; // @[lsu.scala:1197:46] assign _mask_match_T_24 = _GEN_540; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1198:46] assign _mask_overlap_T_24 = _GEN_540; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_25 = _mask_match_T_24 == ldq_ld_byte_mask_12; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_25 = \|_mask_overlap_T_24; // @[lsu.scala:1198:{46,62}] wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:321:49, :1198:62] wire _T_998 = ldq_executed_12 \| ldq_succeeded_12; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_974 = ldq_st_dep_mask_12 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_978 = do_st_search_0 & ldq_valid_12 & ldq_addr_12_valid & _T_998 & ~ldq_addr_is_virtual_12 & _T_974[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_48 = ldq_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_49 = ldq_forward_stq_idx_12 < l_uop_12_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < l_uop_12_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:364:{58,72,78}] wire _T_982 = ~ldq_forward_std_val_12 \| ldq_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:364:72] wire _GEN_541 = _T_978 ? _T_982 \| _GEN_538 \| _GEN_535 : _GEN_538 \| _GEN_535; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_988 = do_ld_search_0 & ldq_valid_12 & ldq_addr_12_valid & ~ldq_addr_is_virtual_12 & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_12 = lcam_younger_load_mask_0[12]; // @[lsu.scala:321:49, :1237:58] wire _T_1007 = ldq_executed_12 & (ldq_succeeded_12 \| ldq_will_succeed_12); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_542 = searcher_is_older_12 \| _GEN_495; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_13; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_40 = ldq_addr_13_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_53 = ldq_addr_13_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_543 = ldq_ld_byte_mask_13 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_26; // @[lsu.scala:1197:46] assign _mask_match_T_26 = _GEN_543; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1198:46] assign _mask_overlap_T_26 = _GEN_543; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_27 = _mask_match_T_26 == ldq_ld_byte_mask_13; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_27 = \|_mask_overlap_T_26; // @[lsu.scala:1198:{46,62}] wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:321:49, :1198:62] wire _T_1050 = ldq_executed_13 \| ldq_succeeded_13; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1026 = ldq_st_dep_mask_13 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_52 = ldq_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_53 = ldq_forward_stq_idx_13 < l_uop_13_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < l_uop_13_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:364:{58,72,78}] wire _GEN_544 = do_st_search_0 & ldq_valid_13 & ldq_addr_13_valid & _T_1050 & ~ldq_addr_is_virtual_13 & _T_1026[0] & dword_addr_matches_13_0 & mask_overlap_13_0 & (~ldq_forward_std_val_13 \| ldq_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13); // @[util.scala:364:72] wire _T_1040 = do_ld_search_0 & ldq_valid_13 & ldq_addr_13_valid & ~ldq_addr_is_virtual_13 & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_13 = lcam_younger_load_mask_0[13]; // @[lsu.scala:321:49, :1237:58] wire _T_1059 = ldq_executed_13 & (ldq_succeeded_13 \| ldq_will_succeed_13); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_545 = searcher_is_older_13 \| _GEN_496; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_14; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_43 = ldq_addr_14_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_57 = ldq_addr_14_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_546 = ldq_ld_byte_mask_14 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_28; // @[lsu.scala:1197:46] assign _mask_match_T_28 = _GEN_546; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1198:46] assign _mask_overlap_T_28 = _GEN_546; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_29 = _mask_match_T_28 == ldq_ld_byte_mask_14; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_29 = \|_mask_overlap_T_28; // @[lsu.scala:1198:{46,62}] wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:321:49, :1198:62] wire _T_1102 = ldq_executed_14 \| ldq_succeeded_14; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1078 = ldq_st_dep_mask_14 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1082 = do_st_search_0 & ldq_valid_14 & ldq_addr_14_valid & _T_1102 & ~ldq_addr_is_virtual_14 & _T_1078[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_56 = ldq_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_57 = ldq_forward_stq_idx_14 < l_uop_14_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < l_uop_14_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:364:{58,72,78}] wire _T_1086 = ~ldq_forward_std_val_14 \| ldq_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:364:72] wire _GEN_547 = _T_1082 ? _T_1086 \| _GEN_544 \| _GEN_541 : _GEN_544 \| _GEN_541; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1092 = do_ld_search_0 & ldq_valid_14 & ldq_addr_14_valid & ~ldq_addr_is_virtual_14 & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_14 = lcam_younger_load_mask_0[14]; // @[lsu.scala:321:49, :1237:58] wire _T_1111 = ldq_executed_14 & (ldq_succeeded_14 \| ldq_will_succeed_14); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_548 = searcher_is_older_14 \| _GEN_497; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_15; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_46 = ldq_addr_15_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_61 = ldq_addr_15_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_549 = ldq_ld_byte_mask_15 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_30; // @[lsu.scala:1197:46] assign _mask_match_T_30 = _GEN_549; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1198:46] assign _mask_overlap_T_30 = _GEN_549; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_31 = _mask_match_T_30 == ldq_ld_byte_mask_15; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_31 = \|_mask_overlap_T_30; // @[lsu.scala:1198:{46,62}] wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:321:49, :1198:62] wire _T_1154 = ldq_executed_15 \| ldq_succeeded_15; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1130 = ldq_st_dep_mask_15 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_60 = ldq_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_61 = ldq_forward_stq_idx_15 < l_uop_15_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < l_uop_15_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:364:{58,72,78}] wire _GEN_550 = do_st_search_0 & ldq_valid_15 & ldq_addr_15_valid & _T_1154 & ~ldq_addr_is_virtual_15 & _T_1130[0] & dword_addr_matches_15_0 & mask_overlap_15_0 & (~ldq_forward_std_val_15 \| ldq_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15); // @[util.scala:364:72] wire _T_1144 = do_ld_search_0 & ldq_valid_15 & ldq_addr_15_valid & ~ldq_addr_is_virtual_15 & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_15 = lcam_younger_load_mask_0[15]; // @[lsu.scala:321:49, :1237:58] wire _T_1163 = ldq_executed_15 & (ldq_succeeded_15 \| ldq_will_succeed_15); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_551 = searcher_is_older_15 \| _GEN_498; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_16; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_49 = ldq_addr_16_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_50 = _block_addr_matches_T_48 == _block_addr_matches_T_49; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_16_0 = _block_addr_matches_T_50; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_65 = ldq_addr_16_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_67 = block_addr_matches_16_0 & _dword_addr_matches_T_66; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_16_0 = _dword_addr_matches_T_67; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_552 = ldq_ld_byte_mask_16 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_32; // @[lsu.scala:1197:46] assign _mask_match_T_32 = _GEN_552; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_32; // @[lsu.scala:1198:46] assign _mask_overlap_T_32 = _GEN_552; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_33 = _mask_match_T_32 == ldq_ld_byte_mask_16; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_16_0 = _mask_match_T_33; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_33 = \|_mask_overlap_T_32; // @[lsu.scala:1198:{46,62}] wire mask_overlap_16_0 = _mask_overlap_T_33; // @[lsu.scala:321:49, :1198:62] wire _T_1206 = ldq_executed_16 \| ldq_succeeded_16; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1182 = ldq_st_dep_mask_16 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1186 = do_st_search_0 & ldq_valid_16 & ldq_addr_16_valid & _T_1206 & ~ldq_addr_is_virtual_16 & _T_1182[0] & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_64 = ldq_forward_stq_idx_16 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_65 = ldq_forward_stq_idx_16 < l_uop_16_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < l_uop_16_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:364:{58,72,78}] wire _T_1190 = ~ldq_forward_std_val_16 \| ldq_forward_stq_idx_16 != lcam_stq_idx_0 & forwarded_is_older_16; // @[util.scala:364:72] wire _GEN_553 = _T_1186 ? _T_1190 \| _GEN_550 \| _GEN_547 : _GEN_550 \| _GEN_547; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1196 = do_ld_search_0 & ldq_valid_16 & ldq_addr_16_valid & ~ldq_addr_is_virtual_16 & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_16 = lcam_younger_load_mask_0[16]; // @[lsu.scala:321:49, :1237:58] wire _T_1215 = ldq_executed_16 & (ldq_succeeded_16 \| ldq_will_succeed_16); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_554 = searcher_is_older_16 \| _GEN_499; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_17; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_52 = ldq_addr_17_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_53 = _block_addr_matches_T_51 == _block_addr_matches_T_52; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_17_0 = _block_addr_matches_T_53; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_69 = ldq_addr_17_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_71 = block_addr_matches_17_0 & _dword_addr_matches_T_70; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_17_0 = _dword_addr_matches_T_71; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_555 = ldq_ld_byte_mask_17 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_34; // @[lsu.scala:1197:46] assign _mask_match_T_34 = _GEN_555; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_34; // @[lsu.scala:1198:46] assign _mask_overlap_T_34 = _GEN_555; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_35 = _mask_match_T_34 == ldq_ld_byte_mask_17; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_17_0 = _mask_match_T_35; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_35 = \|_mask_overlap_T_34; // @[lsu.scala:1198:{46,62}] wire mask_overlap_17_0 = _mask_overlap_T_35; // @[lsu.scala:321:49, :1198:62] wire _T_1258 = ldq_executed_17 \| ldq_succeeded_17; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1234 = ldq_st_dep_mask_17 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_68 = ldq_forward_stq_idx_17 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_69 = ldq_forward_stq_idx_17 < l_uop_17_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_70 = _forwarded_is_older_T_68 ^ _forwarded_is_older_T_69; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_71 = lcam_stq_idx_0 < l_uop_17_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_17 = _forwarded_is_older_T_70 ^ _forwarded_is_older_T_71; // @[util.scala:364:{58,72,78}] wire _GEN_556 = do_st_search_0 & ldq_valid_17 & ldq_addr_17_valid & _T_1258 & ~ldq_addr_is_virtual_17 & _T_1234[0] & dword_addr_matches_17_0 & mask_overlap_17_0 & (~ldq_forward_std_val_17 \| ldq_forward_stq_idx_17 != lcam_stq_idx_0 & forwarded_is_older_17); // @[util.scala:364:72] wire _T_1248 = do_ld_search_0 & ldq_valid_17 & ldq_addr_17_valid & ~ldq_addr_is_virtual_17 & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_17 = lcam_younger_load_mask_0[17]; // @[lsu.scala:321:49, :1237:58] wire _T_1267 = ldq_executed_17 & (ldq_succeeded_17 \| ldq_will_succeed_17); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_557 = searcher_is_older_17 \| _GEN_500; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_18; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_55 = ldq_addr_18_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_56 = _block_addr_matches_T_54 == _block_addr_matches_T_55; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_18_0 = _block_addr_matches_T_56; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_73 = ldq_addr_18_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 == _dword_addr_matches_T_73; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_75 = block_addr_matches_18_0 & _dword_addr_matches_T_74; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_18_0 = _dword_addr_matches_T_75; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_558 = ldq_ld_byte_mask_18 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_36; // @[lsu.scala:1197:46] assign _mask_match_T_36 = _GEN_558; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_36; // @[lsu.scala:1198:46] assign _mask_overlap_T_36 = _GEN_558; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_37 = _mask_match_T_36 == ldq_ld_byte_mask_18; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_18_0 = _mask_match_T_37; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_37 = \|_mask_overlap_T_36; // @[lsu.scala:1198:{46,62}] wire mask_overlap_18_0 = _mask_overlap_T_37; // @[lsu.scala:321:49, :1198:62] wire _T_1310 = ldq_executed_18 \| ldq_succeeded_18; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1286 = ldq_st_dep_mask_18 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1290 = do_st_search_0 & ldq_valid_18 & ldq_addr_18_valid & _T_1310 & ~ldq_addr_is_virtual_18 & _T_1286[0] & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_72 = ldq_forward_stq_idx_18 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_73 = ldq_forward_stq_idx_18 < l_uop_18_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_74 = _forwarded_is_older_T_72 ^ _forwarded_is_older_T_73; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_75 = lcam_stq_idx_0 < l_uop_18_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_18 = _forwarded_is_older_T_74 ^ _forwarded_is_older_T_75; // @[util.scala:364:{58,72,78}] wire _T_1294 = ~ldq_forward_std_val_18 \| ldq_forward_stq_idx_18 != lcam_stq_idx_0 & forwarded_is_older_18; // @[util.scala:364:72] wire _GEN_559 = _T_1290 ? _T_1294 \| _GEN_556 \| _GEN_553 : _GEN_556 \| _GEN_553; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1300 = do_ld_search_0 & ldq_valid_18 & ldq_addr_18_valid & ~ldq_addr_is_virtual_18 & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_18 = lcam_younger_load_mask_0[18]; // @[lsu.scala:321:49, :1237:58] wire _T_1319 = ldq_executed_18 & (ldq_succeeded_18 \| ldq_will_succeed_18); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_560 = searcher_is_older_18 \| _GEN_501; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_19; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_58 = ldq_addr_19_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_59 = _block_addr_matches_T_57 == _block_addr_matches_T_58; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_19_0 = _block_addr_matches_T_59; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_77 = ldq_addr_19_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_79 = block_addr_matches_19_0 & _dword_addr_matches_T_78; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_19_0 = _dword_addr_matches_T_79; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_561 = ldq_ld_byte_mask_19 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_38; // @[lsu.scala:1197:46] assign _mask_match_T_38 = _GEN_561; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_38; // @[lsu.scala:1198:46] assign _mask_overlap_T_38 = _GEN_561; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_39 = _mask_match_T_38 == ldq_ld_byte_mask_19; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_19_0 = _mask_match_T_39; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_39 = \|_mask_overlap_T_38; // @[lsu.scala:1198:{46,62}] wire mask_overlap_19_0 = _mask_overlap_T_39; // @[lsu.scala:321:49, :1198:62] wire _T_1362 = ldq_executed_19 \| ldq_succeeded_19; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1338 = ldq_st_dep_mask_19 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_76 = ldq_forward_stq_idx_19 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_77 = ldq_forward_stq_idx_19 < l_uop_19_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_78 = _forwarded_is_older_T_76 ^ _forwarded_is_older_T_77; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_79 = lcam_stq_idx_0 < l_uop_19_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_19 = _forwarded_is_older_T_78 ^ _forwarded_is_older_T_79; // @[util.scala:364:{58,72,78}] wire _GEN_562 = do_st_search_0 & ldq_valid_19 & ldq_addr_19_valid & _T_1362 & ~ldq_addr_is_virtual_19 & _T_1338[0] & dword_addr_matches_19_0 & mask_overlap_19_0 & (~ldq_forward_std_val_19 \| ldq_forward_stq_idx_19 != lcam_stq_idx_0 & forwarded_is_older_19); // @[util.scala:364:72] wire _T_1352 = do_ld_search_0 & ldq_valid_19 & ldq_addr_19_valid & ~ldq_addr_is_virtual_19 & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_19 = lcam_younger_load_mask_0[19]; // @[lsu.scala:321:49, :1237:58] wire _T_1371 = ldq_executed_19 & (ldq_succeeded_19 \| ldq_will_succeed_19); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_563 = searcher_is_older_19 \| _GEN_502; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_20; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_61 = ldq_addr_20_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_62 = _block_addr_matches_T_60 == _block_addr_matches_T_61; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_20_0 = _block_addr_matches_T_62; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_81 = ldq_addr_20_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_82 = _dword_addr_matches_T_80 == _dword_addr_matches_T_81; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_83 = block_addr_matches_20_0 & _dword_addr_matches_T_82; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_20_0 = _dword_addr_matches_T_83; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_564 = ldq_ld_byte_mask_20 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_40; // @[lsu.scala:1197:46] assign _mask_match_T_40 = _GEN_564; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_40; // @[lsu.scala:1198:46] assign _mask_overlap_T_40 = _GEN_564; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_41 = _mask_match_T_40 == ldq_ld_byte_mask_20; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_20_0 = _mask_match_T_41; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_41 = \|_mask_overlap_T_40; // @[lsu.scala:1198:{46,62}] wire mask_overlap_20_0 = _mask_overlap_T_41; // @[lsu.scala:321:49, :1198:62] wire _T_1414 = ldq_executed_20 \| ldq_succeeded_20; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1390 = ldq_st_dep_mask_20 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1394 = do_st_search_0 & ldq_valid_20 & ldq_addr_20_valid & _T_1414 & ~ldq_addr_is_virtual_20 & _T_1390[0] & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_80 = ldq_forward_stq_idx_20 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_81 = ldq_forward_stq_idx_20 < l_uop_20_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_82 = _forwarded_is_older_T_80 ^ _forwarded_is_older_T_81; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_83 = lcam_stq_idx_0 < l_uop_20_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_20 = _forwarded_is_older_T_82 ^ _forwarded_is_older_T_83; // @[util.scala:364:{58,72,78}] wire _T_1398 = ~ldq_forward_std_val_20 \| ldq_forward_stq_idx_20 != lcam_stq_idx_0 & forwarded_is_older_20; // @[util.scala:364:72] wire _GEN_565 = _T_1394 ? _T_1398 \| _GEN_562 \| _GEN_559 : _GEN_562 \| _GEN_559; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1404 = do_ld_search_0 & ldq_valid_20 & ldq_addr_20_valid & ~ldq_addr_is_virtual_20 & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_20 = lcam_younger_load_mask_0[20]; // @[lsu.scala:321:49, :1237:58] wire _T_1423 = ldq_executed_20 & (ldq_succeeded_20 \| ldq_will_succeed_20); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_566 = searcher_is_older_20 \| _GEN_503; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_21; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_64 = ldq_addr_21_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_65 = _block_addr_matches_T_63 == _block_addr_matches_T_64; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_21_0 = _block_addr_matches_T_65; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_85 = ldq_addr_21_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_86 = _dword_addr_matches_T_84 == _dword_addr_matches_T_85; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_87 = block_addr_matches_21_0 & _dword_addr_matches_T_86; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_21_0 = _dword_addr_matches_T_87; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_567 = ldq_ld_byte_mask_21 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_42; // @[lsu.scala:1197:46] assign _mask_match_T_42 = _GEN_567; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_42; // @[lsu.scala:1198:46] assign _mask_overlap_T_42 = _GEN_567; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_43 = _mask_match_T_42 == ldq_ld_byte_mask_21; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_21_0 = _mask_match_T_43; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_43 = \|_mask_overlap_T_42; // @[lsu.scala:1198:{46,62}] wire mask_overlap_21_0 = _mask_overlap_T_43; // @[lsu.scala:321:49, :1198:62] wire _T_1466 = ldq_executed_21 \| ldq_succeeded_21; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1442 = ldq_st_dep_mask_21 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_84 = ldq_forward_stq_idx_21 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_85 = ldq_forward_stq_idx_21 < l_uop_21_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_86 = _forwarded_is_older_T_84 ^ _forwarded_is_older_T_85; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_87 = lcam_stq_idx_0 < l_uop_21_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_21 = _forwarded_is_older_T_86 ^ _forwarded_is_older_T_87; // @[util.scala:364:{58,72,78}] wire _GEN_568 = do_st_search_0 & ldq_valid_21 & ldq_addr_21_valid & _T_1466 & ~ldq_addr_is_virtual_21 & _T_1442[0] & dword_addr_matches_21_0 & mask_overlap_21_0 & (~ldq_forward_std_val_21 \| ldq_forward_stq_idx_21 != lcam_stq_idx_0 & forwarded_is_older_21); // @[util.scala:364:72] wire _T_1456 = do_ld_search_0 & ldq_valid_21 & ldq_addr_21_valid & ~ldq_addr_is_virtual_21 & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_21 = lcam_younger_load_mask_0[21]; // @[lsu.scala:321:49, :1237:58] wire _T_1475 = ldq_executed_21 & (ldq_succeeded_21 \| ldq_will_succeed_21); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_569 = searcher_is_older_21 \| _GEN_504; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_22; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_67 = ldq_addr_22_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_68 = _block_addr_matches_T_66 == _block_addr_matches_T_67; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_22_0 = _block_addr_matches_T_68; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_89 = ldq_addr_22_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_90 = _dword_addr_matches_T_88 == _dword_addr_matches_T_89; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_91 = block_addr_matches_22_0 & _dword_addr_matches_T_90; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_22_0 = _dword_addr_matches_T_91; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_570 = ldq_ld_byte_mask_22 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_44; // @[lsu.scala:1197:46] assign _mask_match_T_44 = _GEN_570; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_44; // @[lsu.scala:1198:46] assign _mask_overlap_T_44 = _GEN_570; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_45 = _mask_match_T_44 == ldq_ld_byte_mask_22; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_22_0 = _mask_match_T_45; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_45 = \|_mask_overlap_T_44; // @[lsu.scala:1198:{46,62}] wire mask_overlap_22_0 = _mask_overlap_T_45; // @[lsu.scala:321:49, :1198:62] wire _T_1518 = ldq_executed_22 \| ldq_succeeded_22; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1494 = ldq_st_dep_mask_22 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1498 = do_st_search_0 & ldq_valid_22 & ldq_addr_22_valid & _T_1518 & ~ldq_addr_is_virtual_22 & _T_1494[0] & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_88 = ldq_forward_stq_idx_22 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_89 = ldq_forward_stq_idx_22 < l_uop_22_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_90 = _forwarded_is_older_T_88 ^ _forwarded_is_older_T_89; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_91 = lcam_stq_idx_0 < l_uop_22_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_22 = _forwarded_is_older_T_90 ^ _forwarded_is_older_T_91; // @[util.scala:364:{58,72,78}] wire _T_1502 = ~ldq_forward_std_val_22 \| ldq_forward_stq_idx_22 != lcam_stq_idx_0 & forwarded_is_older_22; // @[util.scala:364:72] wire _T_1508 = do_ld_search_0 & ldq_valid_22 & ldq_addr_22_valid & ~ldq_addr_is_virtual_22 & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_22 = lcam_younger_load_mask_0[22]; // @[lsu.scala:321:49, :1237:58] wire _T_1527 = ldq_executed_22 & (ldq_succeeded_22 \| ldq_will_succeed_22); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_571 = searcher_is_older_22 \| _GEN_505; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_23; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_70 = ldq_addr_23_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_71 = _block_addr_matches_T_69 == _block_addr_matches_T_70; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_23_0 = _block_addr_matches_T_71; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_93 = ldq_addr_23_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_94 = _dword_addr_matches_T_92 == _dword_addr_matches_T_93; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_95 = block_addr_matches_23_0 & _dword_addr_matches_T_94; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_23_0 = _dword_addr_matches_T_95; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_572 = ldq_ld_byte_mask_23 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_46; // @[lsu.scala:1197:46] assign _mask_match_T_46 = _GEN_572; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_46; // @[lsu.scala:1198:46] assign _mask_overlap_T_46 = _GEN_572; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_47 = _mask_match_T_46 == ldq_ld_byte_mask_23; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_23_0 = _mask_match_T_47; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_47 = \|_mask_overlap_T_46; // @[lsu.scala:1198:{46,62}] wire mask_overlap_23_0 = _mask_overlap_T_47; // @[lsu.scala:321:49, :1198:62] wire _T_1570 = ldq_executed_23 \| ldq_succeeded_23; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1546 = ldq_st_dep_mask_23 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_92 = ldq_forward_stq_idx_23 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_93 = ldq_forward_stq_idx_23 < l_uop_23_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_94 = _forwarded_is_older_T_92 ^ _forwarded_is_older_T_93; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_95 = lcam_stq_idx_0 < l_uop_23_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_23 = _forwarded_is_older_T_94 ^ _forwarded_is_older_T_95; // @[util.scala:364:{58,72,78}] wire _GEN_573 = do_st_search_0 & ldq_valid_23 & ldq_addr_23_valid & _T_1570 & ~ldq_addr_is_virtual_23 & _T_1546[0] & dword_addr_matches_23_0 & mask_overlap_23_0 & (~ldq_forward_std_val_23 \| ldq_forward_stq_idx_23 != lcam_stq_idx_0 & forwarded_is_older_23); // @[util.scala:364:72] wire _T_1560 = do_ld_search_0 & ldq_valid_23 & ldq_addr_23_valid & ~ldq_addr_is_virtual_23 & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_23 = lcam_younger_load_mask_0[23]; // @[lsu.scala:321:49, :1237:58] wire _T_1579 = ldq_executed_23 & (ldq_succeeded_23 \| ldq_will_succeed_23); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_574 = searcher_is_older_23 \| _GEN_506; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] wire _GEN_575 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_483)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_483)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_483)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_483)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_483)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_483)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_483)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_483)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_483)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_483)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_483)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_483)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_483)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_483)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_483)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_483)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_483)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_483)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_483)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_483)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_483)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_483)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_483)) & s1_executing_loads_0; // @[lsu.scala:1168:35, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_576 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_484)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_484)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_484)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_484)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_484)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_484)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_484)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_484)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_484)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_484)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_484)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_484)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_484)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_484)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_484)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_484)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_484)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_484)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_484)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_484)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_484)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_484)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_484)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_484)) & s1_executing_loads_1; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_577 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_485)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_485)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_485)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_485)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_485)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_485)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_485)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_485)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_485)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_485)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_485)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_485)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_485)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_485)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_485)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_485)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_485)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_485)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_485)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_485)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_485)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_485)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_485)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_485)) & s1_executing_loads_2; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_578 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_486)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_486)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_486)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_486)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_486)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_486)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_486)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_486)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_486)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_486)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_486)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_486)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_486)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_486)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_486)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_486)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_486)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_486)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_486)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_486)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_486)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_486)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_486)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_486)) & s1_executing_loads_3; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_579 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_487)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_487)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_487)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_487)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_487)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_487)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_487)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_487)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_487)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_487)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_487)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_487)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_487)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_487)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_487)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_487)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_487)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_487)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_487)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_487)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_487)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_487)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_487)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_487)) & s1_executing_loads_4; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_580 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_488)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_488)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_488)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_488)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_488)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_488)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_488)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_488)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_488)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_488)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_488)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_488)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_488)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_488)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_488)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_488)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_488)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_488)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_488)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_488)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_488)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_488)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_488)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_488)) & s1_executing_loads_5; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_581 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_489)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_489)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_489)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_489)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_489)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_489)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_489)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_489)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_489)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_489)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_489)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_489)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_489)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_489)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_489)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_489)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_489)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_489)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_489)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_489)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_489)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_489)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_489)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_489)) & s1_executing_loads_6; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_582 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_490)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_490)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_490)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_490)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_490)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_490)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_490)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_490)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_490)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_490)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_490)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_490)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_490)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_490)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_490)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_490)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_490)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_490)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_490)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_490)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_490)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_490)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_490)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_490)) & s1_executing_loads_7; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_583 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_491)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_491)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_491)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_491)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_491)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_491)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_491)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_491)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_491)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_491)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_491)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_491)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_491)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_491)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_491)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_491)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_491)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_491)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_491)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_491)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_491)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_491)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_491)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_491)) & s1_executing_loads_8; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_584 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_492)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_492)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_492)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_492)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_492)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_492)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_492)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_492)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_492)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_492)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_492)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_492)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_492)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_492)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_492)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_492)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_492)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_492)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_492)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_492)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_492)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_492)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_492)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_492)) & s1_executing_loads_9; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_585 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_493)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_493)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_493)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_493)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_493)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_493)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_493)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_493)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_493)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_493)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_493)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_493)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_493)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_493)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_493)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_493)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_493)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_493)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_493)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_493)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_493)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_493)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_493)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_493)) & s1_executing_loads_10; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_586 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_494)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_494)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_494)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_494)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_494)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_494)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_494)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_494)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_494)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_494)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_494)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_494)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_494)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_494)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_494)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_494)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_494)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_494)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_494)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_494)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_494)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_494)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_494)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_494)) & s1_executing_loads_11; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_587 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_495)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_495)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_495)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_495)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_495)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_495)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_495)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_495)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_495)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_495)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_495)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_495)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_495)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_495)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_495)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_495)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_495)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_495)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_495)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_495)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_495)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_495)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_495)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_495)) & s1_executing_loads_12; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_588 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_496)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_496)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_496)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_496)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_496)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_496)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_496)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_496)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_496)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_496)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_496)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_496)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_496)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_496)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_496)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_496)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_496)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_496)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_496)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_496)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_496)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_496)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_496)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_496)) & s1_executing_loads_13; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_589 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_497)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_497)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_497)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_497)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_497)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_497)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_497)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_497)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_497)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_497)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_497)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_497)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_497)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_497)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_497)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_497)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_497)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_497)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_497)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_497)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_497)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_497)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_497)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_497)) & s1_executing_loads_14; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_590 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_498)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_498)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_498)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_498)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_498)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_498)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_498)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_498)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_498)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_498)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_498)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_498)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_498)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_498)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_498)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_498)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_498)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_498)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_498)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_498)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_498)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_498)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_498)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_498)) & s1_executing_loads_15; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_591 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_499)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_499)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_499)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_499)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_499)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_499)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_499)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_499)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_499)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_499)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_499)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_499)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_499)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_499)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_499)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_499)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_499)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_499)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_499)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_499)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_499)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_499)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_499)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_499)) & s1_executing_loads_16; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_592 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_500)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_500)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_500)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_500)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_500)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_500)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_500)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_500)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_500)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_500)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_500)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_500)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_500)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_500)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_500)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_500)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_500)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_500)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_500)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_500)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_500)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_500)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_500)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_500)) & s1_executing_loads_17; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_593 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_501)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_501)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_501)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_501)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_501)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_501)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_501)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_501)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_501)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_501)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_501)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_501)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_501)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_501)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_501)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_501)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_501)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_501)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_501)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_501)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_501)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_501)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_501)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_501)) & s1_executing_loads_18; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_594 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_502)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_502)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_502)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_502)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_502)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_502)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_502)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_502)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_502)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_502)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_502)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_502)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_502)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_502)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_502)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_502)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_502)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_502)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_502)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_502)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_502)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_502)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_502)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_502)) & s1_executing_loads_19; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_595 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_503)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_503)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_503)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_503)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_503)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_503)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_503)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_503)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_503)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_503)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_503)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_503)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_503)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_503)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_503)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_503)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_503)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_503)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_503)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_503)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_503)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_503)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_503)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_503)) & s1_executing_loads_20; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_596 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_504)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_504)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_504)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_504)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_504)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_504)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_504)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_504)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_504)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_504)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_504)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_504)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_504)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_504)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_504)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_504)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_504)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_504)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_504)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_504)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_504)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_504)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_504)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_504)) & s1_executing_loads_21; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_597 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_505)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_505)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_505)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_505)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_505)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_505)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_505)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_505)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_505)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_505)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_505)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_505)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_505)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_505)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_505)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_505)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_505)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_505)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_505)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_505)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_505)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_505)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_505)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_505)) & s1_executing_loads_22; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_598 = (~_T_1560 \| _GEN_574 \| ~(~_T_1579 & _GEN_506)) & (~_T_1508 \| _GEN_571 \| ~(~_T_1527 & _GEN_506)) & (~_T_1456 \| _GEN_569 \| ~(~_T_1475 & _GEN_506)) & (~_T_1404 \| _GEN_566 \| ~(~_T_1423 & _GEN_506)) & (~_T_1352 \| _GEN_563 \| ~(~_T_1371 & _GEN_506)) & (~_T_1300 \| _GEN_560 \| ~(~_T_1319 & _GEN_506)) & (~_T_1248 \| _GEN_557 \| ~(~_T_1267 & _GEN_506)) & (~_T_1196 \| _GEN_554 \| ~(~_T_1215 & _GEN_506)) & (~_T_1144 \| _GEN_551 \| ~(~_T_1163 & _GEN_506)) & (~_T_1092 \| _GEN_548 \| ~(~_T_1111 & _GEN_506)) & (~_T_1040 \| _GEN_545 \| ~(~_T_1059 & _GEN_506)) & (~_T_988 \| _GEN_542 \| ~(~_T_1007 & _GEN_506)) & (~_T_936 \| _GEN_539 \| ~(~_T_955 & _GEN_506)) & (~_T_884 \| _GEN_536 \| ~(~_T_903 & _GEN_506)) & (~_T_832 \| _GEN_533 \| ~(~_T_851 & _GEN_506)) & (~_T_780 \| _GEN_530 \| ~(~_T_799 & _GEN_506)) & (~_T_728 \| _GEN_527 \| ~(~_T_747 & _GEN_506)) & (~_T_676 \| _GEN_524 \| ~(~_T_695 & _GEN_506)) & (~_T_624 \| _GEN_521 \| ~(~_T_643 & _GEN_506)) & (~_T_572 \| _GEN_518 \| ~(~_T_591 & _GEN_506)) & (~_T_520 \| _GEN_515 \| ~(~_T_539 & _GEN_506)) & (~_T_468 \| _GEN_512 \| ~(~_T_487 & _GEN_506)) & (~_T_416 \| _GEN_509 \| ~(~_T_435 & _GEN_506)) & (~_T_364 \| searcher_is_older \| ~((\|lcam_ldq_idx_0) & ~_T_383 & _GEN_506)) & s1_executing_loads_23; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_24; // @[lsu.scala:1255:26] wire _GEN_599 = _T_1560 & ~_GEN_574 & ~_T_1579 & REG_24 & ~fired_load_agen_0 \| _T_1508 & ~_GEN_571 & ~_T_1527 & REG_23 & ~fired_load_agen_0 \| _T_1456 & ~_GEN_569 & ~_T_1475 & REG_22 & ~fired_load_agen_0 \| _T_1404 & ~_GEN_566 & ~_T_1423 & REG_21 & ~fired_load_agen_0 \| _T_1352 & ~_GEN_563 & ~_T_1371 & REG_20 & ~fired_load_agen_0 \| _T_1300 & ~_GEN_560 & ~_T_1319 & REG_19 & ~fired_load_agen_0 \| _T_1248 & ~_GEN_557 & ~_T_1267 & REG_18 & ~fired_load_agen_0 \| _T_1196 & ~_GEN_554 & ~_T_1215 & REG_17 & ~fired_load_agen_0 \| _T_1144 & ~_GEN_551 & ~_T_1163 & REG_16 & ~fired_load_agen_0 \| _T_1092 & ~_GEN_548 & ~_T_1111 & REG_15 & ~fired_load_agen_0 \| _T_1040 & ~_GEN_545 & ~_T_1059 & REG_14 & ~fired_load_agen_0 \| _T_988 & ~_GEN_542 & ~_T_1007 & REG_13 & ~fired_load_agen_0 \| _T_936 & ~_GEN_539 & ~_T_955 & REG_12 & ~fired_load_agen_0 \| _T_884 & ~_GEN_536 & ~_T_903 & REG_11 & ~fired_load_agen_0 \| _T_832 & ~_GEN_533 & ~_T_851 & REG_10 & ~fired_load_agen_0 \| _T_780 & ~_GEN_530 & ~_T_799 & REG_9 & ~fired_load_agen_0 \| _T_728 & ~_GEN_527 & ~_T_747 & REG_8 & ~fired_load_agen_0 \| _T_676 & ~_GEN_524 & ~_T_695 & REG_7 & ~fired_load_agen_0 \| _T_624 & ~_GEN_521 & ~_T_643 & REG_6 & ~fired_load_agen_0 \| _T_572 & ~_GEN_518 & ~_T_591 & REG_5 & ~fired_load_agen_0 \| _T_520 & ~_GEN_515 & ~_T_539 & REG_4 & ~fired_load_agen_0 \| _T_468 & ~_GEN_512 & ~_T_487 & REG_3 & ~fired_load_agen_0 \| _T_416 & ~_GEN_509 & ~_T_435 & REG_2 & ~fired_load_agen_0 \| _T_364 & ~searcher_is_older & (\|lcam_ldq_idx_0) & ~_T_383 & REG_1 & ~fired_load_agen_0 \| io_dmem_s1_kill_0_REG; // @[lsu.scala:321:49, :893:{24,34}, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1255:{26,61,64,85}, :1256:48] wire _GEN_600 = _T_1560 & ~_GEN_574 & ~_T_1579 \| _T_1508 & ~_GEN_571 & ~_T_1527 \| _T_1456 & ~_GEN_569 & ~_T_1475 \| _T_1404 & ~_GEN_566 & ~_T_1423 \| _T_1352 & ~_GEN_563 & ~_T_1371 \| _T_1300 & ~_GEN_560 & ~_T_1319 \| _T_1248 & ~_GEN_557 & ~_T_1267 \| _T_1196 & ~_GEN_554 & ~_T_1215 \| _T_1144 & ~_GEN_551 & ~_T_1163 \| _T_1092 & ~_GEN_548 & ~_T_1111 \| _T_1040 & ~_GEN_545 & ~_T_1059 \| _T_988 & ~_GEN_542 & ~_T_1007 \| _T_936 & ~_GEN_539 & ~_T_955 \| _T_884 & ~_GEN_536 & ~_T_903 \| _T_832 & ~_GEN_533 & ~_T_851 \| _T_780 & ~_GEN_530 & ~_T_799 \| _T_728 & ~_GEN_527 & ~_T_747 \| _T_676 & ~_GEN_524 & ~_T_695 \| _T_624 & ~_GEN_521 & ~_T_643 \| _T_572 & ~_GEN_518 & ~_T_591 \| _T_520 & ~_GEN_515 & ~_T_539 \| _T_468 & ~_GEN_512 & ~_T_487 \| _T_416 & ~_GEN_509 & ~_T_435 \| _T_364 & ~searcher_is_older & (\|lcam_ldq_idx_0) & ~_T_383; // @[lsu.scala:321:49, :893:24, :1159:30, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1258:48] wire [36:0] _nack_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51] wire [36:0] _forward_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51, :1289:54] wire [36:0] _nack_dword_addr_matches_T_1 = io_dmem_nack_0_bits_addr_0[39:3]; // @[lsu.scala:211:7, :1270:89] wire nack_dword_addr_matches = _nack_dword_addr_matches_T == _nack_dword_addr_matches_T_1; // @[lsu.scala:1270:{51,57,89}] wire [7:0] nack_mask; // @[lsu.scala:1951:22] wire _nack_mask_mask_T = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h0; // @[lsu.scala:211:7, :1953:26] wire [2:0] _nack_mask_mask_T_1 = io_dmem_nack_0_bits_addr_0[2:0]; // @[lsu.scala:211:7, :1953:55] wire [14:0] _nack_mask_mask_T_2 = 15'h1 << _nack_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _nack_mask_mask_T_3 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h1; // @[lsu.scala:211:7, :1954:26] wire [1:0] _nack_mask_mask_T_4 = io_dmem_nack_0_bits_addr_0[2:1]; // @[lsu.scala:211:7, :1954:56] wire [2:0] _nack_mask_mask_T_5 = {_nack_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _nack_mask_mask_T_6 = 15'h3 << _nack_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _nack_mask_mask_T_7 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h2; // @[lsu.scala:211:7, :1955:26] wire _nack_mask_mask_T_8 = io_dmem_nack_0_bits_addr_0[2]; // @[lsu.scala:211:7, :1955:46] wire [7:0] _nack_mask_mask_T_9 = _nack_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _nack_mask_mask_T_10 = &io_dmem_nack_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1956:26] wire [7:0] _nack_mask_mask_T_12 = _nack_mask_mask_T_7 ? _nack_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_13 = _nack_mask_mask_T_3 ? _nack_mask_mask_T_6 : {7'h0, _nack_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_14 = _nack_mask_mask_T ? _nack_mask_mask_T_2 : _nack_mask_mask_T_13; // @[Mux.scala:126:16] assign nack_mask = _nack_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _nack_mask_overlap_T = nack_mask & lcam_mask_0; // @[lsu.scala:321:49, :1272:42, :1951:22] wire nack_mask_overlap = \|_nack_mask_overlap_T; // @[lsu.scala:1272:{42,58}] wire _T_1596 = do_ld_search_0 & io_dmem_nack_0_valid_0 & io_dmem_nack_0_bits_uop_uses_ldq_0 & nack_dword_addr_matches & nack_mask_overlap & (io_dmem_nack_0_bits_uop_ldq_idx_0 < lcam_ldq_idx_0 ^ io_dmem_nack_0_bits_uop_ldq_idx_0 < ldq_head ^ _lcam_younger_load_mask_T); // @[util.scala:364:{52,58,64,72}, :372:11] wire _GEN_601 = _T_1596 & _GEN_483; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_602 = _T_1596 & _GEN_484; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_603 = _T_1596 & _GEN_485; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_604 = _T_1596 & _GEN_486; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_605 = _T_1596 & _GEN_487; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_606 = _T_1596 & _GEN_488; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_607 = _T_1596 & _GEN_489; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_608 = _T_1596 & _GEN_490; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_609 = _T_1596 & _GEN_491; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_610 = _T_1596 & _GEN_492; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_611 = _T_1596 & _GEN_493; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_612 = _T_1596 & _GEN_494; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_613 = _T_1596 & _GEN_495; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_614 = _T_1596 & _GEN_496; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_615 = _T_1596 & _GEN_497; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_616 = _T_1596 & _GEN_498; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_617 = _T_1596 & _GEN_499; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_618 = _T_1596 & _GEN_500; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_619 = _T_1596 & _GEN_501; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_620 = _T_1596 & _GEN_502; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_621 = _T_1596 & _GEN_503; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_622 = _T_1596 & _GEN_504; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_623 = _T_1596 & _GEN_505; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_624 = _T_1596 & _GEN_506; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] reg REG_25; // @[lsu.scala:1280:22] wire _GEN_625 = _T_1596 & REG_25 & ~fired_load_agen_0; // @[lsu.scala:321:49, :1235:37, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1280:{22,57,60,81}, :1281:30] wire [36:0] _forward_dword_addr_matches_T_1 = wb_ldst_forward_ld_addr_0[39:3]; // @[lsu.scala:1175:41, :1289:91] wire forward_dword_addr_matches = _forward_dword_addr_matches_T == _forward_dword_addr_matches_T_1; // @[lsu.scala:1289:{54,59,91}] wire [7:0] forward_mask; // @[lsu.scala:1951:22] wire _forward_mask_mask_T = wb_ldst_forward_e_0_uop_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _forward_mask_mask_T_1 = wb_ldst_forward_ld_addr_0[2:0]; // @[lsu.scala:1175:41, :1953:55] wire [14:0] _forward_mask_mask_T_2 = 15'h1 << _forward_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _forward_mask_mask_T_3 = wb_ldst_forward_e_0_uop_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _forward_mask_mask_T_4 = wb_ldst_forward_ld_addr_0[2:1]; // @[lsu.scala:1175:41, :1954:56] wire [2:0] _forward_mask_mask_T_5 = {_forward_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _forward_mask_mask_T_6 = 15'h3 << _forward_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _forward_mask_mask_T_7 = wb_ldst_forward_e_0_uop_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _forward_mask_mask_T_8 = wb_ldst_forward_ld_addr_0[2]; // @[lsu.scala:1175:41, :1955:46] wire _iresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [7:0] _forward_mask_mask_T_9 = _forward_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _forward_mask_mask_T_10 = &wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _forward_mask_mask_T_12 = _forward_mask_mask_T_7 ? _forward_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_13 = _forward_mask_mask_T_3 ? _forward_mask_mask_T_6 : {7'h0, _forward_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_14 = _forward_mask_mask_T ? _forward_mask_mask_T_2 : _forward_mask_mask_T_13; // @[Mux.scala:126:16] assign forward_mask = _forward_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _forward_mask_overlap_T = forward_mask & lcam_mask_0; // @[lsu.scala:321:49, :1291:48, :1951:22] wire forward_mask_overlap = \|_forward_mask_overlap_T; // @[lsu.scala:1291:{48,64}] wire _T_1612 = do_ld_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & wb_ldst_forward_e_0_observed & (lcam_ldq_idx_0 < wb_ldst_forward_ldq_idx_0 ^ _lcam_younger_load_mask_T ^ wb_ldst_forward_ldq_idx_0 < ldq_head); // @[util.scala:364:{52,58,72,78}, :372:11] wire _GEN_626 = wb_ldst_forward_ldq_idx_0 == 5'h0; // @[lsu.scala:1174:41, :1298:53] wire _GEN_627 = wb_ldst_forward_ldq_idx_0 == 5'h1; // @[lsu.scala:1174:41, :1298:53] wire _GEN_628 = wb_ldst_forward_ldq_idx_0 == 5'h2; // @[lsu.scala:1174:41, :1298:53] wire _GEN_629 = wb_ldst_forward_ldq_idx_0 == 5'h3; // @[lsu.scala:1174:41, :1298:53] wire _GEN_630 = wb_ldst_forward_ldq_idx_0 == 5'h4; // @[lsu.scala:1174:41, :1298:53] wire _GEN_631 = wb_ldst_forward_ldq_idx_0 == 5'h5; // @[lsu.scala:1174:41, :1298:53] wire _GEN_632 = wb_ldst_forward_ldq_idx_0 == 5'h6; // @[lsu.scala:1174:41, :1298:53] wire _GEN_633 = wb_ldst_forward_ldq_idx_0 == 5'h7; // @[lsu.scala:1174:41, :1298:53] wire _GEN_634 = wb_ldst_forward_ldq_idx_0 == 5'h8; // @[lsu.scala:1174:41, :1298:53] wire _GEN_635 = wb_ldst_forward_ldq_idx_0 == 5'h9; // @[lsu.scala:1174:41, :1298:53] wire _GEN_636 = wb_ldst_forward_ldq_idx_0 == 5'hA; // @[lsu.scala:1174:41, :1298:53] wire _GEN_637 = wb_ldst_forward_ldq_idx_0 == 5'hB; // @[lsu.scala:1174:41, :1298:53] wire _GEN_638 = wb_ldst_forward_ldq_idx_0 == 5'hC; // @[lsu.scala:1174:41, :1298:53] wire _GEN_639 = wb_ldst_forward_ldq_idx_0 == 5'hD; // @[lsu.scala:1174:41, :1298:53] wire _GEN_640 = wb_ldst_forward_ldq_idx_0 == 5'hE; // @[lsu.scala:1174:41, :1298:53] wire _GEN_641 = wb_ldst_forward_ldq_idx_0 == 5'hF; // @[lsu.scala:1174:41, :1298:53] wire _GEN_642 = wb_ldst_forward_ldq_idx_0 == 5'h10; // @[lsu.scala:1174:41, :1298:53] wire _GEN_643 = wb_ldst_forward_ldq_idx_0 == 5'h11; // @[lsu.scala:1174:41, :1298:53] wire _GEN_644 = wb_ldst_forward_ldq_idx_0 == 5'h12; // @[lsu.scala:1174:41, :1298:53] wire _GEN_645 = wb_ldst_forward_ldq_idx_0 == 5'h13; // @[lsu.scala:1174:41, :1298:53] wire _GEN_646 = wb_ldst_forward_ldq_idx_0 == 5'h14; // @[lsu.scala:1174:41, :1298:53] wire _GEN_647 = wb_ldst_forward_ldq_idx_0 == 5'h15; // @[lsu.scala:1174:41, :1298:53] wire _GEN_648 = wb_ldst_forward_ldq_idx_0 == 5'h16; // @[lsu.scala:1174:41, :1298:53] wire _GEN_649 = wb_ldst_forward_ldq_idx_0 == 5'h17; // @[lsu.scala:1174:41, :1298:53] wire _forwarded_is_older_T_96 = wb_ldst_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_97 = wb_ldst_forward_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_98 = _forwarded_is_older_T_96 ^ _forwarded_is_older_T_97; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_99 = lcam_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_24 = _forwarded_is_older_T_98 ^ _forwarded_is_older_T_99; // @[util.scala:364:{58,72,78}] wire [23:0] _T_1618 = wb_ldst_forward_e_0_st_dep_mask >> _GEN_481; // @[lsu.scala:321:49, :1218:33, :1308:46] wire _T_1621 = do_st_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & _T_1618[0] & forwarded_is_older_24; // @[util.scala:364:72] assign failed_load = _T_1621 \| _T_1612 \| _GEN_573 \| (_T_1498 ? _T_1502 \| _GEN_568 \| _GEN_565 : _GEN_568 \| _GEN_565); // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23, :1292:47, :1293:47, :1294:47, :1295:47, :1296:47, :1297:78, :1299:21, :1304:64, :1305:64, :1306:64, :1307:64, :1308:64, :1309:33, :1311:21] wire _addr_matches_0_0_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_1_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_2_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_3_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_4_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_5_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_6_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_7_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_8_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_9_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_10_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_11_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_12_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_13_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_14_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_15_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_16_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_17_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_18_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_19_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_20_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_21_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_22_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_23_T_1; // @[lsu.scala:1334:53] wire addr_matches_0_0; // @[lsu.scala:1316:29] wire addr_matches_0_1; // @[lsu.scala:1316:29] wire addr_matches_0_2; // @[lsu.scala:1316:29] wire addr_matches_0_3; // @[lsu.scala:1316:29] wire addr_matches_0_4; // @[lsu.scala:1316:29] wire addr_matches_0_5; // @[lsu.scala:1316:29] wire addr_matches_0_6; // @[lsu.scala:1316:29] wire addr_matches_0_7; // @[lsu.scala:1316:29] wire addr_matches_0_8; // @[lsu.scala:1316:29] wire addr_matches_0_9; // @[lsu.scala:1316:29] wire addr_matches_0_10; // @[lsu.scala:1316:29] wire addr_matches_0_11; // @[lsu.scala:1316:29] wire addr_matches_0_12; // @[lsu.scala:1316:29] wire addr_matches_0_13; // @[lsu.scala:1316:29] wire addr_matches_0_14; // @[lsu.scala:1316:29] wire addr_matches_0_15; // @[lsu.scala:1316:29] wire addr_matches_0_16; // @[lsu.scala:1316:29] wire addr_matches_0_17; // @[lsu.scala:1316:29] wire addr_matches_0_18; // @[lsu.scala:1316:29] wire addr_matches_0_19; // @[lsu.scala:1316:29] wire addr_matches_0_20; // @[lsu.scala:1316:29] wire addr_matches_0_21; // @[lsu.scala:1316:29] wire addr_matches_0_22; // @[lsu.scala:1316:29] wire addr_matches_0_23; // @[lsu.scala:1316:29] wire _forward_matches_0_0_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_1_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_2_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_3_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_4_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_5_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_6_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_7_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_8_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_9_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_10_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_11_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_12_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_13_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_14_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_15_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_16_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_17_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_18_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_19_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_20_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_21_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_22_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_23_T_2; // @[lsu.scala:1335:67] wire forward_matches_0_0; // @[lsu.scala:1317:29] wire forward_matches_0_1; // @[lsu.scala:1317:29] wire forward_matches_0_2; // @[lsu.scala:1317:29] wire forward_matches_0_3; // @[lsu.scala:1317:29] wire forward_matches_0_4; // @[lsu.scala:1317:29] wire forward_matches_0_5; // @[lsu.scala:1317:29] wire forward_matches_0_6; // @[lsu.scala:1317:29] wire forward_matches_0_7; // @[lsu.scala:1317:29] wire forward_matches_0_8; // @[lsu.scala:1317:29] wire forward_matches_0_9; // @[lsu.scala:1317:29] wire forward_matches_0_10; // @[lsu.scala:1317:29] wire forward_matches_0_11; // @[lsu.scala:1317:29] wire forward_matches_0_12; // @[lsu.scala:1317:29] wire forward_matches_0_13; // @[lsu.scala:1317:29] wire forward_matches_0_14; // @[lsu.scala:1317:29] wire forward_matches_0_15; // @[lsu.scala:1317:29] wire forward_matches_0_16; // @[lsu.scala:1317:29] wire forward_matches_0_17; // @[lsu.scala:1317:29] wire forward_matches_0_18; // @[lsu.scala:1317:29] wire forward_matches_0_19; // @[lsu.scala:1317:29] wire forward_matches_0_20; // @[lsu.scala:1317:29] wire forward_matches_0_21; // @[lsu.scala:1317:29] wire forward_matches_0_22; // @[lsu.scala:1317:29] wire forward_matches_0_23; // @[lsu.scala:1317:29] wire _prs2_matches_0_0_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_1_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_2_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_3_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_4_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_5_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_6_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_7_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_8_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_9_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_10_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_11_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_12_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_13_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_14_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_15_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_16_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_17_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_18_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_19_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_20_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_21_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_22_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_23_T_3; // @[lsu.scala:1338:58] wire prs2_matches_0_0; // @[lsu.scala:1318:29] wire prs2_matches_0_1; // @[lsu.scala:1318:29] wire prs2_matches_0_2; // @[lsu.scala:1318:29] wire prs2_matches_0_3; // @[lsu.scala:1318:29] wire prs2_matches_0_4; // @[lsu.scala:1318:29] wire prs2_matches_0_5; // @[lsu.scala:1318:29] wire prs2_matches_0_6; // @[lsu.scala:1318:29] wire prs2_matches_0_7; // @[lsu.scala:1318:29] wire prs2_matches_0_8; // @[lsu.scala:1318:29] wire prs2_matches_0_9; // @[lsu.scala:1318:29] wire prs2_matches_0_10; // @[lsu.scala:1318:29] wire prs2_matches_0_11; // @[lsu.scala:1318:29] wire prs2_matches_0_12; // @[lsu.scala:1318:29] wire prs2_matches_0_13; // @[lsu.scala:1318:29] wire prs2_matches_0_14; // @[lsu.scala:1318:29] wire prs2_matches_0_15; // @[lsu.scala:1318:29] wire prs2_matches_0_16; // @[lsu.scala:1318:29] wire prs2_matches_0_17; // @[lsu.scala:1318:29] wire prs2_matches_0_18; // @[lsu.scala:1318:29] wire prs2_matches_0_19; // @[lsu.scala:1318:29] wire prs2_matches_0_20; // @[lsu.scala:1318:29] wire prs2_matches_0_21; // @[lsu.scala:1318:29] wire prs2_matches_0_22; // @[lsu.scala:1318:29] wire prs2_matches_0_23; // @[lsu.scala:1318:29] wire [7:0] write_mask; // @[lsu.scala:1951:22] wire _write_mask_mask_T = s_uop_3_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_1 = stq_addr_0_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_3 = s_uop_3_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_4 = stq_addr_0_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_7 = s_uop_3_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_8 = stq_addr_0_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_10 = &s_uop_3_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_96 = ~s_uop_3_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_97 = stq_addr_0_valid & _dword_addr_matches_T_96; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_98 = ~stq_addr_is_virtual_0; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_99 = _dword_addr_matches_T_97 & _dword_addr_matches_T_98; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_100 = stq_addr_0_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire [28:0] _dword_addr_matches_T_101 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_108 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_115 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_122 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_129 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_136 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_143 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_150 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_157 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_164 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_171 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_178 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_185 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_192 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_199 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_206 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_213 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_220 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_227 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_234 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_241 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_248 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_255 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_262 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire _dword_addr_matches_T_102 = _dword_addr_matches_T_100 == _dword_addr_matches_T_101; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_24 = _dword_addr_matches_T_99 & _dword_addr_matches_T_102; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union = lcam_mask_0 & write_mask; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_0_T = \|mask_union; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_0_T_1 = _addr_matches_0_0_T & dword_addr_matches_24; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_0 = _addr_matches_0_0_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_0_T = addr_matches_0_0 & stq_data_0_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_0_T_1 = mask_union == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_0_T_2 = _forward_matches_0_0_T & _forward_matches_0_0_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_0 = _forward_matches_0_0_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_0_T = s_uop_3_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_0_T_1 = s_uop_3_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_0_T_2 = _prs2_matches_0_0_T & _prs2_matches_0_0_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_0_T_3 = _prs2_matches_0_0_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_0 = _prs2_matches_0_0_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_1; // @[lsu.scala:1951:22] wire _write_mask_mask_T_15 = s_uop_4_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_16 = stq_addr_1_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_18 = s_uop_4_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_19 = stq_addr_1_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_22 = s_uop_4_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_23 = stq_addr_1_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_25 = &s_uop_4_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_103 = ~s_uop_4_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_104 = stq_addr_1_valid & _dword_addr_matches_T_103; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_105 = ~stq_addr_is_virtual_1; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_106 = _dword_addr_matches_T_104 & _dword_addr_matches_T_105; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_107 = stq_addr_1_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_109 = _dword_addr_matches_T_107 == _dword_addr_matches_T_108; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_25 = _dword_addr_matches_T_106 & _dword_addr_matches_T_109; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_1 = lcam_mask_0 & write_mask_1; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_1_T = \|mask_union_1; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_1_T_1 = _addr_matches_0_1_T & dword_addr_matches_25; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_1 = _addr_matches_0_1_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_1_T = addr_matches_0_1 & stq_data_1_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_1_T_1 = mask_union_1 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_1_T_2 = _forward_matches_0_1_T & _forward_matches_0_1_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_1 = _forward_matches_0_1_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_1_T = s_uop_4_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_1_T_1 = s_uop_4_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_1_T_2 = _prs2_matches_0_1_T & _prs2_matches_0_1_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_1_T_3 = _prs2_matches_0_1_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_1 = _prs2_matches_0_1_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_2; // @[lsu.scala:1951:22] wire _write_mask_mask_T_30 = s_uop_5_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_31 = stq_addr_2_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_33 = s_uop_5_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_34 = stq_addr_2_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_37 = s_uop_5_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_38 = stq_addr_2_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_40 = &s_uop_5_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_110 = ~s_uop_5_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_111 = stq_addr_2_valid & _dword_addr_matches_T_110; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_112 = ~stq_addr_is_virtual_2; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_113 = _dword_addr_matches_T_111 & _dword_addr_matches_T_112; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_114 = stq_addr_2_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_116 = _dword_addr_matches_T_114 == _dword_addr_matches_T_115; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_26 = _dword_addr_matches_T_113 & _dword_addr_matches_T_116; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_2 = lcam_mask_0 & write_mask_2; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_2_T = \|mask_union_2; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_2_T_1 = _addr_matches_0_2_T & dword_addr_matches_26; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_2 = _addr_matches_0_2_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_2_T = addr_matches_0_2 & stq_data_2_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_2_T_1 = mask_union_2 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_2_T_2 = _forward_matches_0_2_T & _forward_matches_0_2_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_2 = _forward_matches_0_2_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_2_T = s_uop_5_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_2_T_1 = s_uop_5_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_2_T_2 = _prs2_matches_0_2_T & _prs2_matches_0_2_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_2_T_3 = _prs2_matches_0_2_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_2 = _prs2_matches_0_2_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_3; // @[lsu.scala:1951:22] wire _write_mask_mask_T_45 = s_uop_6_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_46 = stq_addr_3_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_48 = s_uop_6_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_49 = stq_addr_3_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_52 = s_uop_6_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_53 = stq_addr_3_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_55 = &s_uop_6_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_117 = ~s_uop_6_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_118 = stq_addr_3_valid & _dword_addr_matches_T_117; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_119 = ~stq_addr_is_virtual_3; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_120 = _dword_addr_matches_T_118 & _dword_addr_matches_T_119; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_121 = stq_addr_3_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_123 = _dword_addr_matches_T_121 == _dword_addr_matches_T_122; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_27 = _dword_addr_matches_T_120 & _dword_addr_matches_T_123; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_3 = lcam_mask_0 & write_mask_3; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_3_T = \|mask_union_3; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_3_T_1 = _addr_matches_0_3_T & dword_addr_matches_27; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_3 = _addr_matches_0_3_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_3_T = addr_matches_0_3 & stq_data_3_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_3_T_1 = mask_union_3 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_3_T_2 = _forward_matches_0_3_T & _forward_matches_0_3_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_3 = _forward_matches_0_3_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_3_T = s_uop_6_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_3_T_1 = s_uop_6_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_3_T_2 = _prs2_matches_0_3_T & _prs2_matches_0_3_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_3_T_3 = _prs2_matches_0_3_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_3 = _prs2_matches_0_3_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_4; // @[lsu.scala:1951:22] wire _write_mask_mask_T_60 = s_uop_7_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_61 = stq_addr_4_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_63 = s_uop_7_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_64 = stq_addr_4_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_67 = s_uop_7_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_68 = stq_addr_4_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_70 = &s_uop_7_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_124 = ~s_uop_7_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_125 = stq_addr_4_valid & _dword_addr_matches_T_124; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_126 = ~stq_addr_is_virtual_4; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_127 = _dword_addr_matches_T_125 & _dword_addr_matches_T_126; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_128 = stq_addr_4_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 == _dword_addr_matches_T_129; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_28 = _dword_addr_matches_T_127 & _dword_addr_matches_T_130; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_4 = lcam_mask_0 & write_mask_4; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_4_T = \|mask_union_4; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_4_T_1 = _addr_matches_0_4_T & dword_addr_matches_28; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_4 = _addr_matches_0_4_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_4_T = addr_matches_0_4 & stq_data_4_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_4_T_1 = mask_union_4 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_4_T_2 = _forward_matches_0_4_T & _forward_matches_0_4_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_4 = _forward_matches_0_4_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_4_T = s_uop_7_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_4_T_1 = s_uop_7_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_4_T_2 = _prs2_matches_0_4_T & _prs2_matches_0_4_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_4_T_3 = _prs2_matches_0_4_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_4 = _prs2_matches_0_4_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_5; // @[lsu.scala:1951:22] wire _write_mask_mask_T_75 = s_uop_8_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_76 = stq_addr_5_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_78 = s_uop_8_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_79 = stq_addr_5_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_82 = s_uop_8_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_83 = stq_addr_5_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_85 = &s_uop_8_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_131 = ~s_uop_8_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_132 = stq_addr_5_valid & _dword_addr_matches_T_131; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_133 = ~stq_addr_is_virtual_5; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_134 = _dword_addr_matches_T_132 & _dword_addr_matches_T_133; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_135 = stq_addr_5_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_137 = _dword_addr_matches_T_135 == _dword_addr_matches_T_136; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_29 = _dword_addr_matches_T_134 & _dword_addr_matches_T_137; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_5 = lcam_mask_0 & write_mask_5; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_5_T = \|mask_union_5; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_5_T_1 = _addr_matches_0_5_T & dword_addr_matches_29; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_5 = _addr_matches_0_5_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_5_T = addr_matches_0_5 & stq_data_5_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_5_T_1 = mask_union_5 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_5_T_2 = _forward_matches_0_5_T & _forward_matches_0_5_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_5 = _forward_matches_0_5_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_5_T = s_uop_8_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_5_T_1 = s_uop_8_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_5_T_2 = _prs2_matches_0_5_T & _prs2_matches_0_5_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_5_T_3 = _prs2_matches_0_5_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_5 = _prs2_matches_0_5_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_6; // @[lsu.scala:1951:22] wire _write_mask_mask_T_90 = s_uop_9_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_91 = stq_addr_6_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_93 = s_uop_9_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_94 = stq_addr_6_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_97 = s_uop_9_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_98 = stq_addr_6_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_100 = &s_uop_9_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_138 = ~s_uop_9_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_139 = stq_addr_6_valid & _dword_addr_matches_T_138; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_140 = ~stq_addr_is_virtual_6; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_141 = _dword_addr_matches_T_139 & _dword_addr_matches_T_140; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_142 = stq_addr_6_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_144 = _dword_addr_matches_T_142 == _dword_addr_matches_T_143; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_30 = _dword_addr_matches_T_141 & _dword_addr_matches_T_144; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_6 = lcam_mask_0 & write_mask_6; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_6_T = \|mask_union_6; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_6_T_1 = _addr_matches_0_6_T & dword_addr_matches_30; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_6 = _addr_matches_0_6_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_6_T = addr_matches_0_6 & stq_data_6_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_6_T_1 = mask_union_6 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_6_T_2 = _forward_matches_0_6_T & _forward_matches_0_6_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_6 = _forward_matches_0_6_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_6_T = s_uop_9_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_6_T_1 = s_uop_9_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_6_T_2 = _prs2_matches_0_6_T & _prs2_matches_0_6_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_6_T_3 = _prs2_matches_0_6_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_6 = _prs2_matches_0_6_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_7; // @[lsu.scala:1951:22] wire _write_mask_mask_T_105 = s_uop_10_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_106 = stq_addr_7_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_108 = s_uop_10_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_109 = stq_addr_7_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_112 = s_uop_10_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_113 = stq_addr_7_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_115 = &s_uop_10_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_145 = ~s_uop_10_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_146 = stq_addr_7_valid & _dword_addr_matches_T_145; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_147 = ~stq_addr_is_virtual_7; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_148 = _dword_addr_matches_T_146 & _dword_addr_matches_T_147; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_149 = stq_addr_7_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_151 = _dword_addr_matches_T_149 == _dword_addr_matches_T_150; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_31 = _dword_addr_matches_T_148 & _dword_addr_matches_T_151; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_7 = lcam_mask_0 & write_mask_7; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_7_T = \|mask_union_7; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_7_T_1 = _addr_matches_0_7_T & dword_addr_matches_31; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_7 = _addr_matches_0_7_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_7_T = addr_matches_0_7 & stq_data_7_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_7_T_1 = mask_union_7 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_7_T_2 = _forward_matches_0_7_T & _forward_matches_0_7_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_7 = _forward_matches_0_7_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_7_T = s_uop_10_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_7_T_1 = s_uop_10_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_7_T_2 = _prs2_matches_0_7_T & _prs2_matches_0_7_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_7_T_3 = _prs2_matches_0_7_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_7 = _prs2_matches_0_7_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_8; // @[lsu.scala:1951:22] wire _write_mask_mask_T_120 = s_uop_11_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_121 = stq_addr_8_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_123 = s_uop_11_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_124 = stq_addr_8_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_127 = s_uop_11_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_128 = stq_addr_8_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_130 = &s_uop_11_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16] assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_152 = ~s_uop_11_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_153 = stq_addr_8_valid & _dword_addr_matches_T_152; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_154 = ~stq_addr_is_virtual_8; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_155 = _dword_addr_matches_T_153 & _dword_addr_matches_T_154; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_156 = stq_addr_8_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_158 = _dword_addr_matches_T_156 == _dword_addr_matches_T_157; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_32 = _dword_addr_matches_T_155 & _dword_addr_matches_T_158; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_8 = lcam_mask_0 & write_mask_8; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_8_T = \|mask_union_8; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_8_T_1 = _addr_matches_0_8_T & dword_addr_matches_32; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_8 = _addr_matches_0_8_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_8_T = addr_matches_0_8 & stq_data_8_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_8_T_1 = mask_union_8 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_8_T_2 = _forward_matches_0_8_T & _forward_matches_0_8_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_8 = _forward_matches_0_8_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_8_T = s_uop_11_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_8_T_1 = s_uop_11_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_8_T_2 = _prs2_matches_0_8_T & _prs2_matches_0_8_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_8_T_3 = _prs2_matches_0_8_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_8 = _prs2_matches_0_8_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_9; // @[lsu.scala:1951:22] wire _write_mask_mask_T_135 = s_uop_12_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_136 = stq_addr_9_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_138 = s_uop_12_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_139 = stq_addr_9_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_142 = s_uop_12_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_143 = stq_addr_9_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_145 = &s_uop_12_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16] assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_159 = ~s_uop_12_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_160 = stq_addr_9_valid & _dword_addr_matches_T_159; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_161 = ~stq_addr_is_virtual_9; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_162 = _dword_addr_matches_T_160 & _dword_addr_matches_T_161; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_163 = stq_addr_9_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_165 = _dword_addr_matches_T_163 == _dword_addr_matches_T_164; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_33 = _dword_addr_matches_T_162 & _dword_addr_matches_T_165; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_9 = lcam_mask_0 & write_mask_9; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_9_T = \|mask_union_9; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_9_T_1 = _addr_matches_0_9_T & dword_addr_matches_33; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_9 = _addr_matches_0_9_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_9_T = addr_matches_0_9 & stq_data_9_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_9_T_1 = mask_union_9 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_9_T_2 = _forward_matches_0_9_T & _forward_matches_0_9_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_9 = _forward_matches_0_9_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_9_T = s_uop_12_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_9_T_1 = s_uop_12_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_9_T_2 = _prs2_matches_0_9_T & _prs2_matches_0_9_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_9_T_3 = _prs2_matches_0_9_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_9 = _prs2_matches_0_9_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_10; // @[lsu.scala:1951:22] wire _write_mask_mask_T_150 = s_uop_13_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_151 = stq_addr_10_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_153 = s_uop_13_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_154 = stq_addr_10_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_157 = s_uop_13_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_158 = stq_addr_10_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_160 = &s_uop_13_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16] assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_166 = ~s_uop_13_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_167 = stq_addr_10_valid & _dword_addr_matches_T_166; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_168 = ~stq_addr_is_virtual_10; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_169 = _dword_addr_matches_T_167 & _dword_addr_matches_T_168; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_170 = stq_addr_10_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 == _dword_addr_matches_T_171; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_34 = _dword_addr_matches_T_169 & _dword_addr_matches_T_172; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_10 = lcam_mask_0 & write_mask_10; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_10_T = \|mask_union_10; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_10_T_1 = _addr_matches_0_10_T & dword_addr_matches_34; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_10 = _addr_matches_0_10_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_10_T = addr_matches_0_10 & stq_data_10_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_10_T_1 = mask_union_10 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_10_T_2 = _forward_matches_0_10_T & _forward_matches_0_10_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_10 = _forward_matches_0_10_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_10_T = s_uop_13_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_10_T_1 = s_uop_13_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_10_T_2 = _prs2_matches_0_10_T & _prs2_matches_0_10_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_10_T_3 = _prs2_matches_0_10_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_10 = _prs2_matches_0_10_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_11; // @[lsu.scala:1951:22] wire _write_mask_mask_T_165 = s_uop_14_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_166 = stq_addr_11_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_168 = s_uop_14_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_169 = stq_addr_11_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_172 = s_uop_14_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_173 = stq_addr_11_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_175 = &s_uop_14_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16] assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_173 = ~s_uop_14_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_174 = stq_addr_11_valid & _dword_addr_matches_T_173; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_175 = ~stq_addr_is_virtual_11; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_176 = _dword_addr_matches_T_174 & _dword_addr_matches_T_175; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_177 = stq_addr_11_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_179 = _dword_addr_matches_T_177 == _dword_addr_matches_T_178; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_35 = _dword_addr_matches_T_176 & _dword_addr_matches_T_179; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_11 = lcam_mask_0 & write_mask_11; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_11_T = \|mask_union_11; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_11_T_1 = _addr_matches_0_11_T & dword_addr_matches_35; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_11 = _addr_matches_0_11_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_11_T = addr_matches_0_11 & stq_data_11_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_11_T_1 = mask_union_11 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_11_T_2 = _forward_matches_0_11_T & _forward_matches_0_11_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_11 = _forward_matches_0_11_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_11_T = s_uop_14_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_11_T_1 = s_uop_14_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_11_T_2 = _prs2_matches_0_11_T & _prs2_matches_0_11_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_11_T_3 = _prs2_matches_0_11_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_11 = _prs2_matches_0_11_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_12; // @[lsu.scala:1951:22] wire _write_mask_mask_T_180 = s_uop_15_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_181 = stq_addr_12_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_183 = s_uop_15_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_184 = stq_addr_12_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_187 = s_uop_15_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_188 = stq_addr_12_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_190 = &s_uop_15_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16] assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_180 = ~s_uop_15_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_181 = stq_addr_12_valid & _dword_addr_matches_T_180; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_182 = ~stq_addr_is_virtual_12; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_183 = _dword_addr_matches_T_181 & _dword_addr_matches_T_182; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_184 = stq_addr_12_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_186 = _dword_addr_matches_T_184 == _dword_addr_matches_T_185; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_36 = _dword_addr_matches_T_183 & _dword_addr_matches_T_186; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_12 = lcam_mask_0 & write_mask_12; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_12_T = \|mask_union_12; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_12_T_1 = _addr_matches_0_12_T & dword_addr_matches_36; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_12 = _addr_matches_0_12_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_12_T = addr_matches_0_12 & stq_data_12_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_12_T_1 = mask_union_12 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_12_T_2 = _forward_matches_0_12_T & _forward_matches_0_12_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_12 = _forward_matches_0_12_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_12_T = s_uop_15_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_12_T_1 = s_uop_15_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_12_T_2 = _prs2_matches_0_12_T & _prs2_matches_0_12_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_12_T_3 = _prs2_matches_0_12_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_12 = _prs2_matches_0_12_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_13; // @[lsu.scala:1951:22] wire _write_mask_mask_T_195 = s_uop_16_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_196 = stq_addr_13_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_198 = s_uop_16_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_199 = stq_addr_13_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_202 = s_uop_16_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_203 = stq_addr_13_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_205 = &s_uop_16_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16] assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_187 = ~s_uop_16_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_188 = stq_addr_13_valid & _dword_addr_matches_T_187; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_189 = ~stq_addr_is_virtual_13; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_190 = _dword_addr_matches_T_188 & _dword_addr_matches_T_189; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_191 = stq_addr_13_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_193 = _dword_addr_matches_T_191 == _dword_addr_matches_T_192; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_37 = _dword_addr_matches_T_190 & _dword_addr_matches_T_193; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_13 = lcam_mask_0 & write_mask_13; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_13_T = \|mask_union_13; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_13_T_1 = _addr_matches_0_13_T & dword_addr_matches_37; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_13 = _addr_matches_0_13_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_13_T = addr_matches_0_13 & stq_data_13_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_13_T_1 = mask_union_13 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_13_T_2 = _forward_matches_0_13_T & _forward_matches_0_13_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_13 = _forward_matches_0_13_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_13_T = s_uop_16_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_13_T_1 = s_uop_16_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_13_T_2 = _prs2_matches_0_13_T & _prs2_matches_0_13_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_13_T_3 = _prs2_matches_0_13_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_13 = _prs2_matches_0_13_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_14; // @[lsu.scala:1951:22] wire _write_mask_mask_T_210 = s_uop_17_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_211 = stq_addr_14_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_213 = s_uop_17_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_214 = stq_addr_14_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_217 = s_uop_17_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_218 = stq_addr_14_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_220 = &s_uop_17_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16] assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_194 = ~s_uop_17_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_195 = stq_addr_14_valid & _dword_addr_matches_T_194; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_196 = ~stq_addr_is_virtual_14; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_197 = _dword_addr_matches_T_195 & _dword_addr_matches_T_196; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_198 = stq_addr_14_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_200 = _dword_addr_matches_T_198 == _dword_addr_matches_T_199; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_38 = _dword_addr_matches_T_197 & _dword_addr_matches_T_200; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_14 = lcam_mask_0 & write_mask_14; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_14_T = \|mask_union_14; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_14_T_1 = _addr_matches_0_14_T & dword_addr_matches_38; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_14 = _addr_matches_0_14_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_14_T = addr_matches_0_14 & stq_data_14_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_14_T_1 = mask_union_14 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_14_T_2 = _forward_matches_0_14_T & _forward_matches_0_14_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_14 = _forward_matches_0_14_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_14_T = s_uop_17_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_14_T_1 = s_uop_17_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_14_T_2 = _prs2_matches_0_14_T & _prs2_matches_0_14_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_14_T_3 = _prs2_matches_0_14_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_14 = _prs2_matches_0_14_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_15; // @[lsu.scala:1951:22] wire _write_mask_mask_T_225 = s_uop_18_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_226 = stq_addr_15_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_228 = s_uop_18_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_229 = stq_addr_15_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_232 = s_uop_18_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_233 = stq_addr_15_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_235 = &s_uop_18_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16] assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_201 = ~s_uop_18_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_202 = stq_addr_15_valid & _dword_addr_matches_T_201; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_203 = ~stq_addr_is_virtual_15; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_204 = _dword_addr_matches_T_202 & _dword_addr_matches_T_203; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_205 = stq_addr_15_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_207 = _dword_addr_matches_T_205 == _dword_addr_matches_T_206; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_39 = _dword_addr_matches_T_204 & _dword_addr_matches_T_207; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_15 = lcam_mask_0 & write_mask_15; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_15_T = \|mask_union_15; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_15_T_1 = _addr_matches_0_15_T & dword_addr_matches_39; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_15 = _addr_matches_0_15_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_15_T = addr_matches_0_15 & stq_data_15_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_15_T_1 = mask_union_15 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_15_T_2 = _forward_matches_0_15_T & _forward_matches_0_15_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_15 = _forward_matches_0_15_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_15_T = s_uop_18_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_15_T_1 = s_uop_18_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_15_T_2 = _prs2_matches_0_15_T & _prs2_matches_0_15_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_15_T_3 = _prs2_matches_0_15_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_15 = _prs2_matches_0_15_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_16; // @[lsu.scala:1951:22] wire _write_mask_mask_T_240 = s_uop_19_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_241 = stq_addr_16_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_242 = 15'h1 << _write_mask_mask_T_241; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_243 = s_uop_19_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_244 = stq_addr_16_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_245 = {_write_mask_mask_T_244, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_246 = 15'h3 << _write_mask_mask_T_245; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_247 = s_uop_19_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_248 = stq_addr_16_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_249 = _write_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_250 = &s_uop_19_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_252 = _write_mask_mask_T_247 ? _write_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_253 = _write_mask_mask_T_243 ? _write_mask_mask_T_246 : {7'h0, _write_mask_mask_T_252}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_254 = _write_mask_mask_T_240 ? _write_mask_mask_T_242 : _write_mask_mask_T_253; // @[Mux.scala:126:16] assign write_mask_16 = _write_mask_mask_T_254[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_208 = ~s_uop_19_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_209 = stq_addr_16_valid & _dword_addr_matches_T_208; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_210 = ~stq_addr_is_virtual_16; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_211 = _dword_addr_matches_T_209 & _dword_addr_matches_T_210; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_212 = stq_addr_16_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_214 = _dword_addr_matches_T_212 == _dword_addr_matches_T_213; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_40 = _dword_addr_matches_T_211 & _dword_addr_matches_T_214; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_16 = lcam_mask_0 & write_mask_16; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_16_T = \|mask_union_16; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_16_T_1 = _addr_matches_0_16_T & dword_addr_matches_40; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_16 = _addr_matches_0_16_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_16_T = addr_matches_0_16 & stq_data_16_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_16_T_1 = mask_union_16 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_16_T_2 = _forward_matches_0_16_T & _forward_matches_0_16_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_16 = _forward_matches_0_16_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_16_T = s_uop_19_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_16_T_1 = s_uop_19_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_16_T_2 = _prs2_matches_0_16_T & _prs2_matches_0_16_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_16_T_3 = _prs2_matches_0_16_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_16 = _prs2_matches_0_16_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_17; // @[lsu.scala:1951:22] wire _write_mask_mask_T_255 = s_uop_20_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_256 = stq_addr_17_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_257 = 15'h1 << _write_mask_mask_T_256; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_258 = s_uop_20_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_259 = stq_addr_17_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_260 = {_write_mask_mask_T_259, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_261 = 15'h3 << _write_mask_mask_T_260; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_262 = s_uop_20_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_263 = stq_addr_17_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_264 = _write_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_265 = &s_uop_20_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_267 = _write_mask_mask_T_262 ? _write_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_268 = _write_mask_mask_T_258 ? _write_mask_mask_T_261 : {7'h0, _write_mask_mask_T_267}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_269 = _write_mask_mask_T_255 ? _write_mask_mask_T_257 : _write_mask_mask_T_268; // @[Mux.scala:126:16] assign write_mask_17 = _write_mask_mask_T_269[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_215 = ~s_uop_20_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_216 = stq_addr_17_valid & _dword_addr_matches_T_215; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_217 = ~stq_addr_is_virtual_17; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_218 = _dword_addr_matches_T_216 & _dword_addr_matches_T_217; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_219 = stq_addr_17_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_221 = _dword_addr_matches_T_219 == _dword_addr_matches_T_220; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_41 = _dword_addr_matches_T_218 & _dword_addr_matches_T_221; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_17 = lcam_mask_0 & write_mask_17; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_17_T = \|mask_union_17; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_17_T_1 = _addr_matches_0_17_T & dword_addr_matches_41; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_17 = _addr_matches_0_17_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_17_T = addr_matches_0_17 & stq_data_17_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_17_T_1 = mask_union_17 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_17_T_2 = _forward_matches_0_17_T & _forward_matches_0_17_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_17 = _forward_matches_0_17_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_17_T = s_uop_20_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_17_T_1 = s_uop_20_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_17_T_2 = _prs2_matches_0_17_T & _prs2_matches_0_17_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_17_T_3 = _prs2_matches_0_17_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_17 = _prs2_matches_0_17_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_18; // @[lsu.scala:1951:22] wire _write_mask_mask_T_270 = s_uop_21_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_271 = stq_addr_18_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_272 = 15'h1 << _write_mask_mask_T_271; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_273 = s_uop_21_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_274 = stq_addr_18_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_275 = {_write_mask_mask_T_274, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_276 = 15'h3 << _write_mask_mask_T_275; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_277 = s_uop_21_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_278 = stq_addr_18_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_279 = _write_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_280 = &s_uop_21_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_282 = _write_mask_mask_T_277 ? _write_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_283 = _write_mask_mask_T_273 ? _write_mask_mask_T_276 : {7'h0, _write_mask_mask_T_282}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_284 = _write_mask_mask_T_270 ? _write_mask_mask_T_272 : _write_mask_mask_T_283; // @[Mux.scala:126:16] assign write_mask_18 = _write_mask_mask_T_284[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_222 = ~s_uop_21_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_223 = stq_addr_18_valid & _dword_addr_matches_T_222; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_224 = ~stq_addr_is_virtual_18; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_225 = _dword_addr_matches_T_223 & _dword_addr_matches_T_224; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_226 = stq_addr_18_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_228 = _dword_addr_matches_T_226 == _dword_addr_matches_T_227; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_42 = _dword_addr_matches_T_225 & _dword_addr_matches_T_228; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_18 = lcam_mask_0 & write_mask_18; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_18_T = \|mask_union_18; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_18_T_1 = _addr_matches_0_18_T & dword_addr_matches_42; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_18 = _addr_matches_0_18_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_18_T = addr_matches_0_18 & stq_data_18_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_18_T_1 = mask_union_18 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_18_T_2 = _forward_matches_0_18_T & _forward_matches_0_18_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_18 = _forward_matches_0_18_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_18_T = s_uop_21_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_18_T_1 = s_uop_21_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_18_T_2 = _prs2_matches_0_18_T & _prs2_matches_0_18_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_18_T_3 = _prs2_matches_0_18_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_18 = _prs2_matches_0_18_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_19; // @[lsu.scala:1951:22] wire _write_mask_mask_T_285 = s_uop_22_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_286 = stq_addr_19_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_287 = 15'h1 << _write_mask_mask_T_286; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_288 = s_uop_22_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_289 = stq_addr_19_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_290 = {_write_mask_mask_T_289, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_291 = 15'h3 << _write_mask_mask_T_290; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_292 = s_uop_22_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_293 = stq_addr_19_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_294 = _write_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_295 = &s_uop_22_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_297 = _write_mask_mask_T_292 ? _write_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_298 = _write_mask_mask_T_288 ? _write_mask_mask_T_291 : {7'h0, _write_mask_mask_T_297}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_299 = _write_mask_mask_T_285 ? _write_mask_mask_T_287 : _write_mask_mask_T_298; // @[Mux.scala:126:16] assign write_mask_19 = _write_mask_mask_T_299[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_229 = ~s_uop_22_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_230 = stq_addr_19_valid & _dword_addr_matches_T_229; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_231 = ~stq_addr_is_virtual_19; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_232 = _dword_addr_matches_T_230 & _dword_addr_matches_T_231; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_233 = stq_addr_19_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_235 = _dword_addr_matches_T_233 == _dword_addr_matches_T_234; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_43 = _dword_addr_matches_T_232 & _dword_addr_matches_T_235; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_19 = lcam_mask_0 & write_mask_19; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_19_T = \|mask_union_19; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_19_T_1 = _addr_matches_0_19_T & dword_addr_matches_43; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_19 = _addr_matches_0_19_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_19_T = addr_matches_0_19 & stq_data_19_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_19_T_1 = mask_union_19 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_19_T_2 = _forward_matches_0_19_T & _forward_matches_0_19_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_19 = _forward_matches_0_19_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_19_T = s_uop_22_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_19_T_1 = s_uop_22_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_19_T_2 = _prs2_matches_0_19_T & _prs2_matches_0_19_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_19_T_3 = _prs2_matches_0_19_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_19 = _prs2_matches_0_19_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_20; // @[lsu.scala:1951:22] wire _write_mask_mask_T_300 = s_uop_23_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_301 = stq_addr_20_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_302 = 15'h1 << _write_mask_mask_T_301; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_303 = s_uop_23_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_304 = stq_addr_20_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_305 = {_write_mask_mask_T_304, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_306 = 15'h3 << _write_mask_mask_T_305; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_307 = s_uop_23_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_308 = stq_addr_20_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_309 = _write_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_310 = &s_uop_23_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_312 = _write_mask_mask_T_307 ? _write_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_313 = _write_mask_mask_T_303 ? _write_mask_mask_T_306 : {7'h0, _write_mask_mask_T_312}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_314 = _write_mask_mask_T_300 ? _write_mask_mask_T_302 : _write_mask_mask_T_313; // @[Mux.scala:126:16] assign write_mask_20 = _write_mask_mask_T_314[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_236 = ~s_uop_23_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_237 = stq_addr_20_valid & _dword_addr_matches_T_236; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_238 = ~stq_addr_is_virtual_20; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_239 = _dword_addr_matches_T_237 & _dword_addr_matches_T_238; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_240 = stq_addr_20_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_242 = _dword_addr_matches_T_240 == _dword_addr_matches_T_241; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_44 = _dword_addr_matches_T_239 & _dword_addr_matches_T_242; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_20 = lcam_mask_0 & write_mask_20; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_20_T = \|mask_union_20; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_20_T_1 = _addr_matches_0_20_T & dword_addr_matches_44; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_20 = _addr_matches_0_20_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_20_T = addr_matches_0_20 & stq_data_20_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_20_T_1 = mask_union_20 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_20_T_2 = _forward_matches_0_20_T & _forward_matches_0_20_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_20 = _forward_matches_0_20_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_20_T = s_uop_23_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_20_T_1 = s_uop_23_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_20_T_2 = _prs2_matches_0_20_T & _prs2_matches_0_20_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_20_T_3 = _prs2_matches_0_20_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_20 = _prs2_matches_0_20_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_21; // @[lsu.scala:1951:22] wire _write_mask_mask_T_315 = s_uop_24_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_316 = stq_addr_21_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_317 = 15'h1 << _write_mask_mask_T_316; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_318 = s_uop_24_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_319 = stq_addr_21_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_320 = {_write_mask_mask_T_319, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_321 = 15'h3 << _write_mask_mask_T_320; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_322 = s_uop_24_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_323 = stq_addr_21_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_324 = _write_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_325 = &s_uop_24_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_327 = _write_mask_mask_T_322 ? _write_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_328 = _write_mask_mask_T_318 ? _write_mask_mask_T_321 : {7'h0, _write_mask_mask_T_327}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_329 = _write_mask_mask_T_315 ? _write_mask_mask_T_317 : _write_mask_mask_T_328; // @[Mux.scala:126:16] assign write_mask_21 = _write_mask_mask_T_329[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_243 = ~s_uop_24_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_244 = stq_addr_21_valid & _dword_addr_matches_T_243; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_245 = ~stq_addr_is_virtual_21; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_246 = _dword_addr_matches_T_244 & _dword_addr_matches_T_245; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_247 = stq_addr_21_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_249 = _dword_addr_matches_T_247 == _dword_addr_matches_T_248; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_45 = _dword_addr_matches_T_246 & _dword_addr_matches_T_249; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_21 = lcam_mask_0 & write_mask_21; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_21_T = \|mask_union_21; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_21_T_1 = _addr_matches_0_21_T & dword_addr_matches_45; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_21 = _addr_matches_0_21_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_21_T = addr_matches_0_21 & stq_data_21_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_21_T_1 = mask_union_21 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_21_T_2 = _forward_matches_0_21_T & _forward_matches_0_21_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_21 = _forward_matches_0_21_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_21_T = s_uop_24_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_21_T_1 = s_uop_24_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_21_T_2 = _prs2_matches_0_21_T & _prs2_matches_0_21_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_21_T_3 = _prs2_matches_0_21_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_21 = _prs2_matches_0_21_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_22; // @[lsu.scala:1951:22] wire _write_mask_mask_T_330 = s_uop_25_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_331 = stq_addr_22_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_332 = 15'h1 << _write_mask_mask_T_331; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_333 = s_uop_25_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_334 = stq_addr_22_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_335 = {_write_mask_mask_T_334, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_336 = 15'h3 << _write_mask_mask_T_335; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_337 = s_uop_25_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_338 = stq_addr_22_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_339 = _write_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_340 = &s_uop_25_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_342 = _write_mask_mask_T_337 ? _write_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_343 = _write_mask_mask_T_333 ? _write_mask_mask_T_336 : {7'h0, _write_mask_mask_T_342}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_344 = _write_mask_mask_T_330 ? _write_mask_mask_T_332 : _write_mask_mask_T_343; // @[Mux.scala:126:16] assign write_mask_22 = _write_mask_mask_T_344[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_250 = ~s_uop_25_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_251 = stq_addr_22_valid & _dword_addr_matches_T_250; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_252 = ~stq_addr_is_virtual_22; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_253 = _dword_addr_matches_T_251 & _dword_addr_matches_T_252; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_254 = stq_addr_22_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_256 = _dword_addr_matches_T_254 == _dword_addr_matches_T_255; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_46 = _dword_addr_matches_T_253 & _dword_addr_matches_T_256; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_22 = lcam_mask_0 & write_mask_22; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_22_T = \|mask_union_22; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_22_T_1 = _addr_matches_0_22_T & dword_addr_matches_46; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_22 = _addr_matches_0_22_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_22_T = addr_matches_0_22 & stq_data_22_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_22_T_1 = mask_union_22 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_22_T_2 = _forward_matches_0_22_T & _forward_matches_0_22_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_22 = _forward_matches_0_22_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_22_T = s_uop_25_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_22_T_1 = s_uop_25_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_22_T_2 = _prs2_matches_0_22_T & _prs2_matches_0_22_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_22_T_3 = _prs2_matches_0_22_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_22 = _prs2_matches_0_22_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_23; // @[lsu.scala:1951:22] wire _write_mask_mask_T_345 = s_uop_26_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_346 = stq_addr_23_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_347 = 15'h1 << _write_mask_mask_T_346; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_348 = s_uop_26_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_349 = stq_addr_23_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_350 = {_write_mask_mask_T_349, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_351 = 15'h3 << _write_mask_mask_T_350; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_352 = s_uop_26_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_353 = stq_addr_23_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_354 = _write_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_355 = &s_uop_26_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_357 = _write_mask_mask_T_352 ? _write_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_358 = _write_mask_mask_T_348 ? _write_mask_mask_T_351 : {7'h0, _write_mask_mask_T_357}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_359 = _write_mask_mask_T_345 ? _write_mask_mask_T_347 : _write_mask_mask_T_358; // @[Mux.scala:126:16] assign write_mask_23 = _write_mask_mask_T_359[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_257 = ~s_uop_26_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_258 = stq_addr_23_valid & _dword_addr_matches_T_257; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_259 = ~stq_addr_is_virtual_23; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_260 = _dword_addr_matches_T_258 & _dword_addr_matches_T_259; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_261 = stq_addr_23_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_263 = _dword_addr_matches_T_261 == _dword_addr_matches_T_262; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_47 = _dword_addr_matches_T_260 & _dword_addr_matches_T_263; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_23 = lcam_mask_0 & write_mask_23; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_23_T = \|mask_union_23; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_23_T_1 = _addr_matches_0_23_T & dword_addr_matches_47; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_23 = _addr_matches_0_23_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_23_T = addr_matches_0_23 & stq_data_23_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_23_T_1 = mask_union_23 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_23_T_2 = _forward_matches_0_23_T & _forward_matches_0_23_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_23 = _forward_matches_0_23_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_23_T = s_uop_26_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_23_T_1 = s_uop_26_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_23_T_2 = _prs2_matches_0_23_T & _prs2_matches_0_23_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_23_T_3 = _prs2_matches_0_23_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_23 = _prs2_matches_0_23_T_3; // @[lsu.scala:1318:29, :1338:58] wire [2:0] fast_stq_valids_lo_lo_lo = {fast_stq_valids_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_lo_lo_hi = {fast_stq_valids_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_lo_lo = {fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_lo_hi_lo = {fast_stq_valids_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_lo_hi_hi = {fast_stq_valids_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_lo_hi = {fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo}; // @[lsu.scala:1342:35] wire [11:0] fast_stq_valids_lo = {fast_stq_valids_lo_hi, fast_stq_valids_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_hi_lo_lo = {fast_stq_valids_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_hi_lo_hi = {fast_stq_valids_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_hi_lo = {fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_hi_hi_lo = {fast_stq_valids_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_hi_hi_hi = {fast_stq_valids_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_hi_hi = {fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo}; // @[lsu.scala:1342:35] wire [11:0] fast_stq_valids_hi = {fast_stq_valids_hi_hi, fast_stq_valids_hi_lo}; // @[lsu.scala:1342:35] wire [23:0] fast_stq_valids = {fast_stq_valids_hi, fast_stq_valids_lo}; // @[lsu.scala:1342:35] wire [1:0] ldst_addr_matches_0_lo_lo_lo_hi = {addr_matches_0_2, addr_matches_0_1}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_lo_lo = {ldst_addr_matches_0_lo_lo_lo_hi, addr_matches_0_0}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_lo_hi_hi = {addr_matches_0_5, addr_matches_0_4}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_lo_hi = {ldst_addr_matches_0_lo_lo_hi_hi, addr_matches_0_3}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_lo_lo = {ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_lo_hi = {addr_matches_0_8, addr_matches_0_7}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_hi_lo = {ldst_addr_matches_0_lo_hi_lo_hi, addr_matches_0_6}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_hi_hi = {addr_matches_0_11, addr_matches_0_10}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_hi_hi = {ldst_addr_matches_0_lo_hi_hi_hi, addr_matches_0_9}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_lo_hi = {ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo}; // @[lsu.scala:1344:49] wire [11:0] ldst_addr_matches_0_lo = {ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_lo_hi = {addr_matches_0_14, addr_matches_0_13}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_lo_lo = {ldst_addr_matches_0_hi_lo_lo_hi, addr_matches_0_12}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_hi_hi = {addr_matches_0_17, addr_matches_0_16}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_lo_hi = {ldst_addr_matches_0_hi_lo_hi_hi, addr_matches_0_15}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_hi_lo = {ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_lo_hi = {addr_matches_0_20, addr_matches_0_19}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_hi_lo = {ldst_addr_matches_0_hi_hi_lo_hi, addr_matches_0_18}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_hi_hi = {addr_matches_0_23, addr_matches_0_22}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_hi_hi = {ldst_addr_matches_0_hi_hi_hi_hi, addr_matches_0_21}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_hi_hi = {ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo}; // @[lsu.scala:1344:49] wire [11:0] ldst_addr_matches_0_hi = {ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo}; // @[lsu.scala:1344:49] wire [23:0] _ldst_addr_matches_0_T = {ldst_addr_matches_0_hi, ldst_addr_matches_0_lo}; // @[lsu.scala:1344:49] wire [23:0] _ldst_addr_matches_0_T_1 = _ldst_addr_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1344:{49,56}] assign _ldst_addr_matches_0_T_2 = _ldst_addr_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1344:{56,79}] assign ldst_addr_matches_0 = _ldst_addr_matches_0_T_2; // @[lsu.scala:1162:34, :1344:79] wire [1:0] ldst_forward_matches_0_lo_lo_lo_hi = {forward_matches_0_2, forward_matches_0_1}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_lo_lo = {ldst_forward_matches_0_lo_lo_lo_hi, forward_matches_0_0}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_lo_hi_hi = {forward_matches_0_5, forward_matches_0_4}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_lo_hi = {ldst_forward_matches_0_lo_lo_hi_hi, forward_matches_0_3}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_lo_lo = {ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_lo_hi = {forward_matches_0_8, forward_matches_0_7}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_hi_lo = {ldst_forward_matches_0_lo_hi_lo_hi, forward_matches_0_6}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_hi_hi = {forward_matches_0_11, forward_matches_0_10}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_hi_hi = {ldst_forward_matches_0_lo_hi_hi_hi, forward_matches_0_9}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_lo_hi = {ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo}; // @[lsu.scala:1345:52] wire [11:0] ldst_forward_matches_0_lo = {ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_lo_hi = {forward_matches_0_14, forward_matches_0_13}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_lo_lo = {ldst_forward_matches_0_hi_lo_lo_hi, forward_matches_0_12}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_hi_hi = {forward_matches_0_17, forward_matches_0_16}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_lo_hi = {ldst_forward_matches_0_hi_lo_hi_hi, forward_matches_0_15}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_hi_lo = {ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_lo_hi = {forward_matches_0_20, forward_matches_0_19}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_hi_lo = {ldst_forward_matches_0_hi_hi_lo_hi, forward_matches_0_18}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_hi_hi = {forward_matches_0_23, forward_matches_0_22}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_hi_hi = {ldst_forward_matches_0_hi_hi_hi_hi, forward_matches_0_21}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_hi_hi = {ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo}; // @[lsu.scala:1345:52] wire [11:0] ldst_forward_matches_0_hi = {ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo}; // @[lsu.scala:1345:52] wire [23:0] _ldst_forward_matches_0_T = {ldst_forward_matches_0_hi, ldst_forward_matches_0_lo}; // @[lsu.scala:1345:52] wire [23:0] _ldst_forward_matches_0_T_1 = _ldst_forward_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1345:{52,59}] assign _ldst_forward_matches_0_T_2 = _ldst_forward_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1345:{59,82}] assign ldst_forward_matches_0 = _ldst_forward_matches_0_T_2; // @[lsu.scala:1164:34, :1345:82] wire [1:0] stld_prs2_matches_0_lo_lo_lo_hi = {prs2_matches_0_2, prs2_matches_0_1}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_lo_lo = {stld_prs2_matches_0_lo_lo_lo_hi, prs2_matches_0_0}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_lo_hi_hi = {prs2_matches_0_5, prs2_matches_0_4}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_lo_hi = {stld_prs2_matches_0_lo_lo_hi_hi, prs2_matches_0_3}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_lo_lo = {stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_lo_hi = {prs2_matches_0_8, prs2_matches_0_7}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_hi_lo = {stld_prs2_matches_0_lo_hi_lo_hi, prs2_matches_0_6}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_hi_hi = {prs2_matches_0_11, prs2_matches_0_10}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_hi_hi = {stld_prs2_matches_0_lo_hi_hi_hi, prs2_matches_0_9}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_lo_hi = {stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo}; // @[lsu.scala:1346:49] wire [11:0] stld_prs2_matches_0_lo = {stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_lo_hi = {prs2_matches_0_14, prs2_matches_0_13}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_lo_lo = {stld_prs2_matches_0_hi_lo_lo_hi, prs2_matches_0_12}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_hi_hi = {prs2_matches_0_17, prs2_matches_0_16}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_lo_hi = {stld_prs2_matches_0_hi_lo_hi_hi, prs2_matches_0_15}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_hi_lo = {stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_lo_hi = {prs2_matches_0_20, prs2_matches_0_19}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_hi_lo = {stld_prs2_matches_0_hi_hi_lo_hi, prs2_matches_0_18}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_hi_hi = {prs2_matches_0_23, prs2_matches_0_22}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_hi_hi = {stld_prs2_matches_0_hi_hi_hi_hi, prs2_matches_0_21}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_hi_hi = {stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo}; // @[lsu.scala:1346:49] wire [11:0] stld_prs2_matches_0_hi = {stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo}; // @[lsu.scala:1346:49] wire [23:0] _stld_prs2_matches_0_T = {stld_prs2_matches_0_hi, stld_prs2_matches_0_lo}; // @[lsu.scala:1346:49] wire [23:0] _stld_prs2_matches_0_T_1 = ~lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1346:58] wire [23:0] _stld_prs2_matches_0_T_2 = _stld_prs2_matches_0_T & _stld_prs2_matches_0_T_1; // @[lsu.scala:1346:{49,56,58}] assign _stld_prs2_matches_0_T_3 = _stld_prs2_matches_0_T_2 & fast_stq_valids; // @[lsu.scala:1342:35, :1346:{56,80}] assign stld_prs2_matches_0 = _stld_prs2_matches_0_T_3; // @[lsu.scala:1166:34, :1346:80] wire _stq_amos_T = stq_uop_0_is_fence \| stq_uop_0_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_0 = _stq_amos_T; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_1 = stq_uop_1_is_fence \| stq_uop_1_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_1 = _stq_amos_T_1; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_2 = stq_uop_2_is_fence \| stq_uop_2_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_2 = _stq_amos_T_2; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_3 = stq_uop_3_is_fence \| stq_uop_3_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_3 = _stq_amos_T_3; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_4 = stq_uop_4_is_fence \| stq_uop_4_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_4 = _stq_amos_T_4; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_5 = stq_uop_5_is_fence \| stq_uop_5_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_5 = _stq_amos_T_5; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_6 = stq_uop_6_is_fence \| stq_uop_6_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_6 = _stq_amos_T_6; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_7 = stq_uop_7_is_fence \| stq_uop_7_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_7 = _stq_amos_T_7; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_8 = stq_uop_8_is_fence \| stq_uop_8_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_8 = _stq_amos_T_8; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_9 = stq_uop_9_is_fence \| stq_uop_9_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_9 = _stq_amos_T_9; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_10 = stq_uop_10_is_fence \| stq_uop_10_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_10 = _stq_amos_T_10; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_11 = stq_uop_11_is_fence \| stq_uop_11_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_11 = _stq_amos_T_11; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_12 = stq_uop_12_is_fence \| stq_uop_12_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_12 = _stq_amos_T_12; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_13 = stq_uop_13_is_fence \| stq_uop_13_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_13 = _stq_amos_T_13; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_14 = stq_uop_14_is_fence \| stq_uop_14_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_14 = _stq_amos_T_14; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_15 = stq_uop_15_is_fence \| stq_uop_15_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_15 = _stq_amos_T_15; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_16 = stq_uop_16_is_fence \| stq_uop_16_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_16 = _stq_amos_T_16; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_17 = stq_uop_17_is_fence \| stq_uop_17_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_17 = _stq_amos_T_17; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_18 = stq_uop_18_is_fence \| stq_uop_18_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_18 = _stq_amos_T_18; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_19 = stq_uop_19_is_fence \| stq_uop_19_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_19 = _stq_amos_T_19; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_20 = stq_uop_20_is_fence \| stq_uop_20_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_20 = _stq_amos_T_20; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_21 = stq_uop_21_is_fence \| stq_uop_21_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_21 = _stq_amos_T_21; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_22 = stq_uop_22_is_fence \| stq_uop_22_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_22 = _stq_amos_T_22; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_23 = stq_uop_23_is_fence \| stq_uop_23_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_23 = _stq_amos_T_23; // @[lsu.scala:1349:{25,54}] wire [1:0] has_older_amo_lo_lo_lo_hi = {stq_amos_2, stq_amos_1}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_lo_lo = {has_older_amo_lo_lo_lo_hi, stq_amos_0}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_lo_hi_hi = {stq_amos_5, stq_amos_4}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_lo_hi = {has_older_amo_lo_lo_hi_hi, stq_amos_3}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_lo_lo = {has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_lo_hi_lo_hi = {stq_amos_8, stq_amos_7}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_hi_lo = {has_older_amo_lo_hi_lo_hi, stq_amos_6}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_hi_hi_hi = {stq_amos_11, stq_amos_10}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_hi_hi = {has_older_amo_lo_hi_hi_hi, stq_amos_9}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_lo_hi = {has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo}; // @[lsu.scala:1351:35] wire [11:0] has_older_amo_lo = {has_older_amo_lo_hi, has_older_amo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_lo_lo_hi = {stq_amos_14, stq_amos_13}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_lo_lo = {has_older_amo_hi_lo_lo_hi, stq_amos_12}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_lo_hi_hi = {stq_amos_17, stq_amos_16}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_lo_hi = {has_older_amo_hi_lo_hi_hi, stq_amos_15}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_hi_lo = {has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_hi_lo_hi = {stq_amos_20, stq_amos_19}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_hi_lo = {has_older_amo_hi_hi_lo_hi, stq_amos_18}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_hi_hi_hi = {stq_amos_23, stq_amos_22}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_hi_hi = {has_older_amo_hi_hi_hi_hi, stq_amos_21}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_hi_hi = {has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo}; // @[lsu.scala:1351:35] wire [11:0] has_older_amo_hi = {has_older_amo_hi_hi, has_older_amo_hi_lo}; // @[lsu.scala:1351:35] wire [23:0] _has_older_amo_T = {has_older_amo_hi, has_older_amo_lo}; // @[lsu.scala:1351:35] wire [23:0] _has_older_amo_T_1 = _has_older_amo_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1351:{35,42}] wire has_older_amo = \|_has_older_amo_T_1; // @[lsu.scala:1351:{42,65}] wire _T_1626 = do_ld_search_0 & (\|{has_older_amo, ldst_addr_matches_0}); // @[lsu.scala:321:49, :1162:34, :1351:65, :1352:{27,45,70}] reg REG_26; // @[lsu.scala:1353:20] assign io_dmem_s1_kill_0_0 = _T_1626 ? REG_26 & ~fired_load_agen_0 \| _GEN_625 \| _GEN_599 : _GEN_625 \| _GEN_599; // @[lsu.scala:211:7, :321:49, :893:24, :1235:37, :1239:34, :1278:84, :1280:{57,81}, :1281:30, :1352:{27,81}, :1353:{20,55,58,79}, :1354:42] assign s1_set_execute_0 = _T_1626 ? ~(_GEN_483 \| _GEN_601) & _GEN_575 : ~_GEN_601 & _GEN_575; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_1 = _T_1626 ? ~(_GEN_484 \| _GEN_602) & _GEN_576 : ~_GEN_602 & _GEN_576; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_2 = _T_1626 ? ~(_GEN_485 \| _GEN_603) & _GEN_577 : ~_GEN_603 & _GEN_577; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_3 = _T_1626 ? ~(_GEN_486 \| _GEN_604) & _GEN_578 : ~_GEN_604 & _GEN_578; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_4 = _T_1626 ? ~(_GEN_487 \| _GEN_605) & _GEN_579 : ~_GEN_605 & _GEN_579; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_5 = _T_1626 ? ~(_GEN_488 \| _GEN_606) & _GEN_580 : ~_GEN_606 & _GEN_580; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_6 = _T_1626 ? ~(_GEN_489 \| _GEN_607) & _GEN_581 : ~_GEN_607 & _GEN_581; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_7 = _T_1626 ? ~(_GEN_490 \| _GEN_608) & _GEN_582 : ~_GEN_608 & _GEN_582; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_8 = _T_1626 ? ~(_GEN_491 \| _GEN_609) & _GEN_583 : ~_GEN_609 & _GEN_583; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_9 = _T_1626 ? ~(_GEN_492 \| _GEN_610) & _GEN_584 : ~_GEN_610 & _GEN_584; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_10 = _T_1626 ? ~(_GEN_493 \| _GEN_611) & _GEN_585 : ~_GEN_611 & _GEN_585; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_11 = _T_1626 ? ~(_GEN_494 \| _GEN_612) & _GEN_586 : ~_GEN_612 & _GEN_586; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_12 = _T_1626 ? ~(_GEN_495 \| _GEN_613) & _GEN_587 : ~_GEN_613 & _GEN_587; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_13 = _T_1626 ? ~(_GEN_496 \| _GEN_614) & _GEN_588 : ~_GEN_614 & _GEN_588; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_14 = _T_1626 ? ~(_GEN_497 \| _GEN_615) & _GEN_589 : ~_GEN_615 & _GEN_589; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_15 = _T_1626 ? ~(_GEN_498 \| _GEN_616) & _GEN_590 : ~_GEN_616 & _GEN_590; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_16 = _T_1626 ? ~(_GEN_499 \| _GEN_617) & _GEN_591 : ~_GEN_617 & _GEN_591; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_17 = _T_1626 ? ~(_GEN_500 \| _GEN_618) & _GEN_592 : ~_GEN_618 & _GEN_592; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_18 = _T_1626 ? ~(_GEN_501 \| _GEN_619) & _GEN_593 : ~_GEN_619 & _GEN_593; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_19 = _T_1626 ? ~(_GEN_502 \| _GEN_620) & _GEN_594 : ~_GEN_620 & _GEN_594; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_20 = _T_1626 ? ~(_GEN_503 \| _GEN_621) & _GEN_595 : ~_GEN_621 & _GEN_595; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_21 = _T_1626 ? ~(_GEN_504 \| _GEN_622) & _GEN_596 : ~_GEN_622 & _GEN_596; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_22 = _T_1626 ? ~(_GEN_505 \| _GEN_623) & _GEN_597 : ~_GEN_623 & _GEN_597; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_23 = _T_1626 ? ~(_GEN_506 \| _GEN_624) & _GEN_598 : ~_GEN_624 & _GEN_598; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign kill_forward_0 = _T_1626 ? has_older_amo \| _T_1596 \| _GEN_600 : _T_1596 \| _GEN_600; // @[lsu.scala:1159:30, :1235:37, :1239:34, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1283:25, :1351:65, :1352:{27,81}, :1357:28, :1358:25] wire _wb_ldst_forward_valid_0_T = _logic_io_found_idx == _logic_1_io_found_idx; // @[lsu.scala:1377:55, :1965:23] wire _wb_ldst_forward_valid_0_T_1 = _wb_ldst_forward_valid_0_T & _logic_io_found; // @[lsu.scala:1377:{55,100}, :1965:23] wire _wb_ldst_forward_valid_0_T_2 = _wb_ldst_forward_valid_0_T_1 & _logic_1_io_found; // @[lsu.scala:1377:100, :1378:100, :1965:23] wire _wb_ldst_forward_valid_0_T_3 = ~kill_forward_0; // @[lsu.scala:1159:30, :1380:63] wire _wb_ldst_forward_valid_0_T_4 = can_forward_0 & _wb_ldst_forward_valid_0_T_3; // @[lsu.scala:321:49, :1380:{60,63}] wire _wb_ldst_forward_valid_0_T_5 = _wb_ldst_forward_valid_0_T_4 & do_ld_search_0; // @[lsu.scala:321:49, :1380:{60,80}] reg wb_ldst_forward_valid_0_REG; // @[lsu.scala:1380:44] wire _wb_ldst_forward_valid_0_T_6 = _wb_ldst_forward_valid_0_T_2 & wb_ldst_forward_valid_0_REG; // @[lsu.scala:1378:100, :1379:100, :1380:44] wire [15:0] _wb_ldst_forward_valid_0_T_7 = io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask; // @[util.scala:126:51] wire _wb_ldst_forward_valid_0_T_8 = \|_wb_ldst_forward_valid_0_T_7; // @[util.scala:126:{51,59}] wire _wb_ldst_forward_valid_0_T_9 = _wb_ldst_forward_valid_0_T_8 \| io_core_exception_0; // @[util.scala:61:61, :126:59] reg wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:45] wire _wb_ldst_forward_valid_0_T_10 = ~wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:{37,45}] assign _wb_ldst_forward_valid_0_T_11 = _wb_ldst_forward_valid_0_T_6 & _wb_ldst_forward_valid_0_T_10; // @[lsu.scala:1379:100, :1380:100, :1381:37] assign wb_ldst_forward_valid_0 = _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1172:38, :1380:100] reg REG_27; // @[lsu.scala:1394:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1399:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1399:36, :1403:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1399:36, :1403:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1403:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1403:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) \| REG_27 & ~wb_ldst_forward_valid_0; // @[lsu.scala:623:35, :1172:38, :1394:{18,49,52,79}, :1399:36, :1405:{33,43}, :1406:25] wire _mem_stld_forward_stq_idx_T = stld_prs2_matches_0[0]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_1 = stld_prs2_matches_0[1]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_2 = stld_prs2_matches_0[2]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_3 = stld_prs2_matches_0[3]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_4 = stld_prs2_matches_0[4]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_5 = stld_prs2_matches_0[5]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_6 = stld_prs2_matches_0[6]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_7 = stld_prs2_matches_0[7]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_8 = stld_prs2_matches_0[8]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_9 = stld_prs2_matches_0[9]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_10 = stld_prs2_matches_0[10]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_11 = stld_prs2_matches_0[11]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_12 = stld_prs2_matches_0[12]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_13 = stld_prs2_matches_0[13]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_14 = stld_prs2_matches_0[14]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_15 = stld_prs2_matches_0[15]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_16 = stld_prs2_matches_0[16]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_17 = stld_prs2_matches_0[17]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_18 = stld_prs2_matches_0[18]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_19 = stld_prs2_matches_0[19]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_20 = stld_prs2_matches_0[20]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_21 = stld_prs2_matches_0[21]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_22 = stld_prs2_matches_0[22]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_23 = stld_prs2_matches_0[23]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_temp_vec_T = lcam_uop_0_stq_idx == 5'h0; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_0 = _mem_stld_forward_stq_idx_T & _mem_stld_forward_stq_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_1 = lcam_uop_0_stq_idx < 5'h2; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_1 = _mem_stld_forward_stq_idx_T_1 & _mem_stld_forward_stq_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_2 = lcam_uop_0_stq_idx < 5'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_2 = _mem_stld_forward_stq_idx_T_2 & _mem_stld_forward_stq_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_3 = lcam_uop_0_stq_idx < 5'h4; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_3 = _mem_stld_forward_stq_idx_T_3 & _mem_stld_forward_stq_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_4 = lcam_uop_0_stq_idx < 5'h5; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_4 = _mem_stld_forward_stq_idx_T_4 & _mem_stld_forward_stq_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_5 = lcam_uop_0_stq_idx < 5'h6; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_5 = _mem_stld_forward_stq_idx_T_5 & _mem_stld_forward_stq_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_6 = lcam_uop_0_stq_idx < 5'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_6 = _mem_stld_forward_stq_idx_T_6 & _mem_stld_forward_stq_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_7 = lcam_uop_0_stq_idx < 5'h8; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_7 = _mem_stld_forward_stq_idx_T_7 & _mem_stld_forward_stq_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_8 = lcam_uop_0_stq_idx < 5'h9; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_8 = _mem_stld_forward_stq_idx_T_8 & _mem_stld_forward_stq_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_9 = lcam_uop_0_stq_idx < 5'hA; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_9 = _mem_stld_forward_stq_idx_T_9 & _mem_stld_forward_stq_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_10 = lcam_uop_0_stq_idx < 5'hB; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_10 = _mem_stld_forward_stq_idx_T_10 & _mem_stld_forward_stq_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_11 = lcam_uop_0_stq_idx < 5'hC; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_11 = _mem_stld_forward_stq_idx_T_11 & _mem_stld_forward_stq_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_12 = lcam_uop_0_stq_idx < 5'hD; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_12 = _mem_stld_forward_stq_idx_T_12 & _mem_stld_forward_stq_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_13 = lcam_uop_0_stq_idx < 5'hE; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_13 = _mem_stld_forward_stq_idx_T_13 & _mem_stld_forward_stq_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_14 = lcam_uop_0_stq_idx < 5'hF; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_14 = _mem_stld_forward_stq_idx_T_14 & _mem_stld_forward_stq_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_15 = ~(lcam_uop_0_stq_idx[4]); // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_15 = _mem_stld_forward_stq_idx_T_15 & _mem_stld_forward_stq_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_16 = lcam_uop_0_stq_idx < 5'h11; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_16 = _mem_stld_forward_stq_idx_T_16 & _mem_stld_forward_stq_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_17 = lcam_uop_0_stq_idx < 5'h12; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_17 = _mem_stld_forward_stq_idx_T_17 & _mem_stld_forward_stq_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_18 = lcam_uop_0_stq_idx < 5'h13; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_18 = _mem_stld_forward_stq_idx_T_18 & _mem_stld_forward_stq_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_19 = lcam_uop_0_stq_idx < 5'h14; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_19 = _mem_stld_forward_stq_idx_T_19 & _mem_stld_forward_stq_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_20 = lcam_uop_0_stq_idx < 5'h15; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_20 = _mem_stld_forward_stq_idx_T_20 & _mem_stld_forward_stq_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_21 = lcam_uop_0_stq_idx < 5'h16; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_21 = _mem_stld_forward_stq_idx_T_21 & _mem_stld_forward_stq_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_22 = lcam_uop_0_stq_idx < 5'h17; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_22 = _mem_stld_forward_stq_idx_T_22 & _mem_stld_forward_stq_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_23 = lcam_uop_0_stq_idx[4:3] != 2'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_23 = _mem_stld_forward_stq_idx_T_23 & _mem_stld_forward_stq_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _mem_stld_forward_stq_idx_idx_T = {5'h1B, ~_mem_stld_forward_stq_idx_T_22}; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_1 = _mem_stld_forward_stq_idx_T_21 ? 6'h35 : _mem_stld_forward_stq_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_2 = _mem_stld_forward_stq_idx_T_20 ? 6'h34 : _mem_stld_forward_stq_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_3 = _mem_stld_forward_stq_idx_T_19 ? 6'h33 : _mem_stld_forward_stq_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_4 = _mem_stld_forward_stq_idx_T_18 ? 6'h32 : _mem_stld_forward_stq_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_5 = _mem_stld_forward_stq_idx_T_17 ? 6'h31 : _mem_stld_forward_stq_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_6 = _mem_stld_forward_stq_idx_T_16 ? 6'h30 : _mem_stld_forward_stq_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_7 = _mem_stld_forward_stq_idx_T_15 ? 6'h2F : _mem_stld_forward_stq_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_8 = _mem_stld_forward_stq_idx_T_14 ? 6'h2E : _mem_stld_forward_stq_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_9 = _mem_stld_forward_stq_idx_T_13 ? 6'h2D : _mem_stld_forward_stq_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_10 = _mem_stld_forward_stq_idx_T_12 ? 6'h2C : _mem_stld_forward_stq_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_11 = _mem_stld_forward_stq_idx_T_11 ? 6'h2B : _mem_stld_forward_stq_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_12 = _mem_stld_forward_stq_idx_T_10 ? 6'h2A : _mem_stld_forward_stq_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_13 = _mem_stld_forward_stq_idx_T_9 ? 6'h29 : _mem_stld_forward_stq_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_14 = _mem_stld_forward_stq_idx_T_8 ? 6'h28 : _mem_stld_forward_stq_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_15 = _mem_stld_forward_stq_idx_T_7 ? 6'h27 : _mem_stld_forward_stq_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_16 = _mem_stld_forward_stq_idx_T_6 ? 6'h26 : _mem_stld_forward_stq_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_17 = _mem_stld_forward_stq_idx_T_5 ? 6'h25 : _mem_stld_forward_stq_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_18 = _mem_stld_forward_stq_idx_T_4 ? 6'h24 : _mem_stld_forward_stq_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_19 = _mem_stld_forward_stq_idx_T_3 ? 6'h23 : _mem_stld_forward_stq_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_20 = _mem_stld_forward_stq_idx_T_2 ? 6'h22 : _mem_stld_forward_stq_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_21 = _mem_stld_forward_stq_idx_T_1 ? 6'h21 : _mem_stld_forward_stq_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_22 = _mem_stld_forward_stq_idx_T ? 6'h20 : _mem_stld_forward_stq_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_23 = _mem_stld_forward_stq_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_24 = _mem_stld_forward_stq_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_25 = _mem_stld_forward_stq_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_26 = _mem_stld_forward_stq_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_27 = _mem_stld_forward_stq_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_28 = _mem_stld_forward_stq_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_29 = _mem_stld_forward_stq_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_30 = _mem_stld_forward_stq_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_31 = mem_stld_forward_stq_idx_temp_vec_23 ? 6'h17 : _mem_stld_forward_stq_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_32 = mem_stld_forward_stq_idx_temp_vec_22 ? 6'h16 : _mem_stld_forward_stq_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_33 = mem_stld_forward_stq_idx_temp_vec_21 ? 6'h15 : _mem_stld_forward_stq_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_34 = mem_stld_forward_stq_idx_temp_vec_20 ? 6'h14 : _mem_stld_forward_stq_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_35 = mem_stld_forward_stq_idx_temp_vec_19 ? 6'h13 : _mem_stld_forward_stq_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_36 = mem_stld_forward_stq_idx_temp_vec_18 ? 6'h12 : _mem_stld_forward_stq_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_37 = mem_stld_forward_stq_idx_temp_vec_17 ? 6'h11 : _mem_stld_forward_stq_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_38 = mem_stld_forward_stq_idx_temp_vec_16 ? 6'h10 : _mem_stld_forward_stq_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_39 = mem_stld_forward_stq_idx_temp_vec_15 ? 6'hF : _mem_stld_forward_stq_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_40 = mem_stld_forward_stq_idx_temp_vec_14 ? 6'hE : _mem_stld_forward_stq_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_41 = mem_stld_forward_stq_idx_temp_vec_13 ? 6'hD : _mem_stld_forward_stq_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_42 = mem_stld_forward_stq_idx_temp_vec_12 ? 6'hC : _mem_stld_forward_stq_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_43 = mem_stld_forward_stq_idx_temp_vec_11 ? 6'hB : _mem_stld_forward_stq_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_44 = mem_stld_forward_stq_idx_temp_vec_10 ? 6'hA : _mem_stld_forward_stq_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_45 = mem_stld_forward_stq_idx_temp_vec_9 ? 6'h9 : _mem_stld_forward_stq_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_46 = mem_stld_forward_stq_idx_temp_vec_8 ? 6'h8 : _mem_stld_forward_stq_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_47 = mem_stld_forward_stq_idx_temp_vec_7 ? 6'h7 : _mem_stld_forward_stq_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_48 = mem_stld_forward_stq_idx_temp_vec_6 ? 6'h6 : _mem_stld_forward_stq_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_49 = mem_stld_forward_stq_idx_temp_vec_5 ? 6'h5 : _mem_stld_forward_stq_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_50 = mem_stld_forward_stq_idx_temp_vec_4 ? 6'h4 : _mem_stld_forward_stq_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_51 = mem_stld_forward_stq_idx_temp_vec_3 ? 6'h3 : _mem_stld_forward_stq_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_52 = mem_stld_forward_stq_idx_temp_vec_2 ? 6'h2 : _mem_stld_forward_stq_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_53 = mem_stld_forward_stq_idx_temp_vec_1 ? 6'h1 : _mem_stld_forward_stq_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] mem_stld_forward_stq_idx_idx = mem_stld_forward_stq_idx_temp_vec_0 ? 6'h0 : _mem_stld_forward_stq_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_T_24 = mem_stld_forward_stq_idx_idx[4:0]; // @[Mux.scala:50:70] wire [4:0] mem_stld_forward_stq_idx_0 = _mem_stld_forward_stq_idx_T_24; // @[util.scala:354:8] wire [23:0] _mem_stld_forward_valid_T = stld_prs2_matches_0 >> mem_stld_forward_stq_idx_0; // @[lsu.scala:321:49, :1166:34, :1413:87] wire _mem_stld_forward_valid_T_1 = _mem_stld_forward_valid_T[0]; // @[lsu.scala:1413:87] wire _mem_stld_forward_valid_T_2 = do_ld_search_0 & _mem_stld_forward_valid_T_1; // @[lsu.scala:321:49, :1413:{64,87}] wire mem_stld_forward_valid_0 = _mem_stld_forward_valid_T_2; // @[lsu.scala:321:49, :1413:64] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1421:14] wire _io_core_clr_unsafe_0_valid_T = ~io_dmem_nack_0_valid_0; // @[lsu.scala:211:7, :1422:8] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_agen_0; // @[lsu.scala:321:49, :1422:61] wire _io_core_clr_unsafe_0_valid_T_2 = do_ld_search_0 & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:321:49, :1422:{58,61}] wire _io_core_clr_unsafe_0_valid_T_3 = ~io_dmem_s1_kill_0_0; // @[lsu.scala:211:7, :1422:84] wire _io_core_clr_unsafe_0_valid_T_4 = _io_core_clr_unsafe_0_valid_T_2 & _io_core_clr_unsafe_0_valid_T_3; // @[lsu.scala:1422:{58,81,84}] reg io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:114] wire _io_core_clr_unsafe_0_valid_T_5 = _io_core_clr_unsafe_0_valid_T_4 & io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:{81,104,114}] reg io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:41] wire _io_core_clr_unsafe_0_valid_T_6 = _io_core_clr_unsafe_0_valid_T & io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:{8,31,41}] wire _io_core_clr_unsafe_0_valid_T_7 = io_core_clr_unsafe_0_valid_REG \| _io_core_clr_unsafe_0_valid_T_6; // @[lsu.scala:1421:{14,32}, :1422:31] reg io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:18] wire _io_core_clr_unsafe_0_valid_T_8 = ~io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:{10,18}] assign _io_core_clr_unsafe_0_valid_T_9 = _io_core_clr_unsafe_0_valid_T_7 & _io_core_clr_unsafe_0_valid_T_8; // @[lsu.scala:1421:32, :1423:{7,10}] assign io_core_clr_unsafe_0_valid_0 = _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:211:7, :1423:7] reg [6:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1424:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:211:7, :1424:43] wire _l_idx_T = ldq_valid_0 & ldq_order_fail_0; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_1 = ldq_valid_1 & ldq_order_fail_1; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_2 = ldq_valid_2 & ldq_order_fail_2; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_3 = ldq_valid_3 & ldq_order_fail_3; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_4 = ldq_valid_4 & ldq_order_fail_4; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_5 = ldq_valid_5 & ldq_order_fail_5; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_6 = ldq_valid_6 & ldq_order_fail_6; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_7 = ldq_valid_7 & ldq_order_fail_7; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_8 = ldq_valid_8 & ldq_order_fail_8; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_9 = ldq_valid_9 & ldq_order_fail_9; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_10 = ldq_valid_10 & ldq_order_fail_10; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_11 = ldq_valid_11 & ldq_order_fail_11; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_12 = ldq_valid_12 & ldq_order_fail_12; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_13 = ldq_valid_13 & ldq_order_fail_13; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_14 = ldq_valid_14 & ldq_order_fail_14; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_15 = ldq_valid_15 & ldq_order_fail_15; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_16 = ldq_valid_16 & ldq_order_fail_16; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_17 = ldq_valid_17 & ldq_order_fail_17; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_18 = ldq_valid_18 & ldq_order_fail_18; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_19 = ldq_valid_19 & ldq_order_fail_19; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_20 = ldq_valid_20 & ldq_order_fail_20; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_21 = ldq_valid_21 & ldq_order_fail_21; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_22 = ldq_valid_22 & ldq_order_fail_22; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_23 = ldq_valid_23 & ldq_order_fail_23; // @[lsu.scala:218:36, :225:36, :1429:82] wire l_idx_temp_vec_0 = _l_idx_T & _l_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_1 = _l_idx_T_1 & _l_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_2 = _l_idx_T_2 & _l_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_3 = _l_idx_T_3 & _l_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_4 = _l_idx_T_4 & _l_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_5 = _l_idx_T_5 & _l_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_6 = _l_idx_T_6 & _l_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_7 = _l_idx_T_7 & _l_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_8 = _l_idx_T_8 & _l_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_9 = _l_idx_T_9 & _l_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_10 = _l_idx_T_10 & _l_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_11 = _l_idx_T_11 & _l_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_12 = _l_idx_T_12 & _l_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_13 = _l_idx_T_13 & _l_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_14 = _l_idx_T_14 & _l_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _l_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire l_idx_temp_vec_15 = _l_idx_T_15 & _l_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_16 = _l_idx_T_16 & _l_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_17 = _l_idx_T_17 & _l_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_18 = _l_idx_T_18 & _l_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_19 = _l_idx_T_19 & _l_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_20 = _l_idx_T_20 & _l_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_21 = _l_idx_T_21 & _l_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_22 = _l_idx_T_22 & _l_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_23 = _l_idx_T_23 & _l_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _l_idx_idx_T = {5'h1B, ~_l_idx_T_22}; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_1 = _l_idx_T_21 ? 6'h35 : _l_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_2 = _l_idx_T_20 ? 6'h34 : _l_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_3 = _l_idx_T_19 ? 6'h33 : _l_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_4 = _l_idx_T_18 ? 6'h32 : _l_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_5 = _l_idx_T_17 ? 6'h31 : _l_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_6 = _l_idx_T_16 ? 6'h30 : _l_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_7 = _l_idx_T_15 ? 6'h2F : _l_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_8 = _l_idx_T_14 ? 6'h2E : _l_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_9 = _l_idx_T_13 ? 6'h2D : _l_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_10 = _l_idx_T_12 ? 6'h2C : _l_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_11 = _l_idx_T_11 ? 6'h2B : _l_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_12 = _l_idx_T_10 ? 6'h2A : _l_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_13 = _l_idx_T_9 ? 6'h29 : _l_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_14 = _l_idx_T_8 ? 6'h28 : _l_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_15 = _l_idx_T_7 ? 6'h27 : _l_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_16 = _l_idx_T_6 ? 6'h26 : _l_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_17 = _l_idx_T_5 ? 6'h25 : _l_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_18 = _l_idx_T_4 ? 6'h24 : _l_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_19 = _l_idx_T_3 ? 6'h23 : _l_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_20 = _l_idx_T_2 ? 6'h22 : _l_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_21 = _l_idx_T_1 ? 6'h21 : _l_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_22 = _l_idx_T ? 6'h20 : _l_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_23 = _l_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_24 = _l_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_25 = _l_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_26 = _l_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_27 = _l_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_28 = _l_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_29 = _l_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_30 = _l_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_31 = l_idx_temp_vec_23 ? 6'h17 : _l_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_32 = l_idx_temp_vec_22 ? 6'h16 : _l_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_33 = l_idx_temp_vec_21 ? 6'h15 : _l_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_34 = l_idx_temp_vec_20 ? 6'h14 : _l_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_35 = l_idx_temp_vec_19 ? 6'h13 : _l_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_36 = l_idx_temp_vec_18 ? 6'h12 : _l_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_37 = l_idx_temp_vec_17 ? 6'h11 : _l_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_38 = l_idx_temp_vec_16 ? 6'h10 : _l_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_39 = l_idx_temp_vec_15 ? 6'hF : _l_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_40 = l_idx_temp_vec_14 ? 6'hE : _l_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_41 = l_idx_temp_vec_13 ? 6'hD : _l_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_42 = l_idx_temp_vec_12 ? 6'hC : _l_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_43 = l_idx_temp_vec_11 ? 6'hB : _l_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_44 = l_idx_temp_vec_10 ? 6'hA : _l_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_45 = l_idx_temp_vec_9 ? 6'h9 : _l_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_46 = l_idx_temp_vec_8 ? 6'h8 : _l_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_47 = l_idx_temp_vec_7 ? 6'h7 : _l_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_48 = l_idx_temp_vec_6 ? 6'h6 : _l_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_49 = l_idx_temp_vec_5 ? 6'h5 : _l_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_50 = l_idx_temp_vec_4 ? 6'h4 : _l_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_51 = l_idx_temp_vec_3 ? 6'h3 : _l_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_52 = l_idx_temp_vec_2 ? 6'h2 : _l_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_53 = l_idx_temp_vec_1 ? 6'h1 : _l_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] l_idx_idx = l_idx_temp_vec_0 ? 6'h0 : _l_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] l_idx = l_idx_idx[4:0]; // @[Mux.scala:50:70] reg r_xcpt_valid; // @[lsu.scala:1434:29] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:211:7, :1435:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_0_0 = r_xcpt_uop_iq_type_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_1_0 = r_xcpt_uop_iq_type_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_2_0 = r_xcpt_uop_iq_type_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_3_0 = r_xcpt_uop_iq_type_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_0_0 = r_xcpt_uop_fu_code_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_1_0 = r_xcpt_uop_fu_code_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_2_0 = r_xcpt_uop_fu_code_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_3_0 = r_xcpt_uop_fu_code_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_4; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_4_0 = r_xcpt_uop_fu_code_4; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_5; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_5_0 = r_xcpt_uop_fu_code_5; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_6; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_6_0 = r_xcpt_uop_fu_code_6; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_7; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_7_0 = r_xcpt_uop_fu_code_7; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_8; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_8_0 = r_xcpt_uop_fu_code_8; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_9; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_9_0 = r_xcpt_uop_fu_code_9; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_0 = r_xcpt_uop_iw_issued; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_agen_0 = r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0 = r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_speculative_child_0 = r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_speculative_child_0 = r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0 = r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0 = r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0 = r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_dis_col_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dis_col_sel_0 = r_xcpt_uop_dis_col_sel; // @[lsu.scala:211:7, :1435:25] reg [15:0] r_xcpt_uop_br_mask; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_type; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_type_0 = r_xcpt_uop_br_type; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfence_0 = r_xcpt_uop_is_sfence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_eret; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_eret_0 = r_xcpt_uop_is_eret; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rocc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rocc_0 = r_xcpt_uop_is_rocc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_mov; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_mov_0 = r_xcpt_uop_is_mov; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_taken; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_imm_rename; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_rename_0 = r_xcpt_uop_imm_rename; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_imm_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_sel_0 = r_xcpt_uop_imm_sel; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_pimm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pimm_0 = r_xcpt_uop_pimm; // @[lsu.scala:211:7, :1435:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_op1_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op1_sel_0 = r_xcpt_uop_op1_sel; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_op2_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op2_sel_0 = r_xcpt_uop_op2_sel; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ldst_0 = r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wen_0 = r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren1_0 = r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren2_0 = r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren3_0 = r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap12_0 = r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap23_0 = r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fromint_0 = r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_toint_0 = r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fma_0 = r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_div_0 = r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0 = r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wflags_0 = r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_vec_0 = r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_exception; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:211:7, :1435:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_csr_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_csr_cmd_0 = r_xcpt_uop_csr_cmd; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fcn_dw; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_dw_0 = r_xcpt_uop_fcn_dw; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_fcn_op; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_op_0 = r_xcpt_uop_fcn_op; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_fp_rm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_rm_0 = r_xcpt_uop_fp_rm; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_typ; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_typ_0 = r_xcpt_uop_fp_typ; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:211:7, :1435:25] wire [1:0] ld_xcpt_valid_lo_lo_lo_hi = {ldq_order_fail_2, ldq_order_fail_1}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_lo_lo = {ld_xcpt_valid_lo_lo_lo_hi, ldq_order_fail_0}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_lo_hi_hi = {ldq_order_fail_5, ldq_order_fail_4}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_lo_hi = {ld_xcpt_valid_lo_lo_hi_hi, ldq_order_fail_3}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_lo_lo = {ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_lo_hi_lo_hi = {ldq_order_fail_8, ldq_order_fail_7}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_hi_lo = {ld_xcpt_valid_lo_hi_lo_hi, ldq_order_fail_6}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_hi_hi_hi = {ldq_order_fail_11, ldq_order_fail_10}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_hi_hi = {ld_xcpt_valid_lo_hi_hi_hi, ldq_order_fail_9}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_lo_hi = {ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo}; // @[lsu.scala:1437:39] wire [11:0] ld_xcpt_valid_lo = {ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_lo_lo_hi = {ldq_order_fail_14, ldq_order_fail_13}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_lo_lo = {ld_xcpt_valid_hi_lo_lo_hi, ldq_order_fail_12}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_lo_hi_hi = {ldq_order_fail_17, ldq_order_fail_16}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_lo_hi = {ld_xcpt_valid_hi_lo_hi_hi, ldq_order_fail_15}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_hi_lo = {ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_hi_lo_hi = {ldq_order_fail_20, ldq_order_fail_19}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_hi_lo = {ld_xcpt_valid_hi_hi_lo_hi, ldq_order_fail_18}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_hi_hi_hi = {ldq_order_fail_23, ldq_order_fail_22}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_hi_hi = {ld_xcpt_valid_hi_hi_hi_hi, ldq_order_fail_21}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_hi_hi = {ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo}; // @[lsu.scala:1437:39] wire [11:0] ld_xcpt_valid_hi = {ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo}; // @[lsu.scala:1437:39] wire [23:0] _ld_xcpt_valid_T = {ld_xcpt_valid_hi, ld_xcpt_valid_lo}; // @[lsu.scala:1437:39] wire [2:0] ld_xcpt_valid_lo_lo_lo_1 = {ld_xcpt_valid_lo_lo_lo_hi_1, ldq_valid_0}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_lo_lo_hi_1 = {ld_xcpt_valid_lo_lo_hi_hi_1, ldq_valid_3}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_lo_lo_1 = {ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_lo_hi_lo_1 = {ld_xcpt_valid_lo_hi_lo_hi_1, ldq_valid_6}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_lo_hi_hi_1 = {ld_xcpt_valid_lo_hi_hi_hi_1, ldq_valid_9}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_lo_hi_1 = {ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1}; // @[lsu.scala:1437:58] wire [11:0] ld_xcpt_valid_lo_1 = {ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_hi_lo_lo_1 = {ld_xcpt_valid_hi_lo_lo_hi_1, ldq_valid_12}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_hi_lo_hi_1 = {ld_xcpt_valid_hi_lo_hi_hi_1, ldq_valid_15}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_hi_lo_1 = {ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_hi_hi_lo_1 = {ld_xcpt_valid_hi_hi_lo_hi_1, ldq_valid_18}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_hi_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_hi_1, ldq_valid_21}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1}; // @[lsu.scala:1437:58] wire [11:0] ld_xcpt_valid_hi_1 = {ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1}; // @[lsu.scala:1437:58] wire [23:0] _ld_xcpt_valid_T_1 = {ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1}; // @[lsu.scala:1437:58] wire [23:0] _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T & _ld_xcpt_valid_T_1; // @[lsu.scala:1437:{39,46,58}] wire ld_xcpt_valid = \|_ld_xcpt_valid_T_2; // @[lsu.scala:1437:{46,66}] wire _ld_xcpt_uop_T = l_idx > 5'h17; // @[util.scala:354:8] wire [5:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 6'h18; // @[util.scala:354:8] wire [4:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[4:0]; // @[lsu.scala:1438:76] wire [4:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[util.scala:354:8] wire ld_xcpt_uop_iq_type_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_4; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_5; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_6; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_7; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_8; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_9; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_inst; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_debug_inst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rvc; // @[lsu.scala:1438:31] wire [39:0] ld_xcpt_uop_debug_pc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_dis_col_sel; // @[lsu.scala:1438:31] wire [15:0] ld_xcpt_uop_br_mask; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_tag; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_type; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfb; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fencei; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_amo; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_eret; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rocc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_mov; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ftq_idx; // @[lsu.scala:1438:31] wire ld_xcpt_uop_edge_inst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_pc_lob; // @[lsu.scala:1438:31] wire ld_xcpt_uop_taken; // @[lsu.scala:1438:31] wire ld_xcpt_uop_imm_rename; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_imm_sel; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_pimm; // @[lsu.scala:1438:31] wire [19:0] ld_xcpt_uop_imm_packed; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_op1_sel; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_op2_sel; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_rob_idx; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ldq_idx; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_stq_idx; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_rxq_idx; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_pdst; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs1; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs2; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs3; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ppred; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs1_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs2_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs3_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ppred_busy; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_stale_pdst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_exception; // @[lsu.scala:1438:31] wire [63:0] ld_xcpt_uop_exc_cause; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_mem_cmd; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_mem_size; // @[lsu.scala:1438:31] wire ld_xcpt_uop_mem_signed; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_ldq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_stq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_unique; // @[lsu.scala:1438:31] wire ld_xcpt_uop_flush_on_commit; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_csr_cmd; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_ldst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs2; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs3; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dst_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:1438:31] wire ld_xcpt_uop_frs3_en; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fcn_dw; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_fcn_op; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_val; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_fp_rm; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_typ; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_debug_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_fsrc; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_tsrc; // @[lsu.scala:1438:31] assign ld_xcpt_uop_inst = _GEN_127[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_inst = _GEN_128[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_rvc = _GEN_129[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_pc = _GEN_130[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_0 = _GEN_131[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_1 = _GEN_132[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_2 = _GEN_133[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_3 = _GEN_134[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_0 = _GEN_135[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_1 = _GEN_136[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_2 = _GEN_137[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_3 = _GEN_138[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_4 = _GEN_139[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_5 = _GEN_140[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_6 = _GEN_141[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_7 = _GEN_142[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_8 = _GEN_143[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_9 = _GEN_144[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued = _GEN_145[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued_partial_agen = _GEN_146[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued_partial_dgen = _GEN_147[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p1_speculative_child = _GEN_148[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p2_speculative_child = _GEN_149[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p1_bypass_hint = _GEN_150[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p2_bypass_hint = _GEN_151[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p3_bypass_hint = _GEN_152[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_dis_col_sel = _GEN_153[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_mask = _GEN_154[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_tag = _GEN_155[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_type = _GEN_156[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sfb = _GEN_157[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_fence = _GEN_158[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_fencei = _GEN_159[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sfence = _GEN_160[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_amo = _GEN_161[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_eret = _GEN_162[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sys_pc2epc = _GEN_163[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_rocc = _GEN_164[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_mov = _GEN_165[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ftq_idx = _GEN_166[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_edge_inst = _GEN_167[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pc_lob = _GEN_168[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_taken = _GEN_169[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_rename = _GEN_170[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_sel = _GEN_171[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pimm = _GEN_172[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_packed = _GEN_173[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_op1_sel = _GEN_174[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_op2_sel = _GEN_175[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ldst = _GEN_176[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_wen = _GEN_177[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren1 = _GEN_178[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren2 = _GEN_179[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren3 = _GEN_180[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_swap12 = _GEN_181[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_swap23 = _GEN_182[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_typeTagIn = _GEN_183[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_typeTagOut = _GEN_184[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fromint = _GEN_185[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_toint = _GEN_186[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fastpipe = _GEN_187[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fma = _GEN_188[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_div = _GEN_189[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_sqrt = _GEN_190[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_wflags = _GEN_191[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_vec = _GEN_192[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_rob_idx = _GEN_193[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldq_idx = _GEN_194[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_stq_idx = _GEN_195[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_rxq_idx = _GEN_196[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pdst = _GEN_197[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs1 = _GEN_198[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs2 = _GEN_199[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs3 = _GEN_200[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ppred = _GEN_201[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs1_busy = _GEN_202[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs2_busy = _GEN_203[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs3_busy = _GEN_204[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ppred_busy = _GEN_205[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_stale_pdst = _GEN_206[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_exception = _GEN_207[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_exc_cause = _GEN_208[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_cmd = _GEN_209[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_size = _GEN_210[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_signed = _GEN_211[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_uses_ldq = _GEN_212[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_uses_stq = _GEN_213[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_unique = _GEN_214[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_flush_on_commit = _GEN_215[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_csr_cmd = _GEN_216[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldst_is_rs1 = _GEN_217[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldst = _GEN_218[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs1 = _GEN_219[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs2 = _GEN_220[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs3 = _GEN_221[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_dst_rtype = _GEN_222[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs1_rtype = _GEN_223[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs2_rtype = _GEN_224[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_frs3_en = _GEN_225[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fcn_dw = _GEN_226[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fcn_op = _GEN_227[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_val = _GEN_228[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_rm = _GEN_229[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_typ = _GEN_230[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_pf_if = _GEN_231[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_ae_if = _GEN_232[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_ma_if = _GEN_233[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_bp_debug_if = _GEN_234[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_bp_xcpt_if = _GEN_235[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_fsrc = _GEN_236[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_tsrc = _GEN_237[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < ld_xcpt_uop_rob_idx; // @[util.scala:364:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:364:{52,58,64}] wire _use_mem_xcpt_T_3 = ld_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:78] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:364:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:364:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1437:66, :1440:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 \| _use_mem_xcpt_T_6; // @[lsu.scala:1440:{38,115,118}] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : ld_xcpt_uop_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : ld_xcpt_uop_debug_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : ld_xcpt_uop_is_rvc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : ld_xcpt_uop_debug_pc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_0 = use_mem_xcpt ? mem_xcpt_uop_iq_type_0 : ld_xcpt_uop_iq_type_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_1 = use_mem_xcpt ? mem_xcpt_uop_iq_type_1 : ld_xcpt_uop_iq_type_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_2 = use_mem_xcpt ? mem_xcpt_uop_iq_type_2 : ld_xcpt_uop_iq_type_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_3 = use_mem_xcpt ? mem_xcpt_uop_iq_type_3 : ld_xcpt_uop_iq_type_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_0 = use_mem_xcpt ? mem_xcpt_uop_fu_code_0 : ld_xcpt_uop_fu_code_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_1 = use_mem_xcpt ? mem_xcpt_uop_fu_code_1 : ld_xcpt_uop_fu_code_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_2 = use_mem_xcpt ? mem_xcpt_uop_fu_code_2 : ld_xcpt_uop_fu_code_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_3 = use_mem_xcpt ? mem_xcpt_uop_fu_code_3 : ld_xcpt_uop_fu_code_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_4 = use_mem_xcpt ? mem_xcpt_uop_fu_code_4 : ld_xcpt_uop_fu_code_4; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_5 = use_mem_xcpt ? mem_xcpt_uop_fu_code_5 : ld_xcpt_uop_fu_code_5; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_6 = use_mem_xcpt ? mem_xcpt_uop_fu_code_6 : ld_xcpt_uop_fu_code_6; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_7 = use_mem_xcpt ? mem_xcpt_uop_fu_code_7 : ld_xcpt_uop_fu_code_7; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_8 = use_mem_xcpt ? mem_xcpt_uop_fu_code_8 : ld_xcpt_uop_fu_code_8; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_9 = use_mem_xcpt ? mem_xcpt_uop_fu_code_9 : ld_xcpt_uop_fu_code_9; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued = use_mem_xcpt ? mem_xcpt_uop_iw_issued : ld_xcpt_uop_iw_issued; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_agen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_agen : ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_dgen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_dgen : ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_iw_p1_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p1_speculative_child : ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_iw_p2_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p2_speculative_child : ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p1_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p1_bypass_hint : ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p2_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p2_bypass_hint : ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p3_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p3_bypass_hint : ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_dis_col_sel = use_mem_xcpt ? mem_xcpt_uop_dis_col_sel : ld_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [15:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : ld_xcpt_uop_br_mask; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : ld_xcpt_uop_br_tag; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_type = use_mem_xcpt ? mem_xcpt_uop_br_type : ld_xcpt_uop_br_type; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : ld_xcpt_uop_is_sfb; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : ld_xcpt_uop_is_fence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : ld_xcpt_uop_is_fencei; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfence = use_mem_xcpt ? mem_xcpt_uop_is_sfence : ld_xcpt_uop_is_sfence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : ld_xcpt_uop_is_amo; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_eret = use_mem_xcpt ? mem_xcpt_uop_is_eret : ld_xcpt_uop_is_eret; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rocc = use_mem_xcpt ? mem_xcpt_uop_is_rocc : ld_xcpt_uop_is_rocc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_mov = use_mem_xcpt ? mem_xcpt_uop_is_mov : ld_xcpt_uop_is_mov; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : ld_xcpt_uop_ftq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : ld_xcpt_uop_edge_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : ld_xcpt_uop_pc_lob; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : ld_xcpt_uop_taken; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_imm_rename = use_mem_xcpt ? mem_xcpt_uop_imm_rename : ld_xcpt_uop_imm_rename; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_imm_sel = use_mem_xcpt ? mem_xcpt_uop_imm_sel : ld_xcpt_uop_imm_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_pimm = use_mem_xcpt ? mem_xcpt_uop_pimm : ld_xcpt_uop_pimm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : ld_xcpt_uop_imm_packed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_op1_sel = use_mem_xcpt ? mem_xcpt_uop_op1_sel : ld_xcpt_uop_op1_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_op2_sel = use_mem_xcpt ? mem_xcpt_uop_op2_sel : ld_xcpt_uop_op2_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ldst = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ldst : ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wen = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wen : ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren1 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren1 : ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren2 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren2 : ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren3 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren3 : ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap12 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap12 : ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap23 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap23 : ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagIn = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagIn : ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagOut = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagOut : ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fromint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fromint : ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_toint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_toint : ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fastpipe = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fastpipe : ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fma = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fma : ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_div = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_div : ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_sqrt = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_sqrt : ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wflags = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wflags : ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_vec = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_vec : ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : ld_xcpt_uop_rob_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : ld_xcpt_uop_ldq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : ld_xcpt_uop_stq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : ld_xcpt_uop_rxq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : ld_xcpt_uop_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : ld_xcpt_uop_prs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : ld_xcpt_uop_prs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : ld_xcpt_uop_prs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : ld_xcpt_uop_ppred; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : ld_xcpt_uop_prs1_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : ld_xcpt_uop_prs2_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : ld_xcpt_uop_prs3_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ppred_busy = use_mem_xcpt ? mem_xcpt_uop_ppred_busy : ld_xcpt_uop_ppred_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : ld_xcpt_uop_stale_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : ld_xcpt_uop_exception; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : ld_xcpt_uop_exc_cause; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : ld_xcpt_uop_mem_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : ld_xcpt_uop_mem_size; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : ld_xcpt_uop_mem_signed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : ld_xcpt_uop_uses_ldq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : ld_xcpt_uop_uses_stq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : ld_xcpt_uop_is_unique; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : ld_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_csr_cmd : ld_xcpt_uop_csr_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : ld_xcpt_uop_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : ld_xcpt_uop_lrs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : ld_xcpt_uop_lrs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : ld_xcpt_uop_lrs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : ld_xcpt_uop_dst_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : ld_xcpt_uop_frs3_en; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_fcn_dw : ld_xcpt_uop_fcn_dw; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_fcn_op = use_mem_xcpt ? mem_xcpt_uop_fcn_op : ld_xcpt_uop_fcn_op; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : ld_xcpt_uop_fp_val; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_fp_rm = use_mem_xcpt ? mem_xcpt_uop_fp_rm : ld_xcpt_uop_fp_rm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_typ = use_mem_xcpt ? mem_xcpt_uop_fp_typ : ld_xcpt_uop_fp_typ; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : ld_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : ld_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : ld_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire _r_xcpt_valid_T = ld_xcpt_valid \| mem_xcpt_valid; // @[lsu.scala:457:29, :1437:66, :1444:34] wire [15:0] _r_xcpt_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:126:51] wire _r_xcpt_valid_T_2 = \|_r_xcpt_valid_T_1; // @[util.scala:126:{51,59}] wire _r_xcpt_valid_T_3 = _r_xcpt_valid_T_2 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _r_xcpt_valid_T_4 = ~_r_xcpt_valid_T_3; // @[util.scala:61:61] wire _r_xcpt_valid_T_5 = _r_xcpt_valid_T & _r_xcpt_valid_T_4; // @[lsu.scala:1444:{34,53,56}] wire [15:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [15:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:93:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:458:29, :1440:115, :1447:28] wire [15:0] _io_core_lxcpt_valid_T = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:126:51] wire _io_core_lxcpt_valid_T_1 = \|_io_core_lxcpt_valid_T; // @[util.scala:126:{51,59}] wire _io_core_lxcpt_valid_T_2 = _io_core_lxcpt_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_lxcpt_valid_T_3 = ~_io_core_lxcpt_valid_T_2; // @[util.scala:61:61] assign _io_core_lxcpt_valid_T_4 = r_xcpt_valid & _io_core_lxcpt_valid_T_3; // @[lsu.scala:1434:29, :1450:{39,42}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_4; // @[lsu.scala:211:7, :1450:39] reg wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:1458:47] wire _wakeupArbs_0_io_in_1_valid_T = fired_load_agen_exec_0 & wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:321:49, :1457:69, :1458:47] wire _wakeupArbs_0_io_in_1_valid_T_2 = _wakeupArbs_0_io_in_1_valid_T; // @[lsu.scala:1457:69, :1458:69] wire _wakeupArbs_0_io_in_1_valid_T_3 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37, :1460:40] wire _wakeupArbs_0_io_in_1_valid_T_4 = _wakeupArbs_0_io_in_1_valid_T_2 & _wakeupArbs_0_io_in_1_valid_T_3; // @[lsu.scala:1458:69, :1459:69, :1460:40] wire [31:0] io_core_iresp_0_out_bits_uop_inst = iresp_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] io_core_iresp_0_out_bits_uop_debug_inst = iresp_0_bits_uop_debug_inst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rvc = iresp_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] io_core_iresp_0_out_bits_uop_debug_pc = iresp_0_bits_uop_debug_pc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_0 = iresp_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_1 = iresp_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_2 = iresp_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_3 = iresp_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_0 = iresp_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_1 = iresp_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_2 = iresp_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_3 = iresp_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_4 = iresp_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_5 = iresp_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_6 = iresp_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_7 = iresp_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_8 = iresp_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_9 = iresp_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued = iresp_0_bits_uop_iw_issued; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_agen = iresp_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_dgen = iresp_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_iw_p1_speculative_child = iresp_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_iw_p2_speculative_child = iresp_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p1_bypass_hint = iresp_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p2_bypass_hint = iresp_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p3_bypass_hint = iresp_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_dis_col_sel = iresp_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_tag = iresp_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_type = iresp_0_bits_uop_br_type; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfb = iresp_0_bits_uop_is_sfb; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fence = iresp_0_bits_uop_is_fence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fencei = iresp_0_bits_uop_is_fencei; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfence = iresp_0_bits_uop_is_sfence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_amo = iresp_0_bits_uop_is_amo; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_eret = iresp_0_bits_uop_is_eret; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sys_pc2epc = iresp_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rocc = iresp_0_bits_uop_is_rocc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_mov = iresp_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ftq_idx = iresp_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_edge_inst = iresp_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_pc_lob = iresp_0_bits_uop_pc_lob; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_taken = iresp_0_bits_uop_taken; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_imm_rename = iresp_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_imm_sel = iresp_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_pimm = iresp_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] io_core_iresp_0_out_bits_uop_imm_packed = iresp_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_op1_sel = iresp_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_op2_sel = iresp_0_bits_uop_op2_sel; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ldst = iresp_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wen = iresp_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren1 = iresp_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren2 = iresp_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren3 = iresp_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap12 = iresp_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap23 = iresp_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagIn = iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagOut = iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fromint = iresp_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_toint = iresp_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fastpipe = iresp_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fma = iresp_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_div = iresp_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_sqrt = iresp_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wflags = iresp_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_vec = iresp_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_rob_idx = iresp_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ldq_idx = iresp_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_stq_idx = iresp_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_rxq_idx = iresp_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_pdst = iresp_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs1 = iresp_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs2 = iresp_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs3 = iresp_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ppred = iresp_0_bits_uop_ppred; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs1_busy = iresp_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs2_busy = iresp_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs3_busy = iresp_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ppred_busy = iresp_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_stale_pdst = iresp_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_exception = iresp_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_uop_exc_cause = iresp_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_mem_cmd = iresp_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_mem_size = iresp_0_bits_uop_mem_size; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_mem_signed = iresp_0_bits_uop_mem_signed; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_ldq = iresp_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_stq = iresp_0_bits_uop_uses_stq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_unique = iresp_0_bits_uop_is_unique; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_flush_on_commit = iresp_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_csr_cmd = iresp_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ldst_is_rs1 = iresp_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_ldst = iresp_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs1 = iresp_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs2 = iresp_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs3 = iresp_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dst_rtype = iresp_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs1_rtype = iresp_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs2_rtype = iresp_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_frs3_en = iresp_0_bits_uop_frs3_en; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fcn_dw = iresp_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_fcn_op = iresp_0_bits_uop_fcn_op; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_val = iresp_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_fp_rm = iresp_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_typ = iresp_0_bits_uop_fp_typ; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_pf_if = iresp_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ae_if = iresp_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ma_if = iresp_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_debug_if = iresp_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_xcpt_if = iresp_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_fsrc = iresp_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_tsrc = iresp_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_data = iresp_0_bits_data; // @[util.scala:114:23] wire [15:0] iresp_0_bits_uop_br_mask; // @[lsu.scala:1477:19] wire iresp_0_valid; // @[lsu.scala:1477:19] assign io_core_fresp_0_valid_0 = fresp_0_valid; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_inst_0 = fresp_0_bits_uop_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_inst_0 = fresp_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rvc_0 = fresp_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_pc_0 = fresp_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_0_0 = fresp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_1_0 = fresp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_2_0 = fresp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_3_0 = fresp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_0_0 = fresp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_1_0 = fresp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_2_0 = fresp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_3_0 = fresp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_4_0 = fresp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_5_0 = fresp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_6_0 = fresp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_7_0 = fresp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_8_0 = fresp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_9_0 = fresp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_0 = fresp_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_agen_0 = fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0 = fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_speculative_child_0 = fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_speculative_child_0 = fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0 = fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0 = fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0 = fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dis_col_sel_0 = fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_mask_0 = fresp_0_bits_uop_br_mask; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_tag_0 = fresp_0_bits_uop_br_tag; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_type_0 = fresp_0_bits_uop_br_type; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfb_0 = fresp_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fence_0 = fresp_0_bits_uop_is_fence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fencei_0 = fresp_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfence_0 = fresp_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_amo_0 = fresp_0_bits_uop_is_amo; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_eret_0 = fresp_0_bits_uop_is_eret; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sys_pc2epc_0 = fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rocc_0 = fresp_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_mov_0 = fresp_0_bits_uop_is_mov; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ftq_idx_0 = fresp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_edge_inst_0 = fresp_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pc_lob_0 = fresp_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_taken_0 = fresp_0_bits_uop_taken; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_rename_0 = fresp_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_sel_0 = fresp_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pimm_0 = fresp_0_bits_uop_pimm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_packed_0 = fresp_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op1_sel_0 = fresp_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op2_sel_0 = fresp_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ldst_0 = fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wen_0 = fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren1_0 = fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren2_0 = fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren3_0 = fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap12_0 = fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap23_0 = fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fromint_0 = fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_toint_0 = fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fma_0 = fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_div_0 = fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0 = fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wflags_0 = fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_vec_0 = fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rob_idx_0 = fresp_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldq_idx_0 = fresp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stq_idx_0 = fresp_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rxq_idx_0 = fresp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pdst_0 = fresp_0_bits_uop_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_0 = fresp_0_bits_uop_prs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_0 = fresp_0_bits_uop_prs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_0 = fresp_0_bits_uop_prs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_0 = fresp_0_bits_uop_ppred; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_busy_0 = fresp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_busy_0 = fresp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_busy_0 = fresp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_busy_0 = fresp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stale_pdst_0 = fresp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exception_0 = fresp_0_bits_uop_exception; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exc_cause_0 = fresp_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_cmd_0 = fresp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_size_0 = fresp_0_bits_uop_mem_size; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_signed_0 = fresp_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_ldq_0 = fresp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_stq_0 = fresp_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_unique_0 = fresp_0_bits_uop_is_unique; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_flush_on_commit_0 = fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_csr_cmd_0 = fresp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_is_rs1_0 = fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_0 = fresp_0_bits_uop_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_0 = fresp_0_bits_uop_lrs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_0 = fresp_0_bits_uop_lrs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs3_0 = fresp_0_bits_uop_lrs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dst_rtype_0 = fresp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_rtype_0 = fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_rtype_0 = fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_frs3_en_0 = fresp_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_dw_0 = fresp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_op_0 = fresp_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_val_0 = fresp_0_bits_uop_fp_val; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_rm_0 = fresp_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_typ_0 = fresp_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_pf_if_0 = fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ae_if_0 = fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ma_if_0 = fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_debug_if_0 = fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_xcpt_if_0 = fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_fsrc_0 = fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_tsrc_0 = fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_data_0 = fresp_0_bits_data; // @[lsu.scala:211:7, :1478:19] wire _io_core_iresp_0_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] io_core_iresp_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire io_core_iresp_0_out_valid; // @[util.scala:114:23] wire [15:0] _io_core_iresp_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _io_core_iresp_0_out_bits_uop_br_mask_T_1 = iresp_0_bits_uop_br_mask & _io_core_iresp_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign io_core_iresp_0_out_bits_uop_br_mask = _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _io_core_iresp_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & iresp_0_bits_uop_br_mask; // @[util.scala:126:51] wire _io_core_iresp_0_out_valid_T_1 = \|_io_core_iresp_0_out_valid_T; // @[util.scala:126:{51,59}] wire _io_core_iresp_0_out_valid_T_2 = _io_core_iresp_0_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_iresp_0_out_valid_T_3 = ~_io_core_iresp_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _io_core_iresp_0_out_valid_T_4 = iresp_0_valid & _io_core_iresp_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign io_core_iresp_0_out_valid = _io_core_iresp_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg io_core_iresp_0_REG_valid; // @[lsu.scala:1485:70] assign io_core_iresp_0_valid_0 = io_core_iresp_0_REG_valid; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_inst_0 = io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_inst_0 = io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rvc_0 = io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:211:7, :1485:70] reg [39:0] io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_pc_0 = io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_0_0 = io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_1_0 = io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_2_0 = io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_3_0 = io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_0_0 = io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_1_0 = io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_2_0 = io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_3_0 = io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_4_0 = io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_5_0 = io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_6_0 = io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_7_0 = io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_8_0 = io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_9_0 = io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_0 = io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dis_col_sel_0 = io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1485:70] reg [15:0] io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_mask_0 = io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_tag_0 = io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_type_0 = io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfb_0 = io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fence_0 = io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fencei_0 = io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfence_0 = io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_amo_0 = io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_eret_0 = io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sys_pc2epc_0 = io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rocc_0 = io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_mov_0 = io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ftq_idx_0 = io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_edge_inst_0 = io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pc_lob_0 = io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_taken_0 = io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_rename_0 = io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_sel_0 = io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pimm_0 = io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:211:7, :1485:70] reg [19:0] io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_packed_0 = io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op1_sel_0 = io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op2_sel_0 = io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wen_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_toint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fma_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_div_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_vec_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rob_idx_0 = io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldq_idx_0 = io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stq_idx_0 = io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rxq_idx_0 = io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pdst_0 = io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_0 = io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_0 = io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_0 = io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_0 = io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_busy_0 = io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_busy_0 = io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_busy_0 = io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_busy_0 = io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stale_pdst_0 = io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exception_0 = io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exc_cause_0 = io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_cmd_0 = io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_size_0 = io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_signed_0 = io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_ldq_0 = io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_stq_0 = io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_unique_0 = io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_flush_on_commit_0 = io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_csr_cmd_0 = io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_is_rs1_0 = io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_0 = io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_0 = io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_0 = io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs3_0 = io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dst_rtype_0 = io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_frs3_en_0 = io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_dw_0 = io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_op_0 = io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_val_0 = io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_rm_0 = io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_typ_0 = io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_pf_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ae_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ma_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_debug_if_0 = io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_xcpt_if_0 = io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_fsrc_0 = io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_tsrc_0 = io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_data; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_data_0 = io_core_iresp_0_REG_bits_data; // @[lsu.scala:211:7, :1485:70] wire wb_spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1491:29] wire [39:0] wb_spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1491:29] wire [15:0] wb_spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1491:29] wire [19:0] wb_spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1491:29] wire [63:0] wb_spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29] wire spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1492:26] wire [39:0] spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1492:26] wire [15:0] spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1492:26] wire [19:0] spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1492:26] wire [63:0] spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_bypassable; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_speculative_mask; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_rebusy; // @[lsu.scala:1492:26] wire spec_wakeups_0_valid; // @[lsu.scala:1492:26] wire [31:0] slow_wakeups_0_out_bits_uop_inst = wb_slow_wakeups_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] slow_wakeups_0_out_bits_uop_debug_inst = wb_slow_wakeups_0_bits_uop_debug_inst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rvc = wb_slow_wakeups_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] slow_wakeups_0_out_bits_uop_debug_pc = wb_slow_wakeups_0_bits_uop_debug_pc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_0 = wb_slow_wakeups_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_1 = wb_slow_wakeups_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_2 = wb_slow_wakeups_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_3 = wb_slow_wakeups_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_0 = wb_slow_wakeups_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_1 = wb_slow_wakeups_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_2 = wb_slow_wakeups_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_3 = wb_slow_wakeups_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_4 = wb_slow_wakeups_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_5 = wb_slow_wakeups_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_6 = wb_slow_wakeups_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_7 = wb_slow_wakeups_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_8 = wb_slow_wakeups_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_9 = wb_slow_wakeups_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued = wb_slow_wakeups_0_bits_uop_iw_issued; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_agen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_dgen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_iw_p1_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_iw_p2_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p1_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p2_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p3_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_dis_col_sel = wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_tag = wb_slow_wakeups_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_type = wb_slow_wakeups_0_bits_uop_br_type; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfb = wb_slow_wakeups_0_bits_uop_is_sfb; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fence = wb_slow_wakeups_0_bits_uop_is_fence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fencei = wb_slow_wakeups_0_bits_uop_is_fencei; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfence = wb_slow_wakeups_0_bits_uop_is_sfence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_amo = wb_slow_wakeups_0_bits_uop_is_amo; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_eret = wb_slow_wakeups_0_bits_uop_is_eret; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sys_pc2epc = wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rocc = wb_slow_wakeups_0_bits_uop_is_rocc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_mov = wb_slow_wakeups_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ftq_idx = wb_slow_wakeups_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_edge_inst = wb_slow_wakeups_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_pc_lob = wb_slow_wakeups_0_bits_uop_pc_lob; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_taken = wb_slow_wakeups_0_bits_uop_taken; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_imm_rename = wb_slow_wakeups_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_imm_sel = wb_slow_wakeups_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_pimm = wb_slow_wakeups_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] slow_wakeups_0_out_bits_uop_imm_packed = wb_slow_wakeups_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_op1_sel = wb_slow_wakeups_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_op2_sel = wb_slow_wakeups_0_bits_uop_op2_sel; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ldst = wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wen = wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren1 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren2 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren3 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap12 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap23 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagIn = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagOut = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fromint = wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_toint = wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fastpipe = wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fma = wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_div = wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_sqrt = wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wflags = wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_vec = wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_rob_idx = wb_slow_wakeups_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ldq_idx = wb_slow_wakeups_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_stq_idx = wb_slow_wakeups_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_rxq_idx = wb_slow_wakeups_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_pdst = wb_slow_wakeups_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs1 = wb_slow_wakeups_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs2 = wb_slow_wakeups_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs3 = wb_slow_wakeups_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ppred = wb_slow_wakeups_0_bits_uop_ppred; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs1_busy = wb_slow_wakeups_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs2_busy = wb_slow_wakeups_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs3_busy = wb_slow_wakeups_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ppred_busy = wb_slow_wakeups_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_stale_pdst = wb_slow_wakeups_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_exception = wb_slow_wakeups_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] slow_wakeups_0_out_bits_uop_exc_cause = wb_slow_wakeups_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_mem_cmd = wb_slow_wakeups_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_mem_size = wb_slow_wakeups_0_bits_uop_mem_size; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_mem_signed = wb_slow_wakeups_0_bits_uop_mem_signed; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_ldq = wb_slow_wakeups_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_stq = wb_slow_wakeups_0_bits_uop_uses_stq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_unique = wb_slow_wakeups_0_bits_uop_is_unique; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_flush_on_commit = wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_csr_cmd = wb_slow_wakeups_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ldst_is_rs1 = wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_ldst = wb_slow_wakeups_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs1 = wb_slow_wakeups_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs2 = wb_slow_wakeups_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs3 = wb_slow_wakeups_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dst_rtype = wb_slow_wakeups_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs1_rtype = wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs2_rtype = wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_frs3_en = wb_slow_wakeups_0_bits_uop_frs3_en; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fcn_dw = wb_slow_wakeups_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_fcn_op = wb_slow_wakeups_0_bits_uop_fcn_op; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_val = wb_slow_wakeups_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_fp_rm = wb_slow_wakeups_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_typ = wb_slow_wakeups_0_bits_uop_fp_typ; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_pf_if = wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ae_if = wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ma_if = wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_debug_if = wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_xcpt_if = wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_fsrc = wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_tsrc = wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [15:0] wb_slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_valid; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1495:26] wire [39:0] slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1495:26] wire [15:0] slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1495:26] wire [19:0] slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1495:26] wire [63:0] slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1495:26] wire dmem_resp_fired_0; // @[lsu.scala:1497:33] reg w1_valid; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_valid = w1_valid; // @[lsu.scala:1491:29, :1499:17] reg [31:0] w1_bits_uop_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_inst = w1_bits_uop_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_inst = w1_bits_uop_inst; // @[util.scala:109:23] reg [31:0] w1_bits_uop_debug_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_inst = w1_bits_uop_debug_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_debug_inst = w1_bits_uop_debug_inst; // @[util.scala:109:23] reg w1_bits_uop_is_rvc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rvc = w1_bits_uop_is_rvc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rvc = w1_bits_uop_is_rvc; // @[util.scala:109:23] reg [39:0] w1_bits_uop_debug_pc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_pc = w1_bits_uop_debug_pc; // @[lsu.scala:1491:29, :1499:17] wire [39:0] w2_bits_out_uop_debug_pc = w1_bits_uop_debug_pc; // @[util.scala:109:23] reg w1_bits_uop_iq_type_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[util.scala:109:23] reg w1_bits_uop_iq_type_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[util.scala:109:23] reg w1_bits_uop_iq_type_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[util.scala:109:23] reg w1_bits_uop_iq_type_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[util.scala:109:23] reg w1_bits_uop_fu_code_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[util.scala:109:23] reg w1_bits_uop_fu_code_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[util.scala:109:23] reg w1_bits_uop_fu_code_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_4; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[util.scala:109:23] reg w1_bits_uop_fu_code_5; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[util.scala:109:23] reg w1_bits_uop_fu_code_6; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[util.scala:109:23] reg w1_bits_uop_fu_code_7; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[util.scala:109:23] reg w1_bits_uop_fu_code_8; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[util.scala:109:23] reg w1_bits_uop_fu_code_9; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[util.scala:109:23] reg w1_bits_uop_iw_issued; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued = w1_bits_uop_iw_issued; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued = w1_bits_uop_iw_issued; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] reg [2:0] w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] reg [2:0] w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] reg w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] reg [2:0] w1_bits_uop_dis_col_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[util.scala:109:23] reg [15:0] w1_bits_uop_br_mask; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_mask = w1_bits_uop_br_mask; // @[lsu.scala:1491:29, :1499:17] reg [3:0] w1_bits_uop_br_tag; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_tag = w1_bits_uop_br_tag; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_tag = w1_bits_uop_br_tag; // @[util.scala:109:23] reg [3:0] w1_bits_uop_br_type; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_type = w1_bits_uop_br_type; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_type = w1_bits_uop_br_type; // @[util.scala:109:23] reg w1_bits_uop_is_sfb; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfb = w1_bits_uop_is_sfb; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfb = w1_bits_uop_is_sfb; // @[util.scala:109:23] reg w1_bits_uop_is_fence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fence = w1_bits_uop_is_fence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fence = w1_bits_uop_is_fence; // @[util.scala:109:23] reg w1_bits_uop_is_fencei; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fencei = w1_bits_uop_is_fencei; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fencei = w1_bits_uop_is_fencei; // @[util.scala:109:23] reg w1_bits_uop_is_sfence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfence = w1_bits_uop_is_sfence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfence = w1_bits_uop_is_sfence; // @[util.scala:109:23] reg w1_bits_uop_is_amo; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_amo = w1_bits_uop_is_amo; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_amo = w1_bits_uop_is_amo; // @[util.scala:109:23] reg w1_bits_uop_is_eret; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_eret = w1_bits_uop_is_eret; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_eret = w1_bits_uop_is_eret; // @[util.scala:109:23] reg w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] reg w1_bits_uop_is_rocc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rocc = w1_bits_uop_is_rocc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rocc = w1_bits_uop_is_rocc; // @[util.scala:109:23] reg w1_bits_uop_is_mov; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_mov = w1_bits_uop_is_mov; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_mov = w1_bits_uop_is_mov; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ftq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[util.scala:109:23] reg w1_bits_uop_edge_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_edge_inst = w1_bits_uop_edge_inst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_edge_inst = w1_bits_uop_edge_inst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_pc_lob; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pc_lob = w1_bits_uop_pc_lob; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_pc_lob = w1_bits_uop_pc_lob; // @[util.scala:109:23] reg w1_bits_uop_taken; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_taken = w1_bits_uop_taken; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_taken = w1_bits_uop_taken; // @[util.scala:109:23] reg w1_bits_uop_imm_rename; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_rename = w1_bits_uop_imm_rename; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_imm_rename = w1_bits_uop_imm_rename; // @[util.scala:109:23] reg [2:0] w1_bits_uop_imm_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_sel = w1_bits_uop_imm_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_imm_sel = w1_bits_uop_imm_sel; // @[util.scala:109:23] reg [4:0] w1_bits_uop_pimm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pimm = w1_bits_uop_pimm; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_pimm = w1_bits_uop_pimm; // @[util.scala:109:23] reg [19:0] w1_bits_uop_imm_packed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_packed = w1_bits_uop_imm_packed; // @[lsu.scala:1491:29, :1499:17] wire [19:0] w2_bits_out_uop_imm_packed = w1_bits_uop_imm_packed; // @[util.scala:109:23] reg [1:0] w1_bits_uop_op1_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op1_sel = w1_bits_uop_op1_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_op1_sel = w1_bits_uop_op1_sel; // @[util.scala:109:23] reg [2:0] w1_bits_uop_op2_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op2_sel = w1_bits_uop_op2_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_op2_sel = w1_bits_uop_op2_sel; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] reg [6:0] w1_bits_uop_rob_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rob_idx = w1_bits_uop_rob_idx; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_rob_idx = w1_bits_uop_rob_idx; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ldq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[util.scala:109:23] reg [4:0] w1_bits_uop_stq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stq_idx = w1_bits_uop_stq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_stq_idx = w1_bits_uop_stq_idx; // @[util.scala:109:23] reg [1:0] w1_bits_uop_rxq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[util.scala:109:23] reg [6:0] w1_bits_uop_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pdst = w1_bits_uop_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_pdst = w1_bits_uop_pdst; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1 = w1_bits_uop_prs1; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs1 = w1_bits_uop_prs1; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2 = w1_bits_uop_prs2; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs2 = w1_bits_uop_prs2; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3 = w1_bits_uop_prs3; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs3 = w1_bits_uop_prs3; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ppred; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred = w1_bits_uop_ppred; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ppred = w1_bits_uop_ppred; // @[util.scala:109:23] reg w1_bits_uop_prs1_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[util.scala:109:23] reg w1_bits_uop_prs2_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[util.scala:109:23] reg w1_bits_uop_prs3_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[util.scala:109:23] reg w1_bits_uop_ppred_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[util.scala:109:23] reg [6:0] w1_bits_uop_stale_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[util.scala:109:23] reg w1_bits_uop_exception; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exception = w1_bits_uop_exception; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_exception = w1_bits_uop_exception; // @[util.scala:109:23] reg [63:0] w1_bits_uop_exc_cause; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exc_cause = w1_bits_uop_exc_cause; // @[lsu.scala:1491:29, :1499:17] wire [63:0] w2_bits_out_uop_exc_cause = w1_bits_uop_exc_cause; // @[util.scala:109:23] reg [4:0] w1_bits_uop_mem_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[util.scala:109:23] reg [1:0] w1_bits_uop_mem_size; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_size = w1_bits_uop_mem_size; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_mem_size = w1_bits_uop_mem_size; // @[util.scala:109:23] reg w1_bits_uop_mem_signed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_signed = w1_bits_uop_mem_signed; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_mem_signed = w1_bits_uop_mem_signed; // @[util.scala:109:23] reg w1_bits_uop_uses_ldq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[util.scala:109:23] reg w1_bits_uop_uses_stq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_stq = w1_bits_uop_uses_stq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_stq = w1_bits_uop_uses_stq; // @[util.scala:109:23] reg w1_bits_uop_is_unique; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_unique = w1_bits_uop_is_unique; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_unique = w1_bits_uop_is_unique; // @[util.scala:109:23] reg w1_bits_uop_flush_on_commit; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[util.scala:109:23] reg [2:0] w1_bits_uop_csr_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[util.scala:109:23] reg w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst = w1_bits_uop_ldst; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_ldst = w1_bits_uop_ldst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1 = w1_bits_uop_lrs1; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs1 = w1_bits_uop_lrs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2 = w1_bits_uop_lrs2; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs2 = w1_bits_uop_lrs2; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs3 = w1_bits_uop_lrs3; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs3 = w1_bits_uop_lrs3; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dst_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs1_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs2_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[util.scala:109:23] reg w1_bits_uop_frs3_en; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_frs3_en = w1_bits_uop_frs3_en; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_frs3_en = w1_bits_uop_frs3_en; // @[util.scala:109:23] reg w1_bits_uop_fcn_dw; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[util.scala:109:23] reg [4:0] w1_bits_uop_fcn_op; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_op = w1_bits_uop_fcn_op; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_fcn_op = w1_bits_uop_fcn_op; // @[util.scala:109:23] reg w1_bits_uop_fp_val; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_val = w1_bits_uop_fp_val; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_val = w1_bits_uop_fp_val; // @[util.scala:109:23] reg [2:0] w1_bits_uop_fp_rm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_rm = w1_bits_uop_fp_rm; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_fp_rm = w1_bits_uop_fp_rm; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_typ; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_typ = w1_bits_uop_fp_typ; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_typ = w1_bits_uop_fp_typ; // @[util.scala:109:23] reg w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[util.scala:109:23] reg w1_bits_uop_bp_debug_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[util.scala:109:23] reg w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_fsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_tsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[util.scala:109:23] wire _w1_valid_T = _wakeupArbs_0_io_in_1_ready & _wakeupArbs_0_io_in_1_valid_T_4; // @[Decoupled.scala:51:35] wire [15:0] _w1_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & mem_incoming_uop_0_br_mask; // @[util.scala:126:51] wire _w1_valid_T_2 = \|_w1_valid_T_1; // @[util.scala:126:{51,59}] wire _w1_valid_T_3 = _w1_valid_T_2 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w1_valid_T_4 = ~_w1_valid_T_3; // @[util.scala:61:61] wire _w1_valid_T_5 = _w1_valid_T & _w1_valid_T_4; // @[Decoupled.scala:51:35] wire [15:0] _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] w1_bits_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _w1_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w1_bits_out_uop_br_mask_T_1 = mem_incoming_uop_0_br_mask & _w1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w1_bits_out_uop_br_mask = _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg w2_valid; // @[lsu.scala:1503:17] assign spec_wakeups_0_valid = w2_valid; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_inst = w2_bits_uop_inst; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_debug_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_inst = w2_bits_uop_debug_inst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rvc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rvc = w2_bits_uop_is_rvc; // @[lsu.scala:1492:26, :1503:17] reg [39:0] w2_bits_uop_debug_pc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_pc = w2_bits_uop_debug_pc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_0 = w2_bits_uop_iq_type_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_1 = w2_bits_uop_iq_type_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_2 = w2_bits_uop_iq_type_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_3 = w2_bits_uop_iq_type_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_0 = w2_bits_uop_fu_code_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_1 = w2_bits_uop_fu_code_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_2 = w2_bits_uop_fu_code_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_3 = w2_bits_uop_fu_code_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_4; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_4 = w2_bits_uop_fu_code_4; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_5; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_5 = w2_bits_uop_fu_code_5; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_6; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_6 = w2_bits_uop_fu_code_6; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_7; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_7 = w2_bits_uop_fu_code_7; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_8; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_8 = w2_bits_uop_fu_code_8; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_9; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_9 = w2_bits_uop_fu_code_9; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued = w2_bits_uop_iw_issued; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_agen = w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_speculative_child = w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_speculative_child = w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_dis_col_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dis_col_sel = w2_bits_uop_dis_col_sel; // @[lsu.scala:1492:26, :1503:17] reg [15:0] w2_bits_uop_br_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_mask = w2_bits_uop_br_mask; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_tag; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_tag = w2_bits_uop_br_tag; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_type; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_type = w2_bits_uop_br_type; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfb; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfb = w2_bits_uop_is_sfb; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fence = w2_bits_uop_is_fence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fencei; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fencei = w2_bits_uop_is_fencei; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfence = w2_bits_uop_is_sfence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_amo; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_amo = w2_bits_uop_is_amo; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_eret; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_eret = w2_bits_uop_is_eret; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sys_pc2epc = w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rocc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rocc = w2_bits_uop_is_rocc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_mov; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_mov = w2_bits_uop_is_mov; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ftq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ftq_idx = w2_bits_uop_ftq_idx; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_edge_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_edge_inst = w2_bits_uop_edge_inst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_pc_lob; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pc_lob = w2_bits_uop_pc_lob; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_taken; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_taken = w2_bits_uop_taken; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_imm_rename; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_rename = w2_bits_uop_imm_rename; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_imm_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_sel = w2_bits_uop_imm_sel; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_pimm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pimm = w2_bits_uop_pimm; // @[lsu.scala:1492:26, :1503:17] reg [19:0] w2_bits_uop_imm_packed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_packed = w2_bits_uop_imm_packed; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_op1_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op1_sel = w2_bits_uop_op1_sel; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_op2_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op2_sel = w2_bits_uop_op2_sel; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ldst = w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wen = w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fromint = w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_toint = w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fma = w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_div = w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wflags = w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_vec = w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_rob_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rob_idx = w2_bits_uop_rob_idx; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ldq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldq_idx = w2_bits_uop_ldq_idx; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_stq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stq_idx = w2_bits_uop_stq_idx; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_rxq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rxq_idx = w2_bits_uop_rxq_idx; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pdst = w2_bits_uop_pdst; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1 = w2_bits_uop_prs1; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2 = w2_bits_uop_prs2; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3 = w2_bits_uop_prs3; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ppred; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred = w2_bits_uop_ppred; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs1_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1_busy = w2_bits_uop_prs1_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs2_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2_busy = w2_bits_uop_prs2_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs3_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3_busy = w2_bits_uop_prs3_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ppred_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred_busy = w2_bits_uop_ppred_busy; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_stale_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stale_pdst = w2_bits_uop_stale_pdst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_exception; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exception = w2_bits_uop_exception; // @[lsu.scala:1492:26, :1503:17] reg [63:0] w2_bits_uop_exc_cause; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exc_cause = w2_bits_uop_exc_cause; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_mem_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_cmd = w2_bits_uop_mem_cmd; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_mem_size; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_size = w2_bits_uop_mem_size; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_mem_signed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_signed = w2_bits_uop_mem_signed; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_ldq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_ldq = w2_bits_uop_uses_ldq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_stq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_stq = w2_bits_uop_uses_stq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_unique; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_unique = w2_bits_uop_is_unique; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_flush_on_commit; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_flush_on_commit = w2_bits_uop_flush_on_commit; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_csr_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_csr_cmd = w2_bits_uop_csr_cmd; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst_is_rs1 = w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst = w2_bits_uop_ldst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1 = w2_bits_uop_lrs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2 = w2_bits_uop_lrs2; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs3 = w2_bits_uop_lrs3; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dst_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dst_rtype = w2_bits_uop_dst_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs1_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1_rtype = w2_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs2_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2_rtype = w2_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_frs3_en; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_frs3_en = w2_bits_uop_frs3_en; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fcn_dw; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_dw = w2_bits_uop_fcn_dw; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_fcn_op; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_op = w2_bits_uop_fcn_op; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_val; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_val = w2_bits_uop_fp_val; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_fp_rm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_rm = w2_bits_uop_fp_rm; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_typ; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_typ = w2_bits_uop_fp_typ; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_pf_if = w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ae_if = w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ma_if = w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_debug_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_debug_if = w2_bits_uop_bp_debug_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_xcpt_if = w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_fsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_fsrc = w2_bits_uop_debug_fsrc; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_tsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_tsrc = w2_bits_uop_debug_tsrc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_bypassable; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_bypassable = w2_bits_bypassable; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_speculative_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_speculative_mask = w2_bits_speculative_mask; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_rebusy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_rebusy = w2_bits_rebusy; // @[lsu.scala:1492:26, :1503:17] wire [15:0] _w2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & w1_bits_uop_br_mask; // @[util.scala:126:51] wire _w2_valid_T_1 = \|_w2_valid_T; // @[util.scala:126:{51,59}] wire _w2_valid_T_2 = _w2_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w2_valid_T_3 = ~_w2_valid_T_2; // @[util.scala:61:61] wire _w2_valid_T_4 = w1_valid & _w2_valid_T_3; // @[lsu.scala:1499:17, :1504:{26,29}] wire [15:0] _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] w2_bits_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _w2_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w2_bits_out_uop_br_mask_T_1 = w1_bits_uop_br_mask & _w2_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w2_bits_out_uop_br_mask = _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _GEN_650 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:211:7, :1520:44] wire _GEN_651 = _GEN_650 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:211:7, :1520:44, :1522:55, :1523:15] wire _T_1659 = io_dmem_nack_0_bits_uop_stq_idx_0 < stq_execute_head ^ io_dmem_nack_0_bits_uop_stq_idx_0 < stq_head ^ stq_execute_head < stq_head; // @[util.scala:364:{52,58,64,72,78}] wire _GEN_652 = io_dmem_nack_0_bits_is_hella_0 \| io_dmem_nack_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :895:40, :1520:44, :1522:55, :1527:86] assign stq_execute_queue_flush = io_dmem_nack_0_valid_0 & ~_GEN_652 & _T_1659 \| ~_GEN_473 & _T_1639 & ~dmem_req_fire_0; // @[util.scala:364:{58,72}] wire _resp_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20] wire _resp_T_1 = _resp_T; // @[lsu.scala:1534:{20,43}] wire [31:0] resp_uop_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_inst_0 : io_dmem_resp_0_bits_uop_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [31:0] resp_uop_debug_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_inst_0 : io_dmem_resp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rvc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rvc_0 : io_dmem_resp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [39:0] resp_uop_debug_pc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_pc_0 : io_dmem_resp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_0_0 : io_dmem_resp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_1_0 : io_dmem_resp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_2_0 : io_dmem_resp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_3_0 : io_dmem_resp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_0_0 : io_dmem_resp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_1_0 : io_dmem_resp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_2_0 : io_dmem_resp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_3_0 : io_dmem_resp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_4 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_4_0 : io_dmem_resp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_5 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_5_0 : io_dmem_resp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_6 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_6_0 : io_dmem_resp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_7 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_7_0 : io_dmem_resp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_8 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_8_0 : io_dmem_resp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_9 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_9_0 : io_dmem_resp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_0 : io_dmem_resp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_agen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_dgen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_iw_p1_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_iw_p2_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p1_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p2_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p3_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_dis_col_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dis_col_sel_0 : io_dmem_resp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [15:0] resp_uop_br_mask = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_mask_0 : io_dmem_resp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_tag = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_tag_0 : io_dmem_resp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_type = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_type_0 : io_dmem_resp_0_bits_uop_br_type_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfb = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfb_0 : io_dmem_resp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fence_0 : io_dmem_resp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fencei = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fencei_0 : io_dmem_resp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfence_0 : io_dmem_resp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_amo = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_amo_0 : io_dmem_resp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_eret = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_eret_0 : io_dmem_resp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sys_pc2epc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 : io_dmem_resp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rocc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rocc_0 : io_dmem_resp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_mov = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_mov_0 : io_dmem_resp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ftq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ftq_idx_0 : io_dmem_resp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_edge_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_edge_inst_0 : io_dmem_resp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_pc_lob = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pc_lob_0 : io_dmem_resp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_taken = _resp_T_1 ? io_dmem_ll_resp_bits_uop_taken_0 : io_dmem_resp_0_bits_uop_taken_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_imm_rename = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_rename_0 : io_dmem_resp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_imm_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_sel_0 : io_dmem_resp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_pimm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pimm_0 : io_dmem_resp_0_bits_uop_pimm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [19:0] resp_uop_imm_packed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_packed_0 : io_dmem_resp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_op1_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op1_sel_0 : io_dmem_resp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_op2_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op2_sel_0 : io_dmem_resp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap12 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap23 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagIn = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagOut = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fromint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_toint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fastpipe = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fma = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_div = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 : io_dmem_resp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_sqrt = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 : io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wflags = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_vec = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 : io_dmem_resp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_rob_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rob_idx_0 : io_dmem_resp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ldq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldq_idx_0 : io_dmem_resp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_stq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stq_idx_0 : io_dmem_resp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_rxq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rxq_idx_0 : io_dmem_resp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pdst_0 : io_dmem_resp_0_bits_uop_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_0 : io_dmem_resp_0_bits_uop_prs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_0 : io_dmem_resp_0_bits_uop_prs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_0 : io_dmem_resp_0_bits_uop_prs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ppred = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_0 : io_dmem_resp_0_bits_uop_ppred_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs1_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_busy_0 : io_dmem_resp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs2_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_busy_0 : io_dmem_resp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs3_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_busy_0 : io_dmem_resp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ppred_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_busy_0 : io_dmem_resp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_stale_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stale_pdst_0 : io_dmem_resp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_exception = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exception_0 : io_dmem_resp_0_bits_uop_exception_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_uop_exc_cause = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exc_cause_0 : io_dmem_resp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_mem_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_cmd_0 : io_dmem_resp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_mem_size = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_size_0 : io_dmem_resp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_mem_signed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_signed_0 : io_dmem_resp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_ldq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_ldq_0 : io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_stq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_stq_0 : io_dmem_resp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_unique = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_unique_0 : io_dmem_resp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_flush_on_commit = _resp_T_1 ? io_dmem_ll_resp_bits_uop_flush_on_commit_0 : io_dmem_resp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_csr_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_csr_cmd_0 : io_dmem_resp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ldst_is_rs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 : io_dmem_resp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_0 : io_dmem_resp_0_bits_uop_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_0 : io_dmem_resp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_0 : io_dmem_resp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs3_0 : io_dmem_resp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dst_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dst_rtype_0 : io_dmem_resp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs1_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_rtype_0 : io_dmem_resp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs2_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_rtype_0 : io_dmem_resp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_frs3_en = _resp_T_1 ? io_dmem_ll_resp_bits_uop_frs3_en_0 : io_dmem_resp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fcn_dw = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_dw_0 : io_dmem_resp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_fcn_op = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_op_0 : io_dmem_resp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_val = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_val_0 : io_dmem_resp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_fp_rm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_rm_0 : io_dmem_resp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_typ = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_typ_0 : io_dmem_resp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_pf_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 : io_dmem_resp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ae_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 : io_dmem_resp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ma_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 : io_dmem_resp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_debug_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_debug_if_0 : io_dmem_resp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_xcpt_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 : io_dmem_resp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_fsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_fsrc_0 : io_dmem_resp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_tsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_tsrc_0 : io_dmem_resp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_data = _resp_T_1 ? io_dmem_ll_resp_bits_data_0 : io_dmem_resp_0_bits_data_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_is_hella = _resp_T_1 ? io_dmem_ll_resp_bits_is_hella_0 : io_dmem_resp_0_bits_is_hella_0; // @[lsu.scala:211:7, :1534:{19,43}] wire _io_dmem_ll_resp_ready_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20, :1537:32] wire _io_dmem_ll_resp_ready_T_1 = ~wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29, :1537:58] assign _io_dmem_ll_resp_ready_T_2 = _io_dmem_ll_resp_ready_T & _io_dmem_ll_resp_ready_T_1; // @[lsu.scala:1537:{32,55,58}] assign io_dmem_ll_resp_ready_0 = _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:211:7, :1537:55] wire _T_2143 = io_dmem_ll_resp_ready_0 & io_dmem_ll_resp_valid_0; // @[Decoupled.scala:51:35] wire _T_1662 = io_dmem_resp_0_valid_0 \| _T_2143; // @[Decoupled.scala:51:35] wire _GEN_653 = _T_1662 & resp_uop_uses_ldq; // @[lsu.scala:1534:19, :1539:33, :1540:32] wire uop_iq_type_0; // @[lsu.scala:1543:27] wire uop_iq_type_1; // @[lsu.scala:1543:27] wire uop_iq_type_2; // @[lsu.scala:1543:27] wire uop_iq_type_3; // @[lsu.scala:1543:27] wire uop_fu_code_0; // @[lsu.scala:1543:27] wire uop_fu_code_1; // @[lsu.scala:1543:27] wire uop_fu_code_2; // @[lsu.scala:1543:27] wire uop_fu_code_3; // @[lsu.scala:1543:27] wire uop_fu_code_4; // @[lsu.scala:1543:27] wire uop_fu_code_5; // @[lsu.scala:1543:27] wire uop_fu_code_6; // @[lsu.scala:1543:27] wire uop_fu_code_7; // @[lsu.scala:1543:27] wire uop_fu_code_8; // @[lsu.scala:1543:27] wire uop_fu_code_9; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ldst; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wen; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren1; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren2; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren3; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap12; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap23; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagIn; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagOut; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fromint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_toint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fastpipe; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fma; // @[lsu.scala:1543:27] wire uop_fp_ctrl_div; // @[lsu.scala:1543:27] wire uop_fp_ctrl_sqrt; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wflags; // @[lsu.scala:1543:27] wire uop_fp_ctrl_vec; // @[lsu.scala:1543:27] wire [31:0] uop_inst; // @[lsu.scala:1543:27] wire [31:0] uop_debug_inst; // @[lsu.scala:1543:27] wire uop_is_rvc; // @[lsu.scala:1543:27] wire [39:0] uop_debug_pc; // @[lsu.scala:1543:27] wire uop_iw_issued; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_agen; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_dgen; // @[lsu.scala:1543:27] wire [2:0] uop_iw_p1_speculative_child; // @[lsu.scala:1543:27] wire [2:0] uop_iw_p2_speculative_child; // @[lsu.scala:1543:27] wire uop_iw_p1_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p2_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p3_bypass_hint; // @[lsu.scala:1543:27] wire [2:0] uop_dis_col_sel; // @[lsu.scala:1543:27] wire [15:0] uop_br_mask; // @[lsu.scala:1543:27] wire [3:0] uop_br_tag; // @[lsu.scala:1543:27] wire [3:0] uop_br_type; // @[lsu.scala:1543:27] wire uop_is_sfb; // @[lsu.scala:1543:27] wire uop_is_fence; // @[lsu.scala:1543:27] wire uop_is_fencei; // @[lsu.scala:1543:27] wire uop_is_sfence; // @[lsu.scala:1543:27] wire uop_is_amo; // @[lsu.scala:1543:27] wire uop_is_eret; // @[lsu.scala:1543:27] wire uop_is_sys_pc2epc; // @[lsu.scala:1543:27] wire uop_is_rocc; // @[lsu.scala:1543:27] wire uop_is_mov; // @[lsu.scala:1543:27] wire [4:0] uop_ftq_idx; // @[lsu.scala:1543:27] wire uop_edge_inst; // @[lsu.scala:1543:27] wire [5:0] uop_pc_lob; // @[lsu.scala:1543:27] wire uop_taken; // @[lsu.scala:1543:27] wire uop_imm_rename; // @[lsu.scala:1543:27] wire [2:0] uop_imm_sel; // @[lsu.scala:1543:27] wire [4:0] uop_pimm; // @[lsu.scala:1543:27] wire [19:0] uop_imm_packed; // @[lsu.scala:1543:27] wire [1:0] uop_op1_sel; // @[lsu.scala:1543:27] wire [2:0] uop_op2_sel; // @[lsu.scala:1543:27] wire [6:0] uop_rob_idx; // @[lsu.scala:1543:27] wire [4:0] uop_ldq_idx; // @[lsu.scala:1543:27] wire [4:0] uop_stq_idx; // @[lsu.scala:1543:27] wire [1:0] uop_rxq_idx; // @[lsu.scala:1543:27] wire [6:0] uop_pdst; // @[lsu.scala:1543:27] wire [6:0] uop_prs1; // @[lsu.scala:1543:27] wire [6:0] uop_prs2; // @[lsu.scala:1543:27] wire [6:0] uop_prs3; // @[lsu.scala:1543:27] wire [4:0] uop_ppred; // @[lsu.scala:1543:27] wire uop_prs1_busy; // @[lsu.scala:1543:27] wire uop_prs2_busy; // @[lsu.scala:1543:27] wire uop_prs3_busy; // @[lsu.scala:1543:27] wire uop_ppred_busy; // @[lsu.scala:1543:27] wire [6:0] uop_stale_pdst; // @[lsu.scala:1543:27] wire uop_exception; // @[lsu.scala:1543:27] wire [63:0] uop_exc_cause; // @[lsu.scala:1543:27] wire [4:0] uop_mem_cmd; // @[lsu.scala:1543:27] wire [1:0] uop_mem_size; // @[lsu.scala:1543:27] wire uop_mem_signed; // @[lsu.scala:1543:27] wire uop_uses_ldq; // @[lsu.scala:1543:27] wire uop_uses_stq; // @[lsu.scala:1543:27] wire uop_is_unique; // @[lsu.scala:1543:27] wire uop_flush_on_commit; // @[lsu.scala:1543:27] wire [2:0] uop_csr_cmd; // @[lsu.scala:1543:27] wire uop_ldst_is_rs1; // @[lsu.scala:1543:27] wire [5:0] uop_ldst; // @[lsu.scala:1543:27] wire [5:0] uop_lrs1; // @[lsu.scala:1543:27] wire [5:0] uop_lrs2; // @[lsu.scala:1543:27] wire [5:0] uop_lrs3; // @[lsu.scala:1543:27] wire [1:0] uop_dst_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs1_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs2_rtype; // @[lsu.scala:1543:27] wire uop_frs3_en; // @[lsu.scala:1543:27] wire uop_fcn_dw; // @[lsu.scala:1543:27] wire [4:0] uop_fcn_op; // @[lsu.scala:1543:27] wire uop_fp_val; // @[lsu.scala:1543:27] wire [2:0] uop_fp_rm; // @[lsu.scala:1543:27] wire [1:0] uop_fp_typ; // @[lsu.scala:1543:27] wire uop_xcpt_pf_if; // @[lsu.scala:1543:27] wire uop_xcpt_ae_if; // @[lsu.scala:1543:27] wire uop_xcpt_ma_if; // @[lsu.scala:1543:27] wire uop_bp_debug_if; // @[lsu.scala:1543:27] wire uop_bp_xcpt_if; // @[lsu.scala:1543:27] wire [2:0] uop_debug_fsrc; // @[lsu.scala:1543:27] wire [2:0] uop_debug_tsrc; // @[lsu.scala:1543:27] assign uop_inst = _GEN_127[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_inst = _GEN_128[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rvc = _GEN_129[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_pc = _GEN_130[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_0 = _GEN_131[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_1 = _GEN_132[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_2 = _GEN_133[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_3 = _GEN_134[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_0 = _GEN_135[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_1 = _GEN_136[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_2 = _GEN_137[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_3 = _GEN_138[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_4 = _GEN_139[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_5 = _GEN_140[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_6 = _GEN_141[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_7 = _GEN_142[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_8 = _GEN_143[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_9 = _GEN_144[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued = _GEN_145[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_agen = _GEN_146[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_dgen = _GEN_147[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_speculative_child = _GEN_148[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_speculative_child = _GEN_149[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_bypass_hint = _GEN_150[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_bypass_hint = _GEN_151[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p3_bypass_hint = _GEN_152[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dis_col_sel = _GEN_153[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_mask = _GEN_154[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_tag = _GEN_155[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_type = _GEN_156[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfb = _GEN_157[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fence = _GEN_158[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fencei = _GEN_159[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfence = _GEN_160[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_amo = _GEN_161[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_eret = _GEN_162[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sys_pc2epc = _GEN_163[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rocc = _GEN_164[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_mov = _GEN_165[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ftq_idx = _GEN_166[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_edge_inst = _GEN_167[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pc_lob = _GEN_168[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_taken = _GEN_169[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_rename = _GEN_170[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_sel = _GEN_171[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pimm = _GEN_172[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_packed = _GEN_173[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op1_sel = _GEN_174[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op2_sel = _GEN_175[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ldst = _GEN_176[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wen = _GEN_177[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren1 = _GEN_178[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren2 = _GEN_179[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren3 = _GEN_180[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap12 = _GEN_181[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap23 = _GEN_182[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagIn = _GEN_183[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagOut = _GEN_184[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fromint = _GEN_185[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_toint = _GEN_186[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fastpipe = _GEN_187[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fma = _GEN_188[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_div = _GEN_189[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_sqrt = _GEN_190[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wflags = _GEN_191[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_vec = _GEN_192[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rob_idx = _GEN_193[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldq_idx = _GEN_194[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stq_idx = _GEN_195[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rxq_idx = _GEN_196[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pdst = _GEN_197[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1 = _GEN_198[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2 = _GEN_199[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3 = _GEN_200[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred = _GEN_201[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1_busy = _GEN_202[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2_busy = _GEN_203[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3_busy = _GEN_204[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred_busy = _GEN_205[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stale_pdst = _GEN_206[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exception = _GEN_207[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exc_cause = _GEN_208[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_cmd = _GEN_209[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_size = _GEN_210[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_signed = _GEN_211[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_ldq = _GEN_212[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_stq = _GEN_213[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_unique = _GEN_214[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_flush_on_commit = _GEN_215[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_csr_cmd = _GEN_216[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst_is_rs1 = _GEN_217[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst = _GEN_218[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1 = _GEN_219[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2 = _GEN_220[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs3 = _GEN_221[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dst_rtype = _GEN_222[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1_rtype = _GEN_223[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2_rtype = _GEN_224[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_frs3_en = _GEN_225[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_dw = _GEN_226[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_op = _GEN_227[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_val = _GEN_228[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_rm = _GEN_229[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_typ = _GEN_230[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_pf_if = _GEN_231[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ae_if = _GEN_232[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ma_if = _GEN_233[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_debug_if = _GEN_234[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_xcpt_if = _GEN_235[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_fsrc = _GEN_236[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_tsrc = _GEN_237[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] wire send_iresp = uop_dst_rtype == 2'h0; // @[lsu.scala:1543:27, :1544:40] wire send_fresp = uop_dst_rtype == 2'h1; // @[lsu.scala:1543:27, :1545:40] wire _ldq_will_succeed_T = iresp_0_valid \| fresp_0_valid; // @[lsu.scala:1477:19, :1478:19, :1560:54] wire _GEN_654 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h0; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_655 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h1; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_656 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h2; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_657 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h3; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_658 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h4; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_659 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h5; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_660 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h6; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_661 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h7; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_662 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h8; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_663 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h9; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_664 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hA; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_665 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hB; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_666 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hC; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_667 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hD; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_668 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hE; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_669 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hF; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_670 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h10; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_671 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h11; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_672 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h12; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_673 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h13; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_674 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h14; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_675 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h15; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_676 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h16; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_677 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h17; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] assign dmem_resp_fired_0 = _T_1662 & (resp_uop_uses_stq \| resp_uop_uses_ldq); // @[lsu.scala:1497:33, :1534:19, :1539:{33,83}, :1540:32, :1558:28, :1571:7, :1574:28] wire _GEN_678 = _T_1662 & (resp_uop_uses_stq \| resp_uop_uses_ldq & send_iresp); // @[lsu.scala:1481:20, :1534:19, :1539:{33,83}, :1540:32, :1544:40, :1549:28, :1571:7, :1575:28] wire _T_1676 = dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1594:30] wire _T_1678 = ~dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1598:{18,38}] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_334[wb_ldst_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire [3:0][63:0] _GEN_679 = {{_GEN_366[wb_ldst_forward_stq_idx_0]}, {{2{_GEN_366[wb_ldst_forward_stq_idx_0][31:0]}}}, {{2{{2{_GEN_366[wb_ldst_forward_stq_idx_0][15:0]}}}}}, {{2{{2{{2{_GEN_366[wb_ldst_forward_stq_idx_0][7:0]}}}}}}}}; // @[AMOALU.scala:29:{13,19,32,69}] wire _GEN_680 = wb_ldst_forward_e_0_uop_dst_rtype == 2'h0; // @[lsu.scala:321:49, :1612:60] wire _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1612:60] assign _wb_slow_wakeups_0_valid_T = _GEN_680; // @[lsu.scala:1612:60] wire _iresp_0_valid_T; // @[lsu.scala:1618:48] assign _iresp_0_valid_T = _GEN_680; // @[lsu.scala:1612:60, :1618:48] wire _GEN_681 = _T_1676 \| ~_T_1678; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1598:38, :1599:5] assign wb_slow_wakeups_0_valid = _GEN_681 ? _GEN_678 : _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1481:20, :1494:29, :1539:83, :1571:7, :1595:5, :1599:5, :1612:60] wire [31:0] _GEN_682 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_251[resp_uop_stq_idx] : uop_inst) : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_inst = _GEN_682; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_inst = _GEN_682; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [31:0] _GEN_683 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_252[resp_uop_stq_idx] : uop_debug_inst) : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_inst = _GEN_683; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_inst = _GEN_683; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_684 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_253[resp_uop_stq_idx] : uop_is_rvc) : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rvc = _GEN_684; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rvc = _GEN_684; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [39:0] _GEN_685 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_254[resp_uop_stq_idx] : uop_debug_pc) : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_pc = _GEN_685; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_pc = _GEN_685; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_686 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_255[resp_uop_stq_idx] : uop_iq_type_0) : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_0 = _GEN_686; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_0 = _GEN_686; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_687 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_256[resp_uop_stq_idx] : uop_iq_type_1) : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_1 = _GEN_687; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_1 = _GEN_687; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_688 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_257[resp_uop_stq_idx] : uop_iq_type_2) : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_2 = _GEN_688; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_2 = _GEN_688; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_689 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_258[resp_uop_stq_idx] : uop_iq_type_3) : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_3 = _GEN_689; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_3 = _GEN_689; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_690 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_259[resp_uop_stq_idx] : uop_fu_code_0) : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_0 = _GEN_690; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_0 = _GEN_690; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_691 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_260[resp_uop_stq_idx] : uop_fu_code_1) : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_1 = _GEN_691; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_1 = _GEN_691; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_692 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_261[resp_uop_stq_idx] : uop_fu_code_2) : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_2 = _GEN_692; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_2 = _GEN_692; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_693 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_262[resp_uop_stq_idx] : uop_fu_code_3) : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_3 = _GEN_693; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_3 = _GEN_693; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_694 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_263[resp_uop_stq_idx] : uop_fu_code_4) : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_4 = _GEN_694; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_4 = _GEN_694; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_695 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_264[resp_uop_stq_idx] : uop_fu_code_5) : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_5 = _GEN_695; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_5 = _GEN_695; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_696 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_265[resp_uop_stq_idx] : uop_fu_code_6) : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_6 = _GEN_696; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_6 = _GEN_696; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_697 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_266[resp_uop_stq_idx] : uop_fu_code_7) : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_7 = _GEN_697; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_7 = _GEN_697; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_698 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_267[resp_uop_stq_idx] : uop_fu_code_8) : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_8 = _GEN_698; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_8 = _GEN_698; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_699 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_268[resp_uop_stq_idx] : uop_fu_code_9) : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_9 = _GEN_699; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_9 = _GEN_699; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_700 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_269[resp_uop_stq_idx] : uop_iw_issued) : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued = _GEN_700; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued = _GEN_700; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_701 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_270[resp_uop_stq_idx] : uop_iw_issued_partial_agen) : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_agen = _GEN_701; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen = _GEN_701; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_702 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_271[resp_uop_stq_idx] : uop_iw_issued_partial_dgen) : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_dgen = _GEN_702; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen = _GEN_702; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_703 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_272[resp_uop_stq_idx] : uop_iw_p1_speculative_child) : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_speculative_child = _GEN_703; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child = _GEN_703; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_704 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_273[resp_uop_stq_idx] : uop_iw_p2_speculative_child) : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_speculative_child = _GEN_704; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child = _GEN_704; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_705 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_274[resp_uop_stq_idx] : uop_iw_p1_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_bypass_hint = _GEN_705; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint = _GEN_705; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_706 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_275[resp_uop_stq_idx] : uop_iw_p2_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_bypass_hint = _GEN_706; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint = _GEN_706; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_707 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_276[resp_uop_stq_idx] : uop_iw_p3_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p3_bypass_hint = _GEN_707; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint = _GEN_707; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_708 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_277[resp_uop_stq_idx] : uop_dis_col_sel) : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dis_col_sel = _GEN_708; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dis_col_sel = _GEN_708; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [15:0] _GEN_709 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_278[resp_uop_stq_idx] : uop_br_mask) : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_mask = _GEN_709; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_mask = _GEN_709; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_710 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_279[resp_uop_stq_idx] : uop_br_tag) : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_tag = _GEN_710; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_tag = _GEN_710; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_711 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_280[resp_uop_stq_idx] : uop_br_type) : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_type = _GEN_711; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_type = _GEN_711; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_712 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_281[resp_uop_stq_idx] : uop_is_sfb) : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfb = _GEN_712; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfb = _GEN_712; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_713 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_282[resp_uop_stq_idx] : uop_is_fence) : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fence = _GEN_713; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fence = _GEN_713; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_714 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_283[resp_uop_stq_idx] : uop_is_fencei) : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fencei = _GEN_714; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fencei = _GEN_714; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_715 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_284[resp_uop_stq_idx] : uop_is_sfence) : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfence = _GEN_715; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfence = _GEN_715; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_716 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_285[resp_uop_stq_idx] : uop_is_amo) : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_amo = _GEN_716; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_amo = _GEN_716; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_717 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_286[resp_uop_stq_idx] : uop_is_eret) : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_eret = _GEN_717; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_eret = _GEN_717; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_718 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_287[resp_uop_stq_idx] : uop_is_sys_pc2epc) : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sys_pc2epc = _GEN_718; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sys_pc2epc = _GEN_718; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_719 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_288[resp_uop_stq_idx] : uop_is_rocc) : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rocc = _GEN_719; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rocc = _GEN_719; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_720 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_289[resp_uop_stq_idx] : uop_is_mov) : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_mov = _GEN_720; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_mov = _GEN_720; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_721 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_290[resp_uop_stq_idx] : uop_ftq_idx) : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ftq_idx = _GEN_721; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ftq_idx = _GEN_721; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_722 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_291[resp_uop_stq_idx] : uop_edge_inst) : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_edge_inst = _GEN_722; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_edge_inst = _GEN_722; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_723 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_292[resp_uop_stq_idx] : uop_pc_lob) : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pc_lob = _GEN_723; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pc_lob = _GEN_723; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_724 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_293[resp_uop_stq_idx] : uop_taken) : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_taken = _GEN_724; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_taken = _GEN_724; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_725 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_294[resp_uop_stq_idx] : uop_imm_rename) : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_rename = _GEN_725; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_rename = _GEN_725; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_726 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_295[resp_uop_stq_idx] : uop_imm_sel) : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_sel = _GEN_726; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_sel = _GEN_726; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_727 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_296[resp_uop_stq_idx] : uop_pimm) : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pimm = _GEN_727; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pimm = _GEN_727; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [19:0] _GEN_728 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_297[resp_uop_stq_idx] : uop_imm_packed) : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_packed = _GEN_728; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_packed = _GEN_728; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_729 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_298[resp_uop_stq_idx] : uop_op1_sel) : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op1_sel = _GEN_729; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op1_sel = _GEN_729; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_730 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_299[resp_uop_stq_idx] : uop_op2_sel) : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op2_sel = _GEN_730; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op2_sel = _GEN_730; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_731 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_300[resp_uop_stq_idx] : uop_fp_ctrl_ldst) : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ldst = _GEN_731; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst = _GEN_731; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_732 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_301[resp_uop_stq_idx] : uop_fp_ctrl_wen) : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wen = _GEN_732; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wen = _GEN_732; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_733 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_302[resp_uop_stq_idx] : uop_fp_ctrl_ren1) : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren1 = _GEN_733; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1 = _GEN_733; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_734 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_303[resp_uop_stq_idx] : uop_fp_ctrl_ren2) : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren2 = _GEN_734; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2 = _GEN_734; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_735 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_304[resp_uop_stq_idx] : uop_fp_ctrl_ren3) : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren3 = _GEN_735; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3 = _GEN_735; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_736 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_305[resp_uop_stq_idx] : uop_fp_ctrl_swap12) : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap12 = _GEN_736; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12 = _GEN_736; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_737 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_306[resp_uop_stq_idx] : uop_fp_ctrl_swap23) : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap23 = _GEN_737; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23 = _GEN_737; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_738 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_307[resp_uop_stq_idx] : uop_fp_ctrl_typeTagIn) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_738; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = _GEN_738; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_739 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_308[resp_uop_stq_idx] : uop_fp_ctrl_typeTagOut) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_739; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = _GEN_739; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_740 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_309[resp_uop_stq_idx] : uop_fp_ctrl_fromint) : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fromint = _GEN_740; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint = _GEN_740; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_741 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_310[resp_uop_stq_idx] : uop_fp_ctrl_toint) : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_toint = _GEN_741; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_toint = _GEN_741; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_742 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_311[resp_uop_stq_idx] : uop_fp_ctrl_fastpipe) : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_742; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = _GEN_742; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_743 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_312[resp_uop_stq_idx] : uop_fp_ctrl_fma) : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fma = _GEN_743; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fma = _GEN_743; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_744 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_313[resp_uop_stq_idx] : uop_fp_ctrl_div) : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_div = _GEN_744; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_div = _GEN_744; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_745 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_314[resp_uop_stq_idx] : uop_fp_ctrl_sqrt) : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_sqrt = _GEN_745; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt = _GEN_745; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_746 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_315[resp_uop_stq_idx] : uop_fp_ctrl_wflags) : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wflags = _GEN_746; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags = _GEN_746; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_747 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_316[resp_uop_stq_idx] : uop_fp_ctrl_vec) : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_vec = _GEN_747; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_vec = _GEN_747; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_748 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_317[resp_uop_stq_idx] : uop_rob_idx) : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rob_idx = _GEN_748; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rob_idx = _GEN_748; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_749 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_318[resp_uop_stq_idx] : uop_ldq_idx) : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldq_idx = _GEN_749; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldq_idx = _GEN_749; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_750 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_319[resp_uop_stq_idx] : uop_stq_idx) : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stq_idx = _GEN_750; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stq_idx = _GEN_750; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_751 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_320[resp_uop_stq_idx] : uop_rxq_idx) : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rxq_idx = _GEN_751; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rxq_idx = _GEN_751; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_752 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_321[resp_uop_stq_idx] : uop_pdst) : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pdst = _GEN_752; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pdst = _GEN_752; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_753 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_322[resp_uop_stq_idx] : uop_prs1) : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1 = _GEN_753; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1 = _GEN_753; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_754 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_323[resp_uop_stq_idx] : uop_prs2) : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2 = _GEN_754; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2 = _GEN_754; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_755 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_324[resp_uop_stq_idx] : uop_prs3) : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3 = _GEN_755; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3 = _GEN_755; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_756 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_325[resp_uop_stq_idx] : uop_ppred) : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred = _GEN_756; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred = _GEN_756; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_757 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_326[resp_uop_stq_idx] : uop_prs1_busy) : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1_busy = _GEN_757; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1_busy = _GEN_757; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_758 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_327[resp_uop_stq_idx] : uop_prs2_busy) : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2_busy = _GEN_758; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2_busy = _GEN_758; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_759 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_328[resp_uop_stq_idx] : uop_prs3_busy) : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3_busy = _GEN_759; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3_busy = _GEN_759; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_760 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_329[resp_uop_stq_idx] : uop_ppred_busy) : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred_busy = _GEN_760; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred_busy = _GEN_760; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_761 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_330[resp_uop_stq_idx] : uop_stale_pdst) : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stale_pdst = _GEN_761; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stale_pdst = _GEN_761; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_762 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_331[resp_uop_stq_idx] : uop_exception) : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exception = _GEN_762; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exception = _GEN_762; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [63:0] _GEN_763 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_332[resp_uop_stq_idx] : uop_exc_cause) : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exc_cause = _GEN_763; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exc_cause = _GEN_763; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_764 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_333[resp_uop_stq_idx] : uop_mem_cmd) : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_cmd = _GEN_764; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_cmd = _GEN_764; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_765 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_334[resp_uop_stq_idx] : uop_mem_size) : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_size = _GEN_765; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_size = _GEN_765; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_766 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_335[resp_uop_stq_idx] : uop_mem_signed) : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_signed = _GEN_766; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_signed = _GEN_766; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_767 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_336[resp_uop_stq_idx] : uop_uses_ldq) : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_ldq = _GEN_767; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_ldq = _GEN_767; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_768 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_337[resp_uop_stq_idx] : uop_uses_stq) : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_stq = _GEN_768; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_stq = _GEN_768; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_769 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_338[resp_uop_stq_idx] : uop_is_unique) : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_unique = _GEN_769; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_unique = _GEN_769; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_770 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_339[resp_uop_stq_idx] : uop_flush_on_commit) : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_flush_on_commit = _GEN_770; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_flush_on_commit = _GEN_770; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_771 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_340[resp_uop_stq_idx] : uop_csr_cmd) : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_csr_cmd = _GEN_771; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_csr_cmd = _GEN_771; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_772 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_341[resp_uop_stq_idx] : uop_ldst_is_rs1) : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst_is_rs1 = _GEN_772; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst_is_rs1 = _GEN_772; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_773 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_342[resp_uop_stq_idx] : uop_ldst) : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst = _GEN_773; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst = _GEN_773; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_774 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_343[resp_uop_stq_idx] : uop_lrs1) : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1 = _GEN_774; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1 = _GEN_774; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_775 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_344[resp_uop_stq_idx] : uop_lrs2) : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2 = _GEN_775; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2 = _GEN_775; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_776 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_345[resp_uop_stq_idx] : uop_lrs3) : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs3 = _GEN_776; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs3 = _GEN_776; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_777 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_346[resp_uop_stq_idx] : uop_dst_rtype) : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dst_rtype = _GEN_777; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dst_rtype = _GEN_777; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_778 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_347[resp_uop_stq_idx] : uop_lrs1_rtype) : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1_rtype = _GEN_778; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1_rtype = _GEN_778; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_779 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_348[resp_uop_stq_idx] : uop_lrs2_rtype) : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2_rtype = _GEN_779; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2_rtype = _GEN_779; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_780 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_349[resp_uop_stq_idx] : uop_frs3_en) : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_frs3_en = _GEN_780; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_frs3_en = _GEN_780; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_781 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_350[resp_uop_stq_idx] : uop_fcn_dw) : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_dw = _GEN_781; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_dw = _GEN_781; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_782 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_351[resp_uop_stq_idx] : uop_fcn_op) : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_op = _GEN_782; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_op = _GEN_782; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_783 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_352[resp_uop_stq_idx] : uop_fp_val) : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_val = _GEN_783; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_val = _GEN_783; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_784 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_353[resp_uop_stq_idx] : uop_fp_rm) : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_rm = _GEN_784; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_rm = _GEN_784; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_785 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_354[resp_uop_stq_idx] : uop_fp_typ) : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_typ = _GEN_785; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_typ = _GEN_785; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_786 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_355[resp_uop_stq_idx] : uop_xcpt_pf_if) : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_pf_if = _GEN_786; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_pf_if = _GEN_786; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_787 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_356[resp_uop_stq_idx] : uop_xcpt_ae_if) : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ae_if = _GEN_787; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ae_if = _GEN_787; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_788 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_357[resp_uop_stq_idx] : uop_xcpt_ma_if) : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ma_if = _GEN_788; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ma_if = _GEN_788; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_789 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_358[resp_uop_stq_idx] : uop_bp_debug_if) : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_debug_if = _GEN_789; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_debug_if = _GEN_789; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_790 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_359[resp_uop_stq_idx] : uop_bp_xcpt_if) : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_xcpt_if = _GEN_790; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_xcpt_if = _GEN_790; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_791 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_360[resp_uop_stq_idx] : uop_debug_fsrc) : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_fsrc = _GEN_791; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_fsrc = _GEN_791; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_792 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_361[resp_uop_stq_idx] : uop_debug_tsrc) : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_tsrc = _GEN_792; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_tsrc = _GEN_792; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] assign iresp_0_valid = _GEN_681 ? _GEN_678 : _iresp_0_valid_T; // @[lsu.scala:1477:19, :1481:20, :1539:83, :1571:7, :1595:5, :1599:5, :1618:48] wire _fresp_0_valid_T = wb_ldst_forward_e_0_uop_dst_rtype == 2'h1; // @[lsu.scala:321:49, :1619:48] assign fresp_0_valid = _GEN_681 ? _GEN_653 & send_fresp : _fresp_0_valid_T; // @[lsu.scala:1478:19, :1483:20, :1539:83, :1540:32, :1545:40, :1554:28, :1595:5, :1599:5, :1619:48] assign fresp_0_bits_uop_inst = _GEN_681 ? uop_inst : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_inst = _GEN_681 ? uop_debug_inst : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rvc = _GEN_681 ? uop_is_rvc : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_pc = _GEN_681 ? uop_debug_pc : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_0 = _GEN_681 ? uop_iq_type_0 : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_1 = _GEN_681 ? uop_iq_type_1 : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_2 = _GEN_681 ? uop_iq_type_2 : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_3 = _GEN_681 ? uop_iq_type_3 : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_0 = _GEN_681 ? uop_fu_code_0 : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_1 = _GEN_681 ? uop_fu_code_1 : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_2 = _GEN_681 ? uop_fu_code_2 : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_3 = _GEN_681 ? uop_fu_code_3 : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_4 = _GEN_681 ? uop_fu_code_4 : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_5 = _GEN_681 ? uop_fu_code_5 : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_6 = _GEN_681 ? uop_fu_code_6 : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_7 = _GEN_681 ? uop_fu_code_7 : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_8 = _GEN_681 ? uop_fu_code_8 : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_9 = _GEN_681 ? uop_fu_code_9 : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued = _GEN_681 ? uop_iw_issued : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_agen = _GEN_681 ? uop_iw_issued_partial_agen : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_dgen = _GEN_681 ? uop_iw_issued_partial_dgen : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_speculative_child = _GEN_681 ? uop_iw_p1_speculative_child : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_speculative_child = _GEN_681 ? uop_iw_p2_speculative_child : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_bypass_hint = _GEN_681 ? uop_iw_p1_bypass_hint : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_bypass_hint = _GEN_681 ? uop_iw_p2_bypass_hint : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p3_bypass_hint = _GEN_681 ? uop_iw_p3_bypass_hint : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dis_col_sel = _GEN_681 ? uop_dis_col_sel : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_mask = _GEN_681 ? uop_br_mask : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_tag = _GEN_681 ? uop_br_tag : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_type = _GEN_681 ? uop_br_type : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfb = _GEN_681 ? uop_is_sfb : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fence = _GEN_681 ? uop_is_fence : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fencei = _GEN_681 ? uop_is_fencei : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfence = _GEN_681 ? uop_is_sfence : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_amo = _GEN_681 ? uop_is_amo : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_eret = _GEN_681 ? uop_is_eret : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sys_pc2epc = _GEN_681 ? uop_is_sys_pc2epc : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rocc = _GEN_681 ? uop_is_rocc : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_mov = _GEN_681 ? uop_is_mov : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ftq_idx = _GEN_681 ? uop_ftq_idx : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_edge_inst = _GEN_681 ? uop_edge_inst : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pc_lob = _GEN_681 ? uop_pc_lob : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_taken = _GEN_681 ? uop_taken : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_rename = _GEN_681 ? uop_imm_rename : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_sel = _GEN_681 ? uop_imm_sel : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pimm = _GEN_681 ? uop_pimm : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_packed = _GEN_681 ? uop_imm_packed : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op1_sel = _GEN_681 ? uop_op1_sel : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op2_sel = _GEN_681 ? uop_op2_sel : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ldst = _GEN_681 ? uop_fp_ctrl_ldst : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wen = _GEN_681 ? uop_fp_ctrl_wen : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren1 = _GEN_681 ? uop_fp_ctrl_ren1 : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren2 = _GEN_681 ? uop_fp_ctrl_ren2 : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren3 = _GEN_681 ? uop_fp_ctrl_ren3 : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap12 = _GEN_681 ? uop_fp_ctrl_swap12 : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap23 = _GEN_681 ? uop_fp_ctrl_swap23 : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_681 ? uop_fp_ctrl_typeTagIn : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_681 ? uop_fp_ctrl_typeTagOut : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fromint = _GEN_681 ? uop_fp_ctrl_fromint : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_toint = _GEN_681 ? uop_fp_ctrl_toint : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_681 ? uop_fp_ctrl_fastpipe : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fma = _GEN_681 ? uop_fp_ctrl_fma : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_div = _GEN_681 ? uop_fp_ctrl_div : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_sqrt = _GEN_681 ? uop_fp_ctrl_sqrt : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wflags = _GEN_681 ? uop_fp_ctrl_wflags : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_vec = _GEN_681 ? uop_fp_ctrl_vec : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rob_idx = _GEN_681 ? uop_rob_idx : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldq_idx = _GEN_681 ? uop_ldq_idx : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stq_idx = _GEN_681 ? uop_stq_idx : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rxq_idx = _GEN_681 ? uop_rxq_idx : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pdst = _GEN_681 ? uop_pdst : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1 = _GEN_681 ? uop_prs1 : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2 = _GEN_681 ? uop_prs2 : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3 = _GEN_681 ? uop_prs3 : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred = _GEN_681 ? uop_ppred : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1_busy = _GEN_681 ? uop_prs1_busy : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2_busy = _GEN_681 ? uop_prs2_busy : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3_busy = _GEN_681 ? uop_prs3_busy : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred_busy = _GEN_681 ? uop_ppred_busy : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stale_pdst = _GEN_681 ? uop_stale_pdst : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exception = _GEN_681 ? uop_exception : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exc_cause = _GEN_681 ? uop_exc_cause : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_cmd = _GEN_681 ? uop_mem_cmd : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_size = _GEN_681 ? uop_mem_size : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_signed = _GEN_681 ? uop_mem_signed : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_ldq = _GEN_681 ? uop_uses_ldq : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_stq = _GEN_681 ? uop_uses_stq : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_unique = _GEN_681 ? uop_is_unique : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_flush_on_commit = _GEN_681 ? uop_flush_on_commit : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_csr_cmd = _GEN_681 ? uop_csr_cmd : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst_is_rs1 = _GEN_681 ? uop_ldst_is_rs1 : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst = _GEN_681 ? uop_ldst : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1 = _GEN_681 ? uop_lrs1 : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2 = _GEN_681 ? uop_lrs2 : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs3 = _GEN_681 ? uop_lrs3 : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dst_rtype = _GEN_681 ? uop_dst_rtype : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1_rtype = _GEN_681 ? uop_lrs1_rtype : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2_rtype = _GEN_681 ? uop_lrs2_rtype : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_frs3_en = _GEN_681 ? uop_frs3_en : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_dw = _GEN_681 ? uop_fcn_dw : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_op = _GEN_681 ? uop_fcn_op : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_val = _GEN_681 ? uop_fp_val : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_rm = _GEN_681 ? uop_fp_rm : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_typ = _GEN_681 ? uop_fp_typ : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_pf_if = _GEN_681 ? uop_xcpt_pf_if : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ae_if = _GEN_681 ? uop_xcpt_ae_if : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ma_if = _GEN_681 ? uop_xcpt_ma_if : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_debug_if = _GEN_681 ? uop_bp_debug_if : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_xcpt_if = _GEN_681 ? uop_bp_xcpt_if : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_fsrc = _GEN_681 ? uop_debug_fsrc : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_tsrc = _GEN_681 ? uop_debug_tsrc : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] wire [31:0] _iresp_0_bits_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _iresp_0_bits_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _fresp_0_bits_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _fresp_0_bits_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_debug_wb_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_debug_wb_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _iresp_0_bits_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _fresp_0_bits_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_debug_wb_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] iresp_0_bits_data_shifted = _iresp_0_bits_data_shifted_T ? _iresp_0_bits_data_shifted_T_1 : _iresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] iresp_0_bits_data_zeroed = iresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_793 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_1 = _iresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_2 = iresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _iresp_0_bits_data_T_4 = {32{_iresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _iresp_0_bits_data_T_6 = _iresp_0_bits_data_T_1 ? _iresp_0_bits_data_T_4 : _iresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_7 = {_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _iresp_0_bits_data_shifted_T_4 = _iresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _iresp_0_bits_data_shifted_T_5 = _iresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] iresp_0_bits_data_shifted_1 = _iresp_0_bits_data_shifted_T_3 ? _iresp_0_bits_data_shifted_T_4 : _iresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] iresp_0_bits_data_zeroed_1 = iresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_794 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_9 = _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_10 = iresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _iresp_0_bits_data_T_12 = {48{_iresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _iresp_0_bits_data_T_13 = _iresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _iresp_0_bits_data_T_14 = _iresp_0_bits_data_T_9 ? _iresp_0_bits_data_T_12 : _iresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_15 = {_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _iresp_0_bits_data_shifted_T_7 = _iresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _iresp_0_bits_data_shifted_T_8 = _iresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] iresp_0_bits_data_shifted_2 = _iresp_0_bits_data_shifted_T_6 ? _iresp_0_bits_data_shifted_T_7 : _iresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] iresp_0_bits_data_zeroed_2 = iresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_795 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_17 = _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_18 = iresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _iresp_0_bits_data_T_20 = {56{_iresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _iresp_0_bits_data_T_21 = _iresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _iresp_0_bits_data_T_22 = _iresp_0_bits_data_T_17 ? _iresp_0_bits_data_T_20 : _iresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_23 = {_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign iresp_0_bits_data = _GEN_681 ? resp_data : _iresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] fresp_0_bits_data_shifted = _fresp_0_bits_data_shifted_T ? _fresp_0_bits_data_shifted_T_1 : _fresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] fresp_0_bits_data_zeroed = fresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_1 = _fresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_2 = fresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _fresp_0_bits_data_T_4 = {32{_fresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _fresp_0_bits_data_T_6 = _fresp_0_bits_data_T_1 ? _fresp_0_bits_data_T_4 : _fresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_7 = {_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _fresp_0_bits_data_shifted_T_4 = _fresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _fresp_0_bits_data_shifted_T_5 = _fresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] fresp_0_bits_data_shifted_1 = _fresp_0_bits_data_shifted_T_3 ? _fresp_0_bits_data_shifted_T_4 : _fresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] fresp_0_bits_data_zeroed_1 = fresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_9 = _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_10 = fresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _fresp_0_bits_data_T_12 = {48{_fresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _fresp_0_bits_data_T_13 = _fresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _fresp_0_bits_data_T_14 = _fresp_0_bits_data_T_9 ? _fresp_0_bits_data_T_12 : _fresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_15 = {_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _fresp_0_bits_data_shifted_T_7 = _fresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _fresp_0_bits_data_shifted_T_8 = _fresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] fresp_0_bits_data_shifted_2 = _fresp_0_bits_data_shifted_T_6 ? _fresp_0_bits_data_shifted_T_7 : _fresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] fresp_0_bits_data_zeroed_2 = fresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_17 = _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_18 = fresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _fresp_0_bits_data_T_20 = {56{_fresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _fresp_0_bits_data_T_21 = _fresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _fresp_0_bits_data_T_22 = _fresp_0_bits_data_T_17 ? _fresp_0_bits_data_T_20 : _fresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_23 = {_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign fresp_0_bits_data = _GEN_681 ? resp_data : _fresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire _GEN_796 = _T_1678 & _GEN_626; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_797 = ~_T_1676 & _GEN_796; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_0 = _GEN_797 \| (_GEN_654 ? _ldq_will_succeed_T : ~_GEN_102 & (_T_60 ? ~_GEN_77 & ldq_succeeded_0 : ~_GEN_28 & ldq_succeeded_0)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_798 = _T_1678 & _GEN_627; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_799 = ~_T_1676 & _GEN_798; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_1 = _GEN_799 \| (_GEN_655 ? _ldq_will_succeed_T : ~_GEN_103 & (_T_60 ? ~_GEN_78 & ldq_succeeded_1 : ~_GEN_29 & ldq_succeeded_1)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_800 = _T_1678 & _GEN_628; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_801 = ~_T_1676 & _GEN_800; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_2 = _GEN_801 \| (_GEN_656 ? _ldq_will_succeed_T : ~_GEN_104 & (_T_60 ? ~_GEN_79 & ldq_succeeded_2 : ~_GEN_30 & ldq_succeeded_2)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_802 = _T_1678 & _GEN_629; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_803 = ~_T_1676 & _GEN_802; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_3 = _GEN_803 \| (_GEN_657 ? _ldq_will_succeed_T : ~_GEN_105 & (_T_60 ? ~_GEN_80 & ldq_succeeded_3 : ~_GEN_31 & ldq_succeeded_3)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_804 = _T_1678 & _GEN_630; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_805 = ~_T_1676 & _GEN_804; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_4 = _GEN_805 \| (_GEN_658 ? _ldq_will_succeed_T : ~_GEN_106 & (_T_60 ? ~_GEN_81 & ldq_succeeded_4 : ~_GEN_32 & ldq_succeeded_4)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_806 = _T_1678 & _GEN_631; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_807 = ~_T_1676 & _GEN_806; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_5 = _GEN_807 \| (_GEN_659 ? _ldq_will_succeed_T : ~_GEN_107 & (_T_60 ? ~_GEN_82 & ldq_succeeded_5 : ~_GEN_33 & ldq_succeeded_5)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_808 = _T_1678 & _GEN_632; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_809 = ~_T_1676 & _GEN_808; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_6 = _GEN_809 \| (_GEN_660 ? _ldq_will_succeed_T : ~_GEN_108 & (_T_60 ? ~_GEN_83 & ldq_succeeded_6 : ~_GEN_34 & ldq_succeeded_6)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_810 = _T_1678 & _GEN_633; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_811 = ~_T_1676 & _GEN_810; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_7 = _GEN_811 \| (_GEN_661 ? _ldq_will_succeed_T : ~_GEN_109 & (_T_60 ? ~_GEN_84 & ldq_succeeded_7 : ~_GEN_35 & ldq_succeeded_7)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_812 = _T_1678 & _GEN_634; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_813 = ~_T_1676 & _GEN_812; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_8 = _GEN_813 \| (_GEN_662 ? _ldq_will_succeed_T : ~_GEN_110 & (_T_60 ? ~_GEN_85 & ldq_succeeded_8 : ~_GEN_36 & ldq_succeeded_8)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_814 = _T_1678 & _GEN_635; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_815 = ~_T_1676 & _GEN_814; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_9 = _GEN_815 \| (_GEN_663 ? _ldq_will_succeed_T : ~_GEN_111 & (_T_60 ? ~_GEN_86 & ldq_succeeded_9 : ~_GEN_37 & ldq_succeeded_9)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_816 = _T_1678 & _GEN_636; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_817 = ~_T_1676 & _GEN_816; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_10 = _GEN_817 \| (_GEN_664 ? _ldq_will_succeed_T : ~_GEN_112 & (_T_60 ? ~_GEN_87 & ldq_succeeded_10 : ~_GEN_38 & ldq_succeeded_10)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_818 = _T_1678 & _GEN_637; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_819 = ~_T_1676 & _GEN_818; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_11 = _GEN_819 \| (_GEN_665 ? _ldq_will_succeed_T : ~_GEN_113 & (_T_60 ? ~_GEN_88 & ldq_succeeded_11 : ~_GEN_39 & ldq_succeeded_11)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_820 = _T_1678 & _GEN_638; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_821 = ~_T_1676 & _GEN_820; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_12 = _GEN_821 \| (_GEN_666 ? _ldq_will_succeed_T : ~_GEN_114 & (_T_60 ? ~_GEN_89 & ldq_succeeded_12 : ~_GEN_40 & ldq_succeeded_12)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_822 = _T_1678 & _GEN_639; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_823 = ~_T_1676 & _GEN_822; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_13 = _GEN_823 \| (_GEN_667 ? _ldq_will_succeed_T : ~_GEN_115 & (_T_60 ? ~_GEN_90 & ldq_succeeded_13 : ~_GEN_41 & ldq_succeeded_13)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_824 = _T_1678 & _GEN_640; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_825 = ~_T_1676 & _GEN_824; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_14 = _GEN_825 \| (_GEN_668 ? _ldq_will_succeed_T : ~_GEN_116 & (_T_60 ? ~_GEN_91 & ldq_succeeded_14 : ~_GEN_42 & ldq_succeeded_14)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_826 = _T_1678 & _GEN_641; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_827 = ~_T_1676 & _GEN_826; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_15 = _GEN_827 \| (_GEN_669 ? _ldq_will_succeed_T : ~_GEN_117 & (_T_60 ? ~_GEN_92 & ldq_succeeded_15 : ~_GEN_43 & ldq_succeeded_15)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_828 = _T_1678 & _GEN_642; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_829 = ~_T_1676 & _GEN_828; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_16 = _GEN_829 \| (_GEN_670 ? _ldq_will_succeed_T : ~_GEN_118 & (_T_60 ? ~_GEN_93 & ldq_succeeded_16 : ~_GEN_44 & ldq_succeeded_16)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_830 = _T_1678 & _GEN_643; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_831 = ~_T_1676 & _GEN_830; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_17 = _GEN_831 \| (_GEN_671 ? _ldq_will_succeed_T : ~_GEN_119 & (_T_60 ? ~_GEN_94 & ldq_succeeded_17 : ~_GEN_45 & ldq_succeeded_17)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_832 = _T_1678 & _GEN_644; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_833 = ~_T_1676 & _GEN_832; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_18 = _GEN_833 \| (_GEN_672 ? _ldq_will_succeed_T : ~_GEN_120 & (_T_60 ? ~_GEN_95 & ldq_succeeded_18 : ~_GEN_46 & ldq_succeeded_18)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_834 = _T_1678 & _GEN_645; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_835 = ~_T_1676 & _GEN_834; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_19 = _GEN_835 \| (_GEN_673 ? _ldq_will_succeed_T : ~_GEN_121 & (_T_60 ? ~_GEN_96 & ldq_succeeded_19 : ~_GEN_47 & ldq_succeeded_19)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_836 = _T_1678 & _GEN_646; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_837 = ~_T_1676 & _GEN_836; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_20 = _GEN_837 \| (_GEN_674 ? _ldq_will_succeed_T : ~_GEN_122 & (_T_60 ? ~_GEN_97 & ldq_succeeded_20 : ~_GEN_48 & ldq_succeeded_20)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_838 = _T_1678 & _GEN_647; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_839 = ~_T_1676 & _GEN_838; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_21 = _GEN_839 \| (_GEN_675 ? _ldq_will_succeed_T : ~_GEN_123 & (_T_60 ? ~_GEN_98 & ldq_succeeded_21 : ~_GEN_49 & ldq_succeeded_21)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_840 = _T_1678 & _GEN_648; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_841 = ~_T_1676 & _GEN_840; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_22 = _GEN_841 \| (_GEN_676 ? _ldq_will_succeed_T : ~_GEN_124 & (_T_60 ? ~_GEN_99 & ldq_succeeded_22 : ~_GEN_50 & ldq_succeeded_22)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_842 = _T_1678 & _GEN_649; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_843 = ~_T_1676 & _GEN_842; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_23 = _GEN_843 \| (_GEN_677 ? _ldq_will_succeed_T : ~_GEN_125 & (_T_60 ? ~_GEN_100 & ldq_succeeded_23 : ~_GEN_51 & ldq_succeeded_23)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire [31:0] ldq_debug_wb_data_shifted = _ldq_debug_wb_data_shifted_T ? _ldq_debug_wb_data_shifted_T_1 : _ldq_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_debug_wb_data_zeroed = ldq_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_1 = _ldq_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_2 = ldq_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_debug_wb_data_T_4 = {32{_ldq_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_debug_wb_data_T_6 = _ldq_debug_wb_data_T_1 ? _ldq_debug_wb_data_T_4 : _ldq_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_7 = {_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_debug_wb_data_shifted_T_4 = _ldq_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_debug_wb_data_shifted_T_5 = _ldq_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_debug_wb_data_shifted_1 = _ldq_debug_wb_data_shifted_T_3 ? _ldq_debug_wb_data_shifted_T_4 : _ldq_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_debug_wb_data_zeroed_1 = ldq_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_9 = _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_10 = ldq_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_debug_wb_data_T_12 = {48{_ldq_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_debug_wb_data_T_13 = _ldq_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_debug_wb_data_T_14 = _ldq_debug_wb_data_T_9 ? _ldq_debug_wb_data_T_12 : _ldq_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_15 = {_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_debug_wb_data_shifted_T_7 = _ldq_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_debug_wb_data_shifted_T_8 = _ldq_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_debug_wb_data_shifted_2 = _ldq_debug_wb_data_shifted_T_6 ? _ldq_debug_wb_data_shifted_T_7 : _ldq_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_debug_wb_data_zeroed_2 = ldq_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_17 = _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_18 = ldq_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_debug_wb_data_T_20 = {56{_ldq_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_debug_wb_data_T_21 = _ldq_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_debug_wb_data_T_22 = _ldq_debug_wb_data_T_17 ? _ldq_debug_wb_data_T_20 : _ldq_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_23 = {_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _slow_wakeups_0_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] slow_wakeups_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire slow_wakeups_0_out_valid; // @[util.scala:114:23] wire [15:0] _slow_wakeups_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _slow_wakeups_0_out_bits_uop_br_mask_T_1 = wb_slow_wakeups_0_bits_uop_br_mask & _slow_wakeups_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign slow_wakeups_0_out_bits_uop_br_mask = _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _slow_wakeups_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & wb_slow_wakeups_0_bits_uop_br_mask; // @[util.scala:126:51] wire _slow_wakeups_0_out_valid_T_1 = \|_slow_wakeups_0_out_valid_T; // @[util.scala:126:{51,59}] wire _slow_wakeups_0_out_valid_T_2 = _slow_wakeups_0_out_valid_T_1 \| io_core_exception_0; // @[util.scala:61:61, :126:59] wire _slow_wakeups_0_out_valid_T_3 = ~_slow_wakeups_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _slow_wakeups_0_out_valid_T_4 = wb_slow_wakeups_0_valid & _slow_wakeups_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign slow_wakeups_0_out_valid = _slow_wakeups_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg slow_wakeups_0_REG_valid; // @[lsu.scala:1647:79] assign slow_wakeups_0_valid = slow_wakeups_0_REG_valid; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_inst = slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_inst = slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rvc = slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1495:26, :1647:79] reg [39:0] slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_pc = slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_0 = slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_1 = slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_2 = slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_3 = slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_0 = slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_1 = slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_2 = slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_3 = slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_4 = slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_5 = slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_6 = slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_7 = slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_8 = slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_9 = slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued = slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_agen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_dgen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p3_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dis_col_sel = slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1495:26, :1647:79] reg [15:0] slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_mask = slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_tag = slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_type = slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfb = slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fence = slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fencei = slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfence = slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_amo = slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_eret = slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sys_pc2epc = slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rocc = slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_mov = slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ftq_idx = slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_edge_inst = slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pc_lob = slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_taken = slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_rename = slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_sel = slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pimm = slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1495:26, :1647:79] reg [19:0] slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_packed = slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op1_sel = slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op2_sel = slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ldst = slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wen = slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren1 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren2 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren3 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap12 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap23 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fromint = slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_toint = slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fma = slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_div = slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_sqrt = slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wflags = slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_vec = slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rob_idx = slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldq_idx = slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stq_idx = slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rxq_idx = slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pdst = slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1 = slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2 = slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3 = slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred = slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1_busy = slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2_busy = slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3_busy = slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred_busy = slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stale_pdst = slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exception = slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1495:26, :1647:79] reg [63:0] slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exc_cause = slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_cmd = slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_size = slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_signed = slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_ldq = slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_stq = slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_unique = slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_flush_on_commit = slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_csr_cmd = slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst_is_rs1 = slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst = slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1 = slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2 = slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs3 = slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dst_rtype = slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1_rtype = slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2_rtype = slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_frs3_en = slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_dw = slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_op = slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_val = slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_rm = slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_typ = slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_pf_if = slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ae_if = slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ma_if = slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_debug_if = slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_xcpt_if = slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_fsrc = slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_tsrc = slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1495:26, :1647:79] wire [15:0] _stq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_0_br_mask_T_1 = uop_1_br_mask & _stq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_1_br_mask_T_1 = uop_2_br_mask & _stq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_2_br_mask_T_1 = uop_3_br_mask & _stq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_3_br_mask_T_1 = uop_4_br_mask & _stq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_4_br_mask_T_1 = uop_5_br_mask & _stq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_5_br_mask_T_1 = uop_6_br_mask & _stq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_6_br_mask_T_1 = uop_7_br_mask & _stq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_7_br_mask_T_1 = uop_8_br_mask & _stq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_8_br_mask_T_1 = uop_9_br_mask & _stq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_9_br_mask_T_1 = uop_10_br_mask & _stq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_10_br_mask_T_1 = uop_11_br_mask & _stq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_11_br_mask_T_1 = uop_12_br_mask & _stq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_12_br_mask_T_1 = uop_13_br_mask & _stq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_13_br_mask_T_1 = uop_14_br_mask & _stq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_14_br_mask_T_1 = uop_15_br_mask & _stq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_15_br_mask_T_1 = uop_16_br_mask & _stq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_16_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_16_br_mask_T_1 = uop_17_br_mask & _stq_uop_16_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_17_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_17_br_mask_T_1 = uop_18_br_mask & _stq_uop_17_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_18_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_18_br_mask_T_1 = uop_19_br_mask & _stq_uop_18_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_19_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_19_br_mask_T_1 = uop_20_br_mask & _stq_uop_19_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_20_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_20_br_mask_T_1 = uop_21_br_mask & _stq_uop_20_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_21_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_21_br_mask_T_1 = uop_22_br_mask & _stq_uop_21_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_22_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_22_br_mask_T_1 = uop_23_br_mask & _stq_uop_22_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_23_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_23_br_mask_T_1 = uop_24_br_mask & _stq_uop_23_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_0_br_mask_T_1 = uop_25_br_mask & _ldq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_1_br_mask_T_1 = uop_26_br_mask & _ldq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_2_br_mask_T_1 = uop_27_br_mask & _ldq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_3_br_mask_T_1 = uop_28_br_mask & _ldq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_4_br_mask_T_1 = uop_29_br_mask & _ldq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_5_br_mask_T_1 = uop_30_br_mask & _ldq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_6_br_mask_T_1 = uop_31_br_mask & _ldq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_7_br_mask_T_1 = uop_32_br_mask & _ldq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_8_br_mask_T_1 = uop_33_br_mask & _ldq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_9_br_mask_T_1 = uop_34_br_mask & _ldq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_10_br_mask_T_1 = uop_35_br_mask & _ldq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_11_br_mask_T_1 = uop_36_br_mask & _ldq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_12_br_mask_T_1 = uop_37_br_mask & _ldq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_13_br_mask_T_1 = uop_38_br_mask & _ldq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_14_br_mask_T_1 = uop_39_br_mask & _ldq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_15_br_mask_T_1 = uop_40_br_mask & _ldq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_16_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_16_br_mask_T_1 = uop_41_br_mask & _ldq_uop_16_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_17_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_17_br_mask_T_1 = uop_42_br_mask & _ldq_uop_17_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_18_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_18_br_mask_T_1 = uop_43_br_mask & _ldq_uop_18_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_19_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_19_br_mask_T_1 = uop_44_br_mask & _ldq_uop_19_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_20_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_20_br_mask_T_1 = uop_45_br_mask & _ldq_uop_20_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_21_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_21_br_mask_T_1 = uop_46_br_mask & _ldq_uop_21_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_22_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_22_br_mask_T_1 = uop_47_br_mask & _ldq_uop_22_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_23_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_23_br_mask_T_1 = uop_48_br_mask & _ldq_uop_23_br_mask_T; // @[util.scala:97:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_24_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_24_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_24_debug_inst; // @[lsu.scala:1728:25] wire l_uop_24_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_24_debug_pc; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_24_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_24_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_24_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_24_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_24_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_24_br_type; // @[lsu.scala:1728:25] wire l_uop_24_is_sfb; // @[lsu.scala:1728:25] wire l_uop_24_is_fence; // @[lsu.scala:1728:25] wire l_uop_24_is_fencei; // @[lsu.scala:1728:25] wire l_uop_24_is_sfence; // @[lsu.scala:1728:25] wire l_uop_24_is_amo; // @[lsu.scala:1728:25] wire l_uop_24_is_eret; // @[lsu.scala:1728:25] wire l_uop_24_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_24_is_rocc; // @[lsu.scala:1728:25] wire l_uop_24_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_24_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_pc_lob; // @[lsu.scala:1728:25] wire l_uop_24_taken; // @[lsu.scala:1728:25] wire l_uop_24_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_24_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ppred; // @[lsu.scala:1728:25] wire l_uop_24_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_24_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_24_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_24_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_24_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_24_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_mem_size; // @[lsu.scala:1728:25] wire l_uop_24_mem_signed; // @[lsu.scala:1728:25] wire l_uop_24_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_24_uses_stq; // @[lsu.scala:1728:25] wire l_uop_24_is_unique; // @[lsu.scala:1728:25] wire l_uop_24_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_24_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_24_frs3_en; // @[lsu.scala:1728:25] wire l_uop_24_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_fcn_op; // @[lsu.scala:1728:25] wire l_uop_24_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_typ; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_24_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_24_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_24_inst = _GEN_127[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_inst = _GEN_128[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_rvc = _GEN_129[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_pc = _GEN_130[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_0 = _GEN_131[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_1 = _GEN_132[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_2 = _GEN_133[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_3 = _GEN_134[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_0 = _GEN_135[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_1 = _GEN_136[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_2 = _GEN_137[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_3 = _GEN_138[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_4 = _GEN_139[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_5 = _GEN_140[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_6 = _GEN_141[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_7 = _GEN_142[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_8 = _GEN_143[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_9 = _GEN_144[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued = _GEN_145[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued_partial_agen = _GEN_146[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued_partial_dgen = _GEN_147[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p1_speculative_child = _GEN_148[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p2_speculative_child = _GEN_149[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p1_bypass_hint = _GEN_150[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p2_bypass_hint = _GEN_151[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p3_bypass_hint = _GEN_152[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_dis_col_sel = _GEN_153[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_mask = _GEN_154[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_tag = _GEN_155[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_type = _GEN_156[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sfb = _GEN_157[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_fence = _GEN_158[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_fencei = _GEN_159[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sfence = _GEN_160[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_amo = _GEN_161[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_eret = _GEN_162[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sys_pc2epc = _GEN_163[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_rocc = _GEN_164[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_mov = _GEN_165[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ftq_idx = _GEN_166[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_edge_inst = _GEN_167[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pc_lob = _GEN_168[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_taken = _GEN_169[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_rename = _GEN_170[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_sel = _GEN_171[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pimm = _GEN_172[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_packed = _GEN_173[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_op1_sel = _GEN_174[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_op2_sel = _GEN_175[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ldst = _GEN_176[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_wen = _GEN_177[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren1 = _GEN_178[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren2 = _GEN_179[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren3 = _GEN_180[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_swap12 = _GEN_181[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_swap23 = _GEN_182[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_typeTagIn = _GEN_183[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_typeTagOut = _GEN_184[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fromint = _GEN_185[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_toint = _GEN_186[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fastpipe = _GEN_187[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fma = _GEN_188[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_div = _GEN_189[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_sqrt = _GEN_190[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_wflags = _GEN_191[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_vec = _GEN_192[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_rob_idx = _GEN_193[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldq_idx = _GEN_194[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_stq_idx = _GEN_195[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_rxq_idx = _GEN_196[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pdst = _GEN_197[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs1 = _GEN_198[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs2 = _GEN_199[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs3 = _GEN_200[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ppred = _GEN_201[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs1_busy = _GEN_202[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs2_busy = _GEN_203[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs3_busy = _GEN_204[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ppred_busy = _GEN_205[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_stale_pdst = _GEN_206[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_exception = _GEN_207[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_exc_cause = _GEN_208[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_cmd = _GEN_209[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_size = _GEN_210[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_signed = _GEN_211[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_uses_ldq = _GEN_212[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_uses_stq = _GEN_213[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_unique = _GEN_214[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_flush_on_commit = _GEN_215[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_csr_cmd = _GEN_216[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldst_is_rs1 = _GEN_217[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldst = _GEN_218[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs1 = _GEN_219[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs2 = _GEN_220[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs3 = _GEN_221[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_dst_rtype = _GEN_222[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs1_rtype = _GEN_223[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs2_rtype = _GEN_224[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_frs3_en = _GEN_225[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fcn_dw = _GEN_226[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fcn_op = _GEN_227[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_val = _GEN_228[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_rm = _GEN_229[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_typ = _GEN_230[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_pf_if = _GEN_231[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_ae_if = _GEN_232[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_ma_if = _GEN_233[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_bp_debug_if = _GEN_234[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_bp_xcpt_if = _GEN_235[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_fsrc = _GEN_236[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_tsrc = _GEN_237[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] wire s_uop_27_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_27_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_27_debug_inst; // @[lsu.scala:1729:25] wire s_uop_27_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_27_debug_pc; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_27_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_27_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_27_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_27_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_27_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_27_br_type; // @[lsu.scala:1729:25] wire s_uop_27_is_sfb; // @[lsu.scala:1729:25] wire s_uop_27_is_fence; // @[lsu.scala:1729:25] wire s_uop_27_is_fencei; // @[lsu.scala:1729:25] wire s_uop_27_is_sfence; // @[lsu.scala:1729:25] wire s_uop_27_is_amo; // @[lsu.scala:1729:25] wire s_uop_27_is_eret; // @[lsu.scala:1729:25] wire s_uop_27_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_27_is_rocc; // @[lsu.scala:1729:25] wire s_uop_27_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_27_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_pc_lob; // @[lsu.scala:1729:25] wire s_uop_27_taken; // @[lsu.scala:1729:25] wire s_uop_27_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_27_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ppred; // @[lsu.scala:1729:25] wire s_uop_27_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_27_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_27_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_27_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_27_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_27_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_mem_size; // @[lsu.scala:1729:25] wire s_uop_27_mem_signed; // @[lsu.scala:1729:25] wire s_uop_27_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_27_uses_stq; // @[lsu.scala:1729:25] wire s_uop_27_is_unique; // @[lsu.scala:1729:25] wire s_uop_27_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_27_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_27_frs3_en; // @[lsu.scala:1729:25] wire s_uop_27_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_fcn_op; // @[lsu.scala:1729:25] wire s_uop_27_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_typ; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_27_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_27_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_27_inst = _GEN_251[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_inst = _GEN_252[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_rvc = _GEN_253[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_pc = _GEN_254[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_0 = _GEN_255[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_1 = _GEN_256[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_2 = _GEN_257[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_3 = _GEN_258[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_0 = _GEN_259[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_1 = _GEN_260[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_2 = _GEN_261[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_3 = _GEN_262[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_4 = _GEN_263[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_5 = _GEN_264[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_6 = _GEN_265[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_7 = _GEN_266[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_8 = _GEN_267[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_9 = _GEN_268[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued = _GEN_269[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued_partial_agen = _GEN_270[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued_partial_dgen = _GEN_271[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p1_speculative_child = _GEN_272[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p2_speculative_child = _GEN_273[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p1_bypass_hint = _GEN_274[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p2_bypass_hint = _GEN_275[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p3_bypass_hint = _GEN_276[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_dis_col_sel = _GEN_277[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_mask = _GEN_278[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_tag = _GEN_279[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_type = _GEN_280[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sfb = _GEN_281[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_fence = _GEN_282[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_fencei = _GEN_283[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sfence = _GEN_284[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_amo = _GEN_285[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_eret = _GEN_286[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sys_pc2epc = _GEN_287[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_rocc = _GEN_288[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_mov = _GEN_289[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ftq_idx = _GEN_290[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_edge_inst = _GEN_291[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pc_lob = _GEN_292[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_taken = _GEN_293[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_rename = _GEN_294[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_sel = _GEN_295[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pimm = _GEN_296[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_packed = _GEN_297[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_op1_sel = _GEN_298[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_op2_sel = _GEN_299[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ldst = _GEN_300[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_wen = _GEN_301[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren1 = _GEN_302[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren2 = _GEN_303[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren3 = _GEN_304[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_swap12 = _GEN_305[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_swap23 = _GEN_306[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_typeTagIn = _GEN_307[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_typeTagOut = _GEN_308[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fromint = _GEN_309[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_toint = _GEN_310[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fastpipe = _GEN_311[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fma = _GEN_312[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_div = _GEN_313[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_sqrt = _GEN_314[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_wflags = _GEN_315[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_vec = _GEN_316[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_rob_idx = _GEN_317[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldq_idx = _GEN_318[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_stq_idx = _GEN_319[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_rxq_idx = _GEN_320[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pdst = _GEN_321[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs1 = _GEN_322[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs2 = _GEN_323[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs3 = _GEN_324[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ppred = _GEN_325[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs1_busy = _GEN_326[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs2_busy = _GEN_327[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs3_busy = _GEN_328[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ppred_busy = _GEN_329[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_stale_pdst = _GEN_330[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_exception = _GEN_331[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_exc_cause = _GEN_332[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_cmd = _GEN_333[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_size = _GEN_334[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_signed = _GEN_335[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_uses_ldq = _GEN_336[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_uses_stq = _GEN_337[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_unique = _GEN_338[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_flush_on_commit = _GEN_339[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_csr_cmd = _GEN_340[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldst_is_rs1 = _GEN_341[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldst = _GEN_342[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs1 = _GEN_343[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs2 = _GEN_344[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs3 = _GEN_345[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_dst_rtype = _GEN_346[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs1_rtype = _GEN_347[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs2_rtype = _GEN_348[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_frs3_en = _GEN_349[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fcn_dw = _GEN_350[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fcn_op = _GEN_351[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_val = _GEN_352[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_rm = _GEN_353[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_typ = _GEN_354[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_pf_if = _GEN_355[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_ae_if = _GEN_356[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_ma_if = _GEN_357[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_bp_debug_if = _GEN_358[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_bp_xcpt_if = _GEN_359[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_fsrc = _GEN_360[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_tsrc = _GEN_361[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] wire wrap_9 = stq_commit_head == 5'h17; // @[util.scala:213:25] wire _GEN_844 = ~commit_store & commit_load; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_845 = _GEN_844 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire _GEN_846 = _GEN_25[ldq_head]; // @[lsu.scala:278:29, :387:15, :1736:14] wire wrap_10 = ldq_head == 5'h17; // @[util.scala:213:25] wire [4:0] _T_2078 = wrap_9 ? 5'h0 : stq_commit_head + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2079 = commit_store ? _T_2078 : stq_commit_head; // @[util.scala:214:10] wire [4:0] _T_2082 = wrap_10 ? 5'h0 : ldq_head + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2083 = commit_load ? _T_2082 : ldq_head; // @[util.scala:214:10] wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_25_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_25_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_25_debug_inst; // @[lsu.scala:1728:25] wire l_uop_25_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_25_debug_pc; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_25_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_25_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_25_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_25_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_25_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_25_br_type; // @[lsu.scala:1728:25] wire l_uop_25_is_sfb; // @[lsu.scala:1728:25] wire l_uop_25_is_fence; // @[lsu.scala:1728:25] wire l_uop_25_is_fencei; // @[lsu.scala:1728:25] wire l_uop_25_is_sfence; // @[lsu.scala:1728:25] wire l_uop_25_is_amo; // @[lsu.scala:1728:25] wire l_uop_25_is_eret; // @[lsu.scala:1728:25] wire l_uop_25_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_25_is_rocc; // @[lsu.scala:1728:25] wire l_uop_25_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_25_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_pc_lob; // @[lsu.scala:1728:25] wire l_uop_25_taken; // @[lsu.scala:1728:25] wire l_uop_25_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_25_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ppred; // @[lsu.scala:1728:25] wire l_uop_25_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_25_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_25_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_25_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_25_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_25_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_mem_size; // @[lsu.scala:1728:25] wire l_uop_25_mem_signed; // @[lsu.scala:1728:25] wire l_uop_25_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_25_uses_stq; // @[lsu.scala:1728:25] wire l_uop_25_is_unique; // @[lsu.scala:1728:25] wire l_uop_25_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_25_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_25_frs3_en; // @[lsu.scala:1728:25] wire l_uop_25_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_fcn_op; // @[lsu.scala:1728:25] wire l_uop_25_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_typ; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_25_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_25_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_25_inst = _GEN_127[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_inst = _GEN_128[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_rvc = _GEN_129[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_pc = _GEN_130[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_0 = _GEN_131[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_1 = _GEN_132[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_2 = _GEN_133[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_3 = _GEN_134[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_0 = _GEN_135[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_1 = _GEN_136[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_2 = _GEN_137[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_3 = _GEN_138[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_4 = _GEN_139[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_5 = _GEN_140[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_6 = _GEN_141[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_7 = _GEN_142[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_8 = _GEN_143[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_9 = _GEN_144[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued = _GEN_145[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued_partial_agen = _GEN_146[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued_partial_dgen = _GEN_147[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p1_speculative_child = _GEN_148[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p2_speculative_child = _GEN_149[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p1_bypass_hint = _GEN_150[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p2_bypass_hint = _GEN_151[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p3_bypass_hint = _GEN_152[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_dis_col_sel = _GEN_153[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_mask = _GEN_154[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_tag = _GEN_155[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_type = _GEN_156[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sfb = _GEN_157[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_fence = _GEN_158[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_fencei = _GEN_159[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sfence = _GEN_160[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_amo = _GEN_161[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_eret = _GEN_162[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sys_pc2epc = _GEN_163[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_rocc = _GEN_164[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_mov = _GEN_165[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ftq_idx = _GEN_166[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_edge_inst = _GEN_167[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pc_lob = _GEN_168[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_taken = _GEN_169[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_rename = _GEN_170[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_sel = _GEN_171[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pimm = _GEN_172[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_packed = _GEN_173[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_op1_sel = _GEN_174[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_op2_sel = _GEN_175[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ldst = _GEN_176[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_wen = _GEN_177[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren1 = _GEN_178[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren2 = _GEN_179[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren3 = _GEN_180[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_swap12 = _GEN_181[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_swap23 = _GEN_182[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_typeTagIn = _GEN_183[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_typeTagOut = _GEN_184[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fromint = _GEN_185[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_toint = _GEN_186[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fastpipe = _GEN_187[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fma = _GEN_188[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_div = _GEN_189[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_sqrt = _GEN_190[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_wflags = _GEN_191[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_vec = _GEN_192[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_rob_idx = _GEN_193[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldq_idx = _GEN_194[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_stq_idx = _GEN_195[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_rxq_idx = _GEN_196[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pdst = _GEN_197[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs1 = _GEN_198[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs2 = _GEN_199[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs3 = _GEN_200[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ppred = _GEN_201[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs1_busy = _GEN_202[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs2_busy = _GEN_203[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs3_busy = _GEN_204[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ppred_busy = _GEN_205[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_stale_pdst = _GEN_206[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_exception = _GEN_207[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_exc_cause = _GEN_208[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_cmd = _GEN_209[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_size = _GEN_210[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_signed = _GEN_211[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_uses_ldq = _GEN_212[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_uses_stq = _GEN_213[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_unique = _GEN_214[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_flush_on_commit = _GEN_215[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_csr_cmd = _GEN_216[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldst_is_rs1 = _GEN_217[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldst = _GEN_218[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs1 = _GEN_219[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs2 = _GEN_220[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs3 = _GEN_221[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_dst_rtype = _GEN_222[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs1_rtype = _GEN_223[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs2_rtype = _GEN_224[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_frs3_en = _GEN_225[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fcn_dw = _GEN_226[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fcn_op = _GEN_227[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_val = _GEN_228[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_rm = _GEN_229[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_typ = _GEN_230[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_pf_if = _GEN_231[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_ae_if = _GEN_232[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_ma_if = _GEN_233[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_bp_debug_if = _GEN_234[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_bp_xcpt_if = _GEN_235[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_fsrc = _GEN_236[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_tsrc = _GEN_237[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_28_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_28_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_28_debug_inst; // @[lsu.scala:1729:25] wire s_uop_28_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_28_debug_pc; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_28_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_28_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_28_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_28_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_28_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_28_br_type; // @[lsu.scala:1729:25] wire s_uop_28_is_sfb; // @[lsu.scala:1729:25] wire s_uop_28_is_fence; // @[lsu.scala:1729:25] wire s_uop_28_is_fencei; // @[lsu.scala:1729:25] wire s_uop_28_is_sfence; // @[lsu.scala:1729:25] wire s_uop_28_is_amo; // @[lsu.scala:1729:25] wire s_uop_28_is_eret; // @[lsu.scala:1729:25] wire s_uop_28_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_28_is_rocc; // @[lsu.scala:1729:25] wire s_uop_28_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_28_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_pc_lob; // @[lsu.scala:1729:25] wire s_uop_28_taken; // @[lsu.scala:1729:25] wire s_uop_28_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_28_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ppred; // @[lsu.scala:1729:25] wire s_uop_28_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_28_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_28_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_28_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_28_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_28_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_mem_size; // @[lsu.scala:1729:25] wire s_uop_28_mem_signed; // @[lsu.scala:1729:25] wire s_uop_28_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_28_uses_stq; // @[lsu.scala:1729:25] wire s_uop_28_is_unique; // @[lsu.scala:1729:25] wire s_uop_28_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_28_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_28_frs3_en; // @[lsu.scala:1729:25] wire s_uop_28_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_fcn_op; // @[lsu.scala:1729:25] wire s_uop_28_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_typ; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_28_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_28_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_28_inst = _GEN_251[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_inst = _GEN_252[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_rvc = _GEN_253[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_pc = _GEN_254[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_0 = _GEN_255[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_1 = _GEN_256[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_2 = _GEN_257[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_3 = _GEN_258[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_0 = _GEN_259[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_1 = _GEN_260[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_2 = _GEN_261[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_3 = _GEN_262[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_4 = _GEN_263[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_5 = _GEN_264[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_6 = _GEN_265[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_7 = _GEN_266[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_8 = _GEN_267[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_9 = _GEN_268[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued = _GEN_269[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued_partial_agen = _GEN_270[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued_partial_dgen = _GEN_271[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p1_speculative_child = _GEN_272[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p2_speculative_child = _GEN_273[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p1_bypass_hint = _GEN_274[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p2_bypass_hint = _GEN_275[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p3_bypass_hint = _GEN_276[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_dis_col_sel = _GEN_277[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_mask = _GEN_278[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_tag = _GEN_279[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_type = _GEN_280[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sfb = _GEN_281[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_fence = _GEN_282[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_fencei = _GEN_283[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sfence = _GEN_284[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_amo = _GEN_285[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_eret = _GEN_286[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sys_pc2epc = _GEN_287[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_rocc = _GEN_288[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_mov = _GEN_289[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ftq_idx = _GEN_290[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_edge_inst = _GEN_291[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pc_lob = _GEN_292[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_taken = _GEN_293[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_rename = _GEN_294[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_sel = _GEN_295[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pimm = _GEN_296[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_packed = _GEN_297[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_op1_sel = _GEN_298[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_op2_sel = _GEN_299[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ldst = _GEN_300[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_wen = _GEN_301[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren1 = _GEN_302[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren2 = _GEN_303[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren3 = _GEN_304[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_swap12 = _GEN_305[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_swap23 = _GEN_306[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_typeTagIn = _GEN_307[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_typeTagOut = _GEN_308[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fromint = _GEN_309[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_toint = _GEN_310[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fastpipe = _GEN_311[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fma = _GEN_312[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_div = _GEN_313[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_sqrt = _GEN_314[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_wflags = _GEN_315[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_vec = _GEN_316[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_rob_idx = _GEN_317[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldq_idx = _GEN_318[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_stq_idx = _GEN_319[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_rxq_idx = _GEN_320[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pdst = _GEN_321[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs1 = _GEN_322[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs2 = _GEN_323[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs3 = _GEN_324[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ppred = _GEN_325[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs1_busy = _GEN_326[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs2_busy = _GEN_327[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs3_busy = _GEN_328[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ppred_busy = _GEN_329[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_stale_pdst = _GEN_330[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_exception = _GEN_331[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_exc_cause = _GEN_332[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_cmd = _GEN_333[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_size = _GEN_334[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_signed = _GEN_335[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_uses_ldq = _GEN_336[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_uses_stq = _GEN_337[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_unique = _GEN_338[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_flush_on_commit = _GEN_339[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_csr_cmd = _GEN_340[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldst_is_rs1 = _GEN_341[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldst = _GEN_342[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs1 = _GEN_343[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs2 = _GEN_344[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs3 = _GEN_345[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_dst_rtype = _GEN_346[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs1_rtype = _GEN_347[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs2_rtype = _GEN_348[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_frs3_en = _GEN_349[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fcn_dw = _GEN_350[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fcn_op = _GEN_351[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_val = _GEN_352[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_rm = _GEN_353[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_typ = _GEN_354[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_pf_if = _GEN_355[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_ae_if = _GEN_356[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_ma_if = _GEN_357[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_bp_debug_if = _GEN_358[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_bp_xcpt_if = _GEN_359[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_fsrc = _GEN_360[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_tsrc = _GEN_361[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire wrap_11 = _T_2079 == 5'h17; // @[util.scala:213:25] wire _GEN_847 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_848 = _GEN_847 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire wrap_12 = _T_2083 == 5'h17; // @[util.scala:213:25] wire [4:0] _T_2094 = wrap_11 ? 5'h0 : _T_2079 + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2095 = commit_store_1 ? _T_2094 : _T_2079; // @[util.scala:214:10] wire [4:0] _T_2098 = wrap_12 ? 5'h0 : _T_2083 + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2099 = commit_load_1 ? _T_2098 : _T_2083; // @[util.scala:214:10] wire commit_store_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_26_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_26_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_26_debug_inst; // @[lsu.scala:1728:25] wire l_uop_26_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_26_debug_pc; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_26_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_26_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_26_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_26_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_26_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_26_br_type; // @[lsu.scala:1728:25] wire l_uop_26_is_sfb; // @[lsu.scala:1728:25] wire l_uop_26_is_fence; // @[lsu.scala:1728:25] wire l_uop_26_is_fencei; // @[lsu.scala:1728:25] wire l_uop_26_is_sfence; // @[lsu.scala:1728:25] wire l_uop_26_is_amo; // @[lsu.scala:1728:25] wire l_uop_26_is_eret; // @[lsu.scala:1728:25] wire l_uop_26_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_26_is_rocc; // @[lsu.scala:1728:25] wire l_uop_26_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_26_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_pc_lob; // @[lsu.scala:1728:25] wire l_uop_26_taken; // @[lsu.scala:1728:25] wire l_uop_26_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_26_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ppred; // @[lsu.scala:1728:25] wire l_uop_26_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_26_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_26_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_26_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_26_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_26_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_mem_size; // @[lsu.scala:1728:25] wire l_uop_26_mem_signed; // @[lsu.scala:1728:25] wire l_uop_26_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_26_uses_stq; // @[lsu.scala:1728:25] wire l_uop_26_is_unique; // @[lsu.scala:1728:25] wire l_uop_26_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_26_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_26_frs3_en; // @[lsu.scala:1728:25] wire l_uop_26_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_fcn_op; // @[lsu.scala:1728:25] wire l_uop_26_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_typ; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_26_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_26_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_26_inst = _GEN_127[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_inst = _GEN_128[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_rvc = _GEN_129[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_pc = _GEN_130[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_0 = _GEN_131[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_1 = _GEN_132[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_2 = _GEN_133[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_3 = _GEN_134[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_0 = _GEN_135[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_1 = _GEN_136[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_2 = _GEN_137[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_3 = _GEN_138[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_4 = _GEN_139[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_5 = _GEN_140[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_6 = _GEN_141[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_7 = _GEN_142[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_8 = _GEN_143[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_9 = _GEN_144[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued = _GEN_145[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued_partial_agen = _GEN_146[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued_partial_dgen = _GEN_147[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p1_speculative_child = _GEN_148[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p2_speculative_child = _GEN_149[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p1_bypass_hint = _GEN_150[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p2_bypass_hint = _GEN_151[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p3_bypass_hint = _GEN_152[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_dis_col_sel = _GEN_153[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_mask = _GEN_154[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_tag = _GEN_155[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_type = _GEN_156[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sfb = _GEN_157[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_fence = _GEN_158[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_fencei = _GEN_159[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sfence = _GEN_160[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_amo = _GEN_161[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_eret = _GEN_162[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sys_pc2epc = _GEN_163[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_rocc = _GEN_164[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_mov = _GEN_165[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ftq_idx = _GEN_166[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_edge_inst = _GEN_167[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pc_lob = _GEN_168[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_taken = _GEN_169[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_rename = _GEN_170[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_sel = _GEN_171[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pimm = _GEN_172[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_packed = _GEN_173[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_op1_sel = _GEN_174[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_op2_sel = _GEN_175[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ldst = _GEN_176[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_wen = _GEN_177[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren1 = _GEN_178[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren2 = _GEN_179[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren3 = _GEN_180[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_swap12 = _GEN_181[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_swap23 = _GEN_182[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_typeTagIn = _GEN_183[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_typeTagOut = _GEN_184[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fromint = _GEN_185[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_toint = _GEN_186[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fastpipe = _GEN_187[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fma = _GEN_188[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_div = _GEN_189[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_sqrt = _GEN_190[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_wflags = _GEN_191[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_vec = _GEN_192[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_rob_idx = _GEN_193[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldq_idx = _GEN_194[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_stq_idx = _GEN_195[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_rxq_idx = _GEN_196[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pdst = _GEN_197[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs1 = _GEN_198[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs2 = _GEN_199[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs3 = _GEN_200[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ppred = _GEN_201[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs1_busy = _GEN_202[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs2_busy = _GEN_203[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs3_busy = _GEN_204[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ppred_busy = _GEN_205[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_stale_pdst = _GEN_206[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_exception = _GEN_207[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_exc_cause = _GEN_208[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_cmd = _GEN_209[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_size = _GEN_210[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_signed = _GEN_211[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_uses_ldq = _GEN_212[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_uses_stq = _GEN_213[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_unique = _GEN_214[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_flush_on_commit = _GEN_215[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_csr_cmd = _GEN_216[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldst_is_rs1 = _GEN_217[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldst = _GEN_218[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs1 = _GEN_219[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs2 = _GEN_220[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs3 = _GEN_221[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_dst_rtype = _GEN_222[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs1_rtype = _GEN_223[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs2_rtype = _GEN_224[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_frs3_en = _GEN_225[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fcn_dw = _GEN_226[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fcn_op = _GEN_227[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_val = _GEN_228[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_rm = _GEN_229[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_typ = _GEN_230[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_pf_if = _GEN_231[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_ae_if = _GEN_232[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_ma_if = _GEN_233[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_bp_debug_if = _GEN_234[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_bp_xcpt_if = _GEN_235[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_fsrc = _GEN_236[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_tsrc = _GEN_237[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_29_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_29_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_29_debug_inst; // @[lsu.scala:1729:25] wire s_uop_29_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_29_debug_pc; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_29_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_29_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_29_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_29_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_29_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_29_br_type; // @[lsu.scala:1729:25] wire s_uop_29_is_sfb; // @[lsu.scala:1729:25] wire s_uop_29_is_fence; // @[lsu.scala:1729:25] wire s_uop_29_is_fencei; // @[lsu.scala:1729:25] wire s_uop_29_is_sfence; // @[lsu.scala:1729:25] wire s_uop_29_is_amo; // @[lsu.scala:1729:25] wire s_uop_29_is_eret; // @[lsu.scala:1729:25] wire s_uop_29_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_29_is_rocc; // @[lsu.scala:1729:25] wire s_uop_29_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_29_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_pc_lob; // @[lsu.scala:1729:25] wire s_uop_29_taken; // @[lsu.scala:1729:25] wire s_uop_29_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_29_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ppred; // @[lsu.scala:1729:25] wire s_uop_29_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_29_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_29_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_29_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_29_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_29_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_mem_size; // @[lsu.scala:1729:25] wire s_uop_29_mem_signed; // @[lsu.scala:1729:25] wire s_uop_29_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_29_uses_stq; // @[lsu.scala:1729:25] wire s_uop_29_is_unique; // @[lsu.scala:1729:25] wire s_uop_29_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_29_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_29_frs3_en; // @[lsu.scala:1729:25] wire s_uop_29_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_fcn_op; // @[lsu.scala:1729:25] wire s_uop_29_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_typ; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_29_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_29_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_29_inst = _GEN_251[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_inst = _GEN_252[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_rvc = _GEN_253[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_pc = _GEN_254[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_0 = _GEN_255[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_1 = _GEN_256[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_2 = _GEN_257[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_3 = _GEN_258[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_0 = _GEN_259[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_1 = _GEN_260[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_2 = _GEN_261[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_3 = _GEN_262[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_4 = _GEN_263[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_5 = _GEN_264[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_6 = _GEN_265[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_7 = _GEN_266[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_8 = _GEN_267[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_9 = _GEN_268[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued = _GEN_269[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued_partial_agen = _GEN_270[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued_partial_dgen = _GEN_271[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p1_speculative_child = _GEN_272[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p2_speculative_child = _GEN_273[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p1_bypass_hint = _GEN_274[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p2_bypass_hint = _GEN_275[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p3_bypass_hint = _GEN_276[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_dis_col_sel = _GEN_277[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_mask = _GEN_278[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_tag = _GEN_279[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_type = _GEN_280[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sfb = _GEN_281[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_fence = _GEN_282[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_fencei = _GEN_283[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sfence = _GEN_284[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_amo = _GEN_285[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_eret = _GEN_286[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sys_pc2epc = _GEN_287[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_rocc = _GEN_288[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_mov = _GEN_289[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ftq_idx = _GEN_290[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_edge_inst = _GEN_291[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pc_lob = _GEN_292[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_taken = _GEN_293[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_rename = _GEN_294[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_sel = _GEN_295[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pimm = _GEN_296[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_packed = _GEN_297[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_op1_sel = _GEN_298[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_op2_sel = _GEN_299[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ldst = _GEN_300[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_wen = _GEN_301[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren1 = _GEN_302[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren2 = _GEN_303[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren3 = _GEN_304[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_swap12 = _GEN_305[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_swap23 = _GEN_306[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_typeTagIn = _GEN_307[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_typeTagOut = _GEN_308[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fromint = _GEN_309[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_toint = _GEN_310[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fastpipe = _GEN_311[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fma = _GEN_312[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_div = _GEN_313[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_sqrt = _GEN_314[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_wflags = _GEN_315[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_vec = _GEN_316[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_rob_idx = _GEN_317[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldq_idx = _GEN_318[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_stq_idx = _GEN_319[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_rxq_idx = _GEN_320[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pdst = _GEN_321[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs1 = _GEN_322[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs2 = _GEN_323[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs3 = _GEN_324[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ppred = _GEN_325[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs1_busy = _GEN_326[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs2_busy = _GEN_327[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs3_busy = _GEN_328[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ppred_busy = _GEN_329[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_stale_pdst = _GEN_330[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_exception = _GEN_331[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_exc_cause = _GEN_332[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_cmd = _GEN_333[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_size = _GEN_334[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_signed = _GEN_335[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_uses_ldq = _GEN_336[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_uses_stq = _GEN_337[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_unique = _GEN_338[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_flush_on_commit = _GEN_339[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_csr_cmd = _GEN_340[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldst_is_rs1 = _GEN_341[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldst = _GEN_342[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs1 = _GEN_343[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs2 = _GEN_344[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs3 = _GEN_345[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_dst_rtype = _GEN_346[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs1_rtype = _GEN_347[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs2_rtype = _GEN_348[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_frs3_en = _GEN_349[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fcn_dw = _GEN_350[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fcn_op = _GEN_351[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_val = _GEN_352[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_rm = _GEN_353[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_typ = _GEN_354[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_pf_if = _GEN_355[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_ae_if = _GEN_356[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_ma_if = _GEN_357[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_bp_debug_if = _GEN_358[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_bp_xcpt_if = _GEN_359[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_fsrc = _GEN_360[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_tsrc = _GEN_361[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire wrap_13 = _T_2095 == 5'h17; // @[util.scala:213:25] wire _GEN_849 = ~commit_store_2 & commit_load_2; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_850 = _GEN_849 & ~reset; // @[lsu.scala:1735:31, :1736:14]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_127 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_127( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_162 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_162( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_436 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_180 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_436( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_180 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_52 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_65 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_52( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_65 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAFromNoC_13 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<47>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, const connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T = shr(const, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T connect protocol.bits.user, _protocol_bits_user_WIRE node _T_1 = shr(_T, 0) wire _protocol_bits_address_WIRE : UInt<32> connect _protocol_bits_address_WIRE, _T_1 connect protocol.bits.address, _protocol_bits_address_WIRE node _T_2 = shr(_T_1, 32) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_2 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_3 = shr(_T_2, 6) wire _protocol_bits_size_WIRE : UInt<3> connect _protocol_bits_size_WIRE, _T_3 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_4 = shr(_T_3, 3) wire _protocol_bits_param_WIRE : UInt<3> connect _protocol_bits_param_WIRE, _T_4 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_5 = shr(_T_4, 3) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_5 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_6 = shr(_T_5, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_7 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_7 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_8 = shr(_T_7, 64) wire _protocol_bits_mask_WIRE : UInt<8> connect _protocol_bits_mask_WIRE, _T_8 connect protocol.bits.mask, _protocol_bits_mask_WIRE node _T_9 = shr(_T_8, 8) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol when io.flit.bits.head : node _io_protocol_bits_mask_T = not(UInt<8>(0h0)) connect io.protocol.bits.mask, _io_protocol_bits_mask_T	module TLAFromNoC_13( // @[TilelinkAdapters.scala:128:7] input clock, // @[TilelinkAdapters.scala:128:7] input reset, // @[TilelinkAdapters.scala:128:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14] output [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [72:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [46:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [46:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[46:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail \| io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:128:7] if (reset) // @[TilelinkAdapters.scala:128:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :128:7] else // @[TilelinkAdapters.scala:128:7] is_const <= _GEN & io_flit_bits_tail \| ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[46:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module BoomDuplicatedDataArray_1 : input clock : Clock input reset : Reset output io : { flip read : { valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}[1], flip write : { valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, resp : UInt<64>[4][1], nacks : UInt<1>[1]} node waddr = shr(io.write.bits.addr, 3) node raddr = shr(io.read[0].bits.addr, 3) smem array_0_0 : UInt<64>[1] [512] node _T = bits(io.write.bits.way_en, 0, 0) node _T_1 = and(_T, io.write.valid) when _T_1 : node _data_T = bits(io.write.bits.data, 63, 0) wire data : UInt<64>[1] connect data[0], _data_T node _T_2 = bits(io.write.bits.wmask, 0, 0) write mport MPORT = array_0_0[waddr], clock when _T_2 : connect MPORT[0], data[0] node _io_resp_0_0_T = bits(io.read[0].bits.way_en, 0, 0) node _io_resp_0_0_T_1 = and(_io_resp_0_0_T, io.read[0].valid) wire _io_resp_0_0_WIRE : UInt<9> invalidate _io_resp_0_0_WIRE when _io_resp_0_0_T_1 : connect _io_resp_0_0_WIRE, raddr read mport io_resp_0_0_MPORT = array_0_0[_io_resp_0_0_WIRE], clock reg io_resp_0_0_REG : UInt, clock connect io_resp_0_0_REG, io_resp_0_0_MPORT[0] connect io.resp[0][0], io_resp_0_0_REG smem array_1_0 : UInt<64>[1] [512] node _T_3 = bits(io.write.bits.way_en, 1, 1) node _T_4 = and(_T_3, io.write.valid) when _T_4 : node _data_T_1 = bits(io.write.bits.data, 63, 0) wire data_1 : UInt<64>[1] connect data_1[0], _data_T_1 node _T_5 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_1 = array_1_0[waddr], clock when _T_5 : connect MPORT_1[0], data_1[0] node _io_resp_0_1_T = bits(io.read[0].bits.way_en, 1, 1) node _io_resp_0_1_T_1 = and(_io_resp_0_1_T, io.read[0].valid) wire _io_resp_0_1_WIRE : UInt<9> invalidate _io_resp_0_1_WIRE when _io_resp_0_1_T_1 : connect _io_resp_0_1_WIRE, raddr read mport io_resp_0_1_MPORT = array_1_0[_io_resp_0_1_WIRE], clock reg io_resp_0_1_REG : UInt, clock connect io_resp_0_1_REG, io_resp_0_1_MPORT[0] connect io.resp[0][1], io_resp_0_1_REG smem array_2_0 : UInt<64>[1] [512] node _T_6 = bits(io.write.bits.way_en, 2, 2) node _T_7 = and(_T_6, io.write.valid) when _T_7 : node _data_T_2 = bits(io.write.bits.data, 63, 0) wire data_2 : UInt<64>[1] connect data_2[0], _data_T_2 node _T_8 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_2 = array_2_0[waddr], clock when _T_8 : connect MPORT_2[0], data_2[0] node _io_resp_0_2_T = bits(io.read[0].bits.way_en, 2, 2) node _io_resp_0_2_T_1 = and(_io_resp_0_2_T, io.read[0].valid) wire _io_resp_0_2_WIRE : UInt<9> invalidate _io_resp_0_2_WIRE when _io_resp_0_2_T_1 : connect _io_resp_0_2_WIRE, raddr read mport io_resp_0_2_MPORT = array_2_0[_io_resp_0_2_WIRE], clock reg io_resp_0_2_REG : UInt, clock connect io_resp_0_2_REG, io_resp_0_2_MPORT[0] connect io.resp[0][2], io_resp_0_2_REG smem array_3_0 : UInt<64>[1] [512] node _T_9 = bits(io.write.bits.way_en, 3, 3) node _T_10 = and(_T_9, io.write.valid) when _T_10 : node _data_T_3 = bits(io.write.bits.data, 63, 0) wire data_3 : UInt<64>[1] connect data_3[0], _data_T_3 node _T_11 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_3 = array_3_0[waddr], clock when _T_11 : connect MPORT_3[0], data_3[0] node _io_resp_0_3_T = bits(io.read[0].bits.way_en, 3, 3) node _io_resp_0_3_T_1 = and(_io_resp_0_3_T, io.read[0].valid) wire _io_resp_0_3_WIRE : UInt<9> invalidate _io_resp_0_3_WIRE when _io_resp_0_3_T_1 : connect _io_resp_0_3_WIRE, raddr read mport io_resp_0_3_MPORT = array_3_0[_io_resp_0_3_WIRE], clock reg io_resp_0_3_REG : UInt, clock connect io_resp_0_3_REG, io_resp_0_3_MPORT[0] connect io.resp[0][3], io_resp_0_3_REG connect io.nacks[0], UInt<1>(0h0)	module BoomDuplicatedDataArray_1( // @[dcache.scala:281:7] input clock, // @[dcache.scala:281:7] input reset, // @[dcache.scala:281:7] input io_read_0_valid, // @[dcache.scala:270:14] input [3:0] io_read_0_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_read_0_bits_addr, // @[dcache.scala:270:14] input io_write_valid, // @[dcache.scala:270:14] input [3:0] io_write_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_write_bits_addr, // @[dcache.scala:270:14] input [63:0] io_write_bits_data, // @[dcache.scala:270:14] output [63:0] io_resp_0_0, // @[dcache.scala:270:14] output [63:0] io_resp_0_1, // @[dcache.scala:270:14] output [63:0] io_resp_0_2, // @[dcache.scala:270:14] output [63:0] io_resp_0_3 // @[dcache.scala:270:14] ); wire [63:0] _array_3_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_2_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire io_read_0_valid_0 = io_read_0_valid; // @[dcache.scala:281:7] wire [3:0] io_read_0_bits_way_en_0 = io_read_0_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_read_0_bits_addr_0 = io_read_0_bits_addr; // @[dcache.scala:281:7] wire io_write_valid_0 = io_write_valid; // @[dcache.scala:281:7] wire [3:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_write_bits_addr_0 = io_write_bits_addr; // @[dcache.scala:281:7] wire [63:0] io_write_bits_data_0 = io_write_bits_data; // @[dcache.scala:281:7] wire io_nacks_0 = 1'h0; // @[dcache.scala:281:7] wire io_write_bits_wmask = 1'h1; // @[DescribedSRAM.scala:17:26] wire [63:0] _data_T = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_1 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_2 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_3 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] io_resp_0_0_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_1_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_2_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_3_0; // @[dcache.scala:281:7] wire [8:0] waddr = io_write_bits_addr_0[11:3]; // @[dcache.scala:281:7, :284:34] wire [8:0] raddr = io_read_0_bits_addr_0[11:3]; // @[dcache.scala:281:7, :287:38] wire [8:0] _io_resp_0_0_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_1_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_2_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_3_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [63:0] data_0 = _data_T; // @[dcache.scala:296:{27,75}] wire _io_resp_0_0_T = io_read_0_bits_way_en_0[0]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_0_T_1 = _io_resp_0_0_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_0_REG; // @[dcache.scala:299:31] assign io_resp_0_0_0 = io_resp_0_0_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_1_0 = _data_T_1; // @[dcache.scala:296:{27,75}] wire _io_resp_0_1_T = io_read_0_bits_way_en_0[1]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_1_T_1 = _io_resp_0_1_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_1_REG; // @[dcache.scala:299:31] assign io_resp_0_1_0 = io_resp_0_1_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_2_0 = _data_T_2; // @[dcache.scala:296:{27,75}] wire _io_resp_0_2_T = io_read_0_bits_way_en_0[2]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_2_T_1 = _io_resp_0_2_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_2_REG; // @[dcache.scala:299:31] assign io_resp_0_2_0 = io_resp_0_2_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_3_0 = _data_T_3; // @[dcache.scala:296:{27,75}] wire _io_resp_0_3_T = io_read_0_bits_way_en_0[3]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_3_T_1 = _io_resp_0_3_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_3_REG; // @[dcache.scala:299:31] assign io_resp_0_3_0 = io_resp_0_3_REG; // @[dcache.scala:281:7, :299:31] always @(posedge clock) begin // @[dcache.scala:281:7] io_resp_0_0_REG <= _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_1_REG <= _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_2_REG <= _array_2_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_3_REG <= _array_3_0_0_R0_data; // @[DescribedSRAM.scala:17:26] always @(posedge) array_0_0_0_0 array_0_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_0_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_0_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_0_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[0] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_1_0_0_0 array_1_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_1_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_1_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_1_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[1] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_1_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_2_0_0_0 array_2_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_2_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_2_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_2_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[2] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_2_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_3_0_0_0 array_3_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_3_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_3_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_3_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[3] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_3_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0_0 = io_resp_0_0_0; // @[dcache.scala:281:7] assign io_resp_0_1 = io_resp_0_1_0; // @[dcache.scala:281:7] assign io_resp_0_2 = io_resp_0_2_0; // @[dcache.scala:281:7] assign io_resp_0_3 = io_resp_0_3_0; // @[dcache.scala:281:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_6ClockSinkDomain : output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_22 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget_8 connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst egress_width_widget of EgressWidthWidget_8 connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_be_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [3:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_22 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid), .auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head), .auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail), .auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload), .auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id), .auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return), .auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid), .auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head), .auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail), .auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload), .auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return), .auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget_2 ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_tail (auto_ingress_width_widget_in_flit_bits_tail), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (1'h1), // @[LazyModuleImp.scala:107:25] .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_45 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_58 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_45( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_58 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_95 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_96 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Router_7 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_7 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_23 of InputUnit_7 connect input_unit_0_from_23.clock, clock connect input_unit_0_from_23.reset, reset inst ingress_unit_1_from_12 of IngressUnit_18 connect ingress_unit_1_from_12.clock, clock connect ingress_unit_1_from_12.reset, reset inst ingress_unit_2_from_13 of IngressUnit_19 connect ingress_unit_2_from_13.clock, clock connect ingress_unit_2_from_13.reset, reset inst ingress_unit_3_from_14 of IngressUnit_20 connect ingress_unit_3_from_14.clock, clock connect ingress_unit_3_from_14.reset, reset inst output_unit_0_to_23 of OutputUnit_7 connect output_unit_0_to_23.clock, clock connect output_unit_0_to_23.reset, reset inst egress_unit_1_to_8 of EgressUnit_17 connect egress_unit_1_to_8.clock, clock connect egress_unit_1_to_8.reset, reset inst egress_unit_2_to_9 of EgressUnit_18 connect egress_unit_2_to_9.clock, clock connect egress_unit_2_to_9.reset, reset inst switch of Switch_7 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_7 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_7 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_7 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_23.io.in, destNodesIn connect ingress_unit_1_from_12.io.in, ingressNodesIn.flit connect ingress_unit_2_from_13.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_14.io.in, ingressNodesIn_2.flit connect output_unit_0_to_23.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_23.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_23.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_8.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_8.io.out.valid connect egress_unit_1_to_8.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_9.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_9.io.out.valid connect egress_unit_2_to_9.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_23.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_12.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_13.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_14.io.router_req connect input_unit_0_from_23.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_13.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_14.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_23.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_12.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_13.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_14.io.vcalloc_req connect input_unit_0_from_23.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_13.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_14.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_23.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_8.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_9.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_23.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_23.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_23.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_23.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_23.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_23.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_23.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_23.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_23.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_23.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_23.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_23.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_23.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_23.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_23.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_23.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_23.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_23.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_23.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_23.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_23.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_23.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_23.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_23.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_23.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_23.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_23.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_23.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_23.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_23.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_23.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_23.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_23.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_23.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_23.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_23.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_23.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_23.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_23.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_23.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_8.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_8.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_8.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_9.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_9.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_9.io.channel_status[0].occupied connect input_unit_0_from_23.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect input_unit_0_from_23.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect input_unit_0_from_23.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect input_unit_0_from_23.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect input_unit_0_from_23.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect input_unit_0_from_23.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect input_unit_0_from_23.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect input_unit_0_from_23.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect input_unit_0_from_23.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect input_unit_0_from_23.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_1_from_12.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_1_from_12.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_1_from_12.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_1_from_12.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_1_from_12.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_1_from_12.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_1_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_2_from_13.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_2_from_13.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_2_from_13.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_2_from_13.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_2_from_13.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_2_from_13.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_2_from_13.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_3_from_14.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_3_from_14.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_3_from_14.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_3_from_14.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_3_from_14.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_23.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_12.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_13.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_14.io.salloc_req[0] connect output_unit_0_to_23.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_23.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_23.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_23.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_23.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_23.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_23.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_23.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_23.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_23.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_23.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_23.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_23.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_23.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_23.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_23.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_8.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_8.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_23.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_12.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_13.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_14.io.out[0] connect output_unit_0_to_23.io.in, switch.io.out.`0` connect egress_unit_1_to_8.io.in, switch.io.out.`1` connect egress_unit_2_to_9.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_23.io.block, UInt<1>(0h0) connect ingress_unit_1_from_12.io.block, UInt<1>(0h0) connect ingress_unit_2_from_13.io.block, UInt<1>(0h0) connect ingress_unit_3_from_14.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_23.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_12.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_13.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_14.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_23.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_13.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_14.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_25 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 23 7 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i12 7 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i13 7 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i14 7 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e8 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e9 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47	module Router_7( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_9_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_9_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_9_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_23_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_14_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_14_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_13_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_23_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_23_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_23_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_12_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_13_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_14_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_NoOutput_8 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset	module BundleBridgeNexus_NoOutput_8(); // @[BundleBridgeNexus.scala:20:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLUARTClockSinkDomain : output auto : { uart_0_int_xing_out : { sync : UInt<1>[1]}, flip uart_0_control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, uart_0_io_out : { txd : UInt<1>, flip rxd : UInt<1>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst uart_0 of TLUART connect uart_0.clock, childClock connect uart_0.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect uart_0.auto.io_out.rxd, auto.uart_0_io_out.rxd connect auto.uart_0_io_out.txd, uart_0.auto.io_out.txd connect uart_0.auto.control_xing_in, auto.uart_0_control_xing_in connect auto.uart_0_int_xing_out, uart_0.auto.int_xing_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLUARTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_uart_0_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_uart_0_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_uart_0_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_uart_0_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_uart_0_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_uart_0_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_uart_0_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_uart_0_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_uart_0_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_uart_0_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_uart_0_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_uart_0_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_uart_0_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_uart_0_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_uart_0_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_uart_0_io_out_rxd, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); TLUART uart_0 ( // @[UART.scala:271:51] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_xing_out_sync_0 (auto_uart_0_int_xing_out_sync_0), .auto_control_xing_in_a_ready (auto_uart_0_control_xing_in_a_ready), .auto_control_xing_in_a_valid (auto_uart_0_control_xing_in_a_valid), .auto_control_xing_in_a_bits_opcode (auto_uart_0_control_xing_in_a_bits_opcode), .auto_control_xing_in_a_bits_param (auto_uart_0_control_xing_in_a_bits_param), .auto_control_xing_in_a_bits_size (auto_uart_0_control_xing_in_a_bits_size), .auto_control_xing_in_a_bits_source (auto_uart_0_control_xing_in_a_bits_source), .auto_control_xing_in_a_bits_address (auto_uart_0_control_xing_in_a_bits_address), .auto_control_xing_in_a_bits_mask (auto_uart_0_control_xing_in_a_bits_mask), .auto_control_xing_in_a_bits_data (auto_uart_0_control_xing_in_a_bits_data), .auto_control_xing_in_a_bits_corrupt (auto_uart_0_control_xing_in_a_bits_corrupt), .auto_control_xing_in_d_ready (auto_uart_0_control_xing_in_d_ready), .auto_control_xing_in_d_valid (auto_uart_0_control_xing_in_d_valid), .auto_control_xing_in_d_bits_opcode (auto_uart_0_control_xing_in_d_bits_opcode), .auto_control_xing_in_d_bits_size (auto_uart_0_control_xing_in_d_bits_size), .auto_control_xing_in_d_bits_source (auto_uart_0_control_xing_in_d_bits_source), .auto_control_xing_in_d_bits_data (auto_uart_0_control_xing_in_d_bits_data), .auto_io_out_txd (auto_uart_0_io_out_txd), .auto_io_out_rxd (auto_uart_0_io_out_rxd) ); // @[UART.scala:271:51] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain_1 : output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_boom_l1_tracegen_status_out : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}}, element_reset_domain_boom_l1_tracegen_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_boom_l1_tracegen_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_boom_l1_tracegen_reset_vector_in : UInt<32>, flip element_reset_domain_boom_l1_tracegen_hartid_in : UInt<1>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst element_reset_domain of HierarchicalElementResetDomain_1 inst clockNode of FixedClockBroadcast_1_4 inst buffer of TLBuffer_a32d64s4k3z4c_3 connect buffer.clock, childClock connect buffer.reset, childReset inst buffer_1 of TLBuffer_6 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst intsink of IntSyncAsyncCrossingSink_n1x1_1 connect intsink.clock, childClock connect intsink.reset, childReset inst intsink_1 of IntSyncSyncCrossingSink_n1x2_1 inst intsink_2 of IntSyncSyncCrossingSink_n1x1_5 inst intsink_3 of IntSyncSyncCrossingSink_n1x1_6 inst intsink_4 of IntSyncSyncCrossingSink_n1x1_7 inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsink_5 of IntSyncSyncCrossingSink_n1x1_8 inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsink_6 of IntSyncSyncCrossingSink_n1x1_9 inst intsource_2 of IntSyncCrossingSource_n1x1_5 connect intsource_2.clock, childClock connect intsource_2.reset, childReset wire tapClockNodeOut : { clock : Clock, reset : Reset} invalidate tapClockNodeOut.reset invalidate tapClockNodeOut.clock wire tapClockNodeIn : { clock : Clock, reset : Reset} invalidate tapClockNodeIn.reset invalidate tapClockNodeIn.clock connect tapClockNodeOut, tapClockNodeIn wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlMasterClockXingOut.e.bits.sink invalidate tlMasterClockXingOut.e.valid invalidate tlMasterClockXingOut.e.ready invalidate tlMasterClockXingOut.d.bits.corrupt invalidate tlMasterClockXingOut.d.bits.data invalidate tlMasterClockXingOut.d.bits.denied invalidate tlMasterClockXingOut.d.bits.sink invalidate tlMasterClockXingOut.d.bits.source invalidate tlMasterClockXingOut.d.bits.size invalidate tlMasterClockXingOut.d.bits.param invalidate tlMasterClockXingOut.d.bits.opcode invalidate tlMasterClockXingOut.d.valid invalidate tlMasterClockXingOut.d.ready invalidate tlMasterClockXingOut.c.bits.corrupt invalidate tlMasterClockXingOut.c.bits.data invalidate tlMasterClockXingOut.c.bits.address invalidate tlMasterClockXingOut.c.bits.source invalidate tlMasterClockXingOut.c.bits.size invalidate tlMasterClockXingOut.c.bits.param invalidate tlMasterClockXingOut.c.bits.opcode invalidate tlMasterClockXingOut.c.valid invalidate tlMasterClockXingOut.c.ready invalidate tlMasterClockXingOut.b.bits.corrupt invalidate tlMasterClockXingOut.b.bits.data invalidate tlMasterClockXingOut.b.bits.mask invalidate tlMasterClockXingOut.b.bits.address invalidate tlMasterClockXingOut.b.bits.source invalidate tlMasterClockXingOut.b.bits.size invalidate tlMasterClockXingOut.b.bits.param invalidate tlMasterClockXingOut.b.bits.opcode invalidate tlMasterClockXingOut.b.valid invalidate tlMasterClockXingOut.b.ready invalidate tlMasterClockXingOut.a.bits.corrupt invalidate tlMasterClockXingOut.a.bits.data invalidate tlMasterClockXingOut.a.bits.mask invalidate tlMasterClockXingOut.a.bits.address invalidate tlMasterClockXingOut.a.bits.source invalidate tlMasterClockXingOut.a.bits.size invalidate tlMasterClockXingOut.a.bits.param invalidate tlMasterClockXingOut.a.bits.opcode invalidate tlMasterClockXingOut.a.valid invalidate tlMasterClockXingOut.a.ready wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlMasterClockXingIn.e.bits.sink invalidate tlMasterClockXingIn.e.valid invalidate tlMasterClockXingIn.e.ready invalidate tlMasterClockXingIn.d.bits.corrupt invalidate tlMasterClockXingIn.d.bits.data invalidate tlMasterClockXingIn.d.bits.denied invalidate tlMasterClockXingIn.d.bits.sink invalidate tlMasterClockXingIn.d.bits.source invalidate tlMasterClockXingIn.d.bits.size invalidate tlMasterClockXingIn.d.bits.param invalidate tlMasterClockXingIn.d.bits.opcode invalidate tlMasterClockXingIn.d.valid invalidate tlMasterClockXingIn.d.ready invalidate tlMasterClockXingIn.c.bits.corrupt invalidate tlMasterClockXingIn.c.bits.data invalidate tlMasterClockXingIn.c.bits.address invalidate tlMasterClockXingIn.c.bits.source invalidate tlMasterClockXingIn.c.bits.size invalidate tlMasterClockXingIn.c.bits.param invalidate tlMasterClockXingIn.c.bits.opcode invalidate tlMasterClockXingIn.c.valid invalidate tlMasterClockXingIn.c.ready invalidate tlMasterClockXingIn.b.bits.corrupt invalidate tlMasterClockXingIn.b.bits.data invalidate tlMasterClockXingIn.b.bits.mask invalidate tlMasterClockXingIn.b.bits.address invalidate tlMasterClockXingIn.b.bits.source invalidate tlMasterClockXingIn.b.bits.size invalidate tlMasterClockXingIn.b.bits.param invalidate tlMasterClockXingIn.b.bits.opcode invalidate tlMasterClockXingIn.b.valid invalidate tlMasterClockXingIn.b.ready invalidate tlMasterClockXingIn.a.bits.corrupt invalidate tlMasterClockXingIn.a.bits.data invalidate tlMasterClockXingIn.a.bits.mask invalidate tlMasterClockXingIn.a.bits.address invalidate tlMasterClockXingIn.a.bits.source invalidate tlMasterClockXingIn.a.bits.size invalidate tlMasterClockXingIn.a.bits.param invalidate tlMasterClockXingIn.a.bits.opcode invalidate tlMasterClockXingIn.a.valid invalidate tlMasterClockXingIn.a.ready connect tlMasterClockXingOut, tlMasterClockXingIn wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[1]} invalidate intInClockXingOut_2.sync[0] wire intInClockXingIn_2 : { sync : UInt<1>[1]} invalidate intInClockXingIn_2.sync[0] connect intInClockXingOut_2, intInClockXingIn_2 wire intOutClockXingOut : { sync : UInt<1>[1]} invalidate intOutClockXingOut.sync[0] wire intOutClockXingIn : { sync : UInt<1>[1]} invalidate intOutClockXingIn.sync[0] connect intOutClockXingOut, intOutClockXingIn wire intOutClockXingOut_1 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_1.sync[0] wire intOutClockXingIn_1 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_1.sync[0] connect intOutClockXingOut_1, intOutClockXingIn_1 wire intOutClockXingOut_2 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_2.sync[0] wire intOutClockXingIn_2 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_2.sync[0] connect intOutClockXingOut_2, intOutClockXingIn_2 wire intOutClockXingOut_3 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_3.sync[0] wire intOutClockXingIn_3 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_3.sync[0] connect intOutClockXingOut_3, intOutClockXingIn_3 wire intOutClockXingOut_4 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_4.sync[0] wire intOutClockXingIn_4 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_4.sync[0] connect intOutClockXingOut_4, intOutClockXingIn_4 wire intOutClockXingOut_5 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_5.sync[0] wire intOutClockXingIn_5 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_5.sync[0] connect intOutClockXingOut_5, intOutClockXingIn_5 connect clockNode.auto.anon_in, tapClockNodeOut connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out connect intsource.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_halt_out[0] connect intsource_2.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_cease_out[0] connect intsource_1.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_wfi_out[0] connect buffer.auto.in, element_reset_domain.auto.boom_l1_tracegen_buffer_out connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready connect buffer.auto.out.d, tlMasterClockXingIn.d connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready connect buffer.auto.out.b, tlMasterClockXingIn.b connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_0[0], intsink.auto.out[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_1[0], intsink_1.auto.out[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_1[1], intsink_1.auto.out[1] connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0] connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_2[0], intsink_2.auto.out[0] connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_3[0], intsink_3.auto.out[0] connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0] connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0] connect intOutClockXingIn, intOutClockXingOut_1 connect intOutClockXingIn_1, intsource.auto.out connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0] connect intOutClockXingIn_2, intOutClockXingOut_3 connect intOutClockXingIn_3, intsource_1.auto.out connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0] connect intOutClockXingIn_4, intOutClockXingOut_5 connect intOutClockXingIn_5, intsource_2.auto.out connect tapClockNodeIn, auto.tap_clock_in connect auto.tl_master_clock_xing_out, tlMasterClockXingOut connect intInClockXingIn, auto.int_in_clock_xing_in_0 connect intInClockXingIn_1, auto.int_in_clock_xing_in_1 connect intInClockXingIn_2, auto.int_in_clock_xing_in_2 connect element_reset_domain.auto.boom_l1_tracegen_hartid_in, auto.element_reset_domain_boom_l1_tracegen_hartid_in connect element_reset_domain.auto.boom_l1_tracegen_reset_vector_in, auto.element_reset_domain_boom_l1_tracegen_reset_vector_in connect auto.element_reset_domain_boom_l1_tracegen_trace_source_out.time, element_reset_domain.auto.boom_l1_tracegen_trace_source_out.time connect auto.element_reset_domain_boom_l1_tracegen_trace_source_out.insns, element_reset_domain.auto.boom_l1_tracegen_trace_source_out.insns connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.cause, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.cause connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.tval, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.tval connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.priv, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.priv connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.group, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.group connect auto.element_reset_domain_boom_l1_tracegen_status_out, element_reset_domain.auto.boom_l1_tracegen_status_out connect intsink.auto.in.sync[0], auto.intsink_in.sync[0] connect auto.intsink_out_0, intsink_4.auto.out connect auto.intsink_out_1, intsink_5.auto.out connect auto.intsink_out_2, intsink_6.auto.out connect childClock, tapClockNodeIn.clock connect childReset, tapClockNodeIn.reset connect clock, tapClockNodeIn.clock connect reset, tapClockNodeIn.reset	module TilePRCIDomain_1( // @[ClockDomain.scala:14:9] output auto_intsink_out_2_0, // @[LazyModuleImp.scala:107:25] output auto_intsink_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid, // @[LazyModuleImp.scala:107:25] input auto_element_reset_domain_boom_l1_tracegen_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_hartid_in_0 = auto_element_reset_domain_boom_l1_tracegen_hartid_in; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_status_out_error_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_status_out_error_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_reset_vector_in = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_reset_vector_in = 32'h0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_iaddr = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_tval = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_iaddr = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_tval = 40'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [3:0] auto_tl_master_clock_xing_out_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire auto_intsink_out_1_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_intsink_in_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_status_out_error_valid = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_2_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_1_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_1 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_status_out_error_valid = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_wfi_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_3_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_2_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_1_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_1_1 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_1 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_2_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_2_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_2_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_2_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_3_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_3_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_hartid_in = auto_element_reset_domain_boom_l1_tracegen_hartid_in_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_2_0_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_0_0_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0 = element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_cease_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_halt_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31] wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31] assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17] wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9] assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17] assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17] assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17] assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9] assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_sync_0 = intOutClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_sync_0 = intOutClockXingOut_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_1_sync_0 = intOutClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_4_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_4_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_5_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_4_sync_0 = intOutClockXingIn_4_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_5_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_4_sync_0 = intOutClockXingOut_5_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_5_sync_0 = intOutClockXingIn_5_sync_0; // @[MixedNode.scala:542:17, :551:17] BoomTraceGenTile_1 element_reset_domain_boom_l1_tracegen ( // @[HasTiles.scala:164:59] .clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31] .reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data), .auto_buffer_out_b_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready), .auto_buffer_out_b_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data), .auto_buffer_out_d_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready), .auto_buffer_out_d_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink), .auto_status_out_timeout_valid (element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid), .auto_cease_out_0 (element_reset_domain_auto_boom_l1_tracegen_cease_out_0), .auto_halt_out_0 (element_reset_domain_auto_boom_l1_tracegen_halt_out_0), .auto_int_local_in_0_0 (element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0), // @[ClockDomain.scala:14:9] .auto_hartid_in (element_reset_domain_auto_boom_l1_tracegen_hartid_in) // @[ClockDomain.scala:14:9] ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s4k3z4c_3 buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready), .auto_in_a_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_b_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready), // @[ClockDomain.scala:14:9] .auto_in_b_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid), .auto_in_b_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode), .auto_in_b_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param), .auto_in_b_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size), .auto_in_b_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source), .auto_in_b_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address), .auto_in_b_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask), .auto_in_b_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data), .auto_in_b_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt), .auto_in_c_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready), .auto_in_c_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid), // @[ClockDomain.scala:14:9] .auto_in_c_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_c_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9] .auto_in_c_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9] .auto_in_c_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9] .auto_in_c_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9] .auto_in_c_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9] .auto_in_d_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready), // @[ClockDomain.scala:14:9] .auto_in_d_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid), .auto_in_d_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode), .auto_in_d_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param), .auto_in_d_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size), .auto_in_d_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source), .auto_in_d_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink), .auto_in_d_bits_denied (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied), .auto_in_d_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data), .auto_in_d_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt), .auto_in_e_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready), .auto_in_e_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid), // @[ClockDomain.scala:14:9] .auto_in_e_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9] .auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlMasterClockXingIn_a_valid), .auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode), .auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param), .auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size), .auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source), .auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address), .auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask), .auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data), .auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt), .auto_out_b_ready (tlMasterClockXingIn_b_ready), .auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlMasterClockXingIn_c_valid), .auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode), .auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param), .auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size), .auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source), .auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address), .auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data), .auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt), .auto_out_d_ready (tlMasterClockXingIn_d_ready), .auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlMasterClockXingIn_e_valid), .auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_6 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1_1 intsink ( // @[Crossing.scala:86:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_out_0 (element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2_1 intsink_1 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_5 intsink_2 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_6 intsink_3 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_7 intsink_4 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_0_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_boom_l1_tracegen_halt_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_8 intsink_5 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_9 intsink_6 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_4_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_2_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_5 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_boom_l1_tracegen_cease_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_5_sync_0) ); // @[Crossing.scala:29:31] assign auto_intsink_out_2_0 = auto_intsink_out_2_0_0; // @[ClockDomain.scala:14:9] assign auto_intsink_out_0_0 = auto_intsink_out_0_0_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid = auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_211 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_211( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_167 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_181 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_167( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_181 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_3 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<25> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_65) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_10_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_42_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_2_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_14_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_0_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_1_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_16_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_48_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_12) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_39_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_53_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_14) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_17_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_62_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_18) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_59_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_24) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_51_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_28) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19, _rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_29) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 24, 24) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 24, 21) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 20, 20) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 17, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid	module RegisterReadDecode_3( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [7:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [7:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [7:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [7:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [4:0] rrd_cs_decoder_4; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [24:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [24:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = rrd_cs_decoder_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = rrd_cs_decoder_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:90:45, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] _GEN = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = _GEN; // @[pla.scala:114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_14_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_5; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = _GEN_0; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN_0; // @[pla.scala:114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [12:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_1_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_16_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_48_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [14:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [10:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_62_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = _GEN_1; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_59_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = \|_rrd_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, 3'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, 1'h0}; // @[pla.scala:102:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_19, _rrd_cs_decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_27, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:102:36] wire [12:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:102:36] wire [24:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_21; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = rrd_cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [3:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[24:21]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[20]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] assign rrd_cs_decoder_4 = rrd_cs_decoder_decoded[17:13]; // @[pla.scala:81:23] assign rrd_cs_op_fcn = rrd_cs_decoder_4; // @[Decode.scala:50:77] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T \| _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T \| _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 \| _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T \| _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 6'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_32 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_32( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_37 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} inst mulFullRaw of MulFullRawFN_37 connect mulFullRaw.io.a.sig, io.a.sig connect mulFullRaw.io.a.sExp, io.a.sExp connect mulFullRaw.io.a.sign, io.a.sign connect mulFullRaw.io.a.isZero, io.a.isZero connect mulFullRaw.io.a.isInf, io.a.isInf connect mulFullRaw.io.a.isNaN, io.a.isNaN connect mulFullRaw.io.b.sig, io.b.sig connect mulFullRaw.io.b.sExp, io.b.sExp connect mulFullRaw.io.b.sign, io.b.sign connect mulFullRaw.io.b.isZero, io.b.isZero connect mulFullRaw.io.b.isInf, io.b.isInf connect mulFullRaw.io.b.isNaN, io.b.isNaN connect io.invalidExc, mulFullRaw.io.invalidExc connect io.rawOut, mulFullRaw.io.rawOut node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) connect io.rawOut.sig, _io_rawOut_sig_T_3	module MulRawFN_37( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = \|_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_37 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x2_11 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[2], out : { sync : UInt<1>[2]}} wire nodeIn : UInt<1>[2] invalidate nodeIn[0] invalidate nodeIn[1] wire nodeOut : { sync : UInt<1>[2]} invalidate nodeOut.sync[0] invalidate nodeOut.sync[1] connect auto.out, nodeOut connect nodeIn, auto.in node _T = cat(nodeIn[1], nodeIn[0]) inst reg of AsyncResetRegVec_w2_i0_11 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, _T connect reg.io.en, UInt<1>(0h1) node _T_1 = bits(reg.io.q, 0, 0) node _T_2 = bits(reg.io.q, 1, 1) connect nodeOut.sync[0], _T_1 connect nodeOut.sync[1], _T_2	module IntSyncCrossingSource_n1x2_11( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] input auto_in_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1 // @[LazyModuleImp.scala:107:25] ); wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w2_i0_11 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36] .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CSRFile_7 : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<3>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2)) node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv) connect reg_mstatus.prv, _reg_mstatus_prv_T_1 wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h1) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h1) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h1) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<40>, clock reg reg_dscratch0 : UInt<64>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<64>, clock reg reg_mideleg : UInt<64>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<64>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<40>, clock regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) reg reg_mtval : UInt<40>, clock reg reg_mtval2 : UInt<40>, clock reg reg_mscratch : UInt<64>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<64>, clock reg reg_mnepc : UInt<40>, clock regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<64>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<64>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_htval : UInt<40>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<40>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node _T_14 = and(reg_vstvec, _T_13) node _T_15 = bits(_T_14, 39, 39) node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0)) node read_vstvec = cat(_T_16, _T_14) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<64>, clock reg reg_vsepc : UInt<40>, clock reg reg_vscause : UInt<64>, clock reg reg_vstval : UInt<40>, clock reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_sepc : UInt<40>, clock reg reg_scause : UInt<64>, clock reg reg_stval : UInt<40>, clock reg reg_sscratch : UInt<64>, clock reg reg_stvec : UInt<39>, clock reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_17 = eq(x3, UInt<1>(0h0)) when _T_17 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_18 = eq(x11, UInt<1>(0h0)) when _T_18 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip) connect mip.seip, _mip_seip_T connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 62) node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 63, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38) node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38) node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T_2 = not(reg_mepc) node _read_mapping_T_3 = bits(reg_misa, 2, 2) node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) node _read_mapping_T_6 = not(_read_mapping_T_5) node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39) node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) node _read_mapping_T_9 = bits(reg_mtval, 39, 39) node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node _debug_csrs_T_4 = not(_debug_csrs_T_3) node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39) node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0)) node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom) node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie) node lo_4 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze) node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_19 = cat(hi_6, lo_4) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) node read_sie = and(reg_mie, sie_mask) node read_sip = and(read_mip, sie_mask) wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _read_sstatus_WIRE.uie, UInt<1>(0h0) connect _read_sstatus_WIRE.sie, UInt<1>(0h0) connect _read_sstatus_WIRE.hie, UInt<1>(0h0) connect _read_sstatus_WIRE.mie, UInt<1>(0h0) connect _read_sstatus_WIRE.upie, UInt<1>(0h0) connect _read_sstatus_WIRE.spie, UInt<1>(0h0) connect _read_sstatus_WIRE.ube, UInt<1>(0h0) connect _read_sstatus_WIRE.mpie, UInt<1>(0h0) connect _read_sstatus_WIRE.spp, UInt<1>(0h0) connect _read_sstatus_WIRE.vs, UInt<2>(0h0) connect _read_sstatus_WIRE.mpp, UInt<2>(0h0) connect _read_sstatus_WIRE.fs, UInt<2>(0h0) connect _read_sstatus_WIRE.xs, UInt<2>(0h0) connect _read_sstatus_WIRE.mprv, UInt<1>(0h0) connect _read_sstatus_WIRE.sum, UInt<1>(0h0) connect _read_sstatus_WIRE.mxr, UInt<1>(0h0) connect _read_sstatus_WIRE.tvm, UInt<1>(0h0) connect _read_sstatus_WIRE.tw, UInt<1>(0h0) connect _read_sstatus_WIRE.tsr, UInt<1>(0h0) connect _read_sstatus_WIRE.zero1, UInt<8>(0h0) connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _read_sstatus_WIRE.uxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sbe, UInt<1>(0h0) connect _read_sstatus_WIRE.mbe, UInt<1>(0h0) connect _read_sstatus_WIRE.gva, UInt<1>(0h0) connect _read_sstatus_WIRE.mpv, UInt<1>(0h0) connect _read_sstatus_WIRE.zero2, UInt<23>(0h0) connect _read_sstatus_WIRE.sd, UInt<1>(0h0) connect _read_sstatus_WIRE.v, UInt<1>(0h0) connect _read_sstatus_WIRE.prv, UInt<2>(0h0) connect _read_sstatus_WIRE.dv, UInt<1>(0h0) connect _read_sstatus_WIRE.dprv, UInt<2>(0h0) connect _read_sstatus_WIRE.isa, UInt<32>(0h0) connect _read_sstatus_WIRE.wfi, UInt<1>(0h0) connect _read_sstatus_WIRE.cease, UInt<1>(0h0) connect _read_sstatus_WIRE.debug, UInt<1>(0h0) wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect read_sstatus, _read_sstatus_WIRE connect read_sstatus.sd, io.status.sd connect read_sstatus.uxl, io.status.uxl connect read_sstatus.sd_rv32, io.status.sd_rv32 connect read_sstatus.mxr, io.status.mxr connect read_sstatus.sum, io.status.sum connect read_sstatus.xs, io.status.xs connect read_sstatus.fs, io.status.fs connect read_sstatus.vs, io.status.vs connect read_sstatus.spp, io.status.spp connect read_sstatus.spie, io.status.spie connect read_sstatus.sie, io.status.sie node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie) node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie) node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo) node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie) node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie) node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube) node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo) node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4) node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs) node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs) node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo) node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv) node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm) node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr) node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo) node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4) node lo_5 = cat(lo_hi_5, lo_lo_5) node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr) node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32) node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo) node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl) node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva) node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe) node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo) node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4) node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2) node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv) node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v) node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo) node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv) node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease) node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi) node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo) node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_20 = cat(hi_7, lo_5) node _T_21 = bits(_T_20, 63, 0) node _T_22 = bits(reg_stval, 39, 39) node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_24 = cat(_T_23, reg_stval) node hi_8 = cat(reg_satp.mode, reg_satp.asid) node _T_25 = cat(hi_8, reg_satp.ppn) node _T_26 = not(reg_sepc) node _T_27 = bits(reg_misa, 2, 2) node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3)) node _T_29 = or(_T_26, _T_28) node _T_30 = not(_T_29) node _T_31 = bits(_T_30, 39, 39) node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_33 = cat(_T_32, _T_30) node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom) node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie) node lo_6 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze) node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_34 = cat(hi_9, lo_6) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r) node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a) node _T_35 = cat(hi_10, lo_7) node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r) node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a) node _T_36 = cat(hi_11, lo_8) node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r) node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a) node _T_37 = cat(hi_12, lo_9) node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r) node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a) node _T_38 = cat(hi_13, lo_10) node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r) node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a) node _T_39 = cat(hi_14, lo_11) node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r) node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a) node _T_40 = cat(hi_15, lo_12) node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r) node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a) node _T_41 = cat(hi_16, lo_13) node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r) node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a) node _T_42 = cat(hi_17, lo_14) node lo_lo_7 = cat(_T_36, _T_35) node lo_hi_15 = cat(_T_38, _T_37) node lo_15 = cat(lo_hi_15, lo_lo_7) node hi_lo_7 = cat(_T_40, _T_39) node hi_hi_15 = cat(_T_42, _T_41) node hi_18 = cat(hi_hi_15, hi_lo_7) node _T_43 = cat(hi_18, lo_15) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_44 = cat(hi_19, lo_16) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_45 = cat(hi_20, lo_17) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_46 = cat(hi_21, lo_18) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_47 = cat(hi_22, lo_19) node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a) node _T_48 = cat(hi_23, lo_20) node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r) node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a) node _T_49 = cat(hi_24, lo_21) node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r) node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a) node _T_50 = cat(hi_25, lo_22) node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r) node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a) node _T_51 = cat(hi_26, lo_23) node lo_lo_8 = cat(_T_45, _T_44) node lo_hi_24 = cat(_T_47, _T_46) node lo_24 = cat(lo_hi_24, lo_lo_8) node hi_lo_8 = cat(_T_49, _T_48) node hi_hi_24 = cat(_T_51, _T_50) node hi_27 = cat(hi_hi_24, hi_lo_8) node _T_52 = cat(hi_27, lo_24) regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<150> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_53 = bits(decoded, 8, 8) node _T_54 = bits(decoded, 7, 7) node _T_55 = bits(decoded, 6, 6) node _T_56 = bits(decoded, 5, 5) node _T_57 = bits(decoded, 4, 4) node _T_58 = bits(decoded, 3, 3) node _T_59 = bits(decoded, 2, 2) node _T_60 = bits(decoded, 1, 1) node _T_61 = bits(decoded, 0, 0) node _T_62 = bits(_T_53, 0, 0) node insn_call = and(system_insn, _T_62) node _T_63 = bits(_T_54, 0, 0) node insn_break = and(system_insn, _T_63) node _T_64 = bits(_T_55, 0, 0) node insn_ret = and(system_insn, _T_64) node _T_65 = bits(_T_56, 0, 0) node insn_cease = and(system_insn, _T_65) node _T_66 = bits(_T_57, 0, 0) node insn_wfi = and(system_insn, _T_66) node _T_67 = bits(_T_58, 0, 0) node _T_68 = and(system_insn, _T_67) node _T_69 = bits(_T_59, 0, 0) node _T_70 = and(system_insn, _T_69) node _T_71 = bits(_T_60, 0, 0) node _T_72 = and(system_insn, _T_71) node _T_73 = bits(_T_61, 0, 0) node _T_74 = and(system_insn, _T_73) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_75 = bits(decoded_1, 8, 8) node _T_76 = bits(decoded_1, 7, 7) node _T_77 = bits(decoded_1, 6, 6) node _T_78 = bits(decoded_1, 5, 5) node _T_79 = bits(decoded_1, 4, 4) node _T_80 = bits(decoded_1, 3, 3) node _T_81 = bits(decoded_1, 2, 2) node _T_82 = bits(decoded_1, 1, 1) node _T_83 = bits(decoded_1, 0, 0) node _T_84 = bits(_T_75, 0, 0) node is_break = bits(_T_76, 0, 0) node is_ret = bits(_T_77, 0, 0) node _T_85 = bits(_T_78, 0, 0) node is_wfi = bits(_T_79, 0, 0) node is_sfence = bits(_T_80, 0, 0) node is_hfence_vvma = bits(_T_81, 0, 0) node is_hfence_gvma = bits(_T_82, 0, 0) node is_hlsv = bits(_T_83, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11) node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3) node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo) node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h306)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a)) node _csr_exists_T_114 = eq(addr, UInt<9>(0h100)) node _csr_exists_T_115 = eq(addr, UInt<9>(0h144)) node _csr_exists_T_116 = eq(addr, UInt<9>(0h104)) node _csr_exists_T_117 = eq(addr, UInt<9>(0h140)) node _csr_exists_T_118 = eq(addr, UInt<9>(0h142)) node _csr_exists_T_119 = eq(addr, UInt<9>(0h143)) node _csr_exists_T_120 = eq(addr, UInt<9>(0h180)) node _csr_exists_T_121 = eq(addr, UInt<9>(0h141)) node _csr_exists_T_122 = eq(addr, UInt<9>(0h105)) node _csr_exists_T_123 = eq(addr, UInt<9>(0h106)) node _csr_exists_T_124 = eq(addr, UInt<10>(0h303)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h302)) node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a)) node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2) node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3) node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4) node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5) node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6) node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7) node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8) node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9) node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10) node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11) node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12) node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13) node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14) node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15) node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16) node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17) node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18) node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19) node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20) node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21) node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22) node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23) node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24) node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25) node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26) node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27) node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28) node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29) node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30) node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31) node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32) node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33) node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34) node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35) node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36) node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37) node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38) node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39) node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40) node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41) node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42) node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43) node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44) node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45) node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46) node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148) node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 5, 0) node _causeIsDebugInt_T = bits(cause, 63, 63) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 63, 63) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 63, 63) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T) node _delegate_T_2 = bits(cause, 63, 63) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 63, 63) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 63, 63) node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 63, 63) node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<2>(0h2) connect io.status.sxl, UInt<2>(0h2) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<2>(0h2) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<2>(0h2) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_86 = add(insn_ret, insn_call) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(insn_break, io.exception) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_87, _T_89) node _T_91 = bits(_T_90, 2, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_92, UInt<1>(0h1), "") : assert node _T_96 = eq(io.singleStep, UInt<1>(0h0)) node _T_97 = and(insn_wfi, _T_96) node _T_98 = eq(reg_debug, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) when _T_99 : connect reg_wfi, UInt<1>(0h1) node _T_100 = orr(pending_interrupts) node _T_101 = or(_T_100, io.interrupts.debug) node _T_102 = or(_T_101, exception) when _T_102 : connect reg_wfi, UInt<1>(0h0) node _T_103 = bits(io.retire, 0, 0) node _T_104 = or(_T_103, exception) when _T_104 : connect reg_singleStepped, UInt<1>(0h1) node _T_105 = eq(io.singleStep, UInt<1>(0h0)) when _T_105 : connect reg_singleStepped, UInt<1>(0h0) node _T_106 = eq(io.singleStep, UInt<1>(0h0)) node _T_107 = leq(io.retire, UInt<1>(0h1)) node _T_108 = or(_T_106, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep \|\| io.retire <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_113 = eq(io.retire, UInt<1>(0h0)) node _T_114 = or(_T_112, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped \|\| io.retire === 0.U)\n") : printf_2 assert(clock, _T_114, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_118 = eq(reg_debug, UInt<1>(0h0)) when _T_118 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, reg_mstatus.prv connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, reg_mstatus.prv connect new_prv, UInt<2>(0h3) else : node _T_119 = and(delegateVS, reg_rnmie) when _T_119 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 63, 63) node _reg_vscause_T_1 = bits(cause, 63, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_120 = and(delegate, reg_rnmie) when _T_120 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, reg_mstatus.prv connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_121 = eq(delegate, UInt<1>(0h0)) node _T_122 = and(en, _T_121) node _T_123 = and(en, delegable) node _T_124 = and(_T_123, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_125 = eq(delegate, UInt<1>(0h0)) node _T_126 = and(en_1, _T_125) node _T_127 = and(en_1, delegable_1) node _T_128 = and(_T_127, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_129 = eq(delegate, UInt<1>(0h0)) node _T_130 = and(en_2, _T_129) node _T_131 = and(en_2, delegable_2) node _T_132 = and(_T_131, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_133 = eq(delegate, UInt<1>(0h0)) node _T_134 = and(en_3, _T_133) node _T_135 = and(en_3, delegable_3) node _T_136 = and(_T_135, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_137 = eq(delegate, UInt<1>(0h0)) node _T_138 = and(en_4, _T_137) node _T_139 = and(en_4, delegable_4) node _T_140 = and(_T_139, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_141 = eq(delegate, UInt<1>(0h0)) node _T_142 = and(en_5, _T_141) node _T_143 = and(en_5, delegable_5) node _T_144 = and(_T_143, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_145 = eq(delegate, UInt<1>(0h0)) node _T_146 = and(en_6, _T_145) node _T_147 = and(en_6, delegable_6) node _T_148 = and(_T_147, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_149 = eq(delegate, UInt<1>(0h0)) node _T_150 = and(en_7, _T_149) node _T_151 = and(en_7, delegable_7) node _T_152 = and(_T_151, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_153 = eq(delegate, UInt<1>(0h0)) node _T_154 = and(en_8, _T_153) node _T_155 = and(en_8, delegable_8) node _T_156 = and(_T_155, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_157 = eq(delegate, UInt<1>(0h0)) node _T_158 = and(en_9, _T_157) node _T_159 = and(en_9, delegable_9) node _T_160 = and(_T_159, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_161 = eq(delegate, UInt<1>(0h0)) node _T_162 = and(en_10, _T_161) node _T_163 = and(en_10, delegable_10) node _T_164 = and(_T_163, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_165 = eq(delegate, UInt<1>(0h0)) node _T_166 = and(en_11, _T_165) node _T_167 = and(en_11, delegable_11) node _T_168 = and(_T_167, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_169 = eq(delegate, UInt<1>(0h0)) node _T_170 = and(en_12, _T_169) node _T_171 = and(en_12, delegable_12) node _T_172 = and(_T_171, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_173 = eq(delegate, UInt<1>(0h0)) node _T_174 = and(en_13, _T_173) node _T_175 = and(en_13, delegable_13) node _T_176 = and(_T_175, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_177 = eq(delegate, UInt<1>(0h0)) node _T_178 = and(en_14, _T_177) node _T_179 = and(en_14, delegable_14) node _T_180 = and(_T_179, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_181 = eq(delegate, UInt<1>(0h0)) node _T_182 = and(en_15, _T_181) node _T_183 = and(en_15, delegable_15) node _T_184 = and(_T_183, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_185 = eq(delegate, UInt<1>(0h0)) node _T_186 = and(en_16, _T_185) node _T_187 = and(en_16, delegable_16) node _T_188 = and(_T_187, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_189 = eq(delegate, UInt<1>(0h0)) node _T_190 = and(en_17, _T_189) node _T_191 = and(en_17, delegable_17) node _T_192 = and(_T_191, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_193 = eq(delegate, UInt<1>(0h0)) node _T_194 = and(en_18, _T_193) node _T_195 = and(en_18, delegable_18) node _T_196 = and(_T_195, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_197 = eq(delegate, UInt<1>(0h0)) node _T_198 = and(en_19, _T_197) node _T_199 = and(en_19, delegable_19) node _T_200 = and(_T_199, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_201 = eq(delegate, UInt<1>(0h0)) node _T_202 = and(en_20, _T_201) node _T_203 = and(en_20, delegable_20) node _T_204 = and(_T_203, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_205 = eq(delegate, UInt<1>(0h0)) node _T_206 = and(en_21, _T_205) node _T_207 = and(en_21, delegable_21) node _T_208 = and(_T_207, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_209 = eq(delegate, UInt<1>(0h0)) node _T_210 = and(en_22, _T_209) node _T_211 = and(en_22, delegable_22) node _T_212 = and(_T_211, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_213 = eq(delegate, UInt<1>(0h0)) node _T_214 = and(en_23, _T_213) node _T_215 = and(en_23, delegable_23) node _T_216 = and(_T_215, delegate) node _en_T_104 = eq(cause, UInt<4>(0h8)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_217 = eq(delegate, UInt<1>(0h0)) node _T_218 = and(en_24, _T_217) node _T_219 = and(en_24, delegable_24) node _T_220 = and(_T_219, delegate) node _en_T_105 = eq(cause, UInt<4>(0h9)) node en_25 = and(exception, _en_T_105) node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200)) node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0)) node _T_221 = eq(delegate, UInt<1>(0h0)) node _T_222 = and(en_25, _T_221) node _T_223 = and(en_25, delegable_25) node _T_224 = and(_T_223, delegate) node _en_T_106 = eq(cause, UInt<4>(0hb)) node en_26 = and(exception, _en_T_106) node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0)) node _T_225 = eq(delegate, UInt<1>(0h0)) node _T_226 = and(en_26, _T_225) node _T_227 = and(en_26, delegable_26) node _T_228 = and(_T_227, delegate) node _en_T_107 = eq(cause, UInt<4>(0hc)) node en_27 = and(exception, _en_T_107) node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000)) node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0)) node _T_229 = eq(delegate, UInt<1>(0h0)) node _T_230 = and(en_27, _T_229) node _T_231 = and(en_27, delegable_27) node _T_232 = and(_T_231, delegate) node _en_T_108 = eq(cause, UInt<4>(0hd)) node en_28 = and(exception, _en_T_108) node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000)) node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0)) node _T_233 = eq(delegate, UInt<1>(0h0)) node _T_234 = and(en_28, _T_233) node _T_235 = and(en_28, delegable_28) node _T_236 = and(_T_235, delegate) node _en_T_109 = eq(cause, UInt<4>(0hf)) node en_29 = and(exception, _en_T_109) node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000)) node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0)) node _T_237 = eq(delegate, UInt<1>(0h0)) node _T_238 = and(en_29, _T_237) node _T_239 = and(en_29, delegable_29) node _T_240 = and(_T_239, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_241 = bits(io.rw.addr, 9, 9) node _T_242 = eq(_T_241, UInt<1>(0h0)) node _T_243 = and(UInt<1>(0h1), _T_242) when _T_243 : node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_244 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_245 = bits(io.rw.addr, 10, 10) node _T_246 = and(UInt<1>(0h1), _T_245) node _T_247 = bits(io.rw.addr, 7, 7) node _T_248 = and(_T_246, _T_247) when _T_248 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_249 = bits(io.rw.addr, 10, 10) node _T_250 = and(UInt<1>(0h0), _T_249) node _T_251 = bits(io.rw.addr, 7, 7) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(_T_250, _T_252) when _T_253 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2)) node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0)) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1 connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_254 = leq(ret_prv, UInt<1>(0h1)) node _T_255 = and(UInt<1>(0h1), _T_254) when _T_255 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2) node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3) node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4) node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5) node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6) node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7) node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8) node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9) node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10) node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11) node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12) node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13) node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14) node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15) node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16) node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17) node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18) node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19) node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20) node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21) node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22) node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23) node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24) node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25) node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26) node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27) node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28) node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29) node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30) node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31) node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32) node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33) node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34) node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35) node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36) node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37) node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38) node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39) node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40) node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41) node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42) node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43) node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44) node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45) node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_256 = andr(UInt<2>(0h1)) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_261 = or(_T_258, _T_259) node _T_262 = or(_T_261, _T_260) node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_264 = and(_T_262, _T_263) else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_267 = and(_T_265, _T_266) node _T_268 = andr(UInt<2>(0h1)) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_273 = or(_T_270, _T_271) node _T_274 = or(_T_273, _T_272) node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_276 = and(_T_274, _T_275) else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_279 = and(_T_277, _T_278) node _T_280 = andr(UInt<2>(0h1)) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_285 = or(_T_282, _T_283) node _T_286 = or(_T_285, _T_284) node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_288 = and(_T_286, _T_287) else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_291 = and(_T_289, _T_290) node _T_292 = andr(UInt<2>(0h1)) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_297 = or(_T_294, _T_295) node _T_298 = or(_T_297, _T_296) node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_300 = and(_T_298, _T_299) else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_303 = and(_T_301, _T_302) node _T_304 = andr(UInt<2>(0h0)) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_309 = or(_T_306, _T_307) node _T_310 = or(_T_309, _T_308) node _T_311 = eq(io.rw.addr, UInt<10>(0h301)) node _T_312 = and(_T_310, _T_311) else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_314 = eq(io.rw.addr, UInt<10>(0h301)) node _T_315 = and(_T_313, _T_314) node _T_316 = andr(UInt<2>(0h0)) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_321 = or(_T_318, _T_319) node _T_322 = or(_T_321, _T_320) node _T_323 = eq(io.rw.addr, UInt<10>(0h300)) node _T_324 = and(_T_322, _T_323) else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_326 = eq(io.rw.addr, UInt<10>(0h300)) node _T_327 = and(_T_325, _T_326) node _T_328 = andr(UInt<2>(0h0)) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_333 = or(_T_330, _T_331) node _T_334 = or(_T_333, _T_332) node _T_335 = eq(io.rw.addr, UInt<10>(0h305)) node _T_336 = and(_T_334, _T_335) else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_338 = eq(io.rw.addr, UInt<10>(0h305)) node _T_339 = and(_T_337, _T_338) node _T_340 = andr(UInt<2>(0h0)) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_345 = or(_T_342, _T_343) node _T_346 = or(_T_345, _T_344) node _T_347 = eq(io.rw.addr, UInt<10>(0h344)) node _T_348 = and(_T_346, _T_347) else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_350 = eq(io.rw.addr, UInt<10>(0h344)) node _T_351 = and(_T_349, _T_350) node _T_352 = andr(UInt<2>(0h0)) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_357 = or(_T_354, _T_355) node _T_358 = or(_T_357, _T_356) node _T_359 = eq(io.rw.addr, UInt<10>(0h304)) node _T_360 = and(_T_358, _T_359) else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_362 = eq(io.rw.addr, UInt<10>(0h304)) node _T_363 = and(_T_361, _T_362) node _T_364 = andr(UInt<2>(0h0)) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_369 = or(_T_366, _T_367) node _T_370 = or(_T_369, _T_368) node _T_371 = eq(io.rw.addr, UInt<10>(0h340)) node _T_372 = and(_T_370, _T_371) else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_374 = eq(io.rw.addr, UInt<10>(0h340)) node _T_375 = and(_T_373, _T_374) node _T_376 = andr(UInt<2>(0h0)) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_381 = or(_T_378, _T_379) node _T_382 = or(_T_381, _T_380) node _T_383 = eq(io.rw.addr, UInt<10>(0h341)) node _T_384 = and(_T_382, _T_383) else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_386 = eq(io.rw.addr, UInt<10>(0h341)) node _T_387 = and(_T_385, _T_386) node _T_388 = andr(UInt<2>(0h0)) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_393 = or(_T_390, _T_391) node _T_394 = or(_T_393, _T_392) node _T_395 = eq(io.rw.addr, UInt<10>(0h343)) node _T_396 = and(_T_394, _T_395) else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_398 = eq(io.rw.addr, UInt<10>(0h343)) node _T_399 = and(_T_397, _T_398) node _T_400 = andr(UInt<2>(0h0)) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_405 = or(_T_402, _T_403) node _T_406 = or(_T_405, _T_404) node _T_407 = eq(io.rw.addr, UInt<10>(0h342)) node _T_408 = and(_T_406, _T_407) else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_410 = eq(io.rw.addr, UInt<10>(0h342)) node _T_411 = and(_T_409, _T_410) node _T_412 = andr(UInt<2>(0h3)) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_417 = or(_T_414, _T_415) node _T_418 = or(_T_417, _T_416) node _T_419 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_420 = and(_T_418, _T_419) else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_422 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_423 = and(_T_421, _T_422) node _T_424 = andr(UInt<2>(0h1)) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_429 = or(_T_426, _T_427) node _T_430 = or(_T_429, _T_428) node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_432 = and(_T_430, _T_431) else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_435 = and(_T_433, _T_434) node _T_436 = andr(UInt<2>(0h1)) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_441 = or(_T_438, _T_439) node _T_442 = or(_T_441, _T_440) node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_444 = and(_T_442, _T_443) else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_447 = and(_T_445, _T_446) node _T_448 = andr(UInt<2>(0h1)) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_453 = or(_T_450, _T_451) node _T_454 = or(_T_453, _T_452) node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_456 = and(_T_454, _T_455) else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_459 = and(_T_457, _T_458) node _T_460 = andr(UInt<2>(0h0)) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_465 = or(_T_462, _T_463) node _T_466 = or(_T_465, _T_464) node _T_467 = eq(io.rw.addr, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_470 = eq(io.rw.addr, UInt<1>(0h1)) node _T_471 = and(_T_469, _T_470) node _T_472 = andr(UInt<2>(0h0)) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_477 = or(_T_474, _T_475) node _T_478 = or(_T_477, _T_476) node _T_479 = eq(io.rw.addr, UInt<2>(0h2)) node _T_480 = and(_T_478, _T_479) else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_482 = eq(io.rw.addr, UInt<2>(0h2)) node _T_483 = and(_T_481, _T_482) node _T_484 = andr(UInt<2>(0h0)) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_489 = or(_T_486, _T_487) node _T_490 = or(_T_489, _T_488) node _T_491 = eq(io.rw.addr, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_494 = eq(io.rw.addr, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = andr(UInt<2>(0h0)) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_501 = or(_T_498, _T_499) node _T_502 = or(_T_501, _T_500) node _T_503 = eq(io.rw.addr, UInt<10>(0h320)) node _T_504 = and(_T_502, _T_503) else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_506 = eq(io.rw.addr, UInt<10>(0h320)) node _T_507 = and(_T_505, _T_506) node _T_508 = andr(UInt<2>(0h2)) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_513 = or(_T_510, _T_511) node _T_514 = or(_T_513, _T_512) node _T_515 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_516 = and(_T_514, _T_515) else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_518 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_519 = and(_T_517, _T_518) node _T_520 = andr(UInt<2>(0h2)) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_525 = or(_T_522, _T_523) node _T_526 = or(_T_525, _T_524) node _T_527 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_528 = and(_T_526, _T_527) else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_530 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_531 = and(_T_529, _T_530) node _T_532 = andr(UInt<2>(0h0)) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_537 = or(_T_534, _T_535) node _T_538 = or(_T_537, _T_536) node _T_539 = eq(io.rw.addr, UInt<10>(0h323)) node _T_540 = and(_T_538, _T_539) else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_542 = eq(io.rw.addr, UInt<10>(0h323)) node _T_543 = and(_T_541, _T_542) node _T_544 = andr(UInt<2>(0h2)) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_549 = or(_T_546, _T_547) node _T_550 = or(_T_549, _T_548) node _T_551 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_552 = and(_T_550, _T_551) else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_554 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_555 = and(_T_553, _T_554) node _T_556 = andr(UInt<2>(0h0)) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_561 = or(_T_558, _T_559) node _T_562 = or(_T_561, _T_560) node _T_563 = eq(io.rw.addr, UInt<10>(0h324)) node _T_564 = and(_T_562, _T_563) else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_566 = eq(io.rw.addr, UInt<10>(0h324)) node _T_567 = and(_T_565, _T_566) node _T_568 = andr(UInt<2>(0h2)) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_573 = or(_T_570, _T_571) node _T_574 = or(_T_573, _T_572) node _T_575 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_576 = and(_T_574, _T_575) else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_578 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_579 = and(_T_577, _T_578) node _T_580 = andr(UInt<2>(0h0)) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_585 = or(_T_582, _T_583) node _T_586 = or(_T_585, _T_584) node _T_587 = eq(io.rw.addr, UInt<10>(0h325)) node _T_588 = and(_T_586, _T_587) else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_590 = eq(io.rw.addr, UInt<10>(0h325)) node _T_591 = and(_T_589, _T_590) node _T_592 = andr(UInt<2>(0h2)) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_597 = or(_T_594, _T_595) node _T_598 = or(_T_597, _T_596) node _T_599 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_600 = and(_T_598, _T_599) else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_602 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_603 = and(_T_601, _T_602) node _T_604 = andr(UInt<2>(0h0)) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_609 = or(_T_606, _T_607) node _T_610 = or(_T_609, _T_608) node _T_611 = eq(io.rw.addr, UInt<10>(0h326)) node _T_612 = and(_T_610, _T_611) else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_614 = eq(io.rw.addr, UInt<10>(0h326)) node _T_615 = and(_T_613, _T_614) node _T_616 = andr(UInt<2>(0h2)) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_621 = or(_T_618, _T_619) node _T_622 = or(_T_621, _T_620) node _T_623 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_624 = and(_T_622, _T_623) else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_626 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_627 = and(_T_625, _T_626) node _T_628 = andr(UInt<2>(0h0)) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_633 = or(_T_630, _T_631) node _T_634 = or(_T_633, _T_632) node _T_635 = eq(io.rw.addr, UInt<10>(0h327)) node _T_636 = and(_T_634, _T_635) else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_638 = eq(io.rw.addr, UInt<10>(0h327)) node _T_639 = and(_T_637, _T_638) node _T_640 = andr(UInt<2>(0h2)) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_645 = or(_T_642, _T_643) node _T_646 = or(_T_645, _T_644) node _T_647 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_648 = and(_T_646, _T_647) else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_650 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_651 = and(_T_649, _T_650) node _T_652 = andr(UInt<2>(0h0)) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_657 = or(_T_654, _T_655) node _T_658 = or(_T_657, _T_656) node _T_659 = eq(io.rw.addr, UInt<10>(0h328)) node _T_660 = and(_T_658, _T_659) else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_662 = eq(io.rw.addr, UInt<10>(0h328)) node _T_663 = and(_T_661, _T_662) node _T_664 = andr(UInt<2>(0h2)) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_669 = or(_T_666, _T_667) node _T_670 = or(_T_669, _T_668) node _T_671 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_672 = and(_T_670, _T_671) else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_674 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_675 = and(_T_673, _T_674) node _T_676 = andr(UInt<2>(0h0)) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_681 = or(_T_678, _T_679) node _T_682 = or(_T_681, _T_680) node _T_683 = eq(io.rw.addr, UInt<10>(0h329)) node _T_684 = and(_T_682, _T_683) else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_686 = eq(io.rw.addr, UInt<10>(0h329)) node _T_687 = and(_T_685, _T_686) node _T_688 = andr(UInt<2>(0h2)) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_693 = or(_T_690, _T_691) node _T_694 = or(_T_693, _T_692) node _T_695 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_696 = and(_T_694, _T_695) else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_698 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_699 = and(_T_697, _T_698) node _T_700 = andr(UInt<2>(0h0)) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_705 = or(_T_702, _T_703) node _T_706 = or(_T_705, _T_704) node _T_707 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_708 = and(_T_706, _T_707) else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_710 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_711 = and(_T_709, _T_710) node _T_712 = andr(UInt<2>(0h2)) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_717 = or(_T_714, _T_715) node _T_718 = or(_T_717, _T_716) node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_720 = and(_T_718, _T_719) else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_723 = and(_T_721, _T_722) node _T_724 = andr(UInt<2>(0h0)) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_729 = or(_T_726, _T_727) node _T_730 = or(_T_729, _T_728) node _T_731 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_732 = and(_T_730, _T_731) else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_734 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_735 = and(_T_733, _T_734) node _T_736 = andr(UInt<2>(0h2)) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_741 = or(_T_738, _T_739) node _T_742 = or(_T_741, _T_740) node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_744 = and(_T_742, _T_743) else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_747 = and(_T_745, _T_746) node _T_748 = andr(UInt<2>(0h0)) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_753 = or(_T_750, _T_751) node _T_754 = or(_T_753, _T_752) node _T_755 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_756 = and(_T_754, _T_755) else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_758 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_759 = and(_T_757, _T_758) node _T_760 = andr(UInt<2>(0h2)) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_765 = or(_T_762, _T_763) node _T_766 = or(_T_765, _T_764) node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_768 = and(_T_766, _T_767) else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_771 = and(_T_769, _T_770) node _T_772 = andr(UInt<2>(0h0)) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_777 = or(_T_774, _T_775) node _T_778 = or(_T_777, _T_776) node _T_779 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_780 = and(_T_778, _T_779) else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_782 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_783 = and(_T_781, _T_782) node _T_784 = andr(UInt<2>(0h2)) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_789 = or(_T_786, _T_787) node _T_790 = or(_T_789, _T_788) node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_792 = and(_T_790, _T_791) else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_795 = and(_T_793, _T_794) node _T_796 = andr(UInt<2>(0h0)) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_801 = or(_T_798, _T_799) node _T_802 = or(_T_801, _T_800) node _T_803 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_804 = and(_T_802, _T_803) else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_806 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_807 = and(_T_805, _T_806) node _T_808 = andr(UInt<2>(0h2)) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_813 = or(_T_810, _T_811) node _T_814 = or(_T_813, _T_812) node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_816 = and(_T_814, _T_815) else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_819 = and(_T_817, _T_818) node _T_820 = andr(UInt<2>(0h0)) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_825 = or(_T_822, _T_823) node _T_826 = or(_T_825, _T_824) node _T_827 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_828 = and(_T_826, _T_827) else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_830 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_831 = and(_T_829, _T_830) node _T_832 = andr(UInt<2>(0h2)) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_837 = or(_T_834, _T_835) node _T_838 = or(_T_837, _T_836) node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_840 = and(_T_838, _T_839) else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_843 = and(_T_841, _T_842) node _T_844 = andr(UInt<2>(0h0)) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_849 = or(_T_846, _T_847) node _T_850 = or(_T_849, _T_848) node _T_851 = eq(io.rw.addr, UInt<10>(0h330)) node _T_852 = and(_T_850, _T_851) else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_854 = eq(io.rw.addr, UInt<10>(0h330)) node _T_855 = and(_T_853, _T_854) node _T_856 = andr(UInt<2>(0h2)) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_864 = and(_T_862, _T_863) else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_866 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_867 = and(_T_865, _T_866) node _T_868 = andr(UInt<2>(0h0)) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_873 = or(_T_870, _T_871) node _T_874 = or(_T_873, _T_872) node _T_875 = eq(io.rw.addr, UInt<10>(0h331)) node _T_876 = and(_T_874, _T_875) else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_878 = eq(io.rw.addr, UInt<10>(0h331)) node _T_879 = and(_T_877, _T_878) node _T_880 = andr(UInt<2>(0h2)) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_885 = or(_T_882, _T_883) node _T_886 = or(_T_885, _T_884) node _T_887 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_888 = and(_T_886, _T_887) else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_890 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_891 = and(_T_889, _T_890) node _T_892 = andr(UInt<2>(0h0)) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_897 = or(_T_894, _T_895) node _T_898 = or(_T_897, _T_896) node _T_899 = eq(io.rw.addr, UInt<10>(0h332)) node _T_900 = and(_T_898, _T_899) else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_902 = eq(io.rw.addr, UInt<10>(0h332)) node _T_903 = and(_T_901, _T_902) node _T_904 = andr(UInt<2>(0h2)) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_909 = or(_T_906, _T_907) node _T_910 = or(_T_909, _T_908) node _T_911 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_912 = and(_T_910, _T_911) else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_914 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_915 = and(_T_913, _T_914) node _T_916 = andr(UInt<2>(0h0)) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_921 = or(_T_918, _T_919) node _T_922 = or(_T_921, _T_920) node _T_923 = eq(io.rw.addr, UInt<10>(0h333)) node _T_924 = and(_T_922, _T_923) else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_926 = eq(io.rw.addr, UInt<10>(0h333)) node _T_927 = and(_T_925, _T_926) node _T_928 = andr(UInt<2>(0h2)) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_933 = or(_T_930, _T_931) node _T_934 = or(_T_933, _T_932) node _T_935 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_936 = and(_T_934, _T_935) else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_938 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_939 = and(_T_937, _T_938) node _T_940 = andr(UInt<2>(0h0)) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_945 = or(_T_942, _T_943) node _T_946 = or(_T_945, _T_944) node _T_947 = eq(io.rw.addr, UInt<10>(0h334)) node _T_948 = and(_T_946, _T_947) else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_950 = eq(io.rw.addr, UInt<10>(0h334)) node _T_951 = and(_T_949, _T_950) node _T_952 = andr(UInt<2>(0h2)) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_957 = or(_T_954, _T_955) node _T_958 = or(_T_957, _T_956) node _T_959 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_960 = and(_T_958, _T_959) else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_962 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_963 = and(_T_961, _T_962) node _T_964 = andr(UInt<2>(0h0)) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_969 = or(_T_966, _T_967) node _T_970 = or(_T_969, _T_968) node _T_971 = eq(io.rw.addr, UInt<10>(0h335)) node _T_972 = and(_T_970, _T_971) else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_974 = eq(io.rw.addr, UInt<10>(0h335)) node _T_975 = and(_T_973, _T_974) node _T_976 = andr(UInt<2>(0h2)) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_981 = or(_T_978, _T_979) node _T_982 = or(_T_981, _T_980) node _T_983 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_984 = and(_T_982, _T_983) else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_986 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_987 = and(_T_985, _T_986) node _T_988 = andr(UInt<2>(0h0)) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_993 = or(_T_990, _T_991) node _T_994 = or(_T_993, _T_992) node _T_995 = eq(io.rw.addr, UInt<10>(0h336)) node _T_996 = and(_T_994, _T_995) else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_998 = eq(io.rw.addr, UInt<10>(0h336)) node _T_999 = and(_T_997, _T_998) node _T_1000 = andr(UInt<2>(0h2)) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1005 = or(_T_1002, _T_1003) node _T_1006 = or(_T_1005, _T_1004) node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1008 = and(_T_1006, _T_1007) else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = andr(UInt<2>(0h0)) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1017 = or(_T_1014, _T_1015) node _T_1018 = or(_T_1017, _T_1016) node _T_1019 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1020 = and(_T_1018, _T_1019) else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1022 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = andr(UInt<2>(0h2)) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1029 = or(_T_1026, _T_1027) node _T_1030 = or(_T_1029, _T_1028) node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1032 = and(_T_1030, _T_1031) else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1035 = and(_T_1033, _T_1034) node _T_1036 = andr(UInt<2>(0h0)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1041 = or(_T_1038, _T_1039) node _T_1042 = or(_T_1041, _T_1040) node _T_1043 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1044 = and(_T_1042, _T_1043) else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1046 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = andr(UInt<2>(0h2)) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1053 = or(_T_1050, _T_1051) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1056 = and(_T_1054, _T_1055) else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = andr(UInt<2>(0h0)) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1065 = or(_T_1062, _T_1063) node _T_1066 = or(_T_1065, _T_1064) node _T_1067 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1068 = and(_T_1066, _T_1067) else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1070 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = andr(UInt<2>(0h2)) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1077 = or(_T_1074, _T_1075) node _T_1078 = or(_T_1077, _T_1076) node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1080 = and(_T_1078, _T_1079) else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = andr(UInt<2>(0h0)) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1089 = or(_T_1086, _T_1087) node _T_1090 = or(_T_1089, _T_1088) node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1092 = and(_T_1090, _T_1091) else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = andr(UInt<2>(0h2)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1101 = or(_T_1098, _T_1099) node _T_1102 = or(_T_1101, _T_1100) node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1104 = and(_T_1102, _T_1103) else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = andr(UInt<2>(0h0)) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1113 = or(_T_1110, _T_1111) node _T_1114 = or(_T_1113, _T_1112) node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1116 = and(_T_1114, _T_1115) else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = andr(UInt<2>(0h2)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1125 = or(_T_1122, _T_1123) node _T_1126 = or(_T_1125, _T_1124) node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1128 = and(_T_1126, _T_1127) else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = andr(UInt<2>(0h0)) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1137 = or(_T_1134, _T_1135) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1140 = and(_T_1138, _T_1139) else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = andr(UInt<2>(0h2)) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1149 = or(_T_1146, _T_1147) node _T_1150 = or(_T_1149, _T_1148) node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1152 = and(_T_1150, _T_1151) else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = andr(UInt<2>(0h0)) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1161 = or(_T_1158, _T_1159) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1164 = and(_T_1162, _T_1163) else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = andr(UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1173 = or(_T_1170, _T_1171) node _T_1174 = or(_T_1173, _T_1172) node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1176 = and(_T_1174, _T_1175) else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = andr(UInt<2>(0h0)) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1185 = or(_T_1182, _T_1183) node _T_1186 = or(_T_1185, _T_1184) node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1188 = and(_T_1186, _T_1187) else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = andr(UInt<2>(0h2)) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1197 = or(_T_1194, _T_1195) node _T_1198 = or(_T_1197, _T_1196) node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1200 = and(_T_1198, _T_1199) else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = andr(UInt<2>(0h0)) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1209 = or(_T_1206, _T_1207) node _T_1210 = or(_T_1209, _T_1208) node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1212 = and(_T_1210, _T_1211) else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = andr(UInt<2>(0h2)) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1221 = or(_T_1218, _T_1219) node _T_1222 = or(_T_1221, _T_1220) node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1224 = and(_T_1222, _T_1223) else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = andr(UInt<2>(0h0)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1233 = or(_T_1230, _T_1231) node _T_1234 = or(_T_1233, _T_1232) node _T_1235 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1236 = and(_T_1234, _T_1235) else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1238 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = andr(UInt<2>(0h3)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1245 = or(_T_1242, _T_1243) node _T_1246 = or(_T_1245, _T_1244) node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1248 = and(_T_1246, _T_1247) else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = andr(UInt<2>(0h3)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1257 = or(_T_1254, _T_1255) node _T_1258 = or(_T_1257, _T_1256) node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1260 = and(_T_1258, _T_1259) else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = andr(UInt<2>(0h0)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1269 = or(_T_1266, _T_1267) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1272 = and(_T_1270, _T_1271) else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = andr(UInt<2>(0h0)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1281 = or(_T_1278, _T_1279) node _T_1282 = or(_T_1281, _T_1280) node _T_1283 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1284 = and(_T_1282, _T_1283) else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1286 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = andr(UInt<2>(0h0)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1293 = or(_T_1290, _T_1291) node _T_1294 = or(_T_1293, _T_1292) node _T_1295 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1296 = and(_T_1294, _T_1295) else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1298 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = andr(UInt<2>(0h0)) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1305 = or(_T_1302, _T_1303) node _T_1306 = or(_T_1305, _T_1304) node _T_1307 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1308 = and(_T_1306, _T_1307) else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1310 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = andr(UInt<2>(0h0)) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1317 = or(_T_1314, _T_1315) node _T_1318 = or(_T_1317, _T_1316) node _T_1319 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1320 = and(_T_1318, _T_1319) else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1322 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = andr(UInt<2>(0h0)) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1329 = or(_T_1326, _T_1327) node _T_1330 = or(_T_1329, _T_1328) node _T_1331 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1332 = and(_T_1330, _T_1331) else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1334 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = andr(UInt<2>(0h0)) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1341 = or(_T_1338, _T_1339) node _T_1342 = or(_T_1341, _T_1340) node _T_1343 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1344 = and(_T_1342, _T_1343) else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1346 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = andr(UInt<2>(0h0)) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1353 = or(_T_1350, _T_1351) node _T_1354 = or(_T_1353, _T_1352) node _T_1355 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1356 = and(_T_1354, _T_1355) else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1358 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = andr(UInt<2>(0h0)) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1365 = or(_T_1362, _T_1363) node _T_1366 = or(_T_1365, _T_1364) node _T_1367 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1368 = and(_T_1366, _T_1367) else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1370 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1371 = and(_T_1369, _T_1370) node _T_1372 = andr(UInt<2>(0h0)) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1377 = or(_T_1374, _T_1375) node _T_1378 = or(_T_1377, _T_1376) node _T_1379 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1380 = and(_T_1378, _T_1379) else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1382 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = andr(UInt<2>(0h0)) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1389 = or(_T_1386, _T_1387) node _T_1390 = or(_T_1389, _T_1388) node _T_1391 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1392 = and(_T_1390, _T_1391) else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1394 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = andr(UInt<2>(0h0)) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1401 = or(_T_1398, _T_1399) node _T_1402 = or(_T_1401, _T_1400) node _T_1403 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1404 = and(_T_1402, _T_1403) else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1406 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = andr(UInt<2>(0h0)) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1413 = or(_T_1410, _T_1411) node _T_1414 = or(_T_1413, _T_1412) node _T_1415 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1416 = and(_T_1414, _T_1415) else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1418 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = andr(UInt<2>(0h0)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1425 = or(_T_1422, _T_1423) node _T_1426 = or(_T_1425, _T_1424) node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1428 = and(_T_1426, _T_1427) else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = andr(UInt<2>(0h0)) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1437 = or(_T_1434, _T_1435) node _T_1438 = or(_T_1437, _T_1436) node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1440 = and(_T_1438, _T_1439) else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = andr(UInt<2>(0h0)) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1449 = or(_T_1446, _T_1447) node _T_1450 = or(_T_1449, _T_1448) node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1452 = and(_T_1450, _T_1451) else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = andr(UInt<2>(0h0)) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1461 = or(_T_1458, _T_1459) node _T_1462 = or(_T_1461, _T_1460) node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1464 = and(_T_1462, _T_1463) else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = andr(UInt<2>(0h0)) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1473 = or(_T_1470, _T_1471) node _T_1474 = or(_T_1473, _T_1472) node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1476 = and(_T_1474, _T_1475) else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = andr(UInt<2>(0h0)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1485 = or(_T_1482, _T_1483) node _T_1486 = or(_T_1485, _T_1484) node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1488 = and(_T_1486, _T_1487) else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = andr(UInt<2>(0h0)) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1497 = or(_T_1494, _T_1495) node _T_1498 = or(_T_1497, _T_1496) node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1500 = and(_T_1498, _T_1499) else : node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = andr(UInt<2>(0h0)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1509 = or(_T_1506, _T_1507) node _T_1510 = or(_T_1509, _T_1508) node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1512 = and(_T_1510, _T_1511) else : node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = andr(UInt<2>(0h0)) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1521 = or(_T_1518, _T_1519) node _T_1522 = or(_T_1521, _T_1520) node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1524 = and(_T_1522, _T_1523) else : node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = andr(UInt<2>(0h0)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1533 = or(_T_1530, _T_1531) node _T_1534 = or(_T_1533, _T_1532) node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1536 = and(_T_1534, _T_1535) else : node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1539 = and(_T_1537, _T_1538) node _T_1540 = andr(UInt<2>(0h0)) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1545 = or(_T_1542, _T_1543) node _T_1546 = or(_T_1545, _T_1544) node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1548 = and(_T_1546, _T_1547) else : node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = andr(UInt<2>(0h0)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1557 = or(_T_1554, _T_1555) node _T_1558 = or(_T_1557, _T_1556) node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1560 = and(_T_1558, _T_1559) else : node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = andr(UInt<2>(0h0)) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1569 = or(_T_1566, _T_1567) node _T_1570 = or(_T_1569, _T_1568) node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1572 = and(_T_1570, _T_1571) else : node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = andr(UInt<2>(0h0)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1581 = or(_T_1578, _T_1579) node _T_1582 = or(_T_1581, _T_1580) node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1584 = and(_T_1582, _T_1583) else : node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1587 = and(_T_1585, _T_1586) node _T_1588 = andr(UInt<2>(0h0)) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1593 = or(_T_1590, _T_1591) node _T_1594 = or(_T_1593, _T_1592) node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1596 = and(_T_1594, _T_1595) else : node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = andr(UInt<2>(0h0)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1605 = or(_T_1602, _T_1603) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1608 = and(_T_1606, _T_1607) else : node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = andr(UInt<2>(0h0)) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1617 = or(_T_1614, _T_1615) node _T_1618 = or(_T_1617, _T_1616) node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1620 = and(_T_1618, _T_1619) else : node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = andr(UInt<2>(0h0)) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1629 = or(_T_1626, _T_1627) node _T_1630 = or(_T_1629, _T_1628) node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1632 = and(_T_1630, _T_1631) else : node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = andr(UInt<2>(0h0)) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1641 = or(_T_1638, _T_1639) node _T_1642 = or(_T_1641, _T_1640) node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1644 = and(_T_1642, _T_1643) else : node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = andr(UInt<2>(0h1)) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1653 = or(_T_1650, _T_1651) node _T_1654 = or(_T_1653, _T_1652) node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1656 = and(_T_1654, _T_1655) else : node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = andr(UInt<2>(0h3)) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1665 = or(_T_1662, _T_1663) node _T_1666 = or(_T_1665, _T_1664) node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1668 = and(_T_1666, _T_1667) else : node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = andr(UInt<2>(0h3)) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1677 = or(_T_1674, _T_1675) node _T_1678 = or(_T_1677, _T_1676) node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1680 = and(_T_1678, _T_1679) else : node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = andr(UInt<2>(0h3)) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1689 = or(_T_1686, _T_1687) node _T_1690 = or(_T_1689, _T_1688) node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1692 = and(_T_1690, _T_1691) else : node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = andr(UInt<2>(0h3)) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1701 = or(_T_1698, _T_1699) node _T_1702 = or(_T_1701, _T_1700) node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1704 = and(_T_1702, _T_1703) else : node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1707 = and(_T_1705, _T_1706) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_100_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.mprv, new_mstatus.mprv node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2)) node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3 connect reg_mstatus.spp, new_mstatus.spp connect reg_mstatus.spie, new_mstatus.spie connect reg_mstatus.sie, new_mstatus.sie connect reg_mstatus.tw, new_mstatus.tw connect reg_mstatus.tsr, new_mstatus.tsr connect reg_mstatus.mxr, new_mstatus.mxr connect reg_mstatus.sum, new_mstatus.sum connect reg_mstatus.tvm, new_mstatus.tvm node _reg_mstatus_fs_T = orr(new_mstatus.fs) node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_1 connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_94_2 : node f = bits(wdata, 5, 5) node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_1709 = bits(io.pc, 1, 1) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1708, _T_1710) node _T_1712 = bits(wdata, 2, 2) node _T_1713 = or(_T_1711, _T_1712) when _T_1713 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) node _reg_misa_T_6 = not(UInt<64>(0h102d)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_108_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 connect reg_mip.ssip, new_mip.ssip connect reg_mip.stip, new_mip.stip connect reg_mip.seip, new_mip.seip when decoded_addr_76_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_132_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_129_2 : connect reg_mscratch, wdata when decoded_addr_72_2 : connect reg_mtvec, wdata when decoded_addr_29_2 : node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_136_2 : connect reg_mtval, wdata when decoded_addr_130_2 : node _reg_mcountinhibit_T = not(UInt<64>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_103_2 : node _T_1714 = bits(wdata, 63, 0) connect small_1, _T_1714 node _large_T_6 = shr(_T_1714, 6) connect large_1, _large_T_6 when decoded_addr_121_2 : node _T_1715 = bits(wdata, 63, 0) connect small, _T_1715 node _large_T_7 = shr(_T_1715, 6) connect large, _large_T_7 when decoded_addr_36_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata when decoded_addr_68_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_frm, wdata when decoded_addr_99_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata node _reg_frm_T = shr(wdata, 5) connect reg_frm, _reg_frm_T when decoded_addr_49_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm connect reg_dcsr.ebreaks, new_dcsr.ebreaks connect reg_dcsr.ebreaku, new_dcsr.ebreaku node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2)) node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv) connect reg_dcsr.prv, _reg_dcsr_prv_T_1 when decoded_addr_89_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_57_2 : connect reg_dscratch0, wdata when decoded_addr_61_2 : wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_sstatus_WIRE : UInt<105> connect _new_sstatus_WIRE, wdata node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0) connect new_sstatus.uie, _new_sstatus_T node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1) connect new_sstatus.sie, _new_sstatus_T_1 node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2) connect new_sstatus.hie, _new_sstatus_T_2 node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3) connect new_sstatus.mie, _new_sstatus_T_3 node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4) connect new_sstatus.upie, _new_sstatus_T_4 node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5) connect new_sstatus.spie, _new_sstatus_T_5 node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6) connect new_sstatus.ube, _new_sstatus_T_6 node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7) connect new_sstatus.mpie, _new_sstatus_T_7 node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8) connect new_sstatus.spp, _new_sstatus_T_8 node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9) connect new_sstatus.vs, _new_sstatus_T_9 node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11) connect new_sstatus.mpp, _new_sstatus_T_10 node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13) connect new_sstatus.fs, _new_sstatus_T_11 node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15) connect new_sstatus.xs, _new_sstatus_T_12 node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17) connect new_sstatus.mprv, _new_sstatus_T_13 node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18) connect new_sstatus.sum, _new_sstatus_T_14 node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19) connect new_sstatus.mxr, _new_sstatus_T_15 node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20) connect new_sstatus.tvm, _new_sstatus_T_16 node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21) connect new_sstatus.tw, _new_sstatus_T_17 node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22) connect new_sstatus.tsr, _new_sstatus_T_18 node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23) connect new_sstatus.zero1, _new_sstatus_T_19 node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31) connect new_sstatus.sd_rv32, _new_sstatus_T_20 node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32) connect new_sstatus.uxl, _new_sstatus_T_21 node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34) connect new_sstatus.sxl, _new_sstatus_T_22 node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36) connect new_sstatus.sbe, _new_sstatus_T_23 node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37) connect new_sstatus.mbe, _new_sstatus_T_24 node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38) connect new_sstatus.gva, _new_sstatus_T_25 node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39) connect new_sstatus.mpv, _new_sstatus_T_26 node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40) connect new_sstatus.zero2, _new_sstatus_T_27 node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63) connect new_sstatus.sd, _new_sstatus_T_28 node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64) connect new_sstatus.v, _new_sstatus_T_29 node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65) connect new_sstatus.prv, _new_sstatus_T_30 node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67) connect new_sstatus.dv, _new_sstatus_T_31 node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68) connect new_sstatus.dprv, _new_sstatus_T_32 node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70) connect new_sstatus.isa, _new_sstatus_T_33 node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102) connect new_sstatus.wfi, _new_sstatus_T_34 node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103) connect new_sstatus.cease, _new_sstatus_T_35 node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104) connect new_sstatus.debug, _new_sstatus_T_36 connect reg_mstatus.sie, new_sstatus.sie connect reg_mstatus.spie, new_sstatus.spie connect reg_mstatus.spp, new_sstatus.spp node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs) node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_3 connect reg_mstatus.vs, UInt<1>(0h0) connect reg_mstatus.mxr, new_sstatus.mxr connect reg_mstatus.sum, new_sstatus.sum when decoded_addr_48_2 : node _new_sip_T = not(read_mideleg) node _new_sip_T_1 = and(read_mip, _new_sip_T) node _new_sip_T_2 = and(wdata, read_mideleg) node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2) wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_sip_WIRE : UInt<16> connect _new_sip_WIRE, _new_sip_T_3 node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0) connect new_sip.usip, _new_sip_T_4 node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1) connect new_sip.ssip, _new_sip_T_5 node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2) connect new_sip.vssip, _new_sip_T_6 node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3) connect new_sip.msip, _new_sip_T_7 node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4) connect new_sip.utip, _new_sip_T_8 node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5) connect new_sip.stip, _new_sip_T_9 node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6) connect new_sip.vstip, _new_sip_T_10 node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7) connect new_sip.mtip, _new_sip_T_11 node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8) connect new_sip.ueip, _new_sip_T_12 node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9) connect new_sip.seip, _new_sip_T_13 node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10) connect new_sip.vseip, _new_sip_T_14 node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11) connect new_sip.meip, _new_sip_T_15 node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12) connect new_sip.sgeip, _new_sip_T_16 node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13) connect new_sip.rocc, _new_sip_T_17 node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14) connect new_sip.debug, _new_sip_T_18 node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15) connect new_sip.zero1, _new_sip_T_19 connect reg_mip.ssip, new_sip.ssip when decoded_addr_6_2 : wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} wire _new_satp_WIRE : UInt<64> connect _new_satp_WIRE, wdata node _new_satp_T = bits(_new_satp_WIRE, 43, 0) connect new_satp.ppn, _new_satp_T node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44) connect new_satp.asid, _new_satp_T_1 node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60) connect new_satp.mode, _new_satp_T_2 node _T_1716 = eq(new_satp.mode, UInt<1>(0h0)) node _T_1717 = eq(new_satp.mode, UInt<4>(0h8)) node _T_1718 = or(_T_1716, _T_1717) when _T_1718 : node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8)) connect reg_satp.mode, _reg_satp_mode_T node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0) connect reg_satp.ppn, _reg_satp_ppn_T when decoded_addr_44_2 : node _reg_mie_T_1 = not(sie_mask) node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1) node _reg_mie_T_3 = and(wdata, sie_mask) node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3) connect reg_mie, _reg_mie_T_4 when decoded_addr_15_2 : connect reg_sscratch, wdata when decoded_addr_28_2 : node _reg_sepc_T = not(wdata) node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1)) node _reg_sepc_T_2 = not(_reg_sepc_T_1) connect reg_sepc, _reg_sepc_T_2 when decoded_addr_25_2 : connect reg_stvec, wdata when decoded_addr_145_2 : node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f)) connect reg_scause, _reg_scause_T when decoded_addr_93_2 : connect reg_stval, wdata when decoded_addr_123_2 : connect reg_mideleg, wdata when decoded_addr_23_2 : connect reg_medeleg, wdata when decoded_addr_137_2 : connect reg_scounteren, wdata when decoded_addr_69_2 : wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE : UInt<64> connect _new_envcfg_WIRE, wdata node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0) connect new_envcfg.fiom, _new_envcfg_T node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1) connect new_envcfg.zero3, _new_envcfg_T_1 node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4) connect new_envcfg.cbie, _new_envcfg_T_2 node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6) connect new_envcfg.cbcfe, _new_envcfg_T_3 node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7) connect new_envcfg.cbze, _new_envcfg_T_4 node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8) connect new_envcfg.zero54, _new_envcfg_T_5 node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62) connect new_envcfg.pbmte, _new_envcfg_T_6 node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63) connect new_envcfg.stce, _new_envcfg_T_7 connect reg_senvcfg.fiom, new_envcfg.fiom when decoded_addr_35_2 : connect reg_mcounteren, wdata when decoded_addr_42_2 : wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE_1 : UInt<64> connect _new_envcfg_WIRE_1, wdata node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0) connect new_envcfg_1.fiom, _new_envcfg_T_8 node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1) connect new_envcfg_1.zero3, _new_envcfg_T_9 node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4) connect new_envcfg_1.cbie, _new_envcfg_T_10 node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6) connect new_envcfg_1.cbcfe, _new_envcfg_T_11 node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7) connect new_envcfg_1.cbze, _new_envcfg_T_12 node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8) connect new_envcfg_1.zero54, _new_envcfg_T_13 node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62) connect new_envcfg_1.pbmte, _new_envcfg_T_14 node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63) connect new_envcfg_1.stce, _new_envcfg_T_15 connect reg_menvcfg.fiom, new_envcfg_1.fiom when decoded_addr_97_2 : connect reg_tselect, wdata node _T_1719 = eq(UInt<1>(0h0), reg_tselect) node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_1721 = or(_T_1720, reg_debug) node _T_1722 = and(_T_1719, _T_1721) when _T_1722 : when decoded_addr_10_2 : connect reg_bp[0].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<64> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<64> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_1723 = gt(newBPC.action, UInt<1>(0h1)) node _T_1724 = or(dMode, _T_1723) when _T_1724 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_1725 = eq(UInt<1>(0h1), reg_tselect) node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_1727 = or(_T_1726, reg_debug) node _T_1728 = and(_T_1725, _T_1727) when _T_1728 : when decoded_addr_10_2 : connect reg_bp[1].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<64> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<64> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_1730 = or(dMode_1, _T_1729) when _T_1730 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_1732 = and(decoded_addr_141_2, _T_1731) when _T_1732 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736) node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737) node _T_1739 = eq(_T_1738, UInt<1>(0h0)) node _T_1740 = and(decoded_addr_104_2, _T_1739) when _T_1740 : connect reg_pmp[0].addr, wdata node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_1742 = and(decoded_addr_141_2, _T_1741) when _T_1742 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746) node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = and(decoded_addr_8_2, _T_1749) when _T_1750 : connect reg_pmp[1].addr, wdata node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_1752 = and(decoded_addr_141_2, _T_1751) when _T_1752 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756) node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = and(decoded_addr_125_2, _T_1759) when _T_1760 : connect reg_pmp[2].addr, wdata node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_1762 = and(decoded_addr_141_2, _T_1761) when _T_1762 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766) node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = and(decoded_addr_85_2, _T_1769) when _T_1770 : connect reg_pmp[3].addr, wdata node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_1772 = and(decoded_addr_141_2, _T_1771) when _T_1772 : node _newCfg_T_28 = shr(wdata, 32) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776) node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) node _T_1780 = and(decoded_addr_54_2, _T_1779) when _T_1780 : connect reg_pmp[4].addr, wdata node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_1782 = and(decoded_addr_141_2, _T_1781) when _T_1782 : node _newCfg_T_35 = shr(wdata, 40) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786) node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = and(decoded_addr_20_2, _T_1789) when _T_1790 : connect reg_pmp[5].addr, wdata node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_1792 = and(decoded_addr_141_2, _T_1791) when _T_1792 : node _newCfg_T_42 = shr(wdata, 48) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1796 = and(_T_1794, _T_1795) node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796) node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = and(decoded_addr_135_2, _T_1799) when _T_1800 : connect reg_pmp[6].addr, wdata node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_1802 = and(decoded_addr_141_2, _T_1801) when _T_1802 : node _newCfg_T_49 = shr(wdata, 56) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806) node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = and(decoded_addr_115_2, _T_1809) when _T_1810 : connect reg_pmp[7].addr, wdata when decoded_addr_18_2 : node _reg_custom_0_T = and(wdata, UInt<64>(0h208)) node _reg_custom_0_T_1 = not(UInt<64>(0h208)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) node _reg_custom_1_T_1 = not(UInt<64>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_38_2 : node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) node _reg_custom_2_T_1 = not(UInt<64>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_127_2 : node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) node _reg_custom_3_T_1 = not(UInt<64>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208)) node _reg_custom_0_T_5 = not(UInt<64>(0h208)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) node _reg_custom_1_T_5 = not(UInt<64>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) node _reg_custom_2_T_5 = not(UInt<64>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) node _reg_custom_3_T_5 = not(UInt<64>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_1811 = asUInt(reset) when _T_1811 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) node _T_1812 = asUInt(reset) when _T_1812 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) node _T_1813 = asUInt(reset) when _T_1813 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<39>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_1814 = asUInt(reset) when _T_1814 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_1815 = asUInt(reset) when _T_1815 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_1816 = asUInt(reset) when _T_1816 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_1817 = asUInt(reset) when _T_1817 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_1818 = asUInt(reset) when _T_1818 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_1819 = asUInt(reset) when _T_1819 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_1820 = asUInt(reset) when _T_1820 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_1821 = asUInt(reset) when _T_1821 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 63, 63) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval	module CSRFile_7( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [2:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output io_hstatus_spvp, // @[CSR.scala:384:14] output io_hstatus_spv, // @[CSR.scala:384:14] output io_hstatus_gva, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output io_gstatus_sd, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output [1:0] io_gstatus_vs, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input [39:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [63:0] io_trace_0_cause, // @[CSR.scala:384:14] output [39:0] io_trace_0_tval, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire [2:0] io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire delegable_24 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire delegable_29 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire delegable_26 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67] wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48] wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp_0; // @[CSR.scala:377:7] wire io_hstatus_spv_0; // @[CSR.scala:377:7] wire io_hstatus_gva_0; // @[CSR.scala:377:7] wire io_gstatus_sd_0; // @[CSR.scala:377:7] wire io_gstatus_spp_0; // @[CSR.scala:377:7] wire io_gstatus_spie_0; // @[CSR.scala:377:7] wire io_gstatus_sie_0; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_m_0; // @[CSR.scala:377:7] wire io_bp_0_control_s_0; // @[CSR.scala:377:7] wire io_bp_0_control_u_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip \| io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T \| reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 \| read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v \| _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 \| _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T \| _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T \| _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 \| _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 \| _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 \| _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 \| _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 \| _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 \| _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 \| _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 \| _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 \| _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 \| _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 \| _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 \| _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 \| _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 \| _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 \| _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 \| _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 \| _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 \| _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 \| _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 \| _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 \| _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 \| _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 \| _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 \| _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 \| _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 \| _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 \| _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 \| _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 \| _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 \| _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 \| _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 \| _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 \| _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 \| _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 \| _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 \| _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 \| _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 \| _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 \| _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 \| _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 \| _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 \| _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 \| _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 \| _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 \| _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 \| reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug \| io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 \| _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48] assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67] assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48] assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67] assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67] wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67] wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48] wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38] wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] \| _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] \| _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] \| {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = \|io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 \| io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] \| 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = \|_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = \|_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 \| _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 \| _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 \| _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 \| _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T \| _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = \|reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 \| _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T \| _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 \| _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T \| _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 \| _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 \| _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 \| _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 \| _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 \| _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 \| _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 \| _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 \| _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 \| _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 \| _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 \| _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 \| _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 \| _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 \| _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 \| _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 \| _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 \| _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 \| _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 \| _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 \| _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 \| _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 \| _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 \| _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 \| _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 \| _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 \| _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 \| _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 \| _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 \| _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 \| _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 \| _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 \| _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 \| _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 \| _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 \| _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 \| _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 \| _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 \| _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 \| _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 \| _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 \| _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 \| _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 \| _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 \| _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 \| _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 \| _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 \| _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 \| _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 \| _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 \| _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 \| _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 \| _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 \| _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 \| _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 \| _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 \| _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 \| _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 \| _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 \| _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 \| _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 \| _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 \| _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 \| _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 \| _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 \| _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 \| _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 \| _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 \| _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 \| _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 \| _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 \| _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 \| _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 \| _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 \| _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 \| _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 \| _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 \| _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 \| _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 \| _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 \| _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 \| _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 \| _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 \| _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 \| _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 \| _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 \| _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 \| _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 \| _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 \| _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 \| _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 \| _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 \| _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 \| _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 \| _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 \| _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 \| _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 \| _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 \| _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 \| _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 \| _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 \| _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 \| _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 \| _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 \| _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 \| _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 \| _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 \| _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 \| _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 \| _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 \| _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 \| _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 \| _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 \| _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 \| _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 \| _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 \| _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 \| _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 \| _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 \| _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 \| _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 \| _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 \| _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 \| _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 \| _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 \| _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 \| _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 \| _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 \| _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 \| _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 \| _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 \| _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 \| _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 \| _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 \| _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 \| _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 \| _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 \| _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 \| _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 \| _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 \| _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 \| _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 \| _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 \| _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 \| _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 \| _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 \| _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 \| _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 \| _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T \| _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 \| _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 \| _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 \| _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 \| _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 \| _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] \| 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 \| _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 \| _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 \| _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence \| is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 \| _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 \| _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 \| _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 \| _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma \| is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T \| is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 \| _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 \| _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 \| _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped \| causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T \| causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 \| causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 \| reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 \| _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_19 = insn_call \| insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T \| insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v \| _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78] assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 \| _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}] assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61] wire exception = _exception_T \| io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_476 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_476( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 : input clock : Clock input reset : Reset output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clientNodeOut.d.bits.corrupt invalidate clientNodeOut.d.bits.data invalidate clientNodeOut.d.bits.denied invalidate clientNodeOut.d.bits.sink invalidate clientNodeOut.d.bits.source invalidate clientNodeOut.d.bits.size invalidate clientNodeOut.d.bits.param invalidate clientNodeOut.d.bits.opcode invalidate clientNodeOut.d.valid invalidate clientNodeOut.d.ready invalidate clientNodeOut.a.bits.corrupt invalidate clientNodeOut.a.bits.data invalidate clientNodeOut.a.bits.mask invalidate clientNodeOut.a.bits.address invalidate clientNodeOut.a.bits.source invalidate clientNodeOut.a.bits.size invalidate clientNodeOut.a.bits.param invalidate clientNodeOut.a.bits.opcode invalidate clientNodeOut.a.valid invalidate clientNodeOut.a.ready connect auto.client_out, clientNodeOut wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect manager_tl.e.bits.sink, UInt<8>(0h0) connect manager_tl.e.valid, UInt<1>(0h0) connect manager_tl.e.ready, UInt<1>(0h0) connect manager_tl.d.bits.corrupt, UInt<1>(0h0) connect manager_tl.d.bits.data, UInt<64>(0h0) connect manager_tl.d.bits.denied, UInt<1>(0h0) connect manager_tl.d.bits.sink, UInt<8>(0h0) connect manager_tl.d.bits.source, UInt<8>(0h0) connect manager_tl.d.bits.size, UInt<8>(0h0) connect manager_tl.d.bits.param, UInt<2>(0h0) connect manager_tl.d.bits.opcode, UInt<3>(0h0) connect manager_tl.d.valid, UInt<1>(0h0) connect manager_tl.d.ready, UInt<1>(0h0) connect manager_tl.c.bits.corrupt, UInt<1>(0h0) connect manager_tl.c.bits.data, UInt<64>(0h0) connect manager_tl.c.bits.address, UInt<64>(0h0) connect manager_tl.c.bits.source, UInt<8>(0h0) connect manager_tl.c.bits.size, UInt<8>(0h0) connect manager_tl.c.bits.param, UInt<3>(0h0) connect manager_tl.c.bits.opcode, UInt<3>(0h0) connect manager_tl.c.valid, UInt<1>(0h0) connect manager_tl.c.ready, UInt<1>(0h0) connect manager_tl.b.bits.corrupt, UInt<1>(0h0) connect manager_tl.b.bits.data, UInt<64>(0h0) connect manager_tl.b.bits.mask, UInt<8>(0h0) connect manager_tl.b.bits.address, UInt<64>(0h0) connect manager_tl.b.bits.source, UInt<8>(0h0) connect manager_tl.b.bits.size, UInt<8>(0h0) connect manager_tl.b.bits.param, UInt<2>(0h0) connect manager_tl.b.bits.opcode, UInt<3>(0h0) connect manager_tl.b.valid, UInt<1>(0h0) connect manager_tl.b.ready, UInt<1>(0h0) connect manager_tl.a.bits.corrupt, UInt<1>(0h0) connect manager_tl.a.bits.data, UInt<64>(0h0) connect manager_tl.a.bits.mask, UInt<8>(0h0) connect manager_tl.a.bits.address, UInt<64>(0h0) connect manager_tl.a.bits.source, UInt<8>(0h0) connect manager_tl.a.bits.size, UInt<8>(0h0) connect manager_tl.a.bits.param, UInt<3>(0h0) connect manager_tl.a.bits.opcode, UInt<3>(0h0) connect manager_tl.a.valid, UInt<1>(0h0) connect manager_tl.a.ready, UInt<1>(0h0) inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_1_2.clock, clock connect out_channels_1_2.reset, reset wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE.bits.data, UInt<64>(0h0) connect _out_channels_WIRE.bits.mask, UInt<8>(0h0) connect _out_channels_WIRE.bits.address, UInt<32>(0h0) connect _out_channels_WIRE.bits.source, UInt<4>(0h0) connect _out_channels_WIRE.bits.size, UInt<4>(0h0) connect _out_channels_WIRE.bits.param, UInt<2>(0h0) connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_3_1.bits, _out_channels_WIRE.bits connect out_channels_3_1.valid, _out_channels_WIRE.valid connect out_channels_3_1.ready, _out_channels_WIRE.ready inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_3_2.clock, clock connect out_channels_3_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_1_2.io.protocol, clientNodeOut.d inst ser_1 of GenericSerializer_TLBeatw67_f32 connect ser_1.clock, clock connect ser_1.reset, reset connect ser_1.io.in, out_channels_1_2.io.beat connect io.ser[1].out.bits, ser_1.io.out.bits connect io.ser[1].out.valid, ser_1.io.out.valid connect ser_1.io.out.ready, io.ser[1].out.ready connect out_channels_3_2.io.protocol, out_channels_3_1 inst ser_3 of GenericSerializer_TLBeatw87_f32 connect ser_3.clock, clock connect ser_3.reset, reset connect ser_3.io.in, out_channels_3_2.io.beat connect io.ser[3].out.bits, ser_3.io.out.bits connect io.ser[3].out.valid, ser_3.io.out.valid connect ser_3.io.out.ready, io.ser[3].out.ready node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _in_channels_WIRE.bits.sink, UInt<3>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect in_channels_0_1.bits, _in_channels_WIRE.bits connect in_channels_0_1.valid, _in_channels_WIRE.valid connect in_channels_0_1.ready, _in_channels_WIRE.ready inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE_1.valid, UInt<1>(0h0) connect _in_channels_WIRE_1.ready, UInt<1>(0h0) wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_2_1.bits, _in_channels_WIRE_1.bits connect in_channels_2_1.valid, _in_channels_WIRE_1.valid connect in_channels_2_1.ready, _in_channels_WIRE_1.ready inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready inst des_0 of GenericDeserializer_TLBeatw10_f32 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready inst des_2 of GenericDeserializer_TLBeatw88_f32 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready inst des_3 of GenericDeserializer_TLBeatw87_f32 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_1 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3	module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_1_out_ready, // @[TLSerdes.scala:40:16] output io_ser_1_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_3_out_ready, // @[TLSerdes.scala:40:16] output io_ser_3_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28] wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50] wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50] wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50] wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50] TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50] .clock (clock), .reset (reset), .io_protocol_ready (auto_client_out_d_ready), .io_protocol_valid (auto_client_out_d_valid), .io_protocol_bits_opcode (auto_client_out_d_bits_opcode), .io_protocol_bits_param (auto_client_out_d_bits_param), .io_protocol_bits_size ({4'h0, auto_client_out_d_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({4'h0, auto_client_out_d_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_sink ({5'h0, auto_client_out_d_bits_sink}), // @[TLSerdes.scala:68:21] .io_protocol_bits_denied (auto_client_out_d_bits_denied), .io_protocol_bits_data (auto_client_out_d_bits_data), .io_protocol_bits_corrupt (auto_client_out_d_bits_corrupt), .io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_1_2_io_beat_valid), .io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_1_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail) ); // @[TLSerdes.scala:60:50] TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50] .clock (clock), .reset (reset), .io_beat_bits_head (_out_channels_3_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail) ); // @[TLSerdes.scala:62:50] GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_1_io_in_ready), .io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50] .io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50] .io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50] .io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50] .io_out_ready (io_ser_1_out_ready), .io_out_valid (io_ser_1_out_valid), .io_out_bits_flit (io_ser_1_out_bits_flit) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50] .io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50] .io_out_ready (io_ser_3_out_ready), .io_out_valid (io_ser_3_out_valid), .io_out_bits_flit (io_ser_3_out_bits_flit) ); // @[TLSerdes.scala:69:23] TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_ready (auto_client_out_a_ready), .io_protocol_valid (auto_client_out_a_valid), .io_protocol_bits_opcode (auto_client_out_a_bits_opcode), .io_protocol_bits_param (auto_client_out_a_bits_param), .io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address), .io_protocol_bits_mask (auto_client_out_a_bits_mask), .io_protocol_bits_data (auto_client_out_a_bits_data), .io_protocol_bits_corrupt (auto_client_out_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23] .io_in_ready (io_ser_0_in_ready), .io_in_valid (io_ser_0_in_valid), .io_in_bits_flit (io_ser_0_in_bits_flit), .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready), .io_in_valid (io_ser_1_in_valid), .io_in_bits_flit (io_ser_1_in_bits_flit), .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (/* unused /), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready), .io_in_valid (io_ser_2_in_valid), .io_in_bits_flit (io_ser_2_in_bits_flit), .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (/ unused */), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready), .io_in_valid (io_ser_3_in_valid), .io_in_bits_flit (io_ser_3_in_bits_flit), .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready), .io_in_valid (io_ser_4_in_valid), .io_in_bits_flit (io_ser_4_in_bits_flit), .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] assign auto_client_out_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] assign auto_client_out_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] assign auto_client_out_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_UInt_6 : input clock : Clock input reset : Reset output io : { flip x : UInt, y : UInt} connect io.y, io.x	module OptimizationBarrier_UInt_6( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [2:0] io_x, // @[package.scala:268:18] output [2:0] io_y // @[package.scala:268:18] ); wire [2:0] io_x_0 = io_x; // @[package.scala:267:30] wire [2:0] io_y_0 = io_x_0; // @[package.scala:267:30] assign io_y = io_y_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_91 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_104 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_91( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_7 : input clock : Clock input reset : Reset output auto : { } skip	module TLFragmenter_7( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset // @[Fragmenter.scala:92:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module DTLB_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_126 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_6 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_9 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_127 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_128 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_129 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_130 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_131 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_132 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_133 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_134 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_135 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_136 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_137 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_138 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_139 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)	module DTLB_6( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input io_req_bits_passthrough, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_ma_st, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [1:0] io_resp_size, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input io_ptw_gstatus_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire _io_req_ready_T; // @[TLB.scala:631:25] wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_ma_st_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64] wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T = do_refill \| io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 \| sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 \| sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 \| sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 \| sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 \| sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 \| sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 \| sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 \| sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 \| _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 \| _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 \| _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 \| _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 \| _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 \| _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 \| _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 \| _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 \| _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] \| _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] \| _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] \| _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 \| _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 \| _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 \| _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 \| _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 \| _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 \| _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 \| _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 \| _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 \| _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 \| _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 \| _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 \| _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 \| _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T \| sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 \| _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] _must_alloc_array_T_9 = {14{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 \| lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {\|hi_1, \|hi_2, hi_2[1] \| lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {\|hi_4, hi_4[1] \| lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 \| _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 \| _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 \| multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 \| multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 \| _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 \| multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 \| multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 \| multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 \| multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 \| _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 \| multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 \| multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 \| _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 \| multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 \| multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 \| _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T \| sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 \| sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 \| sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 \| sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 \| sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 \| sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 \| sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 \| sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 \| sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 \| sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 \| sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 \| sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 \| sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 \| sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 \| sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 \| sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 \| sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 \| sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 \| sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 \| sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = \|r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 \| r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 \| superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T \| superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 \| superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = \|r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 \| r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_109 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_109( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_30 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_30( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s13k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_24 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s13k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s13k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<13>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<13>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_50 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_51 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLBuffer_a26d64s13k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [12:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [12:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_24 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s13k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s13k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_42 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_42 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_42(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_42 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_150 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<14>(0h2000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<18>(0h2f000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<17>(0h10000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<13>(0h1000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<27>(0h4000000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = or(_T_154, _T_159) node _T_191 = or(_T_190, _T_164) node _T_192 = or(_T_191, _T_169) node _T_193 = or(_T_192, _T_174) node _T_194 = or(_T_193, _T_179) node _T_195 = or(_T_194, _T_184) node _T_196 = or(_T_195, _T_189) node _T_197 = and(_T_149, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = and(_T_148, _T_198) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_199, UInt<1>(0h1), "") : assert_2 node _T_203 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_204 = shr(io.in.a.bits.source, 2) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = leq(UInt<1>(0h0), uncommonBits_10) node _T_207 = and(_T_205, _T_206) node _T_208 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_210 = shr(io.in.a.bits.source, 2) node _T_211 = eq(_T_210, UInt<1>(0h1)) node _T_212 = leq(UInt<1>(0h0), uncommonBits_11) node _T_213 = and(_T_211, _T_212) node _T_214 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_215 = and(_T_213, _T_214) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_216 = shr(io.in.a.bits.source, 2) node _T_217 = eq(_T_216, UInt<2>(0h2)) node _T_218 = leq(UInt<1>(0h0), uncommonBits_12) node _T_219 = and(_T_217, _T_218) node _T_220 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_221 = and(_T_219, _T_220) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_222 = shr(io.in.a.bits.source, 2) node _T_223 = eq(_T_222, UInt<2>(0h3)) node _T_224 = leq(UInt<1>(0h0), uncommonBits_13) node _T_225 = and(_T_223, _T_224) node _T_226 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_227 = and(_T_225, _T_226) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_228 = shr(io.in.a.bits.source, 3) node _T_229 = eq(_T_228, UInt<3>(0h4)) node _T_230 = leq(UInt<1>(0h0), uncommonBits_14) node _T_231 = and(_T_229, _T_230) node _T_232 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_203 connect _WIRE[1], _T_209 connect _WIRE[2], _T_215 connect _WIRE[3], _T_221 connect _WIRE[4], _T_227 connect _WIRE[5], _T_233 connect _WIRE[6], _T_234 connect _WIRE[7], _T_235 node _T_236 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_237 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_238 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_242 = mux(_WIRE[5], _T_236, UInt<1>(0h0)) node _T_243 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_244 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_245 = or(_T_237, _T_238) node _T_246 = or(_T_245, _T_239) node _T_247 = or(_T_246, _T_240) node _T_248 = or(_T_247, _T_241) node _T_249 = or(_T_248, _T_242) node _T_250 = or(_T_249, _T_243) node _T_251 = or(_T_250, _T_244) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<14>(0h2000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<18>(0h2f000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<27>(0h4000000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = or(_T_260, _T_265) node _T_297 = or(_T_296, _T_270) node _T_298 = or(_T_297, _T_275) node _T_299 = or(_T_298, _T_280) node _T_300 = or(_T_299, _T_285) node _T_301 = or(_T_300, _T_290) node _T_302 = or(_T_301, _T_295) node _T_303 = and(_T_255, _T_302) node _T_304 = or(UInt<1>(0h0), _T_303) node _T_305 = and(_WIRE_1, _T_304) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_305, UInt<1>(0h1), "") : assert_3 node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(source_ok, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_312 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_312, UInt<1>(0h1), "") : assert_5 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_319 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_319, UInt<1>(0h1), "") : assert_7 node _T_323 = not(io.in.a.bits.mask) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_324, UInt<1>(0h1), "") : assert_8 node _T_328 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_328, UInt<1>(0h1), "") : assert_9 node _T_332 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_332 : node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_334 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_15) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<1>(0h1)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_16) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<2>(0h2)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_17) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_355 = shr(io.in.a.bits.source, 2) node _T_356 = eq(_T_355, UInt<2>(0h3)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_18) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_361 = shr(io.in.a.bits.source, 3) node _T_362 = eq(_T_361, UInt<3>(0h4)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_19) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_369 = or(_T_336, _T_342) node _T_370 = or(_T_369, _T_348) node _T_371 = or(_T_370, _T_354) node _T_372 = or(_T_371, _T_360) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) node _T_375 = or(_T_374, _T_368) node _T_376 = and(_T_335, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<13>(0h1000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<17>(0h10000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<18>(0h2f000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<17>(0h10000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<13>(0h1000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_383, _T_388) node _T_420 = or(_T_419, _T_393) node _T_421 = or(_T_420, _T_398) node _T_422 = or(_T_421, _T_403) node _T_423 = or(_T_422, _T_408) node _T_424 = or(_T_423, _T_413) node _T_425 = or(_T_424, _T_418) node _T_426 = and(_T_378, _T_425) node _T_427 = or(UInt<1>(0h0), _T_426) node _T_428 = and(_T_377, _T_427) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_428, UInt<1>(0h1), "") : assert_10 node _T_432 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_20) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<1>(0h1)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_21) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<2>(0h2)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_22) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_451 = shr(io.in.a.bits.source, 2) node _T_452 = eq(_T_451, UInt<2>(0h3)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_23) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_456 = and(_T_454, _T_455) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_457 = shr(io.in.a.bits.source, 3) node _T_458 = eq(_T_457, UInt<3>(0h4)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_24) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_432 connect _WIRE_2[1], _T_438 connect _WIRE_2[2], _T_444 connect _WIRE_2[3], _T_450 connect _WIRE_2[4], _T_456 connect _WIRE_2[5], _T_462 connect _WIRE_2[6], _T_463 connect _WIRE_2[7], _T_464 node _T_465 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_466 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE_2[5], _T_465, UInt<1>(0h0)) node _T_472 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = or(_T_466, _T_467) node _T_475 = or(_T_474, _T_468) node _T_476 = or(_T_475, _T_469) node _T_477 = or(_T_476, _T_470) node _T_478 = or(_T_477, _T_471) node _T_479 = or(_T_478, _T_472) node _T_480 = or(_T_479, _T_473) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_480 node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<14>(0h2000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_491 = cvt(_T_490) node _T_492 = and(_T_491, asSInt(UInt<13>(0h1000))) node _T_493 = asSInt(_T_492) node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0))) node _T_495 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<17>(0h10000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<18>(0h2f000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<17>(0h10000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<13>(0h1000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = or(_T_489, _T_494) node _T_526 = or(_T_525, _T_499) node _T_527 = or(_T_526, _T_504) node _T_528 = or(_T_527, _T_509) node _T_529 = or(_T_528, _T_514) node _T_530 = or(_T_529, _T_519) node _T_531 = or(_T_530, _T_524) node _T_532 = and(_T_484, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = and(_WIRE_3, _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_534, UInt<1>(0h1), "") : assert_11 node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(source_ok, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_541 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_541, UInt<1>(0h1), "") : assert_13 node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(is_aligned, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_548 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_548, UInt<1>(0h1), "") : assert_15 node _T_552 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_552, UInt<1>(0h1), "") : assert_16 node _T_556 = not(io.in.a.bits.mask) node _T_557 = eq(_T_556, UInt<1>(0h0)) node _T_558 = asUInt(reset) node _T_559 = eq(_T_558, UInt<1>(0h0)) when _T_559 : node _T_560 = eq(_T_557, UInt<1>(0h0)) when _T_560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_557, UInt<1>(0h1), "") : assert_17 node _T_561 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_561, UInt<1>(0h1), "") : assert_18 node _T_565 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_565 : node _T_566 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_567 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_570 = shr(io.in.a.bits.source, 2) node _T_571 = eq(_T_570, UInt<1>(0h0)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_25) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<1>(0h1)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_26) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<2>(0h2)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_27) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<2>(0h3)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_28) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_594 = shr(io.in.a.bits.source, 3) node _T_595 = eq(_T_594, UInt<3>(0h4)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_29) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_602 = or(_T_569, _T_575) node _T_603 = or(_T_602, _T_581) node _T_604 = or(_T_603, _T_587) node _T_605 = or(_T_604, _T_593) node _T_606 = or(_T_605, _T_599) node _T_607 = or(_T_606, _T_600) node _T_608 = or(_T_607, _T_601) node _T_609 = and(_T_568, _T_608) node _T_610 = or(UInt<1>(0h0), _T_609) node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_T_610, UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_610, UInt<1>(0h1), "") : assert_19 node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<17>(0h10000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<18>(0h2f000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<17>(0h10000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<13>(0h1000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = or(_T_632, _T_637) node _T_664 = or(_T_663, _T_642) node _T_665 = or(_T_664, _T_647) node _T_666 = or(_T_665, _T_652) node _T_667 = or(_T_666, _T_657) node _T_668 = or(_T_667, _T_662) node _T_669 = and(_T_627, _T_668) node _T_670 = or(UInt<1>(0h0), _T_623) node _T_671 = or(_T_670, _T_669) node _T_672 = asUInt(reset) node _T_673 = eq(_T_672, UInt<1>(0h0)) when _T_673 : node _T_674 = eq(_T_671, UInt<1>(0h0)) when _T_674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_671, UInt<1>(0h1), "") : assert_20 node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(source_ok, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(is_aligned, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_681 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_681, UInt<1>(0h1), "") : assert_23 node _T_685 = eq(io.in.a.bits.mask, mask) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_685, UInt<1>(0h1), "") : assert_24 node _T_689 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_689, UInt<1>(0h1), "") : assert_25 node _T_693 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_693 : node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<1>(0h0)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_30) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<1>(0h1)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_31) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_710 = shr(io.in.a.bits.source, 2) node _T_711 = eq(_T_710, UInt<2>(0h2)) node _T_712 = leq(UInt<1>(0h0), uncommonBits_32) node _T_713 = and(_T_711, _T_712) node _T_714 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_715 = and(_T_713, _T_714) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_716 = shr(io.in.a.bits.source, 2) node _T_717 = eq(_T_716, UInt<2>(0h3)) node _T_718 = leq(UInt<1>(0h0), uncommonBits_33) node _T_719 = and(_T_717, _T_718) node _T_720 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_722 = shr(io.in.a.bits.source, 3) node _T_723 = eq(_T_722, UInt<3>(0h4)) node _T_724 = leq(UInt<1>(0h0), uncommonBits_34) node _T_725 = and(_T_723, _T_724) node _T_726 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_727 = and(_T_725, _T_726) node _T_728 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_729 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_730 = or(_T_697, _T_703) node _T_731 = or(_T_730, _T_709) node _T_732 = or(_T_731, _T_715) node _T_733 = or(_T_732, _T_721) node _T_734 = or(_T_733, _T_727) node _T_735 = or(_T_734, _T_728) node _T_736 = or(_T_735, _T_729) node _T_737 = and(_T_696, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_740 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_741 = and(_T_739, _T_740) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = and(_T_742, _T_747) node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_751 = and(_T_749, _T_750) node _T_752 = or(UInt<1>(0h0), _T_751) node _T_753 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<14>(0h2000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<18>(0h2f000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<17>(0h10000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<13>(0h1000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<27>(0h4000000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = or(_T_757, _T_762) node _T_784 = or(_T_783, _T_767) node _T_785 = or(_T_784, _T_772) node _T_786 = or(_T_785, _T_777) node _T_787 = or(_T_786, _T_782) node _T_788 = and(_T_752, _T_787) node _T_789 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_790 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = and(_T_789, _T_794) node _T_796 = or(UInt<1>(0h0), _T_748) node _T_797 = or(_T_796, _T_788) node _T_798 = or(_T_797, _T_795) node _T_799 = and(_T_738, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_799, UInt<1>(0h1), "") : assert_26 node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(source_ok, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(is_aligned, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_809 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_809, UInt<1>(0h1), "") : assert_29 node _T_813 = eq(io.in.a.bits.mask, mask) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_813, UInt<1>(0h1), "") : assert_30 node _T_817 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_817 : node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<1>(0h0)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_35) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<1>(0h1)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_36) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_834 = shr(io.in.a.bits.source, 2) node _T_835 = eq(_T_834, UInt<2>(0h2)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_37) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_840 = shr(io.in.a.bits.source, 2) node _T_841 = eq(_T_840, UInt<2>(0h3)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_38) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_845 = and(_T_843, _T_844) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_846 = shr(io.in.a.bits.source, 3) node _T_847 = eq(_T_846, UInt<3>(0h4)) node _T_848 = leq(UInt<1>(0h0), uncommonBits_39) node _T_849 = and(_T_847, _T_848) node _T_850 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_854 = or(_T_821, _T_827) node _T_855 = or(_T_854, _T_833) node _T_856 = or(_T_855, _T_839) node _T_857 = or(_T_856, _T_845) node _T_858 = or(_T_857, _T_851) node _T_859 = or(_T_858, _T_852) node _T_860 = or(_T_859, _T_853) node _T_861 = and(_T_820, _T_860) node _T_862 = or(UInt<1>(0h0), _T_861) node _T_863 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_864 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_865 = and(_T_863, _T_864) node _T_866 = or(UInt<1>(0h0), _T_865) node _T_867 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<13>(0h1000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = and(_T_866, _T_871) node _T_873 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_874 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_875 = and(_T_873, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<14>(0h2000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<18>(0h2f000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<17>(0h10000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<27>(0h4000000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = or(_T_881, _T_886) node _T_908 = or(_T_907, _T_891) node _T_909 = or(_T_908, _T_896) node _T_910 = or(_T_909, _T_901) node _T_911 = or(_T_910, _T_906) node _T_912 = and(_T_876, _T_911) node _T_913 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_914 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = and(_T_913, _T_918) node _T_920 = or(UInt<1>(0h0), _T_872) node _T_921 = or(_T_920, _T_912) node _T_922 = or(_T_921, _T_919) node _T_923 = and(_T_862, _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_923, UInt<1>(0h1), "") : assert_31 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(source_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(is_aligned, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_933 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_933, UInt<1>(0h1), "") : assert_34 node _T_937 = not(mask) node _T_938 = and(io.in.a.bits.mask, _T_937) node _T_939 = eq(_T_938, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_939, UInt<1>(0h1), "") : assert_35 node _T_943 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_943 : node _T_944 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_945 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_946 = and(_T_944, _T_945) node _T_947 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h0)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_40) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<1>(0h1)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_41) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h2)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_42) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<2>(0h3)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_43) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_972 = shr(io.in.a.bits.source, 3) node _T_973 = eq(_T_972, UInt<3>(0h4)) node _T_974 = leq(UInt<1>(0h0), uncommonBits_44) node _T_975 = and(_T_973, _T_974) node _T_976 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_977 = and(_T_975, _T_976) node _T_978 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_979 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_980 = or(_T_947, _T_953) node _T_981 = or(_T_980, _T_959) node _T_982 = or(_T_981, _T_965) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_977) node _T_985 = or(_T_984, _T_978) node _T_986 = or(_T_985, _T_979) node _T_987 = and(_T_946, _T_986) node _T_988 = or(UInt<1>(0h0), _T_987) node _T_989 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_990 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _T_992 = or(UInt<1>(0h0), _T_991) node _T_993 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<14>(0h2000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<18>(0h2f000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<17>(0h10000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<27>(0h4000000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<13>(0h1000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_997, _T_1002) node _T_1029 = or(_T_1028, _T_1007) node _T_1030 = or(_T_1029, _T_1012) node _T_1031 = or(_T_1030, _T_1017) node _T_1032 = or(_T_1031, _T_1022) node _T_1033 = or(_T_1032, _T_1027) node _T_1034 = and(_T_992, _T_1033) node _T_1035 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1036 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1037 = cvt(_T_1036) node _T_1038 = and(_T_1037, asSInt(UInt<17>(0h10000))) node _T_1039 = asSInt(_T_1038) node _T_1040 = eq(_T_1039, asSInt(UInt<1>(0h0))) node _T_1041 = and(_T_1035, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1034) node _T_1043 = or(_T_1042, _T_1041) node _T_1044 = and(_T_988, _T_1043) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_36 node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(source_ok, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(is_aligned, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1054 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_39 node _T_1058 = eq(io.in.a.bits.mask, mask) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_40 node _T_1062 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1062 : node _T_1063 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1064 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1067 = shr(io.in.a.bits.source, 2) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1072 = and(_T_1070, _T_1071) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1073 = shr(io.in.a.bits.source, 2) node _T_1074 = eq(_T_1073, UInt<1>(0h1)) node _T_1075 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1076 = and(_T_1074, _T_1075) node _T_1077 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<2>(0h2)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<2>(0h3)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_1091 = shr(io.in.a.bits.source, 3) node _T_1092 = eq(_T_1091, UInt<3>(0h4)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1099 = or(_T_1066, _T_1072) node _T_1100 = or(_T_1099, _T_1078) node _T_1101 = or(_T_1100, _T_1084) node _T_1102 = or(_T_1101, _T_1090) node _T_1103 = or(_T_1102, _T_1096) node _T_1104 = or(_T_1103, _T_1097) node _T_1105 = or(_T_1104, _T_1098) node _T_1106 = and(_T_1065, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1109 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = or(UInt<1>(0h0), _T_1110) node _T_1112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<14>(0h2000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<13>(0h1000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<18>(0h2f000))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<17>(0h10000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<13>(0h1000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<27>(0h4000000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<13>(0h1000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = or(_T_1116, _T_1121) node _T_1148 = or(_T_1147, _T_1126) node _T_1149 = or(_T_1148, _T_1131) node _T_1150 = or(_T_1149, _T_1136) node _T_1151 = or(_T_1150, _T_1141) node _T_1152 = or(_T_1151, _T_1146) node _T_1153 = and(_T_1111, _T_1152) node _T_1154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1155 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = and(_T_1154, _T_1159) node _T_1161 = or(UInt<1>(0h0), _T_1153) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = and(_T_1107, _T_1162) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_41 node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(source_ok, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(is_aligned, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1173 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_44 node _T_1177 = eq(io.in.a.bits.mask, mask) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_45 node _T_1181 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1181 : node _T_1182 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1183 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1184 = and(_T_1182, _T_1183) node _T_1185 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1186 = shr(io.in.a.bits.source, 2) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) node _T_1188 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1189 = and(_T_1187, _T_1188) node _T_1190 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1191 = and(_T_1189, _T_1190) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1192 = shr(io.in.a.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h1)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1197 = and(_T_1195, _T_1196) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1198 = shr(io.in.a.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1204 = shr(io.in.a.bits.source, 2) node _T_1205 = eq(_T_1204, UInt<2>(0h3)) node _T_1206 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1209 = and(_T_1207, _T_1208) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_1210 = shr(io.in.a.bits.source, 3) node _T_1211 = eq(_T_1210, UInt<3>(0h4)) node _T_1212 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1218 = or(_T_1185, _T_1191) node _T_1219 = or(_T_1218, _T_1197) node _T_1220 = or(_T_1219, _T_1203) node _T_1221 = or(_T_1220, _T_1209) node _T_1222 = or(_T_1221, _T_1215) node _T_1223 = or(_T_1222, _T_1216) node _T_1224 = or(_T_1223, _T_1217) node _T_1225 = and(_T_1184, _T_1224) node _T_1226 = or(UInt<1>(0h0), _T_1225) node _T_1227 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1228 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1229 = and(_T_1227, _T_1228) node _T_1230 = or(UInt<1>(0h0), _T_1229) node _T_1231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1232 = cvt(_T_1231) node _T_1233 = and(_T_1232, asSInt(UInt<13>(0h1000))) node _T_1234 = asSInt(_T_1233) node _T_1235 = eq(_T_1234, asSInt(UInt<1>(0h0))) node _T_1236 = and(_T_1230, _T_1235) node _T_1237 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1238 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<14>(0h2000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<27>(0h4000000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<13>(0h1000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = or(_T_1242, _T_1247) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1257) node _T_1276 = or(_T_1275, _T_1262) node _T_1277 = or(_T_1276, _T_1267) node _T_1278 = or(_T_1277, _T_1272) node _T_1279 = and(_T_1237, _T_1278) node _T_1280 = or(UInt<1>(0h0), _T_1236) node _T_1281 = or(_T_1280, _T_1279) node _T_1282 = and(_T_1226, _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_46 node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(source_ok, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(is_aligned, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1292 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_49 node _T_1296 = eq(io.in.a.bits.mask, mask) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_50 node _T_1300 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1304 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h28)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1308 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1312 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_54 node _T_1316 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_55 node _T_1320 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_56 node _T_1324 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_57 node _T_1328 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1328 : node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(source_ok_1, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(sink_ok, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1335 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_60 node _T_1339 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_61 node _T_1343 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_62 node _T_1347 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_63 node _T_1351 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1352 = or(UInt<1>(0h1), _T_1351) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_64 node _T_1356 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1356 : node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok_1, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(sink_ok, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1363 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_67 node _T_1367 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_68 node _T_1371 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_69 node _T_1375 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1376 = or(_T_1375, io.in.d.bits.corrupt) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_70 node _T_1380 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1381 = or(UInt<1>(0h1), _T_1380) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_71 node _T_1385 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1385 : node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(source_ok_1, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1389 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_73 node _T_1393 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_74 node _T_1397 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1398 = or(UInt<1>(0h1), _T_1397) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_75 node _T_1402 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1402 : node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok_1, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1406 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_77 node _T_1410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1411 = or(_T_1410, io.in.d.bits.corrupt) node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(_T_1411, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1411, UInt<1>(0h1), "") : assert_78 node _T_1415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1416 = or(UInt<1>(0h1), _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_79 node _T_1420 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1420 : node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(source_ok_1, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1425 = asUInt(reset) node _T_1426 = eq(_T_1425, UInt<1>(0h0)) when _T_1426 : node _T_1427 = eq(_T_1424, UInt<1>(0h0)) when _T_1427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1424, UInt<1>(0h1), "") : assert_81 node _T_1428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_82 node _T_1432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1433 = or(UInt<1>(0h1), _T_1432) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1437 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1441 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1445 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1449 = eq(a_first, UInt<1>(0h0)) node _T_1450 = and(io.in.a.valid, _T_1449) when _T_1450 : node _T_1451 = eq(io.in.a.bits.opcode, opcode) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_87 node _T_1455 = eq(io.in.a.bits.param, param) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_88 node _T_1459 = eq(io.in.a.bits.size, size) node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(_T_1459, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1459, UInt<1>(0h1), "") : assert_89 node _T_1463 = eq(io.in.a.bits.source, source) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_90 node _T_1467 = eq(io.in.a.bits.address, address) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_91 node _T_1471 = and(io.in.a.ready, io.in.a.valid) node _T_1472 = and(_T_1471, a_first) when _T_1472 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1473 = eq(d_first, UInt<1>(0h0)) node _T_1474 = and(io.in.d.valid, _T_1473) when _T_1474 : node _T_1475 = eq(io.in.d.bits.opcode, opcode_1) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_92 node _T_1479 = eq(io.in.d.bits.param, param_1) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_93 node _T_1483 = eq(io.in.d.bits.size, size_1) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_94 node _T_1487 = eq(io.in.d.bits.source, source_1) node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(_T_1487, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1487, UInt<1>(0h1), "") : assert_95 node _T_1491 = eq(io.in.d.bits.sink, sink) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_96 node _T_1495 = eq(io.in.d.bits.denied, denied) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_97 node _T_1499 = and(io.in.d.ready, io.in.d.valid) node _T_1500 = and(_T_1499, d_first) when _T_1500 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<41>, clock, reset, UInt<41>(0h0) regreset inflight_opcodes : UInt<164>, clock, reset, UInt<164>(0h0) regreset inflight_sizes : UInt<328>, clock, reset, UInt<328>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<41> connect a_set, UInt<41>(0h0) wire a_set_wo_ready : UInt<41> connect a_set_wo_ready, UInt<41>(0h0) wire a_opcodes_set : UInt<164> connect a_opcodes_set, UInt<164>(0h0) wire a_sizes_set : UInt<328> connect a_sizes_set, UInt<328>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1501 = and(io.in.a.valid, a_first_1) node _T_1502 = and(_T_1501, UInt<1>(0h1)) when _T_1502 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1503 = and(io.in.a.ready, io.in.a.valid) node _T_1504 = and(_T_1503, a_first_1) node _T_1505 = and(_T_1504, UInt<1>(0h1)) when _T_1505 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1506 = dshr(inflight, io.in.a.bits.source) node _T_1507 = bits(_T_1506, 0, 0) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<41> connect d_clr, UInt<41>(0h0) wire d_clr_wo_ready : UInt<41> connect d_clr_wo_ready, UInt<41>(0h0) wire d_opcodes_clr : UInt<164> connect d_opcodes_clr, UInt<164>(0h0) wire d_sizes_clr : UInt<328> connect d_sizes_clr, UInt<328>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1512 = and(io.in.d.valid, d_first_1) node _T_1513 = and(_T_1512, UInt<1>(0h1)) node _T_1514 = eq(d_release_ack, UInt<1>(0h0)) node _T_1515 = and(_T_1513, _T_1514) when _T_1515 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1516 = and(io.in.d.ready, io.in.d.valid) node _T_1517 = and(_T_1516, d_first_1) node _T_1518 = and(_T_1517, UInt<1>(0h1)) node _T_1519 = eq(d_release_ack, UInt<1>(0h0)) node _T_1520 = and(_T_1518, _T_1519) when _T_1520 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1521 = and(io.in.d.valid, d_first_1) node _T_1522 = and(_T_1521, UInt<1>(0h1)) node _T_1523 = eq(d_release_ack, UInt<1>(0h0)) node _T_1524 = and(_T_1522, _T_1523) when _T_1524 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1525 = dshr(inflight, io.in.d.bits.source) node _T_1526 = bits(_T_1525, 0, 0) node _T_1527 = or(_T_1526, same_cycle_resp) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1531 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1532 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1533 = or(_T_1531, _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_100 node _T_1537 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_101 else : node _T_1541 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1542 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1543 = or(_T_1541, _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_102 node _T_1547 = eq(io.in.d.bits.size, a_size_lookup) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_103 node _T_1551 = and(io.in.d.valid, d_first_1) node _T_1552 = and(_T_1551, a_first_1) node _T_1553 = and(_T_1552, io.in.a.valid) node _T_1554 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = eq(d_release_ack, UInt<1>(0h0)) node _T_1557 = and(_T_1555, _T_1556) when _T_1557 : node _T_1558 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1559 = or(_T_1558, io.in.a.ready) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_104 node _T_1563 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1564 = orr(a_set_wo_ready) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = or(_T_1563, _T_1565) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1570 = orr(inflight) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) node _T_1572 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1573 = or(_T_1571, _T_1572) node _T_1574 = lt(watchdog, plusarg_reader.out) node _T_1575 = or(_T_1573, _T_1574) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1579 = and(io.in.a.ready, io.in.a.valid) node _T_1580 = and(io.in.d.ready, io.in.d.valid) node _T_1581 = or(_T_1579, _T_1580) when _T_1581 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<41>, clock, reset, UInt<41>(0h0) regreset inflight_opcodes_1 : UInt<164>, clock, reset, UInt<164>(0h0) regreset inflight_sizes_1 : UInt<328>, clock, reset, UInt<328>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<41> connect c_set, UInt<41>(0h0) wire c_set_wo_ready : UInt<41> connect c_set_wo_ready, UInt<41>(0h0) wire c_opcodes_set : UInt<164> connect c_opcodes_set, UInt<164>(0h0) wire c_sizes_set : UInt<328> connect c_sizes_set, UInt<328>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1582 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1583 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1584 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = and(_T_1582, _T_1585) when _T_1586 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1587 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1588 = and(_T_1587, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1589 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1590 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = and(_T_1588, _T_1591) when _T_1592 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1593 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1594 = bits(_T_1593, 0, 0) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<41> connect d_clr_1, UInt<41>(0h0) wire d_clr_wo_ready_1 : UInt<41> connect d_clr_wo_ready_1, UInt<41>(0h0) wire d_opcodes_clr_1 : UInt<164> connect d_opcodes_clr_1, UInt<164>(0h0) wire d_sizes_clr_1 : UInt<328> connect d_sizes_clr_1, UInt<328>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1599 = and(io.in.d.valid, d_first_2) node _T_1600 = and(_T_1599, UInt<1>(0h1)) node _T_1601 = and(_T_1600, d_release_ack_1) when _T_1601 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1602 = and(io.in.d.ready, io.in.d.valid) node _T_1603 = and(_T_1602, d_first_2) node _T_1604 = and(_T_1603, UInt<1>(0h1)) node _T_1605 = and(_T_1604, d_release_ack_1) when _T_1605 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1606 = and(io.in.d.valid, d_first_2) node _T_1607 = and(_T_1606, UInt<1>(0h1)) node _T_1608 = and(_T_1607, d_release_ack_1) when _T_1608 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1609 = dshr(inflight_1, io.in.d.bits.source) node _T_1610 = bits(_T_1609, 0, 0) node _T_1611 = or(_T_1610, same_cycle_resp_1) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1615 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_109 else : node _T_1619 = eq(io.in.d.bits.size, c_size_lookup) node _T_1620 = asUInt(reset) node _T_1621 = eq(_T_1620, UInt<1>(0h0)) when _T_1621 : node _T_1622 = eq(_T_1619, UInt<1>(0h0)) when _T_1622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1619, UInt<1>(0h1), "") : assert_110 node _T_1623 = and(io.in.d.valid, d_first_2) node _T_1624 = and(_T_1623, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1625 = and(_T_1624, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1626 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1627 = and(_T_1625, _T_1626) node _T_1628 = and(_T_1627, d_release_ack_1) node _T_1629 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1630 = and(_T_1628, _T_1629) when _T_1630 : node _T_1631 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<6>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1632 = or(_T_1631, _WIRE_27.ready) node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(_T_1632, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1632, UInt<1>(0h1), "") : assert_111 node _T_1636 = orr(c_set_wo_ready) when _T_1636 : node _T_1637 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1641 = orr(inflight_1) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) node _T_1643 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1644 = or(_T_1642, _T_1643) node _T_1645 = lt(watchdog_1, plusarg_reader_1.out) node _T_1646 = or(_T_1644, _T_1645) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1650 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1651 = and(io.in.d.ready, io.in.d.valid) node _T_1652 = or(_T_1650, _T_1651) when _T_1652 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [327:0] c_sizes_set = 328'h0; // @[Monitor.scala:741:34] wire [163:0] c_opcodes_set = 164'h0; // @[Monitor.scala:740:34] wire [40:0] c_set = 41'h0; // @[Monitor.scala:738:34] wire [40:0] c_set_wo_ready = 41'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = \|(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 \| _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_69 = _source_ok_T_67 & _source_ok_T_68; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1579 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1579; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1579; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1652 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1652; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [40:0] inflight; // @[Monitor.scala:614:27] reg [163:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [327:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [40:0] a_set; // @[Monitor.scala:626:34] wire [40:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [163:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [327:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [163:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [163:0] _a_opcode_lookup_T_6 = {160'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [163:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [327:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [327:0] _a_size_lookup_T_6 = {320'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [327:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[327:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1505 = _T_1579 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1505 ? _a_set_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1505 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1505 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1505 ? _a_opcodes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1505 ? _a_sizes_set_T_1[327:0] : 328'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [40:0] d_clr; // @[Monitor.scala:664:34] wire [40:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [163:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [327:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1551 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1551 & ~d_release_ack ? _d_clr_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1520 = _T_1652 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1520 ? _d_clr_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1520 ? _d_opcodes_clr_T_5[163:0] : 164'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1520 ? _d_sizes_clr_T_5[327:0] : 328'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [40:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [40:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [40:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [163:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [163:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [163:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [327:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [327:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [327:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [40:0] inflight_1; // @[Monitor.scala:726:35] wire [40:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [163:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [163:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [327:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [327:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [163:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [163:0] _c_opcode_lookup_T_6 = {160'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [163:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [327:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [327:0] _c_size_lookup_T_6 = {320'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [327:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[327:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [40:0] d_clr_1; // @[Monitor.scala:774:34] wire [40:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [163:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [327:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1623 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1623 & d_release_ack_1 ? _d_clr_wo_ready_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1605 = _T_1652 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1605 ? _d_clr_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1605 ? _d_opcodes_clr_T_11[163:0] : 164'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1605 ? _d_sizes_clr_T_11[327:0] : 328'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [40:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [40:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [163:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [163:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [327:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [327:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AccPipe_5 : input clock : Clock input reset : Reset output io : { flip op1 : SInt<32>, flip op2 : SInt<32>, sum : SInt<32>} node _io_sum_T = add(io.op1, io.op2) node _io_sum_T_1 = tail(_io_sum_T, 1) node _io_sum_T_2 = asSInt(_io_sum_T_1) reg io_sum_r : SInt<32>, clock when UInt<1>(0h1) : connect io_sum_r, _io_sum_T_2 connect io.sum, io_sum_r	module AccPipe_5( // @[AccumulatorMem.scala:63:7] input clock, // @[AccumulatorMem.scala:63:7] input reset, // @[AccumulatorMem.scala:63:7] input [31:0] io_op1, // @[AccumulatorMem.scala:64:14] input [31:0] io_op2, // @[AccumulatorMem.scala:64:14] output [31:0] io_sum // @[AccumulatorMem.scala:64:14] ); wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7] wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7] wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7] wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38] reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26] assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26] always @(posedge clock) // @[AccumulatorMem.scala:63:7] io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38] assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<17>(0h10000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<17>(0h10000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<17>(0h10000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1294 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<17>(0h10000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = and(_T_1293, _T_1298) node _T_1300 = or(UInt<1>(0h0), _T_1299) node _T_1301 = and(_T_1292, _T_1300) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_26 node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(source_ok, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(is_aligned, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_29 node _T_1315 = eq(io.in.a.bits.mask, mask) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_30 node _T_1319 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1324 = shr(io.in.a.bits.source, 2) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) node _T_1326 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1329 = and(_T_1327, _T_1328) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1330 = shr(io.in.a.bits.source, 2) node _T_1331 = eq(_T_1330, UInt<1>(0h1)) node _T_1332 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1335 = and(_T_1333, _T_1334) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1336 = shr(io.in.a.bits.source, 2) node _T_1337 = eq(_T_1336, UInt<2>(0h2)) node _T_1338 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1341 = and(_T_1339, _T_1340) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1342 = shr(io.in.a.bits.source, 2) node _T_1343 = eq(_T_1342, UInt<2>(0h3)) node _T_1344 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1345 = and(_T_1343, _T_1344) node _T_1346 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1349 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1350 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1360 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1361 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1362 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1384 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1385 = or(_T_1323, _T_1329) node _T_1386 = or(_T_1385, _T_1335) node _T_1387 = or(_T_1386, _T_1341) node _T_1388 = or(_T_1387, _T_1347) node _T_1389 = or(_T_1388, _T_1348) node _T_1390 = or(_T_1389, _T_1349) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = and(_T_1322, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1429 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<17>(0h10000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = and(_T_1428, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = and(_T_1427, _T_1435) node _T_1437 = asUInt(reset) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : node _T_1439 = eq(_T_1436, UInt<1>(0h0)) when _T_1439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1436, UInt<1>(0h1), "") : assert_31 node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(source_ok, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(is_aligned, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1446 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_34 node _T_1450 = not(mask) node _T_1451 = and(io.in.a.bits.mask, _T_1450) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_35 node _T_1456 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1456 : node _T_1457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1461 = shr(io.in.a.bits.source, 2) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) node _T_1463 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1466 = and(_T_1464, _T_1465) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h1)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<2>(0h2)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h3)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _T_1485 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1486 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1487 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1488 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1489 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1490 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1521 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1522 = or(_T_1460, _T_1466) node _T_1523 = or(_T_1522, _T_1472) node _T_1524 = or(_T_1523, _T_1478) node _T_1525 = or(_T_1524, _T_1484) node _T_1526 = or(_T_1525, _T_1485) node _T_1527 = or(_T_1526, _T_1486) node _T_1528 = or(_T_1527, _T_1487) node _T_1529 = or(_T_1528, _T_1488) node _T_1530 = or(_T_1529, _T_1489) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = and(_T_1459, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1566 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1567 = cvt(_T_1566) node _T_1568 = and(_T_1567, asSInt(UInt<17>(0h10000))) node _T_1569 = asSInt(_T_1568) node _T_1570 = eq(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = and(_T_1565, _T_1570) node _T_1572 = or(UInt<1>(0h0), _T_1571) node _T_1573 = and(_T_1564, _T_1572) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_36 node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(source_ok, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(is_aligned, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1583 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(_T_1583, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1583, UInt<1>(0h1), "") : assert_39 node _T_1587 = eq(io.in.a.bits.mask, mask) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_40 node _T_1591 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1591 : node _T_1592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1594 = and(_T_1592, _T_1593) node _T_1595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1596 = shr(io.in.a.bits.source, 2) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) node _T_1598 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1601 = and(_T_1599, _T_1600) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h1)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<2>(0h2)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h3)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _T_1620 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1621 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1622 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1623 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1624 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1625 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1632 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1633 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1634 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1635 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1636 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1637 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1656 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1657 = or(_T_1595, _T_1601) node _T_1658 = or(_T_1657, _T_1607) node _T_1659 = or(_T_1658, _T_1613) node _T_1660 = or(_T_1659, _T_1619) node _T_1661 = or(_T_1660, _T_1620) node _T_1662 = or(_T_1661, _T_1621) node _T_1663 = or(_T_1662, _T_1622) node _T_1664 = or(_T_1663, _T_1623) node _T_1665 = or(_T_1664, _T_1624) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = and(_T_1594, _T_1697) node _T_1699 = or(UInt<1>(0h0), _T_1698) node _T_1700 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1701 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1702 = cvt(_T_1701) node _T_1703 = and(_T_1702, asSInt(UInt<17>(0h10000))) node _T_1704 = asSInt(_T_1703) node _T_1705 = eq(_T_1704, asSInt(UInt<1>(0h0))) node _T_1706 = and(_T_1700, _T_1705) node _T_1707 = or(UInt<1>(0h0), _T_1706) node _T_1708 = and(_T_1699, _T_1707) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_41 node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(source_ok, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(is_aligned, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1718 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_44 node _T_1722 = eq(io.in.a.bits.mask, mask) node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(_T_1722, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1722, UInt<1>(0h1), "") : assert_45 node _T_1726 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1726 : node _T_1727 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1728 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1729 = and(_T_1727, _T_1728) node _T_1730 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1731 = shr(io.in.a.bits.source, 2) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) node _T_1733 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1734 = and(_T_1732, _T_1733) node _T_1735 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1736 = and(_T_1734, _T_1735) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h1)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<2>(0h2)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h3)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _T_1755 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1756 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1757 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1758 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1759 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1760 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1767 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1768 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1769 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1770 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1771 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1772 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1791 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1792 = or(_T_1730, _T_1736) node _T_1793 = or(_T_1792, _T_1742) node _T_1794 = or(_T_1793, _T_1748) node _T_1795 = or(_T_1794, _T_1754) node _T_1796 = or(_T_1795, _T_1755) node _T_1797 = or(_T_1796, _T_1756) node _T_1798 = or(_T_1797, _T_1757) node _T_1799 = or(_T_1798, _T_1758) node _T_1800 = or(_T_1799, _T_1759) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = and(_T_1729, _T_1832) node _T_1834 = or(UInt<1>(0h0), _T_1833) node _T_1835 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1836 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1837 = cvt(_T_1836) node _T_1838 = and(_T_1837, asSInt(UInt<17>(0h10000))) node _T_1839 = asSInt(_T_1838) node _T_1840 = eq(_T_1839, asSInt(UInt<1>(0h0))) node _T_1841 = and(_T_1835, _T_1840) node _T_1842 = or(UInt<1>(0h0), _T_1841) node _T_1843 = and(_T_1834, _T_1842) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_46 node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(source_ok, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(is_aligned, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1853 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_49 node _T_1857 = eq(io.in.a.bits.mask, mask) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_50 node _T_1861 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1865 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1869 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1869 : node _T_1870 = asUInt(reset) node _T_1871 = eq(_T_1870, UInt<1>(0h0)) when _T_1871 : node _T_1872 = eq(source_ok_1, UInt<1>(0h0)) when _T_1872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1873 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(_T_1873, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1873, UInt<1>(0h1), "") : assert_54 node _T_1877 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_55 node _T_1881 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1882 = asUInt(reset) node _T_1883 = eq(_T_1882, UInt<1>(0h0)) when _T_1883 : node _T_1884 = eq(_T_1881, UInt<1>(0h0)) when _T_1884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1881, UInt<1>(0h1), "") : assert_56 node _T_1885 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1886 = asUInt(reset) node _T_1887 = eq(_T_1886, UInt<1>(0h0)) when _T_1887 : node _T_1888 = eq(_T_1885, UInt<1>(0h0)) when _T_1888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1885, UInt<1>(0h1), "") : assert_57 node _T_1889 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1889 : node _T_1890 = asUInt(reset) node _T_1891 = eq(_T_1890, UInt<1>(0h0)) when _T_1891 : node _T_1892 = eq(source_ok_1, UInt<1>(0h0)) when _T_1892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1893 = asUInt(reset) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) when _T_1894 : node _T_1895 = eq(sink_ok, UInt<1>(0h0)) when _T_1895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1896 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(_T_1896, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1896, UInt<1>(0h1), "") : assert_60 node _T_1900 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1901 = asUInt(reset) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(_T_1900, UInt<1>(0h0)) when _T_1903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1900, UInt<1>(0h1), "") : assert_61 node _T_1904 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1905 = asUInt(reset) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) when _T_1906 : node _T_1907 = eq(_T_1904, UInt<1>(0h0)) when _T_1907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1904, UInt<1>(0h1), "") : assert_62 node _T_1908 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_63 node _T_1912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1913 = or(UInt<1>(0h0), _T_1912) node _T_1914 = asUInt(reset) node _T_1915 = eq(_T_1914, UInt<1>(0h0)) when _T_1915 : node _T_1916 = eq(_T_1913, UInt<1>(0h0)) when _T_1916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1913, UInt<1>(0h1), "") : assert_64 node _T_1917 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1917 : node _T_1918 = asUInt(reset) node _T_1919 = eq(_T_1918, UInt<1>(0h0)) when _T_1919 : node _T_1920 = eq(source_ok_1, UInt<1>(0h0)) when _T_1920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1921 = asUInt(reset) node _T_1922 = eq(_T_1921, UInt<1>(0h0)) when _T_1922 : node _T_1923 = eq(sink_ok, UInt<1>(0h0)) when _T_1923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1924 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1925 = asUInt(reset) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(_T_1924, UInt<1>(0h0)) when _T_1927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1924, UInt<1>(0h1), "") : assert_67 node _T_1928 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1929 = asUInt(reset) node _T_1930 = eq(_T_1929, UInt<1>(0h0)) when _T_1930 : node _T_1931 = eq(_T_1928, UInt<1>(0h0)) when _T_1931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1928, UInt<1>(0h1), "") : assert_68 node _T_1932 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1933 = asUInt(reset) node _T_1934 = eq(_T_1933, UInt<1>(0h0)) when _T_1934 : node _T_1935 = eq(_T_1932, UInt<1>(0h0)) when _T_1935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1932, UInt<1>(0h1), "") : assert_69 node _T_1936 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1937 = or(_T_1936, io.in.d.bits.corrupt) node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(_T_1937, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1937, UInt<1>(0h1), "") : assert_70 node _T_1941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1942 = or(UInt<1>(0h0), _T_1941) node _T_1943 = asUInt(reset) node _T_1944 = eq(_T_1943, UInt<1>(0h0)) when _T_1944 : node _T_1945 = eq(_T_1942, UInt<1>(0h0)) when _T_1945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1942, UInt<1>(0h1), "") : assert_71 node _T_1946 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1946 : node _T_1947 = asUInt(reset) node _T_1948 = eq(_T_1947, UInt<1>(0h0)) when _T_1948 : node _T_1949 = eq(source_ok_1, UInt<1>(0h0)) when _T_1949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1950 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1951 = asUInt(reset) node _T_1952 = eq(_T_1951, UInt<1>(0h0)) when _T_1952 : node _T_1953 = eq(_T_1950, UInt<1>(0h0)) when _T_1953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1950, UInt<1>(0h1), "") : assert_73 node _T_1954 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_74 node _T_1958 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1959 = or(UInt<1>(0h0), _T_1958) node _T_1960 = asUInt(reset) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) when _T_1961 : node _T_1962 = eq(_T_1959, UInt<1>(0h0)) when _T_1962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1959, UInt<1>(0h1), "") : assert_75 node _T_1963 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1963 : node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(source_ok_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1967 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_77 node _T_1971 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1972 = or(_T_1971, io.in.d.bits.corrupt) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_78 node _T_1976 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1977 = or(UInt<1>(0h0), _T_1976) node _T_1978 = asUInt(reset) node _T_1979 = eq(_T_1978, UInt<1>(0h0)) when _T_1979 : node _T_1980 = eq(_T_1977, UInt<1>(0h0)) when _T_1980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1977, UInt<1>(0h1), "") : assert_79 node _T_1981 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1981 : node _T_1982 = asUInt(reset) node _T_1983 = eq(_T_1982, UInt<1>(0h0)) when _T_1983 : node _T_1984 = eq(source_ok_1, UInt<1>(0h0)) when _T_1984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1985 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1986 = asUInt(reset) node _T_1987 = eq(_T_1986, UInt<1>(0h0)) when _T_1987 : node _T_1988 = eq(_T_1985, UInt<1>(0h0)) when _T_1988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1985, UInt<1>(0h1), "") : assert_81 node _T_1989 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_82 node _T_1993 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1994 = or(UInt<1>(0h0), _T_1993) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1998 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2002 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2006 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2010 = eq(a_first, UInt<1>(0h0)) node _T_2011 = and(io.in.a.valid, _T_2010) when _T_2011 : node _T_2012 = eq(io.in.a.bits.opcode, opcode) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_87 node _T_2016 = eq(io.in.a.bits.param, param) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_88 node _T_2020 = eq(io.in.a.bits.size, size) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_89 node _T_2024 = eq(io.in.a.bits.source, source) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_90 node _T_2028 = eq(io.in.a.bits.address, address) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_91 node _T_2032 = and(io.in.a.ready, io.in.a.valid) node _T_2033 = and(_T_2032, a_first) when _T_2033 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2034 = eq(d_first, UInt<1>(0h0)) node _T_2035 = and(io.in.d.valid, _T_2034) when _T_2035 : node _T_2036 = eq(io.in.d.bits.opcode, opcode_1) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_92 node _T_2040 = eq(io.in.d.bits.param, param_1) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_93 node _T_2044 = eq(io.in.d.bits.size, size_1) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_94 node _T_2048 = eq(io.in.d.bits.source, source_1) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_95 node _T_2052 = eq(io.in.d.bits.sink, sink) node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(_T_2052, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2052, UInt<1>(0h1), "") : assert_96 node _T_2056 = eq(io.in.d.bits.denied, denied) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_97 node _T_2060 = and(io.in.d.ready, io.in.d.valid) node _T_2061 = and(_T_2060, d_first) when _T_2061 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2062 = and(io.in.a.valid, a_first_1) node _T_2063 = and(_T_2062, UInt<1>(0h1)) when _T_2063 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2064 = and(io.in.a.ready, io.in.a.valid) node _T_2065 = and(_T_2064, a_first_1) node _T_2066 = and(_T_2065, UInt<1>(0h1)) when _T_2066 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2067 = dshr(inflight, io.in.a.bits.source) node _T_2068 = bits(_T_2067, 0, 0) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2073 = and(io.in.d.valid, d_first_1) node _T_2074 = and(_T_2073, UInt<1>(0h1)) node _T_2075 = eq(d_release_ack, UInt<1>(0h0)) node _T_2076 = and(_T_2074, _T_2075) when _T_2076 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2077 = and(io.in.d.ready, io.in.d.valid) node _T_2078 = and(_T_2077, d_first_1) node _T_2079 = and(_T_2078, UInt<1>(0h1)) node _T_2080 = eq(d_release_ack, UInt<1>(0h0)) node _T_2081 = and(_T_2079, _T_2080) when _T_2081 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2082 = and(io.in.d.valid, d_first_1) node _T_2083 = and(_T_2082, UInt<1>(0h1)) node _T_2084 = eq(d_release_ack, UInt<1>(0h0)) node _T_2085 = and(_T_2083, _T_2084) when _T_2085 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2086 = dshr(inflight, io.in.d.bits.source) node _T_2087 = bits(_T_2086, 0, 0) node _T_2088 = or(_T_2087, same_cycle_resp) node _T_2089 = asUInt(reset) node _T_2090 = eq(_T_2089, UInt<1>(0h0)) when _T_2090 : node _T_2091 = eq(_T_2088, UInt<1>(0h0)) when _T_2091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2088, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2092 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2093 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2094 = or(_T_2092, _T_2093) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_100 node _T_2098 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2099 = asUInt(reset) node _T_2100 = eq(_T_2099, UInt<1>(0h0)) when _T_2100 : node _T_2101 = eq(_T_2098, UInt<1>(0h0)) when _T_2101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2098, UInt<1>(0h1), "") : assert_101 else : node _T_2102 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2103 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2104 = or(_T_2102, _T_2103) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_102 node _T_2108 = eq(io.in.d.bits.size, a_size_lookup) node _T_2109 = asUInt(reset) node _T_2110 = eq(_T_2109, UInt<1>(0h0)) when _T_2110 : node _T_2111 = eq(_T_2108, UInt<1>(0h0)) when _T_2111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2108, UInt<1>(0h1), "") : assert_103 node _T_2112 = and(io.in.d.valid, d_first_1) node _T_2113 = and(_T_2112, a_first_1) node _T_2114 = and(_T_2113, io.in.a.valid) node _T_2115 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2116 = and(_T_2114, _T_2115) node _T_2117 = eq(d_release_ack, UInt<1>(0h0)) node _T_2118 = and(_T_2116, _T_2117) when _T_2118 : node _T_2119 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2120 = or(_T_2119, io.in.a.ready) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_110 node _T_2124 = orr(inflight) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) node _T_2126 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2127 = or(_T_2125, _T_2126) node _T_2128 = lt(watchdog, plusarg_reader.out) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2133 = and(io.in.a.ready, io.in.a.valid) node _T_2134 = and(io.in.d.ready, io.in.d.valid) node _T_2135 = or(_T_2133, _T_2134) when _T_2135 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2136 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2137 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2138 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = and(_T_2136, _T_2139) when _T_2140 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2141 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2142 = and(_T_2141, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2143 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2147 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2148 = bits(_T_2147, 0, 0) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = asUInt(reset) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) when _T_2151 : node _T_2152 = eq(_T_2149, UInt<1>(0h0)) when _T_2152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2149, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2153 = and(io.in.d.valid, d_first_2) node _T_2154 = and(_T_2153, UInt<1>(0h1)) node _T_2155 = and(_T_2154, d_release_ack_1) when _T_2155 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2156 = and(io.in.d.ready, io.in.d.valid) node _T_2157 = and(_T_2156, d_first_2) node _T_2158 = and(_T_2157, UInt<1>(0h1)) node _T_2159 = and(_T_2158, d_release_ack_1) when _T_2159 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2160 = and(io.in.d.valid, d_first_2) node _T_2161 = and(_T_2160, UInt<1>(0h1)) node _T_2162 = and(_T_2161, d_release_ack_1) when _T_2162 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2163 = dshr(inflight_1, io.in.d.bits.source) node _T_2164 = bits(_T_2163, 0, 0) node _T_2165 = or(_T_2164, same_cycle_resp_1) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2169 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_108 else : node _T_2173 = eq(io.in.d.bits.size, c_size_lookup) node _T_2174 = asUInt(reset) node _T_2175 = eq(_T_2174, UInt<1>(0h0)) when _T_2175 : node _T_2176 = eq(_T_2173, UInt<1>(0h0)) when _T_2176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2173, UInt<1>(0h1), "") : assert_109 node _T_2177 = and(io.in.d.valid, d_first_2) node _T_2178 = and(_T_2177, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2179 = and(_T_2178, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2180 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2181 = and(_T_2179, _T_2180) node _T_2182 = and(_T_2181, d_release_ack_1) node _T_2183 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : node _T_2185 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2186 = or(_T_2185, _WIRE_27.ready) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_111 node _T_2190 = orr(inflight_1) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) node _T_2192 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2193 = or(_T_2191, _T_2192) node _T_2194 = lt(watchdog_1, plusarg_reader_1.out) node _T_2195 = or(_T_2193, _T_2194) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2199 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2200 = and(io.in.d.ready, io.in.d.valid) node _T_2201 = or(_T_2199, _T_2200) when _T_2201 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN = a_first_done & a_first_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_21 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_21( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ShiftQueue_7 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, count : UInt<3>, mask : UInt<5>} wire _valid_WIRE : UInt<1>[5] connect _valid_WIRE[0], UInt<1>(0h0) connect _valid_WIRE[1], UInt<1>(0h0) connect _valid_WIRE[2], UInt<1>(0h0) connect _valid_WIRE[3], UInt<1>(0h0) connect _valid_WIRE[4], UInt<1>(0h0) regreset valid : UInt<1>[5], clock, reset, _valid_WIRE reg elts : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}[5], clock node wdata = mux(valid[1], elts[1], io.enq.bits) node _wen_T = and(io.enq.ready, io.enq.valid) node _wen_T_1 = or(UInt<1>(0h0), valid[0]) node _wen_T_2 = and(_wen_T, _wen_T_1) node _wen_T_3 = or(valid[1], _wen_T_2) node _wen_T_4 = and(io.enq.ready, io.enq.valid) node _wen_T_5 = and(_wen_T_4, UInt<1>(0h1)) node _wen_T_6 = eq(valid[0], UInt<1>(0h0)) node _wen_T_7 = and(_wen_T_5, _wen_T_6) node wen = mux(io.deq.ready, _wen_T_3, _wen_T_7) when wen : connect elts[0], wdata node _valid_0_T = and(io.enq.ready, io.enq.valid) node _valid_0_T_1 = or(UInt<1>(0h0), valid[0]) node _valid_0_T_2 = and(_valid_0_T, _valid_0_T_1) node _valid_0_T_3 = or(valid[1], _valid_0_T_2) node _valid_0_T_4 = and(io.enq.ready, io.enq.valid) node _valid_0_T_5 = and(_valid_0_T_4, UInt<1>(0h1)) node _valid_0_T_6 = or(_valid_0_T_5, valid[0]) node _valid_0_T_7 = mux(io.deq.ready, _valid_0_T_3, _valid_0_T_6) connect valid[0], _valid_0_T_7 node wdata_1 = mux(valid[2], elts[2], io.enq.bits) node _wen_T_8 = and(io.enq.ready, io.enq.valid) node _wen_T_9 = or(UInt<1>(0h0), valid[1]) node _wen_T_10 = and(_wen_T_8, _wen_T_9) node _wen_T_11 = or(valid[2], _wen_T_10) node _wen_T_12 = and(io.enq.ready, io.enq.valid) node _wen_T_13 = and(_wen_T_12, valid[0]) node _wen_T_14 = eq(valid[1], UInt<1>(0h0)) node _wen_T_15 = and(_wen_T_13, _wen_T_14) node wen_1 = mux(io.deq.ready, _wen_T_11, _wen_T_15) when wen_1 : connect elts[1], wdata_1 node _valid_1_T = and(io.enq.ready, io.enq.valid) node _valid_1_T_1 = or(UInt<1>(0h0), valid[1]) node _valid_1_T_2 = and(_valid_1_T, _valid_1_T_1) node _valid_1_T_3 = or(valid[2], _valid_1_T_2) node _valid_1_T_4 = and(io.enq.ready, io.enq.valid) node _valid_1_T_5 = and(_valid_1_T_4, valid[0]) node _valid_1_T_6 = or(_valid_1_T_5, valid[1]) node _valid_1_T_7 = mux(io.deq.ready, _valid_1_T_3, _valid_1_T_6) connect valid[1], _valid_1_T_7 node wdata_2 = mux(valid[3], elts[3], io.enq.bits) node _wen_T_16 = and(io.enq.ready, io.enq.valid) node _wen_T_17 = or(UInt<1>(0h0), valid[2]) node _wen_T_18 = and(_wen_T_16, _wen_T_17) node _wen_T_19 = or(valid[3], _wen_T_18) node _wen_T_20 = and(io.enq.ready, io.enq.valid) node _wen_T_21 = and(_wen_T_20, valid[1]) node _wen_T_22 = eq(valid[2], UInt<1>(0h0)) node _wen_T_23 = and(_wen_T_21, _wen_T_22) node wen_2 = mux(io.deq.ready, _wen_T_19, _wen_T_23) when wen_2 : connect elts[2], wdata_2 node _valid_2_T = and(io.enq.ready, io.enq.valid) node _valid_2_T_1 = or(UInt<1>(0h0), valid[2]) node _valid_2_T_2 = and(_valid_2_T, _valid_2_T_1) node _valid_2_T_3 = or(valid[3], _valid_2_T_2) node _valid_2_T_4 = and(io.enq.ready, io.enq.valid) node _valid_2_T_5 = and(_valid_2_T_4, valid[1]) node _valid_2_T_6 = or(_valid_2_T_5, valid[2]) node _valid_2_T_7 = mux(io.deq.ready, _valid_2_T_3, _valid_2_T_6) connect valid[2], _valid_2_T_7 node wdata_3 = mux(valid[4], elts[4], io.enq.bits) node _wen_T_24 = and(io.enq.ready, io.enq.valid) node _wen_T_25 = or(UInt<1>(0h0), valid[3]) node _wen_T_26 = and(_wen_T_24, _wen_T_25) node _wen_T_27 = or(valid[4], _wen_T_26) node _wen_T_28 = and(io.enq.ready, io.enq.valid) node _wen_T_29 = and(_wen_T_28, valid[2]) node _wen_T_30 = eq(valid[3], UInt<1>(0h0)) node _wen_T_31 = and(_wen_T_29, _wen_T_30) node wen_3 = mux(io.deq.ready, _wen_T_27, _wen_T_31) when wen_3 : connect elts[3], wdata_3 node _valid_3_T = and(io.enq.ready, io.enq.valid) node _valid_3_T_1 = or(UInt<1>(0h0), valid[3]) node _valid_3_T_2 = and(_valid_3_T, _valid_3_T_1) node _valid_3_T_3 = or(valid[4], _valid_3_T_2) node _valid_3_T_4 = and(io.enq.ready, io.enq.valid) node _valid_3_T_5 = and(_valid_3_T_4, valid[2]) node _valid_3_T_6 = or(_valid_3_T_5, valid[3]) node _valid_3_T_7 = mux(io.deq.ready, _valid_3_T_3, _valid_3_T_6) connect valid[3], _valid_3_T_7 node _wen_T_32 = and(io.enq.ready, io.enq.valid) node _wen_T_33 = or(UInt<1>(0h0), valid[4]) node _wen_T_34 = and(_wen_T_32, _wen_T_33) node _wen_T_35 = or(UInt<1>(0h0), _wen_T_34) node _wen_T_36 = and(io.enq.ready, io.enq.valid) node _wen_T_37 = and(_wen_T_36, valid[3]) node _wen_T_38 = eq(valid[4], UInt<1>(0h0)) node _wen_T_39 = and(_wen_T_37, _wen_T_38) node wen_4 = mux(io.deq.ready, _wen_T_35, _wen_T_39) when wen_4 : connect elts[4], io.enq.bits node _valid_4_T = and(io.enq.ready, io.enq.valid) node _valid_4_T_1 = or(UInt<1>(0h0), valid[4]) node _valid_4_T_2 = and(_valid_4_T, _valid_4_T_1) node _valid_4_T_3 = or(UInt<1>(0h0), _valid_4_T_2) node _valid_4_T_4 = and(io.enq.ready, io.enq.valid) node _valid_4_T_5 = and(_valid_4_T_4, valid[3]) node _valid_4_T_6 = or(_valid_4_T_5, valid[4]) node _valid_4_T_7 = mux(io.deq.ready, _valid_4_T_3, _valid_4_T_6) connect valid[4], _valid_4_T_7 node _io_enq_ready_T = eq(valid[4], UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T connect io.deq.valid, valid[0] connect io.deq.bits, elts[0] when io.enq.valid : connect io.deq.valid, UInt<1>(0h1) node _T = eq(valid[0], UInt<1>(0h0)) when _T : connect io.deq.bits, io.enq.bits node io_mask_lo = cat(valid[1], valid[0]) node io_mask_hi_hi = cat(valid[4], valid[3]) node io_mask_hi = cat(io_mask_hi_hi, valid[2]) node _io_mask_T = cat(io_mask_hi, io_mask_lo) connect io.mask, _io_mask_T node _io_count_T = bits(io.mask, 0, 0) node _io_count_T_1 = bits(io.mask, 1, 1) node _io_count_T_2 = bits(io.mask, 2, 2) node _io_count_T_3 = bits(io.mask, 3, 3) node _io_count_T_4 = bits(io.mask, 4, 4) node _io_count_T_5 = add(_io_count_T, _io_count_T_1) node _io_count_T_6 = bits(_io_count_T_5, 1, 0) node _io_count_T_7 = add(_io_count_T_3, _io_count_T_4) node _io_count_T_8 = bits(_io_count_T_7, 1, 0) node _io_count_T_9 = add(_io_count_T_2, _io_count_T_8) node _io_count_T_10 = bits(_io_count_T_9, 1, 0) node _io_count_T_11 = add(_io_count_T_6, _io_count_T_10) node _io_count_T_12 = bits(_io_count_T_11, 2, 0) connect io.count, _io_count_T_12	module ShiftQueue_7( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [38:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [39:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [38:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [39:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [38:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [38:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [39:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 \| _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 \| _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 \| valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 \| _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 \| _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 \| valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 \| _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 \| _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 \| valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 \| _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 \| _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 \| valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 \| valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 \| valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker : input clock : Clock input reset : Reset output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready inst monitor of TLMonitor_30 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_31 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeOut, nodeIn connect x1_nodeOut, nodeIn_1	module ProbePicker( // @[ProbePicker.scala:42:9] input clock, // @[ProbePicker.scala:42:9] input reset, // @[ProbePicker.scala:42:9] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLMonitor_30 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_0_a_ready), .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (auto_out_0_d_valid), .io_in_d_bits_opcode (auto_out_0_d_bits_opcode), .io_in_d_bits_size (auto_out_0_d_bits_size), .io_in_d_bits_source (auto_out_0_d_bits_source), .io_in_d_bits_denied (auto_out_0_d_bits_denied), .io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_31 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_1_a_ready), .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (auto_out_1_d_valid), .io_in_d_bits_opcode (auto_out_1_d_bits_opcode), .io_in_d_bits_param (auto_out_1_d_bits_param), .io_in_d_bits_size (auto_out_1_d_bits_size), .io_in_d_bits_source (auto_out_1_d_bits_source), .io_in_d_bits_sink (auto_out_1_d_bits_sink), .io_in_d_bits_denied (auto_out_1_d_bits_denied), .io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt) ); // @[Nodes.scala:27:25] assign auto_in_1_a_ready = auto_out_1_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_1_d_valid = auto_out_1_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_in_0_a_ready = auto_out_0_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_0_d_valid = auto_out_0_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_a_valid = auto_in_1_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_d_ready = auto_in_1_d_ready; // @[ProbePicker.scala:42:9] assign auto_out_0_a_valid = auto_in_0_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_0_d_ready = auto_in_0_d_ready; // @[ProbePicker.scala:42:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RenameBusyTable : input clock : Clock input reset : Reset output io : { flip ren_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2], busy_resps : { prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>}[2], flip rebusy_reqs : UInt<1>[2], flip wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip child_rebusys : UInt<2>, debug : { busytable : UInt<80>}} wire wakeups_0 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG : UInt<1>, clock connect wakeups_wu_valid_REG, io.wakeups[0].valid reg wakeups_wu_valid_REG_1 : UInt, clock connect wakeups_wu_valid_REG_1, io.wakeups[0].bits.speculative_mask node _wakeups_wu_valid_T = and(wakeups_wu_valid_REG_1, io.child_rebusys) node _wakeups_wu_valid_T_1 = eq(_wakeups_wu_valid_T, UInt<1>(0h0)) node _wakeups_wu_valid_T_2 = and(wakeups_wu_valid_REG, _wakeups_wu_valid_T_1) connect wakeups_0.valid, _wakeups_wu_valid_T_2 reg wakeups_wu_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG, io.wakeups[0].bits connect wakeups_0.bits, wakeups_wu_bits_REG wire wakeups_1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_2 : UInt<1>, clock connect wakeups_wu_valid_REG_2, io.wakeups[1].valid reg wakeups_wu_valid_REG_3 : UInt, clock connect wakeups_wu_valid_REG_3, io.wakeups[1].bits.speculative_mask node _wakeups_wu_valid_T_3 = and(wakeups_wu_valid_REG_3, io.child_rebusys) node _wakeups_wu_valid_T_4 = eq(_wakeups_wu_valid_T_3, UInt<1>(0h0)) node _wakeups_wu_valid_T_5 = and(wakeups_wu_valid_REG_2, _wakeups_wu_valid_T_4) connect wakeups_1.valid, _wakeups_wu_valid_T_5 reg wakeups_wu_bits_REG_1 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_1, io.wakeups[1].bits connect wakeups_1.bits, wakeups_wu_bits_REG_1 wire wakeups_2 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_4 : UInt<1>, clock connect wakeups_wu_valid_REG_4, io.wakeups[2].valid reg wakeups_wu_valid_REG_5 : UInt, clock connect wakeups_wu_valid_REG_5, io.wakeups[2].bits.speculative_mask node _wakeups_wu_valid_T_6 = and(wakeups_wu_valid_REG_5, io.child_rebusys) node _wakeups_wu_valid_T_7 = eq(_wakeups_wu_valid_T_6, UInt<1>(0h0)) node _wakeups_wu_valid_T_8 = and(wakeups_wu_valid_REG_4, _wakeups_wu_valid_T_7) connect wakeups_2.valid, _wakeups_wu_valid_T_8 reg wakeups_wu_bits_REG_2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_2, io.wakeups[2].bits connect wakeups_2.bits, wakeups_wu_bits_REG_2 wire wakeups_3 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} reg wakeups_wu_valid_REG_6 : UInt<1>, clock connect wakeups_wu_valid_REG_6, io.wakeups[3].valid reg wakeups_wu_valid_REG_7 : UInt, clock connect wakeups_wu_valid_REG_7, io.wakeups[3].bits.speculative_mask node _wakeups_wu_valid_T_9 = and(wakeups_wu_valid_REG_7, io.child_rebusys) node _wakeups_wu_valid_T_10 = eq(_wakeups_wu_valid_T_9, UInt<1>(0h0)) node _wakeups_wu_valid_T_11 = and(wakeups_wu_valid_REG_6, _wakeups_wu_valid_T_10) connect wakeups_3.valid, _wakeups_wu_valid_T_11 reg wakeups_wu_bits_REG_3 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}, clock connect wakeups_wu_bits_REG_3, io.wakeups[3].bits connect wakeups_3.bits, wakeups_wu_bits_REG_3 regreset busy_table : UInt<80>, clock, reset, UInt<80>(0h0) node _busy_table_wb_T = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_wb_T_1 = eq(wakeups_0.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_2 = and(wakeups_0.valid, _busy_table_wb_T_1) node _busy_table_wb_T_3 = mux(_busy_table_wb_T_2, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_4 = and(_busy_table_wb_T, _busy_table_wb_T_3) node _busy_table_wb_T_5 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_wb_T_6 = eq(wakeups_1.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_7 = and(wakeups_1.valid, _busy_table_wb_T_6) node _busy_table_wb_T_8 = mux(_busy_table_wb_T_7, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_9 = and(_busy_table_wb_T_5, _busy_table_wb_T_8) node _busy_table_wb_T_10 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst) node _busy_table_wb_T_11 = eq(wakeups_2.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_12 = and(wakeups_2.valid, _busy_table_wb_T_11) node _busy_table_wb_T_13 = mux(_busy_table_wb_T_12, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_14 = and(_busy_table_wb_T_10, _busy_table_wb_T_13) node _busy_table_wb_T_15 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst) node _busy_table_wb_T_16 = eq(wakeups_3.bits.rebusy, UInt<1>(0h0)) node _busy_table_wb_T_17 = and(wakeups_3.valid, _busy_table_wb_T_16) node _busy_table_wb_T_18 = mux(_busy_table_wb_T_17, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_wb_T_19 = and(_busy_table_wb_T_15, _busy_table_wb_T_18) node _busy_table_wb_T_20 = or(_busy_table_wb_T_4, _busy_table_wb_T_9) node _busy_table_wb_T_21 = or(_busy_table_wb_T_20, _busy_table_wb_T_14) node _busy_table_wb_T_22 = or(_busy_table_wb_T_21, _busy_table_wb_T_19) node _busy_table_wb_T_23 = not(_busy_table_wb_T_22) node busy_table_wb = and(busy_table, _busy_table_wb_T_23) node _busy_table_next_T = dshl(UInt<1>(0h1), io.ren_uops[0].pdst) node _busy_table_next_T_1 = mux(io.rebusy_reqs[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_2 = and(_busy_table_next_T, _busy_table_next_T_1) node _busy_table_next_T_3 = dshl(UInt<1>(0h1), io.ren_uops[1].pdst) node _busy_table_next_T_4 = mux(io.rebusy_reqs[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_5 = and(_busy_table_next_T_3, _busy_table_next_T_4) node _busy_table_next_T_6 = or(_busy_table_next_T_2, _busy_table_next_T_5) node _busy_table_next_T_7 = or(busy_table_wb, _busy_table_next_T_6) node _busy_table_next_T_8 = dshl(UInt<1>(0h1), wakeups_0.bits.uop.pdst) node _busy_table_next_T_9 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _busy_table_next_T_10 = mux(_busy_table_next_T_9, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_11 = and(_busy_table_next_T_8, _busy_table_next_T_10) node _busy_table_next_T_12 = dshl(UInt<1>(0h1), wakeups_1.bits.uop.pdst) node _busy_table_next_T_13 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _busy_table_next_T_14 = mux(_busy_table_next_T_13, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_15 = and(_busy_table_next_T_12, _busy_table_next_T_14) node _busy_table_next_T_16 = dshl(UInt<1>(0h1), wakeups_2.bits.uop.pdst) node _busy_table_next_T_17 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _busy_table_next_T_18 = mux(_busy_table_next_T_17, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_19 = and(_busy_table_next_T_16, _busy_table_next_T_18) node _busy_table_next_T_20 = dshl(UInt<1>(0h1), wakeups_3.bits.uop.pdst) node _busy_table_next_T_21 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _busy_table_next_T_22 = mux(_busy_table_next_T_21, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _busy_table_next_T_23 = and(_busy_table_next_T_20, _busy_table_next_T_22) node _busy_table_next_T_24 = or(_busy_table_next_T_11, _busy_table_next_T_15) node _busy_table_next_T_25 = or(_busy_table_next_T_24, _busy_table_next_T_19) node _busy_table_next_T_26 = or(_busy_table_next_T_25, _busy_table_next_T_23) node busy_table_next = or(_busy_table_next_T_7, _busy_table_next_T_26) connect busy_table, busy_table_next node _prs1_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_0 = and(wakeups_0.valid, _prs1_match_T) node _prs1_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_1 = and(wakeups_1.valid, _prs1_match_T_1) node _prs1_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_2 = and(wakeups_2.valid, _prs1_match_T_2) node _prs1_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs1) node prs1_match_3 = and(wakeups_3.valid, _prs1_match_T_3) node _prs2_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_0 = and(wakeups_0.valid, _prs2_match_T) node _prs2_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_1 = and(wakeups_1.valid, _prs2_match_T_1) node _prs2_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_2 = and(wakeups_2.valid, _prs2_match_T_2) node _prs2_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs2) node prs2_match_3 = and(wakeups_3.valid, _prs2_match_T_3) node _prs3_match_T = eq(wakeups_0.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_0 = and(wakeups_0.valid, _prs3_match_T) node _prs3_match_T_1 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_1 = and(wakeups_1.valid, _prs3_match_T_1) node _prs3_match_T_2 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_2 = and(wakeups_2.valid, _prs3_match_T_2) node _prs3_match_T_3 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[0].prs3) node prs3_match_3 = and(wakeups_3.valid, _prs3_match_T_3) node _io_busy_resps_0_prs1_busy_T = dshr(busy_table, io.ren_uops[0].prs1) node _io_busy_resps_0_prs1_busy_T_1 = bits(_io_busy_resps_0_prs1_busy_T, 0, 0) connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_T_1 node _io_busy_resps_0_prs2_busy_T = dshr(busy_table, io.ren_uops[0].prs2) node _io_busy_resps_0_prs2_busy_T_1 = bits(_io_busy_resps_0_prs2_busy_T, 0, 0) connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_T_1 node _io_busy_resps_0_prs3_busy_T = dshr(busy_table, io.ren_uops[0].prs3) node _io_busy_resps_0_prs3_busy_T_1 = bits(_io_busy_resps_0_prs3_busy_T, 0, 0) connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_T_1 node _T = or(prs1_match_0, prs1_match_1) node _T_1 = or(_T, prs1_match_2) node _T_2 = or(_T_1, prs1_match_3) when _T_2 : node _io_busy_resps_0_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs1_busy_T_6 = mux(prs1_match_0, _io_busy_resps_0_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_7 = mux(prs1_match_1, _io_busy_resps_0_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_8 = mux(prs1_match_2, _io_busy_resps_0_prs1_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_9 = mux(prs1_match_3, _io_busy_resps_0_prs1_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs1_busy_T_10 = or(_io_busy_resps_0_prs1_busy_T_6, _io_busy_resps_0_prs1_busy_T_7) node _io_busy_resps_0_prs1_busy_T_11 = or(_io_busy_resps_0_prs1_busy_T_10, _io_busy_resps_0_prs1_busy_T_8) node _io_busy_resps_0_prs1_busy_T_12 = or(_io_busy_resps_0_prs1_busy_T_11, _io_busy_resps_0_prs1_busy_T_9) wire _io_busy_resps_0_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs1_busy_WIRE, _io_busy_resps_0_prs1_busy_T_12 connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_WIRE node _T_3 = or(prs2_match_0, prs2_match_1) node _T_4 = or(_T_3, prs2_match_2) node _T_5 = or(_T_4, prs2_match_3) when _T_5 : node _io_busy_resps_0_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs2_busy_T_6 = mux(prs2_match_0, _io_busy_resps_0_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_7 = mux(prs2_match_1, _io_busy_resps_0_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_8 = mux(prs2_match_2, _io_busy_resps_0_prs2_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_9 = mux(prs2_match_3, _io_busy_resps_0_prs2_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs2_busy_T_10 = or(_io_busy_resps_0_prs2_busy_T_6, _io_busy_resps_0_prs2_busy_T_7) node _io_busy_resps_0_prs2_busy_T_11 = or(_io_busy_resps_0_prs2_busy_T_10, _io_busy_resps_0_prs2_busy_T_8) node _io_busy_resps_0_prs2_busy_T_12 = or(_io_busy_resps_0_prs2_busy_T_11, _io_busy_resps_0_prs2_busy_T_9) wire _io_busy_resps_0_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs2_busy_WIRE, _io_busy_resps_0_prs2_busy_T_12 connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_WIRE node _T_6 = or(prs3_match_0, prs3_match_1) node _T_7 = or(_T_6, prs3_match_2) node _T_8 = or(_T_7, prs3_match_3) when _T_8 : node _io_busy_resps_0_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_0_prs3_busy_T_6 = mux(prs3_match_0, _io_busy_resps_0_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_7 = mux(prs3_match_1, _io_busy_resps_0_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_8 = mux(prs3_match_2, _io_busy_resps_0_prs3_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_9 = mux(prs3_match_3, _io_busy_resps_0_prs3_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_0_prs3_busy_T_10 = or(_io_busy_resps_0_prs3_busy_T_6, _io_busy_resps_0_prs3_busy_T_7) node _io_busy_resps_0_prs3_busy_T_11 = or(_io_busy_resps_0_prs3_busy_T_10, _io_busy_resps_0_prs3_busy_T_8) node _io_busy_resps_0_prs3_busy_T_12 = or(_io_busy_resps_0_prs3_busy_T_11, _io_busy_resps_0_prs3_busy_T_9) wire _io_busy_resps_0_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_0_prs3_busy_WIRE, _io_busy_resps_0_prs3_busy_T_12 connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_WIRE connect io.busy_resps[0].prs3_busy, UInt<1>(0h0) node _prs1_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_0_1 = and(wakeups_0.valid, _prs1_match_T_4) node _prs1_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_1_1 = and(wakeups_1.valid, _prs1_match_T_5) node _prs1_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_2_1 = and(wakeups_2.valid, _prs1_match_T_6) node _prs1_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs1) node prs1_match_3_1 = and(wakeups_3.valid, _prs1_match_T_7) node _prs2_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_0_1 = and(wakeups_0.valid, _prs2_match_T_4) node _prs2_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_1_1 = and(wakeups_1.valid, _prs2_match_T_5) node _prs2_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_2_1 = and(wakeups_2.valid, _prs2_match_T_6) node _prs2_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs2) node prs2_match_3_1 = and(wakeups_3.valid, _prs2_match_T_7) node _prs3_match_T_4 = eq(wakeups_0.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_0_1 = and(wakeups_0.valid, _prs3_match_T_4) node _prs3_match_T_5 = eq(wakeups_1.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_1_1 = and(wakeups_1.valid, _prs3_match_T_5) node _prs3_match_T_6 = eq(wakeups_2.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_2_1 = and(wakeups_2.valid, _prs3_match_T_6) node _prs3_match_T_7 = eq(wakeups_3.bits.uop.pdst, io.ren_uops[1].prs3) node prs3_match_3_1 = and(wakeups_3.valid, _prs3_match_T_7) node _io_busy_resps_1_prs1_busy_T = dshr(busy_table, io.ren_uops[1].prs1) node _io_busy_resps_1_prs1_busy_T_1 = bits(_io_busy_resps_1_prs1_busy_T, 0, 0) connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_T_1 node _io_busy_resps_1_prs2_busy_T = dshr(busy_table, io.ren_uops[1].prs2) node _io_busy_resps_1_prs2_busy_T_1 = bits(_io_busy_resps_1_prs2_busy_T, 0, 0) connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_T_1 node _io_busy_resps_1_prs3_busy_T = dshr(busy_table, io.ren_uops[1].prs3) node _io_busy_resps_1_prs3_busy_T_1 = bits(_io_busy_resps_1_prs3_busy_T, 0, 0) connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_T_1 node _T_9 = or(prs1_match_0_1, prs1_match_1_1) node _T_10 = or(_T_9, prs1_match_2_1) node _T_11 = or(_T_10, prs1_match_3_1) when _T_11 : node _io_busy_resps_1_prs1_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs1_busy_T_6 = mux(prs1_match_0_1, _io_busy_resps_1_prs1_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_7 = mux(prs1_match_1_1, _io_busy_resps_1_prs1_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_8 = mux(prs1_match_2_1, _io_busy_resps_1_prs1_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_9 = mux(prs1_match_3_1, _io_busy_resps_1_prs1_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs1_busy_T_10 = or(_io_busy_resps_1_prs1_busy_T_6, _io_busy_resps_1_prs1_busy_T_7) node _io_busy_resps_1_prs1_busy_T_11 = or(_io_busy_resps_1_prs1_busy_T_10, _io_busy_resps_1_prs1_busy_T_8) node _io_busy_resps_1_prs1_busy_T_12 = or(_io_busy_resps_1_prs1_busy_T_11, _io_busy_resps_1_prs1_busy_T_9) wire _io_busy_resps_1_prs1_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs1_busy_WIRE, _io_busy_resps_1_prs1_busy_T_12 connect io.busy_resps[1].prs1_busy, _io_busy_resps_1_prs1_busy_WIRE node _T_12 = or(prs2_match_0_1, prs2_match_1_1) node _T_13 = or(_T_12, prs2_match_2_1) node _T_14 = or(_T_13, prs2_match_3_1) when _T_14 : node _io_busy_resps_1_prs2_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs2_busy_T_6 = mux(prs2_match_0_1, _io_busy_resps_1_prs2_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_7 = mux(prs2_match_1_1, _io_busy_resps_1_prs2_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_8 = mux(prs2_match_2_1, _io_busy_resps_1_prs2_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_9 = mux(prs2_match_3_1, _io_busy_resps_1_prs2_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs2_busy_T_10 = or(_io_busy_resps_1_prs2_busy_T_6, _io_busy_resps_1_prs2_busy_T_7) node _io_busy_resps_1_prs2_busy_T_11 = or(_io_busy_resps_1_prs2_busy_T_10, _io_busy_resps_1_prs2_busy_T_8) node _io_busy_resps_1_prs2_busy_T_12 = or(_io_busy_resps_1_prs2_busy_T_11, _io_busy_resps_1_prs2_busy_T_9) wire _io_busy_resps_1_prs2_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs2_busy_WIRE, _io_busy_resps_1_prs2_busy_T_12 connect io.busy_resps[1].prs2_busy, _io_busy_resps_1_prs2_busy_WIRE node _T_15 = or(prs3_match_0_1, prs3_match_1_1) node _T_16 = or(_T_15, prs3_match_2_1) node _T_17 = or(_T_16, prs3_match_3_1) when _T_17 : node _io_busy_resps_1_prs3_busy_T_2 = and(wakeups_0.valid, wakeups_0.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_3 = and(wakeups_1.valid, wakeups_1.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_4 = and(wakeups_2.valid, wakeups_2.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_5 = and(wakeups_3.valid, wakeups_3.bits.rebusy) node _io_busy_resps_1_prs3_busy_T_6 = mux(prs3_match_0_1, _io_busy_resps_1_prs3_busy_T_2, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_7 = mux(prs3_match_1_1, _io_busy_resps_1_prs3_busy_T_3, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_8 = mux(prs3_match_2_1, _io_busy_resps_1_prs3_busy_T_4, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_9 = mux(prs3_match_3_1, _io_busy_resps_1_prs3_busy_T_5, UInt<1>(0h0)) node _io_busy_resps_1_prs3_busy_T_10 = or(_io_busy_resps_1_prs3_busy_T_6, _io_busy_resps_1_prs3_busy_T_7) node _io_busy_resps_1_prs3_busy_T_11 = or(_io_busy_resps_1_prs3_busy_T_10, _io_busy_resps_1_prs3_busy_T_8) node _io_busy_resps_1_prs3_busy_T_12 = or(_io_busy_resps_1_prs3_busy_T_11, _io_busy_resps_1_prs3_busy_T_9) wire _io_busy_resps_1_prs3_busy_WIRE : UInt<1> connect _io_busy_resps_1_prs3_busy_WIRE, _io_busy_resps_1_prs3_busy_T_12 connect io.busy_resps[1].prs3_busy, _io_busy_resps_1_prs3_busy_WIRE connect io.busy_resps[1].prs3_busy, UInt<1>(0h0) connect io.debug.busytable, busy_table

module RenameBusyTable( // @[rename-busytable.scala:27:7] input clock, // @[rename-busytable.scala:27:7] input reset, // @[rename-busytable.scala:27:7] input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_0_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_0_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_0_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_0_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_0_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_0_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_0_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_inst, // @[rename-busytable.scala:36:14] input [31:0] io_ren_uops_1_debug_inst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_ren_uops_1_debug_pc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iq_type_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_0, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_4, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_5, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_6, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_7, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_8, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fu_code_9, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_ren_uops_1_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_br_type, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfb, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_fencei, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sfence, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_amo, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_eret, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_rocc, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ftq_idx, // @[rename-busytable.scala:36:14] input io_ren_uops_1_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_pc_lob, // @[rename-busytable.scala:36:14] input io_ren_uops_1_taken, // @[rename-busytable.scala:36:14] input io_ren_uops_1_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_ren_uops_1_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_op2_sel, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_ren_uops_1_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_ppred, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs1_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_prs2_busy, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_ren_uops_1_stale_pdst, // @[rename-busytable.scala:36:14] input io_ren_uops_1_exception, // @[rename-busytable.scala:36:14] input [63:0] io_ren_uops_1_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_mem_size, // @[rename-busytable.scala:36:14] input io_ren_uops_1_mem_signed, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_ldq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_uses_stq, // @[rename-busytable.scala:36:14] input io_ren_uops_1_is_unique, // @[rename-busytable.scala:36:14] input io_ren_uops_1_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_csr_cmd, // @[rename-busytable.scala:36:14] input io_ren_uops_1_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_ren_uops_1_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_ren_uops_1_frs3_en, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_ren_uops_1_fcn_op, // @[rename-busytable.scala:36:14] input io_ren_uops_1_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_ren_uops_1_fp_typ, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_debug_if, // @[rename-busytable.scala:36:14] input io_ren_uops_1_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_ren_uops_1_debug_tsrc, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs1_busy, // @[rename-busytable.scala:36:14] output io_busy_resps_1_prs2_busy, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_0, // @[rename-busytable.scala:36:14] input io_rebusy_reqs_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_0_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_0_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_0_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_0_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_0_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_0_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_0_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_0_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_0_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_0_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_bypassable, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_0_bits_speculative_mask, // @[rename-busytable.scala:36:14] input io_wakeups_0_bits_rebusy, // @[rename-busytable.scala:36:14] input io_wakeups_1_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_1_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_1_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_agen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_issued_partial_dgen, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_1_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_1_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_1_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_1_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_1_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_1_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_1_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_1_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_1_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_1_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_2_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_2_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_2_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_2_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_2_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_2_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_2_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_2_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_2_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_2_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_2_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_2_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_2_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_2_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input io_wakeups_3_valid, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_3_bits_uop_inst, // @[rename-busytable.scala:36:14] input [31:0] io_wakeups_3_bits_uop_debug_inst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_rvc, // @[rename-busytable.scala:36:14] input [39:0] io_wakeups_3_bits_uop_debug_pc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_0, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iq_type_3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_0, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_4, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_5, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_6, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_7, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_8, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fu_code_9, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_issued, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_iw_p1_speculative_child, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_iw_p2_speculative_child, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p1_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p2_bypass_hint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_iw_p3_bypass_hint, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_dis_col_sel, // @[rename-busytable.scala:36:14] input [11:0] io_wakeups_3_bits_uop_br_mask, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_br_tag, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_br_type, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sfb, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_fence, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_fencei, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sfence, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_amo, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_eret, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_sys_pc2epc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_rocc, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_mov, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_ftq_idx, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_edge_inst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_pc_lob, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_taken, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_imm_rename, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_imm_sel, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_pimm, // @[rename-busytable.scala:36:14] input [19:0] io_wakeups_3_bits_uop_imm_packed, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_op1_sel, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_op2_sel, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ldst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_wen, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren1, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren2, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_ren3, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_swap12, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_swap23, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fromint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_toint, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fastpipe, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_fma, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_div, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_sqrt, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_wflags, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_ctrl_vec, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_rob_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_ldq_idx, // @[rename-busytable.scala:36:14] input [3:0] io_wakeups_3_bits_uop_stq_idx, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_rxq_idx, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_pdst, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs1, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs2, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_prs3, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_ppred, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs1_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs2_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_prs3_busy, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_ppred_busy, // @[rename-busytable.scala:36:14] input [6:0] io_wakeups_3_bits_uop_stale_pdst, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_exception, // @[rename-busytable.scala:36:14] input [63:0] io_wakeups_3_bits_uop_exc_cause, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_mem_cmd, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_mem_size, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_mem_signed, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_uses_ldq, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_uses_stq, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_is_unique, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_flush_on_commit, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_csr_cmd, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_ldst_is_rs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_ldst, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs1, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs2, // @[rename-busytable.scala:36:14] input [5:0] io_wakeups_3_bits_uop_lrs3, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_dst_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_lrs1_rtype, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_lrs2_rtype, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_frs3_en, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fcn_dw, // @[rename-busytable.scala:36:14] input [4:0] io_wakeups_3_bits_uop_fcn_op, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_fp_val, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_fp_rm, // @[rename-busytable.scala:36:14] input [1:0] io_wakeups_3_bits_uop_fp_typ, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_pf_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_ae_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_xcpt_ma_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_bp_debug_if, // @[rename-busytable.scala:36:14] input io_wakeups_3_bits_uop_bp_xcpt_if, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_debug_fsrc, // @[rename-busytable.scala:36:14] input [2:0] io_wakeups_3_bits_uop_debug_tsrc, // @[rename-busytable.scala:36:14] input [1:0] io_child_rebusys // @[rename-busytable.scala:36:14] ); wire wakeups_3_valid; // @[rename-busytable.scala:47:18] wire wakeups_2_valid; // @[rename-busytable.scala:47:18] wire wakeups_1_valid; // @[rename-busytable.scala:47:18] wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_0_0 = io_ren_uops_0_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_1_0 = io_ren_uops_0_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_2_0 = io_ren_uops_0_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iq_type_3_0 = io_ren_uops_0_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_0_0 = io_ren_uops_0_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_1_0 = io_ren_uops_0_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_2_0 = io_ren_uops_0_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_3_0 = io_ren_uops_0_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_4_0 = io_ren_uops_0_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_5_0 = io_ren_uops_0_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_6_0 = io_ren_uops_0_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_7_0 = io_ren_uops_0_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_8_0 = io_ren_uops_0_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fu_code_9_0 = io_ren_uops_0_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_0 = io_ren_uops_0_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_agen_0 = io_ren_uops_0_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_issued_partial_dgen_0 = io_ren_uops_0_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p1_speculative_child_0 = io_ren_uops_0_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_iw_p2_speculative_child_0 = io_ren_uops_0_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p1_bypass_hint_0 = io_ren_uops_0_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p2_bypass_hint_0 = io_ren_uops_0_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_iw_p3_bypass_hint_0 = io_ren_uops_0_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dis_col_sel_0 = io_ren_uops_0_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_br_type_0 = io_ren_uops_0_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sfence_0 = io_ren_uops_0_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_eret_0 = io_ren_uops_0_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_rocc_0 = io_ren_uops_0_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_mov_0 = io_ren_uops_0_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_imm_rename_0 = io_ren_uops_0_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_imm_sel_0 = io_ren_uops_0_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_pimm_0 = io_ren_uops_0_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_op1_sel_0 = io_ren_uops_0_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_op2_sel_0 = io_ren_uops_0_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ldst_0 = io_ren_uops_0_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wen_0 = io_ren_uops_0_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren1_0 = io_ren_uops_0_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren2_0 = io_ren_uops_0_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_ren3_0 = io_ren_uops_0_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap12_0 = io_ren_uops_0_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_swap23_0 = io_ren_uops_0_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagIn_0 = io_ren_uops_0_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_ctrl_typeTagOut_0 = io_ren_uops_0_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fromint_0 = io_ren_uops_0_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_toint_0 = io_ren_uops_0_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fastpipe_0 = io_ren_uops_0_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_fma_0 = io_ren_uops_0_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_div_0 = io_ren_uops_0_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_sqrt_0 = io_ren_uops_0_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_wflags_0 = io_ren_uops_0_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_ctrl_vec_0 = io_ren_uops_0_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_prs3_0 = io_ren_uops_0_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_csr_cmd_0 = io_ren_uops_0_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fcn_dw_0 = io_ren_uops_0_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_0_fcn_op_0 = io_ren_uops_0_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_fp_rm_0 = io_ren_uops_0_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_0_fp_typ_0 = io_ren_uops_0_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_inst_0 = io_ren_uops_1_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_ren_uops_1_debug_inst_0 = io_ren_uops_1_debug_inst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rvc_0 = io_ren_uops_1_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_ren_uops_1_debug_pc_0 = io_ren_uops_1_debug_pc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_0_0 = io_ren_uops_1_iq_type_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_1_0 = io_ren_uops_1_iq_type_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_2_0 = io_ren_uops_1_iq_type_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iq_type_3_0 = io_ren_uops_1_iq_type_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_0_0 = io_ren_uops_1_fu_code_0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_1_0 = io_ren_uops_1_fu_code_1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_2_0 = io_ren_uops_1_fu_code_2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_3_0 = io_ren_uops_1_fu_code_3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_4_0 = io_ren_uops_1_fu_code_4; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_5_0 = io_ren_uops_1_fu_code_5; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_6_0 = io_ren_uops_1_fu_code_6; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_7_0 = io_ren_uops_1_fu_code_7; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_8_0 = io_ren_uops_1_fu_code_8; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fu_code_9_0 = io_ren_uops_1_fu_code_9; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_0 = io_ren_uops_1_iw_issued; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_agen_0 = io_ren_uops_1_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_issued_partial_dgen_0 = io_ren_uops_1_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p1_speculative_child_0 = io_ren_uops_1_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_iw_p2_speculative_child_0 = io_ren_uops_1_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p1_bypass_hint_0 = io_ren_uops_1_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p2_bypass_hint_0 = io_ren_uops_1_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_iw_p3_bypass_hint_0 = io_ren_uops_1_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dis_col_sel_0 = io_ren_uops_1_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_ren_uops_1_br_mask_0 = io_ren_uops_1_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_tag_0 = io_ren_uops_1_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_br_type_0 = io_ren_uops_1_br_type; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfb_0 = io_ren_uops_1_is_sfb; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fence_0 = io_ren_uops_1_is_fence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_fencei_0 = io_ren_uops_1_is_fencei; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sfence_0 = io_ren_uops_1_is_sfence; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_amo_0 = io_ren_uops_1_is_amo; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_eret_0 = io_ren_uops_1_is_eret; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_sys_pc2epc_0 = io_ren_uops_1_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_rocc_0 = io_ren_uops_1_is_rocc; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_mov_0 = io_ren_uops_1_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ftq_idx_0 = io_ren_uops_1_ftq_idx; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_edge_inst_0 = io_ren_uops_1_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_pc_lob_0 = io_ren_uops_1_pc_lob; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_taken_0 = io_ren_uops_1_taken; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_imm_rename_0 = io_ren_uops_1_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_imm_sel_0 = io_ren_uops_1_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_pimm_0 = io_ren_uops_1_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_ren_uops_1_imm_packed_0 = io_ren_uops_1_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_op1_sel_0 = io_ren_uops_1_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_op2_sel_0 = io_ren_uops_1_op2_sel; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ldst_0 = io_ren_uops_1_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wen_0 = io_ren_uops_1_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren1_0 = io_ren_uops_1_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren2_0 = io_ren_uops_1_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_ren3_0 = io_ren_uops_1_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap12_0 = io_ren_uops_1_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_swap23_0 = io_ren_uops_1_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagIn_0 = io_ren_uops_1_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_ctrl_typeTagOut_0 = io_ren_uops_1_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fromint_0 = io_ren_uops_1_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_toint_0 = io_ren_uops_1_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fastpipe_0 = io_ren_uops_1_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_fma_0 = io_ren_uops_1_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_div_0 = io_ren_uops_1_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_sqrt_0 = io_ren_uops_1_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_wflags_0 = io_ren_uops_1_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_ctrl_vec_0 = io_ren_uops_1_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_rob_idx_0 = io_ren_uops_1_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_ldq_idx_0 = io_ren_uops_1_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_ren_uops_1_stq_idx_0 = io_ren_uops_1_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_rxq_idx_0 = io_ren_uops_1_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_pdst_0 = io_ren_uops_1_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs1_0 = io_ren_uops_1_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs2_0 = io_ren_uops_1_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_prs3_0 = io_ren_uops_1_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_ppred_0 = io_ren_uops_1_ppred; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs1_busy_0 = io_ren_uops_1_prs1_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs2_busy_0 = io_ren_uops_1_prs2_busy; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ppred_busy_0 = io_ren_uops_1_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_ren_uops_1_stale_pdst_0 = io_ren_uops_1_stale_pdst; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_exception_0 = io_ren_uops_1_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_ren_uops_1_exc_cause_0 = io_ren_uops_1_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_mem_cmd_0 = io_ren_uops_1_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_mem_size_0 = io_ren_uops_1_mem_size; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_mem_signed_0 = io_ren_uops_1_mem_signed; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_ldq_0 = io_ren_uops_1_uses_ldq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_uses_stq_0 = io_ren_uops_1_uses_stq; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_is_unique_0 = io_ren_uops_1_is_unique; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_flush_on_commit_0 = io_ren_uops_1_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_csr_cmd_0 = io_ren_uops_1_csr_cmd; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_ldst_is_rs1_0 = io_ren_uops_1_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_ldst_0 = io_ren_uops_1_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs1_0 = io_ren_uops_1_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs2_0 = io_ren_uops_1_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_ren_uops_1_lrs3_0 = io_ren_uops_1_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_dst_rtype_0 = io_ren_uops_1_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs1_rtype_0 = io_ren_uops_1_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_lrs2_rtype_0 = io_ren_uops_1_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_frs3_en_0 = io_ren_uops_1_frs3_en; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fcn_dw_0 = io_ren_uops_1_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_ren_uops_1_fcn_op_0 = io_ren_uops_1_fcn_op; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_fp_val_0 = io_ren_uops_1_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_fp_rm_0 = io_ren_uops_1_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_ren_uops_1_fp_typ_0 = io_ren_uops_1_fp_typ; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_pf_if_0 = io_ren_uops_1_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ae_if_0 = io_ren_uops_1_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_xcpt_ma_if_0 = io_ren_uops_1_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_debug_if_0 = io_ren_uops_1_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_bp_xcpt_if_0 = io_ren_uops_1_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_fsrc_0 = io_ren_uops_1_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_ren_uops_1_debug_tsrc_0 = io_ren_uops_1_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7] wire io_rebusy_reqs_1_0 = io_rebusy_reqs_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_valid_0 = io_wakeups_0_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_inst_0 = io_wakeups_0_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_0_bits_uop_debug_inst_0 = io_wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rvc_0 = io_wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_0_bits_uop_debug_pc_0 = io_wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_0_0 = io_wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_1_0 = io_wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_2_0 = io_wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iq_type_3_0 = io_wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_0_0 = io_wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_1_0 = io_wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_2_0 = io_wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_3_0 = io_wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_4_0 = io_wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_5_0 = io_wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_6_0 = io_wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_7_0 = io_wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_8_0 = io_wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fu_code_9_0 = io_wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_0 = io_wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_agen_0 = io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p1_speculative_child_0 = io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_iw_p2_speculative_child_0 = io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dis_col_sel_0 = io_wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_0_bits_uop_br_mask_0 = io_wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_tag_0 = io_wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_br_type_0 = io_wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfb_0 = io_wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fence_0 = io_wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_fencei_0 = io_wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sfence_0 = io_wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_amo_0 = io_wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_eret_0 = io_wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_sys_pc2epc_0 = io_wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_rocc_0 = io_wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_mov_0 = io_wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ftq_idx_0 = io_wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_edge_inst_0 = io_wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_pc_lob_0 = io_wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_taken_0 = io_wakeups_0_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_imm_rename_0 = io_wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_imm_sel_0 = io_wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_pimm_0 = io_wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_0_bits_uop_imm_packed_0 = io_wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_op1_sel_0 = io_wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_op2_sel_0 = io_wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ldst_0 = io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wen_0 = io_wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren1_0 = io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren2_0 = io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_ren3_0 = io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap12_0 = io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_swap23_0 = io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fromint_0 = io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_toint_0 = io_wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_fma_0 = io_wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_div_0 = io_wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_wflags_0 = io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_ctrl_vec_0 = io_wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_rob_idx_0 = io_wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_ldq_idx_0 = io_wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_0_bits_uop_stq_idx_0 = io_wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_rxq_idx_0 = io_wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_pdst_0 = io_wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs1_0 = io_wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs2_0 = io_wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_prs3_0 = io_wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_ppred_0 = io_wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs1_busy_0 = io_wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs2_busy_0 = io_wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_prs3_busy_0 = io_wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ppred_busy_0 = io_wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_0_bits_uop_stale_pdst_0 = io_wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_exception_0 = io_wakeups_0_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_0_bits_uop_exc_cause_0 = io_wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_mem_cmd_0 = io_wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_mem_size_0 = io_wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_mem_signed_0 = io_wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_ldq_0 = io_wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_uses_stq_0 = io_wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_is_unique_0 = io_wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_flush_on_commit_0 = io_wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_csr_cmd_0 = io_wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_ldst_is_rs1_0 = io_wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_ldst_0 = io_wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs1_0 = io_wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs2_0 = io_wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_0_bits_uop_lrs3_0 = io_wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_dst_rtype_0 = io_wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs1_rtype_0 = io_wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_lrs2_rtype_0 = io_wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_frs3_en_0 = io_wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fcn_dw_0 = io_wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_0_bits_uop_fcn_op_0 = io_wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_fp_val_0 = io_wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_fp_rm_0 = io_wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_uop_fp_typ_0 = io_wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_pf_if_0 = io_wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ae_if_0 = io_wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_xcpt_ma_if_0 = io_wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_debug_if_0 = io_wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_uop_bp_xcpt_if_0 = io_wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_fsrc_0 = io_wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_0_bits_uop_debug_tsrc_0 = io_wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_bypassable_0 = io_wakeups_0_bits_bypassable; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_0_bits_speculative_mask_0 = io_wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:27:7] wire io_wakeups_0_bits_rebusy_0 = io_wakeups_0_bits_rebusy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_valid_0 = io_wakeups_1_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_inst_0 = io_wakeups_1_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_1_bits_uop_debug_inst_0 = io_wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rvc_0 = io_wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_1_bits_uop_debug_pc_0 = io_wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_0_0 = io_wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_1_0 = io_wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_2_0 = io_wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iq_type_3_0 = io_wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_0_0 = io_wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_1_0 = io_wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_2_0 = io_wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_3_0 = io_wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_4_0 = io_wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_5_0 = io_wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_6_0 = io_wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_7_0 = io_wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_8_0 = io_wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fu_code_9_0 = io_wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_0 = io_wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_agen_0 = io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p1_speculative_child_0 = io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_iw_p2_speculative_child_0 = io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dis_col_sel_0 = io_wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_1_bits_uop_br_mask_0 = io_wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_tag_0 = io_wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_br_type_0 = io_wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfb_0 = io_wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fence_0 = io_wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_fencei_0 = io_wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sfence_0 = io_wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_amo_0 = io_wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_eret_0 = io_wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_sys_pc2epc_0 = io_wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_rocc_0 = io_wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_mov_0 = io_wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ftq_idx_0 = io_wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_edge_inst_0 = io_wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_pc_lob_0 = io_wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_taken_0 = io_wakeups_1_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_imm_rename_0 = io_wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_imm_sel_0 = io_wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_pimm_0 = io_wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_1_bits_uop_imm_packed_0 = io_wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_op1_sel_0 = io_wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_op2_sel_0 = io_wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ldst_0 = io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wen_0 = io_wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren1_0 = io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren2_0 = io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_ren3_0 = io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap12_0 = io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_swap23_0 = io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fromint_0 = io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_toint_0 = io_wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_fma_0 = io_wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_div_0 = io_wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_wflags_0 = io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_ctrl_vec_0 = io_wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_rob_idx_0 = io_wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_ldq_idx_0 = io_wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_1_bits_uop_stq_idx_0 = io_wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_rxq_idx_0 = io_wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_pdst_0 = io_wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs1_0 = io_wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs2_0 = io_wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_prs3_0 = io_wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_ppred_0 = io_wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs1_busy_0 = io_wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs2_busy_0 = io_wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_prs3_busy_0 = io_wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ppred_busy_0 = io_wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_1_bits_uop_stale_pdst_0 = io_wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_exception_0 = io_wakeups_1_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_1_bits_uop_exc_cause_0 = io_wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_mem_cmd_0 = io_wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_mem_size_0 = io_wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_mem_signed_0 = io_wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_ldq_0 = io_wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_uses_stq_0 = io_wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_is_unique_0 = io_wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_flush_on_commit_0 = io_wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_csr_cmd_0 = io_wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_ldst_is_rs1_0 = io_wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_ldst_0 = io_wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs1_0 = io_wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs2_0 = io_wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_1_bits_uop_lrs3_0 = io_wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_dst_rtype_0 = io_wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs1_rtype_0 = io_wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_lrs2_rtype_0 = io_wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_frs3_en_0 = io_wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fcn_dw_0 = io_wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_1_bits_uop_fcn_op_0 = io_wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_fp_val_0 = io_wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_fp_rm_0 = io_wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_uop_fp_typ_0 = io_wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_pf_if_0 = io_wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ae_if_0 = io_wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_xcpt_ma_if_0 = io_wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_debug_if_0 = io_wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_uop_bp_xcpt_if_0 = io_wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_fsrc_0 = io_wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_1_bits_uop_debug_tsrc_0 = io_wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_valid_0 = io_wakeups_2_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_2_bits_uop_inst_0 = io_wakeups_2_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_2_bits_uop_debug_inst_0 = io_wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_rvc_0 = io_wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_2_bits_uop_debug_pc_0 = io_wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_0_0 = io_wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_1_0 = io_wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_2_0 = io_wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iq_type_3_0 = io_wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_0_0 = io_wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_1_0 = io_wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_2_0 = io_wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_3_0 = io_wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_4_0 = io_wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_5_0 = io_wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_6_0 = io_wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_7_0 = io_wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_8_0 = io_wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fu_code_9_0 = io_wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_0 = io_wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_iw_p1_speculative_child_0 = io_wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_iw_p2_speculative_child_0 = io_wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_dis_col_sel_0 = io_wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_2_bits_uop_br_mask_0 = io_wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_br_tag_0 = io_wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_br_type_0 = io_wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sfb_0 = io_wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_fence_0 = io_wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_fencei_0 = io_wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sfence_0 = io_wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_amo_0 = io_wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_eret_0 = io_wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_sys_pc2epc_0 = io_wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_rocc_0 = io_wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_mov_0 = io_wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_ftq_idx_0 = io_wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_edge_inst_0 = io_wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_pc_lob_0 = io_wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_taken_0 = io_wakeups_2_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_imm_rename_0 = io_wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_imm_sel_0 = io_wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_pimm_0 = io_wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_2_bits_uop_imm_packed_0 = io_wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_op1_sel_0 = io_wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_op2_sel_0 = io_wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ldst_0 = io_wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_wen_0 = io_wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren1_0 = io_wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren2_0 = io_wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_ren3_0 = io_wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_swap12_0 = io_wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_swap23_0 = io_wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fromint_0 = io_wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_toint_0 = io_wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_fma_0 = io_wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_div_0 = io_wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_wflags_0 = io_wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_ctrl_vec_0 = io_wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_rob_idx_0 = io_wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_ldq_idx_0 = io_wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_2_bits_uop_stq_idx_0 = io_wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_rxq_idx_0 = io_wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_pdst_0 = io_wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs1_0 = io_wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs2_0 = io_wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_prs3_0 = io_wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_ppred_0 = io_wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs1_busy_0 = io_wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs2_busy_0 = io_wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_prs3_busy_0 = io_wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_ppred_busy_0 = io_wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_2_bits_uop_stale_pdst_0 = io_wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_exception_0 = io_wakeups_2_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_2_bits_uop_exc_cause_0 = io_wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_mem_cmd_0 = io_wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_mem_size_0 = io_wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_mem_signed_0 = io_wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_uses_ldq_0 = io_wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_uses_stq_0 = io_wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_is_unique_0 = io_wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_flush_on_commit_0 = io_wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_csr_cmd_0 = io_wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_ldst_is_rs1_0 = io_wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_ldst_0 = io_wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs1_0 = io_wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs2_0 = io_wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_2_bits_uop_lrs3_0 = io_wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_dst_rtype_0 = io_wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_lrs1_rtype_0 = io_wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_lrs2_rtype_0 = io_wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_frs3_en_0 = io_wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fcn_dw_0 = io_wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_2_bits_uop_fcn_op_0 = io_wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_fp_val_0 = io_wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_fp_rm_0 = io_wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_2_bits_uop_fp_typ_0 = io_wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_pf_if_0 = io_wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_ae_if_0 = io_wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_xcpt_ma_if_0 = io_wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_bp_debug_if_0 = io_wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_bp_xcpt_if_0 = io_wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_debug_fsrc_0 = io_wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_2_bits_uop_debug_tsrc_0 = io_wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_valid_0 = io_wakeups_3_valid; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_3_bits_uop_inst_0 = io_wakeups_3_bits_uop_inst; // @[rename-busytable.scala:27:7] wire [31:0] io_wakeups_3_bits_uop_debug_inst_0 = io_wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_rvc_0 = io_wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:27:7] wire [39:0] io_wakeups_3_bits_uop_debug_pc_0 = io_wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_0_0 = io_wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_1_0 = io_wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_2_0 = io_wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iq_type_3_0 = io_wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_0_0 = io_wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_1_0 = io_wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_2_0 = io_wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_3_0 = io_wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_4_0 = io_wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_5_0 = io_wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_6_0 = io_wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_7_0 = io_wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_8_0 = io_wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fu_code_9_0 = io_wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_0 = io_wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_iw_p1_speculative_child_0 = io_wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_iw_p2_speculative_child_0 = io_wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_dis_col_sel_0 = io_wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:27:7] wire [11:0] io_wakeups_3_bits_uop_br_mask_0 = io_wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_br_tag_0 = io_wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_br_type_0 = io_wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sfb_0 = io_wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_fence_0 = io_wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_fencei_0 = io_wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sfence_0 = io_wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_amo_0 = io_wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_eret_0 = io_wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_sys_pc2epc_0 = io_wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_rocc_0 = io_wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_mov_0 = io_wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_ftq_idx_0 = io_wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_edge_inst_0 = io_wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_pc_lob_0 = io_wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_taken_0 = io_wakeups_3_bits_uop_taken; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_imm_rename_0 = io_wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_imm_sel_0 = io_wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_pimm_0 = io_wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:27:7] wire [19:0] io_wakeups_3_bits_uop_imm_packed_0 = io_wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_op1_sel_0 = io_wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_op2_sel_0 = io_wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ldst_0 = io_wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_wen_0 = io_wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren1_0 = io_wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren2_0 = io_wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_ren3_0 = io_wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_swap12_0 = io_wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_swap23_0 = io_wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fromint_0 = io_wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_toint_0 = io_wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_fma_0 = io_wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_div_0 = io_wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_wflags_0 = io_wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_ctrl_vec_0 = io_wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_rob_idx_0 = io_wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_ldq_idx_0 = io_wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:27:7] wire [3:0] io_wakeups_3_bits_uop_stq_idx_0 = io_wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_rxq_idx_0 = io_wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_pdst_0 = io_wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs1_0 = io_wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs2_0 = io_wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_prs3_0 = io_wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_ppred_0 = io_wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs1_busy_0 = io_wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs2_busy_0 = io_wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_prs3_busy_0 = io_wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_ppred_busy_0 = io_wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:27:7] wire [6:0] io_wakeups_3_bits_uop_stale_pdst_0 = io_wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_exception_0 = io_wakeups_3_bits_uop_exception; // @[rename-busytable.scala:27:7] wire [63:0] io_wakeups_3_bits_uop_exc_cause_0 = io_wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_mem_cmd_0 = io_wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_mem_size_0 = io_wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_mem_signed_0 = io_wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_uses_ldq_0 = io_wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_uses_stq_0 = io_wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_is_unique_0 = io_wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_flush_on_commit_0 = io_wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_csr_cmd_0 = io_wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_ldst_is_rs1_0 = io_wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_ldst_0 = io_wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs1_0 = io_wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs2_0 = io_wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:27:7] wire [5:0] io_wakeups_3_bits_uop_lrs3_0 = io_wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_dst_rtype_0 = io_wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_lrs1_rtype_0 = io_wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_lrs2_rtype_0 = io_wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_frs3_en_0 = io_wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fcn_dw_0 = io_wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:27:7] wire [4:0] io_wakeups_3_bits_uop_fcn_op_0 = io_wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_fp_val_0 = io_wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_fp_rm_0 = io_wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_3_bits_uop_fp_typ_0 = io_wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_pf_if_0 = io_wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_ae_if_0 = io_wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_xcpt_ma_if_0 = io_wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_bp_debug_if_0 = io_wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_bp_xcpt_if_0 = io_wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_debug_fsrc_0 = io_wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:27:7] wire [2:0] io_wakeups_3_bits_uop_debug_tsrc_0 = io_wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:27:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[rename-busytable.scala:27:7] wire [1:0] io_wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_1_bits_speculative_mask = 2'h0; // @[rename-busytable.scala:47:18] wire [1:0] _wakeups_wu_valid_T_3 = 2'h0; // @[rename-busytable.scala:48:72] wire [1:0] io_wakeups_2_bits_speculative_mask = 2'h1; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_2_bits_speculative_mask = 2'h1; // @[rename-busytable.scala:47:18] wire [1:0] io_wakeups_3_bits_speculative_mask = 2'h2; // @[rename-busytable.scala:27:7] wire [1:0] wakeups_3_bits_speculative_mask = 2'h2; // @[rename-busytable.scala:47:18] wire io_wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_4 = 1'h1; // @[rename-busytable.scala:48:92] wire wakeups_2_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_bypassable = 1'h1; // @[rename-busytable.scala:47:18] wire _busy_table_wb_T_6 = 1'h1; // @[rename-busytable.scala:56:59] wire _busy_table_wb_T_11 = 1'h1; // @[rename-busytable.scala:56:59] wire _busy_table_wb_T_16 = 1'h1; // @[rename-busytable.scala:56:59] wire [79:0] _busy_table_next_T_14 = 80'h0; // @[rename-busytable.scala:63:37] wire [79:0] _busy_table_next_T_18 = 80'h0; // @[rename-busytable.scala:63:37] wire [79:0] _busy_table_next_T_22 = 80'h0; // @[rename-busytable.scala:63:37] wire [127:0] _busy_table_next_T_15 = 128'h0; // @[rename-busytable.scala:63:31] wire [127:0] _busy_table_next_T_19 = 128'h0; // @[rename-busytable.scala:63:31] wire [127:0] _busy_table_next_T_23 = 128'h0; // @[rename-busytable.scala:63:31] wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_ren_uops_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[rename-busytable.scala:27:7] wire io_wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:27:7] wire wakeups_1_bits_bypassable = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_rebusy = 1'h0; // @[rename-busytable.scala:47:18] wire _busy_table_next_T_13 = 1'h0; // @[rename-busytable.scala:63:56] wire _busy_table_next_T_17 = 1'h0; // @[rename-busytable.scala:63:56] wire _busy_table_next_T_21 = 1'h0; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_0_prs1_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_0_prs2_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_0_prs3_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_3 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_4 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_5 = 1'h0; // @[rename-busytable.scala:79:82] wire _io_busy_resps_1_prs1_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_3 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_4 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_5 = 1'h0; // @[rename-busytable.scala:82:82] wire _io_busy_resps_1_prs2_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_3 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_4 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_5 = 1'h0; // @[rename-busytable.scala:85:82] wire _io_busy_resps_1_prs3_busy_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_9 = 1'h0; // @[Mux.scala:30:73] wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] wire io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] wire [79:0] io_debug_busytable; // @[rename-busytable.scala:27:7] wire _wakeups_wu_valid_T_2; // @[rename-busytable.scala:48:34] wire wakeups_0_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_0_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_0_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_0_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_0_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_0_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_0_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_0_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_0_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_0_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_0_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_bypassable; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_0_bits_speculative_mask; // @[rename-busytable.scala:47:18] wire wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18] wire wakeups_0_valid; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG; // @[rename-busytable.scala:48:24] reg [1:0] wakeups_wu_valid_REG_1; // @[rename-busytable.scala:48:46] wire [1:0] _wakeups_wu_valid_T = wakeups_wu_valid_REG_1 & io_child_rebusys_0; // @[rename-busytable.scala:27:7, :48:{46,72}] wire _wakeups_wu_valid_T_1 = _wakeups_wu_valid_T == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_2 = wakeups_wu_valid_REG & _wakeups_wu_valid_T_1; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_0_valid = _wakeups_wu_valid_T_2; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_inst = wakeups_wu_bits_REG_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_inst = wakeups_wu_bits_REG_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rvc = wakeups_wu_bits_REG_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_pc = wakeups_wu_bits_REG_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_0 = wakeups_wu_bits_REG_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_1 = wakeups_wu_bits_REG_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_2 = wakeups_wu_bits_REG_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iq_type_3 = wakeups_wu_bits_REG_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_0 = wakeups_wu_bits_REG_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_1 = wakeups_wu_bits_REG_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_2 = wakeups_wu_bits_REG_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_3 = wakeups_wu_bits_REG_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_4 = wakeups_wu_bits_REG_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_5 = wakeups_wu_bits_REG_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_6 = wakeups_wu_bits_REG_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_7 = wakeups_wu_bits_REG_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_8 = wakeups_wu_bits_REG_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fu_code_9 = wakeups_wu_bits_REG_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued = wakeups_wu_bits_REG_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dis_col_sel = wakeups_wu_bits_REG_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_mask = wakeups_wu_bits_REG_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_tag = wakeups_wu_bits_REG_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_br_type = wakeups_wu_bits_REG_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfb = wakeups_wu_bits_REG_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fence = wakeups_wu_bits_REG_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_fencei = wakeups_wu_bits_REG_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sfence = wakeups_wu_bits_REG_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_amo = wakeups_wu_bits_REG_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_eret = wakeups_wu_bits_REG_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_rocc = wakeups_wu_bits_REG_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_mov = wakeups_wu_bits_REG_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ftq_idx = wakeups_wu_bits_REG_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_edge_inst = wakeups_wu_bits_REG_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pc_lob = wakeups_wu_bits_REG_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_taken = wakeups_wu_bits_REG_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_rename = wakeups_wu_bits_REG_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_sel = wakeups_wu_bits_REG_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pimm = wakeups_wu_bits_REG_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_imm_packed = wakeups_wu_bits_REG_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op1_sel = wakeups_wu_bits_REG_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_op2_sel = wakeups_wu_bits_REG_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rob_idx = wakeups_wu_bits_REG_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldq_idx = wakeups_wu_bits_REG_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stq_idx = wakeups_wu_bits_REG_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_rxq_idx = wakeups_wu_bits_REG_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_pdst = wakeups_wu_bits_REG_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1 = wakeups_wu_bits_REG_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2 = wakeups_wu_bits_REG_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3 = wakeups_wu_bits_REG_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred = wakeups_wu_bits_REG_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs1_busy = wakeups_wu_bits_REG_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs2_busy = wakeups_wu_bits_REG_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_prs3_busy = wakeups_wu_bits_REG_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ppred_busy = wakeups_wu_bits_REG_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_stale_pdst = wakeups_wu_bits_REG_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exception = wakeups_wu_bits_REG_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_exc_cause = wakeups_wu_bits_REG_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_cmd = wakeups_wu_bits_REG_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_size = wakeups_wu_bits_REG_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_mem_signed = wakeups_wu_bits_REG_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_ldq = wakeups_wu_bits_REG_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_uses_stq = wakeups_wu_bits_REG_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_is_unique = wakeups_wu_bits_REG_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_flush_on_commit = wakeups_wu_bits_REG_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_csr_cmd = wakeups_wu_bits_REG_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_ldst = wakeups_wu_bits_REG_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1 = wakeups_wu_bits_REG_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2 = wakeups_wu_bits_REG_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs3 = wakeups_wu_bits_REG_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_dst_rtype = wakeups_wu_bits_REG_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_frs3_en = wakeups_wu_bits_REG_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_dw = wakeups_wu_bits_REG_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fcn_op = wakeups_wu_bits_REG_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_val = wakeups_wu_bits_REG_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_rm = wakeups_wu_bits_REG_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_fp_typ = wakeups_wu_bits_REG_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_debug_if = wakeups_wu_bits_REG_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_fsrc = wakeups_wu_bits_REG_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_uop_debug_tsrc = wakeups_wu_bits_REG_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_bypassable = wakeups_wu_bits_REG_bypassable; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_speculative_mask = wakeups_wu_bits_REG_speculative_mask; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:49:24] assign wakeups_0_bits_rebusy = wakeups_wu_bits_REG_rebusy; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_5; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_7 = wakeups_1_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_1_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_1_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_1_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_1_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_1_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_1_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_1_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_1_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_1_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_1_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_1_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_1_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_1_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:24] assign _wakeups_wu_valid_T_5 = wakeups_wu_valid_REG_2; // @[rename-busytable.scala:48:{24,34}] assign wakeups_1_valid = _wakeups_wu_valid_T_5; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_inst = wakeups_wu_bits_REG_1_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_inst = wakeups_wu_bits_REG_1_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rvc = wakeups_wu_bits_REG_1_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_pc = wakeups_wu_bits_REG_1_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_0 = wakeups_wu_bits_REG_1_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_1 = wakeups_wu_bits_REG_1_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_2 = wakeups_wu_bits_REG_1_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iq_type_3 = wakeups_wu_bits_REG_1_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_0 = wakeups_wu_bits_REG_1_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_1 = wakeups_wu_bits_REG_1_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_2 = wakeups_wu_bits_REG_1_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_3 = wakeups_wu_bits_REG_1_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_4 = wakeups_wu_bits_REG_1_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_5 = wakeups_wu_bits_REG_1_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_6 = wakeups_wu_bits_REG_1_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_7 = wakeups_wu_bits_REG_1_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_8 = wakeups_wu_bits_REG_1_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fu_code_9 = wakeups_wu_bits_REG_1_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued = wakeups_wu_bits_REG_1_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dis_col_sel = wakeups_wu_bits_REG_1_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_mask = wakeups_wu_bits_REG_1_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_tag = wakeups_wu_bits_REG_1_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_br_type = wakeups_wu_bits_REG_1_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfb = wakeups_wu_bits_REG_1_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fence = wakeups_wu_bits_REG_1_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_fencei = wakeups_wu_bits_REG_1_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sfence = wakeups_wu_bits_REG_1_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_amo = wakeups_wu_bits_REG_1_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_eret = wakeups_wu_bits_REG_1_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_1_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_rocc = wakeups_wu_bits_REG_1_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_mov = wakeups_wu_bits_REG_1_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ftq_idx = wakeups_wu_bits_REG_1_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_edge_inst = wakeups_wu_bits_REG_1_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pc_lob = wakeups_wu_bits_REG_1_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_taken = wakeups_wu_bits_REG_1_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_rename = wakeups_wu_bits_REG_1_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_sel = wakeups_wu_bits_REG_1_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pimm = wakeups_wu_bits_REG_1_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_imm_packed = wakeups_wu_bits_REG_1_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op1_sel = wakeups_wu_bits_REG_1_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_op2_sel = wakeups_wu_bits_REG_1_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_1_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_1_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_1_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_1_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_1_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rob_idx = wakeups_wu_bits_REG_1_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldq_idx = wakeups_wu_bits_REG_1_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stq_idx = wakeups_wu_bits_REG_1_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_rxq_idx = wakeups_wu_bits_REG_1_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_pdst = wakeups_wu_bits_REG_1_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1 = wakeups_wu_bits_REG_1_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2 = wakeups_wu_bits_REG_1_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3 = wakeups_wu_bits_REG_1_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred = wakeups_wu_bits_REG_1_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs1_busy = wakeups_wu_bits_REG_1_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs2_busy = wakeups_wu_bits_REG_1_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_prs3_busy = wakeups_wu_bits_REG_1_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ppred_busy = wakeups_wu_bits_REG_1_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_stale_pdst = wakeups_wu_bits_REG_1_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exception = wakeups_wu_bits_REG_1_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_exc_cause = wakeups_wu_bits_REG_1_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_cmd = wakeups_wu_bits_REG_1_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_size = wakeups_wu_bits_REG_1_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_mem_signed = wakeups_wu_bits_REG_1_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_ldq = wakeups_wu_bits_REG_1_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_uses_stq = wakeups_wu_bits_REG_1_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_is_unique = wakeups_wu_bits_REG_1_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_flush_on_commit = wakeups_wu_bits_REG_1_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_csr_cmd = wakeups_wu_bits_REG_1_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_1_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_ldst = wakeups_wu_bits_REG_1_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1 = wakeups_wu_bits_REG_1_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2 = wakeups_wu_bits_REG_1_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs3 = wakeups_wu_bits_REG_1_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_dst_rtype = wakeups_wu_bits_REG_1_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_1_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_1_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_frs3_en = wakeups_wu_bits_REG_1_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_dw = wakeups_wu_bits_REG_1_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fcn_op = wakeups_wu_bits_REG_1_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_val = wakeups_wu_bits_REG_1_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_rm = wakeups_wu_bits_REG_1_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_fp_typ = wakeups_wu_bits_REG_1_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_1_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_1_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_1_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_debug_if = wakeups_wu_bits_REG_1_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_1_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_fsrc = wakeups_wu_bits_REG_1_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_1_bits_uop_debug_tsrc = wakeups_wu_bits_REG_1_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_8; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_12 = wakeups_2_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_2_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_2_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_2_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_2_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_2_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_2_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_2_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_2_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_2_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_2_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_2_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_2_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_2_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_2_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_4; // @[rename-busytable.scala:48:24] wire [1:0] _wakeups_wu_valid_T_6 = io_child_rebusys_0 & 2'h1; // @[rename-busytable.scala:27:7, :48:72] wire _wakeups_wu_valid_T_7 = _wakeups_wu_valid_T_6 == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_8 = wakeups_wu_valid_REG_4 & _wakeups_wu_valid_T_7; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_2_valid = _wakeups_wu_valid_T_8; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_inst = wakeups_wu_bits_REG_2_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_inst = wakeups_wu_bits_REG_2_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_rvc = wakeups_wu_bits_REG_2_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_pc = wakeups_wu_bits_REG_2_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_0 = wakeups_wu_bits_REG_2_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_1 = wakeups_wu_bits_REG_2_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_2 = wakeups_wu_bits_REG_2_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iq_type_3 = wakeups_wu_bits_REG_2_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_0 = wakeups_wu_bits_REG_2_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_1 = wakeups_wu_bits_REG_2_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_2 = wakeups_wu_bits_REG_2_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_3 = wakeups_wu_bits_REG_2_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_4 = wakeups_wu_bits_REG_2_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_5 = wakeups_wu_bits_REG_2_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_6 = wakeups_wu_bits_REG_2_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_7 = wakeups_wu_bits_REG_2_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_8 = wakeups_wu_bits_REG_2_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fu_code_9 = wakeups_wu_bits_REG_2_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued = wakeups_wu_bits_REG_2_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_dis_col_sel = wakeups_wu_bits_REG_2_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_mask = wakeups_wu_bits_REG_2_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_tag = wakeups_wu_bits_REG_2_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_br_type = wakeups_wu_bits_REG_2_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sfb = wakeups_wu_bits_REG_2_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_fence = wakeups_wu_bits_REG_2_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_fencei = wakeups_wu_bits_REG_2_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sfence = wakeups_wu_bits_REG_2_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_amo = wakeups_wu_bits_REG_2_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_eret = wakeups_wu_bits_REG_2_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_2_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_rocc = wakeups_wu_bits_REG_2_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_mov = wakeups_wu_bits_REG_2_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ftq_idx = wakeups_wu_bits_REG_2_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_edge_inst = wakeups_wu_bits_REG_2_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pc_lob = wakeups_wu_bits_REG_2_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_taken = wakeups_wu_bits_REG_2_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_rename = wakeups_wu_bits_REG_2_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_sel = wakeups_wu_bits_REG_2_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pimm = wakeups_wu_bits_REG_2_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_imm_packed = wakeups_wu_bits_REG_2_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_op1_sel = wakeups_wu_bits_REG_2_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_op2_sel = wakeups_wu_bits_REG_2_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_2_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_2_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_2_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_2_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_2_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_rob_idx = wakeups_wu_bits_REG_2_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldq_idx = wakeups_wu_bits_REG_2_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_stq_idx = wakeups_wu_bits_REG_2_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_rxq_idx = wakeups_wu_bits_REG_2_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_pdst = wakeups_wu_bits_REG_2_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs1 = wakeups_wu_bits_REG_2_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs2 = wakeups_wu_bits_REG_2_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs3 = wakeups_wu_bits_REG_2_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ppred = wakeups_wu_bits_REG_2_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs1_busy = wakeups_wu_bits_REG_2_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs2_busy = wakeups_wu_bits_REG_2_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_prs3_busy = wakeups_wu_bits_REG_2_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ppred_busy = wakeups_wu_bits_REG_2_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_stale_pdst = wakeups_wu_bits_REG_2_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_exception = wakeups_wu_bits_REG_2_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_exc_cause = wakeups_wu_bits_REG_2_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_cmd = wakeups_wu_bits_REG_2_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_size = wakeups_wu_bits_REG_2_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_mem_signed = wakeups_wu_bits_REG_2_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_uses_ldq = wakeups_wu_bits_REG_2_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_uses_stq = wakeups_wu_bits_REG_2_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_is_unique = wakeups_wu_bits_REG_2_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_flush_on_commit = wakeups_wu_bits_REG_2_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_csr_cmd = wakeups_wu_bits_REG_2_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_2_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_ldst = wakeups_wu_bits_REG_2_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs1 = wakeups_wu_bits_REG_2_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs2 = wakeups_wu_bits_REG_2_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs3 = wakeups_wu_bits_REG_2_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_dst_rtype = wakeups_wu_bits_REG_2_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_2_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_2_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_frs3_en = wakeups_wu_bits_REG_2_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fcn_dw = wakeups_wu_bits_REG_2_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fcn_op = wakeups_wu_bits_REG_2_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_val = wakeups_wu_bits_REG_2_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_rm = wakeups_wu_bits_REG_2_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_fp_typ = wakeups_wu_bits_REG_2_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_2_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_2_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_2_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_bp_debug_if = wakeups_wu_bits_REG_2_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_2_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_fsrc = wakeups_wu_bits_REG_2_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_2_bits_uop_debug_tsrc = wakeups_wu_bits_REG_2_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] wire _wakeups_wu_valid_T_11; // @[rename-busytable.scala:48:34] wire _busy_table_wb_T_17 = wakeups_3_valid; // @[rename-busytable.scala:47:18, :56:56] wire wakeups_3_bits_uop_iq_type_0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iq_type_3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_0; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_4; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_5; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_6; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_7; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_8; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fu_code_9; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_3_bits_uop_inst; // @[rename-busytable.scala:47:18] wire [31:0] wakeups_3_bits_uop_debug_inst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_rvc; // @[rename-busytable.scala:47:18] wire [39:0] wakeups_3_bits_uop_debug_pc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_dis_col_sel; // @[rename-busytable.scala:47:18] wire [11:0] wakeups_3_bits_uop_br_mask; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_br_tag; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_br_type; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sfb; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_fence; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_fencei; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sfence; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_amo; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_eret; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_rocc; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_mov; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_ftq_idx; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_edge_inst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_pc_lob; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_taken; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_imm_rename; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_imm_sel; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_pimm; // @[rename-busytable.scala:47:18] wire [19:0] wakeups_3_bits_uop_imm_packed; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_op1_sel; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_op2_sel; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_rob_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_ldq_idx; // @[rename-busytable.scala:47:18] wire [3:0] wakeups_3_bits_uop_stq_idx; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_rxq_idx; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_pdst; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs1; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs2; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_prs3; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_ppred; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs1_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs2_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_prs3_busy; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_ppred_busy; // @[rename-busytable.scala:47:18] wire [6:0] wakeups_3_bits_uop_stale_pdst; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_exception; // @[rename-busytable.scala:47:18] wire [63:0] wakeups_3_bits_uop_exc_cause; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_mem_cmd; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_mem_size; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_mem_signed; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_uses_ldq; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_uses_stq; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_is_unique; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_flush_on_commit; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_csr_cmd; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_ldst; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs1; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs2; // @[rename-busytable.scala:47:18] wire [5:0] wakeups_3_bits_uop_lrs3; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_dst_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_lrs1_rtype; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_lrs2_rtype; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_frs3_en; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fcn_dw; // @[rename-busytable.scala:47:18] wire [4:0] wakeups_3_bits_uop_fcn_op; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_fp_val; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_fp_rm; // @[rename-busytable.scala:47:18] wire [1:0] wakeups_3_bits_uop_fp_typ; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_bp_debug_if; // @[rename-busytable.scala:47:18] wire wakeups_3_bits_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_debug_fsrc; // @[rename-busytable.scala:47:18] wire [2:0] wakeups_3_bits_uop_debug_tsrc; // @[rename-busytable.scala:47:18] reg wakeups_wu_valid_REG_6; // @[rename-busytable.scala:48:24] wire [1:0] _wakeups_wu_valid_T_9 = io_child_rebusys_0 & 2'h2; // @[rename-busytable.scala:27:7, :48:72] wire _wakeups_wu_valid_T_10 = _wakeups_wu_valid_T_9 == 2'h0; // @[rename-busytable.scala:48:{72,92}] assign _wakeups_wu_valid_T_11 = wakeups_wu_valid_REG_6 & _wakeups_wu_valid_T_10; // @[rename-busytable.scala:48:{24,34,92}] assign wakeups_3_valid = _wakeups_wu_valid_T_11; // @[rename-busytable.scala:47:18, :48:34] reg [31:0] wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_inst = wakeups_wu_bits_REG_3_uop_inst; // @[rename-busytable.scala:47:18, :49:24] reg [31:0] wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_inst = wakeups_wu_bits_REG_3_uop_debug_inst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_rvc = wakeups_wu_bits_REG_3_uop_is_rvc; // @[rename-busytable.scala:47:18, :49:24] reg [39:0] wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_pc = wakeups_wu_bits_REG_3_uop_debug_pc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_0 = wakeups_wu_bits_REG_3_uop_iq_type_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_1 = wakeups_wu_bits_REG_3_uop_iq_type_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_2 = wakeups_wu_bits_REG_3_uop_iq_type_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iq_type_3 = wakeups_wu_bits_REG_3_uop_iq_type_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_0 = wakeups_wu_bits_REG_3_uop_fu_code_0; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_1 = wakeups_wu_bits_REG_3_uop_fu_code_1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_2 = wakeups_wu_bits_REG_3_uop_fu_code_2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_3 = wakeups_wu_bits_REG_3_uop_fu_code_3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_4 = wakeups_wu_bits_REG_3_uop_fu_code_4; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_5 = wakeups_wu_bits_REG_3_uop_fu_code_5; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_6 = wakeups_wu_bits_REG_3_uop_fu_code_6; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_7 = wakeups_wu_bits_REG_3_uop_fu_code_7; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_8 = wakeups_wu_bits_REG_3_uop_fu_code_8; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fu_code_9 = wakeups_wu_bits_REG_3_uop_fu_code_9; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued = wakeups_wu_bits_REG_3_uop_iw_issued; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued_partial_agen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_issued_partial_dgen = wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p1_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p2_speculative_child = wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p1_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p2_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_iw_p3_bypass_hint = wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_dis_col_sel = wakeups_wu_bits_REG_3_uop_dis_col_sel; // @[rename-busytable.scala:47:18, :49:24] reg [11:0] wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_mask = wakeups_wu_bits_REG_3_uop_br_mask; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_tag = wakeups_wu_bits_REG_3_uop_br_tag; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_br_type = wakeups_wu_bits_REG_3_uop_br_type; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sfb = wakeups_wu_bits_REG_3_uop_is_sfb; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_fence = wakeups_wu_bits_REG_3_uop_is_fence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_fencei = wakeups_wu_bits_REG_3_uop_is_fencei; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sfence = wakeups_wu_bits_REG_3_uop_is_sfence; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_amo = wakeups_wu_bits_REG_3_uop_is_amo; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_eret = wakeups_wu_bits_REG_3_uop_is_eret; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_sys_pc2epc = wakeups_wu_bits_REG_3_uop_is_sys_pc2epc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_rocc = wakeups_wu_bits_REG_3_uop_is_rocc; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_mov = wakeups_wu_bits_REG_3_uop_is_mov; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ftq_idx = wakeups_wu_bits_REG_3_uop_ftq_idx; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_edge_inst = wakeups_wu_bits_REG_3_uop_edge_inst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pc_lob = wakeups_wu_bits_REG_3_uop_pc_lob; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_taken = wakeups_wu_bits_REG_3_uop_taken; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_rename = wakeups_wu_bits_REG_3_uop_imm_rename; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_sel = wakeups_wu_bits_REG_3_uop_imm_sel; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pimm = wakeups_wu_bits_REG_3_uop_pimm; // @[rename-busytable.scala:47:18, :49:24] reg [19:0] wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_imm_packed = wakeups_wu_bits_REG_3_uop_imm_packed; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_op1_sel = wakeups_wu_bits_REG_3_uop_op1_sel; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_op2_sel = wakeups_wu_bits_REG_3_uop_op2_sel; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ldst = wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_wen = wakeups_wu_bits_REG_3_uop_fp_ctrl_wen; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren1 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren2 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_ren3 = wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_swap12 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_swap23 = wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_typeTagIn = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_typeTagOut = wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fromint = wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_toint = wakeups_wu_bits_REG_3_uop_fp_ctrl_toint; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fastpipe = wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_fma = wakeups_wu_bits_REG_3_uop_fp_ctrl_fma; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_div = wakeups_wu_bits_REG_3_uop_fp_ctrl_div; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_sqrt = wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_wflags = wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_ctrl_vec = wakeups_wu_bits_REG_3_uop_fp_ctrl_vec; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_rob_idx = wakeups_wu_bits_REG_3_uop_rob_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldq_idx = wakeups_wu_bits_REG_3_uop_ldq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [3:0] wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_stq_idx = wakeups_wu_bits_REG_3_uop_stq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_rxq_idx = wakeups_wu_bits_REG_3_uop_rxq_idx; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_pdst = wakeups_wu_bits_REG_3_uop_pdst; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs1 = wakeups_wu_bits_REG_3_uop_prs1; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs2 = wakeups_wu_bits_REG_3_uop_prs2; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs3 = wakeups_wu_bits_REG_3_uop_prs3; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ppred = wakeups_wu_bits_REG_3_uop_ppred; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs1_busy = wakeups_wu_bits_REG_3_uop_prs1_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs2_busy = wakeups_wu_bits_REG_3_uop_prs2_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_prs3_busy = wakeups_wu_bits_REG_3_uop_prs3_busy; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ppred_busy = wakeups_wu_bits_REG_3_uop_ppred_busy; // @[rename-busytable.scala:47:18, :49:24] reg [6:0] wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_stale_pdst = wakeups_wu_bits_REG_3_uop_stale_pdst; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_exception = wakeups_wu_bits_REG_3_uop_exception; // @[rename-busytable.scala:47:18, :49:24] reg [63:0] wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_exc_cause = wakeups_wu_bits_REG_3_uop_exc_cause; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_cmd = wakeups_wu_bits_REG_3_uop_mem_cmd; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_size = wakeups_wu_bits_REG_3_uop_mem_size; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_mem_signed = wakeups_wu_bits_REG_3_uop_mem_signed; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_uses_ldq = wakeups_wu_bits_REG_3_uop_uses_ldq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_uses_stq = wakeups_wu_bits_REG_3_uop_uses_stq; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_is_unique = wakeups_wu_bits_REG_3_uop_is_unique; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_flush_on_commit = wakeups_wu_bits_REG_3_uop_flush_on_commit; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_csr_cmd = wakeups_wu_bits_REG_3_uop_csr_cmd; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldst_is_rs1 = wakeups_wu_bits_REG_3_uop_ldst_is_rs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_ldst = wakeups_wu_bits_REG_3_uop_ldst; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs1 = wakeups_wu_bits_REG_3_uop_lrs1; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs2 = wakeups_wu_bits_REG_3_uop_lrs2; // @[rename-busytable.scala:47:18, :49:24] reg [5:0] wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs3 = wakeups_wu_bits_REG_3_uop_lrs3; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_dst_rtype = wakeups_wu_bits_REG_3_uop_dst_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs1_rtype = wakeups_wu_bits_REG_3_uop_lrs1_rtype; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_lrs2_rtype = wakeups_wu_bits_REG_3_uop_lrs2_rtype; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_frs3_en = wakeups_wu_bits_REG_3_uop_frs3_en; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fcn_dw = wakeups_wu_bits_REG_3_uop_fcn_dw; // @[rename-busytable.scala:47:18, :49:24] reg [4:0] wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fcn_op = wakeups_wu_bits_REG_3_uop_fcn_op; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_val = wakeups_wu_bits_REG_3_uop_fp_val; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_rm = wakeups_wu_bits_REG_3_uop_fp_rm; // @[rename-busytable.scala:47:18, :49:24] reg [1:0] wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_fp_typ = wakeups_wu_bits_REG_3_uop_fp_typ; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_pf_if = wakeups_wu_bits_REG_3_uop_xcpt_pf_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_ae_if = wakeups_wu_bits_REG_3_uop_xcpt_ae_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_xcpt_ma_if = wakeups_wu_bits_REG_3_uop_xcpt_ma_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_bp_debug_if = wakeups_wu_bits_REG_3_uop_bp_debug_if; // @[rename-busytable.scala:47:18, :49:24] reg wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_bp_xcpt_if = wakeups_wu_bits_REG_3_uop_bp_xcpt_if; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_fsrc = wakeups_wu_bits_REG_3_uop_debug_fsrc; // @[rename-busytable.scala:47:18, :49:24] reg [2:0] wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:49:24] assign wakeups_3_bits_uop_debug_tsrc = wakeups_wu_bits_REG_3_uop_debug_tsrc; // @[rename-busytable.scala:47:18, :49:24] reg [79:0] busy_table; // @[rename-busytable.scala:53:27] assign io_debug_busytable = busy_table; // @[rename-busytable.scala:27:7, :53:27] wire [127:0] _GEN = 128'h1 << wakeups_0_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T; // @[OneHot.scala:58:35] assign _busy_table_wb_T = _GEN; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_8; // @[OneHot.scala:58:35] assign _busy_table_next_T_8 = _GEN; // @[OneHot.scala:58:35] wire _busy_table_wb_T_1 = ~wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :56:59] wire _busy_table_wb_T_2 = wakeups_0_valid & _busy_table_wb_T_1; // @[rename-busytable.scala:47:18, :56:{56,59}] wire [79:0] _busy_table_wb_T_3 = {80{_busy_table_wb_T_2}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_4 = {48'h0, _busy_table_wb_T[79:0] & _busy_table_wb_T_3}; // @[OneHot.scala:58:35] wire [127:0] _GEN_0 = 128'h1 << wakeups_1_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_5; // @[OneHot.scala:58:35] assign _busy_table_wb_T_5 = _GEN_0; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_12; // @[OneHot.scala:58:35] assign _busy_table_next_T_12 = _GEN_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_8 = {80{_busy_table_wb_T_7}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_9 = {48'h0, _busy_table_wb_T_5[79:0] & _busy_table_wb_T_8}; // @[OneHot.scala:58:35] wire [127:0] _GEN_1 = 128'h1 << wakeups_2_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_10; // @[OneHot.scala:58:35] assign _busy_table_wb_T_10 = _GEN_1; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_16; // @[OneHot.scala:58:35] assign _busy_table_next_T_16 = _GEN_1; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_13 = {80{_busy_table_wb_T_12}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_14 = {48'h0, _busy_table_wb_T_10[79:0] & _busy_table_wb_T_13}; // @[OneHot.scala:58:35] wire [127:0] _GEN_2 = 128'h1 << wakeups_3_bits_uop_pdst; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_15; // @[OneHot.scala:58:35] assign _busy_table_wb_T_15 = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_20; // @[OneHot.scala:58:35] assign _busy_table_next_T_20 = _GEN_2; // @[OneHot.scala:58:35] wire [79:0] _busy_table_wb_T_18 = {80{_busy_table_wb_T_17}}; // @[rename-busytable.scala:56:{37,56}] wire [127:0] _busy_table_wb_T_19 = {48'h0, _busy_table_wb_T_15[79:0] & _busy_table_wb_T_18}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_wb_T_20 = _busy_table_wb_T_4 | _busy_table_wb_T_9; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_21 = _busy_table_wb_T_20 | _busy_table_wb_T_14; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_22 = _busy_table_wb_T_21 | _busy_table_wb_T_19; // @[rename-busytable.scala:56:31, :57:14] wire [127:0] _busy_table_wb_T_23 = ~_busy_table_wb_T_22; // @[rename-busytable.scala:55:36, :57:14] wire [127:0] busy_table_wb = {48'h0, _busy_table_wb_T_23[79:0] & busy_table}; // @[rename-busytable.scala:53:27, :55:{34,36}, :56:31] wire [127:0] _busy_table_next_T = 128'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_next_T_1 = {80{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_2 = {48'h0, _busy_table_next_T[79:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_3 = 128'h1 << io_ren_uops_1_pdst_0; // @[OneHot.scala:58:35] wire [79:0] _busy_table_next_T_4 = {80{io_rebusy_reqs_1_0}}; // @[rename-busytable.scala:27:7, :61:57] wire [127:0] _busy_table_next_T_5 = {48'h0, _busy_table_next_T_3[79:0] & _busy_table_next_T_4}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_6 = _busy_table_next_T_2 | _busy_table_next_T_5; // @[rename-busytable.scala:61:{51,82}] wire [127:0] _busy_table_next_T_7 = busy_table_wb | _busy_table_next_T_6; // @[rename-busytable.scala:55:34, :59:39, :61:82] wire _GEN_3 = wakeups_0_valid & wakeups_0_bits_rebusy; // @[rename-busytable.scala:47:18, :63:56] wire _busy_table_next_T_9; // @[rename-busytable.scala:63:56] assign _busy_table_next_T_9 = _GEN_3; // @[rename-busytable.scala:63:56] wire _io_busy_resps_0_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_0_prs1_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_0_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_0_prs2_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_0_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_0_prs3_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :85:82] wire _io_busy_resps_1_prs1_busy_T_2; // @[rename-busytable.scala:79:82] assign _io_busy_resps_1_prs1_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :79:82] wire _io_busy_resps_1_prs2_busy_T_2; // @[rename-busytable.scala:82:82] assign _io_busy_resps_1_prs2_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :82:82] wire _io_busy_resps_1_prs3_busy_T_2; // @[rename-busytable.scala:85:82] assign _io_busy_resps_1_prs3_busy_T_2 = _GEN_3; // @[rename-busytable.scala:63:56, :85:82] wire [79:0] _busy_table_next_T_10 = {80{_busy_table_next_T_9}}; // @[rename-busytable.scala:63:{37,56}] wire [127:0] _busy_table_next_T_11 = {48'h0, _busy_table_next_T_8[79:0] & _busy_table_next_T_10}; // @[OneHot.scala:58:35] wire [127:0] _busy_table_next_T_24 = _busy_table_next_T_11; // @[rename-busytable.scala:63:31, :64:14] wire [127:0] _busy_table_next_T_25 = _busy_table_next_T_24; // @[rename-busytable.scala:64:14] wire [127:0] _busy_table_next_T_26 = _busy_table_next_T_25; // @[rename-busytable.scala:64:14] wire [127:0] busy_table_next = _busy_table_next_T_7 | _busy_table_next_T_26; // @[rename-busytable.scala:59:39, :62:5, :64:14] wire _prs1_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0 = wakeups_0_valid & _prs1_match_T; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1 = wakeups_1_valid & _prs1_match_T_1; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_2 = wakeups_2_valid & _prs1_match_T_2; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_3 = wakeups_3_valid & _prs1_match_T_3; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0 = wakeups_0_valid & _prs2_match_T; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1 = wakeups_1_valid & _prs2_match_T_1; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_2 = wakeups_2_valid & _prs2_match_T_2; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_3 = wakeups_3_valid & _prs2_match_T_3; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T = wakeups_0_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0 = wakeups_0_valid & _prs3_match_T; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_1 = wakeups_1_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1 = wakeups_1_valid & _prs3_match_T_1; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_2 = wakeups_2_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_2 = wakeups_2_valid & _prs3_match_T_2; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_3 = wakeups_3_bits_uop_pdst == io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_3 = wakeups_3_valid & _prs3_match_T_3; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [79:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [79:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [79:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_0_prs1_busy_T_6 = prs1_match_0 & _io_busy_resps_0_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_10 = _io_busy_resps_0_prs1_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_11 = _io_busy_resps_0_prs1_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_T_12 = _io_busy_resps_0_prs1_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs1_busy_WIRE = _io_busy_resps_0_prs1_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_0_prs1_busy_0 = prs1_match_0 | prs1_match_1 | prs1_match_2 | prs1_match_3 ? _io_busy_resps_0_prs1_busy_WIRE : _io_busy_resps_0_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_6 = prs2_match_0 & _io_busy_resps_0_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_10 = _io_busy_resps_0_prs2_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_11 = _io_busy_resps_0_prs2_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_T_12 = _io_busy_resps_0_prs2_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs2_busy_WIRE = _io_busy_resps_0_prs2_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_0_prs2_busy_0 = prs2_match_0 | prs2_match_1 | prs2_match_2 | prs2_match_3 ? _io_busy_resps_0_prs2_busy_WIRE : _io_busy_resps_0_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_6 = prs3_match_0 & _io_busy_resps_0_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_10 = _io_busy_resps_0_prs3_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_11 = _io_busy_resps_0_prs3_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_T_12 = _io_busy_resps_0_prs3_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_0_prs3_busy_WIRE = _io_busy_resps_0_prs3_busy_T_12; // @[Mux.scala:30:73] wire _prs1_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_0_1 = wakeups_0_valid & _prs1_match_T_4; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_1_1 = wakeups_1_valid & _prs1_match_T_5; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_2_1 = wakeups_2_valid & _prs1_match_T_6; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs1_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :47:18, :70:68] wire prs1_match_3_1 = wakeups_3_valid & _prs1_match_T_7; // @[rename-busytable.scala:47:18, :70:{49,68}] wire _prs2_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_0_1 = wakeups_0_valid & _prs2_match_T_4; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_1_1 = wakeups_1_valid & _prs2_match_T_5; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_2_1 = wakeups_2_valid & _prs2_match_T_6; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs2_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :47:18, :71:68] wire prs2_match_3_1 = wakeups_3_valid & _prs2_match_T_7; // @[rename-busytable.scala:47:18, :71:{49,68}] wire _prs3_match_T_4 = wakeups_0_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_0_1 = wakeups_0_valid & _prs3_match_T_4; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_5 = wakeups_1_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_1_1 = wakeups_1_valid & _prs3_match_T_5; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_6 = wakeups_2_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_2_1 = wakeups_2_valid & _prs3_match_T_6; // @[rename-busytable.scala:47:18, :72:{49,68}] wire _prs3_match_T_7 = wakeups_3_bits_uop_pdst == io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :47:18, :72:68] wire prs3_match_3_1 = wakeups_3_valid & _prs3_match_T_7; // @[rename-busytable.scala:47:18, :72:{49,68}] wire [79:0] _io_busy_resps_1_prs1_busy_T = busy_table >> io_ren_uops_1_prs1_0; // @[rename-busytable.scala:27:7, :53:27, :74:45] wire _io_busy_resps_1_prs1_busy_T_1 = _io_busy_resps_1_prs1_busy_T[0]; // @[rename-busytable.scala:74:45] wire [79:0] _io_busy_resps_1_prs2_busy_T = busy_table >> io_ren_uops_1_prs2_0; // @[rename-busytable.scala:27:7, :53:27, :75:45] wire _io_busy_resps_1_prs2_busy_T_1 = _io_busy_resps_1_prs2_busy_T[0]; // @[rename-busytable.scala:75:45] wire [79:0] _io_busy_resps_1_prs3_busy_T = busy_table >> io_ren_uops_1_prs3_0; // @[rename-busytable.scala:27:7, :53:27, :76:45] wire _io_busy_resps_1_prs3_busy_T_1 = _io_busy_resps_1_prs3_busy_T[0]; // @[rename-busytable.scala:76:45] wire _io_busy_resps_1_prs1_busy_T_6 = prs1_match_0_1 & _io_busy_resps_1_prs1_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_10 = _io_busy_resps_1_prs1_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_11 = _io_busy_resps_1_prs1_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_T_12 = _io_busy_resps_1_prs1_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs1_busy_WIRE = _io_busy_resps_1_prs1_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_1_prs1_busy_0 = prs1_match_0_1 | prs1_match_1_1 | prs1_match_2_1 | prs1_match_3_1 ? _io_busy_resps_1_prs1_busy_WIRE : _io_busy_resps_1_prs1_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_6 = prs2_match_0_1 & _io_busy_resps_1_prs2_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_10 = _io_busy_resps_1_prs2_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_11 = _io_busy_resps_1_prs2_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_T_12 = _io_busy_resps_1_prs2_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs2_busy_WIRE = _io_busy_resps_1_prs2_busy_T_12; // @[Mux.scala:30:73] assign io_busy_resps_1_prs2_busy_0 = prs2_match_0_1 | prs2_match_1_1 | prs2_match_2_1 | prs2_match_3_1 ? _io_busy_resps_1_prs2_busy_WIRE : _io_busy_resps_1_prs2_busy_T_1; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_6 = prs3_match_0_1 & _io_busy_resps_1_prs3_busy_T_2; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_10 = _io_busy_resps_1_prs3_busy_T_6; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_11 = _io_busy_resps_1_prs3_busy_T_10; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_T_12 = _io_busy_resps_1_prs3_busy_T_11; // @[Mux.scala:30:73] wire _io_busy_resps_1_prs3_busy_WIRE = _io_busy_resps_1_prs3_busy_T_12; // @[Mux.scala:30:73] always @(posedge clock) begin // @[rename-busytable.scala:27:7] wakeups_wu_valid_REG <= io_wakeups_0_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_valid_REG_1 <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :48:46] wakeups_wu_bits_REG_uop_inst <= io_wakeups_0_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_inst <= io_wakeups_0_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rvc <= io_wakeups_0_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_pc <= io_wakeups_0_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_0 <= io_wakeups_0_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_1 <= io_wakeups_0_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_2 <= io_wakeups_0_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iq_type_3 <= io_wakeups_0_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_0 <= io_wakeups_0_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_1 <= io_wakeups_0_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_2 <= io_wakeups_0_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_3 <= io_wakeups_0_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_4 <= io_wakeups_0_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_5 <= io_wakeups_0_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_6 <= io_wakeups_0_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_7 <= io_wakeups_0_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_8 <= io_wakeups_0_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fu_code_9 <= io_wakeups_0_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued <= io_wakeups_0_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_agen <= io_wakeups_0_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_issued_partial_dgen <= io_wakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_speculative_child <= io_wakeups_0_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_speculative_child <= io_wakeups_0_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p1_bypass_hint <= io_wakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p2_bypass_hint <= io_wakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_iw_p3_bypass_hint <= io_wakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dis_col_sel <= io_wakeups_0_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_mask <= io_wakeups_0_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_tag <= io_wakeups_0_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_br_type <= io_wakeups_0_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfb <= io_wakeups_0_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fence <= io_wakeups_0_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_fencei <= io_wakeups_0_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sfence <= io_wakeups_0_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_amo <= io_wakeups_0_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_eret <= io_wakeups_0_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_sys_pc2epc <= io_wakeups_0_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_rocc <= io_wakeups_0_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_mov <= io_wakeups_0_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ftq_idx <= io_wakeups_0_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_edge_inst <= io_wakeups_0_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pc_lob <= io_wakeups_0_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_taken <= io_wakeups_0_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_rename <= io_wakeups_0_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_sel <= io_wakeups_0_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pimm <= io_wakeups_0_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_imm_packed <= io_wakeups_0_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op1_sel <= io_wakeups_0_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_op2_sel <= io_wakeups_0_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ldst <= io_wakeups_0_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wen <= io_wakeups_0_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren1 <= io_wakeups_0_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren2 <= io_wakeups_0_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_ren3 <= io_wakeups_0_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap12 <= io_wakeups_0_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_swap23 <= io_wakeups_0_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagIn <= io_wakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_typeTagOut <= io_wakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fromint <= io_wakeups_0_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_toint <= io_wakeups_0_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fastpipe <= io_wakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_fma <= io_wakeups_0_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_div <= io_wakeups_0_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_sqrt <= io_wakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_wflags <= io_wakeups_0_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_ctrl_vec <= io_wakeups_0_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rob_idx <= io_wakeups_0_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldq_idx <= io_wakeups_0_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stq_idx <= io_wakeups_0_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_rxq_idx <= io_wakeups_0_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_pdst <= io_wakeups_0_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1 <= io_wakeups_0_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2 <= io_wakeups_0_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3 <= io_wakeups_0_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred <= io_wakeups_0_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs1_busy <= io_wakeups_0_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs2_busy <= io_wakeups_0_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_prs3_busy <= io_wakeups_0_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ppred_busy <= io_wakeups_0_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_stale_pdst <= io_wakeups_0_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exception <= io_wakeups_0_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_exc_cause <= io_wakeups_0_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_cmd <= io_wakeups_0_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_size <= io_wakeups_0_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_mem_signed <= io_wakeups_0_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_ldq <= io_wakeups_0_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_uses_stq <= io_wakeups_0_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_is_unique <= io_wakeups_0_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_flush_on_commit <= io_wakeups_0_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_csr_cmd <= io_wakeups_0_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst_is_rs1 <= io_wakeups_0_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_ldst <= io_wakeups_0_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1 <= io_wakeups_0_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2 <= io_wakeups_0_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs3 <= io_wakeups_0_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_dst_rtype <= io_wakeups_0_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs1_rtype <= io_wakeups_0_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_lrs2_rtype <= io_wakeups_0_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_frs3_en <= io_wakeups_0_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_dw <= io_wakeups_0_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fcn_op <= io_wakeups_0_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_val <= io_wakeups_0_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_rm <= io_wakeups_0_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_fp_typ <= io_wakeups_0_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_pf_if <= io_wakeups_0_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ae_if <= io_wakeups_0_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_xcpt_ma_if <= io_wakeups_0_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_debug_if <= io_wakeups_0_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_bp_xcpt_if <= io_wakeups_0_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_fsrc <= io_wakeups_0_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_uop_debug_tsrc <= io_wakeups_0_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_bypassable <= io_wakeups_0_bits_bypassable_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_speculative_mask <= io_wakeups_0_bits_speculative_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_rebusy <= io_wakeups_0_bits_rebusy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_2 <= io_wakeups_1_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_1_uop_inst <= io_wakeups_1_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_inst <= io_wakeups_1_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rvc <= io_wakeups_1_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_pc <= io_wakeups_1_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_0 <= io_wakeups_1_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_1 <= io_wakeups_1_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_2 <= io_wakeups_1_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iq_type_3 <= io_wakeups_1_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_0 <= io_wakeups_1_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_1 <= io_wakeups_1_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_2 <= io_wakeups_1_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_3 <= io_wakeups_1_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_4 <= io_wakeups_1_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_5 <= io_wakeups_1_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_6 <= io_wakeups_1_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_7 <= io_wakeups_1_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_8 <= io_wakeups_1_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fu_code_9 <= io_wakeups_1_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued <= io_wakeups_1_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_agen <= io_wakeups_1_bits_uop_iw_issued_partial_agen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_issued_partial_dgen <= io_wakeups_1_bits_uop_iw_issued_partial_dgen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_speculative_child <= io_wakeups_1_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_speculative_child <= io_wakeups_1_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p1_bypass_hint <= io_wakeups_1_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p2_bypass_hint <= io_wakeups_1_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_iw_p3_bypass_hint <= io_wakeups_1_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dis_col_sel <= io_wakeups_1_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_mask <= io_wakeups_1_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_tag <= io_wakeups_1_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_br_type <= io_wakeups_1_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfb <= io_wakeups_1_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fence <= io_wakeups_1_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_fencei <= io_wakeups_1_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sfence <= io_wakeups_1_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_amo <= io_wakeups_1_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_eret <= io_wakeups_1_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_sys_pc2epc <= io_wakeups_1_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_rocc <= io_wakeups_1_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_mov <= io_wakeups_1_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ftq_idx <= io_wakeups_1_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_edge_inst <= io_wakeups_1_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pc_lob <= io_wakeups_1_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_taken <= io_wakeups_1_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_rename <= io_wakeups_1_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_sel <= io_wakeups_1_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pimm <= io_wakeups_1_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_imm_packed <= io_wakeups_1_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op1_sel <= io_wakeups_1_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_op2_sel <= io_wakeups_1_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ldst <= io_wakeups_1_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wen <= io_wakeups_1_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren1 <= io_wakeups_1_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren2 <= io_wakeups_1_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_ren3 <= io_wakeups_1_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap12 <= io_wakeups_1_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_swap23 <= io_wakeups_1_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagIn <= io_wakeups_1_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_typeTagOut <= io_wakeups_1_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fromint <= io_wakeups_1_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_toint <= io_wakeups_1_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fastpipe <= io_wakeups_1_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_fma <= io_wakeups_1_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_div <= io_wakeups_1_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_sqrt <= io_wakeups_1_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_wflags <= io_wakeups_1_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_ctrl_vec <= io_wakeups_1_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rob_idx <= io_wakeups_1_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldq_idx <= io_wakeups_1_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stq_idx <= io_wakeups_1_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_rxq_idx <= io_wakeups_1_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_pdst <= io_wakeups_1_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1 <= io_wakeups_1_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2 <= io_wakeups_1_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3 <= io_wakeups_1_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred <= io_wakeups_1_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs1_busy <= io_wakeups_1_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs2_busy <= io_wakeups_1_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_prs3_busy <= io_wakeups_1_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ppred_busy <= io_wakeups_1_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_stale_pdst <= io_wakeups_1_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exception <= io_wakeups_1_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_exc_cause <= io_wakeups_1_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_cmd <= io_wakeups_1_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_size <= io_wakeups_1_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_mem_signed <= io_wakeups_1_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_ldq <= io_wakeups_1_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_uses_stq <= io_wakeups_1_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_is_unique <= io_wakeups_1_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_flush_on_commit <= io_wakeups_1_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_csr_cmd <= io_wakeups_1_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst_is_rs1 <= io_wakeups_1_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_ldst <= io_wakeups_1_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1 <= io_wakeups_1_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2 <= io_wakeups_1_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs3 <= io_wakeups_1_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_dst_rtype <= io_wakeups_1_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs1_rtype <= io_wakeups_1_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_lrs2_rtype <= io_wakeups_1_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_frs3_en <= io_wakeups_1_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_dw <= io_wakeups_1_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fcn_op <= io_wakeups_1_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_val <= io_wakeups_1_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_rm <= io_wakeups_1_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_fp_typ <= io_wakeups_1_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_pf_if <= io_wakeups_1_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ae_if <= io_wakeups_1_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_xcpt_ma_if <= io_wakeups_1_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_debug_if <= io_wakeups_1_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_bp_xcpt_if <= io_wakeups_1_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_fsrc <= io_wakeups_1_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_1_uop_debug_tsrc <= io_wakeups_1_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_4 <= io_wakeups_2_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_2_uop_inst <= io_wakeups_2_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_inst <= io_wakeups_2_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_rvc <= io_wakeups_2_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_pc <= io_wakeups_2_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_0 <= io_wakeups_2_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_1 <= io_wakeups_2_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_2 <= io_wakeups_2_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iq_type_3 <= io_wakeups_2_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_0 <= io_wakeups_2_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_1 <= io_wakeups_2_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_2 <= io_wakeups_2_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_3 <= io_wakeups_2_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_4 <= io_wakeups_2_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_5 <= io_wakeups_2_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_6 <= io_wakeups_2_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_7 <= io_wakeups_2_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_8 <= io_wakeups_2_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fu_code_9 <= io_wakeups_2_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_issued <= io_wakeups_2_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_2_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_2_uop_iw_p1_speculative_child <= io_wakeups_2_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p2_speculative_child <= io_wakeups_2_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p1_bypass_hint <= io_wakeups_2_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p2_bypass_hint <= io_wakeups_2_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_iw_p3_bypass_hint <= io_wakeups_2_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_dis_col_sel <= io_wakeups_2_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_mask <= io_wakeups_2_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_tag <= io_wakeups_2_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_br_type <= io_wakeups_2_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sfb <= io_wakeups_2_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_fence <= io_wakeups_2_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_fencei <= io_wakeups_2_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sfence <= io_wakeups_2_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_amo <= io_wakeups_2_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_eret <= io_wakeups_2_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_sys_pc2epc <= io_wakeups_2_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_rocc <= io_wakeups_2_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_mov <= io_wakeups_2_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ftq_idx <= io_wakeups_2_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_edge_inst <= io_wakeups_2_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pc_lob <= io_wakeups_2_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_taken <= io_wakeups_2_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_rename <= io_wakeups_2_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_sel <= io_wakeups_2_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pimm <= io_wakeups_2_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_imm_packed <= io_wakeups_2_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_op1_sel <= io_wakeups_2_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_op2_sel <= io_wakeups_2_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ldst <= io_wakeups_2_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_wen <= io_wakeups_2_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren1 <= io_wakeups_2_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren2 <= io_wakeups_2_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_ren3 <= io_wakeups_2_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_swap12 <= io_wakeups_2_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_swap23 <= io_wakeups_2_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagIn <= io_wakeups_2_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_typeTagOut <= io_wakeups_2_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fromint <= io_wakeups_2_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_toint <= io_wakeups_2_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fastpipe <= io_wakeups_2_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_fma <= io_wakeups_2_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_div <= io_wakeups_2_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_sqrt <= io_wakeups_2_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_wflags <= io_wakeups_2_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_ctrl_vec <= io_wakeups_2_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_rob_idx <= io_wakeups_2_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldq_idx <= io_wakeups_2_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_stq_idx <= io_wakeups_2_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_rxq_idx <= io_wakeups_2_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_pdst <= io_wakeups_2_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs1 <= io_wakeups_2_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs2 <= io_wakeups_2_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs3 <= io_wakeups_2_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ppred <= io_wakeups_2_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs1_busy <= io_wakeups_2_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs2_busy <= io_wakeups_2_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_prs3_busy <= io_wakeups_2_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ppred_busy <= io_wakeups_2_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_stale_pdst <= io_wakeups_2_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_exception <= io_wakeups_2_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_exc_cause <= io_wakeups_2_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_cmd <= io_wakeups_2_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_size <= io_wakeups_2_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_mem_signed <= io_wakeups_2_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_uses_ldq <= io_wakeups_2_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_uses_stq <= io_wakeups_2_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_is_unique <= io_wakeups_2_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_flush_on_commit <= io_wakeups_2_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_csr_cmd <= io_wakeups_2_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldst_is_rs1 <= io_wakeups_2_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_ldst <= io_wakeups_2_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs1 <= io_wakeups_2_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs2 <= io_wakeups_2_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs3 <= io_wakeups_2_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_dst_rtype <= io_wakeups_2_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs1_rtype <= io_wakeups_2_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_lrs2_rtype <= io_wakeups_2_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_frs3_en <= io_wakeups_2_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fcn_dw <= io_wakeups_2_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fcn_op <= io_wakeups_2_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_val <= io_wakeups_2_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_rm <= io_wakeups_2_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_fp_typ <= io_wakeups_2_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_pf_if <= io_wakeups_2_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_ae_if <= io_wakeups_2_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_xcpt_ma_if <= io_wakeups_2_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_bp_debug_if <= io_wakeups_2_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_bp_xcpt_if <= io_wakeups_2_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_fsrc <= io_wakeups_2_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_2_uop_debug_tsrc <= io_wakeups_2_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_valid_REG_6 <= io_wakeups_3_valid_0; // @[rename-busytable.scala:27:7, :48:24] wakeups_wu_bits_REG_3_uop_inst <= io_wakeups_3_bits_uop_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_inst <= io_wakeups_3_bits_uop_debug_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_rvc <= io_wakeups_3_bits_uop_is_rvc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_pc <= io_wakeups_3_bits_uop_debug_pc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_0 <= io_wakeups_3_bits_uop_iq_type_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_1 <= io_wakeups_3_bits_uop_iq_type_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_2 <= io_wakeups_3_bits_uop_iq_type_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iq_type_3 <= io_wakeups_3_bits_uop_iq_type_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_0 <= io_wakeups_3_bits_uop_fu_code_0_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_1 <= io_wakeups_3_bits_uop_fu_code_1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_2 <= io_wakeups_3_bits_uop_fu_code_2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_3 <= io_wakeups_3_bits_uop_fu_code_3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_4 <= io_wakeups_3_bits_uop_fu_code_4_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_5 <= io_wakeups_3_bits_uop_fu_code_5_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_6 <= io_wakeups_3_bits_uop_fu_code_6_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_7 <= io_wakeups_3_bits_uop_fu_code_7_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_8 <= io_wakeups_3_bits_uop_fu_code_8_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fu_code_9 <= io_wakeups_3_bits_uop_fu_code_9_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_issued <= io_wakeups_3_bits_uop_iw_issued_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_issued_partial_agen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_3_uop_iw_issued_partial_dgen <= 1'h0; // @[rename-busytable.scala:49:24] wakeups_wu_bits_REG_3_uop_iw_p1_speculative_child <= io_wakeups_3_bits_uop_iw_p1_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p2_speculative_child <= io_wakeups_3_bits_uop_iw_p2_speculative_child_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p1_bypass_hint <= io_wakeups_3_bits_uop_iw_p1_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p2_bypass_hint <= io_wakeups_3_bits_uop_iw_p2_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_iw_p3_bypass_hint <= io_wakeups_3_bits_uop_iw_p3_bypass_hint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_dis_col_sel <= io_wakeups_3_bits_uop_dis_col_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_mask <= io_wakeups_3_bits_uop_br_mask_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_tag <= io_wakeups_3_bits_uop_br_tag_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_br_type <= io_wakeups_3_bits_uop_br_type_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sfb <= io_wakeups_3_bits_uop_is_sfb_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_fence <= io_wakeups_3_bits_uop_is_fence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_fencei <= io_wakeups_3_bits_uop_is_fencei_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sfence <= io_wakeups_3_bits_uop_is_sfence_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_amo <= io_wakeups_3_bits_uop_is_amo_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_eret <= io_wakeups_3_bits_uop_is_eret_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_sys_pc2epc <= io_wakeups_3_bits_uop_is_sys_pc2epc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_rocc <= io_wakeups_3_bits_uop_is_rocc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_mov <= io_wakeups_3_bits_uop_is_mov_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ftq_idx <= io_wakeups_3_bits_uop_ftq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_edge_inst <= io_wakeups_3_bits_uop_edge_inst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pc_lob <= io_wakeups_3_bits_uop_pc_lob_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_taken <= io_wakeups_3_bits_uop_taken_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_rename <= io_wakeups_3_bits_uop_imm_rename_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_sel <= io_wakeups_3_bits_uop_imm_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pimm <= io_wakeups_3_bits_uop_pimm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_imm_packed <= io_wakeups_3_bits_uop_imm_packed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_op1_sel <= io_wakeups_3_bits_uop_op1_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_op2_sel <= io_wakeups_3_bits_uop_op2_sel_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ldst <= io_wakeups_3_bits_uop_fp_ctrl_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_wen <= io_wakeups_3_bits_uop_fp_ctrl_wen_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren1 <= io_wakeups_3_bits_uop_fp_ctrl_ren1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren2 <= io_wakeups_3_bits_uop_fp_ctrl_ren2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_ren3 <= io_wakeups_3_bits_uop_fp_ctrl_ren3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_swap12 <= io_wakeups_3_bits_uop_fp_ctrl_swap12_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_swap23 <= io_wakeups_3_bits_uop_fp_ctrl_swap23_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagIn <= io_wakeups_3_bits_uop_fp_ctrl_typeTagIn_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_typeTagOut <= io_wakeups_3_bits_uop_fp_ctrl_typeTagOut_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fromint <= io_wakeups_3_bits_uop_fp_ctrl_fromint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_toint <= io_wakeups_3_bits_uop_fp_ctrl_toint_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fastpipe <= io_wakeups_3_bits_uop_fp_ctrl_fastpipe_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_fma <= io_wakeups_3_bits_uop_fp_ctrl_fma_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_div <= io_wakeups_3_bits_uop_fp_ctrl_div_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_sqrt <= io_wakeups_3_bits_uop_fp_ctrl_sqrt_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_wflags <= io_wakeups_3_bits_uop_fp_ctrl_wflags_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_ctrl_vec <= io_wakeups_3_bits_uop_fp_ctrl_vec_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_rob_idx <= io_wakeups_3_bits_uop_rob_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldq_idx <= io_wakeups_3_bits_uop_ldq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_stq_idx <= io_wakeups_3_bits_uop_stq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_rxq_idx <= io_wakeups_3_bits_uop_rxq_idx_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_pdst <= io_wakeups_3_bits_uop_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs1 <= io_wakeups_3_bits_uop_prs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs2 <= io_wakeups_3_bits_uop_prs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs3 <= io_wakeups_3_bits_uop_prs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ppred <= io_wakeups_3_bits_uop_ppred_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs1_busy <= io_wakeups_3_bits_uop_prs1_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs2_busy <= io_wakeups_3_bits_uop_prs2_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_prs3_busy <= io_wakeups_3_bits_uop_prs3_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ppred_busy <= io_wakeups_3_bits_uop_ppred_busy_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_stale_pdst <= io_wakeups_3_bits_uop_stale_pdst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_exception <= io_wakeups_3_bits_uop_exception_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_exc_cause <= io_wakeups_3_bits_uop_exc_cause_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_cmd <= io_wakeups_3_bits_uop_mem_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_size <= io_wakeups_3_bits_uop_mem_size_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_mem_signed <= io_wakeups_3_bits_uop_mem_signed_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_uses_ldq <= io_wakeups_3_bits_uop_uses_ldq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_uses_stq <= io_wakeups_3_bits_uop_uses_stq_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_is_unique <= io_wakeups_3_bits_uop_is_unique_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_flush_on_commit <= io_wakeups_3_bits_uop_flush_on_commit_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_csr_cmd <= io_wakeups_3_bits_uop_csr_cmd_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldst_is_rs1 <= io_wakeups_3_bits_uop_ldst_is_rs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_ldst <= io_wakeups_3_bits_uop_ldst_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs1 <= io_wakeups_3_bits_uop_lrs1_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs2 <= io_wakeups_3_bits_uop_lrs2_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs3 <= io_wakeups_3_bits_uop_lrs3_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_dst_rtype <= io_wakeups_3_bits_uop_dst_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs1_rtype <= io_wakeups_3_bits_uop_lrs1_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_lrs2_rtype <= io_wakeups_3_bits_uop_lrs2_rtype_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_frs3_en <= io_wakeups_3_bits_uop_frs3_en_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fcn_dw <= io_wakeups_3_bits_uop_fcn_dw_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fcn_op <= io_wakeups_3_bits_uop_fcn_op_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_val <= io_wakeups_3_bits_uop_fp_val_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_rm <= io_wakeups_3_bits_uop_fp_rm_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_fp_typ <= io_wakeups_3_bits_uop_fp_typ_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_pf_if <= io_wakeups_3_bits_uop_xcpt_pf_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_ae_if <= io_wakeups_3_bits_uop_xcpt_ae_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_xcpt_ma_if <= io_wakeups_3_bits_uop_xcpt_ma_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_bp_debug_if <= io_wakeups_3_bits_uop_bp_debug_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_bp_xcpt_if <= io_wakeups_3_bits_uop_bp_xcpt_if_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_fsrc <= io_wakeups_3_bits_uop_debug_fsrc_0; // @[rename-busytable.scala:27:7, :49:24] wakeups_wu_bits_REG_3_uop_debug_tsrc <= io_wakeups_3_bits_uop_debug_tsrc_0; // @[rename-busytable.scala:27:7, :49:24] if (reset) // @[rename-busytable.scala:27:7] busy_table <= 80'h0; // @[rename-busytable.scala:53:27] else // @[rename-busytable.scala:27:7] busy_table <= busy_table_next[79:0]; // @[rename-busytable.scala:53:27, :62:5, :66:14] always @(posedge) assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs1_busy = io_busy_resps_1_prs1_busy_0; // @[rename-busytable.scala:27:7] assign io_busy_resps_1_prs2_busy = io_busy_resps_1_prs2_busy_0; // @[rename-busytable.scala:27:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_3 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_123 = shr(io.in.a.bits.source, 3) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_130 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_240 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_314 = shr(io.in.a.bits.source, 3) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_321 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_428 = shr(io.in.a.bits.source, 3) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_435 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_538 = shr(io.in.a.bits.source, 3) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_545 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_651 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_759 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<27>(0h4000000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<13>(0h1000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = or(_T_772, _T_777) node _T_804 = or(_T_803, _T_782) node _T_805 = or(_T_804, _T_787) node _T_806 = or(_T_805, _T_792) node _T_807 = or(_T_806, _T_797) node _T_808 = or(_T_807, _T_802) node _T_809 = and(_T_767, _T_808) node _T_810 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_811 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_812 = cvt(_T_811) node _T_813 = and(_T_812, asSInt(UInt<17>(0h10000))) node _T_814 = asSInt(_T_813) node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = and(_T_810, _T_815) node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_818 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_819 = and(_T_817, _T_818) node _T_820 = or(UInt<1>(0h0), _T_819) node _T_821 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_822 = cvt(_T_821) node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000))) node _T_824 = asSInt(_T_823) node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0))) node _T_826 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<29>(0h10000000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = or(_T_825, _T_830) node _T_832 = and(_T_820, _T_831) node _T_833 = or(UInt<1>(0h0), _T_809) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_832) node _T_836 = and(_T_763, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_836, UInt<1>(0h1), "") : assert_36 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(is_aligned, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_846 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_846, UInt<1>(0h1), "") : assert_39 node _T_850 = eq(io.in.a.bits.mask, mask) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_850, UInt<1>(0h1), "") : assert_40 node _T_854 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_854 : node _T_855 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_856 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_858 = shr(io.in.a.bits.source, 3) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_9) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_863 = and(_T_861, _T_862) node _T_864 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_865 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_866 = or(_T_863, _T_864) node _T_867 = or(_T_866, _T_865) node _T_868 = and(_T_857, _T_867) node _T_869 = or(UInt<1>(0h0), _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<13>(0h1000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = and(_T_916, _T_921) node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_925 = and(_T_923, _T_924) node _T_926 = or(UInt<1>(0h0), _T_925) node _T_927 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<29>(0h10000000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = or(_T_931, _T_936) node _T_938 = and(_T_926, _T_937) node _T_939 = or(UInt<1>(0h0), _T_915) node _T_940 = or(_T_939, _T_922) node _T_941 = or(_T_940, _T_938) node _T_942 = and(_T_869, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_942, UInt<1>(0h1), "") : assert_41 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(is_aligned, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_952 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_952, UInt<1>(0h1), "") : assert_44 node _T_956 = eq(io.in.a.bits.mask, mask) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_956, UInt<1>(0h1), "") : assert_45 node _T_960 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_960 : node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_962 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_964 = shr(io.in.a.bits.source, 3) node _T_965 = eq(_T_964, UInt<1>(0h0)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_10) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_971 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_972 = or(_T_969, _T_970) node _T_973 = or(_T_972, _T_971) node _T_974 = and(_T_963, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<14>(0h2000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_991, _T_996) node _T_1023 = or(_T_1022, _T_1001) node _T_1024 = or(_T_1023, _T_1006) node _T_1025 = or(_T_1024, _T_1011) node _T_1026 = or(_T_1025, _T_1016) node _T_1027 = or(_T_1026, _T_1021) node _T_1028 = and(_T_986, _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<17>(0h10000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<29>(0h10000000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _T_1044 = and(_T_1032, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_985) node _T_1046 = or(_T_1045, _T_1028) node _T_1047 = or(_T_1046, _T_1044) node _T_1048 = and(_T_975, _T_1047) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_46 node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(is_aligned, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1058 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_49 node _T_1062 = eq(io.in.a.bits.mask, mask) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_50 node _T_1066 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1070 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1074 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1074 : node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok_1, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1078 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_54 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_55 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_56 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_57 node _T_1094 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1094 : node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(source_ok_1, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(sink_ok, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1101 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_60 node _T_1105 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_61 node _T_1109 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_62 node _T_1113 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_63 node _T_1117 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1118 = or(UInt<1>(0h1), _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_64 node _T_1122 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(source_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(sink_ok, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1129 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_67 node _T_1133 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_68 node _T_1137 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_69 node _T_1141 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.d.bits.corrupt) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_70 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h1), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_71 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_73 node _T_1159 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_74 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(UInt<1>(0h1), _T_1163) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_75 node _T_1168 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1168 : node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(source_ok_1, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1172 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_77 node _T_1176 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1177 = or(_T_1176, io.in.d.bits.corrupt) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_78 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h1), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_79 node _T_1186 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1186 : node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(source_ok_1, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1190 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_81 node _T_1194 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_82 node _T_1198 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1199 = or(UInt<1>(0h1), _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1203 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1207 = shr(io.in.b.bits.source, 3) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1213, _T_1218) node _T_1220 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = and(_T_1219, _T_1227) node _T_1237 = and(_T_1236, _T_1235) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1241 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1241 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1242 = shr(io.in.b.bits.source, 3) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1249 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1247 connect _WIRE_4[1], _T_1248 connect _WIRE_4[2], _T_1249 node _T_1250 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1251 = mux(_WIRE_4[0], _T_1250, UInt<1>(0h0)) node _T_1252 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1253 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1252) node _T_1255 = or(_T_1254, _T_1253) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1255 node _T_1256 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1257 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = or(UInt<1>(0h0), _T_1258) node _T_1260 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<14>(0h2000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<13>(0h1000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<18>(0h2f000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<27>(0h4000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1301 = cvt(_T_1300) node _T_1302 = and(_T_1301, asSInt(UInt<13>(0h1000))) node _T_1303 = asSInt(_T_1302) node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0))) node _T_1305 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = or(_T_1264, _T_1269) node _T_1311 = or(_T_1310, _T_1274) node _T_1312 = or(_T_1311, _T_1279) node _T_1313 = or(_T_1312, _T_1284) node _T_1314 = or(_T_1313, _T_1289) node _T_1315 = or(_T_1314, _T_1294) node _T_1316 = or(_T_1315, _T_1299) node _T_1317 = or(_T_1316, _T_1304) node _T_1318 = or(_T_1317, _T_1309) node _T_1319 = and(_T_1259, _T_1318) node _T_1320 = or(UInt<1>(0h0), _T_1319) node _T_1321 = and(_WIRE_5, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_86 node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(address_ok, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(legal_source, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1334 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_90 node _T_1338 = eq(io.in.b.bits.mask, mask_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_91 node _T_1342 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1346 : node _T_1347 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1348 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<14>(0h2000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<13>(0h1000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<18>(0h2f000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<13>(0h1000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<17>(0h10000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<27>(0h4000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<29>(0h10000000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = or(_T_1355, _T_1360) node _T_1402 = or(_T_1401, _T_1365) node _T_1403 = or(_T_1402, _T_1370) node _T_1404 = or(_T_1403, _T_1375) node _T_1405 = or(_T_1404, _T_1380) node _T_1406 = or(_T_1405, _T_1385) node _T_1407 = or(_T_1406, _T_1390) node _T_1408 = or(_T_1407, _T_1395) node _T_1409 = or(_T_1408, _T_1400) node _T_1410 = and(_T_1350, _T_1409) node _T_1411 = or(UInt<1>(0h0), _T_1410) node _T_1412 = and(UInt<1>(0h0), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_93 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(address_ok, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(legal_source, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1425 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_97 node _T_1429 = eq(io.in.b.bits.mask, mask_1) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_98 node _T_1433 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_99 node _T_1437 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1437 : node _T_1438 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1439 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1440 = and(_T_1438, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<14>(0h2000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<13>(0h1000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<18>(0h2f000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<17>(0h10000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<27>(0h4000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<13>(0h1000))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1488 = cvt(_T_1487) node _T_1489 = and(_T_1488, asSInt(UInt<29>(0h10000000))) node _T_1490 = asSInt(_T_1489) node _T_1491 = eq(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = or(_T_1446, _T_1451) node _T_1493 = or(_T_1492, _T_1456) node _T_1494 = or(_T_1493, _T_1461) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1471) node _T_1497 = or(_T_1496, _T_1476) node _T_1498 = or(_T_1497, _T_1481) node _T_1499 = or(_T_1498, _T_1486) node _T_1500 = or(_T_1499, _T_1491) node _T_1501 = and(_T_1441, _T_1500) node _T_1502 = or(UInt<1>(0h0), _T_1501) node _T_1503 = and(UInt<1>(0h0), _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_100 node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(address_ok, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(legal_source, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1516 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_104 node _T_1520 = eq(io.in.b.bits.mask, mask_1) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_105 node _T_1524 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1524 : node _T_1525 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1526 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = or(UInt<1>(0h0), _T_1527) node _T_1529 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<14>(0h2000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<13>(0h1000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<18>(0h2f000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<27>(0h4000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<29>(0h10000000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = or(_T_1533, _T_1538) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1548) node _T_1582 = or(_T_1581, _T_1553) node _T_1583 = or(_T_1582, _T_1558) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1568) node _T_1586 = or(_T_1585, _T_1573) node _T_1587 = or(_T_1586, _T_1578) node _T_1588 = and(_T_1528, _T_1587) node _T_1589 = or(UInt<1>(0h0), _T_1588) node _T_1590 = and(UInt<1>(0h0), _T_1589) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_106 node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(address_ok, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(legal_source, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1603 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_110 node _T_1607 = not(mask_1) node _T_1608 = and(io.in.b.bits.mask, _T_1607) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_111 node _T_1613 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1613 : node _T_1614 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1615 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = or(UInt<1>(0h0), _T_1616) node _T_1618 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<14>(0h2000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<18>(0h2f000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<13>(0h1000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<17>(0h10000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<27>(0h4000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1659 = cvt(_T_1658) node _T_1660 = and(_T_1659, asSInt(UInt<13>(0h1000))) node _T_1661 = asSInt(_T_1660) node _T_1662 = eq(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1664 = cvt(_T_1663) node _T_1665 = and(_T_1664, asSInt(UInt<29>(0h10000000))) node _T_1666 = asSInt(_T_1665) node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0))) node _T_1668 = or(_T_1622, _T_1627) node _T_1669 = or(_T_1668, _T_1632) node _T_1670 = or(_T_1669, _T_1637) node _T_1671 = or(_T_1670, _T_1642) node _T_1672 = or(_T_1671, _T_1647) node _T_1673 = or(_T_1672, _T_1652) node _T_1674 = or(_T_1673, _T_1657) node _T_1675 = or(_T_1674, _T_1662) node _T_1676 = or(_T_1675, _T_1667) node _T_1677 = and(_T_1617, _T_1676) node _T_1678 = or(UInt<1>(0h0), _T_1677) node _T_1679 = and(UInt<1>(0h0), _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_112 node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(address_ok, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(legal_source, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1689 = asUInt(reset) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) when _T_1690 : node _T_1691 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1692 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_116 node _T_1696 = eq(io.in.b.bits.mask, mask_1) node _T_1697 = asUInt(reset) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(_T_1696, UInt<1>(0h0)) when _T_1699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1696, UInt<1>(0h1), "") : assert_117 node _T_1700 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1700 : node _T_1701 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1702 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = or(UInt<1>(0h0), _T_1703) node _T_1705 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<14>(0h2000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<13>(0h1000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<18>(0h2f000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<13>(0h1000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<17>(0h10000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<27>(0h4000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1746 = cvt(_T_1745) node _T_1747 = and(_T_1746, asSInt(UInt<13>(0h1000))) node _T_1748 = asSInt(_T_1747) node _T_1749 = eq(_T_1748, asSInt(UInt<1>(0h0))) node _T_1750 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<29>(0h10000000))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = or(_T_1709, _T_1714) node _T_1756 = or(_T_1755, _T_1719) node _T_1757 = or(_T_1756, _T_1724) node _T_1758 = or(_T_1757, _T_1729) node _T_1759 = or(_T_1758, _T_1734) node _T_1760 = or(_T_1759, _T_1739) node _T_1761 = or(_T_1760, _T_1744) node _T_1762 = or(_T_1761, _T_1749) node _T_1763 = or(_T_1762, _T_1754) node _T_1764 = and(_T_1704, _T_1763) node _T_1765 = or(UInt<1>(0h0), _T_1764) node _T_1766 = and(UInt<1>(0h0), _T_1765) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_118 node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(address_ok, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(legal_source, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1779 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_122 node _T_1783 = eq(io.in.b.bits.mask, mask_1) node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(_T_1783, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1783, UInt<1>(0h1), "") : assert_123 node _T_1787 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1787 : node _T_1788 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1789 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1790 = and(_T_1788, _T_1789) node _T_1791 = or(UInt<1>(0h0), _T_1790) node _T_1792 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<14>(0h2000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<13>(0h1000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1796, _T_1801) node _T_1843 = or(_T_1842, _T_1806) node _T_1844 = or(_T_1843, _T_1811) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1821) node _T_1847 = or(_T_1846, _T_1826) node _T_1848 = or(_T_1847, _T_1831) node _T_1849 = or(_T_1848, _T_1836) node _T_1850 = or(_T_1849, _T_1841) node _T_1851 = and(_T_1791, _T_1850) node _T_1852 = or(UInt<1>(0h0), _T_1851) node _T_1853 = and(UInt<1>(0h0), _T_1852) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_124 node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(address_ok, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(legal_source, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1866 = eq(io.in.b.bits.mask, mask_1) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_128 node _T_1870 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1874 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1878 = shr(io.in.c.bits.source, 3) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) node _T_1885 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) node _T_1893 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = or(_T_1892, _T_1897) node _T_1899 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) node _T_1901 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1890, _T_1898) node _T_1908 = and(_T_1907, _T_1906) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_131 node _T_1912 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1912 : node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(address_ok_1, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok_2, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1919 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_134 node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1926 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_136 node _T_1930 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_137 node _T_1934 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1941 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_140 node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1948 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_142 node _T_1952 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1952 : node _T_1953 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1954 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1955 = and(_T_1953, _T_1954) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_1956 = shr(io.in.c.bits.source, 3) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) node _T_1958 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1959 = and(_T_1957, _T_1958) node _T_1960 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_1961 = and(_T_1959, _T_1960) node _T_1962 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1963 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1964 = or(_T_1961, _T_1962) node _T_1965 = or(_T_1964, _T_1963) node _T_1966 = and(_T_1955, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1966) node _T_1968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<14>(0h2000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<13>(0h1000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<18>(0h2f000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<17>(0h10000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2000 = cvt(_T_1999) node _T_2001 = and(_T_2000, asSInt(UInt<27>(0h4000000))) node _T_2002 = asSInt(_T_2001) node _T_2003 = eq(_T_2002, asSInt(UInt<1>(0h0))) node _T_2004 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2005 = cvt(_T_2004) node _T_2006 = and(_T_2005, asSInt(UInt<13>(0h1000))) node _T_2007 = asSInt(_T_2006) node _T_2008 = eq(_T_2007, asSInt(UInt<1>(0h0))) node _T_2009 = or(_T_1973, _T_1978) node _T_2010 = or(_T_2009, _T_1983) node _T_2011 = or(_T_2010, _T_1988) node _T_2012 = or(_T_2011, _T_1993) node _T_2013 = or(_T_2012, _T_1998) node _T_2014 = or(_T_2013, _T_2003) node _T_2015 = or(_T_2014, _T_2008) node _T_2016 = and(_T_1968, _T_2015) node _T_2017 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2018 = or(UInt<1>(0h0), _T_2017) node _T_2019 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2020 = cvt(_T_2019) node _T_2021 = and(_T_2020, asSInt(UInt<17>(0h10000))) node _T_2022 = asSInt(_T_2021) node _T_2023 = eq(_T_2022, asSInt(UInt<1>(0h0))) node _T_2024 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2025 = cvt(_T_2024) node _T_2026 = and(_T_2025, asSInt(UInt<29>(0h10000000))) node _T_2027 = asSInt(_T_2026) node _T_2028 = eq(_T_2027, asSInt(UInt<1>(0h0))) node _T_2029 = or(_T_2023, _T_2028) node _T_2030 = and(_T_2018, _T_2029) node _T_2031 = or(UInt<1>(0h0), _T_2016) node _T_2032 = or(_T_2031, _T_2030) node _T_2033 = and(_T_1967, _T_2032) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2037 = shr(io.in.c.bits.source, 3) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) node _T_2039 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2040 = and(_T_2038, _T_2039) node _T_2041 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2044 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2042 connect _WIRE_6[1], _T_2043 connect _WIRE_6[2], _T_2044 node _T_2045 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2046 = mux(_WIRE_6[0], _T_2045, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = or(_T_2046, _T_2047) node _T_2050 = or(_T_2049, _T_2048) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2050 node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<14>(0h2000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<13>(0h1000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<18>(0h2f000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<13>(0h1000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<29>(0h10000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2059, _T_2064) node _T_2106 = or(_T_2105, _T_2069) node _T_2107 = or(_T_2106, _T_2074) node _T_2108 = or(_T_2107, _T_2079) node _T_2109 = or(_T_2108, _T_2084) node _T_2110 = or(_T_2109, _T_2089) node _T_2111 = or(_T_2110, _T_2094) node _T_2112 = or(_T_2111, _T_2099) node _T_2113 = or(_T_2112, _T_2104) node _T_2114 = and(_T_2054, _T_2113) node _T_2115 = or(UInt<1>(0h0), _T_2114) node _T_2116 = and(_WIRE_7, _T_2115) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_144 node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(source_ok_2, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2123 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_146 node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2130 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_148 node _T_2134 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_149 node _T_2138 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2138 : node _T_2139 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2140 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2141 = and(_T_2139, _T_2140) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2142 = shr(io.in.c.bits.source, 3) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) node _T_2144 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2149 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2150 = or(_T_2147, _T_2148) node _T_2151 = or(_T_2150, _T_2149) node _T_2152 = and(_T_2141, _T_2151) node _T_2153 = or(UInt<1>(0h0), _T_2152) node _T_2154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2155 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<14>(0h2000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<13>(0h1000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<18>(0h2f000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<17>(0h10000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2186 = cvt(_T_2185) node _T_2187 = and(_T_2186, asSInt(UInt<27>(0h4000000))) node _T_2188 = asSInt(_T_2187) node _T_2189 = eq(_T_2188, asSInt(UInt<1>(0h0))) node _T_2190 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<13>(0h1000))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2159, _T_2164) node _T_2196 = or(_T_2195, _T_2169) node _T_2197 = or(_T_2196, _T_2174) node _T_2198 = or(_T_2197, _T_2179) node _T_2199 = or(_T_2198, _T_2184) node _T_2200 = or(_T_2199, _T_2189) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = and(_T_2154, _T_2201) node _T_2203 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<17>(0h10000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<29>(0h10000000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = or(_T_2209, _T_2214) node _T_2216 = and(_T_2204, _T_2215) node _T_2217 = or(UInt<1>(0h0), _T_2202) node _T_2218 = or(_T_2217, _T_2216) node _T_2219 = and(_T_2153, _T_2218) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2223 = shr(io.in.c.bits.source, 3) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) node _T_2225 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2226 = and(_T_2224, _T_2225) node _T_2227 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2228 = and(_T_2226, _T_2227) node _T_2229 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2230 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2228 connect _WIRE_8[1], _T_2229 connect _WIRE_8[2], _T_2230 node _T_2231 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2232 = mux(_WIRE_8[0], _T_2231, UInt<1>(0h0)) node _T_2233 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2234 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2235 = or(_T_2232, _T_2233) node _T_2236 = or(_T_2235, _T_2234) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2236 node _T_2237 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2238 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2239 = and(_T_2237, _T_2238) node _T_2240 = or(UInt<1>(0h0), _T_2239) node _T_2241 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<14>(0h2000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<13>(0h1000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<18>(0h2f000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<13>(0h1000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<17>(0h10000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<27>(0h4000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2282 = cvt(_T_2281) node _T_2283 = and(_T_2282, asSInt(UInt<13>(0h1000))) node _T_2284 = asSInt(_T_2283) node _T_2285 = eq(_T_2284, asSInt(UInt<1>(0h0))) node _T_2286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2287 = cvt(_T_2286) node _T_2288 = and(_T_2287, asSInt(UInt<29>(0h10000000))) node _T_2289 = asSInt(_T_2288) node _T_2290 = eq(_T_2289, asSInt(UInt<1>(0h0))) node _T_2291 = or(_T_2245, _T_2250) node _T_2292 = or(_T_2291, _T_2255) node _T_2293 = or(_T_2292, _T_2260) node _T_2294 = or(_T_2293, _T_2265) node _T_2295 = or(_T_2294, _T_2270) node _T_2296 = or(_T_2295, _T_2275) node _T_2297 = or(_T_2296, _T_2280) node _T_2298 = or(_T_2297, _T_2285) node _T_2299 = or(_T_2298, _T_2290) node _T_2300 = and(_T_2240, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2300) node _T_2302 = and(_WIRE_9, _T_2301) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_151 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(source_ok_2, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2309 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_153 node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2316 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_155 node _T_2320 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2320 : node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(address_ok_1, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : node _T_2326 = eq(source_ok_2, UInt<1>(0h0)) when _T_2326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2330 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2331 = asUInt(reset) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) when _T_2332 : node _T_2333 = eq(_T_2330, UInt<1>(0h0)) when _T_2333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2330, UInt<1>(0h1), "") : assert_159 node _T_2334 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(_T_2334, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2334, UInt<1>(0h1), "") : assert_160 node _T_2338 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2338 : node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(address_ok_1, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(source_ok_2, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2345 = asUInt(reset) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) when _T_2346 : node _T_2347 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2348 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_164 node _T_2352 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2352 : node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(address_ok_1, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok_2, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2362 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_168 node _T_2366 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2373 = eq(a_first, UInt<1>(0h0)) node _T_2374 = and(io.in.a.valid, _T_2373) when _T_2374 : node _T_2375 = eq(io.in.a.bits.opcode, opcode) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_171 node _T_2379 = eq(io.in.a.bits.param, param) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_172 node _T_2383 = eq(io.in.a.bits.size, size) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_173 node _T_2387 = eq(io.in.a.bits.source, source) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_174 node _T_2391 = eq(io.in.a.bits.address, address) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_175 node _T_2395 = and(io.in.a.ready, io.in.a.valid) node _T_2396 = and(_T_2395, a_first) when _T_2396 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2397 = eq(d_first, UInt<1>(0h0)) node _T_2398 = and(io.in.d.valid, _T_2397) when _T_2398 : node _T_2399 = eq(io.in.d.bits.opcode, opcode_1) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_176 node _T_2403 = eq(io.in.d.bits.param, param_1) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_177 node _T_2407 = eq(io.in.d.bits.size, size_1) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_178 node _T_2411 = eq(io.in.d.bits.source, source_1) node _T_2412 = asUInt(reset) node _T_2413 = eq(_T_2412, UInt<1>(0h0)) when _T_2413 : node _T_2414 = eq(_T_2411, UInt<1>(0h0)) when _T_2414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2411, UInt<1>(0h1), "") : assert_179 node _T_2415 = eq(io.in.d.bits.sink, sink) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_180 node _T_2419 = eq(io.in.d.bits.denied, denied) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_181 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first) when _T_2424 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2425 = eq(b_first, UInt<1>(0h0)) node _T_2426 = and(io.in.b.valid, _T_2425) when _T_2426 : node _T_2427 = eq(io.in.b.bits.opcode, opcode_2) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_182 node _T_2431 = eq(io.in.b.bits.param, param_2) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_183 node _T_2435 = eq(io.in.b.bits.size, size_2) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_184 node _T_2439 = eq(io.in.b.bits.source, source_2) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_185 node _T_2443 = eq(io.in.b.bits.address, address_1) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_186 node _T_2447 = and(io.in.b.ready, io.in.b.valid) node _T_2448 = and(_T_2447, b_first) when _T_2448 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2449 = eq(c_first, UInt<1>(0h0)) node _T_2450 = and(io.in.c.valid, _T_2449) when _T_2450 : node _T_2451 = eq(io.in.c.bits.opcode, opcode_3) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_187 node _T_2455 = eq(io.in.c.bits.param, param_3) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_188 node _T_2459 = eq(io.in.c.bits.size, size_3) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_189 node _T_2463 = eq(io.in.c.bits.source, source_3) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_190 node _T_2467 = eq(io.in.c.bits.address, address_2) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_191 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(_T_2471, c_first) when _T_2472 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2473 = and(io.in.a.valid, a_first_1) node _T_2474 = and(_T_2473, UInt<1>(0h1)) when _T_2474 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2475 = and(io.in.a.ready, io.in.a.valid) node _T_2476 = and(_T_2475, a_first_1) node _T_2477 = and(_T_2476, UInt<1>(0h1)) when _T_2477 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2478 = dshr(inflight, io.in.a.bits.source) node _T_2479 = bits(_T_2478, 0, 0) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2484 = and(io.in.d.valid, d_first_1) node _T_2485 = and(_T_2484, UInt<1>(0h1)) node _T_2486 = eq(d_release_ack, UInt<1>(0h0)) node _T_2487 = and(_T_2485, _T_2486) when _T_2487 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2488 = and(io.in.d.ready, io.in.d.valid) node _T_2489 = and(_T_2488, d_first_1) node _T_2490 = and(_T_2489, UInt<1>(0h1)) node _T_2491 = eq(d_release_ack, UInt<1>(0h0)) node _T_2492 = and(_T_2490, _T_2491) when _T_2492 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2493 = and(io.in.d.valid, d_first_1) node _T_2494 = and(_T_2493, UInt<1>(0h1)) node _T_2495 = eq(d_release_ack, UInt<1>(0h0)) node _T_2496 = and(_T_2494, _T_2495) when _T_2496 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2497 = dshr(inflight, io.in.d.bits.source) node _T_2498 = bits(_T_2497, 0, 0) node _T_2499 = or(_T_2498, same_cycle_resp) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_194 node _T_2509 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_195 else : node _T_2513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2515 = or(_T_2513, _T_2514) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_196 node _T_2519 = eq(io.in.d.bits.size, a_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_197 node _T_2523 = and(io.in.d.valid, d_first_1) node _T_2524 = and(_T_2523, a_first_1) node _T_2525 = and(_T_2524, io.in.a.valid) node _T_2526 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = eq(d_release_ack, UInt<1>(0h0)) node _T_2529 = and(_T_2527, _T_2528) when _T_2529 : node _T_2530 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2531 = or(_T_2530, io.in.a.ready) node _T_2532 = asUInt(reset) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) when _T_2533 : node _T_2534 = eq(_T_2531, UInt<1>(0h0)) when _T_2534 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2531, UInt<1>(0h1), "") : assert_198 node _T_2535 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2536 = orr(a_set_wo_ready) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = or(_T_2535, _T_2537) node _T_2539 = asUInt(reset) node _T_2540 = eq(_T_2539, UInt<1>(0h0)) when _T_2540 : node _T_2541 = eq(_T_2538, UInt<1>(0h0)) when _T_2541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2538, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_6 node _T_2542 = orr(inflight) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) node _T_2544 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2545 = or(_T_2543, _T_2544) node _T_2546 = lt(watchdog, plusarg_reader.out) node _T_2547 = or(_T_2545, _T_2546) node _T_2548 = asUInt(reset) node _T_2549 = eq(_T_2548, UInt<1>(0h0)) when _T_2549 : node _T_2550 = eq(_T_2547, UInt<1>(0h0)) when _T_2550 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2547, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2551 = and(io.in.a.ready, io.in.a.valid) node _T_2552 = and(io.in.d.ready, io.in.d.valid) node _T_2553 = or(_T_2551, _T_2552) when _T_2553 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2554 = and(io.in.c.valid, c_first_1) node _T_2555 = bits(io.in.c.bits.opcode, 2, 2) node _T_2556 = bits(io.in.c.bits.opcode, 1, 1) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = and(_T_2554, _T_2557) when _T_2558 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2559 = and(io.in.c.ready, io.in.c.valid) node _T_2560 = and(_T_2559, c_first_1) node _T_2561 = bits(io.in.c.bits.opcode, 2, 2) node _T_2562 = bits(io.in.c.bits.opcode, 1, 1) node _T_2563 = and(_T_2561, _T_2562) node _T_2564 = and(_T_2560, _T_2563) when _T_2564 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2565 = dshr(inflight_1, io.in.c.bits.source) node _T_2566 = bits(_T_2565, 0, 0) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) node _T_2568 = asUInt(reset) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) when _T_2569 : node _T_2570 = eq(_T_2567, UInt<1>(0h0)) when _T_2570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2567, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2571 = and(io.in.d.valid, d_first_2) node _T_2572 = and(_T_2571, UInt<1>(0h1)) node _T_2573 = and(_T_2572, d_release_ack_1) when _T_2573 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2574 = and(io.in.d.ready, io.in.d.valid) node _T_2575 = and(_T_2574, d_first_2) node _T_2576 = and(_T_2575, UInt<1>(0h1)) node _T_2577 = and(_T_2576, d_release_ack_1) when _T_2577 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2578 = and(io.in.d.valid, d_first_2) node _T_2579 = and(_T_2578, UInt<1>(0h1)) node _T_2580 = and(_T_2579, d_release_ack_1) when _T_2580 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2581 = dshr(inflight_1, io.in.d.bits.source) node _T_2582 = bits(_T_2581, 0, 0) node _T_2583 = or(_T_2582, same_cycle_resp_1) node _T_2584 = asUInt(reset) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) when _T_2585 : node _T_2586 = eq(_T_2583, UInt<1>(0h0)) when _T_2586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2583, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2587 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_203 else : node _T_2591 = eq(io.in.d.bits.size, c_size_lookup) node _T_2592 = asUInt(reset) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) when _T_2593 : node _T_2594 = eq(_T_2591, UInt<1>(0h0)) when _T_2594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2591, UInt<1>(0h1), "") : assert_204 node _T_2595 = and(io.in.d.valid, d_first_2) node _T_2596 = and(_T_2595, c_first_1) node _T_2597 = and(_T_2596, io.in.c.valid) node _T_2598 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2599 = and(_T_2597, _T_2598) node _T_2600 = and(_T_2599, d_release_ack_1) node _T_2601 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2602 = and(_T_2600, _T_2601) when _T_2602 : node _T_2603 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2604 = or(_T_2603, io.in.c.ready) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_205 node _T_2608 = orr(c_set_wo_ready) when _T_2608 : node _T_2609 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_7 node _T_2613 = orr(inflight_1) node _T_2614 = eq(_T_2613, UInt<1>(0h0)) node _T_2615 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2616 = or(_T_2614, _T_2615) node _T_2617 = lt(watchdog_1, plusarg_reader_1.out) node _T_2618 = or(_T_2616, _T_2617) node _T_2619 = asUInt(reset) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) when _T_2620 : node _T_2621 = eq(_T_2618, UInt<1>(0h0)) when _T_2621 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2618, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2622 = and(io.in.c.ready, io.in.c.valid) node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = or(_T_2622, _T_2623) when _T_2624 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2625 = and(io.in.d.ready, io.in.d.valid) node _T_2626 = and(_T_2625, d_first_3) node _T_2627 = bits(io.in.d.bits.opcode, 2, 2) node _T_2628 = bits(io.in.d.bits.opcode, 1, 1) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) node _T_2630 = and(_T_2627, _T_2629) node _T_2631 = and(_T_2626, _T_2630) when _T_2631 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2632 = dshr(inflight_2, io.in.d.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = asUInt(reset) node _T_2636 = eq(_T_2635, UInt<1>(0h0)) when _T_2636 : node _T_2637 = eq(_T_2634, UInt<1>(0h0)) when _T_2637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2634, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2638 = and(io.in.e.ready, io.in.e.valid) node _T_2639 = and(_T_2638, UInt<1>(0h1)) node _T_2640 = and(_T_2639, UInt<1>(0h1)) when _T_2640 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2641 = or(d_set, inflight_2) node _T_2642 = dshr(_T_2641, io.in.e.bits.sink) node _T_2643 = bits(_T_2642, 0, 0) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_8 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_9 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] io_in_b_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] b_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask_1 = 12'h3F; // @[package.scala:243:46] wire [11:0] _b_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_3 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _b_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T_2 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10] wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[3]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_9 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_10 = {_legal_source_WIRE_2, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_8 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_9 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_9}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_10 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_11 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_12 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_14 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_16 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2551; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2551; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2625 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2625; // @[Decoupled.scala:51:35] wire [26:0] _GEN_17 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_17; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_17; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2622 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2622; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2622; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_18 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_18; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_18; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_18; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_19 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_19; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_19; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_19; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_20 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_20; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_20; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2551 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2477 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2477 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2477 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_21 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_21; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_21; // @[Monitor.scala:673:46, :783:46] wire _T_2523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_22 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_22; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_22; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2523 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2625 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2492 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2492 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2492 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_23 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_23; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2564 = _T_2622 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2564 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2564 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2564 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2564 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2564 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2577 = _T_2625 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2577 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2577 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2577 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2631 = _T_2625 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_24 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_24; // @[OneHot.scala:58:35] assign d_set = _T_2631 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2640 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign e_clr = _T_2640 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_38 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hfc))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node adjustedSig = shl(io.in.sig, 25) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _common_expOut_T = bits(sAdjustedExp, 8, 0) node _common_expOut_T_1 = add(_common_expOut_T, UInt<1>(0h0)) node _common_expOut_T_2 = tail(_common_expOut_T_1, 1) connect common_expOut, _common_expOut_T_2 node _common_fractOut_T = bits(adjustedSig, 25, 3) node _common_fractOut_T_1 = bits(adjustedSig, 24, 2) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) connect common_underflow, UInt<1>(0h0) connect common_inexact, UInt<1>(0h0) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_38(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<64>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<64>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_wdat : { data : UInt<64>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<3>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 1, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 2, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<4>(0hf)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h3)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 3) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 3) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<3>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<8>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_18 = and(s2_valid, s3_ready) when _T_18 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_19 = eq(s3_ready, UInt<1>(0h0)) node _T_20 = and(s2_valid, _T_19) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<3>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 63, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 63, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_21 = eq(s3_full, UInt<1>(0h0)) node _T_22 = eq(s3_need_r, UInt<1>(0h0)) node _T_23 = or(_T_21, _T_22) node _T_24 = or(_T_23, queue.io.deq.valid) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_28 = and(s3_valid, s4_ready) when _T_28 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_29 = eq(s4_ready, UInt<1>(0h0)) node _T_30 = and(s3_valid, _T_29) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<3>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<64>, mask : UInt<8>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<64>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = bits(s4_pdata.mask, 4, 4) node _io_bs_wadr_bits_mask_T_5 = bits(s4_pdata.mask, 5, 5) node _io_bs_wadr_bits_mask_T_6 = bits(s4_pdata.mask, 6, 6) node _io_bs_wadr_bits_mask_T_7 = bits(s4_pdata.mask, 7, 7) node _io_bs_wadr_bits_mask_T_8 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_9 = or(_io_bs_wadr_bits_mask_T_8, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_10 = or(_io_bs_wadr_bits_mask_T_9, _io_bs_wadr_bits_mask_T_3) node _io_bs_wadr_bits_mask_T_11 = or(_io_bs_wadr_bits_mask_T_10, _io_bs_wadr_bits_mask_T_4) node _io_bs_wadr_bits_mask_T_12 = or(_io_bs_wadr_bits_mask_T_11, _io_bs_wadr_bits_mask_T_5) node _io_bs_wadr_bits_mask_T_13 = or(_io_bs_wadr_bits_mask_T_12, _io_bs_wadr_bits_mask_T_6) node _io_bs_wadr_bits_mask_T_14 = or(_io_bs_wadr_bits_mask_T_13, _io_bs_wadr_bits_mask_T_7) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_14 connect io.bs_wdat.data, atomics.io.data_out node _T_31 = and(s4_full, s4_need_pb) node _T_32 = and(_T_31, s4_pdata.corrupt) node _T_33 = eq(_T_32, UInt<1>(0h0)) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_38 = and(io.bs_wadr.valid, _T_37) node _T_39 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_40 = and(s4_req.prio[0], _T_39) node _T_41 = eq(s4_req.param, UInt<3>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_44 = and(s4_req.prio[0], _T_43) node _T_45 = eq(s4_req.param, UInt<3>(0h1)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_48 = and(s4_req.prio[0], _T_47) node _T_49 = eq(s4_req.param, UInt<3>(0h2)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_52 = and(s4_req.prio[0], _T_51) node _T_53 = eq(s4_req.param, UInt<3>(0h3)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_56 = and(s4_req.prio[0], _T_55) node _T_57 = eq(s4_req.param, UInt<3>(0h4)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_60 = and(s4_req.prio[0], _T_59) node _T_61 = eq(s4_req.param, UInt<3>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_64 = and(s4_req.prio[0], _T_63) node _T_65 = eq(s4_req.param, UInt<3>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_68 = and(s4_req.prio[0], _T_67) node _T_69 = eq(s4_req.param, UInt<3>(0h2)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_72 = and(s4_req.prio[0], _T_71) node _T_73 = eq(s4_req.param, UInt<3>(0h3)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(s4_need_bs, UInt<1>(0h0)) node _T_76 = or(io.bs_wadr.ready, _T_75) when _T_76 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<3>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<64>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<3>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<64>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<64>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<3>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 1, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 2, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<3>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 1, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 2, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<3>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 1, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 2, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<4>(0hf)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 63, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 63, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 63, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 63, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 63, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 63, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_77 = and(io.req.valid, s2) node _T_78 = and(_T_77, s3) node _T_79 = and(_T_78, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_80 = and(io.req.valid, s2_1) node _T_81 = and(_T_80, s3_1) node _T_82 = and(_T_81, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_83 = and(io.req.valid, s2_2) node _T_84 = and(_T_83, s3_2) node _T_85 = and(_T_84, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_86 = and(io.req.valid, s2_3) node _T_87 = and(_T_86, s3_3) node _T_88 = and(_T_87, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_89 = and(io.req.valid, s2_4) node _T_90 = and(_T_89, s3_4) node _T_91 = and(_T_90, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_92 = and(io.req.valid, s2_5) node _T_93 = and(_T_92, s3_5) node _T_94 = and(_T_93, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_95 = and(io.req.valid, s2_6) node _T_96 = and(_T_95, s3_6) node _T_97 = and(_T_96, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_98 = and(io.req.valid, s2_7) node _T_99 = and(_T_98, s3_7) node _T_100 = and(_T_99, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<3>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 1, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 2, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<3>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 1, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 2, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<3>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 1, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 2, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<4>(0hf)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22

module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [63:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [63:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [7:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [63:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [63:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [63:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [63:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [7:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [63:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_rel_pop_ready = 1'h1; // @[SourceD.scala:48:7] wire [63:0] io_rel_beat_data = 64'h0; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt = 1'h0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [7:0] _s2_pdata_raw_mask_T = 8'hFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [63:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [2:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [63:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [63:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [2:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [2:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:3]; // @[package.scala:243:46] wire [2:0] s1_beats1 = s1_single ? 3'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [2:0] _s1_beat_T = s1_req_offset[5:3]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 3'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [3:0] _s1_counter_T = {1'h0, s1_counter} + 4'h1; // @[SourceD.scala:86:27, :130:30] wire [2:0] _s1_counter_T_1 = _s1_counter_T[2:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [2:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [63:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [7:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [63:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [7:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [63:0] s2_pdata_r_data; // @[package.scala:88:63] reg [7:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [63:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [7:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : 64'h0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 8'hFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 & io_pb_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = ~s2_req_prio_0 | io_pb_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [2:0] s3_beat; // @[SourceD.scala:192:26] wire [2:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [63:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [7:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [63:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [63:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [63:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [63:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [2:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [2:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [63:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [7:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [63:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_9 = _io_bs_wadr_bits_mask_T_8 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_10 = _io_bs_wadr_bits_mask_T_9 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_11 = _io_bs_wadr_bits_mask_T_10 | _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_12 = _io_bs_wadr_bits_mask_T_11 | _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_13 = _io_bs_wadr_bits_mask_T_12 | _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_14 = _io_bs_wadr_bits_mask_T_13 | _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:48:7, :275:87]

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_98 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_98( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_13 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x

module PMPChecker_s3_13( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RenameFreeList : input clock : Clock input reset : Reset output io : { flip initial_allocation : UInt<80>, flip reqs : UInt<1>[2], alloc_pregs : { valid : UInt<1>, bits : UInt<7>}[2], flip despec : { valid : UInt<1>, bits : UInt<7>}[2], flip dealloc : { valid : UInt<1>, bits : UInt<7>}[2], flip ren_br_tags : { valid : UInt<1>, bits : UInt<4>}[3], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rollback : UInt<1>, debug_freelist : UInt<80>} regreset free_list : UInt<80>, clock, reset, io.initial_allocation regreset spec_alloc_list : UInt<80>, clock, reset, UInt<80>(0h0) reg br_alloc_lists : UInt<80>[12], clock wire sels : UInt<80>[2] node _sels_sels_0_T = bits(free_list, 0, 0) node _sels_sels_0_T_1 = bits(free_list, 1, 1) node _sels_sels_0_T_2 = bits(free_list, 2, 2) node _sels_sels_0_T_3 = bits(free_list, 3, 3) node _sels_sels_0_T_4 = bits(free_list, 4, 4) node _sels_sels_0_T_5 = bits(free_list, 5, 5) node _sels_sels_0_T_6 = bits(free_list, 6, 6) node _sels_sels_0_T_7 = bits(free_list, 7, 7) node _sels_sels_0_T_8 = bits(free_list, 8, 8) node _sels_sels_0_T_9 = bits(free_list, 9, 9) node _sels_sels_0_T_10 = bits(free_list, 10, 10) node _sels_sels_0_T_11 = bits(free_list, 11, 11) node _sels_sels_0_T_12 = bits(free_list, 12, 12) node _sels_sels_0_T_13 = bits(free_list, 13, 13) node _sels_sels_0_T_14 = bits(free_list, 14, 14) node _sels_sels_0_T_15 = bits(free_list, 15, 15) node _sels_sels_0_T_16 = bits(free_list, 16, 16) node _sels_sels_0_T_17 = bits(free_list, 17, 17) node _sels_sels_0_T_18 = bits(free_list, 18, 18) node _sels_sels_0_T_19 = bits(free_list, 19, 19) node _sels_sels_0_T_20 = bits(free_list, 20, 20) node _sels_sels_0_T_21 = bits(free_list, 21, 21) node _sels_sels_0_T_22 = bits(free_list, 22, 22) node _sels_sels_0_T_23 = bits(free_list, 23, 23) node _sels_sels_0_T_24 = bits(free_list, 24, 24) node _sels_sels_0_T_25 = bits(free_list, 25, 25) node _sels_sels_0_T_26 = bits(free_list, 26, 26) node _sels_sels_0_T_27 = bits(free_list, 27, 27) node _sels_sels_0_T_28 = bits(free_list, 28, 28) node _sels_sels_0_T_29 = bits(free_list, 29, 29) node _sels_sels_0_T_30 = bits(free_list, 30, 30) node _sels_sels_0_T_31 = bits(free_list, 31, 31) node _sels_sels_0_T_32 = bits(free_list, 32, 32) node _sels_sels_0_T_33 = bits(free_list, 33, 33) node _sels_sels_0_T_34 = bits(free_list, 34, 34) node _sels_sels_0_T_35 = bits(free_list, 35, 35) node _sels_sels_0_T_36 = bits(free_list, 36, 36) node _sels_sels_0_T_37 = bits(free_list, 37, 37) node _sels_sels_0_T_38 = bits(free_list, 38, 38) node _sels_sels_0_T_39 = bits(free_list, 39, 39) node _sels_sels_0_T_40 = bits(free_list, 40, 40) node _sels_sels_0_T_41 = bits(free_list, 41, 41) node _sels_sels_0_T_42 = bits(free_list, 42, 42) node _sels_sels_0_T_43 = bits(free_list, 43, 43) node _sels_sels_0_T_44 = bits(free_list, 44, 44) node _sels_sels_0_T_45 = bits(free_list, 45, 45) node _sels_sels_0_T_46 = bits(free_list, 46, 46) node _sels_sels_0_T_47 = bits(free_list, 47, 47) node _sels_sels_0_T_48 = bits(free_list, 48, 48) node _sels_sels_0_T_49 = bits(free_list, 49, 49) node _sels_sels_0_T_50 = bits(free_list, 50, 50) node _sels_sels_0_T_51 = bits(free_list, 51, 51) node _sels_sels_0_T_52 = bits(free_list, 52, 52) node _sels_sels_0_T_53 = bits(free_list, 53, 53) node _sels_sels_0_T_54 = bits(free_list, 54, 54) node _sels_sels_0_T_55 = bits(free_list, 55, 55) node _sels_sels_0_T_56 = bits(free_list, 56, 56) node _sels_sels_0_T_57 = bits(free_list, 57, 57) node _sels_sels_0_T_58 = bits(free_list, 58, 58) node _sels_sels_0_T_59 = bits(free_list, 59, 59) node _sels_sels_0_T_60 = bits(free_list, 60, 60) node _sels_sels_0_T_61 = bits(free_list, 61, 61) node _sels_sels_0_T_62 = bits(free_list, 62, 62) node _sels_sels_0_T_63 = bits(free_list, 63, 63) node _sels_sels_0_T_64 = bits(free_list, 64, 64) node _sels_sels_0_T_65 = bits(free_list, 65, 65) node _sels_sels_0_T_66 = bits(free_list, 66, 66) node _sels_sels_0_T_67 = bits(free_list, 67, 67) node _sels_sels_0_T_68 = bits(free_list, 68, 68) node _sels_sels_0_T_69 = bits(free_list, 69, 69) node _sels_sels_0_T_70 = bits(free_list, 70, 70) node _sels_sels_0_T_71 = bits(free_list, 71, 71) node _sels_sels_0_T_72 = bits(free_list, 72, 72) node _sels_sels_0_T_73 = bits(free_list, 73, 73) node _sels_sels_0_T_74 = bits(free_list, 74, 74) node _sels_sels_0_T_75 = bits(free_list, 75, 75) node _sels_sels_0_T_76 = bits(free_list, 76, 76) node _sels_sels_0_T_77 = bits(free_list, 77, 77) node _sels_sels_0_T_78 = bits(free_list, 78, 78) node _sels_sels_0_T_79 = bits(free_list, 79, 79) node _sels_sels_0_T_80 = mux(_sels_sels_0_T_79, UInt<80>(0h80000000000000000000), UInt<80>(0h0)) node _sels_sels_0_T_81 = mux(_sels_sels_0_T_78, UInt<80>(0h40000000000000000000), _sels_sels_0_T_80) node _sels_sels_0_T_82 = mux(_sels_sels_0_T_77, UInt<80>(0h20000000000000000000), _sels_sels_0_T_81) node _sels_sels_0_T_83 = mux(_sels_sels_0_T_76, UInt<80>(0h10000000000000000000), _sels_sels_0_T_82) node _sels_sels_0_T_84 = mux(_sels_sels_0_T_75, UInt<80>(0h8000000000000000000), _sels_sels_0_T_83) node _sels_sels_0_T_85 = mux(_sels_sels_0_T_74, UInt<80>(0h4000000000000000000), _sels_sels_0_T_84) node _sels_sels_0_T_86 = mux(_sels_sels_0_T_73, UInt<80>(0h2000000000000000000), _sels_sels_0_T_85) node _sels_sels_0_T_87 = mux(_sels_sels_0_T_72, UInt<80>(0h1000000000000000000), _sels_sels_0_T_86) node _sels_sels_0_T_88 = mux(_sels_sels_0_T_71, UInt<80>(0h800000000000000000), _sels_sels_0_T_87) node _sels_sels_0_T_89 = mux(_sels_sels_0_T_70, UInt<80>(0h400000000000000000), _sels_sels_0_T_88) node _sels_sels_0_T_90 = mux(_sels_sels_0_T_69, UInt<80>(0h200000000000000000), _sels_sels_0_T_89) node _sels_sels_0_T_91 = mux(_sels_sels_0_T_68, UInt<80>(0h100000000000000000), _sels_sels_0_T_90) node _sels_sels_0_T_92 = mux(_sels_sels_0_T_67, UInt<80>(0h80000000000000000), _sels_sels_0_T_91) node _sels_sels_0_T_93 = mux(_sels_sels_0_T_66, UInt<80>(0h40000000000000000), _sels_sels_0_T_92) node _sels_sels_0_T_94 = mux(_sels_sels_0_T_65, UInt<80>(0h20000000000000000), _sels_sels_0_T_93) node _sels_sels_0_T_95 = mux(_sels_sels_0_T_64, UInt<80>(0h10000000000000000), _sels_sels_0_T_94) node _sels_sels_0_T_96 = mux(_sels_sels_0_T_63, UInt<80>(0h8000000000000000), _sels_sels_0_T_95) node _sels_sels_0_T_97 = mux(_sels_sels_0_T_62, UInt<80>(0h4000000000000000), _sels_sels_0_T_96) node _sels_sels_0_T_98 = mux(_sels_sels_0_T_61, UInt<80>(0h2000000000000000), _sels_sels_0_T_97) node _sels_sels_0_T_99 = mux(_sels_sels_0_T_60, UInt<80>(0h1000000000000000), _sels_sels_0_T_98) node _sels_sels_0_T_100 = mux(_sels_sels_0_T_59, UInt<80>(0h800000000000000), _sels_sels_0_T_99) node _sels_sels_0_T_101 = mux(_sels_sels_0_T_58, UInt<80>(0h400000000000000), _sels_sels_0_T_100) node _sels_sels_0_T_102 = mux(_sels_sels_0_T_57, UInt<80>(0h200000000000000), _sels_sels_0_T_101) node _sels_sels_0_T_103 = mux(_sels_sels_0_T_56, UInt<80>(0h100000000000000), _sels_sels_0_T_102) node _sels_sels_0_T_104 = mux(_sels_sels_0_T_55, UInt<80>(0h80000000000000), _sels_sels_0_T_103) node _sels_sels_0_T_105 = mux(_sels_sels_0_T_54, UInt<80>(0h40000000000000), _sels_sels_0_T_104) node _sels_sels_0_T_106 = mux(_sels_sels_0_T_53, UInt<80>(0h20000000000000), _sels_sels_0_T_105) node _sels_sels_0_T_107 = mux(_sels_sels_0_T_52, UInt<80>(0h10000000000000), _sels_sels_0_T_106) node _sels_sels_0_T_108 = mux(_sels_sels_0_T_51, UInt<80>(0h8000000000000), _sels_sels_0_T_107) node _sels_sels_0_T_109 = mux(_sels_sels_0_T_50, UInt<80>(0h4000000000000), _sels_sels_0_T_108) node _sels_sels_0_T_110 = mux(_sels_sels_0_T_49, UInt<80>(0h2000000000000), _sels_sels_0_T_109) node _sels_sels_0_T_111 = mux(_sels_sels_0_T_48, UInt<80>(0h1000000000000), _sels_sels_0_T_110) node _sels_sels_0_T_112 = mux(_sels_sels_0_T_47, UInt<80>(0h800000000000), _sels_sels_0_T_111) node _sels_sels_0_T_113 = mux(_sels_sels_0_T_46, UInt<80>(0h400000000000), _sels_sels_0_T_112) node _sels_sels_0_T_114 = mux(_sels_sels_0_T_45, UInt<80>(0h200000000000), _sels_sels_0_T_113) node _sels_sels_0_T_115 = mux(_sels_sels_0_T_44, UInt<80>(0h100000000000), _sels_sels_0_T_114) node _sels_sels_0_T_116 = mux(_sels_sels_0_T_43, UInt<80>(0h80000000000), _sels_sels_0_T_115) node _sels_sels_0_T_117 = mux(_sels_sels_0_T_42, UInt<80>(0h40000000000), _sels_sels_0_T_116) node _sels_sels_0_T_118 = mux(_sels_sels_0_T_41, UInt<80>(0h20000000000), _sels_sels_0_T_117) node _sels_sels_0_T_119 = mux(_sels_sels_0_T_40, UInt<80>(0h10000000000), _sels_sels_0_T_118) node _sels_sels_0_T_120 = mux(_sels_sels_0_T_39, UInt<80>(0h8000000000), _sels_sels_0_T_119) node _sels_sels_0_T_121 = mux(_sels_sels_0_T_38, UInt<80>(0h4000000000), _sels_sels_0_T_120) node _sels_sels_0_T_122 = mux(_sels_sels_0_T_37, UInt<80>(0h2000000000), _sels_sels_0_T_121) node _sels_sels_0_T_123 = mux(_sels_sels_0_T_36, UInt<80>(0h1000000000), _sels_sels_0_T_122) node _sels_sels_0_T_124 = mux(_sels_sels_0_T_35, UInt<80>(0h800000000), _sels_sels_0_T_123) node _sels_sels_0_T_125 = mux(_sels_sels_0_T_34, UInt<80>(0h400000000), _sels_sels_0_T_124) node _sels_sels_0_T_126 = mux(_sels_sels_0_T_33, UInt<80>(0h200000000), _sels_sels_0_T_125) node _sels_sels_0_T_127 = mux(_sels_sels_0_T_32, UInt<80>(0h100000000), _sels_sels_0_T_126) node _sels_sels_0_T_128 = mux(_sels_sels_0_T_31, UInt<80>(0h80000000), _sels_sels_0_T_127) node _sels_sels_0_T_129 = mux(_sels_sels_0_T_30, UInt<80>(0h40000000), _sels_sels_0_T_128) node _sels_sels_0_T_130 = mux(_sels_sels_0_T_29, UInt<80>(0h20000000), _sels_sels_0_T_129) node _sels_sels_0_T_131 = mux(_sels_sels_0_T_28, UInt<80>(0h10000000), _sels_sels_0_T_130) node _sels_sels_0_T_132 = mux(_sels_sels_0_T_27, UInt<80>(0h8000000), _sels_sels_0_T_131) node _sels_sels_0_T_133 = mux(_sels_sels_0_T_26, UInt<80>(0h4000000), _sels_sels_0_T_132) node _sels_sels_0_T_134 = mux(_sels_sels_0_T_25, UInt<80>(0h2000000), _sels_sels_0_T_133) node _sels_sels_0_T_135 = mux(_sels_sels_0_T_24, UInt<80>(0h1000000), _sels_sels_0_T_134) node _sels_sels_0_T_136 = mux(_sels_sels_0_T_23, UInt<80>(0h800000), _sels_sels_0_T_135) node _sels_sels_0_T_137 = mux(_sels_sels_0_T_22, UInt<80>(0h400000), _sels_sels_0_T_136) node _sels_sels_0_T_138 = mux(_sels_sels_0_T_21, UInt<80>(0h200000), _sels_sels_0_T_137) node _sels_sels_0_T_139 = mux(_sels_sels_0_T_20, UInt<80>(0h100000), _sels_sels_0_T_138) node _sels_sels_0_T_140 = mux(_sels_sels_0_T_19, UInt<80>(0h80000), _sels_sels_0_T_139) node _sels_sels_0_T_141 = mux(_sels_sels_0_T_18, UInt<80>(0h40000), _sels_sels_0_T_140) node _sels_sels_0_T_142 = mux(_sels_sels_0_T_17, UInt<80>(0h20000), _sels_sels_0_T_141) node _sels_sels_0_T_143 = mux(_sels_sels_0_T_16, UInt<80>(0h10000), _sels_sels_0_T_142) node _sels_sels_0_T_144 = mux(_sels_sels_0_T_15, UInt<80>(0h8000), _sels_sels_0_T_143) node _sels_sels_0_T_145 = mux(_sels_sels_0_T_14, UInt<80>(0h4000), _sels_sels_0_T_144) node _sels_sels_0_T_146 = mux(_sels_sels_0_T_13, UInt<80>(0h2000), _sels_sels_0_T_145) node _sels_sels_0_T_147 = mux(_sels_sels_0_T_12, UInt<80>(0h1000), _sels_sels_0_T_146) node _sels_sels_0_T_148 = mux(_sels_sels_0_T_11, UInt<80>(0h800), _sels_sels_0_T_147) node _sels_sels_0_T_149 = mux(_sels_sels_0_T_10, UInt<80>(0h400), _sels_sels_0_T_148) node _sels_sels_0_T_150 = mux(_sels_sels_0_T_9, UInt<80>(0h200), _sels_sels_0_T_149) node _sels_sels_0_T_151 = mux(_sels_sels_0_T_8, UInt<80>(0h100), _sels_sels_0_T_150) node _sels_sels_0_T_152 = mux(_sels_sels_0_T_7, UInt<80>(0h80), _sels_sels_0_T_151) node _sels_sels_0_T_153 = mux(_sels_sels_0_T_6, UInt<80>(0h40), _sels_sels_0_T_152) node _sels_sels_0_T_154 = mux(_sels_sels_0_T_5, UInt<80>(0h20), _sels_sels_0_T_153) node _sels_sels_0_T_155 = mux(_sels_sels_0_T_4, UInt<80>(0h10), _sels_sels_0_T_154) node _sels_sels_0_T_156 = mux(_sels_sels_0_T_3, UInt<80>(0h8), _sels_sels_0_T_155) node _sels_sels_0_T_157 = mux(_sels_sels_0_T_2, UInt<80>(0h4), _sels_sels_0_T_156) node _sels_sels_0_T_158 = mux(_sels_sels_0_T_1, UInt<80>(0h2), _sels_sels_0_T_157) node _sels_sels_0_T_159 = mux(_sels_sels_0_T, UInt<80>(0h1), _sels_sels_0_T_158) connect sels[0], _sels_sels_0_T_159 node _sels_T = not(sels[0]) node _sels_T_1 = and(free_list, _sels_T) node _sels_sels_1_T = bits(_sels_T_1, 0, 0) node _sels_sels_1_T_1 = bits(_sels_T_1, 1, 1) node _sels_sels_1_T_2 = bits(_sels_T_1, 2, 2) node _sels_sels_1_T_3 = bits(_sels_T_1, 3, 3) node _sels_sels_1_T_4 = bits(_sels_T_1, 4, 4) node _sels_sels_1_T_5 = bits(_sels_T_1, 5, 5) node _sels_sels_1_T_6 = bits(_sels_T_1, 6, 6) node _sels_sels_1_T_7 = bits(_sels_T_1, 7, 7) node _sels_sels_1_T_8 = bits(_sels_T_1, 8, 8) node _sels_sels_1_T_9 = bits(_sels_T_1, 9, 9) node _sels_sels_1_T_10 = bits(_sels_T_1, 10, 10) node _sels_sels_1_T_11 = bits(_sels_T_1, 11, 11) node _sels_sels_1_T_12 = bits(_sels_T_1, 12, 12) node _sels_sels_1_T_13 = bits(_sels_T_1, 13, 13) node _sels_sels_1_T_14 = bits(_sels_T_1, 14, 14) node _sels_sels_1_T_15 = bits(_sels_T_1, 15, 15) node _sels_sels_1_T_16 = bits(_sels_T_1, 16, 16) node _sels_sels_1_T_17 = bits(_sels_T_1, 17, 17) node _sels_sels_1_T_18 = bits(_sels_T_1, 18, 18) node _sels_sels_1_T_19 = bits(_sels_T_1, 19, 19) node _sels_sels_1_T_20 = bits(_sels_T_1, 20, 20) node _sels_sels_1_T_21 = bits(_sels_T_1, 21, 21) node _sels_sels_1_T_22 = bits(_sels_T_1, 22, 22) node _sels_sels_1_T_23 = bits(_sels_T_1, 23, 23) node _sels_sels_1_T_24 = bits(_sels_T_1, 24, 24) node _sels_sels_1_T_25 = bits(_sels_T_1, 25, 25) node _sels_sels_1_T_26 = bits(_sels_T_1, 26, 26) node _sels_sels_1_T_27 = bits(_sels_T_1, 27, 27) node _sels_sels_1_T_28 = bits(_sels_T_1, 28, 28) node _sels_sels_1_T_29 = bits(_sels_T_1, 29, 29) node _sels_sels_1_T_30 = bits(_sels_T_1, 30, 30) node _sels_sels_1_T_31 = bits(_sels_T_1, 31, 31) node _sels_sels_1_T_32 = bits(_sels_T_1, 32, 32) node _sels_sels_1_T_33 = bits(_sels_T_1, 33, 33) node _sels_sels_1_T_34 = bits(_sels_T_1, 34, 34) node _sels_sels_1_T_35 = bits(_sels_T_1, 35, 35) node _sels_sels_1_T_36 = bits(_sels_T_1, 36, 36) node _sels_sels_1_T_37 = bits(_sels_T_1, 37, 37) node _sels_sels_1_T_38 = bits(_sels_T_1, 38, 38) node _sels_sels_1_T_39 = bits(_sels_T_1, 39, 39) node _sels_sels_1_T_40 = bits(_sels_T_1, 40, 40) node _sels_sels_1_T_41 = bits(_sels_T_1, 41, 41) node _sels_sels_1_T_42 = bits(_sels_T_1, 42, 42) node _sels_sels_1_T_43 = bits(_sels_T_1, 43, 43) node _sels_sels_1_T_44 = bits(_sels_T_1, 44, 44) node _sels_sels_1_T_45 = bits(_sels_T_1, 45, 45) node _sels_sels_1_T_46 = bits(_sels_T_1, 46, 46) node _sels_sels_1_T_47 = bits(_sels_T_1, 47, 47) node _sels_sels_1_T_48 = bits(_sels_T_1, 48, 48) node _sels_sels_1_T_49 = bits(_sels_T_1, 49, 49) node _sels_sels_1_T_50 = bits(_sels_T_1, 50, 50) node _sels_sels_1_T_51 = bits(_sels_T_1, 51, 51) node _sels_sels_1_T_52 = bits(_sels_T_1, 52, 52) node _sels_sels_1_T_53 = bits(_sels_T_1, 53, 53) node _sels_sels_1_T_54 = bits(_sels_T_1, 54, 54) node _sels_sels_1_T_55 = bits(_sels_T_1, 55, 55) node _sels_sels_1_T_56 = bits(_sels_T_1, 56, 56) node _sels_sels_1_T_57 = bits(_sels_T_1, 57, 57) node _sels_sels_1_T_58 = bits(_sels_T_1, 58, 58) node _sels_sels_1_T_59 = bits(_sels_T_1, 59, 59) node _sels_sels_1_T_60 = bits(_sels_T_1, 60, 60) node _sels_sels_1_T_61 = bits(_sels_T_1, 61, 61) node _sels_sels_1_T_62 = bits(_sels_T_1, 62, 62) node _sels_sels_1_T_63 = bits(_sels_T_1, 63, 63) node _sels_sels_1_T_64 = bits(_sels_T_1, 64, 64) node _sels_sels_1_T_65 = bits(_sels_T_1, 65, 65) node _sels_sels_1_T_66 = bits(_sels_T_1, 66, 66) node _sels_sels_1_T_67 = bits(_sels_T_1, 67, 67) node _sels_sels_1_T_68 = bits(_sels_T_1, 68, 68) node _sels_sels_1_T_69 = bits(_sels_T_1, 69, 69) node _sels_sels_1_T_70 = bits(_sels_T_1, 70, 70) node _sels_sels_1_T_71 = bits(_sels_T_1, 71, 71) node _sels_sels_1_T_72 = bits(_sels_T_1, 72, 72) node _sels_sels_1_T_73 = bits(_sels_T_1, 73, 73) node _sels_sels_1_T_74 = bits(_sels_T_1, 74, 74) node _sels_sels_1_T_75 = bits(_sels_T_1, 75, 75) node _sels_sels_1_T_76 = bits(_sels_T_1, 76, 76) node _sels_sels_1_T_77 = bits(_sels_T_1, 77, 77) node _sels_sels_1_T_78 = bits(_sels_T_1, 78, 78) node _sels_sels_1_T_79 = bits(_sels_T_1, 79, 79) node _sels_sels_1_T_80 = mux(_sels_sels_1_T_79, UInt<80>(0h80000000000000000000), UInt<80>(0h0)) node _sels_sels_1_T_81 = mux(_sels_sels_1_T_78, UInt<80>(0h40000000000000000000), _sels_sels_1_T_80) node _sels_sels_1_T_82 = mux(_sels_sels_1_T_77, UInt<80>(0h20000000000000000000), _sels_sels_1_T_81) node _sels_sels_1_T_83 = mux(_sels_sels_1_T_76, UInt<80>(0h10000000000000000000), _sels_sels_1_T_82) node _sels_sels_1_T_84 = mux(_sels_sels_1_T_75, UInt<80>(0h8000000000000000000), _sels_sels_1_T_83) node _sels_sels_1_T_85 = mux(_sels_sels_1_T_74, UInt<80>(0h4000000000000000000), _sels_sels_1_T_84) node _sels_sels_1_T_86 = mux(_sels_sels_1_T_73, UInt<80>(0h2000000000000000000), _sels_sels_1_T_85) node _sels_sels_1_T_87 = mux(_sels_sels_1_T_72, UInt<80>(0h1000000000000000000), _sels_sels_1_T_86) node _sels_sels_1_T_88 = mux(_sels_sels_1_T_71, UInt<80>(0h800000000000000000), _sels_sels_1_T_87) node _sels_sels_1_T_89 = mux(_sels_sels_1_T_70, UInt<80>(0h400000000000000000), _sels_sels_1_T_88) node _sels_sels_1_T_90 = mux(_sels_sels_1_T_69, UInt<80>(0h200000000000000000), _sels_sels_1_T_89) node _sels_sels_1_T_91 = mux(_sels_sels_1_T_68, UInt<80>(0h100000000000000000), _sels_sels_1_T_90) node _sels_sels_1_T_92 = mux(_sels_sels_1_T_67, UInt<80>(0h80000000000000000), _sels_sels_1_T_91) node _sels_sels_1_T_93 = mux(_sels_sels_1_T_66, UInt<80>(0h40000000000000000), _sels_sels_1_T_92) node _sels_sels_1_T_94 = mux(_sels_sels_1_T_65, UInt<80>(0h20000000000000000), _sels_sels_1_T_93) node _sels_sels_1_T_95 = mux(_sels_sels_1_T_64, UInt<80>(0h10000000000000000), _sels_sels_1_T_94) node _sels_sels_1_T_96 = mux(_sels_sels_1_T_63, UInt<80>(0h8000000000000000), _sels_sels_1_T_95) node _sels_sels_1_T_97 = mux(_sels_sels_1_T_62, UInt<80>(0h4000000000000000), _sels_sels_1_T_96) node _sels_sels_1_T_98 = mux(_sels_sels_1_T_61, UInt<80>(0h2000000000000000), _sels_sels_1_T_97) node _sels_sels_1_T_99 = mux(_sels_sels_1_T_60, UInt<80>(0h1000000000000000), _sels_sels_1_T_98) node _sels_sels_1_T_100 = mux(_sels_sels_1_T_59, UInt<80>(0h800000000000000), _sels_sels_1_T_99) node _sels_sels_1_T_101 = mux(_sels_sels_1_T_58, UInt<80>(0h400000000000000), _sels_sels_1_T_100) node _sels_sels_1_T_102 = mux(_sels_sels_1_T_57, UInt<80>(0h200000000000000), _sels_sels_1_T_101) node _sels_sels_1_T_103 = mux(_sels_sels_1_T_56, UInt<80>(0h100000000000000), _sels_sels_1_T_102) node _sels_sels_1_T_104 = mux(_sels_sels_1_T_55, UInt<80>(0h80000000000000), _sels_sels_1_T_103) node _sels_sels_1_T_105 = mux(_sels_sels_1_T_54, UInt<80>(0h40000000000000), _sels_sels_1_T_104) node _sels_sels_1_T_106 = mux(_sels_sels_1_T_53, UInt<80>(0h20000000000000), _sels_sels_1_T_105) node _sels_sels_1_T_107 = mux(_sels_sels_1_T_52, UInt<80>(0h10000000000000), _sels_sels_1_T_106) node _sels_sels_1_T_108 = mux(_sels_sels_1_T_51, UInt<80>(0h8000000000000), _sels_sels_1_T_107) node _sels_sels_1_T_109 = mux(_sels_sels_1_T_50, UInt<80>(0h4000000000000), _sels_sels_1_T_108) node _sels_sels_1_T_110 = mux(_sels_sels_1_T_49, UInt<80>(0h2000000000000), _sels_sels_1_T_109) node _sels_sels_1_T_111 = mux(_sels_sels_1_T_48, UInt<80>(0h1000000000000), _sels_sels_1_T_110) node _sels_sels_1_T_112 = mux(_sels_sels_1_T_47, UInt<80>(0h800000000000), _sels_sels_1_T_111) node _sels_sels_1_T_113 = mux(_sels_sels_1_T_46, UInt<80>(0h400000000000), _sels_sels_1_T_112) node _sels_sels_1_T_114 = mux(_sels_sels_1_T_45, UInt<80>(0h200000000000), _sels_sels_1_T_113) node _sels_sels_1_T_115 = mux(_sels_sels_1_T_44, UInt<80>(0h100000000000), _sels_sels_1_T_114) node _sels_sels_1_T_116 = mux(_sels_sels_1_T_43, UInt<80>(0h80000000000), _sels_sels_1_T_115) node _sels_sels_1_T_117 = mux(_sels_sels_1_T_42, UInt<80>(0h40000000000), _sels_sels_1_T_116) node _sels_sels_1_T_118 = mux(_sels_sels_1_T_41, UInt<80>(0h20000000000), _sels_sels_1_T_117) node _sels_sels_1_T_119 = mux(_sels_sels_1_T_40, UInt<80>(0h10000000000), _sels_sels_1_T_118) node _sels_sels_1_T_120 = mux(_sels_sels_1_T_39, UInt<80>(0h8000000000), _sels_sels_1_T_119) node _sels_sels_1_T_121 = mux(_sels_sels_1_T_38, UInt<80>(0h4000000000), _sels_sels_1_T_120) node _sels_sels_1_T_122 = mux(_sels_sels_1_T_37, UInt<80>(0h2000000000), _sels_sels_1_T_121) node _sels_sels_1_T_123 = mux(_sels_sels_1_T_36, UInt<80>(0h1000000000), _sels_sels_1_T_122) node _sels_sels_1_T_124 = mux(_sels_sels_1_T_35, UInt<80>(0h800000000), _sels_sels_1_T_123) node _sels_sels_1_T_125 = mux(_sels_sels_1_T_34, UInt<80>(0h400000000), _sels_sels_1_T_124) node _sels_sels_1_T_126 = mux(_sels_sels_1_T_33, UInt<80>(0h200000000), _sels_sels_1_T_125) node _sels_sels_1_T_127 = mux(_sels_sels_1_T_32, UInt<80>(0h100000000), _sels_sels_1_T_126) node _sels_sels_1_T_128 = mux(_sels_sels_1_T_31, UInt<80>(0h80000000), _sels_sels_1_T_127) node _sels_sels_1_T_129 = mux(_sels_sels_1_T_30, UInt<80>(0h40000000), _sels_sels_1_T_128) node _sels_sels_1_T_130 = mux(_sels_sels_1_T_29, UInt<80>(0h20000000), _sels_sels_1_T_129) node _sels_sels_1_T_131 = mux(_sels_sels_1_T_28, UInt<80>(0h10000000), _sels_sels_1_T_130) node _sels_sels_1_T_132 = mux(_sels_sels_1_T_27, UInt<80>(0h8000000), _sels_sels_1_T_131) node _sels_sels_1_T_133 = mux(_sels_sels_1_T_26, UInt<80>(0h4000000), _sels_sels_1_T_132) node _sels_sels_1_T_134 = mux(_sels_sels_1_T_25, UInt<80>(0h2000000), _sels_sels_1_T_133) node _sels_sels_1_T_135 = mux(_sels_sels_1_T_24, UInt<80>(0h1000000), _sels_sels_1_T_134) node _sels_sels_1_T_136 = mux(_sels_sels_1_T_23, UInt<80>(0h800000), _sels_sels_1_T_135) node _sels_sels_1_T_137 = mux(_sels_sels_1_T_22, UInt<80>(0h400000), _sels_sels_1_T_136) node _sels_sels_1_T_138 = mux(_sels_sels_1_T_21, UInt<80>(0h200000), _sels_sels_1_T_137) node _sels_sels_1_T_139 = mux(_sels_sels_1_T_20, UInt<80>(0h100000), _sels_sels_1_T_138) node _sels_sels_1_T_140 = mux(_sels_sels_1_T_19, UInt<80>(0h80000), _sels_sels_1_T_139) node _sels_sels_1_T_141 = mux(_sels_sels_1_T_18, UInt<80>(0h40000), _sels_sels_1_T_140) node _sels_sels_1_T_142 = mux(_sels_sels_1_T_17, UInt<80>(0h20000), _sels_sels_1_T_141) node _sels_sels_1_T_143 = mux(_sels_sels_1_T_16, UInt<80>(0h10000), _sels_sels_1_T_142) node _sels_sels_1_T_144 = mux(_sels_sels_1_T_15, UInt<80>(0h8000), _sels_sels_1_T_143) node _sels_sels_1_T_145 = mux(_sels_sels_1_T_14, UInt<80>(0h4000), _sels_sels_1_T_144) node _sels_sels_1_T_146 = mux(_sels_sels_1_T_13, UInt<80>(0h2000), _sels_sels_1_T_145) node _sels_sels_1_T_147 = mux(_sels_sels_1_T_12, UInt<80>(0h1000), _sels_sels_1_T_146) node _sels_sels_1_T_148 = mux(_sels_sels_1_T_11, UInt<80>(0h800), _sels_sels_1_T_147) node _sels_sels_1_T_149 = mux(_sels_sels_1_T_10, UInt<80>(0h400), _sels_sels_1_T_148) node _sels_sels_1_T_150 = mux(_sels_sels_1_T_9, UInt<80>(0h200), _sels_sels_1_T_149) node _sels_sels_1_T_151 = mux(_sels_sels_1_T_8, UInt<80>(0h100), _sels_sels_1_T_150) node _sels_sels_1_T_152 = mux(_sels_sels_1_T_7, UInt<80>(0h80), _sels_sels_1_T_151) node _sels_sels_1_T_153 = mux(_sels_sels_1_T_6, UInt<80>(0h40), _sels_sels_1_T_152) node _sels_sels_1_T_154 = mux(_sels_sels_1_T_5, UInt<80>(0h20), _sels_sels_1_T_153) node _sels_sels_1_T_155 = mux(_sels_sels_1_T_4, UInt<80>(0h10), _sels_sels_1_T_154) node _sels_sels_1_T_156 = mux(_sels_sels_1_T_3, UInt<80>(0h8), _sels_sels_1_T_155) node _sels_sels_1_T_157 = mux(_sels_sels_1_T_2, UInt<80>(0h4), _sels_sels_1_T_156) node _sels_sels_1_T_158 = mux(_sels_sels_1_T_1, UInt<80>(0h2), _sels_sels_1_T_157) node _sels_sels_1_T_159 = mux(_sels_sels_1_T, UInt<80>(0h1), _sels_sels_1_T_158) connect sels[1], _sels_sels_1_T_159 node _sels_T_2 = not(sels[1]) node _sels_T_3 = and(_sels_T_1, _sels_T_2) wire sel_fire : UInt<1>[2] node _allocs_T = dshl(UInt<1>(0h1), io.alloc_pregs[0].bits) node allocs_0 = bits(_allocs_T, 79, 0) node _allocs_T_1 = dshl(UInt<1>(0h1), io.alloc_pregs[1].bits) node allocs_1 = bits(_allocs_T_1, 79, 0) node _alloc_masks_T = mux(io.reqs[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _alloc_masks_T_1 = and(allocs_1, _alloc_masks_T) node alloc_masks_1 = or(UInt<80>(0h0), _alloc_masks_T_1) node _alloc_masks_T_2 = mux(io.reqs[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _alloc_masks_T_3 = and(allocs_0, _alloc_masks_T_2) node alloc_masks_0 = or(alloc_masks_1, _alloc_masks_T_3) node _sel_mask_T = mux(sel_fire[0], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _sel_mask_T_1 = and(sels[0], _sel_mask_T) node _sel_mask_T_2 = mux(sel_fire[1], UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _sel_mask_T_3 = and(sels[1], _sel_mask_T_2) node sel_mask = or(_sel_mask_T_1, _sel_mask_T_3) node _br_deallocs_T = mux(io.brupdate.b2.mispredict, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node br_deallocs = and(br_alloc_lists[io.brupdate.b2.uop.br_tag], _br_deallocs_T) reg com_deallocs_REG : { valid : UInt<1>, bits : UInt<7>}[2], clock connect com_deallocs_REG[0].bits, io.dealloc[0].bits connect com_deallocs_REG[0].valid, io.dealloc[0].valid connect com_deallocs_REG[1].bits, io.dealloc[1].bits connect com_deallocs_REG[1].valid, io.dealloc[1].valid node _com_deallocs_T = dshl(UInt<1>(0h1), com_deallocs_REG[0].bits) node _com_deallocs_T_1 = bits(_com_deallocs_T, 79, 0) node _com_deallocs_T_2 = mux(com_deallocs_REG[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_deallocs_T_3 = and(_com_deallocs_T_1, _com_deallocs_T_2) node _com_deallocs_T_4 = dshl(UInt<1>(0h1), com_deallocs_REG[1].bits) node _com_deallocs_T_5 = bits(_com_deallocs_T_4, 79, 0) node _com_deallocs_T_6 = mux(com_deallocs_REG[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_deallocs_T_7 = and(_com_deallocs_T_5, _com_deallocs_T_6) node com_deallocs = or(_com_deallocs_T_3, _com_deallocs_T_7) node _rollback_deallocs_T = mux(io.rollback, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node rollback_deallocs = and(spec_alloc_list, _rollback_deallocs_T) node _dealloc_mask_T = or(com_deallocs, br_deallocs) node dealloc_mask = or(_dealloc_mask_T, rollback_deallocs) node _com_despec_T = dshl(UInt<1>(0h1), io.despec[0].bits) node _com_despec_T_1 = bits(_com_despec_T, 79, 0) node _com_despec_T_2 = mux(io.despec[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_despec_T_3 = and(_com_despec_T_1, _com_despec_T_2) node _com_despec_T_4 = dshl(UInt<1>(0h1), io.despec[1].bits) node _com_despec_T_5 = bits(_com_despec_T_4, 79, 0) node _com_despec_T_6 = mux(io.despec[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _com_despec_T_7 = and(_com_despec_T_5, _com_despec_T_6) node com_despec = or(_com_despec_T_3, _com_despec_T_7) node _updated_br_alloc_list_T = not(br_deallocs) node _updated_br_alloc_list_T_1 = and(br_alloc_lists[0], _updated_br_alloc_list_T) node updated_br_alloc_list = or(_updated_br_alloc_list_T_1, alloc_masks_0) connect br_alloc_lists[0], updated_br_alloc_list node _updated_br_alloc_list_T_2 = not(br_deallocs) node _updated_br_alloc_list_T_3 = and(br_alloc_lists[1], _updated_br_alloc_list_T_2) node updated_br_alloc_list_1 = or(_updated_br_alloc_list_T_3, alloc_masks_0) connect br_alloc_lists[1], updated_br_alloc_list_1 node _updated_br_alloc_list_T_4 = not(br_deallocs) node _updated_br_alloc_list_T_5 = and(br_alloc_lists[2], _updated_br_alloc_list_T_4) node updated_br_alloc_list_2 = or(_updated_br_alloc_list_T_5, alloc_masks_0) connect br_alloc_lists[2], updated_br_alloc_list_2 node _updated_br_alloc_list_T_6 = not(br_deallocs) node _updated_br_alloc_list_T_7 = and(br_alloc_lists[3], _updated_br_alloc_list_T_6) node updated_br_alloc_list_3 = or(_updated_br_alloc_list_T_7, alloc_masks_0) connect br_alloc_lists[3], updated_br_alloc_list_3 node _updated_br_alloc_list_T_8 = not(br_deallocs) node _updated_br_alloc_list_T_9 = and(br_alloc_lists[4], _updated_br_alloc_list_T_8) node updated_br_alloc_list_4 = or(_updated_br_alloc_list_T_9, alloc_masks_0) connect br_alloc_lists[4], updated_br_alloc_list_4 node _updated_br_alloc_list_T_10 = not(br_deallocs) node _updated_br_alloc_list_T_11 = and(br_alloc_lists[5], _updated_br_alloc_list_T_10) node updated_br_alloc_list_5 = or(_updated_br_alloc_list_T_11, alloc_masks_0) connect br_alloc_lists[5], updated_br_alloc_list_5 node _updated_br_alloc_list_T_12 = not(br_deallocs) node _updated_br_alloc_list_T_13 = and(br_alloc_lists[6], _updated_br_alloc_list_T_12) node updated_br_alloc_list_6 = or(_updated_br_alloc_list_T_13, alloc_masks_0) connect br_alloc_lists[6], updated_br_alloc_list_6 node _updated_br_alloc_list_T_14 = not(br_deallocs) node _updated_br_alloc_list_T_15 = and(br_alloc_lists[7], _updated_br_alloc_list_T_14) node updated_br_alloc_list_7 = or(_updated_br_alloc_list_T_15, alloc_masks_0) connect br_alloc_lists[7], updated_br_alloc_list_7 node _updated_br_alloc_list_T_16 = not(br_deallocs) node _updated_br_alloc_list_T_17 = and(br_alloc_lists[8], _updated_br_alloc_list_T_16) node updated_br_alloc_list_8 = or(_updated_br_alloc_list_T_17, alloc_masks_0) connect br_alloc_lists[8], updated_br_alloc_list_8 node _updated_br_alloc_list_T_18 = not(br_deallocs) node _updated_br_alloc_list_T_19 = and(br_alloc_lists[9], _updated_br_alloc_list_T_18) node updated_br_alloc_list_9 = or(_updated_br_alloc_list_T_19, alloc_masks_0) connect br_alloc_lists[9], updated_br_alloc_list_9 node _updated_br_alloc_list_T_20 = not(br_deallocs) node _updated_br_alloc_list_T_21 = and(br_alloc_lists[10], _updated_br_alloc_list_T_20) node updated_br_alloc_list_10 = or(_updated_br_alloc_list_T_21, alloc_masks_0) connect br_alloc_lists[10], updated_br_alloc_list_10 node _updated_br_alloc_list_T_22 = not(br_deallocs) node _updated_br_alloc_list_T_23 = and(br_alloc_lists[11], _updated_br_alloc_list_T_22) node updated_br_alloc_list_11 = or(_updated_br_alloc_list_T_23, alloc_masks_0) connect br_alloc_lists[11], updated_br_alloc_list_11 wire _br_slots_WIRE : UInt<1>[3] connect _br_slots_WIRE[0], io.ren_br_tags[0].valid connect _br_slots_WIRE[1], io.ren_br_tags[1].valid connect _br_slots_WIRE[2], io.ren_br_tags[2].valid node br_slots_hi = cat(_br_slots_WIRE[2], _br_slots_WIRE[1]) node br_slots = cat(br_slots_hi, _br_slots_WIRE[0]) node _list_req_T = eq(io.ren_br_tags[0].bits, UInt<1>(0h0)) node _list_req_T_1 = eq(io.ren_br_tags[1].bits, UInt<1>(0h0)) node _list_req_T_2 = eq(io.ren_br_tags[2].bits, UInt<1>(0h0)) wire _list_req_WIRE : UInt<1>[3] connect _list_req_WIRE[0], _list_req_T connect _list_req_WIRE[1], _list_req_T_1 connect _list_req_WIRE[2], _list_req_T_2 node list_req_hi = cat(_list_req_WIRE[2], _list_req_WIRE[1]) node _list_req_T_3 = cat(list_req_hi, _list_req_WIRE[0]) node list_req = and(_list_req_T_3, br_slots) node new_list = orr(list_req) when new_list : node _br_alloc_lists_0_T = bits(list_req, 0, 0) node _br_alloc_lists_0_T_1 = bits(list_req, 1, 1) node _br_alloc_lists_0_T_2 = bits(list_req, 2, 2) node _br_alloc_lists_0_T_3 = mux(_br_alloc_lists_0_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_0_T_4 = mux(_br_alloc_lists_0_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_0_T_5 = mux(_br_alloc_lists_0_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_0_T_6 = or(_br_alloc_lists_0_T_3, _br_alloc_lists_0_T_4) node _br_alloc_lists_0_T_7 = or(_br_alloc_lists_0_T_6, _br_alloc_lists_0_T_5) wire _br_alloc_lists_0_WIRE : UInt<80> connect _br_alloc_lists_0_WIRE, _br_alloc_lists_0_T_7 connect br_alloc_lists[0], _br_alloc_lists_0_WIRE node _list_req_T_4 = eq(io.ren_br_tags[0].bits, UInt<1>(0h1)) node _list_req_T_5 = eq(io.ren_br_tags[1].bits, UInt<1>(0h1)) node _list_req_T_6 = eq(io.ren_br_tags[2].bits, UInt<1>(0h1)) wire _list_req_WIRE_1 : UInt<1>[3] connect _list_req_WIRE_1[0], _list_req_T_4 connect _list_req_WIRE_1[1], _list_req_T_5 connect _list_req_WIRE_1[2], _list_req_T_6 node list_req_hi_1 = cat(_list_req_WIRE_1[2], _list_req_WIRE_1[1]) node _list_req_T_7 = cat(list_req_hi_1, _list_req_WIRE_1[0]) node list_req_1 = and(_list_req_T_7, br_slots) node new_list_1 = orr(list_req_1) when new_list_1 : node _br_alloc_lists_1_T = bits(list_req_1, 0, 0) node _br_alloc_lists_1_T_1 = bits(list_req_1, 1, 1) node _br_alloc_lists_1_T_2 = bits(list_req_1, 2, 2) node _br_alloc_lists_1_T_3 = mux(_br_alloc_lists_1_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_1_T_4 = mux(_br_alloc_lists_1_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_1_T_5 = mux(_br_alloc_lists_1_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_1_T_6 = or(_br_alloc_lists_1_T_3, _br_alloc_lists_1_T_4) node _br_alloc_lists_1_T_7 = or(_br_alloc_lists_1_T_6, _br_alloc_lists_1_T_5) wire _br_alloc_lists_1_WIRE : UInt<80> connect _br_alloc_lists_1_WIRE, _br_alloc_lists_1_T_7 connect br_alloc_lists[1], _br_alloc_lists_1_WIRE node _list_req_T_8 = eq(io.ren_br_tags[0].bits, UInt<2>(0h2)) node _list_req_T_9 = eq(io.ren_br_tags[1].bits, UInt<2>(0h2)) node _list_req_T_10 = eq(io.ren_br_tags[2].bits, UInt<2>(0h2)) wire _list_req_WIRE_2 : UInt<1>[3] connect _list_req_WIRE_2[0], _list_req_T_8 connect _list_req_WIRE_2[1], _list_req_T_9 connect _list_req_WIRE_2[2], _list_req_T_10 node list_req_hi_2 = cat(_list_req_WIRE_2[2], _list_req_WIRE_2[1]) node _list_req_T_11 = cat(list_req_hi_2, _list_req_WIRE_2[0]) node list_req_2 = and(_list_req_T_11, br_slots) node new_list_2 = orr(list_req_2) when new_list_2 : node _br_alloc_lists_2_T = bits(list_req_2, 0, 0) node _br_alloc_lists_2_T_1 = bits(list_req_2, 1, 1) node _br_alloc_lists_2_T_2 = bits(list_req_2, 2, 2) node _br_alloc_lists_2_T_3 = mux(_br_alloc_lists_2_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_2_T_4 = mux(_br_alloc_lists_2_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_2_T_5 = mux(_br_alloc_lists_2_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_2_T_6 = or(_br_alloc_lists_2_T_3, _br_alloc_lists_2_T_4) node _br_alloc_lists_2_T_7 = or(_br_alloc_lists_2_T_6, _br_alloc_lists_2_T_5) wire _br_alloc_lists_2_WIRE : UInt<80> connect _br_alloc_lists_2_WIRE, _br_alloc_lists_2_T_7 connect br_alloc_lists[2], _br_alloc_lists_2_WIRE node _list_req_T_12 = eq(io.ren_br_tags[0].bits, UInt<2>(0h3)) node _list_req_T_13 = eq(io.ren_br_tags[1].bits, UInt<2>(0h3)) node _list_req_T_14 = eq(io.ren_br_tags[2].bits, UInt<2>(0h3)) wire _list_req_WIRE_3 : UInt<1>[3] connect _list_req_WIRE_3[0], _list_req_T_12 connect _list_req_WIRE_3[1], _list_req_T_13 connect _list_req_WIRE_3[2], _list_req_T_14 node list_req_hi_3 = cat(_list_req_WIRE_3[2], _list_req_WIRE_3[1]) node _list_req_T_15 = cat(list_req_hi_3, _list_req_WIRE_3[0]) node list_req_3 = and(_list_req_T_15, br_slots) node new_list_3 = orr(list_req_3) when new_list_3 : node _br_alloc_lists_3_T = bits(list_req_3, 0, 0) node _br_alloc_lists_3_T_1 = bits(list_req_3, 1, 1) node _br_alloc_lists_3_T_2 = bits(list_req_3, 2, 2) node _br_alloc_lists_3_T_3 = mux(_br_alloc_lists_3_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_3_T_4 = mux(_br_alloc_lists_3_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_3_T_5 = mux(_br_alloc_lists_3_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_3_T_6 = or(_br_alloc_lists_3_T_3, _br_alloc_lists_3_T_4) node _br_alloc_lists_3_T_7 = or(_br_alloc_lists_3_T_6, _br_alloc_lists_3_T_5) wire _br_alloc_lists_3_WIRE : UInt<80> connect _br_alloc_lists_3_WIRE, _br_alloc_lists_3_T_7 connect br_alloc_lists[3], _br_alloc_lists_3_WIRE node _list_req_T_16 = eq(io.ren_br_tags[0].bits, UInt<3>(0h4)) node _list_req_T_17 = eq(io.ren_br_tags[1].bits, UInt<3>(0h4)) node _list_req_T_18 = eq(io.ren_br_tags[2].bits, UInt<3>(0h4)) wire _list_req_WIRE_4 : UInt<1>[3] connect _list_req_WIRE_4[0], _list_req_T_16 connect _list_req_WIRE_4[1], _list_req_T_17 connect _list_req_WIRE_4[2], _list_req_T_18 node list_req_hi_4 = cat(_list_req_WIRE_4[2], _list_req_WIRE_4[1]) node _list_req_T_19 = cat(list_req_hi_4, _list_req_WIRE_4[0]) node list_req_4 = and(_list_req_T_19, br_slots) node new_list_4 = orr(list_req_4) when new_list_4 : node _br_alloc_lists_4_T = bits(list_req_4, 0, 0) node _br_alloc_lists_4_T_1 = bits(list_req_4, 1, 1) node _br_alloc_lists_4_T_2 = bits(list_req_4, 2, 2) node _br_alloc_lists_4_T_3 = mux(_br_alloc_lists_4_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_4_T_4 = mux(_br_alloc_lists_4_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_4_T_5 = mux(_br_alloc_lists_4_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_4_T_6 = or(_br_alloc_lists_4_T_3, _br_alloc_lists_4_T_4) node _br_alloc_lists_4_T_7 = or(_br_alloc_lists_4_T_6, _br_alloc_lists_4_T_5) wire _br_alloc_lists_4_WIRE : UInt<80> connect _br_alloc_lists_4_WIRE, _br_alloc_lists_4_T_7 connect br_alloc_lists[4], _br_alloc_lists_4_WIRE node _list_req_T_20 = eq(io.ren_br_tags[0].bits, UInt<3>(0h5)) node _list_req_T_21 = eq(io.ren_br_tags[1].bits, UInt<3>(0h5)) node _list_req_T_22 = eq(io.ren_br_tags[2].bits, UInt<3>(0h5)) wire _list_req_WIRE_5 : UInt<1>[3] connect _list_req_WIRE_5[0], _list_req_T_20 connect _list_req_WIRE_5[1], _list_req_T_21 connect _list_req_WIRE_5[2], _list_req_T_22 node list_req_hi_5 = cat(_list_req_WIRE_5[2], _list_req_WIRE_5[1]) node _list_req_T_23 = cat(list_req_hi_5, _list_req_WIRE_5[0]) node list_req_5 = and(_list_req_T_23, br_slots) node new_list_5 = orr(list_req_5) when new_list_5 : node _br_alloc_lists_5_T = bits(list_req_5, 0, 0) node _br_alloc_lists_5_T_1 = bits(list_req_5, 1, 1) node _br_alloc_lists_5_T_2 = bits(list_req_5, 2, 2) node _br_alloc_lists_5_T_3 = mux(_br_alloc_lists_5_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_5_T_4 = mux(_br_alloc_lists_5_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_5_T_5 = mux(_br_alloc_lists_5_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_5_T_6 = or(_br_alloc_lists_5_T_3, _br_alloc_lists_5_T_4) node _br_alloc_lists_5_T_7 = or(_br_alloc_lists_5_T_6, _br_alloc_lists_5_T_5) wire _br_alloc_lists_5_WIRE : UInt<80> connect _br_alloc_lists_5_WIRE, _br_alloc_lists_5_T_7 connect br_alloc_lists[5], _br_alloc_lists_5_WIRE node _list_req_T_24 = eq(io.ren_br_tags[0].bits, UInt<3>(0h6)) node _list_req_T_25 = eq(io.ren_br_tags[1].bits, UInt<3>(0h6)) node _list_req_T_26 = eq(io.ren_br_tags[2].bits, UInt<3>(0h6)) wire _list_req_WIRE_6 : UInt<1>[3] connect _list_req_WIRE_6[0], _list_req_T_24 connect _list_req_WIRE_6[1], _list_req_T_25 connect _list_req_WIRE_6[2], _list_req_T_26 node list_req_hi_6 = cat(_list_req_WIRE_6[2], _list_req_WIRE_6[1]) node _list_req_T_27 = cat(list_req_hi_6, _list_req_WIRE_6[0]) node list_req_6 = and(_list_req_T_27, br_slots) node new_list_6 = orr(list_req_6) when new_list_6 : node _br_alloc_lists_6_T = bits(list_req_6, 0, 0) node _br_alloc_lists_6_T_1 = bits(list_req_6, 1, 1) node _br_alloc_lists_6_T_2 = bits(list_req_6, 2, 2) node _br_alloc_lists_6_T_3 = mux(_br_alloc_lists_6_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_6_T_4 = mux(_br_alloc_lists_6_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_6_T_5 = mux(_br_alloc_lists_6_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_6_T_6 = or(_br_alloc_lists_6_T_3, _br_alloc_lists_6_T_4) node _br_alloc_lists_6_T_7 = or(_br_alloc_lists_6_T_6, _br_alloc_lists_6_T_5) wire _br_alloc_lists_6_WIRE : UInt<80> connect _br_alloc_lists_6_WIRE, _br_alloc_lists_6_T_7 connect br_alloc_lists[6], _br_alloc_lists_6_WIRE node _list_req_T_28 = eq(io.ren_br_tags[0].bits, UInt<3>(0h7)) node _list_req_T_29 = eq(io.ren_br_tags[1].bits, UInt<3>(0h7)) node _list_req_T_30 = eq(io.ren_br_tags[2].bits, UInt<3>(0h7)) wire _list_req_WIRE_7 : UInt<1>[3] connect _list_req_WIRE_7[0], _list_req_T_28 connect _list_req_WIRE_7[1], _list_req_T_29 connect _list_req_WIRE_7[2], _list_req_T_30 node list_req_hi_7 = cat(_list_req_WIRE_7[2], _list_req_WIRE_7[1]) node _list_req_T_31 = cat(list_req_hi_7, _list_req_WIRE_7[0]) node list_req_7 = and(_list_req_T_31, br_slots) node new_list_7 = orr(list_req_7) when new_list_7 : node _br_alloc_lists_7_T = bits(list_req_7, 0, 0) node _br_alloc_lists_7_T_1 = bits(list_req_7, 1, 1) node _br_alloc_lists_7_T_2 = bits(list_req_7, 2, 2) node _br_alloc_lists_7_T_3 = mux(_br_alloc_lists_7_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_7_T_4 = mux(_br_alloc_lists_7_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_7_T_5 = mux(_br_alloc_lists_7_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_7_T_6 = or(_br_alloc_lists_7_T_3, _br_alloc_lists_7_T_4) node _br_alloc_lists_7_T_7 = or(_br_alloc_lists_7_T_6, _br_alloc_lists_7_T_5) wire _br_alloc_lists_7_WIRE : UInt<80> connect _br_alloc_lists_7_WIRE, _br_alloc_lists_7_T_7 connect br_alloc_lists[7], _br_alloc_lists_7_WIRE node _list_req_T_32 = eq(io.ren_br_tags[0].bits, UInt<4>(0h8)) node _list_req_T_33 = eq(io.ren_br_tags[1].bits, UInt<4>(0h8)) node _list_req_T_34 = eq(io.ren_br_tags[2].bits, UInt<4>(0h8)) wire _list_req_WIRE_8 : UInt<1>[3] connect _list_req_WIRE_8[0], _list_req_T_32 connect _list_req_WIRE_8[1], _list_req_T_33 connect _list_req_WIRE_8[2], _list_req_T_34 node list_req_hi_8 = cat(_list_req_WIRE_8[2], _list_req_WIRE_8[1]) node _list_req_T_35 = cat(list_req_hi_8, _list_req_WIRE_8[0]) node list_req_8 = and(_list_req_T_35, br_slots) node new_list_8 = orr(list_req_8) when new_list_8 : node _br_alloc_lists_8_T = bits(list_req_8, 0, 0) node _br_alloc_lists_8_T_1 = bits(list_req_8, 1, 1) node _br_alloc_lists_8_T_2 = bits(list_req_8, 2, 2) node _br_alloc_lists_8_T_3 = mux(_br_alloc_lists_8_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_8_T_4 = mux(_br_alloc_lists_8_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_8_T_5 = mux(_br_alloc_lists_8_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_8_T_6 = or(_br_alloc_lists_8_T_3, _br_alloc_lists_8_T_4) node _br_alloc_lists_8_T_7 = or(_br_alloc_lists_8_T_6, _br_alloc_lists_8_T_5) wire _br_alloc_lists_8_WIRE : UInt<80> connect _br_alloc_lists_8_WIRE, _br_alloc_lists_8_T_7 connect br_alloc_lists[8], _br_alloc_lists_8_WIRE node _list_req_T_36 = eq(io.ren_br_tags[0].bits, UInt<4>(0h9)) node _list_req_T_37 = eq(io.ren_br_tags[1].bits, UInt<4>(0h9)) node _list_req_T_38 = eq(io.ren_br_tags[2].bits, UInt<4>(0h9)) wire _list_req_WIRE_9 : UInt<1>[3] connect _list_req_WIRE_9[0], _list_req_T_36 connect _list_req_WIRE_9[1], _list_req_T_37 connect _list_req_WIRE_9[2], _list_req_T_38 node list_req_hi_9 = cat(_list_req_WIRE_9[2], _list_req_WIRE_9[1]) node _list_req_T_39 = cat(list_req_hi_9, _list_req_WIRE_9[0]) node list_req_9 = and(_list_req_T_39, br_slots) node new_list_9 = orr(list_req_9) when new_list_9 : node _br_alloc_lists_9_T = bits(list_req_9, 0, 0) node _br_alloc_lists_9_T_1 = bits(list_req_9, 1, 1) node _br_alloc_lists_9_T_2 = bits(list_req_9, 2, 2) node _br_alloc_lists_9_T_3 = mux(_br_alloc_lists_9_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_9_T_4 = mux(_br_alloc_lists_9_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_9_T_5 = mux(_br_alloc_lists_9_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_9_T_6 = or(_br_alloc_lists_9_T_3, _br_alloc_lists_9_T_4) node _br_alloc_lists_9_T_7 = or(_br_alloc_lists_9_T_6, _br_alloc_lists_9_T_5) wire _br_alloc_lists_9_WIRE : UInt<80> connect _br_alloc_lists_9_WIRE, _br_alloc_lists_9_T_7 connect br_alloc_lists[9], _br_alloc_lists_9_WIRE node _list_req_T_40 = eq(io.ren_br_tags[0].bits, UInt<4>(0ha)) node _list_req_T_41 = eq(io.ren_br_tags[1].bits, UInt<4>(0ha)) node _list_req_T_42 = eq(io.ren_br_tags[2].bits, UInt<4>(0ha)) wire _list_req_WIRE_10 : UInt<1>[3] connect _list_req_WIRE_10[0], _list_req_T_40 connect _list_req_WIRE_10[1], _list_req_T_41 connect _list_req_WIRE_10[2], _list_req_T_42 node list_req_hi_10 = cat(_list_req_WIRE_10[2], _list_req_WIRE_10[1]) node _list_req_T_43 = cat(list_req_hi_10, _list_req_WIRE_10[0]) node list_req_10 = and(_list_req_T_43, br_slots) node new_list_10 = orr(list_req_10) when new_list_10 : node _br_alloc_lists_10_T = bits(list_req_10, 0, 0) node _br_alloc_lists_10_T_1 = bits(list_req_10, 1, 1) node _br_alloc_lists_10_T_2 = bits(list_req_10, 2, 2) node _br_alloc_lists_10_T_3 = mux(_br_alloc_lists_10_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_10_T_4 = mux(_br_alloc_lists_10_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_10_T_5 = mux(_br_alloc_lists_10_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_10_T_6 = or(_br_alloc_lists_10_T_3, _br_alloc_lists_10_T_4) node _br_alloc_lists_10_T_7 = or(_br_alloc_lists_10_T_6, _br_alloc_lists_10_T_5) wire _br_alloc_lists_10_WIRE : UInt<80> connect _br_alloc_lists_10_WIRE, _br_alloc_lists_10_T_7 connect br_alloc_lists[10], _br_alloc_lists_10_WIRE node _list_req_T_44 = eq(io.ren_br_tags[0].bits, UInt<4>(0hb)) node _list_req_T_45 = eq(io.ren_br_tags[1].bits, UInt<4>(0hb)) node _list_req_T_46 = eq(io.ren_br_tags[2].bits, UInt<4>(0hb)) wire _list_req_WIRE_11 : UInt<1>[3] connect _list_req_WIRE_11[0], _list_req_T_44 connect _list_req_WIRE_11[1], _list_req_T_45 connect _list_req_WIRE_11[2], _list_req_T_46 node list_req_hi_11 = cat(_list_req_WIRE_11[2], _list_req_WIRE_11[1]) node _list_req_T_47 = cat(list_req_hi_11, _list_req_WIRE_11[0]) node list_req_11 = and(_list_req_T_47, br_slots) node new_list_11 = orr(list_req_11) when new_list_11 : node _br_alloc_lists_11_T = bits(list_req_11, 0, 0) node _br_alloc_lists_11_T_1 = bits(list_req_11, 1, 1) node _br_alloc_lists_11_T_2 = bits(list_req_11, 2, 2) node _br_alloc_lists_11_T_3 = mux(_br_alloc_lists_11_T, alloc_masks_0, UInt<1>(0h0)) node _br_alloc_lists_11_T_4 = mux(_br_alloc_lists_11_T_1, alloc_masks_1, UInt<1>(0h0)) node _br_alloc_lists_11_T_5 = mux(_br_alloc_lists_11_T_2, UInt<80>(0h0), UInt<1>(0h0)) node _br_alloc_lists_11_T_6 = or(_br_alloc_lists_11_T_3, _br_alloc_lists_11_T_4) node _br_alloc_lists_11_T_7 = or(_br_alloc_lists_11_T_6, _br_alloc_lists_11_T_5) wire _br_alloc_lists_11_WIRE : UInt<80> connect _br_alloc_lists_11_WIRE, _br_alloc_lists_11_T_7 connect br_alloc_lists[11], _br_alloc_lists_11_WIRE node _spec_alloc_list_T = or(spec_alloc_list, alloc_masks_0) node _spec_alloc_list_T_1 = not(dealloc_mask) node _spec_alloc_list_T_2 = and(_spec_alloc_list_T, _spec_alloc_list_T_1) node _spec_alloc_list_T_3 = not(com_despec) node _spec_alloc_list_T_4 = and(_spec_alloc_list_T_2, _spec_alloc_list_T_3) connect spec_alloc_list, _spec_alloc_list_T_4 node _free_list_T = not(sel_mask) node _free_list_T_1 = and(free_list, _free_list_T) node _free_list_T_2 = or(_free_list_T_1, dealloc_mask) connect free_list, _free_list_T_2 node can_sel = orr(sels[0]) regreset r_valid : UInt<1>, clock, reset, UInt<1>(0h0) node r_sel_hi = bits(sels[0], 79, 64) node r_sel_lo = bits(sels[0], 63, 0) node _r_sel_T = orr(r_sel_hi) node _r_sel_T_1 = or(r_sel_hi, r_sel_lo) node r_sel_hi_1 = bits(_r_sel_T_1, 63, 32) node r_sel_lo_1 = bits(_r_sel_T_1, 31, 0) node _r_sel_T_2 = orr(r_sel_hi_1) node _r_sel_T_3 = or(r_sel_hi_1, r_sel_lo_1) node r_sel_hi_2 = bits(_r_sel_T_3, 31, 16) node r_sel_lo_2 = bits(_r_sel_T_3, 15, 0) node _r_sel_T_4 = orr(r_sel_hi_2) node _r_sel_T_5 = or(r_sel_hi_2, r_sel_lo_2) node r_sel_hi_3 = bits(_r_sel_T_5, 15, 8) node r_sel_lo_3 = bits(_r_sel_T_5, 7, 0) node _r_sel_T_6 = orr(r_sel_hi_3) node _r_sel_T_7 = or(r_sel_hi_3, r_sel_lo_3) node r_sel_hi_4 = bits(_r_sel_T_7, 7, 4) node r_sel_lo_4 = bits(_r_sel_T_7, 3, 0) node _r_sel_T_8 = orr(r_sel_hi_4) node _r_sel_T_9 = or(r_sel_hi_4, r_sel_lo_4) node r_sel_hi_5 = bits(_r_sel_T_9, 3, 2) node r_sel_lo_5 = bits(_r_sel_T_9, 1, 0) node _r_sel_T_10 = orr(r_sel_hi_5) node _r_sel_T_11 = or(r_sel_hi_5, r_sel_lo_5) node _r_sel_T_12 = bits(_r_sel_T_11, 1, 1) node _r_sel_T_13 = cat(_r_sel_T_10, _r_sel_T_12) node _r_sel_T_14 = cat(_r_sel_T_8, _r_sel_T_13) node _r_sel_T_15 = cat(_r_sel_T_6, _r_sel_T_14) node _r_sel_T_16 = cat(_r_sel_T_4, _r_sel_T_15) node _r_sel_T_17 = cat(_r_sel_T_2, _r_sel_T_16) node _r_sel_T_18 = cat(_r_sel_T, _r_sel_T_17) reg r_sel : UInt<7>, clock when sel_fire[0] : connect r_sel, _r_sel_T_18 node _r_valid_T = eq(io.reqs[0], UInt<1>(0h0)) node _r_valid_T_1 = and(r_valid, _r_valid_T) node _r_valid_T_2 = or(_r_valid_T_1, can_sel) connect r_valid, _r_valid_T_2 node _sel_fire_0_T = eq(r_valid, UInt<1>(0h0)) node _sel_fire_0_T_1 = or(_sel_fire_0_T, io.reqs[0]) node _sel_fire_0_T_2 = and(_sel_fire_0_T_1, can_sel) connect sel_fire[0], _sel_fire_0_T_2 connect io.alloc_pregs[0].bits, r_sel connect io.alloc_pregs[0].valid, r_valid node can_sel_1 = orr(sels[1]) regreset r_valid_1 : UInt<1>, clock, reset, UInt<1>(0h0) node r_sel_hi_6 = bits(sels[1], 79, 64) node r_sel_lo_6 = bits(sels[1], 63, 0) node _r_sel_T_19 = orr(r_sel_hi_6) node _r_sel_T_20 = or(r_sel_hi_6, r_sel_lo_6) node r_sel_hi_7 = bits(_r_sel_T_20, 63, 32) node r_sel_lo_7 = bits(_r_sel_T_20, 31, 0) node _r_sel_T_21 = orr(r_sel_hi_7) node _r_sel_T_22 = or(r_sel_hi_7, r_sel_lo_7) node r_sel_hi_8 = bits(_r_sel_T_22, 31, 16) node r_sel_lo_8 = bits(_r_sel_T_22, 15, 0) node _r_sel_T_23 = orr(r_sel_hi_8) node _r_sel_T_24 = or(r_sel_hi_8, r_sel_lo_8) node r_sel_hi_9 = bits(_r_sel_T_24, 15, 8) node r_sel_lo_9 = bits(_r_sel_T_24, 7, 0) node _r_sel_T_25 = orr(r_sel_hi_9) node _r_sel_T_26 = or(r_sel_hi_9, r_sel_lo_9) node r_sel_hi_10 = bits(_r_sel_T_26, 7, 4) node r_sel_lo_10 = bits(_r_sel_T_26, 3, 0) node _r_sel_T_27 = orr(r_sel_hi_10) node _r_sel_T_28 = or(r_sel_hi_10, r_sel_lo_10) node r_sel_hi_11 = bits(_r_sel_T_28, 3, 2) node r_sel_lo_11 = bits(_r_sel_T_28, 1, 0) node _r_sel_T_29 = orr(r_sel_hi_11) node _r_sel_T_30 = or(r_sel_hi_11, r_sel_lo_11) node _r_sel_T_31 = bits(_r_sel_T_30, 1, 1) node _r_sel_T_32 = cat(_r_sel_T_29, _r_sel_T_31) node _r_sel_T_33 = cat(_r_sel_T_27, _r_sel_T_32) node _r_sel_T_34 = cat(_r_sel_T_25, _r_sel_T_33) node _r_sel_T_35 = cat(_r_sel_T_23, _r_sel_T_34) node _r_sel_T_36 = cat(_r_sel_T_21, _r_sel_T_35) node _r_sel_T_37 = cat(_r_sel_T_19, _r_sel_T_36) reg r_sel_1 : UInt<7>, clock when sel_fire[1] : connect r_sel_1, _r_sel_T_37 node _r_valid_T_3 = eq(io.reqs[1], UInt<1>(0h0)) node _r_valid_T_4 = and(r_valid_1, _r_valid_T_3) node _r_valid_T_5 = or(_r_valid_T_4, can_sel_1) connect r_valid_1, _r_valid_T_5 node _sel_fire_1_T = eq(r_valid_1, UInt<1>(0h0)) node _sel_fire_1_T_1 = or(_sel_fire_1_T, io.reqs[1]) node _sel_fire_1_T_2 = and(_sel_fire_1_T_1, can_sel_1) connect sel_fire[1], _sel_fire_1_T_2 connect io.alloc_pregs[1].bits, r_sel_1 connect io.alloc_pregs[1].valid, r_valid_1 node _io_debug_freelist_T = dshl(UInt<1>(0h1), io.alloc_pregs[0].bits) node _io_debug_freelist_T_1 = bits(_io_debug_freelist_T, 79, 0) node _io_debug_freelist_T_2 = mux(io.alloc_pregs[0].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _io_debug_freelist_T_3 = and(_io_debug_freelist_T_1, _io_debug_freelist_T_2) node _io_debug_freelist_T_4 = dshl(UInt<1>(0h1), io.alloc_pregs[1].bits) node _io_debug_freelist_T_5 = bits(_io_debug_freelist_T_4, 79, 0) node _io_debug_freelist_T_6 = mux(io.alloc_pregs[1].valid, UInt<80>(0hffffffffffffffffffff), UInt<80>(0h0)) node _io_debug_freelist_T_7 = and(_io_debug_freelist_T_5, _io_debug_freelist_T_6) node _io_debug_freelist_T_8 = or(_io_debug_freelist_T_3, _io_debug_freelist_T_7) node _io_debug_freelist_T_9 = or(free_list, _io_debug_freelist_T_8) connect io.debug_freelist, _io_debug_freelist_T_9 node _T = and(io.debug_freelist, dealloc_mask) node _T_1 = orr(_T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed: [freelist] Returning a free physical register.\n at rename-freelist.scala:137 assert (!(io.debug_freelist & dealloc_mask).orR, \"[freelist] Returning a free physical register.\")\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert

module RenameFreeList( // @[rename-freelist.scala:52:7] input clock, // @[rename-freelist.scala:52:7] input reset, // @[rename-freelist.scala:52:7] input io_reqs_0, // @[rename-freelist.scala:29:14] input io_reqs_1, // @[rename-freelist.scala:29:14] output io_alloc_pregs_0_valid, // @[rename-freelist.scala:29:14] output [6:0] io_alloc_pregs_0_bits, // @[rename-freelist.scala:29:14] output io_alloc_pregs_1_valid, // @[rename-freelist.scala:29:14] output [6:0] io_alloc_pregs_1_bits, // @[rename-freelist.scala:29:14] input io_despec_0_valid, // @[rename-freelist.scala:29:14] input [6:0] io_despec_0_bits, // @[rename-freelist.scala:29:14] input io_despec_1_valid, // @[rename-freelist.scala:29:14] input [6:0] io_despec_1_bits, // @[rename-freelist.scala:29:14] input io_dealloc_0_valid, // @[rename-freelist.scala:29:14] input [6:0] io_dealloc_0_bits, // @[rename-freelist.scala:29:14] input io_dealloc_1_valid, // @[rename-freelist.scala:29:14] input [6:0] io_dealloc_1_bits, // @[rename-freelist.scala:29:14] input io_ren_br_tags_1_valid, // @[rename-freelist.scala:29:14] input [3:0] io_ren_br_tags_1_bits, // @[rename-freelist.scala:29:14] input io_ren_br_tags_2_valid, // @[rename-freelist.scala:29:14] input [3:0] io_ren_br_tags_2_bits, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b1_resolve_mask, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[rename-freelist.scala:29:14] input [31:0] io_brupdate_b2_uop_inst, // @[rename-freelist.scala:29:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_rvc, // @[rename-freelist.scala:29:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_0, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iq_type_3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_0, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_4, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_5, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_6, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_7, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_8, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fu_code_9, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[rename-freelist.scala:29:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_br_type, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sfb, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_fence, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_fencei, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sfence, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_amo, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_eret, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_rocc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_mov, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_edge_inst, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_taken, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_imm_rename, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_pimm, // @[rename-freelist.scala:29:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[rename-freelist.scala:29:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_pdst, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs1, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs2, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_prs3, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_ppred, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs1_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs2_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_prs3_busy, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_ppred_busy, // @[rename-freelist.scala:29:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_exception, // @[rename-freelist.scala:29:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_mem_signed, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_uses_ldq, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_uses_stq, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_is_unique, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_flush_on_commit, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_ldst, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[rename-freelist.scala:29:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_frs3_en, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fcn_dw, // @[rename-freelist.scala:29:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_fp_val, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_bp_debug_if, // @[rename-freelist.scala:29:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[rename-freelist.scala:29:14] input io_brupdate_b2_mispredict, // @[rename-freelist.scala:29:14] input io_brupdate_b2_taken, // @[rename-freelist.scala:29:14] input [2:0] io_brupdate_b2_cfi_type, // @[rename-freelist.scala:29:14] input [1:0] io_brupdate_b2_pc_sel, // @[rename-freelist.scala:29:14] input [39:0] io_brupdate_b2_jalr_target, // @[rename-freelist.scala:29:14] input [20:0] io_brupdate_b2_target_offset, // @[rename-freelist.scala:29:14] input io_rollback, // @[rename-freelist.scala:29:14] output [79:0] io_debug_freelist // @[rename-freelist.scala:29:14] ); wire io_reqs_0_0 = io_reqs_0; // @[rename-freelist.scala:52:7] wire io_reqs_1_0 = io_reqs_1; // @[rename-freelist.scala:52:7] wire io_despec_0_valid_0 = io_despec_0_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_despec_0_bits_0 = io_despec_0_bits; // @[rename-freelist.scala:52:7] wire io_despec_1_valid_0 = io_despec_1_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_despec_1_bits_0 = io_despec_1_bits; // @[rename-freelist.scala:52:7] wire io_dealloc_0_valid_0 = io_dealloc_0_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_dealloc_0_bits_0 = io_dealloc_0_bits; // @[rename-freelist.scala:52:7] wire io_dealloc_1_valid_0 = io_dealloc_1_valid; // @[rename-freelist.scala:52:7] wire [6:0] io_dealloc_1_bits_0 = io_dealloc_1_bits; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_1_valid_0 = io_ren_br_tags_1_valid; // @[rename-freelist.scala:52:7] wire [3:0] io_ren_br_tags_1_bits_0 = io_ren_br_tags_1_bits; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_2_valid_0 = io_ren_br_tags_2_valid; // @[rename-freelist.scala:52:7] wire [3:0] io_ren_br_tags_2_bits_0 = io_ren_br_tags_2_bits; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rename-freelist.scala:52:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rename-freelist.scala:52:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rename-freelist.scala:52:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[rename-freelist.scala:52:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[rename-freelist.scala:52:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rename-freelist.scala:52:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rename-freelist.scala:52:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rename-freelist.scala:52:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rename-freelist.scala:52:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[rename-freelist.scala:52:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rename-freelist.scala:52:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rename-freelist.scala:52:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rename-freelist.scala:52:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rename-freelist.scala:52:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rename-freelist.scala:52:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rename-freelist.scala:52:7] wire io_rollback_0 = io_rollback; // @[rename-freelist.scala:52:7] wire [79:0] io_initial_allocation = 80'hFFFFFFFFFFFF00000000; // @[rename-freelist.scala:52:7] wire io_ren_br_tags_0_valid = 1'h0; // @[rename-freelist.scala:52:7] wire _br_slots_WIRE_0 = 1'h0; // @[rename-freelist.scala:96:27] wire _list_req_T_4 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_1_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_8 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_2_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_12 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_3_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_16 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_4_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_20 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_5_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_24 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_6_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_28 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_7_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_32 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_8_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_36 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_9_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_40 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_10_0 = 1'h0; // @[rename-freelist.scala:99:29] wire _list_req_T_44 = 1'h0; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_11_0 = 1'h0; // @[rename-freelist.scala:99:29] wire [3:0] io_ren_br_tags_0_bits = 4'h0; // @[rename-freelist.scala:52:7] wire [79:0] _br_alloc_lists_0_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_T_5 = 80'h0; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_T_5 = 80'h0; // @[Mux.scala:30:73] wire _list_req_T = 1'h1; // @[rename-freelist.scala:99:65] wire _list_req_WIRE_0 = 1'h1; // @[rename-freelist.scala:99:29] wire _br_slots_WIRE_1 = io_ren_br_tags_1_valid_0; // @[rename-freelist.scala:52:7, :96:27] wire _br_slots_WIRE_2 = io_ren_br_tags_2_valid_0; // @[rename-freelist.scala:52:7, :96:27] wire [79:0] _io_debug_freelist_T_9; // @[rename-freelist.scala:134:34] wire io_alloc_pregs_0_valid_0; // @[rename-freelist.scala:52:7] wire [6:0] io_alloc_pregs_0_bits_0; // @[rename-freelist.scala:52:7] wire io_alloc_pregs_1_valid_0; // @[rename-freelist.scala:52:7] wire [6:0] io_alloc_pregs_1_bits_0; // @[rename-freelist.scala:52:7] wire [79:0] io_debug_freelist_0; // @[rename-freelist.scala:52:7] reg [79:0] free_list; // @[rename-freelist.scala:62:26] reg [79:0] spec_alloc_list; // @[rename-freelist.scala:63:32] reg [79:0] br_alloc_lists_0; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_1; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_2; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_3; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_4; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_5; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_6; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_7; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_8; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_9; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_10; // @[rename-freelist.scala:64:27] reg [79:0] br_alloc_lists_11; // @[rename-freelist.scala:64:27] wire [79:0] _sels_sels_0_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_sels_1_T_159; // @[Mux.scala:50:70] wire [79:0] sels_0; // @[util.scala:415:20] wire [79:0] sels_1; // @[util.scala:415:20] wire _sels_sels_0_T = free_list[0]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_1 = free_list[1]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_2 = free_list[2]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_3 = free_list[3]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_4 = free_list[4]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_5 = free_list[5]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_6 = free_list[6]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_7 = free_list[7]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_8 = free_list[8]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_9 = free_list[9]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_10 = free_list[10]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_11 = free_list[11]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_12 = free_list[12]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_13 = free_list[13]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_14 = free_list[14]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_15 = free_list[15]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_16 = free_list[16]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_17 = free_list[17]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_18 = free_list[18]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_19 = free_list[19]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_20 = free_list[20]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_21 = free_list[21]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_22 = free_list[22]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_23 = free_list[23]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_24 = free_list[24]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_25 = free_list[25]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_26 = free_list[26]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_27 = free_list[27]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_28 = free_list[28]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_29 = free_list[29]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_30 = free_list[30]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_31 = free_list[31]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_32 = free_list[32]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_33 = free_list[33]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_34 = free_list[34]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_35 = free_list[35]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_36 = free_list[36]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_37 = free_list[37]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_38 = free_list[38]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_39 = free_list[39]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_40 = free_list[40]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_41 = free_list[41]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_42 = free_list[42]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_43 = free_list[43]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_44 = free_list[44]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_45 = free_list[45]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_46 = free_list[46]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_47 = free_list[47]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_48 = free_list[48]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_49 = free_list[49]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_50 = free_list[50]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_51 = free_list[51]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_52 = free_list[52]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_53 = free_list[53]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_54 = free_list[54]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_55 = free_list[55]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_56 = free_list[56]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_57 = free_list[57]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_58 = free_list[58]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_59 = free_list[59]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_60 = free_list[60]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_61 = free_list[61]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_62 = free_list[62]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_63 = free_list[63]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_64 = free_list[64]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_65 = free_list[65]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_66 = free_list[66]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_67 = free_list[67]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_68 = free_list[68]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_69 = free_list[69]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_70 = free_list[70]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_71 = free_list[71]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_72 = free_list[72]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_73 = free_list[73]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_74 = free_list[74]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_75 = free_list[75]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_76 = free_list[76]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_77 = free_list[77]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_78 = free_list[78]; // @[OneHot.scala:85:71] wire _sels_sels_0_T_79 = free_list[79]; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_80 = {_sels_sels_0_T_79, 79'h0}; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_81 = _sels_sels_0_T_78 ? 80'h40000000000000000000 : _sels_sels_0_T_80; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_82 = _sels_sels_0_T_77 ? 80'h20000000000000000000 : _sels_sels_0_T_81; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_83 = _sels_sels_0_T_76 ? 80'h10000000000000000000 : _sels_sels_0_T_82; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_84 = _sels_sels_0_T_75 ? 80'h8000000000000000000 : _sels_sels_0_T_83; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_85 = _sels_sels_0_T_74 ? 80'h4000000000000000000 : _sels_sels_0_T_84; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_86 = _sels_sels_0_T_73 ? 80'h2000000000000000000 : _sels_sels_0_T_85; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_87 = _sels_sels_0_T_72 ? 80'h1000000000000000000 : _sels_sels_0_T_86; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_88 = _sels_sels_0_T_71 ? 80'h800000000000000000 : _sels_sels_0_T_87; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_89 = _sels_sels_0_T_70 ? 80'h400000000000000000 : _sels_sels_0_T_88; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_90 = _sels_sels_0_T_69 ? 80'h200000000000000000 : _sels_sels_0_T_89; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_91 = _sels_sels_0_T_68 ? 80'h100000000000000000 : _sels_sels_0_T_90; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_92 = _sels_sels_0_T_67 ? 80'h80000000000000000 : _sels_sels_0_T_91; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_93 = _sels_sels_0_T_66 ? 80'h40000000000000000 : _sels_sels_0_T_92; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_94 = _sels_sels_0_T_65 ? 80'h20000000000000000 : _sels_sels_0_T_93; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_95 = _sels_sels_0_T_64 ? 80'h10000000000000000 : _sels_sels_0_T_94; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_96 = _sels_sels_0_T_63 ? 80'h8000000000000000 : _sels_sels_0_T_95; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_97 = _sels_sels_0_T_62 ? 80'h4000000000000000 : _sels_sels_0_T_96; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_98 = _sels_sels_0_T_61 ? 80'h2000000000000000 : _sels_sels_0_T_97; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_99 = _sels_sels_0_T_60 ? 80'h1000000000000000 : _sels_sels_0_T_98; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_100 = _sels_sels_0_T_59 ? 80'h800000000000000 : _sels_sels_0_T_99; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_101 = _sels_sels_0_T_58 ? 80'h400000000000000 : _sels_sels_0_T_100; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_102 = _sels_sels_0_T_57 ? 80'h200000000000000 : _sels_sels_0_T_101; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_103 = _sels_sels_0_T_56 ? 80'h100000000000000 : _sels_sels_0_T_102; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_104 = _sels_sels_0_T_55 ? 80'h80000000000000 : _sels_sels_0_T_103; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_105 = _sels_sels_0_T_54 ? 80'h40000000000000 : _sels_sels_0_T_104; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_106 = _sels_sels_0_T_53 ? 80'h20000000000000 : _sels_sels_0_T_105; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_107 = _sels_sels_0_T_52 ? 80'h10000000000000 : _sels_sels_0_T_106; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_108 = _sels_sels_0_T_51 ? 80'h8000000000000 : _sels_sels_0_T_107; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_109 = _sels_sels_0_T_50 ? 80'h4000000000000 : _sels_sels_0_T_108; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_110 = _sels_sels_0_T_49 ? 80'h2000000000000 : _sels_sels_0_T_109; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_111 = _sels_sels_0_T_48 ? 80'h1000000000000 : _sels_sels_0_T_110; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_112 = _sels_sels_0_T_47 ? 80'h800000000000 : _sels_sels_0_T_111; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_113 = _sels_sels_0_T_46 ? 80'h400000000000 : _sels_sels_0_T_112; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_114 = _sels_sels_0_T_45 ? 80'h200000000000 : _sels_sels_0_T_113; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_115 = _sels_sels_0_T_44 ? 80'h100000000000 : _sels_sels_0_T_114; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_116 = _sels_sels_0_T_43 ? 80'h80000000000 : _sels_sels_0_T_115; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_117 = _sels_sels_0_T_42 ? 80'h40000000000 : _sels_sels_0_T_116; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_118 = _sels_sels_0_T_41 ? 80'h20000000000 : _sels_sels_0_T_117; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_119 = _sels_sels_0_T_40 ? 80'h10000000000 : _sels_sels_0_T_118; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_120 = _sels_sels_0_T_39 ? 80'h8000000000 : _sels_sels_0_T_119; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_121 = _sels_sels_0_T_38 ? 80'h4000000000 : _sels_sels_0_T_120; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_122 = _sels_sels_0_T_37 ? 80'h2000000000 : _sels_sels_0_T_121; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_123 = _sels_sels_0_T_36 ? 80'h1000000000 : _sels_sels_0_T_122; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_124 = _sels_sels_0_T_35 ? 80'h800000000 : _sels_sels_0_T_123; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_125 = _sels_sels_0_T_34 ? 80'h400000000 : _sels_sels_0_T_124; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_126 = _sels_sels_0_T_33 ? 80'h200000000 : _sels_sels_0_T_125; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_127 = _sels_sels_0_T_32 ? 80'h100000000 : _sels_sels_0_T_126; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_128 = _sels_sels_0_T_31 ? 80'h80000000 : _sels_sels_0_T_127; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_129 = _sels_sels_0_T_30 ? 80'h40000000 : _sels_sels_0_T_128; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_130 = _sels_sels_0_T_29 ? 80'h20000000 : _sels_sels_0_T_129; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_131 = _sels_sels_0_T_28 ? 80'h10000000 : _sels_sels_0_T_130; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_132 = _sels_sels_0_T_27 ? 80'h8000000 : _sels_sels_0_T_131; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_133 = _sels_sels_0_T_26 ? 80'h4000000 : _sels_sels_0_T_132; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_134 = _sels_sels_0_T_25 ? 80'h2000000 : _sels_sels_0_T_133; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_135 = _sels_sels_0_T_24 ? 80'h1000000 : _sels_sels_0_T_134; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_136 = _sels_sels_0_T_23 ? 80'h800000 : _sels_sels_0_T_135; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_137 = _sels_sels_0_T_22 ? 80'h400000 : _sels_sels_0_T_136; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_138 = _sels_sels_0_T_21 ? 80'h200000 : _sels_sels_0_T_137; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_139 = _sels_sels_0_T_20 ? 80'h100000 : _sels_sels_0_T_138; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_140 = _sels_sels_0_T_19 ? 80'h80000 : _sels_sels_0_T_139; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_141 = _sels_sels_0_T_18 ? 80'h40000 : _sels_sels_0_T_140; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_142 = _sels_sels_0_T_17 ? 80'h20000 : _sels_sels_0_T_141; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_143 = _sels_sels_0_T_16 ? 80'h10000 : _sels_sels_0_T_142; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_144 = _sels_sels_0_T_15 ? 80'h8000 : _sels_sels_0_T_143; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_145 = _sels_sels_0_T_14 ? 80'h4000 : _sels_sels_0_T_144; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_146 = _sels_sels_0_T_13 ? 80'h2000 : _sels_sels_0_T_145; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_147 = _sels_sels_0_T_12 ? 80'h1000 : _sels_sels_0_T_146; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_148 = _sels_sels_0_T_11 ? 80'h800 : _sels_sels_0_T_147; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_149 = _sels_sels_0_T_10 ? 80'h400 : _sels_sels_0_T_148; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_150 = _sels_sels_0_T_9 ? 80'h200 : _sels_sels_0_T_149; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_151 = _sels_sels_0_T_8 ? 80'h100 : _sels_sels_0_T_150; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_152 = _sels_sels_0_T_7 ? 80'h80 : _sels_sels_0_T_151; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_153 = _sels_sels_0_T_6 ? 80'h40 : _sels_sels_0_T_152; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_154 = _sels_sels_0_T_5 ? 80'h20 : _sels_sels_0_T_153; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_155 = _sels_sels_0_T_4 ? 80'h10 : _sels_sels_0_T_154; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_156 = _sels_sels_0_T_3 ? 80'h8 : _sels_sels_0_T_155; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_157 = _sels_sels_0_T_2 ? 80'h4 : _sels_sels_0_T_156; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_0_T_158 = _sels_sels_0_T_1 ? 80'h2 : _sels_sels_0_T_157; // @[OneHot.scala:85:71] assign _sels_sels_0_T_159 = _sels_sels_0_T ? 80'h1 : _sels_sels_0_T_158; // @[OneHot.scala:85:71] assign sels_0 = _sels_sels_0_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_T = ~sels_0; // @[util.scala:415:20, :420:21] wire [79:0] _sels_T_1 = free_list & _sels_T; // @[util.scala:420:{19,21}] wire _sels_sels_1_T = _sels_T_1[0]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_1 = _sels_T_1[1]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_2 = _sels_T_1[2]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_3 = _sels_T_1[3]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_4 = _sels_T_1[4]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_5 = _sels_T_1[5]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_6 = _sels_T_1[6]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_7 = _sels_T_1[7]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_8 = _sels_T_1[8]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_9 = _sels_T_1[9]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_10 = _sels_T_1[10]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_11 = _sels_T_1[11]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_12 = _sels_T_1[12]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_13 = _sels_T_1[13]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_14 = _sels_T_1[14]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_15 = _sels_T_1[15]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_16 = _sels_T_1[16]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_17 = _sels_T_1[17]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_18 = _sels_T_1[18]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_19 = _sels_T_1[19]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_20 = _sels_T_1[20]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_21 = _sels_T_1[21]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_22 = _sels_T_1[22]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_23 = _sels_T_1[23]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_24 = _sels_T_1[24]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_25 = _sels_T_1[25]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_26 = _sels_T_1[26]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_27 = _sels_T_1[27]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_28 = _sels_T_1[28]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_29 = _sels_T_1[29]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_30 = _sels_T_1[30]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_31 = _sels_T_1[31]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_32 = _sels_T_1[32]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_33 = _sels_T_1[33]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_34 = _sels_T_1[34]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_35 = _sels_T_1[35]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_36 = _sels_T_1[36]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_37 = _sels_T_1[37]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_38 = _sels_T_1[38]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_39 = _sels_T_1[39]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_40 = _sels_T_1[40]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_41 = _sels_T_1[41]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_42 = _sels_T_1[42]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_43 = _sels_T_1[43]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_44 = _sels_T_1[44]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_45 = _sels_T_1[45]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_46 = _sels_T_1[46]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_47 = _sels_T_1[47]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_48 = _sels_T_1[48]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_49 = _sels_T_1[49]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_50 = _sels_T_1[50]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_51 = _sels_T_1[51]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_52 = _sels_T_1[52]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_53 = _sels_T_1[53]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_54 = _sels_T_1[54]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_55 = _sels_T_1[55]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_56 = _sels_T_1[56]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_57 = _sels_T_1[57]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_58 = _sels_T_1[58]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_59 = _sels_T_1[59]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_60 = _sels_T_1[60]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_61 = _sels_T_1[61]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_62 = _sels_T_1[62]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_63 = _sels_T_1[63]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_64 = _sels_T_1[64]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_65 = _sels_T_1[65]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_66 = _sels_T_1[66]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_67 = _sels_T_1[67]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_68 = _sels_T_1[68]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_69 = _sels_T_1[69]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_70 = _sels_T_1[70]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_71 = _sels_T_1[71]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_72 = _sels_T_1[72]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_73 = _sels_T_1[73]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_74 = _sels_T_1[74]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_75 = _sels_T_1[75]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_76 = _sels_T_1[76]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_77 = _sels_T_1[77]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_78 = _sels_T_1[78]; // @[OneHot.scala:85:71] wire _sels_sels_1_T_79 = _sels_T_1[79]; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_80 = {_sels_sels_1_T_79, 79'h0}; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_81 = _sels_sels_1_T_78 ? 80'h40000000000000000000 : _sels_sels_1_T_80; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_82 = _sels_sels_1_T_77 ? 80'h20000000000000000000 : _sels_sels_1_T_81; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_83 = _sels_sels_1_T_76 ? 80'h10000000000000000000 : _sels_sels_1_T_82; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_84 = _sels_sels_1_T_75 ? 80'h8000000000000000000 : _sels_sels_1_T_83; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_85 = _sels_sels_1_T_74 ? 80'h4000000000000000000 : _sels_sels_1_T_84; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_86 = _sels_sels_1_T_73 ? 80'h2000000000000000000 : _sels_sels_1_T_85; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_87 = _sels_sels_1_T_72 ? 80'h1000000000000000000 : _sels_sels_1_T_86; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_88 = _sels_sels_1_T_71 ? 80'h800000000000000000 : _sels_sels_1_T_87; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_89 = _sels_sels_1_T_70 ? 80'h400000000000000000 : _sels_sels_1_T_88; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_90 = _sels_sels_1_T_69 ? 80'h200000000000000000 : _sels_sels_1_T_89; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_91 = _sels_sels_1_T_68 ? 80'h100000000000000000 : _sels_sels_1_T_90; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_92 = _sels_sels_1_T_67 ? 80'h80000000000000000 : _sels_sels_1_T_91; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_93 = _sels_sels_1_T_66 ? 80'h40000000000000000 : _sels_sels_1_T_92; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_94 = _sels_sels_1_T_65 ? 80'h20000000000000000 : _sels_sels_1_T_93; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_95 = _sels_sels_1_T_64 ? 80'h10000000000000000 : _sels_sels_1_T_94; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_96 = _sels_sels_1_T_63 ? 80'h8000000000000000 : _sels_sels_1_T_95; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_97 = _sels_sels_1_T_62 ? 80'h4000000000000000 : _sels_sels_1_T_96; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_98 = _sels_sels_1_T_61 ? 80'h2000000000000000 : _sels_sels_1_T_97; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_99 = _sels_sels_1_T_60 ? 80'h1000000000000000 : _sels_sels_1_T_98; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_100 = _sels_sels_1_T_59 ? 80'h800000000000000 : _sels_sels_1_T_99; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_101 = _sels_sels_1_T_58 ? 80'h400000000000000 : _sels_sels_1_T_100; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_102 = _sels_sels_1_T_57 ? 80'h200000000000000 : _sels_sels_1_T_101; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_103 = _sels_sels_1_T_56 ? 80'h100000000000000 : _sels_sels_1_T_102; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_104 = _sels_sels_1_T_55 ? 80'h80000000000000 : _sels_sels_1_T_103; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_105 = _sels_sels_1_T_54 ? 80'h40000000000000 : _sels_sels_1_T_104; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_106 = _sels_sels_1_T_53 ? 80'h20000000000000 : _sels_sels_1_T_105; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_107 = _sels_sels_1_T_52 ? 80'h10000000000000 : _sels_sels_1_T_106; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_108 = _sels_sels_1_T_51 ? 80'h8000000000000 : _sels_sels_1_T_107; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_109 = _sels_sels_1_T_50 ? 80'h4000000000000 : _sels_sels_1_T_108; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_110 = _sels_sels_1_T_49 ? 80'h2000000000000 : _sels_sels_1_T_109; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_111 = _sels_sels_1_T_48 ? 80'h1000000000000 : _sels_sels_1_T_110; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_112 = _sels_sels_1_T_47 ? 80'h800000000000 : _sels_sels_1_T_111; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_113 = _sels_sels_1_T_46 ? 80'h400000000000 : _sels_sels_1_T_112; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_114 = _sels_sels_1_T_45 ? 80'h200000000000 : _sels_sels_1_T_113; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_115 = _sels_sels_1_T_44 ? 80'h100000000000 : _sels_sels_1_T_114; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_116 = _sels_sels_1_T_43 ? 80'h80000000000 : _sels_sels_1_T_115; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_117 = _sels_sels_1_T_42 ? 80'h40000000000 : _sels_sels_1_T_116; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_118 = _sels_sels_1_T_41 ? 80'h20000000000 : _sels_sels_1_T_117; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_119 = _sels_sels_1_T_40 ? 80'h10000000000 : _sels_sels_1_T_118; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_120 = _sels_sels_1_T_39 ? 80'h8000000000 : _sels_sels_1_T_119; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_121 = _sels_sels_1_T_38 ? 80'h4000000000 : _sels_sels_1_T_120; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_122 = _sels_sels_1_T_37 ? 80'h2000000000 : _sels_sels_1_T_121; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_123 = _sels_sels_1_T_36 ? 80'h1000000000 : _sels_sels_1_T_122; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_124 = _sels_sels_1_T_35 ? 80'h800000000 : _sels_sels_1_T_123; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_125 = _sels_sels_1_T_34 ? 80'h400000000 : _sels_sels_1_T_124; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_126 = _sels_sels_1_T_33 ? 80'h200000000 : _sels_sels_1_T_125; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_127 = _sels_sels_1_T_32 ? 80'h100000000 : _sels_sels_1_T_126; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_128 = _sels_sels_1_T_31 ? 80'h80000000 : _sels_sels_1_T_127; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_129 = _sels_sels_1_T_30 ? 80'h40000000 : _sels_sels_1_T_128; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_130 = _sels_sels_1_T_29 ? 80'h20000000 : _sels_sels_1_T_129; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_131 = _sels_sels_1_T_28 ? 80'h10000000 : _sels_sels_1_T_130; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_132 = _sels_sels_1_T_27 ? 80'h8000000 : _sels_sels_1_T_131; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_133 = _sels_sels_1_T_26 ? 80'h4000000 : _sels_sels_1_T_132; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_134 = _sels_sels_1_T_25 ? 80'h2000000 : _sels_sels_1_T_133; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_135 = _sels_sels_1_T_24 ? 80'h1000000 : _sels_sels_1_T_134; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_136 = _sels_sels_1_T_23 ? 80'h800000 : _sels_sels_1_T_135; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_137 = _sels_sels_1_T_22 ? 80'h400000 : _sels_sels_1_T_136; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_138 = _sels_sels_1_T_21 ? 80'h200000 : _sels_sels_1_T_137; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_139 = _sels_sels_1_T_20 ? 80'h100000 : _sels_sels_1_T_138; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_140 = _sels_sels_1_T_19 ? 80'h80000 : _sels_sels_1_T_139; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_141 = _sels_sels_1_T_18 ? 80'h40000 : _sels_sels_1_T_140; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_142 = _sels_sels_1_T_17 ? 80'h20000 : _sels_sels_1_T_141; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_143 = _sels_sels_1_T_16 ? 80'h10000 : _sels_sels_1_T_142; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_144 = _sels_sels_1_T_15 ? 80'h8000 : _sels_sels_1_T_143; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_145 = _sels_sels_1_T_14 ? 80'h4000 : _sels_sels_1_T_144; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_146 = _sels_sels_1_T_13 ? 80'h2000 : _sels_sels_1_T_145; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_147 = _sels_sels_1_T_12 ? 80'h1000 : _sels_sels_1_T_146; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_148 = _sels_sels_1_T_11 ? 80'h800 : _sels_sels_1_T_147; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_149 = _sels_sels_1_T_10 ? 80'h400 : _sels_sels_1_T_148; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_150 = _sels_sels_1_T_9 ? 80'h200 : _sels_sels_1_T_149; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_151 = _sels_sels_1_T_8 ? 80'h100 : _sels_sels_1_T_150; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_152 = _sels_sels_1_T_7 ? 80'h80 : _sels_sels_1_T_151; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_153 = _sels_sels_1_T_6 ? 80'h40 : _sels_sels_1_T_152; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_154 = _sels_sels_1_T_5 ? 80'h20 : _sels_sels_1_T_153; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_155 = _sels_sels_1_T_4 ? 80'h10 : _sels_sels_1_T_154; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_156 = _sels_sels_1_T_3 ? 80'h8 : _sels_sels_1_T_155; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_157 = _sels_sels_1_T_2 ? 80'h4 : _sels_sels_1_T_156; // @[OneHot.scala:85:71] wire [79:0] _sels_sels_1_T_158 = _sels_sels_1_T_1 ? 80'h2 : _sels_sels_1_T_157; // @[OneHot.scala:85:71] assign _sels_sels_1_T_159 = _sels_sels_1_T ? 80'h1 : _sels_sels_1_T_158; // @[OneHot.scala:85:71] assign sels_1 = _sels_sels_1_T_159; // @[Mux.scala:50:70] wire [79:0] _sels_T_2 = ~sels_1; // @[util.scala:415:20, :420:21] wire [79:0] _sels_T_3 = _sels_T_1 & _sels_T_2; // @[util.scala:420:{19,21}] wire _sel_fire_0_T_2; // @[rename-freelist.scala:128:45] wire _sel_fire_1_T_2; // @[rename-freelist.scala:128:45] wire sel_fire_0; // @[rename-freelist.scala:68:23] wire sel_fire_1; // @[rename-freelist.scala:68:23] wire [127:0] _GEN = 128'h1 << io_alloc_pregs_0_bits_0; // @[OneHot.scala:58:35] wire [127:0] _allocs_T; // @[OneHot.scala:58:35] assign _allocs_T = _GEN; // @[OneHot.scala:58:35] wire [127:0] _io_debug_freelist_T; // @[OneHot.scala:58:35] assign _io_debug_freelist_T = _GEN; // @[OneHot.scala:58:35] wire [79:0] allocs_0 = _allocs_T[79:0]; // @[OneHot.scala:58:35] wire [127:0] _GEN_0 = 128'h1 << io_alloc_pregs_1_bits_0; // @[OneHot.scala:58:35] wire [127:0] _allocs_T_1; // @[OneHot.scala:58:35] assign _allocs_T_1 = _GEN_0; // @[OneHot.scala:58:35] wire [127:0] _io_debug_freelist_T_4; // @[OneHot.scala:58:35] assign _io_debug_freelist_T_4 = _GEN_0; // @[OneHot.scala:58:35] wire [79:0] allocs_1 = _allocs_T_1[79:0]; // @[OneHot.scala:58:35] wire [79:0] _alloc_masks_T = {80{io_reqs_1_0}}; // @[rename-freelist.scala:52:7, :72:94] wire [79:0] _alloc_masks_T_1 = allocs_1 & _alloc_masks_T; // @[rename-freelist.scala:71:57, :72:{88,94}] wire [79:0] alloc_masks_1 = _alloc_masks_T_1; // @[rename-freelist.scala:72:{84,88}] wire [79:0] _alloc_masks_T_2 = {80{io_reqs_0_0}}; // @[rename-freelist.scala:52:7, :72:94] wire [79:0] _alloc_masks_T_3 = allocs_0 & _alloc_masks_T_2; // @[rename-freelist.scala:71:57, :72:{88,94}] wire [79:0] alloc_masks_0 = alloc_masks_1 | _alloc_masks_T_3; // @[rename-freelist.scala:72:{84,88}] wire [79:0] _sel_mask_T = {80{sel_fire_0}}; // @[rename-freelist.scala:68:23, :75:66] wire [79:0] _sel_mask_T_1 = sels_0 & _sel_mask_T; // @[util.scala:415:20] wire [79:0] _sel_mask_T_2 = {80{sel_fire_1}}; // @[rename-freelist.scala:68:23, :75:66] wire [79:0] _sel_mask_T_3 = sels_1 & _sel_mask_T_2; // @[util.scala:415:20] wire [79:0] sel_mask = _sel_mask_T_1 | _sel_mask_T_3; // @[rename-freelist.scala:75:{60,82}] wire [79:0] _br_deallocs_T = {80{io_brupdate_b2_mispredict_0}}; // @[rename-freelist.scala:52:7, :77:69] wire [15:0][79:0] _GEN_1 = {{br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_0}, {br_alloc_lists_11}, {br_alloc_lists_10}, {br_alloc_lists_9}, {br_alloc_lists_8}, {br_alloc_lists_7}, {br_alloc_lists_6}, {br_alloc_lists_5}, {br_alloc_lists_4}, {br_alloc_lists_3}, {br_alloc_lists_2}, {br_alloc_lists_1}, {br_alloc_lists_0}}; // @[rename-freelist.scala:64:27, :77:63] wire [79:0] br_deallocs = _GEN_1[io_brupdate_b2_uop_br_tag_0] & _br_deallocs_T; // @[rename-freelist.scala:52:7, :77:{63,69}] reg com_deallocs_REG_0_valid; // @[rename-freelist.scala:78:29] reg [6:0] com_deallocs_REG_0_bits; // @[rename-freelist.scala:78:29] reg com_deallocs_REG_1_valid; // @[rename-freelist.scala:78:29] reg [6:0] com_deallocs_REG_1_bits; // @[rename-freelist.scala:78:29] wire [127:0] _com_deallocs_T = 128'h1 << com_deallocs_REG_0_bits; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_1 = _com_deallocs_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_2 = {80{com_deallocs_REG_0_valid}}; // @[rename-freelist.scala:78:{29,88}] wire [79:0] _com_deallocs_T_3 = _com_deallocs_T_1 & _com_deallocs_T_2; // @[rename-freelist.scala:78:{67,82,88}] wire [127:0] _com_deallocs_T_4 = 128'h1 << com_deallocs_REG_1_bits; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_5 = _com_deallocs_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_deallocs_T_6 = {80{com_deallocs_REG_1_valid}}; // @[rename-freelist.scala:78:{29,88}] wire [79:0] _com_deallocs_T_7 = _com_deallocs_T_5 & _com_deallocs_T_6; // @[rename-freelist.scala:78:{67,82,88}] wire [79:0] com_deallocs = _com_deallocs_T_3 | _com_deallocs_T_7; // @[rename-freelist.scala:78:{82,109}] wire [79:0] _rollback_deallocs_T = {80{io_rollback_0}}; // @[rename-freelist.scala:52:7, :79:49] wire [79:0] rollback_deallocs = spec_alloc_list & _rollback_deallocs_T; // @[rename-freelist.scala:63:32, :79:{43,49}] wire [79:0] _dealloc_mask_T = com_deallocs | br_deallocs; // @[rename-freelist.scala:77:63, :78:109, :80:35] wire [79:0] dealloc_mask = _dealloc_mask_T | rollback_deallocs; // @[rename-freelist.scala:79:43, :80:{35,49}] wire [127:0] _com_despec_T = 128'h1 << io_despec_0_bits_0; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_1 = _com_despec_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_2 = {80{io_despec_0_valid_0}}; // @[rename-freelist.scala:52:7, :82:76] wire [79:0] _com_despec_T_3 = _com_despec_T_1 & _com_despec_T_2; // @[rename-freelist.scala:82:{55,70,76}] wire [127:0] _com_despec_T_4 = 128'h1 << io_despec_1_bits_0; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_5 = _com_despec_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _com_despec_T_6 = {80{io_despec_1_valid_0}}; // @[rename-freelist.scala:52:7, :82:76] wire [79:0] _com_despec_T_7 = _com_despec_T_5 & _com_despec_T_6; // @[rename-freelist.scala:82:{55,70,76}] wire [79:0] com_despec = _com_despec_T_3 | _com_despec_T_7; // @[rename-freelist.scala:82:{70,97}] wire [79:0] _updated_br_alloc_list_T = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_1 = br_alloc_lists_0 & _updated_br_alloc_list_T; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list = _updated_br_alloc_list_T_1 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_2 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_3 = br_alloc_lists_1 & _updated_br_alloc_list_T_2; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_1 = _updated_br_alloc_list_T_3 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_4 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_5 = br_alloc_lists_2 & _updated_br_alloc_list_T_4; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_2 = _updated_br_alloc_list_T_5 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_6 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_7 = br_alloc_lists_3 & _updated_br_alloc_list_T_6; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_3 = _updated_br_alloc_list_T_7 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_8 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_9 = br_alloc_lists_4 & _updated_br_alloc_list_T_8; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_4 = _updated_br_alloc_list_T_9 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_10 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_11 = br_alloc_lists_5 & _updated_br_alloc_list_T_10; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_5 = _updated_br_alloc_list_T_11 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_12 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_13 = br_alloc_lists_6 & _updated_br_alloc_list_T_12; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_6 = _updated_br_alloc_list_T_13 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_14 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_15 = br_alloc_lists_7 & _updated_br_alloc_list_T_14; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_7 = _updated_br_alloc_list_T_15 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_16 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_17 = br_alloc_lists_8 & _updated_br_alloc_list_T_16; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_8 = _updated_br_alloc_list_T_17 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_18 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_19 = br_alloc_lists_9 & _updated_br_alloc_list_T_18; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_9 = _updated_br_alloc_list_T_19 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_20 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_21 = br_alloc_lists_10 & _updated_br_alloc_list_T_20; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_10 = _updated_br_alloc_list_T_21 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [79:0] _updated_br_alloc_list_T_22 = ~br_deallocs; // @[rename-freelist.scala:77:63, :91:27] wire [79:0] _updated_br_alloc_list_T_23 = br_alloc_lists_11 & _updated_br_alloc_list_T_22; // @[rename-freelist.scala:64:27, :91:{25,27}] wire [79:0] updated_br_alloc_list_11 = _updated_br_alloc_list_T_23 | alloc_masks_0; // @[rename-freelist.scala:72:84, :91:{25,40}] wire [1:0] br_slots_hi = {_br_slots_WIRE_2, _br_slots_WIRE_1}; // @[rename-freelist.scala:96:{27,66}] wire [2:0] br_slots = {br_slots_hi, 1'h0}; // @[rename-freelist.scala:96:66] wire _list_req_T_1 = io_ren_br_tags_1_bits_0 == 4'h0; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1 = _list_req_T_1; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_2 = io_ren_br_tags_2_bits_0 == 4'h0; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2 = _list_req_T_2; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi = {_list_req_WIRE_2, _list_req_WIRE_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_3 = {list_req_hi, 1'h1}; // @[rename-freelist.scala:99:75] wire [2:0] list_req = _list_req_T_3 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list = |list_req; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_0_T = list_req[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_0_T_1 = list_req[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_0_T_2 = list_req[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_0_T_3 = _br_alloc_lists_0_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_0_T_4 = _br_alloc_lists_0_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_0_T_6 = _br_alloc_lists_0_T_3 | _br_alloc_lists_0_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_0_T_7 = _br_alloc_lists_0_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_0_WIRE = _br_alloc_lists_0_T_7; // @[Mux.scala:30:73] wire _list_req_T_5 = io_ren_br_tags_1_bits_0 == 4'h1; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1_1 = _list_req_T_5; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_6 = io_ren_br_tags_2_bits_0 == 4'h1; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_1_2 = _list_req_T_6; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_1 = {_list_req_WIRE_1_2, _list_req_WIRE_1_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_7 = {list_req_hi_1, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_1 = _list_req_T_7 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_1 = |list_req_1; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_1_T = list_req_1[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_1_T_1 = list_req_1[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_1_T_2 = list_req_1[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_1_T_3 = _br_alloc_lists_1_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_1_T_4 = _br_alloc_lists_1_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_1_T_6 = _br_alloc_lists_1_T_3 | _br_alloc_lists_1_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_T_7 = _br_alloc_lists_1_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_1_WIRE = _br_alloc_lists_1_T_7; // @[Mux.scala:30:73] wire _list_req_T_9 = io_ren_br_tags_1_bits_0 == 4'h2; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2_1 = _list_req_T_9; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_10 = io_ren_br_tags_2_bits_0 == 4'h2; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_2_2 = _list_req_T_10; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_2 = {_list_req_WIRE_2_2, _list_req_WIRE_2_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_11 = {list_req_hi_2, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_2 = _list_req_T_11 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_2 = |list_req_2; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_2_T = list_req_2[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_2_T_1 = list_req_2[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_2_T_2 = list_req_2[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_2_T_3 = _br_alloc_lists_2_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_2_T_4 = _br_alloc_lists_2_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_2_T_6 = _br_alloc_lists_2_T_3 | _br_alloc_lists_2_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_T_7 = _br_alloc_lists_2_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_2_WIRE = _br_alloc_lists_2_T_7; // @[Mux.scala:30:73] wire _list_req_T_13 = io_ren_br_tags_1_bits_0 == 4'h3; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_3_1 = _list_req_T_13; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_14 = io_ren_br_tags_2_bits_0 == 4'h3; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_3_2 = _list_req_T_14; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_3 = {_list_req_WIRE_3_2, _list_req_WIRE_3_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_15 = {list_req_hi_3, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_3 = _list_req_T_15 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_3 = |list_req_3; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_3_T = list_req_3[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_3_T_1 = list_req_3[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_3_T_2 = list_req_3[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_3_T_3 = _br_alloc_lists_3_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_3_T_4 = _br_alloc_lists_3_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_3_T_6 = _br_alloc_lists_3_T_3 | _br_alloc_lists_3_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_T_7 = _br_alloc_lists_3_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_3_WIRE = _br_alloc_lists_3_T_7; // @[Mux.scala:30:73] wire _list_req_T_17 = io_ren_br_tags_1_bits_0 == 4'h4; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_4_1 = _list_req_T_17; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_18 = io_ren_br_tags_2_bits_0 == 4'h4; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_4_2 = _list_req_T_18; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_4 = {_list_req_WIRE_4_2, _list_req_WIRE_4_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_19 = {list_req_hi_4, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_4 = _list_req_T_19 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_4 = |list_req_4; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_4_T = list_req_4[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_4_T_1 = list_req_4[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_4_T_2 = list_req_4[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_4_T_3 = _br_alloc_lists_4_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_4_T_4 = _br_alloc_lists_4_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_4_T_6 = _br_alloc_lists_4_T_3 | _br_alloc_lists_4_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_T_7 = _br_alloc_lists_4_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_4_WIRE = _br_alloc_lists_4_T_7; // @[Mux.scala:30:73] wire _list_req_T_21 = io_ren_br_tags_1_bits_0 == 4'h5; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_5_1 = _list_req_T_21; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_22 = io_ren_br_tags_2_bits_0 == 4'h5; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_5_2 = _list_req_T_22; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_5 = {_list_req_WIRE_5_2, _list_req_WIRE_5_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_23 = {list_req_hi_5, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_5 = _list_req_T_23 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_5 = |list_req_5; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_5_T = list_req_5[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_5_T_1 = list_req_5[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_5_T_2 = list_req_5[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_5_T_3 = _br_alloc_lists_5_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_5_T_4 = _br_alloc_lists_5_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_5_T_6 = _br_alloc_lists_5_T_3 | _br_alloc_lists_5_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_T_7 = _br_alloc_lists_5_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_5_WIRE = _br_alloc_lists_5_T_7; // @[Mux.scala:30:73] wire _list_req_T_25 = io_ren_br_tags_1_bits_0 == 4'h6; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_6_1 = _list_req_T_25; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_26 = io_ren_br_tags_2_bits_0 == 4'h6; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_6_2 = _list_req_T_26; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_6 = {_list_req_WIRE_6_2, _list_req_WIRE_6_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_27 = {list_req_hi_6, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_6 = _list_req_T_27 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_6 = |list_req_6; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_6_T = list_req_6[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_6_T_1 = list_req_6[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_6_T_2 = list_req_6[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_6_T_3 = _br_alloc_lists_6_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_6_T_4 = _br_alloc_lists_6_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_6_T_6 = _br_alloc_lists_6_T_3 | _br_alloc_lists_6_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_T_7 = _br_alloc_lists_6_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_6_WIRE = _br_alloc_lists_6_T_7; // @[Mux.scala:30:73] wire _list_req_T_29 = io_ren_br_tags_1_bits_0 == 4'h7; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_7_1 = _list_req_T_29; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_30 = io_ren_br_tags_2_bits_0 == 4'h7; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_7_2 = _list_req_T_30; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_7 = {_list_req_WIRE_7_2, _list_req_WIRE_7_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_31 = {list_req_hi_7, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_7 = _list_req_T_31 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_7 = |list_req_7; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_7_T = list_req_7[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_7_T_1 = list_req_7[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_7_T_2 = list_req_7[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_7_T_3 = _br_alloc_lists_7_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_7_T_4 = _br_alloc_lists_7_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_7_T_6 = _br_alloc_lists_7_T_3 | _br_alloc_lists_7_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_T_7 = _br_alloc_lists_7_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_7_WIRE = _br_alloc_lists_7_T_7; // @[Mux.scala:30:73] wire _list_req_T_33 = io_ren_br_tags_1_bits_0 == 4'h8; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_8_1 = _list_req_T_33; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_34 = io_ren_br_tags_2_bits_0 == 4'h8; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_8_2 = _list_req_T_34; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_8 = {_list_req_WIRE_8_2, _list_req_WIRE_8_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_35 = {list_req_hi_8, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_8 = _list_req_T_35 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_8 = |list_req_8; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_8_T = list_req_8[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_8_T_1 = list_req_8[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_8_T_2 = list_req_8[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_8_T_3 = _br_alloc_lists_8_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_8_T_4 = _br_alloc_lists_8_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_8_T_6 = _br_alloc_lists_8_T_3 | _br_alloc_lists_8_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_T_7 = _br_alloc_lists_8_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_8_WIRE = _br_alloc_lists_8_T_7; // @[Mux.scala:30:73] wire _list_req_T_37 = io_ren_br_tags_1_bits_0 == 4'h9; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_9_1 = _list_req_T_37; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_38 = io_ren_br_tags_2_bits_0 == 4'h9; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_9_2 = _list_req_T_38; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_9 = {_list_req_WIRE_9_2, _list_req_WIRE_9_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_39 = {list_req_hi_9, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_9 = _list_req_T_39 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_9 = |list_req_9; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_9_T = list_req_9[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_9_T_1 = list_req_9[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_9_T_2 = list_req_9[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_9_T_3 = _br_alloc_lists_9_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_9_T_4 = _br_alloc_lists_9_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_9_T_6 = _br_alloc_lists_9_T_3 | _br_alloc_lists_9_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_T_7 = _br_alloc_lists_9_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_9_WIRE = _br_alloc_lists_9_T_7; // @[Mux.scala:30:73] wire _list_req_T_41 = io_ren_br_tags_1_bits_0 == 4'hA; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_10_1 = _list_req_T_41; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_42 = io_ren_br_tags_2_bits_0 == 4'hA; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_10_2 = _list_req_T_42; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_10 = {_list_req_WIRE_10_2, _list_req_WIRE_10_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_43 = {list_req_hi_10, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_10 = _list_req_T_43 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_10 = |list_req_10; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_10_T = list_req_10[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_10_T_1 = list_req_10[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_10_T_2 = list_req_10[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_10_T_3 = _br_alloc_lists_10_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_10_T_4 = _br_alloc_lists_10_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_10_T_6 = _br_alloc_lists_10_T_3 | _br_alloc_lists_10_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_T_7 = _br_alloc_lists_10_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_10_WIRE = _br_alloc_lists_10_T_7; // @[Mux.scala:30:73] wire _list_req_T_45 = io_ren_br_tags_1_bits_0 == 4'hB; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_11_1 = _list_req_T_45; // @[rename-freelist.scala:99:{29,65}] wire _list_req_T_46 = io_ren_br_tags_2_bits_0 == 4'hB; // @[rename-freelist.scala:52:7, :99:65] wire _list_req_WIRE_11_2 = _list_req_T_46; // @[rename-freelist.scala:99:{29,65}] wire [1:0] list_req_hi_11 = {_list_req_WIRE_11_2, _list_req_WIRE_11_1}; // @[rename-freelist.scala:99:{29,75}] wire [2:0] _list_req_T_47 = {list_req_hi_11, 1'h0}; // @[rename-freelist.scala:99:75] wire [2:0] list_req_11 = _list_req_T_47 & br_slots; // @[rename-freelist.scala:96:66, :99:{75,82}] wire new_list_11 = |list_req_11; // @[rename-freelist.scala:99:82, :100:31] wire _br_alloc_lists_11_T = list_req_11[0]; // @[Mux.scala:32:36] wire _br_alloc_lists_11_T_1 = list_req_11[1]; // @[Mux.scala:32:36] wire _br_alloc_lists_11_T_2 = list_req_11[2]; // @[Mux.scala:32:36] wire [79:0] _br_alloc_lists_11_T_3 = _br_alloc_lists_11_T ? alloc_masks_0 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_11_T_4 = _br_alloc_lists_11_T_1 ? alloc_masks_1 : 80'h0; // @[Mux.scala:30:73, :32:36] wire [79:0] _br_alloc_lists_11_T_6 = _br_alloc_lists_11_T_3 | _br_alloc_lists_11_T_4; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_T_7 = _br_alloc_lists_11_T_6; // @[Mux.scala:30:73] wire [79:0] _br_alloc_lists_11_WIRE = _br_alloc_lists_11_T_7; // @[Mux.scala:30:73] wire [79:0] _spec_alloc_list_T = spec_alloc_list | alloc_masks_0; // @[rename-freelist.scala:63:32, :72:84, :116:39] wire [79:0] _spec_alloc_list_T_1 = ~dealloc_mask; // @[rename-freelist.scala:80:49, :116:59] wire [79:0] _spec_alloc_list_T_2 = _spec_alloc_list_T & _spec_alloc_list_T_1; // @[rename-freelist.scala:116:{39,57,59}] wire [79:0] _spec_alloc_list_T_3 = ~com_despec; // @[rename-freelist.scala:82:97, :116:75] wire [79:0] _spec_alloc_list_T_4 = _spec_alloc_list_T_2 & _spec_alloc_list_T_3; // @[rename-freelist.scala:116:{57,73,75}] wire [79:0] _free_list_T = ~sel_mask; // @[rename-freelist.scala:75:82, :119:33] wire [79:0] _free_list_T_1 = free_list & _free_list_T; // @[rename-freelist.scala:62:26, :119:{31,33}] wire [79:0] _free_list_T_2 = _free_list_T_1 | dealloc_mask; // @[rename-freelist.scala:80:49, :119:{31,44}] wire can_sel = |sels_0; // @[util.scala:415:20] reg r_valid; // @[rename-freelist.scala:124:26] assign io_alloc_pregs_0_valid_0 = r_valid; // @[rename-freelist.scala:52:7, :124:26] wire [15:0] r_sel_hi = sels_0[79:64]; // @[OneHot.scala:30:18] wire [63:0] r_sel_lo = sels_0[63:0]; // @[OneHot.scala:31:18] wire _r_sel_T = |r_sel_hi; // @[OneHot.scala:30:18, :32:14] wire [63:0] _r_sel_T_1 = {48'h0, r_sel_hi} | r_sel_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [31:0] r_sel_hi_1 = _r_sel_T_1[63:32]; // @[OneHot.scala:30:18, :32:28] wire [31:0] r_sel_lo_1 = _r_sel_T_1[31:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_2 = |r_sel_hi_1; // @[OneHot.scala:30:18, :32:14] wire [31:0] _r_sel_T_3 = r_sel_hi_1 | r_sel_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] r_sel_hi_2 = _r_sel_T_3[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] r_sel_lo_2 = _r_sel_T_3[15:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_4 = |r_sel_hi_2; // @[OneHot.scala:30:18, :32:14] wire [15:0] _r_sel_T_5 = r_sel_hi_2 | r_sel_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] r_sel_hi_3 = _r_sel_T_5[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] r_sel_lo_3 = _r_sel_T_5[7:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_6 = |r_sel_hi_3; // @[OneHot.scala:30:18, :32:14] wire [7:0] _r_sel_T_7 = r_sel_hi_3 | r_sel_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] r_sel_hi_4 = _r_sel_T_7[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] r_sel_lo_4 = _r_sel_T_7[3:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_8 = |r_sel_hi_4; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sel_T_9 = r_sel_hi_4 | r_sel_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sel_hi_5 = _r_sel_T_9[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sel_lo_5 = _r_sel_T_9[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_10 = |r_sel_hi_5; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sel_T_11 = r_sel_hi_5 | r_sel_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sel_T_12 = _r_sel_T_11[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sel_T_13 = {_r_sel_T_10, _r_sel_T_12}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sel_T_14 = {_r_sel_T_8, _r_sel_T_13}; // @[OneHot.scala:32:{10,14}] wire [3:0] _r_sel_T_15 = {_r_sel_T_6, _r_sel_T_14}; // @[OneHot.scala:32:{10,14}] wire [4:0] _r_sel_T_16 = {_r_sel_T_4, _r_sel_T_15}; // @[OneHot.scala:32:{10,14}] wire [5:0] _r_sel_T_17 = {_r_sel_T_2, _r_sel_T_16}; // @[OneHot.scala:32:{10,14}] wire [6:0] _r_sel_T_18 = {_r_sel_T, _r_sel_T_17}; // @[OneHot.scala:32:{10,14}] reg [6:0] r_sel; // @[rename-freelist.scala:125:28] assign io_alloc_pregs_0_bits_0 = r_sel; // @[rename-freelist.scala:52:7, :125:28] wire _r_valid_T = ~io_reqs_0_0; // @[rename-freelist.scala:52:7, :127:27] wire _r_valid_T_1 = r_valid & _r_valid_T; // @[rename-freelist.scala:124:26, :127:{24,27}] wire _r_valid_T_2 = _r_valid_T_1 | can_sel; // @[rename-freelist.scala:123:27, :127:{24,39}] wire _sel_fire_0_T = ~r_valid; // @[rename-freelist.scala:124:26, :128:21] wire _sel_fire_0_T_1 = _sel_fire_0_T | io_reqs_0_0; // @[rename-freelist.scala:52:7, :128:{21,30}] assign _sel_fire_0_T_2 = _sel_fire_0_T_1 & can_sel; // @[rename-freelist.scala:123:27, :128:{30,45}] assign sel_fire_0 = _sel_fire_0_T_2; // @[rename-freelist.scala:68:23, :128:45] wire can_sel_1 = |sels_1; // @[util.scala:415:20] reg r_valid_1; // @[rename-freelist.scala:124:26] assign io_alloc_pregs_1_valid_0 = r_valid_1; // @[rename-freelist.scala:52:7, :124:26] wire [15:0] r_sel_hi_6 = sels_1[79:64]; // @[OneHot.scala:30:18] wire [63:0] r_sel_lo_6 = sels_1[63:0]; // @[OneHot.scala:31:18] wire _r_sel_T_19 = |r_sel_hi_6; // @[OneHot.scala:30:18, :32:14] wire [63:0] _r_sel_T_20 = {48'h0, r_sel_hi_6} | r_sel_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire [31:0] r_sel_hi_7 = _r_sel_T_20[63:32]; // @[OneHot.scala:30:18, :32:28] wire [31:0] r_sel_lo_7 = _r_sel_T_20[31:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_21 = |r_sel_hi_7; // @[OneHot.scala:30:18, :32:14] wire [31:0] _r_sel_T_22 = r_sel_hi_7 | r_sel_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] r_sel_hi_8 = _r_sel_T_22[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] r_sel_lo_8 = _r_sel_T_22[15:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_23 = |r_sel_hi_8; // @[OneHot.scala:30:18, :32:14] wire [15:0] _r_sel_T_24 = r_sel_hi_8 | r_sel_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] r_sel_hi_9 = _r_sel_T_24[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] r_sel_lo_9 = _r_sel_T_24[7:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_25 = |r_sel_hi_9; // @[OneHot.scala:30:18, :32:14] wire [7:0] _r_sel_T_26 = r_sel_hi_9 | r_sel_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] r_sel_hi_10 = _r_sel_T_26[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] r_sel_lo_10 = _r_sel_T_26[3:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_27 = |r_sel_hi_10; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sel_T_28 = r_sel_hi_10 | r_sel_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sel_hi_11 = _r_sel_T_28[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sel_lo_11 = _r_sel_T_28[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sel_T_29 = |r_sel_hi_11; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sel_T_30 = r_sel_hi_11 | r_sel_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sel_T_31 = _r_sel_T_30[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sel_T_32 = {_r_sel_T_29, _r_sel_T_31}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sel_T_33 = {_r_sel_T_27, _r_sel_T_32}; // @[OneHot.scala:32:{10,14}] wire [3:0] _r_sel_T_34 = {_r_sel_T_25, _r_sel_T_33}; // @[OneHot.scala:32:{10,14}] wire [4:0] _r_sel_T_35 = {_r_sel_T_23, _r_sel_T_34}; // @[OneHot.scala:32:{10,14}] wire [5:0] _r_sel_T_36 = {_r_sel_T_21, _r_sel_T_35}; // @[OneHot.scala:32:{10,14}] wire [6:0] _r_sel_T_37 = {_r_sel_T_19, _r_sel_T_36}; // @[OneHot.scala:32:{10,14}] reg [6:0] r_sel_1; // @[rename-freelist.scala:125:28] assign io_alloc_pregs_1_bits_0 = r_sel_1; // @[rename-freelist.scala:52:7, :125:28] wire _r_valid_T_3 = ~io_reqs_1_0; // @[rename-freelist.scala:52:7, :127:27] wire _r_valid_T_4 = r_valid_1 & _r_valid_T_3; // @[rename-freelist.scala:124:26, :127:{24,27}] wire _r_valid_T_5 = _r_valid_T_4 | can_sel_1; // @[rename-freelist.scala:123:27, :127:{24,39}] wire _sel_fire_1_T = ~r_valid_1; // @[rename-freelist.scala:124:26, :128:21] wire _sel_fire_1_T_1 = _sel_fire_1_T | io_reqs_1_0; // @[rename-freelist.scala:52:7, :128:{21,30}] assign _sel_fire_1_T_2 = _sel_fire_1_T_1 & can_sel_1; // @[rename-freelist.scala:123:27, :128:{30,45}] assign sel_fire_1 = _sel_fire_1_T_2; // @[rename-freelist.scala:68:23, :128:45] wire [79:0] _io_debug_freelist_T_1 = _io_debug_freelist_T[79:0]; // @[OneHot.scala:58:35] wire [79:0] _io_debug_freelist_T_2 = {80{io_alloc_pregs_0_valid_0}}; // @[rename-freelist.scala:52:7, :134:90] wire [79:0] _io_debug_freelist_T_3 = _io_debug_freelist_T_1 & _io_debug_freelist_T_2; // @[rename-freelist.scala:134:{76,84,90}] wire [79:0] _io_debug_freelist_T_5 = _io_debug_freelist_T_4[79:0]; // @[OneHot.scala:58:35] wire [79:0] _io_debug_freelist_T_6 = {80{io_alloc_pregs_1_valid_0}}; // @[rename-freelist.scala:52:7, :134:90] wire [79:0] _io_debug_freelist_T_7 = _io_debug_freelist_T_5 & _io_debug_freelist_T_6; // @[rename-freelist.scala:134:{76,84,90}] wire [79:0] _io_debug_freelist_T_8 = _io_debug_freelist_T_3 | _io_debug_freelist_T_7; // @[rename-freelist.scala:134:{84,111}] assign _io_debug_freelist_T_9 = free_list | _io_debug_freelist_T_8; // @[rename-freelist.scala:62:26, :134:{34,111}] assign io_debug_freelist_0 = _io_debug_freelist_T_9; // @[rename-freelist.scala:52:7, :134:34]

Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_3 : input clock : Clock input reset : Reset output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}, flip prober_state : { valid : UInt<1>, bits : UInt<40>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<8>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<20>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<40>, commit_coh : { state : UInt<2>}, lb_read : { offset : UInt<2>}, flip lb_resp : UInt<128>, lb_write : { valid : UInt<1>, bits : { offset : UInt<2>, data : UInt<128>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>} regreset state : UInt<5>, clock, reset, UInt<5>(0h0) reg req : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}, clock node req_idx = bits(req.addr, 11, 6) node req_tag = shr(req.addr, 12) node _req_block_addr_T = shr(req.addr, 6) node req_block_addr = shl(_req_block_addr_T, 6) regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0) wire new_coh_meta : { state : UInt<2>} connect new_coh_meta.state, UInt<2>(0h0) regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1) node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3) node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state) node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _r_T_19 = eq(_r_T_18, _r_T_6) node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _r_T_23 = eq(_r_T_17, _r_T_6) node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20) node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21) node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22) node _r_T_27 = eq(_r_T_16, _r_T_6) node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24) node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25) node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26) node _r_T_31 = eq(_r_T_15, _r_T_6) node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28) node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29) node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30) node _r_T_35 = eq(_r_T_14, _r_T_6) node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32) node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33) node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34) node _r_T_39 = eq(_r_T_13, _r_T_6) node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36) node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37) node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38) node _r_T_43 = eq(_r_T_12, _r_T_6) node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40) node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41) node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42) node _r_T_47 = eq(_r_T_11, _r_T_6) node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44) node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45) node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46) node _r_T_51 = eq(_r_T_10, _r_T_6) node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48) node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49) node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50) node _r_T_55 = eq(_r_T_9, _r_T_6) node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52) node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53) node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54) node _r_T_59 = eq(_r_T_8, _r_T_6) node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56) node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57) node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58) node _r_T_63 = eq(_r_T_7, _r_T_6) node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60) node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61) node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62) wire coh_on_clear : { state : UInt<2>} connect coh_on_clear.state, r_3 node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1) node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3) node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6) node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7) node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8) node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13) node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14) node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15) node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16) node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20) node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21) node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24) node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26) node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29) node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30) node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31) node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36) node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37) node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38) node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39) node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43) node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44) node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46) node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48) node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49) node _grow_param_r_T = cat(grow_param_r_c, new_coh.state) node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3)) node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2)) node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1)) node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3)) node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2)) node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3)) node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2)) node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0)) node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1)) node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0)) node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1)) node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0)) node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T) node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T) node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26) node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27) node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T) node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29) node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30) node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T) node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32) node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33) node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T) node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35) node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36) node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T) node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38) node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39) node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T) node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41) node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42) node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T) node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44) node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45) node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T) node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47) node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48) node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T) node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50) node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51) node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T) node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53) node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54) node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T) node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56) node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57) wire grow_param_meta : { state : UInt<2>} connect grow_param_meta.state, grow_param node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1) node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3) node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6) node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7) node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8) node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13) node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14) node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15) node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16) node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20) node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21) node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24) node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26) node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29) node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30) node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31) node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36) node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37) node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38) node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39) node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43) node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44) node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46) node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48) node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49) node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param) node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1)) node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0)) node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0)) node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0)) node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T) node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0)) node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T) node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10) node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T) node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12) node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T) node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14) wire coh_on_grant : { state : UInt<2>} connect coh_on_grant.state, _coh_on_grant_T_16 node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1) node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3) node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6) node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7) node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8) node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13) node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14) node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15) node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16) node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20) node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21) node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24) node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26) node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29) node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30) node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31) node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36) node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37) node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38) node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39) node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43) node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44) node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46) node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48) node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49) node _r1_T = cat(r1_c, new_coh.state) node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3)) node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2)) node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1)) node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3)) node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2)) node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3)) node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2)) node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0)) node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1)) node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0)) node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1)) node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0)) node _r1_T_25 = eq(_r1_T_24, _r1_T) node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r1_T_28 = eq(_r1_T_22, _r1_T) node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26) node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27) node _r1_T_31 = eq(_r1_T_20, _r1_T) node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29) node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30) node _r1_T_34 = eq(_r1_T_18, _r1_T) node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32) node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33) node _r1_T_37 = eq(_r1_T_16, _r1_T) node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35) node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36) node _r1_T_40 = eq(_r1_T_14, _r1_T) node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38) node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39) node _r1_T_43 = eq(_r1_T_12, _r1_T) node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41) node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42) node _r1_T_46 = eq(_r1_T_10, _r1_T) node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44) node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45) node _r1_T_49 = eq(_r1_T_8, _r1_T) node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47) node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48) node _r1_T_52 = eq(_r1_T_6, _r1_T) node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50) node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51) node _r1_T_55 = eq(_r1_T_4, _r1_T) node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53) node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54) node _r1_T_58 = eq(_r1_T_2, _r1_T) node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56) node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57) node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1) node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3) node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6) node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7) node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8) node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13) node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14) node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15) node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16) node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20) node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21) node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24) node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26) node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29) node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30) node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31) node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36) node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37) node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38) node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39) node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43) node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44) node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46) node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48) node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49) node _r2_T = cat(r2_c, new_coh.state) node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3)) node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2)) node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1)) node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3)) node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2)) node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3)) node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2)) node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0)) node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1)) node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0)) node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1)) node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0)) node _r2_T_25 = eq(_r2_T_24, _r2_T) node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _r2_T_28 = eq(_r2_T_22, _r2_T) node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26) node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27) node _r2_T_31 = eq(_r2_T_20, _r2_T) node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29) node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30) node _r2_T_34 = eq(_r2_T_18, _r2_T) node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32) node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33) node _r2_T_37 = eq(_r2_T_16, _r2_T) node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35) node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36) node _r2_T_40 = eq(_r2_T_14, _r2_T) node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38) node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39) node _r2_T_43 = eq(_r2_T_12, _r2_T) node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41) node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42) node _r2_T_46 = eq(_r2_T_10, _r2_T) node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44) node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45) node _r2_T_49 = eq(_r2_T_8, _r2_T) node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47) node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48) node _r2_T_52 = eq(_r2_T_6, _r2_T) node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50) node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51) node _r2_T_55 = eq(_r2_T_4, _r2_T) node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53) node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54) node _r2_T_58 = eq(_r2_T_2, _r2_T) node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56) node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57) node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1) node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3) node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6) node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7) node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8) node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13) node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14) node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15) node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16) node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20) node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21) node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23) node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25) node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1)) node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11)) node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28) node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7)) node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30) node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4)) node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9)) node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha)) node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb)) node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33) node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34) node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35) node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8)) node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc)) node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd)) node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he)) node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf)) node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40) node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41) node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42) node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43) node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47) node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48) node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3)) node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50) node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6)) node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52) node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0)) node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54) node is_hit_again = and(r1_1, r2_1) node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1) node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3) node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6) node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7) node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8) node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13) node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14) node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15) node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16) node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20) node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21) node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24) node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26) node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29) node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30) node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31) node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36) node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37) node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38) node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39) node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43) node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44) node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46) node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48) node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49) node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1)) node dirties = eq(dirties_cat, _dirties_T) node biggest_grow_param = mux(dirties, r2_2, r1_2) wire dirtier_coh : { state : UInt<2>} connect dirtier_coh.state, biggest_grow_param node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd) node _T = and(io.mem_grant.ready, io.mem_grant.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 4) node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node r_1_1 = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node r_2 = or(_r_last_T, _r_last_T_1) node refill_done = and(r_2, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(r_1_1, r_beats1, r_counter1) connect r_counter, _r_counter_T node refill_address_inc = shl(r_4, 4) node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0)) node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0)) node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1) node _sec_rdy_T_3 = eq(state, UInt<5>(0h0)) node _sec_rdy_T_4 = eq(state, UInt<5>(0hd)) node _sec_rdy_T_5 = eq(state, UInt<5>(0he)) node _sec_rdy_T_6 = eq(state, UInt<5>(0hf)) node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4) node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5) node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6) node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0)) node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10) inst rpq of BranchKillableQueue_7 connect rpq.clock, clock connect rpq.reset, reset connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect rpq.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect rpq.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect rpq.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect rpq.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect rpq.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect rpq.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect rpq.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect rpq.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect rpq.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect rpq.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect rpq.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect rpq.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect rpq.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect rpq.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect rpq.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect rpq.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect rpq.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect rpq.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect rpq.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect rpq.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect rpq.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect rpq.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect rpq.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect rpq.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect rpq.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect rpq.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect rpq.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect rpq.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect rpq.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect rpq.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect rpq.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect rpq.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect rpq.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect rpq.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect rpq.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect rpq.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect rpq.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect rpq.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect rpq.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect rpq.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect rpq.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect rpq.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect rpq.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect rpq.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect rpq.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect rpq.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect rpq.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect rpq.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect rpq.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect rpq.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect rpq.io.flush, io.exception node _T_1 = eq(state, UInt<5>(0h0)) node _T_2 = eq(rpq.io.empty, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(_T_3, UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy) node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy) node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1) node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2)) node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4) node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0)) node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6) connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7 connect rpq.io.enq.bits.sdq_id, io.req.sdq_id connect rpq.io.enq.bits.way_en, io.req.way_en connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state connect rpq.io.enq.bits.tag_match, io.req.tag_match connect rpq.io.enq.bits.is_hella, io.req.is_hella connect rpq.io.enq.bits.data, io.req.data connect rpq.io.enq.bits.addr, io.req.addr connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if connect rpq.io.enq.bits.uop.fp_typ, io.req.uop.fp_typ connect rpq.io.enq.bits.uop.fp_rm, io.req.uop.fp_rm connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val connect rpq.io.enq.bits.uop.fcn_op, io.req.uop.fcn_op connect rpq.io.enq.bits.uop.fcn_dw, io.req.uop.fcn_dw connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3 connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2 connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1 connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1 connect rpq.io.enq.bits.uop.csr_cmd, io.req.uop.csr_cmd connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause connect rpq.io.enq.bits.uop.exception, io.req.uop.exception connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3 connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2 connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1 connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx connect rpq.io.enq.bits.uop.fp_ctrl.vec, io.req.uop.fp_ctrl.vec connect rpq.io.enq.bits.uop.fp_ctrl.wflags, io.req.uop.fp_ctrl.wflags connect rpq.io.enq.bits.uop.fp_ctrl.sqrt, io.req.uop.fp_ctrl.sqrt connect rpq.io.enq.bits.uop.fp_ctrl.div, io.req.uop.fp_ctrl.div connect rpq.io.enq.bits.uop.fp_ctrl.fma, io.req.uop.fp_ctrl.fma connect rpq.io.enq.bits.uop.fp_ctrl.fastpipe, io.req.uop.fp_ctrl.fastpipe connect rpq.io.enq.bits.uop.fp_ctrl.toint, io.req.uop.fp_ctrl.toint connect rpq.io.enq.bits.uop.fp_ctrl.fromint, io.req.uop.fp_ctrl.fromint connect rpq.io.enq.bits.uop.fp_ctrl.typeTagOut, io.req.uop.fp_ctrl.typeTagOut connect rpq.io.enq.bits.uop.fp_ctrl.typeTagIn, io.req.uop.fp_ctrl.typeTagIn connect rpq.io.enq.bits.uop.fp_ctrl.swap23, io.req.uop.fp_ctrl.swap23 connect rpq.io.enq.bits.uop.fp_ctrl.swap12, io.req.uop.fp_ctrl.swap12 connect rpq.io.enq.bits.uop.fp_ctrl.ren3, io.req.uop.fp_ctrl.ren3 connect rpq.io.enq.bits.uop.fp_ctrl.ren2, io.req.uop.fp_ctrl.ren2 connect rpq.io.enq.bits.uop.fp_ctrl.ren1, io.req.uop.fp_ctrl.ren1 connect rpq.io.enq.bits.uop.fp_ctrl.wen, io.req.uop.fp_ctrl.wen connect rpq.io.enq.bits.uop.fp_ctrl.ldst, io.req.uop.fp_ctrl.ldst connect rpq.io.enq.bits.uop.op2_sel, io.req.uop.op2_sel connect rpq.io.enq.bits.uop.op1_sel, io.req.uop.op1_sel connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed connect rpq.io.enq.bits.uop.pimm, io.req.uop.pimm connect rpq.io.enq.bits.uop.imm_sel, io.req.uop.imm_sel connect rpq.io.enq.bits.uop.imm_rename, io.req.uop.imm_rename connect rpq.io.enq.bits.uop.taken, io.req.uop.taken connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx connect rpq.io.enq.bits.uop.is_mov, io.req.uop.is_mov connect rpq.io.enq.bits.uop.is_rocc, io.req.uop.is_rocc connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc connect rpq.io.enq.bits.uop.is_eret, io.req.uop.is_eret connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo connect rpq.io.enq.bits.uop.is_sfence, io.req.uop.is_sfence connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb connect rpq.io.enq.bits.uop.br_type, io.req.uop.br_type connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask connect rpq.io.enq.bits.uop.dis_col_sel, io.req.uop.dis_col_sel connect rpq.io.enq.bits.uop.iw_p3_bypass_hint, io.req.uop.iw_p3_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_bypass_hint, io.req.uop.iw_p2_bypass_hint connect rpq.io.enq.bits.uop.iw_p1_bypass_hint, io.req.uop.iw_p1_bypass_hint connect rpq.io.enq.bits.uop.iw_p2_speculative_child, io.req.uop.iw_p2_speculative_child connect rpq.io.enq.bits.uop.iw_p1_speculative_child, io.req.uop.iw_p1_speculative_child connect rpq.io.enq.bits.uop.iw_issued_partial_dgen, io.req.uop.iw_issued_partial_dgen connect rpq.io.enq.bits.uop.iw_issued_partial_agen, io.req.uop.iw_issued_partial_agen connect rpq.io.enq.bits.uop.iw_issued, io.req.uop.iw_issued connect rpq.io.enq.bits.uop.fu_code[0], io.req.uop.fu_code[0] connect rpq.io.enq.bits.uop.fu_code[1], io.req.uop.fu_code[1] connect rpq.io.enq.bits.uop.fu_code[2], io.req.uop.fu_code[2] connect rpq.io.enq.bits.uop.fu_code[3], io.req.uop.fu_code[3] connect rpq.io.enq.bits.uop.fu_code[4], io.req.uop.fu_code[4] connect rpq.io.enq.bits.uop.fu_code[5], io.req.uop.fu_code[5] connect rpq.io.enq.bits.uop.fu_code[6], io.req.uop.fu_code[6] connect rpq.io.enq.bits.uop.fu_code[7], io.req.uop.fu_code[7] connect rpq.io.enq.bits.uop.fu_code[8], io.req.uop.fu_code[8] connect rpq.io.enq.bits.uop.fu_code[9], io.req.uop.fu_code[9] connect rpq.io.enq.bits.uop.iq_type[0], io.req.uop.iq_type[0] connect rpq.io.enq.bits.uop.iq_type[1], io.req.uop.iq_type[1] connect rpq.io.enq.bits.uop.iq_type[2], io.req.uop.iq_type[2] connect rpq.io.enq.bits.uop.iq_type[3], io.req.uop.iq_type[3] connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst connect rpq.io.enq.bits.uop.inst, io.req.uop.inst connect rpq.io.deq.ready, UInt<1>(0h0) reg grantack : { valid : UInt<1>, bits : { sink : UInt<4>}}, clock reg refill_ctr : UInt<2>, clock reg commit_line : UInt<1>, clock reg grant_had_data : UInt<1>, clock reg finish_to_prefetch : UInt<1>, clock regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0) node _T_8 = neq(meta_hazard, UInt<1>(0h0)) when _T_8 : node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1)) node _meta_hazard_T_1 = tail(_meta_hazard_T, 1) connect meta_hazard, _meta_hazard_T_1 node _T_9 = and(io.meta_write.ready, io.meta_write.valid) when _T_9 : connect meta_hazard, UInt<1>(0h1) node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0)) node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0)) node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1)) node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2)) node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3)) node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2) node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3) node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4) node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4)) node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid) node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9) node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10) connect io.probe_rdy, _io_probe_rdy_T_11 node _io_idx_valid_T = neq(state, UInt<5>(0h0)) connect io.idx.valid, _io_idx_valid_T node _io_tag_valid_T = neq(state, UInt<5>(0h0)) connect io.tag.valid, _io_tag_valid_T node _io_way_valid_T = eq(state, UInt<5>(0h0)) node _io_way_valid_T_1 = eq(state, UInt<5>(0h11)) node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1) node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0)) connect io.way.valid, _io_way_valid_T_3 connect io.idx.bits, req_idx connect io.tag.bits, req_tag connect io.way.bits, req.way_en connect io.meta_write.valid, UInt<1>(0h0) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, coh_on_clear connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en connect io.meta_write.bits.tag, req_tag connect io.req_pri_rdy, UInt<1>(0h0) node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready) connect io.req_sec_rdy, _io_req_sec_rdy_T connect io.mem_acquire.valid, UInt<1>(0h0) node _io_mem_acquire_bits_T = cat(req_tag, req_idx) node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6) node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0)) node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1) node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3) node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000)) node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6) node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000))) node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8) node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000)) node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11) node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000))) node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13) node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10) node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15) node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17) node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6)) node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19) node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000)) node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21) node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000))) node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23) node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000)) node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26) node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000))) node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28) node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0))) node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30) node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31) node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18) node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32) wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6) connect io_mem_acquire_bits_a.param, grow_param connect io_mem_acquire_bits_a.size, UInt<3>(0h6) connect io_mem_acquire_bits_a.source, io.id connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1 node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0)) node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0) node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount) node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 3, 0) node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4)) node io_mem_acquire_bits_a_mask_sub_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 3, 3) node io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2) node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2) node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2) node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_2_2) node io_mem_acquire_bits_a_mask_sub_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_sub_bit) node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_3_2) node io_mem_acquire_bits_a_mask_sub_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1) node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1) node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2) node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T) node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2) node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1) node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2) node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2) node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2) node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3) node io_mem_acquire_bits_a_mask_sub_4_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_4 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_4_2) node io_mem_acquire_bits_a_mask_sub_4_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_4) node io_mem_acquire_bits_a_mask_sub_5_2 = and(io_mem_acquire_bits_a_mask_sub_sub_2_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_5 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_5_2) node io_mem_acquire_bits_a_mask_sub_5_1 = or(io_mem_acquire_bits_a_mask_sub_sub_2_1, _io_mem_acquire_bits_a_mask_sub_acc_T_5) node io_mem_acquire_bits_a_mask_sub_6_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_nbit) node _io_mem_acquire_bits_a_mask_sub_acc_T_6 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_6_2) node io_mem_acquire_bits_a_mask_sub_6_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_6) node io_mem_acquire_bits_a_mask_sub_7_2 = and(io_mem_acquire_bits_a_mask_sub_sub_3_2, io_mem_acquire_bits_a_mask_sub_bit) node _io_mem_acquire_bits_a_mask_sub_acc_T_7 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_7_2) node io_mem_acquire_bits_a_mask_sub_7_1 = or(io_mem_acquire_bits_a_mask_sub_sub_3_1, _io_mem_acquire_bits_a_mask_sub_acc_T_7) node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0) node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0) node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0)) node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq) node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T) node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1) node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1) node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2) node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2) node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3) node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3) node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4) node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4) node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5) node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5) node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6) node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6) node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7) node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7) node io_mem_acquire_bits_a_mask_eq_8 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_8 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_8) node io_mem_acquire_bits_a_mask_acc_8 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_8) node io_mem_acquire_bits_a_mask_eq_9 = and(io_mem_acquire_bits_a_mask_sub_4_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_9 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_9) node io_mem_acquire_bits_a_mask_acc_9 = or(io_mem_acquire_bits_a_mask_sub_4_1, _io_mem_acquire_bits_a_mask_acc_T_9) node io_mem_acquire_bits_a_mask_eq_10 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_10 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_10) node io_mem_acquire_bits_a_mask_acc_10 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_10) node io_mem_acquire_bits_a_mask_eq_11 = and(io_mem_acquire_bits_a_mask_sub_5_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_11 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_11) node io_mem_acquire_bits_a_mask_acc_11 = or(io_mem_acquire_bits_a_mask_sub_5_1, _io_mem_acquire_bits_a_mask_acc_T_11) node io_mem_acquire_bits_a_mask_eq_12 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_12 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_12) node io_mem_acquire_bits_a_mask_acc_12 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_12) node io_mem_acquire_bits_a_mask_eq_13 = and(io_mem_acquire_bits_a_mask_sub_6_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_13 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_13) node io_mem_acquire_bits_a_mask_acc_13 = or(io_mem_acquire_bits_a_mask_sub_6_1, _io_mem_acquire_bits_a_mask_acc_T_13) node io_mem_acquire_bits_a_mask_eq_14 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_nbit) node _io_mem_acquire_bits_a_mask_acc_T_14 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_14) node io_mem_acquire_bits_a_mask_acc_14 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_14) node io_mem_acquire_bits_a_mask_eq_15 = and(io_mem_acquire_bits_a_mask_sub_7_2, io_mem_acquire_bits_a_mask_bit) node _io_mem_acquire_bits_a_mask_acc_T_15 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_15) node io_mem_acquire_bits_a_mask_acc_15 = or(io_mem_acquire_bits_a_mask_sub_7_1, _io_mem_acquire_bits_a_mask_acc_T_15) node io_mem_acquire_bits_a_mask_lo_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc) node io_mem_acquire_bits_a_mask_lo_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2) node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_lo_lo_hi, io_mem_acquire_bits_a_mask_lo_lo_lo) node io_mem_acquire_bits_a_mask_lo_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4) node io_mem_acquire_bits_a_mask_lo_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6) node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_lo_hi_hi, io_mem_acquire_bits_a_mask_lo_hi_lo) node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo) node io_mem_acquire_bits_a_mask_hi_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_9, io_mem_acquire_bits_a_mask_acc_8) node io_mem_acquire_bits_a_mask_hi_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_11, io_mem_acquire_bits_a_mask_acc_10) node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_hi_lo_hi, io_mem_acquire_bits_a_mask_hi_lo_lo) node io_mem_acquire_bits_a_mask_hi_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_13, io_mem_acquire_bits_a_mask_acc_12) node io_mem_acquire_bits_a_mask_hi_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_15, io_mem_acquire_bits_a_mask_acc_14) node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_hi_hi_hi, io_mem_acquire_bits_a_mask_hi_hi_lo) node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo) node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo) connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T invalidate io_mem_acquire_bits_a.data connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0) connect io.mem_acquire.bits, io_mem_acquire_bits_a connect io.refill.valid, UInt<1>(0h0) node _io_refill_bits_addr_T = shl(refill_ctr, 4) node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T) connect io.refill.bits.addr, _io_refill_bits_addr_T_1 connect io.refill.bits.way_en, req.way_en node _io_refill_bits_wmask_T = not(UInt<2>(0h0)) connect io.refill.bits.wmask, _io_refill_bits_wmask_T connect io.refill.bits.data, io.lb_resp connect io.replay.valid, UInt<1>(0h0) connect io.replay.bits, rpq.io.deq.bits connect io.wb_req.valid, UInt<1>(0h0) connect io.wb_req.bits.tag, req.old_meta.tag connect io.wb_req.bits.idx, req_idx connect io.wb_req.bits.param, shrink_param connect io.wb_req.bits.way_en, req.way_en connect io.wb_req.bits.source, io.id connect io.wb_req.bits.voluntary, UInt<1>(0h1) connect io.resp.valid, UInt<1>(0h0) connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella connect io.resp.bits.data, rpq.io.deq.bits.data connect io.resp.bits.uop, rpq.io.deq.bits.uop connect io.commit_val, UInt<1>(0h0) connect io.commit_addr, req.addr connect io.commit_coh, coh_on_grant connect io.meta_read.valid, UInt<1>(0h0) connect io.meta_read.bits.idx, req_idx connect io.meta_read.bits.tag, req_tag connect io.meta_read.bits.way_en, req.way_en connect io.mem_finish.valid, UInt<1>(0h0) connect io.mem_finish.bits, grantack.bits connect io.lb_write.valid, UInt<1>(0h0) node _io_lb_write_bits_offset_T = shr(refill_address_inc, 4) connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T connect io.lb_write.bits.data, io.mem_grant.bits.data connect io.mem_grant.ready, UInt<1>(0h0) node _io_lb_read_offset_T = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.offset, _io_lb_read_offset_T node _T_10 = and(io.req_sec_val, io.req_sec_rdy) when _T_10 : connect req.uop.mem_cmd, dirtier_cmd when is_hit_again : connect new_coh, dirtier_coh node _T_11 = eq(state, UInt<5>(0h0)) when _T_11 : connect io.req_pri_rdy, UInt<1>(0h1) connect grant_had_data, UInt<1>(0h0) node _T_12 = and(io.req_pri_val, io.req_pri_rdy) when _T_12 : wire state_new_state : UInt connect state_new_state, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T = asUInt(reset) node _state_T_1 = eq(_state_T, UInt<1>(0h0)) when _state_T_1 : node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_2 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert connect req, io.req node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1) node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3) node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20) node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21) node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22) node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24) node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25) node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26) node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28) node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29) node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30) node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32) node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33) node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34) node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36) node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37) node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38) node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40) node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41) node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42) node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44) node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45) node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46) node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48) node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49) node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50) node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52) node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53) node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54) node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6) node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56) node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57) node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58) node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6) node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60) node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61) node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62) wire state_req_needs_wb_meta : { state : UInt<2>} connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3 connect req_needs_wb, state_req_needs_wb_r_1 when io.req.tag_match : node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1) node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3) node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6) node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7) node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8) node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13) node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14) node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15) node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16) node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20) node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21) node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24) node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26) node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29) node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30) node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31) node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36) node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37) node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38) node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39) node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43) node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44) node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46) node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48) node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49) node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state) node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3)) node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2)) node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1)) node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3)) node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2)) node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3)) node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2)) node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0)) node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1)) node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0)) node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1)) node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0)) node _state_r_T_25 = eq(_state_r_T_24, _state_r_T) node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_28 = eq(_state_r_T_22, _state_r_T) node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26) node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27) node _state_r_T_31 = eq(_state_r_T_20, _state_r_T) node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29) node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30) node _state_r_T_34 = eq(_state_r_T_18, _state_r_T) node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32) node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33) node _state_r_T_37 = eq(_state_r_T_16, _state_r_T) node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35) node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36) node _state_r_T_40 = eq(_state_r_T_14, _state_r_T) node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38) node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39) node _state_r_T_43 = eq(_state_r_T_12, _state_r_T) node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41) node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42) node _state_r_T_46 = eq(_state_r_T_10, _state_r_T) node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44) node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45) node _state_r_T_49 = eq(_state_r_T_8, _state_r_T) node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47) node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48) node _state_r_T_52 = eq(_state_r_T_6, _state_r_T) node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50) node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51) node _state_r_T_55 = eq(_state_r_T_4, _state_r_T) node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53) node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54) node _state_r_T_58 = eq(_state_r_T_2, _state_r_T) node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56) node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57) wire state_coh_on_hit : { state : UInt<2>} connect state_coh_on_hit.state, state_r_2 when state_is_hit : node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_5 = or(_state_T_3, _state_T_4) node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_7 = or(_state_T_5, _state_T_6) node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_12 = or(_state_T_8, _state_T_9) node _state_T_13 = or(_state_T_12, _state_T_10) node _state_T_14 = or(_state_T_13, _state_T_11) node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_20 = or(_state_T_15, _state_T_16) node _state_T_21 = or(_state_T_20, _state_T_17) node _state_T_22 = or(_state_T_21, _state_T_18) node _state_T_23 = or(_state_T_22, _state_T_19) node _state_T_24 = or(_state_T_14, _state_T_23) node _state_T_25 = or(_state_T_7, _state_T_24) node _state_T_26 = asUInt(reset) node _state_T_27 = eq(_state_T_26, UInt<1>(0h0)) when _state_T_27 : node _state_T_28 = eq(_state_T_25, UInt<1>(0h0)) when _state_T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1 assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1 connect new_coh, state_coh_on_hit connect state_new_state, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state, UInt<5>(0h1) else : wire state_new_coh_meta : { state : UInt<2>} connect state_new_coh_meta.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta connect state_new_state, UInt<5>(0h1) connect state, state_new_state else : node _T_13 = eq(state, UInt<5>(0h1)) when _T_13 : connect io.mem_acquire.valid, UInt<1>(0h1) node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid) when _T_14 : connect state, UInt<5>(0h2) else : node _T_15 = eq(state, UInt<5>(0h2)) when _T_15 : connect io.mem_grant.ready, UInt<1>(0h1) node opdata = bits(io.mem_grant.bits.opcode, 0, 0) when opdata : connect io.lb_write.valid, io.mem_grant.valid else : connect io.mem_grant.ready, UInt<1>(0h1) node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid) when _T_16 : node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0) connect grant_had_data, grant_had_data_opdata when refill_done : node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2) node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1) node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0)) node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2) connect grantack.valid, _grantack_valid_T_3 wire grantack_bits_e : { sink : UInt<4>} connect grantack_bits_e.sink, io.mem_grant.bits.sink connect grantack.bits, grantack_bits_e node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc)) connect state, _state_T_29 node _T_17 = eq(grant_had_data, UInt<1>(0h0)) node _T_18 = and(_T_17, req_needs_wb) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:261 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 connect commit_line, UInt<1>(0h0) connect new_coh, coh_on_grant else : node _T_23 = eq(state, UInt<5>(0h3)) when _T_23 : node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0)) node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10)) node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1) node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2) node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3) node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8) node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9) node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10) node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15) node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16) node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17) node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18) node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22) node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23) node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26) node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28) node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31) node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32) node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33) node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38) node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39) node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40) node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41) node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45) node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46) node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0)) node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48) node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node drain_load = and(_drain_load_T_49, _drain_load_T_50) node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node rp_addr_hi = cat(req_tag, req_idx) node rp_addr = cat(rp_addr_hi, _rp_addr_T) node word_idx = bits(rp_addr, 3, 3) node _data_word_T = cat(word_idx, UInt<6>(0h0)) node data_word = dshr(io.lb_resp, _data_word_T) node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0) node hi = cat(req_tag, req_idx) node _T_25 = cat(hi, _T_24) wire size : UInt<2> connect size, rpq.io.deq.bits.uop.mem_size node _rpq_io_deq_ready_T = and(io.resp.ready, drain_load) connect rpq.io.deq.ready, _rpq_io_deq_ready_T node _io_lb_read_offset_T_1 = shr(rpq.io.deq.bits.addr, 4) connect io.lb_read.offset, _io_lb_read_offset_T_1 node _io_resp_valid_T = and(rpq.io.deq.valid, drain_load) connect io.resp.valid, _io_resp_valid_T node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2) node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32) node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0) node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2) node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted) node _io_resp_bits_data_T = eq(size, UInt<2>(0h2)) node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero) node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31) node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2) node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_resp_bits_data_T_5 = bits(data_word, 63, 32) node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5) node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed) node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1) node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16) node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0) node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5) node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1) node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1)) node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1) node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15) node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10) node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16) node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13) node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1) node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0) node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8) node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0) node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8) node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2) node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0)) node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2) node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7) node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18) node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8) node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21) node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2) connect io.resp.bits.data, _io_resp_bits_data_T_23 connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid) when _T_26 : connect commit_line, UInt<1>(0h1) else : node _T_27 = eq(commit_line, UInt<1>(0h0)) node _T_28 = and(rpq.io.empty, _T_27) when _T_28 : node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_31 = eq(drain_load, UInt<1>(0h0)) node _T_32 = and(rpq.io.deq.valid, _T_31) node _T_33 = or(rpq.io.empty, _T_32) when _T_33 : connect io.commit_val, UInt<1>(0h1) connect state, UInt<5>(0h4) else : node _T_34 = eq(state, UInt<5>(0h4)) when _T_34 : node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0)) node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1) node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 11, 6) node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx) node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4) connect io.meta_read.valid, _io_meta_read_valid_T_5 node _T_35 = and(io.meta_read.ready, io.meta_read.valid) when _T_35 : connect state, UInt<5>(0h5) else : node _T_36 = eq(state, UInt<5>(0h5)) when _T_36 : connect state, UInt<5>(0h6) else : node _T_37 = eq(state, UInt<5>(0h6)) when _T_37 : node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10)) node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1) node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3) node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state) node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6) node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0)) node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0)) node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6) node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20) node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21) node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22) node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6) node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24) node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25) node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26) node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6) node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28) node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29) node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30) node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6) node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32) node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33) node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34) node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6) node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36) node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37) node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38) node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6) node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40) node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41) node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42) node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6) node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44) node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45) node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46) node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6) node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48) node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49) node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50) node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6) node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52) node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53) node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54) node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6) node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56) node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57) node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58) node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6) node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60) node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61) node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62) wire needs_wb_meta : { state : UInt<2>} connect needs_wb_meta.state, needs_wb_r_3 node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0)) node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb)) node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31) connect state, _state_T_32 else : node _T_38 = eq(state, UInt<5>(0h7)) when _T_38 : connect io.meta_write.valid, UInt<1>(0h1) node _T_39 = and(io.meta_write.ready, io.meta_write.valid) when _T_39 : connect state, UInt<5>(0h9) else : node _T_40 = eq(state, UInt<5>(0h9)) when _T_40 : connect io.wb_req.valid, UInt<1>(0h1) node _T_41 = and(io.wb_req.ready, io.wb_req.valid) when _T_41 : connect state, UInt<5>(0ha) else : node _T_42 = eq(state, UInt<5>(0ha)) when _T_42 : when io.wb_resp : connect state, UInt<5>(0hb) else : node _T_43 = eq(state, UInt<5>(0hb)) when _T_43 : connect io.lb_read.offset, refill_ctr connect io.refill.valid, UInt<1>(0h1) node _T_44 = and(io.refill.ready, io.refill.valid) when _T_44 : node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1)) node _refill_ctr_T_1 = tail(_refill_ctr_T, 1) connect refill_ctr, _refill_ctr_T_1 node _T_45 = eq(refill_ctr, UInt<2>(0h3)) when _T_45 : connect state, UInt<5>(0hc) else : node _T_46 = eq(state, UInt<5>(0hc)) when _T_46 : connect io.replay.bits, rpq.io.deq.bits connect io.replay.valid, rpq.io.deq.valid connect rpq.io.deq.ready, io.replay.ready connect io.replay.bits.way_en, req.way_en node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0) node io_replay_bits_addr_hi = cat(req_tag, req_idx) node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T) connect io.replay.bits.addr, _io_replay_bits_addr_T_1 node _T_47 = and(io.replay.ready, io.replay.valid) node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _T_50 = or(_T_48, _T_49) node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _T_52 = or(_T_50, _T_51) node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _T_57 = or(_T_53, _T_54) node _T_58 = or(_T_57, _T_55) node _T_59 = or(_T_58, _T_56) node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _T_65 = or(_T_60, _T_61) node _T_66 = or(_T_65, _T_62) node _T_67 = or(_T_66, _T_63) node _T_68 = or(_T_67, _T_64) node _T_69 = or(_T_59, _T_68) node _T_70 = or(_T_52, _T_69) node _T_71 = and(_T_47, _T_70) when _T_71 : node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1) node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3) node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6) node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7) node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8) node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13) node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14) node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15) node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16) node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20) node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21) node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24) node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26) node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29) node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30) node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31) node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36) node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37) node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38) node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39) node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43) node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44) node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46) node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48) node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49) node _r_T_64 = cat(r_c, new_coh.state) node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_66 = cat(_r_T_65, UInt<2>(0h3)) node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_68 = cat(_r_T_67, UInt<2>(0h2)) node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_70 = cat(_r_T_69, UInt<2>(0h1)) node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_72 = cat(_r_T_71, UInt<2>(0h3)) node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_74 = cat(_r_T_73, UInt<2>(0h2)) node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_76 = cat(_r_T_75, UInt<2>(0h3)) node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_78 = cat(_r_T_77, UInt<2>(0h2)) node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_80 = cat(_r_T_79, UInt<2>(0h0)) node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_82 = cat(_r_T_81, UInt<2>(0h1)) node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_84 = cat(_r_T_83, UInt<2>(0h0)) node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_86 = cat(_r_T_85, UInt<2>(0h1)) node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_88 = cat(_r_T_87, UInt<2>(0h0)) node _r_T_89 = eq(_r_T_88, _r_T_64) node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_92 = eq(_r_T_86, _r_T_64) node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90) node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91) node _r_T_95 = eq(_r_T_84, _r_T_64) node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93) node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94) node _r_T_98 = eq(_r_T_82, _r_T_64) node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96) node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97) node _r_T_101 = eq(_r_T_80, _r_T_64) node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99) node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100) node _r_T_104 = eq(_r_T_78, _r_T_64) node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102) node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103) node _r_T_107 = eq(_r_T_76, _r_T_64) node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105) node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106) node _r_T_110 = eq(_r_T_74, _r_T_64) node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108) node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109) node _r_T_113 = eq(_r_T_72, _r_T_64) node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111) node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112) node _r_T_116 = eq(_r_T_70, _r_T_64) node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114) node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115) node _r_T_119 = eq(_r_T_68, _r_T_64) node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117) node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118) node _r_T_122 = eq(_r_T_66, _r_T_64) node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120) node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121) wire coh_on_hit : { state : UInt<2>} connect coh_on_hit.state, r_2_1 node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(is_hit, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:345 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2 assert(clock, is_hit, UInt<1>(0h1), "") : assert_2 connect new_coh, coh_on_hit node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0)) node _T_76 = and(rpq.io.empty, _T_75) when _T_76 : connect state, UInt<5>(0hd) else : node _T_77 = eq(state, UInt<5>(0hd)) when _T_77 : connect io.meta_write.valid, UInt<1>(0h1) connect io.meta_write.bits.idx, req_idx connect io.meta_write.bits.data.coh, new_coh connect io.meta_write.bits.data.tag, req_tag connect io.meta_write.bits.way_en, req.way_en node _T_78 = and(io.meta_write.ready, io.meta_write.valid) when _T_78 : connect state, UInt<5>(0he) connect finish_to_prefetch, UInt<1>(0h0) else : node _T_79 = eq(state, UInt<5>(0he)) when _T_79 : connect io.mem_finish.valid, grantack.valid node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid) node _T_81 = eq(grantack.valid, UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) when _T_82 : connect grantack.valid, UInt<1>(0h0) connect state, UInt<5>(0hf) else : node _T_83 = eq(state, UInt<5>(0hf)) when _T_83 : node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0)) connect state, _state_T_33 else : node _T_84 = eq(state, UInt<5>(0h11)) when _T_84 : connect io.req_pri_rdy, UInt<1>(0h1) node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0)) node _T_86 = and(io.req_sec_val, _T_85) node _T_87 = or(_T_86, io.clear_prefetch) when _T_87 : connect state, UInt<5>(0h0) else : node _T_88 = and(io.req_sec_val, io.req_sec_rdy) when _T_88 : node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51) node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53) node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56) node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57) node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58) node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63) node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64) node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65) node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66) node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70) node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71) node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74) node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76) node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79) node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80) node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81) node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86) node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87) node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88) node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89) node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93) node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94) node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96) node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98) node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99) node _r_T_123 = cat(r_c_1, new_coh.state) node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_125 = cat(_r_T_124, UInt<2>(0h3)) node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_127 = cat(_r_T_126, UInt<2>(0h2)) node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_129 = cat(_r_T_128, UInt<2>(0h1)) node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_131 = cat(_r_T_130, UInt<2>(0h3)) node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_133 = cat(_r_T_132, UInt<2>(0h2)) node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_135 = cat(_r_T_134, UInt<2>(0h3)) node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_137 = cat(_r_T_136, UInt<2>(0h2)) node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _r_T_139 = cat(_r_T_138, UInt<2>(0h0)) node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_141 = cat(_r_T_140, UInt<2>(0h1)) node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _r_T_143 = cat(_r_T_142, UInt<2>(0h0)) node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_145 = cat(_r_T_144, UInt<2>(0h1)) node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _r_T_147 = cat(_r_T_146, UInt<2>(0h0)) node _r_T_148 = eq(_r_T_147, _r_T_123) node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0)) node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0)) node _r_T_151 = eq(_r_T_145, _r_T_123) node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149) node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150) node _r_T_154 = eq(_r_T_143, _r_T_123) node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152) node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153) node _r_T_157 = eq(_r_T_141, _r_T_123) node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155) node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156) node _r_T_160 = eq(_r_T_139, _r_T_123) node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158) node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159) node _r_T_163 = eq(_r_T_137, _r_T_123) node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161) node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162) node _r_T_166 = eq(_r_T_135, _r_T_123) node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164) node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165) node _r_T_169 = eq(_r_T_133, _r_T_123) node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167) node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168) node _r_T_172 = eq(_r_T_131, _r_T_123) node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170) node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171) node _r_T_175 = eq(_r_T_129, _r_T_123) node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173) node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174) node _r_T_178 = eq(_r_T_127, _r_T_123) node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176) node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177) node _r_T_181 = eq(_r_T_125, _r_T_123) node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179) node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180) wire coh_on_hit_1 : { state : UInt<2>} connect coh_on_hit_1.state, r_2_2 when is_hit_1 : connect new_coh, coh_on_hit_1 connect state, UInt<5>(0h4) else : wire new_coh_meta_1 : { state : UInt<2>} connect new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, new_coh_meta_1 connect state, UInt<5>(0h1) else : node _T_89 = and(io.req_pri_val, io.req_pri_rdy) when _T_89 : connect grant_had_data, UInt<1>(0h0) wire state_new_state_1 : UInt connect state_new_state_1, state connect grantack.valid, UInt<1>(0h0) connect refill_ctr, UInt<1>(0h0) node _state_T_34 = asUInt(reset) node _state_T_35 = eq(_state_T_34, UInt<1>(0h0)) when _state_T_35 : node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0)) when _state_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:213 assert(rpq.io.enq.ready)\n") : state_printf_2 assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2 connect req, io.req node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10)) node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10)) node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65) node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10)) node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67) node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state) node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3)) node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2)) node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1)) node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0)) node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3)) node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2)) node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1)) node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0)) node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3)) node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2)) node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1)) node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0)) node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0)) node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0)) node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84) node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85) node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86) node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88) node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89) node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90) node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92) node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93) node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94) node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96) node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97) node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98) node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100) node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101) node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102) node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104) node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105) node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106) node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108) node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109) node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110) node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112) node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113) node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114) node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116) node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117) node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118) node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70) node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120) node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121) node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122) node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70) node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124) node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125) node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126) wire state_req_needs_wb_meta_1 : { state : UInt<2>} connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1 connect req_needs_wb, state_req_needs_wb_r_1_1 when io.req.tag_match : node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51) node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53) node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56) node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57) node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58) node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63) node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64) node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65) node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66) node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70) node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71) node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74) node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76) node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79) node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80) node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81) node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86) node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87) node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88) node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89) node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93) node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94) node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3)) node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96) node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6)) node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98) node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99) node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state) node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3)) node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2)) node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1)) node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3)) node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2)) node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3)) node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2)) node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0)) node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1)) node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1)) node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0)) node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1)) node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1)) node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0)) node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59) node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0)) node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0)) node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59) node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85) node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86) node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59) node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88) node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89) node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59) node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91) node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92) node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59) node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94) node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95) node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59) node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97) node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98) node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59) node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100) node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101) node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59) node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103) node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104) node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59) node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106) node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107) node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59) node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109) node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110) node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59) node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112) node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113) node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59) node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115) node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116) wire state_coh_on_hit_1 : { state : UInt<2>} connect state_coh_on_hit_1.state, state_r_2_1 when state_is_hit_1 : node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1)) node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11)) node _state_T_39 = or(_state_T_37, _state_T_38) node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7)) node _state_T_41 = or(_state_T_39, _state_T_40) node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4)) node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9)) node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha)) node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb)) node _state_T_46 = or(_state_T_42, _state_T_43) node _state_T_47 = or(_state_T_46, _state_T_44) node _state_T_48 = or(_state_T_47, _state_T_45) node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8)) node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc)) node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd)) node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he)) node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf)) node _state_T_54 = or(_state_T_49, _state_T_50) node _state_T_55 = or(_state_T_54, _state_T_51) node _state_T_56 = or(_state_T_55, _state_T_52) node _state_T_57 = or(_state_T_56, _state_T_53) node _state_T_58 = or(_state_T_48, _state_T_57) node _state_T_59 = or(_state_T_41, _state_T_58) node _state_T_60 = asUInt(reset) node _state_T_61 = eq(_state_T_60, UInt<1>(0h0)) when _state_T_61 : node _state_T_62 = eq(_state_T_59, UInt<1>(0h0)) when _state_T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:220 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3 assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3 connect new_coh, state_coh_on_hit_1 connect state_new_state_1, UInt<5>(0hc) else : connect new_coh, io.req.old_meta.coh connect state_new_state_1, UInt<5>(0h1) else : wire state_new_coh_meta_1 : { state : UInt<2>} connect state_new_coh_meta_1.state, UInt<2>(0h0) connect new_coh, state_new_coh_meta_1 connect state_new_state_1, UInt<5>(0h1) connect state, state_new_state_1

module BoomMSHR_3( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:39:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:39:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:39:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:39:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:39:14] input io_brupdate_b2_taken, // @[mshrs.scala:39:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:39:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:39:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:39:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:39:14] input io_exception, // @[mshrs.scala:39:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [39:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input io_req_uop_iq_type_0, // @[mshrs.scala:39:14] input io_req_uop_iq_type_1, // @[mshrs.scala:39:14] input io_req_uop_iq_type_2, // @[mshrs.scala:39:14] input io_req_uop_iq_type_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_0, // @[mshrs.scala:39:14] input io_req_uop_fu_code_1, // @[mshrs.scala:39:14] input io_req_uop_fu_code_2, // @[mshrs.scala:39:14] input io_req_uop_fu_code_3, // @[mshrs.scala:39:14] input io_req_uop_fu_code_4, // @[mshrs.scala:39:14] input io_req_uop_fu_code_5, // @[mshrs.scala:39:14] input io_req_uop_fu_code_6, // @[mshrs.scala:39:14] input io_req_uop_fu_code_7, // @[mshrs.scala:39:14] input io_req_uop_fu_code_8, // @[mshrs.scala:39:14] input io_req_uop_fu_code_9, // @[mshrs.scala:39:14] input io_req_uop_iw_issued, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] input io_req_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] input io_req_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] input [2:0] io_req_uop_dis_col_sel, // @[mshrs.scala:39:14] input [15:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_type, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_sfence, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_is_eret, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_rocc, // @[mshrs.scala:39:14] input io_req_uop_is_mov, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input io_req_uop_imm_rename, // @[mshrs.scala:39:14] input [2:0] io_req_uop_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_pimm, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [1:0] io_req_uop_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_op2_sel, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_div, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] input io_req_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] input [6:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [4:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input [2:0] io_req_uop_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fcn_dw, // @[mshrs.scala:39:14] input [4:0] io_req_uop_fcn_op, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input [2:0] io_req_uop_fp_rm, // @[mshrs.scala:39:14] input [1:0] io_req_uop_fp_typ, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [39:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [19:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [7:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [5:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [7:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [27:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [39:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] output [1:0] io_lb_read_offset, // @[mshrs.scala:39:14] input [127:0] io_lb_resp, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [1:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [127:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:39:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:39:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :234:30, :241:40, :246:41, :266:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iq_type_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_0; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_4; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_5; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_6; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_7; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_8; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fu_code_9; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_dis_col_sel; // @[mshrs.scala:128:19] wire [15:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_type; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_eret; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rocc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_mov; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_imm_rename; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_pimm; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_op2_sel; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wen; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_toint; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_fma; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_div; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_ctrl_vec; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fcn_dw; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_fcn_op; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_fp_rm; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_fp_typ; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [39:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_data; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire [7:0] _rpq_io_deq_bits_way_en; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:36:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:36:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:36:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:36:7] wire io_exception_0 = io_exception; // @[mshrs.scala:36:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [39:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_0_0 = io_req_uop_iq_type_0; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_1_0 = io_req_uop_iq_type_1; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_2_0 = io_req_uop_iq_type_2; // @[mshrs.scala:36:7] wire io_req_uop_iq_type_3_0 = io_req_uop_iq_type_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_0_0 = io_req_uop_fu_code_0; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_1_0 = io_req_uop_fu_code_1; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_2_0 = io_req_uop_fu_code_2; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_3_0 = io_req_uop_fu_code_3; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_4_0 = io_req_uop_fu_code_4; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_5_0 = io_req_uop_fu_code_5; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_6_0 = io_req_uop_fu_code_6; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_7_0 = io_req_uop_fu_code_7; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_8_0 = io_req_uop_fu_code_8; // @[mshrs.scala:36:7] wire io_req_uop_fu_code_9_0 = io_req_uop_fu_code_9; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_0 = io_req_uop_iw_issued; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_agen_0 = io_req_uop_iw_issued_partial_agen; // @[mshrs.scala:36:7] wire io_req_uop_iw_issued_partial_dgen_0 = io_req_uop_iw_issued_partial_dgen; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iw_p1_speculative_child_0 = io_req_uop_iw_p1_speculative_child; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iw_p2_speculative_child_0 = io_req_uop_iw_p2_speculative_child; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_bypass_hint_0 = io_req_uop_iw_p1_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_bypass_hint_0 = io_req_uop_iw_p2_bypass_hint; // @[mshrs.scala:36:7] wire io_req_uop_iw_p3_bypass_hint_0 = io_req_uop_iw_p3_bypass_hint; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_dis_col_sel_0 = io_req_uop_dis_col_sel; // @[mshrs.scala:36:7] wire [15:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_type_0 = io_req_uop_br_type; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_sfence_0 = io_req_uop_is_sfence; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_is_eret_0 = io_req_uop_is_eret; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_rocc_0 = io_req_uop_is_rocc; // @[mshrs.scala:36:7] wire io_req_uop_is_mov_0 = io_req_uop_is_mov; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire io_req_uop_imm_rename_0 = io_req_uop_imm_rename; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_imm_sel_0 = io_req_uop_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_pimm_0 = io_req_uop_pimm; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_op1_sel_0 = io_req_uop_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_op2_sel_0 = io_req_uop_op2_sel; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ldst_0 = io_req_uop_fp_ctrl_ldst; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wen_0 = io_req_uop_fp_ctrl_wen; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren1_0 = io_req_uop_fp_ctrl_ren1; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren2_0 = io_req_uop_fp_ctrl_ren2; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_ren3_0 = io_req_uop_fp_ctrl_ren3; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap12_0 = io_req_uop_fp_ctrl_swap12; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_swap23_0 = io_req_uop_fp_ctrl_swap23; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagIn_0 = io_req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_ctrl_typeTagOut_0 = io_req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fromint_0 = io_req_uop_fp_ctrl_fromint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_toint_0 = io_req_uop_fp_ctrl_toint; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fastpipe_0 = io_req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_fma_0 = io_req_uop_fp_ctrl_fma; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_div_0 = io_req_uop_fp_ctrl_div; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_sqrt_0 = io_req_uop_fp_ctrl_sqrt; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_wflags_0 = io_req_uop_fp_ctrl_wflags; // @[mshrs.scala:36:7] wire io_req_uop_fp_ctrl_vec_0 = io_req_uop_fp_ctrl_vec; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_csr_cmd_0 = io_req_uop_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fcn_dw_0 = io_req_uop_fcn_dw; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_fcn_op_0 = io_req_uop_fcn_op; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_fp_rm_0 = io_req_uop_fp_rm; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_fp_typ_0 = io_req_uop_fp_typ; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [39:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [7:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire [127:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:213:11] wire _state_T_26 = reset; // @[mshrs.scala:220:15] wire _state_T_34 = reset; // @[mshrs.scala:213:11] wire _state_T_60 = reset; // @[mshrs.scala:220:15] wire [1:0] io_id = 2'h3; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:36:7] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _io_refill_bits_wmask_T = 2'h3; // @[mshrs.scala:174:28] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [2:0] io_mem_acquire_bits_source = 3'h3; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_source = 3'h3; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_source = 3'h3; // @[Edges.scala:346:17] wire [15:0] io_mem_acquire_bits_mask = 16'hFFFF; // @[mshrs.scala:36:7] wire [15:0] io_mem_acquire_bits_a_mask = 16'hFFFF; // @[Edges.scala:346:17] wire [15:0] _io_mem_acquire_bits_a_mask_T = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_mem_acquire_bits_data = 128'h0; // @[mshrs.scala:36:7] wire [127:0] io_mem_acquire_bits_a_data = 128'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] io_mem_acquire_bits_a_mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [7:0] io_mem_acquire_bits_a_mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] io_mem_acquire_bits_a_mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:163:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [5:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [27:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [3:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [127:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [127:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [27:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_read_offset_0; // @[mshrs.scala:36:7] wire [1:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:36:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [39:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [39:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg req_uop_iq_type_0; // @[mshrs.scala:109:20] reg req_uop_iq_type_1; // @[mshrs.scala:109:20] reg req_uop_iq_type_2; // @[mshrs.scala:109:20] reg req_uop_iq_type_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_0; // @[mshrs.scala:109:20] reg req_uop_fu_code_1; // @[mshrs.scala:109:20] reg req_uop_fu_code_2; // @[mshrs.scala:109:20] reg req_uop_fu_code_3; // @[mshrs.scala:109:20] reg req_uop_fu_code_4; // @[mshrs.scala:109:20] reg req_uop_fu_code_5; // @[mshrs.scala:109:20] reg req_uop_fu_code_6; // @[mshrs.scala:109:20] reg req_uop_fu_code_7; // @[mshrs.scala:109:20] reg req_uop_fu_code_8; // @[mshrs.scala:109:20] reg req_uop_fu_code_9; // @[mshrs.scala:109:20] reg req_uop_iw_issued; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_agen; // @[mshrs.scala:109:20] reg req_uop_iw_issued_partial_dgen; // @[mshrs.scala:109:20] reg [2:0] req_uop_iw_p1_speculative_child; // @[mshrs.scala:109:20] reg [2:0] req_uop_iw_p2_speculative_child; // @[mshrs.scala:109:20] reg req_uop_iw_p1_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p2_bypass_hint; // @[mshrs.scala:109:20] reg req_uop_iw_p3_bypass_hint; // @[mshrs.scala:109:20] reg [2:0] req_uop_dis_col_sel; // @[mshrs.scala:109:20] reg [15:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_type; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_sfence; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_is_eret; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_rocc; // @[mshrs.scala:109:20] reg req_uop_is_mov; // @[mshrs.scala:109:20] reg [4:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg req_uop_imm_rename; // @[mshrs.scala:109:20] reg [2:0] req_uop_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_pimm; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [1:0] req_uop_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_op2_sel; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ldst; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wen; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren1; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren2; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_ren3; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap12; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_swap23; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fromint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_toint; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fastpipe; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_fma; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_div; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_sqrt; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_wflags; // @[mshrs.scala:109:20] reg req_uop_fp_ctrl_vec; // @[mshrs.scala:109:20] reg [6:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [4:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [4:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg [2:0] req_uop_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fcn_dw; // @[mshrs.scala:109:20] reg [4:0] req_uop_fcn_op; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg [2:0] req_uop_fp_rm; // @[mshrs.scala:109:20] reg [1:0] req_uop_fp_typ; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [2:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [39:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [19:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [7:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[11:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[39:12]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[mshrs.scala:109:20, :112:34] wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] r_beats1_decode = _r_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [7:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] r_counter; // @[Edges.scala:229:27] wire [8:0] _r_counter1_T = {1'h0, r_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] r_counter1 = _r_counter1_T[7:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [7:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 4'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [3:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [1:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = |state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = |state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign io_meta_write_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_write_bits_data_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign io_meta_read_bits_tag_0 = req_tag[19:0]; // @[mshrs.scala:36:7, :111:26, :159:31] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :163:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :163:37] wire [33:0] _GEN_27 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :168:26] wire [33:0] _io_mem_acquire_bits_T; // @[mshrs.scala:168:26] assign _io_mem_acquire_bits_T = _GEN_27; // @[mshrs.scala:168:26] wire [33:0] rp_addr_hi; // @[mshrs.scala:271:22] assign rp_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :271:22] wire [33:0] hi; // @[mshrs.scala:276:10] assign hi = _GEN_27; // @[mshrs.scala:168:26, :276:10] wire [33:0] io_replay_bits_addr_hi; // @[mshrs.scala:341:31] assign io_replay_bits_addr_hi = _GEN_27; // @[mshrs.scala:168:26, :341:31] wire [39:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:168:{26,45}] wire [39:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[39:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[39:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [39:0] _io_mem_acquire_bits_legal_T_26 = {_io_mem_acquire_bits_T_1[39:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42] wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_sub_bit = _io_mem_acquire_bits_T_1[3]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_3 = io_mem_acquire_bits_a_mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_4_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_5_2 = io_mem_acquire_bits_a_mask_sub_sub_2_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_6_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_7_2 = io_mem_acquire_bits_a_mask_sub_sub_3_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_8 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_8 = io_mem_acquire_bits_a_mask_eq_8; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_9 = io_mem_acquire_bits_a_mask_sub_4_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_9 = io_mem_acquire_bits_a_mask_eq_9; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_10 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_10 = io_mem_acquire_bits_a_mask_eq_10; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_11 = io_mem_acquire_bits_a_mask_sub_5_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_11 = io_mem_acquire_bits_a_mask_eq_11; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_12 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_12 = io_mem_acquire_bits_a_mask_eq_12; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_13 = io_mem_acquire_bits_a_mask_sub_6_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_13 = io_mem_acquire_bits_a_mask_eq_13; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_14 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_14 = io_mem_acquire_bits_a_mask_eq_14; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_15 = io_mem_acquire_bits_a_mask_sub_7_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_15 = io_mem_acquire_bits_a_mask_eq_15; // @[Misc.scala:214:27, :215:38] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 4'h0}; // @[mshrs.scala:139:24, :172:57] wire [39:0] _io_refill_bits_addr_T_1 = {req_block_addr[39:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :172:{43,57}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[11:0]; // @[mshrs.scala:36:7, :172:{25,43}] wire [7:0] _io_lb_write_bits_offset_T = refill_address_inc[11:4]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[1:0]; // @[mshrs.scala:36:7, :197:{27,49}] wire [35:0] _io_lb_read_offset_T = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45] wire [35:0] _io_lb_read_offset_T_1 = _rpq_io_deq_bits_addr[39:4]; // @[mshrs.scala:128:19, :200:45, :282:47] wire [4:0] state_new_state; // @[mshrs.scala:210:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:213:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire [3:0] _GEN_28 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_28; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_28; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:220:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :260:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :269:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:267:59, :268:60, :269:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :271:61] wire [39:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:271:{22,61}] wire word_idx = rp_addr[3]; // @[mshrs.scala:271:22, :272:56] wire [6:0] _data_word_T = {word_idx, 6'h0}; // @[mshrs.scala:272:56, :274:32] wire [127:0] data_word = io_lb_resp_0 >> _data_word_T; // @[mshrs.scala:36:7, :274:{26,32}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & drain_load; // @[mshrs.scala:36:7, :268:60, :280:40] wire _io_resp_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :268:60, :284:43] wire _GEN_41 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_41 & _io_probe_rdy_T_4 & _io_resp_valid_T; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _GEN_41 | ~_io_probe_rdy_T_4 ? _rpq_io_deq_bits_data : _io_resp_bits_data_T_23; // @[package.scala:16:47] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :290:{31,34}] wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :268:60, :296:{31,52,55}] assign io_commit_val_0 = ~_GEN_41 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :303:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :303:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:303:{27,50,53}] wire [5:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[11:6]; // @[mshrs.scala:36:7, :303:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :303:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:303:{50,69,120}] assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :307:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :309:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :311:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:311:{17,18}, :312:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :313:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :319:22] assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :324:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :328:22] wire _GEN_42 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :200:21, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:41] assign io_lb_read_offset_0 = _GEN_41 ? _io_lb_read_offset_T[1:0] : _io_probe_rdy_T_4 ? _io_lb_read_offset_T_1[1:0] : _GEN_42 | ~_T_43 ? _io_lb_read_offset_T[1:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_43 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_42; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(|state) | _GEN_43) & _T_43; // @[package.scala:16:47] wire [2:0] _refill_ctr_T = {1'h0, refill_ctr} + 3'h1; // @[mshrs.scala:139:24, :333:32] wire [1:0] _refill_ctr_T_1 = _refill_ctr_T[1:0]; // @[mshrs.scala:333:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :338:22] wire _GEN_44 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :176:26, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:39] wire _GEN_45 = _io_probe_rdy_T_4 | _GEN_44; // @[package.scala:16:47] wire _GEN_46 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~_GEN_46 & _T_46 & _rpq_io_deq_valid; // @[mshrs.scala:36:7, :128:19, :176:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}, :339:15] assign rpq_io_deq_ready = ~_GEN_41 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T : ~_GEN_44 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire _GEN_47 = _GEN_46 | ~_T_46; // @[mshrs.scala:176:26, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:{22,39}] assign io_replay_bits_way_en_0 = _GEN_47 ? _rpq_io_deq_bits_way_en : req_way_en; // @[mshrs.scala:36:7, :109:20, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :341:70] wire [39:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:341:{31,70}] assign io_replay_bits_addr_0 = _GEN_47 ? _rpq_io_deq_bits_addr : _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :128:19, :177:26, :234:30, :241:40, :246:41, :266:45, :302:39, :307:41, :309:41, :313:40, :319:36, :324:37, :328:41, :338:39, :341:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_48 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :319:{22,36}, :324:{22,37}, :328:{22,41}, :338:{22,39}, :351:44] assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_48 & _sec_rdy_T_4); // @[package.scala:16:47] wire _GEN_49 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _GEN_48; // @[mshrs.scala:148:129, :156:26, :158:31, :302:39, :307:{22,41}, :309:{22,41}, :313:{22,40}, :319:36, :324:37, :328:41, :338:39, :351:44] assign io_meta_write_bits_data_coh_state_0 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_49 | ~_sec_rdy_T_4 ? coh_on_clear_state : new_coh_state; // @[package.scala:16:47] wire _GEN_50 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_50) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :368:17] wire _GEN_51 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_52 = _T_46 | _GEN_51; // @[mshrs.scala:162:26, :338:{22,39}, :351:44, :361:42, :367:42, :369:38] wire _GEN_53 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_52; // @[package.scala:16:47] wire _GEN_54 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_53; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_54 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :371:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:210:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:213:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :213:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:220:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_142 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_246 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_142( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_246 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ITLB_5 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_238 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s2_5 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_17 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_239 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_240 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_241 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_242 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_243 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_244 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_245 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_246 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_247 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_248 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_249 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_250 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_251 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gf_inst_array, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)

module ITLB_5( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output io_ptw_req_bits_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input io_ptw_gstatus_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value, // @[TLB.scala:320:14] input io_kill // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire io_kill_0 = io_kill; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_resp_size = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8] wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8] wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53] wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46] wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33] wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [3:0] _misaligned_T_2 = 4'h3; // @[TLB.scala:550:69] wire [4:0] _misaligned_T_1 = 5'h3; // @[TLB.scala:550:69] wire [3:0] _misaligned_T = 4'h4; // @[OneHot.scala:58:35] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire _io_ptw_req_bits_valid_T; // @[TLB.scala:663:28] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {38'h0, io_req_bits_vaddr_0[1:0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] assign _io_ptw_req_bits_valid_T = ~io_kill_0; // @[TLB.scala:318:7, :663:28] assign io_ptw_req_bits_valid_0 = _io_ptw_req_bits_valid_T; // @[TLB.scala:318:7, :663:28] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_144 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_144( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1_1 : input clock : Clock input reset : Reset output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in inst chain of SynchronizerShiftReg_w1_d3_1 connect chain.clock, clock connect chain.reset, reset connect chain.io.d, nodeIn.sync[0] wire _WIRE : UInt<1>[1] wire _WIRE_1 : UInt<1> connect _WIRE_1, chain.io.q node _T = bits(_WIRE_1, 0, 0) connect _WIRE[0], _T connect nodeOut, _WIRE

module IntSyncAsyncCrossingSink_n1x1_1( // @[Crossing.scala:74:9] input clock, // @[Crossing.scala:74:9] input reset, // @[Crossing.scala:74:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:74:9] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:74:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:74:9] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9] SynchronizerShiftReg_w1_d3_1 chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (nodeIn_sync_0), // @[MixedNode.scala:551:17] .io_q (nodeOut_0) ); // @[ShiftReg.scala:45:23] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_22 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_22( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_46 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TageTable_3 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<8>(0hff)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) node idx_history = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 7, 0) node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) node tag_history = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1) node _tag_T = shr(_T_1, 8) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 7, 0) smem hi_us : UInt<1>[4] [256] smem lo_us : UInt<1>[4] [256] smem table : UInt<12>[4] [256] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire _s2_req_rtage_WIRE : UInt<8> invalidate _s2_req_rtage_WIRE when io.f1_req_valid : connect _s2_req_rtage_WIRE, s1_hashed_idx read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_2 : UInt<12> connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0] node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0) connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 10, 3) connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1 node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 11, 11) connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2 wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_4 : UInt<12> connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1] node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0) connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3 node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 10, 3) connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4 node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 11, 11) connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5 wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_6 : UInt<12> connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2] node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0) connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6 node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 10, 3) connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7 node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 11, 11) connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8 wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} wire _s2_req_rtage_WIRE_8 : UInt<12> connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3] node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0) connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9 node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 10, 3) connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10 node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 11, 11) connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11 wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid wire _s2_req_rhius_WIRE : UInt<8> invalidate _s2_req_rhius_WIRE when io.f1_req_valid : connect _s2_req_rhius_WIRE, s1_hashed_idx read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock wire _s2_req_rlous_WIRE : UInt<8> invalidate _s2_req_rlous_WIRE when io.f1_req_valid : connect _s2_req_rlous_WIRE, s1_hashed_idx read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 reg io_f3_resp_0_valid_REG : UInt<1>, clock connect io_f3_resp_0_valid_REG, s2_req_rhits[0] connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0]) reg io_f3_resp_0_bits_u_REG : UInt, clock connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG reg io_f3_resp_0_bits_ctr_REG : UInt, clock connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG reg io_f3_resp_1_valid_REG : UInt<1>, clock connect io_f3_resp_1_valid_REG, s2_req_rhits[1] connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1]) reg io_f3_resp_1_bits_u_REG : UInt, clock connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG reg io_f3_resp_1_bits_ctr_REG : UInt, clock connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG reg io_f3_resp_2_valid_REG : UInt<1>, clock connect io_f3_resp_2_valid_REG, s2_req_rhits[2] connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2]) reg io_f3_resp_2_bits_u_REG : UInt, clock connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG reg io_f3_resp_2_bits_ctr_REG : UInt, clock connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG reg io_f3_resp_3_valid_REG : UInt<1>, clock connect io_f3_resp_3_valid_REG, s2_req_rhits[3] connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3]) reg io_f3_resp_3_bits_u_REG : UInt, clock connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG reg io_f3_resp_3_bits_ctr_REG : UInt, clock connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _doing_clear_u_hi_T = bits(clear_u_ctr, 19, 19) node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1)) node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1) node _doing_clear_u_lo_T = bits(clear_u_ctr, 19, 19) node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0)) node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1) node clear_u_idx = shr(clear_u_ctr, 11) node _T_2 = shr(io.update_pc, 4) node idx_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) node idx_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) node idx_history_1 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 7, 0) node tag_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) node tag_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) node tag_history_1 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1) node _tag_T_2 = shr(_T_2, 8) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 7, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] node _T_3 = mux(doing_reset, reset_idx, update_idx) wire _WIRE : UInt<12>[4] connect _WIRE[0], UInt<12>(0h0) connect _WIRE[1], UInt<12>(0h0) connect _WIRE[2], UInt<12>(0h0) connect _WIRE[3], UInt<12>(0h0) node hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _T_4 = cat(hi, update_wdata[0].ctr) node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _T_5 = cat(hi_1, update_wdata[1].ctr) node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _T_6 = cat(hi_2, update_wdata[2].ctr) node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _T_7 = cat(hi_3, update_wdata[3].ctr) wire _WIRE_1 : UInt<12>[4] connect _WIRE_1[0], _T_4 connect _WIRE_1[1], _T_5 connect _WIRE_1[2], _T_6 connect _WIRE_1[3], _T_7 node _T_8 = mux(doing_reset, _WIRE, _WIRE_1) node _T_9 = not(UInt<4>(0h0)) node lo = cat(io.update_mask[1], io.update_mask[0]) node hi_4 = cat(io.update_mask[3], io.update_mask[2]) node _T_10 = cat(hi_4, lo) node _T_11 = mux(doing_reset, _T_9, _T_10) node _T_12 = bits(_T_11, 0, 0) node _T_13 = bits(_T_11, 1, 1) node _T_14 = bits(_T_11, 2, 2) node _T_15 = bits(_T_11, 3, 3) write mport MPORT = table[_T_3], clock when _T_12 : connect MPORT[0], _T_8[0] when _T_13 : connect MPORT[1], _T_8[1] when _T_14 : connect MPORT[2], _T_8[2] when _T_15 : connect MPORT[3], _T_8[3] wire update_hi_wdata : UInt<1>[4] node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx) node _T_17 = mux(doing_reset, reset_idx, _T_16) node _T_18 = or(doing_reset, doing_clear_u_hi) wire _WIRE_2 : UInt<1>[4] connect _WIRE_2[0], UInt<1>(0h0) connect _WIRE_2[1], UInt<1>(0h0) connect _WIRE_2[2], UInt<1>(0h0) connect _WIRE_2[3], UInt<1>(0h0) node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata) node _T_20 = or(doing_reset, doing_clear_u_hi) node _T_21 = not(UInt<4>(0h0)) node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_22 = cat(hi_5, lo_1) node _T_23 = mux(_T_20, _T_21, _T_22) node _T_24 = bits(_T_23, 0, 0) node _T_25 = bits(_T_23, 1, 1) node _T_26 = bits(_T_23, 2, 2) node _T_27 = bits(_T_23, 3, 3) node _T_28 = bits(_T_17, 7, 0) write mport MPORT_1 = hi_us[_T_28], clock when _T_24 : connect MPORT_1[0], _T_19[0] when _T_25 : connect MPORT_1[1], _T_19[1] when _T_26 : connect MPORT_1[2], _T_19[2] when _T_27 : connect MPORT_1[3], _T_19[3] wire update_lo_wdata : UInt<1>[4] node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx) node _T_30 = mux(doing_reset, reset_idx, _T_29) node _T_31 = or(doing_reset, doing_clear_u_lo) wire _WIRE_3 : UInt<1>[4] connect _WIRE_3[0], UInt<1>(0h0) connect _WIRE_3[1], UInt<1>(0h0) connect _WIRE_3[2], UInt<1>(0h0) connect _WIRE_3[3], UInt<1>(0h0) node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata) node _T_33 = or(doing_reset, doing_clear_u_lo) node _T_34 = not(UInt<4>(0h0)) node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0]) node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2]) node _T_35 = cat(hi_6, lo_2) node _T_36 = mux(_T_33, _T_34, _T_35) node _T_37 = bits(_T_36, 0, 0) node _T_38 = bits(_T_36, 1, 1) node _T_39 = bits(_T_36, 2, 2) node _T_40 = bits(_T_36, 3, 3) node _T_41 = bits(_T_30, 7, 0) write mport MPORT_2 = lo_us[_T_41], clock when _T_37 : connect MPORT_2[0], _T_32[0] when _T_38 : connect MPORT_2[1], _T_32[1] when _T_39 : connect MPORT_2[2], _T_32[2] when _T_40 : connect MPORT_2[3], _T_32[3] reg wrbypass_tags : UInt<8>[2], clock reg wrbypass_idxs : UInt<8>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1) connect update_hi_wdata[0], _update_hi_wdata_0_T node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0) connect update_lo_wdata[0], _update_lo_wdata_0_T node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1) connect update_hi_wdata[1], _update_hi_wdata_1_T node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0) connect update_lo_wdata[1], _update_lo_wdata_1_T node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1) connect update_hi_wdata[2], _update_hi_wdata_2_T node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0) connect update_lo_wdata[2], _update_lo_wdata_2_T node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1) connect update_hi_wdata[3], _update_hi_wdata_3_T node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0) connect update_lo_wdata[3], _update_lo_wdata_3_T node _T_42 = or(io.update_mask[0], io.update_mask[1]) node _T_43 = or(_T_42, io.update_mask[2]) node _T_44 = or(_T_43, io.update_mask[3]) when _T_44 : node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_45 : wire _WIRE_4 : UInt<3>[4] connect _WIRE_4[0], update_wdata[0].ctr connect _WIRE_4[1], update_wdata[1].ctr connect _WIRE_4[2], update_wdata[2].ctr connect _WIRE_4[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_4 else : wire _WIRE_5 : UInt<3>[4] connect _WIRE_5[0], update_wdata[0].ctr connect _WIRE_5[1], update_wdata[1].ctr connect _WIRE_5[2], update_wdata[2].ctr connect _WIRE_5[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_5 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2

module TageTable_3( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [11:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [11:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [47:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [7:0] reset_idx; // @[tage.scala:73:26] wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26] wire [7:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:162:35] wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:162:35] wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [7:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [7:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [7:0] tag_history = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}] wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}] wire [11:0] _s2_req_rtage_WIRE_2 = _table_R0_data[11:0]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_4 = _table_R0_data[23:12]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_6 = _table_R0_data[35:24]; // @[tage.scala:91:27, :97:87] wire [11:0] _s2_req_rtage_WIRE_8 = _table_R0_data[47:36]; // @[tage.scala:91:27, :97:87] reg [7:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [7:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [7:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[10:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[11]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [19:0] clear_u_ctr; // @[tage.scala:109:28] wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85] wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33] wire [7:0] idx_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] tag_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11] wire [7:0] idx_history_1 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:162:35] wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:162:35] wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}] wire [7:0] tag_history_1 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25] wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}] wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}] wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [8:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [8:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 12'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 12'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 12'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 12'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [7:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [7:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [7:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [7:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 8'h0; // @[tage.scala:73:26] clear_u_ctr <= 20'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_2 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_2 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_2 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e5_s11_1 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} inst divSqrtRawFN of DivSqrtRawFN_small_e5_s11_1 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 15, 10) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 5, 3) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 5, 4) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 3, 3) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 16, 16) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 9, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 15, 10) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 5, 3) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 5, 4) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 3, 3) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 16, 16) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 9, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut

module DivSqrtRecFMToRaw_small_e5_s11_1( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [5:0] divSqrtRawFN_io_a_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [5:0] divSqrtRawFN_io_b_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e5_s11_1 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CompareRecFN_3 : output io : { flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} node rawA_exp = bits(io.a, 63, 52) node _rawA_isZero_T = bits(rawA_exp, 11, 9) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 64, 64) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 63, 52) node _rawB_isZero_T = bits(rawB_exp, 11, 9) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 64, 64) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node _ordered_T = eq(rawA.isNaN, UInt<1>(0h0)) node _ordered_T_1 = eq(rawB.isNaN, UInt<1>(0h0)) node ordered = and(_ordered_T, _ordered_T_1) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) node _common_ltMags_T = lt(rawA.sExp, rawB.sExp) node _common_ltMags_T_1 = lt(rawA.sig, rawB.sig) node _common_ltMags_T_2 = and(eqExps, _common_ltMags_T_1) node common_ltMags = or(_common_ltMags_T, _common_ltMags_T_2) node _common_eqMags_T = eq(rawA.sig, rawB.sig) node common_eqMags = and(eqExps, _common_eqMags_T) node _ordered_lt_T = eq(bothZeros, UInt<1>(0h0)) node _ordered_lt_T_1 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_2 = and(rawA.sign, _ordered_lt_T_1) node _ordered_lt_T_3 = eq(bothInfs, UInt<1>(0h0)) node _ordered_lt_T_4 = eq(common_ltMags, UInt<1>(0h0)) node _ordered_lt_T_5 = and(rawA.sign, _ordered_lt_T_4) node _ordered_lt_T_6 = eq(common_eqMags, UInt<1>(0h0)) node _ordered_lt_T_7 = and(_ordered_lt_T_5, _ordered_lt_T_6) node _ordered_lt_T_8 = eq(rawB.sign, UInt<1>(0h0)) node _ordered_lt_T_9 = and(_ordered_lt_T_8, common_ltMags) node _ordered_lt_T_10 = or(_ordered_lt_T_7, _ordered_lt_T_9) node _ordered_lt_T_11 = and(_ordered_lt_T_3, _ordered_lt_T_10) node _ordered_lt_T_12 = or(_ordered_lt_T_2, _ordered_lt_T_11) node ordered_lt = and(_ordered_lt_T, _ordered_lt_T_12) node _ordered_eq_T = eq(rawA.sign, rawB.sign) node _ordered_eq_T_1 = or(bothInfs, common_eqMags) node _ordered_eq_T_2 = and(_ordered_eq_T, _ordered_eq_T_1) node ordered_eq = or(bothZeros, _ordered_eq_T_2) node _invalid_T = bits(rawA.sig, 51, 51) node _invalid_T_1 = eq(_invalid_T, UInt<1>(0h0)) node _invalid_T_2 = and(rawA.isNaN, _invalid_T_1) node _invalid_T_3 = bits(rawB.sig, 51, 51) node _invalid_T_4 = eq(_invalid_T_3, UInt<1>(0h0)) node _invalid_T_5 = and(rawB.isNaN, _invalid_T_4) node _invalid_T_6 = or(_invalid_T_2, _invalid_T_5) node _invalid_T_7 = eq(ordered, UInt<1>(0h0)) node _invalid_T_8 = and(io.signaling, _invalid_T_7) node invalid = or(_invalid_T_6, _invalid_T_8) node _io_lt_T = and(ordered, ordered_lt) connect io.lt, _io_lt_T node _io_eq_T = and(ordered, ordered_eq) connect io.eq, _io_eq_T node _io_gt_T = eq(ordered_lt, UInt<1>(0h0)) node _io_gt_T_1 = and(ordered, _io_gt_T) node _io_gt_T_2 = eq(ordered_eq, UInt<1>(0h0)) node _io_gt_T_3 = and(_io_gt_T_1, _io_gt_T_2) connect io.gt, _io_gt_T_3 node _io_exceptionFlags_T = cat(invalid, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T

module CompareRecFN_3( // @[CompareRecFN.scala:42:7] input [64:0] io_a, // @[CompareRecFN.scala:44:16] input [64:0] io_b, // @[CompareRecFN.scala:44:16] input io_signaling, // @[CompareRecFN.scala:44:16] output io_lt, // @[CompareRecFN.scala:44:16] output io_eq, // @[CompareRecFN.scala:44:16] output [4:0] io_exceptionFlags // @[CompareRecFN.scala:44:16] ); wire [64:0] io_a_0 = io_a; // @[CompareRecFN.scala:42:7] wire [64:0] io_b_0 = io_b; // @[CompareRecFN.scala:42:7] wire io_signaling_0 = io_signaling; // @[CompareRecFN.scala:42:7] wire _io_lt_T; // @[CompareRecFN.scala:78:22] wire _io_eq_T; // @[CompareRecFN.scala:79:22] wire _io_gt_T_3; // @[CompareRecFN.scala:80:38] wire [4:0] _io_exceptionFlags_T; // @[CompareRecFN.scala:81:34] wire io_lt_0; // @[CompareRecFN.scala:42:7] wire io_eq_0; // @[CompareRecFN.scala:42:7] wire io_gt; // @[CompareRecFN.scala:42:7] wire [4:0] io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_isZero_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_isZero_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _ordered_T = ~rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_T_1 = ~rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire ordered = _ordered_T & _ordered_T_1; // @[CompareRecFN.scala:57:{19,32,35}] wire bothInfs = rawA_isInf & rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire bothZeros = rawA_isZero_0 & rawB_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire eqExps = rawA_sExp == rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T = $signed(rawA_sExp) < $signed(rawB_sExp); // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_1 = rawA_sig < rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _common_ltMags_T_2 = eqExps & _common_ltMags_T_1; // @[CompareRecFN.scala:60:29, :62:{44,57}] wire common_ltMags = _common_ltMags_T | _common_ltMags_T_2; // @[CompareRecFN.scala:62:{20,33,44}] wire _common_eqMags_T = rawA_sig == rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire common_eqMags = eqExps & _common_eqMags_T; // @[CompareRecFN.scala:60:29, :63:{32,45}] wire _ordered_lt_T = ~bothZeros; // @[CompareRecFN.scala:59:33, :66:9] wire _ordered_lt_T_1 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_2 = rawA_sign & _ordered_lt_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_3 = ~bothInfs; // @[CompareRecFN.scala:58:33, :68:19] wire _ordered_lt_T_4 = ~common_ltMags; // @[CompareRecFN.scala:62:33, :69:38] wire _ordered_lt_T_5 = rawA_sign & _ordered_lt_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_6 = ~common_eqMags; // @[CompareRecFN.scala:63:32, :69:57] wire _ordered_lt_T_7 = _ordered_lt_T_5 & _ordered_lt_T_6; // @[CompareRecFN.scala:69:{35,54,57}] wire _ordered_lt_T_8 = ~rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_lt_T_9 = _ordered_lt_T_8 & common_ltMags; // @[CompareRecFN.scala:62:33, :70:{29,41}] wire _ordered_lt_T_10 = _ordered_lt_T_7 | _ordered_lt_T_9; // @[CompareRecFN.scala:69:{54,74}, :70:41] wire _ordered_lt_T_11 = _ordered_lt_T_3 & _ordered_lt_T_10; // @[CompareRecFN.scala:68:{19,30}, :69:74] wire _ordered_lt_T_12 = _ordered_lt_T_2 | _ordered_lt_T_11; // @[CompareRecFN.scala:67:{25,41}, :68:30] wire ordered_lt = _ordered_lt_T & _ordered_lt_T_12; // @[CompareRecFN.scala:66:{9,21}, :67:41] wire _ordered_eq_T = rawA_sign == rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _ordered_eq_T_1 = bothInfs | common_eqMags; // @[CompareRecFN.scala:58:33, :63:32, :72:62] wire _ordered_eq_T_2 = _ordered_eq_T & _ordered_eq_T_1; // @[CompareRecFN.scala:72:{34,49,62}] wire ordered_eq = bothZeros | _ordered_eq_T_2; // @[CompareRecFN.scala:59:33, :72:{19,49}] wire _invalid_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_1 = ~_invalid_T; // @[common.scala:82:{49,56}] wire _invalid_T_2 = rawA_isNaN & _invalid_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_4 = ~_invalid_T_3; // @[common.scala:82:{49,56}] wire _invalid_T_5 = rawB_isNaN & _invalid_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _invalid_T_6 = _invalid_T_2 | _invalid_T_5; // @[common.scala:82:46] wire _invalid_T_7 = ~ordered; // @[CompareRecFN.scala:57:32, :76:30] wire _invalid_T_8 = io_signaling_0 & _invalid_T_7; // @[CompareRecFN.scala:42:7, :76:{27,30}] wire invalid = _invalid_T_6 | _invalid_T_8; // @[CompareRecFN.scala:75:{32,58}, :76:27] assign _io_lt_T = ordered & ordered_lt; // @[CompareRecFN.scala:57:32, :66:21, :78:22] assign io_lt_0 = _io_lt_T; // @[CompareRecFN.scala:42:7, :78:22] assign _io_eq_T = ordered & ordered_eq; // @[CompareRecFN.scala:57:32, :72:19, :79:22] assign io_eq_0 = _io_eq_T; // @[CompareRecFN.scala:42:7, :79:22] wire _io_gt_T = ~ordered_lt; // @[CompareRecFN.scala:66:21, :80:25] wire _io_gt_T_1 = ordered & _io_gt_T; // @[CompareRecFN.scala:57:32, :80:{22,25}] wire _io_gt_T_2 = ~ordered_eq; // @[CompareRecFN.scala:72:19, :80:41] assign _io_gt_T_3 = _io_gt_T_1 & _io_gt_T_2; // @[CompareRecFN.scala:80:{22,38,41}] assign io_gt = _io_gt_T_3; // @[CompareRecFN.scala:42:7, :80:38] assign _io_exceptionFlags_T = {invalid, 4'h0}; // @[CompareRecFN.scala:75:58, :81:34] assign io_exceptionFlags_0 = _io_exceptionFlags_T; // @[CompareRecFN.scala:42:7, :81:34] assign io_lt = io_lt_0; // @[CompareRecFN.scala:42:7] assign io_eq = io_eq_0; // @[CompareRecFN.scala:42:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[CompareRecFN.scala:42:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_74 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) node _source_ok_T = shr(io.in.a.bits.source, 5) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5)) node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4) node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4) node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit) node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2) node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T) node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit) node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2) node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2) node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2) node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2) node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2) node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2) node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2) node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit) node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2) node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8) node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit) node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2) node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9) node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit) node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2) node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10) node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit) node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2) node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11) node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit) node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2) node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12) node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit) node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2) node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13) node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit) node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2) node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14) node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit) node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2) node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_eq_16 = and(mask_sub_8_2, mask_nbit) node _mask_acc_T_16 = and(mask_size, mask_eq_16) node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_8_2, mask_bit) node _mask_acc_T_17 = and(mask_size, mask_eq_17) node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_9_2, mask_nbit) node _mask_acc_T_18 = and(mask_size, mask_eq_18) node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_9_2, mask_bit) node _mask_acc_T_19 = and(mask_size, mask_eq_19) node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_10_2, mask_nbit) node _mask_acc_T_20 = and(mask_size, mask_eq_20) node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_10_2, mask_bit) node _mask_acc_T_21 = and(mask_size, mask_eq_21) node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_11_2, mask_nbit) node _mask_acc_T_22 = and(mask_size, mask_eq_22) node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_11_2, mask_bit) node _mask_acc_T_23 = and(mask_size, mask_eq_23) node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_12_2, mask_nbit) node _mask_acc_T_24 = and(mask_size, mask_eq_24) node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_12_2, mask_bit) node _mask_acc_T_25 = and(mask_size, mask_eq_25) node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_13_2, mask_nbit) node _mask_acc_T_26 = and(mask_size, mask_eq_26) node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_13_2, mask_bit) node _mask_acc_T_27 = and(mask_size, mask_eq_27) node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_14_2, mask_nbit) node _mask_acc_T_28 = and(mask_size, mask_eq_28) node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_14_2, mask_bit) node _mask_acc_T_29 = and(mask_size, mask_eq_29) node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_15_2, mask_nbit) node _mask_acc_T_30 = and(mask_size, mask_eq_30) node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_15_2, mask_bit) node _mask_acc_T_31 = and(mask_size, mask_eq_31) node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31) node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo) node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo) node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16) node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18) node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo) node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20) node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22) node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24) node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26) node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo) node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits = bits(_uncommonBits_T, 4, 0) node _T_4 = shr(io.in.a.bits.source, 5) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<5>(0h1f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) node _T_24 = shr(io.in.a.bits.source, 5) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) node _T_197 = shr(io.in.a.bits.source, 5) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) node _T_374 = shr(io.in.a.bits.source, 5) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_480 = shr(io.in.a.bits.source, 5) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_582 = shr(io.in.a.bits.source, 5) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_686 = shr(io.in.a.bits.source, 5) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_783 = shr(io.in.a.bits.source, 5) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_880 = shr(io.in.a.bits.source, 5) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 5) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<256>(0h0) connect _WIRE.bits.mask, UInt<32>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<256>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_148 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<256>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<256>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<256>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<256>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<256>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<256>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<256>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<256>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<256>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<256>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<256>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<256>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_149 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:89:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<256>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_74( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59] wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14] wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27] wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25] wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28] wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28] wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74] wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49] wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}] wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21] wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [6:0] a_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_1; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46] wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [6:0] d_first_counter_2; // @[Edges.scala:229:27] wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28] wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a12d64s9k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)

module Repeater_TLBundleA_a12d64s9k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [8:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [11:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [8:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [11:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [8:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [11:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [8:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [11:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [8:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [11:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [8:0] saved_source; // @[Repeater.scala:21:18] reg [11:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SystemBus_1 : output auto : { flip coupler_from_rockettile_tl_master_clock_xing_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, system_bus_xbar_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip csbus0_clock_groups_in : { member : { csbus0_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst csbus0_clock_groups of ClockGroupAggregator_csbus0 inst clockGroup of ClockGroup_6 inst fixedClockNode of FixedClockBroadcast_7_1 inst broadcast of BundleBridgeNexus_NoOutput_6 inst system_bus_xbar of TLXbar_csbus0_i4_o1_a32d64s4k3z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer_5 connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_csbus0_from_rockettile connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset inst coupler_from_rockettile_1 of TLInterconnectCoupler_csbus0_from_rockettile_1 connect coupler_from_rockettile_1.clock, childClock connect coupler_from_rockettile_1.reset, childReset inst coupler_from_rockettile_2 of TLInterconnectCoupler_csbus0_from_rockettile_2 connect coupler_from_rockettile_2.clock, childClock connect coupler_from_rockettile_2.reset, childReset inst coupler_from_rockettile_3 of TLInterconnectCoupler_csbus0_from_rockettile_3 connect coupler_from_rockettile_3.clock, childClock connect coupler_from_rockettile_3.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, csbus0_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2 connect system_bus_xbar.auto.anon_in_3, fixer.auto.anon_out_3 connect fixer.auto.anon_in_0, coupler_from_rockettile.auto.tl_out connect fixer.auto.anon_in_1, coupler_from_rockettile_1.auto.tl_out connect fixer.auto.anon_in_2, coupler_from_rockettile_2.auto.tl_out connect fixer.auto.anon_in_3, coupler_from_rockettile_3.auto.tl_out connect csbus0_clock_groups.auto.in, auto.csbus0_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5 connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6 connect auto.system_bus_xbar_anon_out.e.bits, system_bus_xbar.auto.anon_out.e.bits connect auto.system_bus_xbar_anon_out.e.valid, system_bus_xbar.auto.anon_out.e.valid connect system_bus_xbar.auto.anon_out.e.ready, auto.system_bus_xbar_anon_out.e.ready connect system_bus_xbar.auto.anon_out.d, auto.system_bus_xbar_anon_out.d connect auto.system_bus_xbar_anon_out.c.bits, system_bus_xbar.auto.anon_out.c.bits connect auto.system_bus_xbar_anon_out.c.valid, system_bus_xbar.auto.anon_out.c.valid connect system_bus_xbar.auto.anon_out.c.ready, auto.system_bus_xbar_anon_out.c.ready connect system_bus_xbar.auto.anon_out.b, auto.system_bus_xbar_anon_out.b connect auto.system_bus_xbar_anon_out.a.bits, system_bus_xbar.auto.anon_out.a.bits connect auto.system_bus_xbar_anon_out.a.valid, system_bus_xbar.auto.anon_out.a.valid connect system_bus_xbar.auto.anon_out.a.ready, auto.system_bus_xbar_anon_out.a.ready connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_0 connect coupler_from_rockettile_1.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_1 connect coupler_from_rockettile_2.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_2 connect coupler_from_rockettile_3.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in_3 connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset

module SystemBus_1( // @[ClockDomain.scala:14:9] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_system_bus_xbar_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_system_bus_xbar_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_system_bus_xbar_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_system_bus_xbar_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_system_bus_xbar_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_system_bus_xbar_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_system_bus_xbar_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_system_bus_xbar_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_system_bus_xbar_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_system_bus_xbar_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_system_bus_xbar_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_system_bus_xbar_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_system_bus_xbar_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_system_bus_xbar_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_system_bus_xbar_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_system_bus_xbar_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_system_bus_xbar_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_csbus0_clock_groups_in_member_csbus0_0_clock, // @[LazyModuleImp.scala:107:25] input auto_csbus0_clock_groups_in_member_csbus0_0_reset // @[LazyModuleImp.scala:107:25] ); wire fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire csbus0_clock_groups_auto_out_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_auto_out_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_ready_0 = auto_system_bus_xbar_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_valid_0 = auto_system_bus_xbar_anon_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode_0 = auto_system_bus_xbar_anon_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_system_bus_xbar_anon_out_b_bits_param_0 = auto_system_bus_xbar_anon_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_b_bits_size_0 = auto_system_bus_xbar_anon_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_b_bits_source_0 = auto_system_bus_xbar_anon_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_b_bits_address_0 = auto_system_bus_xbar_anon_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_system_bus_xbar_anon_out_b_bits_mask_0 = auto_system_bus_xbar_anon_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_b_bits_data_0 = auto_system_bus_xbar_anon_out_b_bits_data; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_bits_corrupt_0 = auto_system_bus_xbar_anon_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_ready_0 = auto_system_bus_xbar_anon_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_valid_0 = auto_system_bus_xbar_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode_0 = auto_system_bus_xbar_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_system_bus_xbar_anon_out_d_bits_param_0 = auto_system_bus_xbar_anon_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_d_bits_size_0 = auto_system_bus_xbar_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_d_bits_source_0 = auto_system_bus_xbar_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_d_bits_sink_0 = auto_system_bus_xbar_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_bits_denied_0 = auto_system_bus_xbar_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_d_bits_data_0 = auto_system_bus_xbar_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_bits_corrupt_0 = auto_system_bus_xbar_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_e_ready_0 = auto_system_bus_xbar_anon_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_csbus0_clock_groups_in_member_csbus0_0_clock_0 = auto_csbus0_clock_groups_in_member_csbus0_0_clock; // @[ClockDomain.scala:14:9] wire auto_csbus0_clock_groups_in_member_csbus0_0_reset_0 = auto_csbus0_clock_groups_in_member_csbus0_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] fixer__allIDs_FIFOed_T = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_1 = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_2 = 3'h7; // @[FIFOFixer.scala:127:48] wire [2:0] fixer__allIDs_FIFOed_T_3 = 3'h7; // @[FIFOFixer.scala:127:48] wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_14 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_6 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_7 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_6 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_7 = 1'h1; // @[FIFOFixer.scala:96:47] wire fixer__a_id_T_19 = 1'h1; // @[Parameters.scala:137:59] wire fixer__anonOut_a_valid_T_9 = 1'h1; // @[FIFOFixer.scala:95:50] wire fixer__anonOut_a_valid_T_10 = 1'h1; // @[FIFOFixer.scala:95:47] wire fixer__anonIn_a_ready_T_9 = 1'h1; // @[FIFOFixer.scala:96:50] wire fixer__anonIn_a_ready_T_10 = 1'h1; // @[FIFOFixer.scala:96:47] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire csbus0_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire csbus0_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire csbus0_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_90 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_2 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_2_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_2_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__a_notFIFO_T_121 = 1'h0; // @[Mux.scala:30:73] wire fixer_a_noDomain_3 = 1'h0; // @[FIFOFixer.scala:63:29] wire fixer__flight_WIRE_3_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire fixer__flight_WIRE_3_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] fixer__a_id_T_18 = 33'h0; // @[Parameters.scala:137:46] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire csbus0_clock_groups_auto_in_member_csbus0_0_clock = auto_csbus0_clock_groups_in_member_csbus0_0_clock_0; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_auto_in_member_csbus0_0_reset = auto_csbus0_clock_groups_in_member_csbus0_0_reset_0; // @[ClockGroup.scala:53:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire csbus0_clock_groups_nodeIn_member_csbus0_0_clock = csbus0_clock_groups_auto_in_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_nodeOut_member_csbus0_0_clock; // @[MixedNode.scala:542:17] wire csbus0_clock_groups_nodeIn_member_csbus0_0_reset = csbus0_clock_groups_auto_in_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] wire csbus0_clock_groups_nodeOut_member_csbus0_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_csbus0_0_clock = csbus0_clock_groups_auto_out_member_csbus0_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_csbus0_0_reset = csbus0_clock_groups_auto_out_member_csbus0_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign csbus0_clock_groups_auto_out_member_csbus0_0_clock = csbus0_clock_groups_nodeOut_member_csbus0_0_clock; // @[ClockGroup.scala:53:9] assign csbus0_clock_groups_auto_out_member_csbus0_0_reset = csbus0_clock_groups_nodeOut_member_csbus0_0_reset; // @[ClockGroup.scala:53:9] assign csbus0_clock_groups_nodeOut_member_csbus0_0_clock = csbus0_clock_groups_nodeIn_member_csbus0_0_clock; // @[MixedNode.scala:542:17, :551:17] assign csbus0_clock_groups_nodeOut_member_csbus0_0_reset = csbus0_clock_groups_nodeIn_member_csbus0_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_csbus0_0_clock = clockGroup_auto_in_member_csbus0_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_csbus0_0_reset = clockGroup_auto_in_member_csbus0_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_csbus0_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_csbus0_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixer_x1_anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_a_ready = fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_a_valid = fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_a_bits_opcode = fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_a_bits_param = fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_2_a_bits_size = fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_2_a_bits_source = fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_2_a_bits_address = fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_2_a_bits_mask = fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_2_a_bits_data = fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_a_bits_corrupt = fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_b_ready = fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_b_valid = fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_2_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_param = fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_auto_tl_out_b_bits_size = fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_source = fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_2_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_auto_tl_out_b_bits_address = fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_2_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_3_auto_tl_out_b_bits_mask = fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_auto_tl_out_b_bits_data = fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_ready = fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_c_valid = fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_c_bits_opcode = fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_2_c_bits_param = fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_2_c_bits_size = fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_2_c_bits_source = fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_2_c_bits_address = fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_2_c_bits_data = fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_c_bits_corrupt = fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_d_ready = fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_valid = fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_param = fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_auto_tl_out_d_bits_size = fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_source = fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_sink = fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_bits_denied = fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_auto_tl_out_d_bits_data = fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_2_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_e_ready = fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_2_e_valid = fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_2_e_bits_sink = fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_ready = fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_valid = fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_opcode = fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_a_bits_param = fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_a_bits_size = fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_a_bits_source = fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_a_bits_address = fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_1_a_bits_mask = fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_1_a_bits_data = fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_a_bits_corrupt = fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_b_ready = fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_b_valid = fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_param = fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_auto_tl_out_b_bits_size = fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_source = fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_1_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_auto_tl_out_b_bits_address = fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_1_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_2_auto_tl_out_b_bits_mask = fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_auto_tl_out_b_bits_data = fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_ready = fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_valid = fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_opcode = fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_1_c_bits_param = fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_1_c_bits_size = fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_1_c_bits_source = fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_1_c_bits_address = fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_1_c_bits_data = fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_c_bits_corrupt = fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_d_ready = fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_valid = fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_param = fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_auto_tl_out_d_bits_size = fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_source = fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_sink = fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_bits_denied = fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_auto_tl_out_d_bits_data = fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_e_ready = fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_1_e_valid = fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_1_e_bits_sink = fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_b_ready = fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_b_valid = fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_param = fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_auto_tl_out_b_bits_size = fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_source = fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_auto_tl_out_b_bits_address = fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_1_auto_tl_out_b_bits_mask = fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_auto_tl_out_b_bits_data = fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_ready = fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_valid = fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_opcode = fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_x1_anonIn_c_bits_param = fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_x1_anonIn_c_bits_size = fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_x1_anonIn_c_bits_source = fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_x1_anonIn_c_bits_address = fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_x1_anonIn_c_bits_data = fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_c_bits_corrupt = fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonIn_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_e_ready = fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_x1_anonIn_e_valid = fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] fixer_x1_anonIn_e_bits_sink = fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_ready = fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_b_ready = fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_b_valid = fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_param = fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_b_bits_size = fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_source = fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_auto_tl_out_b_bits_address = fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_auto_tl_out_b_bits_mask = fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_auto_tl_out_b_bits_data = fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_ready = fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_c_valid = fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_c_bits_opcode = fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_c_bits_param = fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7] wire [3:0] fixer_anonIn_c_bits_size = fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7] wire [1:0] fixer_anonIn_c_bits_source = fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7] wire [31:0] fixer_anonIn_c_bits_address = fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7] wire [63:0] fixer_anonIn_c_bits_data = fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_c_bits_corrupt = fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_valid = fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_param = fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_auto_tl_out_d_bits_size = fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_source = fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_auto_tl_out_d_bits_data = fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonIn_e_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_e_ready = fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7] wire fixer_anonIn_e_valid = fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7] wire [2:0] fixer_anonIn_e_bits_sink = fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_a_ready = fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_b_valid = fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_b_bits_opcode = fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_b_bits_param = fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_2_b_bits_size = fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_b_bits_source = fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_2_b_bits_address = fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_2_b_bits_mask = fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_2_b_bits_data = fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_b_bits_corrupt = fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_c_ready = fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_2_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_2_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_2_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_2_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_2_d_valid = fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_d_bits_opcode = fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_d_bits_param = fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_2_d_bits_size = fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_2_d_bits_source = fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_2_d_bits_sink = fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_d_bits_denied = fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_2_d_bits_data = fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_d_bits_corrupt = fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_e_ready = fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_2_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_2_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_a_ready = fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_b_valid = fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_b_bits_opcode = fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_param = fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_b_bits_size = fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_b_bits_source = fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_1_b_bits_address = fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_1_b_bits_mask = fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_1_b_bits_data = fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_b_bits_corrupt = fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_ready = fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_1_d_valid = fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_d_bits_opcode = fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_param = fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_1_d_bits_size = fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_1_d_bits_source = fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_1_d_bits_sink = fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_denied = fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_1_d_bits_data = fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_d_bits_corrupt = fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_ready = fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_b_valid = fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_b_bits_opcode = fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_param = fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_b_bits_size = fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_b_bits_source = fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_x1_anonOut_b_bits_address = fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_x1_anonOut_b_bits_mask = fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_b_bits_data = fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_b_bits_corrupt = fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_ready = fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_ready = fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_b_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_b_valid = fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_b_bits_opcode = fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_b_bits_param = fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_b_bits_size = fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_b_bits_source = fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_anonOut_b_bits_address = fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_anonOut_b_bits_mask = fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_b_bits_data = fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_b_bits_corrupt = fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_c_ready = fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] fixer_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] fixer_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] fixer_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] fixer_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire fixer_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17] wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_e_ready = fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9] wire fixer_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] fixer_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] fixer_auto_anon_out_3_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_3_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_3_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_3_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_3_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_3_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_3_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_3_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_2_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_2_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_2_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_2_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_2_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_2_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_b_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] fixer_auto_anon_out_0_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] fixer_auto_anon_out_0_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] fixer_auto_anon_out_0_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] fixer_auto_anon_out_0_c_bits_data; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_c_valid; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9] wire [2:0] fixer_auto_anon_out_0_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer_auto_anon_out_0_e_valid; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_b_ready = fixer_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_b_valid = fixer_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_opcode = fixer_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_param = fixer_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_size = fixer_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_source = fixer_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_address = fixer_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_mask = fixer_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_data = fixer_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_b_bits_corrupt = fixer_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_c_ready = fixer_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_0_c_valid = fixer_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_opcode = fixer_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_param = fixer_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_size = fixer_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_source = fixer_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_address = fixer_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_data = fixer_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_c_bits_corrupt = fixer_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonIn_e_ready = fixer_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_0_e_valid = fixer_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_0_e_bits_sink = fixer_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_b_ready = fixer_x1_anonOut_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_b_valid = fixer_x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_opcode = fixer_x1_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_param = fixer_x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_size = fixer_x1_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_source = fixer_x1_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_address = fixer_x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_mask = fixer_x1_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_data = fixer_x1_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_b_bits_corrupt = fixer_x1_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_c_ready = fixer_x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_c_valid = fixer_x1_anonOut_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_opcode = fixer_x1_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_param = fixer_x1_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_size = fixer_x1_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_source = fixer_x1_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_address = fixer_x1_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_data = fixer_x1_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_c_bits_corrupt = fixer_x1_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_e_ready = fixer_x1_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_1_e_valid = fixer_x1_anonOut_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_1_e_bits_sink = fixer_x1_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_8 = fixer_x1_anonOut_1_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_2_a_valid = fixer_x1_anonOut_1_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_opcode = fixer_x1_anonOut_1_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_param = fixer_x1_anonOut_1_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_size = fixer_x1_anonOut_1_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_source = fixer_x1_anonOut_1_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_address = fixer_x1_anonOut_1_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_mask = fixer_x1_anonOut_1_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_data = fixer_x1_anonOut_1_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_a_bits_corrupt = fixer_x1_anonOut_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_b_ready = fixer_x1_anonOut_1_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_b_valid = fixer_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_opcode = fixer_x1_anonOut_1_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_param = fixer_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_size = fixer_x1_anonOut_1_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_source = fixer_x1_anonOut_1_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_address = fixer_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_mask = fixer_x1_anonOut_1_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_data = fixer_x1_anonOut_1_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_b_bits_corrupt = fixer_x1_anonOut_1_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_c_ready = fixer_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_c_valid = fixer_x1_anonOut_1_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_opcode = fixer_x1_anonOut_1_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_param = fixer_x1_anonOut_1_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_size = fixer_x1_anonOut_1_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_source = fixer_x1_anonOut_1_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_address = fixer_x1_anonOut_1_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_data = fixer_x1_anonOut_1_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_c_bits_corrupt = fixer_x1_anonOut_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_d_ready = fixer_x1_anonOut_1_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_1_d_valid = fixer_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_opcode = fixer_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_param = fixer_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_size = fixer_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_source = fixer_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_sink = fixer_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_denied = fixer_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_data = fixer_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_d_bits_corrupt = fixer_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_1_e_ready = fixer_x1_anonOut_1_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_2_e_valid = fixer_x1_anonOut_1_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_2_e_bits_sink = fixer_x1_anonOut_1_e_bits_sink; // @[FIFOFixer.scala:50:9] wire fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33] wire fixer__anonIn_a_ready_T_11 = fixer_x1_anonOut_2_a_ready; // @[FIFOFixer.scala:96:33] assign fixer_auto_anon_out_3_a_valid = fixer_x1_anonOut_2_a_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_opcode = fixer_x1_anonOut_2_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_param = fixer_x1_anonOut_2_a_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_size = fixer_x1_anonOut_2_a_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_source = fixer_x1_anonOut_2_a_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_address = fixer_x1_anonOut_2_a_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_mask = fixer_x1_anonOut_2_a_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_data = fixer_x1_anonOut_2_a_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_a_bits_corrupt = fixer_x1_anonOut_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_b_ready = fixer_x1_anonOut_2_b_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_2_b_valid = fixer_x1_anonOut_2_b_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_opcode = fixer_x1_anonOut_2_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_param = fixer_x1_anonOut_2_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_size = fixer_x1_anonOut_2_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_source = fixer_x1_anonOut_2_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_address = fixer_x1_anonOut_2_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_mask = fixer_x1_anonOut_2_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_data = fixer_x1_anonOut_2_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_b_bits_corrupt = fixer_x1_anonOut_2_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_c_ready = fixer_x1_anonOut_2_c_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_3_c_valid = fixer_x1_anonOut_2_c_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_opcode = fixer_x1_anonOut_2_c_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_param = fixer_x1_anonOut_2_c_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_size = fixer_x1_anonOut_2_c_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_source = fixer_x1_anonOut_2_c_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_address = fixer_x1_anonOut_2_c_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_data = fixer_x1_anonOut_2_c_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_c_bits_corrupt = fixer_x1_anonOut_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_d_ready = fixer_x1_anonOut_2_d_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonIn_2_d_valid = fixer_x1_anonOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_opcode = fixer_x1_anonOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_param = fixer_x1_anonOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_size = fixer_x1_anonOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_source = fixer_x1_anonOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_sink = fixer_x1_anonOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_denied = fixer_x1_anonOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_data = fixer_x1_anonOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_d_bits_corrupt = fixer_x1_anonOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonIn_2_e_ready = fixer_x1_anonOut_2_e_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_out_3_e_valid = fixer_x1_anonOut_2_e_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_out_3_e_bits_sink = fixer_x1_anonOut_2_e_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_b_ready = fixer_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_b_valid = fixer_anonIn_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_opcode = fixer_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_param = fixer_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_size = fixer_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_source = fixer_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_address = fixer_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_mask = fixer_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_data = fixer_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_b_bits_corrupt = fixer_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_c_ready = fixer_anonIn_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonOut_c_valid = fixer_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_opcode = fixer_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_param = fixer_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_size = fixer_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_source = fixer_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_address = fixer_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_data = fixer_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_c_bits_corrupt = fixer_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_0_e_ready = fixer_anonIn_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_anonOut_e_valid = fixer_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_anonOut_e_bits_sink = fixer_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_b_ready = fixer_x1_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_b_valid = fixer_x1_anonIn_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_opcode = fixer_x1_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_param = fixer_x1_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_size = fixer_x1_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_source = fixer_x1_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_address = fixer_x1_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_mask = fixer_x1_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_data = fixer_x1_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_b_bits_corrupt = fixer_x1_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_c_ready = fixer_x1_anonIn_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_c_valid = fixer_x1_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_opcode = fixer_x1_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_param = fixer_x1_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_size = fixer_x1_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_source = fixer_x1_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_address = fixer_x1_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_data = fixer_x1_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_c_bits_corrupt = fixer_x1_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_1_e_ready = fixer_x1_anonIn_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_e_valid = fixer_x1_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_e_bits_sink = fixer_x1_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_a_ready = fixer_x1_anonIn_1_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_8 = fixer_x1_anonIn_1_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_1_a_bits_opcode = fixer_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_param = fixer_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_size = fixer_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_source = fixer_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_address = fixer_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_62 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_10 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_1_a_bits_mask = fixer_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_data = fixer_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_a_bits_corrupt = fixer_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_b_ready = fixer_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_b_valid = fixer_x1_anonIn_1_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_opcode = fixer_x1_anonIn_1_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_param = fixer_x1_anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_size = fixer_x1_anonIn_1_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_source = fixer_x1_anonIn_1_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_address = fixer_x1_anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_mask = fixer_x1_anonIn_1_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_data = fixer_x1_anonIn_1_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_b_bits_corrupt = fixer_x1_anonIn_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_c_ready = fixer_x1_anonIn_1_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_c_valid = fixer_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_opcode = fixer_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_param = fixer_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_size = fixer_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_source = fixer_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_address = fixer_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_data = fixer_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_c_bits_corrupt = fixer_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_d_ready = fixer_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_2_d_valid = fixer_x1_anonIn_1_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_opcode = fixer_x1_anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_param = fixer_x1_anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_size = fixer_x1_anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_source = fixer_x1_anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_sink = fixer_x1_anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_denied = fixer_x1_anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_data = fixer_x1_anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_d_bits_corrupt = fixer_x1_anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_2_e_ready = fixer_x1_anonIn_1_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_1_e_valid = fixer_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_1_e_bits_sink = fixer_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_a_ready = fixer_x1_anonIn_2_a_ready; // @[FIFOFixer.scala:50:9] assign fixer__anonOut_a_valid_T_11 = fixer_x1_anonIn_2_a_valid; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonOut_2_a_bits_opcode = fixer_x1_anonIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_param = fixer_x1_anonIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_size = fixer_x1_anonIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_source = fixer_x1_anonIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_address = fixer_x1_anonIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [31:0] fixer__a_notFIFO_T_93 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31] wire [31:0] fixer__a_id_T_15 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31] assign fixer_x1_anonOut_2_a_bits_mask = fixer_x1_anonIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_data = fixer_x1_anonIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_a_bits_corrupt = fixer_x1_anonIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_b_ready = fixer_x1_anonIn_2_b_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_b_valid = fixer_x1_anonIn_2_b_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_opcode = fixer_x1_anonIn_2_b_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_param = fixer_x1_anonIn_2_b_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_size = fixer_x1_anonIn_2_b_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_source = fixer_x1_anonIn_2_b_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_address = fixer_x1_anonIn_2_b_bits_address; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_mask = fixer_x1_anonIn_2_b_bits_mask; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_data = fixer_x1_anonIn_2_b_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_b_bits_corrupt = fixer_x1_anonIn_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_c_ready = fixer_x1_anonIn_2_c_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_2_c_valid = fixer_x1_anonIn_2_c_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_opcode = fixer_x1_anonIn_2_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_param = fixer_x1_anonIn_2_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_size = fixer_x1_anonIn_2_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_source = fixer_x1_anonIn_2_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_address = fixer_x1_anonIn_2_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_data = fixer_x1_anonIn_2_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_c_bits_corrupt = fixer_x1_anonIn_2_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_d_ready = fixer_x1_anonIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17] assign fixer_auto_anon_in_3_d_valid = fixer_x1_anonIn_2_d_valid; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_opcode = fixer_x1_anonIn_2_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_param = fixer_x1_anonIn_2_d_bits_param; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_size = fixer_x1_anonIn_2_d_bits_size; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_source = fixer_x1_anonIn_2_d_bits_source; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_sink = fixer_x1_anonIn_2_d_bits_sink; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_denied = fixer_x1_anonIn_2_d_bits_denied; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_data = fixer_x1_anonIn_2_d_bits_data; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_d_bits_corrupt = fixer_x1_anonIn_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9] assign fixer_auto_anon_in_3_e_ready = fixer_x1_anonIn_2_e_ready; // @[FIFOFixer.scala:50:9] assign fixer_x1_anonOut_2_e_valid = fixer_x1_anonIn_2_e_valid; // @[MixedNode.scala:542:17, :551:17] assign fixer_x1_anonOut_2_e_bits_sink = fixer_x1_anonIn_2_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 | fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 | fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73] wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73] wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T = 4'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T = 4'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 | fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 | fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 | fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73] wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_1 = fixer_a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73] wire fixer__T_18 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_1 = 4'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_1 = 4'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_18 ? fixer__SourceIdClear_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_63 = {1'h0, fixer__a_notFIFO_T_62}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_64 = fixer__a_notFIFO_T_63 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_66 = fixer__a_notFIFO_T_65 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_67 = {fixer_x1_anonIn_1_a_bits_address[31:17], fixer_x1_anonIn_1_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_68 = {1'h0, fixer__a_notFIFO_T_67}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_72 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_73 = {1'h0, fixer__a_notFIFO_T_72}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_75 = fixer__a_notFIFO_T_74; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_76 = fixer__a_notFIFO_T_75 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_77 = fixer__a_notFIFO_T_66 | fixer__a_notFIFO_T_71; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_78 = fixer__a_notFIFO_T_77 | fixer__a_notFIFO_T_76; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_79 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_80 = {1'h0, fixer__a_notFIFO_T_79}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_81 = fixer__a_notFIFO_T_80 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_82 = fixer__a_notFIFO_T_81; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_83 = fixer__a_notFIFO_T_82 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_84 = fixer_x1_anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_85 = {1'h0, fixer__a_notFIFO_T_84}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_86 = fixer__a_notFIFO_T_85 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_87 = fixer__a_notFIFO_T_86; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_88 = fixer__a_notFIFO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_89 = fixer__a_notFIFO_T_83 | fixer__a_notFIFO_T_88; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_91 = fixer__a_notFIFO_T_89; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_92 = fixer__a_notFIFO_T_91; // @[Mux.scala:30:73] wire fixer_a_notFIFO_2 = fixer__a_notFIFO_T_92; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_2 = fixer_x1_anonIn_1_a_ready & fixer_x1_anonIn_1_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonIn_1_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_7 = fixer__a_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_8 = ~fixer__a_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_2 = fixer__a_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_2 = fixer_x1_anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_2 = ~fixer__a_first_beats1_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_2 = fixer_a_first_beats1_opdata_2 ? fixer_a_first_beats1_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_2; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_2 = {1'h0, fixer_a_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_2 = fixer__a_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_2 = fixer_a_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_4 = fixer_a_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_5 = fixer_a_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_2 = fixer__a_first_last_T_4 | fixer__a_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_2 = fixer_a_first_last_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_2 = ~fixer_a_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_2 = fixer_a_first_beats1_2 & fixer__a_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_2 = fixer_a_first_2 ? fixer_a_first_beats1_2 : fixer_a_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_4 = fixer_x1_anonOut_1_d_ready & fixer_x1_anonOut_1_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonOut_1_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_7 = fixer__d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_8 = ~fixer__d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_2 = fixer__d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_2 = fixer_x1_anonOut_1_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_2 = fixer_d_first_beats1_opdata_2 ? fixer_d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_2 = {1'h0, fixer_d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_2 = fixer__d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_2 = fixer_d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_4 = fixer_d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_5 = fixer_d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_2 = fixer__d_first_last_T_4 | fixer__d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_2 = fixer_d_first_last_2 & fixer__d_first_T_4; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_2 = ~fixer_d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_2 = fixer_d_first_beats1_2 & fixer__d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_2 = fixer_d_first_first_2 ? fixer_d_first_beats1_2 : fixer_d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_5 = fixer_x1_anonOut_1_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_2 = fixer_d_first_first_2 & fixer__d_first_T_5; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_2_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_2_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_2 = ~fixer_a_notFIFO_2; // @[Mux.scala:30:73] wire fixer__T_34 = fixer_x1_anonIn_1_d_ready & fixer_x1_anonIn_1_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_1_a_valid = fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_1_a_ready = fixer__anonIn_a_ready_T_8; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_2; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_2; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_2 = 4'h1 << fixer_x1_anonIn_1_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_2 = fixer_a_first_2 & fixer__a_first_T_2 & ~fixer_a_notFIFO_2 ? fixer__SourceIdSet_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_2 = 4'h1 << fixer_x1_anonIn_1_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_2 = fixer_d_first_2 & fixer__T_34 ? fixer__SourceIdClear_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_2 = fixer_SourceIdFIFOed_2 | fixer_SourceIdSet_2; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_2 = &fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35, :127:41] wire [32:0] fixer__a_notFIFO_T_94 = {1'h0, fixer__a_notFIFO_T_93}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_95 = fixer__a_notFIFO_T_94 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_96 = fixer__a_notFIFO_T_95; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_97 = fixer__a_notFIFO_T_96 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_98 = {fixer_x1_anonIn_2_a_bits_address[31:17], fixer_x1_anonIn_2_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_99 = {1'h0, fixer__a_notFIFO_T_98}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_100 = fixer__a_notFIFO_T_99 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_101 = fixer__a_notFIFO_T_100; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_102 = fixer__a_notFIFO_T_101 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_103 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_104 = {1'h0, fixer__a_notFIFO_T_103}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_105 = fixer__a_notFIFO_T_104 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_106 = fixer__a_notFIFO_T_105; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_107 = fixer__a_notFIFO_T_106 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_108 = fixer__a_notFIFO_T_97 | fixer__a_notFIFO_T_102; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_109 = fixer__a_notFIFO_T_108 | fixer__a_notFIFO_T_107; // @[Parameters.scala:629:89] wire [31:0] fixer__a_notFIFO_T_110 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_111 = {1'h0, fixer__a_notFIFO_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_112 = fixer__a_notFIFO_T_111 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_113 = fixer__a_notFIFO_T_112; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_114 = fixer__a_notFIFO_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] fixer__a_notFIFO_T_115 = fixer_x1_anonIn_2_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] fixer__a_notFIFO_T_116 = {1'h0, fixer__a_notFIFO_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] fixer__a_notFIFO_T_117 = fixer__a_notFIFO_T_116 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] fixer__a_notFIFO_T_118 = fixer__a_notFIFO_T_117; // @[Parameters.scala:137:46] wire fixer__a_notFIFO_T_119 = fixer__a_notFIFO_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire fixer__a_notFIFO_T_120 = fixer__a_notFIFO_T_114 | fixer__a_notFIFO_T_119; // @[Parameters.scala:629:89] wire fixer__a_notFIFO_T_122 = fixer__a_notFIFO_T_120; // @[Mux.scala:30:73] wire fixer__a_notFIFO_T_123 = fixer__a_notFIFO_T_122; // @[Mux.scala:30:73] wire fixer_a_notFIFO_3 = fixer__a_notFIFO_T_123; // @[Mux.scala:30:73] wire [32:0] fixer__a_id_T_16 = {1'h0, fixer__a_id_T_15}; // @[Parameters.scala:137:{31,41}] wire fixer__a_first_T_3 = fixer_x1_anonIn_2_a_ready & fixer_x1_anonIn_2_a_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__a_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonIn_2_a_bits_size; // @[package.scala:243:71] wire [11:0] fixer__a_first_beats1_decode_T_10 = fixer__a_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__a_first_beats1_decode_T_11 = ~fixer__a_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] fixer_a_first_beats1_decode_3 = fixer__a_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire fixer__a_first_beats1_opdata_T_3 = fixer_x1_anonIn_2_a_bits_opcode[2]; // @[Edges.scala:92:37] wire fixer_a_first_beats1_opdata_3 = ~fixer__a_first_beats1_opdata_T_3; // @[Edges.scala:92:{28,37}] wire [8:0] fixer_a_first_beats1_3 = fixer_a_first_beats1_opdata_3 ? fixer_a_first_beats1_decode_3 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] fixer_a_first_counter_3; // @[Edges.scala:229:27] wire [9:0] fixer__a_first_counter1_T_3 = {1'h0, fixer_a_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_a_first_counter1_3 = fixer__a_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire fixer_a_first_3 = fixer_a_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__a_first_last_T_6 = fixer_a_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__a_first_last_T_7 = fixer_a_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_a_first_last_3 = fixer__a_first_last_T_6 | fixer__a_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire fixer_a_first_done_3 = fixer_a_first_last_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] fixer__a_first_count_T_3 = ~fixer_a_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_a_first_count_3 = fixer_a_first_beats1_3 & fixer__a_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__a_first_counter_T_3 = fixer_a_first_3 ? fixer_a_first_beats1_3 : fixer_a_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_6 = fixer_x1_anonOut_2_d_ready & fixer_x1_anonOut_2_d_valid; // @[Decoupled.scala:51:35] wire [26:0] fixer__d_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonOut_2_d_bits_size; // @[package.scala:243:71] wire [11:0] fixer__d_first_beats1_decode_T_10 = fixer__d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] fixer__d_first_beats1_decode_T_11 = ~fixer__d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] fixer_d_first_beats1_decode_3 = fixer__d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire fixer_d_first_beats1_opdata_3 = fixer_x1_anonOut_2_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] fixer_d_first_beats1_3 = fixer_d_first_beats1_opdata_3 ? fixer_d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] fixer_d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] fixer__d_first_counter1_T_3 = {1'h0, fixer_d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] fixer_d_first_counter1_3 = fixer__d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire fixer_d_first_first_3 = fixer_d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire fixer__d_first_last_T_6 = fixer_d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire fixer__d_first_last_T_7 = fixer_d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire fixer_d_first_last_3 = fixer__d_first_last_T_6 | fixer__d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire fixer_d_first_done_3 = fixer_d_first_last_3 & fixer__d_first_T_6; // @[Decoupled.scala:51:35] wire [8:0] fixer__d_first_count_T_3 = ~fixer_d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] fixer_d_first_count_3 = fixer_d_first_beats1_3 & fixer__d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] fixer__d_first_counter_T_3 = fixer_d_first_first_3 ? fixer_d_first_beats1_3 : fixer_d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire fixer__d_first_T_7 = fixer_x1_anonOut_2_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire fixer_d_first_3 = fixer_d_first_first_3 & fixer__d_first_T_7; // @[FIFOFixer.scala:75:{42,63}] reg fixer_flight_3_0; // @[FIFOFixer.scala:79:27] reg fixer_flight_3_1; // @[FIFOFixer.scala:79:27] reg fixer_flight_3_2; // @[FIFOFixer.scala:79:27] wire fixer__flight_T_3 = ~fixer_a_notFIFO_3; // @[Mux.scala:30:73] wire fixer__T_50 = fixer_x1_anonIn_2_d_ready & fixer_x1_anonIn_2_d_valid; // @[Decoupled.scala:51:35] assign fixer_x1_anonOut_2_a_valid = fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33] assign fixer_x1_anonIn_2_a_ready = fixer__anonIn_a_ready_T_11; // @[FIFOFixer.scala:96:33] reg [2:0] fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35] wire [2:0] fixer_SourceIdSet_3; // @[FIFOFixer.scala:116:36] wire [2:0] fixer_SourceIdClear_3; // @[FIFOFixer.scala:117:38] wire [3:0] fixer__SourceIdSet_T_3 = 4'h1 << fixer_x1_anonIn_2_a_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdSet_3 = fixer_a_first_3 & fixer__a_first_T_3 & ~fixer_a_notFIFO_3 ? fixer__SourceIdSet_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [3:0] fixer__SourceIdClear_T_3 = 4'h1 << fixer_x1_anonIn_2_d_bits_source; // @[OneHot.scala:58:35] assign fixer_SourceIdClear_3 = fixer_d_first_3 & fixer__T_50 ? fixer__SourceIdClear_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35] wire [2:0] fixer__SourceIdFIFOed_T_3 = fixer_SourceIdFIFOed_3 | fixer_SourceIdSet_3; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire fixer_allIDs_FIFOed_3 = &fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35, :127:41] wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_b_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_c_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_tlMasterClockXingIn_e_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_valid = coupler_from_rockettile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_opcode = coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_param = coupler_from_rockettile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_size = coupler_from_rockettile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_source = coupler_from_rockettile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_address = coupler_from_rockettile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_mask = coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_data = coupler_from_rockettile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_b_ready = coupler_from_rockettile_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_b_valid = coupler_from_rockettile_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_b_bits_opcode = coupler_from_rockettile_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_b_bits_param = coupler_from_rockettile_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlOut_b_bits_size = coupler_from_rockettile_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_b_bits_source = coupler_from_rockettile_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlOut_b_bits_address = coupler_from_rockettile_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_tlOut_b_bits_mask = coupler_from_rockettile_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlOut_b_bits_data = coupler_from_rockettile_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_b_bits_corrupt = coupler_from_rockettile_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_c_ready = coupler_from_rockettile_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_valid = coupler_from_rockettile_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_opcode = coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_param = coupler_from_rockettile_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_size = coupler_from_rockettile_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_source = coupler_from_rockettile_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_address = coupler_from_rockettile_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_data = coupler_from_rockettile_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_c_bits_corrupt = coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_d_ready = coupler_from_rockettile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_e_ready = coupler_from_rockettile_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_e_valid = coupler_from_rockettile_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_0_e_bits_sink = coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_b_ready = coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_b_valid = coupler_from_rockettile_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_b_bits_opcode = coupler_from_rockettile_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_b_bits_param = coupler_from_rockettile_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlIn_b_bits_size = coupler_from_rockettile_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_b_bits_source = coupler_from_rockettile_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlIn_b_bits_address = coupler_from_rockettile_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlIn_b_bits_mask = coupler_from_rockettile_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlIn_b_bits_data = coupler_from_rockettile_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_b_bits_corrupt = coupler_from_rockettile_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_c_ready = coupler_from_rockettile_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_valid = coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_opcode = coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_param = coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_size = coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_source = coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_address = coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_data = coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_e_ready = coupler_from_rockettile_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_e_valid = coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_out_e_bits_sink = coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_b_ready = coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_valid = coupler_from_rockettile_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_b_bits_opcode = coupler_from_rockettile_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_param = coupler_from_rockettile_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_b_bits_size = coupler_from_rockettile_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_source = coupler_from_rockettile_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_b_bits_address = coupler_from_rockettile_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferOut_b_bits_mask = coupler_from_rockettile_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_b_bits_data = coupler_from_rockettile_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_ready = coupler_from_rockettile_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_valid = coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_opcode = coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_param = coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_size = coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_source = coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_address = coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_data = coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_c_bits_corrupt = coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_e_ready = coupler_from_rockettile_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_e_valid = coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_tlOut_e_bits_sink = coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_b_ready = coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_valid = coupler_from_rockettile_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_b_bits_opcode = coupler_from_rockettile_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_param = coupler_from_rockettile_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_b_bits_size = coupler_from_rockettile_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_source = coupler_from_rockettile_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_b_bits_address = coupler_from_rockettile_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_no_bufferIn_b_bits_mask = coupler_from_rockettile_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_b_bits_data = coupler_from_rockettile_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_ready = coupler_from_rockettile_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_valid = coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_opcode = coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_param = coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_size = coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_source = coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_address = coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_data = coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_c_bits_corrupt = coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_e_ready = coupler_from_rockettile_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_e_valid = coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlIn_e_bits_sink = coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_b_ready = coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_valid = coupler_from_rockettile_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_ready = coupler_from_rockettile_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_valid = coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_opcode = coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_param = coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_size = coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_source = coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_address = coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_data = coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_e_ready = coupler_from_rockettile_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_e_valid = coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_no_bufferOut_e_bits_sink = coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_b_ready = coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_valid = coupler_from_rockettile_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_c_ready = coupler_from_rockettile_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_valid = coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_param = coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_size = coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_source = coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_address = coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_data = coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingIn_e_ready = coupler_from_rockettile_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_e_valid = coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_no_bufferIn_e_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_b_ready = coupler_from_rockettile_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_valid = coupler_from_rockettile_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_tlMasterClockXingOut_e_valid = coupler_from_rockettile_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_1_tlMasterClockXingIn_e_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_1_tlOut_a_ready = coupler_from_rockettile_1_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_1_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_b_ready = coupler_from_rockettile_1_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_b_valid = coupler_from_rockettile_1_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_b_bits_opcode = coupler_from_rockettile_1_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_param = coupler_from_rockettile_1_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlOut_b_bits_size = coupler_from_rockettile_1_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_source = coupler_from_rockettile_1_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlOut_b_bits_address = coupler_from_rockettile_1_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_1_tlOut_b_bits_mask = coupler_from_rockettile_1_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlOut_b_bits_data = coupler_from_rockettile_1_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_b_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_c_ready = coupler_from_rockettile_1_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_valid = coupler_from_rockettile_1_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_opcode = coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_param = coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_size = coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_source = coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_address = coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_data = coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_1_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlOut_d_valid = coupler_from_rockettile_1_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_opcode = coupler_from_rockettile_1_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_param = coupler_from_rockettile_1_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlOut_d_bits_size = coupler_from_rockettile_1_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_source = coupler_from_rockettile_1_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_sink = coupler_from_rockettile_1_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_d_bits_denied = coupler_from_rockettile_1_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlOut_d_bits_data = coupler_from_rockettile_1_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_d_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_e_ready = coupler_from_rockettile_1_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_valid = coupler_from_rockettile_1_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_1_e_bits_sink = coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_1_tlIn_a_ready = coupler_from_rockettile_1_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_valid = coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_opcode = coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_param = coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_size = coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_source = coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_address = coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_mask = coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_data = coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_b_ready = coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_b_valid = coupler_from_rockettile_1_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_b_bits_opcode = coupler_from_rockettile_1_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_param = coupler_from_rockettile_1_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlIn_b_bits_size = coupler_from_rockettile_1_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_source = coupler_from_rockettile_1_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlIn_b_bits_address = coupler_from_rockettile_1_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlIn_b_bits_mask = coupler_from_rockettile_1_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlIn_b_bits_data = coupler_from_rockettile_1_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_b_bits_corrupt = coupler_from_rockettile_1_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_c_ready = coupler_from_rockettile_1_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_valid = coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_opcode = coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_param = coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_size = coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_source = coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_address = coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_data = coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_d_ready = coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_tlIn_d_valid = coupler_from_rockettile_1_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_opcode = coupler_from_rockettile_1_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_param = coupler_from_rockettile_1_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlIn_d_bits_size = coupler_from_rockettile_1_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_source = coupler_from_rockettile_1_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_sink = coupler_from_rockettile_1_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_d_bits_denied = coupler_from_rockettile_1_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlIn_d_bits_data = coupler_from_rockettile_1_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_d_bits_corrupt = coupler_from_rockettile_1_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_e_ready = coupler_from_rockettile_1_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_e_valid = coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_out_e_bits_sink = coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_1_no_bufferOut_a_ready = coupler_from_rockettile_1_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_valid = coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_opcode = coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_param = coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_size = coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_source = coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_address = coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_mask = coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_data = coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_a_bits_corrupt = coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_b_ready = coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_valid = coupler_from_rockettile_1_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_b_bits_opcode = coupler_from_rockettile_1_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_param = coupler_from_rockettile_1_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_b_bits_size = coupler_from_rockettile_1_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_source = coupler_from_rockettile_1_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_b_bits_address = coupler_from_rockettile_1_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferOut_b_bits_mask = coupler_from_rockettile_1_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_b_bits_data = coupler_from_rockettile_1_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_1_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_ready = coupler_from_rockettile_1_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_valid = coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_opcode = coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_param = coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_size = coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_source = coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_address = coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_data = coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_c_bits_corrupt = coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_d_ready = coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_valid = coupler_from_rockettile_1_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_opcode = coupler_from_rockettile_1_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_param = coupler_from_rockettile_1_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferOut_d_bits_size = coupler_from_rockettile_1_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_source = coupler_from_rockettile_1_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_sink = coupler_from_rockettile_1_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_bits_denied = coupler_from_rockettile_1_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferOut_d_bits_data = coupler_from_rockettile_1_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_1_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_e_ready = coupler_from_rockettile_1_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_e_valid = coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_tlOut_e_bits_sink = coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_ready = coupler_from_rockettile_1_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_valid = coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_opcode = coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_param = coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_size = coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_source = coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_address = coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_mask = coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_data = coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_a_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_b_ready = coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_valid = coupler_from_rockettile_1_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_b_bits_opcode = coupler_from_rockettile_1_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_param = coupler_from_rockettile_1_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_b_bits_size = coupler_from_rockettile_1_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_source = coupler_from_rockettile_1_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_b_bits_address = coupler_from_rockettile_1_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_no_bufferIn_b_bits_mask = coupler_from_rockettile_1_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_b_bits_data = coupler_from_rockettile_1_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_ready = coupler_from_rockettile_1_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_valid = coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_opcode = coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_param = coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_size = coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_source = coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_address = coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_data = coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_c_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_d_ready = coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_valid = coupler_from_rockettile_1_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_opcode = coupler_from_rockettile_1_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_param = coupler_from_rockettile_1_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_no_bufferIn_d_bits_size = coupler_from_rockettile_1_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_source = coupler_from_rockettile_1_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_sink = coupler_from_rockettile_1_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_bits_denied = coupler_from_rockettile_1_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_no_bufferIn_d_bits_data = coupler_from_rockettile_1_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_e_ready = coupler_from_rockettile_1_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_e_valid = coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlIn_e_bits_sink = coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_ready = coupler_from_rockettile_1_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_valid = coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_opcode = coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_param = coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_size = coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_source = coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_address = coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_mask = coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_data = coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_b_ready = coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_valid = coupler_from_rockettile_1_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_1_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_1_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_1_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_1_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_1_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_1_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_1_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_ready = coupler_from_rockettile_1_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_valid = coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_opcode = coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_param = coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_size = coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_source = coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_address = coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_data = coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_d_ready = coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_valid = coupler_from_rockettile_1_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_1_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_1_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_1_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_1_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_1_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_1_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_1_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_e_ready = coupler_from_rockettile_1_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_e_valid = coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_1_no_bufferOut_e_bits_sink = coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_a_ready = coupler_from_rockettile_1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_valid = coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_b_ready = coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_valid = coupler_from_rockettile_1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_c_ready = coupler_from_rockettile_1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_valid = coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_d_ready = coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_valid = coupler_from_rockettile_1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingIn_e_ready = coupler_from_rockettile_1_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_e_valid = coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_no_bufferIn_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_valid = coupler_from_rockettile_1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_b_ready = coupler_from_rockettile_1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_valid = coupler_from_rockettile_1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_d_ready = coupler_from_rockettile_1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_e_valid = coupler_from_rockettile_1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_2_tlMasterClockXingIn_e_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_2_tlOut_a_ready = coupler_from_rockettile_2_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_valid = coupler_from_rockettile_2_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_opcode = coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_param = coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_size = coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_source = coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_address = coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_mask = coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_data = coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_b_ready = coupler_from_rockettile_2_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_b_valid = coupler_from_rockettile_2_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_b_bits_opcode = coupler_from_rockettile_2_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_param = coupler_from_rockettile_2_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlOut_b_bits_size = coupler_from_rockettile_2_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_source = coupler_from_rockettile_2_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlOut_b_bits_address = coupler_from_rockettile_2_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_2_tlOut_b_bits_mask = coupler_from_rockettile_2_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlOut_b_bits_data = coupler_from_rockettile_2_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_b_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_c_ready = coupler_from_rockettile_2_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_valid = coupler_from_rockettile_2_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_opcode = coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_param = coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_size = coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_source = coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_address = coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_data = coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_d_ready = coupler_from_rockettile_2_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlOut_d_valid = coupler_from_rockettile_2_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_opcode = coupler_from_rockettile_2_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_param = coupler_from_rockettile_2_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlOut_d_bits_size = coupler_from_rockettile_2_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_source = coupler_from_rockettile_2_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_sink = coupler_from_rockettile_2_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_d_bits_denied = coupler_from_rockettile_2_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlOut_d_bits_data = coupler_from_rockettile_2_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_d_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_e_ready = coupler_from_rockettile_2_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_valid = coupler_from_rockettile_2_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_2_e_bits_sink = coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_2_tlIn_a_ready = coupler_from_rockettile_2_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_valid = coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_opcode = coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_param = coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_size = coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_source = coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_address = coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_mask = coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_data = coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_b_ready = coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_b_valid = coupler_from_rockettile_2_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_b_bits_opcode = coupler_from_rockettile_2_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_param = coupler_from_rockettile_2_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlIn_b_bits_size = coupler_from_rockettile_2_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_source = coupler_from_rockettile_2_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlIn_b_bits_address = coupler_from_rockettile_2_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlIn_b_bits_mask = coupler_from_rockettile_2_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlIn_b_bits_data = coupler_from_rockettile_2_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_b_bits_corrupt = coupler_from_rockettile_2_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_c_ready = coupler_from_rockettile_2_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_valid = coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_opcode = coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_param = coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_size = coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_source = coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_address = coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_data = coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_d_ready = coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_tlIn_d_valid = coupler_from_rockettile_2_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_opcode = coupler_from_rockettile_2_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_param = coupler_from_rockettile_2_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlIn_d_bits_size = coupler_from_rockettile_2_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_source = coupler_from_rockettile_2_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_sink = coupler_from_rockettile_2_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_d_bits_denied = coupler_from_rockettile_2_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlIn_d_bits_data = coupler_from_rockettile_2_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_d_bits_corrupt = coupler_from_rockettile_2_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_e_ready = coupler_from_rockettile_2_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_e_valid = coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_out_e_bits_sink = coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_2_no_bufferOut_a_ready = coupler_from_rockettile_2_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_valid = coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_opcode = coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_param = coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_size = coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_source = coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_address = coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_mask = coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_data = coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_a_bits_corrupt = coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_b_ready = coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_valid = coupler_from_rockettile_2_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_b_bits_opcode = coupler_from_rockettile_2_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_param = coupler_from_rockettile_2_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_b_bits_size = coupler_from_rockettile_2_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_source = coupler_from_rockettile_2_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_b_bits_address = coupler_from_rockettile_2_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferOut_b_bits_mask = coupler_from_rockettile_2_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_b_bits_data = coupler_from_rockettile_2_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_2_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_ready = coupler_from_rockettile_2_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_valid = coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_opcode = coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_param = coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_size = coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_source = coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_address = coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_data = coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_c_bits_corrupt = coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_d_ready = coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_valid = coupler_from_rockettile_2_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_opcode = coupler_from_rockettile_2_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_param = coupler_from_rockettile_2_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferOut_d_bits_size = coupler_from_rockettile_2_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_source = coupler_from_rockettile_2_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_sink = coupler_from_rockettile_2_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_bits_denied = coupler_from_rockettile_2_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferOut_d_bits_data = coupler_from_rockettile_2_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_2_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_e_ready = coupler_from_rockettile_2_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_e_valid = coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_tlOut_e_bits_sink = coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_ready = coupler_from_rockettile_2_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_valid = coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_opcode = coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_param = coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_size = coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_source = coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_address = coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_mask = coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_data = coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_a_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_b_ready = coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_valid = coupler_from_rockettile_2_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_b_bits_opcode = coupler_from_rockettile_2_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_param = coupler_from_rockettile_2_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_b_bits_size = coupler_from_rockettile_2_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_source = coupler_from_rockettile_2_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_b_bits_address = coupler_from_rockettile_2_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_no_bufferIn_b_bits_mask = coupler_from_rockettile_2_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_b_bits_data = coupler_from_rockettile_2_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_ready = coupler_from_rockettile_2_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_valid = coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_opcode = coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_param = coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_size = coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_source = coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_address = coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_data = coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_c_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_d_ready = coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_valid = coupler_from_rockettile_2_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_opcode = coupler_from_rockettile_2_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_param = coupler_from_rockettile_2_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_no_bufferIn_d_bits_size = coupler_from_rockettile_2_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_source = coupler_from_rockettile_2_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_sink = coupler_from_rockettile_2_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_bits_denied = coupler_from_rockettile_2_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_no_bufferIn_d_bits_data = coupler_from_rockettile_2_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_e_ready = coupler_from_rockettile_2_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_e_valid = coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlIn_e_bits_sink = coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_ready = coupler_from_rockettile_2_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_valid = coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_opcode = coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_param = coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_size = coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_source = coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_address = coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_mask = coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_data = coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_b_ready = coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_valid = coupler_from_rockettile_2_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_2_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_2_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_2_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_2_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_2_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_2_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_2_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_ready = coupler_from_rockettile_2_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_valid = coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_opcode = coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_param = coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_size = coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_source = coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_address = coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_data = coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_d_ready = coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_valid = coupler_from_rockettile_2_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_2_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_2_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_2_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_2_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_2_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_2_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_2_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_e_ready = coupler_from_rockettile_2_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_e_valid = coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_2_no_bufferOut_e_bits_sink = coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_a_ready = coupler_from_rockettile_2_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_valid = coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_b_ready = coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_valid = coupler_from_rockettile_2_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_c_ready = coupler_from_rockettile_2_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_valid = coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_d_ready = coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_valid = coupler_from_rockettile_2_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingIn_e_ready = coupler_from_rockettile_2_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_e_valid = coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_no_bufferIn_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_valid = coupler_from_rockettile_2_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_b_ready = coupler_from_rockettile_2_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_valid = coupler_from_rockettile_2_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_d_ready = coupler_from_rockettile_2_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_e_valid = coupler_from_rockettile_2_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9] wire coupler_from_rockettile_3_tlMasterClockXingIn_e_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_rockettile_3_tlOut_a_ready = coupler_from_rockettile_3_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_valid = coupler_from_rockettile_3_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_opcode = coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_param = coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_size = coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_source = coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_address = coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_mask = coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_data = coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_b_ready = coupler_from_rockettile_3_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_b_valid = coupler_from_rockettile_3_auto_tl_out_b_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_b_bits_opcode = coupler_from_rockettile_3_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_param = coupler_from_rockettile_3_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlOut_b_bits_size = coupler_from_rockettile_3_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_source = coupler_from_rockettile_3_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlOut_b_bits_address = coupler_from_rockettile_3_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_3_tlOut_b_bits_mask = coupler_from_rockettile_3_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlOut_b_bits_data = coupler_from_rockettile_3_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_b_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_c_ready = coupler_from_rockettile_3_auto_tl_out_c_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_valid = coupler_from_rockettile_3_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_opcode = coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_param = coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9] wire [3:0] coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_size = coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9] wire [1:0] coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_source = coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9] wire [31:0] coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_address = coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9] wire [63:0] coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_data = coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_d_ready = coupler_from_rockettile_3_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlOut_d_valid = coupler_from_rockettile_3_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_opcode = coupler_from_rockettile_3_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_param = coupler_from_rockettile_3_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlOut_d_bits_size = coupler_from_rockettile_3_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_source = coupler_from_rockettile_3_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_sink = coupler_from_rockettile_3_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_d_bits_denied = coupler_from_rockettile_3_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlOut_d_bits_data = coupler_from_rockettile_3_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_d_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_e_ready = coupler_from_rockettile_3_auto_tl_out_e_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_e_valid = coupler_from_rockettile_3_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9] wire [2:0] coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] assign fixer_auto_anon_in_3_e_bits_sink = coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9] wire coupler_from_rockettile_3_tlIn_a_ready = coupler_from_rockettile_3_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_valid = coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_opcode = coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_param = coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_size = coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_source = coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_address = coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_mask = coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_data = coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_b_ready = coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_b_valid = coupler_from_rockettile_3_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_b_bits_opcode = coupler_from_rockettile_3_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_param = coupler_from_rockettile_3_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlIn_b_bits_size = coupler_from_rockettile_3_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_source = coupler_from_rockettile_3_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlIn_b_bits_address = coupler_from_rockettile_3_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlIn_b_bits_mask = coupler_from_rockettile_3_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlIn_b_bits_data = coupler_from_rockettile_3_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_b_bits_corrupt = coupler_from_rockettile_3_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_c_ready = coupler_from_rockettile_3_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_valid = coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_opcode = coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_param = coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_size = coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_source = coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_address = coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_data = coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_d_ready = coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_tlIn_d_valid = coupler_from_rockettile_3_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_opcode = coupler_from_rockettile_3_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_param = coupler_from_rockettile_3_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlIn_d_bits_size = coupler_from_rockettile_3_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_source = coupler_from_rockettile_3_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_sink = coupler_from_rockettile_3_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_d_bits_denied = coupler_from_rockettile_3_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlIn_d_bits_data = coupler_from_rockettile_3_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_d_bits_corrupt = coupler_from_rockettile_3_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_e_ready = coupler_from_rockettile_3_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_e_valid = coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_out_e_bits_sink = coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_rockettile_3_no_bufferOut_a_ready = coupler_from_rockettile_3_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_valid = coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_opcode = coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_param = coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_size = coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_source = coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_address = coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_mask = coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_data = coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_a_bits_corrupt = coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_b_ready = coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_valid = coupler_from_rockettile_3_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_b_bits_opcode = coupler_from_rockettile_3_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_param = coupler_from_rockettile_3_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_b_bits_size = coupler_from_rockettile_3_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_source = coupler_from_rockettile_3_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_b_bits_address = coupler_from_rockettile_3_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferOut_b_bits_mask = coupler_from_rockettile_3_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_b_bits_data = coupler_from_rockettile_3_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_3_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_ready = coupler_from_rockettile_3_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_valid = coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_opcode = coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_param = coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_size = coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_source = coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_address = coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_data = coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_c_bits_corrupt = coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_d_ready = coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_valid = coupler_from_rockettile_3_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_opcode = coupler_from_rockettile_3_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_param = coupler_from_rockettile_3_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferOut_d_bits_size = coupler_from_rockettile_3_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_source = coupler_from_rockettile_3_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_sink = coupler_from_rockettile_3_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_bits_denied = coupler_from_rockettile_3_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferOut_d_bits_data = coupler_from_rockettile_3_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_3_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_e_ready = coupler_from_rockettile_3_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_e_valid = coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_tlOut_e_bits_sink = coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_ready = coupler_from_rockettile_3_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_valid = coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_opcode = coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_param = coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_size = coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_source = coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_address = coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_mask = coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_data = coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_a_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_b_ready = coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_valid = coupler_from_rockettile_3_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_b_bits_opcode = coupler_from_rockettile_3_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_param = coupler_from_rockettile_3_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_b_bits_size = coupler_from_rockettile_3_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_source = coupler_from_rockettile_3_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_b_bits_address = coupler_from_rockettile_3_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_no_bufferIn_b_bits_mask = coupler_from_rockettile_3_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_b_bits_data = coupler_from_rockettile_3_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_ready = coupler_from_rockettile_3_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_valid = coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_opcode = coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_param = coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_size = coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_source = coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_address = coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_data = coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_c_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_d_ready = coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_valid = coupler_from_rockettile_3_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_opcode = coupler_from_rockettile_3_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_param = coupler_from_rockettile_3_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_no_bufferIn_d_bits_size = coupler_from_rockettile_3_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_source = coupler_from_rockettile_3_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_sink = coupler_from_rockettile_3_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_bits_denied = coupler_from_rockettile_3_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_no_bufferIn_d_bits_data = coupler_from_rockettile_3_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_e_ready = coupler_from_rockettile_3_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_e_valid = coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlIn_e_bits_sink = coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_ready = coupler_from_rockettile_3_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_valid = coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_opcode = coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_param = coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_size = coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_source = coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_address = coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_mask = coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_data = coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_b_ready = coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_valid = coupler_from_rockettile_3_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_3_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_3_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_3_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_3_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_3_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_3_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_3_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_ready = coupler_from_rockettile_3_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_valid = coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_opcode = coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_param = coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_size = coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_source = coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_address = coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_data = coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_d_ready = coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_valid = coupler_from_rockettile_3_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_3_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_3_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_3_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_3_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_3_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_3_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_3_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_e_ready = coupler_from_rockettile_3_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17] wire coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_e_valid = coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] assign coupler_from_rockettile_3_no_bufferOut_e_bits_sink = coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_a_ready = coupler_from_rockettile_3_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_valid = coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_b_ready = coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_valid = coupler_from_rockettile_3_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_c_ready = coupler_from_rockettile_3_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_valid = coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_d_ready = coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_valid = coupler_from_rockettile_3_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingIn_e_ready = coupler_from_rockettile_3_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_e_valid = coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_no_bufferIn_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_valid = coupler_from_rockettile_3_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_b_ready = coupler_from_rockettile_3_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_valid = coupler_from_rockettile_3_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_d_ready = coupler_from_rockettile_3_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_e_valid = coupler_from_rockettile_3_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35] wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35] wire fixer__T_17 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35] wire fixer__T_19 = fixer_d_first_1 & fixer__T_18; // @[Decoupled.scala:51:35] wire fixer__T_33 = fixer_a_first_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35] wire fixer__T_35 = fixer_d_first_2 & fixer__T_34; // @[Decoupled.scala:51:35] wire fixer__T_49 = fixer_a_first_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35] wire fixer__T_51 = fixer_d_first_3 & fixer__T_50; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31] fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27] fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_1 <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_2 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_2 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_2_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_2_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_2 <= 3'h0; // @[FIFOFixer.scala:115:35] fixer_a_first_counter_3 <= 9'h0; // @[Edges.scala:229:27] fixer_d_first_counter_3 <= 9'h0; // @[Edges.scala:229:27] fixer_flight_3_0 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3_1 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_flight_3_2 <= 1'h0; // @[FIFOFixer.scala:79:27] fixer_SourceIdFIFOed_3 <= 3'h0; // @[FIFOFixer.scala:115:35] end else begin // @[LazyModuleImp.scala:155:31] if (fixer__a_first_T) // @[Decoupled.scala:51:35] fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T) // @[Decoupled.scala:51:35] fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21] fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_1) // @[Decoupled.scala:51:35] fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_2) // @[Decoupled.scala:51:35] fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21] fixer_flight_1_0 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h0) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_1 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h1) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_1_2 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h2) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_2) // @[Decoupled.scala:51:35] fixer_a_first_counter_2 <= fixer__a_first_counter_T_2; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_4) // @[Decoupled.scala:51:35] fixer_d_first_counter_2 <= fixer__d_first_counter_T_2; // @[Edges.scala:229:27, :236:21] fixer_flight_2_0 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h0) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h0 ? fixer__flight_T_2 : fixer_flight_2_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_1 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h1) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h1 ? fixer__flight_T_2 : fixer_flight_2_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_2_2 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h2) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h2 ? fixer__flight_T_2 : fixer_flight_2_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_2 <= fixer__SourceIdFIFOed_T_2; // @[FIFOFixer.scala:115:35, :126:40] if (fixer__a_first_T_3) // @[Decoupled.scala:51:35] fixer_a_first_counter_3 <= fixer__a_first_counter_T_3; // @[Edges.scala:229:27, :236:21] if (fixer__d_first_T_6) // @[Decoupled.scala:51:35] fixer_d_first_counter_3 <= fixer__d_first_counter_T_3; // @[Edges.scala:229:27, :236:21] fixer_flight_3_0 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h0) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h0 ? fixer__flight_T_3 : fixer_flight_3_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3_1 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h1) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h1 ? fixer__flight_T_3 : fixer_flight_3_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_flight_3_2 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h2) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h2 ? fixer__flight_T_3 : fixer_flight_3_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}] fixer_SourceIdFIFOed_3 <= fixer__SourceIdFIFOed_T_3; // @[FIFOFixer.scala:115:35, :126:40] end always @(posedge) FixedClockBroadcast_7_1 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLXbar_csbus0_i4_o1_a32d64s4k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_3_a_ready (fixer_auto_anon_out_3_a_ready), .auto_anon_in_3_a_valid (fixer_auto_anon_out_3_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_opcode (fixer_auto_anon_out_3_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_param (fixer_auto_anon_out_3_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_size (fixer_auto_anon_out_3_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_source (fixer_auto_anon_out_3_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_address (fixer_auto_anon_out_3_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_mask (fixer_auto_anon_out_3_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_data (fixer_auto_anon_out_3_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_a_bits_corrupt (fixer_auto_anon_out_3_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_b_ready (fixer_auto_anon_out_3_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_b_valid (fixer_auto_anon_out_3_b_valid), .auto_anon_in_3_b_bits_opcode (fixer_auto_anon_out_3_b_bits_opcode), .auto_anon_in_3_b_bits_param (fixer_auto_anon_out_3_b_bits_param), .auto_anon_in_3_b_bits_size (fixer_auto_anon_out_3_b_bits_size), .auto_anon_in_3_b_bits_source (fixer_auto_anon_out_3_b_bits_source), .auto_anon_in_3_b_bits_address (fixer_auto_anon_out_3_b_bits_address), .auto_anon_in_3_b_bits_mask (fixer_auto_anon_out_3_b_bits_mask), .auto_anon_in_3_b_bits_data (fixer_auto_anon_out_3_b_bits_data), .auto_anon_in_3_b_bits_corrupt (fixer_auto_anon_out_3_b_bits_corrupt), .auto_anon_in_3_c_ready (fixer_auto_anon_out_3_c_ready), .auto_anon_in_3_c_valid (fixer_auto_anon_out_3_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_opcode (fixer_auto_anon_out_3_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_param (fixer_auto_anon_out_3_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_size (fixer_auto_anon_out_3_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_source (fixer_auto_anon_out_3_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_address (fixer_auto_anon_out_3_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_data (fixer_auto_anon_out_3_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_c_bits_corrupt (fixer_auto_anon_out_3_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_d_ready (fixer_auto_anon_out_3_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_d_valid (fixer_auto_anon_out_3_d_valid), .auto_anon_in_3_d_bits_opcode (fixer_auto_anon_out_3_d_bits_opcode), .auto_anon_in_3_d_bits_param (fixer_auto_anon_out_3_d_bits_param), .auto_anon_in_3_d_bits_size (fixer_auto_anon_out_3_d_bits_size), .auto_anon_in_3_d_bits_source (fixer_auto_anon_out_3_d_bits_source), .auto_anon_in_3_d_bits_sink (fixer_auto_anon_out_3_d_bits_sink), .auto_anon_in_3_d_bits_denied (fixer_auto_anon_out_3_d_bits_denied), .auto_anon_in_3_d_bits_data (fixer_auto_anon_out_3_d_bits_data), .auto_anon_in_3_d_bits_corrupt (fixer_auto_anon_out_3_d_bits_corrupt), .auto_anon_in_3_e_ready (fixer_auto_anon_out_3_e_ready), .auto_anon_in_3_e_valid (fixer_auto_anon_out_3_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_3_e_bits_sink (fixer_auto_anon_out_3_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_ready (fixer_auto_anon_out_2_a_ready), .auto_anon_in_2_a_valid (fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_opcode (fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_param (fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_size (fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_source (fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_address (fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_mask (fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_data (fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_a_bits_corrupt (fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_ready (fixer_auto_anon_out_2_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_b_valid (fixer_auto_anon_out_2_b_valid), .auto_anon_in_2_b_bits_opcode (fixer_auto_anon_out_2_b_bits_opcode), .auto_anon_in_2_b_bits_param (fixer_auto_anon_out_2_b_bits_param), .auto_anon_in_2_b_bits_size (fixer_auto_anon_out_2_b_bits_size), .auto_anon_in_2_b_bits_source (fixer_auto_anon_out_2_b_bits_source), .auto_anon_in_2_b_bits_address (fixer_auto_anon_out_2_b_bits_address), .auto_anon_in_2_b_bits_mask (fixer_auto_anon_out_2_b_bits_mask), .auto_anon_in_2_b_bits_data (fixer_auto_anon_out_2_b_bits_data), .auto_anon_in_2_b_bits_corrupt (fixer_auto_anon_out_2_b_bits_corrupt), .auto_anon_in_2_c_ready (fixer_auto_anon_out_2_c_ready), .auto_anon_in_2_c_valid (fixer_auto_anon_out_2_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_opcode (fixer_auto_anon_out_2_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_param (fixer_auto_anon_out_2_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_size (fixer_auto_anon_out_2_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_source (fixer_auto_anon_out_2_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_address (fixer_auto_anon_out_2_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_data (fixer_auto_anon_out_2_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_c_bits_corrupt (fixer_auto_anon_out_2_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_ready (fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_d_valid (fixer_auto_anon_out_2_d_valid), .auto_anon_in_2_d_bits_opcode (fixer_auto_anon_out_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (fixer_auto_anon_out_2_d_bits_param), .auto_anon_in_2_d_bits_size (fixer_auto_anon_out_2_d_bits_size), .auto_anon_in_2_d_bits_source (fixer_auto_anon_out_2_d_bits_source), .auto_anon_in_2_d_bits_sink (fixer_auto_anon_out_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (fixer_auto_anon_out_2_d_bits_denied), .auto_anon_in_2_d_bits_data (fixer_auto_anon_out_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (fixer_auto_anon_out_2_d_bits_corrupt), .auto_anon_in_2_e_ready (fixer_auto_anon_out_2_e_ready), .auto_anon_in_2_e_valid (fixer_auto_anon_out_2_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_2_e_bits_sink (fixer_auto_anon_out_2_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready), .auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_ready (fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_b_valid (fixer_auto_anon_out_1_b_valid), .auto_anon_in_1_b_bits_opcode (fixer_auto_anon_out_1_b_bits_opcode), .auto_anon_in_1_b_bits_param (fixer_auto_anon_out_1_b_bits_param), .auto_anon_in_1_b_bits_size (fixer_auto_anon_out_1_b_bits_size), .auto_anon_in_1_b_bits_source (fixer_auto_anon_out_1_b_bits_source), .auto_anon_in_1_b_bits_address (fixer_auto_anon_out_1_b_bits_address), .auto_anon_in_1_b_bits_mask (fixer_auto_anon_out_1_b_bits_mask), .auto_anon_in_1_b_bits_data (fixer_auto_anon_out_1_b_bits_data), .auto_anon_in_1_b_bits_corrupt (fixer_auto_anon_out_1_b_bits_corrupt), .auto_anon_in_1_c_ready (fixer_auto_anon_out_1_c_ready), .auto_anon_in_1_c_valid (fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_opcode (fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_param (fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_size (fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_source (fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_address (fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_data (fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_c_bits_corrupt (fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid), .auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param), .auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size), .auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source), .auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied), .auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt), .auto_anon_in_1_e_ready (fixer_auto_anon_out_1_e_ready), .auto_anon_in_1_e_valid (fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_1_e_bits_sink (fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready), .auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_b_ready (fixer_auto_anon_out_0_b_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_b_valid (fixer_auto_anon_out_0_b_valid), .auto_anon_in_0_b_bits_opcode (fixer_auto_anon_out_0_b_bits_opcode), .auto_anon_in_0_b_bits_param (fixer_auto_anon_out_0_b_bits_param), .auto_anon_in_0_b_bits_size (fixer_auto_anon_out_0_b_bits_size), .auto_anon_in_0_b_bits_source (fixer_auto_anon_out_0_b_bits_source), .auto_anon_in_0_b_bits_address (fixer_auto_anon_out_0_b_bits_address), .auto_anon_in_0_b_bits_mask (fixer_auto_anon_out_0_b_bits_mask), .auto_anon_in_0_b_bits_data (fixer_auto_anon_out_0_b_bits_data), .auto_anon_in_0_b_bits_corrupt (fixer_auto_anon_out_0_b_bits_corrupt), .auto_anon_in_0_c_ready (fixer_auto_anon_out_0_c_ready), .auto_anon_in_0_c_valid (fixer_auto_anon_out_0_c_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_opcode (fixer_auto_anon_out_0_c_bits_opcode), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_param (fixer_auto_anon_out_0_c_bits_param), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_size (fixer_auto_anon_out_0_c_bits_size), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_source (fixer_auto_anon_out_0_c_bits_source), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_address (fixer_auto_anon_out_0_c_bits_address), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_data (fixer_auto_anon_out_0_c_bits_data), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_c_bits_corrupt (fixer_auto_anon_out_0_c_bits_corrupt), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid), .auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param), .auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size), .auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source), .auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied), .auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt), .auto_anon_in_0_e_ready (fixer_auto_anon_out_0_e_ready), .auto_anon_in_0_e_valid (fixer_auto_anon_out_0_e_valid), // @[FIFOFixer.scala:50:9] .auto_anon_in_0_e_bits_sink (fixer_auto_anon_out_0_e_bits_sink), // @[FIFOFixer.scala:50:9] .auto_anon_out_a_ready (auto_system_bus_xbar_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_a_valid (auto_system_bus_xbar_anon_out_a_valid_0), .auto_anon_out_a_bits_opcode (auto_system_bus_xbar_anon_out_a_bits_opcode_0), .auto_anon_out_a_bits_param (auto_system_bus_xbar_anon_out_a_bits_param_0), .auto_anon_out_a_bits_size (auto_system_bus_xbar_anon_out_a_bits_size_0), .auto_anon_out_a_bits_source (auto_system_bus_xbar_anon_out_a_bits_source_0), .auto_anon_out_a_bits_address (auto_system_bus_xbar_anon_out_a_bits_address_0), .auto_anon_out_a_bits_mask (auto_system_bus_xbar_anon_out_a_bits_mask_0), .auto_anon_out_a_bits_data (auto_system_bus_xbar_anon_out_a_bits_data_0), .auto_anon_out_a_bits_corrupt (auto_system_bus_xbar_anon_out_a_bits_corrupt_0), .auto_anon_out_b_ready (auto_system_bus_xbar_anon_out_b_ready_0), .auto_anon_out_b_valid (auto_system_bus_xbar_anon_out_b_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_opcode (auto_system_bus_xbar_anon_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_param (auto_system_bus_xbar_anon_out_b_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_size (auto_system_bus_xbar_anon_out_b_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_source (auto_system_bus_xbar_anon_out_b_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_address (auto_system_bus_xbar_anon_out_b_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_mask (auto_system_bus_xbar_anon_out_b_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_data (auto_system_bus_xbar_anon_out_b_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_out_b_bits_corrupt (auto_system_bus_xbar_anon_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_out_c_ready (auto_system_bus_xbar_anon_out_c_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_c_valid (auto_system_bus_xbar_anon_out_c_valid_0), .auto_anon_out_c_bits_opcode (auto_system_bus_xbar_anon_out_c_bits_opcode_0), .auto_anon_out_c_bits_param (auto_system_bus_xbar_anon_out_c_bits_param_0), .auto_anon_out_c_bits_size (auto_system_bus_xbar_anon_out_c_bits_size_0), .auto_anon_out_c_bits_source (auto_system_bus_xbar_anon_out_c_bits_source_0), .auto_anon_out_c_bits_address (auto_system_bus_xbar_anon_out_c_bits_address_0), .auto_anon_out_c_bits_data (auto_system_bus_xbar_anon_out_c_bits_data_0), .auto_anon_out_c_bits_corrupt (auto_system_bus_xbar_anon_out_c_bits_corrupt_0), .auto_anon_out_d_ready (auto_system_bus_xbar_anon_out_d_ready_0), .auto_anon_out_d_valid (auto_system_bus_xbar_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_opcode (auto_system_bus_xbar_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_param (auto_system_bus_xbar_anon_out_d_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_size (auto_system_bus_xbar_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_source (auto_system_bus_xbar_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_sink (auto_system_bus_xbar_anon_out_d_bits_sink_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_denied (auto_system_bus_xbar_anon_out_d_bits_denied_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_data (auto_system_bus_xbar_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_out_d_bits_corrupt (auto_system_bus_xbar_anon_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_out_e_ready (auto_system_bus_xbar_anon_out_e_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_out_e_valid (auto_system_bus_xbar_anon_out_e_valid_0), .auto_anon_out_e_bits_sink (auto_system_bus_xbar_anon_out_e_bits_sink_0) ); // @[SystemBus.scala:47:43] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_valid = auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_opcode = auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_param = auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_size = auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_source = auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_address = auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_mask = auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_data = auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_a_bits_corrupt = auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_b_ready = auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_valid = auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_opcode = auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_param = auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_size = auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_source = auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_address = auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_data = auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_c_bits_corrupt = auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_d_ready = auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_e_valid = auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_system_bus_xbar_anon_out_e_bits_sink = auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_19 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut

module MulFullRawFN_19( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_159 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_159( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_6 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_12 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_6 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h1)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1] connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`2`[1], io.router_resp.vc_sel.`2`[1] connect route_q.io.enq.bits.vc_sel.`2`[2], io.router_resp.vc_sel.`2`[2] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_16 = eq(UInt<2>(0h2), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_13 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_6 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1] connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[1], io.vcalloc_resp.vc_sel.`2`[1] connect vcalloc_q.io.enq.bits.vc_sel.`2`[2], io.vcalloc_resp.vc_sel.`2`[2] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _c_T_2 = cat(c_hi_2, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node c_lo = cat(_c_T_1, _c_T) node c_hi_3 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], _c_T_2) node _c_T_3 = cat(c_hi_3, c_lo) node c_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _c_T_4 = cat(c_hi_4, io.out_credit_available.`0`[0]) node c_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _c_T_5 = cat(c_hi_5, io.out_credit_available.`1`[0]) node c_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _c_T_6 = cat(c_hi_6, io.out_credit_available.`2`[0]) node c_lo_1 = cat(_c_T_5, _c_T_4) node c_hi_7 = cat(io.out_credit_available.`3`[0], _c_T_6) node _c_T_7 = cat(c_hi_7, c_lo_1) node _c_T_8 = and(_c_T_3, _c_T_7) node c = neq(_c_T_8, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}} connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2]) node _out_channel_oh_T_2 = or(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node out_channel_oh_2 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`2`[2]) node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2) node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo) node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1) node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3) node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1]) node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0) node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1) node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8) node out_bundle_bits_out_virt_channel_hi_4 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[2], vcalloc_q.io.deq.bits.vc_sel.`2`[1]) node _out_bundle_bits_out_virt_channel_T_10 = cat(out_bundle_bits_out_virt_channel_hi_4, vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node out_bundle_bits_out_virt_channel_hi_5 = bits(_out_bundle_bits_out_virt_channel_T_10, 2, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_10, 1, 0) node _out_bundle_bits_out_virt_channel_T_11 = orr(out_bundle_bits_out_virt_channel_hi_5) node _out_bundle_bits_out_virt_channel_T_12 = or(out_bundle_bits_out_virt_channel_hi_5, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_13 = bits(_out_bundle_bits_out_virt_channel_T_12, 1, 1) node _out_bundle_bits_out_virt_channel_T_14 = cat(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_15 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_16 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_17 = mux(out_channel_oh_2, _out_bundle_bits_out_virt_channel_T_14, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_18 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_19 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_16) node _out_bundle_bits_out_virt_channel_T_20 = or(_out_bundle_bits_out_virt_channel_T_19, _out_bundle_bits_out_virt_channel_T_17) node _out_bundle_bits_out_virt_channel_T_21 = or(_out_bundle_bits_out_virt_channel_T_20, _out_bundle_bits_out_virt_channel_T_18) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_21 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_6( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [1:0] route_buffer_io_enq_bits_flow_egress_node_id = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_4 | _route_buffer_io_enq_bits_flow_egress_node_id_T_5 | _route_buffer_io_enq_bits_flow_egress_node_id_T_6 | _route_buffer_io_enq_bits_flow_egress_node_id_T_7}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h1; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h1; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module SinkE : input clock : Clock input reset : Reset output io : { resp : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} connect io.e.ready, UInt<1>(0h1) connect io.resp.valid, io.e.valid connect io.resp.bits.sink, io.e.bits.sink

module SinkE( // @[SinkE.scala:29:7] input clock, // @[SinkE.scala:29:7] input reset, // @[SinkE.scala:29:7] output io_resp_valid, // @[SinkE.scala:31:14] output [2:0] io_resp_bits_sink, // @[SinkE.scala:31:14] input io_e_valid, // @[SinkE.scala:31:14] input [2:0] io_e_bits_sink // @[SinkE.scala:31:14] ); wire io_e_valid_0 = io_e_valid; // @[SinkE.scala:29:7] wire [2:0] io_e_bits_sink_0 = io_e_bits_sink; // @[SinkE.scala:29:7] wire io_e_ready = 1'h1; // @[SinkE.scala:29:7] wire io_resp_valid_0 = io_e_valid_0; // @[SinkE.scala:29:7] wire [2:0] io_resp_bits_sink_0 = io_e_bits_sink_0; // @[SinkE.scala:29:7] assign io_resp_valid = io_resp_valid_0; // @[SinkE.scala:29:7] assign io_resp_bits_sink = io_resp_bits_sink_0; // @[SinkE.scala:29:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_64 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T

module MulAddRecFNToRaw_postMul_e8_s24_64( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PLICClockSinkDomain : output auto : { flip plic_int_in : UInt<1>[1], flip plic_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, int_in_clock_xing_out_1 : { sync : UInt<1>[1]}, int_in_clock_xing_out_0 : { sync : UInt<1>[1]}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst plic of TLPLIC connect plic.clock, childClock connect plic.reset, childReset inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock wire intInClockXingOut : { sync : UInt<1>[1]} invalidate intInClockXingOut.sync[0] wire intInClockXingIn : { sync : UInt<1>[1]} invalidate intInClockXingIn.sync[0] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 connect intsource.auto.in[0], plic.auto.int_out_0[0] connect intsource_1.auto.in[0], plic.auto.int_out_1[0] connect intInClockXingIn, intsource.auto.out connect intInClockXingIn_1, intsource_1.auto.out connect clockNodeIn, auto.clock_in connect auto.int_in_clock_xing_out_0, intInClockXingOut connect auto.int_in_clock_xing_out_1, intInClockXingOut_1 connect plic.auto.in, auto.plic_in connect plic.auto.int_in[0], auto.plic_int_in[0] connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset extmodule plusarg_reader_101 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module PLICClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_plic_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_plic_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_plic_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_plic_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_plic_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_plic_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_plic_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_plic_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_plic_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_plic_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_plic_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_plic_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_plic_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_plic_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_plic_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_int_in_clock_xing_out_0_sync_0, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _plic_auto_int_out_1_0; // @[Plic.scala:367:46] wire _plic_auto_int_out_0_0; // @[Plic.scala:367:46] wire auto_plic_int_in_0_0 = auto_plic_int_in_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_valid_0 = auto_plic_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_opcode_0 = auto_plic_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_a_bits_param_0 = auto_plic_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_a_bits_size_0 = auto_plic_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_a_bits_source_0 = auto_plic_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [27:0] auto_plic_in_a_bits_address_0 = auto_plic_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_plic_in_a_bits_mask_0 = auto_plic_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_a_bits_data_0 = auto_plic_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_bits_corrupt_0 = auto_plic_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_ready_0 = auto_plic_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire intInClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_0_sync_0_0 = intInClockXingOut_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_sync_0 = intInClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intInClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign auto_int_in_clock_xing_out_1_sync_0_0 = intInClockXingOut_1_sync_0; // @[ClockDomain.scala:14:9] assign intInClockXingOut_1_sync_0 = intInClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] TLPLIC plic ( // @[Plic.scala:367:46] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_int_in_0 (auto_plic_int_in_0_0), // @[ClockDomain.scala:14:9] .auto_int_out_1_0 (_plic_auto_int_out_1_0), .auto_int_out_0_0 (_plic_auto_int_out_0_0), .auto_in_a_ready (auto_plic_in_a_ready_0), .auto_in_a_valid (auto_plic_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (auto_plic_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (auto_plic_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (auto_plic_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (auto_plic_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (auto_plic_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (auto_plic_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (auto_plic_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_in_a_bits_corrupt (auto_plic_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_in_d_ready (auto_plic_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_in_d_valid (auto_plic_in_d_valid_0), .auto_in_d_bits_opcode (auto_plic_in_d_bits_opcode_0), .auto_in_d_bits_size (auto_plic_in_d_bits_size_0), .auto_in_d_bits_source (auto_plic_in_d_bits_source_0), .auto_in_d_bits_data (auto_plic_in_d_bits_data_0) ); // @[Plic.scala:367:46] IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_0_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_sync_0) ); // @[Crossing.scala:29:31] IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (_plic_auto_int_out_1_0), // @[Plic.scala:367:46] .auto_out_sync_0 (intInClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] assign auto_plic_in_a_ready = auto_plic_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_valid = auto_plic_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_opcode = auto_plic_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_size = auto_plic_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_source = auto_plic_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_plic_in_d_bits_data = auto_plic_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_1_sync_0 = auto_int_in_clock_xing_out_1_sync_0_0; // @[ClockDomain.scala:14:9] assign auto_int_in_clock_xing_out_0_sync_0 = auto_int_in_clock_xing_out_0_sync_0_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_27 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt<21>}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} inst main of BranchKillableQueue_26 connect main.clock, clock connect main.reset, reset reg out_reg : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock regreset out_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect main.io.enq, io.enq connect main.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset connect main.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect main.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect main.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect main.io.brupdate.b2.taken, io.brupdate.b2.taken connect main.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict connect main.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect main.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect main.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect main.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect main.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect main.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect main.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect main.io.brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect main.io.brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect main.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect main.io.brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect main.io.brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect main.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect main.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect main.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect main.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect main.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect main.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect main.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect main.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect main.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect main.io.brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect main.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect main.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect main.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect main.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect main.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect main.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect main.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect main.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect main.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect main.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect main.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect main.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect main.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect main.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect main.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect main.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect main.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect main.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect main.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect main.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect main.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect main.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect main.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect main.io.brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect main.io.brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect main.io.brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect main.io.brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect main.io.brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect main.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect main.io.brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect main.io.brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect main.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect main.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect main.io.brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect main.io.brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect main.io.brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect main.io.brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect main.io.brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect main.io.brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect main.io.brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect main.io.brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect main.io.brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect main.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect main.io.brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect main.io.brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect main.io.brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect main.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect main.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect main.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect main.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect main.io.brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect main.io.brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect main.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect main.io.brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect main.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect main.io.brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect main.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect main.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect main.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect main.io.brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect main.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect main.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect main.io.brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect main.io.brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect main.io.brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect main.io.brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect main.io.brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect main.io.brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect main.io.brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect main.io.brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect main.io.brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect main.io.brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect main.io.brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect main.io.brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect main.io.brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect main.io.brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect main.io.brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect main.io.brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect main.io.brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect main.io.brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect main.io.brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect main.io.brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect main.io.brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect main.io.brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect main.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect main.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect main.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect main.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect main.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect main.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect main.io.flush, io.flush node _io_empty_T = eq(out_valid, UInt<1>(0h0)) node _io_empty_T_1 = and(main.io.empty, _io_empty_T) connect io.empty, _io_empty_T_1 node _io_count_T = add(main.io.count, out_valid) node _io_count_T_1 = tail(_io_count_T, 1) connect io.count, _io_count_T_1 connect io.deq.valid, out_valid connect io.deq.bits, out_reg connect io.deq.bits.uop, out_uop wire out_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out, out_uop node _out_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_1 = and(out_uop.br_mask, _out_uop_out_br_mask_T) connect out_uop_out.br_mask, _out_uop_out_br_mask_T_1 connect out_uop, out_uop_out node _out_valid_T = and(io.brupdate.b1.mispredict_mask, out_uop.br_mask) node _out_valid_T_1 = neq(_out_valid_T, UInt<1>(0h0)) node _out_valid_T_2 = or(_out_valid_T_1, UInt<1>(0h0)) node _out_valid_T_3 = eq(_out_valid_T_2, UInt<1>(0h0)) node _out_valid_T_4 = and(out_valid, _out_valid_T_3) node _out_valid_T_5 = and(io.flush, out_uop.uses_ldq) node _out_valid_T_6 = eq(_out_valid_T_5, UInt<1>(0h0)) node _out_valid_T_7 = and(_out_valid_T_4, _out_valid_T_6) connect out_valid, _out_valid_T_7 connect main.io.deq.ready, UInt<1>(0h0) node _T = and(io.deq.ready, io.deq.valid) node _T_1 = eq(out_valid, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) when _T_2 : node _out_valid_T_8 = and(io.brupdate.b1.mispredict_mask, main.io.deq.bits.uop.br_mask) node _out_valid_T_9 = neq(_out_valid_T_8, UInt<1>(0h0)) node _out_valid_T_10 = or(_out_valid_T_9, UInt<1>(0h0)) node _out_valid_T_11 = eq(_out_valid_T_10, UInt<1>(0h0)) node _out_valid_T_12 = and(main.io.deq.valid, _out_valid_T_11) node _out_valid_T_13 = and(io.flush, main.io.deq.bits.uop.uses_ldq) node _out_valid_T_14 = eq(_out_valid_T_13, UInt<1>(0h0)) node _out_valid_T_15 = and(_out_valid_T_12, _out_valid_T_14) connect out_valid, _out_valid_T_15 connect out_reg, main.io.deq.bits wire out_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<1>, iw_p2_speculative_child : UInt<1>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<5>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect out_uop_out_1, main.io.deq.bits.uop node _out_uop_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _out_uop_out_br_mask_T_3 = and(main.io.deq.bits.uop.br_mask, _out_uop_out_br_mask_T_2) connect out_uop_out_1.br_mask, _out_uop_out_br_mask_T_3 connect out_uop, out_uop_out_1 connect main.io.deq.ready, UInt<1>(0h1)

module BranchKillableQueue_27( // @[util.scala:458:7] input clock, // @[util.scala:458:7] input reset, // @[util.scala:458:7] output io_enq_ready, // @[util.scala:463:14] input io_enq_valid, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14] input io_enq_bits_uop_is_rvc, // @[util.scala:463:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14] input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14] input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] input io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14] input io_enq_bits_uop_is_sfb, // @[util.scala:463:14] input io_enq_bits_uop_is_fence, // @[util.scala:463:14] input io_enq_bits_uop_is_fencei, // @[util.scala:463:14] input io_enq_bits_uop_is_sfence, // @[util.scala:463:14] input io_enq_bits_uop_is_amo, // @[util.scala:463:14] input io_enq_bits_uop_is_eret, // @[util.scala:463:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] input io_enq_bits_uop_is_rocc, // @[util.scala:463:14] input io_enq_bits_uop_is_mov, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14] input io_enq_bits_uop_edge_inst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14] input io_enq_bits_uop_taken, // @[util.scala:463:14] input io_enq_bits_uop_imm_rename, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_pdst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_prs3, // @[util.scala:463:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:463:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14] input io_enq_bits_uop_exception, // @[util.scala:463:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14] input io_enq_bits_uop_mem_signed, // @[util.scala:463:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14] input io_enq_bits_uop_uses_stq, // @[util.scala:463:14] input io_enq_bits_uop_is_unique, // @[util.scala:463:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14] input io_enq_bits_uop_frs3_en, // @[util.scala:463:14] input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14] input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14] input io_enq_bits_uop_fp_val, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14] input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14] input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14] input [33:0] io_enq_bits_addr, // @[util.scala:463:14] input [63:0] io_enq_bits_data, // @[util.scala:463:14] input io_enq_bits_is_hella, // @[util.scala:463:14] input io_enq_bits_tag_match, // @[util.scala:463:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:463:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:463:14] input [1:0] io_enq_bits_way_en, // @[util.scala:463:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:463:14] input io_deq_ready, // @[util.scala:463:14] output io_deq_valid, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14] output io_deq_bits_uop_is_rvc, // @[util.scala:463:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14] output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14] output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14] output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14] output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14] output io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14] output io_deq_bits_uop_is_sfb, // @[util.scala:463:14] output io_deq_bits_uop_is_fence, // @[util.scala:463:14] output io_deq_bits_uop_is_fencei, // @[util.scala:463:14] output io_deq_bits_uop_is_sfence, // @[util.scala:463:14] output io_deq_bits_uop_is_amo, // @[util.scala:463:14] output io_deq_bits_uop_is_eret, // @[util.scala:463:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14] output io_deq_bits_uop_is_rocc, // @[util.scala:463:14] output io_deq_bits_uop_is_mov, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14] output io_deq_bits_uop_edge_inst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14] output io_deq_bits_uop_taken, // @[util.scala:463:14] output io_deq_bits_uop_imm_rename, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14] output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_pdst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_prs3, // @[util.scala:463:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:463:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14] output io_deq_bits_uop_exception, // @[util.scala:463:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14] output io_deq_bits_uop_mem_signed, // @[util.scala:463:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14] output io_deq_bits_uop_uses_stq, // @[util.scala:463:14] output io_deq_bits_uop_is_unique, // @[util.scala:463:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14] output io_deq_bits_uop_frs3_en, // @[util.scala:463:14] output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14] output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14] output io_deq_bits_uop_fp_val, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14] output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14] output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14] output [33:0] io_deq_bits_addr, // @[util.scala:463:14] output [63:0] io_deq_bits_data, // @[util.scala:463:14] output io_deq_bits_is_hella, // @[util.scala:463:14] output io_deq_bits_tag_match, // @[util.scala:463:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:463:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:463:14] output [1:0] io_deq_bits_way_en, // @[util.scala:463:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:463:14] output io_empty // @[util.scala:463:14] ); wire _out_valid_T_12; // @[util.scala:496:38] wire [31:0] _main_io_deq_bits_uop_inst; // @[util.scala:476:22] wire [31:0] _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_br_type; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22] wire _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22] wire _main_io_deq_bits_uop_taken; // @[util.scala:476:22] wire _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_pimm; // @[util.scala:476:22] wire [19:0] _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_pdst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_prs3; // @[util.scala:476:22] wire [3:0] _main_io_deq_bits_uop_ppred; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22] wire _main_io_deq_bits_uop_exception; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22] wire _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22] wire _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22] wire _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22] wire _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_ldst; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22] wire [5:0] _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22] wire _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22] wire _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22] wire _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22] wire [2:0] _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22] wire [33:0] _main_io_deq_bits_addr; // @[util.scala:476:22] wire [63:0] _main_io_deq_bits_data; // @[util.scala:476:22] wire _main_io_deq_bits_is_hella; // @[util.scala:476:22] wire _main_io_deq_bits_tag_match; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22] wire [21:0] _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22] wire [1:0] _main_io_deq_bits_way_en; // @[util.scala:476:22] wire [4:0] _main_io_deq_bits_sdq_id; // @[util.scala:476:22] wire _main_io_empty; // @[util.scala:476:22] wire [3:0] _main_io_count; // @[util.scala:476:22] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7] wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7] wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7] wire io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7] wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7] wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7] wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7] wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7] wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7] wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7] wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7] wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7] wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7] wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:458:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:458:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:458:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:458:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:458:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:458:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7] wire _out_valid_T_3 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_6 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_11 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire _out_valid_T_14 = 1'h1; // @[util.scala:492:{31,83}, :496:{41,106}] wire [3:0] _out_uop_out_br_mask_T = 4'hF; // @[util.scala:93:27] wire [3:0] _out_uop_out_br_mask_T_2 = 4'hF; // @[util.scala:93:27] wire [20:0] io_brupdate_b2_target_offset = 21'h0; // @[util.scala:458:7, :463:14, :476:22] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:458:7, :463:14, :476:22] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_pimm = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_rob_idx = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [4:0] io_brupdate_b2_uop_fcn_op = 5'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_imm_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_op2_sel = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_csr_cmd = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_fp_rm = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_fsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_uop_debug_tsrc = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_prs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_stale_pdst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_op1_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_uop_fp_typ = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:458:7, :463:14, :476:22] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iq_type_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_0 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_4 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_5 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_6 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_7 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_8 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fu_code_9 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_dis_col_sel = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sfence = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_eret = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_rocc = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_mov = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_imm_rename = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fcn_dw = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:458:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:458:7] wire io_flush = 1'h0; // @[util.scala:458:7] wire _out_valid_T_1 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_2 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_5 = 1'h0; // @[util.scala:492:94] wire _out_valid_T_9 = 1'h0; // @[util.scala:126:59] wire _out_valid_T_10 = 1'h0; // @[util.scala:61:61] wire _out_valid_T_13 = 1'h0; // @[util.scala:496:117] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_br_type = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire [3:0] _out_valid_T_8 = 4'h0; // @[util.scala:126:51, :458:7, :463:14, :476:22] wire _io_empty_T_1; // @[util.scala:484:31] wire [3:0] _io_count_T_1; // @[util.scala:485:31] wire io_enq_ready_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] wire io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] wire io_deq_bits_uop_taken_0; // @[util.scala:458:7] wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] wire io_deq_bits_uop_exception_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:458:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7] wire io_deq_bits_is_hella_0; // @[util.scala:458:7] wire io_deq_bits_tag_match_0; // @[util.scala:458:7] wire [1:0] io_deq_bits_way_en_0; // @[util.scala:458:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:458:7] wire io_deq_valid_0; // @[util.scala:458:7] wire io_empty_0; // @[util.scala:458:7] wire [3:0] io_count; // @[util.scala:458:7] reg [31:0] out_reg_uop_inst; // @[util.scala:477:22] reg [31:0] out_reg_uop_debug_inst; // @[util.scala:477:22] reg out_reg_uop_is_rvc; // @[util.scala:477:22] reg [33:0] out_reg_uop_debug_pc; // @[util.scala:477:22] reg out_reg_uop_iq_type_0; // @[util.scala:477:22] reg out_reg_uop_iq_type_1; // @[util.scala:477:22] reg out_reg_uop_iq_type_2; // @[util.scala:477:22] reg out_reg_uop_iq_type_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_0; // @[util.scala:477:22] reg out_reg_uop_fu_code_1; // @[util.scala:477:22] reg out_reg_uop_fu_code_2; // @[util.scala:477:22] reg out_reg_uop_fu_code_3; // @[util.scala:477:22] reg out_reg_uop_fu_code_4; // @[util.scala:477:22] reg out_reg_uop_fu_code_5; // @[util.scala:477:22] reg out_reg_uop_fu_code_6; // @[util.scala:477:22] reg out_reg_uop_fu_code_7; // @[util.scala:477:22] reg out_reg_uop_fu_code_8; // @[util.scala:477:22] reg out_reg_uop_fu_code_9; // @[util.scala:477:22] reg out_reg_uop_iw_issued; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_agen; // @[util.scala:477:22] reg out_reg_uop_iw_issued_partial_dgen; // @[util.scala:477:22] reg out_reg_uop_iw_p1_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p2_speculative_child; // @[util.scala:477:22] reg out_reg_uop_iw_p1_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p2_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_iw_p3_bypass_hint; // @[util.scala:477:22] reg out_reg_uop_dis_col_sel; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_mask; // @[util.scala:477:22] reg [1:0] out_reg_uop_br_tag; // @[util.scala:477:22] reg [3:0] out_reg_uop_br_type; // @[util.scala:477:22] reg out_reg_uop_is_sfb; // @[util.scala:477:22] reg out_reg_uop_is_fence; // @[util.scala:477:22] reg out_reg_uop_is_fencei; // @[util.scala:477:22] reg out_reg_uop_is_sfence; // @[util.scala:477:22] reg out_reg_uop_is_amo; // @[util.scala:477:22] reg out_reg_uop_is_eret; // @[util.scala:477:22] reg out_reg_uop_is_sys_pc2epc; // @[util.scala:477:22] reg out_reg_uop_is_rocc; // @[util.scala:477:22] reg out_reg_uop_is_mov; // @[util.scala:477:22] reg [3:0] out_reg_uop_ftq_idx; // @[util.scala:477:22] reg out_reg_uop_edge_inst; // @[util.scala:477:22] reg [5:0] out_reg_uop_pc_lob; // @[util.scala:477:22] reg out_reg_uop_taken; // @[util.scala:477:22] reg out_reg_uop_imm_rename; // @[util.scala:477:22] reg [2:0] out_reg_uop_imm_sel; // @[util.scala:477:22] reg [4:0] out_reg_uop_pimm; // @[util.scala:477:22] reg [19:0] out_reg_uop_imm_packed; // @[util.scala:477:22] reg [1:0] out_reg_uop_op1_sel; // @[util.scala:477:22] reg [2:0] out_reg_uop_op2_sel; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ldst; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wen; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren1; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren2; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_ren3; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap12; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_swap23; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagIn; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_ctrl_typeTagOut; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fromint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_toint; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fastpipe; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_fma; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_div; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_sqrt; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_wflags; // @[util.scala:477:22] reg out_reg_uop_fp_ctrl_vec; // @[util.scala:477:22] reg [4:0] out_reg_uop_rob_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_ldq_idx; // @[util.scala:477:22] reg [3:0] out_reg_uop_stq_idx; // @[util.scala:477:22] reg [1:0] out_reg_uop_rxq_idx; // @[util.scala:477:22] reg [5:0] out_reg_uop_pdst; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_prs3; // @[util.scala:477:22] reg [3:0] out_reg_uop_ppred; // @[util.scala:477:22] reg out_reg_uop_prs1_busy; // @[util.scala:477:22] reg out_reg_uop_prs2_busy; // @[util.scala:477:22] reg out_reg_uop_prs3_busy; // @[util.scala:477:22] reg out_reg_uop_ppred_busy; // @[util.scala:477:22] reg [5:0] out_reg_uop_stale_pdst; // @[util.scala:477:22] reg out_reg_uop_exception; // @[util.scala:477:22] reg [63:0] out_reg_uop_exc_cause; // @[util.scala:477:22] reg [4:0] out_reg_uop_mem_cmd; // @[util.scala:477:22] reg [1:0] out_reg_uop_mem_size; // @[util.scala:477:22] reg out_reg_uop_mem_signed; // @[util.scala:477:22] reg out_reg_uop_uses_ldq; // @[util.scala:477:22] reg out_reg_uop_uses_stq; // @[util.scala:477:22] reg out_reg_uop_is_unique; // @[util.scala:477:22] reg out_reg_uop_flush_on_commit; // @[util.scala:477:22] reg [2:0] out_reg_uop_csr_cmd; // @[util.scala:477:22] reg out_reg_uop_ldst_is_rs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_ldst; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs1; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs2; // @[util.scala:477:22] reg [5:0] out_reg_uop_lrs3; // @[util.scala:477:22] reg [1:0] out_reg_uop_dst_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs1_rtype; // @[util.scala:477:22] reg [1:0] out_reg_uop_lrs2_rtype; // @[util.scala:477:22] reg out_reg_uop_frs3_en; // @[util.scala:477:22] reg out_reg_uop_fcn_dw; // @[util.scala:477:22] reg [4:0] out_reg_uop_fcn_op; // @[util.scala:477:22] reg out_reg_uop_fp_val; // @[util.scala:477:22] reg [2:0] out_reg_uop_fp_rm; // @[util.scala:477:22] reg [1:0] out_reg_uop_fp_typ; // @[util.scala:477:22] reg out_reg_uop_xcpt_pf_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ae_if; // @[util.scala:477:22] reg out_reg_uop_xcpt_ma_if; // @[util.scala:477:22] reg out_reg_uop_bp_debug_if; // @[util.scala:477:22] reg out_reg_uop_bp_xcpt_if; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_fsrc; // @[util.scala:477:22] reg [2:0] out_reg_uop_debug_tsrc; // @[util.scala:477:22] reg [33:0] out_reg_addr; // @[util.scala:477:22] assign io_deq_bits_addr_0 = out_reg_addr; // @[util.scala:458:7, :477:22] reg [63:0] out_reg_data; // @[util.scala:477:22] assign io_deq_bits_data_0 = out_reg_data; // @[util.scala:458:7, :477:22] reg out_reg_is_hella; // @[util.scala:477:22] assign io_deq_bits_is_hella_0 = out_reg_is_hella; // @[util.scala:458:7, :477:22] reg out_reg_tag_match; // @[util.scala:477:22] assign io_deq_bits_tag_match_0 = out_reg_tag_match; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_old_meta_coh_state; // @[util.scala:477:22] assign io_deq_bits_old_meta_coh_state_0 = out_reg_old_meta_coh_state; // @[util.scala:458:7, :477:22] reg [21:0] out_reg_old_meta_tag; // @[util.scala:477:22] assign io_deq_bits_old_meta_tag_0 = out_reg_old_meta_tag; // @[util.scala:458:7, :477:22] reg [1:0] out_reg_way_en; // @[util.scala:477:22] assign io_deq_bits_way_en_0 = out_reg_way_en; // @[util.scala:458:7, :477:22] reg [4:0] out_reg_sdq_id; // @[util.scala:477:22] assign io_deq_bits_sdq_id_0 = out_reg_sdq_id; // @[util.scala:458:7, :477:22] reg out_valid; // @[util.scala:478:28] assign io_deq_valid_0 = out_valid; // @[util.scala:458:7, :478:28] wire _out_valid_T_4 = out_valid; // @[util.scala:478:28, :492:28] reg [31:0] out_uop_inst; // @[util.scala:479:22] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_inst = out_uop_inst; // @[util.scala:104:23, :479:22] reg [31:0] out_uop_debug_inst; // @[util.scala:479:22] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :479:22] wire [31:0] out_uop_out_debug_inst = out_uop_debug_inst; // @[util.scala:104:23, :479:22] reg out_uop_is_rvc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rvc = out_uop_is_rvc; // @[util.scala:104:23, :479:22] reg [33:0] out_uop_debug_pc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :479:22] wire [33:0] out_uop_out_debug_pc = out_uop_debug_pc; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_0; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_0 = out_uop_iq_type_0; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_1; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_1 = out_uop_iq_type_1; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_2; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_2 = out_uop_iq_type_2; // @[util.scala:104:23, :479:22] reg out_uop_iq_type_3; // @[util.scala:479:22] assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :479:22] wire out_uop_out_iq_type_3 = out_uop_iq_type_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_0; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_0 = out_uop_fu_code_0; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_1; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_1 = out_uop_fu_code_1; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_2; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_2 = out_uop_fu_code_2; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_3; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_3 = out_uop_fu_code_3; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_4; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_4 = out_uop_fu_code_4; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_5; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_5 = out_uop_fu_code_5; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_6; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_6 = out_uop_fu_code_6; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_7; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_7 = out_uop_fu_code_7; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_8; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_8 = out_uop_fu_code_8; // @[util.scala:104:23, :479:22] reg out_uop_fu_code_9; // @[util.scala:479:22] assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :479:22] wire out_uop_out_fu_code_9 = out_uop_fu_code_9; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued = out_uop_iw_issued; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_agen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_agen = out_uop_iw_issued_partial_agen; // @[util.scala:104:23, :479:22] reg out_uop_iw_issued_partial_dgen; // @[util.scala:479:22] assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_issued_partial_dgen = out_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_speculative_child = out_uop_iw_p1_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_speculative_child; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_speculative_child = out_uop_iw_p2_speculative_child; // @[util.scala:104:23, :479:22] reg out_uop_iw_p1_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p1_bypass_hint = out_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p2_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p2_bypass_hint = out_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_iw_p3_bypass_hint; // @[util.scala:479:22] assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :479:22] wire out_uop_out_iw_p3_bypass_hint = out_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22] reg out_uop_dis_col_sel; // @[util.scala:479:22] assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :479:22] wire out_uop_out_dis_col_sel = out_uop_dis_col_sel; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_mask; // @[util.scala:479:22] assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :479:22] wire [3:0] _out_uop_out_br_mask_T_1 = out_uop_br_mask; // @[util.scala:93:25, :479:22] reg [1:0] out_uop_br_tag; // @[util.scala:479:22] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_br_tag = out_uop_br_tag; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_br_type; // @[util.scala:479:22] assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_br_type = out_uop_br_type; // @[util.scala:104:23, :479:22] reg out_uop_is_sfb; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfb = out_uop_is_sfb; // @[util.scala:104:23, :479:22] reg out_uop_is_fence; // @[util.scala:479:22] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fence = out_uop_is_fence; // @[util.scala:104:23, :479:22] reg out_uop_is_fencei; // @[util.scala:479:22] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :479:22] wire out_uop_out_is_fencei = out_uop_is_fencei; // @[util.scala:104:23, :479:22] reg out_uop_is_sfence; // @[util.scala:479:22] assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sfence = out_uop_is_sfence; // @[util.scala:104:23, :479:22] reg out_uop_is_amo; // @[util.scala:479:22] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :479:22] wire out_uop_out_is_amo = out_uop_is_amo; // @[util.scala:104:23, :479:22] reg out_uop_is_eret; // @[util.scala:479:22] assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :479:22] wire out_uop_out_is_eret = out_uop_is_eret; // @[util.scala:104:23, :479:22] reg out_uop_is_sys_pc2epc; // @[util.scala:479:22] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_sys_pc2epc = out_uop_is_sys_pc2epc; // @[util.scala:104:23, :479:22] reg out_uop_is_rocc; // @[util.scala:479:22] assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :479:22] wire out_uop_out_is_rocc = out_uop_is_rocc; // @[util.scala:104:23, :479:22] reg out_uop_is_mov; // @[util.scala:479:22] assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :479:22] wire out_uop_out_is_mov = out_uop_is_mov; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ftq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ftq_idx = out_uop_ftq_idx; // @[util.scala:104:23, :479:22] reg out_uop_edge_inst; // @[util.scala:479:22] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :479:22] wire out_uop_out_edge_inst = out_uop_edge_inst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pc_lob; // @[util.scala:479:22] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pc_lob = out_uop_pc_lob; // @[util.scala:104:23, :479:22] reg out_uop_taken; // @[util.scala:479:22] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :479:22] wire out_uop_out_taken = out_uop_taken; // @[util.scala:104:23, :479:22] reg out_uop_imm_rename; // @[util.scala:479:22] assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :479:22] wire out_uop_out_imm_rename = out_uop_imm_rename; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_imm_sel; // @[util.scala:479:22] assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_imm_sel = out_uop_imm_sel; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_pimm; // @[util.scala:479:22] assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_pimm = out_uop_pimm; // @[util.scala:104:23, :479:22] reg [19:0] out_uop_imm_packed; // @[util.scala:479:22] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :479:22] wire [19:0] out_uop_out_imm_packed = out_uop_imm_packed; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_op1_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_op1_sel = out_uop_op1_sel; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_op2_sel; // @[util.scala:479:22] assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_op2_sel = out_uop_op2_sel; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ldst = out_uop_fp_ctrl_ldst; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wen; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wen = out_uop_fp_ctrl_wen; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren1; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren1 = out_uop_fp_ctrl_ren1; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren2; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren2 = out_uop_fp_ctrl_ren2; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_ren3; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_ren3 = out_uop_fp_ctrl_ren3; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap12; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap12 = out_uop_fp_ctrl_swap12; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_swap23; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_swap23 = out_uop_fp_ctrl_swap23; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagIn = out_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_ctrl_typeTagOut = out_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fromint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fromint = out_uop_fp_ctrl_fromint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_toint; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_toint = out_uop_fp_ctrl_toint; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fastpipe; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fastpipe = out_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_fma; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_fma = out_uop_fp_ctrl_fma; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_div; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_div = out_uop_fp_ctrl_div; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_sqrt; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_sqrt = out_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_wflags; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_wflags = out_uop_fp_ctrl_wflags; // @[util.scala:104:23, :479:22] reg out_uop_fp_ctrl_vec; // @[util.scala:479:22] assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_ctrl_vec = out_uop_fp_ctrl_vec; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_rob_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_rob_idx = out_uop_rob_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ldq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ldq_idx = out_uop_ldq_idx; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_stq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_stq_idx = out_uop_stq_idx; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_rxq_idx; // @[util.scala:479:22] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_rxq_idx = out_uop_rxq_idx; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_pdst = out_uop_pdst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs1; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs1 = out_uop_prs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs2; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs2 = out_uop_prs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_prs3; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_prs3 = out_uop_prs3; // @[util.scala:104:23, :479:22] reg [3:0] out_uop_ppred; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :479:22] wire [3:0] out_uop_out_ppred = out_uop_ppred; // @[util.scala:104:23, :479:22] reg out_uop_prs1_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs1_busy = out_uop_prs1_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs2_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs2_busy = out_uop_prs2_busy; // @[util.scala:104:23, :479:22] reg out_uop_prs3_busy; // @[util.scala:479:22] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_prs3_busy = out_uop_prs3_busy; // @[util.scala:104:23, :479:22] reg out_uop_ppred_busy; // @[util.scala:479:22] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :479:22] wire out_uop_out_ppred_busy = out_uop_ppred_busy; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_stale_pdst; // @[util.scala:479:22] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_stale_pdst = out_uop_stale_pdst; // @[util.scala:104:23, :479:22] reg out_uop_exception; // @[util.scala:479:22] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :479:22] wire out_uop_out_exception = out_uop_exception; // @[util.scala:104:23, :479:22] reg [63:0] out_uop_exc_cause; // @[util.scala:479:22] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :479:22] wire [63:0] out_uop_out_exc_cause = out_uop_exc_cause; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_mem_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_mem_cmd = out_uop_mem_cmd; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_mem_size; // @[util.scala:479:22] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_mem_size = out_uop_mem_size; // @[util.scala:104:23, :479:22] reg out_uop_mem_signed; // @[util.scala:479:22] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :479:22] wire out_uop_out_mem_signed = out_uop_mem_signed; // @[util.scala:104:23, :479:22] reg out_uop_uses_ldq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_ldq = out_uop_uses_ldq; // @[util.scala:104:23, :479:22] reg out_uop_uses_stq; // @[util.scala:479:22] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :479:22] wire out_uop_out_uses_stq = out_uop_uses_stq; // @[util.scala:104:23, :479:22] reg out_uop_is_unique; // @[util.scala:479:22] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :479:22] wire out_uop_out_is_unique = out_uop_is_unique; // @[util.scala:104:23, :479:22] reg out_uop_flush_on_commit; // @[util.scala:479:22] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :479:22] wire out_uop_out_flush_on_commit = out_uop_flush_on_commit; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_csr_cmd; // @[util.scala:479:22] assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_csr_cmd = out_uop_csr_cmd; // @[util.scala:104:23, :479:22] reg out_uop_ldst_is_rs1; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :479:22] wire out_uop_out_ldst_is_rs1 = out_uop_ldst_is_rs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_ldst; // @[util.scala:479:22] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_ldst = out_uop_ldst; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs1; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs1 = out_uop_lrs1; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs2; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs2 = out_uop_lrs2; // @[util.scala:104:23, :479:22] reg [5:0] out_uop_lrs3; // @[util.scala:479:22] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :479:22] wire [5:0] out_uop_out_lrs3 = out_uop_lrs3; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_dst_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_dst_rtype = out_uop_dst_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs1_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs1_rtype = out_uop_lrs1_rtype; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_lrs2_rtype; // @[util.scala:479:22] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_lrs2_rtype = out_uop_lrs2_rtype; // @[util.scala:104:23, :479:22] reg out_uop_frs3_en; // @[util.scala:479:22] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :479:22] wire out_uop_out_frs3_en = out_uop_frs3_en; // @[util.scala:104:23, :479:22] reg out_uop_fcn_dw; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :479:22] wire out_uop_out_fcn_dw = out_uop_fcn_dw; // @[util.scala:104:23, :479:22] reg [4:0] out_uop_fcn_op; // @[util.scala:479:22] assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :479:22] wire [4:0] out_uop_out_fcn_op = out_uop_fcn_op; // @[util.scala:104:23, :479:22] reg out_uop_fp_val; // @[util.scala:479:22] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :479:22] wire out_uop_out_fp_val = out_uop_fp_val; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_fp_rm; // @[util.scala:479:22] assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_fp_rm = out_uop_fp_rm; // @[util.scala:104:23, :479:22] reg [1:0] out_uop_fp_typ; // @[util.scala:479:22] assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :479:22] wire [1:0] out_uop_out_fp_typ = out_uop_fp_typ; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_pf_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_pf_if = out_uop_xcpt_pf_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ae_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ae_if = out_uop_xcpt_ae_if; // @[util.scala:104:23, :479:22] reg out_uop_xcpt_ma_if; // @[util.scala:479:22] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :479:22] wire out_uop_out_xcpt_ma_if = out_uop_xcpt_ma_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_debug_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_debug_if = out_uop_bp_debug_if; // @[util.scala:104:23, :479:22] reg out_uop_bp_xcpt_if; // @[util.scala:479:22] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :479:22] wire out_uop_out_bp_xcpt_if = out_uop_bp_xcpt_if; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_fsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_fsrc = out_uop_debug_fsrc; // @[util.scala:104:23, :479:22] reg [2:0] out_uop_debug_tsrc; // @[util.scala:479:22] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :479:22] wire [2:0] out_uop_out_debug_tsrc = out_uop_debug_tsrc; // @[util.scala:104:23, :479:22] wire _io_empty_T = ~out_valid; // @[util.scala:478:28, :484:34] assign _io_empty_T_1 = _main_io_empty & _io_empty_T; // @[util.scala:476:22, :484:{31,34}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:458:7, :484:31] wire [4:0] _io_count_T = {1'h0, _main_io_count} + {4'h0, out_valid}; // @[util.scala:126:51, :458:7, :463:14, :476:22, :478:28, :485:31] assign _io_count_T_1 = _io_count_T[3:0]; // @[util.scala:485:31] assign io_count = _io_count_T_1; // @[util.scala:458:7, :485:31] wire [3:0] out_uop_out_br_mask; // @[util.scala:104:23] assign out_uop_out_br_mask = _out_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _out_valid_T_7 = _out_valid_T_4; // @[util.scala:492:{28,80}] wire main_io_deq_ready = io_deq_ready_0 & io_deq_valid_0 | ~out_valid; // @[Decoupled.scala:51:35] wire _out_valid_T_15 = _out_valid_T_12; // @[util.scala:496:{38,103}] wire [3:0] _out_uop_out_br_mask_T_3; // @[util.scala:93:25] wire out_uop_out_1_iq_type_0; // @[util.scala:104:23] wire out_uop_out_1_iq_type_1; // @[util.scala:104:23] wire out_uop_out_1_iq_type_2; // @[util.scala:104:23] wire out_uop_out_1_iq_type_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_0; // @[util.scala:104:23] wire out_uop_out_1_fu_code_1; // @[util.scala:104:23] wire out_uop_out_1_fu_code_2; // @[util.scala:104:23] wire out_uop_out_1_fu_code_3; // @[util.scala:104:23] wire out_uop_out_1_fu_code_4; // @[util.scala:104:23] wire out_uop_out_1_fu_code_5; // @[util.scala:104:23] wire out_uop_out_1_fu_code_6; // @[util.scala:104:23] wire out_uop_out_1_fu_code_7; // @[util.scala:104:23] wire out_uop_out_1_fu_code_8; // @[util.scala:104:23] wire out_uop_out_1_fu_code_9; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ldst; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wen; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren1; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren2; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_ren3; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap12; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fromint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_toint; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_fma; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_div; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_wflags; // @[util.scala:104:23] wire out_uop_out_1_fp_ctrl_vec; // @[util.scala:104:23] wire [31:0] out_uop_out_1_inst; // @[util.scala:104:23] wire [31:0] out_uop_out_1_debug_inst; // @[util.scala:104:23] wire out_uop_out_1_is_rvc; // @[util.scala:104:23] wire [33:0] out_uop_out_1_debug_pc; // @[util.scala:104:23] wire out_uop_out_1_iw_issued; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_agen; // @[util.scala:104:23] wire out_uop_out_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_speculative_child; // @[util.scala:104:23] wire out_uop_out_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire out_uop_out_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_mask; // @[util.scala:104:23] wire [1:0] out_uop_out_1_br_tag; // @[util.scala:104:23] wire [3:0] out_uop_out_1_br_type; // @[util.scala:104:23] wire out_uop_out_1_is_sfb; // @[util.scala:104:23] wire out_uop_out_1_is_fence; // @[util.scala:104:23] wire out_uop_out_1_is_fencei; // @[util.scala:104:23] wire out_uop_out_1_is_sfence; // @[util.scala:104:23] wire out_uop_out_1_is_amo; // @[util.scala:104:23] wire out_uop_out_1_is_eret; // @[util.scala:104:23] wire out_uop_out_1_is_sys_pc2epc; // @[util.scala:104:23] wire out_uop_out_1_is_rocc; // @[util.scala:104:23] wire out_uop_out_1_is_mov; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ftq_idx; // @[util.scala:104:23] wire out_uop_out_1_edge_inst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pc_lob; // @[util.scala:104:23] wire out_uop_out_1_taken; // @[util.scala:104:23] wire out_uop_out_1_imm_rename; // @[util.scala:104:23] wire [2:0] out_uop_out_1_imm_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_pimm; // @[util.scala:104:23] wire [19:0] out_uop_out_1_imm_packed; // @[util.scala:104:23] wire [1:0] out_uop_out_1_op1_sel; // @[util.scala:104:23] wire [2:0] out_uop_out_1_op2_sel; // @[util.scala:104:23] wire [4:0] out_uop_out_1_rob_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ldq_idx; // @[util.scala:104:23] wire [3:0] out_uop_out_1_stq_idx; // @[util.scala:104:23] wire [1:0] out_uop_out_1_rxq_idx; // @[util.scala:104:23] wire [5:0] out_uop_out_1_pdst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_prs3; // @[util.scala:104:23] wire [3:0] out_uop_out_1_ppred; // @[util.scala:104:23] wire out_uop_out_1_prs1_busy; // @[util.scala:104:23] wire out_uop_out_1_prs2_busy; // @[util.scala:104:23] wire out_uop_out_1_prs3_busy; // @[util.scala:104:23] wire out_uop_out_1_ppred_busy; // @[util.scala:104:23] wire [5:0] out_uop_out_1_stale_pdst; // @[util.scala:104:23] wire out_uop_out_1_exception; // @[util.scala:104:23] wire [63:0] out_uop_out_1_exc_cause; // @[util.scala:104:23] wire [4:0] out_uop_out_1_mem_cmd; // @[util.scala:104:23] wire [1:0] out_uop_out_1_mem_size; // @[util.scala:104:23] wire out_uop_out_1_mem_signed; // @[util.scala:104:23] wire out_uop_out_1_uses_ldq; // @[util.scala:104:23] wire out_uop_out_1_uses_stq; // @[util.scala:104:23] wire out_uop_out_1_is_unique; // @[util.scala:104:23] wire out_uop_out_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] out_uop_out_1_csr_cmd; // @[util.scala:104:23] wire out_uop_out_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_ldst; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs1; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs2; // @[util.scala:104:23] wire [5:0] out_uop_out_1_lrs3; // @[util.scala:104:23] wire [1:0] out_uop_out_1_dst_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] out_uop_out_1_lrs2_rtype; // @[util.scala:104:23] wire out_uop_out_1_frs3_en; // @[util.scala:104:23] wire out_uop_out_1_fcn_dw; // @[util.scala:104:23] wire [4:0] out_uop_out_1_fcn_op; // @[util.scala:104:23] wire out_uop_out_1_fp_val; // @[util.scala:104:23] wire [2:0] out_uop_out_1_fp_rm; // @[util.scala:104:23] wire [1:0] out_uop_out_1_fp_typ; // @[util.scala:104:23] wire out_uop_out_1_xcpt_pf_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ae_if; // @[util.scala:104:23] wire out_uop_out_1_xcpt_ma_if; // @[util.scala:104:23] wire out_uop_out_1_bp_debug_if; // @[util.scala:104:23] wire out_uop_out_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] out_uop_out_1_debug_tsrc; // @[util.scala:104:23] assign out_uop_out_1_br_mask = _out_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] always @(posedge clock) begin // @[util.scala:458:7] if (main_io_deq_ready) begin // @[util.scala:495:23] out_reg_uop_inst <= _main_io_deq_bits_uop_inst; // @[util.scala:476:22, :477:22] out_reg_uop_debug_inst <= _main_io_deq_bits_uop_debug_inst; // @[util.scala:476:22, :477:22] out_reg_uop_is_rvc <= _main_io_deq_bits_uop_is_rvc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_pc <= _main_io_deq_bits_uop_debug_pc; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_0 <= _main_io_deq_bits_uop_iq_type_0; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_1 <= _main_io_deq_bits_uop_iq_type_1; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_2 <= _main_io_deq_bits_uop_iq_type_2; // @[util.scala:476:22, :477:22] out_reg_uop_iq_type_3 <= _main_io_deq_bits_uop_iq_type_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_0 <= _main_io_deq_bits_uop_fu_code_0; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_1 <= _main_io_deq_bits_uop_fu_code_1; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_2 <= _main_io_deq_bits_uop_fu_code_2; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_3 <= _main_io_deq_bits_uop_fu_code_3; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_4 <= _main_io_deq_bits_uop_fu_code_4; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_5 <= _main_io_deq_bits_uop_fu_code_5; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_6 <= _main_io_deq_bits_uop_fu_code_6; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_7 <= _main_io_deq_bits_uop_fu_code_7; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_8 <= _main_io_deq_bits_uop_fu_code_8; // @[util.scala:476:22, :477:22] out_reg_uop_fu_code_9 <= _main_io_deq_bits_uop_fu_code_9; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued <= _main_io_deq_bits_uop_iw_issued; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_agen <= _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_issued_partial_dgen <= _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_speculative_child <= _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_speculative_child <= _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p1_bypass_hint <= _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p2_bypass_hint <= _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_iw_p3_bypass_hint <= _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:476:22, :477:22] out_reg_uop_dis_col_sel <= _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:476:22, :477:22] out_reg_uop_br_mask <= _main_io_deq_bits_uop_br_mask; // @[util.scala:476:22, :477:22] out_reg_uop_br_tag <= _main_io_deq_bits_uop_br_tag; // @[util.scala:476:22, :477:22] out_reg_uop_br_type <= _main_io_deq_bits_uop_br_type; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfb <= _main_io_deq_bits_uop_is_sfb; // @[util.scala:476:22, :477:22] out_reg_uop_is_fence <= _main_io_deq_bits_uop_is_fence; // @[util.scala:476:22, :477:22] out_reg_uop_is_fencei <= _main_io_deq_bits_uop_is_fencei; // @[util.scala:476:22, :477:22] out_reg_uop_is_sfence <= _main_io_deq_bits_uop_is_sfence; // @[util.scala:476:22, :477:22] out_reg_uop_is_amo <= _main_io_deq_bits_uop_is_amo; // @[util.scala:476:22, :477:22] out_reg_uop_is_eret <= _main_io_deq_bits_uop_is_eret; // @[util.scala:476:22, :477:22] out_reg_uop_is_sys_pc2epc <= _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:476:22, :477:22] out_reg_uop_is_rocc <= _main_io_deq_bits_uop_is_rocc; // @[util.scala:476:22, :477:22] out_reg_uop_is_mov <= _main_io_deq_bits_uop_is_mov; // @[util.scala:476:22, :477:22] out_reg_uop_ftq_idx <= _main_io_deq_bits_uop_ftq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_edge_inst <= _main_io_deq_bits_uop_edge_inst; // @[util.scala:476:22, :477:22] out_reg_uop_pc_lob <= _main_io_deq_bits_uop_pc_lob; // @[util.scala:476:22, :477:22] out_reg_uop_taken <= _main_io_deq_bits_uop_taken; // @[util.scala:476:22, :477:22] out_reg_uop_imm_rename <= _main_io_deq_bits_uop_imm_rename; // @[util.scala:476:22, :477:22] out_reg_uop_imm_sel <= _main_io_deq_bits_uop_imm_sel; // @[util.scala:476:22, :477:22] out_reg_uop_pimm <= _main_io_deq_bits_uop_pimm; // @[util.scala:476:22, :477:22] out_reg_uop_imm_packed <= _main_io_deq_bits_uop_imm_packed; // @[util.scala:476:22, :477:22] out_reg_uop_op1_sel <= _main_io_deq_bits_uop_op1_sel; // @[util.scala:476:22, :477:22] out_reg_uop_op2_sel <= _main_io_deq_bits_uop_op2_sel; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ldst <= _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wen <= _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren1 <= _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren2 <= _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_ren3 <= _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap12 <= _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_swap23 <= _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagIn <= _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_typeTagOut <= _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fromint <= _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_toint <= _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fastpipe <= _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_fma <= _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_div <= _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_sqrt <= _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_wflags <= _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:476:22, :477:22] out_reg_uop_fp_ctrl_vec <= _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:476:22, :477:22] out_reg_uop_rob_idx <= _main_io_deq_bits_uop_rob_idx; // @[util.scala:476:22, :477:22] out_reg_uop_ldq_idx <= _main_io_deq_bits_uop_ldq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_stq_idx <= _main_io_deq_bits_uop_stq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_rxq_idx <= _main_io_deq_bits_uop_rxq_idx; // @[util.scala:476:22, :477:22] out_reg_uop_pdst <= _main_io_deq_bits_uop_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_prs1 <= _main_io_deq_bits_uop_prs1; // @[util.scala:476:22, :477:22] out_reg_uop_prs2 <= _main_io_deq_bits_uop_prs2; // @[util.scala:476:22, :477:22] out_reg_uop_prs3 <= _main_io_deq_bits_uop_prs3; // @[util.scala:476:22, :477:22] out_reg_uop_ppred <= _main_io_deq_bits_uop_ppred; // @[util.scala:476:22, :477:22] out_reg_uop_prs1_busy <= _main_io_deq_bits_uop_prs1_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs2_busy <= _main_io_deq_bits_uop_prs2_busy; // @[util.scala:476:22, :477:22] out_reg_uop_prs3_busy <= _main_io_deq_bits_uop_prs3_busy; // @[util.scala:476:22, :477:22] out_reg_uop_ppred_busy <= _main_io_deq_bits_uop_ppred_busy; // @[util.scala:476:22, :477:22] out_reg_uop_stale_pdst <= _main_io_deq_bits_uop_stale_pdst; // @[util.scala:476:22, :477:22] out_reg_uop_exception <= _main_io_deq_bits_uop_exception; // @[util.scala:476:22, :477:22] out_reg_uop_exc_cause <= _main_io_deq_bits_uop_exc_cause; // @[util.scala:476:22, :477:22] out_reg_uop_mem_cmd <= _main_io_deq_bits_uop_mem_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_mem_size <= _main_io_deq_bits_uop_mem_size; // @[util.scala:476:22, :477:22] out_reg_uop_mem_signed <= _main_io_deq_bits_uop_mem_signed; // @[util.scala:476:22, :477:22] out_reg_uop_uses_ldq <= _main_io_deq_bits_uop_uses_ldq; // @[util.scala:476:22, :477:22] out_reg_uop_uses_stq <= _main_io_deq_bits_uop_uses_stq; // @[util.scala:476:22, :477:22] out_reg_uop_is_unique <= _main_io_deq_bits_uop_is_unique; // @[util.scala:476:22, :477:22] out_reg_uop_flush_on_commit <= _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:476:22, :477:22] out_reg_uop_csr_cmd <= _main_io_deq_bits_uop_csr_cmd; // @[util.scala:476:22, :477:22] out_reg_uop_ldst_is_rs1 <= _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:476:22, :477:22] out_reg_uop_ldst <= _main_io_deq_bits_uop_ldst; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1 <= _main_io_deq_bits_uop_lrs1; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2 <= _main_io_deq_bits_uop_lrs2; // @[util.scala:476:22, :477:22] out_reg_uop_lrs3 <= _main_io_deq_bits_uop_lrs3; // @[util.scala:476:22, :477:22] out_reg_uop_dst_rtype <= _main_io_deq_bits_uop_dst_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs1_rtype <= _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_lrs2_rtype <= _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:476:22, :477:22] out_reg_uop_frs3_en <= _main_io_deq_bits_uop_frs3_en; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_dw <= _main_io_deq_bits_uop_fcn_dw; // @[util.scala:476:22, :477:22] out_reg_uop_fcn_op <= _main_io_deq_bits_uop_fcn_op; // @[util.scala:476:22, :477:22] out_reg_uop_fp_val <= _main_io_deq_bits_uop_fp_val; // @[util.scala:476:22, :477:22] out_reg_uop_fp_rm <= _main_io_deq_bits_uop_fp_rm; // @[util.scala:476:22, :477:22] out_reg_uop_fp_typ <= _main_io_deq_bits_uop_fp_typ; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_pf_if <= _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ae_if <= _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:476:22, :477:22] out_reg_uop_xcpt_ma_if <= _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_debug_if <= _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:476:22, :477:22] out_reg_uop_bp_xcpt_if <= _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:476:22, :477:22] out_reg_uop_debug_fsrc <= _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:476:22, :477:22] out_reg_uop_debug_tsrc <= _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:476:22, :477:22] out_reg_addr <= _main_io_deq_bits_addr; // @[util.scala:476:22, :477:22] out_reg_data <= _main_io_deq_bits_data; // @[util.scala:476:22, :477:22] out_reg_is_hella <= _main_io_deq_bits_is_hella; // @[util.scala:476:22, :477:22] out_reg_tag_match <= _main_io_deq_bits_tag_match; // @[util.scala:476:22, :477:22] out_reg_old_meta_coh_state <= _main_io_deq_bits_old_meta_coh_state; // @[util.scala:476:22, :477:22] out_reg_old_meta_tag <= _main_io_deq_bits_old_meta_tag; // @[util.scala:476:22, :477:22] out_reg_way_en <= _main_io_deq_bits_way_en; // @[util.scala:476:22, :477:22] out_reg_sdq_id <= _main_io_deq_bits_sdq_id; // @[util.scala:476:22, :477:22] end out_uop_inst <= main_io_deq_ready ? out_uop_out_1_inst : out_uop_out_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_inst <= main_io_deq_ready ? out_uop_out_1_debug_inst : out_uop_out_debug_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rvc <= main_io_deq_ready ? out_uop_out_1_is_rvc : out_uop_out_is_rvc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_pc <= main_io_deq_ready ? out_uop_out_1_debug_pc : out_uop_out_debug_pc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_0 <= main_io_deq_ready ? out_uop_out_1_iq_type_0 : out_uop_out_iq_type_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_1 <= main_io_deq_ready ? out_uop_out_1_iq_type_1 : out_uop_out_iq_type_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_2 <= main_io_deq_ready ? out_uop_out_1_iq_type_2 : out_uop_out_iq_type_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iq_type_3 <= main_io_deq_ready ? out_uop_out_1_iq_type_3 : out_uop_out_iq_type_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_0 <= main_io_deq_ready ? out_uop_out_1_fu_code_0 : out_uop_out_fu_code_0; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_1 <= main_io_deq_ready ? out_uop_out_1_fu_code_1 : out_uop_out_fu_code_1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_2 <= main_io_deq_ready ? out_uop_out_1_fu_code_2 : out_uop_out_fu_code_2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_3 <= main_io_deq_ready ? out_uop_out_1_fu_code_3 : out_uop_out_fu_code_3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_4 <= main_io_deq_ready ? out_uop_out_1_fu_code_4 : out_uop_out_fu_code_4; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_5 <= main_io_deq_ready ? out_uop_out_1_fu_code_5 : out_uop_out_fu_code_5; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_6 <= main_io_deq_ready ? out_uop_out_1_fu_code_6 : out_uop_out_fu_code_6; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_7 <= main_io_deq_ready ? out_uop_out_1_fu_code_7 : out_uop_out_fu_code_7; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_8 <= main_io_deq_ready ? out_uop_out_1_fu_code_8 : out_uop_out_fu_code_8; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fu_code_9 <= main_io_deq_ready ? out_uop_out_1_fu_code_9 : out_uop_out_fu_code_9; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued <= main_io_deq_ready ? out_uop_out_1_iw_issued : out_uop_out_iw_issued; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_agen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_agen : out_uop_out_iw_issued_partial_agen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_issued_partial_dgen <= main_io_deq_ready ? out_uop_out_1_iw_issued_partial_dgen : out_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p1_speculative_child : out_uop_out_iw_p1_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_speculative_child <= main_io_deq_ready ? out_uop_out_1_iw_p2_speculative_child : out_uop_out_iw_p2_speculative_child; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p1_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p1_bypass_hint : out_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p2_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p2_bypass_hint : out_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_iw_p3_bypass_hint <= main_io_deq_ready ? out_uop_out_1_iw_p3_bypass_hint : out_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dis_col_sel <= main_io_deq_ready ? out_uop_out_1_dis_col_sel : out_uop_out_dis_col_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_mask <= main_io_deq_ready ? out_uop_out_1_br_mask : out_uop_out_br_mask; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_tag <= main_io_deq_ready ? out_uop_out_1_br_tag : out_uop_out_br_tag; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_br_type <= main_io_deq_ready ? out_uop_out_1_br_type : out_uop_out_br_type; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfb <= main_io_deq_ready ? out_uop_out_1_is_sfb : out_uop_out_is_sfb; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fence <= main_io_deq_ready ? out_uop_out_1_is_fence : out_uop_out_is_fence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_fencei <= main_io_deq_ready ? out_uop_out_1_is_fencei : out_uop_out_is_fencei; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sfence <= main_io_deq_ready ? out_uop_out_1_is_sfence : out_uop_out_is_sfence; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_amo <= main_io_deq_ready ? out_uop_out_1_is_amo : out_uop_out_is_amo; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_eret <= main_io_deq_ready ? out_uop_out_1_is_eret : out_uop_out_is_eret; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_sys_pc2epc <= main_io_deq_ready ? out_uop_out_1_is_sys_pc2epc : out_uop_out_is_sys_pc2epc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_rocc <= main_io_deq_ready ? out_uop_out_1_is_rocc : out_uop_out_is_rocc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_mov <= main_io_deq_ready ? out_uop_out_1_is_mov : out_uop_out_is_mov; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ftq_idx <= main_io_deq_ready ? out_uop_out_1_ftq_idx : out_uop_out_ftq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_edge_inst <= main_io_deq_ready ? out_uop_out_1_edge_inst : out_uop_out_edge_inst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pc_lob <= main_io_deq_ready ? out_uop_out_1_pc_lob : out_uop_out_pc_lob; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_taken <= main_io_deq_ready ? out_uop_out_1_taken : out_uop_out_taken; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_rename <= main_io_deq_ready ? out_uop_out_1_imm_rename : out_uop_out_imm_rename; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_sel <= main_io_deq_ready ? out_uop_out_1_imm_sel : out_uop_out_imm_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pimm <= main_io_deq_ready ? out_uop_out_1_pimm : out_uop_out_pimm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_imm_packed <= main_io_deq_ready ? out_uop_out_1_imm_packed : out_uop_out_imm_packed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op1_sel <= main_io_deq_ready ? out_uop_out_1_op1_sel : out_uop_out_op1_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_op2_sel <= main_io_deq_ready ? out_uop_out_1_op2_sel : out_uop_out_op2_sel; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ldst <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ldst : out_uop_out_fp_ctrl_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wen <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wen : out_uop_out_fp_ctrl_wen; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren1 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren1 : out_uop_out_fp_ctrl_ren1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren2 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren2 : out_uop_out_fp_ctrl_ren2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_ren3 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_ren3 : out_uop_out_fp_ctrl_ren3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap12 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap12 : out_uop_out_fp_ctrl_swap12; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_swap23 <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_swap23 : out_uop_out_fp_ctrl_swap23; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagIn <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagIn : out_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_typeTagOut <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_typeTagOut : out_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fromint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fromint : out_uop_out_fp_ctrl_fromint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_toint <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_toint : out_uop_out_fp_ctrl_toint; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fastpipe <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fastpipe : out_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_fma <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_fma : out_uop_out_fp_ctrl_fma; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_div <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_div : out_uop_out_fp_ctrl_div; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_sqrt <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_sqrt : out_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_wflags <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_wflags : out_uop_out_fp_ctrl_wflags; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_ctrl_vec <= main_io_deq_ready ? out_uop_out_1_fp_ctrl_vec : out_uop_out_fp_ctrl_vec; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rob_idx <= main_io_deq_ready ? out_uop_out_1_rob_idx : out_uop_out_rob_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldq_idx <= main_io_deq_ready ? out_uop_out_1_ldq_idx : out_uop_out_ldq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stq_idx <= main_io_deq_ready ? out_uop_out_1_stq_idx : out_uop_out_stq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_rxq_idx <= main_io_deq_ready ? out_uop_out_1_rxq_idx : out_uop_out_rxq_idx; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_pdst <= main_io_deq_ready ? out_uop_out_1_pdst : out_uop_out_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1 <= main_io_deq_ready ? out_uop_out_1_prs1 : out_uop_out_prs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2 <= main_io_deq_ready ? out_uop_out_1_prs2 : out_uop_out_prs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3 <= main_io_deq_ready ? out_uop_out_1_prs3 : out_uop_out_prs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred <= main_io_deq_ready ? out_uop_out_1_ppred : out_uop_out_ppred; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs1_busy <= main_io_deq_ready ? out_uop_out_1_prs1_busy : out_uop_out_prs1_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs2_busy <= main_io_deq_ready ? out_uop_out_1_prs2_busy : out_uop_out_prs2_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_prs3_busy <= main_io_deq_ready ? out_uop_out_1_prs3_busy : out_uop_out_prs3_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ppred_busy <= main_io_deq_ready ? out_uop_out_1_ppred_busy : out_uop_out_ppred_busy; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_stale_pdst <= main_io_deq_ready ? out_uop_out_1_stale_pdst : out_uop_out_stale_pdst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exception <= main_io_deq_ready ? out_uop_out_1_exception : out_uop_out_exception; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_exc_cause <= main_io_deq_ready ? out_uop_out_1_exc_cause : out_uop_out_exc_cause; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_cmd <= main_io_deq_ready ? out_uop_out_1_mem_cmd : out_uop_out_mem_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_size <= main_io_deq_ready ? out_uop_out_1_mem_size : out_uop_out_mem_size; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_mem_signed <= main_io_deq_ready ? out_uop_out_1_mem_signed : out_uop_out_mem_signed; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_ldq <= main_io_deq_ready ? out_uop_out_1_uses_ldq : out_uop_out_uses_ldq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_uses_stq <= main_io_deq_ready ? out_uop_out_1_uses_stq : out_uop_out_uses_stq; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_is_unique <= main_io_deq_ready ? out_uop_out_1_is_unique : out_uop_out_is_unique; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_flush_on_commit <= main_io_deq_ready ? out_uop_out_1_flush_on_commit : out_uop_out_flush_on_commit; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_csr_cmd <= main_io_deq_ready ? out_uop_out_1_csr_cmd : out_uop_out_csr_cmd; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst_is_rs1 <= main_io_deq_ready ? out_uop_out_1_ldst_is_rs1 : out_uop_out_ldst_is_rs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_ldst <= main_io_deq_ready ? out_uop_out_1_ldst : out_uop_out_ldst; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1 <= main_io_deq_ready ? out_uop_out_1_lrs1 : out_uop_out_lrs1; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2 <= main_io_deq_ready ? out_uop_out_1_lrs2 : out_uop_out_lrs2; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs3 <= main_io_deq_ready ? out_uop_out_1_lrs3 : out_uop_out_lrs3; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_dst_rtype <= main_io_deq_ready ? out_uop_out_1_dst_rtype : out_uop_out_dst_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs1_rtype <= main_io_deq_ready ? out_uop_out_1_lrs1_rtype : out_uop_out_lrs1_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_lrs2_rtype <= main_io_deq_ready ? out_uop_out_1_lrs2_rtype : out_uop_out_lrs2_rtype; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_frs3_en <= main_io_deq_ready ? out_uop_out_1_frs3_en : out_uop_out_frs3_en; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_dw <= main_io_deq_ready ? out_uop_out_1_fcn_dw : out_uop_out_fcn_dw; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fcn_op <= main_io_deq_ready ? out_uop_out_1_fcn_op : out_uop_out_fcn_op; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_val <= main_io_deq_ready ? out_uop_out_1_fp_val : out_uop_out_fp_val; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_rm <= main_io_deq_ready ? out_uop_out_1_fp_rm : out_uop_out_fp_rm; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_fp_typ <= main_io_deq_ready ? out_uop_out_1_fp_typ : out_uop_out_fp_typ; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_pf_if <= main_io_deq_ready ? out_uop_out_1_xcpt_pf_if : out_uop_out_xcpt_pf_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ae_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ae_if : out_uop_out_xcpt_ae_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_xcpt_ma_if <= main_io_deq_ready ? out_uop_out_1_xcpt_ma_if : out_uop_out_xcpt_ma_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_debug_if <= main_io_deq_ready ? out_uop_out_1_bp_debug_if : out_uop_out_bp_debug_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_bp_xcpt_if <= main_io_deq_ready ? out_uop_out_1_bp_xcpt_if : out_uop_out_bp_xcpt_if; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_fsrc <= main_io_deq_ready ? out_uop_out_1_debug_fsrc : out_uop_out_debug_fsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] out_uop_debug_tsrc <= main_io_deq_ready ? out_uop_out_1_debug_tsrc : out_uop_out_debug_tsrc; // @[util.scala:104:23, :479:22, :491:13, :495:{23,38}, :498:15] if (reset) // @[util.scala:458:7] out_valid <= 1'h0; // @[util.scala:478:28] else // @[util.scala:458:7] out_valid <= main_io_deq_ready ? _out_valid_T_15 : _out_valid_T_7; // @[util.scala:478:28, :492:{15,80}, :495:{23,38}, :496:{17,103}] always @(posedge) BranchKillableQueue_26 main ( // @[util.scala:476:22] .clock (clock), .reset (reset), .io_enq_ready (io_enq_ready_0), .io_enq_valid (io_enq_valid_0), // @[util.scala:458:7] .io_enq_bits_uop_inst (io_enq_bits_uop_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_inst (io_enq_bits_uop_debug_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rvc (io_enq_bits_uop_is_rvc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_pc (io_enq_bits_uop_debug_pc_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_0 (io_enq_bits_uop_iq_type_0_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_1 (io_enq_bits_uop_iq_type_1_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_2 (io_enq_bits_uop_iq_type_2_0), // @[util.scala:458:7] .io_enq_bits_uop_iq_type_3 (io_enq_bits_uop_iq_type_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_0 (io_enq_bits_uop_fu_code_0_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_1 (io_enq_bits_uop_fu_code_1_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_2 (io_enq_bits_uop_fu_code_2_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_3 (io_enq_bits_uop_fu_code_3_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_4 (io_enq_bits_uop_fu_code_4_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_5 (io_enq_bits_uop_fu_code_5_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_6 (io_enq_bits_uop_fu_code_6_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_7 (io_enq_bits_uop_fu_code_7_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_8 (io_enq_bits_uop_fu_code_8_0), // @[util.scala:458:7] .io_enq_bits_uop_fu_code_9 (io_enq_bits_uop_fu_code_9_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued (io_enq_bits_uop_iw_issued_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_agen (io_enq_bits_uop_iw_issued_partial_agen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_issued_partial_dgen (io_enq_bits_uop_iw_issued_partial_dgen_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_speculative_child (io_enq_bits_uop_iw_p1_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_speculative_child (io_enq_bits_uop_iw_p2_speculative_child_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p1_bypass_hint (io_enq_bits_uop_iw_p1_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p2_bypass_hint (io_enq_bits_uop_iw_p2_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_iw_p3_bypass_hint (io_enq_bits_uop_iw_p3_bypass_hint_0), // @[util.scala:458:7] .io_enq_bits_uop_dis_col_sel (io_enq_bits_uop_dis_col_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_br_mask (io_enq_bits_uop_br_mask_0), // @[util.scala:458:7] .io_enq_bits_uop_br_tag (io_enq_bits_uop_br_tag_0), // @[util.scala:458:7] .io_enq_bits_uop_br_type (io_enq_bits_uop_br_type_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfb (io_enq_bits_uop_is_sfb_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fence (io_enq_bits_uop_is_fence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_fencei (io_enq_bits_uop_is_fencei_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sfence (io_enq_bits_uop_is_sfence_0), // @[util.scala:458:7] .io_enq_bits_uop_is_amo (io_enq_bits_uop_is_amo_0), // @[util.scala:458:7] .io_enq_bits_uop_is_eret (io_enq_bits_uop_is_eret_0), // @[util.scala:458:7] .io_enq_bits_uop_is_sys_pc2epc (io_enq_bits_uop_is_sys_pc2epc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_rocc (io_enq_bits_uop_is_rocc_0), // @[util.scala:458:7] .io_enq_bits_uop_is_mov (io_enq_bits_uop_is_mov_0), // @[util.scala:458:7] .io_enq_bits_uop_ftq_idx (io_enq_bits_uop_ftq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_edge_inst (io_enq_bits_uop_edge_inst_0), // @[util.scala:458:7] .io_enq_bits_uop_pc_lob (io_enq_bits_uop_pc_lob_0), // @[util.scala:458:7] .io_enq_bits_uop_taken (io_enq_bits_uop_taken_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_rename (io_enq_bits_uop_imm_rename_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_sel (io_enq_bits_uop_imm_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_pimm (io_enq_bits_uop_pimm_0), // @[util.scala:458:7] .io_enq_bits_uop_imm_packed (io_enq_bits_uop_imm_packed_0), // @[util.scala:458:7] .io_enq_bits_uop_op1_sel (io_enq_bits_uop_op1_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_op2_sel (io_enq_bits_uop_op2_sel_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ldst (io_enq_bits_uop_fp_ctrl_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wen (io_enq_bits_uop_fp_ctrl_wen_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren1 (io_enq_bits_uop_fp_ctrl_ren1_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren2 (io_enq_bits_uop_fp_ctrl_ren2_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_ren3 (io_enq_bits_uop_fp_ctrl_ren3_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap12 (io_enq_bits_uop_fp_ctrl_swap12_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_swap23 (io_enq_bits_uop_fp_ctrl_swap23_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagIn (io_enq_bits_uop_fp_ctrl_typeTagIn_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_typeTagOut (io_enq_bits_uop_fp_ctrl_typeTagOut_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fromint (io_enq_bits_uop_fp_ctrl_fromint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_toint (io_enq_bits_uop_fp_ctrl_toint_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fastpipe (io_enq_bits_uop_fp_ctrl_fastpipe_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_fma (io_enq_bits_uop_fp_ctrl_fma_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_div (io_enq_bits_uop_fp_ctrl_div_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_sqrt (io_enq_bits_uop_fp_ctrl_sqrt_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_wflags (io_enq_bits_uop_fp_ctrl_wflags_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_ctrl_vec (io_enq_bits_uop_fp_ctrl_vec_0), // @[util.scala:458:7] .io_enq_bits_uop_rob_idx (io_enq_bits_uop_rob_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_ldq_idx (io_enq_bits_uop_ldq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_stq_idx (io_enq_bits_uop_stq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_rxq_idx (io_enq_bits_uop_rxq_idx_0), // @[util.scala:458:7] .io_enq_bits_uop_pdst (io_enq_bits_uop_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1 (io_enq_bits_uop_prs1_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2 (io_enq_bits_uop_prs2_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3 (io_enq_bits_uop_prs3_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred (io_enq_bits_uop_ppred_0), // @[util.scala:458:7] .io_enq_bits_uop_prs1_busy (io_enq_bits_uop_prs1_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs2_busy (io_enq_bits_uop_prs2_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_prs3_busy (io_enq_bits_uop_prs3_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_ppred_busy (io_enq_bits_uop_ppred_busy_0), // @[util.scala:458:7] .io_enq_bits_uop_stale_pdst (io_enq_bits_uop_stale_pdst_0), // @[util.scala:458:7] .io_enq_bits_uop_exception (io_enq_bits_uop_exception_0), // @[util.scala:458:7] .io_enq_bits_uop_exc_cause (io_enq_bits_uop_exc_cause_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_cmd (io_enq_bits_uop_mem_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_size (io_enq_bits_uop_mem_size_0), // @[util.scala:458:7] .io_enq_bits_uop_mem_signed (io_enq_bits_uop_mem_signed_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_ldq (io_enq_bits_uop_uses_ldq_0), // @[util.scala:458:7] .io_enq_bits_uop_uses_stq (io_enq_bits_uop_uses_stq_0), // @[util.scala:458:7] .io_enq_bits_uop_is_unique (io_enq_bits_uop_is_unique_0), // @[util.scala:458:7] .io_enq_bits_uop_flush_on_commit (io_enq_bits_uop_flush_on_commit_0), // @[util.scala:458:7] .io_enq_bits_uop_csr_cmd (io_enq_bits_uop_csr_cmd_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst_is_rs1 (io_enq_bits_uop_ldst_is_rs1_0), // @[util.scala:458:7] .io_enq_bits_uop_ldst (io_enq_bits_uop_ldst_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1 (io_enq_bits_uop_lrs1_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2 (io_enq_bits_uop_lrs2_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs3 (io_enq_bits_uop_lrs3_0), // @[util.scala:458:7] .io_enq_bits_uop_dst_rtype (io_enq_bits_uop_dst_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs1_rtype (io_enq_bits_uop_lrs1_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_lrs2_rtype (io_enq_bits_uop_lrs2_rtype_0), // @[util.scala:458:7] .io_enq_bits_uop_frs3_en (io_enq_bits_uop_frs3_en_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_dw (io_enq_bits_uop_fcn_dw_0), // @[util.scala:458:7] .io_enq_bits_uop_fcn_op (io_enq_bits_uop_fcn_op_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_val (io_enq_bits_uop_fp_val_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_rm (io_enq_bits_uop_fp_rm_0), // @[util.scala:458:7] .io_enq_bits_uop_fp_typ (io_enq_bits_uop_fp_typ_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_pf_if (io_enq_bits_uop_xcpt_pf_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ae_if (io_enq_bits_uop_xcpt_ae_if_0), // @[util.scala:458:7] .io_enq_bits_uop_xcpt_ma_if (io_enq_bits_uop_xcpt_ma_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_debug_if (io_enq_bits_uop_bp_debug_if_0), // @[util.scala:458:7] .io_enq_bits_uop_bp_xcpt_if (io_enq_bits_uop_bp_xcpt_if_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_fsrc (io_enq_bits_uop_debug_fsrc_0), // @[util.scala:458:7] .io_enq_bits_uop_debug_tsrc (io_enq_bits_uop_debug_tsrc_0), // @[util.scala:458:7] .io_enq_bits_addr (io_enq_bits_addr_0), // @[util.scala:458:7] .io_enq_bits_data (io_enq_bits_data_0), // @[util.scala:458:7] .io_enq_bits_is_hella (io_enq_bits_is_hella_0), // @[util.scala:458:7] .io_enq_bits_tag_match (io_enq_bits_tag_match_0), // @[util.scala:458:7] .io_enq_bits_old_meta_coh_state (io_enq_bits_old_meta_coh_state_0), // @[util.scala:458:7] .io_enq_bits_old_meta_tag (io_enq_bits_old_meta_tag_0), // @[util.scala:458:7] .io_enq_bits_way_en (io_enq_bits_way_en_0), // @[util.scala:458:7] .io_enq_bits_sdq_id (io_enq_bits_sdq_id_0), // @[util.scala:458:7] .io_deq_ready (main_io_deq_ready), // @[util.scala:495:23] .io_deq_valid (_out_valid_T_12), .io_deq_bits_uop_inst (_main_io_deq_bits_uop_inst), .io_deq_bits_uop_debug_inst (_main_io_deq_bits_uop_debug_inst), .io_deq_bits_uop_is_rvc (_main_io_deq_bits_uop_is_rvc), .io_deq_bits_uop_debug_pc (_main_io_deq_bits_uop_debug_pc), .io_deq_bits_uop_iq_type_0 (_main_io_deq_bits_uop_iq_type_0), .io_deq_bits_uop_iq_type_1 (_main_io_deq_bits_uop_iq_type_1), .io_deq_bits_uop_iq_type_2 (_main_io_deq_bits_uop_iq_type_2), .io_deq_bits_uop_iq_type_3 (_main_io_deq_bits_uop_iq_type_3), .io_deq_bits_uop_fu_code_0 (_main_io_deq_bits_uop_fu_code_0), .io_deq_bits_uop_fu_code_1 (_main_io_deq_bits_uop_fu_code_1), .io_deq_bits_uop_fu_code_2 (_main_io_deq_bits_uop_fu_code_2), .io_deq_bits_uop_fu_code_3 (_main_io_deq_bits_uop_fu_code_3), .io_deq_bits_uop_fu_code_4 (_main_io_deq_bits_uop_fu_code_4), .io_deq_bits_uop_fu_code_5 (_main_io_deq_bits_uop_fu_code_5), .io_deq_bits_uop_fu_code_6 (_main_io_deq_bits_uop_fu_code_6), .io_deq_bits_uop_fu_code_7 (_main_io_deq_bits_uop_fu_code_7), .io_deq_bits_uop_fu_code_8 (_main_io_deq_bits_uop_fu_code_8), .io_deq_bits_uop_fu_code_9 (_main_io_deq_bits_uop_fu_code_9), .io_deq_bits_uop_iw_issued (_main_io_deq_bits_uop_iw_issued), .io_deq_bits_uop_iw_issued_partial_agen (_main_io_deq_bits_uop_iw_issued_partial_agen), .io_deq_bits_uop_iw_issued_partial_dgen (_main_io_deq_bits_uop_iw_issued_partial_dgen), .io_deq_bits_uop_iw_p1_speculative_child (_main_io_deq_bits_uop_iw_p1_speculative_child), .io_deq_bits_uop_iw_p2_speculative_child (_main_io_deq_bits_uop_iw_p2_speculative_child), .io_deq_bits_uop_iw_p1_bypass_hint (_main_io_deq_bits_uop_iw_p1_bypass_hint), .io_deq_bits_uop_iw_p2_bypass_hint (_main_io_deq_bits_uop_iw_p2_bypass_hint), .io_deq_bits_uop_iw_p3_bypass_hint (_main_io_deq_bits_uop_iw_p3_bypass_hint), .io_deq_bits_uop_dis_col_sel (_main_io_deq_bits_uop_dis_col_sel), .io_deq_bits_uop_br_mask (_main_io_deq_bits_uop_br_mask), .io_deq_bits_uop_br_tag (_main_io_deq_bits_uop_br_tag), .io_deq_bits_uop_br_type (_main_io_deq_bits_uop_br_type), .io_deq_bits_uop_is_sfb (_main_io_deq_bits_uop_is_sfb), .io_deq_bits_uop_is_fence (_main_io_deq_bits_uop_is_fence), .io_deq_bits_uop_is_fencei (_main_io_deq_bits_uop_is_fencei), .io_deq_bits_uop_is_sfence (_main_io_deq_bits_uop_is_sfence), .io_deq_bits_uop_is_amo (_main_io_deq_bits_uop_is_amo), .io_deq_bits_uop_is_eret (_main_io_deq_bits_uop_is_eret), .io_deq_bits_uop_is_sys_pc2epc (_main_io_deq_bits_uop_is_sys_pc2epc), .io_deq_bits_uop_is_rocc (_main_io_deq_bits_uop_is_rocc), .io_deq_bits_uop_is_mov (_main_io_deq_bits_uop_is_mov), .io_deq_bits_uop_ftq_idx (_main_io_deq_bits_uop_ftq_idx), .io_deq_bits_uop_edge_inst (_main_io_deq_bits_uop_edge_inst), .io_deq_bits_uop_pc_lob (_main_io_deq_bits_uop_pc_lob), .io_deq_bits_uop_taken (_main_io_deq_bits_uop_taken), .io_deq_bits_uop_imm_rename (_main_io_deq_bits_uop_imm_rename), .io_deq_bits_uop_imm_sel (_main_io_deq_bits_uop_imm_sel), .io_deq_bits_uop_pimm (_main_io_deq_bits_uop_pimm), .io_deq_bits_uop_imm_packed (_main_io_deq_bits_uop_imm_packed), .io_deq_bits_uop_op1_sel (_main_io_deq_bits_uop_op1_sel), .io_deq_bits_uop_op2_sel (_main_io_deq_bits_uop_op2_sel), .io_deq_bits_uop_fp_ctrl_ldst (_main_io_deq_bits_uop_fp_ctrl_ldst), .io_deq_bits_uop_fp_ctrl_wen (_main_io_deq_bits_uop_fp_ctrl_wen), .io_deq_bits_uop_fp_ctrl_ren1 (_main_io_deq_bits_uop_fp_ctrl_ren1), .io_deq_bits_uop_fp_ctrl_ren2 (_main_io_deq_bits_uop_fp_ctrl_ren2), .io_deq_bits_uop_fp_ctrl_ren3 (_main_io_deq_bits_uop_fp_ctrl_ren3), .io_deq_bits_uop_fp_ctrl_swap12 (_main_io_deq_bits_uop_fp_ctrl_swap12), .io_deq_bits_uop_fp_ctrl_swap23 (_main_io_deq_bits_uop_fp_ctrl_swap23), .io_deq_bits_uop_fp_ctrl_typeTagIn (_main_io_deq_bits_uop_fp_ctrl_typeTagIn), .io_deq_bits_uop_fp_ctrl_typeTagOut (_main_io_deq_bits_uop_fp_ctrl_typeTagOut), .io_deq_bits_uop_fp_ctrl_fromint (_main_io_deq_bits_uop_fp_ctrl_fromint), .io_deq_bits_uop_fp_ctrl_toint (_main_io_deq_bits_uop_fp_ctrl_toint), .io_deq_bits_uop_fp_ctrl_fastpipe (_main_io_deq_bits_uop_fp_ctrl_fastpipe), .io_deq_bits_uop_fp_ctrl_fma (_main_io_deq_bits_uop_fp_ctrl_fma), .io_deq_bits_uop_fp_ctrl_div (_main_io_deq_bits_uop_fp_ctrl_div), .io_deq_bits_uop_fp_ctrl_sqrt (_main_io_deq_bits_uop_fp_ctrl_sqrt), .io_deq_bits_uop_fp_ctrl_wflags (_main_io_deq_bits_uop_fp_ctrl_wflags), .io_deq_bits_uop_fp_ctrl_vec (_main_io_deq_bits_uop_fp_ctrl_vec), .io_deq_bits_uop_rob_idx (_main_io_deq_bits_uop_rob_idx), .io_deq_bits_uop_ldq_idx (_main_io_deq_bits_uop_ldq_idx), .io_deq_bits_uop_stq_idx (_main_io_deq_bits_uop_stq_idx), .io_deq_bits_uop_rxq_idx (_main_io_deq_bits_uop_rxq_idx), .io_deq_bits_uop_pdst (_main_io_deq_bits_uop_pdst), .io_deq_bits_uop_prs1 (_main_io_deq_bits_uop_prs1), .io_deq_bits_uop_prs2 (_main_io_deq_bits_uop_prs2), .io_deq_bits_uop_prs3 (_main_io_deq_bits_uop_prs3), .io_deq_bits_uop_ppred (_main_io_deq_bits_uop_ppred), .io_deq_bits_uop_prs1_busy (_main_io_deq_bits_uop_prs1_busy), .io_deq_bits_uop_prs2_busy (_main_io_deq_bits_uop_prs2_busy), .io_deq_bits_uop_prs3_busy (_main_io_deq_bits_uop_prs3_busy), .io_deq_bits_uop_ppred_busy (_main_io_deq_bits_uop_ppred_busy), .io_deq_bits_uop_stale_pdst (_main_io_deq_bits_uop_stale_pdst), .io_deq_bits_uop_exception (_main_io_deq_bits_uop_exception), .io_deq_bits_uop_exc_cause (_main_io_deq_bits_uop_exc_cause), .io_deq_bits_uop_mem_cmd (_main_io_deq_bits_uop_mem_cmd), .io_deq_bits_uop_mem_size (_main_io_deq_bits_uop_mem_size), .io_deq_bits_uop_mem_signed (_main_io_deq_bits_uop_mem_signed), .io_deq_bits_uop_uses_ldq (_main_io_deq_bits_uop_uses_ldq), .io_deq_bits_uop_uses_stq (_main_io_deq_bits_uop_uses_stq), .io_deq_bits_uop_is_unique (_main_io_deq_bits_uop_is_unique), .io_deq_bits_uop_flush_on_commit (_main_io_deq_bits_uop_flush_on_commit), .io_deq_bits_uop_csr_cmd (_main_io_deq_bits_uop_csr_cmd), .io_deq_bits_uop_ldst_is_rs1 (_main_io_deq_bits_uop_ldst_is_rs1), .io_deq_bits_uop_ldst (_main_io_deq_bits_uop_ldst), .io_deq_bits_uop_lrs1 (_main_io_deq_bits_uop_lrs1), .io_deq_bits_uop_lrs2 (_main_io_deq_bits_uop_lrs2), .io_deq_bits_uop_lrs3 (_main_io_deq_bits_uop_lrs3), .io_deq_bits_uop_dst_rtype (_main_io_deq_bits_uop_dst_rtype), .io_deq_bits_uop_lrs1_rtype (_main_io_deq_bits_uop_lrs1_rtype), .io_deq_bits_uop_lrs2_rtype (_main_io_deq_bits_uop_lrs2_rtype), .io_deq_bits_uop_frs3_en (_main_io_deq_bits_uop_frs3_en), .io_deq_bits_uop_fcn_dw (_main_io_deq_bits_uop_fcn_dw), .io_deq_bits_uop_fcn_op (_main_io_deq_bits_uop_fcn_op), .io_deq_bits_uop_fp_val (_main_io_deq_bits_uop_fp_val), .io_deq_bits_uop_fp_rm (_main_io_deq_bits_uop_fp_rm), .io_deq_bits_uop_fp_typ (_main_io_deq_bits_uop_fp_typ), .io_deq_bits_uop_xcpt_pf_if (_main_io_deq_bits_uop_xcpt_pf_if), .io_deq_bits_uop_xcpt_ae_if (_main_io_deq_bits_uop_xcpt_ae_if), .io_deq_bits_uop_xcpt_ma_if (_main_io_deq_bits_uop_xcpt_ma_if), .io_deq_bits_uop_bp_debug_if (_main_io_deq_bits_uop_bp_debug_if), .io_deq_bits_uop_bp_xcpt_if (_main_io_deq_bits_uop_bp_xcpt_if), .io_deq_bits_uop_debug_fsrc (_main_io_deq_bits_uop_debug_fsrc), .io_deq_bits_uop_debug_tsrc (_main_io_deq_bits_uop_debug_tsrc), .io_deq_bits_addr (_main_io_deq_bits_addr), .io_deq_bits_data (_main_io_deq_bits_data), .io_deq_bits_is_hella (_main_io_deq_bits_is_hella), .io_deq_bits_tag_match (_main_io_deq_bits_tag_match), .io_deq_bits_old_meta_coh_state (_main_io_deq_bits_old_meta_coh_state), .io_deq_bits_old_meta_tag (_main_io_deq_bits_old_meta_tag), .io_deq_bits_way_en (_main_io_deq_bits_way_en), .io_deq_bits_sdq_id (_main_io_deq_bits_sdq_id), .io_empty (_main_io_empty), .io_count (_main_io_count) ); // @[util.scala:476:22] assign out_uop_out_1_inst = _main_io_deq_bits_uop_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_inst = _main_io_deq_bits_uop_debug_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rvc = _main_io_deq_bits_uop_is_rvc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_pc = _main_io_deq_bits_uop_debug_pc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_0 = _main_io_deq_bits_uop_iq_type_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_1 = _main_io_deq_bits_uop_iq_type_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_2 = _main_io_deq_bits_uop_iq_type_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iq_type_3 = _main_io_deq_bits_uop_iq_type_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_0 = _main_io_deq_bits_uop_fu_code_0; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_1 = _main_io_deq_bits_uop_fu_code_1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_2 = _main_io_deq_bits_uop_fu_code_2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_3 = _main_io_deq_bits_uop_fu_code_3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_4 = _main_io_deq_bits_uop_fu_code_4; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_5 = _main_io_deq_bits_uop_fu_code_5; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_6 = _main_io_deq_bits_uop_fu_code_6; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_7 = _main_io_deq_bits_uop_fu_code_7; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_8 = _main_io_deq_bits_uop_fu_code_8; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fu_code_9 = _main_io_deq_bits_uop_fu_code_9; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued = _main_io_deq_bits_uop_iw_issued; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_agen = _main_io_deq_bits_uop_iw_issued_partial_agen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_issued_partial_dgen = _main_io_deq_bits_uop_iw_issued_partial_dgen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_speculative_child = _main_io_deq_bits_uop_iw_p1_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_speculative_child = _main_io_deq_bits_uop_iw_p2_speculative_child; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p1_bypass_hint = _main_io_deq_bits_uop_iw_p1_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p2_bypass_hint = _main_io_deq_bits_uop_iw_p2_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_iw_p3_bypass_hint = _main_io_deq_bits_uop_iw_p3_bypass_hint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dis_col_sel = _main_io_deq_bits_uop_dis_col_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_tag = _main_io_deq_bits_uop_br_tag; // @[util.scala:104:23, :476:22] assign out_uop_out_1_br_type = _main_io_deq_bits_uop_br_type; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfb = _main_io_deq_bits_uop_is_sfb; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fence = _main_io_deq_bits_uop_is_fence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_fencei = _main_io_deq_bits_uop_is_fencei; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sfence = _main_io_deq_bits_uop_is_sfence; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_amo = _main_io_deq_bits_uop_is_amo; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_eret = _main_io_deq_bits_uop_is_eret; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_sys_pc2epc = _main_io_deq_bits_uop_is_sys_pc2epc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_rocc = _main_io_deq_bits_uop_is_rocc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_mov = _main_io_deq_bits_uop_is_mov; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ftq_idx = _main_io_deq_bits_uop_ftq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_edge_inst = _main_io_deq_bits_uop_edge_inst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pc_lob = _main_io_deq_bits_uop_pc_lob; // @[util.scala:104:23, :476:22] assign out_uop_out_1_taken = _main_io_deq_bits_uop_taken; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_rename = _main_io_deq_bits_uop_imm_rename; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_sel = _main_io_deq_bits_uop_imm_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pimm = _main_io_deq_bits_uop_pimm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_imm_packed = _main_io_deq_bits_uop_imm_packed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op1_sel = _main_io_deq_bits_uop_op1_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_op2_sel = _main_io_deq_bits_uop_op2_sel; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ldst = _main_io_deq_bits_uop_fp_ctrl_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wen = _main_io_deq_bits_uop_fp_ctrl_wen; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren1 = _main_io_deq_bits_uop_fp_ctrl_ren1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren2 = _main_io_deq_bits_uop_fp_ctrl_ren2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_ren3 = _main_io_deq_bits_uop_fp_ctrl_ren3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap12 = _main_io_deq_bits_uop_fp_ctrl_swap12; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_swap23 = _main_io_deq_bits_uop_fp_ctrl_swap23; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagIn = _main_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_typeTagOut = _main_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fromint = _main_io_deq_bits_uop_fp_ctrl_fromint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_toint = _main_io_deq_bits_uop_fp_ctrl_toint; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fastpipe = _main_io_deq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_fma = _main_io_deq_bits_uop_fp_ctrl_fma; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_div = _main_io_deq_bits_uop_fp_ctrl_div; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_sqrt = _main_io_deq_bits_uop_fp_ctrl_sqrt; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_wflags = _main_io_deq_bits_uop_fp_ctrl_wflags; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_ctrl_vec = _main_io_deq_bits_uop_fp_ctrl_vec; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rob_idx = _main_io_deq_bits_uop_rob_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldq_idx = _main_io_deq_bits_uop_ldq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stq_idx = _main_io_deq_bits_uop_stq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_rxq_idx = _main_io_deq_bits_uop_rxq_idx; // @[util.scala:104:23, :476:22] assign out_uop_out_1_pdst = _main_io_deq_bits_uop_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1 = _main_io_deq_bits_uop_prs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2 = _main_io_deq_bits_uop_prs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3 = _main_io_deq_bits_uop_prs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred = _main_io_deq_bits_uop_ppred; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs1_busy = _main_io_deq_bits_uop_prs1_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs2_busy = _main_io_deq_bits_uop_prs2_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_prs3_busy = _main_io_deq_bits_uop_prs3_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ppred_busy = _main_io_deq_bits_uop_ppred_busy; // @[util.scala:104:23, :476:22] assign out_uop_out_1_stale_pdst = _main_io_deq_bits_uop_stale_pdst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exception = _main_io_deq_bits_uop_exception; // @[util.scala:104:23, :476:22] assign out_uop_out_1_exc_cause = _main_io_deq_bits_uop_exc_cause; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_cmd = _main_io_deq_bits_uop_mem_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_size = _main_io_deq_bits_uop_mem_size; // @[util.scala:104:23, :476:22] assign out_uop_out_1_mem_signed = _main_io_deq_bits_uop_mem_signed; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_ldq = _main_io_deq_bits_uop_uses_ldq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_uses_stq = _main_io_deq_bits_uop_uses_stq; // @[util.scala:104:23, :476:22] assign out_uop_out_1_is_unique = _main_io_deq_bits_uop_is_unique; // @[util.scala:104:23, :476:22] assign out_uop_out_1_flush_on_commit = _main_io_deq_bits_uop_flush_on_commit; // @[util.scala:104:23, :476:22] assign out_uop_out_1_csr_cmd = _main_io_deq_bits_uop_csr_cmd; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst_is_rs1 = _main_io_deq_bits_uop_ldst_is_rs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_ldst = _main_io_deq_bits_uop_ldst; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1 = _main_io_deq_bits_uop_lrs1; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2 = _main_io_deq_bits_uop_lrs2; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs3 = _main_io_deq_bits_uop_lrs3; // @[util.scala:104:23, :476:22] assign out_uop_out_1_dst_rtype = _main_io_deq_bits_uop_dst_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs1_rtype = _main_io_deq_bits_uop_lrs1_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_lrs2_rtype = _main_io_deq_bits_uop_lrs2_rtype; // @[util.scala:104:23, :476:22] assign out_uop_out_1_frs3_en = _main_io_deq_bits_uop_frs3_en; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_dw = _main_io_deq_bits_uop_fcn_dw; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fcn_op = _main_io_deq_bits_uop_fcn_op; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_val = _main_io_deq_bits_uop_fp_val; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_rm = _main_io_deq_bits_uop_fp_rm; // @[util.scala:104:23, :476:22] assign out_uop_out_1_fp_typ = _main_io_deq_bits_uop_fp_typ; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_pf_if = _main_io_deq_bits_uop_xcpt_pf_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ae_if = _main_io_deq_bits_uop_xcpt_ae_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_xcpt_ma_if = _main_io_deq_bits_uop_xcpt_ma_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_debug_if = _main_io_deq_bits_uop_bp_debug_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_bp_xcpt_if = _main_io_deq_bits_uop_bp_xcpt_if; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_fsrc = _main_io_deq_bits_uop_debug_fsrc; // @[util.scala:104:23, :476:22] assign out_uop_out_1_debug_tsrc = _main_io_deq_bits_uop_debug_tsrc; // @[util.scala:104:23, :476:22] assign _out_uop_out_br_mask_T_3 = _main_io_deq_bits_uop_br_mask; // @[util.scala:93:25, :476:22] assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7] assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7] assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7] assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7] assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7] assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7] assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7] assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:458:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:458:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:458:7] assign io_deq_bits_way_en = io_deq_bits_way_en_0; // @[util.scala:458:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:458:7] assign io_empty = io_empty_0; // @[util.scala:458:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_19 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T

module MulAddRecFNToRaw_postMul_e8_s24_19( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OutputUnit_72 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[5], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[5], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[5], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} reg states : { `4` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `3` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `2` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.channel_status[3].occupied, states.`3`.occupied connect io.channel_status[3].flow, states.`3`.flow connect io.channel_status[4].occupied, states.`4`.occupied connect io.channel_status[4].flow, states.`4`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 4, 4) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`4`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`4`.occupied, UInt<1>(0h1), "") : assert connect states.`4`.occupied, UInt<1>(0h0) when io.allocs[4].alloc : connect states.`4`.occupied, UInt<1>(0h1) connect states.`4`.flow, io.allocs[4].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node _io_credit_available_3_T = neq(states.`3`.c, UInt<1>(0h0)) connect io.credit_available[3], _io_credit_available_3_T node _io_credit_available_4_T = neq(states.`4`.c, UInt<1>(0h0)) connect io.credit_available[4], _io_credit_available_4_T node free = bits(io.out.credit_return, 0, 0) node free_1 = bits(io.out.credit_return, 1, 1) node free_2 = bits(io.out.credit_return, 2, 2) node free_3 = bits(io.out.credit_return, 3, 3) node free_4 = bits(io.out.credit_return, 4, 4) node _states_4_c_T = add(states.`4`.c, free_4) node _states_4_c_T_1 = sub(_states_4_c_T, io.credit_alloc[4].alloc) node _states_4_c_T_2 = tail(_states_4_c_T_1, 1) connect states.`4`.c, _states_4_c_T_2 node _T_4 = asUInt(reset) when _T_4 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`3`.occupied, UInt<1>(0h0) connect states.`4`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<3>(0h4) connect states.`1`.c, UInt<3>(0h4) connect states.`2`.c, UInt<3>(0h4) connect states.`3`.c, UInt<3>(0h4) connect states.`4`.c, UInt<3>(0h4)

module OutputUnit_72( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [4:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [4:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [4:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [4:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19]

Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i5_o2_a32d128s7k4z4c : input clock : Clock input reset : Reset output auto : { flip anon_in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_1.e.bits.sink invalidate anonIn_1.e.valid invalidate anonIn_1.e.ready invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.c.bits.corrupt invalidate anonIn_1.c.bits.data invalidate anonIn_1.c.bits.address invalidate anonIn_1.c.bits.source invalidate anonIn_1.c.bits.size invalidate anonIn_1.c.bits.param invalidate anonIn_1.c.bits.opcode invalidate anonIn_1.c.valid invalidate anonIn_1.c.ready invalidate anonIn_1.b.bits.corrupt invalidate anonIn_1.b.bits.data invalidate anonIn_1.b.bits.mask invalidate anonIn_1.b.bits.address invalidate anonIn_1.b.bits.source invalidate anonIn_1.b.bits.size invalidate anonIn_1.b.bits.param invalidate anonIn_1.b.bits.opcode invalidate anonIn_1.b.valid invalidate anonIn_1.b.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_2.e.bits.sink invalidate anonIn_2.e.valid invalidate anonIn_2.e.ready invalidate anonIn_2.d.bits.corrupt invalidate anonIn_2.d.bits.data invalidate anonIn_2.d.bits.denied invalidate anonIn_2.d.bits.sink invalidate anonIn_2.d.bits.source invalidate anonIn_2.d.bits.size invalidate anonIn_2.d.bits.param invalidate anonIn_2.d.bits.opcode invalidate anonIn_2.d.valid invalidate anonIn_2.d.ready invalidate anonIn_2.c.bits.corrupt invalidate anonIn_2.c.bits.data invalidate anonIn_2.c.bits.address invalidate anonIn_2.c.bits.source invalidate anonIn_2.c.bits.size invalidate anonIn_2.c.bits.param invalidate anonIn_2.c.bits.opcode invalidate anonIn_2.c.valid invalidate anonIn_2.c.ready invalidate anonIn_2.b.bits.corrupt invalidate anonIn_2.b.bits.data invalidate anonIn_2.b.bits.mask invalidate anonIn_2.b.bits.address invalidate anonIn_2.b.bits.source invalidate anonIn_2.b.bits.size invalidate anonIn_2.b.bits.param invalidate anonIn_2.b.bits.opcode invalidate anonIn_2.b.valid invalidate anonIn_2.b.ready invalidate anonIn_2.a.bits.corrupt invalidate anonIn_2.a.bits.data invalidate anonIn_2.a.bits.mask invalidate anonIn_2.a.bits.address invalidate anonIn_2.a.bits.source invalidate anonIn_2.a.bits.size invalidate anonIn_2.a.bits.param invalidate anonIn_2.a.bits.opcode invalidate anonIn_2.a.valid invalidate anonIn_2.a.ready wire anonIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_3.e.bits.sink invalidate anonIn_3.e.valid invalidate anonIn_3.e.ready invalidate anonIn_3.d.bits.corrupt invalidate anonIn_3.d.bits.data invalidate anonIn_3.d.bits.denied invalidate anonIn_3.d.bits.sink invalidate anonIn_3.d.bits.source invalidate anonIn_3.d.bits.size invalidate anonIn_3.d.bits.param invalidate anonIn_3.d.bits.opcode invalidate anonIn_3.d.valid invalidate anonIn_3.d.ready invalidate anonIn_3.c.bits.corrupt invalidate anonIn_3.c.bits.data invalidate anonIn_3.c.bits.address invalidate anonIn_3.c.bits.source invalidate anonIn_3.c.bits.size invalidate anonIn_3.c.bits.param invalidate anonIn_3.c.bits.opcode invalidate anonIn_3.c.valid invalidate anonIn_3.c.ready invalidate anonIn_3.b.bits.corrupt invalidate anonIn_3.b.bits.data invalidate anonIn_3.b.bits.mask invalidate anonIn_3.b.bits.address invalidate anonIn_3.b.bits.source invalidate anonIn_3.b.bits.size invalidate anonIn_3.b.bits.param invalidate anonIn_3.b.bits.opcode invalidate anonIn_3.b.valid invalidate anonIn_3.b.ready invalidate anonIn_3.a.bits.corrupt invalidate anonIn_3.a.bits.data invalidate anonIn_3.a.bits.mask invalidate anonIn_3.a.bits.address invalidate anonIn_3.a.bits.source invalidate anonIn_3.a.bits.size invalidate anonIn_3.a.bits.param invalidate anonIn_3.a.bits.opcode invalidate anonIn_3.a.valid invalidate anonIn_3.a.ready wire anonIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate anonIn_4.e.bits.sink invalidate anonIn_4.e.valid invalidate anonIn_4.e.ready invalidate anonIn_4.d.bits.corrupt invalidate anonIn_4.d.bits.data invalidate anonIn_4.d.bits.denied invalidate anonIn_4.d.bits.sink invalidate anonIn_4.d.bits.source invalidate anonIn_4.d.bits.size invalidate anonIn_4.d.bits.param invalidate anonIn_4.d.bits.opcode invalidate anonIn_4.d.valid invalidate anonIn_4.d.ready invalidate anonIn_4.c.bits.corrupt invalidate anonIn_4.c.bits.data invalidate anonIn_4.c.bits.address invalidate anonIn_4.c.bits.source invalidate anonIn_4.c.bits.size invalidate anonIn_4.c.bits.param invalidate anonIn_4.c.bits.opcode invalidate anonIn_4.c.valid invalidate anonIn_4.c.ready invalidate anonIn_4.b.bits.corrupt invalidate anonIn_4.b.bits.data invalidate anonIn_4.b.bits.mask invalidate anonIn_4.b.bits.address invalidate anonIn_4.b.bits.source invalidate anonIn_4.b.bits.size invalidate anonIn_4.b.bits.param invalidate anonIn_4.b.bits.opcode invalidate anonIn_4.b.valid invalidate anonIn_4.b.ready invalidate anonIn_4.a.bits.corrupt invalidate anonIn_4.a.bits.data invalidate anonIn_4.a.bits.mask invalidate anonIn_4.a.bits.address invalidate anonIn_4.a.bits.source invalidate anonIn_4.a.bits.size invalidate anonIn_4.a.bits.param invalidate anonIn_4.a.bits.opcode invalidate anonIn_4.a.valid invalidate anonIn_4.a.ready inst monitor of TLMonitor connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_1 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink connect monitor_1.io.in.e.valid, anonIn_1.e.valid connect monitor_1.io.in.e.ready, anonIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, anonIn_1.c.valid connect monitor_1.io.in.c.ready, anonIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, anonIn_1.b.valid connect monitor_1.io.in.b.ready, anonIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready inst monitor_2 of TLMonitor_2 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.e.bits.sink, anonIn_2.e.bits.sink connect monitor_2.io.in.e.valid, anonIn_2.e.valid connect monitor_2.io.in.e.ready, anonIn_2.e.ready connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, anonIn_2.d.valid connect monitor_2.io.in.d.ready, anonIn_2.d.ready connect monitor_2.io.in.c.bits.corrupt, anonIn_2.c.bits.corrupt connect monitor_2.io.in.c.bits.data, anonIn_2.c.bits.data connect monitor_2.io.in.c.bits.address, anonIn_2.c.bits.address connect monitor_2.io.in.c.bits.source, anonIn_2.c.bits.source connect monitor_2.io.in.c.bits.size, anonIn_2.c.bits.size connect monitor_2.io.in.c.bits.param, anonIn_2.c.bits.param connect monitor_2.io.in.c.bits.opcode, anonIn_2.c.bits.opcode connect monitor_2.io.in.c.valid, anonIn_2.c.valid connect monitor_2.io.in.c.ready, anonIn_2.c.ready connect monitor_2.io.in.b.bits.corrupt, anonIn_2.b.bits.corrupt connect monitor_2.io.in.b.bits.data, anonIn_2.b.bits.data connect monitor_2.io.in.b.bits.mask, anonIn_2.b.bits.mask connect monitor_2.io.in.b.bits.address, anonIn_2.b.bits.address connect monitor_2.io.in.b.bits.source, anonIn_2.b.bits.source connect monitor_2.io.in.b.bits.size, anonIn_2.b.bits.size connect monitor_2.io.in.b.bits.param, anonIn_2.b.bits.param connect monitor_2.io.in.b.bits.opcode, anonIn_2.b.bits.opcode connect monitor_2.io.in.b.valid, anonIn_2.b.valid connect monitor_2.io.in.b.ready, anonIn_2.b.ready connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, anonIn_2.a.valid connect monitor_2.io.in.a.ready, anonIn_2.a.ready inst monitor_3 of TLMonitor_3 connect monitor_3.clock, clock connect monitor_3.reset, reset connect monitor_3.io.in.e.bits.sink, anonIn_3.e.bits.sink connect monitor_3.io.in.e.valid, anonIn_3.e.valid connect monitor_3.io.in.e.ready, anonIn_3.e.ready connect monitor_3.io.in.d.bits.corrupt, anonIn_3.d.bits.corrupt connect monitor_3.io.in.d.bits.data, anonIn_3.d.bits.data connect monitor_3.io.in.d.bits.denied, anonIn_3.d.bits.denied connect monitor_3.io.in.d.bits.sink, anonIn_3.d.bits.sink connect monitor_3.io.in.d.bits.source, anonIn_3.d.bits.source connect monitor_3.io.in.d.bits.size, anonIn_3.d.bits.size connect monitor_3.io.in.d.bits.param, anonIn_3.d.bits.param connect monitor_3.io.in.d.bits.opcode, anonIn_3.d.bits.opcode connect monitor_3.io.in.d.valid, anonIn_3.d.valid connect monitor_3.io.in.d.ready, anonIn_3.d.ready connect monitor_3.io.in.c.bits.corrupt, anonIn_3.c.bits.corrupt connect monitor_3.io.in.c.bits.data, anonIn_3.c.bits.data connect monitor_3.io.in.c.bits.address, anonIn_3.c.bits.address connect monitor_3.io.in.c.bits.source, anonIn_3.c.bits.source connect monitor_3.io.in.c.bits.size, anonIn_3.c.bits.size connect monitor_3.io.in.c.bits.param, anonIn_3.c.bits.param connect monitor_3.io.in.c.bits.opcode, anonIn_3.c.bits.opcode connect monitor_3.io.in.c.valid, anonIn_3.c.valid connect monitor_3.io.in.c.ready, anonIn_3.c.ready connect monitor_3.io.in.b.bits.corrupt, anonIn_3.b.bits.corrupt connect monitor_3.io.in.b.bits.data, anonIn_3.b.bits.data connect monitor_3.io.in.b.bits.mask, anonIn_3.b.bits.mask connect monitor_3.io.in.b.bits.address, anonIn_3.b.bits.address connect monitor_3.io.in.b.bits.source, anonIn_3.b.bits.source connect monitor_3.io.in.b.bits.size, anonIn_3.b.bits.size connect monitor_3.io.in.b.bits.param, anonIn_3.b.bits.param connect monitor_3.io.in.b.bits.opcode, anonIn_3.b.bits.opcode connect monitor_3.io.in.b.valid, anonIn_3.b.valid connect monitor_3.io.in.b.ready, anonIn_3.b.ready connect monitor_3.io.in.a.bits.corrupt, anonIn_3.a.bits.corrupt connect monitor_3.io.in.a.bits.data, anonIn_3.a.bits.data connect monitor_3.io.in.a.bits.mask, anonIn_3.a.bits.mask connect monitor_3.io.in.a.bits.address, anonIn_3.a.bits.address connect monitor_3.io.in.a.bits.source, anonIn_3.a.bits.source connect monitor_3.io.in.a.bits.size, anonIn_3.a.bits.size connect monitor_3.io.in.a.bits.param, anonIn_3.a.bits.param connect monitor_3.io.in.a.bits.opcode, anonIn_3.a.bits.opcode connect monitor_3.io.in.a.valid, anonIn_3.a.valid connect monitor_3.io.in.a.ready, anonIn_3.a.ready inst monitor_4 of TLMonitor_4 connect monitor_4.clock, clock connect monitor_4.reset, reset connect monitor_4.io.in.e.bits.sink, anonIn_4.e.bits.sink connect monitor_4.io.in.e.valid, anonIn_4.e.valid connect monitor_4.io.in.e.ready, anonIn_4.e.ready connect monitor_4.io.in.d.bits.corrupt, anonIn_4.d.bits.corrupt connect monitor_4.io.in.d.bits.data, anonIn_4.d.bits.data connect monitor_4.io.in.d.bits.denied, anonIn_4.d.bits.denied connect monitor_4.io.in.d.bits.sink, anonIn_4.d.bits.sink connect monitor_4.io.in.d.bits.source, anonIn_4.d.bits.source connect monitor_4.io.in.d.bits.size, anonIn_4.d.bits.size connect monitor_4.io.in.d.bits.param, anonIn_4.d.bits.param connect monitor_4.io.in.d.bits.opcode, anonIn_4.d.bits.opcode connect monitor_4.io.in.d.valid, anonIn_4.d.valid connect monitor_4.io.in.d.ready, anonIn_4.d.ready connect monitor_4.io.in.c.bits.corrupt, anonIn_4.c.bits.corrupt connect monitor_4.io.in.c.bits.data, anonIn_4.c.bits.data connect monitor_4.io.in.c.bits.address, anonIn_4.c.bits.address connect monitor_4.io.in.c.bits.source, anonIn_4.c.bits.source connect monitor_4.io.in.c.bits.size, anonIn_4.c.bits.size connect monitor_4.io.in.c.bits.param, anonIn_4.c.bits.param connect monitor_4.io.in.c.bits.opcode, anonIn_4.c.bits.opcode connect monitor_4.io.in.c.valid, anonIn_4.c.valid connect monitor_4.io.in.c.ready, anonIn_4.c.ready connect monitor_4.io.in.b.bits.corrupt, anonIn_4.b.bits.corrupt connect monitor_4.io.in.b.bits.data, anonIn_4.b.bits.data connect monitor_4.io.in.b.bits.mask, anonIn_4.b.bits.mask connect monitor_4.io.in.b.bits.address, anonIn_4.b.bits.address connect monitor_4.io.in.b.bits.source, anonIn_4.b.bits.source connect monitor_4.io.in.b.bits.size, anonIn_4.b.bits.size connect monitor_4.io.in.b.bits.param, anonIn_4.b.bits.param connect monitor_4.io.in.b.bits.opcode, anonIn_4.b.bits.opcode connect monitor_4.io.in.b.valid, anonIn_4.b.valid connect monitor_4.io.in.b.ready, anonIn_4.b.ready connect monitor_4.io.in.a.bits.corrupt, anonIn_4.a.bits.corrupt connect monitor_4.io.in.a.bits.data, anonIn_4.a.bits.data connect monitor_4.io.in.a.bits.mask, anonIn_4.a.bits.mask connect monitor_4.io.in.a.bits.address, anonIn_4.a.bits.address connect monitor_4.io.in.a.bits.source, anonIn_4.a.bits.source connect monitor_4.io.in.a.bits.size, anonIn_4.a.bits.size connect monitor_4.io.in.a.bits.param, anonIn_4.a.bits.param connect monitor_4.io.in.a.bits.opcode, anonIn_4.a.bits.opcode connect monitor_4.io.in.a.valid, anonIn_4.a.valid connect monitor_4.io.in.a.ready, anonIn_4.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}} invalidate x1_anonOut.e.bits.sink invalidate x1_anonOut.e.valid invalidate x1_anonOut.e.ready invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.c.bits.corrupt invalidate x1_anonOut.c.bits.data invalidate x1_anonOut.c.bits.address invalidate x1_anonOut.c.bits.source invalidate x1_anonOut.c.bits.size invalidate x1_anonOut.c.bits.param invalidate x1_anonOut.c.bits.opcode invalidate x1_anonOut.c.valid invalidate x1_anonOut.c.ready invalidate x1_anonOut.b.bits.corrupt invalidate x1_anonOut.b.bits.data invalidate x1_anonOut.b.bits.mask invalidate x1_anonOut.b.bits.address invalidate x1_anonOut.b.bits.source invalidate x1_anonOut.b.bits.size invalidate x1_anonOut.b.bits.param invalidate x1_anonOut.b.bits.opcode invalidate x1_anonOut.b.valid invalidate x1_anonOut.b.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonIn_2, auto.anon_in_2 connect anonIn_3, auto.anon_in_3 connect anonIn_4, auto.anon_in_4 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[5] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode invalidate in[0].b.valid invalidate in[0].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[0].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.mask, UInt<16>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[0].c.bits.corrupt invalidate in[0].c.bits.data invalidate in[0].c.bits.address invalidate in[0].c.bits.source invalidate in[0].c.bits.size invalidate in[0].c.bits.param invalidate in[0].c.bits.opcode invalidate in[0].c.valid invalidate in[0].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[0].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T invalidate in[0].e.bits.sink invalidate in[0].e.valid invalidate in[0].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_8.bits.sink, UInt<4>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[0].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits.sink, UInt<4>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<7>(0h44)) connect in[1].a.bits.source, _in_1_a_bits_source_T connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt connect anonIn_1.b.bits.data, in[1].b.bits.data connect anonIn_1.b.bits.mask, in[1].b.bits.mask connect anonIn_1.b.bits.address, in[1].b.bits.address connect anonIn_1.b.bits.source, in[1].b.bits.source connect anonIn_1.b.bits.size, in[1].b.bits.size connect anonIn_1.b.bits.param, in[1].b.bits.param connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode connect anonIn_1.b.valid, in[1].b.valid connect in[1].b.ready, anonIn_1.b.ready node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0) connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt connect in[1].c.bits.data, anonIn_1.c.bits.data connect in[1].c.bits.address, anonIn_1.c.bits.address connect in[1].c.bits.source, anonIn_1.c.bits.source connect in[1].c.bits.size, anonIn_1.c.bits.size connect in[1].c.bits.param, anonIn_1.c.bits.param connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode connect in[1].c.valid, anonIn_1.c.valid connect anonIn_1.c.ready, in[1].c.ready node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<7>(0h44)) connect in[1].c.bits.source, _in_1_c_bits_source_T connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 connect in[1].e.bits.sink, anonIn_1.e.bits.sink connect in[1].e.valid, anonIn_1.e.valid connect anonIn_1.e.ready, in[1].e.ready connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt connect in[2].a.bits.data, anonIn_2.a.bits.data connect in[2].a.bits.mask, anonIn_2.a.bits.mask connect in[2].a.bits.address, anonIn_2.a.bits.address connect in[2].a.bits.source, anonIn_2.a.bits.source connect in[2].a.bits.size, anonIn_2.a.bits.size connect in[2].a.bits.param, anonIn_2.a.bits.param connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode connect in[2].a.valid, anonIn_2.a.valid connect anonIn_2.a.ready, in[2].a.ready node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<7>(0h40)) connect in[2].a.bits.source, _in_2_a_bits_source_T connect anonIn_2.b.bits.corrupt, in[2].b.bits.corrupt connect anonIn_2.b.bits.data, in[2].b.bits.data connect anonIn_2.b.bits.mask, in[2].b.bits.mask connect anonIn_2.b.bits.address, in[2].b.bits.address connect anonIn_2.b.bits.source, in[2].b.bits.source connect anonIn_2.b.bits.size, in[2].b.bits.size connect anonIn_2.b.bits.param, in[2].b.bits.param connect anonIn_2.b.bits.opcode, in[2].b.bits.opcode connect anonIn_2.b.valid, in[2].b.valid connect in[2].b.ready, anonIn_2.b.ready node _anonIn_b_bits_source_T_1 = bits(in[2].b.bits.source, 1, 0) connect anonIn_2.b.bits.source, _anonIn_b_bits_source_T_1 connect in[2].c.bits.corrupt, anonIn_2.c.bits.corrupt connect in[2].c.bits.data, anonIn_2.c.bits.data connect in[2].c.bits.address, anonIn_2.c.bits.address connect in[2].c.bits.source, anonIn_2.c.bits.source connect in[2].c.bits.size, anonIn_2.c.bits.size connect in[2].c.bits.param, anonIn_2.c.bits.param connect in[2].c.bits.opcode, anonIn_2.c.bits.opcode connect in[2].c.valid, anonIn_2.c.valid connect anonIn_2.c.ready, in[2].c.ready node _in_2_c_bits_source_T = or(anonIn_2.c.bits.source, UInt<7>(0h40)) connect in[2].c.bits.source, _in_2_c_bits_source_T connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt connect anonIn_2.d.bits.data, in[2].d.bits.data connect anonIn_2.d.bits.denied, in[2].d.bits.denied connect anonIn_2.d.bits.sink, in[2].d.bits.sink connect anonIn_2.d.bits.source, in[2].d.bits.source connect anonIn_2.d.bits.size, in[2].d.bits.size connect anonIn_2.d.bits.param, in[2].d.bits.param connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode connect anonIn_2.d.valid, in[2].d.valid connect in[2].d.ready, anonIn_2.d.ready node _anonIn_d_bits_source_T_2 = bits(in[2].d.bits.source, 1, 0) connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_2 connect in[2].e.bits.sink, anonIn_2.e.bits.sink connect in[2].e.valid, anonIn_2.e.valid connect anonIn_2.e.ready, in[2].e.ready connect in[3].a.bits.corrupt, anonIn_3.a.bits.corrupt connect in[3].a.bits.data, anonIn_3.a.bits.data connect in[3].a.bits.mask, anonIn_3.a.bits.mask connect in[3].a.bits.address, anonIn_3.a.bits.address connect in[3].a.bits.source, anonIn_3.a.bits.source connect in[3].a.bits.size, anonIn_3.a.bits.size connect in[3].a.bits.param, anonIn_3.a.bits.param connect in[3].a.bits.opcode, anonIn_3.a.bits.opcode connect in[3].a.valid, anonIn_3.a.valid connect anonIn_3.a.ready, in[3].a.ready node _in_3_a_bits_source_T = or(anonIn_3.a.bits.source, UInt<6>(0h30)) connect in[3].a.bits.source, _in_3_a_bits_source_T connect anonIn_3.b.bits.corrupt, in[3].b.bits.corrupt connect anonIn_3.b.bits.data, in[3].b.bits.data connect anonIn_3.b.bits.mask, in[3].b.bits.mask connect anonIn_3.b.bits.address, in[3].b.bits.address connect anonIn_3.b.bits.source, in[3].b.bits.source connect anonIn_3.b.bits.size, in[3].b.bits.size connect anonIn_3.b.bits.param, in[3].b.bits.param connect anonIn_3.b.bits.opcode, in[3].b.bits.opcode connect anonIn_3.b.valid, in[3].b.valid connect in[3].b.ready, anonIn_3.b.ready node _anonIn_b_bits_source_T_2 = bits(in[3].b.bits.source, 3, 0) connect anonIn_3.b.bits.source, _anonIn_b_bits_source_T_2 connect in[3].c.bits.corrupt, anonIn_3.c.bits.corrupt connect in[3].c.bits.data, anonIn_3.c.bits.data connect in[3].c.bits.address, anonIn_3.c.bits.address connect in[3].c.bits.source, anonIn_3.c.bits.source connect in[3].c.bits.size, anonIn_3.c.bits.size connect in[3].c.bits.param, anonIn_3.c.bits.param connect in[3].c.bits.opcode, anonIn_3.c.bits.opcode connect in[3].c.valid, anonIn_3.c.valid connect anonIn_3.c.ready, in[3].c.ready node _in_3_c_bits_source_T = or(anonIn_3.c.bits.source, UInt<6>(0h30)) connect in[3].c.bits.source, _in_3_c_bits_source_T connect anonIn_3.d.bits.corrupt, in[3].d.bits.corrupt connect anonIn_3.d.bits.data, in[3].d.bits.data connect anonIn_3.d.bits.denied, in[3].d.bits.denied connect anonIn_3.d.bits.sink, in[3].d.bits.sink connect anonIn_3.d.bits.source, in[3].d.bits.source connect anonIn_3.d.bits.size, in[3].d.bits.size connect anonIn_3.d.bits.param, in[3].d.bits.param connect anonIn_3.d.bits.opcode, in[3].d.bits.opcode connect anonIn_3.d.valid, in[3].d.valid connect in[3].d.ready, anonIn_3.d.ready node _anonIn_d_bits_source_T_3 = bits(in[3].d.bits.source, 3, 0) connect anonIn_3.d.bits.source, _anonIn_d_bits_source_T_3 connect in[3].e.bits.sink, anonIn_3.e.bits.sink connect in[3].e.valid, anonIn_3.e.valid connect anonIn_3.e.ready, in[3].e.ready connect in[4].a.bits.corrupt, anonIn_4.a.bits.corrupt connect in[4].a.bits.data, anonIn_4.a.bits.data connect in[4].a.bits.mask, anonIn_4.a.bits.mask connect in[4].a.bits.address, anonIn_4.a.bits.address connect in[4].a.bits.source, anonIn_4.a.bits.source connect in[4].a.bits.size, anonIn_4.a.bits.size connect in[4].a.bits.param, anonIn_4.a.bits.param connect in[4].a.bits.opcode, anonIn_4.a.bits.opcode connect in[4].a.valid, anonIn_4.a.valid connect anonIn_4.a.ready, in[4].a.ready node _in_4_a_bits_source_T = or(anonIn_4.a.bits.source, UInt<6>(0h20)) connect in[4].a.bits.source, _in_4_a_bits_source_T connect anonIn_4.b.bits.corrupt, in[4].b.bits.corrupt connect anonIn_4.b.bits.data, in[4].b.bits.data connect anonIn_4.b.bits.mask, in[4].b.bits.mask connect anonIn_4.b.bits.address, in[4].b.bits.address connect anonIn_4.b.bits.source, in[4].b.bits.source connect anonIn_4.b.bits.size, in[4].b.bits.size connect anonIn_4.b.bits.param, in[4].b.bits.param connect anonIn_4.b.bits.opcode, in[4].b.bits.opcode connect anonIn_4.b.valid, in[4].b.valid connect in[4].b.ready, anonIn_4.b.ready node _anonIn_b_bits_source_T_3 = bits(in[4].b.bits.source, 3, 0) connect anonIn_4.b.bits.source, _anonIn_b_bits_source_T_3 connect in[4].c.bits.corrupt, anonIn_4.c.bits.corrupt connect in[4].c.bits.data, anonIn_4.c.bits.data connect in[4].c.bits.address, anonIn_4.c.bits.address connect in[4].c.bits.source, anonIn_4.c.bits.source connect in[4].c.bits.size, anonIn_4.c.bits.size connect in[4].c.bits.param, anonIn_4.c.bits.param connect in[4].c.bits.opcode, anonIn_4.c.bits.opcode connect in[4].c.valid, anonIn_4.c.valid connect anonIn_4.c.ready, in[4].c.ready node _in_4_c_bits_source_T = or(anonIn_4.c.bits.source, UInt<6>(0h20)) connect in[4].c.bits.source, _in_4_c_bits_source_T connect anonIn_4.d.bits.corrupt, in[4].d.bits.corrupt connect anonIn_4.d.bits.data, in[4].d.bits.data connect anonIn_4.d.bits.denied, in[4].d.bits.denied connect anonIn_4.d.bits.sink, in[4].d.bits.sink connect anonIn_4.d.bits.source, in[4].d.bits.source connect anonIn_4.d.bits.size, in[4].d.bits.size connect anonIn_4.d.bits.param, in[4].d.bits.param connect anonIn_4.d.bits.opcode, in[4].d.bits.opcode connect anonIn_4.d.valid, in[4].d.valid connect in[4].d.ready, anonIn_4.d.ready node _anonIn_d_bits_source_T_4 = bits(in[4].d.bits.source, 3, 0) connect anonIn_4.d.bits.source, _anonIn_d_bits_source_T_4 connect in[4].e.bits.sink, anonIn_4.e.bits.sink connect in[4].e.valid, anonIn_4.e.valid connect anonIn_4.e.ready, in[4].e.ready wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}[2] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready invalidate out[0].b.bits.corrupt invalidate out[0].b.bits.data invalidate out[0].b.bits.mask invalidate out[0].b.bits.address invalidate out[0].b.bits.source invalidate out[0].b.bits.size invalidate out[0].b.bits.param invalidate out[0].b.bits.opcode invalidate out[0].b.valid invalidate out[0].b.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.mask, UInt<16>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<2>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready invalidate _WIRE_13.bits.corrupt invalidate _WIRE_13.bits.data invalidate _WIRE_13.bits.mask invalidate _WIRE_13.bits.address invalidate _WIRE_13.bits.source invalidate _WIRE_13.bits.size invalidate _WIRE_13.bits.param invalidate _WIRE_13.bits.opcode invalidate _WIRE_13.valid invalidate _WIRE_13.ready connect out[0].b.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.mask, UInt<16>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<2>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].c.valid invalidate out[0].c.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.corrupt invalidate _WIRE_17.bits.data invalidate _WIRE_17.bits.address invalidate _WIRE_17.bits.source invalidate _WIRE_17.bits.size invalidate _WIRE_17.bits.param invalidate _WIRE_17.bits.opcode invalidate _WIRE_17.valid invalidate _WIRE_17.ready connect out[0].c.ready, UInt<1>(0h1) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T invalidate out[0].e.bits.sink invalidate out[0].e.valid invalidate out[0].e.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_20.bits.sink, UInt<1>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready invalidate _WIRE_21.bits.sink invalidate _WIRE_21.valid invalidate _WIRE_21.ready connect out[0].e.ready, UInt<1>(0h1) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_22.bits.sink, UInt<1>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.valid, UInt<1>(0h0) connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt connect out[1].b.bits.data, x1_anonOut.b.bits.data connect out[1].b.bits.mask, x1_anonOut.b.bits.mask connect out[1].b.bits.address, x1_anonOut.b.bits.address connect out[1].b.bits.source, x1_anonOut.b.bits.source connect out[1].b.bits.size, x1_anonOut.b.bits.size connect out[1].b.bits.param, x1_anonOut.b.bits.param connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode connect out[1].b.valid, x1_anonOut.b.valid connect x1_anonOut.b.ready, out[1].b.ready connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt connect x1_anonOut.c.bits.data, out[1].c.bits.data connect x1_anonOut.c.bits.address, out[1].c.bits.address connect x1_anonOut.c.bits.source, out[1].c.bits.source connect x1_anonOut.c.bits.size, out[1].c.bits.size connect x1_anonOut.c.bits.param, out[1].c.bits.param connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode connect x1_anonOut.c.valid, out[1].c.valid connect out[1].c.ready, x1_anonOut.c.ready connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T connect x1_anonOut.e.bits.sink, out[1].e.bits.sink connect x1_anonOut.e.valid, out[1].e.valid connect out[1].e.ready, x1_anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 3, 0) connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = or(_requestAIO_T_4, _requestAIO_T_9) node _requestAIO_T_16 = or(_requestAIO_T_15, _requestAIO_T_14) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_16) node _requestAIO_T_17 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_18 = cvt(_requestAIO_T_17) node _requestAIO_T_19 = and(_requestAIO_T_18, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_20 = asSInt(_requestAIO_T_19) node _requestAIO_T_21 = eq(_requestAIO_T_20, asSInt(UInt<1>(0h0))) node _requestAIO_T_22 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_23 = cvt(_requestAIO_T_22) node _requestAIO_T_24 = and(_requestAIO_T_23, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_25 = asSInt(_requestAIO_T_24) node _requestAIO_T_26 = eq(_requestAIO_T_25, asSInt(UInt<1>(0h0))) node _requestAIO_T_27 = or(_requestAIO_T_21, _requestAIO_T_26) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_27) node _requestAIO_T_28 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_29 = cvt(_requestAIO_T_28) node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_31 = asSInt(_requestAIO_T_30) node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0))) node _requestAIO_T_33 = xor(in[1].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_34 = cvt(_requestAIO_T_33) node _requestAIO_T_35 = and(_requestAIO_T_34, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_36 = asSInt(_requestAIO_T_35) node _requestAIO_T_37 = eq(_requestAIO_T_36, asSInt(UInt<1>(0h0))) node _requestAIO_T_38 = xor(in[1].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_39 = cvt(_requestAIO_T_38) node _requestAIO_T_40 = and(_requestAIO_T_39, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_41 = asSInt(_requestAIO_T_40) node _requestAIO_T_42 = eq(_requestAIO_T_41, asSInt(UInt<1>(0h0))) node _requestAIO_T_43 = or(_requestAIO_T_32, _requestAIO_T_37) node _requestAIO_T_44 = or(_requestAIO_T_43, _requestAIO_T_42) node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_44) node _requestAIO_T_45 = xor(in[1].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_46 = cvt(_requestAIO_T_45) node _requestAIO_T_47 = and(_requestAIO_T_46, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_48 = asSInt(_requestAIO_T_47) node _requestAIO_T_49 = eq(_requestAIO_T_48, asSInt(UInt<1>(0h0))) node _requestAIO_T_50 = xor(in[1].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_51 = cvt(_requestAIO_T_50) node _requestAIO_T_52 = and(_requestAIO_T_51, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_53 = asSInt(_requestAIO_T_52) node _requestAIO_T_54 = eq(_requestAIO_T_53, asSInt(UInt<1>(0h0))) node _requestAIO_T_55 = or(_requestAIO_T_49, _requestAIO_T_54) node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_55) node _requestAIO_T_56 = xor(in[2].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_57 = cvt(_requestAIO_T_56) node _requestAIO_T_58 = and(_requestAIO_T_57, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_59 = asSInt(_requestAIO_T_58) node _requestAIO_T_60 = eq(_requestAIO_T_59, asSInt(UInt<1>(0h0))) node _requestAIO_T_61 = xor(in[2].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_62 = cvt(_requestAIO_T_61) node _requestAIO_T_63 = and(_requestAIO_T_62, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_64 = asSInt(_requestAIO_T_63) node _requestAIO_T_65 = eq(_requestAIO_T_64, asSInt(UInt<1>(0h0))) node _requestAIO_T_66 = xor(in[2].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_67 = cvt(_requestAIO_T_66) node _requestAIO_T_68 = and(_requestAIO_T_67, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_69 = asSInt(_requestAIO_T_68) node _requestAIO_T_70 = eq(_requestAIO_T_69, asSInt(UInt<1>(0h0))) node _requestAIO_T_71 = or(_requestAIO_T_60, _requestAIO_T_65) node _requestAIO_T_72 = or(_requestAIO_T_71, _requestAIO_T_70) node requestAIO_2_0 = or(UInt<1>(0h0), _requestAIO_T_72) node _requestAIO_T_73 = xor(in[2].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_74 = cvt(_requestAIO_T_73) node _requestAIO_T_75 = and(_requestAIO_T_74, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_76 = asSInt(_requestAIO_T_75) node _requestAIO_T_77 = eq(_requestAIO_T_76, asSInt(UInt<1>(0h0))) node _requestAIO_T_78 = xor(in[2].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_79 = cvt(_requestAIO_T_78) node _requestAIO_T_80 = and(_requestAIO_T_79, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_81 = asSInt(_requestAIO_T_80) node _requestAIO_T_82 = eq(_requestAIO_T_81, asSInt(UInt<1>(0h0))) node _requestAIO_T_83 = or(_requestAIO_T_77, _requestAIO_T_82) node requestAIO_2_1 = or(UInt<1>(0h0), _requestAIO_T_83) node _requestAIO_T_84 = xor(in[3].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_85 = cvt(_requestAIO_T_84) node _requestAIO_T_86 = and(_requestAIO_T_85, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_87 = asSInt(_requestAIO_T_86) node _requestAIO_T_88 = eq(_requestAIO_T_87, asSInt(UInt<1>(0h0))) node _requestAIO_T_89 = xor(in[3].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_90 = cvt(_requestAIO_T_89) node _requestAIO_T_91 = and(_requestAIO_T_90, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_92 = asSInt(_requestAIO_T_91) node _requestAIO_T_93 = eq(_requestAIO_T_92, asSInt(UInt<1>(0h0))) node _requestAIO_T_94 = xor(in[3].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_95 = cvt(_requestAIO_T_94) node _requestAIO_T_96 = and(_requestAIO_T_95, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_97 = asSInt(_requestAIO_T_96) node _requestAIO_T_98 = eq(_requestAIO_T_97, asSInt(UInt<1>(0h0))) node _requestAIO_T_99 = or(_requestAIO_T_88, _requestAIO_T_93) node _requestAIO_T_100 = or(_requestAIO_T_99, _requestAIO_T_98) node requestAIO_3_0 = or(UInt<1>(0h0), _requestAIO_T_100) node _requestAIO_T_101 = xor(in[3].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_102 = cvt(_requestAIO_T_101) node _requestAIO_T_103 = and(_requestAIO_T_102, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_104 = asSInt(_requestAIO_T_103) node _requestAIO_T_105 = eq(_requestAIO_T_104, asSInt(UInt<1>(0h0))) node _requestAIO_T_106 = xor(in[3].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_107 = cvt(_requestAIO_T_106) node _requestAIO_T_108 = and(_requestAIO_T_107, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_109 = asSInt(_requestAIO_T_108) node _requestAIO_T_110 = eq(_requestAIO_T_109, asSInt(UInt<1>(0h0))) node _requestAIO_T_111 = or(_requestAIO_T_105, _requestAIO_T_110) node requestAIO_3_1 = or(UInt<1>(0h0), _requestAIO_T_111) node _requestAIO_T_112 = xor(in[4].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_113 = cvt(_requestAIO_T_112) node _requestAIO_T_114 = and(_requestAIO_T_113, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_115 = asSInt(_requestAIO_T_114) node _requestAIO_T_116 = eq(_requestAIO_T_115, asSInt(UInt<1>(0h0))) node _requestAIO_T_117 = xor(in[4].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_118 = cvt(_requestAIO_T_117) node _requestAIO_T_119 = and(_requestAIO_T_118, asSInt(UInt<33>(0h8c011000))) node _requestAIO_T_120 = asSInt(_requestAIO_T_119) node _requestAIO_T_121 = eq(_requestAIO_T_120, asSInt(UInt<1>(0h0))) node _requestAIO_T_122 = xor(in[4].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_123 = cvt(_requestAIO_T_122) node _requestAIO_T_124 = and(_requestAIO_T_123, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_125 = asSInt(_requestAIO_T_124) node _requestAIO_T_126 = eq(_requestAIO_T_125, asSInt(UInt<1>(0h0))) node _requestAIO_T_127 = or(_requestAIO_T_116, _requestAIO_T_121) node _requestAIO_T_128 = or(_requestAIO_T_127, _requestAIO_T_126) node requestAIO_4_0 = or(UInt<1>(0h0), _requestAIO_T_128) node _requestAIO_T_129 = xor(in[4].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_130 = cvt(_requestAIO_T_129) node _requestAIO_T_131 = and(_requestAIO_T_130, asSInt(UInt<33>(0h8c010000))) node _requestAIO_T_132 = asSInt(_requestAIO_T_131) node _requestAIO_T_133 = eq(_requestAIO_T_132, asSInt(UInt<1>(0h0))) node _requestAIO_T_134 = xor(in[4].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_135 = cvt(_requestAIO_T_134) node _requestAIO_T_136 = and(_requestAIO_T_135, asSInt(UInt<33>(0h80000000))) node _requestAIO_T_137 = asSInt(_requestAIO_T_136) node _requestAIO_T_138 = eq(_requestAIO_T_137, asSInt(UInt<1>(0h0))) node _requestAIO_T_139 = or(_requestAIO_T_133, _requestAIO_T_138) node requestAIO_4_1 = or(UInt<1>(0h0), _requestAIO_T_139) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19) node _requestCIO_T_20 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_21 = cvt(_requestCIO_T_20) node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0))) node _requestCIO_T_23 = asSInt(_requestCIO_T_22) node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0))) node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_24) node _requestCIO_T_25 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_26 = cvt(_requestCIO_T_25) node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0))) node _requestCIO_T_28 = asSInt(_requestCIO_T_27) node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0))) node requestCIO_2_1 = or(UInt<1>(0h1), _requestCIO_T_29) node _requestCIO_T_30 = xor(in[3].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_31 = cvt(_requestCIO_T_30) node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0))) node _requestCIO_T_33 = asSInt(_requestCIO_T_32) node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0))) node requestCIO_3_0 = or(UInt<1>(0h1), _requestCIO_T_34) node _requestCIO_T_35 = xor(in[3].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_36 = cvt(_requestCIO_T_35) node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0))) node _requestCIO_T_38 = asSInt(_requestCIO_T_37) node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0))) node requestCIO_3_1 = or(UInt<1>(0h1), _requestCIO_T_39) node _requestCIO_T_40 = xor(in[4].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_41 = cvt(_requestCIO_T_40) node _requestCIO_T_42 = and(_requestCIO_T_41, asSInt(UInt<1>(0h0))) node _requestCIO_T_43 = asSInt(_requestCIO_T_42) node _requestCIO_T_44 = eq(_requestCIO_T_43, asSInt(UInt<1>(0h0))) node requestCIO_4_0 = or(UInt<1>(0h1), _requestCIO_T_44) node _requestCIO_T_45 = xor(in[4].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_46 = cvt(_requestCIO_T_45) node _requestCIO_T_47 = and(_requestCIO_T_46, asSInt(UInt<1>(0h0))) node _requestCIO_T_48 = asSInt(_requestCIO_T_47) node _requestCIO_T_49 = eq(_requestCIO_T_48, asSInt(UInt<1>(0h0))) node requestCIO_4_1 = or(UInt<1>(0h1), _requestCIO_T_49) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(out[0].b.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0) node _requestBOI_T_5 = shr(out[0].b.bits.source, 2) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<5>(0h11)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3)) node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestBOI_uncommonBits_T_2 = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 1, 0) node _requestBOI_T_10 = shr(out[0].b.bits.source, 2) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<5>(0h10)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<2>(0h3)) node requestBOI_0_2 = and(_requestBOI_T_13, _requestBOI_T_14) node _requestBOI_uncommonBits_T_3 = or(out[0].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 3, 0) node _requestBOI_T_15 = shr(out[0].b.bits.source, 4) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<2>(0h3)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<4>(0hf)) node requestBOI_0_3 = and(_requestBOI_T_18, _requestBOI_T_19) node _requestBOI_uncommonBits_T_4 = or(out[0].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 3, 0) node _requestBOI_T_20 = shr(out[0].b.bits.source, 4) node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<2>(0h2)) node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4) node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22) node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<4>(0hf)) node requestBOI_0_4 = and(_requestBOI_T_23, _requestBOI_T_24) node _requestBOI_uncommonBits_T_5 = or(out[1].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 4, 0) node _requestBOI_T_25 = shr(out[1].b.bits.source, 5) node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0)) node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5) node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27) node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_28, _requestBOI_T_29) node _requestBOI_uncommonBits_T_6 = or(out[1].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 1, 0) node _requestBOI_T_30 = shr(out[1].b.bits.source, 2) node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<5>(0h11)) node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6) node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32) node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<2>(0h3)) node requestBOI_1_1 = and(_requestBOI_T_33, _requestBOI_T_34) node _requestBOI_uncommonBits_T_7 = or(out[1].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 1, 0) node _requestBOI_T_35 = shr(out[1].b.bits.source, 2) node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<5>(0h10)) node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7) node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37) node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<2>(0h3)) node requestBOI_1_2 = and(_requestBOI_T_38, _requestBOI_T_39) node _requestBOI_uncommonBits_T_8 = or(out[1].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_8 = bits(_requestBOI_uncommonBits_T_8, 3, 0) node _requestBOI_T_40 = shr(out[1].b.bits.source, 4) node _requestBOI_T_41 = eq(_requestBOI_T_40, UInt<2>(0h3)) node _requestBOI_T_42 = leq(UInt<1>(0h0), requestBOI_uncommonBits_8) node _requestBOI_T_43 = and(_requestBOI_T_41, _requestBOI_T_42) node _requestBOI_T_44 = leq(requestBOI_uncommonBits_8, UInt<4>(0hf)) node requestBOI_1_3 = and(_requestBOI_T_43, _requestBOI_T_44) node _requestBOI_uncommonBits_T_9 = or(out[1].b.bits.source, UInt<4>(0h0)) node requestBOI_uncommonBits_9 = bits(_requestBOI_uncommonBits_T_9, 3, 0) node _requestBOI_T_45 = shr(out[1].b.bits.source, 4) node _requestBOI_T_46 = eq(_requestBOI_T_45, UInt<2>(0h2)) node _requestBOI_T_47 = leq(UInt<1>(0h0), requestBOI_uncommonBits_9) node _requestBOI_T_48 = and(_requestBOI_T_46, _requestBOI_T_47) node _requestBOI_T_49 = leq(requestBOI_uncommonBits_9, UInt<4>(0hf)) node requestBOI_1_4 = and(_requestBOI_T_48, _requestBOI_T_49) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0) node _requestDOI_T_5 = shr(out[0].d.bits.source, 2) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<5>(0h11)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3)) node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 1, 0) node _requestDOI_T_10 = shr(out[0].d.bits.source, 2) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<5>(0h10)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<2>(0h3)) node requestDOI_0_2 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 3, 0) node _requestDOI_T_15 = shr(out[0].d.bits.source, 4) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<2>(0h3)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<4>(0hf)) node requestDOI_0_3 = and(_requestDOI_T_18, _requestDOI_T_19) node _requestDOI_uncommonBits_T_4 = or(out[0].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 3, 0) node _requestDOI_T_20 = shr(out[0].d.bits.source, 4) node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<2>(0h2)) node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4) node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22) node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<4>(0hf)) node requestDOI_0_4 = and(_requestDOI_T_23, _requestDOI_T_24) node _requestDOI_uncommonBits_T_5 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 4, 0) node _requestDOI_T_25 = shr(out[1].d.bits.source, 5) node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0)) node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5) node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27) node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_28, _requestDOI_T_29) node _requestDOI_uncommonBits_T_6 = or(out[1].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 1, 0) node _requestDOI_T_30 = shr(out[1].d.bits.source, 2) node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<5>(0h11)) node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6) node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32) node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<2>(0h3)) node requestDOI_1_1 = and(_requestDOI_T_33, _requestDOI_T_34) node _requestDOI_uncommonBits_T_7 = or(out[1].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 1, 0) node _requestDOI_T_35 = shr(out[1].d.bits.source, 2) node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<5>(0h10)) node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7) node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37) node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<2>(0h3)) node requestDOI_1_2 = and(_requestDOI_T_38, _requestDOI_T_39) node _requestDOI_uncommonBits_T_8 = or(out[1].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_8 = bits(_requestDOI_uncommonBits_T_8, 3, 0) node _requestDOI_T_40 = shr(out[1].d.bits.source, 4) node _requestDOI_T_41 = eq(_requestDOI_T_40, UInt<2>(0h3)) node _requestDOI_T_42 = leq(UInt<1>(0h0), requestDOI_uncommonBits_8) node _requestDOI_T_43 = and(_requestDOI_T_41, _requestDOI_T_42) node _requestDOI_T_44 = leq(requestDOI_uncommonBits_8, UInt<4>(0hf)) node requestDOI_1_3 = and(_requestDOI_T_43, _requestDOI_T_44) node _requestDOI_uncommonBits_T_9 = or(out[1].d.bits.source, UInt<4>(0h0)) node requestDOI_uncommonBits_9 = bits(_requestDOI_uncommonBits_T_9, 3, 0) node _requestDOI_T_45 = shr(out[1].d.bits.source, 4) node _requestDOI_T_46 = eq(_requestDOI_T_45, UInt<2>(0h2)) node _requestDOI_T_47 = leq(UInt<1>(0h0), requestDOI_uncommonBits_9) node _requestDOI_T_48 = and(_requestDOI_T_46, _requestDOI_T_47) node _requestDOI_T_49 = leq(requestDOI_uncommonBits_9, UInt<4>(0hf)) node requestDOI_1_4 = and(_requestDOI_T_48, _requestDOI_T_49) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 3, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 4) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<4>(0hf)) node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 3, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 4) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<4>(0hf)) node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9) node _requestEIO_uncommonBits_T_2 = or(in[2].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_2 = bits(_requestEIO_uncommonBits_T_2, 3, 0) node _requestEIO_T_10 = shr(in[2].e.bits.sink, 4) node _requestEIO_T_11 = eq(_requestEIO_T_10, UInt<1>(0h0)) node _requestEIO_T_12 = leq(UInt<1>(0h0), requestEIO_uncommonBits_2) node _requestEIO_T_13 = and(_requestEIO_T_11, _requestEIO_T_12) node _requestEIO_T_14 = leq(requestEIO_uncommonBits_2, UInt<4>(0hf)) node requestEIO_2_1 = and(_requestEIO_T_13, _requestEIO_T_14) node _requestEIO_uncommonBits_T_3 = or(in[3].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_3 = bits(_requestEIO_uncommonBits_T_3, 3, 0) node _requestEIO_T_15 = shr(in[3].e.bits.sink, 4) node _requestEIO_T_16 = eq(_requestEIO_T_15, UInt<1>(0h0)) node _requestEIO_T_17 = leq(UInt<1>(0h0), requestEIO_uncommonBits_3) node _requestEIO_T_18 = and(_requestEIO_T_16, _requestEIO_T_17) node _requestEIO_T_19 = leq(requestEIO_uncommonBits_3, UInt<4>(0hf)) node requestEIO_3_1 = and(_requestEIO_T_18, _requestEIO_T_19) node _requestEIO_uncommonBits_T_4 = or(in[4].e.bits.sink, UInt<4>(0h0)) node requestEIO_uncommonBits_4 = bits(_requestEIO_uncommonBits_T_4, 3, 0) node _requestEIO_T_20 = shr(in[4].e.bits.sink, 4) node _requestEIO_T_21 = eq(_requestEIO_T_20, UInt<1>(0h0)) node _requestEIO_T_22 = leq(UInt<1>(0h0), requestEIO_uncommonBits_4) node _requestEIO_T_23 = and(_requestEIO_T_21, _requestEIO_T_22) node _requestEIO_T_24 = leq(requestEIO_uncommonBits_4, UInt<4>(0hf)) node requestEIO_4_1 = and(_requestEIO_T_23, _requestEIO_T_24) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 4) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 4) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size) node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0) node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7) node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 4) node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2) node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0)) node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0)) node _beatsAI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].a.bits.size) node _beatsAI_decode_T_10 = bits(_beatsAI_decode_T_9, 11, 0) node _beatsAI_decode_T_11 = not(_beatsAI_decode_T_10) node beatsAI_decode_3 = shr(_beatsAI_decode_T_11, 4) node _beatsAI_opdata_T_3 = bits(in[3].a.bits.opcode, 2, 2) node beatsAI_opdata_3 = eq(_beatsAI_opdata_T_3, UInt<1>(0h0)) node beatsAI_3 = mux(beatsAI_opdata_3, beatsAI_decode_3, UInt<1>(0h0)) node _beatsAI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].a.bits.size) node _beatsAI_decode_T_13 = bits(_beatsAI_decode_T_12, 11, 0) node _beatsAI_decode_T_14 = not(_beatsAI_decode_T_13) node beatsAI_decode_4 = shr(_beatsAI_decode_T_14, 4) node _beatsAI_opdata_T_4 = bits(in[4].a.bits.opcode, 2, 2) node beatsAI_opdata_4 = eq(_beatsAI_opdata_T_4, UInt<1>(0h0)) node beatsAI_4 = mux(beatsAI_opdata_4, beatsAI_decode_4, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 4) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 4) node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 4) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 4) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].c.bits.size) node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0) node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7) node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 4) node beatsCI_opdata_2 = bits(in[2].c.bits.opcode, 0, 0) node beatsCI_2 = mux(beatsCI_opdata_2, beatsCI_decode_2, UInt<1>(0h0)) node _beatsCI_decode_T_9 = dshl(UInt<12>(0hfff), in[3].c.bits.size) node _beatsCI_decode_T_10 = bits(_beatsCI_decode_T_9, 11, 0) node _beatsCI_decode_T_11 = not(_beatsCI_decode_T_10) node beatsCI_decode_3 = shr(_beatsCI_decode_T_11, 4) node beatsCI_opdata_3 = bits(in[3].c.bits.opcode, 0, 0) node beatsCI_3 = mux(beatsCI_opdata_3, beatsCI_decode_3, UInt<1>(0h0)) node _beatsCI_decode_T_12 = dshl(UInt<12>(0hfff), in[4].c.bits.size) node _beatsCI_decode_T_13 = bits(_beatsCI_decode_T_12, 11, 0) node _beatsCI_decode_T_14 = not(_beatsCI_decode_T_13) node beatsCI_decode_4 = shr(_beatsCI_decode_T_14, 4) node beatsCI_opdata_4 = bits(in[4].c.bits.opcode, 0, 0) node beatsCI_4 = mux(beatsCI_opdata_4, beatsCI_decode_4, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 4) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 4) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect portsAOI_filtered_1[1].bits, in[1].a.bits node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2) connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3 node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1) wire _portsAOI_in_1_a_ready_WIRE : UInt<1> connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2 connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_2[0].bits, in[2].a.bits node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4) connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5 connect portsAOI_filtered_2[1].bits, in[2].a.bits node _portsAOI_filtered_1_valid_T_4 = or(requestAIO_2_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_1_valid_T_4) connect portsAOI_filtered_2[1].valid, _portsAOI_filtered_1_valid_T_5 node _portsAOI_in_2_a_ready_T = mux(requestAIO_2_0, portsAOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_1 = mux(requestAIO_2_1, portsAOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_2 = or(_portsAOI_in_2_a_ready_T, _portsAOI_in_2_a_ready_T_1) wire _portsAOI_in_2_a_ready_WIRE : UInt<1> connect _portsAOI_in_2_a_ready_WIRE, _portsAOI_in_2_a_ready_T_2 connect in[2].a.ready, _portsAOI_in_2_a_ready_WIRE wire portsAOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_3[0].bits, in[3].a.bits node _portsAOI_filtered_0_valid_T_6 = or(requestAIO_3_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_0_valid_T_6) connect portsAOI_filtered_3[0].valid, _portsAOI_filtered_0_valid_T_7 connect portsAOI_filtered_3[1].bits, in[3].a.bits node _portsAOI_filtered_1_valid_T_6 = or(requestAIO_3_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_1_valid_T_6) connect portsAOI_filtered_3[1].valid, _portsAOI_filtered_1_valid_T_7 node _portsAOI_in_3_a_ready_T = mux(requestAIO_3_0, portsAOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsAOI_in_3_a_ready_T_1 = mux(requestAIO_3_1, portsAOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsAOI_in_3_a_ready_T_2 = or(_portsAOI_in_3_a_ready_T, _portsAOI_in_3_a_ready_T_1) wire _portsAOI_in_3_a_ready_WIRE : UInt<1> connect _portsAOI_in_3_a_ready_WIRE, _portsAOI_in_3_a_ready_T_2 connect in[3].a.ready, _portsAOI_in_3_a_ready_WIRE wire portsAOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_4[0].bits, in[4].a.bits node _portsAOI_filtered_0_valid_T_8 = or(requestAIO_4_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_0_valid_T_8) connect portsAOI_filtered_4[0].valid, _portsAOI_filtered_0_valid_T_9 connect portsAOI_filtered_4[1].bits, in[4].a.bits node _portsAOI_filtered_1_valid_T_8 = or(requestAIO_4_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_9 = and(in[4].a.valid, _portsAOI_filtered_1_valid_T_8) connect portsAOI_filtered_4[1].valid, _portsAOI_filtered_1_valid_T_9 node _portsAOI_in_4_a_ready_T = mux(requestAIO_4_0, portsAOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsAOI_in_4_a_ready_T_1 = mux(requestAIO_4_1, portsAOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsAOI_in_4_a_ready_T_2 = or(_portsAOI_in_4_a_ready_T, _portsAOI_in_4_a_ready_T_1) wire _portsAOI_in_4_a_ready_WIRE : UInt<1> connect _portsAOI_in_4_a_ready_WIRE, _portsAOI_in_4_a_ready_T_2 connect in[4].a.ready, _portsAOI_in_4_a_ready_WIRE wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 connect portsBIO_filtered[2].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[2].bits.data, out[0].b.bits.data connect portsBIO_filtered[2].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[2].bits.address, out[0].b.bits.address connect portsBIO_filtered[2].bits.source, out[0].b.bits.source connect portsBIO_filtered[2].bits.size, out[0].b.bits.size connect portsBIO_filtered[2].bits.param, out[0].b.bits.param connect portsBIO_filtered[2].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_2_valid_T) connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1 connect portsBIO_filtered[3].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[3].bits.data, out[0].b.bits.data connect portsBIO_filtered[3].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[3].bits.address, out[0].b.bits.address connect portsBIO_filtered[3].bits.source, out[0].b.bits.source connect portsBIO_filtered[3].bits.size, out[0].b.bits.size connect portsBIO_filtered[3].bits.param, out[0].b.bits.param connect portsBIO_filtered[3].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_3_valid_T = or(requestBOI_0_3, UInt<1>(0h0)) node _portsBIO_filtered_3_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_3_valid_T) connect portsBIO_filtered[3].valid, _portsBIO_filtered_3_valid_T_1 connect portsBIO_filtered[4].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[4].bits.data, out[0].b.bits.data connect portsBIO_filtered[4].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[4].bits.address, out[0].b.bits.address connect portsBIO_filtered[4].bits.source, out[0].b.bits.source connect portsBIO_filtered[4].bits.size, out[0].b.bits.size connect portsBIO_filtered[4].bits.param, out[0].b.bits.param connect portsBIO_filtered[4].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_4_valid_T = or(requestBOI_0_4, UInt<1>(0h0)) node _portsBIO_filtered_4_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_4_valid_T) connect portsBIO_filtered[4].valid, _portsBIO_filtered_4_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_3 = mux(requestBOI_0_3, portsBIO_filtered[3].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_4 = mux(requestBOI_0_4, portsBIO_filtered[4].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_5 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) node _portsBIO_out_0_b_ready_T_6 = or(_portsBIO_out_0_b_ready_T_5, _portsBIO_out_0_b_ready_T_2) node _portsBIO_out_0_b_ready_T_7 = or(_portsBIO_out_0_b_ready_T_6, _portsBIO_out_0_b_ready_T_3) node _portsBIO_out_0_b_ready_T_8 = or(_portsBIO_out_0_b_ready_T_7, _portsBIO_out_0_b_ready_T_4) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_8 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2) connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3 connect portsBIO_filtered_1[2].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[2].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[2].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[2].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[2].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[2].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[2].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[2].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_2_valid_T_2 = or(requestBOI_1_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_2_valid_T_2) connect portsBIO_filtered_1[2].valid, _portsBIO_filtered_2_valid_T_3 connect portsBIO_filtered_1[3].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[3].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[3].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[3].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[3].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[3].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[3].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[3].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_3_valid_T_2 = or(requestBOI_1_3, UInt<1>(0h0)) node _portsBIO_filtered_3_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_3_valid_T_2) connect portsBIO_filtered_1[3].valid, _portsBIO_filtered_3_valid_T_3 connect portsBIO_filtered_1[4].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[4].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[4].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[4].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[4].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[4].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[4].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[4].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_4_valid_T_2 = or(requestBOI_1_4, UInt<1>(0h0)) node _portsBIO_filtered_4_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_4_valid_T_2) connect portsBIO_filtered_1[4].valid, _portsBIO_filtered_4_valid_T_3 node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_2 = mux(requestBOI_1_2, portsBIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_3 = mux(requestBOI_1_3, portsBIO_filtered_1[3].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_4 = mux(requestBOI_1_4, portsBIO_filtered_1[4].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_5 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1) node _portsBIO_out_1_b_ready_T_6 = or(_portsBIO_out_1_b_ready_T_5, _portsBIO_out_1_b_ready_T_2) node _portsBIO_out_1_b_ready_T_7 = or(_portsBIO_out_1_b_ready_T_6, _portsBIO_out_1_b_ready_T_3) node _portsBIO_out_1_b_ready_T_8 = or(_portsBIO_out_1_b_ready_T_7, _portsBIO_out_1_b_ready_T_4) wire _portsBIO_out_1_b_ready_WIRE : UInt<1> connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_8 connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, in[0].c.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1) wire _portsCOI_in_0_c_ready_WIRE : UInt<1> connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2 connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect portsCOI_filtered_1[1].bits, in[1].c.bits node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2) connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3 node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1) wire _portsCOI_in_1_c_ready_WIRE : UInt<1> connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2 connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_2[0].bits, in[2].c.bits node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_0_valid_T_4) connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5 connect portsCOI_filtered_2[1].bits, in[2].c.bits node _portsCOI_filtered_1_valid_T_4 = or(requestCIO_2_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_1_valid_T_4) connect portsCOI_filtered_2[1].valid, _portsCOI_filtered_1_valid_T_5 node _portsCOI_in_2_c_ready_T = mux(requestCIO_2_0, portsCOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_1 = mux(requestCIO_2_1, portsCOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_2 = or(_portsCOI_in_2_c_ready_T, _portsCOI_in_2_c_ready_T_1) wire _portsCOI_in_2_c_ready_WIRE : UInt<1> connect _portsCOI_in_2_c_ready_WIRE, _portsCOI_in_2_c_ready_T_2 connect in[2].c.ready, _portsCOI_in_2_c_ready_WIRE wire portsCOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_3[0].bits, in[3].c.bits node _portsCOI_filtered_0_valid_T_6 = or(requestCIO_3_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_0_valid_T_6) connect portsCOI_filtered_3[0].valid, _portsCOI_filtered_0_valid_T_7 connect portsCOI_filtered_3[1].bits, in[3].c.bits node _portsCOI_filtered_1_valid_T_6 = or(requestCIO_3_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_7 = and(in[3].c.valid, _portsCOI_filtered_1_valid_T_6) connect portsCOI_filtered_3[1].valid, _portsCOI_filtered_1_valid_T_7 node _portsCOI_in_3_c_ready_T = mux(requestCIO_3_0, portsCOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsCOI_in_3_c_ready_T_1 = mux(requestCIO_3_1, portsCOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsCOI_in_3_c_ready_T_2 = or(_portsCOI_in_3_c_ready_T, _portsCOI_in_3_c_ready_T_1) wire _portsCOI_in_3_c_ready_WIRE : UInt<1> connect _portsCOI_in_3_c_ready_WIRE, _portsCOI_in_3_c_ready_T_2 connect in[3].c.ready, _portsCOI_in_3_c_ready_WIRE wire portsCOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_4[0].bits, in[4].c.bits node _portsCOI_filtered_0_valid_T_8 = or(requestCIO_4_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_0_valid_T_8) connect portsCOI_filtered_4[0].valid, _portsCOI_filtered_0_valid_T_9 connect portsCOI_filtered_4[1].bits, in[4].c.bits node _portsCOI_filtered_1_valid_T_8 = or(requestCIO_4_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_9 = and(in[4].c.valid, _portsCOI_filtered_1_valid_T_8) connect portsCOI_filtered_4[1].valid, _portsCOI_filtered_1_valid_T_9 node _portsCOI_in_4_c_ready_T = mux(requestCIO_4_0, portsCOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsCOI_in_4_c_ready_T_1 = mux(requestCIO_4_1, portsCOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsCOI_in_4_c_ready_T_2 = or(_portsCOI_in_4_c_ready_T, _portsCOI_in_4_c_ready_T_1) wire _portsCOI_in_4_c_ready_WIRE : UInt<1> connect _portsCOI_in_4_c_ready_WIRE, _portsCOI_in_4_c_ready_T_2 connect in[4].c.ready, _portsCOI_in_4_c_ready_WIRE wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[2].bits.data, out[0].d.bits.data connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[2].bits.source, out[0].d.bits.source connect portsDIO_filtered[2].bits.size, out[0].d.bits.size connect portsDIO_filtered[2].bits.param, out[0].d.bits.param connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T) connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1 connect portsDIO_filtered[3].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[3].bits.data, out[0].d.bits.data connect portsDIO_filtered[3].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[3].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[3].bits.source, out[0].d.bits.source connect portsDIO_filtered[3].bits.size, out[0].d.bits.size connect portsDIO_filtered[3].bits.param, out[0].d.bits.param connect portsDIO_filtered[3].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_3_valid_T = or(requestDOI_0_3, UInt<1>(0h0)) node _portsDIO_filtered_3_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_3_valid_T) connect portsDIO_filtered[3].valid, _portsDIO_filtered_3_valid_T_1 connect portsDIO_filtered[4].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[4].bits.data, out[0].d.bits.data connect portsDIO_filtered[4].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[4].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[4].bits.source, out[0].d.bits.source connect portsDIO_filtered[4].bits.size, out[0].d.bits.size connect portsDIO_filtered[4].bits.param, out[0].d.bits.param connect portsDIO_filtered[4].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_4_valid_T = or(requestDOI_0_4, UInt<1>(0h0)) node _portsDIO_filtered_4_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_4_valid_T) connect portsDIO_filtered[4].valid, _portsDIO_filtered_4_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_3 = mux(requestDOI_0_3, portsDIO_filtered[3].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_4 = mux(requestDOI_0_4, portsDIO_filtered[4].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_5 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) node _portsDIO_out_0_d_ready_T_6 = or(_portsDIO_out_0_d_ready_T_5, _portsDIO_out_0_d_ready_T_2) node _portsDIO_out_0_d_ready_T_7 = or(_portsDIO_out_0_d_ready_T_6, _portsDIO_out_0_d_ready_T_3) node _portsDIO_out_0_d_ready_T_8 = or(_portsDIO_out_0_d_ready_T_7, _portsDIO_out_0_d_ready_T_4) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_8 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[5] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2) connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3 connect portsDIO_filtered_1[2].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[2].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[2].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[2].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[2].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[2].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[2].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[2].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_2_valid_T_2 = or(requestDOI_1_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_2_valid_T_2) connect portsDIO_filtered_1[2].valid, _portsDIO_filtered_2_valid_T_3 connect portsDIO_filtered_1[3].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[3].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[3].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[3].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[3].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[3].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[3].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[3].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_3_valid_T_2 = or(requestDOI_1_3, UInt<1>(0h0)) node _portsDIO_filtered_3_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_3_valid_T_2) connect portsDIO_filtered_1[3].valid, _portsDIO_filtered_3_valid_T_3 connect portsDIO_filtered_1[4].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[4].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[4].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[4].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[4].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[4].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[4].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[4].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_4_valid_T_2 = or(requestDOI_1_4, UInt<1>(0h0)) node _portsDIO_filtered_4_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_4_valid_T_2) connect portsDIO_filtered_1[4].valid, _portsDIO_filtered_4_valid_T_3 node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_2 = mux(requestDOI_1_2, portsDIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_3 = mux(requestDOI_1_3, portsDIO_filtered_1[3].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_4 = mux(requestDOI_1_4, portsDIO_filtered_1[4].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_5 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1) node _portsDIO_out_1_d_ready_T_6 = or(_portsDIO_out_1_d_ready_T_5, _portsDIO_out_1_d_ready_T_2) node _portsDIO_out_1_d_ready_T_7 = or(_portsDIO_out_1_d_ready_T_6, _portsDIO_out_1_d_ready_T_3) node _portsDIO_out_1_d_ready_T_8 = or(_portsDIO_out_1_d_ready_T_7, _portsDIO_out_1_d_ready_T_4) wire _portsDIO_out_1_d_ready_WIRE : UInt<1> connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_8 connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, in[0].e.bits node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1) wire _portsEOI_in_0_e_ready_WIRE : UInt<1> connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2 connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect portsEOI_filtered_1[1].bits, in[1].e.bits node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2) connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3 node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1) wire _portsEOI_in_1_e_ready_WIRE : UInt<1> connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2 connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_2[0].bits, in[2].e.bits node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_0_valid_T_4) connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5 connect portsEOI_filtered_2[1].bits, in[2].e.bits node _portsEOI_filtered_1_valid_T_4 = or(requestEIO_2_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_1_valid_T_4) connect portsEOI_filtered_2[1].valid, _portsEOI_filtered_1_valid_T_5 node _portsEOI_in_2_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_1 = mux(requestEIO_2_1, portsEOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_2 = or(_portsEOI_in_2_e_ready_T, _portsEOI_in_2_e_ready_T_1) wire _portsEOI_in_2_e_ready_WIRE : UInt<1> connect _portsEOI_in_2_e_ready_WIRE, _portsEOI_in_2_e_ready_T_2 connect in[2].e.ready, _portsEOI_in_2_e_ready_WIRE wire portsEOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_3[0].bits, in[3].e.bits node _portsEOI_filtered_0_valid_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_0_valid_T_6) connect portsEOI_filtered_3[0].valid, _portsEOI_filtered_0_valid_T_7 connect portsEOI_filtered_3[1].bits, in[3].e.bits node _portsEOI_filtered_1_valid_T_6 = or(requestEIO_3_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_7 = and(in[3].e.valid, _portsEOI_filtered_1_valid_T_6) connect portsEOI_filtered_3[1].valid, _portsEOI_filtered_1_valid_T_7 node _portsEOI_in_3_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_3[0].ready, UInt<1>(0h0)) node _portsEOI_in_3_e_ready_T_1 = mux(requestEIO_3_1, portsEOI_filtered_3[1].ready, UInt<1>(0h0)) node _portsEOI_in_3_e_ready_T_2 = or(_portsEOI_in_3_e_ready_T, _portsEOI_in_3_e_ready_T_1) wire _portsEOI_in_3_e_ready_WIRE : UInt<1> connect _portsEOI_in_3_e_ready_WIRE, _portsEOI_in_3_e_ready_T_2 connect in[3].e.ready, _portsEOI_in_3_e_ready_WIRE wire portsEOI_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[2] connect portsEOI_filtered_4[0].bits, in[4].e.bits node _portsEOI_filtered_0_valid_T_8 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_0_valid_T_8) connect portsEOI_filtered_4[0].valid, _portsEOI_filtered_0_valid_T_9 connect portsEOI_filtered_4[1].bits, in[4].e.bits node _portsEOI_filtered_1_valid_T_8 = or(requestEIO_4_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_9 = and(in[4].e.valid, _portsEOI_filtered_1_valid_T_8) connect portsEOI_filtered_4[1].valid, _portsEOI_filtered_1_valid_T_9 node _portsEOI_in_4_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_4[0].ready, UInt<1>(0h0)) node _portsEOI_in_4_e_ready_T_1 = mux(requestEIO_4_1, portsEOI_filtered_4[1].ready, UInt<1>(0h0)) node _portsEOI_in_4_e_ready_T_2 = or(_portsEOI_in_4_e_ready_T, _portsEOI_in_4_e_ready_T_1) wire _portsEOI_in_4_e_ready_WIRE : UInt<1> connect _portsEOI_in_4_e_ready_WIRE, _portsEOI_in_4_e_ready_T_2 connect in[4].e.ready, _portsEOI_in_4_e_ready_WIRE regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node readys_lo = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_hi_hi = cat(portsAOI_filtered_4[0].valid, portsAOI_filtered_3[0].valid) node readys_hi = cat(readys_hi_hi, portsAOI_filtered_2[0].valid) node _readys_T = cat(readys_hi, readys_lo) node readys_valid = bits(_readys_T, 4, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<5>, clock, reset, UInt<5>(0h1f) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) node _readys_unready_T_4 = shr(_readys_unready_T_3, 4) node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_unready_T_6 = bits(_readys_unready_T_5, 9, 0) node _readys_unready_T_7 = shr(_readys_unready_T_6, 1) node _readys_unready_T_8 = shl(readys_mask, 5) node readys_unready = or(_readys_unready_T_7, _readys_unready_T_8) node _readys_readys_T = shr(readys_unready, 5) node _readys_readys_T_1 = bits(readys_unready, 4, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 4, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) node _readys_mask_T_5 = bits(_readys_mask_T_4, 4, 0) node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) node _readys_mask_T_7 = shl(_readys_mask_T_6, 4) node _readys_mask_T_8 = bits(_readys_mask_T_7, 4, 0) node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8) node _readys_mask_T_10 = bits(_readys_mask_T_9, 4, 0) connect readys_mask, _readys_mask_T_10 node _readys_T_7 = bits(readys_readys, 4, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) node _readys_T_10 = bits(_readys_T_7, 2, 2) node _readys_T_11 = bits(_readys_T_7, 3, 3) node _readys_T_12 = bits(_readys_T_7, 4, 4) wire readys : UInt<1>[5] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 connect readys[2], _readys_T_10 connect readys[3], _readys_T_11 connect readys[4], _readys_T_12 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid) node _winner_T_3 = and(readys[3], portsAOI_filtered_3[0].valid) node _winner_T_4 = and(readys[4], portsAOI_filtered_4[0].valid) wire winner : UInt<1>[5] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 connect winner[3], _winner_T_3 connect winner[4], _winner_T_4 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node prefixOR_3 = or(prefixOR_2, winner[2]) node prefixOR_4 = or(prefixOR_3, winner[3]) node _prefixOR_T = or(prefixOR_4, winner[4]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) node _T_7 = eq(winner[2], UInt<1>(0h0)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(prefixOR_3, UInt<1>(0h0)) node _T_10 = eq(winner[3], UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = eq(prefixOR_4, UInt<1>(0h0)) node _T_13 = eq(winner[4], UInt<1>(0h0)) node _T_14 = or(_T_12, _T_13) node _T_15 = and(_T_2, _T_5) node _T_16 = and(_T_15, _T_8) node _T_17 = and(_T_16, _T_11) node _T_18 = and(_T_17, _T_14) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert node _T_22 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_23 = or(_T_22, portsAOI_filtered_2[0].valid) node _T_24 = or(_T_23, portsAOI_filtered_3[0].valid) node _T_25 = or(_T_24, portsAOI_filtered_4[0].valid) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = or(winner[0], winner[1]) node _T_28 = or(_T_27, winner[2]) node _T_29 = or(_T_28, winner[3]) node _T_30 = or(_T_29, winner[4]) node _T_31 = or(_T_26, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1 assert(clock, _T_31, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0)) node maskedBeats_3 = mux(winner[3], beatsAI_3, UInt<1>(0h0)) node maskedBeats_4 = mux(winner[4], beatsAI_4, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2) node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3) node initBeats = or(_initBeats_T_2, maskedBeats_4) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[5] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) connect _state_WIRE[3], UInt<1>(0h0) connect _state_WIRE[4], UInt<1>(0h0) regreset state : UInt<1>[5], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2]) connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2 node _filtered_0_ready_T_3 = and(out[0].a.ready, allowed[3]) connect portsAOI_filtered_3[0].ready, _filtered_0_ready_T_3 node _filtered_0_ready_T_4 = and(out[0].a.ready, allowed[4]) connect portsAOI_filtered_4[0].ready, _filtered_0_ready_T_4 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid) node _out_0_a_valid_T_2 = or(_out_0_a_valid_T_1, portsAOI_filtered_3[0].valid) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_2, portsAOI_filtered_4[0].valid) node _out_0_a_valid_T_4 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_5 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_6 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_7 = mux(state[3], portsAOI_filtered_3[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_8 = mux(state[4], portsAOI_filtered_4[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_9 = or(_out_0_a_valid_T_4, _out_0_a_valid_T_5) node _out_0_a_valid_T_10 = or(_out_0_a_valid_T_9, _out_0_a_valid_T_6) node _out_0_a_valid_T_11 = or(_out_0_a_valid_T_10, _out_0_a_valid_T_7) node _out_0_a_valid_T_12 = or(_out_0_a_valid_T_11, _out_0_a_valid_T_8) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_12 node _out_0_a_valid_T_13 = mux(idle, _out_0_a_valid_T_3, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_13 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_3 = mux(muxState[3], portsAOI_filtered_3[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[4], portsAOI_filtered_4[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) node _out_0_a_bits_T_6 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_2) node _out_0_a_bits_T_7 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_3) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_7, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_11 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_12 = mux(muxState[3], portsAOI_filtered_3[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[4], portsAOI_filtered_4[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) node _out_0_a_bits_T_15 = or(_out_0_a_bits_T_14, _out_0_a_bits_T_11) node _out_0_a_bits_T_16 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_12) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_16, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_2 : UInt<128> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_20 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_21 = mux(muxState[3], portsAOI_filtered_3[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[4], portsAOI_filtered_4[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_20) node _out_0_a_bits_T_25 = or(_out_0_a_bits_T_24, _out_0_a_bits_T_21) node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_3 : UInt<16> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_26 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_27 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_28 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_29 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_30 = mux(muxState[3], portsAOI_filtered_3[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_31 = mux(muxState[4], portsAOI_filtered_4[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_27, _out_0_a_bits_T_28) node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_32, _out_0_a_bits_T_29) node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_30) node _out_0_a_bits_T_35 = or(_out_0_a_bits_T_34, _out_0_a_bits_T_31) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_35 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_36 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_37 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_38 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_39 = mux(muxState[3], portsAOI_filtered_3[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_40 = mux(muxState[4], portsAOI_filtered_4[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_36, _out_0_a_bits_T_37) node _out_0_a_bits_T_42 = or(_out_0_a_bits_T_41, _out_0_a_bits_T_38) node _out_0_a_bits_T_43 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_39) node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_43, _out_0_a_bits_T_40) wire _out_0_a_bits_WIRE_7 : UInt<7> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_44 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_45 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_46 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_47 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_48 = mux(muxState[3], portsAOI_filtered_3[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_49 = mux(muxState[4], portsAOI_filtered_4[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_50 = or(_out_0_a_bits_T_45, _out_0_a_bits_T_46) node _out_0_a_bits_T_51 = or(_out_0_a_bits_T_50, _out_0_a_bits_T_47) node _out_0_a_bits_T_52 = or(_out_0_a_bits_T_51, _out_0_a_bits_T_48) node _out_0_a_bits_T_53 = or(_out_0_a_bits_T_52, _out_0_a_bits_T_49) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_53 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_54 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_55 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_56 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_57 = mux(muxState[3], portsAOI_filtered_3[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_58 = mux(muxState[4], portsAOI_filtered_4[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_59 = or(_out_0_a_bits_T_54, _out_0_a_bits_T_55) node _out_0_a_bits_T_60 = or(_out_0_a_bits_T_59, _out_0_a_bits_T_56) node _out_0_a_bits_T_61 = or(_out_0_a_bits_T_60, _out_0_a_bits_T_57) node _out_0_a_bits_T_62 = or(_out_0_a_bits_T_61, _out_0_a_bits_T_58) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_62 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_63 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_64 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_65 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_66 = mux(muxState[3], portsAOI_filtered_3[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_67 = mux(muxState[4], portsAOI_filtered_4[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_68 = or(_out_0_a_bits_T_63, _out_0_a_bits_T_64) node _out_0_a_bits_T_69 = or(_out_0_a_bits_T_68, _out_0_a_bits_T_65) node _out_0_a_bits_T_70 = or(_out_0_a_bits_T_69, _out_0_a_bits_T_66) node _out_0_a_bits_T_71 = or(_out_0_a_bits_T_70, _out_0_a_bits_T_67) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_71 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].e.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsCOI_filtered_2[0].ready, UInt<1>(0h0) connect portsCOI_filtered_3[0].ready, UInt<1>(0h0) connect portsCOI_filtered_4[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_2[0].ready, UInt<1>(0h0) connect portsEOI_filtered_3[0].ready, UInt<1>(0h0) connect portsEOI_filtered_4[0].ready, UInt<1>(0h0) regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, out[1].a.ready) node readys_lo_1 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid) node readys_hi_hi_1 = cat(portsAOI_filtered_4[1].valid, portsAOI_filtered_3[1].valid) node readys_hi_1 = cat(readys_hi_hi_1, portsAOI_filtered_2[1].valid) node _readys_T_13 = cat(readys_hi_1, readys_lo_1) node readys_valid_1 = bits(_readys_T_13, 4, 0) node _readys_T_14 = eq(readys_valid_1, _readys_T_13) node _readys_T_15 = asUInt(reset) node _readys_T_16 = eq(_readys_T_15, UInt<1>(0h0)) when _readys_T_16 : node _readys_T_17 = eq(_readys_T_14, UInt<1>(0h0)) when _readys_T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1 assert(clock, _readys_T_14, UInt<1>(0h1), "") : readys_assert_1 regreset readys_mask_1 : UInt<5>, clock, reset, UInt<5>(0h1f) node _readys_filter_T_2 = not(readys_mask_1) node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2) node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1) node _readys_unready_T_9 = shr(readys_filter_1, 1) node _readys_unready_T_10 = or(readys_filter_1, _readys_unready_T_9) node _readys_unready_T_11 = shr(_readys_unready_T_10, 2) node _readys_unready_T_12 = or(_readys_unready_T_10, _readys_unready_T_11) node _readys_unready_T_13 = shr(_readys_unready_T_12, 4) node _readys_unready_T_14 = or(_readys_unready_T_12, _readys_unready_T_13) node _readys_unready_T_15 = bits(_readys_unready_T_14, 9, 0) node _readys_unready_T_16 = shr(_readys_unready_T_15, 1) node _readys_unready_T_17 = shl(readys_mask_1, 5) node readys_unready_1 = or(_readys_unready_T_16, _readys_unready_T_17) node _readys_readys_T_3 = shr(readys_unready_1, 5) node _readys_readys_T_4 = bits(readys_unready_1, 4, 0) node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4) node readys_readys_1 = not(_readys_readys_T_5) node _readys_T_18 = orr(readys_valid_1) node _readys_T_19 = and(latch_1, _readys_T_18) when _readys_T_19 : node _readys_mask_T_11 = and(readys_readys_1, readys_valid_1) node _readys_mask_T_12 = shl(_readys_mask_T_11, 1) node _readys_mask_T_13 = bits(_readys_mask_T_12, 4, 0) node _readys_mask_T_14 = or(_readys_mask_T_11, _readys_mask_T_13) node _readys_mask_T_15 = shl(_readys_mask_T_14, 2) node _readys_mask_T_16 = bits(_readys_mask_T_15, 4, 0) node _readys_mask_T_17 = or(_readys_mask_T_14, _readys_mask_T_16) node _readys_mask_T_18 = shl(_readys_mask_T_17, 4) node _readys_mask_T_19 = bits(_readys_mask_T_18, 4, 0) node _readys_mask_T_20 = or(_readys_mask_T_17, _readys_mask_T_19) node _readys_mask_T_21 = bits(_readys_mask_T_20, 4, 0) connect readys_mask_1, _readys_mask_T_21 node _readys_T_20 = bits(readys_readys_1, 4, 0) node _readys_T_21 = bits(_readys_T_20, 0, 0) node _readys_T_22 = bits(_readys_T_20, 1, 1) node _readys_T_23 = bits(_readys_T_20, 2, 2) node _readys_T_24 = bits(_readys_T_20, 3, 3) node _readys_T_25 = bits(_readys_T_20, 4, 4) wire readys_1 : UInt<1>[5] connect readys_1[0], _readys_T_21 connect readys_1[1], _readys_T_22 connect readys_1[2], _readys_T_23 connect readys_1[3], _readys_T_24 connect readys_1[4], _readys_T_25 node _winner_T_5 = and(readys_1[0], portsAOI_filtered[1].valid) node _winner_T_6 = and(readys_1[1], portsAOI_filtered_1[1].valid) node _winner_T_7 = and(readys_1[2], portsAOI_filtered_2[1].valid) node _winner_T_8 = and(readys_1[3], portsAOI_filtered_3[1].valid) node _winner_T_9 = and(readys_1[4], portsAOI_filtered_4[1].valid) wire winner_1 : UInt<1>[5] connect winner_1[0], _winner_T_5 connect winner_1[1], _winner_T_6 connect winner_1[2], _winner_T_7 connect winner_1[3], _winner_T_8 connect winner_1[4], _winner_T_9 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node prefixOR_2_1 = or(prefixOR_1_1, winner_1[1]) node prefixOR_3_1 = or(prefixOR_2_1, winner_1[2]) node prefixOR_4_1 = or(prefixOR_3_1, winner_1[3]) node _prefixOR_T_1 = or(prefixOR_4_1, winner_1[4]) node _T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_36 = eq(winner_1[0], UInt<1>(0h0)) node _T_37 = or(_T_35, _T_36) node _T_38 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_39 = eq(winner_1[1], UInt<1>(0h0)) node _T_40 = or(_T_38, _T_39) node _T_41 = eq(prefixOR_2_1, UInt<1>(0h0)) node _T_42 = eq(winner_1[2], UInt<1>(0h0)) node _T_43 = or(_T_41, _T_42) node _T_44 = eq(prefixOR_3_1, UInt<1>(0h0)) node _T_45 = eq(winner_1[3], UInt<1>(0h0)) node _T_46 = or(_T_44, _T_45) node _T_47 = eq(prefixOR_4_1, UInt<1>(0h0)) node _T_48 = eq(winner_1[4], UInt<1>(0h0)) node _T_49 = or(_T_47, _T_48) node _T_50 = and(_T_37, _T_40) node _T_51 = and(_T_50, _T_43) node _T_52 = and(_T_51, _T_46) node _T_53 = and(_T_52, _T_49) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_53, UInt<1>(0h1), "") : assert_2 node _T_57 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _T_58 = or(_T_57, portsAOI_filtered_2[1].valid) node _T_59 = or(_T_58, portsAOI_filtered_3[1].valid) node _T_60 = or(_T_59, portsAOI_filtered_4[1].valid) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = or(winner_1[0], winner_1[1]) node _T_63 = or(_T_62, winner_1[2]) node _T_64 = or(_T_63, winner_1[3]) node _T_65 = or(_T_64, winner_1[4]) node _T_66 = or(_T_61, _T_65) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3 assert(clock, _T_66, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2_1 = mux(winner_1[2], beatsAI_2, UInt<1>(0h0)) node maskedBeats_3_1 = mux(winner_1[3], beatsAI_3, UInt<1>(0h0)) node maskedBeats_4_1 = mux(winner_1[4], beatsAI_4, UInt<1>(0h0)) node _initBeats_T_3 = or(maskedBeats_0_1, maskedBeats_1_1) node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_2_1) node _initBeats_T_5 = or(_initBeats_T_4, maskedBeats_3_1) node initBeats_1 = or(_initBeats_T_5, maskedBeats_4_1) node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[5] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) connect _state_WIRE_1[2], UInt<1>(0h0) connect _state_WIRE_1[3], UInt<1>(0h0) connect _state_WIRE_1[4], UInt<1>(0h0) regreset state_1 : UInt<1>[5], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0]) connect portsAOI_filtered[1].ready, _filtered_1_ready_T node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1]) connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1 node _filtered_1_ready_T_2 = and(out[1].a.ready, allowed_1[2]) connect portsAOI_filtered_2[1].ready, _filtered_1_ready_T_2 node _filtered_1_ready_T_3 = and(out[1].a.ready, allowed_1[3]) connect portsAOI_filtered_3[1].ready, _filtered_1_ready_T_3 node _filtered_1_ready_T_4 = and(out[1].a.ready, allowed_1[4]) connect portsAOI_filtered_4[1].ready, _filtered_1_ready_T_4 node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _out_1_a_valid_T_1 = or(_out_1_a_valid_T, portsAOI_filtered_2[1].valid) node _out_1_a_valid_T_2 = or(_out_1_a_valid_T_1, portsAOI_filtered_3[1].valid) node _out_1_a_valid_T_3 = or(_out_1_a_valid_T_2, portsAOI_filtered_4[1].valid) node _out_1_a_valid_T_4 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_5 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_6 = mux(state_1[2], portsAOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_7 = mux(state_1[3], portsAOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_8 = mux(state_1[4], portsAOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_9 = or(_out_1_a_valid_T_4, _out_1_a_valid_T_5) node _out_1_a_valid_T_10 = or(_out_1_a_valid_T_9, _out_1_a_valid_T_6) node _out_1_a_valid_T_11 = or(_out_1_a_valid_T_10, _out_1_a_valid_T_7) node _out_1_a_valid_T_12 = or(_out_1_a_valid_T_11, _out_1_a_valid_T_8) wire _out_1_a_valid_WIRE : UInt<1> connect _out_1_a_valid_WIRE, _out_1_a_valid_T_12 node _out_1_a_valid_T_13 = mux(idle_1, _out_1_a_valid_T_3, _out_1_a_valid_WIRE) connect out[1].a.valid, _out_1_a_valid_T_13 wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_2 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_3 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_4 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_5 = or(_out_1_a_bits_T, _out_1_a_bits_T_1) node _out_1_a_bits_T_6 = or(_out_1_a_bits_T_5, _out_1_a_bits_T_2) node _out_1_a_bits_T_7 = or(_out_1_a_bits_T_6, _out_1_a_bits_T_3) node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_7, _out_1_a_bits_T_4) wire _out_1_a_bits_WIRE_1 : UInt<1> connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_8 connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1 node _out_1_a_bits_T_9 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_10 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_11 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_12 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_13 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_9, _out_1_a_bits_T_10) node _out_1_a_bits_T_15 = or(_out_1_a_bits_T_14, _out_1_a_bits_T_11) node _out_1_a_bits_T_16 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_12) node _out_1_a_bits_T_17 = or(_out_1_a_bits_T_16, _out_1_a_bits_T_13) wire _out_1_a_bits_WIRE_2 : UInt<128> connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_17 connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2 node _out_1_a_bits_T_18 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_19 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_20 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_21 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_22 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_19) node _out_1_a_bits_T_24 = or(_out_1_a_bits_T_23, _out_1_a_bits_T_20) node _out_1_a_bits_T_25 = or(_out_1_a_bits_T_24, _out_1_a_bits_T_21) node _out_1_a_bits_T_26 = or(_out_1_a_bits_T_25, _out_1_a_bits_T_22) wire _out_1_a_bits_WIRE_3 : UInt<16> connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_26 connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3 wire _out_1_a_bits_WIRE_4 : { } connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4 wire _out_1_a_bits_WIRE_5 : { } connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5 node _out_1_a_bits_T_27 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_28 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_29 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_30 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_31 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_32 = or(_out_1_a_bits_T_27, _out_1_a_bits_T_28) node _out_1_a_bits_T_33 = or(_out_1_a_bits_T_32, _out_1_a_bits_T_29) node _out_1_a_bits_T_34 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_30) node _out_1_a_bits_T_35 = or(_out_1_a_bits_T_34, _out_1_a_bits_T_31) wire _out_1_a_bits_WIRE_6 : UInt<32> connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_35 connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6 node _out_1_a_bits_T_36 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_37 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_38 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_39 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_40 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_41 = or(_out_1_a_bits_T_36, _out_1_a_bits_T_37) node _out_1_a_bits_T_42 = or(_out_1_a_bits_T_41, _out_1_a_bits_T_38) node _out_1_a_bits_T_43 = or(_out_1_a_bits_T_42, _out_1_a_bits_T_39) node _out_1_a_bits_T_44 = or(_out_1_a_bits_T_43, _out_1_a_bits_T_40) wire _out_1_a_bits_WIRE_7 : UInt<7> connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_44 connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7 node _out_1_a_bits_T_45 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_46 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_47 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_48 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_49 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_50 = or(_out_1_a_bits_T_45, _out_1_a_bits_T_46) node _out_1_a_bits_T_51 = or(_out_1_a_bits_T_50, _out_1_a_bits_T_47) node _out_1_a_bits_T_52 = or(_out_1_a_bits_T_51, _out_1_a_bits_T_48) node _out_1_a_bits_T_53 = or(_out_1_a_bits_T_52, _out_1_a_bits_T_49) wire _out_1_a_bits_WIRE_8 : UInt<4> connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_53 connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8 node _out_1_a_bits_T_54 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_55 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_56 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_57 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_58 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_59 = or(_out_1_a_bits_T_54, _out_1_a_bits_T_55) node _out_1_a_bits_T_60 = or(_out_1_a_bits_T_59, _out_1_a_bits_T_56) node _out_1_a_bits_T_61 = or(_out_1_a_bits_T_60, _out_1_a_bits_T_57) node _out_1_a_bits_T_62 = or(_out_1_a_bits_T_61, _out_1_a_bits_T_58) wire _out_1_a_bits_WIRE_9 : UInt<3> connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_62 connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9 node _out_1_a_bits_T_63 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_64 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_65 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_66 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_67 = mux(muxState_1[4], portsAOI_filtered_4[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_68 = or(_out_1_a_bits_T_63, _out_1_a_bits_T_64) node _out_1_a_bits_T_69 = or(_out_1_a_bits_T_68, _out_1_a_bits_T_65) node _out_1_a_bits_T_70 = or(_out_1_a_bits_T_69, _out_1_a_bits_T_66) node _out_1_a_bits_T_71 = or(_out_1_a_bits_T_70, _out_1_a_bits_T_67) wire _out_1_a_bits_WIRE_10 : UInt<3> connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_71 connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10 connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt connect out[1].a.bits.data, _out_1_a_bits_WIRE.data connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask connect out[1].a.bits.address, _out_1_a_bits_WIRE.address connect out[1].a.bits.source, _out_1_a_bits_WIRE.source connect out[1].a.bits.size, _out_1_a_bits_WIRE.size connect out[1].a.bits.param, _out_1_a_bits_WIRE.param connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0) node idle_2 = eq(beatsLeft_2, UInt<1>(0h0)) node latch_2 = and(idle_2, out[1].c.ready) node readys_lo_2 = cat(portsCOI_filtered_2[1].valid, portsCOI_filtered_1[1].valid) node readys_hi_2 = cat(portsCOI_filtered_4[1].valid, portsCOI_filtered_3[1].valid) node _readys_T_26 = cat(readys_hi_2, readys_lo_2) node readys_valid_2 = bits(_readys_T_26, 3, 0) node _readys_T_27 = eq(readys_valid_2, _readys_T_26) node _readys_T_28 = asUInt(reset) node _readys_T_29 = eq(_readys_T_28, UInt<1>(0h0)) when _readys_T_29 : node _readys_T_30 = eq(_readys_T_27, UInt<1>(0h0)) when _readys_T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2 assert(clock, _readys_T_27, UInt<1>(0h1), "") : readys_assert_2 regreset readys_mask_2 : UInt<4>, clock, reset, UInt<4>(0hf) node _readys_filter_T_4 = not(readys_mask_2) node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4) node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2) node _readys_unready_T_18 = shr(readys_filter_2, 1) node _readys_unready_T_19 = or(readys_filter_2, _readys_unready_T_18) node _readys_unready_T_20 = shr(_readys_unready_T_19, 2) node _readys_unready_T_21 = or(_readys_unready_T_19, _readys_unready_T_20) node _readys_unready_T_22 = bits(_readys_unready_T_21, 7, 0) node _readys_unready_T_23 = shr(_readys_unready_T_22, 1) node _readys_unready_T_24 = shl(readys_mask_2, 4) node readys_unready_2 = or(_readys_unready_T_23, _readys_unready_T_24) node _readys_readys_T_6 = shr(readys_unready_2, 4) node _readys_readys_T_7 = bits(readys_unready_2, 3, 0) node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7) node readys_readys_2 = not(_readys_readys_T_8) node _readys_T_31 = orr(readys_valid_2) node _readys_T_32 = and(latch_2, _readys_T_31) when _readys_T_32 : node _readys_mask_T_22 = and(readys_readys_2, readys_valid_2) node _readys_mask_T_23 = shl(_readys_mask_T_22, 1) node _readys_mask_T_24 = bits(_readys_mask_T_23, 3, 0) node _readys_mask_T_25 = or(_readys_mask_T_22, _readys_mask_T_24) node _readys_mask_T_26 = shl(_readys_mask_T_25, 2) node _readys_mask_T_27 = bits(_readys_mask_T_26, 3, 0) node _readys_mask_T_28 = or(_readys_mask_T_25, _readys_mask_T_27) node _readys_mask_T_29 = bits(_readys_mask_T_28, 3, 0) connect readys_mask_2, _readys_mask_T_29 node _readys_T_33 = bits(readys_readys_2, 3, 0) node _readys_T_34 = bits(_readys_T_33, 0, 0) node _readys_T_35 = bits(_readys_T_33, 1, 1) node _readys_T_36 = bits(_readys_T_33, 2, 2) node _readys_T_37 = bits(_readys_T_33, 3, 3) wire readys_2 : UInt<1>[4] connect readys_2[0], _readys_T_34 connect readys_2[1], _readys_T_35 connect readys_2[2], _readys_T_36 connect readys_2[3], _readys_T_37 node _winner_T_10 = and(readys_2[0], portsCOI_filtered_1[1].valid) node _winner_T_11 = and(readys_2[1], portsCOI_filtered_2[1].valid) node _winner_T_12 = and(readys_2[2], portsCOI_filtered_3[1].valid) node _winner_T_13 = and(readys_2[3], portsCOI_filtered_4[1].valid) wire winner_2 : UInt<1>[4] connect winner_2[0], _winner_T_10 connect winner_2[1], _winner_T_11 connect winner_2[2], _winner_T_12 connect winner_2[3], _winner_T_13 node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0]) node prefixOR_2_2 = or(prefixOR_1_2, winner_2[1]) node prefixOR_3_2 = or(prefixOR_2_2, winner_2[2]) node _prefixOR_T_2 = or(prefixOR_3_2, winner_2[3]) node _T_70 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_71 = eq(winner_2[0], UInt<1>(0h0)) node _T_72 = or(_T_70, _T_71) node _T_73 = eq(prefixOR_1_2, UInt<1>(0h0)) node _T_74 = eq(winner_2[1], UInt<1>(0h0)) node _T_75 = or(_T_73, _T_74) node _T_76 = eq(prefixOR_2_2, UInt<1>(0h0)) node _T_77 = eq(winner_2[2], UInt<1>(0h0)) node _T_78 = or(_T_76, _T_77) node _T_79 = eq(prefixOR_3_2, UInt<1>(0h0)) node _T_80 = eq(winner_2[3], UInt<1>(0h0)) node _T_81 = or(_T_79, _T_80) node _T_82 = and(_T_72, _T_75) node _T_83 = and(_T_82, _T_78) node _T_84 = and(_T_83, _T_81) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_84, UInt<1>(0h1), "") : assert_4 node _T_88 = or(portsCOI_filtered_1[1].valid, portsCOI_filtered_2[1].valid) node _T_89 = or(_T_88, portsCOI_filtered_3[1].valid) node _T_90 = or(_T_89, portsCOI_filtered_4[1].valid) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = or(winner_2[0], winner_2[1]) node _T_93 = or(_T_92, winner_2[2]) node _T_94 = or(_T_93, winner_2[3]) node _T_95 = or(_T_91, _T_94) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5 assert(clock, _T_95, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_2 = mux(winner_2[0], beatsCI_1, UInt<1>(0h0)) node maskedBeats_1_2 = mux(winner_2[1], beatsCI_2, UInt<1>(0h0)) node maskedBeats_2_2 = mux(winner_2[2], beatsCI_3, UInt<1>(0h0)) node maskedBeats_3_2 = mux(winner_2[3], beatsCI_4, UInt<1>(0h0)) node _initBeats_T_6 = or(maskedBeats_0_2, maskedBeats_1_2) node _initBeats_T_7 = or(_initBeats_T_6, maskedBeats_2_2) node initBeats_2 = or(_initBeats_T_7, maskedBeats_3_2) node _beatsLeft_T_8 = and(out[1].c.ready, out[1].c.valid) node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8) node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1) node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10) connect beatsLeft_2, _beatsLeft_T_11 wire _state_WIRE_2 : UInt<1>[4] connect _state_WIRE_2[0], UInt<1>(0h0) connect _state_WIRE_2[1], UInt<1>(0h0) connect _state_WIRE_2[2], UInt<1>(0h0) connect _state_WIRE_2[3], UInt<1>(0h0) regreset state_2 : UInt<1>[4], clock, reset, _state_WIRE_2 node muxState_2 = mux(idle_2, winner_2, state_2) connect state_2, muxState_2 node allowed_2 = mux(idle_2, readys_2, state_2) node _filtered_1_ready_T_5 = and(out[1].c.ready, allowed_2[0]) connect portsCOI_filtered_1[1].ready, _filtered_1_ready_T_5 node _filtered_1_ready_T_6 = and(out[1].c.ready, allowed_2[1]) connect portsCOI_filtered_2[1].ready, _filtered_1_ready_T_6 node _filtered_1_ready_T_7 = and(out[1].c.ready, allowed_2[2]) connect portsCOI_filtered_3[1].ready, _filtered_1_ready_T_7 node _filtered_1_ready_T_8 = and(out[1].c.ready, allowed_2[3]) connect portsCOI_filtered_4[1].ready, _filtered_1_ready_T_8 node _out_1_c_valid_T = or(portsCOI_filtered_1[1].valid, portsCOI_filtered_2[1].valid) node _out_1_c_valid_T_1 = or(_out_1_c_valid_T, portsCOI_filtered_3[1].valid) node _out_1_c_valid_T_2 = or(_out_1_c_valid_T_1, portsCOI_filtered_4[1].valid) node _out_1_c_valid_T_3 = mux(state_2[0], portsCOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_4 = mux(state_2[1], portsCOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_5 = mux(state_2[2], portsCOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_6 = mux(state_2[3], portsCOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_c_valid_T_7 = or(_out_1_c_valid_T_3, _out_1_c_valid_T_4) node _out_1_c_valid_T_8 = or(_out_1_c_valid_T_7, _out_1_c_valid_T_5) node _out_1_c_valid_T_9 = or(_out_1_c_valid_T_8, _out_1_c_valid_T_6) wire _out_1_c_valid_WIRE : UInt<1> connect _out_1_c_valid_WIRE, _out_1_c_valid_T_9 node _out_1_c_valid_T_10 = mux(idle_2, _out_1_c_valid_T_2, _out_1_c_valid_WIRE) connect out[1].c.valid, _out_1_c_valid_T_10 wire _out_1_c_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _out_1_c_bits_T = mux(muxState_2[0], portsCOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_1 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_2 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_3 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.corrupt, UInt<1>(0h0)) node _out_1_c_bits_T_4 = or(_out_1_c_bits_T, _out_1_c_bits_T_1) node _out_1_c_bits_T_5 = or(_out_1_c_bits_T_4, _out_1_c_bits_T_2) node _out_1_c_bits_T_6 = or(_out_1_c_bits_T_5, _out_1_c_bits_T_3) wire _out_1_c_bits_WIRE_1 : UInt<1> connect _out_1_c_bits_WIRE_1, _out_1_c_bits_T_6 connect _out_1_c_bits_WIRE.corrupt, _out_1_c_bits_WIRE_1 node _out_1_c_bits_T_7 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_8 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_9 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_10 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.data, UInt<1>(0h0)) node _out_1_c_bits_T_11 = or(_out_1_c_bits_T_7, _out_1_c_bits_T_8) node _out_1_c_bits_T_12 = or(_out_1_c_bits_T_11, _out_1_c_bits_T_9) node _out_1_c_bits_T_13 = or(_out_1_c_bits_T_12, _out_1_c_bits_T_10) wire _out_1_c_bits_WIRE_2 : UInt<128> connect _out_1_c_bits_WIRE_2, _out_1_c_bits_T_13 connect _out_1_c_bits_WIRE.data, _out_1_c_bits_WIRE_2 wire _out_1_c_bits_WIRE_3 : { } connect _out_1_c_bits_WIRE.echo, _out_1_c_bits_WIRE_3 wire _out_1_c_bits_WIRE_4 : { } connect _out_1_c_bits_WIRE.user, _out_1_c_bits_WIRE_4 node _out_1_c_bits_T_14 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_15 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_16 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_17 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.address, UInt<1>(0h0)) node _out_1_c_bits_T_18 = or(_out_1_c_bits_T_14, _out_1_c_bits_T_15) node _out_1_c_bits_T_19 = or(_out_1_c_bits_T_18, _out_1_c_bits_T_16) node _out_1_c_bits_T_20 = or(_out_1_c_bits_T_19, _out_1_c_bits_T_17) wire _out_1_c_bits_WIRE_5 : UInt<32> connect _out_1_c_bits_WIRE_5, _out_1_c_bits_T_20 connect _out_1_c_bits_WIRE.address, _out_1_c_bits_WIRE_5 node _out_1_c_bits_T_21 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_22 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_23 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_24 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.source, UInt<1>(0h0)) node _out_1_c_bits_T_25 = or(_out_1_c_bits_T_21, _out_1_c_bits_T_22) node _out_1_c_bits_T_26 = or(_out_1_c_bits_T_25, _out_1_c_bits_T_23) node _out_1_c_bits_T_27 = or(_out_1_c_bits_T_26, _out_1_c_bits_T_24) wire _out_1_c_bits_WIRE_6 : UInt<7> connect _out_1_c_bits_WIRE_6, _out_1_c_bits_T_27 connect _out_1_c_bits_WIRE.source, _out_1_c_bits_WIRE_6 node _out_1_c_bits_T_28 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_29 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_30 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_31 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.size, UInt<1>(0h0)) node _out_1_c_bits_T_32 = or(_out_1_c_bits_T_28, _out_1_c_bits_T_29) node _out_1_c_bits_T_33 = or(_out_1_c_bits_T_32, _out_1_c_bits_T_30) node _out_1_c_bits_T_34 = or(_out_1_c_bits_T_33, _out_1_c_bits_T_31) wire _out_1_c_bits_WIRE_7 : UInt<4> connect _out_1_c_bits_WIRE_7, _out_1_c_bits_T_34 connect _out_1_c_bits_WIRE.size, _out_1_c_bits_WIRE_7 node _out_1_c_bits_T_35 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_36 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_37 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_38 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.param, UInt<1>(0h0)) node _out_1_c_bits_T_39 = or(_out_1_c_bits_T_35, _out_1_c_bits_T_36) node _out_1_c_bits_T_40 = or(_out_1_c_bits_T_39, _out_1_c_bits_T_37) node _out_1_c_bits_T_41 = or(_out_1_c_bits_T_40, _out_1_c_bits_T_38) wire _out_1_c_bits_WIRE_8 : UInt<3> connect _out_1_c_bits_WIRE_8, _out_1_c_bits_T_41 connect _out_1_c_bits_WIRE.param, _out_1_c_bits_WIRE_8 node _out_1_c_bits_T_42 = mux(muxState_2[0], portsCOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_43 = mux(muxState_2[1], portsCOI_filtered_2[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_44 = mux(muxState_2[2], portsCOI_filtered_3[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_45 = mux(muxState_2[3], portsCOI_filtered_4[1].bits.opcode, UInt<1>(0h0)) node _out_1_c_bits_T_46 = or(_out_1_c_bits_T_42, _out_1_c_bits_T_43) node _out_1_c_bits_T_47 = or(_out_1_c_bits_T_46, _out_1_c_bits_T_44) node _out_1_c_bits_T_48 = or(_out_1_c_bits_T_47, _out_1_c_bits_T_45) wire _out_1_c_bits_WIRE_9 : UInt<3> connect _out_1_c_bits_WIRE_9, _out_1_c_bits_T_48 connect _out_1_c_bits_WIRE.opcode, _out_1_c_bits_WIRE_9 connect out[1].c.bits.corrupt, _out_1_c_bits_WIRE.corrupt connect out[1].c.bits.data, _out_1_c_bits_WIRE.data connect out[1].c.bits.address, _out_1_c_bits_WIRE.address connect out[1].c.bits.source, _out_1_c_bits_WIRE.source connect out[1].c.bits.size, _out_1_c_bits_WIRE.size connect out[1].c.bits.param, _out_1_c_bits_WIRE.param connect out[1].c.bits.opcode, _out_1_c_bits_WIRE.opcode regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0) node idle_3 = eq(beatsLeft_3, UInt<1>(0h0)) node latch_3 = and(idle_3, out[1].e.ready) node readys_lo_3 = cat(portsEOI_filtered_2[1].valid, portsEOI_filtered_1[1].valid) node readys_hi_3 = cat(portsEOI_filtered_4[1].valid, portsEOI_filtered_3[1].valid) node _readys_T_38 = cat(readys_hi_3, readys_lo_3) node readys_valid_3 = bits(_readys_T_38, 3, 0) node _readys_T_39 = eq(readys_valid_3, _readys_T_38) node _readys_T_40 = asUInt(reset) node _readys_T_41 = eq(_readys_T_40, UInt<1>(0h0)) when _readys_T_41 : node _readys_T_42 = eq(_readys_T_39, UInt<1>(0h0)) when _readys_T_42 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3 assert(clock, _readys_T_39, UInt<1>(0h1), "") : readys_assert_3 regreset readys_mask_3 : UInt<4>, clock, reset, UInt<4>(0hf) node _readys_filter_T_6 = not(readys_mask_3) node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6) node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3) node _readys_unready_T_25 = shr(readys_filter_3, 1) node _readys_unready_T_26 = or(readys_filter_3, _readys_unready_T_25) node _readys_unready_T_27 = shr(_readys_unready_T_26, 2) node _readys_unready_T_28 = or(_readys_unready_T_26, _readys_unready_T_27) node _readys_unready_T_29 = bits(_readys_unready_T_28, 7, 0) node _readys_unready_T_30 = shr(_readys_unready_T_29, 1) node _readys_unready_T_31 = shl(readys_mask_3, 4) node readys_unready_3 = or(_readys_unready_T_30, _readys_unready_T_31) node _readys_readys_T_9 = shr(readys_unready_3, 4) node _readys_readys_T_10 = bits(readys_unready_3, 3, 0) node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10) node readys_readys_3 = not(_readys_readys_T_11) node _readys_T_43 = orr(readys_valid_3) node _readys_T_44 = and(latch_3, _readys_T_43) when _readys_T_44 : node _readys_mask_T_30 = and(readys_readys_3, readys_valid_3) node _readys_mask_T_31 = shl(_readys_mask_T_30, 1) node _readys_mask_T_32 = bits(_readys_mask_T_31, 3, 0) node _readys_mask_T_33 = or(_readys_mask_T_30, _readys_mask_T_32) node _readys_mask_T_34 = shl(_readys_mask_T_33, 2) node _readys_mask_T_35 = bits(_readys_mask_T_34, 3, 0) node _readys_mask_T_36 = or(_readys_mask_T_33, _readys_mask_T_35) node _readys_mask_T_37 = bits(_readys_mask_T_36, 3, 0) connect readys_mask_3, _readys_mask_T_37 node _readys_T_45 = bits(readys_readys_3, 3, 0) node _readys_T_46 = bits(_readys_T_45, 0, 0) node _readys_T_47 = bits(_readys_T_45, 1, 1) node _readys_T_48 = bits(_readys_T_45, 2, 2) node _readys_T_49 = bits(_readys_T_45, 3, 3) wire readys_3 : UInt<1>[4] connect readys_3[0], _readys_T_46 connect readys_3[1], _readys_T_47 connect readys_3[2], _readys_T_48 connect readys_3[3], _readys_T_49 node _winner_T_14 = and(readys_3[0], portsEOI_filtered_1[1].valid) node _winner_T_15 = and(readys_3[1], portsEOI_filtered_2[1].valid) node _winner_T_16 = and(readys_3[2], portsEOI_filtered_3[1].valid) node _winner_T_17 = and(readys_3[3], portsEOI_filtered_4[1].valid) wire winner_3 : UInt<1>[4] connect winner_3[0], _winner_T_14 connect winner_3[1], _winner_T_15 connect winner_3[2], _winner_T_16 connect winner_3[3], _winner_T_17 node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0]) node prefixOR_2_3 = or(prefixOR_1_3, winner_3[1]) node prefixOR_3_3 = or(prefixOR_2_3, winner_3[2]) node _prefixOR_T_3 = or(prefixOR_3_3, winner_3[3]) node _T_99 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_100 = eq(winner_3[0], UInt<1>(0h0)) node _T_101 = or(_T_99, _T_100) node _T_102 = eq(prefixOR_1_3, UInt<1>(0h0)) node _T_103 = eq(winner_3[1], UInt<1>(0h0)) node _T_104 = or(_T_102, _T_103) node _T_105 = eq(prefixOR_2_3, UInt<1>(0h0)) node _T_106 = eq(winner_3[2], UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) node _T_108 = eq(prefixOR_3_3, UInt<1>(0h0)) node _T_109 = eq(winner_3[3], UInt<1>(0h0)) node _T_110 = or(_T_108, _T_109) node _T_111 = and(_T_101, _T_104) node _T_112 = and(_T_111, _T_107) node _T_113 = and(_T_112, _T_110) node _T_114 = asUInt(reset) node _T_115 = eq(_T_114, UInt<1>(0h0)) when _T_115 : node _T_116 = eq(_T_113, UInt<1>(0h0)) when _T_116 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6 assert(clock, _T_113, UInt<1>(0h1), "") : assert_6 node _T_117 = or(portsEOI_filtered_1[1].valid, portsEOI_filtered_2[1].valid) node _T_118 = or(_T_117, portsEOI_filtered_3[1].valid) node _T_119 = or(_T_118, portsEOI_filtered_4[1].valid) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = or(winner_3[0], winner_3[1]) node _T_122 = or(_T_121, winner_3[2]) node _T_123 = or(_T_122, winner_3[3]) node _T_124 = or(_T_120, _T_123) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7 assert(clock, _T_124, UInt<1>(0h1), "") : assert_7 node maskedBeats_0_3 = mux(winner_3[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1_3 = mux(winner_3[1], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_2_3 = mux(winner_3[2], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_3_3 = mux(winner_3[3], UInt<1>(0h0), UInt<1>(0h0)) node _initBeats_T_8 = or(maskedBeats_0_3, maskedBeats_1_3) node _initBeats_T_9 = or(_initBeats_T_8, maskedBeats_2_3) node initBeats_3 = or(_initBeats_T_9, maskedBeats_3_3) node _beatsLeft_T_12 = and(out[1].e.ready, out[1].e.valid) node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12) node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1) node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14) connect beatsLeft_3, _beatsLeft_T_15 wire _state_WIRE_3 : UInt<1>[4] connect _state_WIRE_3[0], UInt<1>(0h0) connect _state_WIRE_3[1], UInt<1>(0h0) connect _state_WIRE_3[2], UInt<1>(0h0) connect _state_WIRE_3[3], UInt<1>(0h0) regreset state_3 : UInt<1>[4], clock, reset, _state_WIRE_3 node muxState_3 = mux(idle_3, winner_3, state_3) connect state_3, muxState_3 node allowed_3 = mux(idle_3, readys_3, state_3) node _filtered_1_ready_T_9 = and(out[1].e.ready, allowed_3[0]) connect portsEOI_filtered_1[1].ready, _filtered_1_ready_T_9 node _filtered_1_ready_T_10 = and(out[1].e.ready, allowed_3[1]) connect portsEOI_filtered_2[1].ready, _filtered_1_ready_T_10 node _filtered_1_ready_T_11 = and(out[1].e.ready, allowed_3[2]) connect portsEOI_filtered_3[1].ready, _filtered_1_ready_T_11 node _filtered_1_ready_T_12 = and(out[1].e.ready, allowed_3[3]) connect portsEOI_filtered_4[1].ready, _filtered_1_ready_T_12 node _out_1_e_valid_T = or(portsEOI_filtered_1[1].valid, portsEOI_filtered_2[1].valid) node _out_1_e_valid_T_1 = or(_out_1_e_valid_T, portsEOI_filtered_3[1].valid) node _out_1_e_valid_T_2 = or(_out_1_e_valid_T_1, portsEOI_filtered_4[1].valid) node _out_1_e_valid_T_3 = mux(state_3[0], portsEOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_4 = mux(state_3[1], portsEOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_5 = mux(state_3[2], portsEOI_filtered_3[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_6 = mux(state_3[3], portsEOI_filtered_4[1].valid, UInt<1>(0h0)) node _out_1_e_valid_T_7 = or(_out_1_e_valid_T_3, _out_1_e_valid_T_4) node _out_1_e_valid_T_8 = or(_out_1_e_valid_T_7, _out_1_e_valid_T_5) node _out_1_e_valid_T_9 = or(_out_1_e_valid_T_8, _out_1_e_valid_T_6) wire _out_1_e_valid_WIRE : UInt<1> connect _out_1_e_valid_WIRE, _out_1_e_valid_T_9 node _out_1_e_valid_T_10 = mux(idle_3, _out_1_e_valid_T_2, _out_1_e_valid_WIRE) connect out[1].e.valid, _out_1_e_valid_T_10 wire _out_1_e_bits_WIRE : { sink : UInt<4>} node _out_1_e_bits_T = mux(muxState_3[0], portsEOI_filtered_1[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_1 = mux(muxState_3[1], portsEOI_filtered_2[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_2 = mux(muxState_3[2], portsEOI_filtered_3[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_3 = mux(muxState_3[3], portsEOI_filtered_4[1].bits.sink, UInt<1>(0h0)) node _out_1_e_bits_T_4 = or(_out_1_e_bits_T, _out_1_e_bits_T_1) node _out_1_e_bits_T_5 = or(_out_1_e_bits_T_4, _out_1_e_bits_T_2) node _out_1_e_bits_T_6 = or(_out_1_e_bits_T_5, _out_1_e_bits_T_3) wire _out_1_e_bits_WIRE_1 : UInt<4> connect _out_1_e_bits_WIRE_1, _out_1_e_bits_T_6 connect _out_1_e_bits_WIRE.sink, _out_1_e_bits_WIRE_1 connect out[1].e.bits.sink, _out_1_e_bits_WIRE.sink connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0) node idle_4 = eq(beatsLeft_4, UInt<1>(0h0)) node latch_4 = and(idle_4, in[0].d.ready) node _readys_T_50 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid_4 = bits(_readys_T_50, 1, 0) node _readys_T_51 = eq(readys_valid_4, _readys_T_50) node _readys_T_52 = asUInt(reset) node _readys_T_53 = eq(_readys_T_52, UInt<1>(0h0)) when _readys_T_53 : node _readys_T_54 = eq(_readys_T_51, UInt<1>(0h0)) when _readys_T_54 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_4 assert(clock, _readys_T_51, UInt<1>(0h1), "") : readys_assert_4 regreset readys_mask_4 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_8 = not(readys_mask_4) node _readys_filter_T_9 = and(readys_valid_4, _readys_filter_T_8) node readys_filter_4 = cat(_readys_filter_T_9, readys_valid_4) node _readys_unready_T_32 = shr(readys_filter_4, 1) node _readys_unready_T_33 = or(readys_filter_4, _readys_unready_T_32) node _readys_unready_T_34 = bits(_readys_unready_T_33, 3, 0) node _readys_unready_T_35 = shr(_readys_unready_T_34, 1) node _readys_unready_T_36 = shl(readys_mask_4, 2) node readys_unready_4 = or(_readys_unready_T_35, _readys_unready_T_36) node _readys_readys_T_12 = shr(readys_unready_4, 2) node _readys_readys_T_13 = bits(readys_unready_4, 1, 0) node _readys_readys_T_14 = and(_readys_readys_T_12, _readys_readys_T_13) node readys_readys_4 = not(_readys_readys_T_14) node _readys_T_55 = orr(readys_valid_4) node _readys_T_56 = and(latch_4, _readys_T_55) when _readys_T_56 : node _readys_mask_T_38 = and(readys_readys_4, readys_valid_4) node _readys_mask_T_39 = shl(_readys_mask_T_38, 1) node _readys_mask_T_40 = bits(_readys_mask_T_39, 1, 0) node _readys_mask_T_41 = or(_readys_mask_T_38, _readys_mask_T_40) node _readys_mask_T_42 = bits(_readys_mask_T_41, 1, 0) connect readys_mask_4, _readys_mask_T_42 node _readys_T_57 = bits(readys_readys_4, 1, 0) node _readys_T_58 = bits(_readys_T_57, 0, 0) node _readys_T_59 = bits(_readys_T_57, 1, 1) wire readys_4 : UInt<1>[2] connect readys_4[0], _readys_T_58 connect readys_4[1], _readys_T_59 node _winner_T_18 = and(readys_4[0], portsDIO_filtered[0].valid) node _winner_T_19 = and(readys_4[1], portsDIO_filtered_1[0].valid) wire winner_4 : UInt<1>[2] connect winner_4[0], _winner_T_18 connect winner_4[1], _winner_T_19 node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0]) node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1]) node _T_128 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = eq(winner_4[0], UInt<1>(0h0)) node _T_130 = or(_T_128, _T_129) node _T_131 = eq(prefixOR_1_4, UInt<1>(0h0)) node _T_132 = eq(winner_4[1], UInt<1>(0h0)) node _T_133 = or(_T_131, _T_132) node _T_134 = and(_T_130, _T_133) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8 assert(clock, _T_134, UInt<1>(0h1), "") : assert_8 node _T_138 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_139 = eq(_T_138, UInt<1>(0h0)) node _T_140 = or(winner_4[0], winner_4[1]) node _T_141 = or(_T_139, _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9 assert(clock, _T_141, UInt<1>(0h1), "") : assert_9 node maskedBeats_0_4 = mux(winner_4[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_4 = mux(winner_4[1], beatsDO_1, UInt<1>(0h0)) node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4) node _beatsLeft_T_16 = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16) node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1) node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18) connect beatsLeft_4, _beatsLeft_T_19 wire _state_WIRE_4 : UInt<1>[2] connect _state_WIRE_4[0], UInt<1>(0h0) connect _state_WIRE_4[1], UInt<1>(0h0) regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4 node muxState_4 = mux(idle_4, winner_4, state_4) connect state_4, muxState_4 node allowed_4 = mux(idle_4, readys_4, state_4) node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed_4[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T_5 node _filtered_0_ready_T_6 = and(in[0].d.ready, allowed_4[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_6 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state_4[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state_4[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle_4, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState_4[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState_4[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<128> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState_4[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState_4[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<4> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState_4[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<7> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState_4[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState_4[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState_4[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState_4[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) connect in[1].b, portsBIO_filtered_1[1] regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0) node idle_5 = eq(beatsLeft_5, UInt<1>(0h0)) node latch_5 = and(idle_5, in[1].d.ready) node _readys_T_60 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid) node readys_valid_5 = bits(_readys_T_60, 1, 0) node _readys_T_61 = eq(readys_valid_5, _readys_T_60) node _readys_T_62 = asUInt(reset) node _readys_T_63 = eq(_readys_T_62, UInt<1>(0h0)) when _readys_T_63 : node _readys_T_64 = eq(_readys_T_61, UInt<1>(0h0)) when _readys_T_64 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_5 assert(clock, _readys_T_61, UInt<1>(0h1), "") : readys_assert_5 regreset readys_mask_5 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_10 = not(readys_mask_5) node _readys_filter_T_11 = and(readys_valid_5, _readys_filter_T_10) node readys_filter_5 = cat(_readys_filter_T_11, readys_valid_5) node _readys_unready_T_37 = shr(readys_filter_5, 1) node _readys_unready_T_38 = or(readys_filter_5, _readys_unready_T_37) node _readys_unready_T_39 = bits(_readys_unready_T_38, 3, 0) node _readys_unready_T_40 = shr(_readys_unready_T_39, 1) node _readys_unready_T_41 = shl(readys_mask_5, 2) node readys_unready_5 = or(_readys_unready_T_40, _readys_unready_T_41) node _readys_readys_T_15 = shr(readys_unready_5, 2) node _readys_readys_T_16 = bits(readys_unready_5, 1, 0) node _readys_readys_T_17 = and(_readys_readys_T_15, _readys_readys_T_16) node readys_readys_5 = not(_readys_readys_T_17) node _readys_T_65 = orr(readys_valid_5) node _readys_T_66 = and(latch_5, _readys_T_65) when _readys_T_66 : node _readys_mask_T_43 = and(readys_readys_5, readys_valid_5) node _readys_mask_T_44 = shl(_readys_mask_T_43, 1) node _readys_mask_T_45 = bits(_readys_mask_T_44, 1, 0) node _readys_mask_T_46 = or(_readys_mask_T_43, _readys_mask_T_45) node _readys_mask_T_47 = bits(_readys_mask_T_46, 1, 0) connect readys_mask_5, _readys_mask_T_47 node _readys_T_67 = bits(readys_readys_5, 1, 0) node _readys_T_68 = bits(_readys_T_67, 0, 0) node _readys_T_69 = bits(_readys_T_67, 1, 1) wire readys_5 : UInt<1>[2] connect readys_5[0], _readys_T_68 connect readys_5[1], _readys_T_69 node _winner_T_20 = and(readys_5[0], portsDIO_filtered[1].valid) node _winner_T_21 = and(readys_5[1], portsDIO_filtered_1[1].valid) wire winner_5 : UInt<1>[2] connect winner_5[0], _winner_T_20 connect winner_5[1], _winner_T_21 node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0]) node _prefixOR_T_5 = or(prefixOR_1_5, winner_5[1]) node _T_145 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_146 = eq(winner_5[0], UInt<1>(0h0)) node _T_147 = or(_T_145, _T_146) node _T_148 = eq(prefixOR_1_5, UInt<1>(0h0)) node _T_149 = eq(winner_5[1], UInt<1>(0h0)) node _T_150 = or(_T_148, _T_149) node _T_151 = and(_T_147, _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_10 assert(clock, _T_151, UInt<1>(0h1), "") : assert_10 node _T_155 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _T_156 = eq(_T_155, UInt<1>(0h0)) node _T_157 = or(winner_5[0], winner_5[1]) node _T_158 = or(_T_156, _T_157) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_11 assert(clock, _T_158, UInt<1>(0h1), "") : assert_11 node maskedBeats_0_5 = mux(winner_5[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_5 = mux(winner_5[1], beatsDO_1, UInt<1>(0h0)) node initBeats_5 = or(maskedBeats_0_5, maskedBeats_1_5) node _beatsLeft_T_20 = and(in[1].d.ready, in[1].d.valid) node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20) node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1) node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22) connect beatsLeft_5, _beatsLeft_T_23 wire _state_WIRE_5 : UInt<1>[2] connect _state_WIRE_5[0], UInt<1>(0h0) connect _state_WIRE_5[1], UInt<1>(0h0) regreset state_5 : UInt<1>[2], clock, reset, _state_WIRE_5 node muxState_5 = mux(idle_5, winner_5, state_5) connect state_5, muxState_5 node allowed_5 = mux(idle_5, readys_5, state_5) node _filtered_1_ready_T_13 = and(in[1].d.ready, allowed_5[0]) connect portsDIO_filtered[1].ready, _filtered_1_ready_T_13 node _filtered_1_ready_T_14 = and(in[1].d.ready, allowed_5[1]) connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_14 node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _in_1_d_valid_T_1 = mux(state_5[0], portsDIO_filtered[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_2 = mux(state_5[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2) wire _in_1_d_valid_WIRE : UInt<1> connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3 node _in_1_d_valid_T_4 = mux(idle_5, _in_1_d_valid_T, _in_1_d_valid_WIRE) connect in[1].d.valid, _in_1_d_valid_T_4 wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_1_d_bits_T = mux(muxState_5[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_1 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1) wire _in_1_d_bits_WIRE_1 : UInt<1> connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2 connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1 node _in_1_d_bits_T_3 = mux(muxState_5[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_4 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4) wire _in_1_d_bits_WIRE_2 : UInt<128> connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5 connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2 wire _in_1_d_bits_WIRE_3 : { } connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3 wire _in_1_d_bits_WIRE_4 : { } connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4 node _in_1_d_bits_T_6 = mux(muxState_5[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_7 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7) wire _in_1_d_bits_WIRE_5 : UInt<1> connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8 connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5 node _in_1_d_bits_T_9 = mux(muxState_5[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_10 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10) wire _in_1_d_bits_WIRE_6 : UInt<4> connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11 connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6 node _in_1_d_bits_T_12 = mux(muxState_5[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_13 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13) wire _in_1_d_bits_WIRE_7 : UInt<7> connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14 connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7 node _in_1_d_bits_T_15 = mux(muxState_5[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_16 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16) wire _in_1_d_bits_WIRE_8 : UInt<4> connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17 connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8 node _in_1_d_bits_T_18 = mux(muxState_5[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_19 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19) wire _in_1_d_bits_WIRE_9 : UInt<2> connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20 connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9 node _in_1_d_bits_T_21 = mux(muxState_5[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_22 = mux(muxState_5[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22) wire _in_1_d_bits_WIRE_10 : UInt<3> connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23 connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10 connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt connect in[1].d.bits.data, _in_1_d_bits_WIRE.data connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink connect in[1].d.bits.source, _in_1_d_bits_WIRE.source connect in[1].d.bits.size, _in_1_d_bits_WIRE.size connect in[1].d.bits.param, _in_1_d_bits_WIRE.param connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode connect portsBIO_filtered[1].ready, UInt<1>(0h0) connect in[2].b, portsBIO_filtered_1[2] regreset beatsLeft_6 : UInt, clock, reset, UInt<1>(0h0) node idle_6 = eq(beatsLeft_6, UInt<1>(0h0)) node latch_6 = and(idle_6, in[2].d.ready) node _readys_T_70 = cat(portsDIO_filtered_1[2].valid, portsDIO_filtered[2].valid) node readys_valid_6 = bits(_readys_T_70, 1, 0) node _readys_T_71 = eq(readys_valid_6, _readys_T_70) node _readys_T_72 = asUInt(reset) node _readys_T_73 = eq(_readys_T_72, UInt<1>(0h0)) when _readys_T_73 : node _readys_T_74 = eq(_readys_T_71, UInt<1>(0h0)) when _readys_T_74 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_6 assert(clock, _readys_T_71, UInt<1>(0h1), "") : readys_assert_6 regreset readys_mask_6 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_12 = not(readys_mask_6) node _readys_filter_T_13 = and(readys_valid_6, _readys_filter_T_12) node readys_filter_6 = cat(_readys_filter_T_13, readys_valid_6) node _readys_unready_T_42 = shr(readys_filter_6, 1) node _readys_unready_T_43 = or(readys_filter_6, _readys_unready_T_42) node _readys_unready_T_44 = bits(_readys_unready_T_43, 3, 0) node _readys_unready_T_45 = shr(_readys_unready_T_44, 1) node _readys_unready_T_46 = shl(readys_mask_6, 2) node readys_unready_6 = or(_readys_unready_T_45, _readys_unready_T_46) node _readys_readys_T_18 = shr(readys_unready_6, 2) node _readys_readys_T_19 = bits(readys_unready_6, 1, 0) node _readys_readys_T_20 = and(_readys_readys_T_18, _readys_readys_T_19) node readys_readys_6 = not(_readys_readys_T_20) node _readys_T_75 = orr(readys_valid_6) node _readys_T_76 = and(latch_6, _readys_T_75) when _readys_T_76 : node _readys_mask_T_48 = and(readys_readys_6, readys_valid_6) node _readys_mask_T_49 = shl(_readys_mask_T_48, 1) node _readys_mask_T_50 = bits(_readys_mask_T_49, 1, 0) node _readys_mask_T_51 = or(_readys_mask_T_48, _readys_mask_T_50) node _readys_mask_T_52 = bits(_readys_mask_T_51, 1, 0) connect readys_mask_6, _readys_mask_T_52 node _readys_T_77 = bits(readys_readys_6, 1, 0) node _readys_T_78 = bits(_readys_T_77, 0, 0) node _readys_T_79 = bits(_readys_T_77, 1, 1) wire readys_6 : UInt<1>[2] connect readys_6[0], _readys_T_78 connect readys_6[1], _readys_T_79 node _winner_T_22 = and(readys_6[0], portsDIO_filtered[2].valid) node _winner_T_23 = and(readys_6[1], portsDIO_filtered_1[2].valid) wire winner_6 : UInt<1>[2] connect winner_6[0], _winner_T_22 connect winner_6[1], _winner_T_23 node prefixOR_1_6 = or(UInt<1>(0h0), winner_6[0]) node _prefixOR_T_6 = or(prefixOR_1_6, winner_6[1]) node _T_162 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_163 = eq(winner_6[0], UInt<1>(0h0)) node _T_164 = or(_T_162, _T_163) node _T_165 = eq(prefixOR_1_6, UInt<1>(0h0)) node _T_166 = eq(winner_6[1], UInt<1>(0h0)) node _T_167 = or(_T_165, _T_166) node _T_168 = and(_T_164, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_12 assert(clock, _T_168, UInt<1>(0h1), "") : assert_12 node _T_172 = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = or(winner_6[0], winner_6[1]) node _T_175 = or(_T_173, _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_13 assert(clock, _T_175, UInt<1>(0h1), "") : assert_13 node maskedBeats_0_6 = mux(winner_6[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_6 = mux(winner_6[1], beatsDO_1, UInt<1>(0h0)) node initBeats_6 = or(maskedBeats_0_6, maskedBeats_1_6) node _beatsLeft_T_24 = and(in[2].d.ready, in[2].d.valid) node _beatsLeft_T_25 = sub(beatsLeft_6, _beatsLeft_T_24) node _beatsLeft_T_26 = tail(_beatsLeft_T_25, 1) node _beatsLeft_T_27 = mux(latch_6, initBeats_6, _beatsLeft_T_26) connect beatsLeft_6, _beatsLeft_T_27 wire _state_WIRE_6 : UInt<1>[2] connect _state_WIRE_6[0], UInt<1>(0h0) connect _state_WIRE_6[1], UInt<1>(0h0) regreset state_6 : UInt<1>[2], clock, reset, _state_WIRE_6 node muxState_6 = mux(idle_6, winner_6, state_6) connect state_6, muxState_6 node allowed_6 = mux(idle_6, readys_6, state_6) node _filtered_2_ready_T = and(in[2].d.ready, allowed_6[0]) connect portsDIO_filtered[2].ready, _filtered_2_ready_T node _filtered_2_ready_T_1 = and(in[2].d.ready, allowed_6[1]) connect portsDIO_filtered_1[2].ready, _filtered_2_ready_T_1 node _in_2_d_valid_T = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _in_2_d_valid_T_1 = mux(state_6[0], portsDIO_filtered[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_2 = mux(state_6[1], portsDIO_filtered_1[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_3 = or(_in_2_d_valid_T_1, _in_2_d_valid_T_2) wire _in_2_d_valid_WIRE : UInt<1> connect _in_2_d_valid_WIRE, _in_2_d_valid_T_3 node _in_2_d_valid_T_4 = mux(idle_6, _in_2_d_valid_T, _in_2_d_valid_WIRE) connect in[2].d.valid, _in_2_d_valid_T_4 wire _in_2_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_2_d_bits_T = mux(muxState_6[0], portsDIO_filtered[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_1 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_2 = or(_in_2_d_bits_T, _in_2_d_bits_T_1) wire _in_2_d_bits_WIRE_1 : UInt<1> connect _in_2_d_bits_WIRE_1, _in_2_d_bits_T_2 connect _in_2_d_bits_WIRE.corrupt, _in_2_d_bits_WIRE_1 node _in_2_d_bits_T_3 = mux(muxState_6[0], portsDIO_filtered[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_4 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_5 = or(_in_2_d_bits_T_3, _in_2_d_bits_T_4) wire _in_2_d_bits_WIRE_2 : UInt<128> connect _in_2_d_bits_WIRE_2, _in_2_d_bits_T_5 connect _in_2_d_bits_WIRE.data, _in_2_d_bits_WIRE_2 wire _in_2_d_bits_WIRE_3 : { } connect _in_2_d_bits_WIRE.echo, _in_2_d_bits_WIRE_3 wire _in_2_d_bits_WIRE_4 : { } connect _in_2_d_bits_WIRE.user, _in_2_d_bits_WIRE_4 node _in_2_d_bits_T_6 = mux(muxState_6[0], portsDIO_filtered[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_7 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_8 = or(_in_2_d_bits_T_6, _in_2_d_bits_T_7) wire _in_2_d_bits_WIRE_5 : UInt<1> connect _in_2_d_bits_WIRE_5, _in_2_d_bits_T_8 connect _in_2_d_bits_WIRE.denied, _in_2_d_bits_WIRE_5 node _in_2_d_bits_T_9 = mux(muxState_6[0], portsDIO_filtered[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_10 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_11 = or(_in_2_d_bits_T_9, _in_2_d_bits_T_10) wire _in_2_d_bits_WIRE_6 : UInt<4> connect _in_2_d_bits_WIRE_6, _in_2_d_bits_T_11 connect _in_2_d_bits_WIRE.sink, _in_2_d_bits_WIRE_6 node _in_2_d_bits_T_12 = mux(muxState_6[0], portsDIO_filtered[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_13 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_14 = or(_in_2_d_bits_T_12, _in_2_d_bits_T_13) wire _in_2_d_bits_WIRE_7 : UInt<7> connect _in_2_d_bits_WIRE_7, _in_2_d_bits_T_14 connect _in_2_d_bits_WIRE.source, _in_2_d_bits_WIRE_7 node _in_2_d_bits_T_15 = mux(muxState_6[0], portsDIO_filtered[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_16 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_17 = or(_in_2_d_bits_T_15, _in_2_d_bits_T_16) wire _in_2_d_bits_WIRE_8 : UInt<4> connect _in_2_d_bits_WIRE_8, _in_2_d_bits_T_17 connect _in_2_d_bits_WIRE.size, _in_2_d_bits_WIRE_8 node _in_2_d_bits_T_18 = mux(muxState_6[0], portsDIO_filtered[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_19 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_20 = or(_in_2_d_bits_T_18, _in_2_d_bits_T_19) wire _in_2_d_bits_WIRE_9 : UInt<2> connect _in_2_d_bits_WIRE_9, _in_2_d_bits_T_20 connect _in_2_d_bits_WIRE.param, _in_2_d_bits_WIRE_9 node _in_2_d_bits_T_21 = mux(muxState_6[0], portsDIO_filtered[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_22 = mux(muxState_6[1], portsDIO_filtered_1[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_23 = or(_in_2_d_bits_T_21, _in_2_d_bits_T_22) wire _in_2_d_bits_WIRE_10 : UInt<3> connect _in_2_d_bits_WIRE_10, _in_2_d_bits_T_23 connect _in_2_d_bits_WIRE.opcode, _in_2_d_bits_WIRE_10 connect in[2].d.bits.corrupt, _in_2_d_bits_WIRE.corrupt connect in[2].d.bits.data, _in_2_d_bits_WIRE.data connect in[2].d.bits.denied, _in_2_d_bits_WIRE.denied connect in[2].d.bits.sink, _in_2_d_bits_WIRE.sink connect in[2].d.bits.source, _in_2_d_bits_WIRE.source connect in[2].d.bits.size, _in_2_d_bits_WIRE.size connect in[2].d.bits.param, _in_2_d_bits_WIRE.param connect in[2].d.bits.opcode, _in_2_d_bits_WIRE.opcode connect portsBIO_filtered[2].ready, UInt<1>(0h0) connect in[3].b, portsBIO_filtered_1[3] regreset beatsLeft_7 : UInt, clock, reset, UInt<1>(0h0) node idle_7 = eq(beatsLeft_7, UInt<1>(0h0)) node latch_7 = and(idle_7, in[3].d.ready) node _readys_T_80 = cat(portsDIO_filtered_1[3].valid, portsDIO_filtered[3].valid) node readys_valid_7 = bits(_readys_T_80, 1, 0) node _readys_T_81 = eq(readys_valid_7, _readys_T_80) node _readys_T_82 = asUInt(reset) node _readys_T_83 = eq(_readys_T_82, UInt<1>(0h0)) when _readys_T_83 : node _readys_T_84 = eq(_readys_T_81, UInt<1>(0h0)) when _readys_T_84 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_7 assert(clock, _readys_T_81, UInt<1>(0h1), "") : readys_assert_7 regreset readys_mask_7 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_14 = not(readys_mask_7) node _readys_filter_T_15 = and(readys_valid_7, _readys_filter_T_14) node readys_filter_7 = cat(_readys_filter_T_15, readys_valid_7) node _readys_unready_T_47 = shr(readys_filter_7, 1) node _readys_unready_T_48 = or(readys_filter_7, _readys_unready_T_47) node _readys_unready_T_49 = bits(_readys_unready_T_48, 3, 0) node _readys_unready_T_50 = shr(_readys_unready_T_49, 1) node _readys_unready_T_51 = shl(readys_mask_7, 2) node readys_unready_7 = or(_readys_unready_T_50, _readys_unready_T_51) node _readys_readys_T_21 = shr(readys_unready_7, 2) node _readys_readys_T_22 = bits(readys_unready_7, 1, 0) node _readys_readys_T_23 = and(_readys_readys_T_21, _readys_readys_T_22) node readys_readys_7 = not(_readys_readys_T_23) node _readys_T_85 = orr(readys_valid_7) node _readys_T_86 = and(latch_7, _readys_T_85) when _readys_T_86 : node _readys_mask_T_53 = and(readys_readys_7, readys_valid_7) node _readys_mask_T_54 = shl(_readys_mask_T_53, 1) node _readys_mask_T_55 = bits(_readys_mask_T_54, 1, 0) node _readys_mask_T_56 = or(_readys_mask_T_53, _readys_mask_T_55) node _readys_mask_T_57 = bits(_readys_mask_T_56, 1, 0) connect readys_mask_7, _readys_mask_T_57 node _readys_T_87 = bits(readys_readys_7, 1, 0) node _readys_T_88 = bits(_readys_T_87, 0, 0) node _readys_T_89 = bits(_readys_T_87, 1, 1) wire readys_7 : UInt<1>[2] connect readys_7[0], _readys_T_88 connect readys_7[1], _readys_T_89 node _winner_T_24 = and(readys_7[0], portsDIO_filtered[3].valid) node _winner_T_25 = and(readys_7[1], portsDIO_filtered_1[3].valid) wire winner_7 : UInt<1>[2] connect winner_7[0], _winner_T_24 connect winner_7[1], _winner_T_25 node prefixOR_1_7 = or(UInt<1>(0h0), winner_7[0]) node _prefixOR_T_7 = or(prefixOR_1_7, winner_7[1]) node _T_179 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_180 = eq(winner_7[0], UInt<1>(0h0)) node _T_181 = or(_T_179, _T_180) node _T_182 = eq(prefixOR_1_7, UInt<1>(0h0)) node _T_183 = eq(winner_7[1], UInt<1>(0h0)) node _T_184 = or(_T_182, _T_183) node _T_185 = and(_T_181, _T_184) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_14 assert(clock, _T_185, UInt<1>(0h1), "") : assert_14 node _T_189 = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = or(winner_7[0], winner_7[1]) node _T_192 = or(_T_190, _T_191) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_15 assert(clock, _T_192, UInt<1>(0h1), "") : assert_15 node maskedBeats_0_7 = mux(winner_7[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_7 = mux(winner_7[1], beatsDO_1, UInt<1>(0h0)) node initBeats_7 = or(maskedBeats_0_7, maskedBeats_1_7) node _beatsLeft_T_28 = and(in[3].d.ready, in[3].d.valid) node _beatsLeft_T_29 = sub(beatsLeft_7, _beatsLeft_T_28) node _beatsLeft_T_30 = tail(_beatsLeft_T_29, 1) node _beatsLeft_T_31 = mux(latch_7, initBeats_7, _beatsLeft_T_30) connect beatsLeft_7, _beatsLeft_T_31 wire _state_WIRE_7 : UInt<1>[2] connect _state_WIRE_7[0], UInt<1>(0h0) connect _state_WIRE_7[1], UInt<1>(0h0) regreset state_7 : UInt<1>[2], clock, reset, _state_WIRE_7 node muxState_7 = mux(idle_7, winner_7, state_7) connect state_7, muxState_7 node allowed_7 = mux(idle_7, readys_7, state_7) node _filtered_3_ready_T = and(in[3].d.ready, allowed_7[0]) connect portsDIO_filtered[3].ready, _filtered_3_ready_T node _filtered_3_ready_T_1 = and(in[3].d.ready, allowed_7[1]) connect portsDIO_filtered_1[3].ready, _filtered_3_ready_T_1 node _in_3_d_valid_T = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid) node _in_3_d_valid_T_1 = mux(state_7[0], portsDIO_filtered[3].valid, UInt<1>(0h0)) node _in_3_d_valid_T_2 = mux(state_7[1], portsDIO_filtered_1[3].valid, UInt<1>(0h0)) node _in_3_d_valid_T_3 = or(_in_3_d_valid_T_1, _in_3_d_valid_T_2) wire _in_3_d_valid_WIRE : UInt<1> connect _in_3_d_valid_WIRE, _in_3_d_valid_T_3 node _in_3_d_valid_T_4 = mux(idle_7, _in_3_d_valid_T, _in_3_d_valid_WIRE) connect in[3].d.valid, _in_3_d_valid_T_4 wire _in_3_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_3_d_bits_T = mux(muxState_7[0], portsDIO_filtered[3].bits.corrupt, UInt<1>(0h0)) node _in_3_d_bits_T_1 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.corrupt, UInt<1>(0h0)) node _in_3_d_bits_T_2 = or(_in_3_d_bits_T, _in_3_d_bits_T_1) wire _in_3_d_bits_WIRE_1 : UInt<1> connect _in_3_d_bits_WIRE_1, _in_3_d_bits_T_2 connect _in_3_d_bits_WIRE.corrupt, _in_3_d_bits_WIRE_1 node _in_3_d_bits_T_3 = mux(muxState_7[0], portsDIO_filtered[3].bits.data, UInt<1>(0h0)) node _in_3_d_bits_T_4 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.data, UInt<1>(0h0)) node _in_3_d_bits_T_5 = or(_in_3_d_bits_T_3, _in_3_d_bits_T_4) wire _in_3_d_bits_WIRE_2 : UInt<128> connect _in_3_d_bits_WIRE_2, _in_3_d_bits_T_5 connect _in_3_d_bits_WIRE.data, _in_3_d_bits_WIRE_2 wire _in_3_d_bits_WIRE_3 : { } connect _in_3_d_bits_WIRE.echo, _in_3_d_bits_WIRE_3 wire _in_3_d_bits_WIRE_4 : { } connect _in_3_d_bits_WIRE.user, _in_3_d_bits_WIRE_4 node _in_3_d_bits_T_6 = mux(muxState_7[0], portsDIO_filtered[3].bits.denied, UInt<1>(0h0)) node _in_3_d_bits_T_7 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.denied, UInt<1>(0h0)) node _in_3_d_bits_T_8 = or(_in_3_d_bits_T_6, _in_3_d_bits_T_7) wire _in_3_d_bits_WIRE_5 : UInt<1> connect _in_3_d_bits_WIRE_5, _in_3_d_bits_T_8 connect _in_3_d_bits_WIRE.denied, _in_3_d_bits_WIRE_5 node _in_3_d_bits_T_9 = mux(muxState_7[0], portsDIO_filtered[3].bits.sink, UInt<1>(0h0)) node _in_3_d_bits_T_10 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.sink, UInt<1>(0h0)) node _in_3_d_bits_T_11 = or(_in_3_d_bits_T_9, _in_3_d_bits_T_10) wire _in_3_d_bits_WIRE_6 : UInt<4> connect _in_3_d_bits_WIRE_6, _in_3_d_bits_T_11 connect _in_3_d_bits_WIRE.sink, _in_3_d_bits_WIRE_6 node _in_3_d_bits_T_12 = mux(muxState_7[0], portsDIO_filtered[3].bits.source, UInt<1>(0h0)) node _in_3_d_bits_T_13 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.source, UInt<1>(0h0)) node _in_3_d_bits_T_14 = or(_in_3_d_bits_T_12, _in_3_d_bits_T_13) wire _in_3_d_bits_WIRE_7 : UInt<7> connect _in_3_d_bits_WIRE_7, _in_3_d_bits_T_14 connect _in_3_d_bits_WIRE.source, _in_3_d_bits_WIRE_7 node _in_3_d_bits_T_15 = mux(muxState_7[0], portsDIO_filtered[3].bits.size, UInt<1>(0h0)) node _in_3_d_bits_T_16 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.size, UInt<1>(0h0)) node _in_3_d_bits_T_17 = or(_in_3_d_bits_T_15, _in_3_d_bits_T_16) wire _in_3_d_bits_WIRE_8 : UInt<4> connect _in_3_d_bits_WIRE_8, _in_3_d_bits_T_17 connect _in_3_d_bits_WIRE.size, _in_3_d_bits_WIRE_8 node _in_3_d_bits_T_18 = mux(muxState_7[0], portsDIO_filtered[3].bits.param, UInt<1>(0h0)) node _in_3_d_bits_T_19 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.param, UInt<1>(0h0)) node _in_3_d_bits_T_20 = or(_in_3_d_bits_T_18, _in_3_d_bits_T_19) wire _in_3_d_bits_WIRE_9 : UInt<2> connect _in_3_d_bits_WIRE_9, _in_3_d_bits_T_20 connect _in_3_d_bits_WIRE.param, _in_3_d_bits_WIRE_9 node _in_3_d_bits_T_21 = mux(muxState_7[0], portsDIO_filtered[3].bits.opcode, UInt<1>(0h0)) node _in_3_d_bits_T_22 = mux(muxState_7[1], portsDIO_filtered_1[3].bits.opcode, UInt<1>(0h0)) node _in_3_d_bits_T_23 = or(_in_3_d_bits_T_21, _in_3_d_bits_T_22) wire _in_3_d_bits_WIRE_10 : UInt<3> connect _in_3_d_bits_WIRE_10, _in_3_d_bits_T_23 connect _in_3_d_bits_WIRE.opcode, _in_3_d_bits_WIRE_10 connect in[3].d.bits.corrupt, _in_3_d_bits_WIRE.corrupt connect in[3].d.bits.data, _in_3_d_bits_WIRE.data connect in[3].d.bits.denied, _in_3_d_bits_WIRE.denied connect in[3].d.bits.sink, _in_3_d_bits_WIRE.sink connect in[3].d.bits.source, _in_3_d_bits_WIRE.source connect in[3].d.bits.size, _in_3_d_bits_WIRE.size connect in[3].d.bits.param, _in_3_d_bits_WIRE.param connect in[3].d.bits.opcode, _in_3_d_bits_WIRE.opcode connect portsBIO_filtered[3].ready, UInt<1>(0h0) connect in[4].b, portsBIO_filtered_1[4] regreset beatsLeft_8 : UInt, clock, reset, UInt<1>(0h0) node idle_8 = eq(beatsLeft_8, UInt<1>(0h0)) node latch_8 = and(idle_8, in[4].d.ready) node _readys_T_90 = cat(portsDIO_filtered_1[4].valid, portsDIO_filtered[4].valid) node readys_valid_8 = bits(_readys_T_90, 1, 0) node _readys_T_91 = eq(readys_valid_8, _readys_T_90) node _readys_T_92 = asUInt(reset) node _readys_T_93 = eq(_readys_T_92, UInt<1>(0h0)) when _readys_T_93 : node _readys_T_94 = eq(_readys_T_91, UInt<1>(0h0)) when _readys_T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_8 assert(clock, _readys_T_91, UInt<1>(0h1), "") : readys_assert_8 regreset readys_mask_8 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_16 = not(readys_mask_8) node _readys_filter_T_17 = and(readys_valid_8, _readys_filter_T_16) node readys_filter_8 = cat(_readys_filter_T_17, readys_valid_8) node _readys_unready_T_52 = shr(readys_filter_8, 1) node _readys_unready_T_53 = or(readys_filter_8, _readys_unready_T_52) node _readys_unready_T_54 = bits(_readys_unready_T_53, 3, 0) node _readys_unready_T_55 = shr(_readys_unready_T_54, 1) node _readys_unready_T_56 = shl(readys_mask_8, 2) node readys_unready_8 = or(_readys_unready_T_55, _readys_unready_T_56) node _readys_readys_T_24 = shr(readys_unready_8, 2) node _readys_readys_T_25 = bits(readys_unready_8, 1, 0) node _readys_readys_T_26 = and(_readys_readys_T_24, _readys_readys_T_25) node readys_readys_8 = not(_readys_readys_T_26) node _readys_T_95 = orr(readys_valid_8) node _readys_T_96 = and(latch_8, _readys_T_95) when _readys_T_96 : node _readys_mask_T_58 = and(readys_readys_8, readys_valid_8) node _readys_mask_T_59 = shl(_readys_mask_T_58, 1) node _readys_mask_T_60 = bits(_readys_mask_T_59, 1, 0) node _readys_mask_T_61 = or(_readys_mask_T_58, _readys_mask_T_60) node _readys_mask_T_62 = bits(_readys_mask_T_61, 1, 0) connect readys_mask_8, _readys_mask_T_62 node _readys_T_97 = bits(readys_readys_8, 1, 0) node _readys_T_98 = bits(_readys_T_97, 0, 0) node _readys_T_99 = bits(_readys_T_97, 1, 1) wire readys_8 : UInt<1>[2] connect readys_8[0], _readys_T_98 connect readys_8[1], _readys_T_99 node _winner_T_26 = and(readys_8[0], portsDIO_filtered[4].valid) node _winner_T_27 = and(readys_8[1], portsDIO_filtered_1[4].valid) wire winner_8 : UInt<1>[2] connect winner_8[0], _winner_T_26 connect winner_8[1], _winner_T_27 node prefixOR_1_8 = or(UInt<1>(0h0), winner_8[0]) node _prefixOR_T_8 = or(prefixOR_1_8, winner_8[1]) node _T_196 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_197 = eq(winner_8[0], UInt<1>(0h0)) node _T_198 = or(_T_196, _T_197) node _T_199 = eq(prefixOR_1_8, UInt<1>(0h0)) node _T_200 = eq(winner_8[1], UInt<1>(0h0)) node _T_201 = or(_T_199, _T_200) node _T_202 = and(_T_198, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_16 assert(clock, _T_202, UInt<1>(0h1), "") : assert_16 node _T_206 = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid) node _T_207 = eq(_T_206, UInt<1>(0h0)) node _T_208 = or(winner_8[0], winner_8[1]) node _T_209 = or(_T_207, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_17 assert(clock, _T_209, UInt<1>(0h1), "") : assert_17 node maskedBeats_0_8 = mux(winner_8[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_8 = mux(winner_8[1], beatsDO_1, UInt<1>(0h0)) node initBeats_8 = or(maskedBeats_0_8, maskedBeats_1_8) node _beatsLeft_T_32 = and(in[4].d.ready, in[4].d.valid) node _beatsLeft_T_33 = sub(beatsLeft_8, _beatsLeft_T_32) node _beatsLeft_T_34 = tail(_beatsLeft_T_33, 1) node _beatsLeft_T_35 = mux(latch_8, initBeats_8, _beatsLeft_T_34) connect beatsLeft_8, _beatsLeft_T_35 wire _state_WIRE_8 : UInt<1>[2] connect _state_WIRE_8[0], UInt<1>(0h0) connect _state_WIRE_8[1], UInt<1>(0h0) regreset state_8 : UInt<1>[2], clock, reset, _state_WIRE_8 node muxState_8 = mux(idle_8, winner_8, state_8) connect state_8, muxState_8 node allowed_8 = mux(idle_8, readys_8, state_8) node _filtered_4_ready_T = and(in[4].d.ready, allowed_8[0]) connect portsDIO_filtered[4].ready, _filtered_4_ready_T node _filtered_4_ready_T_1 = and(in[4].d.ready, allowed_8[1]) connect portsDIO_filtered_1[4].ready, _filtered_4_ready_T_1 node _in_4_d_valid_T = or(portsDIO_filtered[4].valid, portsDIO_filtered_1[4].valid) node _in_4_d_valid_T_1 = mux(state_8[0], portsDIO_filtered[4].valid, UInt<1>(0h0)) node _in_4_d_valid_T_2 = mux(state_8[1], portsDIO_filtered_1[4].valid, UInt<1>(0h0)) node _in_4_d_valid_T_3 = or(_in_4_d_valid_T_1, _in_4_d_valid_T_2) wire _in_4_d_valid_WIRE : UInt<1> connect _in_4_d_valid_WIRE, _in_4_d_valid_T_3 node _in_4_d_valid_T_4 = mux(idle_8, _in_4_d_valid_T, _in_4_d_valid_WIRE) connect in[4].d.valid, _in_4_d_valid_T_4 wire _in_4_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>} node _in_4_d_bits_T = mux(muxState_8[0], portsDIO_filtered[4].bits.corrupt, UInt<1>(0h0)) node _in_4_d_bits_T_1 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.corrupt, UInt<1>(0h0)) node _in_4_d_bits_T_2 = or(_in_4_d_bits_T, _in_4_d_bits_T_1) wire _in_4_d_bits_WIRE_1 : UInt<1> connect _in_4_d_bits_WIRE_1, _in_4_d_bits_T_2 connect _in_4_d_bits_WIRE.corrupt, _in_4_d_bits_WIRE_1 node _in_4_d_bits_T_3 = mux(muxState_8[0], portsDIO_filtered[4].bits.data, UInt<1>(0h0)) node _in_4_d_bits_T_4 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.data, UInt<1>(0h0)) node _in_4_d_bits_T_5 = or(_in_4_d_bits_T_3, _in_4_d_bits_T_4) wire _in_4_d_bits_WIRE_2 : UInt<128> connect _in_4_d_bits_WIRE_2, _in_4_d_bits_T_5 connect _in_4_d_bits_WIRE.data, _in_4_d_bits_WIRE_2 wire _in_4_d_bits_WIRE_3 : { } connect _in_4_d_bits_WIRE.echo, _in_4_d_bits_WIRE_3 wire _in_4_d_bits_WIRE_4 : { } connect _in_4_d_bits_WIRE.user, _in_4_d_bits_WIRE_4 node _in_4_d_bits_T_6 = mux(muxState_8[0], portsDIO_filtered[4].bits.denied, UInt<1>(0h0)) node _in_4_d_bits_T_7 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.denied, UInt<1>(0h0)) node _in_4_d_bits_T_8 = or(_in_4_d_bits_T_6, _in_4_d_bits_T_7) wire _in_4_d_bits_WIRE_5 : UInt<1> connect _in_4_d_bits_WIRE_5, _in_4_d_bits_T_8 connect _in_4_d_bits_WIRE.denied, _in_4_d_bits_WIRE_5 node _in_4_d_bits_T_9 = mux(muxState_8[0], portsDIO_filtered[4].bits.sink, UInt<1>(0h0)) node _in_4_d_bits_T_10 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.sink, UInt<1>(0h0)) node _in_4_d_bits_T_11 = or(_in_4_d_bits_T_9, _in_4_d_bits_T_10) wire _in_4_d_bits_WIRE_6 : UInt<4> connect _in_4_d_bits_WIRE_6, _in_4_d_bits_T_11 connect _in_4_d_bits_WIRE.sink, _in_4_d_bits_WIRE_6 node _in_4_d_bits_T_12 = mux(muxState_8[0], portsDIO_filtered[4].bits.source, UInt<1>(0h0)) node _in_4_d_bits_T_13 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.source, UInt<1>(0h0)) node _in_4_d_bits_T_14 = or(_in_4_d_bits_T_12, _in_4_d_bits_T_13) wire _in_4_d_bits_WIRE_7 : UInt<7> connect _in_4_d_bits_WIRE_7, _in_4_d_bits_T_14 connect _in_4_d_bits_WIRE.source, _in_4_d_bits_WIRE_7 node _in_4_d_bits_T_15 = mux(muxState_8[0], portsDIO_filtered[4].bits.size, UInt<1>(0h0)) node _in_4_d_bits_T_16 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.size, UInt<1>(0h0)) node _in_4_d_bits_T_17 = or(_in_4_d_bits_T_15, _in_4_d_bits_T_16) wire _in_4_d_bits_WIRE_8 : UInt<4> connect _in_4_d_bits_WIRE_8, _in_4_d_bits_T_17 connect _in_4_d_bits_WIRE.size, _in_4_d_bits_WIRE_8 node _in_4_d_bits_T_18 = mux(muxState_8[0], portsDIO_filtered[4].bits.param, UInt<1>(0h0)) node _in_4_d_bits_T_19 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.param, UInt<1>(0h0)) node _in_4_d_bits_T_20 = or(_in_4_d_bits_T_18, _in_4_d_bits_T_19) wire _in_4_d_bits_WIRE_9 : UInt<2> connect _in_4_d_bits_WIRE_9, _in_4_d_bits_T_20 connect _in_4_d_bits_WIRE.param, _in_4_d_bits_WIRE_9 node _in_4_d_bits_T_21 = mux(muxState_8[0], portsDIO_filtered[4].bits.opcode, UInt<1>(0h0)) node _in_4_d_bits_T_22 = mux(muxState_8[1], portsDIO_filtered_1[4].bits.opcode, UInt<1>(0h0)) node _in_4_d_bits_T_23 = or(_in_4_d_bits_T_21, _in_4_d_bits_T_22) wire _in_4_d_bits_WIRE_10 : UInt<3> connect _in_4_d_bits_WIRE_10, _in_4_d_bits_T_23 connect _in_4_d_bits_WIRE.opcode, _in_4_d_bits_WIRE_10 connect in[4].d.bits.corrupt, _in_4_d_bits_WIRE.corrupt connect in[4].d.bits.data, _in_4_d_bits_WIRE.data connect in[4].d.bits.denied, _in_4_d_bits_WIRE.denied connect in[4].d.bits.sink, _in_4_d_bits_WIRE.sink connect in[4].d.bits.source, _in_4_d_bits_WIRE.source connect in[4].d.bits.size, _in_4_d_bits_WIRE.size connect in[4].d.bits.param, _in_4_d_bits_WIRE.param connect in[4].d.bits.opcode, _in_4_d_bits_WIRE.opcode connect portsBIO_filtered[4].ready, UInt<1>(0h0)

module TLXbar_sbus_i5_o2_a32d128s7k4z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_4_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_4_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_4_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_4_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_4_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_4_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_4_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_4_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_4_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_3_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire portsEOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire [3:0] out_1_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [3:0] out_1_d_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] in_4_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_a_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_4_a_valid_0 = auto_anon_in_4_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_a_bits_opcode_0 = auto_anon_in_4_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_a_bits_param_0 = auto_anon_in_4_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_a_bits_size_0 = auto_anon_in_4_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_a_bits_source_0 = auto_anon_in_4_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_a_bits_address_0 = auto_anon_in_4_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_4_a_bits_mask_0 = auto_anon_in_4_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_a_bits_data_0 = auto_anon_in_4_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_4_a_bits_corrupt_0 = auto_anon_in_4_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_4_b_ready_0 = auto_anon_in_4_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_valid_0 = auto_anon_in_4_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_c_bits_opcode_0 = auto_anon_in_4_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_c_bits_param_0 = auto_anon_in_4_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_c_bits_size_0 = auto_anon_in_4_c_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_c_bits_source_0 = auto_anon_in_4_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_c_bits_address_0 = auto_anon_in_4_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_c_bits_data_0 = auto_anon_in_4_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_bits_corrupt_0 = auto_anon_in_4_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_ready_0 = auto_anon_in_4_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_4_e_valid_0 = auto_anon_in_4_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_e_bits_sink_0 = auto_anon_in_4_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_valid_0 = auto_anon_in_3_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_a_bits_opcode_0 = auto_anon_in_3_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_a_bits_param_0 = auto_anon_in_3_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_a_bits_size_0 = auto_anon_in_3_a_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_a_bits_source_0 = auto_anon_in_3_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_a_bits_address_0 = auto_anon_in_3_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_3_a_bits_mask_0 = auto_anon_in_3_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_a_bits_data_0 = auto_anon_in_3_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_bits_corrupt_0 = auto_anon_in_3_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_ready_0 = auto_anon_in_3_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_valid_0 = auto_anon_in_3_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_c_bits_opcode_0 = auto_anon_in_3_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_c_bits_param_0 = auto_anon_in_3_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_c_bits_size_0 = auto_anon_in_3_c_bits_size; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_c_bits_source_0 = auto_anon_in_3_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_c_bits_address_0 = auto_anon_in_3_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_c_bits_data_0 = auto_anon_in_3_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_bits_corrupt_0 = auto_anon_in_3_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_ready_0 = auto_anon_in_3_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_3_e_valid_0 = auto_anon_in_3_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_e_bits_sink_0 = auto_anon_in_3_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_opcode_0 = auto_anon_in_2_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_a_bits_param_0 = auto_anon_in_2_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_a_bits_size_0 = auto_anon_in_2_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_a_bits_source_0 = auto_anon_in_2_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_2_a_bits_mask_0 = auto_anon_in_2_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_a_bits_data_0 = auto_anon_in_2_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_bits_corrupt_0 = auto_anon_in_2_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_ready_0 = auto_anon_in_2_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_valid_0 = auto_anon_in_2_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_opcode_0 = auto_anon_in_2_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_c_bits_param_0 = auto_anon_in_2_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_c_bits_size_0 = auto_anon_in_2_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_c_bits_source_0 = auto_anon_in_2_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_c_bits_address_0 = auto_anon_in_2_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_c_bits_data_0 = auto_anon_in_2_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_bits_corrupt_0 = auto_anon_in_2_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_ready_0 = auto_anon_in_2_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_valid_0 = auto_anon_in_2_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_e_bits_sink_0 = auto_anon_in_2_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_ready_0 = auto_anon_in_1_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_valid_0 = auto_anon_in_1_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_opcode_0 = auto_anon_in_1_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_c_bits_param_0 = auto_anon_in_1_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_c_bits_size_0 = auto_anon_in_1_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_c_bits_source_0 = auto_anon_in_1_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_c_bits_address_0 = auto_anon_in_1_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_c_bits_data_0 = auto_anon_in_1_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_bits_corrupt_0 = auto_anon_in_1_c_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_valid_0 = auto_anon_in_1_e_valid; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_e_bits_sink_0 = auto_anon_in_1_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_valid_0 = auto_anon_out_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_b_bits_param_0 = auto_anon_out_1_b_bits_param; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_b_bits_source_0 = auto_anon_out_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_b_bits_address_0 = auto_anon_out_1_b_bits_address; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_ready_0 = auto_anon_out_1_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_0_d_bits_param_0 = auto_anon_out_0_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_sink_0 = auto_anon_out_0_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire _readys_T_15 = reset; // @[Arbiter.scala:22:12] wire _readys_T_28 = reset; // @[Arbiter.scala:22:12] wire _readys_T_40 = reset; // @[Arbiter.scala:22:12] wire _readys_T_52 = reset; // @[Arbiter.scala:22:12] wire _readys_T_62 = reset; // @[Arbiter.scala:22:12] wire _readys_T_72 = reset; // @[Arbiter.scala:22:12] wire _readys_T_82 = reset; // @[Arbiter.scala:22:12] wire _readys_T_92 = reset; // @[Arbiter.scala:22:12] wire [2:0] auto_anon_in_4_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_b_bits_size = 3'h6; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_3_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] anonIn_4_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] x1_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] in_1_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_2_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_3_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] in_4_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] out_1_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_1_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_2_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_3_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_4_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [3:0] auto_anon_in_4_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_b_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_2_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_3_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] in_4_b_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] out_1_b_bits_size = 4'h6; // @[Xbar.scala:216:19] wire [3:0] portsBIO_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_1_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_2_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_3_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_4_bits_size = 4'h6; // @[Xbar.scala:352:24] wire [15:0] auto_anon_in_4_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_3_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_2_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_in_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_2_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_3_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] anonIn_4_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] x1_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] in_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_2_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_3_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] in_4_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] out_1_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] portsBIO_filtered_1_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_1_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_2_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_3_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_4_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_anon_in_4_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_b_bits_data = 128'h0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_2_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_3_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] anonIn_4_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] x1_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_0_c_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_1_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_2_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_3_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] in_4_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] out_0_c_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] out_1_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_2_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_3_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_4_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_2_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_3_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsBIO_filtered_1_4_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire [127:0] portsCOI_filtered_1_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_anon_in_4_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_1_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_2_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_3_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_4_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire x1_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_0_e_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_2_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_3_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_4_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire out_0_b_ready = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_valid = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_e_valid = 1'h0; // @[Xbar.scala:216:19] wire out_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestBOI_T_6 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_8 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_11 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_13 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_2 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_16 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_18 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_3 = 1'h0; // @[Parameters.scala:56:48] wire _requestBOI_T_21 = 1'h0; // @[Parameters.scala:54:32] wire _requestBOI_T_23 = 1'h0; // @[Parameters.scala:54:67] wire requestBOI_0_4 = 1'h0; // @[Parameters.scala:56:48] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_10 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_15 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_20 = 1'h0; // @[Parameters.scala:54:10] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire beatsBO_opdata_1 = 1'h0; // @[Edges.scala:97:28] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_2_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_3_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_3_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_filtered_4_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsBIO_filtered_4_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_out_0_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_3 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_4 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_5 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_6 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_7 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_8 = 1'h0; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_3_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_4_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_1_b_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_in_0_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_in_0_c_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_1_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_2_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_3_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_in_4_c_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_0_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_in_0_e_ready_WIRE = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_2 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_1_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_4 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_2_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_3_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_3_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_6 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_7 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_3_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire portsEOI_filtered_4_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_4_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_8 = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_9 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_in_4_e_ready_T = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_4 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2_3 = 1'h0; // @[Arbiter.scala:88:34] wire maskedBeats_0_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2_3 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_3_3 = 1'h0; // @[Arbiter.scala:82:69] wire _initBeats_T_8 = 1'h0; // @[Arbiter.scala:84:44] wire _initBeats_T_9 = 1'h0; // @[Arbiter.scala:84:44] wire initBeats_3 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_3_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_5_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_6_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_7_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_7_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_8_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_8_1 = 1'h0; // @[Arbiter.scala:88:34] wire auto_anon_out_1_e_ready = 1'h1; // @[Xbar.scala:74:9] wire x1_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire in_0_b_ready = 1'h1; // @[Xbar.scala:159:18] wire out_0_c_ready = 1'h1; // @[Xbar.scala:216:19] wire out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire out_1_e_ready = 1'h1; // @[Xbar.scala:216:19] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_19 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_24 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_29 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_2_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_34 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_3_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_39 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_3_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_44 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_4_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_49 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_4_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _requestBOI_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_14 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_19 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_24 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_32 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_34 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_11 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_12 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_13 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_14 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_2_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_16 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_17 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_18 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_19 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_3_1 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_21 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_22 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_23 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_24 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_4_1 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire _beatsBO_opdata_T_1 = 1'h1; // @[Edges.scala:97:37] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_4 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_6 = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_8 = 1'h1; // @[Xbar.scala:355:54] wire [3:0] in_0_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_0_e_bits_sink = 4'h0; // @[Xbar.scala:159:18] wire [3:0] out_0_b_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] out_0_c_bits_size = 4'h0; // @[Xbar.scala:216:19] wire [3:0] out_0_e_bits_sink = 4'h0; // @[Xbar.scala:216:19] wire [3:0] requestBOI_uncommonBits_3 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] requestBOI_uncommonBits_4 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] _requestEIO_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] requestEIO_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_3_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsBIO_filtered_4_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsCOI_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_0_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [3:0] portsEOI_filtered_1_bits_sink = 4'h0; // @[Xbar.scala:352:24] wire [31:0] in_0_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_0_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] out_0_b_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] out_0_c_bits_address = 32'h0; // @[Xbar.scala:216:19] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_3_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_4_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [6:0] in_0_b_bits_source = 7'h0; // @[Xbar.scala:159:18] wire [6:0] in_0_c_bits_source = 7'h0; // @[Xbar.scala:159:18] wire [6:0] out_0_b_bits_source = 7'h0; // @[Xbar.scala:216:19] wire [6:0] out_0_c_bits_source = 7'h0; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_1 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_2 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_3 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] _requestBOI_uncommonBits_T_4 = 7'h0; // @[Parameters.scala:52:29] wire [6:0] portsBIO_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_2_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_3_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsBIO_filtered_4_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_0_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [6:0] portsCOI_filtered_1_bits_source = 7'h0; // @[Xbar.scala:352:24] wire [2:0] in_0_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] out_0_b_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_opcode = 3'h0; // @[Xbar.scala:216:19] wire [2:0] out_0_c_bits_param = 3'h0; // @[Xbar.scala:216:19] wire [2:0] _requestBOI_T_15 = 3'h0; // @[Parameters.scala:54:10] wire [2:0] _requestBOI_T_20 = 3'h0; // @[Parameters.scala:54:10] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_3_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_4_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [15:0] in_0_b_bits_mask = 16'h0; // @[Xbar.scala:159:18] wire [15:0] out_0_b_bits_mask = 16'h0; // @[Xbar.scala:216:19] wire [15:0] portsBIO_filtered_0_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_1_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_2_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_3_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [15:0] portsBIO_filtered_4_bits_mask = 16'h0; // @[Xbar.scala:352:24] wire [1:0] in_0_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] out_0_b_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_T = 2'h0; // @[Parameters.scala:54:10] wire [1:0] requestBOI_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] requestBOI_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] beatsBO_1 = 2'h0; // @[Edges.scala:221:14] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_2_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_3_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsBIO_filtered_4_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [7:0] beatsBO_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14] wire [7:0] beatsCI_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] beatsCI_0 = 8'h0; // @[Edges.scala:221:14] wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71] wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71] wire [1:0] beatsBO_decode_1 = 2'h3; // @[Edges.scala:220:59] wire [5:0] _beatsBO_decode_T_5 = 6'h3F; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_4 = 6'h0; // @[package.scala:243:76] wire [20:0] _beatsBO_decode_T_3 = 21'hFC0; // @[package.scala:243:71] wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56] wire [4:0] _requestBOI_T_5 = 5'h0; // @[Parameters.scala:54:10] wire [4:0] _requestBOI_T_10 = 5'h0; // @[Parameters.scala:54:10] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_18 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_22 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_23 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_27 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_28 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_32 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_33 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_42 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_43 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_47 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_48 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_4_a_ready; // @[MixedNode.scala:551:17] wire anonIn_4_a_valid = auto_anon_in_4_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_a_bits_opcode = auto_anon_in_4_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_a_bits_param = auto_anon_in_4_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_a_bits_size = auto_anon_in_4_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_a_bits_source = auto_anon_in_4_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_4_a_bits_address = auto_anon_in_4_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_4_a_bits_mask = auto_anon_in_4_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_4_a_bits_data = auto_anon_in_4_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_4_a_bits_corrupt = auto_anon_in_4_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_4_b_ready = auto_anon_in_4_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_4_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_4_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_4_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_4_c_ready; // @[MixedNode.scala:551:17] wire anonIn_4_c_valid = auto_anon_in_4_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_c_bits_opcode = auto_anon_in_4_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_4_c_bits_param = auto_anon_in_4_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_c_bits_size = auto_anon_in_4_c_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_4_c_bits_source = auto_anon_in_4_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_4_c_bits_address = auto_anon_in_4_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_4_c_bits_data = auto_anon_in_4_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_4_c_bits_corrupt = auto_anon_in_4_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_4_d_ready = auto_anon_in_4_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_4_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_4_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_4_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_4_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_4_e_ready; // @[MixedNode.scala:551:17] wire anonIn_4_e_valid = auto_anon_in_4_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_3_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_4_e_bits_sink = auto_anon_in_4_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_3_a_valid = auto_anon_in_3_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_a_bits_opcode = auto_anon_in_3_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_a_bits_param = auto_anon_in_3_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_a_bits_size = auto_anon_in_3_a_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_a_bits_source = auto_anon_in_3_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_3_a_bits_address = auto_anon_in_3_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_3_a_bits_mask = auto_anon_in_3_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_3_a_bits_data = auto_anon_in_3_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_3_a_bits_corrupt = auto_anon_in_3_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_3_b_ready = auto_anon_in_3_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_3_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_3_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_3_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_3_c_ready; // @[MixedNode.scala:551:17] wire anonIn_3_c_valid = auto_anon_in_3_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_c_bits_opcode = auto_anon_in_3_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_3_c_bits_param = auto_anon_in_3_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_c_bits_size = auto_anon_in_3_c_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_3_c_bits_source = auto_anon_in_3_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_3_c_bits_address = auto_anon_in_3_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_3_c_bits_data = auto_anon_in_3_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_3_c_bits_corrupt = auto_anon_in_3_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_3_d_ready = auto_anon_in_3_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_3_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_3_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_3_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_3_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_3_e_ready; // @[MixedNode.scala:551:17] wire anonIn_3_e_valid = auto_anon_in_3_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_2_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_3_e_bits_sink = auto_anon_in_3_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_a_bits_param = auto_anon_in_2_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_a_bits_size = auto_anon_in_2_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_a_bits_source = auto_anon_in_2_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_2_a_bits_mask = auto_anon_in_2_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_2_a_bits_data = auto_anon_in_2_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_b_ready = auto_anon_in_2_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_2_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_2_c_ready; // @[MixedNode.scala:551:17] wire anonIn_2_c_valid = auto_anon_in_2_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_opcode = auto_anon_in_2_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_2_c_bits_param = auto_anon_in_2_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_2_c_bits_size = auto_anon_in_2_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_2_c_bits_source = auto_anon_in_2_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_2_c_bits_address = auto_anon_in_2_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_2_c_bits_data = auto_anon_in_2_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_2_c_bits_corrupt = auto_anon_in_2_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_2_d_ready = auto_anon_in_2_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_2_e_ready; // @[MixedNode.scala:551:17] wire anonIn_2_e_valid = auto_anon_in_2_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_2_e_bits_sink = auto_anon_in_2_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_b_ready = auto_anon_in_1_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_b_valid; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_1_b_bits_address; // @[MixedNode.scala:551:17] wire anonIn_1_c_ready; // @[MixedNode.scala:551:17] wire anonIn_1_c_valid = auto_anon_in_1_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_opcode = auto_anon_in_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_c_bits_param = auto_anon_in_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_c_bits_size = auto_anon_in_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonIn_1_c_bits_source = auto_anon_in_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_c_bits_address = auto_anon_in_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_1_c_bits_data = auto_anon_in_1_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_1_c_bits_corrupt = auto_anon_in_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_1_e_ready; // @[MixedNode.scala:551:17] wire anonIn_1_e_valid = auto_anon_in_1_e_valid_0; // @[Xbar.scala:74:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_e_bits_sink = auto_anon_in_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_b_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_b_valid = auto_anon_out_1_b_valid_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_b_bits_param = auto_anon_out_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_b_bits_source = auto_anon_out_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] x1_anonOut_b_bits_address = auto_anon_out_1_b_bits_address_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_ready = auto_anon_out_1_c_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire x1_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = auto_anon_out_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_4_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_4_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_4_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_4_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_4_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_4_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_4_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_3_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_3_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_3_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_3_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_size_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_3_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_3_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_3_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_2_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_2_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_2_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_param_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_b_bits_address_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_e_ready_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_c_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_1_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_1_c_bits_address_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_1_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_1_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [6:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [28:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [15:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [127:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_b_ready = anonIn_1_b_ready; // @[Xbar.scala:159:18] wire in_1_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_valid_0 = anonIn_1_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_1_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_param_0 = anonIn_1_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_1_b_bits_source_0 = anonIn_1_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_1_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_1_b_bits_address_0 = anonIn_1_b_bits_address; // @[Xbar.scala:74:9] wire in_1_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_c_ready_0 = anonIn_1_c_ready; // @[Xbar.scala:74:9] wire in_1_c_valid = anonIn_1_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = anonIn_1_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = anonIn_1_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = anonIn_1_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = anonIn_1_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_1_c_bits_data = anonIn_1_c_bits_data; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = anonIn_1_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_1_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_e_ready_0 = anonIn_1_e_ready; // @[Xbar.scala:74:9] wire in_1_e_valid = anonIn_1_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_1_e_bits_sink = anonIn_1_e_bits_sink; // @[Xbar.scala:159:18] wire in_2_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9] wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_opcode = anonIn_2_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_a_bits_param = anonIn_2_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_a_bits_size = anonIn_2_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_2_a_bits_mask = anonIn_2_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_2_a_bits_data = anonIn_2_a_bits_data; // @[Xbar.scala:159:18] wire in_2_a_bits_corrupt = anonIn_2_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_b_ready = anonIn_2_b_ready; // @[Xbar.scala:159:18] wire in_2_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_valid_0 = anonIn_2_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_2_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_param_0 = anonIn_2_b_bits_param; // @[Xbar.scala:74:9] wire [1:0] _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign auto_anon_in_2_b_bits_source_0 = anonIn_2_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_2_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_2_b_bits_address_0 = anonIn_2_b_bits_address; // @[Xbar.scala:74:9] wire in_2_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_c_ready_0 = anonIn_2_c_ready; // @[Xbar.scala:74:9] wire in_2_c_valid = anonIn_2_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_opcode = anonIn_2_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_2_c_bits_param = anonIn_2_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_2_c_bits_size = anonIn_2_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_2_c_bits_address = anonIn_2_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_2_c_bits_data = anonIn_2_c_bits_data; // @[Xbar.scala:159:18] wire in_2_c_bits_corrupt = anonIn_2_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_2_d_ready = anonIn_2_d_ready; // @[Xbar.scala:159:18] wire in_2_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] assign auto_anon_in_2_d_bits_source_0 = anonIn_2_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_2_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9] wire in_2_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_2_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9] wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_2_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_2_e_ready_0 = anonIn_2_e_ready; // @[Xbar.scala:74:9] wire in_2_e_valid = anonIn_2_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_2_e_bits_sink = anonIn_2_e_bits_sink; // @[Xbar.scala:159:18] wire in_3_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_a_ready_0 = anonIn_3_a_ready; // @[Xbar.scala:74:9] wire in_3_a_valid = anonIn_3_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_3_a_bits_opcode = anonIn_3_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_3_a_bits_param = anonIn_3_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_3_a_bits_size = anonIn_3_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_3_a_bits_address = anonIn_3_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_3_a_bits_mask = anonIn_3_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_3_a_bits_data = anonIn_3_a_bits_data; // @[Xbar.scala:159:18] wire in_3_a_bits_corrupt = anonIn_3_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_3_b_ready = anonIn_3_b_ready; // @[Xbar.scala:159:18] wire in_3_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_valid_0 = anonIn_3_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_3_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_bits_param_0 = anonIn_3_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] _anonIn_b_bits_source_T_2; // @[Xbar.scala:156:69] assign auto_anon_in_3_b_bits_source_0 = anonIn_3_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_3_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_3_b_bits_address_0 = anonIn_3_b_bits_address; // @[Xbar.scala:74:9] wire in_3_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_c_ready_0 = anonIn_3_c_ready; // @[Xbar.scala:74:9] wire in_3_c_valid = anonIn_3_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_3_c_bits_opcode = anonIn_3_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_3_c_bits_param = anonIn_3_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_3_c_bits_size = anonIn_3_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_3_c_bits_address = anonIn_3_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_3_c_bits_data = anonIn_3_c_bits_data; // @[Xbar.scala:159:18] wire in_3_c_bits_corrupt = anonIn_3_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_3_d_ready = anonIn_3_d_ready; // @[Xbar.scala:159:18] wire in_3_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_valid_0 = anonIn_3_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_3_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_opcode_0 = anonIn_3_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_3_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_param_0 = anonIn_3_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_3_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_size_0 = anonIn_3_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69] assign auto_anon_in_3_d_bits_source_0 = anonIn_3_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_3_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_sink_0 = anonIn_3_d_bits_sink; // @[Xbar.scala:74:9] wire in_3_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_denied_0 = anonIn_3_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_3_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_data_0 = anonIn_3_d_bits_data; // @[Xbar.scala:74:9] wire in_3_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_3_d_bits_corrupt_0 = anonIn_3_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_3_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_3_e_ready_0 = anonIn_3_e_ready; // @[Xbar.scala:74:9] wire in_3_e_valid = anonIn_3_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_3_e_bits_sink = anonIn_3_e_bits_sink; // @[Xbar.scala:159:18] wire in_4_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_a_ready_0 = anonIn_4_a_ready; // @[Xbar.scala:74:9] wire in_4_a_valid = anonIn_4_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_4_a_bits_opcode = anonIn_4_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_4_a_bits_param = anonIn_4_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_4_a_bits_size = anonIn_4_a_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_4_a_bits_address = anonIn_4_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] in_4_a_bits_mask = anonIn_4_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] in_4_a_bits_data = anonIn_4_a_bits_data; // @[Xbar.scala:159:18] wire in_4_a_bits_corrupt = anonIn_4_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_4_b_ready = anonIn_4_b_ready; // @[Xbar.scala:159:18] wire in_4_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_valid_0 = anonIn_4_b_valid; // @[Xbar.scala:74:9] wire [1:0] in_4_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_bits_param_0 = anonIn_4_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] _anonIn_b_bits_source_T_3; // @[Xbar.scala:156:69] assign auto_anon_in_4_b_bits_source_0 = anonIn_4_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_4_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_4_b_bits_address_0 = anonIn_4_b_bits_address; // @[Xbar.scala:74:9] wire in_4_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_c_ready_0 = anonIn_4_c_ready; // @[Xbar.scala:74:9] wire in_4_c_valid = anonIn_4_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_4_c_bits_opcode = anonIn_4_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_4_c_bits_param = anonIn_4_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_4_c_bits_size = anonIn_4_c_bits_size; // @[Xbar.scala:159:18] wire [31:0] in_4_c_bits_address = anonIn_4_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] in_4_c_bits_data = anonIn_4_c_bits_data; // @[Xbar.scala:159:18] wire in_4_c_bits_corrupt = anonIn_4_c_bits_corrupt; // @[Xbar.scala:159:18] wire in_4_d_ready = anonIn_4_d_ready; // @[Xbar.scala:159:18] wire in_4_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_valid_0 = anonIn_4_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_4_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_opcode_0 = anonIn_4_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_4_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_param_0 = anonIn_4_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_4_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_size_0 = anonIn_4_d_bits_size; // @[Xbar.scala:74:9] wire [3:0] _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69] assign auto_anon_in_4_d_bits_source_0 = anonIn_4_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] in_4_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_sink_0 = anonIn_4_d_bits_sink; // @[Xbar.scala:74:9] wire in_4_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_denied_0 = anonIn_4_d_bits_denied; // @[Xbar.scala:74:9] wire [127:0] in_4_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_data_0 = anonIn_4_d_bits_data; // @[Xbar.scala:74:9] wire in_4_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_4_d_bits_corrupt_0 = anonIn_4_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_4_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_4_e_ready_0 = anonIn_4_e_ready; // @[Xbar.scala:74:9] wire in_4_e_valid = anonIn_4_e_valid; // @[Xbar.scala:159:18] wire [3:0] in_4_e_bits_sink = anonIn_4_e_bits_sink; // @[Xbar.scala:159:18] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [15:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [127:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_b_ready_0 = x1_anonOut_b_ready; // @[Xbar.scala:74:9] wire out_1_b_valid = x1_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] out_1_b_bits_param = x1_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_1_b_bits_source = x1_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_1_b_bits_address = x1_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire out_1_c_ready = x1_anonOut_c_ready; // @[Xbar.scala:216:19] wire out_1_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_valid_0 = x1_anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_opcode_0 = x1_anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_param_0 = x1_anonOut_c_bits_param; // @[Xbar.scala:74:9] assign auto_anon_out_1_c_bits_size_0 = x1_anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [6:0] out_1_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_source_0 = x1_anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_1_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_address_0 = x1_anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [127:0] out_1_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_data_0 = x1_anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_1_c_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_c_bits_corrupt_0 = x1_anonOut_c_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [6:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_e_valid_0 = x1_anonOut_e_valid; // @[Xbar.scala:74:9] wire [3:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_1_e_bits_sink_0 = x1_anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_1_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_1_1_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_1_1_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_28 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_1_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_1_1_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_1_1_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_1_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_ready = in_1_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_b_valid = in_1_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_param = in_1_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:352:24] assign anonIn_1_b_bits_address = in_1_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_c_ready = in_1_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_3 = in_1_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_1_0_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_opcode = in_1_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_1_1_bits_param = in_1_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_1_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_1_0_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_1_1_bits_size = in_1_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_1_0_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_1_1_bits_source = in_1_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_10 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_15 = in_1_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_1_0_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_1_1_bits_address = in_1_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_1_0_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_1_1_bits_data = in_1_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_0_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_1_1_bits_corrupt = in_1_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_1_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_1_e_ready = in_1_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_3 = in_1_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_1 = in_1_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_1_0_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_1_1_bits_sink = in_1_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_2_0_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_0_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_2_1_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_2_a_bits_source_T; // @[Xbar.scala:166:55] wire [3:0] portsAOI_filtered_2_0_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_2_1_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_2_0_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_2_1_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_56 = in_2_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_2_1_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_2_0_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_2_1_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_2_0_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_2_1_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_0_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_2_1_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_ready = in_2_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_2_valid; // @[Xbar.scala:352:24] assign anonIn_2_b_valid = in_2_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_param = in_2_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:352:24] assign anonIn_2_b_bits_address = in_2_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_c_ready = in_2_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_5 = in_2_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_2_0_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_opcode = in_2_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_0_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_2_1_bits_param = in_2_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [6:0] _in_2_c_bits_source_T; // @[Xbar.scala:187:55] wire [3:0] portsCOI_filtered_2_0_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_2_1_bits_size = in_2_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_2_0_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_2_1_bits_source = in_2_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_20 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_25 = in_2_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_2_0_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_2_1_bits_address = in_2_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_2_0_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_2_1_bits_data = in_2_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_0_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_2_1_bits_corrupt = in_2_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_2_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18] wire _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_2_e_ready = in_2_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_5 = in_2_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_2 = in_2_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_2_0_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_2_1_bits_sink = in_2_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_3_a_ready = in_3_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_3_0_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_1_bits_opcode = in_3_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_0_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_3_1_bits_param = in_3_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_3_0_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_3_1_bits_size = in_3_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_3_0_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_3_1_bits_source = in_3_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_84 = in_3_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_3_0_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_3_1_bits_address = in_3_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_3_0_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_3_1_bits_mask = in_3_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_3_0_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_3_1_bits_data = in_3_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_3_0_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_3_1_bits_corrupt = in_3_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_3_ready = in_3_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_3_valid; // @[Xbar.scala:352:24] assign anonIn_3_b_valid = in_3_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_3_bits_param; // @[Xbar.scala:352:24] assign anonIn_3_b_bits_param = in_3_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_3_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_3_bits_address; // @[Xbar.scala:352:24] assign anonIn_3_b_bits_address = in_3_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_3_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_3_c_ready = in_3_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_7 = in_3_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_7 = in_3_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_3_0_bits_opcode = in_3_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_1_bits_opcode = in_3_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_0_bits_param = in_3_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_3_1_bits_param = in_3_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_3_0_bits_size = in_3_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_3_1_bits_size = in_3_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_3_0_bits_source = in_3_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_3_1_bits_source = in_3_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_30 = in_3_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_35 = in_3_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_3_0_bits_address = in_3_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_3_1_bits_address = in_3_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_3_0_bits_data = in_3_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_3_1_bits_data = in_3_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_3_0_bits_corrupt = in_3_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_3_1_bits_corrupt = in_3_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_3_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_3_d_valid = in_3_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_3_d_bits_opcode = in_3_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_3_d_bits_param = in_3_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_3_d_bits_size = in_3_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_3_d_bits_sink = in_3_d_bits_sink; // @[Xbar.scala:159:18] wire _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_3_d_bits_denied = in_3_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_3_d_bits_data = in_3_d_bits_data; // @[Xbar.scala:159:18] wire _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_3_d_bits_corrupt = in_3_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_3_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_3_e_ready = in_3_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_7 = in_3_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_3 = in_3_e_bits_sink; // @[Xbar.scala:159:18] wire _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73] wire [3:0] portsEOI_filtered_3_0_bits_sink = in_3_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_3_1_bits_sink = in_3_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_4_a_ready = in_4_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_4_0_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_1_bits_opcode = in_4_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_0_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_4_1_bits_param = in_4_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_4_0_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_4_1_bits_size = in_4_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_4_0_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsAOI_filtered_4_1_bits_source = in_4_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_112 = in_4_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_4_0_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_4_1_bits_address = in_4_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_4_0_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [15:0] portsAOI_filtered_4_1_bits_mask = in_4_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_4_0_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsAOI_filtered_4_1_bits_data = in_4_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_4_0_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_4_1_bits_corrupt = in_4_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_4_ready = in_4_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_4_valid; // @[Xbar.scala:352:24] assign anonIn_4_b_valid = in_4_b_valid; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_1_4_bits_param; // @[Xbar.scala:352:24] assign anonIn_4_b_bits_param = in_4_b_bits_param; // @[Xbar.scala:159:18] wire [6:0] portsBIO_filtered_1_4_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_1_4_bits_address; // @[Xbar.scala:352:24] assign anonIn_4_b_bits_address = in_4_b_bits_address; // @[Xbar.scala:159:18] wire _portsCOI_in_4_c_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_4_c_ready = in_4_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_9 = in_4_c_valid; // @[Xbar.scala:159:18, :355:40] wire _portsCOI_filtered_1_valid_T_9 = in_4_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_4_0_bits_opcode = in_4_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_1_bits_opcode = in_4_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_0_bits_param = in_4_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_4_1_bits_param = in_4_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_4_0_bits_size = in_4_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_4_1_bits_size = in_4_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_4_0_bits_source = in_4_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [6:0] portsCOI_filtered_4_1_bits_source = in_4_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T_40 = in_4_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_45 = in_4_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_4_0_bits_address = in_4_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsCOI_filtered_4_1_bits_address = in_4_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_4_0_bits_data = in_4_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire [127:0] portsCOI_filtered_4_1_bits_data = in_4_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_4_0_bits_corrupt = in_4_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsCOI_filtered_4_1_bits_corrupt = in_4_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_4_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_4_d_valid = in_4_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_4_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_4_d_bits_opcode = in_4_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_4_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_4_d_bits_param = in_4_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] _in_4_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_4_d_bits_size = in_4_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] _in_4_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_4_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_4_d_bits_sink = in_4_d_bits_sink; // @[Xbar.scala:159:18] wire _in_4_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_4_d_bits_denied = in_4_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] _in_4_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_4_d_bits_data = in_4_d_bits_data; // @[Xbar.scala:159:18] wire _in_4_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_4_d_bits_corrupt = in_4_d_bits_corrupt; // @[Xbar.scala:159:18] wire _portsEOI_in_4_e_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_4_e_ready = in_4_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_1_valid_T_9 = in_4_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] _requestEIO_uncommonBits_T_4 = in_4_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] portsEOI_filtered_4_0_bits_sink = in_4_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsEOI_filtered_4_1_bits_sink = in_4_e_bits_sink; // @[Xbar.scala:159:18, :352:24] wire [6:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_1_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_2_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_3_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_b_bits_source; // @[Xbar.scala:159:18] wire [6:0] in_4_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {2'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_a_bits_source_T = {5'h11, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55] assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T = in_1_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign _in_1_c_bits_source_T = {5'h11, anonIn_1_c_bits_source}; // @[Xbar.scala:187:55] assign in_1_c_bits_source = _in_1_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_a_bits_source_T = {5'h10, anonIn_2_a_bits_source}; // @[Xbar.scala:166:55] assign in_2_a_bits_source = _in_2_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign _anonIn_b_bits_source_T_1 = in_2_b_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_b_bits_source = _anonIn_b_bits_source_T_1; // @[Xbar.scala:156:69] assign _in_2_c_bits_source_T = {5'h10, anonIn_2_c_bits_source}; // @[Xbar.scala:187:55] assign in_2_c_bits_source = _in_2_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign _anonIn_d_bits_source_T_2 = in_2_d_bits_source[1:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_2_d_bits_source = _anonIn_d_bits_source_T_2; // @[Xbar.scala:156:69] wire [5:0] _in_3_a_bits_source_T = {2'h3, anonIn_3_a_bits_source}; // @[Xbar.scala:166:55] assign in_3_a_bits_source = {1'h0, _in_3_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T_2 = in_3_b_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_3_b_bits_source = _anonIn_b_bits_source_T_2; // @[Xbar.scala:156:69] wire [5:0] _in_3_c_bits_source_T = {2'h3, anonIn_3_c_bits_source}; // @[Xbar.scala:187:55] assign in_3_c_bits_source = {1'h0, _in_3_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T_3 = in_3_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_3_d_bits_source = _anonIn_d_bits_source_T_3; // @[Xbar.scala:156:69] wire [5:0] _in_4_a_bits_source_T = {2'h2, anonIn_4_a_bits_source}; // @[Xbar.scala:166:55] assign in_4_a_bits_source = {1'h0, _in_4_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T_3 = in_4_b_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_4_b_bits_source = _anonIn_b_bits_source_T_3; // @[Xbar.scala:156:69] wire [5:0] _in_4_c_bits_source_T = {2'h2, anonIn_4_c_bits_source}; // @[Xbar.scala:187:55] assign in_4_c_bits_source = {1'h0, _in_4_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T_4 = in_4_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_4_d_bits_source = _anonIn_d_bits_source_T_4; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_13; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [6:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_3_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_4_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_3_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_4_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_3_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_4_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_2 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_3 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_4 = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_3_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_4_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_3_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_4_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_3_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_4_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_3_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_4_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_3_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_4_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_a_valid_T_13; // @[Arbiter.scala:96:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_address = out_1_a_bits_address; // @[Xbar.scala:216:19] wire [15:0] _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] wire [127:0] _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] wire _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_b_ready = out_1_b_ready; // @[Xbar.scala:216:19] wire [1:0] portsBIO_filtered_1_0_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_param = out_1_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestBOI_uncommonBits_T_5 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_6 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_7 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_8 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestBOI_uncommonBits_T_9 = out_1_b_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsBIO_filtered_1_0_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_source = out_1_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_0_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_1_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_2_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_3_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_1_4_bits_address = out_1_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire _out_1_c_valid_T_10; // @[Arbiter.scala:96:24] assign x1_anonOut_c_valid = out_1_c_valid; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_opcode = out_1_c_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_param = out_1_c_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_source = out_1_c_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_address = out_1_c_bits_address; // @[Xbar.scala:216:19] wire [127:0] _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_data = out_1_c_bits_data; // @[Xbar.scala:216:19] wire _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign x1_anonOut_c_bits_corrupt = out_1_c_bits_corrupt; // @[Xbar.scala:216:19] wire _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_1_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_2_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_3_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_4_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_1_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_2_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_3_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_4_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_2_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_3_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_4_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] _requestDOI_uncommonBits_T_5 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_6 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_7 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_8 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] _requestDOI_uncommonBits_T_9 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [6:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_1_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_2_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_3_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [6:0] portsDIO_filtered_1_4_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_1_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_2_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_3_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsDIO_filtered_1_4_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_3_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_4_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_1_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_2_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_3_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire [127:0] portsDIO_filtered_1_4_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_1_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_2_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_3_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_4_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _out_1_e_valid_T_10; // @[Arbiter.scala:96:24] assign x1_anonOut_e_valid = out_1_e_valid; // @[Xbar.scala:216:19] wire _beatsLeft_T_12 = out_1_e_valid; // @[Decoupled.scala:51:35] wire [3:0] _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_1_e_bits_sink; // @[Xbar.scala:156:69, :216:19] wire [3:0] out_1_a_bits_size; // @[Xbar.scala:216:19] wire [3:0] out_1_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address[28:0]; // @[Xbar.scala:216:19, :222:41] assign out_0_d_bits_sink = {3'h0, _out_0_d_bits_sink_T}; // @[Xbar.scala:216:19, :251:{28,53}] assign x1_anonOut_a_bits_size = out_1_a_bits_size[2:0]; // @[Xbar.scala:216:19, :222:41] assign x1_anonOut_c_bits_size = out_1_c_bits_size[2:0]; // @[Xbar.scala:216:19, :241:41] assign out_1_d_bits_size = {1'h0, x1_anonOut_d_bits_size}; // @[Xbar.scala:216:19, :250:29] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign x1_anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_5 = {in_0_a_bits_address[31:17], in_0_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_10 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_12 = _requestAIO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_13 = _requestAIO_T_12; // @[Parameters.scala:137:46] wire _requestAIO_T_14 = _requestAIO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_15 = _requestAIO_T_4 | _requestAIO_T_9; // @[Xbar.scala:291:92] wire _requestAIO_T_16 = _requestAIO_T_15 | _requestAIO_T_14; // @[Xbar.scala:291:92] wire requestAIO_0_0 = _requestAIO_T_16; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_17 = {in_0_a_bits_address[31:28], in_0_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_18 = {1'h0, _requestAIO_T_17}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_19 = _requestAIO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_20 = _requestAIO_T_19; // @[Parameters.scala:137:46] wire _requestAIO_T_21 = _requestAIO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_22 = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_23 = {1'h0, _requestAIO_T_22}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_24 = _requestAIO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_25 = _requestAIO_T_24; // @[Parameters.scala:137:46] wire _requestAIO_T_26 = _requestAIO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_27 = _requestAIO_T_21 | _requestAIO_T_26; // @[Xbar.scala:291:92] wire requestAIO_0_1 = _requestAIO_T_27; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_29 = {1'h0, _requestAIO_T_28}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_30 = _requestAIO_T_29 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_31 = _requestAIO_T_30; // @[Parameters.scala:137:46] wire _requestAIO_T_32 = _requestAIO_T_31 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_33 = {in_1_a_bits_address[31:17], in_1_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_34 = {1'h0, _requestAIO_T_33}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_35 = _requestAIO_T_34 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_36 = _requestAIO_T_35; // @[Parameters.scala:137:46] wire _requestAIO_T_37 = _requestAIO_T_36 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_38 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_39 = {1'h0, _requestAIO_T_38}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_40 = _requestAIO_T_39 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_41 = _requestAIO_T_40; // @[Parameters.scala:137:46] wire _requestAIO_T_42 = _requestAIO_T_41 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_43 = _requestAIO_T_32 | _requestAIO_T_37; // @[Xbar.scala:291:92] wire _requestAIO_T_44 = _requestAIO_T_43 | _requestAIO_T_42; // @[Xbar.scala:291:92] wire requestAIO_1_0 = _requestAIO_T_44; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_2 = requestAIO_1_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_45 = {in_1_a_bits_address[31:28], in_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_46 = {1'h0, _requestAIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_47 = _requestAIO_T_46 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_48 = _requestAIO_T_47; // @[Parameters.scala:137:46] wire _requestAIO_T_49 = _requestAIO_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_50 = in_1_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_51 = {1'h0, _requestAIO_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_52 = _requestAIO_T_51 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_53 = _requestAIO_T_52; // @[Parameters.scala:137:46] wire _requestAIO_T_54 = _requestAIO_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_55 = _requestAIO_T_49 | _requestAIO_T_54; // @[Xbar.scala:291:92] wire requestAIO_1_1 = _requestAIO_T_55; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_2 = requestAIO_1_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_57 = {1'h0, _requestAIO_T_56}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_58 = _requestAIO_T_57 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_59 = _requestAIO_T_58; // @[Parameters.scala:137:46] wire _requestAIO_T_60 = _requestAIO_T_59 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_61 = {in_2_a_bits_address[31:17], in_2_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_62 = {1'h0, _requestAIO_T_61}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_63 = _requestAIO_T_62 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_64 = _requestAIO_T_63; // @[Parameters.scala:137:46] wire _requestAIO_T_65 = _requestAIO_T_64 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_66 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_67 = {1'h0, _requestAIO_T_66}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_68 = _requestAIO_T_67 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_69 = _requestAIO_T_68; // @[Parameters.scala:137:46] wire _requestAIO_T_70 = _requestAIO_T_69 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_71 = _requestAIO_T_60 | _requestAIO_T_65; // @[Xbar.scala:291:92] wire _requestAIO_T_72 = _requestAIO_T_71 | _requestAIO_T_70; // @[Xbar.scala:291:92] wire requestAIO_2_0 = _requestAIO_T_72; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_4 = requestAIO_2_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_73 = {in_2_a_bits_address[31:28], in_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_74 = {1'h0, _requestAIO_T_73}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_75 = _requestAIO_T_74 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_76 = _requestAIO_T_75; // @[Parameters.scala:137:46] wire _requestAIO_T_77 = _requestAIO_T_76 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_78 = in_2_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_79 = {1'h0, _requestAIO_T_78}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_80 = _requestAIO_T_79 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_81 = _requestAIO_T_80; // @[Parameters.scala:137:46] wire _requestAIO_T_82 = _requestAIO_T_81 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_83 = _requestAIO_T_77 | _requestAIO_T_82; // @[Xbar.scala:291:92] wire requestAIO_2_1 = _requestAIO_T_83; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_4 = requestAIO_2_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_85 = {1'h0, _requestAIO_T_84}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_86 = _requestAIO_T_85 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_87 = _requestAIO_T_86; // @[Parameters.scala:137:46] wire _requestAIO_T_88 = _requestAIO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_89 = {in_3_a_bits_address[31:17], in_3_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_90 = {1'h0, _requestAIO_T_89}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_91 = _requestAIO_T_90 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_92 = _requestAIO_T_91; // @[Parameters.scala:137:46] wire _requestAIO_T_93 = _requestAIO_T_92 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_94 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_95 = {1'h0, _requestAIO_T_94}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_96 = _requestAIO_T_95 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_97 = _requestAIO_T_96; // @[Parameters.scala:137:46] wire _requestAIO_T_98 = _requestAIO_T_97 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_99 = _requestAIO_T_88 | _requestAIO_T_93; // @[Xbar.scala:291:92] wire _requestAIO_T_100 = _requestAIO_T_99 | _requestAIO_T_98; // @[Xbar.scala:291:92] wire requestAIO_3_0 = _requestAIO_T_100; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_6 = requestAIO_3_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_101 = {in_3_a_bits_address[31:28], in_3_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_102 = {1'h0, _requestAIO_T_101}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_103 = _requestAIO_T_102 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_104 = _requestAIO_T_103; // @[Parameters.scala:137:46] wire _requestAIO_T_105 = _requestAIO_T_104 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_106 = in_3_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_107 = {1'h0, _requestAIO_T_106}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_108 = _requestAIO_T_107 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_109 = _requestAIO_T_108; // @[Parameters.scala:137:46] wire _requestAIO_T_110 = _requestAIO_T_109 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_111 = _requestAIO_T_105 | _requestAIO_T_110; // @[Xbar.scala:291:92] wire requestAIO_3_1 = _requestAIO_T_111; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_6 = requestAIO_3_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_113 = {1'h0, _requestAIO_T_112}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_114 = _requestAIO_T_113 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_115 = _requestAIO_T_114; // @[Parameters.scala:137:46] wire _requestAIO_T_116 = _requestAIO_T_115 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_117 = {in_4_a_bits_address[31:17], in_4_a_bits_address[16:0] ^ 17'h10000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_118 = {1'h0, _requestAIO_T_117}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_119 = _requestAIO_T_118 & 33'h8C011000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_120 = _requestAIO_T_119; // @[Parameters.scala:137:46] wire _requestAIO_T_121 = _requestAIO_T_120 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_122 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'hC000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_123 = {1'h0, _requestAIO_T_122}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_124 = _requestAIO_T_123 & 33'h8C000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_125 = _requestAIO_T_124; // @[Parameters.scala:137:46] wire _requestAIO_T_126 = _requestAIO_T_125 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_127 = _requestAIO_T_116 | _requestAIO_T_121; // @[Xbar.scala:291:92] wire _requestAIO_T_128 = _requestAIO_T_127 | _requestAIO_T_126; // @[Xbar.scala:291:92] wire requestAIO_4_0 = _requestAIO_T_128; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_0_valid_T_8 = requestAIO_4_0; // @[Xbar.scala:307:107, :355:54] wire [31:0] _requestAIO_T_129 = {in_4_a_bits_address[31:28], in_4_a_bits_address[27:0] ^ 28'h8000000}; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_130 = {1'h0, _requestAIO_T_129}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_131 = _requestAIO_T_130 & 33'h8C010000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_132 = _requestAIO_T_131; // @[Parameters.scala:137:46] wire _requestAIO_T_133 = _requestAIO_T_132 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _requestAIO_T_134 = in_4_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_135 = {1'h0, _requestAIO_T_134}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_136 = _requestAIO_T_135 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_137 = _requestAIO_T_136; // @[Parameters.scala:137:46] wire _requestAIO_T_138 = _requestAIO_T_137 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _requestAIO_T_139 = _requestAIO_T_133 | _requestAIO_T_138; // @[Xbar.scala:291:92] wire requestAIO_4_1 = _requestAIO_T_139; // @[Xbar.scala:291:92, :307:107] wire _portsAOI_filtered_1_valid_T_8 = requestAIO_4_1; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestCIO_T_11 = {1'h0, _requestCIO_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_16 = {1'h0, _requestCIO_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_21 = {1'h0, _requestCIO_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_26 = {1'h0, _requestCIO_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_31 = {1'h0, _requestCIO_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_36 = {1'h0, _requestCIO_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_41 = {1'h0, _requestCIO_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_46 = {1'h0, _requestCIO_T_45}; // @[Parameters.scala:137:{31,41}] wire [4:0] requestBOI_uncommonBits_5 = _requestBOI_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestBOI_T_25 = out_1_b_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestBOI_T_26 = _requestBOI_T_25 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_28 = _requestBOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_0 = _requestBOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T_2 = requestBOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_6 = _requestBOI_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestBOI_T_30 = out_1_b_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestBOI_T_35 = out_1_b_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestBOI_T_31 = _requestBOI_T_30 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_33 = _requestBOI_T_31; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_1 = _requestBOI_T_33; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_1_valid_T_2 = requestBOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestBOI_uncommonBits_7 = _requestBOI_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_36 = _requestBOI_T_35 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_38 = _requestBOI_T_36; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_2 = _requestBOI_T_38; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_2_valid_T_2 = requestBOI_1_2; // @[Xbar.scala:355:54] wire [3:0] requestBOI_uncommonBits_8 = _requestBOI_uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestBOI_T_40 = out_1_b_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestBOI_T_45 = out_1_b_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestBOI_T_41 = _requestBOI_T_40 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_43 = _requestBOI_T_41; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_3 = _requestBOI_T_43; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_3_valid_T_2 = requestBOI_1_3; // @[Xbar.scala:355:54] wire [3:0] requestBOI_uncommonBits_9 = _requestBOI_uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T_46 = _requestBOI_T_45 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_48 = _requestBOI_T_46; // @[Parameters.scala:54:{32,67}] wire requestBOI_1_4 = _requestBOI_T_48; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_4_valid_T_2 = requestBOI_1_4; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestDOI_T = out_0_d_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = _requestDOI_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_5 = out_0_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestDOI_T_10 = out_0_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_6 = _requestDOI_T_5 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_2 = _requestDOI_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_11 = _requestDOI_T_10 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_13 = _requestDOI_T_11; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_2 = _requestDOI_T_13; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_3 = _requestDOI_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestDOI_T_15 = out_0_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestDOI_T_20 = out_0_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestDOI_T_16 = _requestDOI_T_15 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_18 = _requestDOI_T_16; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_3 = _requestDOI_T_18; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_3_valid_T = requestDOI_0_3; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_4 = _requestDOI_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_21 = _requestDOI_T_20 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_23 = _requestDOI_T_21; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_4 = _requestDOI_T_23; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_4_valid_T = requestDOI_0_4; // @[Xbar.scala:355:54] wire [4:0] requestDOI_uncommonBits_5 = _requestDOI_uncommonBits_T_5[4:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _requestDOI_T_25 = out_1_d_bits_source[6:5]; // @[Xbar.scala:216:19] wire _requestDOI_T_26 = _requestDOI_T_25 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_28 = _requestDOI_T_26; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_0 = _requestDOI_T_28; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T_2 = requestDOI_1_0; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_6 = _requestDOI_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _requestDOI_T_30 = out_1_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire [4:0] _requestDOI_T_35 = out_1_d_bits_source[6:2]; // @[Xbar.scala:216:19] wire _requestDOI_T_31 = _requestDOI_T_30 == 5'h11; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_33 = _requestDOI_T_31; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_1 = _requestDOI_T_33; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_1_valid_T_2 = requestDOI_1_1; // @[Xbar.scala:355:54] wire [1:0] requestDOI_uncommonBits_7 = _requestDOI_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_36 = _requestDOI_T_35 == 5'h10; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_38 = _requestDOI_T_36; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_2 = _requestDOI_T_38; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_2_valid_T_2 = requestDOI_1_2; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_8 = _requestDOI_uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _requestDOI_T_40 = out_1_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire [2:0] _requestDOI_T_45 = out_1_d_bits_source[6:4]; // @[Xbar.scala:216:19] wire _requestDOI_T_41 = _requestDOI_T_40 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_43 = _requestDOI_T_41; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_3 = _requestDOI_T_43; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_3_valid_T_2 = requestDOI_1_3; // @[Xbar.scala:355:54] wire [3:0] requestDOI_uncommonBits_9 = _requestDOI_uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T_46 = _requestDOI_T_45 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_48 = _requestDOI_T_46; // @[Parameters.scala:54:{32,67}] wire requestDOI_1_4 = _requestDOI_T_48; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_4_valid_T_2 = requestDOI_1_4; // @[Xbar.scala:355:54] wire [3:0] requestEIO_uncommonBits_1 = _requestEIO_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_2 = _requestEIO_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_3 = _requestEIO_uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] requestEIO_uncommonBits_4 = _requestEIO_uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_6 = 27'hFFF << in_2_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_7 = _beatsAI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_8 = ~_beatsAI_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_2 = _beatsAI_decode_T_8[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_2 = in_2_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_2 = ~_beatsAI_opdata_T_2; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_2 = beatsAI_opdata_2 ? beatsAI_decode_2 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_9 = 27'hFFF << in_3_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_10 = _beatsAI_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_11 = ~_beatsAI_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_3 = _beatsAI_decode_T_11[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_3 = in_3_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_3 = ~_beatsAI_opdata_T_3; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_3 = beatsAI_opdata_3 ? beatsAI_decode_3 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsAI_decode_T_12 = 27'hFFF << in_4_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_13 = _beatsAI_decode_T_12[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_14 = ~_beatsAI_decode_T_13; // @[package.scala:243:{46,76}] wire [7:0] beatsAI_decode_4 = _beatsAI_decode_T_14[11:4]; // @[package.scala:243:46] wire _beatsAI_opdata_T_4 = in_4_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata_4 = ~_beatsAI_opdata_T_4; // @[Edges.scala:92:{28,37}] wire [7:0] beatsAI_4 = beatsAI_opdata_4 ? beatsAI_decode_4 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF << in_1_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_4 = _beatsCI_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_5 = ~_beatsCI_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_1 = _beatsCI_decode_T_5[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_1 = in_1_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_1 = beatsCI_opdata_1 ? beatsCI_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_6 = 27'hFFF << in_2_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_7 = _beatsCI_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_8 = ~_beatsCI_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_2 = _beatsCI_decode_T_8[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_2 = in_2_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_2 = beatsCI_opdata_2 ? beatsCI_decode_2 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_9 = 27'hFFF << in_3_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_10 = _beatsCI_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_11 = ~_beatsCI_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_3 = _beatsCI_decode_T_11[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_3 = in_3_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_3 = beatsCI_opdata_3 ? beatsCI_decode_3 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsCI_decode_T_12 = 27'hFFF << in_4_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_13 = _beatsCI_decode_T_12[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_14 = ~_beatsCI_decode_T_13; // @[package.scala:243:{46,76}] wire [7:0] beatsCI_decode_4 = _beatsCI_decode_T_14[11:4]; // @[package.scala:243:46] wire beatsCI_opdata_4 = in_4_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [7:0] beatsCI_4 = beatsCI_opdata_4 ? beatsCI_decode_4 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [20:0] _beatsDO_decode_T_3 = 21'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [1:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:4]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T | _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_1; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_3 = in_1_a_valid & _portsAOI_filtered_0_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_3 = in_1_a_valid & _portsAOI_filtered_1_valid_T_2; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_1_valid = _portsAOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_1_a_ready_T = requestAIO_1_0 & portsAOI_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_1 = requestAIO_1_1 & portsAOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_1_a_ready_T_2 = _portsAOI_in_1_a_ready_T | _portsAOI_in_1_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_1_a_ready_WIRE = _portsAOI_in_1_a_ready_T_2; // @[Mux.scala:30:73] assign in_1_a_ready = _portsAOI_in_1_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_2; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:355:40] wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_5 = in_2_a_valid & _portsAOI_filtered_0_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_5 = in_2_a_valid & _portsAOI_filtered_1_valid_T_4; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_2_1_valid = _portsAOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_2_a_ready_T = requestAIO_2_0 & portsAOI_filtered_2_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_1 = requestAIO_2_1 & portsAOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_2_a_ready_T_2 = _portsAOI_in_2_a_ready_T | _portsAOI_in_2_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_2_a_ready_WIRE = _portsAOI_in_2_a_ready_T_2; // @[Mux.scala:30:73] assign in_2_a_ready = _portsAOI_in_2_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_3; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_3; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:355:40] wire portsAOI_filtered_3_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_7 = in_3_a_valid & _portsAOI_filtered_0_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_3_0_valid = _portsAOI_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_7 = in_3_a_valid & _portsAOI_filtered_1_valid_T_6; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_3_1_valid = _portsAOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_3_a_ready_T = requestAIO_3_0 & portsAOI_filtered_3_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_3_a_ready_T_1 = requestAIO_3_1 & portsAOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_3_a_ready_T_2 = _portsAOI_in_3_a_ready_T | _portsAOI_in_3_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_3_a_ready_WIRE = _portsAOI_in_3_a_ready_T_2; // @[Mux.scala:30:73] assign in_3_a_ready = _portsAOI_in_3_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_4; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_4; // @[Arbiter.scala:94:31] wire _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:355:40] wire portsAOI_filtered_4_0_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_1_ready; // @[Xbar.scala:352:24] wire portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign _portsAOI_filtered_0_valid_T_9 = in_4_a_valid & _portsAOI_filtered_0_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_4_0_valid = _portsAOI_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_9 = in_4_a_valid & _portsAOI_filtered_1_valid_T_8; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_4_1_valid = _portsAOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_4_a_ready_T = requestAIO_4_0 & portsAOI_filtered_4_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_4_a_ready_T_1 = requestAIO_4_1 & portsAOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_4_a_ready_T_2 = _portsAOI_in_4_a_ready_T | _portsAOI_in_4_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_4_a_ready_WIRE = _portsAOI_in_4_a_ready_T_2; // @[Mux.scala:30:73] assign in_4_a_ready = _portsAOI_in_4_a_ready_WIRE; // @[Mux.scala:30:73] wire _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] assign in_1_b_valid = portsBIO_filtered_1_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_param = portsBIO_filtered_1_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_source = portsBIO_filtered_1_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_b_bits_address = portsBIO_filtered_1_1_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] assign in_2_b_valid = portsBIO_filtered_1_2_valid; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_param = portsBIO_filtered_1_2_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_source = portsBIO_filtered_1_2_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_2_b_bits_address = portsBIO_filtered_1_2_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_3_valid_T_3; // @[Xbar.scala:355:40] assign in_3_b_valid = portsBIO_filtered_1_3_valid; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_param = portsBIO_filtered_1_3_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_source = portsBIO_filtered_1_3_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_3_b_bits_address = portsBIO_filtered_1_3_bits_address; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_4_valid_T_3; // @[Xbar.scala:355:40] assign in_4_b_valid = portsBIO_filtered_1_4_valid; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_param = portsBIO_filtered_1_4_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_source = portsBIO_filtered_1_4_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_4_b_bits_address = portsBIO_filtered_1_4_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_3 = out_1_b_valid & _portsBIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_0_valid = _portsBIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_3 = out_1_b_valid & _portsBIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_1_valid = _portsBIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_2_valid_T_3 = out_1_b_valid & _portsBIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_2_valid = _portsBIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_3_valid_T_3 = out_1_b_valid & _portsBIO_filtered_3_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_3_valid = _portsBIO_filtered_3_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_4_valid_T_3 = out_1_b_valid & _portsBIO_filtered_4_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_4_valid = _portsBIO_filtered_4_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_1_b_ready_T_1 = requestBOI_1_1 & portsBIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_5 = _portsBIO_out_1_b_ready_T_1; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_2 = requestBOI_1_2 & portsBIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_3 = requestBOI_1_3 & portsBIO_filtered_1_3_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_4 = requestBOI_1_4 & portsBIO_filtered_1_4_ready; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_6 = _portsBIO_out_1_b_ready_T_5 | _portsBIO_out_1_b_ready_T_2; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_7 = _portsBIO_out_1_b_ready_T_6 | _portsBIO_out_1_b_ready_T_3; // @[Mux.scala:30:73] wire _portsBIO_out_1_b_ready_T_8 = _portsBIO_out_1_b_ready_T_7 | _portsBIO_out_1_b_ready_T_4; // @[Mux.scala:30:73] assign _portsBIO_out_1_b_ready_WIRE = _portsBIO_out_1_b_ready_T_8; // @[Mux.scala:30:73] assign out_1_b_ready = _portsBIO_out_1_b_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_5; // @[Arbiter.scala:94:31] wire _portsCOI_in_1_c_ready_T_1 = portsCOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_1_0_valid = _portsCOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_1_1_valid = _portsCOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_1_c_ready_T_2 = _portsCOI_in_1_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_1_c_ready_WIRE = _portsCOI_in_1_c_ready_T_2; // @[Mux.scala:30:73] assign in_1_c_ready = _portsCOI_in_1_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_6; // @[Arbiter.scala:94:31] wire _portsCOI_in_2_c_ready_T_1 = portsCOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_2_0_valid = _portsCOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_2_1_valid = _portsCOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_2_c_ready_T_2 = _portsCOI_in_2_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_2_c_ready_WIRE = _portsCOI_in_2_c_ready_T_2; // @[Mux.scala:30:73] assign in_2_c_ready = _portsCOI_in_2_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_7; // @[Arbiter.scala:94:31] wire _portsCOI_in_3_c_ready_T_1 = portsCOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_3_0_valid = _portsCOI_filtered_0_valid_T_7; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_3_1_valid = _portsCOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_3_c_ready_T_2 = _portsCOI_in_3_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_3_c_ready_WIRE = _portsCOI_in_3_c_ready_T_2; // @[Mux.scala:30:73] assign in_3_c_ready = _portsCOI_in_3_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_8; // @[Arbiter.scala:94:31] wire _portsCOI_in_4_c_ready_T_1 = portsCOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire portsCOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign portsCOI_filtered_4_0_valid = _portsCOI_filtered_0_valid_T_9; // @[Xbar.scala:352:24, :355:40] assign portsCOI_filtered_4_1_valid = _portsCOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsCOI_in_4_c_ready_T_2 = _portsCOI_in_4_c_ready_T_1; // @[Mux.scala:30:73] assign _portsCOI_in_4_c_ready_WIRE = _portsCOI_in_4_c_ready_T_2; // @[Mux.scala:30:73] assign in_4_c_ready = _portsCOI_in_4_c_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_5; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_13; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_2_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_3_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:355:40] wire _filtered_4_ready_T; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_3_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_4_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_3_valid_T_1 = out_0_d_valid & _portsDIO_filtered_3_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_3_valid = _portsDIO_filtered_3_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_4_valid_T_1 = out_0_d_valid & _portsDIO_filtered_4_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_4_valid = _portsDIO_filtered_4_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2 & portsDIO_filtered_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_3 = requestDOI_0_3 & portsDIO_filtered_3_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_4 = requestDOI_0_4 & portsDIO_filtered_4_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_5 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_6 = _portsDIO_out_0_d_ready_T_5 | _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_7 = _portsDIO_out_0_d_ready_T_6 | _portsDIO_out_0_d_ready_T_3; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_8 = _portsDIO_out_0_d_ready_T_7 | _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_8; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T_6; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_1_ready_T_14; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_2_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_3_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:355:40] wire _filtered_4_ready_T_1; // @[Arbiter.scala:94:31] wire _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_3_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_4_ready; // @[Xbar.scala:352:24] wire portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24] assign _portsDIO_filtered_0_valid_T_3 = out_1_d_valid & _portsDIO_filtered_0_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_3 = out_1_d_valid & _portsDIO_filtered_1_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_1_valid = _portsDIO_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_2_valid_T_3 = out_1_d_valid & _portsDIO_filtered_2_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_2_valid = _portsDIO_filtered_2_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_3_valid_T_3 = out_1_d_valid & _portsDIO_filtered_3_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_3_valid = _portsDIO_filtered_3_valid_T_3; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_4_valid_T_3 = out_1_d_valid & _portsDIO_filtered_4_valid_T_2; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_4_valid = _portsDIO_filtered_4_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_1_d_ready_T = requestDOI_1_0 & portsDIO_filtered_1_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_1 = requestDOI_1_1 & portsDIO_filtered_1_1_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_2 = requestDOI_1_2 & portsDIO_filtered_1_2_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_3 = requestDOI_1_3 & portsDIO_filtered_1_3_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_4 = requestDOI_1_4 & portsDIO_filtered_1_4_ready; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_5 = _portsDIO_out_1_d_ready_T | _portsDIO_out_1_d_ready_T_1; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_6 = _portsDIO_out_1_d_ready_T_5 | _portsDIO_out_1_d_ready_T_2; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_7 = _portsDIO_out_1_d_ready_T_6 | _portsDIO_out_1_d_ready_T_3; // @[Mux.scala:30:73] wire _portsDIO_out_1_d_ready_T_8 = _portsDIO_out_1_d_ready_T_7 | _portsDIO_out_1_d_ready_T_4; // @[Mux.scala:30:73] assign _portsDIO_out_1_d_ready_WIRE = _portsDIO_out_1_d_ready_T_8; // @[Mux.scala:30:73] assign out_1_d_ready = _portsDIO_out_1_d_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_9; // @[Arbiter.scala:94:31] wire _portsEOI_in_1_e_ready_T_1 = portsEOI_filtered_1_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_1_1_valid = _portsEOI_filtered_1_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_1_e_ready_T_2 = _portsEOI_in_1_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_1_e_ready_WIRE = _portsEOI_in_1_e_ready_T_2; // @[Mux.scala:30:73] assign in_1_e_ready = _portsEOI_in_1_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_10; // @[Arbiter.scala:94:31] wire _portsEOI_in_2_e_ready_T_1 = portsEOI_filtered_2_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_valid = _portsEOI_filtered_1_valid_T_5; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_2_e_ready_T_2 = _portsEOI_in_2_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_2_e_ready_WIRE = _portsEOI_in_2_e_ready_T_2; // @[Mux.scala:30:73] assign in_2_e_ready = _portsEOI_in_2_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_11; // @[Arbiter.scala:94:31] wire _portsEOI_in_3_e_ready_T_1 = portsEOI_filtered_3_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_3_1_valid = _portsEOI_filtered_1_valid_T_7; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_3_e_ready_T_2 = _portsEOI_in_3_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_3_e_ready_WIRE = _portsEOI_in_3_e_ready_T_2; // @[Mux.scala:30:73] assign in_3_e_ready = _portsEOI_in_3_e_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_1_ready_T_12; // @[Arbiter.scala:94:31] wire _portsEOI_in_4_e_ready_T_1 = portsEOI_filtered_4_1_ready; // @[Mux.scala:30:73] wire portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] assign portsEOI_filtered_4_1_valid = _portsEOI_filtered_1_valid_T_9; // @[Xbar.scala:352:24, :355:40] wire _portsEOI_in_4_e_ready_T_2 = _portsEOI_in_4_e_ready_T_1; // @[Mux.scala:30:73] assign _portsEOI_in_4_e_ready_WIRE = _portsEOI_in_4_e_ready_T_2; // @[Mux.scala:30:73] assign in_4_e_ready = _portsEOI_in_4_e_ready_WIRE; // @[Mux.scala:30:73] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_hi = {portsAOI_filtered_4_0_valid, portsAOI_filtered_3_0_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_hi = {readys_hi_hi, portsAOI_filtered_2_0_valid}; // @[Xbar.scala:352:24] wire [4:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51] wire [4:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [4:0] readys_mask; // @[Arbiter.scala:23:23] wire [4:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [4:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [9:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [8:0] _readys_unready_T = readys_filter[9:1]; // @[package.scala:262:48] wire [9:0] _readys_unready_T_1 = {readys_filter[9], readys_filter[8:0] | _readys_unready_T}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_2 = _readys_unready_T_1[9:2]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_3 = {_readys_unready_T_1[9:8], _readys_unready_T_1[7:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_4 = _readys_unready_T_3[9:4]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_5 = {_readys_unready_T_3[9:6], _readys_unready_T_3[5:0] | _readys_unready_T_4}; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_6 = _readys_unready_T_5; // @[package.scala:262:43, :263:17] wire [8:0] _readys_unready_T_7 = _readys_unready_T_6[9:1]; // @[package.scala:263:17] wire [9:0] _readys_unready_T_8 = {readys_mask, 5'h0}; // @[Arbiter.scala:23:23, :25:66] wire [9:0] readys_unready = {1'h0, _readys_unready_T_7} | _readys_unready_T_8; // @[Arbiter.scala:25:{52,58,66}] wire [4:0] _readys_readys_T = readys_unready[9:5]; // @[Arbiter.scala:25:58, :26:29] wire [4:0] _readys_readys_T_1 = readys_unready[4:0]; // @[Arbiter.scala:25:58, :26:48] wire [4:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [4:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [4:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [4:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [5:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [4:0] _readys_mask_T_2 = _readys_mask_T_1[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [6:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_5 = _readys_mask_T_4[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}] wire [8:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_8 = _readys_mask_T_7[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_8; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_10 = _readys_mask_T_9; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}] wire _readys_T_11 = _readys_T_7[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_3 = _readys_T_11; // @[Arbiter.scala:68:{27,76}] wire _readys_T_12 = _readys_T_7[4]; // @[Arbiter.scala:30:11, :68:76] wire readys_4 = _readys_T_12; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_3 & portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_4 & portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3 = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4 = prefixOR_3 | winner_3; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_4 | winner_4; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0 = winner_0 ? beatsAI_0 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1 = winner_1 ? beatsAI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2 = winner_2 ? beatsAI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3 = winner_3 ? beatsAI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_4 = winner_4 ? beatsAI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_1 = _initBeats_T | maskedBeats_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_2 = _initBeats_T_1 | maskedBeats_3; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats = _initBeats_T_2 | maskedBeats_4; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = out_0_a_ready & out_0_a_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {8'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_2 = _beatsLeft_T_1[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] reg state_3; // @[Arbiter.scala:88:26] reg state_4; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3 = idle ? winner_3 : state_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4 = idle ? winner_4 : state_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T = out_0_a_ready & allowed_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_0_ready = _filtered_0_ready_T; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_1 = out_0_a_ready & allowed_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_0_ready = _filtered_0_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_2 = out_0_a_ready & allowed_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_0_ready = _filtered_0_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_3 = out_0_a_ready & allowed_3; // @[Xbar.scala:216:19] assign portsAOI_filtered_3_0_ready = _filtered_0_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_4 = out_0_a_ready & allowed_4; // @[Xbar.scala:216:19] assign portsAOI_filtered_4_0_ready = _filtered_0_ready_T_4; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_1 = _out_0_a_valid_T | portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_2 = _out_0_a_valid_T_1 | portsAOI_filtered_3_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_3 = _out_0_a_valid_T_2 | portsAOI_filtered_4_0_valid; // @[Xbar.scala:352:24] wire _out_0_a_valid_T_4 = state_0 & portsAOI_filtered_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_5 = state_1 & portsAOI_filtered_1_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_6 = state_2 & portsAOI_filtered_2_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_7 = state_3 & portsAOI_filtered_3_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_8 = state_4 & portsAOI_filtered_4_0_valid; // @[Mux.scala:30:73] wire _out_0_a_valid_T_9 = _out_0_a_valid_T_4 | _out_0_a_valid_T_5; // @[Mux.scala:30:73] wire _out_0_a_valid_T_10 = _out_0_a_valid_T_9 | _out_0_a_valid_T_6; // @[Mux.scala:30:73] wire _out_0_a_valid_T_11 = _out_0_a_valid_T_10 | _out_0_a_valid_T_7; // @[Mux.scala:30:73] wire _out_0_a_valid_T_12 = _out_0_a_valid_T_11 | _out_0_a_valid_T_8; // @[Mux.scala:30:73] wire _out_0_a_valid_WIRE = _out_0_a_valid_T_12; // @[Mux.scala:30:73] assign _out_0_a_valid_T_13 = idle ? _out_0_a_valid_T_3 : _out_0_a_valid_WIRE; // @[Mux.scala:30:73] assign out_0_a_valid = _out_0_a_valid_T_13; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_0_a_bits_opcode = _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_0_a_bits_param = _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_0_a_bits_size = _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_0_a_bits_source = _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_0_a_bits_address = _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_0_a_bits_mask = _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_0_a_bits_data = _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_0_a_bits_corrupt = _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T = muxState_0 & portsAOI_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = muxState_1 & portsAOI_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = muxState_2 & portsAOI_filtered_2_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_3 = muxState_3 & portsAOI_filtered_3_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_4 = muxState_4 & portsAOI_filtered_4_0_bits_corrupt; // @[Mux.scala:30:73] wire _out_0_a_bits_T_5 = _out_0_a_bits_T | _out_0_a_bits_T_1; // @[Mux.scala:30:73] wire _out_0_a_bits_T_6 = _out_0_a_bits_T_5 | _out_0_a_bits_T_2; // @[Mux.scala:30:73] wire _out_0_a_bits_T_7 = _out_0_a_bits_T_6 | _out_0_a_bits_T_3; // @[Mux.scala:30:73] wire _out_0_a_bits_T_8 = _out_0_a_bits_T_7 | _out_0_a_bits_T_4; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_1 = _out_0_a_bits_T_8; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_corrupt = _out_0_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_9 = muxState_0 ? portsAOI_filtered_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_10 = muxState_1 ? portsAOI_filtered_1_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_11 = muxState_2 ? portsAOI_filtered_2_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_12 = muxState_3 ? portsAOI_filtered_3_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_13 = muxState_4 ? portsAOI_filtered_4_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_14 = _out_0_a_bits_T_9 | _out_0_a_bits_T_10; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_15 = _out_0_a_bits_T_14 | _out_0_a_bits_T_11; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_16 = _out_0_a_bits_T_15 | _out_0_a_bits_T_12; // @[Mux.scala:30:73] wire [127:0] _out_0_a_bits_T_17 = _out_0_a_bits_T_16 | _out_0_a_bits_T_13; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_2 = _out_0_a_bits_T_17; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_data = _out_0_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_18 = muxState_0 ? portsAOI_filtered_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_19 = muxState_1 ? portsAOI_filtered_1_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_20 = muxState_2 ? portsAOI_filtered_2_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_21 = muxState_3 ? portsAOI_filtered_3_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_22 = muxState_4 ? portsAOI_filtered_4_0_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_23 = _out_0_a_bits_T_18 | _out_0_a_bits_T_19; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_24 = _out_0_a_bits_T_23 | _out_0_a_bits_T_20; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_25 = _out_0_a_bits_T_24 | _out_0_a_bits_T_21; // @[Mux.scala:30:73] wire [15:0] _out_0_a_bits_T_26 = _out_0_a_bits_T_25 | _out_0_a_bits_T_22; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_3 = _out_0_a_bits_T_26; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_mask = _out_0_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_27 = muxState_0 ? portsAOI_filtered_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_28 = muxState_1 ? portsAOI_filtered_1_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_29 = muxState_2 ? portsAOI_filtered_2_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_30 = muxState_3 ? portsAOI_filtered_3_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_31 = muxState_4 ? portsAOI_filtered_4_0_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_32 = _out_0_a_bits_T_27 | _out_0_a_bits_T_28; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_33 = _out_0_a_bits_T_32 | _out_0_a_bits_T_29; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_34 = _out_0_a_bits_T_33 | _out_0_a_bits_T_30; // @[Mux.scala:30:73] wire [31:0] _out_0_a_bits_T_35 = _out_0_a_bits_T_34 | _out_0_a_bits_T_31; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_6 = _out_0_a_bits_T_35; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_address = _out_0_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_36 = muxState_0 ? portsAOI_filtered_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_37 = muxState_1 ? portsAOI_filtered_1_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_38 = muxState_2 ? portsAOI_filtered_2_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_39 = muxState_3 ? portsAOI_filtered_3_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_40 = muxState_4 ? portsAOI_filtered_4_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_41 = _out_0_a_bits_T_36 | _out_0_a_bits_T_37; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_42 = _out_0_a_bits_T_41 | _out_0_a_bits_T_38; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_43 = _out_0_a_bits_T_42 | _out_0_a_bits_T_39; // @[Mux.scala:30:73] wire [6:0] _out_0_a_bits_T_44 = _out_0_a_bits_T_43 | _out_0_a_bits_T_40; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_7 = _out_0_a_bits_T_44; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_source = _out_0_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_45 = muxState_0 ? portsAOI_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_46 = muxState_1 ? portsAOI_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_47 = muxState_2 ? portsAOI_filtered_2_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_48 = muxState_3 ? portsAOI_filtered_3_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_49 = muxState_4 ? portsAOI_filtered_4_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_50 = _out_0_a_bits_T_45 | _out_0_a_bits_T_46; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_51 = _out_0_a_bits_T_50 | _out_0_a_bits_T_47; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_52 = _out_0_a_bits_T_51 | _out_0_a_bits_T_48; // @[Mux.scala:30:73] wire [3:0] _out_0_a_bits_T_53 = _out_0_a_bits_T_52 | _out_0_a_bits_T_49; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_8 = _out_0_a_bits_T_53; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_size = _out_0_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_54 = muxState_0 ? portsAOI_filtered_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_55 = muxState_1 ? portsAOI_filtered_1_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_56 = muxState_2 ? portsAOI_filtered_2_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_57 = muxState_3 ? portsAOI_filtered_3_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_58 = muxState_4 ? portsAOI_filtered_4_0_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_59 = _out_0_a_bits_T_54 | _out_0_a_bits_T_55; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_60 = _out_0_a_bits_T_59 | _out_0_a_bits_T_56; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_61 = _out_0_a_bits_T_60 | _out_0_a_bits_T_57; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_62 = _out_0_a_bits_T_61 | _out_0_a_bits_T_58; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_9 = _out_0_a_bits_T_62; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_param = _out_0_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_63 = muxState_0 ? portsAOI_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_64 = muxState_1 ? portsAOI_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_65 = muxState_2 ? portsAOI_filtered_2_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_66 = muxState_3 ? portsAOI_filtered_3_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_67 = muxState_4 ? portsAOI_filtered_4_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_68 = _out_0_a_bits_T_63 | _out_0_a_bits_T_64; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_69 = _out_0_a_bits_T_68 | _out_0_a_bits_T_65; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_70 = _out_0_a_bits_T_69 | _out_0_a_bits_T_66; // @[Mux.scala:30:73] wire [2:0] _out_0_a_bits_T_71 = _out_0_a_bits_T_70 | _out_0_a_bits_T_67; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_10 = _out_0_a_bits_T_71; // @[Mux.scala:30:73] assign _out_0_a_bits_WIRE_opcode = _out_0_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & out_1_a_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo_1 = {portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_hi_1 = {portsAOI_filtered_4_1_valid, portsAOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [2:0] readys_hi_1 = {readys_hi_hi_1, portsAOI_filtered_2_1_valid}; // @[Xbar.scala:352:24] wire [4:0] _readys_T_13 = {readys_hi_1, readys_lo_1}; // @[Arbiter.scala:68:51] wire [4:0] readys_valid_1 = _readys_T_13; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_14 = readys_valid_1 == _readys_T_13; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_16 = ~_readys_T_15; // @[Arbiter.scala:22:12] wire _readys_T_17 = ~_readys_T_14; // @[Arbiter.scala:22:{12,19}] reg [4:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [4:0] _readys_filter_T_2 = ~readys_mask_1; // @[Arbiter.scala:23:23, :24:30] wire [4:0] _readys_filter_T_3 = readys_valid_1 & _readys_filter_T_2; // @[Arbiter.scala:21:23, :24:{28,30}] wire [9:0] readys_filter_1 = {_readys_filter_T_3, readys_valid_1}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [8:0] _readys_unready_T_9 = readys_filter_1[9:1]; // @[package.scala:262:48] wire [9:0] _readys_unready_T_10 = {readys_filter_1[9], readys_filter_1[8:0] | _readys_unready_T_9}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_11 = _readys_unready_T_10[9:2]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_12 = {_readys_unready_T_10[9:8], _readys_unready_T_10[7:0] | _readys_unready_T_11}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_13 = _readys_unready_T_12[9:4]; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_14 = {_readys_unready_T_12[9:6], _readys_unready_T_12[5:0] | _readys_unready_T_13}; // @[package.scala:262:{43,48}] wire [9:0] _readys_unready_T_15 = _readys_unready_T_14; // @[package.scala:262:43, :263:17] wire [8:0] _readys_unready_T_16 = _readys_unready_T_15[9:1]; // @[package.scala:263:17] wire [9:0] _readys_unready_T_17 = {readys_mask_1, 5'h0}; // @[Arbiter.scala:23:23, :25:66] wire [9:0] readys_unready_1 = {1'h0, _readys_unready_T_16} | _readys_unready_T_17; // @[Arbiter.scala:25:{52,58,66}] wire [4:0] _readys_readys_T_3 = readys_unready_1[9:5]; // @[Arbiter.scala:25:58, :26:29] wire [4:0] _readys_readys_T_4 = readys_unready_1[4:0]; // @[Arbiter.scala:25:58, :26:48] wire [4:0] _readys_readys_T_5 = _readys_readys_T_3 & _readys_readys_T_4; // @[Arbiter.scala:26:{29,39,48}] wire [4:0] readys_readys_1 = ~_readys_readys_T_5; // @[Arbiter.scala:26:{18,39}] wire [4:0] _readys_T_20 = readys_readys_1; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_18 = |readys_valid_1; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_19 = latch_1 & _readys_T_18; // @[Arbiter.scala:27:{18,27}, :62:24] wire [4:0] _readys_mask_T_11 = readys_readys_1 & readys_valid_1; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [5:0] _readys_mask_T_12 = {_readys_mask_T_11, 1'h0}; // @[package.scala:253:48] wire [4:0] _readys_mask_T_13 = _readys_mask_T_12[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_14 = _readys_mask_T_11 | _readys_mask_T_13; // @[package.scala:253:{43,53}] wire [6:0] _readys_mask_T_15 = {_readys_mask_T_14, 2'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_16 = _readys_mask_T_15[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_17 = _readys_mask_T_14 | _readys_mask_T_16; // @[package.scala:253:{43,53}] wire [8:0] _readys_mask_T_18 = {_readys_mask_T_17, 4'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_mask_T_19 = _readys_mask_T_18[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_mask_T_20 = _readys_mask_T_17 | _readys_mask_T_19; // @[package.scala:253:{43,53}] wire [4:0] _readys_mask_T_21 = _readys_mask_T_20; // @[package.scala:253:43, :254:17] wire _readys_T_21 = _readys_T_20[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_0 = _readys_T_21; // @[Arbiter.scala:68:{27,76}] wire _readys_T_22 = _readys_T_20[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_1 = _readys_T_22; // @[Arbiter.scala:68:{27,76}] wire _readys_T_23 = _readys_T_20[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_2 = _readys_T_23; // @[Arbiter.scala:68:{27,76}] wire _readys_T_24 = _readys_T_20[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_3 = _readys_T_24; // @[Arbiter.scala:68:{27,76}] wire _readys_T_25 = _readys_T_20[4]; // @[Arbiter.scala:30:11, :68:76] wire readys_1_4 = _readys_T_25; // @[Arbiter.scala:68:{27,76}] wire _winner_T_5 = readys_1_0 & portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_1_0 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire _winner_T_6 = readys_1_1 & portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_1_1 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_1_2 & portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_1_2 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire _winner_T_8 = readys_1_3 & portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_1_3 = _winner_T_8; // @[Arbiter.scala:71:{27,69}] wire _winner_T_9 = readys_1_4 & portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_1_4 = _winner_T_9; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_1 = prefixOR_2_1 | winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4_1 = prefixOR_3_1 | winner_1_3; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_4_1 | winner_1_4; // @[Arbiter.scala:71:27, :76:48] wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_1 = winner_1_0 ? beatsAI_0 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1_1 = winner_1_1 ? beatsAI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2_1 = winner_1_2 ? beatsAI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3_1 = winner_1_3 ? beatsAI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_4_1 = winner_1_4 ? beatsAI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T_3 = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_4 = _initBeats_T_3 | maskedBeats_2_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_5 = _initBeats_T_4 | maskedBeats_3_1; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats_1 = _initBeats_T_5 | maskedBeats_4_1; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_4 = out_1_a_ready & out_1_a_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_5 = {1'h0, beatsLeft_1} - {8'h0, _beatsLeft_T_4}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_6 = _beatsLeft_T_5[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_7 = latch_1 ? initBeats_1 : _beatsLeft_T_6; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] reg state_1_2; // @[Arbiter.scala:88:26] reg state_1_3; // @[Arbiter.scala:88:26] reg state_1_4; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_3 = idle_1 ? winner_1_3 : state_1_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1_4 = idle_1 ? winner_1_4 : state_1_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_3 = idle_1 ? readys_1_3 : state_1_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1_4 = idle_1 ? readys_1_4 : state_1_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T = out_1_a_ready & allowed_1_0; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_ready = _filtered_1_ready_T; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_1 = out_1_a_ready & allowed_1_1; // @[Xbar.scala:216:19] assign portsAOI_filtered_1_1_ready = _filtered_1_ready_T_1; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_2 = out_1_a_ready & allowed_1_2; // @[Xbar.scala:216:19] assign portsAOI_filtered_2_1_ready = _filtered_1_ready_T_2; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_3 = out_1_a_ready & allowed_1_3; // @[Xbar.scala:216:19] assign portsAOI_filtered_3_1_ready = _filtered_1_ready_T_3; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_4 = out_1_a_ready & allowed_1_4; // @[Xbar.scala:216:19] assign portsAOI_filtered_4_1_ready = _filtered_1_ready_T_4; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_1 = _out_1_a_valid_T | portsAOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_2 = _out_1_a_valid_T_1 | portsAOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_3 = _out_1_a_valid_T_2 | portsAOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_a_valid_T_4 = state_1_0 & portsAOI_filtered_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_5 = state_1_1 & portsAOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_6 = state_1_2 & portsAOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_7 = state_1_3 & portsAOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_8 = state_1_4 & portsAOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_a_valid_T_9 = _out_1_a_valid_T_4 | _out_1_a_valid_T_5; // @[Mux.scala:30:73] wire _out_1_a_valid_T_10 = _out_1_a_valid_T_9 | _out_1_a_valid_T_6; // @[Mux.scala:30:73] wire _out_1_a_valid_T_11 = _out_1_a_valid_T_10 | _out_1_a_valid_T_7; // @[Mux.scala:30:73] wire _out_1_a_valid_T_12 = _out_1_a_valid_T_11 | _out_1_a_valid_T_8; // @[Mux.scala:30:73] wire _out_1_a_valid_WIRE = _out_1_a_valid_T_12; // @[Mux.scala:30:73] assign _out_1_a_valid_T_13 = idle_1 ? _out_1_a_valid_T_3 : _out_1_a_valid_WIRE; // @[Mux.scala:30:73] assign out_1_a_valid = _out_1_a_valid_T_13; // @[Xbar.scala:216:19] wire [2:0] _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] assign out_1_a_bits_opcode = _out_1_a_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_a_bits_param = _out_1_a_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_a_bits_size = _out_1_a_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_a_bits_source = _out_1_a_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_a_bits_address = _out_1_a_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] assign out_1_a_bits_mask = _out_1_a_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_a_bits_data = _out_1_a_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_a_bits_corrupt = _out_1_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T = muxState_1_0 & portsAOI_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_1 = muxState_1_1 & portsAOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_2 = muxState_1_2 & portsAOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_3 = muxState_1_3 & portsAOI_filtered_3_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_4 = muxState_1_4 & portsAOI_filtered_4_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_a_bits_T_5 = _out_1_a_bits_T | _out_1_a_bits_T_1; // @[Mux.scala:30:73] wire _out_1_a_bits_T_6 = _out_1_a_bits_T_5 | _out_1_a_bits_T_2; // @[Mux.scala:30:73] wire _out_1_a_bits_T_7 = _out_1_a_bits_T_6 | _out_1_a_bits_T_3; // @[Mux.scala:30:73] wire _out_1_a_bits_T_8 = _out_1_a_bits_T_7 | _out_1_a_bits_T_4; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_1 = _out_1_a_bits_T_8; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_corrupt = _out_1_a_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_9 = muxState_1_0 ? portsAOI_filtered_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_10 = muxState_1_1 ? portsAOI_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_11 = muxState_1_2 ? portsAOI_filtered_2_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_12 = muxState_1_3 ? portsAOI_filtered_3_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_13 = muxState_1_4 ? portsAOI_filtered_4_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_14 = _out_1_a_bits_T_9 | _out_1_a_bits_T_10; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_15 = _out_1_a_bits_T_14 | _out_1_a_bits_T_11; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_16 = _out_1_a_bits_T_15 | _out_1_a_bits_T_12; // @[Mux.scala:30:73] wire [127:0] _out_1_a_bits_T_17 = _out_1_a_bits_T_16 | _out_1_a_bits_T_13; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_2 = _out_1_a_bits_T_17; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_data = _out_1_a_bits_WIRE_2; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_18 = muxState_1_0 ? portsAOI_filtered_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_19 = muxState_1_1 ? portsAOI_filtered_1_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_20 = muxState_1_2 ? portsAOI_filtered_2_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_21 = muxState_1_3 ? portsAOI_filtered_3_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_22 = muxState_1_4 ? portsAOI_filtered_4_1_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_23 = _out_1_a_bits_T_18 | _out_1_a_bits_T_19; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_24 = _out_1_a_bits_T_23 | _out_1_a_bits_T_20; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_25 = _out_1_a_bits_T_24 | _out_1_a_bits_T_21; // @[Mux.scala:30:73] wire [15:0] _out_1_a_bits_T_26 = _out_1_a_bits_T_25 | _out_1_a_bits_T_22; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_3 = _out_1_a_bits_T_26; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_mask = _out_1_a_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_27 = muxState_1_0 ? portsAOI_filtered_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_28 = muxState_1_1 ? portsAOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_29 = muxState_1_2 ? portsAOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_30 = muxState_1_3 ? portsAOI_filtered_3_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_31 = muxState_1_4 ? portsAOI_filtered_4_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_32 = _out_1_a_bits_T_27 | _out_1_a_bits_T_28; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_33 = _out_1_a_bits_T_32 | _out_1_a_bits_T_29; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_34 = _out_1_a_bits_T_33 | _out_1_a_bits_T_30; // @[Mux.scala:30:73] wire [31:0] _out_1_a_bits_T_35 = _out_1_a_bits_T_34 | _out_1_a_bits_T_31; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_6 = _out_1_a_bits_T_35; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_address = _out_1_a_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_36 = muxState_1_0 ? portsAOI_filtered_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_37 = muxState_1_1 ? portsAOI_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_38 = muxState_1_2 ? portsAOI_filtered_2_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_39 = muxState_1_3 ? portsAOI_filtered_3_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_40 = muxState_1_4 ? portsAOI_filtered_4_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_41 = _out_1_a_bits_T_36 | _out_1_a_bits_T_37; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_42 = _out_1_a_bits_T_41 | _out_1_a_bits_T_38; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_43 = _out_1_a_bits_T_42 | _out_1_a_bits_T_39; // @[Mux.scala:30:73] wire [6:0] _out_1_a_bits_T_44 = _out_1_a_bits_T_43 | _out_1_a_bits_T_40; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_7 = _out_1_a_bits_T_44; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_source = _out_1_a_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_45 = muxState_1_0 ? portsAOI_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_46 = muxState_1_1 ? portsAOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_47 = muxState_1_2 ? portsAOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_48 = muxState_1_3 ? portsAOI_filtered_3_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_49 = muxState_1_4 ? portsAOI_filtered_4_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_50 = _out_1_a_bits_T_45 | _out_1_a_bits_T_46; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_51 = _out_1_a_bits_T_50 | _out_1_a_bits_T_47; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_52 = _out_1_a_bits_T_51 | _out_1_a_bits_T_48; // @[Mux.scala:30:73] wire [3:0] _out_1_a_bits_T_53 = _out_1_a_bits_T_52 | _out_1_a_bits_T_49; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_8 = _out_1_a_bits_T_53; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_size = _out_1_a_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_54 = muxState_1_0 ? portsAOI_filtered_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_55 = muxState_1_1 ? portsAOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_56 = muxState_1_2 ? portsAOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_57 = muxState_1_3 ? portsAOI_filtered_3_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_58 = muxState_1_4 ? portsAOI_filtered_4_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_59 = _out_1_a_bits_T_54 | _out_1_a_bits_T_55; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_60 = _out_1_a_bits_T_59 | _out_1_a_bits_T_56; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_61 = _out_1_a_bits_T_60 | _out_1_a_bits_T_57; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_62 = _out_1_a_bits_T_61 | _out_1_a_bits_T_58; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_9 = _out_1_a_bits_T_62; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_param = _out_1_a_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_63 = muxState_1_0 ? portsAOI_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_64 = muxState_1_1 ? portsAOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_65 = muxState_1_2 ? portsAOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_66 = muxState_1_3 ? portsAOI_filtered_3_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_67 = muxState_1_4 ? portsAOI_filtered_4_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_68 = _out_1_a_bits_T_63 | _out_1_a_bits_T_64; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_69 = _out_1_a_bits_T_68 | _out_1_a_bits_T_65; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_70 = _out_1_a_bits_T_69 | _out_1_a_bits_T_66; // @[Mux.scala:30:73] wire [2:0] _out_1_a_bits_T_71 = _out_1_a_bits_T_70 | _out_1_a_bits_T_67; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_10 = _out_1_a_bits_T_71; // @[Mux.scala:30:73] assign _out_1_a_bits_WIRE_opcode = _out_1_a_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_2 = idle_2 & out_1_c_ready; // @[Xbar.scala:216:19] wire [1:0] readys_lo_2 = {portsCOI_filtered_2_1_valid, portsCOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_2 = {portsCOI_filtered_4_1_valid, portsCOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [3:0] _readys_T_26 = {readys_hi_2, readys_lo_2}; // @[Arbiter.scala:68:51] wire [3:0] readys_valid_2 = _readys_T_26; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_27 = readys_valid_2 == _readys_T_26; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_29 = ~_readys_T_28; // @[Arbiter.scala:22:12] wire _readys_T_30 = ~_readys_T_27; // @[Arbiter.scala:22:{12,19}] reg [3:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [3:0] _readys_filter_T_4 = ~readys_mask_2; // @[Arbiter.scala:23:23, :24:30] wire [3:0] _readys_filter_T_5 = readys_valid_2 & _readys_filter_T_4; // @[Arbiter.scala:21:23, :24:{28,30}] wire [7:0] readys_filter_2 = {_readys_filter_T_5, readys_valid_2}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [6:0] _readys_unready_T_18 = readys_filter_2[7:1]; // @[package.scala:262:48] wire [7:0] _readys_unready_T_19 = {readys_filter_2[7], readys_filter_2[6:0] | _readys_unready_T_18}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_20 = _readys_unready_T_19[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_21 = {_readys_unready_T_19[7:6], _readys_unready_T_19[5:0] | _readys_unready_T_20}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_22 = _readys_unready_T_21; // @[package.scala:262:43, :263:17] wire [6:0] _readys_unready_T_23 = _readys_unready_T_22[7:1]; // @[package.scala:263:17] wire [7:0] _readys_unready_T_24 = {readys_mask_2, 4'h0}; // @[Arbiter.scala:23:23, :25:66] wire [7:0] readys_unready_2 = {1'h0, _readys_unready_T_23} | _readys_unready_T_24; // @[Arbiter.scala:25:{52,58,66}] wire [3:0] _readys_readys_T_6 = readys_unready_2[7:4]; // @[Arbiter.scala:25:58, :26:29] wire [3:0] _readys_readys_T_7 = readys_unready_2[3:0]; // @[Arbiter.scala:25:58, :26:48] wire [3:0] _readys_readys_T_8 = _readys_readys_T_6 & _readys_readys_T_7; // @[Arbiter.scala:26:{29,39,48}] wire [3:0] readys_readys_2 = ~_readys_readys_T_8; // @[Arbiter.scala:26:{18,39}] wire [3:0] _readys_T_33 = readys_readys_2; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_31 = |readys_valid_2; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_32 = latch_2 & _readys_T_31; // @[Arbiter.scala:27:{18,27}, :62:24] wire [3:0] _readys_mask_T_22 = readys_readys_2 & readys_valid_2; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [4:0] _readys_mask_T_23 = {_readys_mask_T_22, 1'h0}; // @[package.scala:253:48] wire [3:0] _readys_mask_T_24 = _readys_mask_T_23[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_25 = _readys_mask_T_22 | _readys_mask_T_24; // @[package.scala:253:{43,53}] wire [5:0] _readys_mask_T_26 = {_readys_mask_T_25, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _readys_mask_T_27 = _readys_mask_T_26[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_28 = _readys_mask_T_25 | _readys_mask_T_27; // @[package.scala:253:{43,53}] wire [3:0] _readys_mask_T_29 = _readys_mask_T_28; // @[package.scala:253:43, :254:17] wire _readys_T_34 = _readys_T_33[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_0 = _readys_T_34; // @[Arbiter.scala:68:{27,76}] wire _readys_T_35 = _readys_T_33[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_1 = _readys_T_35; // @[Arbiter.scala:68:{27,76}] wire _readys_T_36 = _readys_T_33[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_2 = _readys_T_36; // @[Arbiter.scala:68:{27,76}] wire _readys_T_37 = _readys_T_33[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_2_3 = _readys_T_37; // @[Arbiter.scala:68:{27,76}] wire _winner_T_10 = readys_2_0 & portsCOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_2_0 = _winner_T_10; // @[Arbiter.scala:71:{27,69}] wire _winner_T_11 = readys_2_1 & portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_2_1 = _winner_T_11; // @[Arbiter.scala:71:{27,69}] wire _winner_T_12 = readys_2_2 & portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_2_2 = _winner_T_12; // @[Arbiter.scala:71:{27,69}] wire _winner_T_13 = readys_2_3 & portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_2_3 = _winner_T_13; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_2 = winner_2_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_2 = prefixOR_1_2 | winner_2_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_2 = prefixOR_2_2 | winner_2_2; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_2 = prefixOR_3_2 | winner_2_3; // @[Arbiter.scala:71:27, :76:48] wire _out_1_c_valid_T = portsCOI_filtered_1_1_valid | portsCOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_2 = winner_2_0 ? beatsCI_1 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_1_2 = winner_2_1 ? beatsCI_2 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_2_2 = winner_2_2 ? beatsCI_3 : 8'h0; // @[Edges.scala:221:14] wire [7:0] maskedBeats_3_2 = winner_2_3 ? beatsCI_4 : 8'h0; // @[Edges.scala:221:14] wire [7:0] _initBeats_T_6 = maskedBeats_0_2 | maskedBeats_1_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] _initBeats_T_7 = _initBeats_T_6 | maskedBeats_2_2; // @[Arbiter.scala:82:69, :84:44] wire [7:0] initBeats_2 = _initBeats_T_7 | maskedBeats_3_2; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_8 = out_1_c_ready & out_1_c_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_9 = {1'h0, beatsLeft_2} - {8'h0, _beatsLeft_T_8}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_10 = _beatsLeft_T_9[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_11 = latch_2 ? initBeats_2 : _beatsLeft_T_10; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] reg state_2_2; // @[Arbiter.scala:88:26] reg state_2_3; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_2 = idle_2 ? winner_2_2 : state_2_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2_3 = idle_2 ? winner_2_3 : state_2_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_2_0 = idle_2 ? readys_2_0 : state_2_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_1 = idle_2 ? readys_2_1 : state_2_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_2 = idle_2 ? readys_2_2 : state_2_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2_3 = idle_2 ? readys_2_3 : state_2_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_5 = out_1_c_ready & allowed_2_0; // @[Xbar.scala:216:19] assign portsCOI_filtered_1_1_ready = _filtered_1_ready_T_5; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_6 = out_1_c_ready & allowed_2_1; // @[Xbar.scala:216:19] assign portsCOI_filtered_2_1_ready = _filtered_1_ready_T_6; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_7 = out_1_c_ready & allowed_2_2; // @[Xbar.scala:216:19] assign portsCOI_filtered_3_1_ready = _filtered_1_ready_T_7; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_8 = out_1_c_ready & allowed_2_3; // @[Xbar.scala:216:19] assign portsCOI_filtered_4_1_ready = _filtered_1_ready_T_8; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_1 = _out_1_c_valid_T | portsCOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_2 = _out_1_c_valid_T_1 | portsCOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_c_valid_T_3 = state_2_0 & portsCOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_4 = state_2_1 & portsCOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_5 = state_2_2 & portsCOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_6 = state_2_3 & portsCOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_c_valid_T_7 = _out_1_c_valid_T_3 | _out_1_c_valid_T_4; // @[Mux.scala:30:73] wire _out_1_c_valid_T_8 = _out_1_c_valid_T_7 | _out_1_c_valid_T_5; // @[Mux.scala:30:73] wire _out_1_c_valid_T_9 = _out_1_c_valid_T_8 | _out_1_c_valid_T_6; // @[Mux.scala:30:73] wire _out_1_c_valid_WIRE = _out_1_c_valid_T_9; // @[Mux.scala:30:73] assign _out_1_c_valid_T_10 = idle_2 ? _out_1_c_valid_T_2 : _out_1_c_valid_WIRE; // @[Mux.scala:30:73] assign out_1_c_valid = _out_1_c_valid_T_10; // @[Xbar.scala:216:19] wire [2:0] _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] assign out_1_c_bits_opcode = _out_1_c_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] assign out_1_c_bits_param = _out_1_c_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] assign out_1_c_bits_size = _out_1_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] assign out_1_c_bits_source = _out_1_c_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] assign out_1_c_bits_address = _out_1_c_bits_WIRE_address; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] assign out_1_c_bits_data = _out_1_c_bits_WIRE_data; // @[Mux.scala:30:73] wire _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_c_bits_corrupt = _out_1_c_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T = muxState_2_0 & portsCOI_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_1 = muxState_2_1 & portsCOI_filtered_2_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_2 = muxState_2_2 & portsCOI_filtered_3_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_3 = muxState_2_3 & portsCOI_filtered_4_1_bits_corrupt; // @[Mux.scala:30:73] wire _out_1_c_bits_T_4 = _out_1_c_bits_T | _out_1_c_bits_T_1; // @[Mux.scala:30:73] wire _out_1_c_bits_T_5 = _out_1_c_bits_T_4 | _out_1_c_bits_T_2; // @[Mux.scala:30:73] wire _out_1_c_bits_T_6 = _out_1_c_bits_T_5 | _out_1_c_bits_T_3; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_1 = _out_1_c_bits_T_6; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_corrupt = _out_1_c_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_7 = muxState_2_0 ? portsCOI_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_8 = muxState_2_1 ? portsCOI_filtered_2_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_9 = muxState_2_2 ? portsCOI_filtered_3_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_10 = muxState_2_3 ? portsCOI_filtered_4_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_11 = _out_1_c_bits_T_7 | _out_1_c_bits_T_8; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_12 = _out_1_c_bits_T_11 | _out_1_c_bits_T_9; // @[Mux.scala:30:73] wire [127:0] _out_1_c_bits_T_13 = _out_1_c_bits_T_12 | _out_1_c_bits_T_10; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_2 = _out_1_c_bits_T_13; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_data = _out_1_c_bits_WIRE_2; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_14 = muxState_2_0 ? portsCOI_filtered_1_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_15 = muxState_2_1 ? portsCOI_filtered_2_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_16 = muxState_2_2 ? portsCOI_filtered_3_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_17 = muxState_2_3 ? portsCOI_filtered_4_1_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_18 = _out_1_c_bits_T_14 | _out_1_c_bits_T_15; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_19 = _out_1_c_bits_T_18 | _out_1_c_bits_T_16; // @[Mux.scala:30:73] wire [31:0] _out_1_c_bits_T_20 = _out_1_c_bits_T_19 | _out_1_c_bits_T_17; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_5 = _out_1_c_bits_T_20; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_address = _out_1_c_bits_WIRE_5; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_21 = muxState_2_0 ? portsCOI_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_22 = muxState_2_1 ? portsCOI_filtered_2_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_23 = muxState_2_2 ? portsCOI_filtered_3_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_24 = muxState_2_3 ? portsCOI_filtered_4_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_25 = _out_1_c_bits_T_21 | _out_1_c_bits_T_22; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_26 = _out_1_c_bits_T_25 | _out_1_c_bits_T_23; // @[Mux.scala:30:73] wire [6:0] _out_1_c_bits_T_27 = _out_1_c_bits_T_26 | _out_1_c_bits_T_24; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_6 = _out_1_c_bits_T_27; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_source = _out_1_c_bits_WIRE_6; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_28 = muxState_2_0 ? portsCOI_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_29 = muxState_2_1 ? portsCOI_filtered_2_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_30 = muxState_2_2 ? portsCOI_filtered_3_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_31 = muxState_2_3 ? portsCOI_filtered_4_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_32 = _out_1_c_bits_T_28 | _out_1_c_bits_T_29; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_33 = _out_1_c_bits_T_32 | _out_1_c_bits_T_30; // @[Mux.scala:30:73] wire [3:0] _out_1_c_bits_T_34 = _out_1_c_bits_T_33 | _out_1_c_bits_T_31; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_7 = _out_1_c_bits_T_34; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_size = _out_1_c_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_35 = muxState_2_0 ? portsCOI_filtered_1_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_36 = muxState_2_1 ? portsCOI_filtered_2_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_37 = muxState_2_2 ? portsCOI_filtered_3_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_38 = muxState_2_3 ? portsCOI_filtered_4_1_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_39 = _out_1_c_bits_T_35 | _out_1_c_bits_T_36; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_40 = _out_1_c_bits_T_39 | _out_1_c_bits_T_37; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_41 = _out_1_c_bits_T_40 | _out_1_c_bits_T_38; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_8 = _out_1_c_bits_T_41; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_param = _out_1_c_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_42 = muxState_2_0 ? portsCOI_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_43 = muxState_2_1 ? portsCOI_filtered_2_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_44 = muxState_2_2 ? portsCOI_filtered_3_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_45 = muxState_2_3 ? portsCOI_filtered_4_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_46 = _out_1_c_bits_T_42 | _out_1_c_bits_T_43; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_47 = _out_1_c_bits_T_46 | _out_1_c_bits_T_44; // @[Mux.scala:30:73] wire [2:0] _out_1_c_bits_T_48 = _out_1_c_bits_T_47 | _out_1_c_bits_T_45; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_9 = _out_1_c_bits_T_48; // @[Mux.scala:30:73] assign _out_1_c_bits_WIRE_opcode = _out_1_c_bits_WIRE_9; // @[Mux.scala:30:73] reg beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = ~beatsLeft_3; // @[Arbiter.scala:60:30, :61:28] wire latch_3 = idle_3; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_lo_3 = {portsEOI_filtered_2_1_valid, portsEOI_filtered_1_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_hi_3 = {portsEOI_filtered_4_1_valid, portsEOI_filtered_3_1_valid}; // @[Xbar.scala:352:24] wire [3:0] _readys_T_38 = {readys_hi_3, readys_lo_3}; // @[Arbiter.scala:68:51] wire [3:0] readys_valid_3 = _readys_T_38; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_39 = readys_valid_3 == _readys_T_38; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_41 = ~_readys_T_40; // @[Arbiter.scala:22:12] wire _readys_T_42 = ~_readys_T_39; // @[Arbiter.scala:22:{12,19}] reg [3:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [3:0] _readys_filter_T_6 = ~readys_mask_3; // @[Arbiter.scala:23:23, :24:30] wire [3:0] _readys_filter_T_7 = readys_valid_3 & _readys_filter_T_6; // @[Arbiter.scala:21:23, :24:{28,30}] wire [7:0] readys_filter_3 = {_readys_filter_T_7, readys_valid_3}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [6:0] _readys_unready_T_25 = readys_filter_3[7:1]; // @[package.scala:262:48] wire [7:0] _readys_unready_T_26 = {readys_filter_3[7], readys_filter_3[6:0] | _readys_unready_T_25}; // @[package.scala:262:{43,48}] wire [5:0] _readys_unready_T_27 = _readys_unready_T_26[7:2]; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_28 = {_readys_unready_T_26[7:6], _readys_unready_T_26[5:0] | _readys_unready_T_27}; // @[package.scala:262:{43,48}] wire [7:0] _readys_unready_T_29 = _readys_unready_T_28; // @[package.scala:262:43, :263:17] wire [6:0] _readys_unready_T_30 = _readys_unready_T_29[7:1]; // @[package.scala:263:17] wire [7:0] _readys_unready_T_31 = {readys_mask_3, 4'h0}; // @[Arbiter.scala:23:23, :25:66] wire [7:0] readys_unready_3 = {1'h0, _readys_unready_T_30} | _readys_unready_T_31; // @[Arbiter.scala:25:{52,58,66}] wire [3:0] _readys_readys_T_9 = readys_unready_3[7:4]; // @[Arbiter.scala:25:58, :26:29] wire [3:0] _readys_readys_T_10 = readys_unready_3[3:0]; // @[Arbiter.scala:25:58, :26:48] wire [3:0] _readys_readys_T_11 = _readys_readys_T_9 & _readys_readys_T_10; // @[Arbiter.scala:26:{29,39,48}] wire [3:0] readys_readys_3 = ~_readys_readys_T_11; // @[Arbiter.scala:26:{18,39}] wire [3:0] _readys_T_45 = readys_readys_3; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_43 = |readys_valid_3; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_44 = latch_3 & _readys_T_43; // @[Arbiter.scala:27:{18,27}, :62:24] wire [3:0] _readys_mask_T_30 = readys_readys_3 & readys_valid_3; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [4:0] _readys_mask_T_31 = {_readys_mask_T_30, 1'h0}; // @[package.scala:253:48] wire [3:0] _readys_mask_T_32 = _readys_mask_T_31[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_33 = _readys_mask_T_30 | _readys_mask_T_32; // @[package.scala:253:{43,53}] wire [5:0] _readys_mask_T_34 = {_readys_mask_T_33, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _readys_mask_T_35 = _readys_mask_T_34[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_mask_T_36 = _readys_mask_T_33 | _readys_mask_T_35; // @[package.scala:253:{43,53}] wire [3:0] _readys_mask_T_37 = _readys_mask_T_36; // @[package.scala:253:43, :254:17] wire _readys_T_46 = _readys_T_45[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_0 = _readys_T_46; // @[Arbiter.scala:68:{27,76}] wire _readys_T_47 = _readys_T_45[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_1 = _readys_T_47; // @[Arbiter.scala:68:{27,76}] wire _readys_T_48 = _readys_T_45[2]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_2 = _readys_T_48; // @[Arbiter.scala:68:{27,76}] wire _readys_T_49 = _readys_T_45[3]; // @[Arbiter.scala:30:11, :68:76] wire readys_3_3 = _readys_T_49; // @[Arbiter.scala:68:{27,76}] wire _winner_T_14 = readys_3_0 & portsEOI_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_3_0 = _winner_T_14; // @[Arbiter.scala:71:{27,69}] wire _winner_T_15 = readys_3_1 & portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire winner_3_1 = _winner_T_15; // @[Arbiter.scala:71:{27,69}] wire _winner_T_16 = readys_3_2 & portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire winner_3_2 = _winner_T_16; // @[Arbiter.scala:71:{27,69}] wire _winner_T_17 = readys_3_3 & portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire winner_3_3 = _winner_T_17; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_3 = winner_3_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_3 = prefixOR_1_3 | winner_3_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_3 = prefixOR_2_3 | winner_3_2; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_3 = prefixOR_3_3 | winner_3_3; // @[Arbiter.scala:71:27, :76:48] wire _out_1_e_valid_T = portsEOI_filtered_1_1_valid | portsEOI_filtered_2_1_valid; // @[Xbar.scala:352:24] wire [1:0] _beatsLeft_T_13 = {1'h0, beatsLeft_3} - {1'h0, _beatsLeft_T_12}; // @[Decoupled.scala:51:35] wire _beatsLeft_T_14 = _beatsLeft_T_13[0]; // @[Arbiter.scala:85:52] wire _beatsLeft_T_15 = ~latch_3 & _beatsLeft_T_14; // @[Arbiter.scala:62:24, :85:{23,52}] reg state_3_0; // @[Arbiter.scala:88:26] reg state_3_1; // @[Arbiter.scala:88:26] reg state_3_2; // @[Arbiter.scala:88:26] reg state_3_3; // @[Arbiter.scala:88:26] wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_2 = idle_3 ? winner_3_2 : state_3_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3_3 = idle_3 ? winner_3_3 : state_3_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_3_0 = idle_3 ? readys_3_0 : state_3_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_1 = idle_3 ? readys_3_1 : state_3_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_2 = idle_3 ? readys_3_2 : state_3_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3_3 = idle_3 ? readys_3_3 : state_3_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_9 = allowed_3_0; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_10 = allowed_3_1; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_11 = allowed_3_2; // @[Arbiter.scala:92:24, :94:31] assign _filtered_1_ready_T_12 = allowed_3_3; // @[Arbiter.scala:92:24, :94:31] assign portsEOI_filtered_1_1_ready = _filtered_1_ready_T_9; // @[Xbar.scala:352:24] assign portsEOI_filtered_2_1_ready = _filtered_1_ready_T_10; // @[Xbar.scala:352:24] assign portsEOI_filtered_3_1_ready = _filtered_1_ready_T_11; // @[Xbar.scala:352:24] assign portsEOI_filtered_4_1_ready = _filtered_1_ready_T_12; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_1 = _out_1_e_valid_T | portsEOI_filtered_3_1_valid; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_2 = _out_1_e_valid_T_1 | portsEOI_filtered_4_1_valid; // @[Xbar.scala:352:24] wire _out_1_e_valid_T_3 = state_3_0 & portsEOI_filtered_1_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_4 = state_3_1 & portsEOI_filtered_2_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_5 = state_3_2 & portsEOI_filtered_3_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_6 = state_3_3 & portsEOI_filtered_4_1_valid; // @[Mux.scala:30:73] wire _out_1_e_valid_T_7 = _out_1_e_valid_T_3 | _out_1_e_valid_T_4; // @[Mux.scala:30:73] wire _out_1_e_valid_T_8 = _out_1_e_valid_T_7 | _out_1_e_valid_T_5; // @[Mux.scala:30:73] wire _out_1_e_valid_T_9 = _out_1_e_valid_T_8 | _out_1_e_valid_T_6; // @[Mux.scala:30:73] wire _out_1_e_valid_WIRE = _out_1_e_valid_T_9; // @[Mux.scala:30:73] assign _out_1_e_valid_T_10 = idle_3 ? _out_1_e_valid_T_2 : _out_1_e_valid_WIRE; // @[Mux.scala:30:73] assign out_1_e_valid = _out_1_e_valid_T_10; // @[Xbar.scala:216:19] wire [3:0] _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] assign out_1_e_bits_sink = _out_1_e_bits_WIRE_sink; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T = muxState_3_0 ? portsEOI_filtered_1_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_1 = muxState_3_1 ? portsEOI_filtered_2_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_2 = muxState_3_2 ? portsEOI_filtered_3_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_3 = muxState_3_3 ? portsEOI_filtered_4_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_4 = _out_1_e_bits_T | _out_1_e_bits_T_1; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_5 = _out_1_e_bits_T_4 | _out_1_e_bits_T_2; // @[Mux.scala:30:73] wire [3:0] _out_1_e_bits_T_6 = _out_1_e_bits_T_5 | _out_1_e_bits_T_3; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_1 = _out_1_e_bits_T_6; // @[Mux.scala:30:73] assign _out_1_e_bits_WIRE_sink = _out_1_e_bits_WIRE_1; // @[Mux.scala:30:73] reg [7:0] beatsLeft_4; // @[Arbiter.scala:60:30] wire idle_4 = beatsLeft_4 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_4 = idle_4 & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_50 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_4 = _readys_T_50; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_51 = readys_valid_4 == _readys_T_50; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_53 = ~_readys_T_52; // @[Arbiter.scala:22:12] wire _readys_T_54 = ~_readys_T_51; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_8 = ~readys_mask_4; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_9 = readys_valid_4 & _readys_filter_T_8; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_4 = {_readys_filter_T_9, readys_valid_4}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_32 = readys_filter_4[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_33 = {readys_filter_4[3], readys_filter_4[2:0] | _readys_unready_T_32}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_34 = _readys_unready_T_33; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_35 = _readys_unready_T_34[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_36 = {readys_mask_4, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_4 = {1'h0, _readys_unready_T_35} | _readys_unready_T_36; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_12 = readys_unready_4[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_13 = readys_unready_4[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_14 = _readys_readys_T_12 & _readys_readys_T_13; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_4 = ~_readys_readys_T_14; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_57 = readys_readys_4; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_55 = |readys_valid_4; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_56 = latch_4 & _readys_T_55; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_38 = readys_readys_4 & readys_valid_4; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_39 = {_readys_mask_T_38, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_40 = _readys_mask_T_39[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_41 = _readys_mask_T_38 | _readys_mask_T_40; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_42 = _readys_mask_T_41; // @[package.scala:253:43, :254:17] wire _readys_T_58 = _readys_T_57[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_0 = _readys_T_58; // @[Arbiter.scala:68:{27,76}] wire _readys_T_59 = _readys_T_57[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_4_1 = _readys_T_59; // @[Arbiter.scala:68:{27,76}] wire _winner_T_18 = readys_4_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_4_0 = _winner_T_18; // @[Arbiter.scala:71:{27,69}] wire _winner_T_19 = readys_4_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_4_1 = _winner_T_19; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_4 = winner_4_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_4 = prefixOR_1_4 | winner_4_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_4 = winner_4_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_4 = winner_4_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_4 = {maskedBeats_0_4[7:2], maskedBeats_0_4[1:0] | maskedBeats_1_4}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_16 = in_0_d_ready & in_0_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_17 = {1'h0, beatsLeft_4} - {8'h0, _beatsLeft_T_16}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_18 = _beatsLeft_T_17[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_19 = latch_4 ? initBeats_4 : _beatsLeft_T_18; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_4_0; // @[Arbiter.scala:88:26] reg state_4_1; // @[Arbiter.scala:88:26] wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_4_0 = idle_4 ? readys_4_0 : state_4_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4_1 = idle_4 ? readys_4_1 : state_4_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_0_ready_T_5 = in_0_d_ready & allowed_4_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_0_ready = _filtered_0_ready_T_5; // @[Xbar.scala:352:24] assign _filtered_0_ready_T_6 = in_0_d_ready & allowed_4_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_0_ready = _filtered_0_ready_T_6; // @[Xbar.scala:352:24] wire _in_0_d_valid_T_1 = state_4_0 & portsDIO_filtered_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_2 = state_4_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_valid_T_3 = _in_0_d_valid_T_1 | _in_0_d_valid_T_2; // @[Mux.scala:30:73] wire _in_0_d_valid_WIRE = _in_0_d_valid_T_3; // @[Mux.scala:30:73] assign _in_0_d_valid_T_4 = idle_4 ? _in_0_d_valid_T : _in_0_d_valid_WIRE; // @[Mux.scala:30:73] assign in_0_d_valid = _in_0_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_0_d_bits_opcode = _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_0_d_bits_param = _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_0_d_bits_size = _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_0_d_bits_source = _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_0_d_bits_sink = _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_0_d_bits_denied = _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_0_d_bits_data = _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_0_d_bits_corrupt = _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T = muxState_4_0 & portsDIO_filtered_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_1 = muxState_4_1 & portsDIO_filtered_1_0_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = _in_0_d_bits_T | _in_0_d_bits_T_1; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_1 = _in_0_d_bits_T_2; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_corrupt = _in_0_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_3 = muxState_4_0 ? portsDIO_filtered_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_4 = muxState_4_1 ? portsDIO_filtered_1_0_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_0_d_bits_T_5 = _in_0_d_bits_T_3 | _in_0_d_bits_T_4; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_2 = _in_0_d_bits_T_5; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_data = _in_0_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_0_d_bits_T_6 = muxState_4_0 & portsDIO_filtered_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_7 = muxState_4_1 & portsDIO_filtered_1_0_bits_denied; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = _in_0_d_bits_T_6 | _in_0_d_bits_T_7; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_5 = _in_0_d_bits_T_8; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_denied = _in_0_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_9 = muxState_4_0 ? portsDIO_filtered_0_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_10 = muxState_4_1 ? portsDIO_filtered_1_0_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_11 = _in_0_d_bits_T_9 | _in_0_d_bits_T_10; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_6 = _in_0_d_bits_T_11; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_sink = _in_0_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_12 = muxState_4_0 ? portsDIO_filtered_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_13 = muxState_4_1 ? portsDIO_filtered_1_0_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_0_d_bits_T_14 = _in_0_d_bits_T_12 | _in_0_d_bits_T_13; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_7 = _in_0_d_bits_T_14; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_source = _in_0_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_15 = muxState_4_0 ? portsDIO_filtered_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_16 = muxState_4_1 ? portsDIO_filtered_1_0_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = _in_0_d_bits_T_15 | _in_0_d_bits_T_16; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_8 = _in_0_d_bits_T_17; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_size = _in_0_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_18 = muxState_4_0 ? portsDIO_filtered_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_19 = muxState_4_1 ? portsDIO_filtered_1_0_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = _in_0_d_bits_T_18 | _in_0_d_bits_T_19; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_9 = _in_0_d_bits_T_20; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_param = _in_0_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_21 = muxState_4_0 ? portsDIO_filtered_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_22 = muxState_4_1 ? portsDIO_filtered_1_0_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = _in_0_d_bits_T_21 | _in_0_d_bits_T_22; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_10 = _in_0_d_bits_T_23; // @[Mux.scala:30:73] assign _in_0_d_bits_WIRE_opcode = _in_0_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_5; // @[Arbiter.scala:60:30] wire idle_5 = beatsLeft_5 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_5 = idle_5 & in_1_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_60 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_5 = _readys_T_60; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_61 = readys_valid_5 == _readys_T_60; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_63 = ~_readys_T_62; // @[Arbiter.scala:22:12] wire _readys_T_64 = ~_readys_T_61; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_5; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_10 = ~readys_mask_5; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_11 = readys_valid_5 & _readys_filter_T_10; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_5 = {_readys_filter_T_11, readys_valid_5}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_37 = readys_filter_5[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_38 = {readys_filter_5[3], readys_filter_5[2:0] | _readys_unready_T_37}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_39 = _readys_unready_T_38; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_40 = _readys_unready_T_39[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_41 = {readys_mask_5, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_5 = {1'h0, _readys_unready_T_40} | _readys_unready_T_41; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_15 = readys_unready_5[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_16 = readys_unready_5[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_17 = _readys_readys_T_15 & _readys_readys_T_16; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_5 = ~_readys_readys_T_17; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_67 = readys_readys_5; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_65 = |readys_valid_5; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_66 = latch_5 & _readys_T_65; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_43 = readys_readys_5 & readys_valid_5; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_44 = {_readys_mask_T_43, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_45 = _readys_mask_T_44[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_46 = _readys_mask_T_43 | _readys_mask_T_45; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_47 = _readys_mask_T_46; // @[package.scala:253:43, :254:17] wire _readys_T_68 = _readys_T_67[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_0 = _readys_T_68; // @[Arbiter.scala:68:{27,76}] wire _readys_T_69 = _readys_T_67[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_5_1 = _readys_T_69; // @[Arbiter.scala:68:{27,76}] wire _winner_T_20 = readys_5_0 & portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] wire winner_5_0 = _winner_T_20; // @[Arbiter.scala:71:{27,69}] wire _winner_T_21 = readys_5_1 & portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire winner_5_1 = _winner_T_21; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_5 = winner_5_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_5 = prefixOR_1_5 | winner_5_1; // @[Arbiter.scala:71:27, :76:48] wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_5 = winner_5_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_5 = winner_5_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_5 = {maskedBeats_0_5[7:2], maskedBeats_0_5[1:0] | maskedBeats_1_5}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_20 = in_1_d_ready & in_1_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_21 = {1'h0, beatsLeft_5} - {8'h0, _beatsLeft_T_20}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_22 = _beatsLeft_T_21[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_23 = latch_5 ? initBeats_5 : _beatsLeft_T_22; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_5_0; // @[Arbiter.scala:88:26] reg state_5_1; // @[Arbiter.scala:88:26] wire muxState_5_0 = idle_5 ? winner_5_0 : state_5_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_5_1 = idle_5 ? winner_5_1 : state_5_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_5_0 = idle_5 ? readys_5_0 : state_5_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_5_1 = idle_5 ? readys_5_1 : state_5_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_1_ready_T_13 = in_1_d_ready & allowed_5_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_ready = _filtered_1_ready_T_13; // @[Xbar.scala:352:24] assign _filtered_1_ready_T_14 = in_1_d_ready & allowed_5_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_1_ready = _filtered_1_ready_T_14; // @[Xbar.scala:352:24] wire _in_1_d_valid_T_1 = state_5_0 & portsDIO_filtered_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_2 = state_5_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73] wire _in_1_d_valid_T_3 = _in_1_d_valid_T_1 | _in_1_d_valid_T_2; // @[Mux.scala:30:73] wire _in_1_d_valid_WIRE = _in_1_d_valid_T_3; // @[Mux.scala:30:73] assign _in_1_d_valid_T_4 = idle_5 ? _in_1_d_valid_T : _in_1_d_valid_WIRE; // @[Mux.scala:30:73] assign in_1_d_valid = _in_1_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_1_d_bits_opcode = _in_1_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_1_d_bits_param = _in_1_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_1_d_bits_size = _in_1_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_1_d_bits_source = _in_1_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_1_d_bits_sink = _in_1_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_1_d_bits_denied = _in_1_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_1_d_bits_data = _in_1_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_1_d_bits_corrupt = _in_1_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T = muxState_5_0 & portsDIO_filtered_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_1 = muxState_5_1 & portsDIO_filtered_1_1_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_2 = _in_1_d_bits_T | _in_1_d_bits_T_1; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_1 = _in_1_d_bits_T_2; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_corrupt = _in_1_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_3 = muxState_5_0 ? portsDIO_filtered_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_4 = muxState_5_1 ? portsDIO_filtered_1_1_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_1_d_bits_T_5 = _in_1_d_bits_T_3 | _in_1_d_bits_T_4; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_2 = _in_1_d_bits_T_5; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_data = _in_1_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_1_d_bits_T_6 = muxState_5_0 & portsDIO_filtered_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_7 = muxState_5_1 & portsDIO_filtered_1_1_bits_denied; // @[Mux.scala:30:73] wire _in_1_d_bits_T_8 = _in_1_d_bits_T_6 | _in_1_d_bits_T_7; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_5 = _in_1_d_bits_T_8; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_denied = _in_1_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_9 = muxState_5_0 ? portsDIO_filtered_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_10 = muxState_5_1 ? portsDIO_filtered_1_1_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_11 = _in_1_d_bits_T_9 | _in_1_d_bits_T_10; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_6 = _in_1_d_bits_T_11; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_sink = _in_1_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_12 = muxState_5_0 ? portsDIO_filtered_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_13 = muxState_5_1 ? portsDIO_filtered_1_1_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_1_d_bits_T_14 = _in_1_d_bits_T_12 | _in_1_d_bits_T_13; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_7 = _in_1_d_bits_T_14; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_source = _in_1_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_15 = muxState_5_0 ? portsDIO_filtered_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_16 = muxState_5_1 ? portsDIO_filtered_1_1_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_17 = _in_1_d_bits_T_15 | _in_1_d_bits_T_16; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_8 = _in_1_d_bits_T_17; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_size = _in_1_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_18 = muxState_5_0 ? portsDIO_filtered_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_19 = muxState_5_1 ? portsDIO_filtered_1_1_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_20 = _in_1_d_bits_T_18 | _in_1_d_bits_T_19; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_9 = _in_1_d_bits_T_20; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_param = _in_1_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_21 = muxState_5_0 ? portsDIO_filtered_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_22 = muxState_5_1 ? portsDIO_filtered_1_1_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_23 = _in_1_d_bits_T_21 | _in_1_d_bits_T_22; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_10 = _in_1_d_bits_T_23; // @[Mux.scala:30:73] assign _in_1_d_bits_WIRE_opcode = _in_1_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_6; // @[Arbiter.scala:60:30] wire idle_6 = beatsLeft_6 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_6 = idle_6 & in_2_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_70 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_6 = _readys_T_70; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_71 = readys_valid_6 == _readys_T_70; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_73 = ~_readys_T_72; // @[Arbiter.scala:22:12] wire _readys_T_74 = ~_readys_T_71; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_6; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_12 = ~readys_mask_6; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_13 = readys_valid_6 & _readys_filter_T_12; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_6 = {_readys_filter_T_13, readys_valid_6}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_42 = readys_filter_6[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_43 = {readys_filter_6[3], readys_filter_6[2:0] | _readys_unready_T_42}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_44 = _readys_unready_T_43; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_45 = _readys_unready_T_44[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_46 = {readys_mask_6, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_6 = {1'h0, _readys_unready_T_45} | _readys_unready_T_46; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_18 = readys_unready_6[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_19 = readys_unready_6[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_20 = _readys_readys_T_18 & _readys_readys_T_19; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_6 = ~_readys_readys_T_20; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_77 = readys_readys_6; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_75 = |readys_valid_6; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_76 = latch_6 & _readys_T_75; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_48 = readys_readys_6 & readys_valid_6; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_49 = {_readys_mask_T_48, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_50 = _readys_mask_T_49[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_51 = _readys_mask_T_48 | _readys_mask_T_50; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_52 = _readys_mask_T_51; // @[package.scala:253:43, :254:17] wire _readys_T_78 = _readys_T_77[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_0 = _readys_T_78; // @[Arbiter.scala:68:{27,76}] wire _readys_T_79 = _readys_T_77[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_6_1 = _readys_T_79; // @[Arbiter.scala:68:{27,76}] wire _winner_T_22 = readys_6_0 & portsDIO_filtered_2_valid; // @[Xbar.scala:352:24] wire winner_6_0 = _winner_T_22; // @[Arbiter.scala:71:{27,69}] wire _winner_T_23 = readys_6_1 & portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire winner_6_1 = _winner_T_23; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_6 = winner_6_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_6 = prefixOR_1_6 | winner_6_1; // @[Arbiter.scala:71:27, :76:48] wire _in_2_d_valid_T = portsDIO_filtered_2_valid | portsDIO_filtered_1_2_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_6 = winner_6_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_6 = winner_6_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_6 = {maskedBeats_0_6[7:2], maskedBeats_0_6[1:0] | maskedBeats_1_6}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_24 = in_2_d_ready & in_2_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_25 = {1'h0, beatsLeft_6} - {8'h0, _beatsLeft_T_24}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_26 = _beatsLeft_T_25[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_27 = latch_6 ? initBeats_6 : _beatsLeft_T_26; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_6_0; // @[Arbiter.scala:88:26] reg state_6_1; // @[Arbiter.scala:88:26] wire muxState_6_0 = idle_6 ? winner_6_0 : state_6_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_6_1 = idle_6 ? winner_6_1 : state_6_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_6_0 = idle_6 ? readys_6_0 : state_6_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_6_1 = idle_6 ? readys_6_1 : state_6_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_2_ready_T = in_2_d_ready & allowed_6_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_2_ready = _filtered_2_ready_T; // @[Xbar.scala:352:24] assign _filtered_2_ready_T_1 = in_2_d_ready & allowed_6_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_2_ready = _filtered_2_ready_T_1; // @[Xbar.scala:352:24] wire _in_2_d_valid_T_1 = state_6_0 & portsDIO_filtered_2_valid; // @[Mux.scala:30:73] wire _in_2_d_valid_T_2 = state_6_1 & portsDIO_filtered_1_2_valid; // @[Mux.scala:30:73] wire _in_2_d_valid_T_3 = _in_2_d_valid_T_1 | _in_2_d_valid_T_2; // @[Mux.scala:30:73] wire _in_2_d_valid_WIRE = _in_2_d_valid_T_3; // @[Mux.scala:30:73] assign _in_2_d_valid_T_4 = idle_6 ? _in_2_d_valid_T : _in_2_d_valid_WIRE; // @[Mux.scala:30:73] assign in_2_d_valid = _in_2_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_2_d_bits_opcode = _in_2_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_2_d_bits_param = _in_2_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_2_d_bits_size = _in_2_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_2_d_bits_source = _in_2_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_2_d_bits_sink = _in_2_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_2_d_bits_denied = _in_2_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_2_d_bits_data = _in_2_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_2_d_bits_corrupt = _in_2_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T = muxState_6_0 & portsDIO_filtered_2_bits_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T_1 = muxState_6_1 & portsDIO_filtered_1_2_bits_corrupt; // @[Mux.scala:30:73] wire _in_2_d_bits_T_2 = _in_2_d_bits_T | _in_2_d_bits_T_1; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_1 = _in_2_d_bits_T_2; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_corrupt = _in_2_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_3 = muxState_6_0 ? portsDIO_filtered_2_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_4 = muxState_6_1 ? portsDIO_filtered_1_2_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_2_d_bits_T_5 = _in_2_d_bits_T_3 | _in_2_d_bits_T_4; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_2 = _in_2_d_bits_T_5; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_data = _in_2_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_2_d_bits_T_6 = muxState_6_0 & portsDIO_filtered_2_bits_denied; // @[Mux.scala:30:73] wire _in_2_d_bits_T_7 = muxState_6_1 & portsDIO_filtered_1_2_bits_denied; // @[Mux.scala:30:73] wire _in_2_d_bits_T_8 = _in_2_d_bits_T_6 | _in_2_d_bits_T_7; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_5 = _in_2_d_bits_T_8; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_denied = _in_2_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_9 = muxState_6_0 ? portsDIO_filtered_2_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_10 = muxState_6_1 ? portsDIO_filtered_1_2_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_11 = _in_2_d_bits_T_9 | _in_2_d_bits_T_10; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_6 = _in_2_d_bits_T_11; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_sink = _in_2_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_12 = muxState_6_0 ? portsDIO_filtered_2_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_13 = muxState_6_1 ? portsDIO_filtered_1_2_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_2_d_bits_T_14 = _in_2_d_bits_T_12 | _in_2_d_bits_T_13; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_7 = _in_2_d_bits_T_14; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_source = _in_2_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_15 = muxState_6_0 ? portsDIO_filtered_2_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_16 = muxState_6_1 ? portsDIO_filtered_1_2_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_2_d_bits_T_17 = _in_2_d_bits_T_15 | _in_2_d_bits_T_16; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_8 = _in_2_d_bits_T_17; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_size = _in_2_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_18 = muxState_6_0 ? portsDIO_filtered_2_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_19 = muxState_6_1 ? portsDIO_filtered_1_2_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_2_d_bits_T_20 = _in_2_d_bits_T_18 | _in_2_d_bits_T_19; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_9 = _in_2_d_bits_T_20; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_param = _in_2_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_21 = muxState_6_0 ? portsDIO_filtered_2_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_22 = muxState_6_1 ? portsDIO_filtered_1_2_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_2_d_bits_T_23 = _in_2_d_bits_T_21 | _in_2_d_bits_T_22; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_10 = _in_2_d_bits_T_23; // @[Mux.scala:30:73] assign _in_2_d_bits_WIRE_opcode = _in_2_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_7; // @[Arbiter.scala:60:30] wire idle_7 = beatsLeft_7 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_7 = idle_7 & in_3_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_80 = {portsDIO_filtered_1_3_valid, portsDIO_filtered_3_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_7 = _readys_T_80; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_81 = readys_valid_7 == _readys_T_80; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_83 = ~_readys_T_82; // @[Arbiter.scala:22:12] wire _readys_T_84 = ~_readys_T_81; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_7; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_14 = ~readys_mask_7; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_15 = readys_valid_7 & _readys_filter_T_14; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_7 = {_readys_filter_T_15, readys_valid_7}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_47 = readys_filter_7[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_48 = {readys_filter_7[3], readys_filter_7[2:0] | _readys_unready_T_47}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_49 = _readys_unready_T_48; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_50 = _readys_unready_T_49[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_51 = {readys_mask_7, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_7 = {1'h0, _readys_unready_T_50} | _readys_unready_T_51; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_21 = readys_unready_7[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_22 = readys_unready_7[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_23 = _readys_readys_T_21 & _readys_readys_T_22; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_7 = ~_readys_readys_T_23; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_87 = readys_readys_7; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_85 = |readys_valid_7; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_86 = latch_7 & _readys_T_85; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_53 = readys_readys_7 & readys_valid_7; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_54 = {_readys_mask_T_53, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_55 = _readys_mask_T_54[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_56 = _readys_mask_T_53 | _readys_mask_T_55; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_57 = _readys_mask_T_56; // @[package.scala:253:43, :254:17] wire _readys_T_88 = _readys_T_87[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_7_0 = _readys_T_88; // @[Arbiter.scala:68:{27,76}] wire _readys_T_89 = _readys_T_87[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_7_1 = _readys_T_89; // @[Arbiter.scala:68:{27,76}] wire _winner_T_24 = readys_7_0 & portsDIO_filtered_3_valid; // @[Xbar.scala:352:24] wire winner_7_0 = _winner_T_24; // @[Arbiter.scala:71:{27,69}] wire _winner_T_25 = readys_7_1 & portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire winner_7_1 = _winner_T_25; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_7 = winner_7_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_7 = prefixOR_1_7 | winner_7_1; // @[Arbiter.scala:71:27, :76:48] wire _in_3_d_valid_T = portsDIO_filtered_3_valid | portsDIO_filtered_1_3_valid; // @[Xbar.scala:352:24] wire [7:0] maskedBeats_0_7 = winner_7_0 ? beatsDO_0 : 8'h0; // @[Edges.scala:221:14] wire [1:0] maskedBeats_1_7 = winner_7_1 ? beatsDO_1 : 2'h0; // @[Edges.scala:221:14] wire [7:0] initBeats_7 = {maskedBeats_0_7[7:2], maskedBeats_0_7[1:0] | maskedBeats_1_7}; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T_28 = in_3_d_ready & in_3_d_valid; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_29 = {1'h0, beatsLeft_7} - {8'h0, _beatsLeft_T_28}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_30 = _beatsLeft_T_29[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_31 = latch_7 ? initBeats_7 : _beatsLeft_T_30; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_7_0; // @[Arbiter.scala:88:26] reg state_7_1; // @[Arbiter.scala:88:26] wire muxState_7_0 = idle_7 ? winner_7_0 : state_7_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_7_1 = idle_7 ? winner_7_1 : state_7_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_7_0 = idle_7 ? readys_7_0 : state_7_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_7_1 = idle_7 ? readys_7_1 : state_7_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] assign _filtered_3_ready_T = in_3_d_ready & allowed_7_0; // @[Xbar.scala:159:18] assign portsDIO_filtered_3_ready = _filtered_3_ready_T; // @[Xbar.scala:352:24] assign _filtered_3_ready_T_1 = in_3_d_ready & allowed_7_1; // @[Xbar.scala:159:18] assign portsDIO_filtered_1_3_ready = _filtered_3_ready_T_1; // @[Xbar.scala:352:24] wire _in_3_d_valid_T_1 = state_7_0 & portsDIO_filtered_3_valid; // @[Mux.scala:30:73] wire _in_3_d_valid_T_2 = state_7_1 & portsDIO_filtered_1_3_valid; // @[Mux.scala:30:73] wire _in_3_d_valid_T_3 = _in_3_d_valid_T_1 | _in_3_d_valid_T_2; // @[Mux.scala:30:73] wire _in_3_d_valid_WIRE = _in_3_d_valid_T_3; // @[Mux.scala:30:73] assign _in_3_d_valid_T_4 = idle_7 ? _in_3_d_valid_T : _in_3_d_valid_WIRE; // @[Mux.scala:30:73] assign in_3_d_valid = _in_3_d_valid_T_4; // @[Xbar.scala:159:18] wire [2:0] _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73] assign in_3_d_bits_opcode = _in_3_d_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73] assign in_3_d_bits_param = _in_3_d_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73] assign in_3_d_bits_size = _in_3_d_bits_WIRE_size; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73] assign in_3_d_bits_source = _in_3_d_bits_WIRE_source; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73] assign in_3_d_bits_sink = _in_3_d_bits_WIRE_sink; // @[Mux.scala:30:73] wire _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73] assign in_3_d_bits_denied = _in_3_d_bits_WIRE_denied; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73] assign in_3_d_bits_data = _in_3_d_bits_WIRE_data; // @[Mux.scala:30:73] wire _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73] assign in_3_d_bits_corrupt = _in_3_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T = muxState_7_0 & portsDIO_filtered_3_bits_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T_1 = muxState_7_1 & portsDIO_filtered_1_3_bits_corrupt; // @[Mux.scala:30:73] wire _in_3_d_bits_T_2 = _in_3_d_bits_T | _in_3_d_bits_T_1; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_1 = _in_3_d_bits_T_2; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_corrupt = _in_3_d_bits_WIRE_1; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_3 = muxState_7_0 ? portsDIO_filtered_3_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_4 = muxState_7_1 ? portsDIO_filtered_1_3_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _in_3_d_bits_T_5 = _in_3_d_bits_T_3 | _in_3_d_bits_T_4; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_2 = _in_3_d_bits_T_5; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_data = _in_3_d_bits_WIRE_2; // @[Mux.scala:30:73] wire _in_3_d_bits_T_6 = muxState_7_0 & portsDIO_filtered_3_bits_denied; // @[Mux.scala:30:73] wire _in_3_d_bits_T_7 = muxState_7_1 & portsDIO_filtered_1_3_bits_denied; // @[Mux.scala:30:73] wire _in_3_d_bits_T_8 = _in_3_d_bits_T_6 | _in_3_d_bits_T_7; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_5 = _in_3_d_bits_T_8; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_denied = _in_3_d_bits_WIRE_5; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_9 = muxState_7_0 ? portsDIO_filtered_3_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_10 = muxState_7_1 ? portsDIO_filtered_1_3_bits_sink : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_11 = _in_3_d_bits_T_9 | _in_3_d_bits_T_10; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_6 = _in_3_d_bits_T_11; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_sink = _in_3_d_bits_WIRE_6; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_12 = muxState_7_0 ? portsDIO_filtered_3_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_13 = muxState_7_1 ? portsDIO_filtered_1_3_bits_source : 7'h0; // @[Mux.scala:30:73] wire [6:0] _in_3_d_bits_T_14 = _in_3_d_bits_T_12 | _in_3_d_bits_T_13; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_7 = _in_3_d_bits_T_14; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_source = _in_3_d_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_15 = muxState_7_0 ? portsDIO_filtered_3_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_16 = muxState_7_1 ? portsDIO_filtered_1_3_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _in_3_d_bits_T_17 = _in_3_d_bits_T_15 | _in_3_d_bits_T_16; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_8 = _in_3_d_bits_T_17; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_size = _in_3_d_bits_WIRE_8; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_18 = muxState_7_0 ? portsDIO_filtered_3_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_19 = muxState_7_1 ? portsDIO_filtered_1_3_bits_param : 2'h0; // @[Mux.scala:30:73] wire [1:0] _in_3_d_bits_T_20 = _in_3_d_bits_T_18 | _in_3_d_bits_T_19; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_9 = _in_3_d_bits_T_20; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_param = _in_3_d_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_21 = muxState_7_0 ? portsDIO_filtered_3_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_22 = muxState_7_1 ? portsDIO_filtered_1_3_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _in_3_d_bits_T_23 = _in_3_d_bits_T_21 | _in_3_d_bits_T_22; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_10 = _in_3_d_bits_T_23; // @[Mux.scala:30:73] assign _in_3_d_bits_WIRE_opcode = _in_3_d_bits_WIRE_10; // @[Mux.scala:30:73] reg [7:0] beatsLeft_8; // @[Arbiter.scala:60:30] wire idle_8 = beatsLeft_8 == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch_8 = idle_8 & in_4_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T_90 = {portsDIO_filtered_1_4_valid, portsDIO_filtered_4_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid_8 = _readys_T_90; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_91 = readys_valid_8 == _readys_T_90; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_93 = ~_readys_T_92; // @[Arbiter.scala:22:12] wire _readys_T_94 = ~_readys_T_91; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask_8; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_16 = ~readys_mask_8; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_17 = readys_valid_8 & _readys_filter_T_16; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter_8 = {_readys_filter_T_17, readys_valid_8}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T_52 = readys_filter_8[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_53 = {readys_filter_8[3], readys_filter_8[2:0] | _readys_unready_T_52}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_54 = _readys_unready_T_53; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_55 = _readys_unready_T_54[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_56 = {readys_mask_8, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready_8 = {1'h0, _readys_unready_T_55} | _readys_unready_T_56; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T_24 = readys_unready_8[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_25 = readys_unready_8[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_26 = _readys_readys_T_24 & _readys_readys_T_25; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys_8 = ~_readys_readys_T_26; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_97 = readys_readys_8; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_95 = |readys_valid_8; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_96 = latch_8 & _readys_T_95; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T_58 = readys_readys_8 & readys_valid_8; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_59 = {_readys_mask_T_58, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_60 = _readys_mask_T_59[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_61 = _readys_mask_T_58 | _readys_mask_T_60; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_62 = _readys_mask_T_61; // @[package.scala:253:43, :254:17] wire _readys_T_98 = _readys_T_97[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_8_0 = _readys_T_98; // @[Arbiter.scala:68:{27,76}] wire _readys_T_99 = _readys_T_97[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_8_1 = _readys_T_99; // @[Arbiter.scala:68:{27,76}] wire _winner_T_26 = readys_8_0 & portsDIO_filtered_4_valid; // @[Xbar.scala:352:24] wire winner_8_0 = _winner_T_26; // @[Arbiter.scala:71:{27,69}] wire _winner_T_27 = readys_8_1 & portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24] wire winner_8_1 = _winner_T_27; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_8 = winner_8_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_8 = prefixOR_1_8 | winner_8_1; // @[Arbiter.scala:71:27, :76:48] wire _in_4_d_valid_T = portsDIO_filtered_4_valid | portsDIO_filtered_1_4_valid; // @[Xbar.scala:352:24]

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = or(_T_37, _T_42) node _T_44 = and(_T_32, _T_43) node _T_45 = or(UInt<1>(0h0), _T_44) node _T_46 = and(_T_31, _T_45) node _T_47 = asUInt(reset) node _T_48 = eq(_T_47, UInt<1>(0h0)) when _T_48 : node _T_49 = eq(_T_46, UInt<1>(0h0)) when _T_49 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_46, UInt<1>(0h1), "") : assert_2 node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_52 = and(_T_50, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = or(_T_58, _T_63) node _T_65 = and(_T_53, _T_64) node _T_66 = or(UInt<1>(0h0), _T_65) node _T_67 = and(UInt<1>(0h0), _T_66) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_67, UInt<1>(0h1), "") : assert_3 node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(is_aligned, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_81, UInt<1>(0h1), "") : assert_7 node _T_85 = not(io.in.a.bits.mask) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_86, UInt<1>(0h1), "") : assert_8 node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_94 : node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_97 = and(_T_95, _T_96) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_98 = shr(io.in.a.bits.source, 4) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) node _T_101 = and(_T_99, _T_100) node _T_102 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_103 = and(_T_101, _T_102) node _T_104 = and(_T_97, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(_T_105, _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_120, UInt<1>(0h1), "") : assert_10 node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_126 = and(_T_124, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_129 = cvt(_T_128) node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000))) node _T_131 = asSInt(_T_130) node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_134 = cvt(_T_133) node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000))) node _T_136 = asSInt(_T_135) node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = or(_T_132, _T_137) node _T_139 = and(_T_127, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = and(UInt<1>(0h0), _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_141, UInt<1>(0h1), "") : assert_11 node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_148, UInt<1>(0h1), "") : assert_13 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_155, UInt<1>(0h1), "") : assert_15 node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_159, UInt<1>(0h1), "") : assert_16 node _T_163 = not(io.in.a.bits.mask) node _T_164 = eq(_T_163, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_164, UInt<1>(0h1), "") : assert_17 node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_168, UInt<1>(0h1), "") : assert_18 node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_172 : node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_175 = and(_T_173, _T_174) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_176 = shr(io.in.a.bits.source, 4) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) node _T_179 = and(_T_177, _T_178) node _T_180 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_181 = and(_T_179, _T_180) node _T_182 = and(_T_175, _T_181) node _T_183 = or(UInt<1>(0h0), _T_182) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_183, UInt<1>(0h1), "") : assert_19 node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_189 = and(_T_187, _T_188) node _T_190 = or(UInt<1>(0h0), _T_189) node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = or(_T_195, _T_200) node _T_202 = and(_T_190, _T_201) node _T_203 = or(UInt<1>(0h0), _T_202) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_203, UInt<1>(0h1), "") : assert_20 node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(is_aligned, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_213, UInt<1>(0h1), "") : assert_23 node _T_217 = eq(io.in.a.bits.mask, mask) node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(_T_217, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_217, UInt<1>(0h1), "") : assert_24 node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_221, UInt<1>(0h1), "") : assert_25 node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_225 : node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_229 = shr(io.in.a.bits.source, 4) node _T_230 = eq(_T_229, UInt<1>(0h0)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_234 = and(_T_232, _T_233) node _T_235 = and(_T_228, _T_234) node _T_236 = or(UInt<1>(0h0), _T_235) node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_239 = and(_T_237, _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_236, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_254, UInt<1>(0h1), "") : assert_26 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_264, UInt<1>(0h1), "") : assert_29 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_268, UInt<1>(0h1), "") : assert_30 node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_272 : node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_275 = and(_T_273, _T_274) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_276 = shr(io.in.a.bits.source, 4) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_281 = and(_T_279, _T_280) node _T_282 = and(_T_275, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = or(_T_292, _T_297) node _T_299 = and(_T_287, _T_298) node _T_300 = or(UInt<1>(0h0), _T_299) node _T_301 = and(_T_283, _T_300) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_301, UInt<1>(0h1), "") : assert_31 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(is_aligned, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_312 = asUInt(reset) node _T_313 = eq(_T_312, UInt<1>(0h0)) when _T_313 : node _T_314 = eq(_T_311, UInt<1>(0h0)) when _T_314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_311, UInt<1>(0h1), "") : assert_34 node _T_315 = not(mask) node _T_316 = and(io.in.a.bits.mask, _T_315) node _T_317 = eq(_T_316, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_317, UInt<1>(0h1), "") : assert_35 node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_325 = shr(io.in.a.bits.source, 4) node _T_326 = eq(_T_325, UInt<1>(0h0)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_330 = and(_T_328, _T_329) node _T_331 = and(_T_324, _T_330) node _T_332 = or(UInt<1>(0h0), _T_331) node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = or(_T_338, _T_343) node _T_345 = and(_T_333, _T_344) node _T_346 = or(UInt<1>(0h0), _T_345) node _T_347 = and(_T_332, _T_346) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_347, UInt<1>(0h1), "") : assert_36 node _T_351 = asUInt(reset) node _T_352 = eq(_T_351, UInt<1>(0h0)) when _T_352 : node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(is_aligned, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_357, UInt<1>(0h1), "") : assert_39 node _T_361 = eq(io.in.a.bits.mask, mask) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_361, UInt<1>(0h1), "") : assert_40 node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_365 : node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_369 = shr(io.in.a.bits.source, 4) node _T_370 = eq(_T_369, UInt<1>(0h0)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_374 = and(_T_372, _T_373) node _T_375 = and(_T_368, _T_374) node _T_376 = or(UInt<1>(0h0), _T_375) node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_384 = cvt(_T_383) node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000))) node _T_386 = asSInt(_T_385) node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) node _T_388 = or(_T_382, _T_387) node _T_389 = and(_T_377, _T_388) node _T_390 = or(UInt<1>(0h0), _T_389) node _T_391 = and(_T_376, _T_390) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_391, UInt<1>(0h1), "") : assert_41 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(is_aligned, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_T_401, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_401, UInt<1>(0h1), "") : assert_44 node _T_405 = eq(io.in.a.bits.mask, mask) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_405, UInt<1>(0h1), "") : assert_45 node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_409 : node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_412 = and(_T_410, _T_411) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_413 = shr(io.in.a.bits.source, 4) node _T_414 = eq(_T_413, UInt<1>(0h0)) node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) node _T_416 = and(_T_414, _T_415) node _T_417 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_418 = and(_T_416, _T_417) node _T_419 = and(_T_412, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_423 = cvt(_T_422) node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000))) node _T_425 = asSInt(_T_424) node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = or(_T_426, _T_431) node _T_433 = and(_T_421, _T_432) node _T_434 = or(UInt<1>(0h0), _T_433) node _T_435 = and(_T_420, _T_434) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_435, UInt<1>(0h1), "") : assert_46 node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(is_aligned, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_445, UInt<1>(0h1), "") : assert_49 node _T_449 = eq(io.in.a.bits.mask, mask) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_449, UInt<1>(0h1), "") : assert_50 node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_453, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_457, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_461 : node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_465, UInt<1>(0h1), "") : assert_54 node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_469, UInt<1>(0h1), "") : assert_55 node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_473, UInt<1>(0h1), "") : assert_56 node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_477, UInt<1>(0h1), "") : assert_57 node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(sink_ok, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_488, UInt<1>(0h1), "") : assert_60 node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_492, UInt<1>(0h1), "") : assert_61 node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_496, UInt<1>(0h1), "") : assert_62 node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_500, UInt<1>(0h1), "") : assert_63 node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_505 = or(UInt<1>(0h1), _T_504) node _T_506 = asUInt(reset) node _T_507 = eq(_T_506, UInt<1>(0h0)) when _T_507 : node _T_508 = eq(_T_505, UInt<1>(0h0)) when _T_508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_505, UInt<1>(0h1), "") : assert_64 node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_509 : node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(sink_ok, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_516, UInt<1>(0h1), "") : assert_67 node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_520, UInt<1>(0h1), "") : assert_68 node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_524, UInt<1>(0h1), "") : assert_69 node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_529 = or(_T_528, io.in.d.bits.corrupt) node _T_530 = asUInt(reset) node _T_531 = eq(_T_530, UInt<1>(0h0)) when _T_531 : node _T_532 = eq(_T_529, UInt<1>(0h0)) when _T_532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_529, UInt<1>(0h1), "") : assert_70 node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_534 = or(UInt<1>(0h1), _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_534, UInt<1>(0h1), "") : assert_71 node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_538 : node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_542, UInt<1>(0h1), "") : assert_73 node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_546, UInt<1>(0h1), "") : assert_74 node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_551 = or(UInt<1>(0h1), _T_550) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_551, UInt<1>(0h1), "") : assert_75 node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_555 : node _T_556 = asUInt(reset) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_559, UInt<1>(0h1), "") : assert_77 node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_564 = or(_T_563, io.in.d.bits.corrupt) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_564, UInt<1>(0h1), "") : assert_78 node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_569 = or(UInt<1>(0h1), _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_569, UInt<1>(0h1), "") : assert_79 node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_573 : node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_577, UInt<1>(0h1), "") : assert_81 node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_581, UInt<1>(0h1), "") : assert_82 node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_586 = or(UInt<1>(0h1), _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_586, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_590, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_594, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_598, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_602 = eq(a_first, UInt<1>(0h0)) node _T_603 = and(io.in.a.valid, _T_602) when _T_603 : node _T_604 = eq(io.in.a.bits.opcode, opcode) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_604, UInt<1>(0h1), "") : assert_87 node _T_608 = eq(io.in.a.bits.param, param) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_608, UInt<1>(0h1), "") : assert_88 node _T_612 = eq(io.in.a.bits.size, size) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_612, UInt<1>(0h1), "") : assert_89 node _T_616 = eq(io.in.a.bits.source, source) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_616, UInt<1>(0h1), "") : assert_90 node _T_620 = eq(io.in.a.bits.address, address) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_620, UInt<1>(0h1), "") : assert_91 node _T_624 = and(io.in.a.ready, io.in.a.valid) node _T_625 = and(_T_624, a_first) when _T_625 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_626 = eq(d_first, UInt<1>(0h0)) node _T_627 = and(io.in.d.valid, _T_626) when _T_627 : node _T_628 = eq(io.in.d.bits.opcode, opcode_1) node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(_T_628, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_628, UInt<1>(0h1), "") : assert_92 node _T_632 = eq(io.in.d.bits.param, param_1) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_632, UInt<1>(0h1), "") : assert_93 node _T_636 = eq(io.in.d.bits.size, size_1) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_636, UInt<1>(0h1), "") : assert_94 node _T_640 = eq(io.in.d.bits.source, source_1) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_640, UInt<1>(0h1), "") : assert_95 node _T_644 = eq(io.in.d.bits.sink, sink) node _T_645 = asUInt(reset) node _T_646 = eq(_T_645, UInt<1>(0h0)) when _T_646 : node _T_647 = eq(_T_644, UInt<1>(0h0)) when _T_647 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_644, UInt<1>(0h1), "") : assert_96 node _T_648 = eq(io.in.d.bits.denied, denied) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_648, UInt<1>(0h1), "") : assert_97 node _T_652 = and(io.in.d.ready, io.in.d.valid) node _T_653 = and(_T_652, d_first) when _T_653 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_654 = and(io.in.a.valid, a_first_1) node _T_655 = and(_T_654, UInt<1>(0h1)) when _T_655 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_656 = and(io.in.a.ready, io.in.a.valid) node _T_657 = and(_T_656, a_first_1) node _T_658 = and(_T_657, UInt<1>(0h1)) when _T_658 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_659 = dshr(inflight, io.in.a.bits.source) node _T_660 = bits(_T_659, 0, 0) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_661, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_665 = and(io.in.d.valid, d_first_1) node _T_666 = and(_T_665, UInt<1>(0h1)) node _T_667 = eq(d_release_ack, UInt<1>(0h0)) node _T_668 = and(_T_666, _T_667) when _T_668 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_669 = and(io.in.d.ready, io.in.d.valid) node _T_670 = and(_T_669, d_first_1) node _T_671 = and(_T_670, UInt<1>(0h1)) node _T_672 = eq(d_release_ack, UInt<1>(0h0)) node _T_673 = and(_T_671, _T_672) when _T_673 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_674 = and(io.in.d.valid, d_first_1) node _T_675 = and(_T_674, UInt<1>(0h1)) node _T_676 = eq(d_release_ack, UInt<1>(0h0)) node _T_677 = and(_T_675, _T_676) when _T_677 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_678 = dshr(inflight, io.in.d.bits.source) node _T_679 = bits(_T_678, 0, 0) node _T_680 = or(_T_679, same_cycle_resp) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_680, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_686 = or(_T_684, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_686, UInt<1>(0h1), "") : assert_100 node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_690, UInt<1>(0h1), "") : assert_101 else : node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_696 = or(_T_694, _T_695) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_696, UInt<1>(0h1), "") : assert_102 node _T_700 = eq(io.in.d.bits.size, a_size_lookup) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_700, UInt<1>(0h1), "") : assert_103 node _T_704 = and(io.in.d.valid, d_first_1) node _T_705 = and(_T_704, a_first_1) node _T_706 = and(_T_705, io.in.a.valid) node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_708 = and(_T_706, _T_707) node _T_709 = eq(d_release_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_712 = or(_T_711, io.in.a.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_712, UInt<1>(0h1), "") : assert_104 node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_717 = orr(a_set_wo_ready) node _T_718 = eq(_T_717, UInt<1>(0h0)) node _T_719 = or(_T_716, _T_718) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_719, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_92 node _T_723 = orr(inflight) node _T_724 = eq(_T_723, UInt<1>(0h0)) node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_726 = or(_T_724, _T_725) node _T_727 = lt(watchdog, plusarg_reader.out) node _T_728 = or(_T_726, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_728, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_732 = and(io.in.a.ready, io.in.a.valid) node _T_733 = and(io.in.d.ready, io.in.d.valid) node _T_734 = or(_T_732, _T_733) when _T_734 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_735 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_738 = and(_T_736, _T_737) node _T_739 = and(_T_735, _T_738) when _T_739 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_741 = and(_T_740, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_744 = and(_T_742, _T_743) node _T_745 = and(_T_741, _T_744) when _T_745 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) node _T_747 = bits(_T_746, 0, 0) node _T_748 = eq(_T_747, UInt<1>(0h0)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_748, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_752 = and(io.in.d.valid, d_first_2) node _T_753 = and(_T_752, UInt<1>(0h1)) node _T_754 = and(_T_753, d_release_ack_1) when _T_754 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_755 = and(io.in.d.ready, io.in.d.valid) node _T_756 = and(_T_755, d_first_2) node _T_757 = and(_T_756, UInt<1>(0h1)) node _T_758 = and(_T_757, d_release_ack_1) when _T_758 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_759 = and(io.in.d.valid, d_first_2) node _T_760 = and(_T_759, UInt<1>(0h1)) node _T_761 = and(_T_760, d_release_ack_1) when _T_761 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_762 = dshr(inflight_1, io.in.d.bits.source) node _T_763 = bits(_T_762, 0, 0) node _T_764 = or(_T_763, same_cycle_resp_1) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_764, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_768, UInt<1>(0h1), "") : assert_109 else : node _T_772 = eq(io.in.d.bits.size, c_size_lookup) node _T_773 = asUInt(reset) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(_T_772, UInt<1>(0h0)) when _T_775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_772, UInt<1>(0h1), "") : assert_110 node _T_776 = and(io.in.d.valid, d_first_2) node _T_777 = and(_T_776, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_778 = and(_T_777, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_780 = and(_T_778, _T_779) node _T_781 = and(_T_780, d_release_ack_1) node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) node _T_783 = and(_T_781, _T_782) when _T_783 : node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_785 = or(_T_784, _WIRE_23.ready) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_785, UInt<1>(0h1), "") : assert_111 node _T_789 = orr(c_set_wo_ready) when _T_789 : node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(_T_790, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_790, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_93 node _T_794 = orr(inflight_1) node _T_795 = eq(_T_794, UInt<1>(0h0)) node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_797 = or(_T_795, _T_796) node _T_798 = lt(watchdog_1, plusarg_reader_1.out) node _T_799 = or(_T_797, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_799, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_804 = and(io.in.d.ready, io.in.d.valid) node _T_805 = or(_T_803, _T_804) when _T_805 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PLICFanIn : input clock : Clock input reset : Reset output io : { flip prio : UInt<2>[2], flip ip : UInt<2>, dev : UInt<2>, max : UInt<2>} node effectivePriority_0 = shl(UInt<1>(0h1), 2) node _effectivePriority_T = bits(io.ip, 0, 0) node _effectivePriority_T_1 = bits(io.ip, 1, 1) node effectivePriority_1 = cat(_effectivePriority_T, io.prio[0]) node effectivePriority_2 = cat(_effectivePriority_T_1, io.prio[1]) node _left_T = geq(effectivePriority_0, effectivePriority_1) node _left_T_1 = or(UInt<1>(0h1), UInt<1>(0h0)) node left_1 = mux(_left_T, effectivePriority_0, effectivePriority_1) node left_2 = mux(_left_T, UInt<1>(0h0), _left_T_1) node _T = geq(left_1, effectivePriority_2) node _T_1 = or(UInt<2>(0h2), UInt<1>(0h0)) node maxPri = mux(_T, left_1, effectivePriority_2) node maxDev = mux(_T, left_2, _T_1) connect io.max, maxPri connect io.dev, maxDev

module PLICFanIn( // @[Plic.scala:338:7] input [1:0] io_prio_0, // @[Plic.scala:339:14] input [1:0] io_prio_1, // @[Plic.scala:339:14] input [1:0] io_ip, // @[Plic.scala:339:14] output [1:0] io_dev, // @[Plic.scala:339:14] output [1:0] io_max // @[Plic.scala:339:14] ); wire [2:0] effectivePriority_1 = {io_ip[0], io_prio_0}; // @[Plic.scala:355:{55,100}] wire [2:0] left_1 = effectivePriority_1 < 3'h5 ? 3'h4 : effectivePriority_1; // @[Misc.scala:35:9] wire _GEN = left_1 >= {io_ip[1], io_prio_1}; // @[Misc.scala:35:9] assign io_dev = _GEN ? {1'h0, effectivePriority_1 > 3'h4} : 2'h2; // @[Misc.scala:35:36] assign io_max = _GEN ? left_1[1:0] : io_prio_1; // @[Misc.scala:35:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_60 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state

module IssueSlot_60( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]

Generate the Verilog code corresponding to this FIRRTL code module Tile_172 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_428 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_172( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_428 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_50 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE : UInt<1>[13] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[7]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[8]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[9]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[10]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[11]) node source_ok = or(_source_ok_T_43, _source_ok_WIRE[12]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = and(_T_11, _T_24) node _T_129 = and(_T_128, _T_37) node _T_130 = and(_T_129, _T_50) node _T_131 = and(_T_130, _T_63) node _T_132 = and(_T_131, _T_71) node _T_133 = and(_T_132, _T_79) node _T_134 = and(_T_133, _T_87) node _T_135 = and(_T_134, _T_95) node _T_136 = and(_T_135, _T_103) node _T_137 = and(_T_136, _T_111) node _T_138 = and(_T_137, _T_119) node _T_139 = and(_T_138, _T_127) node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(_T_139, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_139, UInt<1>(0h1), "") : assert_1 node _T_143 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_143 : node _T_144 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_145 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_148 = shr(io.in.a.bits.source, 2) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = leq(UInt<1>(0h0), uncommonBits_4) node _T_151 = and(_T_149, _T_150) node _T_152 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_153 = and(_T_151, _T_152) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_154 = shr(io.in.a.bits.source, 2) node _T_155 = eq(_T_154, UInt<1>(0h1)) node _T_156 = leq(UInt<1>(0h0), uncommonBits_5) node _T_157 = and(_T_155, _T_156) node _T_158 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_159 = and(_T_157, _T_158) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_160 = shr(io.in.a.bits.source, 2) node _T_161 = eq(_T_160, UInt<2>(0h2)) node _T_162 = leq(UInt<1>(0h0), uncommonBits_6) node _T_163 = and(_T_161, _T_162) node _T_164 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_166 = shr(io.in.a.bits.source, 2) node _T_167 = eq(_T_166, UInt<2>(0h3)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_7) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_173 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_174 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_175 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_177 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_180 = or(_T_147, _T_153) node _T_181 = or(_T_180, _T_159) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_171) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_173) node _T_186 = or(_T_185, _T_174) node _T_187 = or(_T_186, _T_175) node _T_188 = or(_T_187, _T_176) node _T_189 = or(_T_188, _T_177) node _T_190 = or(_T_189, _T_178) node _T_191 = or(_T_190, _T_179) node _T_192 = and(_T_146, _T_191) node _T_193 = or(UInt<1>(0h0), _T_192) node _T_194 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_195 = or(UInt<1>(0h0), _T_194) node _T_196 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<29>(0h10000000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = or(_T_200, _T_205) node _T_207 = and(_T_195, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = and(_T_193, _T_208) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_209, UInt<1>(0h1), "") : assert_2 node _T_213 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_214 = shr(io.in.a.bits.source, 2) node _T_215 = eq(_T_214, UInt<1>(0h0)) node _T_216 = leq(UInt<1>(0h0), uncommonBits_8) node _T_217 = and(_T_215, _T_216) node _T_218 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_219 = and(_T_217, _T_218) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_220 = shr(io.in.a.bits.source, 2) node _T_221 = eq(_T_220, UInt<1>(0h1)) node _T_222 = leq(UInt<1>(0h0), uncommonBits_9) node _T_223 = and(_T_221, _T_222) node _T_224 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_225 = and(_T_223, _T_224) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_226 = shr(io.in.a.bits.source, 2) node _T_227 = eq(_T_226, UInt<2>(0h2)) node _T_228 = leq(UInt<1>(0h0), uncommonBits_10) node _T_229 = and(_T_227, _T_228) node _T_230 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_231 = and(_T_229, _T_230) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_232 = shr(io.in.a.bits.source, 2) node _T_233 = eq(_T_232, UInt<2>(0h3)) node _T_234 = leq(UInt<1>(0h0), uncommonBits_11) node _T_235 = and(_T_233, _T_234) node _T_236 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _WIRE : UInt<1>[13] connect _WIRE[0], _T_213 connect _WIRE[1], _T_219 connect _WIRE[2], _T_225 connect _WIRE[3], _T_231 connect _WIRE[4], _T_237 connect _WIRE[5], _T_238 connect _WIRE[6], _T_239 connect _WIRE[7], _T_240 connect _WIRE[8], _T_241 connect _WIRE[9], _T_242 connect _WIRE[10], _T_243 connect _WIRE[11], _T_244 connect _WIRE[12], _T_245 node _T_246 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_247 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_248 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_249 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_250 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_251 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_252 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_254 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_255 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_256 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_257 = mux(_WIRE[5], _T_246, UInt<1>(0h0)) node _T_258 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_259 = mux(_WIRE[7], _T_247, UInt<1>(0h0)) node _T_260 = mux(_WIRE[8], _T_248, UInt<1>(0h0)) node _T_261 = mux(_WIRE[9], _T_249, UInt<1>(0h0)) node _T_262 = mux(_WIRE[10], _T_250, UInt<1>(0h0)) node _T_263 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_264 = mux(_WIRE[12], _T_251, UInt<1>(0h0)) node _T_265 = or(_T_252, _T_253) node _T_266 = or(_T_265, _T_254) node _T_267 = or(_T_266, _T_255) node _T_268 = or(_T_267, _T_256) node _T_269 = or(_T_268, _T_257) node _T_270 = or(_T_269, _T_258) node _T_271 = or(_T_270, _T_259) node _T_272 = or(_T_271, _T_260) node _T_273 = or(_T_272, _T_261) node _T_274 = or(_T_273, _T_262) node _T_275 = or(_T_274, _T_263) node _T_276 = or(_T_275, _T_264) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_276 node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = or(UInt<1>(0h0), _T_279) node _T_281 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<17>(0h10000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<29>(0h10000000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = or(_T_285, _T_290) node _T_292 = and(_T_280, _T_291) node _T_293 = or(UInt<1>(0h0), _T_292) node _T_294 = and(_WIRE_1, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_294, UInt<1>(0h1), "") : assert_3 node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(source_ok, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_301 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_301, UInt<1>(0h1), "") : assert_5 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(is_aligned, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_308 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_308, UInt<1>(0h1), "") : assert_7 node _T_312 = not(io.in.a.bits.mask) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_313, UInt<1>(0h1), "") : assert_8 node _T_317 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_317, UInt<1>(0h1), "") : assert_9 node _T_321 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_321 : node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_326 = shr(io.in.a.bits.source, 2) node _T_327 = eq(_T_326, UInt<1>(0h0)) node _T_328 = leq(UInt<1>(0h0), uncommonBits_12) node _T_329 = and(_T_327, _T_328) node _T_330 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_331 = and(_T_329, _T_330) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_332 = shr(io.in.a.bits.source, 2) node _T_333 = eq(_T_332, UInt<1>(0h1)) node _T_334 = leq(UInt<1>(0h0), uncommonBits_13) node _T_335 = and(_T_333, _T_334) node _T_336 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_337 = and(_T_335, _T_336) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_338 = shr(io.in.a.bits.source, 2) node _T_339 = eq(_T_338, UInt<2>(0h2)) node _T_340 = leq(UInt<1>(0h0), uncommonBits_14) node _T_341 = and(_T_339, _T_340) node _T_342 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_343 = and(_T_341, _T_342) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_344 = shr(io.in.a.bits.source, 2) node _T_345 = eq(_T_344, UInt<2>(0h3)) node _T_346 = leq(UInt<1>(0h0), uncommonBits_15) node _T_347 = and(_T_345, _T_346) node _T_348 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_349 = and(_T_347, _T_348) node _T_350 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_351 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_352 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_355 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_356 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_357 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_358 = or(_T_325, _T_331) node _T_359 = or(_T_358, _T_337) node _T_360 = or(_T_359, _T_343) node _T_361 = or(_T_360, _T_349) node _T_362 = or(_T_361, _T_350) node _T_363 = or(_T_362, _T_351) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_353) node _T_366 = or(_T_365, _T_354) node _T_367 = or(_T_366, _T_355) node _T_368 = or(_T_367, _T_356) node _T_369 = or(_T_368, _T_357) node _T_370 = and(_T_324, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_373 = or(UInt<1>(0h0), _T_372) node _T_374 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<17>(0h10000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<29>(0h10000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = or(_T_378, _T_383) node _T_385 = and(_T_373, _T_384) node _T_386 = or(UInt<1>(0h0), _T_385) node _T_387 = and(_T_371, _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_387, UInt<1>(0h1), "") : assert_10 node _T_391 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_392 = shr(io.in.a.bits.source, 2) node _T_393 = eq(_T_392, UInt<1>(0h0)) node _T_394 = leq(UInt<1>(0h0), uncommonBits_16) node _T_395 = and(_T_393, _T_394) node _T_396 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_397 = and(_T_395, _T_396) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_398 = shr(io.in.a.bits.source, 2) node _T_399 = eq(_T_398, UInt<1>(0h1)) node _T_400 = leq(UInt<1>(0h0), uncommonBits_17) node _T_401 = and(_T_399, _T_400) node _T_402 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_403 = and(_T_401, _T_402) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_404 = shr(io.in.a.bits.source, 2) node _T_405 = eq(_T_404, UInt<2>(0h2)) node _T_406 = leq(UInt<1>(0h0), uncommonBits_18) node _T_407 = and(_T_405, _T_406) node _T_408 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_409 = and(_T_407, _T_408) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_410 = shr(io.in.a.bits.source, 2) node _T_411 = eq(_T_410, UInt<2>(0h3)) node _T_412 = leq(UInt<1>(0h0), uncommonBits_19) node _T_413 = and(_T_411, _T_412) node _T_414 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_417 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_423 = eq(io.in.a.bits.source, UInt<6>(0h20)) wire _WIRE_2 : UInt<1>[13] connect _WIRE_2[0], _T_391 connect _WIRE_2[1], _T_397 connect _WIRE_2[2], _T_403 connect _WIRE_2[3], _T_409 connect _WIRE_2[4], _T_415 connect _WIRE_2[5], _T_416 connect _WIRE_2[6], _T_417 connect _WIRE_2[7], _T_418 connect _WIRE_2[8], _T_419 connect _WIRE_2[9], _T_420 connect _WIRE_2[10], _T_421 connect _WIRE_2[11], _T_422 connect _WIRE_2[12], _T_423 node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_425 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_426 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_427 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_428 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_429 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_430 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_431 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_432 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_433 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_434 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_435 = mux(_WIRE_2[5], _T_424, UInt<1>(0h0)) node _T_436 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_437 = mux(_WIRE_2[7], _T_425, UInt<1>(0h0)) node _T_438 = mux(_WIRE_2[8], _T_426, UInt<1>(0h0)) node _T_439 = mux(_WIRE_2[9], _T_427, UInt<1>(0h0)) node _T_440 = mux(_WIRE_2[10], _T_428, UInt<1>(0h0)) node _T_441 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_442 = mux(_WIRE_2[12], _T_429, UInt<1>(0h0)) node _T_443 = or(_T_430, _T_431) node _T_444 = or(_T_443, _T_432) node _T_445 = or(_T_444, _T_433) node _T_446 = or(_T_445, _T_434) node _T_447 = or(_T_446, _T_435) node _T_448 = or(_T_447, _T_436) node _T_449 = or(_T_448, _T_437) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_439) node _T_452 = or(_T_451, _T_440) node _T_453 = or(_T_452, _T_441) node _T_454 = or(_T_453, _T_442) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_454 node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _T_458 = or(UInt<1>(0h0), _T_457) node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<29>(0h10000000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = or(_T_463, _T_468) node _T_470 = and(_T_458, _T_469) node _T_471 = or(UInt<1>(0h0), _T_470) node _T_472 = and(_WIRE_3, _T_471) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_472, UInt<1>(0h1), "") : assert_11 node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(source_ok, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_479 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_479, UInt<1>(0h1), "") : assert_13 node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(is_aligned, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_486 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_486, UInt<1>(0h1), "") : assert_15 node _T_490 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_490, UInt<1>(0h1), "") : assert_16 node _T_494 = not(io.in.a.bits.mask) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_495, UInt<1>(0h1), "") : assert_17 node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_499, UInt<1>(0h1), "") : assert_18 node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_503 : node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_20) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_514 = shr(io.in.a.bits.source, 2) node _T_515 = eq(_T_514, UInt<1>(0h1)) node _T_516 = leq(UInt<1>(0h0), uncommonBits_21) node _T_517 = and(_T_515, _T_516) node _T_518 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_519 = and(_T_517, _T_518) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_520 = shr(io.in.a.bits.source, 2) node _T_521 = eq(_T_520, UInt<2>(0h2)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_22) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_525 = and(_T_523, _T_524) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<2>(0h3)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_23) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_533 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_536 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_537 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_538 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_540 = or(_T_507, _T_513) node _T_541 = or(_T_540, _T_519) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_531) node _T_544 = or(_T_543, _T_532) node _T_545 = or(_T_544, _T_533) node _T_546 = or(_T_545, _T_534) node _T_547 = or(_T_546, _T_535) node _T_548 = or(_T_547, _T_536) node _T_549 = or(_T_548, _T_537) node _T_550 = or(_T_549, _T_538) node _T_551 = or(_T_550, _T_539) node _T_552 = and(_T_506, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_553, UInt<1>(0h1), "") : assert_19 node _T_557 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_558 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(UInt<1>(0h0), _T_559) node _T_561 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_562 = cvt(_T_561) node _T_563 = and(_T_562, asSInt(UInt<17>(0h10000))) node _T_564 = asSInt(_T_563) node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0))) node _T_566 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_567 = cvt(_T_566) node _T_568 = and(_T_567, asSInt(UInt<29>(0h10000000))) node _T_569 = asSInt(_T_568) node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0))) node _T_571 = or(_T_565, _T_570) node _T_572 = and(_T_560, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_573, UInt<1>(0h1), "") : assert_20 node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(source_ok, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(is_aligned, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_583 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(_T_583, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_583, UInt<1>(0h1), "") : assert_23 node _T_587 = eq(io.in.a.bits.mask, mask) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_587, UInt<1>(0h1), "") : assert_24 node _T_591 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_591, UInt<1>(0h1), "") : assert_25 node _T_595 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_595 : node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_598 = and(_T_596, _T_597) node _T_599 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_600 = shr(io.in.a.bits.source, 2) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = leq(UInt<1>(0h0), uncommonBits_24) node _T_603 = and(_T_601, _T_602) node _T_604 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_605 = and(_T_603, _T_604) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_606 = shr(io.in.a.bits.source, 2) node _T_607 = eq(_T_606, UInt<1>(0h1)) node _T_608 = leq(UInt<1>(0h0), uncommonBits_25) node _T_609 = and(_T_607, _T_608) node _T_610 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_611 = and(_T_609, _T_610) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_612 = shr(io.in.a.bits.source, 2) node _T_613 = eq(_T_612, UInt<2>(0h2)) node _T_614 = leq(UInt<1>(0h0), uncommonBits_26) node _T_615 = and(_T_613, _T_614) node _T_616 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_617 = and(_T_615, _T_616) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<2>(0h3)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_27) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _T_624 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_625 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_626 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_627 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_628 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_629 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_630 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_631 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_632 = or(_T_599, _T_605) node _T_633 = or(_T_632, _T_611) node _T_634 = or(_T_633, _T_617) node _T_635 = or(_T_634, _T_623) node _T_636 = or(_T_635, _T_624) node _T_637 = or(_T_636, _T_625) node _T_638 = or(_T_637, _T_626) node _T_639 = or(_T_638, _T_627) node _T_640 = or(_T_639, _T_628) node _T_641 = or(_T_640, _T_629) node _T_642 = or(_T_641, _T_630) node _T_643 = or(_T_642, _T_631) node _T_644 = and(_T_598, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_647 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_648 = and(_T_646, _T_647) node _T_649 = or(UInt<1>(0h0), _T_648) node _T_650 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<29>(0h10000000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_654, _T_659) node _T_661 = and(_T_649, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = and(_T_645, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_663, UInt<1>(0h1), "") : assert_26 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_673, UInt<1>(0h1), "") : assert_29 node _T_677 = eq(io.in.a.bits.mask, mask) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_677, UInt<1>(0h1), "") : assert_30 node _T_681 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_681 : node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_28) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_692 = shr(io.in.a.bits.source, 2) node _T_693 = eq(_T_692, UInt<1>(0h1)) node _T_694 = leq(UInt<1>(0h0), uncommonBits_29) node _T_695 = and(_T_693, _T_694) node _T_696 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_697 = and(_T_695, _T_696) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<2>(0h2)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_30) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<2>(0h3)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_31) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_712 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_713 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_714 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_718 = or(_T_685, _T_691) node _T_719 = or(_T_718, _T_697) node _T_720 = or(_T_719, _T_703) node _T_721 = or(_T_720, _T_709) node _T_722 = or(_T_721, _T_710) node _T_723 = or(_T_722, _T_711) node _T_724 = or(_T_723, _T_712) node _T_725 = or(_T_724, _T_713) node _T_726 = or(_T_725, _T_714) node _T_727 = or(_T_726, _T_715) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_717) node _T_730 = and(_T_684, _T_729) node _T_731 = or(UInt<1>(0h0), _T_730) node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_733 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_734 = and(_T_732, _T_733) node _T_735 = or(UInt<1>(0h0), _T_734) node _T_736 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<29>(0h10000000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = or(_T_740, _T_745) node _T_747 = and(_T_735, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = and(_T_731, _T_748) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_749, UInt<1>(0h1), "") : assert_31 node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(source_ok, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_756 = asUInt(reset) node _T_757 = eq(_T_756, UInt<1>(0h0)) when _T_757 : node _T_758 = eq(is_aligned, UInt<1>(0h0)) when _T_758 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_759 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_759, UInt<1>(0h1), "") : assert_34 node _T_763 = not(mask) node _T_764 = and(io.in.a.bits.mask, _T_763) node _T_765 = eq(_T_764, UInt<1>(0h0)) node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(_T_765, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_765, UInt<1>(0h1), "") : assert_35 node _T_769 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_769 : node _T_770 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_771 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_774 = shr(io.in.a.bits.source, 2) node _T_775 = eq(_T_774, UInt<1>(0h0)) node _T_776 = leq(UInt<1>(0h0), uncommonBits_32) node _T_777 = and(_T_775, _T_776) node _T_778 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_779 = and(_T_777, _T_778) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_780 = shr(io.in.a.bits.source, 2) node _T_781 = eq(_T_780, UInt<1>(0h1)) node _T_782 = leq(UInt<1>(0h0), uncommonBits_33) node _T_783 = and(_T_781, _T_782) node _T_784 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_785 = and(_T_783, _T_784) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_786 = shr(io.in.a.bits.source, 2) node _T_787 = eq(_T_786, UInt<2>(0h2)) node _T_788 = leq(UInt<1>(0h0), uncommonBits_34) node _T_789 = and(_T_787, _T_788) node _T_790 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_791 = and(_T_789, _T_790) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_792 = shr(io.in.a.bits.source, 2) node _T_793 = eq(_T_792, UInt<2>(0h3)) node _T_794 = leq(UInt<1>(0h0), uncommonBits_35) node _T_795 = and(_T_793, _T_794) node _T_796 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_797 = and(_T_795, _T_796) node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_806 = or(_T_773, _T_779) node _T_807 = or(_T_806, _T_785) node _T_808 = or(_T_807, _T_791) node _T_809 = or(_T_808, _T_797) node _T_810 = or(_T_809, _T_798) node _T_811 = or(_T_810, _T_799) node _T_812 = or(_T_811, _T_800) node _T_813 = or(_T_812, _T_801) node _T_814 = or(_T_813, _T_802) node _T_815 = or(_T_814, _T_803) node _T_816 = or(_T_815, _T_804) node _T_817 = or(_T_816, _T_805) node _T_818 = and(_T_772, _T_817) node _T_819 = or(UInt<1>(0h0), _T_818) node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_821 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_822 = and(_T_820, _T_821) node _T_823 = or(UInt<1>(0h0), _T_822) node _T_824 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<17>(0h10000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<29>(0h10000000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = or(_T_828, _T_833) node _T_835 = and(_T_823, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_819, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_837, UInt<1>(0h1), "") : assert_36 node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(source_ok, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_844 = asUInt(reset) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(is_aligned, UInt<1>(0h0)) when _T_846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_847 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_848 = asUInt(reset) node _T_849 = eq(_T_848, UInt<1>(0h0)) when _T_849 : node _T_850 = eq(_T_847, UInt<1>(0h0)) when _T_850 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_847, UInt<1>(0h1), "") : assert_39 node _T_851 = eq(io.in.a.bits.mask, mask) node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(_T_851, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_851, UInt<1>(0h1), "") : assert_40 node _T_855 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_855 : node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<1>(0h0)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_36) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_866 = shr(io.in.a.bits.source, 2) node _T_867 = eq(_T_866, UInt<1>(0h1)) node _T_868 = leq(UInt<1>(0h0), uncommonBits_37) node _T_869 = and(_T_867, _T_868) node _T_870 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_872 = shr(io.in.a.bits.source, 2) node _T_873 = eq(_T_872, UInt<2>(0h2)) node _T_874 = leq(UInt<1>(0h0), uncommonBits_38) node _T_875 = and(_T_873, _T_874) node _T_876 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_877 = and(_T_875, _T_876) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_878 = shr(io.in.a.bits.source, 2) node _T_879 = eq(_T_878, UInt<2>(0h3)) node _T_880 = leq(UInt<1>(0h0), uncommonBits_39) node _T_881 = and(_T_879, _T_880) node _T_882 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_883 = and(_T_881, _T_882) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_892 = or(_T_859, _T_865) node _T_893 = or(_T_892, _T_871) node _T_894 = or(_T_893, _T_877) node _T_895 = or(_T_894, _T_883) node _T_896 = or(_T_895, _T_884) node _T_897 = or(_T_896, _T_885) node _T_898 = or(_T_897, _T_886) node _T_899 = or(_T_898, _T_887) node _T_900 = or(_T_899, _T_888) node _T_901 = or(_T_900, _T_889) node _T_902 = or(_T_901, _T_890) node _T_903 = or(_T_902, _T_891) node _T_904 = and(_T_858, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_921) node _T_923 = and(_T_905, _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_923, UInt<1>(0h1), "") : assert_41 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(source_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(is_aligned, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_933 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_933, UInt<1>(0h1), "") : assert_44 node _T_937 = eq(io.in.a.bits.mask, mask) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_937, UInt<1>(0h1), "") : assert_45 node _T_941 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_941 : node _T_942 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_943 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_944 = and(_T_942, _T_943) node _T_945 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_946 = shr(io.in.a.bits.source, 2) node _T_947 = eq(_T_946, UInt<1>(0h0)) node _T_948 = leq(UInt<1>(0h0), uncommonBits_40) node _T_949 = and(_T_947, _T_948) node _T_950 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_951 = and(_T_949, _T_950) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_952 = shr(io.in.a.bits.source, 2) node _T_953 = eq(_T_952, UInt<1>(0h1)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_41) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_958 = shr(io.in.a.bits.source, 2) node _T_959 = eq(_T_958, UInt<2>(0h2)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_42) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_964 = shr(io.in.a.bits.source, 2) node _T_965 = eq(_T_964, UInt<2>(0h3)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_43) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_971 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_972 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_973 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_974 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_977 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_978 = or(_T_945, _T_951) node _T_979 = or(_T_978, _T_957) node _T_980 = or(_T_979, _T_963) node _T_981 = or(_T_980, _T_969) node _T_982 = or(_T_981, _T_970) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_972) node _T_985 = or(_T_984, _T_973) node _T_986 = or(_T_985, _T_974) node _T_987 = or(_T_986, _T_975) node _T_988 = or(_T_987, _T_976) node _T_989 = or(_T_988, _T_977) node _T_990 = and(_T_944, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_994 = and(_T_992, _T_993) node _T_995 = or(UInt<1>(0h0), _T_994) node _T_996 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_997 = cvt(_T_996) node _T_998 = and(_T_997, asSInt(UInt<17>(0h10000))) node _T_999 = asSInt(_T_998) node _T_1000 = eq(_T_999, asSInt(UInt<1>(0h0))) node _T_1001 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1002 = cvt(_T_1001) node _T_1003 = and(_T_1002, asSInt(UInt<29>(0h10000000))) node _T_1004 = asSInt(_T_1003) node _T_1005 = eq(_T_1004, asSInt(UInt<1>(0h0))) node _T_1006 = or(_T_1000, _T_1005) node _T_1007 = and(_T_995, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_T_991, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_46 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(is_aligned, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1019 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_49 node _T_1023 = eq(io.in.a.bits.mask, mask) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_50 node _T_1027 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1031 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_52 node _source_ok_T_44 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h0)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<1>(0h1)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h2)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<2>(0h3)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_1 : UInt<1>[13] connect _source_ok_WIRE_1[0], _source_ok_T_44 connect _source_ok_WIRE_1[1], _source_ok_T_50 connect _source_ok_WIRE_1[2], _source_ok_T_56 connect _source_ok_WIRE_1[3], _source_ok_T_62 connect _source_ok_WIRE_1[4], _source_ok_T_68 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 connect _source_ok_WIRE_1[8], _source_ok_T_72 connect _source_ok_WIRE_1[9], _source_ok_T_73 connect _source_ok_WIRE_1[10], _source_ok_T_74 connect _source_ok_WIRE_1[11], _source_ok_T_75 connect _source_ok_WIRE_1[12], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[11]) node source_ok_1 = or(_source_ok_T_87, _source_ok_WIRE_1[12]) node sink_ok = lt(io.in.d.bits.sink, UInt<3>(0h7)) node _T_1035 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(source_ok_1, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1039 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_54 node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_55 node _T_1047 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_56 node _T_1051 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_57 node _T_1055 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(sink_ok, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1062 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_60 node _T_1066 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_61 node _T_1070 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_62 node _T_1074 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_63 node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1079 = or(UInt<1>(0h1), _T_1078) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_64 node _T_1083 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1083 : node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok_1, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(sink_ok, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1090 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_67 node _T_1094 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_68 node _T_1098 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_69 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(_T_1102, io.in.d.bits.corrupt) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_70 node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1108 = or(UInt<1>(0h1), _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_71 node _T_1112 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1112 : node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1116 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_73 node _T_1120 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_74 node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1125 = or(UInt<1>(0h1), _T_1124) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_75 node _T_1129 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1129 : node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(source_ok_1, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1133 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_77 node _T_1137 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1138 = or(_T_1137, io.in.d.bits.corrupt) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_78 node _T_1142 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1143 = or(UInt<1>(0h1), _T_1142) node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(_T_1143, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1143, UInt<1>(0h1), "") : assert_79 node _T_1147 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1147 : node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(source_ok_1, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1151 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_81 node _T_1155 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_82 node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1160 = or(UInt<1>(0h1), _T_1159) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1164 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_84 node _T_1168 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) node _T_1170 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<1>(0h0))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1169, _T_1174) node _uncommonBits_T_44 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_1176 = shr(io.in.b.bits.source, 2) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) node _T_1178 = leq(UInt<1>(0h0), uncommonBits_44) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) node _T_1183 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1184 = cvt(_T_1183) node _T_1185 = and(_T_1184, asSInt(UInt<1>(0h0))) node _T_1186 = asSInt(_T_1185) node _T_1187 = eq(_T_1186, asSInt(UInt<1>(0h0))) node _T_1188 = or(_T_1182, _T_1187) node _uncommonBits_T_45 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1189 = shr(io.in.b.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h1)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) node _T_1196 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1197 = cvt(_T_1196) node _T_1198 = and(_T_1197, asSInt(UInt<1>(0h0))) node _T_1199 = asSInt(_T_1198) node _T_1200 = eq(_T_1199, asSInt(UInt<1>(0h0))) node _T_1201 = or(_T_1195, _T_1200) node _uncommonBits_T_46 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1202 = shr(io.in.b.bits.source, 2) node _T_1203 = eq(_T_1202, UInt<2>(0h2)) node _T_1204 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1205 = and(_T_1203, _T_1204) node _T_1206 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1210 = cvt(_T_1209) node _T_1211 = and(_T_1210, asSInt(UInt<1>(0h0))) node _T_1212 = asSInt(_T_1211) node _T_1213 = eq(_T_1212, asSInt(UInt<1>(0h0))) node _T_1214 = or(_T_1208, _T_1213) node _uncommonBits_T_47 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1215 = shr(io.in.b.bits.source, 2) node _T_1216 = eq(_T_1215, UInt<2>(0h3)) node _T_1217 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1220 = and(_T_1218, _T_1219) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) node _T_1238 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<1>(0h0))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = or(_T_1237, _T_1242) node _T_1244 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) node _T_1246 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1247 = cvt(_T_1246) node _T_1248 = and(_T_1247, asSInt(UInt<1>(0h0))) node _T_1249 = asSInt(_T_1248) node _T_1250 = eq(_T_1249, asSInt(UInt<1>(0h0))) node _T_1251 = or(_T_1245, _T_1250) node _T_1252 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) node _T_1254 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<1>(0h0))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = or(_T_1253, _T_1258) node _T_1260 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) node _T_1262 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1263 = cvt(_T_1262) node _T_1264 = and(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = asSInt(_T_1264) node _T_1266 = eq(_T_1265, asSInt(UInt<1>(0h0))) node _T_1267 = or(_T_1261, _T_1266) node _T_1268 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1269 = eq(_T_1268, UInt<1>(0h0)) node _T_1270 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = or(_T_1269, _T_1274) node _T_1276 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) node _T_1278 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<1>(0h0))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1277, _T_1282) node _T_1284 = eq(io.in.b.bits.source, UInt<6>(0h20)) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1287 = cvt(_T_1286) node _T_1288 = and(_T_1287, asSInt(UInt<1>(0h0))) node _T_1289 = asSInt(_T_1288) node _T_1290 = eq(_T_1289, asSInt(UInt<1>(0h0))) node _T_1291 = or(_T_1285, _T_1290) node _T_1292 = and(_T_1175, _T_1188) node _T_1293 = and(_T_1292, _T_1201) node _T_1294 = and(_T_1293, _T_1214) node _T_1295 = and(_T_1294, _T_1227) node _T_1296 = and(_T_1295, _T_1235) node _T_1297 = and(_T_1296, _T_1243) node _T_1298 = and(_T_1297, _T_1251) node _T_1299 = and(_T_1298, _T_1259) node _T_1300 = and(_T_1299, _T_1267) node _T_1301 = and(_T_1300, _T_1275) node _T_1302 = and(_T_1301, _T_1283) node _T_1303 = and(_T_1302, _T_1291) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<5>(0h10)) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T_1 = shr(io.in.b.bits.source, 2) node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0) node _legal_source_T_7 = shr(io.in.b.bits.source, 2) node _legal_source_T_8 = eq(_legal_source_T_7, UInt<1>(0h1)) node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1) node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3)) node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11) node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0) node _legal_source_T_13 = shr(io.in.b.bits.source, 2) node _legal_source_T_14 = eq(_legal_source_T_13, UInt<2>(0h2)) node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2) node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15) node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3)) node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17) node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0) node _legal_source_T_19 = shr(io.in.b.bits.source, 2) node _legal_source_T_20 = eq(_legal_source_T_19, UInt<2>(0h3)) node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3) node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21) node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3)) node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23) node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _legal_source_T_26 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _legal_source_T_27 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _legal_source_T_28 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _legal_source_T_29 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _legal_source_T_30 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _legal_source_T_31 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _legal_source_T_32 = eq(io.in.b.bits.source, UInt<6>(0h20)) wire _legal_source_WIRE : UInt<1>[13] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_12 connect _legal_source_WIRE[3], _legal_source_T_18 connect _legal_source_WIRE[4], _legal_source_T_24 connect _legal_source_WIRE[5], _legal_source_T_25 connect _legal_source_WIRE[6], _legal_source_T_26 connect _legal_source_WIRE[7], _legal_source_T_27 connect _legal_source_WIRE[8], _legal_source_T_28 connect _legal_source_WIRE[9], _legal_source_T_29 connect _legal_source_WIRE[10], _legal_source_T_30 connect _legal_source_WIRE[11], _legal_source_T_31 connect _legal_source_WIRE[12], _legal_source_T_32 node _legal_source_T_33 = mux(_legal_source_WIRE[0], UInt<5>(0h10), UInt<1>(0h0)) node _legal_source_T_34 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_35 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_36 = mux(_legal_source_WIRE[3], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_37 = mux(_legal_source_WIRE[4], UInt<4>(0hc), UInt<1>(0h0)) node _legal_source_T_38 = mux(_legal_source_WIRE[5], UInt<6>(0h24), UInt<1>(0h0)) node _legal_source_T_39 = mux(_legal_source_WIRE[6], UInt<6>(0h26), UInt<1>(0h0)) node _legal_source_T_40 = mux(_legal_source_WIRE[7], UInt<6>(0h2e), UInt<1>(0h0)) node _legal_source_T_41 = mux(_legal_source_WIRE[8], UInt<6>(0h2c), UInt<1>(0h0)) node _legal_source_T_42 = mux(_legal_source_WIRE[9], UInt<6>(0h2a), UInt<1>(0h0)) node _legal_source_T_43 = mux(_legal_source_WIRE[10], UInt<6>(0h28), UInt<1>(0h0)) node _legal_source_T_44 = mux(_legal_source_WIRE[11], UInt<6>(0h22), UInt<1>(0h0)) node _legal_source_T_45 = mux(_legal_source_WIRE[12], UInt<6>(0h20), UInt<1>(0h0)) node _legal_source_T_46 = or(_legal_source_T_33, _legal_source_T_34) node _legal_source_T_47 = or(_legal_source_T_46, _legal_source_T_35) node _legal_source_T_48 = or(_legal_source_T_47, _legal_source_T_36) node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_37) node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_38) node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_39) node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_40) node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_41) node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_42) node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_43) node _legal_source_T_56 = or(_legal_source_T_55, _legal_source_T_44) node _legal_source_T_57 = or(_legal_source_T_56, _legal_source_T_45) wire _legal_source_WIRE_1 : UInt<6> connect _legal_source_WIRE_1, _legal_source_T_57 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1307 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1307 : node _T_1308 = eq(io.in.b.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1309 = shr(io.in.b.bits.source, 2) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) node _T_1311 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1314 = and(_T_1312, _T_1313) node _uncommonBits_T_49 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1315 = shr(io.in.b.bits.source, 2) node _T_1316 = eq(_T_1315, UInt<1>(0h1)) node _T_1317 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1318 = and(_T_1316, _T_1317) node _T_1319 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1320 = and(_T_1318, _T_1319) node _uncommonBits_T_50 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1321 = shr(io.in.b.bits.source, 2) node _T_1322 = eq(_T_1321, UInt<2>(0h2)) node _T_1323 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1324 = and(_T_1322, _T_1323) node _T_1325 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1326 = and(_T_1324, _T_1325) node _uncommonBits_T_51 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1327 = shr(io.in.b.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<2>(0h3)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _T_1333 = eq(io.in.b.bits.source, UInt<6>(0h24)) node _T_1334 = eq(io.in.b.bits.source, UInt<6>(0h26)) node _T_1335 = eq(io.in.b.bits.source, UInt<6>(0h2e)) node _T_1336 = eq(io.in.b.bits.source, UInt<6>(0h2c)) node _T_1337 = eq(io.in.b.bits.source, UInt<6>(0h2a)) node _T_1338 = eq(io.in.b.bits.source, UInt<6>(0h28)) node _T_1339 = eq(io.in.b.bits.source, UInt<6>(0h22)) node _T_1340 = eq(io.in.b.bits.source, UInt<6>(0h20)) wire _WIRE_4 : UInt<1>[13] connect _WIRE_4[0], _T_1308 connect _WIRE_4[1], _T_1314 connect _WIRE_4[2], _T_1320 connect _WIRE_4[3], _T_1326 connect _WIRE_4[4], _T_1332 connect _WIRE_4[5], _T_1333 connect _WIRE_4[6], _T_1334 connect _WIRE_4[7], _T_1335 connect _WIRE_4[8], _T_1336 connect _WIRE_4[9], _T_1337 connect _WIRE_4[10], _T_1338 connect _WIRE_4[11], _T_1339 connect _WIRE_4[12], _T_1340 node _T_1341 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1342 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1343 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1344 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1345 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1346 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1347 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1348 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1349 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1350 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1351 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1352 = mux(_WIRE_4[5], _T_1341, UInt<1>(0h0)) node _T_1353 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1354 = mux(_WIRE_4[7], _T_1342, UInt<1>(0h0)) node _T_1355 = mux(_WIRE_4[8], _T_1343, UInt<1>(0h0)) node _T_1356 = mux(_WIRE_4[9], _T_1344, UInt<1>(0h0)) node _T_1357 = mux(_WIRE_4[10], _T_1345, UInt<1>(0h0)) node _T_1358 = mux(_WIRE_4[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1359 = mux(_WIRE_4[12], _T_1346, UInt<1>(0h0)) node _T_1360 = or(_T_1347, _T_1348) node _T_1361 = or(_T_1360, _T_1349) node _T_1362 = or(_T_1361, _T_1350) node _T_1363 = or(_T_1362, _T_1351) node _T_1364 = or(_T_1363, _T_1352) node _T_1365 = or(_T_1364, _T_1353) node _T_1366 = or(_T_1365, _T_1354) node _T_1367 = or(_T_1366, _T_1355) node _T_1368 = or(_T_1367, _T_1356) node _T_1369 = or(_T_1368, _T_1357) node _T_1370 = or(_T_1369, _T_1358) node _T_1371 = or(_T_1370, _T_1359) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1371 node _T_1372 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1373 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1374 = and(_T_1372, _T_1373) node _T_1375 = or(UInt<1>(0h0), _T_1374) node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<17>(0h10000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<29>(0h10000000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = or(_T_1380, _T_1385) node _T_1387 = and(_T_1375, _T_1386) node _T_1388 = or(UInt<1>(0h0), _T_1387) node _T_1389 = and(_WIRE_5, _T_1388) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_86 node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(address_ok, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(legal_source, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1402 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_90 node _T_1406 = eq(io.in.b.bits.mask, mask_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_91 node _T_1410 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_92 node _T_1414 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1414 : node _T_1415 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1416 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = or(UInt<1>(0h0), _T_1417) node _T_1419 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1420 = cvt(_T_1419) node _T_1421 = and(_T_1420, asSInt(UInt<17>(0h10000))) node _T_1422 = asSInt(_T_1421) node _T_1423 = eq(_T_1422, asSInt(UInt<1>(0h0))) node _T_1424 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1425 = cvt(_T_1424) node _T_1426 = and(_T_1425, asSInt(UInt<29>(0h10000000))) node _T_1427 = asSInt(_T_1426) node _T_1428 = eq(_T_1427, asSInt(UInt<1>(0h0))) node _T_1429 = or(_T_1423, _T_1428) node _T_1430 = and(_T_1418, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = and(UInt<1>(0h0), _T_1431) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_93 node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(address_ok, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(legal_source, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1445 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_97 node _T_1449 = eq(io.in.b.bits.mask, mask_1) node _T_1450 = asUInt(reset) node _T_1451 = eq(_T_1450, UInt<1>(0h0)) when _T_1451 : node _T_1452 = eq(_T_1449, UInt<1>(0h0)) when _T_1452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1449, UInt<1>(0h1), "") : assert_98 node _T_1453 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1454 = asUInt(reset) node _T_1455 = eq(_T_1454, UInt<1>(0h0)) when _T_1455 : node _T_1456 = eq(_T_1453, UInt<1>(0h0)) when _T_1456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1453, UInt<1>(0h1), "") : assert_99 node _T_1457 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1457 : node _T_1458 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1459 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1460 = and(_T_1458, _T_1459) node _T_1461 = or(UInt<1>(0h0), _T_1460) node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<29>(0h10000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = or(_T_1466, _T_1471) node _T_1473 = and(_T_1461, _T_1472) node _T_1474 = or(UInt<1>(0h0), _T_1473) node _T_1475 = and(UInt<1>(0h0), _T_1474) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_100 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(address_ok, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(legal_source, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1488 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_104 node _T_1492 = eq(io.in.b.bits.mask, mask_1) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_105 node _T_1496 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1496 : node _T_1497 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1498 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1499 = and(_T_1497, _T_1498) node _T_1500 = or(UInt<1>(0h0), _T_1499) node _T_1501 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1502 = cvt(_T_1501) node _T_1503 = and(_T_1502, asSInt(UInt<17>(0h10000))) node _T_1504 = asSInt(_T_1503) node _T_1505 = eq(_T_1504, asSInt(UInt<1>(0h0))) node _T_1506 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1507 = cvt(_T_1506) node _T_1508 = and(_T_1507, asSInt(UInt<29>(0h10000000))) node _T_1509 = asSInt(_T_1508) node _T_1510 = eq(_T_1509, asSInt(UInt<1>(0h0))) node _T_1511 = or(_T_1505, _T_1510) node _T_1512 = and(_T_1500, _T_1511) node _T_1513 = or(UInt<1>(0h0), _T_1512) node _T_1514 = and(UInt<1>(0h0), _T_1513) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_106 node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(address_ok, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(legal_source, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1527 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_110 node _T_1531 = not(mask_1) node _T_1532 = and(io.in.b.bits.mask, _T_1531) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_111 node _T_1537 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1537 : node _T_1538 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1539 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1540 = and(_T_1538, _T_1539) node _T_1541 = or(UInt<1>(0h0), _T_1540) node _T_1542 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1543 = cvt(_T_1542) node _T_1544 = and(_T_1543, asSInt(UInt<17>(0h10000))) node _T_1545 = asSInt(_T_1544) node _T_1546 = eq(_T_1545, asSInt(UInt<1>(0h0))) node _T_1547 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1548 = cvt(_T_1547) node _T_1549 = and(_T_1548, asSInt(UInt<29>(0h10000000))) node _T_1550 = asSInt(_T_1549) node _T_1551 = eq(_T_1550, asSInt(UInt<1>(0h0))) node _T_1552 = or(_T_1546, _T_1551) node _T_1553 = and(_T_1541, _T_1552) node _T_1554 = or(UInt<1>(0h0), _T_1553) node _T_1555 = and(UInt<1>(0h0), _T_1554) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_112 node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(address_ok, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(legal_source, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1568 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(_T_1568, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1568, UInt<1>(0h1), "") : assert_116 node _T_1572 = eq(io.in.b.bits.mask, mask_1) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_117 node _T_1576 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1576 : node _T_1577 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1578 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1579 = and(_T_1577, _T_1578) node _T_1580 = or(UInt<1>(0h0), _T_1579) node _T_1581 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1582 = cvt(_T_1581) node _T_1583 = and(_T_1582, asSInt(UInt<17>(0h10000))) node _T_1584 = asSInt(_T_1583) node _T_1585 = eq(_T_1584, asSInt(UInt<1>(0h0))) node _T_1586 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1587 = cvt(_T_1586) node _T_1588 = and(_T_1587, asSInt(UInt<29>(0h10000000))) node _T_1589 = asSInt(_T_1588) node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0))) node _T_1591 = or(_T_1585, _T_1590) node _T_1592 = and(_T_1580, _T_1591) node _T_1593 = or(UInt<1>(0h0), _T_1592) node _T_1594 = and(UInt<1>(0h0), _T_1593) node _T_1595 = asUInt(reset) node _T_1596 = eq(_T_1595, UInt<1>(0h0)) when _T_1596 : node _T_1597 = eq(_T_1594, UInt<1>(0h0)) when _T_1597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1594, UInt<1>(0h1), "") : assert_118 node _T_1598 = asUInt(reset) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) when _T_1599 : node _T_1600 = eq(address_ok, UInt<1>(0h0)) when _T_1600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(legal_source, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1607 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_122 node _T_1611 = eq(io.in.b.bits.mask, mask_1) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_123 node _T_1615 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1615 : node _T_1616 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1617 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1618 = and(_T_1616, _T_1617) node _T_1619 = or(UInt<1>(0h0), _T_1618) node _T_1620 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1621 = cvt(_T_1620) node _T_1622 = and(_T_1621, asSInt(UInt<17>(0h10000))) node _T_1623 = asSInt(_T_1622) node _T_1624 = eq(_T_1623, asSInt(UInt<1>(0h0))) node _T_1625 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1626 = cvt(_T_1625) node _T_1627 = and(_T_1626, asSInt(UInt<29>(0h10000000))) node _T_1628 = asSInt(_T_1627) node _T_1629 = eq(_T_1628, asSInt(UInt<1>(0h0))) node _T_1630 = or(_T_1624, _T_1629) node _T_1631 = and(_T_1619, _T_1630) node _T_1632 = or(UInt<1>(0h0), _T_1631) node _T_1633 = and(UInt<1>(0h0), _T_1632) node _T_1634 = asUInt(reset) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) when _T_1635 : node _T_1636 = eq(_T_1633, UInt<1>(0h0)) when _T_1636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1633, UInt<1>(0h1), "") : assert_124 node _T_1637 = asUInt(reset) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(address_ok, UInt<1>(0h0)) when _T_1639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(legal_source, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1646 = eq(io.in.b.bits.mask, mask_1) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_128 node _T_1650 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1651 = asUInt(reset) node _T_1652 = eq(_T_1651, UInt<1>(0h0)) when _T_1652 : node _T_1653 = eq(_T_1650, UInt<1>(0h0)) when _T_1653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1650, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1654 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(_T_1654, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1654, UInt<1>(0h1), "") : assert_130 node _source_ok_T_88 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_8 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_89 = shr(io.in.c.bits.source, 2) node _source_ok_T_90 = eq(_source_ok_T_89, UInt<1>(0h0)) node _source_ok_T_91 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_92 = and(_source_ok_T_90, _source_ok_T_91) node _source_ok_T_93 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_uncommonBits_T_9 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_95 = shr(io.in.c.bits.source, 2) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<1>(0h1)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_uncommonBits_T_10 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_101 = shr(io.in.c.bits.source, 2) node _source_ok_T_102 = eq(_source_ok_T_101, UInt<2>(0h2)) node _source_ok_T_103 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_T_105 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_uncommonBits_T_11 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_107 = shr(io.in.c.bits.source, 2) node _source_ok_T_108 = eq(_source_ok_T_107, UInt<2>(0h3)) node _source_ok_T_109 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_T_111 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _source_ok_T_114 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _source_ok_T_115 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _source_ok_T_116 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _source_ok_T_118 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _source_ok_T_120 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _source_ok_WIRE_2 : UInt<1>[13] connect _source_ok_WIRE_2[0], _source_ok_T_88 connect _source_ok_WIRE_2[1], _source_ok_T_94 connect _source_ok_WIRE_2[2], _source_ok_T_100 connect _source_ok_WIRE_2[3], _source_ok_T_106 connect _source_ok_WIRE_2[4], _source_ok_T_112 connect _source_ok_WIRE_2[5], _source_ok_T_113 connect _source_ok_WIRE_2[6], _source_ok_T_114 connect _source_ok_WIRE_2[7], _source_ok_T_115 connect _source_ok_WIRE_2[8], _source_ok_T_116 connect _source_ok_WIRE_2[9], _source_ok_T_117 connect _source_ok_WIRE_2[10], _source_ok_T_118 connect _source_ok_WIRE_2[11], _source_ok_T_119 connect _source_ok_WIRE_2[12], _source_ok_T_120 node _source_ok_T_121 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_2[2]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_2[3]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_2[4]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_2[5]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_2[6]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_2[7]) node _source_ok_T_128 = or(_source_ok_T_127, _source_ok_WIRE_2[8]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_2[9]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_2[10]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_2[11]) node source_ok_2 = or(_source_ok_T_131, _source_ok_WIRE_2[12]) node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _T_1658 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) node _T_1660 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1661 = cvt(_T_1660) node _T_1662 = and(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = asSInt(_T_1662) node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0))) node _T_1665 = or(_T_1659, _T_1664) node _uncommonBits_T_52 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1666 = shr(io.in.c.bits.source, 2) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) node _T_1668 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1669 = and(_T_1667, _T_1668) node _T_1670 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) node _T_1673 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1674 = cvt(_T_1673) node _T_1675 = and(_T_1674, asSInt(UInt<1>(0h0))) node _T_1676 = asSInt(_T_1675) node _T_1677 = eq(_T_1676, asSInt(UInt<1>(0h0))) node _T_1678 = or(_T_1672, _T_1677) node _uncommonBits_T_53 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1679 = shr(io.in.c.bits.source, 2) node _T_1680 = eq(_T_1679, UInt<1>(0h1)) node _T_1681 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1682 = and(_T_1680, _T_1681) node _T_1683 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1684 = and(_T_1682, _T_1683) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) node _T_1686 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1687 = cvt(_T_1686) node _T_1688 = and(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = asSInt(_T_1688) node _T_1690 = eq(_T_1689, asSInt(UInt<1>(0h0))) node _T_1691 = or(_T_1685, _T_1690) node _uncommonBits_T_54 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1692 = shr(io.in.c.bits.source, 2) node _T_1693 = eq(_T_1692, UInt<2>(0h2)) node _T_1694 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1697 = and(_T_1695, _T_1696) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) node _T_1699 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<1>(0h0))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = or(_T_1698, _T_1703) node _uncommonBits_T_55 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1705 = shr(io.in.c.bits.source, 2) node _T_1706 = eq(_T_1705, UInt<2>(0h3)) node _T_1707 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1710 = and(_T_1708, _T_1709) node _T_1711 = eq(_T_1710, UInt<1>(0h0)) node _T_1712 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1713 = cvt(_T_1712) node _T_1714 = and(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = asSInt(_T_1714) node _T_1716 = eq(_T_1715, asSInt(UInt<1>(0h0))) node _T_1717 = or(_T_1711, _T_1716) node _T_1718 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) node _T_1720 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<1>(0h0))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = or(_T_1719, _T_1724) node _T_1726 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) node _T_1728 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1729 = cvt(_T_1728) node _T_1730 = and(_T_1729, asSInt(UInt<1>(0h0))) node _T_1731 = asSInt(_T_1730) node _T_1732 = eq(_T_1731, asSInt(UInt<1>(0h0))) node _T_1733 = or(_T_1727, _T_1732) node _T_1734 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1735 = eq(_T_1734, UInt<1>(0h0)) node _T_1736 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1737 = cvt(_T_1736) node _T_1738 = and(_T_1737, asSInt(UInt<1>(0h0))) node _T_1739 = asSInt(_T_1738) node _T_1740 = eq(_T_1739, asSInt(UInt<1>(0h0))) node _T_1741 = or(_T_1735, _T_1740) node _T_1742 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) node _T_1744 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1745 = cvt(_T_1744) node _T_1746 = and(_T_1745, asSInt(UInt<1>(0h0))) node _T_1747 = asSInt(_T_1746) node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0))) node _T_1749 = or(_T_1743, _T_1748) node _T_1750 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1751 = eq(_T_1750, UInt<1>(0h0)) node _T_1752 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1753 = cvt(_T_1752) node _T_1754 = and(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = asSInt(_T_1754) node _T_1756 = eq(_T_1755, asSInt(UInt<1>(0h0))) node _T_1757 = or(_T_1751, _T_1756) node _T_1758 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1761 = cvt(_T_1760) node _T_1762 = and(_T_1761, asSInt(UInt<1>(0h0))) node _T_1763 = asSInt(_T_1762) node _T_1764 = eq(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = or(_T_1759, _T_1764) node _T_1766 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) node _T_1768 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1769 = cvt(_T_1768) node _T_1770 = and(_T_1769, asSInt(UInt<1>(0h0))) node _T_1771 = asSInt(_T_1770) node _T_1772 = eq(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = or(_T_1767, _T_1772) node _T_1774 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) node _T_1776 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1777 = cvt(_T_1776) node _T_1778 = and(_T_1777, asSInt(UInt<1>(0h0))) node _T_1779 = asSInt(_T_1778) node _T_1780 = eq(_T_1779, asSInt(UInt<1>(0h0))) node _T_1781 = or(_T_1775, _T_1780) node _T_1782 = and(_T_1665, _T_1678) node _T_1783 = and(_T_1782, _T_1691) node _T_1784 = and(_T_1783, _T_1704) node _T_1785 = and(_T_1784, _T_1717) node _T_1786 = and(_T_1785, _T_1725) node _T_1787 = and(_T_1786, _T_1733) node _T_1788 = and(_T_1787, _T_1741) node _T_1789 = and(_T_1788, _T_1749) node _T_1790 = and(_T_1789, _T_1757) node _T_1791 = and(_T_1790, _T_1765) node _T_1792 = and(_T_1791, _T_1773) node _T_1793 = and(_T_1792, _T_1781) node _T_1794 = asUInt(reset) node _T_1795 = eq(_T_1794, UInt<1>(0h0)) when _T_1795 : node _T_1796 = eq(_T_1793, UInt<1>(0h0)) when _T_1796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1793, UInt<1>(0h1), "") : assert_131 node _T_1797 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1797 : node _T_1798 = asUInt(reset) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) when _T_1799 : node _T_1800 = eq(address_ok_1, UInt<1>(0h0)) when _T_1800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(source_ok_2, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1804 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1805 = asUInt(reset) node _T_1806 = eq(_T_1805, UInt<1>(0h0)) when _T_1806 : node _T_1807 = eq(_T_1804, UInt<1>(0h0)) when _T_1807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1804, UInt<1>(0h1), "") : assert_134 node _T_1808 = asUInt(reset) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) when _T_1809 : node _T_1810 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1811 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1812 = asUInt(reset) node _T_1813 = eq(_T_1812, UInt<1>(0h0)) when _T_1813 : node _T_1814 = eq(_T_1811, UInt<1>(0h0)) when _T_1814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1811, UInt<1>(0h1), "") : assert_136 node _T_1815 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1816 = asUInt(reset) node _T_1817 = eq(_T_1816, UInt<1>(0h0)) when _T_1817 : node _T_1818 = eq(_T_1815, UInt<1>(0h0)) when _T_1818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1815, UInt<1>(0h1), "") : assert_137 node _T_1819 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1819 : node _T_1820 = asUInt(reset) node _T_1821 = eq(_T_1820, UInt<1>(0h0)) when _T_1821 : node _T_1822 = eq(address_ok_1, UInt<1>(0h0)) when _T_1822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(source_ok_2, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1826 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1827 = asUInt(reset) node _T_1828 = eq(_T_1827, UInt<1>(0h0)) when _T_1828 : node _T_1829 = eq(_T_1826, UInt<1>(0h0)) when _T_1829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1826, UInt<1>(0h1), "") : assert_140 node _T_1830 = asUInt(reset) node _T_1831 = eq(_T_1830, UInt<1>(0h0)) when _T_1831 : node _T_1832 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1832 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1833 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1834 = asUInt(reset) node _T_1835 = eq(_T_1834, UInt<1>(0h0)) when _T_1835 : node _T_1836 = eq(_T_1833, UInt<1>(0h0)) when _T_1836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1833, UInt<1>(0h1), "") : assert_142 node _T_1837 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1837 : node _T_1838 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1839 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1840 = and(_T_1838, _T_1839) node _T_1841 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_56 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1842 = shr(io.in.c.bits.source, 2) node _T_1843 = eq(_T_1842, UInt<1>(0h0)) node _T_1844 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1845 = and(_T_1843, _T_1844) node _T_1846 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1847 = and(_T_1845, _T_1846) node _uncommonBits_T_57 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1848 = shr(io.in.c.bits.source, 2) node _T_1849 = eq(_T_1848, UInt<1>(0h1)) node _T_1850 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1851 = and(_T_1849, _T_1850) node _T_1852 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1853 = and(_T_1851, _T_1852) node _uncommonBits_T_58 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0) node _T_1854 = shr(io.in.c.bits.source, 2) node _T_1855 = eq(_T_1854, UInt<2>(0h2)) node _T_1856 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1857 = and(_T_1855, _T_1856) node _T_1858 = leq(uncommonBits_58, UInt<2>(0h3)) node _T_1859 = and(_T_1857, _T_1858) node _uncommonBits_T_59 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0) node _T_1860 = shr(io.in.c.bits.source, 2) node _T_1861 = eq(_T_1860, UInt<2>(0h3)) node _T_1862 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1863 = and(_T_1861, _T_1862) node _T_1864 = leq(uncommonBits_59, UInt<2>(0h3)) node _T_1865 = and(_T_1863, _T_1864) node _T_1866 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1867 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1868 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1869 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1870 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1871 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1872 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1873 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_1874 = or(_T_1841, _T_1847) node _T_1875 = or(_T_1874, _T_1853) node _T_1876 = or(_T_1875, _T_1859) node _T_1877 = or(_T_1876, _T_1865) node _T_1878 = or(_T_1877, _T_1866) node _T_1879 = or(_T_1878, _T_1867) node _T_1880 = or(_T_1879, _T_1868) node _T_1881 = or(_T_1880, _T_1869) node _T_1882 = or(_T_1881, _T_1870) node _T_1883 = or(_T_1882, _T_1871) node _T_1884 = or(_T_1883, _T_1872) node _T_1885 = or(_T_1884, _T_1873) node _T_1886 = and(_T_1840, _T_1885) node _T_1887 = or(UInt<1>(0h0), _T_1886) node _T_1888 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1889 = or(UInt<1>(0h0), _T_1888) node _T_1890 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1891 = cvt(_T_1890) node _T_1892 = and(_T_1891, asSInt(UInt<17>(0h10000))) node _T_1893 = asSInt(_T_1892) node _T_1894 = eq(_T_1893, asSInt(UInt<1>(0h0))) node _T_1895 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1896 = cvt(_T_1895) node _T_1897 = and(_T_1896, asSInt(UInt<29>(0h10000000))) node _T_1898 = asSInt(_T_1897) node _T_1899 = eq(_T_1898, asSInt(UInt<1>(0h0))) node _T_1900 = or(_T_1894, _T_1899) node _T_1901 = and(_T_1889, _T_1900) node _T_1902 = or(UInt<1>(0h0), _T_1901) node _T_1903 = and(_T_1887, _T_1902) node _T_1904 = asUInt(reset) node _T_1905 = eq(_T_1904, UInt<1>(0h0)) when _T_1905 : node _T_1906 = eq(_T_1903, UInt<1>(0h0)) when _T_1906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1903, UInt<1>(0h1), "") : assert_143 node _T_1907 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1908 = shr(io.in.c.bits.source, 2) node _T_1909 = eq(_T_1908, UInt<1>(0h0)) node _T_1910 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1911 = and(_T_1909, _T_1910) node _T_1912 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1913 = and(_T_1911, _T_1912) node _uncommonBits_T_61 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1914 = shr(io.in.c.bits.source, 2) node _T_1915 = eq(_T_1914, UInt<1>(0h1)) node _T_1916 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1917 = and(_T_1915, _T_1916) node _T_1918 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1919 = and(_T_1917, _T_1918) node _uncommonBits_T_62 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1920 = shr(io.in.c.bits.source, 2) node _T_1921 = eq(_T_1920, UInt<2>(0h2)) node _T_1922 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1923 = and(_T_1921, _T_1922) node _T_1924 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1925 = and(_T_1923, _T_1924) node _uncommonBits_T_63 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1926 = shr(io.in.c.bits.source, 2) node _T_1927 = eq(_T_1926, UInt<2>(0h3)) node _T_1928 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1929 = and(_T_1927, _T_1928) node _T_1930 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1931 = and(_T_1929, _T_1930) node _T_1932 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_1933 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_1934 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_1935 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_1936 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_1937 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_1938 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_1939 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _WIRE_6 : UInt<1>[13] connect _WIRE_6[0], _T_1907 connect _WIRE_6[1], _T_1913 connect _WIRE_6[2], _T_1919 connect _WIRE_6[3], _T_1925 connect _WIRE_6[4], _T_1931 connect _WIRE_6[5], _T_1932 connect _WIRE_6[6], _T_1933 connect _WIRE_6[7], _T_1934 connect _WIRE_6[8], _T_1935 connect _WIRE_6[9], _T_1936 connect _WIRE_6[10], _T_1937 connect _WIRE_6[11], _T_1938 connect _WIRE_6[12], _T_1939 node _T_1940 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1941 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1942 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1943 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1944 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1945 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1946 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_1947 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1948 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1949 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_1950 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_1951 = mux(_WIRE_6[5], _T_1940, UInt<1>(0h0)) node _T_1952 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_1953 = mux(_WIRE_6[7], _T_1941, UInt<1>(0h0)) node _T_1954 = mux(_WIRE_6[8], _T_1942, UInt<1>(0h0)) node _T_1955 = mux(_WIRE_6[9], _T_1943, UInt<1>(0h0)) node _T_1956 = mux(_WIRE_6[10], _T_1944, UInt<1>(0h0)) node _T_1957 = mux(_WIRE_6[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_1958 = mux(_WIRE_6[12], _T_1945, UInt<1>(0h0)) node _T_1959 = or(_T_1946, _T_1947) node _T_1960 = or(_T_1959, _T_1948) node _T_1961 = or(_T_1960, _T_1949) node _T_1962 = or(_T_1961, _T_1950) node _T_1963 = or(_T_1962, _T_1951) node _T_1964 = or(_T_1963, _T_1952) node _T_1965 = or(_T_1964, _T_1953) node _T_1966 = or(_T_1965, _T_1954) node _T_1967 = or(_T_1966, _T_1955) node _T_1968 = or(_T_1967, _T_1956) node _T_1969 = or(_T_1968, _T_1957) node _T_1970 = or(_T_1969, _T_1958) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1970 node _T_1971 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1972 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1973 = and(_T_1971, _T_1972) node _T_1974 = or(UInt<1>(0h0), _T_1973) node _T_1975 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1976 = cvt(_T_1975) node _T_1977 = and(_T_1976, asSInt(UInt<17>(0h10000))) node _T_1978 = asSInt(_T_1977) node _T_1979 = eq(_T_1978, asSInt(UInt<1>(0h0))) node _T_1980 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1981 = cvt(_T_1980) node _T_1982 = and(_T_1981, asSInt(UInt<29>(0h10000000))) node _T_1983 = asSInt(_T_1982) node _T_1984 = eq(_T_1983, asSInt(UInt<1>(0h0))) node _T_1985 = or(_T_1979, _T_1984) node _T_1986 = and(_T_1974, _T_1985) node _T_1987 = or(UInt<1>(0h0), _T_1986) node _T_1988 = and(_WIRE_7, _T_1987) node _T_1989 = asUInt(reset) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) when _T_1990 : node _T_1991 = eq(_T_1988, UInt<1>(0h0)) when _T_1991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1988, UInt<1>(0h1), "") : assert_144 node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(source_ok_2, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1995 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_146 node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2002 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_148 node _T_2006 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_149 node _T_2010 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2010 : node _T_2011 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2012 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2013 = and(_T_2011, _T_2012) node _T_2014 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_64 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0) node _T_2015 = shr(io.in.c.bits.source, 2) node _T_2016 = eq(_T_2015, UInt<1>(0h0)) node _T_2017 = leq(UInt<1>(0h0), uncommonBits_64) node _T_2018 = and(_T_2016, _T_2017) node _T_2019 = leq(uncommonBits_64, UInt<2>(0h3)) node _T_2020 = and(_T_2018, _T_2019) node _uncommonBits_T_65 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0) node _T_2021 = shr(io.in.c.bits.source, 2) node _T_2022 = eq(_T_2021, UInt<1>(0h1)) node _T_2023 = leq(UInt<1>(0h0), uncommonBits_65) node _T_2024 = and(_T_2022, _T_2023) node _T_2025 = leq(uncommonBits_65, UInt<2>(0h3)) node _T_2026 = and(_T_2024, _T_2025) node _uncommonBits_T_66 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0) node _T_2027 = shr(io.in.c.bits.source, 2) node _T_2028 = eq(_T_2027, UInt<2>(0h2)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_66) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_66, UInt<2>(0h3)) node _T_2032 = and(_T_2030, _T_2031) node _uncommonBits_T_67 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0) node _T_2033 = shr(io.in.c.bits.source, 2) node _T_2034 = eq(_T_2033, UInt<2>(0h3)) node _T_2035 = leq(UInt<1>(0h0), uncommonBits_67) node _T_2036 = and(_T_2034, _T_2035) node _T_2037 = leq(uncommonBits_67, UInt<2>(0h3)) node _T_2038 = and(_T_2036, _T_2037) node _T_2039 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2040 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2041 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2042 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2043 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2044 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2045 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2046 = eq(io.in.c.bits.source, UInt<6>(0h20)) node _T_2047 = or(_T_2014, _T_2020) node _T_2048 = or(_T_2047, _T_2026) node _T_2049 = or(_T_2048, _T_2032) node _T_2050 = or(_T_2049, _T_2038) node _T_2051 = or(_T_2050, _T_2039) node _T_2052 = or(_T_2051, _T_2040) node _T_2053 = or(_T_2052, _T_2041) node _T_2054 = or(_T_2053, _T_2042) node _T_2055 = or(_T_2054, _T_2043) node _T_2056 = or(_T_2055, _T_2044) node _T_2057 = or(_T_2056, _T_2045) node _T_2058 = or(_T_2057, _T_2046) node _T_2059 = and(_T_2013, _T_2058) node _T_2060 = or(UInt<1>(0h0), _T_2059) node _T_2061 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2062 = or(UInt<1>(0h0), _T_2061) node _T_2063 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2064 = cvt(_T_2063) node _T_2065 = and(_T_2064, asSInt(UInt<17>(0h10000))) node _T_2066 = asSInt(_T_2065) node _T_2067 = eq(_T_2066, asSInt(UInt<1>(0h0))) node _T_2068 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2069 = cvt(_T_2068) node _T_2070 = and(_T_2069, asSInt(UInt<29>(0h10000000))) node _T_2071 = asSInt(_T_2070) node _T_2072 = eq(_T_2071, asSInt(UInt<1>(0h0))) node _T_2073 = or(_T_2067, _T_2072) node _T_2074 = and(_T_2062, _T_2073) node _T_2075 = or(UInt<1>(0h0), _T_2074) node _T_2076 = and(_T_2060, _T_2075) node _T_2077 = asUInt(reset) node _T_2078 = eq(_T_2077, UInt<1>(0h0)) when _T_2078 : node _T_2079 = eq(_T_2076, UInt<1>(0h0)) when _T_2079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2076, UInt<1>(0h1), "") : assert_150 node _T_2080 = eq(io.in.c.bits.source, UInt<5>(0h10)) node _uncommonBits_T_68 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0) node _T_2081 = shr(io.in.c.bits.source, 2) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) node _T_2083 = leq(UInt<1>(0h0), uncommonBits_68) node _T_2084 = and(_T_2082, _T_2083) node _T_2085 = leq(uncommonBits_68, UInt<2>(0h3)) node _T_2086 = and(_T_2084, _T_2085) node _uncommonBits_T_69 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0) node _T_2087 = shr(io.in.c.bits.source, 2) node _T_2088 = eq(_T_2087, UInt<1>(0h1)) node _T_2089 = leq(UInt<1>(0h0), uncommonBits_69) node _T_2090 = and(_T_2088, _T_2089) node _T_2091 = leq(uncommonBits_69, UInt<2>(0h3)) node _T_2092 = and(_T_2090, _T_2091) node _uncommonBits_T_70 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0) node _T_2093 = shr(io.in.c.bits.source, 2) node _T_2094 = eq(_T_2093, UInt<2>(0h2)) node _T_2095 = leq(UInt<1>(0h0), uncommonBits_70) node _T_2096 = and(_T_2094, _T_2095) node _T_2097 = leq(uncommonBits_70, UInt<2>(0h3)) node _T_2098 = and(_T_2096, _T_2097) node _uncommonBits_T_71 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0) node _T_2099 = shr(io.in.c.bits.source, 2) node _T_2100 = eq(_T_2099, UInt<2>(0h3)) node _T_2101 = leq(UInt<1>(0h0), uncommonBits_71) node _T_2102 = and(_T_2100, _T_2101) node _T_2103 = leq(uncommonBits_71, UInt<2>(0h3)) node _T_2104 = and(_T_2102, _T_2103) node _T_2105 = eq(io.in.c.bits.source, UInt<6>(0h24)) node _T_2106 = eq(io.in.c.bits.source, UInt<6>(0h26)) node _T_2107 = eq(io.in.c.bits.source, UInt<6>(0h2e)) node _T_2108 = eq(io.in.c.bits.source, UInt<6>(0h2c)) node _T_2109 = eq(io.in.c.bits.source, UInt<6>(0h2a)) node _T_2110 = eq(io.in.c.bits.source, UInt<6>(0h28)) node _T_2111 = eq(io.in.c.bits.source, UInt<6>(0h22)) node _T_2112 = eq(io.in.c.bits.source, UInt<6>(0h20)) wire _WIRE_8 : UInt<1>[13] connect _WIRE_8[0], _T_2080 connect _WIRE_8[1], _T_2086 connect _WIRE_8[2], _T_2092 connect _WIRE_8[3], _T_2098 connect _WIRE_8[4], _T_2104 connect _WIRE_8[5], _T_2105 connect _WIRE_8[6], _T_2106 connect _WIRE_8[7], _T_2107 connect _WIRE_8[8], _T_2108 connect _WIRE_8[9], _T_2109 connect _WIRE_8[10], _T_2110 connect _WIRE_8[11], _T_2111 connect _WIRE_8[12], _T_2112 node _T_2113 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2114 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2115 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2116 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2117 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2118 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2119 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_2120 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2121 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2122 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_2123 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_2124 = mux(_WIRE_8[5], _T_2113, UInt<1>(0h0)) node _T_2125 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_2126 = mux(_WIRE_8[7], _T_2114, UInt<1>(0h0)) node _T_2127 = mux(_WIRE_8[8], _T_2115, UInt<1>(0h0)) node _T_2128 = mux(_WIRE_8[9], _T_2116, UInt<1>(0h0)) node _T_2129 = mux(_WIRE_8[10], _T_2117, UInt<1>(0h0)) node _T_2130 = mux(_WIRE_8[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_2131 = mux(_WIRE_8[12], _T_2118, UInt<1>(0h0)) node _T_2132 = or(_T_2119, _T_2120) node _T_2133 = or(_T_2132, _T_2121) node _T_2134 = or(_T_2133, _T_2122) node _T_2135 = or(_T_2134, _T_2123) node _T_2136 = or(_T_2135, _T_2124) node _T_2137 = or(_T_2136, _T_2125) node _T_2138 = or(_T_2137, _T_2126) node _T_2139 = or(_T_2138, _T_2127) node _T_2140 = or(_T_2139, _T_2128) node _T_2141 = or(_T_2140, _T_2129) node _T_2142 = or(_T_2141, _T_2130) node _T_2143 = or(_T_2142, _T_2131) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2143 node _T_2144 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2145 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2146 = and(_T_2144, _T_2145) node _T_2147 = or(UInt<1>(0h0), _T_2146) node _T_2148 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2149 = cvt(_T_2148) node _T_2150 = and(_T_2149, asSInt(UInt<17>(0h10000))) node _T_2151 = asSInt(_T_2150) node _T_2152 = eq(_T_2151, asSInt(UInt<1>(0h0))) node _T_2153 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2154 = cvt(_T_2153) node _T_2155 = and(_T_2154, asSInt(UInt<29>(0h10000000))) node _T_2156 = asSInt(_T_2155) node _T_2157 = eq(_T_2156, asSInt(UInt<1>(0h0))) node _T_2158 = or(_T_2152, _T_2157) node _T_2159 = and(_T_2147, _T_2158) node _T_2160 = or(UInt<1>(0h0), _T_2159) node _T_2161 = and(_WIRE_9, _T_2160) node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(_T_2161, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2161, UInt<1>(0h1), "") : assert_151 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(source_ok_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2168 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_153 node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2175 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_155 node _T_2179 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2179 : node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(address_ok_1, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(source_ok_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2186 = asUInt(reset) node _T_2187 = eq(_T_2186, UInt<1>(0h0)) when _T_2187 : node _T_2188 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2189 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2190 = asUInt(reset) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) when _T_2191 : node _T_2192 = eq(_T_2189, UInt<1>(0h0)) when _T_2192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2189, UInt<1>(0h1), "") : assert_159 node _T_2193 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(_T_2193, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2193, UInt<1>(0h1), "") : assert_160 node _T_2197 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2197 : node _T_2198 = asUInt(reset) node _T_2199 = eq(_T_2198, UInt<1>(0h0)) when _T_2199 : node _T_2200 = eq(address_ok_1, UInt<1>(0h0)) when _T_2200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(source_ok_2, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : node _T_2206 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2207 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(_T_2207, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2207, UInt<1>(0h1), "") : assert_164 node _T_2211 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2211 : node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : node _T_2214 = eq(address_ok_1, UInt<1>(0h0)) when _T_2214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2215 = asUInt(reset) node _T_2216 = eq(_T_2215, UInt<1>(0h0)) when _T_2216 : node _T_2217 = eq(source_ok_2, UInt<1>(0h0)) when _T_2217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2221 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_168 node _T_2225 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<3>(0h7)) node _T_2229 = asUInt(reset) node _T_2230 = eq(_T_2229, UInt<1>(0h0)) when _T_2230 : node _T_2231 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2232 = eq(a_first, UInt<1>(0h0)) node _T_2233 = and(io.in.a.valid, _T_2232) when _T_2233 : node _T_2234 = eq(io.in.a.bits.opcode, opcode) node _T_2235 = asUInt(reset) node _T_2236 = eq(_T_2235, UInt<1>(0h0)) when _T_2236 : node _T_2237 = eq(_T_2234, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2234, UInt<1>(0h1), "") : assert_171 node _T_2238 = eq(io.in.a.bits.param, param) node _T_2239 = asUInt(reset) node _T_2240 = eq(_T_2239, UInt<1>(0h0)) when _T_2240 : node _T_2241 = eq(_T_2238, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2238, UInt<1>(0h1), "") : assert_172 node _T_2242 = eq(io.in.a.bits.size, size) node _T_2243 = asUInt(reset) node _T_2244 = eq(_T_2243, UInt<1>(0h0)) when _T_2244 : node _T_2245 = eq(_T_2242, UInt<1>(0h0)) when _T_2245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2242, UInt<1>(0h1), "") : assert_173 node _T_2246 = eq(io.in.a.bits.source, source) node _T_2247 = asUInt(reset) node _T_2248 = eq(_T_2247, UInt<1>(0h0)) when _T_2248 : node _T_2249 = eq(_T_2246, UInt<1>(0h0)) when _T_2249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2246, UInt<1>(0h1), "") : assert_174 node _T_2250 = eq(io.in.a.bits.address, address) node _T_2251 = asUInt(reset) node _T_2252 = eq(_T_2251, UInt<1>(0h0)) when _T_2252 : node _T_2253 = eq(_T_2250, UInt<1>(0h0)) when _T_2253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2250, UInt<1>(0h1), "") : assert_175 node _T_2254 = and(io.in.a.ready, io.in.a.valid) node _T_2255 = and(_T_2254, a_first) when _T_2255 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2256 = eq(d_first, UInt<1>(0h0)) node _T_2257 = and(io.in.d.valid, _T_2256) when _T_2257 : node _T_2258 = eq(io.in.d.bits.opcode, opcode_1) node _T_2259 = asUInt(reset) node _T_2260 = eq(_T_2259, UInt<1>(0h0)) when _T_2260 : node _T_2261 = eq(_T_2258, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2258, UInt<1>(0h1), "") : assert_176 node _T_2262 = eq(io.in.d.bits.param, param_1) node _T_2263 = asUInt(reset) node _T_2264 = eq(_T_2263, UInt<1>(0h0)) when _T_2264 : node _T_2265 = eq(_T_2262, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2262, UInt<1>(0h1), "") : assert_177 node _T_2266 = eq(io.in.d.bits.size, size_1) node _T_2267 = asUInt(reset) node _T_2268 = eq(_T_2267, UInt<1>(0h0)) when _T_2268 : node _T_2269 = eq(_T_2266, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2266, UInt<1>(0h1), "") : assert_178 node _T_2270 = eq(io.in.d.bits.source, source_1) node _T_2271 = asUInt(reset) node _T_2272 = eq(_T_2271, UInt<1>(0h0)) when _T_2272 : node _T_2273 = eq(_T_2270, UInt<1>(0h0)) when _T_2273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2270, UInt<1>(0h1), "") : assert_179 node _T_2274 = eq(io.in.d.bits.sink, sink) node _T_2275 = asUInt(reset) node _T_2276 = eq(_T_2275, UInt<1>(0h0)) when _T_2276 : node _T_2277 = eq(_T_2274, UInt<1>(0h0)) when _T_2277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2274, UInt<1>(0h1), "") : assert_180 node _T_2278 = eq(io.in.d.bits.denied, denied) node _T_2279 = asUInt(reset) node _T_2280 = eq(_T_2279, UInt<1>(0h0)) when _T_2280 : node _T_2281 = eq(_T_2278, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2278, UInt<1>(0h1), "") : assert_181 node _T_2282 = and(io.in.d.ready, io.in.d.valid) node _T_2283 = and(_T_2282, d_first) when _T_2283 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2284 = eq(b_first, UInt<1>(0h0)) node _T_2285 = and(io.in.b.valid, _T_2284) when _T_2285 : node _T_2286 = eq(io.in.b.bits.opcode, opcode_2) node _T_2287 = asUInt(reset) node _T_2288 = eq(_T_2287, UInt<1>(0h0)) when _T_2288 : node _T_2289 = eq(_T_2286, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2286, UInt<1>(0h1), "") : assert_182 node _T_2290 = eq(io.in.b.bits.param, param_2) node _T_2291 = asUInt(reset) node _T_2292 = eq(_T_2291, UInt<1>(0h0)) when _T_2292 : node _T_2293 = eq(_T_2290, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2290, UInt<1>(0h1), "") : assert_183 node _T_2294 = eq(io.in.b.bits.size, size_2) node _T_2295 = asUInt(reset) node _T_2296 = eq(_T_2295, UInt<1>(0h0)) when _T_2296 : node _T_2297 = eq(_T_2294, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2294, UInt<1>(0h1), "") : assert_184 node _T_2298 = eq(io.in.b.bits.source, source_2) node _T_2299 = asUInt(reset) node _T_2300 = eq(_T_2299, UInt<1>(0h0)) when _T_2300 : node _T_2301 = eq(_T_2298, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2298, UInt<1>(0h1), "") : assert_185 node _T_2302 = eq(io.in.b.bits.address, address_1) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_186 node _T_2306 = and(io.in.b.ready, io.in.b.valid) node _T_2307 = and(_T_2306, b_first) when _T_2307 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2308 = eq(c_first, UInt<1>(0h0)) node _T_2309 = and(io.in.c.valid, _T_2308) when _T_2309 : node _T_2310 = eq(io.in.c.bits.opcode, opcode_3) node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(_T_2310, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2310, UInt<1>(0h1), "") : assert_187 node _T_2314 = eq(io.in.c.bits.param, param_3) node _T_2315 = asUInt(reset) node _T_2316 = eq(_T_2315, UInt<1>(0h0)) when _T_2316 : node _T_2317 = eq(_T_2314, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2314, UInt<1>(0h1), "") : assert_188 node _T_2318 = eq(io.in.c.bits.size, size_3) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_189 node _T_2322 = eq(io.in.c.bits.source, source_3) node _T_2323 = asUInt(reset) node _T_2324 = eq(_T_2323, UInt<1>(0h0)) when _T_2324 : node _T_2325 = eq(_T_2322, UInt<1>(0h0)) when _T_2325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2322, UInt<1>(0h1), "") : assert_190 node _T_2326 = eq(io.in.c.bits.address, address_2) node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(_T_2326, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2326, UInt<1>(0h1), "") : assert_191 node _T_2330 = and(io.in.c.ready, io.in.c.valid) node _T_2331 = and(_T_2330, c_first) when _T_2331 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes : UInt<188>, clock, reset, UInt<188>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<47> connect a_set, UInt<47>(0h0) wire a_set_wo_ready : UInt<47> connect a_set_wo_ready, UInt<47>(0h0) wire a_opcodes_set : UInt<188> connect a_opcodes_set, UInt<188>(0h0) wire a_sizes_set : UInt<188> connect a_sizes_set, UInt<188>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2332 = and(io.in.a.valid, a_first_1) node _T_2333 = and(_T_2332, UInt<1>(0h1)) when _T_2333 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2334 = and(io.in.a.ready, io.in.a.valid) node _T_2335 = and(_T_2334, a_first_1) node _T_2336 = and(_T_2335, UInt<1>(0h1)) when _T_2336 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2337 = dshr(inflight, io.in.a.bits.source) node _T_2338 = bits(_T_2337, 0, 0) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) node _T_2340 = asUInt(reset) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) when _T_2341 : node _T_2342 = eq(_T_2339, UInt<1>(0h0)) when _T_2342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2339, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<47> connect d_clr, UInt<47>(0h0) wire d_clr_wo_ready : UInt<47> connect d_clr_wo_ready, UInt<47>(0h0) wire d_opcodes_clr : UInt<188> connect d_opcodes_clr, UInt<188>(0h0) wire d_sizes_clr : UInt<188> connect d_sizes_clr, UInt<188>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2343 = and(io.in.d.valid, d_first_1) node _T_2344 = and(_T_2343, UInt<1>(0h1)) node _T_2345 = eq(d_release_ack, UInt<1>(0h0)) node _T_2346 = and(_T_2344, _T_2345) when _T_2346 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2347 = and(io.in.d.ready, io.in.d.valid) node _T_2348 = and(_T_2347, d_first_1) node _T_2349 = and(_T_2348, UInt<1>(0h1)) node _T_2350 = eq(d_release_ack, UInt<1>(0h0)) node _T_2351 = and(_T_2349, _T_2350) when _T_2351 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2352 = and(io.in.d.valid, d_first_1) node _T_2353 = and(_T_2352, UInt<1>(0h1)) node _T_2354 = eq(d_release_ack, UInt<1>(0h0)) node _T_2355 = and(_T_2353, _T_2354) when _T_2355 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2356 = dshr(inflight, io.in.d.bits.source) node _T_2357 = bits(_T_2356, 0, 0) node _T_2358 = or(_T_2357, same_cycle_resp) node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(_T_2358, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2358, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2362 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2363 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2364 = or(_T_2362, _T_2363) node _T_2365 = asUInt(reset) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) when _T_2366 : node _T_2367 = eq(_T_2364, UInt<1>(0h0)) when _T_2367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2364, UInt<1>(0h1), "") : assert_194 node _T_2368 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2369 = asUInt(reset) node _T_2370 = eq(_T_2369, UInt<1>(0h0)) when _T_2370 : node _T_2371 = eq(_T_2368, UInt<1>(0h0)) when _T_2371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2368, UInt<1>(0h1), "") : assert_195 else : node _T_2372 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2373 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2374 = or(_T_2372, _T_2373) node _T_2375 = asUInt(reset) node _T_2376 = eq(_T_2375, UInt<1>(0h0)) when _T_2376 : node _T_2377 = eq(_T_2374, UInt<1>(0h0)) when _T_2377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2374, UInt<1>(0h1), "") : assert_196 node _T_2378 = eq(io.in.d.bits.size, a_size_lookup) node _T_2379 = asUInt(reset) node _T_2380 = eq(_T_2379, UInt<1>(0h0)) when _T_2380 : node _T_2381 = eq(_T_2378, UInt<1>(0h0)) when _T_2381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2378, UInt<1>(0h1), "") : assert_197 node _T_2382 = and(io.in.d.valid, d_first_1) node _T_2383 = and(_T_2382, a_first_1) node _T_2384 = and(_T_2383, io.in.a.valid) node _T_2385 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2386 = and(_T_2384, _T_2385) node _T_2387 = eq(d_release_ack, UInt<1>(0h0)) node _T_2388 = and(_T_2386, _T_2387) when _T_2388 : node _T_2389 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2390 = or(_T_2389, io.in.a.ready) node _T_2391 = asUInt(reset) node _T_2392 = eq(_T_2391, UInt<1>(0h0)) when _T_2392 : node _T_2393 = eq(_T_2390, UInt<1>(0h0)) when _T_2393 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2390, UInt<1>(0h1), "") : assert_198 node _T_2394 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2395 = orr(a_set_wo_ready) node _T_2396 = eq(_T_2395, UInt<1>(0h0)) node _T_2397 = or(_T_2394, _T_2396) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_100 node _T_2401 = orr(inflight) node _T_2402 = eq(_T_2401, UInt<1>(0h0)) node _T_2403 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2404 = or(_T_2402, _T_2403) node _T_2405 = lt(watchdog, plusarg_reader.out) node _T_2406 = or(_T_2404, _T_2405) node _T_2407 = asUInt(reset) node _T_2408 = eq(_T_2407, UInt<1>(0h0)) when _T_2408 : node _T_2409 = eq(_T_2406, UInt<1>(0h0)) when _T_2409 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2406, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2410 = and(io.in.a.ready, io.in.a.valid) node _T_2411 = and(io.in.d.ready, io.in.d.valid) node _T_2412 = or(_T_2410, _T_2411) when _T_2412 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<47>, clock, reset, UInt<47>(0h0) regreset inflight_opcodes_1 : UInt<188>, clock, reset, UInt<188>(0h0) regreset inflight_sizes_1 : UInt<188>, clock, reset, UInt<188>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<47> connect c_set, UInt<47>(0h0) wire c_set_wo_ready : UInt<47> connect c_set_wo_ready, UInt<47>(0h0) wire c_opcodes_set : UInt<188> connect c_opcodes_set, UInt<188>(0h0) wire c_sizes_set : UInt<188> connect c_sizes_set, UInt<188>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_2413 = and(io.in.c.valid, c_first_1) node _T_2414 = bits(io.in.c.bits.opcode, 2, 2) node _T_2415 = bits(io.in.c.bits.opcode, 1, 1) node _T_2416 = and(_T_2414, _T_2415) node _T_2417 = and(_T_2413, _T_2416) when _T_2417 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2418 = and(io.in.c.ready, io.in.c.valid) node _T_2419 = and(_T_2418, c_first_1) node _T_2420 = bits(io.in.c.bits.opcode, 2, 2) node _T_2421 = bits(io.in.c.bits.opcode, 1, 1) node _T_2422 = and(_T_2420, _T_2421) node _T_2423 = and(_T_2419, _T_2422) when _T_2423 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2424 = dshr(inflight_1, io.in.c.bits.source) node _T_2425 = bits(_T_2424, 0, 0) node _T_2426 = eq(_T_2425, UInt<1>(0h0)) node _T_2427 = asUInt(reset) node _T_2428 = eq(_T_2427, UInt<1>(0h0)) when _T_2428 : node _T_2429 = eq(_T_2426, UInt<1>(0h0)) when _T_2429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2426, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<47> connect d_clr_1, UInt<47>(0h0) wire d_clr_wo_ready_1 : UInt<47> connect d_clr_wo_ready_1, UInt<47>(0h0) wire d_opcodes_clr_1 : UInt<188> connect d_opcodes_clr_1, UInt<188>(0h0) wire d_sizes_clr_1 : UInt<188> connect d_sizes_clr_1, UInt<188>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2430 = and(io.in.d.valid, d_first_2) node _T_2431 = and(_T_2430, UInt<1>(0h1)) node _T_2432 = and(_T_2431, d_release_ack_1) when _T_2432 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2433 = and(io.in.d.ready, io.in.d.valid) node _T_2434 = and(_T_2433, d_first_2) node _T_2435 = and(_T_2434, UInt<1>(0h1)) node _T_2436 = and(_T_2435, d_release_ack_1) when _T_2436 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2437 = and(io.in.d.valid, d_first_2) node _T_2438 = and(_T_2437, UInt<1>(0h1)) node _T_2439 = and(_T_2438, d_release_ack_1) when _T_2439 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2440 = dshr(inflight_1, io.in.d.bits.source) node _T_2441 = bits(_T_2440, 0, 0) node _T_2442 = or(_T_2441, same_cycle_resp_1) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2446 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2447 = asUInt(reset) node _T_2448 = eq(_T_2447, UInt<1>(0h0)) when _T_2448 : node _T_2449 = eq(_T_2446, UInt<1>(0h0)) when _T_2449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2446, UInt<1>(0h1), "") : assert_203 else : node _T_2450 = eq(io.in.d.bits.size, c_size_lookup) node _T_2451 = asUInt(reset) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) when _T_2452 : node _T_2453 = eq(_T_2450, UInt<1>(0h0)) when _T_2453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2450, UInt<1>(0h1), "") : assert_204 node _T_2454 = and(io.in.d.valid, d_first_2) node _T_2455 = and(_T_2454, c_first_1) node _T_2456 = and(_T_2455, io.in.c.valid) node _T_2457 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2458 = and(_T_2456, _T_2457) node _T_2459 = and(_T_2458, d_release_ack_1) node _T_2460 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2461 = and(_T_2459, _T_2460) when _T_2461 : node _T_2462 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2463 = or(_T_2462, io.in.c.ready) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_205 node _T_2467 = orr(c_set_wo_ready) when _T_2467 : node _T_2468 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2469 = asUInt(reset) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) when _T_2470 : node _T_2471 = eq(_T_2468, UInt<1>(0h0)) when _T_2471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2468, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_101 node _T_2472 = orr(inflight_1) node _T_2473 = eq(_T_2472, UInt<1>(0h0)) node _T_2474 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2475 = or(_T_2473, _T_2474) node _T_2476 = lt(watchdog_1, plusarg_reader_1.out) node _T_2477 = or(_T_2475, _T_2476) node _T_2478 = asUInt(reset) node _T_2479 = eq(_T_2478, UInt<1>(0h0)) when _T_2479 : node _T_2480 = eq(_T_2477, UInt<1>(0h0)) when _T_2480 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2477, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2481 = and(io.in.c.ready, io.in.c.valid) node _T_2482 = and(io.in.d.ready, io.in.d.valid) node _T_2483 = or(_T_2481, _T_2482) when _T_2483 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<7>, clock, reset, UInt<7>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<7> connect d_set, UInt<7>(0h0) node _T_2484 = and(io.in.d.ready, io.in.d.valid) node _T_2485 = and(_T_2484, d_first_3) node _T_2486 = bits(io.in.d.bits.opcode, 2, 2) node _T_2487 = bits(io.in.d.bits.opcode, 1, 1) node _T_2488 = eq(_T_2487, UInt<1>(0h0)) node _T_2489 = and(_T_2486, _T_2488) node _T_2490 = and(_T_2485, _T_2489) when _T_2490 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2491 = dshr(inflight_2, io.in.d.bits.sink) node _T_2492 = bits(_T_2491, 0, 0) node _T_2493 = eq(_T_2492, UInt<1>(0h0)) node _T_2494 = asUInt(reset) node _T_2495 = eq(_T_2494, UInt<1>(0h0)) when _T_2495 : node _T_2496 = eq(_T_2493, UInt<1>(0h0)) when _T_2496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2493, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<7> connect e_clr, UInt<7>(0h0) node _T_2497 = and(io.in.e.ready, io.in.e.valid) node _T_2498 = and(_T_2497, UInt<1>(0h1)) node _T_2499 = and(_T_2498, UInt<1>(0h1)) when _T_2499 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2500 = or(d_set, inflight_2) node _T_2501 = dshr(_T_2500, io.in.e.bits.sink) node _T_2502 = bits(_T_2501, 0, 0) node _T_2503 = asUInt(reset) node _T_2504 = eq(_T_2503, UInt<1>(0h0)) when _T_2504 : node _T_2505 = eq(_T_2502, UInt<1>(0h0)) when _T_2505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:126:26)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2502, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8

module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [5:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_91 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_111 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T_34 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_2 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _legal_source_uncommonBits_T_3 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_43 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_45 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_51 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_57 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_63 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_46 = _source_ok_T_45 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire _source_ok_T_69 = io_in_d_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_86 = _source_ok_T_85 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_87 = _source_ok_T_86 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_87 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire _legal_source_T = io_in_b_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _legal_source_T_1 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_7 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_13 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _legal_source_T_19 = io_in_b_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_25 = io_in_b_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _legal_source_T_26 = io_in_b_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _legal_source_T_27 = io_in_b_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _legal_source_T_28 = io_in_b_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _legal_source_T_29 = io_in_b_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _legal_source_T_30 = io_in_b_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _legal_source_T_31 = io_in_b_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _legal_source_T_32 = io_in_b_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_2 = _legal_source_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_1 = _legal_source_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_8 = _legal_source_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_10 = _legal_source_T_8; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_12 = _legal_source_T_10; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_2 = _legal_source_T_12; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_2 = _legal_source_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_14 = _legal_source_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_16 = _legal_source_T_14; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_18 = _legal_source_T_16; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_3 = _legal_source_T_18; // @[Parameters.scala:1138:31] wire [1:0] legal_source_uncommonBits_3 = _legal_source_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_20 = _legal_source_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_22 = _legal_source_T_20; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_24 = _legal_source_T_22; // @[Parameters.scala:54:67, :56:48] wire _legal_source_WIRE_4 = _legal_source_T_24; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_5 = _legal_source_T_25; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = _legal_source_T_26; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = _legal_source_T_27; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_8 = _legal_source_T_28; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_9 = _legal_source_T_29; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_10 = _legal_source_T_30; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_11 = _legal_source_T_31; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_12 = _legal_source_T_32; // @[Parameters.scala:1138:31] wire [4:0] _legal_source_T_33 = {_legal_source_WIRE_0, 4'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_46 = _legal_source_T_33; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_35 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_36 = {_legal_source_WIRE_3, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_37 = _legal_source_WIRE_4 ? 4'hC : 4'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_38 = _legal_source_WIRE_5 ? 6'h24 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_39 = _legal_source_WIRE_6 ? 6'h26 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_40 = _legal_source_WIRE_7 ? 6'h2E : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_41 = _legal_source_WIRE_8 ? 6'h2C : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_42 = _legal_source_WIRE_9 ? 6'h2A : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_43 = _legal_source_WIRE_10 ? 6'h28 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = _legal_source_WIRE_11 ? 6'h22 : 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = {_legal_source_WIRE_12, 5'h0}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_47 = {_legal_source_T_46[4:3], _legal_source_T_46[2:0] | _legal_source_T_35}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_48 = {_legal_source_T_47[4], _legal_source_T_47[3:0] | _legal_source_T_36}; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_49 = {_legal_source_T_48[4], _legal_source_T_48[3:0] | _legal_source_T_37}; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_50 = {1'h0, _legal_source_T_49} | _legal_source_T_38; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_51 = _legal_source_T_50 | _legal_source_T_39; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_52 = _legal_source_T_51 | _legal_source_T_40; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_53 = _legal_source_T_52 | _legal_source_T_41; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_54 = _legal_source_T_53 | _legal_source_T_42; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_55 = _legal_source_T_54 | _legal_source_T_43; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_56 = _legal_source_T_55 | _legal_source_T_44; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_57 = _legal_source_T_56 | _legal_source_T_45; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1_0 = _legal_source_T_57; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_88 = io_in_c_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_89 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_95 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_101 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_107 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_90 = _source_ok_T_89 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_92 = _source_ok_T_90; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_96 = _source_ok_T_95 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_102 = _source_ok_T_101 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_108 = _source_ok_T_107 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_112 = _source_ok_T_110; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_c_bits_source_0 == 6'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_5 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_c_bits_source_0 == 6'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_6 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_c_bits_source_0 == 6'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_7 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_c_bits_source_0 == 6'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_8 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_c_bits_source_0 == 6'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_9 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_c_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_10 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_c_bits_source_0 == 6'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_11 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_c_bits_source_0 == 6'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_12 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_128 = _source_ok_T_127 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_2_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_2_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_2_11; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_131 | _source_ok_WIRE_2_12; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_67 = _uncommonBits_T_67[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_68 = _uncommonBits_T_68[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_69 = _uncommonBits_T_69[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_2410 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2410; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2410; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2484; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2484; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2481 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2481; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2481; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [46:0] inflight; // @[Monitor.scala:614:27] reg [187:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [187:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [46:0] a_set; // @[Monitor.scala:626:34] wire [46:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [187:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [187:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [187:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [187:0] _a_opcode_lookup_T_6 = {184'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [187:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[187:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [187:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [187:0] _a_size_lookup_T_6 = {184'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [187:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[187:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2336 = _T_2410 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2336 ? _a_set_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2336 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2336 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2336 ? _a_opcodes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2336 ? _a_sizes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [46:0] d_clr; // @[Monitor.scala:664:34] wire [46:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [187:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [187:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2382 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2382 & ~d_release_ack ? _d_clr_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2351 = _T_2484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2351 ? _d_clr_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2351 ? _d_opcodes_clr_T_5[187:0] : 188'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2351 ? _d_sizes_clr_T_5[187:0] : 188'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [46:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [46:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [46:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [187:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [187:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [187:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [187:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [187:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [187:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [46:0] inflight_1; // @[Monitor.scala:726:35] reg [187:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [187:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [46:0] c_set; // @[Monitor.scala:738:34] wire [46:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [187:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [187:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [187:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [187:0] _c_opcode_lookup_T_6 = {184'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [187:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[187:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [187:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [187:0] _c_size_lookup_T_6 = {184'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [187:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[187:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2423 = _T_2481 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2423 ? _c_set_T[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2423 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2423 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2423 ? _c_opcodes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2423 ? _c_sizes_set_T_1[187:0] : 188'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [46:0] d_clr_1; // @[Monitor.scala:774:34] wire [46:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [187:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [187:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2454 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2454 & d_release_ack_1 ? _d_clr_wo_ready_T_1[46:0] : 47'h0; // @[OneHot.scala:58:35] wire _T_2436 = _T_2484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2436 ? _d_clr_T_1[46:0] : 47'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2436 ? _d_opcodes_clr_T_11[187:0] : 188'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2436 ? _d_sizes_clr_T_11[187:0] : 188'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [46:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [46:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [46:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [187:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [187:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [187:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [187:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [187:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [187:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_2490 = _T_2484 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2490 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]

Generate the Verilog code corresponding to this FIRRTL code module SystemBus : output auto : { flip coupler_from_nvdla_dbb_no_buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coupler_from_rockettile_tl_master_clock_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, coupler_to_bus_named_coh_widget_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coupler_from_bus_named_fbus_bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_cbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip sbus_clock_groups_in : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}, sbus_clock_groups_out : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst sbus_clock_groups of ClockGroupAggregator_sbus inst clockGroup of ClockGroup inst fixedClockNode of FixedClockBroadcast_5 inst broadcast of BundleBridgeNexus_NoOutput inst system_bus_xbar of TLXbar_sbus_i3_o2_a32d64s9k3z4c connect system_bus_xbar.clock, childClock connect system_bus_xbar.reset, childReset inst fixer of TLFIFOFixer connect fixer.clock, childClock connect fixer.reset, childReset inst coupler_to_bus_named_cbus of TLInterconnectCoupler_sbus_to_bus_named_cbus connect coupler_to_bus_named_cbus.clock, childClock connect coupler_to_bus_named_cbus.reset, childReset inst coupler_from_bus_named_fbus of TLInterconnectCoupler_sbus_from_bus_named_fbus connect coupler_from_bus_named_fbus.clock, childClock connect coupler_from_bus_named_fbus.reset, childReset inst coupler_to_bus_named_coh of TLInterconnectCoupler_sbus_to_bus_named_coh connect coupler_to_bus_named_coh.clock, childClock connect coupler_to_bus_named_coh.reset, childReset inst coupler_from_rockettile of TLInterconnectCoupler_sbus_from_rockettile connect coupler_from_rockettile.clock, childClock connect coupler_from_rockettile.reset, childReset inst coupler_from_nvdla_dbb of TLInterconnectCoupler_sbus_from_nvdla_dbb connect coupler_from_nvdla_dbb.clock, childClock connect coupler_from_nvdla_dbb.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, sbus_clock_groups.auto.out_0 connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect coupler_to_bus_named_cbus.auto.widget_anon_in, system_bus_xbar.auto.anon_out_0 connect coupler_to_bus_named_coh.auto.widget_anon_in, system_bus_xbar.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_0, fixer.auto.anon_out_0 connect system_bus_xbar.auto.anon_in_1, fixer.auto.anon_out_1 connect system_bus_xbar.auto.anon_in_2, fixer.auto.anon_out_2 connect fixer.auto.anon_in_0, coupler_from_bus_named_fbus.auto.widget_anon_out connect fixer.auto.anon_in_1, coupler_from_rockettile.auto.tl_out connect fixer.auto.anon_in_2, coupler_from_nvdla_dbb.auto.tl_out connect auto.sbus_clock_groups_out, sbus_clock_groups.auto.out_1 connect sbus_clock_groups.auto.in, auto.sbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3 connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4 connect coupler_to_bus_named_cbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_cbus_bus_xing_out.d connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.bits, coupler_to_bus_named_cbus.auto.bus_xing_out.a.bits connect auto.coupler_to_bus_named_cbus_bus_xing_out.a.valid, coupler_to_bus_named_cbus.auto.bus_xing_out.a.valid connect coupler_to_bus_named_cbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_cbus_bus_xing_out.a.ready connect coupler_from_bus_named_fbus.auto.bus_xing_in, auto.coupler_from_bus_named_fbus_bus_xing_in connect auto.coupler_to_bus_named_coh_widget_anon_out.e.bits, coupler_to_bus_named_coh.auto.widget_anon_out.e.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.e.valid, coupler_to_bus_named_coh.auto.widget_anon_out.e.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.e.ready, auto.coupler_to_bus_named_coh_widget_anon_out.e.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.d, auto.coupler_to_bus_named_coh_widget_anon_out.d connect auto.coupler_to_bus_named_coh_widget_anon_out.c.bits, coupler_to_bus_named_coh.auto.widget_anon_out.c.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.c.valid, coupler_to_bus_named_coh.auto.widget_anon_out.c.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.c.ready, auto.coupler_to_bus_named_coh_widget_anon_out.c.ready connect coupler_to_bus_named_coh.auto.widget_anon_out.b, auto.coupler_to_bus_named_coh_widget_anon_out.b connect auto.coupler_to_bus_named_coh_widget_anon_out.a.bits, coupler_to_bus_named_coh.auto.widget_anon_out.a.bits connect auto.coupler_to_bus_named_coh_widget_anon_out.a.valid, coupler_to_bus_named_coh.auto.widget_anon_out.a.valid connect coupler_to_bus_named_coh.auto.widget_anon_out.a.ready, auto.coupler_to_bus_named_coh_widget_anon_out.a.ready connect coupler_from_rockettile.auto.tl_master_clock_xing_in, auto.coupler_from_rockettile_tl_master_clock_xing_in connect coupler_from_nvdla_dbb.auto.no_buffer_in, auto.coupler_from_nvdla_dbb_no_buffer_in connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset

module SystemBus( // @[ClockDomain.scala:14:9] output auto_coupler_from_nvdla_dbb_no_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_nvdla_dbb_no_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_coh_widget_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_1_reset, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_sbus_clock_groups_in_member_sbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] output auto_sbus_clock_groups_out_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire _fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:152:27] wire [1:0] _fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:152:27] wire [1:0] _fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:152:27] wire [2:0] _fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:152:27] wire [3:0] _fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:152:27] wire [4:0] _fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:152:27] wire [31:0] _fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_secure; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch; // @[FIFOFixer.scala:152:27] wire [7:0] _fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:152:27] wire [63:0] _fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:152:27] wire _fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:152:27] wire _system_bus_xbar_auto_anon_in_2_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_2_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_2_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_2_d_bits_size; // @[SystemBus.scala:47:43] wire [7:0] _system_bus_xbar_auto_anon_in_2_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_2_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_2_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_2_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_b_valid; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_b_bits_param; // @[SystemBus.scala:47:43] wire [31:0] _system_bus_xbar_auto_anon_in_1_b_bits_address; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_c_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_1_d_bits_size; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_1_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_1_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_1_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_1_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_a_ready; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_valid; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_opcode; // @[SystemBus.scala:47:43] wire [1:0] _system_bus_xbar_auto_anon_in_0_d_bits_param; // @[SystemBus.scala:47:43] wire [3:0] _system_bus_xbar_auto_anon_in_0_d_bits_size; // @[SystemBus.scala:47:43] wire [4:0] _system_bus_xbar_auto_anon_in_0_d_bits_source; // @[SystemBus.scala:47:43] wire [2:0] _system_bus_xbar_auto_anon_in_0_d_bits_sink; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_bits_denied; // @[SystemBus.scala:47:43] wire [63:0] _system_bus_xbar_auto_anon_in_0_d_bits_data; // @[SystemBus.scala:47:43] wire _system_bus_xbar_auto_anon_in_0_d_bits_corrupt; // @[SystemBus.scala:47:43] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_5 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_sbus_clock_groups_in_member_sbus_0_clock), .auto_anon_in_reset (auto_sbus_clock_groups_in_member_sbus_0_reset), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_sbus_i3_o2_a32d64s9k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_2_a_ready (_system_bus_xbar_auto_anon_in_2_a_ready), .auto_anon_in_2_a_valid (_fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_opcode (_fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_param (_fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_size (_fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_source (_fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_address (_fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_2_a_bits_user_amba_prot_secure), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_mask (_fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_data (_fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_a_bits_corrupt (_fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_d_ready (_fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_2_d_valid (_system_bus_xbar_auto_anon_in_2_d_valid), .auto_anon_in_2_d_bits_opcode (_system_bus_xbar_auto_anon_in_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (_system_bus_xbar_auto_anon_in_2_d_bits_param), .auto_anon_in_2_d_bits_size (_system_bus_xbar_auto_anon_in_2_d_bits_size), .auto_anon_in_2_d_bits_source (_system_bus_xbar_auto_anon_in_2_d_bits_source), .auto_anon_in_2_d_bits_sink (_system_bus_xbar_auto_anon_in_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (_system_bus_xbar_auto_anon_in_2_d_bits_denied), .auto_anon_in_2_d_bits_data (_system_bus_xbar_auto_anon_in_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (_system_bus_xbar_auto_anon_in_2_d_bits_corrupt), .auto_anon_in_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready), .auto_anon_in_1_a_valid (_fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_b_ready (_fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid), .auto_anon_in_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param), .auto_anon_in_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address), .auto_anon_in_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready), .auto_anon_in_1_c_valid (_fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_d_ready (_fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt), .auto_anon_in_1_e_valid (_fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready), .auto_anon_in_0_a_valid (_fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_0_a_bits_user_amba_prot_secure), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_d_ready (_fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:152:27] .auto_anon_in_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size), .auto_anon_in_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source), .auto_anon_in_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt), .auto_anon_out_1_a_ready (auto_coupler_to_bus_named_coh_widget_anon_out_a_ready), .auto_anon_out_1_a_valid (auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_anon_out_1_a_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_anon_out_1_a_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_anon_out_1_a_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_anon_out_1_a_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_anon_out_1_a_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_anon_out_1_a_bits_mask (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_anon_out_1_a_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_anon_out_1_a_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_anon_out_1_b_ready (auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_anon_out_1_b_valid (auto_coupler_to_bus_named_coh_widget_anon_out_b_valid), .auto_anon_out_1_b_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param), .auto_anon_out_1_b_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address), .auto_anon_out_1_c_ready (auto_coupler_to_bus_named_coh_widget_anon_out_c_ready), .auto_anon_out_1_c_valid (auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_anon_out_1_c_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_anon_out_1_c_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_anon_out_1_c_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_anon_out_1_c_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_anon_out_1_c_bits_address (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_anon_out_1_c_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_anon_out_1_c_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_anon_out_1_d_ready (auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_anon_out_1_d_valid (auto_coupler_to_bus_named_coh_widget_anon_out_d_valid), .auto_anon_out_1_d_bits_opcode (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode), .auto_anon_out_1_d_bits_param (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param), .auto_anon_out_1_d_bits_size (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size), .auto_anon_out_1_d_bits_source (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source), .auto_anon_out_1_d_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink), .auto_anon_out_1_d_bits_denied (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied), .auto_anon_out_1_d_bits_data (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data), .auto_anon_out_1_d_bits_corrupt (auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt), .auto_anon_out_1_e_valid (auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_anon_out_1_e_bits_sink (auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_anon_out_0_a_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready), .auto_anon_out_0_a_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_anon_out_0_a_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_anon_out_0_a_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_anon_out_0_a_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_anon_out_0_a_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_anon_out_0_a_bits_address (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_anon_out_0_a_bits_user_amba_prot_bufferable (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_bufferable), .auto_anon_out_0_a_bits_user_amba_prot_modifiable (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_modifiable), .auto_anon_out_0_a_bits_user_amba_prot_readalloc (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_readalloc), .auto_anon_out_0_a_bits_user_amba_prot_writealloc (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_writealloc), .auto_anon_out_0_a_bits_user_amba_prot_privileged (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_privileged), .auto_anon_out_0_a_bits_user_amba_prot_secure (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_secure), .auto_anon_out_0_a_bits_user_amba_prot_fetch (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_user_amba_prot_fetch), .auto_anon_out_0_a_bits_mask (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_anon_out_0_a_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_anon_out_0_a_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_anon_out_0_d_ready (auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_anon_out_0_d_valid (auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid), .auto_anon_out_0_d_bits_opcode (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode), .auto_anon_out_0_d_bits_param (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param), .auto_anon_out_0_d_bits_size (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size), .auto_anon_out_0_d_bits_source (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source), .auto_anon_out_0_d_bits_sink (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink), .auto_anon_out_0_d_bits_denied (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied), .auto_anon_out_0_d_bits_data (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data), .auto_anon_out_0_d_bits_corrupt (auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt) ); // @[SystemBus.scala:47:43] TLFIFOFixer fixer ( // @[FIFOFixer.scala:152:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_2_a_ready (auto_coupler_from_nvdla_dbb_no_buffer_in_a_ready), .auto_anon_in_2_a_valid (auto_coupler_from_nvdla_dbb_no_buffer_in_a_valid), .auto_anon_in_2_a_bits_opcode (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_opcode), .auto_anon_in_2_a_bits_param (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_param), .auto_anon_in_2_a_bits_size (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_size), .auto_anon_in_2_a_bits_source (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_source), .auto_anon_in_2_a_bits_address (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_address), .auto_anon_in_2_a_bits_user_amba_prot_bufferable (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_bufferable), .auto_anon_in_2_a_bits_user_amba_prot_modifiable (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_modifiable), .auto_anon_in_2_a_bits_user_amba_prot_readalloc (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_readalloc), .auto_anon_in_2_a_bits_user_amba_prot_writealloc (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_writealloc), .auto_anon_in_2_a_bits_user_amba_prot_privileged (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_privileged), .auto_anon_in_2_a_bits_user_amba_prot_secure (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_secure), .auto_anon_in_2_a_bits_user_amba_prot_fetch (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_user_amba_prot_fetch), .auto_anon_in_2_a_bits_mask (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_mask), .auto_anon_in_2_a_bits_data (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_data), .auto_anon_in_2_a_bits_corrupt (auto_coupler_from_nvdla_dbb_no_buffer_in_a_bits_corrupt), .auto_anon_in_2_d_ready (auto_coupler_from_nvdla_dbb_no_buffer_in_d_ready), .auto_anon_in_2_d_valid (auto_coupler_from_nvdla_dbb_no_buffer_in_d_valid), .auto_anon_in_2_d_bits_opcode (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_opcode), .auto_anon_in_2_d_bits_param (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_param), .auto_anon_in_2_d_bits_size (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_size), .auto_anon_in_2_d_bits_source (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_source), .auto_anon_in_2_d_bits_sink (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_sink), .auto_anon_in_2_d_bits_denied (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_denied), .auto_anon_in_2_d_bits_data (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_data), .auto_anon_in_2_d_bits_corrupt (auto_coupler_from_nvdla_dbb_no_buffer_in_d_bits_corrupt), .auto_anon_in_1_a_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready), .auto_anon_in_1_a_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_valid), .auto_anon_in_1_a_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_opcode), .auto_anon_in_1_a_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_param), .auto_anon_in_1_a_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_size), .auto_anon_in_1_a_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_source), .auto_anon_in_1_a_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_address), .auto_anon_in_1_a_bits_mask (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_mask), .auto_anon_in_1_a_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_data), .auto_anon_in_1_a_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_a_bits_corrupt), .auto_anon_in_1_b_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_ready), .auto_anon_in_1_b_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid), .auto_anon_in_1_b_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param), .auto_anon_in_1_b_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address), .auto_anon_in_1_c_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready), .auto_anon_in_1_c_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_valid), .auto_anon_in_1_c_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_opcode), .auto_anon_in_1_c_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_param), .auto_anon_in_1_c_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_size), .auto_anon_in_1_c_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_source), .auto_anon_in_1_c_bits_address (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_address), .auto_anon_in_1_c_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_data), .auto_anon_in_1_c_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_c_bits_corrupt), .auto_anon_in_1_d_ready (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_ready), .auto_anon_in_1_d_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid), .auto_anon_in_1_d_bits_opcode (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode), .auto_anon_in_1_d_bits_param (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param), .auto_anon_in_1_d_bits_size (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size), .auto_anon_in_1_d_bits_source (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source), .auto_anon_in_1_d_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink), .auto_anon_in_1_d_bits_denied (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied), .auto_anon_in_1_d_bits_data (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data), .auto_anon_in_1_d_bits_corrupt (auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt), .auto_anon_in_1_e_valid (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_valid), .auto_anon_in_1_e_bits_sink (auto_coupler_from_rockettile_tl_master_clock_xing_in_e_bits_sink), .auto_anon_in_0_a_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_anon_in_0_a_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid), .auto_anon_in_0_a_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode), .auto_anon_in_0_a_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param), .auto_anon_in_0_a_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size), .auto_anon_in_0_a_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source), .auto_anon_in_0_a_bits_address (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address), .auto_anon_in_0_a_bits_user_amba_prot_bufferable (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_bufferable), .auto_anon_in_0_a_bits_user_amba_prot_modifiable (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_modifiable), .auto_anon_in_0_a_bits_user_amba_prot_readalloc (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_readalloc), .auto_anon_in_0_a_bits_user_amba_prot_writealloc (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_writealloc), .auto_anon_in_0_a_bits_user_amba_prot_privileged (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_privileged), .auto_anon_in_0_a_bits_user_amba_prot_secure (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_secure), .auto_anon_in_0_a_bits_user_amba_prot_fetch (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_user_amba_prot_fetch), .auto_anon_in_0_a_bits_mask (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask), .auto_anon_in_0_a_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data), .auto_anon_in_0_a_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt), .auto_anon_in_0_d_ready (auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready), .auto_anon_in_0_d_valid (auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_anon_in_0_d_bits_opcode (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_anon_in_0_d_bits_param (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_anon_in_0_d_bits_size (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_anon_in_0_d_bits_source (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_anon_in_0_d_bits_sink (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_anon_in_0_d_bits_denied (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_anon_in_0_d_bits_data (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_anon_in_0_d_bits_corrupt (auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_anon_out_2_a_ready (_system_bus_xbar_auto_anon_in_2_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_2_a_valid (_fixer_auto_anon_out_2_a_valid), .auto_anon_out_2_a_bits_opcode (_fixer_auto_anon_out_2_a_bits_opcode), .auto_anon_out_2_a_bits_param (_fixer_auto_anon_out_2_a_bits_param), .auto_anon_out_2_a_bits_size (_fixer_auto_anon_out_2_a_bits_size), .auto_anon_out_2_a_bits_source (_fixer_auto_anon_out_2_a_bits_source), .auto_anon_out_2_a_bits_address (_fixer_auto_anon_out_2_a_bits_address), .auto_anon_out_2_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_bufferable), .auto_anon_out_2_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_2_a_bits_user_amba_prot_modifiable), .auto_anon_out_2_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_readalloc), .auto_anon_out_2_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_2_a_bits_user_amba_prot_writealloc), .auto_anon_out_2_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_2_a_bits_user_amba_prot_privileged), .auto_anon_out_2_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_2_a_bits_user_amba_prot_secure), .auto_anon_out_2_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_2_a_bits_user_amba_prot_fetch), .auto_anon_out_2_a_bits_mask (_fixer_auto_anon_out_2_a_bits_mask), .auto_anon_out_2_a_bits_data (_fixer_auto_anon_out_2_a_bits_data), .auto_anon_out_2_a_bits_corrupt (_fixer_auto_anon_out_2_a_bits_corrupt), .auto_anon_out_2_d_ready (_fixer_auto_anon_out_2_d_ready), .auto_anon_out_2_d_valid (_system_bus_xbar_auto_anon_in_2_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_opcode (_system_bus_xbar_auto_anon_in_2_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_param (_system_bus_xbar_auto_anon_in_2_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_size (_system_bus_xbar_auto_anon_in_2_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_source (_system_bus_xbar_auto_anon_in_2_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_sink (_system_bus_xbar_auto_anon_in_2_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_denied (_system_bus_xbar_auto_anon_in_2_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_data (_system_bus_xbar_auto_anon_in_2_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_2_d_bits_corrupt (_system_bus_xbar_auto_anon_in_2_d_bits_corrupt), // @[SystemBus.scala:47:43] .auto_anon_out_1_a_ready (_system_bus_xbar_auto_anon_in_1_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_1_a_valid (_fixer_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_fixer_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_fixer_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_fixer_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_fixer_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_fixer_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_fixer_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_fixer_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_fixer_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_b_ready (_fixer_auto_anon_out_1_b_ready), .auto_anon_out_1_b_valid (_system_bus_xbar_auto_anon_in_1_b_valid), // @[SystemBus.scala:47:43] .auto_anon_out_1_b_bits_param (_system_bus_xbar_auto_anon_in_1_b_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_1_b_bits_address (_system_bus_xbar_auto_anon_in_1_b_bits_address), // @[SystemBus.scala:47:43] .auto_anon_out_1_c_ready (_system_bus_xbar_auto_anon_in_1_c_ready), // @[SystemBus.scala:47:43] .auto_anon_out_1_c_valid (_fixer_auto_anon_out_1_c_valid), .auto_anon_out_1_c_bits_opcode (_fixer_auto_anon_out_1_c_bits_opcode), .auto_anon_out_1_c_bits_param (_fixer_auto_anon_out_1_c_bits_param), .auto_anon_out_1_c_bits_size (_fixer_auto_anon_out_1_c_bits_size), .auto_anon_out_1_c_bits_source (_fixer_auto_anon_out_1_c_bits_source), .auto_anon_out_1_c_bits_address (_fixer_auto_anon_out_1_c_bits_address), .auto_anon_out_1_c_bits_data (_fixer_auto_anon_out_1_c_bits_data), .auto_anon_out_1_c_bits_corrupt (_fixer_auto_anon_out_1_c_bits_corrupt), .auto_anon_out_1_d_ready (_fixer_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_system_bus_xbar_auto_anon_in_1_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_opcode (_system_bus_xbar_auto_anon_in_1_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_param (_system_bus_xbar_auto_anon_in_1_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_size (_system_bus_xbar_auto_anon_in_1_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_source (_system_bus_xbar_auto_anon_in_1_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_sink (_system_bus_xbar_auto_anon_in_1_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_denied (_system_bus_xbar_auto_anon_in_1_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_data (_system_bus_xbar_auto_anon_in_1_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_1_d_bits_corrupt (_system_bus_xbar_auto_anon_in_1_d_bits_corrupt), // @[SystemBus.scala:47:43] .auto_anon_out_1_e_valid (_fixer_auto_anon_out_1_e_valid), .auto_anon_out_1_e_bits_sink (_fixer_auto_anon_out_1_e_bits_sink), .auto_anon_out_0_a_ready (_system_bus_xbar_auto_anon_in_0_a_ready), // @[SystemBus.scala:47:43] .auto_anon_out_0_a_valid (_fixer_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_fixer_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_fixer_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_fixer_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_fixer_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_fixer_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_user_amba_prot_bufferable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_bufferable), .auto_anon_out_0_a_bits_user_amba_prot_modifiable (_fixer_auto_anon_out_0_a_bits_user_amba_prot_modifiable), .auto_anon_out_0_a_bits_user_amba_prot_readalloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_readalloc), .auto_anon_out_0_a_bits_user_amba_prot_writealloc (_fixer_auto_anon_out_0_a_bits_user_amba_prot_writealloc), .auto_anon_out_0_a_bits_user_amba_prot_privileged (_fixer_auto_anon_out_0_a_bits_user_amba_prot_privileged), .auto_anon_out_0_a_bits_user_amba_prot_secure (_fixer_auto_anon_out_0_a_bits_user_amba_prot_secure), .auto_anon_out_0_a_bits_user_amba_prot_fetch (_fixer_auto_anon_out_0_a_bits_user_amba_prot_fetch), .auto_anon_out_0_a_bits_mask (_fixer_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_fixer_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_fixer_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_fixer_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_system_bus_xbar_auto_anon_in_0_d_valid), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_opcode (_system_bus_xbar_auto_anon_in_0_d_bits_opcode), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_param (_system_bus_xbar_auto_anon_in_0_d_bits_param), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_size (_system_bus_xbar_auto_anon_in_0_d_bits_size), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_source (_system_bus_xbar_auto_anon_in_0_d_bits_source), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_sink (_system_bus_xbar_auto_anon_in_0_d_bits_sink), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_denied (_system_bus_xbar_auto_anon_in_0_d_bits_denied), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_data (_system_bus_xbar_auto_anon_in_0_d_bits_data), // @[SystemBus.scala:47:43] .auto_anon_out_0_d_bits_corrupt (_system_bus_xbar_auto_anon_in_0_d_bits_corrupt) // @[SystemBus.scala:47:43] ); // @[FIFOFixer.scala:152:27] assign auto_sbus_clock_groups_out_member_coh_0_clock = auto_sbus_clock_groups_in_member_sbus_1_clock; // @[ClockDomain.scala:14:9] assign auto_sbus_clock_groups_out_member_coh_0_reset = auto_sbus_clock_groups_in_member_sbus_1_reset; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_70 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = or(_T_12, _T_19) node _T_21 = or(_T_5, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = or(_T_32, _T_39) node _T_69 = or(_T_68, _T_46) node _T_70 = or(_T_69, _T_53) node _T_71 = or(_T_70, _T_60) node _T_72 = or(_T_71, _T_67) node _T_73 = or(_T_25, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2

module NoCMonitor_70( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]

Generate the Verilog code corresponding to this FIRRTL code module Tile_142 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_398 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_142( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_398 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_335 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_79 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_335( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_79 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_13 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_13( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_4 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x

module PMPChecker_s3_4( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5] wire [5:0] _res_hit_lsbMask_T = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_3 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_16 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_29 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_42 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_55 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_68 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_81 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_hit_T_94 = 6'hE; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14 = 6'hE; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_4 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_1 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_4 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_17 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_3 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_7 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_30 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_5 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_10 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_43 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_7 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_13 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_56 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_9 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_16 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_69 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_11 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_19 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_82 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_13 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_22 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_T_95 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_aligned_lsbMask_T_15 = 3'h6; // @[package.scala:243:76] wire [2:0] _res_hit_lsbMask_T_2 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_5 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_5 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_18 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_1 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_8 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_31 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_2 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_11 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_44 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_3 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_14 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_57 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_4 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_17 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_70 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_5 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_20 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_83 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_6 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_lsbMask_T_23 = 3'h1; // @[package.scala:243:46] wire [2:0] _res_hit_T_96 = 3'h1; // @[package.scala:243:46] wire [2:0] res_aligned_lsbMask_7 = 3'h1; // @[package.scala:243:46] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire [1:0] io_size = 2'h1; // @[PMP.scala:143:7, :146:14] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | 3'h1}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_7 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_9 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_8 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_2 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_1 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_8 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_11 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_19 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_22 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_23 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_18 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_25 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_2 = _res_aligned_pow2Aligned_T_1 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_13 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_15 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_16 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_18 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_25 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_21 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_31 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_36 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_37 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_35 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_42 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_5 = _res_aligned_pow2Aligned_T_4 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_29 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_30 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_35 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_42 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_31 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_43 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_50 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_51 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_52 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_59 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_8 = _res_aligned_pow2Aligned_T_7 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_37 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_43 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_44 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_52 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_59 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_41 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_55 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_64 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_65 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_69 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_76 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_11 = _res_aligned_pow2Aligned_T_10 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_49 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_57 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_58 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_69 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_76 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_51 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_67 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_78 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_79 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_86 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_93 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_14 = _res_aligned_pow2Aligned_T_13 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_71 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_72 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_86 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_61 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_79 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_92 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_93 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_103 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_110 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_17 = _res_aligned_pow2Aligned_T_16 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_73 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_85 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_86 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_103 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36] assign _res_aligned_straddlesLowerBound_T_110 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_msbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36] assign _res_hit_lsbMatch_T_71 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36] assign _res_hit_msbsLess_T_91 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36] assign _res_hit_msbsEqual_T_106 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36] assign _res_hit_lsbsLess_T_107 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_120 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36] assign _res_aligned_straddlesUpperBound_T_127 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5] wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48] wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}] wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}] wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46] wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_20 = _res_aligned_pow2Aligned_T_19 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7] wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7] wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | 3'h1}; // @[package.scala:243:46] wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}] wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67] wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | 3'h1; // @[package.scala:243:46] wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52] wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}] wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}] wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}] wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64] wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}] wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30] wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}] wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48] wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | 3'h1; // @[package.scala:243:46] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}] wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}] wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}] wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46] wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}] wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}] wire [2:0] _res_aligned_pow2Aligned_T_23 = _res_aligned_pow2Aligned_T_22 & 3'h1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}] wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :146:14, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[package.scala:243:46] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 13, 0) node _source_ok_T = shr(io.in.a.bits.source, 14) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<14>(0h200f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits = bits(_uncommonBits_T, 13, 0) node _T_4 = shr(io.in.a.bits.source, 14) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<14>(0h200f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 13, 0) node _T_24 = shr(io.in.a.bits.source, 14) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<14>(0h200f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 13, 0) node _T_86 = shr(io.in.a.bits.source, 14) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<14>(0h200f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 13, 0) node _T_152 = shr(io.in.a.bits.source, 14) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<14>(0h200f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 13, 0) node _T_199 = shr(io.in.a.bits.source, 14) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<14>(0h200f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 13, 0) node _T_240 = shr(io.in.a.bits.source, 14) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<14>(0h200f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 13, 0) node _T_283 = shr(io.in.a.bits.source, 14) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<14>(0h200f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 13, 0) node _T_321 = shr(io.in.a.bits.source, 14) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<14>(0h200f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 13, 0) node _T_359 = shr(io.in.a.bits.source, 14) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<14>(0h200f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 13, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 14) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<14>(0h200f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes : UInt<32832>, clock, reset, UInt<32832>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<8208> connect a_set, UInt<8208>(0h0) wire a_set_wo_ready : UInt<8208> connect a_set_wo_ready, UInt<8208>(0h0) wire a_opcodes_set : UInt<32832> connect a_opcodes_set, UInt<32832>(0h0) wire a_sizes_set : UInt<32832> connect a_sizes_set, UInt<32832>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<8208> connect d_clr, UInt<8208>(0h0) wire d_clr_wo_ready : UInt<8208> connect d_clr_wo_ready, UInt<8208>(0h0) wire d_opcodes_clr : UInt<32832> connect d_opcodes_clr, UInt<32832>(0h0) wire d_sizes_clr : UInt<32832> connect d_sizes_clr, UInt<32832>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_52 node _T_656 = orr(inflight) node _T_657 = eq(_T_656, UInt<1>(0h0)) node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_659 = or(_T_657, _T_658) node _T_660 = lt(watchdog, plusarg_reader.out) node _T_661 = or(_T_659, _T_660) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_661, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_665 = and(io.in.a.ready, io.in.a.valid) node _T_666 = and(io.in.d.ready, io.in.d.valid) node _T_667 = or(_T_665, _T_666) when _T_667 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<13>(0h0) connect _c_first_WIRE.bits.source, UInt<14>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<13>(0h0) connect _c_first_WIRE_2.bits.source, UInt<14>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<8208> connect c_set, UInt<8208>(0h0) wire c_set_wo_ready : UInt<8208> connect c_set_wo_ready, UInt<8208>(0h0) wire c_opcodes_set : UInt<32832> connect c_opcodes_set, UInt<32832>(0h0) wire c_sizes_set : UInt<32832> connect c_sizes_set, UInt<32832>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<13>(0h0) connect _WIRE_6.bits.source, UInt<14>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_668 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<13>(0h0) connect _WIRE_8.bits.source, UInt<14>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<13>(0h0) connect _WIRE_10.bits.source, UInt<14>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_674 = and(_T_673, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<13>(0h0) connect _WIRE_12.bits.source, UInt<14>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_677 = and(_T_675, _T_676) node _T_678 = and(_T_674, _T_677) when _T_678 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<13>(0h0) connect _c_set_WIRE.bits.source, UInt<14>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<13>(0h0) connect _WIRE_14.bits.source, UInt<14>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_679 = dshr(inflight_1, _WIRE_15.bits.source) node _T_680 = bits(_T_679, 0, 0) node _T_681 = eq(_T_680, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_681, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<8208> connect d_clr_1, UInt<8208>(0h0) wire d_clr_wo_ready_1 : UInt<8208> connect d_clr_wo_ready_1, UInt<8208>(0h0) wire d_opcodes_clr_1 : UInt<32832> connect d_opcodes_clr_1, UInt<32832>(0h0) wire d_sizes_clr_1 : UInt<32832> connect d_sizes_clr_1, UInt<32832>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_688 = and(io.in.d.ready, io.in.d.valid) node _T_689 = and(_T_688, d_first_2) node _T_690 = and(_T_689, UInt<1>(0h1)) node _T_691 = and(_T_690, d_release_ack_1) when _T_691 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_695 = dshr(inflight_1, io.in.d.bits.source) node _T_696 = bits(_T_695, 0, 0) node _T_697 = or(_T_696, same_cycle_resp_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_697, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<13>(0h0) connect _WIRE_16.bits.source, UInt<14>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_701, UInt<1>(0h1), "") : assert_108 else : node _T_705 = eq(io.in.d.bits.size, c_size_lookup) node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(_T_705, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_705, UInt<1>(0h1), "") : assert_109 node _T_709 = and(io.in.d.valid, d_first_2) node _T_710 = and(_T_709, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<13>(0h0) connect _WIRE_18.bits.source, UInt<14>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_711 = and(_T_710, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<13>(0h0) connect _WIRE_20.bits.source, UInt<14>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_713 = and(_T_711, _T_712) node _T_714 = and(_T_713, d_release_ack_1) node _T_715 = eq(c_probe_ack, UInt<1>(0h0)) node _T_716 = and(_T_714, _T_715) when _T_716 : node _T_717 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<13>(0h0) connect _WIRE_22.bits.source, UInt<14>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_718 = or(_T_717, _WIRE_23.ready) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_718, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_53 node _T_722 = orr(inflight_1) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_725 = or(_T_723, _T_724) node _T_726 = lt(watchdog_1, plusarg_reader_1.out) node _T_727 = or(_T_725, _T_726) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:49)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_727, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<13>(0h0) connect _WIRE_24.bits.source, UInt<14>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_732 = and(io.in.d.ready, io.in.d.valid) node _T_733 = or(_T_731, _T_732) when _T_733 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_26( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [13:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_address = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_address = 13'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_source = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_source = 14'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131073:0] _c_sizes_set_T_1 = 131074'h0; // @[Monitor.scala:768:52] wire [16:0] _c_opcodes_set_T = 17'h0; // @[Monitor.scala:767:79] wire [16:0] _c_sizes_set_T = 17'h0; // @[Monitor.scala:768:77] wire [131074:0] _c_opcodes_set_T_1 = 131075'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [16383:0] _c_set_wo_ready_T = 16384'h1; // @[OneHot.scala:58:35] wire [16383:0] _c_set_T = 16384'h1; // @[OneHot.scala:58:35] wire [32831:0] c_opcodes_set = 32832'h0; // @[Monitor.scala:740:34] wire [32831:0] c_sizes_set = 32832'h0; // @[Monitor.scala:741:34] wire [8207:0] c_set = 8208'h0; // @[Monitor.scala:738:34] wire [8207:0] c_set_wo_ready = 8208'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [13:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [13:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [12:0] _is_aligned_T = {10'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 13'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [13:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [13:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [13:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 14'h2010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [12:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [8207:0] a_set; // @[Monitor.scala:626:34] wire [8207:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [32831:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [32831:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [16:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [16:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [16:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [16:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [16:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [16:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [16:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [16:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [16:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [32831:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [32831:0] _a_opcode_lookup_T_6 = {32828'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [32831:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [32831:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [32831:0] _a_size_lookup_T_6 = {32828'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [32831:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[32831:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [16383:0] _GEN_2 = 16384'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [16383:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [16:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [16:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [16:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [131074:0] _a_opcodes_set_T_1 = {131071'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [131073:0] _a_sizes_set_T_1 = {131071'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[32831:0] : 32832'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8207:0] d_clr; // @[Monitor.scala:664:34] wire [8207:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [32831:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [32831:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [16383:0] _GEN_5 = 16384'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [16383:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_5 = 131087'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [131086:0] _d_sizes_clr_T_5 = 131087'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[32831:0] : 32832'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8207:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8207:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8207:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [32831:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [32831:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [32831:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [32831:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [32831:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [32831:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8207:0] inflight_1; // @[Monitor.scala:726:35] wire [8207:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [32831:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [32831:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [32831:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [32831:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [32831:0] _c_opcode_lookup_T_6 = {32828'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [32831:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[32831:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [32831:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [32831:0] _c_size_lookup_T_6 = {32828'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [32831:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[32831:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [8207:0] d_clr_1; // @[Monitor.scala:774:34] wire [8207:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [32831:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [32831:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[8207:0] : 8208'h0; // @[OneHot.scala:58:35] wire [131086:0] _d_opcodes_clr_T_11 = 131087'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [131086:0] _d_sizes_clr_T_11 = 131087'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[32831:0] : 32832'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 14'h0; // @[Monitor.scala:36:7, :795:113] wire [8207:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8207:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [32831:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [32831:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [32831:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [32831:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_146 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_TLBEntryData_146( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_7 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock inst q of Queue3_EgressFlit_7 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h18), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h12), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h14), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow

module EgressUnit_7( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_46 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_46( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_54 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_3 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} inst a of TLAFromNoC_3 connect a.clock, clock connect a.reset, reset inst b of TLBToNoC_3 connect b.clock, clock connect b.reset, reset inst c of TLCFromNoC_3 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_3 connect d.clock, clock connect d.reset, reset inst e of TLEFromNoC_3 connect e.clock, clock connect e.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect b.io.protocol, io.tilelink.b connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect io.tilelink.e.bits, e.io.protocol.bits connect io.tilelink.e.valid, e.io.protocol.valid connect e.io.protocol.ready, io.tilelink.e.ready connect a.io.flit, io.flits.a connect io.flits.b.bits, b.io.flit.bits connect io.flits.b.valid, b.io.flit.valid connect b.io.flit.ready, io.flits.b.ready connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready connect e.io.flit, io.flits.e

module TLSlaveToNoC_3( // @[Tilelink.scala:125:7] input clock, // @[Tilelink.scala:125:7] input reset, // @[Tilelink.scala:125:7] input io_tilelink_a_ready, // @[Tilelink.scala:132:14] output io_tilelink_a_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_b_ready, // @[Tilelink.scala:132:14] input io_tilelink_b_valid, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:132:14] input [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:132:14] input io_tilelink_c_ready, // @[Tilelink.scala:132:14] output io_tilelink_c_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_d_ready, // @[Tilelink.scala:132:14] input io_tilelink_d_valid, // @[Tilelink.scala:132:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_e_valid, // @[Tilelink.scala:132:14] output [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:132:14] output io_flits_a_ready, // @[Tilelink.scala:132:14] input io_flits_a_valid, // @[Tilelink.scala:132:14] input io_flits_a_bits_head, // @[Tilelink.scala:132:14] input io_flits_a_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14] input io_flits_b_ready, // @[Tilelink.scala:132:14] output io_flits_b_valid, // @[Tilelink.scala:132:14] output io_flits_b_bits_head, // @[Tilelink.scala:132:14] output io_flits_b_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_b_bits_egress_id, // @[Tilelink.scala:132:14] output io_flits_c_ready, // @[Tilelink.scala:132:14] input io_flits_c_valid, // @[Tilelink.scala:132:14] input io_flits_c_bits_head, // @[Tilelink.scala:132:14] input io_flits_c_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:132:14] input io_flits_d_ready, // @[Tilelink.scala:132:14] output io_flits_d_valid, // @[Tilelink.scala:132:14] output io_flits_d_bits_head, // @[Tilelink.scala:132:14] output io_flits_d_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14] output [3:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14] input io_flits_e_valid, // @[Tilelink.scala:132:14] input io_flits_e_bits_head, // @[Tilelink.scala:132:14] input io_flits_e_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_e_bits_payload // @[Tilelink.scala:132:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17] TLAFromNoC a ( // @[Tilelink.scala:143:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:143:17] TLBToNoC_1 b ( // @[Tilelink.scala:144:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload), .io_flit_bits_egress_id (io_flits_b_bits_egress_id) ); // @[Tilelink.scala:144:17] TLCFromNoC_1 c ( // @[Tilelink.scala:145:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:156:14] ); // @[Tilelink.scala:145:17] TLDToNoC_3 d ( // @[Tilelink.scala:146:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:146:17] TLEFromNoC_1 e ( // @[Tilelink.scala:147:17] .clock (clock), .reset (reset), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_tail (io_flits_e_bits_tail), .io_flit_bits_payload (io_flits_e_bits_payload[4:0]) // @[Tilelink.scala:158:14] ); // @[Tilelink.scala:147:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14] endmodule

Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_7 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_14 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_7 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h2) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h16), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h19), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1c), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h1f), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h4), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<3>(0h5), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(route_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_15 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_7 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_24 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_25 = and(vcalloc_q.io.enq.valid, _T_24) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : node _T_29 = eq(_T_26, UInt<1>(0h0)) when _T_29 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_26, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1

module IngressUnit_7( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h19; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h1C; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | ((&io_in_bits_egress_id) ? 4'hA : 4'h0); // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h2; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h2; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]

Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_1 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node doEarlyAck = bits(anonOut.d.bits.source, 4, 4) node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(doEarlyAck, dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 5) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a32d64s7k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node aFull = eq(repeater.io.deq.bits.opcode, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_lo = cat(aToggle, aFragnum) node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aFull) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, anonOut_a_bits_source_lo) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)

module TLFragmenter_1( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [6:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [31:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36] wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50] wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50] wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84] wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49] wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49] wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59] wire find_0 = 1'h1; // @[Parameters.scala:616:12] wire [32:0] _find_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _find_T_3 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9] wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9] wire [11:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9] wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9] wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9] wire [6:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9] wire [11:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9] wire [31:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9] wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9] wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41] wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30] wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}] wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71] wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}] wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45] wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27] wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}] wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47] wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46] wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35] wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}] wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53] wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}] wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}] wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18] wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18] wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28] wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28] wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}] wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}] wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55] wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55] wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}] wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41] wire doEarlyAck = anonOut_d_bits_source[4]; // @[Fragmenter.scala:231:54] wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20] wire _drop_T_1 = doEarlyAck ? dFirst : dLast; // @[Fragmenter.scala:205:29, :206:30, :231:54, :234:37] wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}] wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}] assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35] wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39] assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}] assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36] assign _anonIn_d_bits_source_T = anonOut_d_bits_source[11:5]; // @[Fragmenter.scala:238:47] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47] assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32] wire [31:0] _find_T; // @[Parameters.scala:137:31] wire [32:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}] wire _GEN = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T; // @[Fragmenter.scala:288:49] assign _limit_T = _GEN; // @[Fragmenter.scala:288:49] wire aFull; // @[Fragmenter.scala:310:78] assign aFull = _GEN; // @[Fragmenter.scala:288:49, :310:78] wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49] wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49] wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31] wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}] wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71] wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}] wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30] wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46] wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79] wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79] wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}] wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40] wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28] wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}] wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}] wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}] wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}] wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}] wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30] reg aToggle_r; // @[Fragmenter.scala:309:54] wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}] wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}] wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31] wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53] wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}] wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65] wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}] wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46] wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}] wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}] assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[31:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}] assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49] wire [3:0] anonOut_a_bits_source_lo = {aToggle, aFragnum}; // @[Fragmenter.scala:307:24, :309:23, :317:33] wire [7:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aFull}; // @[Fragmenter.scala:274:30, :310:78, :317:33] assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, anonOut_a_bits_source_lo}; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33] assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module MacUnit_32 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3

module MacUnit_32( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MSHR_33 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h28)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h28)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)

module MSHR_33( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [10:0] io_status_bits_set, // @[MSHR.scala:86:14] output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [3:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [10:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [8:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [3:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

Generate the Verilog code corresponding to this FIRRTL code module SimpleHellaCacheIF : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, cache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} invalidate io.cache.clock_enabled invalidate io.cache.keep_clock_enabled invalidate io.cache.perf.storeBufferEmptyAfterStore invalidate io.cache.perf.storeBufferEmptyAfterLoad invalidate io.cache.perf.canAcceptLoadThenLoad invalidate io.cache.perf.canAcceptStoreThenRMW invalidate io.cache.perf.canAcceptStoreThenLoad invalidate io.cache.perf.blocked invalidate io.cache.perf.tlbMiss invalidate io.cache.perf.grant invalidate io.cache.perf.release invalidate io.cache.perf.acquire invalidate io.cache.store_pending invalidate io.cache.ordered invalidate io.cache.s2_gpa_is_pte invalidate io.cache.s2_gpa invalidate io.cache.s2_xcpt.ae.st invalidate io.cache.s2_xcpt.ae.ld invalidate io.cache.s2_xcpt.gf.st invalidate io.cache.s2_xcpt.gf.ld invalidate io.cache.s2_xcpt.pf.st invalidate io.cache.s2_xcpt.pf.ld invalidate io.cache.s2_xcpt.ma.st invalidate io.cache.s2_xcpt.ma.ld invalidate io.cache.replay_next invalidate io.cache.resp.bits.store_data invalidate io.cache.resp.bits.data_raw invalidate io.cache.resp.bits.data_word_bypass invalidate io.cache.resp.bits.has_data invalidate io.cache.resp.bits.replay invalidate io.cache.resp.bits.mask invalidate io.cache.resp.bits.data invalidate io.cache.resp.bits.dv invalidate io.cache.resp.bits.dprv invalidate io.cache.resp.bits.signed invalidate io.cache.resp.bits.size invalidate io.cache.resp.bits.cmd invalidate io.cache.resp.bits.tag invalidate io.cache.resp.bits.addr invalidate io.cache.resp.valid invalidate io.cache.s2_paddr invalidate io.cache.s2_uncached invalidate io.cache.s2_kill invalidate io.cache.s2_nack_cause_raw invalidate io.cache.s2_nack invalidate io.cache.s1_data.mask invalidate io.cache.s1_data.data invalidate io.cache.s1_kill invalidate io.cache.req.bits.mask invalidate io.cache.req.bits.data invalidate io.cache.req.bits.no_xcpt invalidate io.cache.req.bits.no_alloc invalidate io.cache.req.bits.no_resp invalidate io.cache.req.bits.phys invalidate io.cache.req.bits.dv invalidate io.cache.req.bits.dprv invalidate io.cache.req.bits.signed invalidate io.cache.req.bits.size invalidate io.cache.req.bits.cmd invalidate io.cache.req.bits.tag invalidate io.cache.req.bits.addr invalidate io.cache.req.valid invalidate io.cache.req.ready invalidate io.requestor.clock_enabled invalidate io.requestor.keep_clock_enabled invalidate io.requestor.perf.storeBufferEmptyAfterStore invalidate io.requestor.perf.storeBufferEmptyAfterLoad invalidate io.requestor.perf.canAcceptLoadThenLoad invalidate io.requestor.perf.canAcceptStoreThenRMW invalidate io.requestor.perf.canAcceptStoreThenLoad invalidate io.requestor.perf.blocked invalidate io.requestor.perf.tlbMiss invalidate io.requestor.perf.grant invalidate io.requestor.perf.release invalidate io.requestor.perf.acquire invalidate io.requestor.store_pending invalidate io.requestor.ordered invalidate io.requestor.s2_gpa_is_pte invalidate io.requestor.s2_gpa invalidate io.requestor.s2_xcpt.ae.st invalidate io.requestor.s2_xcpt.ae.ld invalidate io.requestor.s2_xcpt.gf.st invalidate io.requestor.s2_xcpt.gf.ld invalidate io.requestor.s2_xcpt.pf.st invalidate io.requestor.s2_xcpt.pf.ld invalidate io.requestor.s2_xcpt.ma.st invalidate io.requestor.s2_xcpt.ma.ld invalidate io.requestor.replay_next invalidate io.requestor.resp.bits.store_data invalidate io.requestor.resp.bits.data_raw invalidate io.requestor.resp.bits.data_word_bypass invalidate io.requestor.resp.bits.has_data invalidate io.requestor.resp.bits.replay invalidate io.requestor.resp.bits.mask invalidate io.requestor.resp.bits.data invalidate io.requestor.resp.bits.dv invalidate io.requestor.resp.bits.dprv invalidate io.requestor.resp.bits.signed invalidate io.requestor.resp.bits.size invalidate io.requestor.resp.bits.cmd invalidate io.requestor.resp.bits.tag invalidate io.requestor.resp.bits.addr invalidate io.requestor.resp.valid invalidate io.requestor.s2_paddr invalidate io.requestor.s2_uncached invalidate io.requestor.s2_kill invalidate io.requestor.s2_nack_cause_raw invalidate io.requestor.s2_nack invalidate io.requestor.s1_data.mask invalidate io.requestor.s1_data.data invalidate io.requestor.s1_kill invalidate io.requestor.req.bits.mask invalidate io.requestor.req.bits.data invalidate io.requestor.req.bits.no_xcpt invalidate io.requestor.req.bits.no_alloc invalidate io.requestor.req.bits.no_resp invalidate io.requestor.req.bits.phys invalidate io.requestor.req.bits.dv invalidate io.requestor.req.bits.dprv invalidate io.requestor.req.bits.signed invalidate io.requestor.req.bits.size invalidate io.requestor.req.bits.cmd invalidate io.requestor.req.bits.tag invalidate io.requestor.req.bits.addr invalidate io.requestor.req.valid invalidate io.requestor.req.ready inst replayq of SimpleHellaCacheIFReplayQueue connect replayq.clock, clock connect replayq.reset, reset inst req_arb of Arbiter2_HellaCacheReq connect req_arb.clock, clock connect req_arb.reset, reset connect req_arb.io.in[0], replayq.io.replay node _req_arb_io_in_1_valid_T = and(replayq.io.req.ready, io.requestor.req.valid) connect req_arb.io.in[1].valid, _req_arb_io_in_1_valid_T connect req_arb.io.in[1].bits.mask, io.requestor.req.bits.mask connect req_arb.io.in[1].bits.data, io.requestor.req.bits.data connect req_arb.io.in[1].bits.no_xcpt, io.requestor.req.bits.no_xcpt connect req_arb.io.in[1].bits.no_alloc, io.requestor.req.bits.no_alloc connect req_arb.io.in[1].bits.no_resp, io.requestor.req.bits.no_resp connect req_arb.io.in[1].bits.phys, io.requestor.req.bits.phys connect req_arb.io.in[1].bits.dv, io.requestor.req.bits.dv connect req_arb.io.in[1].bits.dprv, io.requestor.req.bits.dprv connect req_arb.io.in[1].bits.signed, io.requestor.req.bits.signed connect req_arb.io.in[1].bits.size, io.requestor.req.bits.size connect req_arb.io.in[1].bits.cmd, io.requestor.req.bits.cmd connect req_arb.io.in[1].bits.tag, io.requestor.req.bits.tag connect req_arb.io.in[1].bits.addr, io.requestor.req.bits.addr node _io_requestor_req_ready_T = and(req_arb.io.in[1].ready, replayq.io.req.ready) connect io.requestor.req.ready, _io_requestor_req_ready_T node _replayq_io_req_valid_T = and(req_arb.io.in[1].ready, io.requestor.req.valid) connect replayq.io.req.valid, _replayq_io_req_valid_T connect replayq.io.req.bits.mask, io.requestor.req.bits.mask connect replayq.io.req.bits.data, io.requestor.req.bits.data connect replayq.io.req.bits.no_xcpt, io.requestor.req.bits.no_xcpt connect replayq.io.req.bits.no_alloc, io.requestor.req.bits.no_alloc connect replayq.io.req.bits.no_resp, io.requestor.req.bits.no_resp connect replayq.io.req.bits.phys, io.requestor.req.bits.phys connect replayq.io.req.bits.dv, io.requestor.req.bits.dv connect replayq.io.req.bits.dprv, io.requestor.req.bits.dprv connect replayq.io.req.bits.signed, io.requestor.req.bits.signed connect replayq.io.req.bits.size, io.requestor.req.bits.size connect replayq.io.req.bits.cmd, io.requestor.req.bits.cmd connect replayq.io.req.bits.tag, io.requestor.req.bits.tag connect replayq.io.req.bits.addr, io.requestor.req.bits.addr node s0_req_fire = and(io.cache.req.ready, io.cache.req.valid) reg s1_req_fire : UInt<1>, clock connect s1_req_fire, s0_req_fire reg s2_req_fire : UInt<1>, clock connect s2_req_fire, s1_req_fire reg s1_req_tag : UInt, clock connect s1_req_tag, io.cache.req.bits.tag reg s2_req_tag : UInt, clock connect s2_req_tag, s1_req_tag reg REG : UInt<1>, clock connect REG, io.cache.s2_nack node _T = eq(REG, UInt<1>(0h0)) node _T_1 = eq(s2_req_fire, UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = or(_T_2, io.cache.s2_nack) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:124 assert(!RegNext(io.cache.s2_nack) || !s2_req_fire || io.cache.s2_nack)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _T_7 = eq(io.cache.s2_nack, UInt<1>(0h0)) node _T_8 = eq(io.cache.req.ready, UInt<1>(0h0)) node _T_9 = or(_T_7, _T_8) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SimpleHellaCacheIF.scala:125 assert(!io.cache.s2_nack || !io.cache.req.ready)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 connect io.cache.req.bits, req_arb.io.out.bits connect io.cache.req.valid, req_arb.io.out.valid connect req_arb.io.out.ready, io.cache.req.ready connect io.cache.s1_kill, UInt<1>(0h0) reg io_cache_s1_data_r : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock when s0_req_fire : connect io_cache_s1_data_r, req_arb.io.out.bits connect io.cache.s1_data.mask, io_cache_s1_data_r.mask connect io.cache.s1_data.data, io_cache_s1_data_r.data connect io.cache.s2_kill, UInt<1>(0h0) node _replayq_io_nack_valid_T = and(io.cache.s2_nack, s2_req_fire) connect replayq.io.nack.valid, _replayq_io_nack_valid_T connect replayq.io.nack.bits, s2_req_tag connect replayq.io.resp.bits.store_data, io.cache.resp.bits.store_data connect replayq.io.resp.bits.data_raw, io.cache.resp.bits.data_raw connect replayq.io.resp.bits.data_word_bypass, io.cache.resp.bits.data_word_bypass connect replayq.io.resp.bits.has_data, io.cache.resp.bits.has_data connect replayq.io.resp.bits.replay, io.cache.resp.bits.replay connect replayq.io.resp.bits.mask, io.cache.resp.bits.mask connect replayq.io.resp.bits.data, io.cache.resp.bits.data connect replayq.io.resp.bits.dv, io.cache.resp.bits.dv connect replayq.io.resp.bits.dprv, io.cache.resp.bits.dprv connect replayq.io.resp.bits.signed, io.cache.resp.bits.signed connect replayq.io.resp.bits.size, io.cache.resp.bits.size connect replayq.io.resp.bits.cmd, io.cache.resp.bits.cmd connect replayq.io.resp.bits.tag, io.cache.resp.bits.tag connect replayq.io.resp.bits.addr, io.cache.resp.bits.addr connect replayq.io.resp.valid, io.cache.resp.valid connect io.requestor.resp, io.cache.resp node _T_13 = eq(s2_req_fire, UInt<1>(0h0)) node _T_14 = cat(io.cache.s2_xcpt.ae.ld, io.cache.s2_xcpt.ae.st) node _T_15 = cat(io.cache.s2_xcpt.gf.ld, io.cache.s2_xcpt.gf.st) node _T_16 = cat(io.cache.s2_xcpt.pf.ld, io.cache.s2_xcpt.pf.st) node _T_17 = cat(io.cache.s2_xcpt.ma.ld, io.cache.s2_xcpt.ma.st) node lo = cat(_T_15, _T_14) node hi = cat(_T_17, _T_16) node _T_18 = cat(hi, lo) node _T_19 = orr(_T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = or(_T_13, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed: SimpleHellaCacheIF exception\n at SimpleHellaCacheIF.scala:137 assert(!s2_req_fire || !io.cache.s2_xcpt.asUInt.orR, \"SimpleHellaCacheIF exception\")\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2

module SimpleHellaCacheIF( // @[SimpleHellaCacheIF.scala:95:7] input clock, // @[SimpleHellaCacheIF.scala:95:7] input reset, // @[SimpleHellaCacheIF.scala:95:7] output io_requestor_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] output [39:0] io_requestor_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] output [4:0] io_requestor_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] output [1:0] io_requestor_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_requestor_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] output io_requestor_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_requestor_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_req_ready, // @[SimpleHellaCacheIF.scala:97:14] output io_cache_req_valid, // @[SimpleHellaCacheIF.scala:97:14] output [63:0] io_cache_s1_data_data, // @[SimpleHellaCacheIF.scala:97:14] output [7:0] io_cache_s1_data_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_nack_cause_raw, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_uncached, // @[SimpleHellaCacheIF.scala:97:14] input [31:0] io_cache_s2_paddr, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_valid, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_resp_bits_addr, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_tag, // @[SimpleHellaCacheIF.scala:97:14] input [4:0] io_cache_resp_bits_cmd, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_size, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_signed, // @[SimpleHellaCacheIF.scala:97:14] input [1:0] io_cache_resp_bits_dprv, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_dv, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data, // @[SimpleHellaCacheIF.scala:97:14] input [7:0] io_cache_resp_bits_mask, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_replay, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_resp_bits_has_data, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_word_bypass, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_data_raw, // @[SimpleHellaCacheIF.scala:97:14] input [63:0] io_cache_resp_bits_store_data, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_replay_next, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ma_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_pf_st, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_ld, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_s2_xcpt_ae_st, // @[SimpleHellaCacheIF.scala:97:14] input [39:0] io_cache_s2_gpa, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_ordered, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_store_pending, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_acquire, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_release, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_grant, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_tlbMiss, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_blocked, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptStoreThenRMW, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_canAcceptLoadThenLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterLoad, // @[SimpleHellaCacheIF.scala:97:14] input io_cache_perf_storeBufferEmptyAfterStore // @[SimpleHellaCacheIF.scala:97:14] ); wire _req_arb_io_in_0_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _req_arb_io_in_1_ready; // @[SimpleHellaCacheIF.scala:104:23] wire _replayq_io_req_ready; // @[SimpleHellaCacheIF.scala:103:23] wire _replayq_io_replay_valid; // @[SimpleHellaCacheIF.scala:103:23] wire io_cache_req_ready_0 = io_cache_req_ready; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_0 = io_cache_s2_nack; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_nack_cause_raw_0 = io_cache_s2_nack_cause_raw; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_uncached_0 = io_cache_s2_uncached; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_cache_s2_paddr_0 = io_cache_s2_paddr; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_valid_0 = io_cache_resp_valid; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_resp_bits_addr_0 = io_cache_resp_bits_addr; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_tag_0 = io_cache_resp_bits_tag; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_resp_bits_cmd_0 = io_cache_resp_bits_cmd; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_size_0 = io_cache_resp_bits_size; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_signed_0 = io_cache_resp_bits_signed; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_resp_bits_dprv_0 = io_cache_resp_bits_dprv; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_dv_0 = io_cache_resp_bits_dv; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_0 = io_cache_resp_bits_data; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_resp_bits_mask_0 = io_cache_resp_bits_mask; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_replay_0 = io_cache_resp_bits_replay; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_resp_bits_has_data_0 = io_cache_resp_bits_has_data; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_resp_bits_store_data_0 = io_cache_resp_bits_store_data; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_replay_next_0 = io_cache_replay_next; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_ld_0 = io_cache_s2_xcpt_ma_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ma_st_0 = io_cache_s2_xcpt_ma_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_ld_0 = io_cache_s2_xcpt_pf_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_pf_st_0 = io_cache_s2_xcpt_pf_st; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_ld_0 = io_cache_s2_xcpt_ae_ld; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_ae_st_0 = io_cache_s2_xcpt_ae_st; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_s2_gpa_0 = io_cache_s2_gpa; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_ordered_0 = io_cache_ordered; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_store_pending_0 = io_cache_store_pending; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_acquire_0 = io_cache_perf_acquire; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_release_0 = io_cache_perf_release; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_grant_0 = io_cache_perf_grant; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_tlbMiss_0 = io_cache_perf_tlbMiss; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_blocked_0 = io_cache_perf_blocked; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenLoad_0 = io_cache_perf_canAcceptStoreThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptStoreThenRMW_0 = io_cache_perf_canAcceptStoreThenRMW; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_canAcceptLoadThenLoad_0 = io_cache_perf_canAcceptLoadThenLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterLoad_0 = io_cache_perf_storeBufferEmptyAfterLoad; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_perf_storeBufferEmptyAfterStore_0 = io_cache_perf_storeBufferEmptyAfterStore; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_req_bits_addr = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_s2_gpa = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_cache_req_bits_addr = 40'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_tag = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_s1_data_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_tag = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_req_bits_mask = 8'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_cache_req_bits_cmd = 5'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_size = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_req_bits_dprv = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_size = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_cache_req_bits_dprv = 2'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_valid = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_dv = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_nack_cause_raw = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_uncached = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_replay_next = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ma_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_pf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_xcpt_ae_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_ordered = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_store_pending = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_acquire = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_release = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_grant = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_tlbMiss = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_blocked = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptStoreThenRMW = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_canAcceptLoadThenLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterLoad = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_perf_storeBufferEmptyAfterStore = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_signed = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_dv = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_phys = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_resp = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_alloc = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_bits_no_xcpt = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s1_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_kill = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_ld = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_xcpt_gf_st = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_s2_gpa_is_pte = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_keep_clock_enabled = 1'h0; // @[SimpleHellaCacheIF.scala:95:7] wire _req_arb_io_in_1_valid_T = 1'h0; // @[Misc.scala:26:53] wire _replayq_io_req_valid_T = 1'h0; // @[Misc.scala:26:53] wire [63:0] io_requestor_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_s1_data_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_req_bits_data = 64'h0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_keep_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_clock_enabled = 1'h1; // @[SimpleHellaCacheIF.scala:95:7] wire [31:0] io_requestor_s2_paddr = 32'h0; // @[SimpleHellaCacheIF.scala:95:7] wire _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire io_requestor_resp_valid_0 = io_cache_resp_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [39:0] io_requestor_resp_bits_addr_0 = io_cache_resp_bits_addr_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_tag_0 = io_cache_resp_bits_tag_0; // @[SimpleHellaCacheIF.scala:95:7] wire [4:0] io_requestor_resp_bits_cmd_0 = io_cache_resp_bits_cmd_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_size_0 = io_cache_resp_bits_size_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_signed_0 = io_cache_resp_bits_signed_0; // @[SimpleHellaCacheIF.scala:95:7] wire [1:0] io_requestor_resp_bits_dprv_0 = io_cache_resp_bits_dprv_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_dv_0 = io_cache_resp_bits_dv_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_0 = io_cache_resp_bits_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_requestor_resp_bits_mask_0 = io_cache_resp_bits_mask_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_replay_0 = io_cache_resp_bits_replay_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_resp_bits_has_data_0 = io_cache_resp_bits_has_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_word_bypass_0 = io_cache_resp_bits_data_word_bypass_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_data_raw_0 = io_cache_resp_bits_data_raw_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_requestor_resp_bits_store_data_0 = io_cache_resp_bits_store_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_requestor_req_ready_0; // @[SimpleHellaCacheIF.scala:95:7] wire io_cache_req_valid_0; // @[SimpleHellaCacheIF.scala:95:7] wire [63:0] io_cache_s1_data_data_0; // @[SimpleHellaCacheIF.scala:95:7] wire [7:0] io_cache_s1_data_mask_0; // @[SimpleHellaCacheIF.scala:95:7] assign _io_requestor_req_ready_T = _req_arb_io_in_1_ready & _replayq_io_req_ready; // @[Misc.scala:26:53] assign io_requestor_req_ready_0 = _io_requestor_req_ready_T; // @[Misc.scala:26:53] wire s0_req_fire = io_cache_req_ready_0 & io_cache_req_valid_0; // @[Decoupled.scala:51:35] reg s1_req_fire; // @[SimpleHellaCacheIF.scala:119:28] reg s2_req_fire; // @[SimpleHellaCacheIF.scala:120:28] reg [7:0] s1_req_tag; // @[SimpleHellaCacheIF.scala:121:27] reg [7:0] s2_req_tag; // @[SimpleHellaCacheIF.scala:122:27] reg REG; // @[SimpleHellaCacheIF.scala:124:18] reg [39:0] io_cache_s1_data_r_addr; // @[SimpleHellaCacheIF.scala:129:32] reg [7:0] io_cache_s1_data_r_tag; // @[SimpleHellaCacheIF.scala:129:32] reg [4:0] io_cache_s1_data_r_cmd; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_size; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_signed; // @[SimpleHellaCacheIF.scala:129:32] reg [1:0] io_cache_s1_data_r_dprv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_dv; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_phys; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_resp; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_alloc; // @[SimpleHellaCacheIF.scala:129:32] reg io_cache_s1_data_r_no_xcpt; // @[SimpleHellaCacheIF.scala:129:32] reg [63:0] io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_data_0 = io_cache_s1_data_r_data; // @[SimpleHellaCacheIF.scala:95:7, :129:32] reg [7:0] io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:129:32] assign io_cache_s1_data_mask_0 = io_cache_s1_data_r_mask; // @[SimpleHellaCacheIF.scala:95:7, :129:32] wire _replayq_io_nack_valid_T = io_cache_s2_nack_0 & s2_req_fire; // @[SimpleHellaCacheIF.scala:95:7, :120:28, :132:45] wire [3:0] lo = {2'h0, io_cache_s2_xcpt_ae_ld_0, io_cache_s2_xcpt_ae_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44] wire [3:0] hi = {io_cache_s2_xcpt_ma_ld_0, io_cache_s2_xcpt_ma_st_0, io_cache_s2_xcpt_pf_ld_0, io_cache_s2_xcpt_pf_st_0}; // @[SimpleHellaCacheIF.scala:95:7, :137:44]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_287( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_89 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_29 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_29( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_g, // @[package.scala:268:18] output io_y_ae, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c, // @[package.scala:268:18] output io_y_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_g = io_y_g_0; // @[package.scala:267:30] assign io_y_ae = io_y_ae_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecF64ToRaw_mulAddZ31 : input clock : Clock input reset : Reset output io : { inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} regreset cycleNum_A : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_B : UInt<4>, clock, reset, UInt<4>(0h0) regreset cycleNum_C : UInt<3>, clock, reset, UInt<3>(0h0) regreset cycleNum_E : UInt<3>, clock, reset, UInt<3>(0h0) regreset valid_PA : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PA : UInt<1>, clock reg majorExc_PA : UInt<1>, clock reg isNaN_PA : UInt<1>, clock reg isInf_PA : UInt<1>, clock reg isZero_PA : UInt<1>, clock reg sign_PA : UInt<1>, clock reg sExp_PA : SInt<13>, clock reg fractB_PA : UInt<52>, clock reg fractA_PA : UInt<52>, clock reg roundingMode_PA : UInt<3>, clock regreset valid_PB : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PB : UInt<1>, clock reg majorExc_PB : UInt<1>, clock reg isNaN_PB : UInt<1>, clock reg isInf_PB : UInt<1>, clock reg isZero_PB : UInt<1>, clock reg sign_PB : UInt<1>, clock reg sExp_PB : SInt<13>, clock reg bit0FractA_PB : UInt<1>, clock reg fractB_PB : UInt<52>, clock reg roundingMode_PB : UInt<3>, clock regreset valid_PC : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_PC : UInt<1>, clock reg majorExc_PC : UInt<1>, clock reg isNaN_PC : UInt<1>, clock reg isInf_PC : UInt<1>, clock reg isZero_PC : UInt<1>, clock reg sign_PC : UInt<1>, clock reg sExp_PC : SInt<13>, clock reg bit0FractA_PC : UInt<1>, clock reg fractB_PC : UInt<52>, clock reg roundingMode_PC : UInt<3>, clock reg fractR0_A : UInt<9>, clock reg hiSqrR0_A_sqrt : UInt<10>, clock reg partNegSigma0_A : UInt<21>, clock reg nextMulAdd9A_A : UInt<9>, clock reg nextMulAdd9B_A : UInt<9>, clock reg ER1_B_sqrt : UInt<17>, clock reg ESqrR1_B_sqrt : UInt<32>, clock reg sigX1_B : UInt<58>, clock reg sqrSigma1_C : UInt<33>, clock reg sigXN_C : UInt<58>, clock reg u_C_sqrt : UInt<31>, clock reg E_E_div : UInt<1>, clock reg sigT_E : UInt<54>, clock reg isNegRemT_E : UInt<1>, clock reg isZeroRemT_E : UInt<1>, clock wire ready_PA : UInt<1> wire ready_PB : UInt<1> wire ready_PC : UInt<1> wire leaving_PA : UInt<1> wire leaving_PB : UInt<1> wire leaving_PC : UInt<1> wire zSigma1_B4 : UInt wire sigXNU_B3_CX : UInt wire zComplSigT_C1_sqrt : UInt wire zComplSigT_C1 : UInt node _cyc_S_div_T = and(io.inReady_div, io.inValid) node _cyc_S_div_T_1 = eq(io.sqrtOp, UInt<1>(0h0)) node cyc_S_div = and(_cyc_S_div_T, _cyc_S_div_T_1) node _cyc_S_sqrt_T = and(io.inReady_sqrt, io.inValid) node cyc_S_sqrt = and(_cyc_S_sqrt_T, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) node rawA_S_exp = bits(io.a, 63, 52) node _rawA_S_isZero_T = bits(rawA_S_exp, 11, 9) node rawA_S_isZero = eq(_rawA_S_isZero_T, UInt<1>(0h0)) node _rawA_S_isSpecial_T = bits(rawA_S_exp, 11, 10) node rawA_S_isSpecial = eq(_rawA_S_isSpecial_T, UInt<2>(0h3)) wire rawA_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_S_out_isNaN_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isNaN_T_1 = and(rawA_S_isSpecial, _rawA_S_out_isNaN_T) connect rawA_S.isNaN, _rawA_S_out_isNaN_T_1 node _rawA_S_out_isInf_T = bits(rawA_S_exp, 9, 9) node _rawA_S_out_isInf_T_1 = eq(_rawA_S_out_isInf_T, UInt<1>(0h0)) node _rawA_S_out_isInf_T_2 = and(rawA_S_isSpecial, _rawA_S_out_isInf_T_1) connect rawA_S.isInf, _rawA_S_out_isInf_T_2 connect rawA_S.isZero, rawA_S_isZero node _rawA_S_out_sign_T = bits(io.a, 64, 64) connect rawA_S.sign, _rawA_S_out_sign_T node _rawA_S_out_sExp_T = cvt(rawA_S_exp) connect rawA_S.sExp, _rawA_S_out_sExp_T node _rawA_S_out_sig_T = eq(rawA_S_isZero, UInt<1>(0h0)) node _rawA_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_S_out_sig_T) node _rawA_S_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_S_out_sig_T_3 = cat(_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2) connect rawA_S.sig, _rawA_S_out_sig_T_3 node rawB_S_exp = bits(io.b, 63, 52) node _rawB_S_isZero_T = bits(rawB_S_exp, 11, 9) node rawB_S_isZero = eq(_rawB_S_isZero_T, UInt<1>(0h0)) node _rawB_S_isSpecial_T = bits(rawB_S_exp, 11, 10) node rawB_S_isSpecial = eq(_rawB_S_isSpecial_T, UInt<2>(0h3)) wire rawB_S : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_S_out_isNaN_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isNaN_T_1 = and(rawB_S_isSpecial, _rawB_S_out_isNaN_T) connect rawB_S.isNaN, _rawB_S_out_isNaN_T_1 node _rawB_S_out_isInf_T = bits(rawB_S_exp, 9, 9) node _rawB_S_out_isInf_T_1 = eq(_rawB_S_out_isInf_T, UInt<1>(0h0)) node _rawB_S_out_isInf_T_2 = and(rawB_S_isSpecial, _rawB_S_out_isInf_T_1) connect rawB_S.isInf, _rawB_S_out_isInf_T_2 connect rawB_S.isZero, rawB_S_isZero node _rawB_S_out_sign_T = bits(io.b, 64, 64) connect rawB_S.sign, _rawB_S_out_sign_T node _rawB_S_out_sExp_T = cvt(rawB_S_exp) connect rawB_S.sExp, _rawB_S_out_sExp_T node _rawB_S_out_sig_T = eq(rawB_S_isZero, UInt<1>(0h0)) node _rawB_S_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_S_out_sig_T) node _rawB_S_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_S_out_sig_T_3 = cat(_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2) connect rawB_S.sig, _rawB_S_out_sig_T_3 node _notSigNaNIn_invalidExc_S_div_T = and(rawA_S.isZero, rawB_S.isZero) node _notSigNaNIn_invalidExc_S_div_T_1 = and(rawA_S.isInf, rawB_S.isInf) node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) node _notSigNaNIn_invalidExc_S_sqrt_T = eq(rawB_S.isNaN, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(rawB_S.isZero, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, rawB_S.sign) node _majorExc_S_T = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) node _majorExc_S_T_2 = and(rawB_S.isNaN, _majorExc_S_T_1) node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) node _majorExc_S_T_4 = bits(rawA_S.sig, 51, 51) node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) node _majorExc_S_T_6 = and(rawA_S.isNaN, _majorExc_S_T_5) node _majorExc_S_T_7 = bits(rawB_S.sig, 51, 51) node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) node _majorExc_S_T_9 = and(rawB_S.isNaN, _majorExc_S_T_8) node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) node _majorExc_S_T_12 = eq(rawA_S.isNaN, UInt<1>(0h0)) node _majorExc_S_T_13 = eq(rawA_S.isInf, UInt<1>(0h0)) node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) node _majorExc_S_T_15 = and(_majorExc_S_T_14, rawB_S.isZero) node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) node _isNaN_S_T = or(rawB_S.isNaN, notSigNaNIn_invalidExc_S_sqrt) node _isNaN_S_T_1 = or(rawA_S.isNaN, rawB_S.isNaN) node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) node _isInf_S_T = or(rawA_S.isInf, rawB_S.isZero) node isInf_S = mux(io.sqrtOp, rawB_S.isInf, _isInf_S_T) node _isZero_S_T = or(rawA_S.isZero, rawB_S.isInf) node isZero_S = mux(io.sqrtOp, rawB_S.isZero, _isZero_S_T) node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sign_S_T_1 = and(_sign_S_T, rawA_S.sign) node sign_S = xor(_sign_S_T_1, rawB_S.sign) node _specialCaseA_S_T = or(rawA_S.isNaN, rawA_S.isInf) node specialCaseA_S = or(_specialCaseA_S_T, rawA_S.isZero) node _specialCaseB_S_T = or(rawB_S.isNaN, rawB_S.isInf) node specialCaseB_S = or(_specialCaseB_S_T, rawB_S.isZero) node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) node _normalCase_S_sqrt_T = eq(specialCaseB_S, UInt<1>(0h0)) node _normalCase_S_sqrt_T_1 = eq(rawB_S.sign, UInt<1>(0h0)) node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node _sExpQuot_S_div_T = bits(rawB_S.sExp, 11, 11) node _sExpQuot_S_div_T_1 = bits(rawB_S.sExp, 10, 0) node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) node sExpQuot_S_div = add(rawA_S.sExp, _sExpQuot_S_div_T_4) node _sSatExpQuot_S_div_T = leq(asSInt(UInt<13>(0he00)), sExpQuot_S_div) node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 12, 9) node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 8, 0) node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) node _T = neq(cycleNum_A, UInt<1>(0h0)) node _T_1 = or(entering_PA_normalCase, _T) when _T_1 : node _cycleNum_A_T = mux(entering_PA_normalCase_div, UInt<2>(0h3), UInt<1>(0h0)) node _cycleNum_A_T_1 = mux(entering_PA_normalCase_sqrt, UInt<3>(0h6), UInt<1>(0h0)) node _cycleNum_A_T_2 = or(_cycleNum_A_T, _cycleNum_A_T_1) node _cycleNum_A_T_3 = eq(entering_PA_normalCase, UInt<1>(0h0)) node _cycleNum_A_T_4 = sub(cycleNum_A, UInt<1>(0h1)) node _cycleNum_A_T_5 = tail(_cycleNum_A_T_4, 1) node _cycleNum_A_T_6 = mux(_cycleNum_A_T_3, _cycleNum_A_T_5, UInt<1>(0h0)) node _cycleNum_A_T_7 = or(_cycleNum_A_T_2, _cycleNum_A_T_6) connect cycleNum_A, _cycleNum_A_T_7 node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>(0h6)) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>(0h5)) node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>(0h4)) node cyc_A4 = or(cyc_A4_sqrt, entering_PA_normalCase_div) node cyc_A3 = eq(cycleNum_A, UInt<2>(0h3)) node cyc_A2 = eq(cycleNum_A, UInt<2>(0h2)) node cyc_A1 = eq(cycleNum_A, UInt<1>(0h1)) node _cyc_A3_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A3_div = and(cyc_A3, _cyc_A3_div_T) node _cyc_A2_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A2_div = and(cyc_A2, _cyc_A2_div_T) node _cyc_A1_div_T = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_A1_div = and(cyc_A1, _cyc_A1_div_T) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) node _T_2 = neq(cycleNum_B, UInt<1>(0h0)) node _T_3 = or(cyc_A1, _T_2) when _T_3 : node _cycleNum_B_T = mux(sqrtOp_PA, UInt<4>(0ha), UInt<3>(0h6)) node _cycleNum_B_T_1 = sub(cycleNum_B, UInt<1>(0h1)) node _cycleNum_B_T_2 = tail(_cycleNum_B_T_1, 1) node _cycleNum_B_T_3 = mux(cyc_A1, _cycleNum_B_T, _cycleNum_B_T_2) connect cycleNum_B, _cycleNum_B_T_3 node cyc_B10_sqrt = eq(cycleNum_B, UInt<4>(0ha)) node cyc_B9_sqrt = eq(cycleNum_B, UInt<4>(0h9)) node cyc_B8_sqrt = eq(cycleNum_B, UInt<4>(0h8)) node cyc_B7_sqrt = eq(cycleNum_B, UInt<3>(0h7)) node cyc_B6 = eq(cycleNum_B, UInt<3>(0h6)) node cyc_B5 = eq(cycleNum_B, UInt<3>(0h5)) node cyc_B4 = eq(cycleNum_B, UInt<3>(0h4)) node cyc_B3 = eq(cycleNum_B, UInt<2>(0h3)) node cyc_B2 = eq(cycleNum_B, UInt<2>(0h2)) node cyc_B1 = eq(cycleNum_B, UInt<1>(0h1)) node _cyc_B6_div_T = and(cyc_B6, valid_PA) node _cyc_B6_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B6_div = and(_cyc_B6_div_T, _cyc_B6_div_T_1) node _cyc_B5_div_T = and(cyc_B5, valid_PA) node _cyc_B5_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B5_div = and(_cyc_B5_div_T, _cyc_B5_div_T_1) node _cyc_B4_div_T = and(cyc_B4, valid_PA) node _cyc_B4_div_T_1 = eq(sqrtOp_PA, UInt<1>(0h0)) node cyc_B4_div = and(_cyc_B4_div_T, _cyc_B4_div_T_1) node _cyc_B3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B3_div = and(cyc_B3, _cyc_B3_div_T) node _cyc_B2_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B2_div = and(cyc_B2, _cyc_B2_div_T) node _cyc_B1_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_B1_div = and(cyc_B1, _cyc_B1_div_T) node _cyc_B6_sqrt_T = and(cyc_B6, valid_PB) node cyc_B6_sqrt = and(_cyc_B6_sqrt_T, sqrtOp_PB) node _cyc_B5_sqrt_T = and(cyc_B5, valid_PB) node cyc_B5_sqrt = and(_cyc_B5_sqrt_T, sqrtOp_PB) node _cyc_B4_sqrt_T = and(cyc_B4, valid_PB) node cyc_B4_sqrt = and(_cyc_B4_sqrt_T, sqrtOp_PB) node cyc_B3_sqrt = and(cyc_B3, sqrtOp_PB) node cyc_B2_sqrt = and(cyc_B2, sqrtOp_PB) node cyc_B1_sqrt = and(cyc_B1, sqrtOp_PB) node _T_4 = neq(cycleNum_C, UInt<1>(0h0)) node _T_5 = or(cyc_B1, _T_4) when _T_5 : node _cycleNum_C_T = mux(sqrtOp_PB, UInt<3>(0h6), UInt<3>(0h5)) node _cycleNum_C_T_1 = sub(cycleNum_C, UInt<1>(0h1)) node _cycleNum_C_T_2 = tail(_cycleNum_C_T_1, 1) node _cycleNum_C_T_3 = mux(cyc_B1, _cycleNum_C_T, _cycleNum_C_T_2) connect cycleNum_C, _cycleNum_C_T_3 node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>(0h6)) node cyc_C5 = eq(cycleNum_C, UInt<3>(0h5)) node cyc_C4 = eq(cycleNum_C, UInt<3>(0h4)) node cyc_C3 = eq(cycleNum_C, UInt<2>(0h3)) node cyc_C2 = eq(cycleNum_C, UInt<2>(0h2)) node cyc_C1 = eq(cycleNum_C, UInt<1>(0h1)) node _cyc_C5_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C5_div = and(cyc_C5, _cyc_C5_div_T) node _cyc_C4_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C4_div = and(cyc_C4, _cyc_C4_div_T) node _cyc_C3_div_T = eq(sqrtOp_PB, UInt<1>(0h0)) node cyc_C3_div = and(cyc_C3, _cyc_C3_div_T) node _cyc_C2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C2_div = and(cyc_C2, _cyc_C2_div_T) node _cyc_C1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_C1_div = and(cyc_C1, _cyc_C1_div_T) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) node _T_6 = neq(cycleNum_E, UInt<1>(0h0)) node _T_7 = or(cyc_C1, _T_6) when _T_7 : node _cycleNum_E_T = sub(cycleNum_E, UInt<1>(0h1)) node _cycleNum_E_T_1 = tail(_cycleNum_E_T, 1) node _cycleNum_E_T_2 = mux(cyc_C1, UInt<3>(0h4), _cycleNum_E_T_1) connect cycleNum_E, _cycleNum_E_T_2 node cyc_E4 = eq(cycleNum_E, UInt<3>(0h4)) node cyc_E3 = eq(cycleNum_E, UInt<2>(0h3)) node cyc_E2 = eq(cycleNum_E, UInt<2>(0h2)) node cyc_E1 = eq(cycleNum_E, UInt<1>(0h1)) node _cyc_E4_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E4_div = and(cyc_E4, _cyc_E4_div_T) node _cyc_E3_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E3_div = and(cyc_E3, _cyc_E3_div_T) node _cyc_E2_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E2_div = and(cyc_E2, _cyc_E2_div_T) node _cyc_E1_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node cyc_E1_div = and(cyc_E1, _cyc_E1_div_T) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node _entering_PA_T = eq(ready_PB, UInt<1>(0h0)) node _entering_PA_T_1 = or(valid_PA, _entering_PA_T) node _entering_PA_T_2 = and(cyc_S, _entering_PA_T_1) node entering_PA = or(entering_PA_normalCase, _entering_PA_T_2) node _T_8 = or(entering_PA, leaving_PA) when _T_8 : connect valid_PA, entering_PA when entering_PA : connect sqrtOp_PA, io.sqrtOp connect majorExc_PA, majorExc_S connect isNaN_PA, isNaN_S connect isInf_PA, isInf_S connect isZero_PA, isZero_S connect sign_PA, sign_S when entering_PA_normalCase : node _sExp_PA_T = mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div) connect sExp_PA, _sExp_PA_T node _fractB_PA_T = bits(rawB_S.sig, 51, 0) connect fractB_PA, _fractB_PA_T connect roundingMode_PA, io.roundingMode when entering_PA_normalCase_div : node _fractA_PA_T = bits(rawA_S.sig, 51, 0) connect fractA_PA, _fractA_PA_T node _normalCase_PA_T = eq(isNaN_PA, UInt<1>(0h0)) node _normalCase_PA_T_1 = eq(isInf_PA, UInt<1>(0h0)) node _normalCase_PA_T_2 = and(_normalCase_PA_T, _normalCase_PA_T_1) node _normalCase_PA_T_3 = eq(isZero_PA, UInt<1>(0h0)) node normalCase_PA = and(_normalCase_PA_T_2, _normalCase_PA_T_3) node sigA_PA = cat(UInt<1>(0h1), fractA_PA) node sigB_PA = cat(UInt<1>(0h1), fractB_PA) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) node _leaving_PA_T = and(valid_PA, valid_leaving_PA) connect leaving_PA, _leaving_PA_T node _ready_PA_T = eq(valid_PA, UInt<1>(0h0)) node _ready_PA_T_1 = or(_ready_PA_T, valid_leaving_PA) connect ready_PA, _ready_PA_T_1 node _entering_PB_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PB_S_T_1 = and(cyc_S, _entering_PB_S_T) node _entering_PB_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PB_S_T_3 = and(_entering_PB_S_T_1, _entering_PB_S_T_2) node _entering_PB_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PB_S_T_5 = eq(ready_PC, UInt<1>(0h0)) node _entering_PB_S_T_6 = and(_entering_PB_S_T_4, _entering_PB_S_T_5) node _entering_PB_S_T_7 = or(leaving_PB, _entering_PB_S_T_6) node entering_PB_S = and(_entering_PB_S_T_3, _entering_PB_S_T_7) node _entering_PB_normalCase_T = and(valid_PA, normalCase_PA) node entering_PB_normalCase = and(_entering_PB_normalCase_T, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) node _T_9 = or(entering_PB, leaving_PB) when _T_9 : connect valid_PB, entering_PB when entering_PB : node _sqrtOp_PB_T = mux(valid_PA, sqrtOp_PA, io.sqrtOp) connect sqrtOp_PB, _sqrtOp_PB_T node _majorExc_PB_T = mux(valid_PA, majorExc_PA, majorExc_S) connect majorExc_PB, _majorExc_PB_T node _isNaN_PB_T = mux(valid_PA, isNaN_PA, isNaN_S) connect isNaN_PB, _isNaN_PB_T node _isInf_PB_T = mux(valid_PA, isInf_PA, isInf_S) connect isInf_PB, _isInf_PB_T node _isZero_PB_T = mux(valid_PA, isZero_PA, isZero_S) connect isZero_PB, _isZero_PB_T node _sign_PB_T = mux(valid_PA, sign_PA, sign_S) connect sign_PB, _sign_PB_T when entering_PB_normalCase : connect sExp_PB, sExp_PA node _bit0FractA_PB_T = bits(fractA_PA, 0, 0) connect bit0FractA_PB, _bit0FractA_PB_T connect fractB_PB, fractB_PA node _roundingMode_PB_T = mux(valid_PA, roundingMode_PA, io.roundingMode) connect roundingMode_PB, _roundingMode_PB_T node _normalCase_PB_T = eq(isNaN_PB, UInt<1>(0h0)) node _normalCase_PB_T_1 = eq(isInf_PB, UInt<1>(0h0)) node _normalCase_PB_T_2 = and(_normalCase_PB_T, _normalCase_PB_T_1) node _normalCase_PB_T_3 = eq(isZero_PB, UInt<1>(0h0)) node normalCase_PB = and(_normalCase_PB_T_2, _normalCase_PB_T_3) node valid_leaving_PB = mux(normalCase_PB, cyc_C3, ready_PC) node _leaving_PB_T = and(valid_PB, valid_leaving_PB) connect leaving_PB, _leaving_PB_T node _ready_PB_T = eq(valid_PB, UInt<1>(0h0)) node _ready_PB_T_1 = or(_ready_PB_T, valid_leaving_PB) connect ready_PB, _ready_PB_T_1 node _entering_PC_S_T = eq(normalCase_S, UInt<1>(0h0)) node _entering_PC_S_T_1 = and(cyc_S, _entering_PC_S_T) node _entering_PC_S_T_2 = eq(valid_PA, UInt<1>(0h0)) node _entering_PC_S_T_3 = and(_entering_PC_S_T_1, _entering_PC_S_T_2) node _entering_PC_S_T_4 = eq(valid_PB, UInt<1>(0h0)) node _entering_PC_S_T_5 = and(_entering_PC_S_T_3, _entering_PC_S_T_4) node entering_PC_S = and(_entering_PC_S_T_5, ready_PC) node _entering_PC_normalCase_T = and(valid_PB, normalCase_PB) node entering_PC_normalCase = and(_entering_PC_normalCase_T, cyc_C3) node entering_PC = or(entering_PC_S, leaving_PB) node _T_10 = or(entering_PC, leaving_PC) when _T_10 : connect valid_PC, entering_PC when entering_PC : node _sqrtOp_PC_T = mux(valid_PB, sqrtOp_PB, io.sqrtOp) connect sqrtOp_PC, _sqrtOp_PC_T node _majorExc_PC_T = mux(valid_PB, majorExc_PB, majorExc_S) connect majorExc_PC, _majorExc_PC_T node _isNaN_PC_T = mux(valid_PB, isNaN_PB, isNaN_S) connect isNaN_PC, _isNaN_PC_T node _isInf_PC_T = mux(valid_PB, isInf_PB, isInf_S) connect isInf_PC, _isInf_PC_T node _isZero_PC_T = mux(valid_PB, isZero_PB, isZero_S) connect isZero_PC, _isZero_PC_T node _sign_PC_T = mux(valid_PB, sign_PB, sign_S) connect sign_PC, _sign_PC_T when entering_PC_normalCase : connect sExp_PC, sExp_PB connect bit0FractA_PC, bit0FractA_PB connect fractB_PC, fractB_PB node _roundingMode_PC_T = mux(valid_PB, roundingMode_PB, io.roundingMode) connect roundingMode_PC, _roundingMode_PC_T node _normalCase_PC_T = eq(isNaN_PC, UInt<1>(0h0)) node _normalCase_PC_T_1 = eq(isInf_PC, UInt<1>(0h0)) node _normalCase_PC_T_2 = and(_normalCase_PC_T, _normalCase_PC_T_1) node _normalCase_PC_T_3 = eq(isZero_PC, UInt<1>(0h0)) node normalCase_PC = and(_normalCase_PC_T_2, _normalCase_PC_T_3) node sigB_PC = cat(UInt<1>(0h1), fractB_PC) node _valid_leaving_PC_T = eq(normalCase_PC, UInt<1>(0h0)) node valid_leaving_PC = or(_valid_leaving_PC_T, cyc_E1) node _leaving_PC_T = and(valid_PC, valid_leaving_PC) connect leaving_PC, _leaving_PC_T node _ready_PC_T = eq(valid_PC, UInt<1>(0h0)) node _ready_PC_T_1 = or(_ready_PC_T, valid_leaving_PC) connect ready_PC, _ready_PC_T_1 node _io_inReady_div_T = eq(cyc_B7_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_1 = and(ready_PA, _io_inReady_div_T) node _io_inReady_div_T_2 = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_3 = and(_io_inReady_div_T_1, _io_inReady_div_T_2) node _io_inReady_div_T_4 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_5 = and(_io_inReady_div_T_3, _io_inReady_div_T_4) node _io_inReady_div_T_6 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_7 = and(_io_inReady_div_T_5, _io_inReady_div_T_6) node _io_inReady_div_T_8 = eq(cyc_B3, UInt<1>(0h0)) node _io_inReady_div_T_9 = and(_io_inReady_div_T_7, _io_inReady_div_T_8) node _io_inReady_div_T_10 = eq(cyc_B2, UInt<1>(0h0)) node _io_inReady_div_T_11 = and(_io_inReady_div_T_9, _io_inReady_div_T_10) node _io_inReady_div_T_12 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_div_T_13 = and(_io_inReady_div_T_11, _io_inReady_div_T_12) node _io_inReady_div_T_14 = eq(cyc_C5, UInt<1>(0h0)) node _io_inReady_div_T_15 = and(_io_inReady_div_T_13, _io_inReady_div_T_14) node _io_inReady_div_T_16 = eq(cyc_C4, UInt<1>(0h0)) node _io_inReady_div_T_17 = and(_io_inReady_div_T_15, _io_inReady_div_T_16) connect io.inReady_div, _io_inReady_div_T_17 node _io_inReady_sqrt_T = eq(cyc_B6_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_1 = and(ready_PA, _io_inReady_sqrt_T) node _io_inReady_sqrt_T_2 = eq(cyc_B5_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_3 = and(_io_inReady_sqrt_T_1, _io_inReady_sqrt_T_2) node _io_inReady_sqrt_T_4 = eq(cyc_B4_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_5 = and(_io_inReady_sqrt_T_3, _io_inReady_sqrt_T_4) node _io_inReady_sqrt_T_6 = eq(cyc_B2_div, UInt<1>(0h0)) node _io_inReady_sqrt_T_7 = and(_io_inReady_sqrt_T_5, _io_inReady_sqrt_T_6) node _io_inReady_sqrt_T_8 = eq(cyc_B1_sqrt, UInt<1>(0h0)) node _io_inReady_sqrt_T_9 = and(_io_inReady_sqrt_T_7, _io_inReady_sqrt_T_8) connect io.inReady_sqrt, _io_inReady_sqrt_T_9 node _zFractB_A4_div_T = bits(rawB_S.sig, 51, 0) node zFractB_A4_div = mux(entering_PA_normalCase_div, _zFractB_A4_div_T, UInt<1>(0h0)) node _zLinPiece_0_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_0_A4_div_T_1 = eq(_zLinPiece_0_A4_div_T, UInt<1>(0h0)) node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, _zLinPiece_0_A4_div_T_1) node _zLinPiece_1_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_1_A4_div_T_1 = eq(_zLinPiece_1_A4_div_T, UInt<1>(0h1)) node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, _zLinPiece_1_A4_div_T_1) node _zLinPiece_2_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_2_A4_div_T_1 = eq(_zLinPiece_2_A4_div_T, UInt<2>(0h2)) node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, _zLinPiece_2_A4_div_T_1) node _zLinPiece_3_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_3_A4_div_T_1 = eq(_zLinPiece_3_A4_div_T, UInt<2>(0h3)) node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, _zLinPiece_3_A4_div_T_1) node _zLinPiece_4_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_4_A4_div_T_1 = eq(_zLinPiece_4_A4_div_T, UInt<3>(0h4)) node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, _zLinPiece_4_A4_div_T_1) node _zLinPiece_5_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_5_A4_div_T_1 = eq(_zLinPiece_5_A4_div_T, UInt<3>(0h5)) node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, _zLinPiece_5_A4_div_T_1) node _zLinPiece_6_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_6_A4_div_T_1 = eq(_zLinPiece_6_A4_div_T, UInt<3>(0h6)) node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, _zLinPiece_6_A4_div_T_1) node _zLinPiece_7_A4_div_T = bits(rawB_S.sig, 51, 49) node _zLinPiece_7_A4_div_T_1 = eq(_zLinPiece_7_A4_div_T, UInt<3>(0h7)) node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, _zLinPiece_7_A4_div_T_1) node _zK1_A4_div_T = mux(zLinPiece_0_A4_div, UInt<9>(0h1c7), UInt<1>(0h0)) node _zK1_A4_div_T_1 = mux(zLinPiece_1_A4_div, UInt<9>(0h16c), UInt<1>(0h0)) node _zK1_A4_div_T_2 = or(_zK1_A4_div_T, _zK1_A4_div_T_1) node _zK1_A4_div_T_3 = mux(zLinPiece_2_A4_div, UInt<9>(0h12a), UInt<1>(0h0)) node _zK1_A4_div_T_4 = or(_zK1_A4_div_T_2, _zK1_A4_div_T_3) node _zK1_A4_div_T_5 = mux(zLinPiece_3_A4_div, UInt<8>(0hf8), UInt<1>(0h0)) node _zK1_A4_div_T_6 = or(_zK1_A4_div_T_4, _zK1_A4_div_T_5) node _zK1_A4_div_T_7 = mux(zLinPiece_4_A4_div, UInt<8>(0hd2), UInt<1>(0h0)) node _zK1_A4_div_T_8 = or(_zK1_A4_div_T_6, _zK1_A4_div_T_7) node _zK1_A4_div_T_9 = mux(zLinPiece_5_A4_div, UInt<8>(0hb4), UInt<1>(0h0)) node _zK1_A4_div_T_10 = or(_zK1_A4_div_T_8, _zK1_A4_div_T_9) node _zK1_A4_div_T_11 = mux(zLinPiece_6_A4_div, UInt<8>(0h9c), UInt<1>(0h0)) node _zK1_A4_div_T_12 = or(_zK1_A4_div_T_10, _zK1_A4_div_T_11) node _zK1_A4_div_T_13 = mux(zLinPiece_7_A4_div, UInt<8>(0h89), UInt<1>(0h0)) node zK1_A4_div = or(_zK1_A4_div_T_12, _zK1_A4_div_T_13) node _zComplFractK0_A4_div_T = not(UInt<12>(0hfe3)) node _zComplFractK0_A4_div_T_1 = mux(zLinPiece_0_A4_div, _zComplFractK0_A4_div_T, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_2 = not(UInt<12>(0hc5d)) node _zComplFractK0_A4_div_T_3 = mux(zLinPiece_1_A4_div, _zComplFractK0_A4_div_T_2, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_4 = or(_zComplFractK0_A4_div_T_1, _zComplFractK0_A4_div_T_3) node _zComplFractK0_A4_div_T_5 = not(UInt<12>(0h98a)) node _zComplFractK0_A4_div_T_6 = mux(zLinPiece_2_A4_div, _zComplFractK0_A4_div_T_5, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_7 = or(_zComplFractK0_A4_div_T_4, _zComplFractK0_A4_div_T_6) node _zComplFractK0_A4_div_T_8 = not(UInt<12>(0h739)) node _zComplFractK0_A4_div_T_9 = mux(zLinPiece_3_A4_div, _zComplFractK0_A4_div_T_8, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_10 = or(_zComplFractK0_A4_div_T_7, _zComplFractK0_A4_div_T_9) node _zComplFractK0_A4_div_T_11 = not(UInt<12>(0h54b)) node _zComplFractK0_A4_div_T_12 = mux(zLinPiece_4_A4_div, _zComplFractK0_A4_div_T_11, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_13 = or(_zComplFractK0_A4_div_T_10, _zComplFractK0_A4_div_T_12) node _zComplFractK0_A4_div_T_14 = not(UInt<12>(0h3a9)) node _zComplFractK0_A4_div_T_15 = mux(zLinPiece_5_A4_div, _zComplFractK0_A4_div_T_14, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_16 = or(_zComplFractK0_A4_div_T_13, _zComplFractK0_A4_div_T_15) node _zComplFractK0_A4_div_T_17 = not(UInt<12>(0h242)) node _zComplFractK0_A4_div_T_18 = mux(zLinPiece_6_A4_div, _zComplFractK0_A4_div_T_17, UInt<1>(0h0)) node _zComplFractK0_A4_div_T_19 = or(_zComplFractK0_A4_div_T_16, _zComplFractK0_A4_div_T_18) node _zComplFractK0_A4_div_T_20 = not(UInt<12>(0h10b)) node _zComplFractK0_A4_div_T_21 = mux(zLinPiece_7_A4_div, _zComplFractK0_A4_div_T_20, UInt<1>(0h0)) node zComplFractK0_A4_div = or(_zComplFractK0_A4_div_T_19, _zComplFractK0_A4_div_T_21) node _zFractB_A7_sqrt_T = bits(rawB_S.sig, 51, 0) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, _zFractB_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_0_A7_sqrt_T_1 = eq(_zQuadPiece_0_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_0_A7_sqrt_T_1) node _zQuadPiece_0_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_0_A7_sqrt_T_4 = eq(_zQuadPiece_0_A7_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A7_sqrt = and(_zQuadPiece_0_A7_sqrt_T_2, _zQuadPiece_0_A7_sqrt_T_4) node _zQuadPiece_1_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_1_A7_sqrt_T_1 = eq(_zQuadPiece_1_A7_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A7_sqrt_T_2 = and(entering_PA_normalCase_sqrt, _zQuadPiece_1_A7_sqrt_T_1) node _zQuadPiece_1_A7_sqrt_T_3 = bits(rawB_S.sig, 51, 51) node zQuadPiece_1_A7_sqrt = and(_zQuadPiece_1_A7_sqrt_T_2, _zQuadPiece_1_A7_sqrt_T_3) node _zQuadPiece_2_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_2_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_2_A7_sqrt_T) node _zQuadPiece_2_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node _zQuadPiece_2_A7_sqrt_T_3 = eq(_zQuadPiece_2_A7_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A7_sqrt = and(_zQuadPiece_2_A7_sqrt_T_1, _zQuadPiece_2_A7_sqrt_T_3) node _zQuadPiece_3_A7_sqrt_T = bits(rawB_S.sExp, 0, 0) node _zQuadPiece_3_A7_sqrt_T_1 = and(entering_PA_normalCase_sqrt, _zQuadPiece_3_A7_sqrt_T) node _zQuadPiece_3_A7_sqrt_T_2 = bits(rawB_S.sig, 51, 51) node zQuadPiece_3_A7_sqrt = and(_zQuadPiece_3_A7_sqrt_T_1, _zQuadPiece_3_A7_sqrt_T_2) node _zK2_A7_sqrt_T = mux(zQuadPiece_0_A7_sqrt, UInt<9>(0h1c8), UInt<1>(0h0)) node _zK2_A7_sqrt_T_1 = mux(zQuadPiece_1_A7_sqrt, UInt<8>(0hc1), UInt<1>(0h0)) node _zK2_A7_sqrt_T_2 = or(_zK2_A7_sqrt_T, _zK2_A7_sqrt_T_1) node _zK2_A7_sqrt_T_3 = mux(zQuadPiece_2_A7_sqrt, UInt<9>(0h143), UInt<1>(0h0)) node _zK2_A7_sqrt_T_4 = or(_zK2_A7_sqrt_T_2, _zK2_A7_sqrt_T_3) node _zK2_A7_sqrt_T_5 = mux(zQuadPiece_3_A7_sqrt, UInt<8>(0h89), UInt<1>(0h0)) node zK2_A7_sqrt = or(_zK2_A7_sqrt_T_4, _zK2_A7_sqrt_T_5) node _zComplK1_A7_sqrt_T = not(UInt<10>(0h3d0)) node _zComplK1_A7_sqrt_T_1 = mux(zQuadPiece_0_A7_sqrt, _zComplK1_A7_sqrt_T, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_2 = not(UInt<10>(0h220)) node _zComplK1_A7_sqrt_T_3 = mux(zQuadPiece_1_A7_sqrt, _zComplK1_A7_sqrt_T_2, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_4 = or(_zComplK1_A7_sqrt_T_1, _zComplK1_A7_sqrt_T_3) node _zComplK1_A7_sqrt_T_5 = not(UInt<10>(0h2b2)) node _zComplK1_A7_sqrt_T_6 = mux(zQuadPiece_2_A7_sqrt, _zComplK1_A7_sqrt_T_5, UInt<1>(0h0)) node _zComplK1_A7_sqrt_T_7 = or(_zComplK1_A7_sqrt_T_4, _zComplK1_A7_sqrt_T_6) node _zComplK1_A7_sqrt_T_8 = not(UInt<10>(0h181)) node _zComplK1_A7_sqrt_T_9 = mux(zQuadPiece_3_A7_sqrt, _zComplK1_A7_sqrt_T_8, UInt<1>(0h0)) node zComplK1_A7_sqrt = or(_zComplK1_A7_sqrt_T_7, _zComplK1_A7_sqrt_T_9) node _zQuadPiece_0_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_0_A6_sqrt_T_1 = eq(_zQuadPiece_0_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_0_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_0_A6_sqrt_T_1) node _zQuadPiece_0_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node _zQuadPiece_0_A6_sqrt_T_4 = eq(_zQuadPiece_0_A6_sqrt_T_3, UInt<1>(0h0)) node zQuadPiece_0_A6_sqrt = and(_zQuadPiece_0_A6_sqrt_T_2, _zQuadPiece_0_A6_sqrt_T_4) node _zQuadPiece_1_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_1_A6_sqrt_T_1 = eq(_zQuadPiece_1_A6_sqrt_T, UInt<1>(0h0)) node _zQuadPiece_1_A6_sqrt_T_2 = and(cyc_A6_sqrt, _zQuadPiece_1_A6_sqrt_T_1) node _zQuadPiece_1_A6_sqrt_T_3 = bits(sigB_PA, 51, 51) node zQuadPiece_1_A6_sqrt = and(_zQuadPiece_1_A6_sqrt_T_2, _zQuadPiece_1_A6_sqrt_T_3) node _zQuadPiece_2_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_2_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_2_A6_sqrt_T) node _zQuadPiece_2_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node _zQuadPiece_2_A6_sqrt_T_3 = eq(_zQuadPiece_2_A6_sqrt_T_2, UInt<1>(0h0)) node zQuadPiece_2_A6_sqrt = and(_zQuadPiece_2_A6_sqrt_T_1, _zQuadPiece_2_A6_sqrt_T_3) node _zQuadPiece_3_A6_sqrt_T = bits(sExp_PA, 0, 0) node _zQuadPiece_3_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zQuadPiece_3_A6_sqrt_T) node _zQuadPiece_3_A6_sqrt_T_2 = bits(sigB_PA, 51, 51) node zQuadPiece_3_A6_sqrt = and(_zQuadPiece_3_A6_sqrt_T_1, _zQuadPiece_3_A6_sqrt_T_2) node _zComplFractK0_A6_sqrt_T = not(UInt<13>(0h1fe5)) node _zComplFractK0_A6_sqrt_T_1 = mux(zQuadPiece_0_A6_sqrt, _zComplFractK0_A6_sqrt_T, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_2 = not(UInt<13>(0h1435)) node _zComplFractK0_A6_sqrt_T_3 = mux(zQuadPiece_1_A6_sqrt, _zComplFractK0_A6_sqrt_T_2, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_4 = or(_zComplFractK0_A6_sqrt_T_1, _zComplFractK0_A6_sqrt_T_3) node _zComplFractK0_A6_sqrt_T_5 = not(UInt<13>(0hd2c)) node _zComplFractK0_A6_sqrt_T_6 = mux(zQuadPiece_2_A6_sqrt, _zComplFractK0_A6_sqrt_T_5, UInt<1>(0h0)) node _zComplFractK0_A6_sqrt_T_7 = or(_zComplFractK0_A6_sqrt_T_4, _zComplFractK0_A6_sqrt_T_6) node _zComplFractK0_A6_sqrt_T_8 = not(UInt<13>(0h4e8)) node _zComplFractK0_A6_sqrt_T_9 = mux(zQuadPiece_3_A6_sqrt, _zComplFractK0_A6_sqrt_T_8, UInt<1>(0h0)) node zComplFractK0_A6_sqrt = or(_zComplFractK0_A6_sqrt_T_7, _zComplFractK0_A6_sqrt_T_9) node _mulAdd9A_A_T = bits(zFractB_A4_div, 48, 40) node _mulAdd9A_A_T_1 = or(_mulAdd9A_A_T, zK2_A7_sqrt) node _mulAdd9A_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9A_A_T_3 = mux(_mulAdd9A_A_T_2, nextMulAdd9A_A, UInt<1>(0h0)) node mulAdd9A_A = or(_mulAdd9A_A_T_1, _mulAdd9A_A_T_3) node _mulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _mulAdd9B_A_T_1 = or(zK1_A4_div, _mulAdd9B_A_T) node _mulAdd9B_A_T_2 = eq(cyc_S, UInt<1>(0h0)) node _mulAdd9B_A_T_3 = mux(_mulAdd9B_A_T_2, nextMulAdd9B_A, UInt<1>(0h0)) node mulAdd9B_A = or(_mulAdd9B_A_T_1, _mulAdd9B_A_T_3) node _mulAdd9C_A_T = mux(entering_PA_normalCase_sqrt, UInt<10>(0h3ff), UInt<10>(0h0)) node _mulAdd9C_A_T_1 = cat(zComplK1_A7_sqrt, _mulAdd9C_A_T) node _mulAdd9C_A_T_2 = mux(cyc_A6_sqrt, UInt<6>(0h3f), UInt<6>(0h0)) node mulAdd9C_A_hi = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) node _mulAdd9C_A_T_3 = cat(mulAdd9C_A_hi, _mulAdd9C_A_T_2) node _mulAdd9C_A_T_4 = or(_mulAdd9C_A_T_1, _mulAdd9C_A_T_3) node _mulAdd9C_A_T_5 = mux(entering_PA_normalCase_div, UInt<8>(0hff), UInt<8>(0h0)) node mulAdd9C_A_hi_1 = cat(entering_PA_normalCase_div, zComplFractK0_A4_div) node _mulAdd9C_A_T_6 = cat(mulAdd9C_A_hi_1, _mulAdd9C_A_T_5) node _mulAdd9C_A_T_7 = or(_mulAdd9C_A_T_4, _mulAdd9C_A_T_6) node _mulAdd9C_A_T_8 = shl(fractR0_A, 10) node _mulAdd9C_A_T_9 = add(UInt<19>(0h40000), _mulAdd9C_A_T_8) node _mulAdd9C_A_T_10 = mux(cyc_A5_sqrt, _mulAdd9C_A_T_9, UInt<1>(0h0)) node _mulAdd9C_A_T_11 = or(_mulAdd9C_A_T_7, _mulAdd9C_A_T_10) node _mulAdd9C_A_T_12 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_13 = eq(_mulAdd9C_A_T_12, UInt<1>(0h0)) node _mulAdd9C_A_T_14 = and(cyc_A4_sqrt, _mulAdd9C_A_T_13) node _mulAdd9C_A_T_15 = mux(_mulAdd9C_A_T_14, UInt<11>(0h400), UInt<1>(0h0)) node _mulAdd9C_A_T_16 = or(_mulAdd9C_A_T_11, _mulAdd9C_A_T_15) node _mulAdd9C_A_T_17 = bits(hiSqrR0_A_sqrt, 9, 9) node _mulAdd9C_A_T_18 = and(cyc_A4_sqrt, _mulAdd9C_A_T_17) node _mulAdd9C_A_T_19 = or(_mulAdd9C_A_T_18, cyc_A3_div) node _mulAdd9C_A_T_20 = bits(sigB_PA, 46, 26) node _mulAdd9C_A_T_21 = add(_mulAdd9C_A_T_20, UInt<11>(0h400)) node _mulAdd9C_A_T_22 = tail(_mulAdd9C_A_T_21, 1) node _mulAdd9C_A_T_23 = mux(_mulAdd9C_A_T_19, _mulAdd9C_A_T_22, UInt<1>(0h0)) node _mulAdd9C_A_T_24 = or(_mulAdd9C_A_T_16, _mulAdd9C_A_T_23) node _mulAdd9C_A_T_25 = or(cyc_A3_sqrt, cyc_A2) node _mulAdd9C_A_T_26 = mux(_mulAdd9C_A_T_25, partNegSigma0_A, UInt<1>(0h0)) node _mulAdd9C_A_T_27 = or(_mulAdd9C_A_T_24, _mulAdd9C_A_T_26) node _mulAdd9C_A_T_28 = shl(fractR0_A, 16) node _mulAdd9C_A_T_29 = mux(cyc_A1_sqrt, _mulAdd9C_A_T_28, UInt<1>(0h0)) node _mulAdd9C_A_T_30 = or(_mulAdd9C_A_T_27, _mulAdd9C_A_T_29) node _mulAdd9C_A_T_31 = shl(fractR0_A, 15) node _mulAdd9C_A_T_32 = mux(cyc_A1_div, _mulAdd9C_A_T_31, UInt<1>(0h0)) node mulAdd9C_A = or(_mulAdd9C_A_T_30, _mulAdd9C_A_T_32) node _loMulAdd9Out_A_T = mul(mulAdd9A_A, mulAdd9B_A) node _loMulAdd9Out_A_T_1 = bits(mulAdd9C_A, 17, 0) node loMulAdd9Out_A = add(_loMulAdd9Out_A_T, _loMulAdd9Out_A_T_1) node _mulAdd9Out_A_T = bits(loMulAdd9Out_A, 18, 18) node _mulAdd9Out_A_T_1 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_2 = add(_mulAdd9Out_A_T_1, UInt<1>(0h1)) node _mulAdd9Out_A_T_3 = tail(_mulAdd9Out_A_T_2, 1) node _mulAdd9Out_A_T_4 = bits(mulAdd9C_A, 24, 18) node _mulAdd9Out_A_T_5 = mux(_mulAdd9Out_A_T, _mulAdd9Out_A_T_3, _mulAdd9Out_A_T_4) node _mulAdd9Out_A_T_6 = bits(loMulAdd9Out_A, 17, 0) node mulAdd9Out_A = cat(_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6) node _zFractR0_A6_sqrt_T = bits(mulAdd9Out_A, 19, 19) node _zFractR0_A6_sqrt_T_1 = and(cyc_A6_sqrt, _zFractR0_A6_sqrt_T) node _zFractR0_A6_sqrt_T_2 = shr(mulAdd9Out_A, 10) node _zFractR0_A6_sqrt_T_3 = not(_zFractR0_A6_sqrt_T_2) node zFractR0_A6_sqrt = mux(_zFractR0_A6_sqrt_T_1, _zFractR0_A6_sqrt_T_3, UInt<1>(0h0)) node _sqrR0_A5_sqrt_T = bits(sExp_PA, 0, 0) node _sqrR0_A5_sqrt_T_1 = shl(mulAdd9Out_A, 1) node sqrR0_A5_sqrt = mux(_sqrR0_A5_sqrt_T, _sqrR0_A5_sqrt_T_1, mulAdd9Out_A) node _zFractR0_A4_div_T = bits(mulAdd9Out_A, 20, 20) node _zFractR0_A4_div_T_1 = and(entering_PA_normalCase_div, _zFractR0_A4_div_T) node _zFractR0_A4_div_T_2 = shr(mulAdd9Out_A, 11) node _zFractR0_A4_div_T_3 = not(_zFractR0_A4_div_T_2) node zFractR0_A4_div = mux(_zFractR0_A4_div_T_1, _zFractR0_A4_div_T_3, UInt<1>(0h0)) node _zSigma0_A2_T = bits(mulAdd9Out_A, 11, 11) node _zSigma0_A2_T_1 = and(cyc_A2, _zSigma0_A2_T) node _zSigma0_A2_T_2 = shr(mulAdd9Out_A, 2) node _zSigma0_A2_T_3 = not(_zSigma0_A2_T_2) node zSigma0_A2 = mux(_zSigma0_A2_T_1, _zSigma0_A2_T_3, UInt<1>(0h0)) node _r1_A1_T = shr(mulAdd9Out_A, 10) node _r1_A1_T_1 = shr(mulAdd9Out_A, 9) node _r1_A1_T_2 = mux(sqrtOp_PA, _r1_A1_T, _r1_A1_T_1) node r1_A1 = or(UInt<16>(0h8000), _r1_A1_T_2) node _ER1_A1_sqrt_T = bits(sExp_PA, 0, 0) node _ER1_A1_sqrt_T_1 = shl(r1_A1, 1) node ER1_A1_sqrt = mux(_ER1_A1_sqrt_T, _ER1_A1_sqrt_T_1, r1_A1) node _T_11 = or(cyc_A6_sqrt, entering_PA_normalCase_div) when _T_11 : node _fractR0_A_T = or(zFractR0_A6_sqrt, zFractR0_A4_div) connect fractR0_A, _fractR0_A_T when cyc_A5_sqrt : node _hiSqrR0_A_sqrt_T = shr(sqrR0_A5_sqrt, 10) connect hiSqrR0_A_sqrt, _hiSqrR0_A_sqrt_T node _T_12 = or(cyc_A4_sqrt, cyc_A3) when _T_12 : node _partNegSigma0_A_T = shr(mulAdd9Out_A, 9) node _partNegSigma0_A_T_1 = mux(cyc_A4_sqrt, mulAdd9Out_A, _partNegSigma0_A_T) connect partNegSigma0_A, _partNegSigma0_A_T_1 node _T_13 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_14 = or(_T_13, cyc_A5_sqrt) node _T_15 = or(_T_14, cyc_A4) node _T_16 = or(_T_15, cyc_A3) node _T_17 = or(_T_16, cyc_A2) when _T_17 : node _nextMulAdd9A_A_T = not(mulAdd9Out_A) node _nextMulAdd9A_A_T_1 = shr(_nextMulAdd9A_A_T, 11) node _nextMulAdd9A_A_T_2 = mux(entering_PA_normalCase_sqrt, _nextMulAdd9A_A_T_1, UInt<1>(0h0)) node _nextMulAdd9A_A_T_3 = or(_nextMulAdd9A_A_T_2, zFractR0_A6_sqrt) node _nextMulAdd9A_A_T_4 = bits(sigB_PA, 43, 35) node _nextMulAdd9A_A_T_5 = mux(cyc_A4_sqrt, _nextMulAdd9A_A_T_4, UInt<1>(0h0)) node _nextMulAdd9A_A_T_6 = or(_nextMulAdd9A_A_T_3, _nextMulAdd9A_A_T_5) node _nextMulAdd9A_A_T_7 = bits(zFractB_A4_div, 43, 35) node _nextMulAdd9A_A_T_8 = or(_nextMulAdd9A_A_T_6, _nextMulAdd9A_A_T_7) node _nextMulAdd9A_A_T_9 = or(cyc_A5_sqrt, cyc_A3) node _nextMulAdd9A_A_T_10 = bits(sigB_PA, 52, 44) node _nextMulAdd9A_A_T_11 = mux(_nextMulAdd9A_A_T_9, _nextMulAdd9A_A_T_10, UInt<1>(0h0)) node _nextMulAdd9A_A_T_12 = or(_nextMulAdd9A_A_T_8, _nextMulAdd9A_A_T_11) node _nextMulAdd9A_A_T_13 = or(_nextMulAdd9A_A_T_12, zSigma0_A2) connect nextMulAdd9A_A, _nextMulAdd9A_A_T_13 node _T_18 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) node _T_19 = or(_T_18, cyc_A5_sqrt) node _T_20 = or(_T_19, cyc_A4) node _T_21 = or(_T_20, cyc_A2) when _T_21 : node _nextMulAdd9B_A_T = bits(zFractB_A7_sqrt, 50, 42) node _nextMulAdd9B_A_T_1 = or(_nextMulAdd9B_A_T, zFractR0_A6_sqrt) node _nextMulAdd9B_A_T_2 = bits(sqrR0_A5_sqrt, 9, 1) node _nextMulAdd9B_A_T_3 = mux(cyc_A5_sqrt, _nextMulAdd9B_A_T_2, UInt<1>(0h0)) node _nextMulAdd9B_A_T_4 = or(_nextMulAdd9B_A_T_1, _nextMulAdd9B_A_T_3) node _nextMulAdd9B_A_T_5 = or(_nextMulAdd9B_A_T_4, zFractR0_A4_div) node _nextMulAdd9B_A_T_6 = bits(hiSqrR0_A_sqrt, 8, 0) node _nextMulAdd9B_A_T_7 = mux(cyc_A4_sqrt, _nextMulAdd9B_A_T_6, UInt<1>(0h0)) node _nextMulAdd9B_A_T_8 = or(_nextMulAdd9B_A_T_5, _nextMulAdd9B_A_T_7) node _nextMulAdd9B_A_T_9 = bits(fractR0_A, 8, 1) node _nextMulAdd9B_A_T_10 = cat(UInt<1>(0h1), _nextMulAdd9B_A_T_9) node _nextMulAdd9B_A_T_11 = mux(cyc_A2, _nextMulAdd9B_A_T_10, UInt<1>(0h0)) node _nextMulAdd9B_A_T_12 = or(_nextMulAdd9B_A_T_8, _nextMulAdd9B_A_T_11) connect nextMulAdd9B_A, _nextMulAdd9B_A_T_12 when cyc_A1_sqrt : connect ER1_B_sqrt, ER1_A1_sqrt node _io_latchMulAddA_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddA_0_T_1 = or(_io_latchMulAddA_0_T, cyc_B6_div) node _io_latchMulAddA_0_T_2 = or(_io_latchMulAddA_0_T_1, cyc_B4) node _io_latchMulAddA_0_T_3 = or(_io_latchMulAddA_0_T_2, cyc_B3) node _io_latchMulAddA_0_T_4 = or(_io_latchMulAddA_0_T_3, cyc_C6_sqrt) node _io_latchMulAddA_0_T_5 = or(_io_latchMulAddA_0_T_4, cyc_C4) node _io_latchMulAddA_0_T_6 = or(_io_latchMulAddA_0_T_5, cyc_C1) connect io.latchMulAddA_0, _io_latchMulAddA_0_T_6 node _io_mulAddA_0_T = shl(ER1_A1_sqrt, 36) node _io_mulAddA_0_T_1 = mux(cyc_A1_sqrt, _io_mulAddA_0_T, UInt<1>(0h0)) node _io_mulAddA_0_T_2 = or(cyc_B7_sqrt, cyc_A1_div) node _io_mulAddA_0_T_3 = mux(_io_mulAddA_0_T_2, sigB_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_4 = or(_io_mulAddA_0_T_1, _io_mulAddA_0_T_3) node _io_mulAddA_0_T_5 = mux(cyc_B6_div, sigA_PA, UInt<1>(0h0)) node _io_mulAddA_0_T_6 = or(_io_mulAddA_0_T_4, _io_mulAddA_0_T_5) node _io_mulAddA_0_T_7 = bits(zSigma1_B4, 45, 12) node _io_mulAddA_0_T_8 = or(_io_mulAddA_0_T_6, _io_mulAddA_0_T_7) node _io_mulAddA_0_T_9 = or(cyc_B3, cyc_C6_sqrt) node _io_mulAddA_0_T_10 = bits(sigXNU_B3_CX, 57, 12) node _io_mulAddA_0_T_11 = mux(_io_mulAddA_0_T_9, _io_mulAddA_0_T_10, UInt<1>(0h0)) node _io_mulAddA_0_T_12 = or(_io_mulAddA_0_T_8, _io_mulAddA_0_T_11) node _io_mulAddA_0_T_13 = bits(sigXN_C, 57, 25) node _io_mulAddA_0_T_14 = shl(_io_mulAddA_0_T_13, 13) node _io_mulAddA_0_T_15 = mux(cyc_C4_div, _io_mulAddA_0_T_14, UInt<1>(0h0)) node _io_mulAddA_0_T_16 = or(_io_mulAddA_0_T_12, _io_mulAddA_0_T_15) node _io_mulAddA_0_T_17 = shl(u_C_sqrt, 15) node _io_mulAddA_0_T_18 = mux(cyc_C4_sqrt, _io_mulAddA_0_T_17, UInt<1>(0h0)) node _io_mulAddA_0_T_19 = or(_io_mulAddA_0_T_16, _io_mulAddA_0_T_18) node _io_mulAddA_0_T_20 = mux(cyc_C1_div, sigB_PC, UInt<1>(0h0)) node _io_mulAddA_0_T_21 = or(_io_mulAddA_0_T_19, _io_mulAddA_0_T_20) node _io_mulAddA_0_T_22 = or(_io_mulAddA_0_T_21, zComplSigT_C1_sqrt) connect io.mulAddA_0, _io_mulAddA_0_T_22 node _io_latchMulAddB_0_T = or(cyc_A1, cyc_B7_sqrt) node _io_latchMulAddB_0_T_1 = or(_io_latchMulAddB_0_T, cyc_B6_sqrt) node _io_latchMulAddB_0_T_2 = or(_io_latchMulAddB_0_T_1, cyc_B4) node _io_latchMulAddB_0_T_3 = or(_io_latchMulAddB_0_T_2, cyc_C6_sqrt) node _io_latchMulAddB_0_T_4 = or(_io_latchMulAddB_0_T_3, cyc_C4) node _io_latchMulAddB_0_T_5 = or(_io_latchMulAddB_0_T_4, cyc_C1) connect io.latchMulAddB_0, _io_latchMulAddB_0_T_5 node _io_mulAddB_0_T = shl(r1_A1, 36) node _io_mulAddB_0_T_1 = mux(cyc_A1, _io_mulAddB_0_T, UInt<1>(0h0)) node _io_mulAddB_0_T_2 = shl(ESqrR1_B_sqrt, 19) node _io_mulAddB_0_T_3 = mux(cyc_B7_sqrt, _io_mulAddB_0_T_2, UInt<1>(0h0)) node _io_mulAddB_0_T_4 = or(_io_mulAddB_0_T_1, _io_mulAddB_0_T_3) node _io_mulAddB_0_T_5 = shl(ER1_B_sqrt, 36) node _io_mulAddB_0_T_6 = mux(cyc_B6_sqrt, _io_mulAddB_0_T_5, UInt<1>(0h0)) node _io_mulAddB_0_T_7 = or(_io_mulAddB_0_T_4, _io_mulAddB_0_T_6) node _io_mulAddB_0_T_8 = or(_io_mulAddB_0_T_7, zSigma1_B4) node _io_mulAddB_0_T_9 = bits(sqrSigma1_C, 30, 1) node _io_mulAddB_0_T_10 = mux(cyc_C6_sqrt, _io_mulAddB_0_T_9, UInt<1>(0h0)) node _io_mulAddB_0_T_11 = or(_io_mulAddB_0_T_8, _io_mulAddB_0_T_10) node _io_mulAddB_0_T_12 = mux(cyc_C4, sqrSigma1_C, UInt<1>(0h0)) node _io_mulAddB_0_T_13 = or(_io_mulAddB_0_T_11, _io_mulAddB_0_T_12) node _io_mulAddB_0_T_14 = or(_io_mulAddB_0_T_13, zComplSigT_C1) connect io.mulAddB_0, _io_mulAddB_0_T_14 node _io_usingMulAdd_T = or(cyc_A4, cyc_A3_div) node _io_usingMulAdd_T_1 = or(_io_usingMulAdd_T, cyc_A1_div) node _io_usingMulAdd_T_2 = or(_io_usingMulAdd_T_1, cyc_B10_sqrt) node _io_usingMulAdd_T_3 = or(_io_usingMulAdd_T_2, cyc_B9_sqrt) node _io_usingMulAdd_T_4 = or(_io_usingMulAdd_T_3, cyc_B7_sqrt) node _io_usingMulAdd_T_5 = or(_io_usingMulAdd_T_4, cyc_B6) node _io_usingMulAdd_T_6 = or(_io_usingMulAdd_T_5, cyc_B5_sqrt) node _io_usingMulAdd_T_7 = or(_io_usingMulAdd_T_6, cyc_B3_sqrt) node _io_usingMulAdd_T_8 = or(_io_usingMulAdd_T_7, cyc_B2_div) node _io_usingMulAdd_T_9 = or(_io_usingMulAdd_T_8, cyc_B1_sqrt) node _io_usingMulAdd_T_10 = or(_io_usingMulAdd_T_9, cyc_C4) node _io_usingMulAdd_T_11 = or(cyc_A3, cyc_A2_div) node _io_usingMulAdd_T_12 = or(_io_usingMulAdd_T_11, cyc_B9_sqrt) node _io_usingMulAdd_T_13 = or(_io_usingMulAdd_T_12, cyc_B8_sqrt) node _io_usingMulAdd_T_14 = or(_io_usingMulAdd_T_13, cyc_B6) node _io_usingMulAdd_T_15 = or(_io_usingMulAdd_T_14, cyc_B5) node _io_usingMulAdd_T_16 = or(_io_usingMulAdd_T_15, cyc_B4_sqrt) node _io_usingMulAdd_T_17 = or(_io_usingMulAdd_T_16, cyc_B2_sqrt) node _io_usingMulAdd_T_18 = or(_io_usingMulAdd_T_17, cyc_B1_div) node _io_usingMulAdd_T_19 = or(_io_usingMulAdd_T_18, cyc_C6_sqrt) node _io_usingMulAdd_T_20 = or(_io_usingMulAdd_T_19, cyc_C3) node _io_usingMulAdd_T_21 = or(cyc_A2, cyc_A1_div) node _io_usingMulAdd_T_22 = or(_io_usingMulAdd_T_21, cyc_B8_sqrt) node _io_usingMulAdd_T_23 = or(_io_usingMulAdd_T_22, cyc_B7_sqrt) node _io_usingMulAdd_T_24 = or(_io_usingMulAdd_T_23, cyc_B5) node _io_usingMulAdd_T_25 = or(_io_usingMulAdd_T_24, cyc_B4) node _io_usingMulAdd_T_26 = or(_io_usingMulAdd_T_25, cyc_B3_sqrt) node _io_usingMulAdd_T_27 = or(_io_usingMulAdd_T_26, cyc_B1_sqrt) node _io_usingMulAdd_T_28 = or(_io_usingMulAdd_T_27, cyc_C5) node _io_usingMulAdd_T_29 = or(_io_usingMulAdd_T_28, cyc_C2) node _io_usingMulAdd_T_30 = or(io.latchMulAddA_0, cyc_B6) node _io_usingMulAdd_T_31 = or(_io_usingMulAdd_T_30, cyc_B2_sqrt) node io_usingMulAdd_lo = cat(_io_usingMulAdd_T_29, _io_usingMulAdd_T_31) node io_usingMulAdd_hi = cat(_io_usingMulAdd_T_10, _io_usingMulAdd_T_20) node _io_usingMulAdd_T_32 = cat(io_usingMulAdd_hi, io_usingMulAdd_lo) connect io.usingMulAdd, _io_usingMulAdd_T_32 node _io_mulAddC_2_T = shl(sigX1_B, 47) node _io_mulAddC_2_T_1 = mux(cyc_B1, _io_mulAddC_2_T, UInt<1>(0h0)) node _io_mulAddC_2_T_2 = shl(sigX1_B, 46) node _io_mulAddC_2_T_3 = mux(cyc_C6_sqrt, _io_mulAddC_2_T_2, UInt<1>(0h0)) node _io_mulAddC_2_T_4 = or(_io_mulAddC_2_T_1, _io_mulAddC_2_T_3) node _io_mulAddC_2_T_5 = or(cyc_C4_sqrt, cyc_C2) node _io_mulAddC_2_T_6 = shl(sigXN_C, 47) node _io_mulAddC_2_T_7 = mux(_io_mulAddC_2_T_5, _io_mulAddC_2_T_6, UInt<1>(0h0)) node _io_mulAddC_2_T_8 = or(_io_mulAddC_2_T_4, _io_mulAddC_2_T_7) node _io_mulAddC_2_T_9 = eq(E_E_div, UInt<1>(0h0)) node _io_mulAddC_2_T_10 = and(cyc_E3_div, _io_mulAddC_2_T_9) node _io_mulAddC_2_T_11 = shl(bit0FractA_PC, 53) node _io_mulAddC_2_T_12 = mux(_io_mulAddC_2_T_10, _io_mulAddC_2_T_11, UInt<1>(0h0)) node _io_mulAddC_2_T_13 = or(_io_mulAddC_2_T_8, _io_mulAddC_2_T_12) node _io_mulAddC_2_T_14 = bits(sExp_PC, 0, 0) node _io_mulAddC_2_T_15 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_16 = shl(_io_mulAddC_2_T_15, 1) node _io_mulAddC_2_T_17 = bits(sigB_PC, 1, 1) node _io_mulAddC_2_T_18 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_19 = xor(_io_mulAddC_2_T_17, _io_mulAddC_2_T_18) node _io_mulAddC_2_T_20 = bits(sigB_PC, 0, 0) node _io_mulAddC_2_T_21 = cat(_io_mulAddC_2_T_19, _io_mulAddC_2_T_20) node _io_mulAddC_2_T_22 = mux(_io_mulAddC_2_T_14, _io_mulAddC_2_T_16, _io_mulAddC_2_T_21) node _io_mulAddC_2_T_23 = bits(sigT_E, 0, 0) node _io_mulAddC_2_T_24 = not(_io_mulAddC_2_T_23) node _io_mulAddC_2_T_25 = shl(_io_mulAddC_2_T_24, 1) node _io_mulAddC_2_T_26 = xor(_io_mulAddC_2_T_22, _io_mulAddC_2_T_25) node _io_mulAddC_2_T_27 = shl(_io_mulAddC_2_T_26, 54) node _io_mulAddC_2_T_28 = mux(cyc_E3_sqrt, _io_mulAddC_2_T_27, UInt<1>(0h0)) node _io_mulAddC_2_T_29 = or(_io_mulAddC_2_T_13, _io_mulAddC_2_T_28) connect io.mulAddC_2, _io_mulAddC_2_T_29 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) node _zSigma1_B4_T = bits(io.mulAddResult_3, 90, 45) node _zSigma1_B4_T_1 = not(_zSigma1_B4_T) node _zSigma1_B4_T_2 = mux(cyc_B4, _zSigma1_B4_T_1, UInt<1>(0h0)) connect zSigma1_B4, _zSigma1_B4_T_2 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) node _sigXNU_B3_CX_T = bits(io.mulAddResult_3, 104, 47) connect sigXNU_B3_CX, _sigXNU_B3_CX_T node _E_C1_div_T = bits(io.mulAddResult_3, 104, 104) node E_C1_div = eq(_E_C1_div_T, UInt<1>(0h0)) node _zComplSigT_C1_T = eq(E_C1_div, UInt<1>(0h0)) node _zComplSigT_C1_T_1 = and(cyc_C1_div, _zComplSigT_C1_T) node _zComplSigT_C1_T_2 = or(_zComplSigT_C1_T_1, cyc_C1_sqrt) node _zComplSigT_C1_T_3 = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_T_4 = not(_zComplSigT_C1_T_3) node _zComplSigT_C1_T_5 = mux(_zComplSigT_C1_T_2, _zComplSigT_C1_T_4, UInt<1>(0h0)) node _zComplSigT_C1_T_6 = and(cyc_C1_div, E_C1_div) node _zComplSigT_C1_T_7 = bits(io.mulAddResult_3, 102, 50) node _zComplSigT_C1_T_8 = not(_zComplSigT_C1_T_7) node _zComplSigT_C1_T_9 = mux(_zComplSigT_C1_T_6, _zComplSigT_C1_T_8, UInt<1>(0h0)) node _zComplSigT_C1_T_10 = or(_zComplSigT_C1_T_5, _zComplSigT_C1_T_9) connect zComplSigT_C1, _zComplSigT_C1_T_10 node _zComplSigT_C1_sqrt_T = bits(io.mulAddResult_3, 104, 51) node _zComplSigT_C1_sqrt_T_1 = not(_zComplSigT_C1_sqrt_T) node _zComplSigT_C1_sqrt_T_2 = mux(cyc_C1_sqrt, _zComplSigT_C1_sqrt_T_1, UInt<1>(0h0)) connect zComplSigT_C1_sqrt, _zComplSigT_C1_sqrt_T_2 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : connect ESqrR1_B_sqrt, ESqrR1_B8_sqrt when cyc_B3 : connect sigX1_B, sigXNU_B3_CX when cyc_B1 : connect sqrSigma1_C, sqrSigma1_B1 node _T_22 = or(cyc_C6_sqrt, cyc_C5_div) node _T_23 = or(_T_22, cyc_C3_sqrt) when _T_23 : connect sigXN_C, sigXNU_B3_CX when cyc_C5_sqrt : node _u_C_sqrt_T = bits(sigXNU_B3_CX, 56, 26) connect u_C_sqrt, _u_C_sqrt_T when cyc_C1 : connect E_E_div, E_C1_div connect sigT_E, sigT_C1 when cyc_E2 : node _isNegRemT_E_T = bits(remT_E2, 55, 55) node _isNegRemT_E_T_1 = bits(remT_E2, 53, 53) node _isNegRemT_E_T_2 = mux(sqrtOp_PC, _isNegRemT_E_T, _isNegRemT_E_T_1) connect isNegRemT_E, _isNegRemT_E_T_2 node _isZeroRemT_E_T = bits(remT_E2, 53, 0) node _isZeroRemT_E_T_1 = eq(_isZeroRemT_E_T, UInt<1>(0h0)) node _isZeroRemT_E_T_2 = eq(sqrtOp_PC, UInt<1>(0h0)) node _isZeroRemT_E_T_3 = bits(remT_E2, 55, 54) node _isZeroRemT_E_T_4 = eq(_isZeroRemT_E_T_3, UInt<1>(0h0)) node _isZeroRemT_E_T_5 = or(_isZeroRemT_E_T_2, _isZeroRemT_E_T_4) node _isZeroRemT_E_T_6 = and(_isZeroRemT_E_T_1, _isZeroRemT_E_T_5) connect isZeroRemT_E, _isZeroRemT_E_T_6 node _trueLtX_E1_T = eq(isNegRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _trueLtX_E1_T_2 = and(_trueLtX_E1_T, _trueLtX_E1_T_1) node trueLtX_E1 = mux(sqrtOp_PC, _trueLtX_E1_T_2, isNegRemT_E) node _sExpP1_PC_T = add(sExp_PC, asSInt(UInt<2>(0h1))) node _sExpP1_PC_T_1 = tail(_sExpP1_PC_T, 1) node sExpP1_PC = asSInt(_sExpP1_PC_T_1) node sigTP1_E = add(sigT_E, UInt<1>(0h1)) node _io_rawOutValid_div_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOutValid_div_T_1 = and(leaving_PC, _io_rawOutValid_div_T) connect io.rawOutValid_div, _io_rawOutValid_div_T_1 node _io_rawOutValid_sqrt_T = and(leaving_PC, sqrtOp_PC) connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T connect io.roundingModeOut, roundingMode_PC node _io_invalidExc_T = and(majorExc_PC, isNaN_PC) connect io.invalidExc, _io_invalidExc_T node _io_infiniteExc_T = eq(isNaN_PC, UInt<1>(0h0)) node _io_infiniteExc_T_1 = and(majorExc_PC, _io_infiniteExc_T) connect io.infiniteExc, _io_infiniteExc_T_1 connect io.rawOut.isNaN, isNaN_PC connect io.rawOut.isInf, isInf_PC connect io.rawOut.isZero, isZero_PC connect io.rawOut.sign, sign_PC node _io_rawOut_sExp_T = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_1 = and(_io_rawOut_sExp_T, E_E_div) node _io_rawOut_sExp_T_2 = mux(_io_rawOut_sExp_T_1, sExp_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_3 = eq(sqrtOp_PC, UInt<1>(0h0)) node _io_rawOut_sExp_T_4 = eq(E_E_div, UInt<1>(0h0)) node _io_rawOut_sExp_T_5 = and(_io_rawOut_sExp_T_3, _io_rawOut_sExp_T_4) node _io_rawOut_sExp_T_6 = mux(_io_rawOut_sExp_T_5, sExpP1_PC, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_7 = or(_io_rawOut_sExp_T_2, _io_rawOut_sExp_T_6) node _io_rawOut_sExp_T_8 = asSInt(_io_rawOut_sExp_T_7) node _io_rawOut_sExp_T_9 = shr(sExp_PC, 1) node _io_rawOut_sExp_T_10 = add(_io_rawOut_sExp_T_9, asSInt(UInt<12>(0h400))) node _io_rawOut_sExp_T_11 = mux(sqrtOp_PC, _io_rawOut_sExp_T_10, asSInt(UInt<1>(0h0))) node _io_rawOut_sExp_T_12 = or(_io_rawOut_sExp_T_8, _io_rawOut_sExp_T_11) node _io_rawOut_sExp_T_13 = asSInt(_io_rawOut_sExp_T_12) connect io.rawOut.sExp, _io_rawOut_sExp_T_13 node _io_rawOut_sig_T = mux(trueLtX_E1, sigT_E, sigTP1_E) node _io_rawOut_sig_T_1 = eq(isZeroRemT_E, UInt<1>(0h0)) node _io_rawOut_sig_T_2 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_1) connect io.rawOut.sig, _io_rawOut_sig_T_2

module DivSqrtRecF64ToRaw_mulAddZ31( // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input clock, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] input reset, // @[DivSqrtRecF64_mulAddZ31.scala:51:7] output io_inReady_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_inReady_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_inValid, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input io_sqrtOp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_a, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [64:0] io_b, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [2:0] io_roundingMode, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [3:0] io_usingMulAdd, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddA_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_latchMulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [53:0] io_mulAddB_0, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [104:0] io_mulAddC_2, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] input [104:0] io_mulAddResult_3, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_div, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOutValid_sqrt, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_invalidExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_infiniteExc, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isNaN, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isInf, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_isZero, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output io_rawOut_sign, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [12:0] io_rawOut_sExp, // @[DivSqrtRecF64_mulAddZ31.scala:53:16] output [55:0] io_rawOut_sig // @[DivSqrtRecF64_mulAddZ31.scala:53:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddResult_3_0 = io_mulAddResult_3; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [11:0] _zComplFractK0_A4_div_T = 12'h1C; // @[DivSqrtRecF64_mulAddZ31.scala:460:33] wire [11:0] _zComplFractK0_A4_div_T_2 = 12'h3A2; // @[DivSqrtRecF64_mulAddZ31.scala:461:33] wire [11:0] _zComplFractK0_A4_div_T_5 = 12'h675; // @[DivSqrtRecF64_mulAddZ31.scala:462:33] wire [11:0] _zComplFractK0_A4_div_T_8 = 12'h8C6; // @[DivSqrtRecF64_mulAddZ31.scala:463:33] wire [11:0] _zComplFractK0_A4_div_T_11 = 12'hAB4; // @[DivSqrtRecF64_mulAddZ31.scala:464:33] wire [11:0] _zComplFractK0_A4_div_T_14 = 12'hC56; // @[DivSqrtRecF64_mulAddZ31.scala:465:33] wire [11:0] _zComplFractK0_A4_div_T_17 = 12'hDBD; // @[DivSqrtRecF64_mulAddZ31.scala:466:33] wire [11:0] _zComplFractK0_A4_div_T_20 = 12'hEF4; // @[DivSqrtRecF64_mulAddZ31.scala:467:33] wire [9:0] _zComplK1_A7_sqrt_T = 10'h2F; // @[DivSqrtRecF64_mulAddZ31.scala:484:35] wire [9:0] _zComplK1_A7_sqrt_T_2 = 10'h1DF; // @[DivSqrtRecF64_mulAddZ31.scala:485:35] wire [9:0] _zComplK1_A7_sqrt_T_5 = 10'h14D; // @[DivSqrtRecF64_mulAddZ31.scala:486:35] wire [9:0] _zComplK1_A7_sqrt_T_8 = 10'h27E; // @[DivSqrtRecF64_mulAddZ31.scala:487:35] wire [12:0] _zComplFractK0_A6_sqrt_T = 13'h1A; // @[DivSqrtRecF64_mulAddZ31.scala:494:35] wire [12:0] _zComplFractK0_A6_sqrt_T_2 = 13'hBCA; // @[DivSqrtRecF64_mulAddZ31.scala:495:35] wire [12:0] _zComplFractK0_A6_sqrt_T_5 = 13'h12D3; // @[DivSqrtRecF64_mulAddZ31.scala:496:35] wire _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:432:22] wire [12:0] _zComplFractK0_A6_sqrt_T_8 = 13'h1B17; // @[DivSqrtRecF64_mulAddZ31.scala:497:35] wire _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:435:26] wire [3:0] _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] wire _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:578:35] wire [53:0] _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:588:63] wire _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:592:35] wire [53:0] _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:599:51] wire [104:0] _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:622:62] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:699:39] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:700:39] wire _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:702:40] wire _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:703:40] wire [12:0] _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] wire [55:0] _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:712:56] wire io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [3:0] io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [53:0] io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [104:0] io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] wire io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] reg [2:0] cycleNum_A; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] reg [3:0] cycleNum_B; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] reg [2:0] cycleNum_C; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] reg [2:0] cycleNum_E; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] reg valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] reg sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30] reg majorExc_PA; // @[DivSqrtRecF64_mulAddZ31.scala:93:30] reg isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30] reg isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30] reg isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30] reg sign_PA; // @[DivSqrtRecF64_mulAddZ31.scala:98:30] reg [12:0] sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30] reg [51:0] fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30] reg [51:0] fractA_PA; // @[DivSqrtRecF64_mulAddZ31.scala:101:30] reg [2:0] roundingMode_PA; // @[DivSqrtRecF64_mulAddZ31.scala:102:30] reg valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] reg sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30] reg majorExc_PB; // @[DivSqrtRecF64_mulAddZ31.scala:106:30] reg isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30] reg isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30] reg isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30] reg sign_PB; // @[DivSqrtRecF64_mulAddZ31.scala:111:30] reg [12:0] sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30] reg bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30] reg [51:0] fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30] reg [2:0] roundingMode_PB; // @[DivSqrtRecF64_mulAddZ31.scala:115:30] reg valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] reg sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30] reg majorExc_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30] reg isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30] assign io_rawOut_isNaN_0 = isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :121:30] reg isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30] assign io_rawOut_isInf_0 = isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :122:30] reg isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30] assign io_rawOut_isZero_0 = isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :123:30] reg sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:124:30] assign io_rawOut_sign_0 = sign_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :124:30] reg [12:0] sExp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:125:30] reg bit0FractA_PC; // @[DivSqrtRecF64_mulAddZ31.scala:126:30] reg [51:0] fractB_PC; // @[DivSqrtRecF64_mulAddZ31.scala:127:30] reg [2:0] roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:128:30] assign io_roundingModeOut_0 = roundingMode_PC; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :128:30] reg [8:0] fractR0_A; // @[DivSqrtRecF64_mulAddZ31.scala:130:30] reg [9:0] hiSqrR0_A_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:132:30] reg [20:0] partNegSigma0_A; // @[DivSqrtRecF64_mulAddZ31.scala:133:30] reg [8:0] nextMulAdd9A_A; // @[DivSqrtRecF64_mulAddZ31.scala:134:30] reg [8:0] nextMulAdd9B_A; // @[DivSqrtRecF64_mulAddZ31.scala:135:30] reg [16:0] ER1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30] reg [31:0] ESqrR1_B_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30] reg [57:0] sigX1_B; // @[DivSqrtRecF64_mulAddZ31.scala:139:30] reg [32:0] sqrSigma1_C; // @[DivSqrtRecF64_mulAddZ31.scala:140:30] reg [57:0] sigXN_C; // @[DivSqrtRecF64_mulAddZ31.scala:141:30] reg [30:0] u_C_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:142:30] reg E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30] reg [53:0] sigT_E; // @[DivSqrtRecF64_mulAddZ31.scala:144:30] reg isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30] reg isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30] wire _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:355:28] wire ready_PA; // @[DivSqrtRecF64_mulAddZ31.scala:150:26] wire _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:390:28] wire ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26] wire _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:423:28] wire ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26] wire _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:354:28] wire leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26] wire _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:389:28] wire leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26] wire _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:422:28] wire leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:155:26] wire [45:0] _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:633:22] wire [45:0] zSigma1_B4; // @[DivSqrtRecF64_mulAddZ31.scala:157:34] wire [57:0] _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:635:38] wire [57:0] sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:158:34] wire [53:0] _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:644:12] wire [53:0] zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34] wire [53:0] _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:641:11] wire [53:0] zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34] wire _cyc_S_div_T = io_inReady_div_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:38] wire _cyc_S_div_T_1 = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55] wire cyc_S_div = _cyc_S_div_T & _cyc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:164:{38,52,55}] wire _cyc_S_sqrt_T = io_inReady_sqrt_0 & io_inValid_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:38] wire cyc_S_sqrt = _cyc_S_sqrt_T & io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :165:{38,52}] wire cyc_S = cyc_S_div | cyc_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :165:52, :166:27] wire [11:0] rawA_S_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_S_isZero_T = rawA_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_S_isZero = _rawA_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawA_S_isZero_0 = rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_S_isSpecial_T = rawA_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_S_isSpecial = &_rawA_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_S_out_isNaN_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_S_out_isInf_T = rawA_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_S_out_isNaN_T_1 = rawA_S_isSpecial & _rawA_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_S_isNaN = _rawA_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_S_out_isInf_T_1 = ~_rawA_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_S_out_isInf_T_2 = rawA_S_isSpecial & _rawA_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_S_isInf = _rawA_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_S_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_S_sign = _rawA_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_S_out_sExp_T = {1'h0, rawA_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_S_sExp = _rawA_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_S_out_sig_T = ~rawA_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_S_out_sig_T_1 = {1'h0, _rawA_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_S_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_S_out_sig_T_3 = {_rawA_S_out_sig_T_1, _rawA_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_S_sig = _rawA_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_S_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_S_isZero_T = rawB_S_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_S_isZero = _rawB_S_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawB_S_isZero_0 = rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_S_isSpecial_T = rawB_S_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_S_isSpecial = &_rawB_S_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_S_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_S_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_S_out_isNaN_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_S_out_isInf_T = rawB_S_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_S_out_isNaN_T_1 = rawB_S_isSpecial & _rawB_S_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_S_isNaN = _rawB_S_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_S_out_isInf_T_1 = ~_rawB_S_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_S_out_isInf_T_2 = rawB_S_isSpecial & _rawB_S_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_S_isInf = _rawB_S_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_S_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_S_sign = _rawB_S_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_S_out_sExp_T = {1'h0, rawB_S_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_S_sExp = _rawB_S_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_S_out_sig_T = ~rawB_S_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_S_out_sig_T_1 = {1'h0, _rawB_S_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_S_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_S_out_sig_T_3 = {_rawB_S_out_sig_T_1, _rawB_S_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_S_sig = _rawB_S_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _notSigNaNIn_invalidExc_S_div_T = rawA_S_isZero_0 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_div_T_1 = rawA_S_isInf & rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:172:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:174:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_7 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T_3 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T_2 = rawB_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = rawB_S_isNaN & _majorExc_S_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_4 = rawA_S_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = rawA_S_isNaN & _majorExc_S_T_5; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = rawB_S_isNaN & _majorExc_S_T_8; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :178:{38,66}] wire _majorExc_S_T_12 = ~rawA_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_13 = ~rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:180:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:178:66, :179:46, :180:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :176:12, :177:38, :179:46] wire _isNaN_S_T = rawB_S_isNaN | notSigNaNIn_invalidExc_S_sqrt; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_1 = rawA_S_isNaN | rawB_S_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:172:42, :185:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :183:12, :184:26, :185:42] wire _isInf_S_T = rawA_S_isInf | rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire isInf_S = io_sqrtOp_0 ? rawB_S_isInf : _isInf_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _isZero_S_T = rawA_S_isZero_0 | rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire isZero_S = io_sqrtOp_0 ? rawB_S_isZero_0 : _isZero_S_T; // @[rawFloatFromRecFN.scala:55:23] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :164:55, :189:19] wire _sign_S_T_1 = _sign_S_T & rawA_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire sign_S = _sign_S_T_1 ^ rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseA_S_T = rawA_S_isNaN | rawA_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseA_S = _specialCaseA_S_T | rawA_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _specialCaseB_S_T = rawB_S_isNaN | rawB_S_isInf; // @[rawFloatFromRecFN.scala:55:23] wire specialCaseB_S = _specialCaseB_S_T | rawB_S_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecF64_mulAddZ31.scala:191:55, :193:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:193:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseB_S; // @[DivSqrtRecF64_mulAddZ31.scala:192:55, :193:48, :194:29] wire _normalCase_S_sqrt_T_1 = ~rawB_S_sign; // @[rawFloatFromRecFN.scala:55:23] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:194:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :193:45, :194:46, :195:27] wire _sExpQuot_S_div_T = rawB_S_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_1 = rawB_S_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:198:{44,56}] wire [11:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:198:{36,41,44}] wire [11:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:198:{41,65}] wire [13:0] sExpQuot_S_div = {rawA_S_sExp[12], rawA_S_sExp} + {{2{_sExpQuot_S_div_T_4[11]}}, _sExpQuot_S_div_T_4}; // @[rawFloatFromRecFN.scala:55:23] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 14'shDFF; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :201:24] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[12:9]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :203:27] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:201:{13,24}, :203:27, :257:30] wire [8:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:198:21, :205:27] wire [12:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:201:13, :204:15, :205:27] wire [12:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:204:15, :206:11] wire entering_PA_normalCase_div = cyc_S_div & normalCase_S_div; // @[DivSqrtRecF64_mulAddZ31.scala:164:52, :193:45, :210:50] wire entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:165:52, :194:46, :211:50] wire entering_PA_normalCase = entering_PA_normalCase_div | entering_PA_normalCase_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :211:50, :213:36] wire [1:0] _cycleNum_A_T = {2{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :219:16] wire [2:0] _cycleNum_A_T_1 = entering_PA_normalCase_sqrt ? 3'h6 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :220:16] wire [2:0] _cycleNum_A_T_2 = {1'h0, _cycleNum_A_T} | _cycleNum_A_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:219:{16,69}, :220:16] wire _cycleNum_A_T_3 = ~entering_PA_normalCase; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :221:17] wire [3:0] _cycleNum_A_T_4 = {1'h0, cycleNum_A} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :221:57] wire [2:0] _cycleNum_A_T_5 = _cycleNum_A_T_4[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:221:57] wire [2:0] _cycleNum_A_T_6 = _cycleNum_A_T_3 ? _cycleNum_A_T_5 : 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:221:{16,17,57}] wire [2:0] _cycleNum_A_T_7 = _cycleNum_A_T_2 | _cycleNum_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:219:69, :220:69, :221:16] wire cyc_A6_sqrt = cycleNum_A == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :225:35] wire cyc_A5_sqrt = cycleNum_A == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :226:35] wire cyc_A4_sqrt = cycleNum_A == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :227:35] wire cyc_A4 = cyc_A4_sqrt | entering_PA_normalCase_div; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :227:35, :231:30] wire cyc_A3 = cycleNum_A == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :232:30] wire cyc_A2 = cycleNum_A == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :233:30] wire cyc_A1 = cycleNum_A == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :234:30] wire _cyc_A3_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32] wire cyc_A3_div = cyc_A3 & _cyc_A3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :236:{29,32}] wire _cyc_A2_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :237:32] wire cyc_A2_div = cyc_A2 & _cyc_A2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :237:{29,32}] wire _cyc_A1_div_T = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :238:32] wire cyc_A1_div = cyc_A1 & _cyc_A1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :238:{29,32}] wire cyc_A3_sqrt = cyc_A3 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :232:30, :240:30] wire cyc_A2_sqrt = cyc_A2 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :233:30, :241:30] wire cyc_A1_sqrt = cyc_A1 & sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :234:30, :242:30] wire [3:0] _cycleNum_B_T = sqrtOp_PA ? 4'hA : 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :247:20, :257:30] wire [4:0] _cycleNum_B_T_1 = {1'h0, cycleNum_B} - 5'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :248:28] wire [3:0] _cycleNum_B_T_2 = _cycleNum_B_T_1[3:0]; // @[DivSqrtRecF64_mulAddZ31.scala:248:28] wire [3:0] _cycleNum_B_T_3 = cyc_A1 ? _cycleNum_B_T : _cycleNum_B_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :246:16, :247:20, :248:28] wire cyc_B10_sqrt = cycleNum_B == 4'hA; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :252:36] wire cyc_B9_sqrt = cycleNum_B == 4'h9; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :253:36] wire cyc_B8_sqrt = cycleNum_B == 4'h8; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :254:36] wire cyc_B7_sqrt = cycleNum_B == 4'h7; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :255:36] wire cyc_B6 = cycleNum_B == 4'h6; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :257:30] wire cyc_B5 = cycleNum_B == 4'h5; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :258:30] wire cyc_B4 = cycleNum_B == 4'h4; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :259:30] wire cyc_B3 = cycleNum_B == 4'h3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :260:30] wire cyc_B2 = cycleNum_B == 4'h2; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :261:30] wire cyc_B1 = cycleNum_B == 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :262:30] wire _cyc_B6_div_T = cyc_B6 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :257:30, :264:29] wire _cyc_B6_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :264:44] wire cyc_B6_div = _cyc_B6_div_T & _cyc_B6_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:264:{29,41,44}] wire _cyc_B5_div_T = cyc_B5 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :258:30, :265:29] wire _cyc_B5_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :265:44] wire cyc_B5_div = _cyc_B5_div_T & _cyc_B5_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:265:{29,41,44}] wire _cyc_B4_div_T = cyc_B4 & valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :259:30, :266:29] wire _cyc_B4_div_T_1 = ~sqrtOp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :236:32, :266:44] wire cyc_B4_div = _cyc_B4_div_T & _cyc_B4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:266:{29,41,44}] wire _cyc_B3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32] wire cyc_B3_div = cyc_B3 & _cyc_B3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :267:{29,32}] wire _cyc_B2_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :268:32] wire cyc_B2_div = cyc_B2 & _cyc_B2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :268:{29,32}] wire _cyc_B1_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :269:32] wire cyc_B1_div = cyc_B1 & _cyc_B1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :269:{29,32}] wire _cyc_B6_sqrt_T = cyc_B6 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :257:30, :271:30] wire cyc_B6_sqrt = _cyc_B6_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :271:{30,42}] wire _cyc_B5_sqrt_T = cyc_B5 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :258:30, :272:30] wire cyc_B5_sqrt = _cyc_B5_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :272:{30,42}] wire _cyc_B4_sqrt_T = cyc_B4 & valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :259:30, :273:30] wire cyc_B4_sqrt = _cyc_B4_sqrt_T & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :273:{30,42}] wire cyc_B3_sqrt = cyc_B3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :260:30, :274:30] wire cyc_B2_sqrt = cyc_B2 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :261:30, :275:30] wire cyc_B1_sqrt = cyc_B1 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :262:30, :276:30] wire [2:0] _cycleNum_C_T = sqrtOp_PB ? 3'h6 : 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :280:28] wire [3:0] _cycleNum_C_T_1 = {1'h0, cycleNum_C} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:62] wire [2:0] _cycleNum_C_T_2 = _cycleNum_C_T_1[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:280:62] wire [2:0] _cycleNum_C_T_3 = cyc_B1 ? _cycleNum_C_T : _cycleNum_C_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :280:{16,28,62}] wire cyc_C6_sqrt = cycleNum_C == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :283:35] wire cyc_C5 = cycleNum_C == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :285:30] wire cyc_C4 = cycleNum_C == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :286:30] wire cyc_C3 = cycleNum_C == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :287:30] wire cyc_C2 = cycleNum_C == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :288:30] wire cyc_C1 = cycleNum_C == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :289:30] wire _cyc_C5_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :291:32] wire cyc_C5_div = cyc_C5 & _cyc_C5_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :291:{29,32}] wire _cyc_C4_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :292:32] wire cyc_C4_div = cyc_C4 & _cyc_C4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :292:{29,32}] wire _cyc_C3_div_T = ~sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :267:32, :293:32] wire cyc_C3_div = cyc_C3 & _cyc_C3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :293:{29,32}] wire _cyc_C2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32] wire cyc_C2_div = cyc_C2 & _cyc_C2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :294:{29,32}] wire _cyc_C1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :295:32] wire cyc_C1_div = cyc_C1 & _cyc_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :295:{29,32}] wire cyc_C5_sqrt = cyc_C5 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :285:30, :297:30] wire cyc_C4_sqrt = cyc_C4 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :286:30, :298:30] wire cyc_C3_sqrt = cyc_C3 & sqrtOp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :287:30, :299:30] wire cyc_C2_sqrt = cyc_C2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :288:30, :300:30] wire cyc_C1_sqrt = cyc_C1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :289:30, :301:30] wire [3:0] _cycleNum_E_T = {1'h0, cycleNum_E} - 4'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:51] wire [2:0] _cycleNum_E_T_1 = _cycleNum_E_T[2:0]; // @[DivSqrtRecF64_mulAddZ31.scala:304:51] wire [2:0] _cycleNum_E_T_2 = cyc_C1 ? 3'h4 : _cycleNum_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :304:{26,51}] wire cyc_E4 = cycleNum_E == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :307:30] wire cyc_E3 = cycleNum_E == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :308:30] wire cyc_E2 = cycleNum_E == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :309:30] wire cyc_E1 = cycleNum_E == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :310:30] wire _cyc_E4_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :312:32] wire cyc_E4_div = cyc_E4 & _cyc_E4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:307:30, :312:{29,32}] wire _cyc_E3_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :313:32] wire cyc_E3_div = cyc_E3 & _cyc_E3_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:308:30, :313:{29,32}] wire _cyc_E2_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :314:32] wire cyc_E2_div = cyc_E2 & _cyc_E2_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:309:30, :314:{29,32}] wire _cyc_E1_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :315:32] wire cyc_E1_div = cyc_E1 & _cyc_E1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :315:{29,32}] wire cyc_E4_sqrt = cyc_E4 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :307:30, :317:30] wire cyc_E3_sqrt = cyc_E3 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :308:30, :318:30] wire cyc_E2_sqrt = cyc_E2 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :309:30, :319:30] wire cyc_E1_sqrt = cyc_E1 & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :310:30, :320:30] wire _entering_PA_T = ~ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :325:58] wire _entering_PA_T_1 = valid_PA | _entering_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:{55,58}] wire _entering_PA_T_2 = cyc_S & _entering_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :325:{42,55}] wire entering_PA = entering_PA_normalCase | _entering_PA_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:213:36, :325:{32,42}] wire [12:0] _sExp_PA_T = io_sqrtOp_0 ? rawB_S_sExp : sSatExpQuot_S_div; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractB_PA_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A4_div_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _zFractB_A7_sqrt_T = rawB_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fractA_PA_T = rawA_S_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire _normalCase_PA_T = ~isNaN_PA; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :347:25] wire _normalCase_PA_T_1 = ~isInf_PA; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :347:39] wire _normalCase_PA_T_2 = _normalCase_PA_T & _normalCase_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:347:{25,36,39}] wire _normalCase_PA_T_3 = ~isZero_PA; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :347:53] wire normalCase_PA = _normalCase_PA_T_2 & _normalCase_PA_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:347:{36,50,53}] wire [52:0] sigA_PA = {1'h1, fractA_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :348:28] wire [52:0] sigB_PA = {1'h1, fractB_PA}; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :349:28] wire valid_normalCase_leaving_PA = cyc_B4_div | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :266:41, :351:50] wire valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :347:50, :351:50, :353:12] assign _leaving_PA_T = valid_PA & valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :353:12, :354:28] assign leaving_PA = _leaving_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :354:28] wire _ready_PA_T = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17] assign _ready_PA_T_1 = _ready_PA_T | valid_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:353:12, :355:{17,28}] assign ready_PA = _ready_PA_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :355:28] wire _entering_PB_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18] wire _entering_PB_S_T_1 = cyc_S & _entering_PB_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :360:{15,18}] wire _entering_PB_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :360:36] wire _entering_PB_S_T_3 = _entering_PB_S_T_1 & _entering_PB_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:360:{15,33,36}] wire _entering_PB_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29] wire _entering_PB_S_T_5 = ~ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :361:43] wire _entering_PB_S_T_6 = _entering_PB_S_T_4 & _entering_PB_S_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:361:{29,40,43}] wire _entering_PB_S_T_7 = leaving_PB | _entering_PB_S_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :361:{25,40}] wire entering_PB_S = _entering_PB_S_T_3 & _entering_PB_S_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:360:{33,47}, :361:25] wire _entering_PB_normalCase_T = valid_PA & normalCase_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :347:50, :363:18] wire entering_PB_normalCase = _entering_PB_normalCase_T & valid_normalCase_leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:351:50, :363:{18,35}] wire entering_PB = entering_PB_S | leaving_PA; // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :360:47, :364:37] wire _sqrtOp_PB_T = valid_PA ? sqrtOp_PA : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :92:30, :370:27] wire _majorExc_PB_T = valid_PA ? majorExc_PA : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :93:30, :176:12, :371:27] wire _isNaN_PB_T = valid_PA ? isNaN_PA : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :95:30, :183:12, :372:27] wire _isInf_PB_T = valid_PA ? isInf_PA : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :96:30, :187:23, :373:27] wire _isZero_PB_T = valid_PA ? isZero_PA : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :97:30, :188:23, :374:27] wire _sign_PB_T = valid_PA ? sign_PA : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :98:30, :189:47, :375:27] wire _bit0FractA_PB_T = fractA_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :379:37] wire [2:0] _roundingMode_PB_T = valid_PA ? roundingMode_PA : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :91:34, :102:30, :381:31] wire _normalCase_PB_T = ~isNaN_PB; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :384:25] wire _normalCase_PB_T_1 = ~isInf_PB; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :384:39] wire _normalCase_PB_T_2 = _normalCase_PB_T & _normalCase_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:384:{25,36,39}] wire _normalCase_PB_T_3 = ~isZero_PB; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :384:53] wire normalCase_PB = _normalCase_PB_T_2 & _normalCase_PB_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:384:{36,50,53}] wire valid_leaving_PB = normalCase_PB ? cyc_C3 : ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :287:30, :384:50, :388:12] assign _leaving_PB_T = valid_PB & valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :388:12, :389:28] assign leaving_PB = _leaving_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :389:28] wire _ready_PB_T = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :390:17] assign _ready_PB_T_1 = _ready_PB_T | valid_leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:388:12, :390:{17,28}] assign ready_PB = _ready_PB_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:151:26, :390:28] wire _entering_PC_S_T = ~normalCase_S; // @[DivSqrtRecF64_mulAddZ31.scala:195:27, :360:18, :395:18] wire _entering_PC_S_T_1 = cyc_S & _entering_PC_S_T; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :395:{15,18}] wire _entering_PC_S_T_2 = ~valid_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :355:17, :395:36] wire _entering_PC_S_T_3 = _entering_PC_S_T_1 & _entering_PC_S_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:395:{15,33,36}] wire _entering_PC_S_T_4 = ~valid_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :361:29, :395:50] wire _entering_PC_S_T_5 = _entering_PC_S_T_3 & _entering_PC_S_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:395:{33,47,50}] wire entering_PC_S = _entering_PC_S_T_5 & ready_PC; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :395:{47,61}] wire _entering_PC_normalCase_T = valid_PB & normalCase_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :384:50, :397:18] wire entering_PC_normalCase = _entering_PC_normalCase_T & cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :397:{18,35}] wire entering_PC = entering_PC_S | leaving_PB; // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :395:61, :398:37] wire _sqrtOp_PC_T = valid_PB ? sqrtOp_PB : io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :105:30, :404:27] wire _majorExc_PC_T = valid_PB ? majorExc_PB : majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :106:30, :176:12, :405:27] wire _isNaN_PC_T = valid_PB ? isNaN_PB : isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :108:30, :183:12, :406:27] wire _isInf_PC_T = valid_PB ? isInf_PB : isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :109:30, :187:23, :407:27] wire _isZero_PC_T = valid_PB ? isZero_PB : isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :110:30, :188:23, :408:27] wire _sign_PC_T = valid_PB ? sign_PB : sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :111:30, :189:47, :409:27] wire [2:0] _roundingMode_PC_T = valid_PB ? roundingMode_PB : io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :104:34, :115:30, :415:31] wire _normalCase_PC_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25] wire _normalCase_PC_T_1 = ~isInf_PC; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :418:39] wire _normalCase_PC_T_2 = _normalCase_PC_T & _normalCase_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:418:{25,36,39}] wire _normalCase_PC_T_3 = ~isZero_PC; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :418:53] wire normalCase_PC = _normalCase_PC_T_2 & _normalCase_PC_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:418:{36,50,53}] wire [52:0] sigB_PC = {1'h1, fractB_PC}; // @[DivSqrtRecF64_mulAddZ31.scala:127:30, :419:28] wire _valid_leaving_PC_T = ~normalCase_PC; // @[DivSqrtRecF64_mulAddZ31.scala:418:50, :421:28] wire valid_leaving_PC = _valid_leaving_PC_T | cyc_E1; // @[DivSqrtRecF64_mulAddZ31.scala:310:30, :421:{28,44}] assign _leaving_PC_T = valid_PC & valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :421:44, :422:28] assign leaving_PC = _leaving_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :422:28] wire _ready_PC_T = ~valid_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :423:17] assign _ready_PC_T_1 = _ready_PC_T | valid_leaving_PC; // @[DivSqrtRecF64_mulAddZ31.scala:421:44, :423:{17,28}] assign ready_PC = _ready_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:152:26, :423:28] wire _io_inReady_div_T = ~cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :430:21] wire _io_inReady_div_T_1 = ready_PA & _io_inReady_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :430:{18,21}] wire _io_inReady_div_T_2 = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38] wire _io_inReady_div_T_3 = _io_inReady_div_T_1 & _io_inReady_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:430:{18,35,38}] wire _io_inReady_div_T_4 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55] wire _io_inReady_div_T_5 = _io_inReady_div_T_3 & _io_inReady_div_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:430:{35,52,55}] wire _io_inReady_div_T_6 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13] wire _io_inReady_div_T_7 = _io_inReady_div_T_5 & _io_inReady_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:430:{52,69}, :431:13] wire _io_inReady_div_T_8 = ~cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :431:30] wire _io_inReady_div_T_9 = _io_inReady_div_T_7 & _io_inReady_div_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:430:69, :431:{27,30}] wire _io_inReady_div_T_10 = ~cyc_B2; // @[DivSqrtRecF64_mulAddZ31.scala:261:30, :431:42] wire _io_inReady_div_T_11 = _io_inReady_div_T_9 & _io_inReady_div_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:431:{27,39,42}] wire _io_inReady_div_T_12 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54] wire _io_inReady_div_T_13 = _io_inReady_div_T_11 & _io_inReady_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:431:{39,51,54}] wire _io_inReady_div_T_14 = ~cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :432:13] wire _io_inReady_div_T_15 = _io_inReady_div_T_13 & _io_inReady_div_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:431:{51,68}, :432:13] wire _io_inReady_div_T_16 = ~cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :432:25] assign _io_inReady_div_T_17 = _io_inReady_div_T_15 & _io_inReady_div_T_16; // @[DivSqrtRecF64_mulAddZ31.scala:431:68, :432:{22,25}] assign io_inReady_div_0 = _io_inReady_div_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :432:22] wire _io_inReady_sqrt_T = ~cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :430:38, :434:21] wire _io_inReady_sqrt_T_1 = ready_PA & _io_inReady_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:150:26, :434:{18,21}] wire _io_inReady_sqrt_T_2 = ~cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :430:55, :434:38] wire _io_inReady_sqrt_T_3 = _io_inReady_sqrt_T_1 & _io_inReady_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:434:{18,35,38}] wire _io_inReady_sqrt_T_4 = ~cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :431:13, :434:55] wire _io_inReady_sqrt_T_5 = _io_inReady_sqrt_T_3 & _io_inReady_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:434:{35,52,55}] wire _io_inReady_sqrt_T_6 = ~cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :435:13] wire _io_inReady_sqrt_T_7 = _io_inReady_sqrt_T_5 & _io_inReady_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:434:{52,69}, :435:13] wire _io_inReady_sqrt_T_8 = ~cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :431:54, :435:29] assign _io_inReady_sqrt_T_9 = _io_inReady_sqrt_T_7 & _io_inReady_sqrt_T_8; // @[DivSqrtRecF64_mulAddZ31.scala:434:69, :435:{26,29}] assign io_inReady_sqrt_0 = _io_inReady_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :435:26] wire [51:0] zFractB_A4_div = entering_PA_normalCase_div ? _zFractB_A4_div_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :440:{29,52}] wire [2:0] _zLinPiece_0_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_1_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_2_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_3_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_4_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_5_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_6_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire [2:0] _zLinPiece_7_A4_div_T = rawB_S_sig[51:49]; // @[rawFloatFromRecFN.scala:55:23] wire _zLinPiece_0_A4_div_T_1 = _zLinPiece_0_A4_div_T == 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:{55,64}] wire zLinPiece_0_A4_div = entering_PA_normalCase_div & _zLinPiece_0_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :442:{41,64}] wire _zLinPiece_1_A4_div_T_1 = _zLinPiece_1_A4_div_T == 3'h1; // @[DivSqrtRecF64_mulAddZ31.scala:443:{55,64}] wire zLinPiece_1_A4_div = entering_PA_normalCase_div & _zLinPiece_1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :443:{41,64}] wire _zLinPiece_2_A4_div_T_1 = _zLinPiece_2_A4_div_T == 3'h2; // @[DivSqrtRecF64_mulAddZ31.scala:444:{55,64}] wire zLinPiece_2_A4_div = entering_PA_normalCase_div & _zLinPiece_2_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :444:{41,64}] wire _zLinPiece_3_A4_div_T_1 = _zLinPiece_3_A4_div_T == 3'h3; // @[DivSqrtRecF64_mulAddZ31.scala:445:{55,64}] wire zLinPiece_3_A4_div = entering_PA_normalCase_div & _zLinPiece_3_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :445:{41,64}] wire _zLinPiece_4_A4_div_T_1 = _zLinPiece_4_A4_div_T == 3'h4; // @[DivSqrtRecF64_mulAddZ31.scala:446:{55,64}] wire zLinPiece_4_A4_div = entering_PA_normalCase_div & _zLinPiece_4_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :446:{41,64}] wire _zLinPiece_5_A4_div_T_1 = _zLinPiece_5_A4_div_T == 3'h5; // @[DivSqrtRecF64_mulAddZ31.scala:447:{55,64}] wire zLinPiece_5_A4_div = entering_PA_normalCase_div & _zLinPiece_5_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :447:{41,64}] wire _zLinPiece_6_A4_div_T_1 = _zLinPiece_6_A4_div_T == 3'h6; // @[DivSqrtRecF64_mulAddZ31.scala:448:{55,64}] wire zLinPiece_6_A4_div = entering_PA_normalCase_div & _zLinPiece_6_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :448:{41,64}] wire _zLinPiece_7_A4_div_T_1 = &_zLinPiece_7_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:449:{55,64}] wire zLinPiece_7_A4_div = entering_PA_normalCase_div & _zLinPiece_7_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :449:{41,64}] wire [8:0] _zK1_A4_div_T = zLinPiece_0_A4_div ? 9'h1C7 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :451:12] wire [8:0] _zK1_A4_div_T_1 = zLinPiece_1_A4_div ? 9'h16C : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :452:12] wire [8:0] _zK1_A4_div_T_2 = _zK1_A4_div_T | _zK1_A4_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:451:{12,48}, :452:12] wire [8:0] _zK1_A4_div_T_3 = zLinPiece_2_A4_div ? 9'h12A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :453:12] wire [8:0] _zK1_A4_div_T_4 = _zK1_A4_div_T_2 | _zK1_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:451:48, :452:48, :453:12] wire [7:0] _zK1_A4_div_T_5 = zLinPiece_3_A4_div ? 8'hF8 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :454:12] wire [8:0] _zK1_A4_div_T_6 = {_zK1_A4_div_T_4[8], _zK1_A4_div_T_4[7:0] | _zK1_A4_div_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:452:48, :453:48, :454:12] wire [7:0] _zK1_A4_div_T_7 = zLinPiece_4_A4_div ? 8'hD2 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :455:12] wire [8:0] _zK1_A4_div_T_8 = {_zK1_A4_div_T_6[8], _zK1_A4_div_T_6[7:0] | _zK1_A4_div_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:453:48, :454:48, :455:12] wire [7:0] _zK1_A4_div_T_9 = zLinPiece_5_A4_div ? 8'hB4 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :456:12] wire [8:0] _zK1_A4_div_T_10 = {_zK1_A4_div_T_8[8], _zK1_A4_div_T_8[7:0] | _zK1_A4_div_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:454:48, :455:48, :456:12] wire [7:0] _zK1_A4_div_T_11 = zLinPiece_6_A4_div ? 8'h9C : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :457:12] wire [8:0] _zK1_A4_div_T_12 = {_zK1_A4_div_T_10[8], _zK1_A4_div_T_10[7:0] | _zK1_A4_div_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:455:48, :456:48, :457:12] wire [7:0] _zK1_A4_div_T_13 = zLinPiece_7_A4_div ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :458:12] wire [8:0] zK1_A4_div = {_zK1_A4_div_T_12[8], _zK1_A4_div_T_12[7:0] | _zK1_A4_div_T_13}; // @[DivSqrtRecF64_mulAddZ31.scala:456:48, :457:48, :458:12] wire [11:0] _zComplFractK0_A4_div_T_1 = zLinPiece_0_A4_div ? 12'h1C : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:442:41, :460:12] wire [11:0] _zComplFractK0_A4_div_T_3 = zLinPiece_1_A4_div ? 12'h3A2 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:443:41, :461:12] wire [11:0] _zComplFractK0_A4_div_T_4 = _zComplFractK0_A4_div_T_1 | _zComplFractK0_A4_div_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:460:{12,55}, :461:12] wire [11:0] _zComplFractK0_A4_div_T_6 = zLinPiece_2_A4_div ? 12'h675 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:444:41, :462:12] wire [11:0] _zComplFractK0_A4_div_T_7 = _zComplFractK0_A4_div_T_4 | _zComplFractK0_A4_div_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:460:55, :461:55, :462:12] wire [11:0] _zComplFractK0_A4_div_T_9 = zLinPiece_3_A4_div ? 12'h8C6 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:445:41, :463:12] wire [11:0] _zComplFractK0_A4_div_T_10 = _zComplFractK0_A4_div_T_7 | _zComplFractK0_A4_div_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:461:55, :462:55, :463:12] wire [11:0] _zComplFractK0_A4_div_T_12 = zLinPiece_4_A4_div ? 12'hAB4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:446:41, :464:12] wire [11:0] _zComplFractK0_A4_div_T_13 = _zComplFractK0_A4_div_T_10 | _zComplFractK0_A4_div_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:462:55, :463:55, :464:12] wire [11:0] _zComplFractK0_A4_div_T_15 = zLinPiece_5_A4_div ? 12'hC56 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:447:41, :465:12] wire [11:0] _zComplFractK0_A4_div_T_16 = _zComplFractK0_A4_div_T_13 | _zComplFractK0_A4_div_T_15; // @[DivSqrtRecF64_mulAddZ31.scala:463:55, :464:55, :465:12] wire [11:0] _zComplFractK0_A4_div_T_18 = zLinPiece_6_A4_div ? 12'hDBD : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:448:41, :466:12] wire [11:0] _zComplFractK0_A4_div_T_19 = _zComplFractK0_A4_div_T_16 | _zComplFractK0_A4_div_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:464:55, :465:55, :466:12] wire [11:0] _zComplFractK0_A4_div_T_21 = zLinPiece_7_A4_div ? 12'hEF4 : 12'h0; // @[DivSqrtRecF64_mulAddZ31.scala:449:41, :467:12] wire [11:0] zComplFractK0_A4_div = _zComplFractK0_A4_div_T_19 | _zComplFractK0_A4_div_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:465:55, :466:55, :467:12] wire [51:0] zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? _zFractB_A7_sqrt_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :469:{30,54}] wire _zQuadPiece_0_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_1_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_2_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_3_A7_sqrt_T = rawB_S_sExp[0]; // @[rawFloatFromRecFN.scala:55:23] wire _zQuadPiece_0_A7_sqrt_T_1 = ~_zQuadPiece_0_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:472:{24,37}] wire _zQuadPiece_0_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_0_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :472:{21,24}] wire _zQuadPiece_0_A7_sqrt_T_4 = ~_zQuadPiece_0_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:472:{44,56}] wire zQuadPiece_0_A7_sqrt = _zQuadPiece_0_A7_sqrt_T_2 & _zQuadPiece_0_A7_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:472:{21,41,44}] wire _zQuadPiece_1_A7_sqrt_T_1 = ~_zQuadPiece_1_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:474:{24,37}] wire _zQuadPiece_1_A7_sqrt_T_2 = entering_PA_normalCase_sqrt & _zQuadPiece_1_A7_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :474:{21,24}] wire zQuadPiece_1_A7_sqrt = _zQuadPiece_1_A7_sqrt_T_2 & _zQuadPiece_1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:474:{21,41,56}] wire _zQuadPiece_2_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_2_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :476:{21,37}] wire _zQuadPiece_2_A7_sqrt_T_3 = ~_zQuadPiece_2_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:476:{44,56}] wire zQuadPiece_2_A7_sqrt = _zQuadPiece_2_A7_sqrt_T_1 & _zQuadPiece_2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:476:{21,41,44}] wire _zQuadPiece_3_A7_sqrt_T_1 = entering_PA_normalCase_sqrt & _zQuadPiece_3_A7_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :477:{44,58}] wire zQuadPiece_3_A7_sqrt = _zQuadPiece_3_A7_sqrt_T_1 & _zQuadPiece_3_A7_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:477:{44,62,75}] wire [8:0] _zK2_A7_sqrt_T = zQuadPiece_0_A7_sqrt ? 9'h1C8 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :479:12] wire [7:0] _zK2_A7_sqrt_T_1 = zQuadPiece_1_A7_sqrt ? 8'hC1 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :480:12] wire [8:0] _zK2_A7_sqrt_T_2 = {_zK2_A7_sqrt_T[8], _zK2_A7_sqrt_T[7:0] | _zK2_A7_sqrt_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:479:{12,50}, :480:12] wire [8:0] _zK2_A7_sqrt_T_3 = zQuadPiece_2_A7_sqrt ? 9'h143 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :481:12] wire [8:0] _zK2_A7_sqrt_T_4 = _zK2_A7_sqrt_T_2 | _zK2_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:479:50, :480:50, :481:12] wire [7:0] _zK2_A7_sqrt_T_5 = zQuadPiece_3_A7_sqrt ? 8'h89 : 8'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :482:12] wire [8:0] zK2_A7_sqrt = {_zK2_A7_sqrt_T_4[8], _zK2_A7_sqrt_T_4[7:0] | _zK2_A7_sqrt_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:480:50, :481:50, :482:12] wire [9:0] _zComplK1_A7_sqrt_T_1 = zQuadPiece_0_A7_sqrt ? 10'h2F : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:472:41, :484:12] wire [9:0] _zComplK1_A7_sqrt_T_3 = zQuadPiece_1_A7_sqrt ? 10'h1DF : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:474:41, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_4 = _zComplK1_A7_sqrt_T_1 | _zComplK1_A7_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:484:{12,57}, :485:12] wire [9:0] _zComplK1_A7_sqrt_T_6 = zQuadPiece_2_A7_sqrt ? 10'h14D : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:476:41, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_7 = _zComplK1_A7_sqrt_T_4 | _zComplK1_A7_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:484:57, :485:57, :486:12] wire [9:0] _zComplK1_A7_sqrt_T_9 = zQuadPiece_3_A7_sqrt ? 10'h27E : 10'h0; // @[DivSqrtRecF64_mulAddZ31.scala:477:62, :487:12] wire [9:0] zComplK1_A7_sqrt = _zComplK1_A7_sqrt_T_7 | _zComplK1_A7_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:485:57, :486:57, :487:12] wire _zQuadPiece_0_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56] wire _zQuadPiece_1_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :490:56] wire _zQuadPiece_2_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :491:56] wire _zQuadPiece_3_A6_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :492:56] wire _sqrR0_A5_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :533:36] wire _ER1_A1_sqrt_T = sExp_PA[0]; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :489:56, :539:34] wire _zQuadPiece_0_A6_sqrt_T_1 = ~_zQuadPiece_0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:489:{47,56}] wire _zQuadPiece_0_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_0_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :489:{44,47}] wire _zQuadPiece_0_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72] wire _zQuadPiece_1_A6_sqrt_T_3 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :490:72] wire _zQuadPiece_2_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :491:72] wire _zQuadPiece_3_A6_sqrt_T_2 = sigB_PA[51]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :489:72, :492:72] wire _zQuadPiece_0_A6_sqrt_T_4 = ~_zQuadPiece_0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:489:{63,72}] wire zQuadPiece_0_A6_sqrt = _zQuadPiece_0_A6_sqrt_T_2 & _zQuadPiece_0_A6_sqrt_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:489:{44,60,63}] wire _zQuadPiece_1_A6_sqrt_T_1 = ~_zQuadPiece_1_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:490:{47,56}] wire _zQuadPiece_1_A6_sqrt_T_2 = cyc_A6_sqrt & _zQuadPiece_1_A6_sqrt_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :490:{44,47}] wire zQuadPiece_1_A6_sqrt = _zQuadPiece_1_A6_sqrt_T_2 & _zQuadPiece_1_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:490:{44,60,72}] wire _zQuadPiece_2_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_2_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :491:{44,56}] wire _zQuadPiece_2_A6_sqrt_T_3 = ~_zQuadPiece_2_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:491:{63,72}] wire zQuadPiece_2_A6_sqrt = _zQuadPiece_2_A6_sqrt_T_1 & _zQuadPiece_2_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:491:{44,60,63}] wire _zQuadPiece_3_A6_sqrt_T_1 = cyc_A6_sqrt & _zQuadPiece_3_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :492:{44,56}] wire zQuadPiece_3_A6_sqrt = _zQuadPiece_3_A6_sqrt_T_1 & _zQuadPiece_3_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:492:{44,60,72}] wire [12:0] _zComplFractK0_A6_sqrt_T_1 = zQuadPiece_0_A6_sqrt ? 13'h1A : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:489:60, :494:12] wire [12:0] _zComplFractK0_A6_sqrt_T_3 = zQuadPiece_1_A6_sqrt ? 13'hBCA : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:490:60, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_4 = _zComplFractK0_A6_sqrt_T_1 | _zComplFractK0_A6_sqrt_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:494:{12,58}, :495:12] wire [12:0] _zComplFractK0_A6_sqrt_T_6 = zQuadPiece_2_A6_sqrt ? 13'h12D3 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:491:60, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_7 = _zComplFractK0_A6_sqrt_T_4 | _zComplFractK0_A6_sqrt_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:494:58, :495:58, :496:12] wire [12:0] _zComplFractK0_A6_sqrt_T_9 = zQuadPiece_3_A6_sqrt ? 13'h1B17 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:492:60, :497:12] wire [12:0] zComplFractK0_A6_sqrt = _zComplFractK0_A6_sqrt_T_7 | _zComplFractK0_A6_sqrt_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:495:58, :496:58, :497:12] wire [8:0] _mulAdd9A_A_T = zFractB_A4_div[48:40]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :500:23] wire [8:0] _mulAdd9A_A_T_1 = _mulAdd9A_A_T | zK2_A7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:481:50, :500:{23,32}] wire _mulAdd9A_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17] wire [8:0] _mulAdd9A_A_T_3 = _mulAdd9A_A_T_2 ? nextMulAdd9A_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :501:{16,17}] wire [8:0] mulAdd9A_A = _mulAdd9A_A_T_1 | _mulAdd9A_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:500:{32,46}, :501:16] wire [8:0] _mulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37] wire [8:0] _nextMulAdd9B_A_T = zFractB_A7_sqrt[50:42]; // @[DivSqrtRecF64_mulAddZ31.scala:469:30, :503:37, :563:28] wire [8:0] _mulAdd9B_A_T_1 = zK1_A4_div | _mulAdd9B_A_T; // @[DivSqrtRecF64_mulAddZ31.scala:457:48, :503:{20,37}] wire _mulAdd9B_A_T_2 = ~cyc_S; // @[DivSqrtRecF64_mulAddZ31.scala:166:27, :501:17, :504:17] wire [8:0] _mulAdd9B_A_T_3 = _mulAdd9B_A_T_2 ? nextMulAdd9B_A : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :504:{16,17}] wire [8:0] mulAdd9B_A = _mulAdd9B_A_T_1 | _mulAdd9B_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:503:{20,46}, :504:16] wire [9:0] _mulAdd9C_A_T = {10{entering_PA_normalCase_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :507:50] wire [19:0] _mulAdd9C_A_T_1 = {zComplK1_A7_sqrt, _mulAdd9C_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:486:57, :507:{26,50}] wire [5:0] _mulAdd9C_A_T_2 = {6{cyc_A6_sqrt}}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :508:53] wire [13:0] mulAdd9C_A_hi = {cyc_A6_sqrt, zComplFractK0_A6_sqrt}; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :496:58, :508:12] wire [19:0] _mulAdd9C_A_T_3 = {mulAdd9C_A_hi, _mulAdd9C_A_T_2}; // @[DivSqrtRecF64_mulAddZ31.scala:508:{12,53}] wire [19:0] _mulAdd9C_A_T_4 = _mulAdd9C_A_T_1 | _mulAdd9C_A_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:507:{26,68}, :508:12] wire [7:0] _mulAdd9C_A_T_5 = {8{entering_PA_normalCase_div}}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :509:53] wire [12:0] mulAdd9C_A_hi_1 = {entering_PA_normalCase_div, zComplFractK0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :466:55, :509:12] wire [20:0] _mulAdd9C_A_T_6 = {mulAdd9C_A_hi_1, _mulAdd9C_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:509:{12,53}] wire [20:0] _mulAdd9C_A_T_7 = {1'h0, _mulAdd9C_A_T_4} | _mulAdd9C_A_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:507:68, :508:71, :509:12] wire [18:0] _mulAdd9C_A_T_8 = {fractR0_A, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :510:53] wire [19:0] _mulAdd9C_A_T_9 = {1'h0, _mulAdd9C_A_T_8} + 20'h40000; // @[DivSqrtRecF64_mulAddZ31.scala:510:{40,53}] wire [19:0] _mulAdd9C_A_T_10 = cyc_A5_sqrt ? _mulAdd9C_A_T_9 : 20'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :510:{12,40}] wire [20:0] _mulAdd9C_A_T_11 = {_mulAdd9C_A_T_7[20], _mulAdd9C_A_T_7[19:0] | _mulAdd9C_A_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:508:71, :509:71, :510:12] wire _mulAdd9C_A_T_12 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44] wire _mulAdd9C_A_T_17 = hiSqrR0_A_sqrt[9]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :511:44, :512:43] wire _mulAdd9C_A_T_13 = ~_mulAdd9C_A_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:511:{28,44}] wire _mulAdd9C_A_T_14 = cyc_A4_sqrt & _mulAdd9C_A_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :511:{25,28}] wire [10:0] _mulAdd9C_A_T_15 = {_mulAdd9C_A_T_14, 10'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:511:{12,25}] wire [20:0] _mulAdd9C_A_T_16 = {_mulAdd9C_A_T_11[20:11], _mulAdd9C_A_T_11[10:0] | _mulAdd9C_A_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:509:71, :510:65, :511:12] wire _mulAdd9C_A_T_18 = cyc_A4_sqrt & _mulAdd9C_A_T_17; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :512:{26,43}] wire _mulAdd9C_A_T_19 = _mulAdd9C_A_T_18 | cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:236:29, :512:{26,48}] wire [20:0] _mulAdd9C_A_T_20 = sigB_PA[46:26]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :513:20] wire [21:0] _mulAdd9C_A_T_21 = {1'h0, _mulAdd9C_A_T_20} + 22'h400; // @[DivSqrtRecF64_mulAddZ31.scala:513:{20,29}] wire [20:0] _mulAdd9C_A_T_22 = _mulAdd9C_A_T_21[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:513:29] wire [20:0] _mulAdd9C_A_T_23 = _mulAdd9C_A_T_19 ? _mulAdd9C_A_T_22 : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:512:{12,48}, :513:29] wire [20:0] _mulAdd9C_A_T_24 = _mulAdd9C_A_T_16 | _mulAdd9C_A_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:510:65, :511:65, :512:12] wire _mulAdd9C_A_T_25 = cyc_A3_sqrt | cyc_A2; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :240:30, :516:25] wire [20:0] _mulAdd9C_A_T_26 = _mulAdd9C_A_T_25 ? partNegSigma0_A : 21'h0; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :516:{12,25}] wire [20:0] _mulAdd9C_A_T_27 = _mulAdd9C_A_T_24 | _mulAdd9C_A_T_26; // @[DivSqrtRecF64_mulAddZ31.scala:511:65, :515:11, :516:12] wire [24:0] _mulAdd9C_A_T_28 = {fractR0_A, 16'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :517:45] wire [24:0] _mulAdd9C_A_T_29 = cyc_A1_sqrt ? _mulAdd9C_A_T_28 : 25'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :517:{12,45}] wire [24:0] _mulAdd9C_A_T_30 = {4'h0, _mulAdd9C_A_T_27} | _mulAdd9C_A_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:515:11, :516:58, :517:12] wire [23:0] _mulAdd9C_A_T_31 = {fractR0_A, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :518:45] wire [23:0] _mulAdd9C_A_T_32 = cyc_A1_div ? _mulAdd9C_A_T_31 : 24'h0; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :518:{12,45}] wire [24:0] mulAdd9C_A = {_mulAdd9C_A_T_30[24], _mulAdd9C_A_T_30[23:0] | _mulAdd9C_A_T_32}; // @[DivSqrtRecF64_mulAddZ31.scala:516:58, :517:58, :518:12] wire [17:0] _loMulAdd9Out_A_T = {9'h0, mulAdd9A_A} * {9'h0, mulAdd9B_A}; // @[DivSqrtRecF64_mulAddZ31.scala:500:46, :503:46, :519:37] wire [17:0] _loMulAdd9Out_A_T_1 = mulAdd9C_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :519:63] wire [18:0] loMulAdd9Out_A = {1'h0, _loMulAdd9Out_A_T} + {1'h0, _loMulAdd9Out_A_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:519:{37,50,63}] wire _mulAdd9Out_A_T = loMulAdd9Out_A[18]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :521:31] wire [6:0] _mulAdd9Out_A_T_1 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27] wire [6:0] _mulAdd9Out_A_T_4 = mulAdd9C_A[24:18]; // @[DivSqrtRecF64_mulAddZ31.scala:517:58, :522:27, :523:27] wire [7:0] _mulAdd9Out_A_T_2 = {1'h0, _mulAdd9Out_A_T_1} + 8'h1; // @[DivSqrtRecF64_mulAddZ31.scala:522:{27,36}] wire [6:0] _mulAdd9Out_A_T_3 = _mulAdd9Out_A_T_2[6:0]; // @[DivSqrtRecF64_mulAddZ31.scala:522:36] wire [6:0] _mulAdd9Out_A_T_5 = _mulAdd9Out_A_T ? _mulAdd9Out_A_T_3 : _mulAdd9Out_A_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:521:{16,31}, :522:36, :523:27] wire [17:0] _mulAdd9Out_A_T_6 = loMulAdd9Out_A[17:0]; // @[DivSqrtRecF64_mulAddZ31.scala:519:50, :525:27] wire [24:0] mulAdd9Out_A = {_mulAdd9Out_A_T_5, _mulAdd9Out_A_T_6}; // @[DivSqrtRecF64_mulAddZ31.scala:521:{12,16}, :525:27] wire _zFractR0_A6_sqrt_T = mulAdd9Out_A[19]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:40] wire _zFractR0_A6_sqrt_T_1 = cyc_A6_sqrt & _zFractR0_A6_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:225:35, :529:{25,40}] wire [14:0] _zFractR0_A6_sqrt_T_2 = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60] wire [14:0] _r1_A1_T = mulAdd9Out_A[24:10]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :529:60, :538:56] wire [14:0] _zFractR0_A6_sqrt_T_3 = ~_zFractR0_A6_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:529:{46,60}] wire [14:0] zFractR0_A6_sqrt = _zFractR0_A6_sqrt_T_1 ? _zFractR0_A6_sqrt_T_3 : 15'h0; // @[DivSqrtRecF64_mulAddZ31.scala:529:{12,25,46}] wire [25:0] _sqrR0_A5_sqrt_T_1 = {mulAdd9Out_A, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:53] wire [25:0] sqrR0_A5_sqrt = _sqrR0_A5_sqrt_T ? _sqrR0_A5_sqrt_T_1 : {1'h0, mulAdd9Out_A}; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :533:{28,36,53}] wire _zFractR0_A4_div_T = mulAdd9Out_A[20]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:39] wire _zFractR0_A4_div_T_1 = entering_PA_normalCase_div & _zFractR0_A4_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :535:{24,39}] wire [13:0] _zFractR0_A4_div_T_2 = mulAdd9Out_A[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :535:59] wire [13:0] _zFractR0_A4_div_T_3 = ~_zFractR0_A4_div_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:535:{45,59}] wire [13:0] zFractR0_A4_div = _zFractR0_A4_div_T_1 ? _zFractR0_A4_div_T_3 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:535:{12,24,45}] wire _zSigma0_A2_T = mulAdd9Out_A[11]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:35] wire _zSigma0_A2_T_1 = cyc_A2 & _zSigma0_A2_T; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :537:{20,35}] wire [22:0] _zSigma0_A2_T_2 = mulAdd9Out_A[24:2]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :537:55] wire [22:0] _zSigma0_A2_T_3 = ~_zSigma0_A2_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:537:{41,55}] wire [22:0] zSigma0_A2 = _zSigma0_A2_T_1 ? _zSigma0_A2_T_3 : 23'h0; // @[DivSqrtRecF64_mulAddZ31.scala:537:{12,20,41}] wire [15:0] _r1_A1_T_1 = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74] wire [15:0] _partNegSigma0_A_T = mulAdd9Out_A[24:9]; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :538:74, :548:71] wire [15:0] _r1_A1_T_2 = sqrtOp_PA ? {1'h0, _r1_A1_T} : _r1_A1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:92:30, :538:{32,56,74}] wire [15:0] r1_A1 = _r1_A1_T_2 | 16'h8000; // @[DivSqrtRecF64_mulAddZ31.scala:538:{27,32}] wire [16:0] _ER1_A1_sqrt_T_1 = {r1_A1, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:44] wire [16:0] ER1_A1_sqrt = _ER1_A1_sqrt_T ? _ER1_A1_sqrt_T_1 : {1'h0, r1_A1}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :539:{26,34,44}] wire [14:0] _fractR0_A_T = {zFractR0_A6_sqrt[14], zFractR0_A6_sqrt[13:0] | zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :535:12, :542:39] wire [15:0] _hiSqrR0_A_sqrt_T = sqrR0_A5_sqrt[25:10]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :545:40] wire [24:0] _partNegSigma0_A_T_1 = cyc_A4_sqrt ? mulAdd9Out_A : {9'h0, _partNegSigma0_A_T}; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :521:12, :548:{31,71}] wire [24:0] _nextMulAdd9A_A_T = ~mulAdd9Out_A; // @[DivSqrtRecF64_mulAddZ31.scala:521:12, :554:40] wire [13:0] _nextMulAdd9A_A_T_1 = _nextMulAdd9A_A_T[24:11]; // @[DivSqrtRecF64_mulAddZ31.scala:554:{40,53}] wire [13:0] _nextMulAdd9A_A_T_2 = entering_PA_normalCase_sqrt ? _nextMulAdd9A_A_T_1 : 14'h0; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :554:{16,53}] wire [14:0] _nextMulAdd9A_A_T_3 = {1'h0, _nextMulAdd9A_A_T_2} | zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :554:{16,64}] wire [8:0] _nextMulAdd9A_A_T_4 = sigB_PA[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :556:47] wire [8:0] _nextMulAdd9A_A_T_5 = cyc_A4_sqrt ? _nextMulAdd9A_A_T_4 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :556:{16,47}] wire [14:0] _nextMulAdd9A_A_T_6 = {_nextMulAdd9A_A_T_3[14:9], _nextMulAdd9A_A_T_3[8:0] | _nextMulAdd9A_A_T_5}; // @[DivSqrtRecF64_mulAddZ31.scala:554:64, :555:68, :556:16] wire [8:0] _nextMulAdd9A_A_T_7 = zFractB_A4_div[43:35]; // @[DivSqrtRecF64_mulAddZ31.scala:440:29, :557:27] wire [14:0] _nextMulAdd9A_A_T_8 = {_nextMulAdd9A_A_T_6[14:9], _nextMulAdd9A_A_T_6[8:0] | _nextMulAdd9A_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:555:68, :556:64, :557:27] wire _nextMulAdd9A_A_T_9 = cyc_A5_sqrt | cyc_A3; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :232:30, :558:29] wire [8:0] _nextMulAdd9A_A_T_10 = sigB_PA[52:44]; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :558:47] wire [8:0] _nextMulAdd9A_A_T_11 = _nextMulAdd9A_A_T_9 ? _nextMulAdd9A_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:558:{16,29,47}] wire [14:0] _nextMulAdd9A_A_T_12 = {_nextMulAdd9A_A_T_8[14:9], _nextMulAdd9A_A_T_8[8:0] | _nextMulAdd9A_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:556:64, :557:68, :558:16] wire [22:0] _nextMulAdd9A_A_T_13 = {8'h0, _nextMulAdd9A_A_T_12} | zSigma0_A2; // @[DivSqrtRecF64_mulAddZ31.scala:537:12, :557:68, :558:64] wire [14:0] _nextMulAdd9B_A_T_1 = {6'h0, _nextMulAdd9B_A_T} | zFractR0_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:529:12, :563:{28,73}] wire [8:0] _nextMulAdd9B_A_T_2 = sqrR0_A5_sqrt[9:1]; // @[DivSqrtRecF64_mulAddZ31.scala:533:28, :565:43] wire [8:0] _nextMulAdd9B_A_T_3 = cyc_A5_sqrt ? _nextMulAdd9B_A_T_2 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :565:{16,43}] wire [14:0] _nextMulAdd9B_A_T_4 = {_nextMulAdd9B_A_T_1[14:9], _nextMulAdd9B_A_T_1[8:0] | _nextMulAdd9B_A_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:563:73, :564:73, :565:16] wire [14:0] _nextMulAdd9B_A_T_5 = {_nextMulAdd9B_A_T_4[14], _nextMulAdd9B_A_T_4[13:0] | zFractR0_A4_div}; // @[DivSqrtRecF64_mulAddZ31.scala:535:12, :564:73, :565:69] wire [8:0] _nextMulAdd9B_A_T_6 = hiSqrR0_A_sqrt[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :567:44] wire [8:0] _nextMulAdd9B_A_T_7 = cyc_A4_sqrt ? _nextMulAdd9B_A_T_6 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :567:{16,44}] wire [14:0] _nextMulAdd9B_A_T_8 = {_nextMulAdd9B_A_T_5[14:9], _nextMulAdd9B_A_T_5[8:0] | _nextMulAdd9B_A_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:565:69, :566:73, :567:16] wire [7:0] _nextMulAdd9B_A_T_9 = fractR0_A[8:1]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :568:53] wire [8:0] _nextMulAdd9B_A_T_10 = {1'h1, _nextMulAdd9B_A_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:568:{33,53}] wire [8:0] _nextMulAdd9B_A_T_11 = cyc_A2 ? _nextMulAdd9B_A_T_10 : 9'h0; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :568:{16,33}] wire [14:0] _nextMulAdd9B_A_T_12 = {_nextMulAdd9B_A_T_8[14:9], _nextMulAdd9B_A_T_8[8:0] | _nextMulAdd9B_A_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:566:73, :567:69, :568:16] wire _GEN = cyc_A1 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :255:36, :577:16] wire _io_latchMulAddA_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] assign _io_latchMulAddA_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16] wire _io_latchMulAddB_0_T; // @[DivSqrtRecF64_mulAddZ31.scala:591:16] assign _io_latchMulAddB_0_T = _GEN; // @[DivSqrtRecF64_mulAddZ31.scala:577:16, :591:16] wire _io_latchMulAddA_0_T_1 = _io_latchMulAddA_0_T | cyc_B6_div; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :577:{16,31}] wire _io_latchMulAddA_0_T_2 = _io_latchMulAddA_0_T_1 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :577:{31,45}] wire _io_latchMulAddA_0_T_3 = _io_latchMulAddA_0_T_2 | cyc_B3; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :577:{45,55}] wire _io_latchMulAddA_0_T_4 = _io_latchMulAddA_0_T_3 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :577:{55,65}] wire _io_latchMulAddA_0_T_5 = _io_latchMulAddA_0_T_4 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :577:65, :578:25] assign _io_latchMulAddA_0_T_6 = _io_latchMulAddA_0_T_5 | cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :578:{25,35}] assign io_latchMulAddA_0_0 = _io_latchMulAddA_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :578:35] wire [52:0] _io_mulAddA_0_T = {ER1_A1_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:539:26, :580:51] wire [52:0] _io_mulAddA_0_T_1 = cyc_A1_sqrt ? _io_mulAddA_0_T : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:242:30, :580:{12,51}] wire _io_mulAddA_0_T_2 = cyc_B7_sqrt | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :255:36, :581:25] wire [52:0] _io_mulAddA_0_T_3 = _io_mulAddA_0_T_2 ? sigB_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:349:28, :581:{12,25}] wire [52:0] _io_mulAddA_0_T_4 = _io_mulAddA_0_T_1 | _io_mulAddA_0_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:580:{12,63}, :581:12] wire [52:0] _io_mulAddA_0_T_5 = cyc_B6_div ? sigA_PA : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:264:41, :348:28, :582:12] wire [52:0] _io_mulAddA_0_T_6 = _io_mulAddA_0_T_4 | _io_mulAddA_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:580:63, :581:63, :582:12] wire [33:0] _io_mulAddA_0_T_7 = zSigma1_B4[45:12]; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :583:19] wire [52:0] _io_mulAddA_0_T_8 = {_io_mulAddA_0_T_6[52:34], _io_mulAddA_0_T_6[33:0] | _io_mulAddA_0_T_7}; // @[DivSqrtRecF64_mulAddZ31.scala:581:63, :582:63, :583:19] wire _io_mulAddA_0_T_9 = cyc_B3 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:260:30, :283:35, :585:20] wire [45:0] _io_mulAddA_0_T_10 = sigXNU_B3_CX[57:12]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :585:48] wire [45:0] _io_mulAddA_0_T_11 = _io_mulAddA_0_T_9 ? _io_mulAddA_0_T_10 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:585:{12,20,48}] wire [52:0] _io_mulAddA_0_T_12 = {_io_mulAddA_0_T_8[52:46], _io_mulAddA_0_T_8[45:0] | _io_mulAddA_0_T_11}; // @[DivSqrtRecF64_mulAddZ31.scala:582:63, :583:67, :585:12] wire [32:0] _io_mulAddA_0_T_13 = sigXN_C[57:25]; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :586:43] wire [45:0] _io_mulAddA_0_T_14 = {_io_mulAddA_0_T_13, 13'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:586:{43,51}] wire [45:0] _io_mulAddA_0_T_15 = cyc_C4_div ? _io_mulAddA_0_T_14 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:292:29, :586:{12,51}] wire [52:0] _io_mulAddA_0_T_16 = {_io_mulAddA_0_T_12[52:46], _io_mulAddA_0_T_12[45:0] | _io_mulAddA_0_T_15}; // @[DivSqrtRecF64_mulAddZ31.scala:583:67, :585:63, :586:12] wire [45:0] _io_mulAddA_0_T_17 = {u_C_sqrt, 15'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :587:44] wire [45:0] _io_mulAddA_0_T_18 = cyc_C4_sqrt ? _io_mulAddA_0_T_17 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:298:30, :587:{12,44}] wire [52:0] _io_mulAddA_0_T_19 = {_io_mulAddA_0_T_16[52:46], _io_mulAddA_0_T_16[45:0] | _io_mulAddA_0_T_18}; // @[DivSqrtRecF64_mulAddZ31.scala:585:63, :586:63, :587:12] wire [52:0] _io_mulAddA_0_T_20 = cyc_C1_div ? sigB_PC : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :419:28, :588:12] wire [52:0] _io_mulAddA_0_T_21 = _io_mulAddA_0_T_19 | _io_mulAddA_0_T_20; // @[DivSqrtRecF64_mulAddZ31.scala:586:63, :587:63, :588:12] assign _io_mulAddA_0_T_22 = {1'h0, _io_mulAddA_0_T_21} | zComplSigT_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :587:63, :588:63] assign io_mulAddA_0_0 = _io_mulAddA_0_T_22; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :588:63] wire _io_latchMulAddB_0_T_1 = _io_latchMulAddB_0_T | cyc_B6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :591:{16,31}] wire _io_latchMulAddB_0_T_2 = _io_latchMulAddB_0_T_1 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :591:{31,46}] wire _io_latchMulAddB_0_T_3 = _io_latchMulAddB_0_T_2 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :591:{46,56}] wire _io_latchMulAddB_0_T_4 = _io_latchMulAddB_0_T_3 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :591:56, :592:25] assign _io_latchMulAddB_0_T_5 = _io_latchMulAddB_0_T_4 | cyc_C1; // @[DivSqrtRecF64_mulAddZ31.scala:289:30, :592:{25,35}] assign io_latchMulAddB_0_0 = _io_latchMulAddB_0_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :592:35] wire [51:0] _io_mulAddB_0_T = {r1_A1, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:538:27, :580:51, :594:31] wire [51:0] _io_mulAddB_0_T_1 = cyc_A1 ? _io_mulAddB_0_T : 52'h0; // @[DivSqrtRecF64_mulAddZ31.scala:234:30, :594:{12,31}] wire [50:0] _io_mulAddB_0_T_2 = {ESqrR1_B_sqrt, 19'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :595:39] wire [50:0] _io_mulAddB_0_T_3 = cyc_B7_sqrt ? _io_mulAddB_0_T_2 : 51'h0; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :595:{12,39}] wire [51:0] _io_mulAddB_0_T_4 = {_io_mulAddB_0_T_1[51], _io_mulAddB_0_T_1[50:0] | _io_mulAddB_0_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:594:{12,51}, :595:12] wire [52:0] _io_mulAddB_0_T_5 = {ER1_B_sqrt, 36'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :580:51, :596:36] wire [52:0] _io_mulAddB_0_T_6 = cyc_B6_sqrt ? _io_mulAddB_0_T_5 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:271:42, :596:{12,36}] wire [52:0] _io_mulAddB_0_T_7 = {1'h0, _io_mulAddB_0_T_4} | _io_mulAddB_0_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:594:51, :595:51, :596:12] wire [52:0] _io_mulAddB_0_T_8 = {_io_mulAddB_0_T_7[52:46], _io_mulAddB_0_T_7[45:0] | zSigma1_B4}; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :595:51, :596:51] wire [29:0] _io_mulAddB_0_T_9 = sqrSigma1_C[30:1]; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :598:37] wire [29:0] _io_mulAddB_0_T_10 = cyc_C6_sqrt ? _io_mulAddB_0_T_9 : 30'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :598:{12,37}] wire [52:0] _io_mulAddB_0_T_11 = {_io_mulAddB_0_T_8[52:30], _io_mulAddB_0_T_8[29:0] | _io_mulAddB_0_T_10}; // @[DivSqrtRecF64_mulAddZ31.scala:596:51, :597:55, :598:12] wire [32:0] _io_mulAddB_0_T_12 = cyc_C4 ? sqrSigma1_C : 33'h0; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :286:30, :599:12] wire [52:0] _io_mulAddB_0_T_13 = {_io_mulAddB_0_T_11[52:33], _io_mulAddB_0_T_11[32:0] | _io_mulAddB_0_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:597:55, :598:51, :599:12] assign _io_mulAddB_0_T_14 = {1'h0, _io_mulAddB_0_T_13} | zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :598:51, :599:51] assign io_mulAddB_0_0 = _io_mulAddB_0_T_14; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :599:51] wire _io_usingMulAdd_T = cyc_A4 | cyc_A3_div; // @[DivSqrtRecF64_mulAddZ31.scala:231:30, :236:29, :603:20] wire _io_usingMulAdd_T_1 = _io_usingMulAdd_T | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:238:29, :603:{20,34}] wire _io_usingMulAdd_T_2 = _io_usingMulAdd_T_1 | cyc_B10_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:252:36, :603:{34,48}] wire _io_usingMulAdd_T_3 = _io_usingMulAdd_T_2 | cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :603:48, :604:30] wire _io_usingMulAdd_T_4 = _io_usingMulAdd_T_3 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :604:{30,45}] wire _io_usingMulAdd_T_5 = _io_usingMulAdd_T_4 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :604:{45,60}] wire _io_usingMulAdd_T_6 = _io_usingMulAdd_T_5 | cyc_B5_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:272:42, :604:{60,70}] wire _io_usingMulAdd_T_7 = _io_usingMulAdd_T_6 | cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :604:70, :605:29] wire _io_usingMulAdd_T_8 = _io_usingMulAdd_T_7 | cyc_B2_div; // @[DivSqrtRecF64_mulAddZ31.scala:268:29, :605:{29,44}] wire _io_usingMulAdd_T_9 = _io_usingMulAdd_T_8 | cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :605:{44,58}] wire _io_usingMulAdd_T_10 = _io_usingMulAdd_T_9 | cyc_C4; // @[DivSqrtRecF64_mulAddZ31.scala:286:30, :605:{58,73}] wire _io_usingMulAdd_T_11 = cyc_A3 | cyc_A2_div; // @[DivSqrtRecF64_mulAddZ31.scala:232:30, :237:29, :607:20] wire _io_usingMulAdd_T_12 = _io_usingMulAdd_T_11 | cyc_B9_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:253:36, :607:{20,34}] wire _io_usingMulAdd_T_13 = _io_usingMulAdd_T_12 | cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :607:34, :608:29] wire _io_usingMulAdd_T_14 = _io_usingMulAdd_T_13 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:257:30, :608:{29,44}] wire _io_usingMulAdd_T_15 = _io_usingMulAdd_T_14 | cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :608:{44,54}] wire _io_usingMulAdd_T_16 = _io_usingMulAdd_T_15 | cyc_B4_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:273:42, :608:{54,64}] wire _io_usingMulAdd_T_17 = _io_usingMulAdd_T_16 | cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :608:64, :609:29] wire _io_usingMulAdd_T_18 = _io_usingMulAdd_T_17 | cyc_B1_div; // @[DivSqrtRecF64_mulAddZ31.scala:269:29, :609:{29,44}] wire _io_usingMulAdd_T_19 = _io_usingMulAdd_T_18 | cyc_C6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :609:{44,58}] wire _io_usingMulAdd_T_20 = _io_usingMulAdd_T_19 | cyc_C3; // @[DivSqrtRecF64_mulAddZ31.scala:287:30, :609:{58,73}] wire _io_usingMulAdd_T_21 = cyc_A2 | cyc_A1_div; // @[DivSqrtRecF64_mulAddZ31.scala:233:30, :238:29, :611:20] wire _io_usingMulAdd_T_22 = _io_usingMulAdd_T_21 | cyc_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:254:36, :611:{20,34}] wire _io_usingMulAdd_T_23 = _io_usingMulAdd_T_22 | cyc_B7_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:255:36, :611:34, :612:29] wire _io_usingMulAdd_T_24 = _io_usingMulAdd_T_23 | cyc_B5; // @[DivSqrtRecF64_mulAddZ31.scala:258:30, :612:{29,44}] wire _io_usingMulAdd_T_25 = _io_usingMulAdd_T_24 | cyc_B4; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :612:{44,54}] wire _io_usingMulAdd_T_26 = _io_usingMulAdd_T_25 | cyc_B3_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:274:30, :612:{54,64}] wire _io_usingMulAdd_T_27 = _io_usingMulAdd_T_26 | cyc_B1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:276:30, :612:64, :613:29] wire _io_usingMulAdd_T_28 = _io_usingMulAdd_T_27 | cyc_C5; // @[DivSqrtRecF64_mulAddZ31.scala:285:30, :613:{29,44}] wire _io_usingMulAdd_T_29 = _io_usingMulAdd_T_28 | cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :613:{44,54}] wire _io_usingMulAdd_T_30 = io_latchMulAddA_0_0 | cyc_B6; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :257:30, :615:31] wire _io_usingMulAdd_T_31 = _io_usingMulAdd_T_30 | cyc_B2_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:275:30, :615:{31,41}] wire [1:0] io_usingMulAdd_lo = {_io_usingMulAdd_T_29, _io_usingMulAdd_T_31}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :613:54, :615:41] wire [1:0] io_usingMulAdd_hi = {_io_usingMulAdd_T_10, _io_usingMulAdd_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12, :605:73, :609:73] assign _io_usingMulAdd_T_32 = {io_usingMulAdd_hi, io_usingMulAdd_lo}; // @[DivSqrtRecF64_mulAddZ31.scala:603:12] assign io_usingMulAdd_0 = _io_usingMulAdd_T_32; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :603:12] wire [104:0] _io_mulAddC_2_T = {sigX1_B, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :619:45] wire [104:0] _io_mulAddC_2_T_1 = cyc_B1 ? _io_mulAddC_2_T : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:262:30, :619:{12,45}] wire [103:0] _io_mulAddC_2_T_2 = {sigX1_B, 46'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :620:45] wire [103:0] _io_mulAddC_2_T_3 = cyc_C6_sqrt ? _io_mulAddC_2_T_2 : 104'h0; // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :620:{12,45}] wire [104:0] _io_mulAddC_2_T_4 = {_io_mulAddC_2_T_1[104], _io_mulAddC_2_T_1[103:0] | _io_mulAddC_2_T_3}; // @[DivSqrtRecF64_mulAddZ31.scala:619:{12,62}, :620:12] wire _io_mulAddC_2_T_5 = cyc_C4_sqrt | cyc_C2; // @[DivSqrtRecF64_mulAddZ31.scala:288:30, :298:30, :621:25] wire [104:0] _io_mulAddC_2_T_6 = {sigXN_C, 47'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :619:45, :621:45] wire [104:0] _io_mulAddC_2_T_7 = _io_mulAddC_2_T_5 ? _io_mulAddC_2_T_6 : 105'h0; // @[DivSqrtRecF64_mulAddZ31.scala:621:{12,25,45}] wire [104:0] _io_mulAddC_2_T_8 = _io_mulAddC_2_T_4 | _io_mulAddC_2_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:619:62, :620:62, :621:12] wire _io_mulAddC_2_T_9 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27] wire _io_mulAddC_2_T_10 = cyc_E3_div & _io_mulAddC_2_T_9; // @[DivSqrtRecF64_mulAddZ31.scala:313:29, :622:{24,27}] wire [53:0] _io_mulAddC_2_T_11 = {bit0FractA_PC, 53'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:126:30, :622:51] wire [53:0] _io_mulAddC_2_T_12 = _io_mulAddC_2_T_10 ? _io_mulAddC_2_T_11 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:622:{12,24,51}] wire [104:0] _io_mulAddC_2_T_13 = {_io_mulAddC_2_T_8[104:54], _io_mulAddC_2_T_8[53:0] | _io_mulAddC_2_T_12}; // @[DivSqrtRecF64_mulAddZ31.scala:620:62, :621:62, :622:12] wire _io_mulAddC_2_T_14 = sExp_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :624:25] wire _io_mulAddC_2_T_15 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25] wire _io_mulAddC_2_T_18 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:39] wire _io_mulAddC_2_T_20 = sigB_PC[0]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :625:25, :626:54] wire [1:0] _io_mulAddC_2_T_16 = {_io_mulAddC_2_T_15, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:625:{25,28}] wire _io_mulAddC_2_T_17 = sigB_PC[1]; // @[DivSqrtRecF64_mulAddZ31.scala:419:28, :626:26] wire _io_mulAddC_2_T_19 = _io_mulAddC_2_T_17 ^ _io_mulAddC_2_T_18; // @[DivSqrtRecF64_mulAddZ31.scala:626:{26,30,39}] wire [1:0] _io_mulAddC_2_T_21 = {_io_mulAddC_2_T_19, _io_mulAddC_2_T_20}; // @[DivSqrtRecF64_mulAddZ31.scala:626:{30,44,54}] wire [1:0] _io_mulAddC_2_T_22 = _io_mulAddC_2_T_14 ? _io_mulAddC_2_T_16 : _io_mulAddC_2_T_21; // @[DivSqrtRecF64_mulAddZ31.scala:624:{17,25}, :625:28, :626:44] wire _io_mulAddC_2_T_23 = sigT_E[0]; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :627:28] wire _io_mulAddC_2_T_24 = ~_io_mulAddC_2_T_23; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,28}] wire [1:0] _io_mulAddC_2_T_25 = {_io_mulAddC_2_T_24, 1'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:{20,32}] wire [1:0] _io_mulAddC_2_T_26 = _io_mulAddC_2_T_22 ^ _io_mulAddC_2_T_25; // @[DivSqrtRecF64_mulAddZ31.scala:624:17, :627:{16,32}] wire [55:0] _io_mulAddC_2_T_27 = {_io_mulAddC_2_T_26, 54'h0}; // @[DivSqrtRecF64_mulAddZ31.scala:627:16, :628:14] wire [55:0] _io_mulAddC_2_T_28 = cyc_E3_sqrt ? _io_mulAddC_2_T_27 : 56'h0; // @[DivSqrtRecF64_mulAddZ31.scala:318:30, :623:12, :628:14] assign _io_mulAddC_2_T_29 = {_io_mulAddC_2_T_13[104:56], _io_mulAddC_2_T_13[55:0] | _io_mulAddC_2_T_28}; // @[DivSqrtRecF64_mulAddZ31.scala:621:62, :622:62, :623:12] assign io_mulAddC_2_0 = _io_mulAddC_2_T_29; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :622:62] wire [31:0] ESqrR1_B8_sqrt = io_mulAddResult_3_0[103:72]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :632:43] wire [45:0] _zSigma1_B4_T = io_mulAddResult_3_0[90:45]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :633:49] wire [45:0] _zSigma1_B4_T_1 = ~_zSigma1_B4_T; // @[DivSqrtRecF64_mulAddZ31.scala:633:{31,49}] assign _zSigma1_B4_T_2 = cyc_B4 ? _zSigma1_B4_T_1 : 46'h0; // @[DivSqrtRecF64_mulAddZ31.scala:259:30, :633:{22,31}] assign zSigma1_B4 = _zSigma1_B4_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:157:34, :633:22] wire [32:0] sqrSigma1_B1 = io_mulAddResult_3_0[79:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :634:41] assign _sigXNU_B3_CX_T = io_mulAddResult_3_0[104:47]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :635:38] assign sigXNU_B3_CX = _sigXNU_B3_CX_T; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :635:38] wire _E_C1_div_T = io_mulAddResult_3_0[104]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :636:39] wire E_C1_div = ~_E_C1_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:636:{20,39}] wire _zComplSigT_C1_T = ~E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:636:20, :638:28] wire _zComplSigT_C1_T_1 = cyc_C1_div & _zComplSigT_C1_T; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :638:{25,28}] wire _zComplSigT_C1_T_2 = _zComplSigT_C1_T_1 | cyc_C1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :638:{25,40}] wire [53:0] _zComplSigT_C1_T_3 = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31] wire [53:0] _zComplSigT_C1_sqrt_T = io_mulAddResult_3_0[104:51]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :639:31, :644:44] wire [53:0] _zComplSigT_C1_T_4 = ~_zComplSigT_C1_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:639:{13,31}] wire [53:0] _zComplSigT_C1_T_5 = _zComplSigT_C1_T_2 ? _zComplSigT_C1_T_4 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:638:{12,40}, :639:13] wire _zComplSigT_C1_T_6 = cyc_C1_div & E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:295:29, :636:20, :642:24] wire [52:0] _zComplSigT_C1_T_7 = io_mulAddResult_3_0[102:50]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :642:55] wire [52:0] _zComplSigT_C1_T_8 = ~_zComplSigT_C1_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:642:{37,55}] wire [52:0] _zComplSigT_C1_T_9 = _zComplSigT_C1_T_6 ? _zComplSigT_C1_T_8 : 53'h0; // @[DivSqrtRecF64_mulAddZ31.scala:642:{12,24,37}] assign _zComplSigT_C1_T_10 = {_zComplSigT_C1_T_5[53], _zComplSigT_C1_T_5[52:0] | _zComplSigT_C1_T_9}; // @[DivSqrtRecF64_mulAddZ31.scala:638:12, :641:11, :642:12] assign zComplSigT_C1 = _zComplSigT_C1_T_10; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :641:11] wire [53:0] _zComplSigT_C1_sqrt_T_1 = ~_zComplSigT_C1_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:644:{26,44}] assign _zComplSigT_C1_sqrt_T_2 = cyc_C1_sqrt ? _zComplSigT_C1_sqrt_T_1 : 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:301:30, :644:{12,26}] assign zComplSigT_C1_sqrt = _zComplSigT_C1_sqrt_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:159:34, :644:12] wire [53:0] sigT_C1 = ~zComplSigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:160:34, :648:19] wire [55:0] remT_E2 = io_mulAddResult_3_0[55:0]; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :649:36] wire [30:0] _u_C_sqrt_T = sigXNU_B3_CX[56:26]; // @[DivSqrtRecF64_mulAddZ31.scala:158:34, :665:33] wire _isNegRemT_E_T = remT_E2[55]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:47] wire _isNegRemT_E_T_1 = remT_E2[53]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :673:61] wire _isNegRemT_E_T_2 = sqrtOp_PC ? _isNegRemT_E_T : _isNegRemT_E_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :673:{27,47,61}] wire [53:0] _isZeroRemT_E_T = remT_E2[53:0]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :675:21] wire _isZeroRemT_E_T_1 = _isZeroRemT_E_T == 54'h0; // @[DivSqrtRecF64_mulAddZ31.scala:675:{21,29}] wire _isZeroRemT_E_T_2 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :676:18] wire [1:0] _isZeroRemT_E_T_3 = remT_E2[55:54]; // @[DivSqrtRecF64_mulAddZ31.scala:649:36, :676:41] wire _isZeroRemT_E_T_4 = _isZeroRemT_E_T_3 == 2'h0; // @[DivSqrtRecF64_mulAddZ31.scala:676:{41,50}] wire _isZeroRemT_E_T_5 = _isZeroRemT_E_T_2 | _isZeroRemT_E_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:676:{18,30,50}] wire _isZeroRemT_E_T_6 = _isZeroRemT_E_T_1 & _isZeroRemT_E_T_5; // @[DivSqrtRecF64_mulAddZ31.scala:675:{29,38}, :676:30] wire _trueLtX_E1_T = ~isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :686:24] wire _trueLtX_E1_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41] wire _trueLtX_E1_T_2 = _trueLtX_E1_T & _trueLtX_E1_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:686:{24,38,41}] wire trueLtX_E1 = sqrtOp_PC ? _trueLtX_E1_T_2 : isNegRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :145:30, :686:{12,38}] wire [13:0] _sExpP1_PC_T = {sExp_PC[12], sExp_PC} + 14'h1; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :694:29] wire [12:0] _sExpP1_PC_T_1 = _sExpP1_PC_T[12:0]; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [12:0] sExpP1_PC = _sExpP1_PC_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:694:29] wire [54:0] _GEN_0 = {1'h0, sigT_E}; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :695:27] wire [54:0] sigTP1_E = _GEN_0 + 55'h1; // @[DivSqrtRecF64_mulAddZ31.scala:695:27] wire _io_rawOutValid_div_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :699:42] assign _io_rawOutValid_div_T_1 = leaving_PC & _io_rawOutValid_div_T; // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :699:{39,42}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :699:39] assign _io_rawOutValid_sqrt_T = leaving_PC & sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :155:26, :700:39] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :700:39] assign _io_invalidExc_T = majorExc_PC & isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :121:30, :702:40] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :702:40] wire _io_infiniteExc_T = ~isNaN_PC; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :418:25, :703:43] assign _io_infiniteExc_T_1 = majorExc_PC & _io_infiniteExc_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :703:{40,43}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :703:40] wire _io_rawOut_sExp_T = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :709:13] wire _io_rawOut_sExp_T_1 = _io_rawOut_sExp_T & E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :709:{13,25}] wire [12:0] _io_rawOut_sExp_T_2 = _io_rawOut_sExp_T_1 ? sExp_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :709:{12,25}] wire _io_rawOut_sExp_T_3 = ~sqrtOp_PC; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :294:32, :710:13] wire _io_rawOut_sExp_T_4 = ~E_E_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :622:27, :710:28] wire _io_rawOut_sExp_T_5 = _io_rawOut_sExp_T_3 & _io_rawOut_sExp_T_4; // @[DivSqrtRecF64_mulAddZ31.scala:710:{13,25,28}] wire [12:0] _io_rawOut_sExp_T_6 = _io_rawOut_sExp_T_5 ? sExpP1_PC : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:694:29, :710:{12,25}] wire [12:0] _io_rawOut_sExp_T_7 = _io_rawOut_sExp_T_2 | _io_rawOut_sExp_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:709:{12,72}, :710:12] wire [12:0] _io_rawOut_sExp_T_8 = _io_rawOut_sExp_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:709:72] wire [11:0] _io_rawOut_sExp_T_9 = sExp_PC[12:1]; // @[DivSqrtRecF64_mulAddZ31.scala:125:30, :711:47] wire [12:0] _io_rawOut_sExp_T_10 = {_io_rawOut_sExp_T_9[11], _io_rawOut_sExp_T_9} + 13'h400; // @[DivSqrtRecF64_mulAddZ31.scala:711:{47,52}] wire [12:0] _io_rawOut_sExp_T_11 = sqrtOp_PC ? _io_rawOut_sExp_T_10 : 13'h0; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :711:{12,52}] wire [12:0] _io_rawOut_sExp_T_12 = _io_rawOut_sExp_T_8 | _io_rawOut_sExp_T_11; // @[DivSqrtRecF64_mulAddZ31.scala:709:72, :710:72, :711:12] assign _io_rawOut_sExp_T_13 = _io_rawOut_sExp_T_12; // @[DivSqrtRecF64_mulAddZ31.scala:710:72] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T_13; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :710:72] wire [54:0] _io_rawOut_sig_T = trueLtX_E1 ? _GEN_0 : sigTP1_E; // @[DivSqrtRecF64_mulAddZ31.scala:686:12, :695:27, :712:25] wire _io_rawOut_sig_T_1 = ~isZeroRemT_E; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :686:41, :712:59] assign _io_rawOut_sig_T_2 = {_io_rawOut_sig_T, _io_rawOut_sig_T_1}; // @[DivSqrtRecF64_mulAddZ31.scala:712:{25,56,59}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :712:56] wire _T_18 = entering_PA_normalCase_sqrt | cyc_A6_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:211:50, :225:35, :551:21] always @(posedge clock) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (reset) begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] cycleNum_A <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:86:34] cycleNum_B <= 4'h0; // @[DivSqrtRecF64_mulAddZ31.scala:87:34] cycleNum_C <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:88:34] cycleNum_E <= 3'h0; // @[DivSqrtRecF64_mulAddZ31.scala:89:34] valid_PA <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:91:34] valid_PB <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:104:34] valid_PC <= 1'h0; // @[DivSqrtRecF64_mulAddZ31.scala:117:34] end else begin // @[DivSqrtRecF64_mulAddZ31.scala:51:7] if (|{entering_PA_normalCase, cycleNum_A}) // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :213:36, :217:{34,49}] cycleNum_A <= _cycleNum_A_T_7; // @[DivSqrtRecF64_mulAddZ31.scala:86:34, :220:69] if (|{cyc_A1, cycleNum_B}) // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :234:30, :244:{18,33}] cycleNum_B <= _cycleNum_B_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:87:34, :246:16] if (|{cyc_B1, cycleNum_C}) // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :262:30, :278:{18,33}] cycleNum_C <= _cycleNum_C_T_3; // @[DivSqrtRecF64_mulAddZ31.scala:88:34, :280:16] if (|{cyc_C1, cycleNum_E}) // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :289:30, :303:{18,33}] cycleNum_E <= _cycleNum_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:89:34, :304:26] if (entering_PA | leaving_PA) // @[DivSqrtRecF64_mulAddZ31.scala:153:26, :325:32, :327:23] valid_PA <= entering_PA; // @[DivSqrtRecF64_mulAddZ31.scala:91:34, :325:32] if (entering_PB | leaving_PB) // @[DivSqrtRecF64_mulAddZ31.scala:154:26, :364:37, :366:23] valid_PB <= entering_PB; // @[DivSqrtRecF64_mulAddZ31.scala:104:34, :364:37] if (entering_PC | leaving_PC) // @[DivSqrtRecF64_mulAddZ31.scala:155:26, :398:37, :400:23] valid_PC <= entering_PC; // @[DivSqrtRecF64_mulAddZ31.scala:117:34, :398:37] end if (entering_PA) begin // @[DivSqrtRecF64_mulAddZ31.scala:325:32] sqrtOp_PA <= io_sqrtOp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :92:30] majorExc_PA <= majorExc_S; // @[DivSqrtRecF64_mulAddZ31.scala:93:30, :176:12] isNaN_PA <= isNaN_S; // @[DivSqrtRecF64_mulAddZ31.scala:95:30, :183:12] isInf_PA <= isInf_S; // @[DivSqrtRecF64_mulAddZ31.scala:96:30, :187:23] isZero_PA <= isZero_S; // @[DivSqrtRecF64_mulAddZ31.scala:97:30, :188:23] sign_PA <= sign_S; // @[DivSqrtRecF64_mulAddZ31.scala:98:30, :189:47] end if (entering_PA_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:213:36] sExp_PA <= _sExp_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :339:23] fractB_PA <= _fractB_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :340:32] roundingMode_PA <= io_roundingMode_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7, :102:30] end if (entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50] fractA_PA <= _fractA_PA_T; // @[DivSqrtRecF64_mulAddZ31.scala:101:30, :344:32] if (entering_PB) begin // @[DivSqrtRecF64_mulAddZ31.scala:364:37] sqrtOp_PB <= _sqrtOp_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:105:30, :370:27] majorExc_PB <= _majorExc_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:106:30, :371:27] isNaN_PB <= _isNaN_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:108:30, :372:27] isInf_PB <= _isInf_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:109:30, :373:27] isZero_PB <= _isZero_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:110:30, :374:27] sign_PB <= _sign_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:111:30, :375:27] end if (entering_PB_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:363:35] sExp_PB <= sExp_PA; // @[DivSqrtRecF64_mulAddZ31.scala:99:30, :112:30] bit0FractA_PB <= _bit0FractA_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :379:37] fractB_PB <= fractB_PA; // @[DivSqrtRecF64_mulAddZ31.scala:100:30, :114:30] roundingMode_PB <= _roundingMode_PB_T; // @[DivSqrtRecF64_mulAddZ31.scala:115:30, :381:31] end if (entering_PC) begin // @[DivSqrtRecF64_mulAddZ31.scala:398:37] sqrtOp_PC <= _sqrtOp_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:118:30, :404:27] majorExc_PC <= _majorExc_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:119:30, :405:27] isNaN_PC <= _isNaN_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:121:30, :406:27] isInf_PC <= _isInf_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:122:30, :407:27] isZero_PC <= _isZero_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:123:30, :408:27] sign_PC <= _sign_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:124:30, :409:27] end if (entering_PC_normalCase) begin // @[DivSqrtRecF64_mulAddZ31.scala:397:35] sExp_PC <= sExp_PB; // @[DivSqrtRecF64_mulAddZ31.scala:112:30, :125:30] bit0FractA_PC <= bit0FractA_PB; // @[DivSqrtRecF64_mulAddZ31.scala:113:30, :126:30] fractB_PC <= fractB_PB; // @[DivSqrtRecF64_mulAddZ31.scala:114:30, :127:30] roundingMode_PC <= _roundingMode_PC_T; // @[DivSqrtRecF64_mulAddZ31.scala:128:30, :415:31] end if (cyc_A6_sqrt | entering_PA_normalCase_div) // @[DivSqrtRecF64_mulAddZ31.scala:210:50, :225:35, :541:23] fractR0_A <= _fractR0_A_T[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:130:30, :542:{19,39}] if (cyc_A5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:226:35] hiSqrR0_A_sqrt <= _hiSqrR0_A_sqrt_T[9:0]; // @[DivSqrtRecF64_mulAddZ31.scala:132:30, :545:{24,40}] if (cyc_A4_sqrt | cyc_A3) // @[DivSqrtRecF64_mulAddZ31.scala:227:35, :232:30, :547:23] partNegSigma0_A <= _partNegSigma0_A_T_1[20:0]; // @[DivSqrtRecF64_mulAddZ31.scala:133:30, :548:{25,31}] if (_T_18 | cyc_A5_sqrt | cyc_A4 | cyc_A3 | cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :232:30, :233:30, :551:{21,36,51,61,71}] nextMulAdd9A_A <= _nextMulAdd9A_A_T_13[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:134:30, :553:24, :558:64] if (_T_18 | cyc_A5_sqrt | cyc_A4 | cyc_A2) // @[DivSqrtRecF64_mulAddZ31.scala:226:35, :231:30, :233:30, :551:21, :561:{38,53,63}] nextMulAdd9B_A <= _nextMulAdd9B_A_T_12[8:0]; // @[DivSqrtRecF64_mulAddZ31.scala:135:30, :562:24, :567:69] if (cyc_A1_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:242:30] ER1_B_sqrt <= ER1_A1_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:136:30, :539:26] if (cyc_B8_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:254:36] ESqrR1_B_sqrt <= ESqrR1_B8_sqrt; // @[DivSqrtRecF64_mulAddZ31.scala:138:30, :632:43] if (cyc_B3) // @[DivSqrtRecF64_mulAddZ31.scala:260:30] sigX1_B <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:139:30, :158:34] if (cyc_B1) // @[DivSqrtRecF64_mulAddZ31.scala:262:30] sqrSigma1_C <= sqrSigma1_B1; // @[DivSqrtRecF64_mulAddZ31.scala:140:30, :634:41] if (cyc_C6_sqrt | cyc_C5_div | cyc_C3_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:283:35, :291:29, :299:30, :661:{23,37}] sigXN_C <= sigXNU_B3_CX; // @[DivSqrtRecF64_mulAddZ31.scala:141:30, :158:34] if (cyc_C5_sqrt) // @[DivSqrtRecF64_mulAddZ31.scala:297:30] u_C_sqrt <= _u_C_sqrt_T; // @[DivSqrtRecF64_mulAddZ31.scala:142:30, :665:33] if (cyc_C1) begin // @[DivSqrtRecF64_mulAddZ31.scala:289:30] E_E_div <= E_C1_div; // @[DivSqrtRecF64_mulAddZ31.scala:143:30, :636:20] sigT_E <= sigT_C1; // @[DivSqrtRecF64_mulAddZ31.scala:144:30, :648:19] end if (cyc_E2) begin // @[DivSqrtRecF64_mulAddZ31.scala:309:30] isNegRemT_E <= _isNegRemT_E_T_2; // @[DivSqrtRecF64_mulAddZ31.scala:145:30, :673:27] isZeroRemT_E <= _isZeroRemT_E_T_6; // @[DivSqrtRecF64_mulAddZ31.scala:146:30, :675:38] end always @(posedge) assign io_inReady_div = io_inReady_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_inReady_sqrt = io_inReady_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_usingMulAdd = io_usingMulAdd_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddA_0 = io_latchMulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddA_0 = io_mulAddA_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_latchMulAddB_0 = io_latchMulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddB_0 = io_mulAddB_0_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_mulAddC_2 = io_mulAddC_2_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecF64_mulAddZ31.scala:51:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module SourceD : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}, pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip pb_beat : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, flip rel_beat : { data : UInt<32>, corrupt : UInt<1>}, bs_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<4>, mask : UInt<1>}}, flip bs_rdat : { data : UInt<32>}, bs_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<4>, mask : UInt<1>}}, bs_wdat : { data : UInt<32>}, flip evict_req : { set : UInt<10>, way : UInt<3>}, evict_safe : UInt<1>, flip grant_req : { set : UInt<10>, way : UInt<3>}, grant_safe : UInt<1>} wire s1_valid : UInt<1> wire s2_valid : UInt<1> wire s3_valid : UInt<1> wire s2_ready : UInt<1> wire s3_ready : UInt<1> wire s4_ready : UInt<1> regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_block_r : UInt<1>, clock, reset, UInt<1>(0h0) regreset s1_counter : UInt<4>, clock, reset, UInt<4>(0h0) node _s1_req_reg_T = eq(busy, UInt<1>(0h0)) node _s1_req_reg_T_1 = and(_s1_req_reg_T, io.req.valid) reg s1_req_reg : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when _s1_req_reg_T_1 : connect s1_req_reg, io.req.bits node _s1_req_T = eq(busy, UInt<1>(0h0)) node s1_req = mux(_s1_req_T, io.req.bits, s1_req_reg) wire s1_x_bypass : UInt<1> node _s1_latch_bypass_T = or(busy, io.req.valid) node _s1_latch_bypass_T_1 = eq(_s1_latch_bypass_T, UInt<1>(0h0)) node _s1_latch_bypass_T_2 = or(_s1_latch_bypass_T_1, s2_ready) reg s1_latch_bypass : UInt<1>, clock connect s1_latch_bypass, _s1_latch_bypass_T_2 reg s1_bypass_r : UInt<1>, clock when s1_latch_bypass : connect s1_bypass_r, s1_x_bypass node s1_bypass = mux(s1_latch_bypass, s1_x_bypass, s1_bypass_r) node _s1_mask_sizeOH_T = or(s1_req.size, UInt<2>(0h0)) node s1_mask_sizeOH_shiftAmount = bits(_s1_mask_sizeOH_T, 0, 0) node _s1_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_mask_sizeOH_shiftAmount) node _s1_mask_sizeOH_T_2 = bits(_s1_mask_sizeOH_T_1, 1, 0) node s1_mask_sizeOH = or(_s1_mask_sizeOH_T_2, UInt<3>(0h7)) node _s1_mask_T = not(s1_bypass) node s1_mask = and(UInt<1>(0h1), _s1_mask_T) node _s1_grant_T = eq(s1_req.opcode, UInt<3>(0h6)) node _s1_grant_T_1 = eq(s1_req.param, UInt<2>(0h2)) node _s1_grant_T_2 = and(_s1_grant_T, _s1_grant_T_1) node _s1_grant_T_3 = eq(s1_req.opcode, UInt<3>(0h7)) node s1_grant = or(_s1_grant_T_2, _s1_grant_T_3) node _s1_need_r_T = orr(s1_mask) node _s1_need_r_T_1 = and(_s1_need_r_T, s1_req.prio[0]) node _s1_need_r_T_2 = neq(s1_req.opcode, UInt<3>(0h5)) node _s1_need_r_T_3 = and(_s1_need_r_T_1, _s1_need_r_T_2) node _s1_need_r_T_4 = eq(s1_grant, UInt<1>(0h0)) node _s1_need_r_T_5 = and(_s1_need_r_T_3, _s1_need_r_T_4) node _s1_need_r_T_6 = neq(s1_req.opcode, UInt<1>(0h0)) node _s1_need_r_T_7 = lt(s1_req.size, UInt<2>(0h2)) node _s1_need_r_T_8 = or(_s1_need_r_T_6, _s1_need_r_T_7) node s1_need_r = and(_s1_need_r_T_5, _s1_need_r_T_8) node _s1_valid_r_T = or(busy, io.req.valid) node _s1_valid_r_T_1 = and(_s1_valid_r_T, s1_need_r) node _s1_valid_r_T_2 = eq(s1_block_r, UInt<1>(0h0)) node s1_valid_r = and(_s1_valid_r_T_1, _s1_valid_r_T_2) node _s1_need_pb_T = bits(s1_req.opcode, 2, 2) node _s1_need_pb_T_1 = eq(_s1_need_pb_T, UInt<1>(0h0)) node _s1_need_pb_T_2 = bits(s1_req.opcode, 0, 0) node s1_need_pb = mux(s1_req.prio[0], _s1_need_pb_T_1, _s1_need_pb_T_2) node _s1_single_T = eq(s1_req.opcode, UInt<3>(0h5)) node _s1_single_T_1 = or(_s1_single_T, s1_grant) node _s1_single_T_2 = eq(s1_req.opcode, UInt<3>(0h6)) node s1_single = mux(s1_req.prio[0], _s1_single_T_1, _s1_single_T_2) node s1_retires = eq(s1_single, UInt<1>(0h0)) node _s1_beats1_T = dshl(UInt<6>(0h3f), s1_req.size) node _s1_beats1_T_1 = bits(_s1_beats1_T, 5, 0) node _s1_beats1_T_2 = not(_s1_beats1_T_1) node _s1_beats1_T_3 = shr(_s1_beats1_T_2, 2) node s1_beats1 = mux(s1_single, UInt<1>(0h0), _s1_beats1_T_3) node _s1_beat_T = shr(s1_req.offset, 2) node s1_beat = or(_s1_beat_T, s1_counter) node s1_last = eq(s1_counter, s1_beats1) node s1_first = eq(s1_counter, UInt<1>(0h0)) node _T = eq(s1_latch_bypass, UInt<1>(0h0)) node _T_1 = or(busy, io.req.valid) node _T_2 = eq(s1_need_r, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) connect io.bs_radr.valid, s1_valid_r connect io.bs_radr.bits.noop, UInt<1>(0h0) connect io.bs_radr.bits.way, s1_req.way connect io.bs_radr.bits.set, s1_req.set connect io.bs_radr.bits.beat, s1_beat connect io.bs_radr.bits.mask, s1_mask node _T_4 = eq(io.bs_radr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_radr.valid, _T_4) inst queue of Queue3_BankedStoreInnerDecoded connect queue.clock, clock connect queue.reset, reset node _queue_io_enq_valid_T = and(io.bs_radr.ready, io.bs_radr.valid) reg queue_io_enq_valid_REG : UInt<1>, clock connect queue_io_enq_valid_REG, _queue_io_enq_valid_T reg queue_io_enq_valid_REG_1 : UInt<1>, clock connect queue_io_enq_valid_REG_1, queue_io_enq_valid_REG connect queue.io.enq.valid, queue_io_enq_valid_REG_1 connect queue.io.enq.bits.data, io.bs_rdat.data node _T_6 = eq(queue.io.enq.valid, UInt<1>(0h0)) node _T_7 = or(_T_6, queue.io.enq.ready) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:123 assert (!queue.io.enq.valid || queue.io.enq.ready)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert node _T_11 = eq(queue.io.enq.ready, UInt<1>(0h0)) node _T_12 = and(io.bs_radr.ready, io.bs_radr.valid) when _T_12 : connect s1_block_r, UInt<1>(0h1) when io.req.valid : connect busy, UInt<1>(0h1) node _T_13 = and(s1_valid, s2_ready) when _T_13 : node _s1_counter_T = add(s1_counter, UInt<1>(0h1)) node _s1_counter_T_1 = tail(_s1_counter_T, 1) connect s1_counter, _s1_counter_T_1 connect s1_block_r, UInt<1>(0h0) when s1_last : connect s1_counter, UInt<1>(0h0) connect busy, UInt<1>(0h0) node _T_14 = eq(s2_ready, UInt<1>(0h0)) node _T_15 = and(s1_valid, _T_14) node _io_req_ready_T = eq(busy, UInt<1>(0h0)) connect io.req.ready, _io_req_ready_T node _s1_valid_T = or(busy, io.req.valid) node _s1_valid_T_1 = eq(s1_valid_r, UInt<1>(0h0)) node _s1_valid_T_2 = or(_s1_valid_T_1, io.bs_radr.ready) node _s1_valid_T_3 = and(_s1_valid_T, _s1_valid_T_2) connect s1_valid, _s1_valid_T_3 node s2_latch = and(s1_valid, s2_ready) regreset s2_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_valid_pb : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_beat : UInt<4>, clock when s2_latch : connect s2_beat, s1_beat reg s2_bypass : UInt<1>, clock when s2_latch : connect s2_bypass, s1_bypass reg s2_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s2_latch : connect s2_req, s1_req reg s2_last : UInt<1>, clock when s2_latch : connect s2_last, s1_last reg s2_need_r : UInt<1>, clock when s2_latch : connect s2_need_r, s1_need_r reg s2_need_pb : UInt<1>, clock when s2_latch : connect s2_need_pb, s1_need_pb reg s2_retires : UInt<1>, clock when s2_latch : connect s2_retires, s1_retires node _s2_need_d_T = eq(s1_need_pb, UInt<1>(0h0)) node _s2_need_d_T_1 = or(_s2_need_d_T, s1_first) reg s2_need_d : UInt<1>, clock when s2_latch : connect s2_need_d, _s2_need_d_T_1 wire s2_pdata_raw : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>} reg s2_pdata_r : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s2_valid_pb : connect s2_pdata_r, s2_pdata_raw node s2_pdata = mux(s2_valid_pb, s2_pdata_raw, s2_pdata_r) node _s2_pdata_raw_data_T = mux(s2_req.prio[0], io.pb_beat.data, io.rel_beat.data) connect s2_pdata_raw.data, _s2_pdata_raw_data_T node _s2_pdata_raw_mask_T = not(UInt<4>(0h0)) node _s2_pdata_raw_mask_T_1 = mux(s2_req.prio[0], io.pb_beat.mask, _s2_pdata_raw_mask_T) connect s2_pdata_raw.mask, _s2_pdata_raw_mask_T_1 node _s2_pdata_raw_corrupt_T = mux(s2_req.prio[0], io.pb_beat.corrupt, io.rel_beat.corrupt) connect s2_pdata_raw.corrupt, _s2_pdata_raw_corrupt_T node _io_pb_pop_valid_T = and(s2_valid_pb, s2_req.prio[0]) connect io.pb_pop.valid, _io_pb_pop_valid_T connect io.pb_pop.bits.index, s2_req.put connect io.pb_pop.bits.last, s2_last node _io_rel_pop_valid_T = eq(s2_req.prio[0], UInt<1>(0h0)) node _io_rel_pop_valid_T_1 = and(s2_valid_pb, _io_rel_pop_valid_T) connect io.rel_pop.valid, _io_rel_pop_valid_T_1 connect io.rel_pop.bits.index, s2_req.put connect io.rel_pop.bits.last, s2_last node _T_16 = eq(io.pb_pop.ready, UInt<1>(0h0)) node _T_17 = and(io.pb_pop.valid, _T_16) node pb_ready = mux(s2_req.prio[0], io.pb_pop.ready, io.rel_pop.ready) when pb_ready : connect s2_valid_pb, UInt<1>(0h0) node _T_18 = and(s2_valid, s3_ready) when _T_18 : connect s2_full, UInt<1>(0h0) when s2_latch : connect s2_valid_pb, s1_need_pb when s2_latch : connect s2_full, UInt<1>(0h1) node _T_19 = eq(s3_ready, UInt<1>(0h0)) node _T_20 = and(s2_valid, _T_19) node _s2_valid_T = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_valid_T_1 = or(_s2_valid_T, pb_ready) node _s2_valid_T_2 = and(s2_full, _s2_valid_T_1) connect s2_valid, _s2_valid_T_2 node _s2_ready_T = eq(s2_full, UInt<1>(0h0)) node _s2_ready_T_1 = eq(s2_valid_pb, UInt<1>(0h0)) node _s2_ready_T_2 = or(_s2_ready_T_1, pb_ready) node _s2_ready_T_3 = and(s3_ready, _s2_ready_T_2) node _s2_ready_T_4 = or(_s2_ready_T, _s2_ready_T_3) connect s2_ready, _s2_ready_T_4 node s3_latch = and(s2_valid, s3_ready) regreset s3_full : UInt<1>, clock, reset, UInt<1>(0h0) regreset s3_valid_d : UInt<1>, clock, reset, UInt<1>(0h0) reg s3_beat : UInt<4>, clock when s3_latch : connect s3_beat, s2_beat reg s3_bypass : UInt<1>, clock when s3_latch : connect s3_bypass, s2_bypass reg s3_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s3_latch : connect s3_req, s2_req node s3_adjusted_opcode = mux(s3_req.bad, UInt<3>(0h4), s3_req.opcode) reg s3_last : UInt<1>, clock when s3_latch : connect s3_last, s2_last reg s3_pdata : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s3_latch : connect s3_pdata, s2_pdata reg s3_need_pb : UInt<1>, clock when s3_latch : connect s3_need_pb, s2_need_pb reg s3_retires : UInt<1>, clock when s3_latch : connect s3_retires, s2_retires reg s3_need_r : UInt<1>, clock when s3_latch : connect s3_need_r, s2_need_r node _s3_acq_T = eq(s3_req.opcode, UInt<3>(0h6)) node _s3_acq_T_1 = eq(s3_req.opcode, UInt<3>(0h7)) node s3_acq = or(_s3_acq_T, _s3_acq_T_1) wire s3_bypass_data : UInt node _s3_rdata_T = bits(s3_bypass, 0, 0) node _s3_rdata_T_1 = bits(s3_bypass_data, 31, 0) node _s3_rdata_T_2 = bits(queue.io.deq.bits.data, 31, 0) node s3_rdata = mux(_s3_rdata_T, _s3_rdata_T_1, _s3_rdata_T_2) node _grant_T = eq(s3_req.param, UInt<2>(0h2)) node grant = mux(_grant_T, UInt<3>(0h4), UInt<3>(0h5)) wire resp_opcode : UInt<3>[8] connect resp_opcode[0], UInt<1>(0h0) connect resp_opcode[1], UInt<1>(0h0) connect resp_opcode[2], UInt<1>(0h1) connect resp_opcode[3], UInt<1>(0h1) connect resp_opcode[4], UInt<1>(0h1) connect resp_opcode[5], UInt<2>(0h2) connect resp_opcode[6], grant connect resp_opcode[7], UInt<3>(0h4) wire d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect io.d, d connect d.valid, s3_valid_d node _d_bits_opcode_T = mux(s3_req.prio[0], resp_opcode[s3_req.opcode], UInt<3>(0h6)) connect d.bits.opcode, _d_bits_opcode_T node _d_bits_param_T = and(s3_req.prio[0], s3_acq) node _d_bits_param_T_1 = neq(s3_req.param, UInt<2>(0h0)) node _d_bits_param_T_2 = mux(_d_bits_param_T_1, UInt<2>(0h0), UInt<2>(0h1)) node _d_bits_param_T_3 = mux(_d_bits_param_T, _d_bits_param_T_2, UInt<1>(0h0)) connect d.bits.param, _d_bits_param_T_3 connect d.bits.size, s3_req.size connect d.bits.source, s3_req.source connect d.bits.sink, s3_req.sink connect d.bits.denied, s3_req.bad connect d.bits.data, s3_rdata node _d_bits_corrupt_T = bits(d.bits.opcode, 0, 0) node _d_bits_corrupt_T_1 = and(s3_req.bad, _d_bits_corrupt_T) connect d.bits.corrupt, _d_bits_corrupt_T_1 node _queue_io_deq_ready_T = and(s3_valid, s4_ready) node _queue_io_deq_ready_T_1 = and(_queue_io_deq_ready_T, s3_need_r) connect queue.io.deq.ready, _queue_io_deq_ready_T_1 node _T_21 = eq(s3_full, UInt<1>(0h0)) node _T_22 = eq(s3_need_r, UInt<1>(0h0)) node _T_23 = or(_T_21, _T_22) node _T_24 = or(_T_23, queue.io.deq.valid) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceD.scala:232 assert (!s3_full || !s3_need_r || queue.io.deq.valid)\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 when d.ready : connect s3_valid_d, UInt<1>(0h0) node _T_28 = and(s3_valid, s4_ready) when _T_28 : connect s3_full, UInt<1>(0h0) when s3_latch : connect s3_valid_d, s2_need_d when s3_latch : connect s3_full, UInt<1>(0h1) node _T_29 = eq(s4_ready, UInt<1>(0h0)) node _T_30 = and(s3_valid, _T_29) node _s3_valid_T = eq(s3_valid_d, UInt<1>(0h0)) node _s3_valid_T_1 = or(_s3_valid_T, d.ready) node _s3_valid_T_2 = and(s3_full, _s3_valid_T_1) connect s3_valid, _s3_valid_T_2 node _s3_ready_T = eq(s3_full, UInt<1>(0h0)) node _s3_ready_T_1 = eq(s3_valid_d, UInt<1>(0h0)) node _s3_ready_T_2 = or(_s3_ready_T_1, d.ready) node _s3_ready_T_3 = and(s4_ready, _s3_ready_T_2) node _s3_ready_T_4 = or(_s3_ready_T, _s3_ready_T_3) connect s3_ready, _s3_ready_T_4 node _s4_latch_T = and(s3_valid, s3_retires) node s4_latch = and(_s4_latch_T, s4_ready) regreset s4_full : UInt<1>, clock, reset, UInt<1>(0h0) reg s4_beat : UInt<4>, clock when s4_latch : connect s4_beat, s3_beat reg s4_need_r : UInt<1>, clock when s4_latch : connect s4_need_r, s3_need_r reg s4_need_bs : UInt<1>, clock when s4_latch : connect s4_need_bs, s3_need_pb reg s4_need_pb : UInt<1>, clock when s4_latch : connect s4_need_pb, s3_need_pb reg s4_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when s4_latch : connect s4_req, s3_req reg s4_adjusted_opcode : UInt<3>, clock when s4_latch : connect s4_adjusted_opcode, s3_adjusted_opcode reg s4_pdata : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}, clock when s4_latch : connect s4_pdata, s3_pdata reg s4_rdata : UInt<32>, clock when s4_latch : connect s4_rdata, s3_rdata inst atomics of Atomics connect atomics.clock, clock connect atomics.reset, reset connect atomics.io.write, s4_req.prio[2] connect atomics.io.a.opcode, s4_adjusted_opcode connect atomics.io.a.param, s4_req.param connect atomics.io.a.size, UInt<1>(0h0) connect atomics.io.a.source, UInt<1>(0h0) connect atomics.io.a.address, UInt<1>(0h0) connect atomics.io.a.mask, s4_pdata.mask connect atomics.io.a.data, s4_pdata.data invalidate atomics.io.a.corrupt connect atomics.io.data_in, s4_rdata node _io_bs_wadr_valid_T = and(s4_full, s4_need_bs) connect io.bs_wadr.valid, _io_bs_wadr_valid_T connect io.bs_wadr.bits.noop, UInt<1>(0h0) connect io.bs_wadr.bits.way, s4_req.way connect io.bs_wadr.bits.set, s4_req.set connect io.bs_wadr.bits.beat, s4_beat node _io_bs_wadr_bits_mask_T = bits(s4_pdata.mask, 0, 0) node _io_bs_wadr_bits_mask_T_1 = bits(s4_pdata.mask, 1, 1) node _io_bs_wadr_bits_mask_T_2 = bits(s4_pdata.mask, 2, 2) node _io_bs_wadr_bits_mask_T_3 = bits(s4_pdata.mask, 3, 3) node _io_bs_wadr_bits_mask_T_4 = or(_io_bs_wadr_bits_mask_T, _io_bs_wadr_bits_mask_T_1) node _io_bs_wadr_bits_mask_T_5 = or(_io_bs_wadr_bits_mask_T_4, _io_bs_wadr_bits_mask_T_2) node _io_bs_wadr_bits_mask_T_6 = or(_io_bs_wadr_bits_mask_T_5, _io_bs_wadr_bits_mask_T_3) connect io.bs_wadr.bits.mask, _io_bs_wadr_bits_mask_T_6 connect io.bs_wdat.data, atomics.io.data_out node _T_31 = and(s4_full, s4_need_pb) node _T_32 = and(_T_31, s4_pdata.corrupt) node _T_33 = eq(_T_32, UInt<1>(0h0)) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SourceD.scala:277 assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), \"Data poisoning unsupported\")\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = eq(io.bs_wadr.ready, UInt<1>(0h0)) node _T_38 = and(io.bs_wadr.valid, _T_37) node _T_39 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_40 = and(s4_req.prio[0], _T_39) node _T_41 = eq(s4_req.param, UInt<3>(0h0)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_44 = and(s4_req.prio[0], _T_43) node _T_45 = eq(s4_req.param, UInt<3>(0h1)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_48 = and(s4_req.prio[0], _T_47) node _T_49 = eq(s4_req.param, UInt<3>(0h2)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_52 = and(s4_req.prio[0], _T_51) node _T_53 = eq(s4_req.param, UInt<3>(0h3)) node _T_54 = and(_T_52, _T_53) node _T_55 = eq(s4_req.opcode, UInt<2>(0h2)) node _T_56 = and(s4_req.prio[0], _T_55) node _T_57 = eq(s4_req.param, UInt<3>(0h4)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_60 = and(s4_req.prio[0], _T_59) node _T_61 = eq(s4_req.param, UInt<3>(0h0)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_64 = and(s4_req.prio[0], _T_63) node _T_65 = eq(s4_req.param, UInt<3>(0h1)) node _T_66 = and(_T_64, _T_65) node _T_67 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_68 = and(s4_req.prio[0], _T_67) node _T_69 = eq(s4_req.param, UInt<3>(0h2)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(s4_req.opcode, UInt<2>(0h3)) node _T_72 = and(s4_req.prio[0], _T_71) node _T_73 = eq(s4_req.param, UInt<3>(0h3)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(s4_need_bs, UInt<1>(0h0)) node _T_76 = or(io.bs_wadr.ready, _T_75) when _T_76 : connect s4_full, UInt<1>(0h0) when s4_latch : connect s4_full, UInt<1>(0h1) node _s4_ready_T = eq(s3_retires, UInt<1>(0h0)) node _s4_ready_T_1 = eq(s4_full, UInt<1>(0h0)) node _s4_ready_T_2 = or(_s4_ready_T, _s4_ready_T_1) node _s4_ready_T_3 = or(_s4_ready_T_2, io.bs_wadr.ready) node _s4_ready_T_4 = eq(s4_need_bs, UInt<1>(0h0)) node _s4_ready_T_5 = or(_s4_ready_T_3, _s4_ready_T_4) connect s4_ready, _s4_ready_T_5 node _retire_T = eq(s4_need_bs, UInt<1>(0h0)) node _retire_T_1 = or(io.bs_wadr.ready, _retire_T) node retire = and(s4_full, _retire_T_1) reg s5_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s5_req, s4_req reg s5_beat : UInt<4>, clock when retire : connect s5_beat, s4_beat reg s5_dat : UInt<32>, clock when retire : connect s5_dat, atomics.io.data_out reg s6_req : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}, clock when retire : connect s6_req, s5_req reg s6_beat : UInt<4>, clock when retire : connect s6_beat, s5_beat reg s6_dat : UInt<32>, clock when retire : connect s6_dat, s5_dat reg s7_dat : UInt<32>, clock when retire : connect s7_dat, s6_dat node pre_s3_req = mux(s3_latch, s2_req, s3_req) node pre_s4_req = mux(s4_latch, s3_req, s4_req) node pre_s5_req = mux(retire, s4_req, s5_req) node pre_s6_req = mux(retire, s5_req, s6_req) node pre_s3_beat = mux(s3_latch, s2_beat, s3_beat) node pre_s4_beat = mux(s4_latch, s3_beat, s4_beat) node pre_s5_beat = mux(retire, s4_beat, s5_beat) node pre_s6_beat = mux(retire, s5_beat, s6_beat) node pre_s5_dat = mux(retire, atomics.io.data_out, s5_dat) node pre_s6_dat = mux(retire, s5_dat, s6_dat) node pre_s7_dat = mux(retire, s6_dat, s7_dat) node _pre_s4_full_T = eq(s4_need_bs, UInt<1>(0h0)) node _pre_s4_full_T_1 = or(io.bs_wadr.ready, _pre_s4_full_T) node _pre_s4_full_T_2 = eq(_pre_s4_full_T_1, UInt<1>(0h0)) node _pre_s4_full_T_3 = and(_pre_s4_full_T_2, s4_full) node pre_s4_full = or(s4_latch, _pre_s4_full_T_3) node _pre_s3_4_match_T = eq(pre_s4_req.set, pre_s3_req.set) node _pre_s3_4_match_T_1 = eq(pre_s4_req.way, pre_s3_req.way) node _pre_s3_4_match_T_2 = and(_pre_s3_4_match_T, _pre_s3_4_match_T_1) node _pre_s3_4_match_T_3 = eq(pre_s4_beat, pre_s3_beat) node _pre_s3_4_match_T_4 = and(_pre_s3_4_match_T_2, _pre_s3_4_match_T_3) node pre_s3_4_match = and(_pre_s3_4_match_T_4, pre_s4_full) node _pre_s3_5_match_T = eq(pre_s5_req.set, pre_s3_req.set) node _pre_s3_5_match_T_1 = eq(pre_s5_req.way, pre_s3_req.way) node _pre_s3_5_match_T_2 = and(_pre_s3_5_match_T, _pre_s3_5_match_T_1) node _pre_s3_5_match_T_3 = eq(pre_s5_beat, pre_s3_beat) node pre_s3_5_match = and(_pre_s3_5_match_T_2, _pre_s3_5_match_T_3) node _pre_s3_6_match_T = eq(pre_s6_req.set, pre_s3_req.set) node _pre_s3_6_match_T_1 = eq(pre_s6_req.way, pre_s3_req.way) node _pre_s3_6_match_T_2 = and(_pre_s3_6_match_T, _pre_s3_6_match_T_1) node _pre_s3_6_match_T_3 = eq(pre_s6_beat, pre_s3_beat) node pre_s3_6_match = and(_pre_s3_6_match_T_2, _pre_s3_6_match_T_3) node _pre_s3_4_bypass_sizeOH_T = or(pre_s4_req.size, UInt<2>(0h0)) node pre_s3_4_bypass_sizeOH_shiftAmount = bits(_pre_s3_4_bypass_sizeOH_T, 0, 0) node _pre_s3_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_4_bypass_sizeOH_shiftAmount) node _pre_s3_4_bypass_sizeOH_T_2 = bits(_pre_s3_4_bypass_sizeOH_T_1, 1, 0) node pre_s3_4_bypass_sizeOH = or(_pre_s3_4_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_4_bypass = mux(pre_s3_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_5_bypass_sizeOH_T = or(pre_s5_req.size, UInt<2>(0h0)) node pre_s3_5_bypass_sizeOH_shiftAmount = bits(_pre_s3_5_bypass_sizeOH_T, 0, 0) node _pre_s3_5_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_5_bypass_sizeOH_shiftAmount) node _pre_s3_5_bypass_sizeOH_T_2 = bits(_pre_s3_5_bypass_sizeOH_T_1, 1, 0) node pre_s3_5_bypass_sizeOH = or(_pre_s3_5_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_5_bypass = mux(pre_s3_5_match, UInt<1>(0h1), UInt<1>(0h0)) node _pre_s3_6_bypass_sizeOH_T = or(pre_s6_req.size, UInt<2>(0h0)) node pre_s3_6_bypass_sizeOH_shiftAmount = bits(_pre_s3_6_bypass_sizeOH_T, 0, 0) node _pre_s3_6_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), pre_s3_6_bypass_sizeOH_shiftAmount) node _pre_s3_6_bypass_sizeOH_T_2 = bits(_pre_s3_6_bypass_sizeOH_T_1, 1, 0) node pre_s3_6_bypass_sizeOH = or(_pre_s3_6_bypass_sizeOH_T_2, UInt<3>(0h7)) node pre_s3_6_bypass = mux(pre_s3_6_match, UInt<1>(0h1), UInt<1>(0h0)) reg s3_bypass_data_REG : UInt, clock connect s3_bypass_data_REG, pre_s3_4_bypass node _s3_bypass_data_T = bits(pre_s3_6_bypass, 0, 0) node _s3_bypass_data_T_1 = bits(pre_s6_dat, 31, 0) node _s3_bypass_data_T_2 = bits(pre_s7_dat, 31, 0) node _s3_bypass_data_T_3 = mux(_s3_bypass_data_T, _s3_bypass_data_T_1, _s3_bypass_data_T_2) node _s3_bypass_data_T_4 = bits(pre_s3_5_bypass, 0, 0) node _s3_bypass_data_T_5 = bits(pre_s5_dat, 31, 0) node _s3_bypass_data_T_6 = bits(_s3_bypass_data_T_3, 31, 0) node _s3_bypass_data_T_7 = mux(_s3_bypass_data_T_4, _s3_bypass_data_T_5, _s3_bypass_data_T_6) reg s3_bypass_data_REG_1 : UInt, clock connect s3_bypass_data_REG_1, _s3_bypass_data_T_7 node _s3_bypass_data_T_8 = bits(s3_bypass_data_REG, 0, 0) node _s3_bypass_data_T_9 = bits(atomics.io.data_out, 31, 0) node _s3_bypass_data_T_10 = bits(s3_bypass_data_REG_1, 31, 0) node _s3_bypass_data_T_11 = mux(_s3_bypass_data_T_8, _s3_bypass_data_T_9, _s3_bypass_data_T_10) connect s3_bypass_data, _s3_bypass_data_T_11 node _s1_2_match_T = eq(s2_req.set, s1_req.set) node _s1_2_match_T_1 = eq(s2_req.way, s1_req.way) node _s1_2_match_T_2 = and(_s1_2_match_T, _s1_2_match_T_1) node _s1_2_match_T_3 = eq(s2_beat, s1_beat) node _s1_2_match_T_4 = and(_s1_2_match_T_2, _s1_2_match_T_3) node _s1_2_match_T_5 = and(_s1_2_match_T_4, s2_full) node s1_2_match = and(_s1_2_match_T_5, s2_retires) node _s1_3_match_T = eq(s3_req.set, s1_req.set) node _s1_3_match_T_1 = eq(s3_req.way, s1_req.way) node _s1_3_match_T_2 = and(_s1_3_match_T, _s1_3_match_T_1) node _s1_3_match_T_3 = eq(s3_beat, s1_beat) node _s1_3_match_T_4 = and(_s1_3_match_T_2, _s1_3_match_T_3) node _s1_3_match_T_5 = and(_s1_3_match_T_4, s3_full) node s1_3_match = and(_s1_3_match_T_5, s3_retires) node _s1_4_match_T = eq(s4_req.set, s1_req.set) node _s1_4_match_T_1 = eq(s4_req.way, s1_req.way) node _s1_4_match_T_2 = and(_s1_4_match_T, _s1_4_match_T_1) node _s1_4_match_T_3 = eq(s4_beat, s1_beat) node _s1_4_match_T_4 = and(_s1_4_match_T_2, _s1_4_match_T_3) node s1_4_match = and(_s1_4_match_T_4, s4_full) node s2 = eq(s1_2_match, UInt<1>(0h1)) node s3 = eq(s1_3_match, UInt<1>(0h0)) node s4 = eq(s1_4_match, UInt<1>(0h0)) node _T_77 = and(io.req.valid, s2) node _T_78 = and(_T_77, s3) node _T_79 = and(_T_78, s4) node s2_1 = eq(s1_2_match, UInt<1>(0h1)) node s3_1 = eq(s1_3_match, UInt<1>(0h0)) node s4_1 = eq(s1_4_match, UInt<1>(0h0)) node _T_80 = and(io.req.valid, s2_1) node _T_81 = and(_T_80, s3_1) node _T_82 = and(_T_81, s4_1) node s2_2 = eq(s1_2_match, UInt<1>(0h1)) node s3_2 = eq(s1_3_match, UInt<1>(0h0)) node s4_2 = eq(s1_4_match, UInt<1>(0h0)) node _T_83 = and(io.req.valid, s2_2) node _T_84 = and(_T_83, s3_2) node _T_85 = and(_T_84, s4_2) node s2_3 = eq(s1_2_match, UInt<1>(0h1)) node s3_3 = eq(s1_3_match, UInt<1>(0h0)) node s4_3 = eq(s1_4_match, UInt<1>(0h0)) node _T_86 = and(io.req.valid, s2_3) node _T_87 = and(_T_86, s3_3) node _T_88 = and(_T_87, s4_3) node s2_4 = eq(s1_2_match, UInt<1>(0h1)) node s3_4 = eq(s1_3_match, UInt<1>(0h0)) node s4_4 = eq(s1_4_match, UInt<1>(0h0)) node _T_89 = and(io.req.valid, s2_4) node _T_90 = and(_T_89, s3_4) node _T_91 = and(_T_90, s4_4) node s2_5 = eq(s1_2_match, UInt<1>(0h1)) node s3_5 = eq(s1_3_match, UInt<1>(0h0)) node s4_5 = eq(s1_4_match, UInt<1>(0h0)) node _T_92 = and(io.req.valid, s2_5) node _T_93 = and(_T_92, s3_5) node _T_94 = and(_T_93, s4_5) node s2_6 = eq(s1_2_match, UInt<1>(0h1)) node s3_6 = eq(s1_3_match, UInt<1>(0h0)) node s4_6 = eq(s1_4_match, UInt<1>(0h0)) node _T_95 = and(io.req.valid, s2_6) node _T_96 = and(_T_95, s3_6) node _T_97 = and(_T_96, s4_6) node s2_7 = eq(s1_2_match, UInt<1>(0h1)) node s3_7 = eq(s1_3_match, UInt<1>(0h0)) node s4_7 = eq(s1_4_match, UInt<1>(0h0)) node _T_98 = and(io.req.valid, s2_7) node _T_99 = and(_T_98, s3_7) node _T_100 = and(_T_99, s4_7) node _s1_2_bypass_sizeOH_T = or(s2_req.size, UInt<2>(0h0)) node s1_2_bypass_sizeOH_shiftAmount = bits(_s1_2_bypass_sizeOH_T, 0, 0) node _s1_2_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_2_bypass_sizeOH_shiftAmount) node _s1_2_bypass_sizeOH_T_2 = bits(_s1_2_bypass_sizeOH_T_1, 1, 0) node s1_2_bypass_sizeOH = or(_s1_2_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_2_bypass = mux(s1_2_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_3_bypass_sizeOH_T = or(s3_req.size, UInt<2>(0h0)) node s1_3_bypass_sizeOH_shiftAmount = bits(_s1_3_bypass_sizeOH_T, 0, 0) node _s1_3_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_3_bypass_sizeOH_shiftAmount) node _s1_3_bypass_sizeOH_T_2 = bits(_s1_3_bypass_sizeOH_T_1, 1, 0) node s1_3_bypass_sizeOH = or(_s1_3_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_3_bypass = mux(s1_3_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_4_bypass_sizeOH_T = or(s4_req.size, UInt<2>(0h0)) node s1_4_bypass_sizeOH_shiftAmount = bits(_s1_4_bypass_sizeOH_T, 0, 0) node _s1_4_bypass_sizeOH_T_1 = dshl(UInt<1>(0h1), s1_4_bypass_sizeOH_shiftAmount) node _s1_4_bypass_sizeOH_T_2 = bits(_s1_4_bypass_sizeOH_T_1, 1, 0) node s1_4_bypass_sizeOH = or(_s1_4_bypass_sizeOH_T_2, UInt<3>(0h7)) node s1_4_bypass = mux(s1_4_match, UInt<1>(0h1), UInt<1>(0h0)) node _s1_x_bypass_T = or(s1_2_bypass, s1_3_bypass) node _s1_x_bypass_T_1 = or(_s1_x_bypass_T, s1_4_bypass) connect s1_x_bypass, _s1_x_bypass_T_1 node _io_evict_safe_T = eq(busy, UInt<1>(0h0)) node _io_evict_safe_T_1 = neq(io.evict_req.way, s1_req_reg.way) node _io_evict_safe_T_2 = or(_io_evict_safe_T, _io_evict_safe_T_1) node _io_evict_safe_T_3 = neq(io.evict_req.set, s1_req_reg.set) node _io_evict_safe_T_4 = or(_io_evict_safe_T_2, _io_evict_safe_T_3) node _io_evict_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_evict_safe_T_6 = neq(io.evict_req.way, s2_req.way) node _io_evict_safe_T_7 = or(_io_evict_safe_T_5, _io_evict_safe_T_6) node _io_evict_safe_T_8 = neq(io.evict_req.set, s2_req.set) node _io_evict_safe_T_9 = or(_io_evict_safe_T_7, _io_evict_safe_T_8) node _io_evict_safe_T_10 = and(_io_evict_safe_T_4, _io_evict_safe_T_9) node _io_evict_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_evict_safe_T_12 = neq(io.evict_req.way, s3_req.way) node _io_evict_safe_T_13 = or(_io_evict_safe_T_11, _io_evict_safe_T_12) node _io_evict_safe_T_14 = neq(io.evict_req.set, s3_req.set) node _io_evict_safe_T_15 = or(_io_evict_safe_T_13, _io_evict_safe_T_14) node _io_evict_safe_T_16 = and(_io_evict_safe_T_10, _io_evict_safe_T_15) node _io_evict_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_evict_safe_T_18 = neq(io.evict_req.way, s4_req.way) node _io_evict_safe_T_19 = or(_io_evict_safe_T_17, _io_evict_safe_T_18) node _io_evict_safe_T_20 = neq(io.evict_req.set, s4_req.set) node _io_evict_safe_T_21 = or(_io_evict_safe_T_19, _io_evict_safe_T_20) node _io_evict_safe_T_22 = and(_io_evict_safe_T_16, _io_evict_safe_T_21) connect io.evict_safe, _io_evict_safe_T_22 node _io_grant_safe_T = eq(busy, UInt<1>(0h0)) node _io_grant_safe_T_1 = neq(io.grant_req.way, s1_req_reg.way) node _io_grant_safe_T_2 = or(_io_grant_safe_T, _io_grant_safe_T_1) node _io_grant_safe_T_3 = neq(io.grant_req.set, s1_req_reg.set) node _io_grant_safe_T_4 = or(_io_grant_safe_T_2, _io_grant_safe_T_3) node _io_grant_safe_T_5 = eq(s2_full, UInt<1>(0h0)) node _io_grant_safe_T_6 = neq(io.grant_req.way, s2_req.way) node _io_grant_safe_T_7 = or(_io_grant_safe_T_5, _io_grant_safe_T_6) node _io_grant_safe_T_8 = neq(io.grant_req.set, s2_req.set) node _io_grant_safe_T_9 = or(_io_grant_safe_T_7, _io_grant_safe_T_8) node _io_grant_safe_T_10 = and(_io_grant_safe_T_4, _io_grant_safe_T_9) node _io_grant_safe_T_11 = eq(s3_full, UInt<1>(0h0)) node _io_grant_safe_T_12 = neq(io.grant_req.way, s3_req.way) node _io_grant_safe_T_13 = or(_io_grant_safe_T_11, _io_grant_safe_T_12) node _io_grant_safe_T_14 = neq(io.grant_req.set, s3_req.set) node _io_grant_safe_T_15 = or(_io_grant_safe_T_13, _io_grant_safe_T_14) node _io_grant_safe_T_16 = and(_io_grant_safe_T_10, _io_grant_safe_T_15) node _io_grant_safe_T_17 = eq(s4_full, UInt<1>(0h0)) node _io_grant_safe_T_18 = neq(io.grant_req.way, s4_req.way) node _io_grant_safe_T_19 = or(_io_grant_safe_T_17, _io_grant_safe_T_18) node _io_grant_safe_T_20 = neq(io.grant_req.set, s4_req.set) node _io_grant_safe_T_21 = or(_io_grant_safe_T_19, _io_grant_safe_T_20) node _io_grant_safe_T_22 = and(_io_grant_safe_T_16, _io_grant_safe_T_21) connect io.grant_safe, _io_grant_safe_T_22

module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [5:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [2:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [5:0] io_d_bits_source, // @[SourceD.scala:50:14] output [2:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [31:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [31:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [3:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [3:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [31:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [3:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [31:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [31:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [31:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [3:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [31:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_rel_pop_ready = 1'h1; // @[SourceD.scala:48:7] wire [31:0] io_rel_beat_data = 32'h0; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt = 1'h0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire [2:0] s1_mask_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_4_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_5_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] pre_s3_6_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_2_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_3_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] s1_4_bypass_sizeOH = 3'h7; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [3:0] _s2_pdata_raw_mask_T = 4'hF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [5:0] d_bits_source; // @[SourceD.scala:218:15] wire [2:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [31:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [3:0] s1_beat; // @[SourceD.scala:102:56] wire s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:87] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [5:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [31:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [3:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [31:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [3:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] _s1_mask_sizeOH_T = s1_req_size; // @[Misc.scala:202:34] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy | io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 | s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg s1_bypass_r; // @[SourceD.scala:91:62] wire s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _s1_mask_sizeOH_T_1 = 2'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire _s1_mask_T = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T; // @[SourceD.scala:92:{76,78}] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _s1_need_r_T = s1_mask; // @[SourceD.scala:92:76, :94:27] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 | _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = |s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h2; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 | _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T | s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [3:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:2]; // @[package.scala:243:46] wire [3:0] s1_beats1 = s1_single ? 4'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [3:0] _s1_beat_T = s1_req_offset[5:2]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T | s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 4'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [4:0] _s1_counter_T = {1'h0, s1_counter} + 5'h1; // @[SourceD.scala:86:27, :130:30] wire [3:0] _s1_counter_T_1 = _s1_counter_T[3:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 | io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [3:0] s2_beat; // @[SourceD.scala:149:26] reg s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] wire [2:0] _s1_2_bypass_sizeOH_T = s2_req_size; // @[Misc.scala:202:34] reg [5:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [2:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T | s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [31:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [3:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [31:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [3:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [31:0] s2_pdata_r_data; // @[package.scala:88:63] reg [3:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [31:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [3:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : 32'h0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 4'hF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 & io_pb_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = ~s2_req_prio_0 | io_pb_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T | pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 | pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T | _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [3:0] s3_beat; // @[SourceD.scala:192:26] wire [3:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg s3_bypass; // @[SourceD.scala:193:28] wire _s3_rdata_T = s3_bypass; // @[SourceD.scala:193:28, :208:78] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] wire [2:0] _s1_3_bypass_sizeOH_T = s3_req_size; // @[Misc.scala:202:34] reg [5:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [2:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [31:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [3:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T | _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [31:0] _s3_bypass_data_T_11; // @[SourceD.scala:210:75] wire [31:0] s3_bypass_data; // @[SourceD.scala:206:28] wire [31:0] _s3_rdata_T_1 = s3_bypass_data; // @[SourceD.scala:206:28, :207:78] wire [31:0] _s3_rdata_T_2; // @[SourceD.scala:207:78] wire [31:0] s3_rdata = _s3_rdata_T ? _s3_rdata_T_1 : _s3_rdata_T_2; // @[SourceD.scala:207:78, :208:78, :210:75] assign d_bits_data = s3_rdata; // @[SourceD.scala:210:75, :218:15] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = |s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T | d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 | d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T | _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [3:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [3:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] wire [2:0] _s1_4_bypass_sizeOH_T = s4_req_size; // @[Misc.scala:202:34] reg [5:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [2:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [31:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [3:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [31:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = _io_bs_wadr_bits_mask_T | _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_5 = _io_bs_wadr_bits_mask_T_4 | _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_6 = _io_bs_wadr_bits_mask_T_5 | _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:48:7, :275:87]

Generate the Verilog code corresponding to this FIRRTL code module Tile_91 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_347 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a

module Tile_91( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_347 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0) node _source_ok_T_28 = shr(io.in.a.bits.source, 5) node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0)) node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f)) node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0) node _source_ok_T_34 = shr(io.in.a.bits.source, 5) node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1)) node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f)) node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38) node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0) node _source_ok_T_40 = shr(io.in.a.bits.source, 5) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0) node _source_ok_T_46 = shr(io.in.a.bits.source, 5) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0) node _source_ok_T_52 = shr(io.in.a.bits.source, 5) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0) node _source_ok_T_58 = shr(io.in.a.bits.source, 5) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0) node _source_ok_T_64 = shr(io.in.a.bits.source, 5) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0) node _source_ok_T_70 = shr(io.in.a.bits.source, 5) node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7)) node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f)) node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74) node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE : UInt<1>[17] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_45 connect _source_ok_WIRE[11], _source_ok_T_51 connect _source_ok_WIRE[12], _source_ok_T_57 connect _source_ok_WIRE[13], _source_ok_T_63 connect _source_ok_WIRE[14], _source_ok_T_69 connect _source_ok_WIRE[15], _source_ok_T_75 connect _source_ok_WIRE[16], _source_ok_T_76 node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15]) node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<7>(0h40)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<7>(0h41)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<7>(0h42)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<7>(0h43)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) node _T_88 = shr(io.in.a.bits.source, 5) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_4) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) node _T_101 = shr(io.in.a.bits.source, 5) node _T_102 = eq(_T_101, UInt<1>(0h1)) node _T_103 = leq(UInt<1>(0h0), uncommonBits_5) node _T_104 = and(_T_102, _T_103) node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) node _T_114 = shr(io.in.a.bits.source, 5) node _T_115 = eq(_T_114, UInt<2>(0h2)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = or(_T_120, _T_125) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) node _T_127 = shr(io.in.a.bits.source, 5) node _T_128 = eq(_T_127, UInt<2>(0h3)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_7) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f)) node _T_132 = and(_T_130, _T_131) node _T_133 = eq(_T_132, UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = or(_T_133, _T_138) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) node _T_140 = shr(io.in.a.bits.source, 5) node _T_141 = eq(_T_140, UInt<3>(0h4)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_8) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f)) node _T_145 = and(_T_143, _T_144) node _T_146 = eq(_T_145, UInt<1>(0h0)) node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = or(_T_146, _T_151) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0) node _T_153 = shr(io.in.a.bits.source, 5) node _T_154 = eq(_T_153, UInt<3>(0h5)) node _T_155 = leq(UInt<1>(0h0), uncommonBits_9) node _T_156 = and(_T_154, _T_155) node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<1>(0h0))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = or(_T_159, _T_164) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0) node _T_166 = shr(io.in.a.bits.source, 5) node _T_167 = eq(_T_166, UInt<3>(0h6)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = or(_T_172, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0) node _T_179 = shr(io.in.a.bits.source, 5) node _T_180 = eq(_T_179, UInt<3>(0h7)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = and(_T_11, _T_24) node _T_201 = and(_T_200, _T_37) node _T_202 = and(_T_201, _T_50) node _T_203 = and(_T_202, _T_63) node _T_204 = and(_T_203, _T_71) node _T_205 = and(_T_204, _T_79) node _T_206 = and(_T_205, _T_87) node _T_207 = and(_T_206, _T_100) node _T_208 = and(_T_207, _T_113) node _T_209 = and(_T_208, _T_126) node _T_210 = and(_T_209, _T_139) node _T_211 = and(_T_210, _T_152) node _T_212 = and(_T_211, _T_165) node _T_213 = and(_T_212, _T_178) node _T_214 = and(_T_213, _T_191) node _T_215 = and(_T_214, _T_199) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_215, UInt<1>(0h1), "") : assert_1 node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_219 : node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_222 = and(_T_220, _T_221) node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_224 = shr(io.in.a.bits.source, 2) node _T_225 = eq(_T_224, UInt<7>(0h40)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_12) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_229 = and(_T_227, _T_228) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_230 = shr(io.in.a.bits.source, 2) node _T_231 = eq(_T_230, UInt<7>(0h41)) node _T_232 = leq(UInt<1>(0h0), uncommonBits_13) node _T_233 = and(_T_231, _T_232) node _T_234 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_235 = and(_T_233, _T_234) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_236 = shr(io.in.a.bits.source, 2) node _T_237 = eq(_T_236, UInt<7>(0h42)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_14) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_242 = shr(io.in.a.bits.source, 2) node _T_243 = eq(_T_242, UInt<7>(0h43)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_15) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_247 = and(_T_245, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0) node _T_251 = shr(io.in.a.bits.source, 5) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = leq(UInt<1>(0h0), uncommonBits_16) node _T_254 = and(_T_252, _T_253) node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f)) node _T_256 = and(_T_254, _T_255) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0) node _T_257 = shr(io.in.a.bits.source, 5) node _T_258 = eq(_T_257, UInt<1>(0h1)) node _T_259 = leq(UInt<1>(0h0), uncommonBits_17) node _T_260 = and(_T_258, _T_259) node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f)) node _T_262 = and(_T_260, _T_261) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0) node _T_263 = shr(io.in.a.bits.source, 5) node _T_264 = eq(_T_263, UInt<2>(0h2)) node _T_265 = leq(UInt<1>(0h0), uncommonBits_18) node _T_266 = and(_T_264, _T_265) node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f)) node _T_268 = and(_T_266, _T_267) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0) node _T_269 = shr(io.in.a.bits.source, 5) node _T_270 = eq(_T_269, UInt<2>(0h3)) node _T_271 = leq(UInt<1>(0h0), uncommonBits_19) node _T_272 = and(_T_270, _T_271) node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f)) node _T_274 = and(_T_272, _T_273) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0) node _T_275 = shr(io.in.a.bits.source, 5) node _T_276 = eq(_T_275, UInt<3>(0h4)) node _T_277 = leq(UInt<1>(0h0), uncommonBits_20) node _T_278 = and(_T_276, _T_277) node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f)) node _T_280 = and(_T_278, _T_279) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0) node _T_281 = shr(io.in.a.bits.source, 5) node _T_282 = eq(_T_281, UInt<3>(0h5)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_21) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0) node _T_287 = shr(io.in.a.bits.source, 5) node _T_288 = eq(_T_287, UInt<3>(0h6)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_22) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0) node _T_293 = shr(io.in.a.bits.source, 5) node _T_294 = eq(_T_293, UInt<3>(0h7)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_23) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f)) node _T_298 = and(_T_296, _T_297) node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_300 = or(_T_223, _T_229) node _T_301 = or(_T_300, _T_235) node _T_302 = or(_T_301, _T_241) node _T_303 = or(_T_302, _T_247) node _T_304 = or(_T_303, _T_248) node _T_305 = or(_T_304, _T_249) node _T_306 = or(_T_305, _T_250) node _T_307 = or(_T_306, _T_256) node _T_308 = or(_T_307, _T_262) node _T_309 = or(_T_308, _T_268) node _T_310 = or(_T_309, _T_274) node _T_311 = or(_T_310, _T_280) node _T_312 = or(_T_311, _T_286) node _T_313 = or(_T_312, _T_292) node _T_314 = or(_T_313, _T_298) node _T_315 = or(_T_314, _T_299) node _T_316 = and(_T_222, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = and(_T_318, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = and(_T_317, _T_325) node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(_T_326, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_326, UInt<1>(0h1), "") : assert_2 node _T_330 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<7>(0h40)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_24) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<7>(0h41)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_25) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<7>(0h42)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_26) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<7>(0h43)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_27) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _T_355 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_356 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_357 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0) node _T_358 = shr(io.in.a.bits.source, 5) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = leq(UInt<1>(0h0), uncommonBits_28) node _T_361 = and(_T_359, _T_360) node _T_362 = leq(uncommonBits_28, UInt<5>(0h1f)) node _T_363 = and(_T_361, _T_362) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0) node _T_364 = shr(io.in.a.bits.source, 5) node _T_365 = eq(_T_364, UInt<1>(0h1)) node _T_366 = leq(UInt<1>(0h0), uncommonBits_29) node _T_367 = and(_T_365, _T_366) node _T_368 = leq(uncommonBits_29, UInt<5>(0h1f)) node _T_369 = and(_T_367, _T_368) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0) node _T_370 = shr(io.in.a.bits.source, 5) node _T_371 = eq(_T_370, UInt<2>(0h2)) node _T_372 = leq(UInt<1>(0h0), uncommonBits_30) node _T_373 = and(_T_371, _T_372) node _T_374 = leq(uncommonBits_30, UInt<5>(0h1f)) node _T_375 = and(_T_373, _T_374) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0) node _T_376 = shr(io.in.a.bits.source, 5) node _T_377 = eq(_T_376, UInt<2>(0h3)) node _T_378 = leq(UInt<1>(0h0), uncommonBits_31) node _T_379 = and(_T_377, _T_378) node _T_380 = leq(uncommonBits_31, UInt<5>(0h1f)) node _T_381 = and(_T_379, _T_380) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0) node _T_382 = shr(io.in.a.bits.source, 5) node _T_383 = eq(_T_382, UInt<3>(0h4)) node _T_384 = leq(UInt<1>(0h0), uncommonBits_32) node _T_385 = and(_T_383, _T_384) node _T_386 = leq(uncommonBits_32, UInt<5>(0h1f)) node _T_387 = and(_T_385, _T_386) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0) node _T_388 = shr(io.in.a.bits.source, 5) node _T_389 = eq(_T_388, UInt<3>(0h5)) node _T_390 = leq(UInt<1>(0h0), uncommonBits_33) node _T_391 = and(_T_389, _T_390) node _T_392 = leq(uncommonBits_33, UInt<5>(0h1f)) node _T_393 = and(_T_391, _T_392) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0) node _T_394 = shr(io.in.a.bits.source, 5) node _T_395 = eq(_T_394, UInt<3>(0h6)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_34) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_34, UInt<5>(0h1f)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0) node _T_400 = shr(io.in.a.bits.source, 5) node _T_401 = eq(_T_400, UInt<3>(0h7)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_35) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_35, UInt<5>(0h1f)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE : UInt<1>[17] connect _WIRE[0], _T_330 connect _WIRE[1], _T_336 connect _WIRE[2], _T_342 connect _WIRE[3], _T_348 connect _WIRE[4], _T_354 connect _WIRE[5], _T_355 connect _WIRE[6], _T_356 connect _WIRE[7], _T_357 connect _WIRE[8], _T_363 connect _WIRE[9], _T_369 connect _WIRE[10], _T_375 connect _WIRE[11], _T_381 connect _WIRE[12], _T_387 connect _WIRE[13], _T_393 connect _WIRE[14], _T_399 connect _WIRE[15], _T_405 connect _WIRE[16], _T_406 node _T_407 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_408 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_410 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_411 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_412 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_413 = mux(_WIRE[5], _T_407, UInt<1>(0h0)) node _T_414 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_415 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_416 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_417 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_418 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_419 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_420 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_421 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_422 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_423 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_424 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_425 = or(_T_408, _T_409) node _T_426 = or(_T_425, _T_410) node _T_427 = or(_T_426, _T_411) node _T_428 = or(_T_427, _T_412) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_414) node _T_431 = or(_T_430, _T_415) node _T_432 = or(_T_431, _T_416) node _T_433 = or(_T_432, _T_417) node _T_434 = or(_T_433, _T_418) node _T_435 = or(_T_434, _T_419) node _T_436 = or(_T_435, _T_420) node _T_437 = or(_T_436, _T_421) node _T_438 = or(_T_437, _T_422) node _T_439 = or(_T_438, _T_423) node _T_440 = or(_T_439, _T_424) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_440 node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _T_444 = or(UInt<1>(0h0), _T_443) node _T_445 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_446 = cvt(_T_445) node _T_447 = and(_T_446, asSInt(UInt<13>(0h1000))) node _T_448 = asSInt(_T_447) node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0))) node _T_450 = and(_T_444, _T_449) node _T_451 = or(UInt<1>(0h0), _T_450) node _T_452 = and(_WIRE_1, _T_451) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_452, UInt<1>(0h1), "") : assert_3 node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(source_ok, UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_459 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_459, UInt<1>(0h1), "") : assert_5 node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(is_aligned, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_466 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(_T_466, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_466, UInt<1>(0h1), "") : assert_7 node _T_470 = not(io.in.a.bits.mask) node _T_471 = eq(_T_470, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_471, UInt<1>(0h1), "") : assert_8 node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_475, UInt<1>(0h1), "") : assert_9 node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_479 : node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_482 = and(_T_480, _T_481) node _T_483 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<7>(0h40)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_36) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<7>(0h41)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_37) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<7>(0h42)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_38) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<7>(0h43)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_39) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_509 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_510 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0) node _T_511 = shr(io.in.a.bits.source, 5) node _T_512 = eq(_T_511, UInt<1>(0h0)) node _T_513 = leq(UInt<1>(0h0), uncommonBits_40) node _T_514 = and(_T_512, _T_513) node _T_515 = leq(uncommonBits_40, UInt<5>(0h1f)) node _T_516 = and(_T_514, _T_515) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0) node _T_517 = shr(io.in.a.bits.source, 5) node _T_518 = eq(_T_517, UInt<1>(0h1)) node _T_519 = leq(UInt<1>(0h0), uncommonBits_41) node _T_520 = and(_T_518, _T_519) node _T_521 = leq(uncommonBits_41, UInt<5>(0h1f)) node _T_522 = and(_T_520, _T_521) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0) node _T_523 = shr(io.in.a.bits.source, 5) node _T_524 = eq(_T_523, UInt<2>(0h2)) node _T_525 = leq(UInt<1>(0h0), uncommonBits_42) node _T_526 = and(_T_524, _T_525) node _T_527 = leq(uncommonBits_42, UInt<5>(0h1f)) node _T_528 = and(_T_526, _T_527) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0) node _T_529 = shr(io.in.a.bits.source, 5) node _T_530 = eq(_T_529, UInt<2>(0h3)) node _T_531 = leq(UInt<1>(0h0), uncommonBits_43) node _T_532 = and(_T_530, _T_531) node _T_533 = leq(uncommonBits_43, UInt<5>(0h1f)) node _T_534 = and(_T_532, _T_533) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0) node _T_535 = shr(io.in.a.bits.source, 5) node _T_536 = eq(_T_535, UInt<3>(0h4)) node _T_537 = leq(UInt<1>(0h0), uncommonBits_44) node _T_538 = and(_T_536, _T_537) node _T_539 = leq(uncommonBits_44, UInt<5>(0h1f)) node _T_540 = and(_T_538, _T_539) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0) node _T_541 = shr(io.in.a.bits.source, 5) node _T_542 = eq(_T_541, UInt<3>(0h5)) node _T_543 = leq(UInt<1>(0h0), uncommonBits_45) node _T_544 = and(_T_542, _T_543) node _T_545 = leq(uncommonBits_45, UInt<5>(0h1f)) node _T_546 = and(_T_544, _T_545) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0) node _T_547 = shr(io.in.a.bits.source, 5) node _T_548 = eq(_T_547, UInt<3>(0h6)) node _T_549 = leq(UInt<1>(0h0), uncommonBits_46) node _T_550 = and(_T_548, _T_549) node _T_551 = leq(uncommonBits_46, UInt<5>(0h1f)) node _T_552 = and(_T_550, _T_551) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0) node _T_553 = shr(io.in.a.bits.source, 5) node _T_554 = eq(_T_553, UInt<3>(0h7)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_47) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_47, UInt<5>(0h1f)) node _T_558 = and(_T_556, _T_557) node _T_559 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_560 = or(_T_483, _T_489) node _T_561 = or(_T_560, _T_495) node _T_562 = or(_T_561, _T_501) node _T_563 = or(_T_562, _T_507) node _T_564 = or(_T_563, _T_508) node _T_565 = or(_T_564, _T_509) node _T_566 = or(_T_565, _T_510) node _T_567 = or(_T_566, _T_516) node _T_568 = or(_T_567, _T_522) node _T_569 = or(_T_568, _T_528) node _T_570 = or(_T_569, _T_534) node _T_571 = or(_T_570, _T_540) node _T_572 = or(_T_571, _T_546) node _T_573 = or(_T_572, _T_552) node _T_574 = or(_T_573, _T_558) node _T_575 = or(_T_574, _T_559) node _T_576 = and(_T_482, _T_575) node _T_577 = or(UInt<1>(0h0), _T_576) node _T_578 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_579 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = and(_T_578, _T_583) node _T_585 = or(UInt<1>(0h0), _T_584) node _T_586 = and(_T_577, _T_585) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_586, UInt<1>(0h1), "") : assert_10 node _T_590 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<7>(0h40)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_48) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<7>(0h41)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_49) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<7>(0h42)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_50) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_609 = shr(io.in.a.bits.source, 2) node _T_610 = eq(_T_609, UInt<7>(0h43)) node _T_611 = leq(UInt<1>(0h0), uncommonBits_51) node _T_612 = and(_T_610, _T_611) node _T_613 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_614 = and(_T_612, _T_613) node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_616 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_617 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0) node _T_618 = shr(io.in.a.bits.source, 5) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_52) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_52, UInt<5>(0h1f)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0) node _T_624 = shr(io.in.a.bits.source, 5) node _T_625 = eq(_T_624, UInt<1>(0h1)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_53) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_53, UInt<5>(0h1f)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0) node _T_630 = shr(io.in.a.bits.source, 5) node _T_631 = eq(_T_630, UInt<2>(0h2)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_54) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_54, UInt<5>(0h1f)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0) node _T_636 = shr(io.in.a.bits.source, 5) node _T_637 = eq(_T_636, UInt<2>(0h3)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_55) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_55, UInt<5>(0h1f)) node _T_641 = and(_T_639, _T_640) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0) node _T_642 = shr(io.in.a.bits.source, 5) node _T_643 = eq(_T_642, UInt<3>(0h4)) node _T_644 = leq(UInt<1>(0h0), uncommonBits_56) node _T_645 = and(_T_643, _T_644) node _T_646 = leq(uncommonBits_56, UInt<5>(0h1f)) node _T_647 = and(_T_645, _T_646) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0) node _T_648 = shr(io.in.a.bits.source, 5) node _T_649 = eq(_T_648, UInt<3>(0h5)) node _T_650 = leq(UInt<1>(0h0), uncommonBits_57) node _T_651 = and(_T_649, _T_650) node _T_652 = leq(uncommonBits_57, UInt<5>(0h1f)) node _T_653 = and(_T_651, _T_652) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0) node _T_654 = shr(io.in.a.bits.source, 5) node _T_655 = eq(_T_654, UInt<3>(0h6)) node _T_656 = leq(UInt<1>(0h0), uncommonBits_58) node _T_657 = and(_T_655, _T_656) node _T_658 = leq(uncommonBits_58, UInt<5>(0h1f)) node _T_659 = and(_T_657, _T_658) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0) node _T_660 = shr(io.in.a.bits.source, 5) node _T_661 = eq(_T_660, UInt<3>(0h7)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_59) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_59, UInt<5>(0h1f)) node _T_665 = and(_T_663, _T_664) node _T_666 = eq(io.in.a.bits.source, UInt<10>(0h200)) wire _WIRE_2 : UInt<1>[17] connect _WIRE_2[0], _T_590 connect _WIRE_2[1], _T_596 connect _WIRE_2[2], _T_602 connect _WIRE_2[3], _T_608 connect _WIRE_2[4], _T_614 connect _WIRE_2[5], _T_615 connect _WIRE_2[6], _T_616 connect _WIRE_2[7], _T_617 connect _WIRE_2[8], _T_623 connect _WIRE_2[9], _T_629 connect _WIRE_2[10], _T_635 connect _WIRE_2[11], _T_641 connect _WIRE_2[12], _T_647 connect _WIRE_2[13], _T_653 connect _WIRE_2[14], _T_659 connect _WIRE_2[15], _T_665 connect _WIRE_2[16], _T_666 node _T_667 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_668 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_669 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_670 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_671 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_672 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_673 = mux(_WIRE_2[5], _T_667, UInt<1>(0h0)) node _T_674 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_675 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_676 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_678 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_679 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_680 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_681 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_682 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0)) node _T_683 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_684 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_685 = or(_T_668, _T_669) node _T_686 = or(_T_685, _T_670) node _T_687 = or(_T_686, _T_671) node _T_688 = or(_T_687, _T_672) node _T_689 = or(_T_688, _T_673) node _T_690 = or(_T_689, _T_674) node _T_691 = or(_T_690, _T_675) node _T_692 = or(_T_691, _T_676) node _T_693 = or(_T_692, _T_677) node _T_694 = or(_T_693, _T_678) node _T_695 = or(_T_694, _T_679) node _T_696 = or(_T_695, _T_680) node _T_697 = or(_T_696, _T_681) node _T_698 = or(_T_697, _T_682) node _T_699 = or(_T_698, _T_683) node _T_700 = or(_T_699, _T_684) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_700 node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_703 = and(_T_701, _T_702) node _T_704 = or(UInt<1>(0h0), _T_703) node _T_705 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<13>(0h1000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = and(_T_704, _T_709) node _T_711 = or(UInt<1>(0h0), _T_710) node _T_712 = and(_WIRE_3, _T_711) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_712, UInt<1>(0h1), "") : assert_11 node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(source_ok, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_719 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_719, UInt<1>(0h1), "") : assert_13 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(is_aligned, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_726 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_726, UInt<1>(0h1), "") : assert_15 node _T_730 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_730, UInt<1>(0h1), "") : assert_16 node _T_734 = not(io.in.a.bits.mask) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = asUInt(reset) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(_T_735, UInt<1>(0h0)) when _T_738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_735, UInt<1>(0h1), "") : assert_17 node _T_739 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_739, UInt<1>(0h1), "") : assert_18 node _T_743 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_743 : node _T_744 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_745 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_746 = and(_T_744, _T_745) node _T_747 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_748 = shr(io.in.a.bits.source, 2) node _T_749 = eq(_T_748, UInt<7>(0h40)) node _T_750 = leq(UInt<1>(0h0), uncommonBits_60) node _T_751 = and(_T_749, _T_750) node _T_752 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_754 = shr(io.in.a.bits.source, 2) node _T_755 = eq(_T_754, UInt<7>(0h41)) node _T_756 = leq(UInt<1>(0h0), uncommonBits_61) node _T_757 = and(_T_755, _T_756) node _T_758 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_759 = and(_T_757, _T_758) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_760 = shr(io.in.a.bits.source, 2) node _T_761 = eq(_T_760, UInt<7>(0h42)) node _T_762 = leq(UInt<1>(0h0), uncommonBits_62) node _T_763 = and(_T_761, _T_762) node _T_764 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_765 = and(_T_763, _T_764) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_766 = shr(io.in.a.bits.source, 2) node _T_767 = eq(_T_766, UInt<7>(0h43)) node _T_768 = leq(UInt<1>(0h0), uncommonBits_63) node _T_769 = and(_T_767, _T_768) node _T_770 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_771 = and(_T_769, _T_770) node _T_772 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_774 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0) node _T_775 = shr(io.in.a.bits.source, 5) node _T_776 = eq(_T_775, UInt<1>(0h0)) node _T_777 = leq(UInt<1>(0h0), uncommonBits_64) node _T_778 = and(_T_776, _T_777) node _T_779 = leq(uncommonBits_64, UInt<5>(0h1f)) node _T_780 = and(_T_778, _T_779) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0) node _T_781 = shr(io.in.a.bits.source, 5) node _T_782 = eq(_T_781, UInt<1>(0h1)) node _T_783 = leq(UInt<1>(0h0), uncommonBits_65) node _T_784 = and(_T_782, _T_783) node _T_785 = leq(uncommonBits_65, UInt<5>(0h1f)) node _T_786 = and(_T_784, _T_785) node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0) node _T_787 = shr(io.in.a.bits.source, 5) node _T_788 = eq(_T_787, UInt<2>(0h2)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_66) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_66, UInt<5>(0h1f)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0) node _T_793 = shr(io.in.a.bits.source, 5) node _T_794 = eq(_T_793, UInt<2>(0h3)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_67) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_67, UInt<5>(0h1f)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0) node _T_799 = shr(io.in.a.bits.source, 5) node _T_800 = eq(_T_799, UInt<3>(0h4)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_68) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_68, UInt<5>(0h1f)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0) node _T_805 = shr(io.in.a.bits.source, 5) node _T_806 = eq(_T_805, UInt<3>(0h5)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_69) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_69, UInt<5>(0h1f)) node _T_810 = and(_T_808, _T_809) node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0) node _T_811 = shr(io.in.a.bits.source, 5) node _T_812 = eq(_T_811, UInt<3>(0h6)) node _T_813 = leq(UInt<1>(0h0), uncommonBits_70) node _T_814 = and(_T_812, _T_813) node _T_815 = leq(uncommonBits_70, UInt<5>(0h1f)) node _T_816 = and(_T_814, _T_815) node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0) node _T_817 = shr(io.in.a.bits.source, 5) node _T_818 = eq(_T_817, UInt<3>(0h7)) node _T_819 = leq(UInt<1>(0h0), uncommonBits_71) node _T_820 = and(_T_818, _T_819) node _T_821 = leq(uncommonBits_71, UInt<5>(0h1f)) node _T_822 = and(_T_820, _T_821) node _T_823 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_824 = or(_T_747, _T_753) node _T_825 = or(_T_824, _T_759) node _T_826 = or(_T_825, _T_765) node _T_827 = or(_T_826, _T_771) node _T_828 = or(_T_827, _T_772) node _T_829 = or(_T_828, _T_773) node _T_830 = or(_T_829, _T_774) node _T_831 = or(_T_830, _T_780) node _T_832 = or(_T_831, _T_786) node _T_833 = or(_T_832, _T_792) node _T_834 = or(_T_833, _T_798) node _T_835 = or(_T_834, _T_804) node _T_836 = or(_T_835, _T_810) node _T_837 = or(_T_836, _T_816) node _T_838 = or(_T_837, _T_822) node _T_839 = or(_T_838, _T_823) node _T_840 = and(_T_746, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_841, UInt<1>(0h1), "") : assert_19 node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_846 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_847 = and(_T_845, _T_846) node _T_848 = or(UInt<1>(0h0), _T_847) node _T_849 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_850 = cvt(_T_849) node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000))) node _T_852 = asSInt(_T_851) node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0))) node _T_854 = and(_T_848, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_855, UInt<1>(0h1), "") : assert_20 node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(source_ok, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(is_aligned, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_865 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_865, UInt<1>(0h1), "") : assert_23 node _T_869 = eq(io.in.a.bits.mask, mask) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_869, UInt<1>(0h1), "") : assert_24 node _T_873 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_873, UInt<1>(0h1), "") : assert_25 node _T_877 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_877 : node _T_878 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_879 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_880 = and(_T_878, _T_879) node _T_881 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0) node _T_882 = shr(io.in.a.bits.source, 2) node _T_883 = eq(_T_882, UInt<7>(0h40)) node _T_884 = leq(UInt<1>(0h0), uncommonBits_72) node _T_885 = and(_T_883, _T_884) node _T_886 = leq(uncommonBits_72, UInt<2>(0h3)) node _T_887 = and(_T_885, _T_886) node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0) node _T_888 = shr(io.in.a.bits.source, 2) node _T_889 = eq(_T_888, UInt<7>(0h41)) node _T_890 = leq(UInt<1>(0h0), uncommonBits_73) node _T_891 = and(_T_889, _T_890) node _T_892 = leq(uncommonBits_73, UInt<2>(0h3)) node _T_893 = and(_T_891, _T_892) node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0) node _T_894 = shr(io.in.a.bits.source, 2) node _T_895 = eq(_T_894, UInt<7>(0h42)) node _T_896 = leq(UInt<1>(0h0), uncommonBits_74) node _T_897 = and(_T_895, _T_896) node _T_898 = leq(uncommonBits_74, UInt<2>(0h3)) node _T_899 = and(_T_897, _T_898) node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0) node _T_900 = shr(io.in.a.bits.source, 2) node _T_901 = eq(_T_900, UInt<7>(0h43)) node _T_902 = leq(UInt<1>(0h0), uncommonBits_75) node _T_903 = and(_T_901, _T_902) node _T_904 = leq(uncommonBits_75, UInt<2>(0h3)) node _T_905 = and(_T_903, _T_904) node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0) node _T_909 = shr(io.in.a.bits.source, 5) node _T_910 = eq(_T_909, UInt<1>(0h0)) node _T_911 = leq(UInt<1>(0h0), uncommonBits_76) node _T_912 = and(_T_910, _T_911) node _T_913 = leq(uncommonBits_76, UInt<5>(0h1f)) node _T_914 = and(_T_912, _T_913) node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0) node _T_915 = shr(io.in.a.bits.source, 5) node _T_916 = eq(_T_915, UInt<1>(0h1)) node _T_917 = leq(UInt<1>(0h0), uncommonBits_77) node _T_918 = and(_T_916, _T_917) node _T_919 = leq(uncommonBits_77, UInt<5>(0h1f)) node _T_920 = and(_T_918, _T_919) node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0) node _T_921 = shr(io.in.a.bits.source, 5) node _T_922 = eq(_T_921, UInt<2>(0h2)) node _T_923 = leq(UInt<1>(0h0), uncommonBits_78) node _T_924 = and(_T_922, _T_923) node _T_925 = leq(uncommonBits_78, UInt<5>(0h1f)) node _T_926 = and(_T_924, _T_925) node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0) node _T_927 = shr(io.in.a.bits.source, 5) node _T_928 = eq(_T_927, UInt<2>(0h3)) node _T_929 = leq(UInt<1>(0h0), uncommonBits_79) node _T_930 = and(_T_928, _T_929) node _T_931 = leq(uncommonBits_79, UInt<5>(0h1f)) node _T_932 = and(_T_930, _T_931) node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0) node _T_933 = shr(io.in.a.bits.source, 5) node _T_934 = eq(_T_933, UInt<3>(0h4)) node _T_935 = leq(UInt<1>(0h0), uncommonBits_80) node _T_936 = and(_T_934, _T_935) node _T_937 = leq(uncommonBits_80, UInt<5>(0h1f)) node _T_938 = and(_T_936, _T_937) node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0) node _T_939 = shr(io.in.a.bits.source, 5) node _T_940 = eq(_T_939, UInt<3>(0h5)) node _T_941 = leq(UInt<1>(0h0), uncommonBits_81) node _T_942 = and(_T_940, _T_941) node _T_943 = leq(uncommonBits_81, UInt<5>(0h1f)) node _T_944 = and(_T_942, _T_943) node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0) node _T_945 = shr(io.in.a.bits.source, 5) node _T_946 = eq(_T_945, UInt<3>(0h6)) node _T_947 = leq(UInt<1>(0h0), uncommonBits_82) node _T_948 = and(_T_946, _T_947) node _T_949 = leq(uncommonBits_82, UInt<5>(0h1f)) node _T_950 = and(_T_948, _T_949) node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0) node _T_951 = shr(io.in.a.bits.source, 5) node _T_952 = eq(_T_951, UInt<3>(0h7)) node _T_953 = leq(UInt<1>(0h0), uncommonBits_83) node _T_954 = and(_T_952, _T_953) node _T_955 = leq(uncommonBits_83, UInt<5>(0h1f)) node _T_956 = and(_T_954, _T_955) node _T_957 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_958 = or(_T_881, _T_887) node _T_959 = or(_T_958, _T_893) node _T_960 = or(_T_959, _T_899) node _T_961 = or(_T_960, _T_905) node _T_962 = or(_T_961, _T_906) node _T_963 = or(_T_962, _T_907) node _T_964 = or(_T_963, _T_908) node _T_965 = or(_T_964, _T_914) node _T_966 = or(_T_965, _T_920) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_932) node _T_969 = or(_T_968, _T_938) node _T_970 = or(_T_969, _T_944) node _T_971 = or(_T_970, _T_950) node _T_972 = or(_T_971, _T_956) node _T_973 = or(_T_972, _T_957) node _T_974 = and(_T_880, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), _T_985) node _T_987 = and(_T_975, _T_986) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_987, UInt<1>(0h1), "") : assert_26 node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(source_ok, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(is_aligned, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_997 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_997, UInt<1>(0h1), "") : assert_29 node _T_1001 = eq(io.in.a.bits.mask, mask) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_30 node _T_1005 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1005 : node _T_1006 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1007 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1008 = and(_T_1006, _T_1007) node _T_1009 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0) node _T_1010 = shr(io.in.a.bits.source, 2) node _T_1011 = eq(_T_1010, UInt<7>(0h40)) node _T_1012 = leq(UInt<1>(0h0), uncommonBits_84) node _T_1013 = and(_T_1011, _T_1012) node _T_1014 = leq(uncommonBits_84, UInt<2>(0h3)) node _T_1015 = and(_T_1013, _T_1014) node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0) node _T_1016 = shr(io.in.a.bits.source, 2) node _T_1017 = eq(_T_1016, UInt<7>(0h41)) node _T_1018 = leq(UInt<1>(0h0), uncommonBits_85) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = leq(uncommonBits_85, UInt<2>(0h3)) node _T_1021 = and(_T_1019, _T_1020) node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0) node _T_1022 = shr(io.in.a.bits.source, 2) node _T_1023 = eq(_T_1022, UInt<7>(0h42)) node _T_1024 = leq(UInt<1>(0h0), uncommonBits_86) node _T_1025 = and(_T_1023, _T_1024) node _T_1026 = leq(uncommonBits_86, UInt<2>(0h3)) node _T_1027 = and(_T_1025, _T_1026) node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<7>(0h43)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_87) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_87, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _T_1034 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1035 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1036 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0) node _T_1037 = shr(io.in.a.bits.source, 5) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) node _T_1039 = leq(UInt<1>(0h0), uncommonBits_88) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = leq(uncommonBits_88, UInt<5>(0h1f)) node _T_1042 = and(_T_1040, _T_1041) node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0) node _T_1043 = shr(io.in.a.bits.source, 5) node _T_1044 = eq(_T_1043, UInt<1>(0h1)) node _T_1045 = leq(UInt<1>(0h0), uncommonBits_89) node _T_1046 = and(_T_1044, _T_1045) node _T_1047 = leq(uncommonBits_89, UInt<5>(0h1f)) node _T_1048 = and(_T_1046, _T_1047) node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0) node _T_1049 = shr(io.in.a.bits.source, 5) node _T_1050 = eq(_T_1049, UInt<2>(0h2)) node _T_1051 = leq(UInt<1>(0h0), uncommonBits_90) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = leq(uncommonBits_90, UInt<5>(0h1f)) node _T_1054 = and(_T_1052, _T_1053) node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0) node _T_1055 = shr(io.in.a.bits.source, 5) node _T_1056 = eq(_T_1055, UInt<2>(0h3)) node _T_1057 = leq(UInt<1>(0h0), uncommonBits_91) node _T_1058 = and(_T_1056, _T_1057) node _T_1059 = leq(uncommonBits_91, UInt<5>(0h1f)) node _T_1060 = and(_T_1058, _T_1059) node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0) node _T_1061 = shr(io.in.a.bits.source, 5) node _T_1062 = eq(_T_1061, UInt<3>(0h4)) node _T_1063 = leq(UInt<1>(0h0), uncommonBits_92) node _T_1064 = and(_T_1062, _T_1063) node _T_1065 = leq(uncommonBits_92, UInt<5>(0h1f)) node _T_1066 = and(_T_1064, _T_1065) node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0) node _T_1067 = shr(io.in.a.bits.source, 5) node _T_1068 = eq(_T_1067, UInt<3>(0h5)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_93) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_93, UInt<5>(0h1f)) node _T_1072 = and(_T_1070, _T_1071) node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0) node _T_1073 = shr(io.in.a.bits.source, 5) node _T_1074 = eq(_T_1073, UInt<3>(0h6)) node _T_1075 = leq(UInt<1>(0h0), uncommonBits_94) node _T_1076 = and(_T_1074, _T_1075) node _T_1077 = leq(uncommonBits_94, UInt<5>(0h1f)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0) node _T_1079 = shr(io.in.a.bits.source, 5) node _T_1080 = eq(_T_1079, UInt<3>(0h7)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_95) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_95, UInt<5>(0h1f)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1086 = or(_T_1009, _T_1015) node _T_1087 = or(_T_1086, _T_1021) node _T_1088 = or(_T_1087, _T_1027) node _T_1089 = or(_T_1088, _T_1033) node _T_1090 = or(_T_1089, _T_1034) node _T_1091 = or(_T_1090, _T_1035) node _T_1092 = or(_T_1091, _T_1036) node _T_1093 = or(_T_1092, _T_1042) node _T_1094 = or(_T_1093, _T_1048) node _T_1095 = or(_T_1094, _T_1054) node _T_1096 = or(_T_1095, _T_1060) node _T_1097 = or(_T_1096, _T_1066) node _T_1098 = or(_T_1097, _T_1072) node _T_1099 = or(_T_1098, _T_1078) node _T_1100 = or(_T_1099, _T_1084) node _T_1101 = or(_T_1100, _T_1085) node _T_1102 = and(_T_1008, _T_1101) node _T_1103 = or(UInt<1>(0h0), _T_1102) node _T_1104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1109 = cvt(_T_1108) node _T_1110 = and(_T_1109, asSInt(UInt<13>(0h1000))) node _T_1111 = asSInt(_T_1110) node _T_1112 = eq(_T_1111, asSInt(UInt<1>(0h0))) node _T_1113 = and(_T_1107, _T_1112) node _T_1114 = or(UInt<1>(0h0), _T_1113) node _T_1115 = and(_T_1103, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_31 node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(source_ok, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(is_aligned, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1125 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_34 node _T_1129 = not(mask) node _T_1130 = and(io.in.a.bits.mask, _T_1129) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_35 node _T_1135 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1135 : node _T_1136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1138 = and(_T_1136, _T_1137) node _T_1139 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0) node _T_1140 = shr(io.in.a.bits.source, 2) node _T_1141 = eq(_T_1140, UInt<7>(0h40)) node _T_1142 = leq(UInt<1>(0h0), uncommonBits_96) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = leq(uncommonBits_96, UInt<2>(0h3)) node _T_1145 = and(_T_1143, _T_1144) node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0) node _T_1146 = shr(io.in.a.bits.source, 2) node _T_1147 = eq(_T_1146, UInt<7>(0h41)) node _T_1148 = leq(UInt<1>(0h0), uncommonBits_97) node _T_1149 = and(_T_1147, _T_1148) node _T_1150 = leq(uncommonBits_97, UInt<2>(0h3)) node _T_1151 = and(_T_1149, _T_1150) node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0) node _T_1152 = shr(io.in.a.bits.source, 2) node _T_1153 = eq(_T_1152, UInt<7>(0h42)) node _T_1154 = leq(UInt<1>(0h0), uncommonBits_98) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = leq(uncommonBits_98, UInt<2>(0h3)) node _T_1157 = and(_T_1155, _T_1156) node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0) node _T_1158 = shr(io.in.a.bits.source, 2) node _T_1159 = eq(_T_1158, UInt<7>(0h43)) node _T_1160 = leq(UInt<1>(0h0), uncommonBits_99) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = leq(uncommonBits_99, UInt<2>(0h3)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1165 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1166 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0) node _T_1167 = shr(io.in.a.bits.source, 5) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) node _T_1169 = leq(UInt<1>(0h0), uncommonBits_100) node _T_1170 = and(_T_1168, _T_1169) node _T_1171 = leq(uncommonBits_100, UInt<5>(0h1f)) node _T_1172 = and(_T_1170, _T_1171) node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0) node _T_1173 = shr(io.in.a.bits.source, 5) node _T_1174 = eq(_T_1173, UInt<1>(0h1)) node _T_1175 = leq(UInt<1>(0h0), uncommonBits_101) node _T_1176 = and(_T_1174, _T_1175) node _T_1177 = leq(uncommonBits_101, UInt<5>(0h1f)) node _T_1178 = and(_T_1176, _T_1177) node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0) node _T_1179 = shr(io.in.a.bits.source, 5) node _T_1180 = eq(_T_1179, UInt<2>(0h2)) node _T_1181 = leq(UInt<1>(0h0), uncommonBits_102) node _T_1182 = and(_T_1180, _T_1181) node _T_1183 = leq(uncommonBits_102, UInt<5>(0h1f)) node _T_1184 = and(_T_1182, _T_1183) node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0) node _T_1185 = shr(io.in.a.bits.source, 5) node _T_1186 = eq(_T_1185, UInt<2>(0h3)) node _T_1187 = leq(UInt<1>(0h0), uncommonBits_103) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = leq(uncommonBits_103, UInt<5>(0h1f)) node _T_1190 = and(_T_1188, _T_1189) node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0) node _T_1191 = shr(io.in.a.bits.source, 5) node _T_1192 = eq(_T_1191, UInt<3>(0h4)) node _T_1193 = leq(UInt<1>(0h0), uncommonBits_104) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = leq(uncommonBits_104, UInt<5>(0h1f)) node _T_1196 = and(_T_1194, _T_1195) node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0) node _T_1197 = shr(io.in.a.bits.source, 5) node _T_1198 = eq(_T_1197, UInt<3>(0h5)) node _T_1199 = leq(UInt<1>(0h0), uncommonBits_105) node _T_1200 = and(_T_1198, _T_1199) node _T_1201 = leq(uncommonBits_105, UInt<5>(0h1f)) node _T_1202 = and(_T_1200, _T_1201) node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0) node _T_1203 = shr(io.in.a.bits.source, 5) node _T_1204 = eq(_T_1203, UInt<3>(0h6)) node _T_1205 = leq(UInt<1>(0h0), uncommonBits_106) node _T_1206 = and(_T_1204, _T_1205) node _T_1207 = leq(uncommonBits_106, UInt<5>(0h1f)) node _T_1208 = and(_T_1206, _T_1207) node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0) node _T_1209 = shr(io.in.a.bits.source, 5) node _T_1210 = eq(_T_1209, UInt<3>(0h7)) node _T_1211 = leq(UInt<1>(0h0), uncommonBits_107) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = leq(uncommonBits_107, UInt<5>(0h1f)) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1216 = or(_T_1139, _T_1145) node _T_1217 = or(_T_1216, _T_1151) node _T_1218 = or(_T_1217, _T_1157) node _T_1219 = or(_T_1218, _T_1163) node _T_1220 = or(_T_1219, _T_1164) node _T_1221 = or(_T_1220, _T_1165) node _T_1222 = or(_T_1221, _T_1166) node _T_1223 = or(_T_1222, _T_1172) node _T_1224 = or(_T_1223, _T_1178) node _T_1225 = or(_T_1224, _T_1184) node _T_1226 = or(_T_1225, _T_1190) node _T_1227 = or(_T_1226, _T_1196) node _T_1228 = or(_T_1227, _T_1202) node _T_1229 = or(_T_1228, _T_1208) node _T_1230 = or(_T_1229, _T_1214) node _T_1231 = or(_T_1230, _T_1215) node _T_1232 = and(_T_1138, _T_1231) node _T_1233 = or(UInt<1>(0h0), _T_1232) node _T_1234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1235 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1236 = and(_T_1234, _T_1235) node _T_1237 = or(UInt<1>(0h0), _T_1236) node _T_1238 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = and(_T_1237, _T_1242) node _T_1244 = or(UInt<1>(0h0), _T_1243) node _T_1245 = and(_T_1233, _T_1244) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_36 node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(source_ok, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(is_aligned, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1255 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1256 = asUInt(reset) node _T_1257 = eq(_T_1256, UInt<1>(0h0)) when _T_1257 : node _T_1258 = eq(_T_1255, UInt<1>(0h0)) when _T_1258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1255, UInt<1>(0h1), "") : assert_39 node _T_1259 = eq(io.in.a.bits.mask, mask) node _T_1260 = asUInt(reset) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) when _T_1261 : node _T_1262 = eq(_T_1259, UInt<1>(0h0)) when _T_1262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1259, UInt<1>(0h1), "") : assert_40 node _T_1263 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1263 : node _T_1264 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1265 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1266 = and(_T_1264, _T_1265) node _T_1267 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0) node _T_1268 = shr(io.in.a.bits.source, 2) node _T_1269 = eq(_T_1268, UInt<7>(0h40)) node _T_1270 = leq(UInt<1>(0h0), uncommonBits_108) node _T_1271 = and(_T_1269, _T_1270) node _T_1272 = leq(uncommonBits_108, UInt<2>(0h3)) node _T_1273 = and(_T_1271, _T_1272) node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0) node _T_1274 = shr(io.in.a.bits.source, 2) node _T_1275 = eq(_T_1274, UInt<7>(0h41)) node _T_1276 = leq(UInt<1>(0h0), uncommonBits_109) node _T_1277 = and(_T_1275, _T_1276) node _T_1278 = leq(uncommonBits_109, UInt<2>(0h3)) node _T_1279 = and(_T_1277, _T_1278) node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0) node _T_1280 = shr(io.in.a.bits.source, 2) node _T_1281 = eq(_T_1280, UInt<7>(0h42)) node _T_1282 = leq(UInt<1>(0h0), uncommonBits_110) node _T_1283 = and(_T_1281, _T_1282) node _T_1284 = leq(uncommonBits_110, UInt<2>(0h3)) node _T_1285 = and(_T_1283, _T_1284) node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0) node _T_1286 = shr(io.in.a.bits.source, 2) node _T_1287 = eq(_T_1286, UInt<7>(0h43)) node _T_1288 = leq(UInt<1>(0h0), uncommonBits_111) node _T_1289 = and(_T_1287, _T_1288) node _T_1290 = leq(uncommonBits_111, UInt<2>(0h3)) node _T_1291 = and(_T_1289, _T_1290) node _T_1292 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1293 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1294 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0) node _T_1295 = shr(io.in.a.bits.source, 5) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) node _T_1297 = leq(UInt<1>(0h0), uncommonBits_112) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = leq(uncommonBits_112, UInt<5>(0h1f)) node _T_1300 = and(_T_1298, _T_1299) node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0) node _T_1301 = shr(io.in.a.bits.source, 5) node _T_1302 = eq(_T_1301, UInt<1>(0h1)) node _T_1303 = leq(UInt<1>(0h0), uncommonBits_113) node _T_1304 = and(_T_1302, _T_1303) node _T_1305 = leq(uncommonBits_113, UInt<5>(0h1f)) node _T_1306 = and(_T_1304, _T_1305) node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0) node _T_1307 = shr(io.in.a.bits.source, 5) node _T_1308 = eq(_T_1307, UInt<2>(0h2)) node _T_1309 = leq(UInt<1>(0h0), uncommonBits_114) node _T_1310 = and(_T_1308, _T_1309) node _T_1311 = leq(uncommonBits_114, UInt<5>(0h1f)) node _T_1312 = and(_T_1310, _T_1311) node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0) node _T_1313 = shr(io.in.a.bits.source, 5) node _T_1314 = eq(_T_1313, UInt<2>(0h3)) node _T_1315 = leq(UInt<1>(0h0), uncommonBits_115) node _T_1316 = and(_T_1314, _T_1315) node _T_1317 = leq(uncommonBits_115, UInt<5>(0h1f)) node _T_1318 = and(_T_1316, _T_1317) node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0) node _T_1319 = shr(io.in.a.bits.source, 5) node _T_1320 = eq(_T_1319, UInt<3>(0h4)) node _T_1321 = leq(UInt<1>(0h0), uncommonBits_116) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = leq(uncommonBits_116, UInt<5>(0h1f)) node _T_1324 = and(_T_1322, _T_1323) node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0) node _T_1325 = shr(io.in.a.bits.source, 5) node _T_1326 = eq(_T_1325, UInt<3>(0h5)) node _T_1327 = leq(UInt<1>(0h0), uncommonBits_117) node _T_1328 = and(_T_1326, _T_1327) node _T_1329 = leq(uncommonBits_117, UInt<5>(0h1f)) node _T_1330 = and(_T_1328, _T_1329) node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0) node _T_1331 = shr(io.in.a.bits.source, 5) node _T_1332 = eq(_T_1331, UInt<3>(0h6)) node _T_1333 = leq(UInt<1>(0h0), uncommonBits_118) node _T_1334 = and(_T_1332, _T_1333) node _T_1335 = leq(uncommonBits_118, UInt<5>(0h1f)) node _T_1336 = and(_T_1334, _T_1335) node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0) node _T_1337 = shr(io.in.a.bits.source, 5) node _T_1338 = eq(_T_1337, UInt<3>(0h7)) node _T_1339 = leq(UInt<1>(0h0), uncommonBits_119) node _T_1340 = and(_T_1338, _T_1339) node _T_1341 = leq(uncommonBits_119, UInt<5>(0h1f)) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1344 = or(_T_1267, _T_1273) node _T_1345 = or(_T_1344, _T_1279) node _T_1346 = or(_T_1345, _T_1285) node _T_1347 = or(_T_1346, _T_1291) node _T_1348 = or(_T_1347, _T_1292) node _T_1349 = or(_T_1348, _T_1293) node _T_1350 = or(_T_1349, _T_1294) node _T_1351 = or(_T_1350, _T_1300) node _T_1352 = or(_T_1351, _T_1306) node _T_1353 = or(_T_1352, _T_1312) node _T_1354 = or(_T_1353, _T_1318) node _T_1355 = or(_T_1354, _T_1324) node _T_1356 = or(_T_1355, _T_1330) node _T_1357 = or(_T_1356, _T_1336) node _T_1358 = or(_T_1357, _T_1342) node _T_1359 = or(_T_1358, _T_1343) node _T_1360 = and(_T_1266, _T_1359) node _T_1361 = or(UInt<1>(0h0), _T_1360) node _T_1362 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1363 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = or(UInt<1>(0h0), _T_1364) node _T_1366 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = and(_T_1365, _T_1370) node _T_1372 = or(UInt<1>(0h0), _T_1371) node _T_1373 = and(_T_1361, _T_1372) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_41 node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(source_ok, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1380 = asUInt(reset) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) when _T_1381 : node _T_1382 = eq(is_aligned, UInt<1>(0h0)) when _T_1382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1383 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1384 = asUInt(reset) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(_T_1383, UInt<1>(0h0)) when _T_1386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1383, UInt<1>(0h1), "") : assert_44 node _T_1387 = eq(io.in.a.bits.mask, mask) node _T_1388 = asUInt(reset) node _T_1389 = eq(_T_1388, UInt<1>(0h0)) when _T_1389 : node _T_1390 = eq(_T_1387, UInt<1>(0h0)) when _T_1390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1387, UInt<1>(0h1), "") : assert_45 node _T_1391 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1391 : node _T_1392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1394 = and(_T_1392, _T_1393) node _T_1395 = eq(io.in.a.bits.source, UInt<9>(0h110)) node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0) node _T_1396 = shr(io.in.a.bits.source, 2) node _T_1397 = eq(_T_1396, UInt<7>(0h40)) node _T_1398 = leq(UInt<1>(0h0), uncommonBits_120) node _T_1399 = and(_T_1397, _T_1398) node _T_1400 = leq(uncommonBits_120, UInt<2>(0h3)) node _T_1401 = and(_T_1399, _T_1400) node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0) node _T_1402 = shr(io.in.a.bits.source, 2) node _T_1403 = eq(_T_1402, UInt<7>(0h41)) node _T_1404 = leq(UInt<1>(0h0), uncommonBits_121) node _T_1405 = and(_T_1403, _T_1404) node _T_1406 = leq(uncommonBits_121, UInt<2>(0h3)) node _T_1407 = and(_T_1405, _T_1406) node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0) node _T_1408 = shr(io.in.a.bits.source, 2) node _T_1409 = eq(_T_1408, UInt<7>(0h42)) node _T_1410 = leq(UInt<1>(0h0), uncommonBits_122) node _T_1411 = and(_T_1409, _T_1410) node _T_1412 = leq(uncommonBits_122, UInt<2>(0h3)) node _T_1413 = and(_T_1411, _T_1412) node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0) node _T_1414 = shr(io.in.a.bits.source, 2) node _T_1415 = eq(_T_1414, UInt<7>(0h43)) node _T_1416 = leq(UInt<1>(0h0), uncommonBits_123) node _T_1417 = and(_T_1415, _T_1416) node _T_1418 = leq(uncommonBits_123, UInt<2>(0h3)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = eq(io.in.a.bits.source, UInt<9>(0h120)) node _T_1421 = eq(io.in.a.bits.source, UInt<9>(0h121)) node _T_1422 = eq(io.in.a.bits.source, UInt<9>(0h122)) node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0) node _T_1423 = shr(io.in.a.bits.source, 5) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) node _T_1425 = leq(UInt<1>(0h0), uncommonBits_124) node _T_1426 = and(_T_1424, _T_1425) node _T_1427 = leq(uncommonBits_124, UInt<5>(0h1f)) node _T_1428 = and(_T_1426, _T_1427) node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0) node _T_1429 = shr(io.in.a.bits.source, 5) node _T_1430 = eq(_T_1429, UInt<1>(0h1)) node _T_1431 = leq(UInt<1>(0h0), uncommonBits_125) node _T_1432 = and(_T_1430, _T_1431) node _T_1433 = leq(uncommonBits_125, UInt<5>(0h1f)) node _T_1434 = and(_T_1432, _T_1433) node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0) node _T_1435 = shr(io.in.a.bits.source, 5) node _T_1436 = eq(_T_1435, UInt<2>(0h2)) node _T_1437 = leq(UInt<1>(0h0), uncommonBits_126) node _T_1438 = and(_T_1436, _T_1437) node _T_1439 = leq(uncommonBits_126, UInt<5>(0h1f)) node _T_1440 = and(_T_1438, _T_1439) node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0) node _T_1441 = shr(io.in.a.bits.source, 5) node _T_1442 = eq(_T_1441, UInt<2>(0h3)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_127) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_127, UInt<5>(0h1f)) node _T_1446 = and(_T_1444, _T_1445) node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0) node _T_1447 = shr(io.in.a.bits.source, 5) node _T_1448 = eq(_T_1447, UInt<3>(0h4)) node _T_1449 = leq(UInt<1>(0h0), uncommonBits_128) node _T_1450 = and(_T_1448, _T_1449) node _T_1451 = leq(uncommonBits_128, UInt<5>(0h1f)) node _T_1452 = and(_T_1450, _T_1451) node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0) node _T_1453 = shr(io.in.a.bits.source, 5) node _T_1454 = eq(_T_1453, UInt<3>(0h5)) node _T_1455 = leq(UInt<1>(0h0), uncommonBits_129) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = leq(uncommonBits_129, UInt<5>(0h1f)) node _T_1458 = and(_T_1456, _T_1457) node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0) node _T_1459 = shr(io.in.a.bits.source, 5) node _T_1460 = eq(_T_1459, UInt<3>(0h6)) node _T_1461 = leq(UInt<1>(0h0), uncommonBits_130) node _T_1462 = and(_T_1460, _T_1461) node _T_1463 = leq(uncommonBits_130, UInt<5>(0h1f)) node _T_1464 = and(_T_1462, _T_1463) node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0)) node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0) node _T_1465 = shr(io.in.a.bits.source, 5) node _T_1466 = eq(_T_1465, UInt<3>(0h7)) node _T_1467 = leq(UInt<1>(0h0), uncommonBits_131) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = leq(uncommonBits_131, UInt<5>(0h1f)) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = eq(io.in.a.bits.source, UInt<10>(0h200)) node _T_1472 = or(_T_1395, _T_1401) node _T_1473 = or(_T_1472, _T_1407) node _T_1474 = or(_T_1473, _T_1413) node _T_1475 = or(_T_1474, _T_1419) node _T_1476 = or(_T_1475, _T_1420) node _T_1477 = or(_T_1476, _T_1421) node _T_1478 = or(_T_1477, _T_1422) node _T_1479 = or(_T_1478, _T_1428) node _T_1480 = or(_T_1479, _T_1434) node _T_1481 = or(_T_1480, _T_1440) node _T_1482 = or(_T_1481, _T_1446) node _T_1483 = or(_T_1482, _T_1452) node _T_1484 = or(_T_1483, _T_1458) node _T_1485 = or(_T_1484, _T_1464) node _T_1486 = or(_T_1485, _T_1470) node _T_1487 = or(_T_1486, _T_1471) node _T_1488 = and(_T_1394, _T_1487) node _T_1489 = or(UInt<1>(0h0), _T_1488) node _T_1490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1492 = and(_T_1490, _T_1491) node _T_1493 = or(UInt<1>(0h0), _T_1492) node _T_1494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1495 = cvt(_T_1494) node _T_1496 = and(_T_1495, asSInt(UInt<13>(0h1000))) node _T_1497 = asSInt(_T_1496) node _T_1498 = eq(_T_1497, asSInt(UInt<1>(0h0))) node _T_1499 = and(_T_1493, _T_1498) node _T_1500 = or(UInt<1>(0h0), _T_1499) node _T_1501 = and(_T_1489, _T_1500) node _T_1502 = asUInt(reset) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) when _T_1503 : node _T_1504 = eq(_T_1501, UInt<1>(0h0)) when _T_1504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1501, UInt<1>(0h1), "") : assert_46 node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(is_aligned, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1511 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(_T_1511, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1511, UInt<1>(0h1), "") : assert_49 node _T_1515 = eq(io.in.a.bits.mask, mask) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_50 node _T_1519 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1523 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1524 = asUInt(reset) node _T_1525 = eq(_T_1524, UInt<1>(0h0)) when _T_1525 : node _T_1526 = eq(_T_1523, UInt<1>(0h0)) when _T_1526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1523, UInt<1>(0h1), "") : assert_52 node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110)) node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0) node _source_ok_T_93 = shr(io.in.d.bits.source, 2) node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40)) node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3)) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0) node _source_ok_T_99 = shr(io.in.d.bits.source, 2) node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41)) node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3)) node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103) node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0) node _source_ok_T_105 = shr(io.in.d.bits.source, 2) node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42)) node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3)) node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109) node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0) node _source_ok_T_111 = shr(io.in.d.bits.source, 2) node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43)) node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3)) node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122)) node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0) node _source_ok_T_120 = shr(io.in.d.bits.source, 5) node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0)) node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16) node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122) node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f)) node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124) node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0) node _source_ok_T_126 = shr(io.in.d.bits.source, 5) node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1)) node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17) node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128) node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f)) node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130) node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0) node _source_ok_T_132 = shr(io.in.d.bits.source, 5) node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2)) node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18) node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134) node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f)) node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136) node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0) node _source_ok_T_138 = shr(io.in.d.bits.source, 5) node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3)) node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19) node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140) node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f)) node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142) node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0) node _source_ok_T_144 = shr(io.in.d.bits.source, 5) node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4)) node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20) node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146) node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f)) node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148) node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0) node _source_ok_T_150 = shr(io.in.d.bits.source, 5) node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5)) node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21) node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152) node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f)) node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154) node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0) node _source_ok_T_156 = shr(io.in.d.bits.source, 5) node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6)) node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22) node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158) node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f)) node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160) node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0)) node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0) node _source_ok_T_162 = shr(io.in.d.bits.source, 5) node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7)) node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23) node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164) node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f)) node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166) node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200)) wire _source_ok_WIRE_1 : UInt<1>[17] connect _source_ok_WIRE_1[0], _source_ok_T_92 connect _source_ok_WIRE_1[1], _source_ok_T_98 connect _source_ok_WIRE_1[2], _source_ok_T_104 connect _source_ok_WIRE_1[3], _source_ok_T_110 connect _source_ok_WIRE_1[4], _source_ok_T_116 connect _source_ok_WIRE_1[5], _source_ok_T_117 connect _source_ok_WIRE_1[6], _source_ok_T_118 connect _source_ok_WIRE_1[7], _source_ok_T_119 connect _source_ok_WIRE_1[8], _source_ok_T_125 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_137 connect _source_ok_WIRE_1[11], _source_ok_T_143 connect _source_ok_WIRE_1[12], _source_ok_T_149 connect _source_ok_WIRE_1[13], _source_ok_T_155 connect _source_ok_WIRE_1[14], _source_ok_T_161 connect _source_ok_WIRE_1[15], _source_ok_T_167 connect _source_ok_WIRE_1[16], _source_ok_T_168 node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15]) node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1527 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1527 : node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(source_ok_1, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1531 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1532 = asUInt(reset) node _T_1533 = eq(_T_1532, UInt<1>(0h0)) when _T_1533 : node _T_1534 = eq(_T_1531, UInt<1>(0h0)) when _T_1534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1531, UInt<1>(0h1), "") : assert_54 node _T_1535 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_55 node _T_1539 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1540 = asUInt(reset) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(_T_1539, UInt<1>(0h0)) when _T_1542 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1539, UInt<1>(0h1), "") : assert_56 node _T_1543 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_57 node _T_1547 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1547 : node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(source_ok_1, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(sink_ok, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1554 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_60 node _T_1558 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1559 = asUInt(reset) node _T_1560 = eq(_T_1559, UInt<1>(0h0)) when _T_1560 : node _T_1561 = eq(_T_1558, UInt<1>(0h0)) when _T_1561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1558, UInt<1>(0h1), "") : assert_61 node _T_1562 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1563 = asUInt(reset) node _T_1564 = eq(_T_1563, UInt<1>(0h0)) when _T_1564 : node _T_1565 = eq(_T_1562, UInt<1>(0h0)) when _T_1565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1562, UInt<1>(0h1), "") : assert_62 node _T_1566 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_63 node _T_1570 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1571 = or(UInt<1>(0h1), _T_1570) node _T_1572 = asUInt(reset) node _T_1573 = eq(_T_1572, UInt<1>(0h0)) when _T_1573 : node _T_1574 = eq(_T_1571, UInt<1>(0h0)) when _T_1574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1571, UInt<1>(0h1), "") : assert_64 node _T_1575 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1575 : node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(source_ok_1, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(sink_ok, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1582 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(_T_1582, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1582, UInt<1>(0h1), "") : assert_67 node _T_1586 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(_T_1586, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1586, UInt<1>(0h1), "") : assert_68 node _T_1590 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_69 node _T_1594 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1595 = or(_T_1594, io.in.d.bits.corrupt) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_70 node _T_1599 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1600 = or(UInt<1>(0h1), _T_1599) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_71 node _T_1604 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1604 : node _T_1605 = asUInt(reset) node _T_1606 = eq(_T_1605, UInt<1>(0h0)) when _T_1606 : node _T_1607 = eq(source_ok_1, UInt<1>(0h0)) when _T_1607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1608 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1609 = asUInt(reset) node _T_1610 = eq(_T_1609, UInt<1>(0h0)) when _T_1610 : node _T_1611 = eq(_T_1608, UInt<1>(0h0)) when _T_1611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1608, UInt<1>(0h1), "") : assert_73 node _T_1612 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(_T_1612, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1612, UInt<1>(0h1), "") : assert_74 node _T_1616 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1617 = or(UInt<1>(0h1), _T_1616) node _T_1618 = asUInt(reset) node _T_1619 = eq(_T_1618, UInt<1>(0h0)) when _T_1619 : node _T_1620 = eq(_T_1617, UInt<1>(0h0)) when _T_1620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1617, UInt<1>(0h1), "") : assert_75 node _T_1621 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1621 : node _T_1622 = asUInt(reset) node _T_1623 = eq(_T_1622, UInt<1>(0h0)) when _T_1623 : node _T_1624 = eq(source_ok_1, UInt<1>(0h0)) when _T_1624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1625 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1626 = asUInt(reset) node _T_1627 = eq(_T_1626, UInt<1>(0h0)) when _T_1627 : node _T_1628 = eq(_T_1625, UInt<1>(0h0)) when _T_1628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1625, UInt<1>(0h1), "") : assert_77 node _T_1629 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1630 = or(_T_1629, io.in.d.bits.corrupt) node _T_1631 = asUInt(reset) node _T_1632 = eq(_T_1631, UInt<1>(0h0)) when _T_1632 : node _T_1633 = eq(_T_1630, UInt<1>(0h0)) when _T_1633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1630, UInt<1>(0h1), "") : assert_78 node _T_1634 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1635 = or(UInt<1>(0h1), _T_1634) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_79 node _T_1639 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1639 : node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(source_ok_1, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1643 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_81 node _T_1647 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1648 = asUInt(reset) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(_T_1647, UInt<1>(0h0)) when _T_1650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1647, UInt<1>(0h1), "") : assert_82 node _T_1651 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1652 = or(UInt<1>(0h1), _T_1651) node _T_1653 = asUInt(reset) node _T_1654 = eq(_T_1653, UInt<1>(0h0)) when _T_1654 : node _T_1655 = eq(_T_1652, UInt<1>(0h0)) when _T_1655 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1652, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<10>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1656 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<10>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1660 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1661 = asUInt(reset) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(_T_1660, UInt<1>(0h0)) when _T_1663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1660, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1664 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1668 = eq(a_first, UInt<1>(0h0)) node _T_1669 = and(io.in.a.valid, _T_1668) when _T_1669 : node _T_1670 = eq(io.in.a.bits.opcode, opcode) node _T_1671 = asUInt(reset) node _T_1672 = eq(_T_1671, UInt<1>(0h0)) when _T_1672 : node _T_1673 = eq(_T_1670, UInt<1>(0h0)) when _T_1673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1670, UInt<1>(0h1), "") : assert_87 node _T_1674 = eq(io.in.a.bits.param, param) node _T_1675 = asUInt(reset) node _T_1676 = eq(_T_1675, UInt<1>(0h0)) when _T_1676 : node _T_1677 = eq(_T_1674, UInt<1>(0h0)) when _T_1677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1674, UInt<1>(0h1), "") : assert_88 node _T_1678 = eq(io.in.a.bits.size, size) node _T_1679 = asUInt(reset) node _T_1680 = eq(_T_1679, UInt<1>(0h0)) when _T_1680 : node _T_1681 = eq(_T_1678, UInt<1>(0h0)) when _T_1681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1678, UInt<1>(0h1), "") : assert_89 node _T_1682 = eq(io.in.a.bits.source, source) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_90 node _T_1686 = eq(io.in.a.bits.address, address) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_91 node _T_1690 = and(io.in.a.ready, io.in.a.valid) node _T_1691 = and(_T_1690, a_first) when _T_1691 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1692 = eq(d_first, UInt<1>(0h0)) node _T_1693 = and(io.in.d.valid, _T_1692) when _T_1693 : node _T_1694 = eq(io.in.d.bits.opcode, opcode_1) node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(_T_1694, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1694, UInt<1>(0h1), "") : assert_92 node _T_1698 = eq(io.in.d.bits.param, param_1) node _T_1699 = asUInt(reset) node _T_1700 = eq(_T_1699, UInt<1>(0h0)) when _T_1700 : node _T_1701 = eq(_T_1698, UInt<1>(0h0)) when _T_1701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1698, UInt<1>(0h1), "") : assert_93 node _T_1702 = eq(io.in.d.bits.size, size_1) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_94 node _T_1706 = eq(io.in.d.bits.source, source_1) node _T_1707 = asUInt(reset) node _T_1708 = eq(_T_1707, UInt<1>(0h0)) when _T_1708 : node _T_1709 = eq(_T_1706, UInt<1>(0h0)) when _T_1709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1706, UInt<1>(0h1), "") : assert_95 node _T_1710 = eq(io.in.d.bits.sink, sink) node _T_1711 = asUInt(reset) node _T_1712 = eq(_T_1711, UInt<1>(0h0)) when _T_1712 : node _T_1713 = eq(_T_1710, UInt<1>(0h0)) when _T_1713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1710, UInt<1>(0h1), "") : assert_96 node _T_1714 = eq(io.in.d.bits.denied, denied) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_97 node _T_1718 = and(io.in.d.ready, io.in.d.valid) node _T_1719 = and(_T_1718, d_first) when _T_1719 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes : UInt<4104>, clock, reset, UInt<4104>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<513> connect a_set, UInt<513>(0h0) wire a_set_wo_ready : UInt<513> connect a_set_wo_ready, UInt<513>(0h0) wire a_opcodes_set : UInt<2052> connect a_opcodes_set, UInt<2052>(0h0) wire a_sizes_set : UInt<4104> connect a_sizes_set, UInt<4104>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1720 = and(io.in.a.valid, a_first_1) node _T_1721 = and(_T_1720, UInt<1>(0h1)) when _T_1721 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1722 = and(io.in.a.ready, io.in.a.valid) node _T_1723 = and(_T_1722, a_first_1) node _T_1724 = and(_T_1723, UInt<1>(0h1)) when _T_1724 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1725 = dshr(inflight, io.in.a.bits.source) node _T_1726 = bits(_T_1725, 0, 0) node _T_1727 = eq(_T_1726, UInt<1>(0h0)) node _T_1728 = asUInt(reset) node _T_1729 = eq(_T_1728, UInt<1>(0h0)) when _T_1729 : node _T_1730 = eq(_T_1727, UInt<1>(0h0)) when _T_1730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1727, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<513> connect d_clr, UInt<513>(0h0) wire d_clr_wo_ready : UInt<513> connect d_clr_wo_ready, UInt<513>(0h0) wire d_opcodes_clr : UInt<2052> connect d_opcodes_clr, UInt<2052>(0h0) wire d_sizes_clr : UInt<4104> connect d_sizes_clr, UInt<4104>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1731 = and(io.in.d.valid, d_first_1) node _T_1732 = and(_T_1731, UInt<1>(0h1)) node _T_1733 = eq(d_release_ack, UInt<1>(0h0)) node _T_1734 = and(_T_1732, _T_1733) when _T_1734 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1735 = and(io.in.d.ready, io.in.d.valid) node _T_1736 = and(_T_1735, d_first_1) node _T_1737 = and(_T_1736, UInt<1>(0h1)) node _T_1738 = eq(d_release_ack, UInt<1>(0h0)) node _T_1739 = and(_T_1737, _T_1738) when _T_1739 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1740 = and(io.in.d.valid, d_first_1) node _T_1741 = and(_T_1740, UInt<1>(0h1)) node _T_1742 = eq(d_release_ack, UInt<1>(0h0)) node _T_1743 = and(_T_1741, _T_1742) when _T_1743 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1744 = dshr(inflight, io.in.d.bits.source) node _T_1745 = bits(_T_1744, 0, 0) node _T_1746 = or(_T_1745, same_cycle_resp) node _T_1747 = asUInt(reset) node _T_1748 = eq(_T_1747, UInt<1>(0h0)) when _T_1748 : node _T_1749 = eq(_T_1746, UInt<1>(0h0)) when _T_1749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1746, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1750 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1751 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1752 = or(_T_1750, _T_1751) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_100 node _T_1756 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_101 else : node _T_1760 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1761 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1762 = or(_T_1760, _T_1761) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_102 node _T_1766 = eq(io.in.d.bits.size, a_size_lookup) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_103 node _T_1770 = and(io.in.d.valid, d_first_1) node _T_1771 = and(_T_1770, a_first_1) node _T_1772 = and(_T_1771, io.in.a.valid) node _T_1773 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1774 = and(_T_1772, _T_1773) node _T_1775 = eq(d_release_ack, UInt<1>(0h0)) node _T_1776 = and(_T_1774, _T_1775) when _T_1776 : node _T_1777 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1778 = or(_T_1777, io.in.a.ready) node _T_1779 = asUInt(reset) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : node _T_1781 = eq(_T_1778, UInt<1>(0h0)) when _T_1781 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1778, UInt<1>(0h1), "") : assert_104 node _T_1782 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1783 = orr(a_set_wo_ready) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = or(_T_1782, _T_1784) node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(_T_1785, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1785, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_56 node _T_1789 = orr(inflight) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) node _T_1791 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1792 = or(_T_1790, _T_1791) node _T_1793 = lt(watchdog, plusarg_reader.out) node _T_1794 = or(_T_1792, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1798 = and(io.in.a.ready, io.in.a.valid) node _T_1799 = and(io.in.d.ready, io.in.d.valid) node _T_1800 = or(_T_1798, _T_1799) when _T_1800 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0) regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0) regreset inflight_sizes_1 : UInt<4104>, clock, reset, UInt<4104>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<10>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<10>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<513> connect c_set, UInt<513>(0h0) wire c_set_wo_ready : UInt<513> connect c_set_wo_ready, UInt<513>(0h0) wire c_opcodes_set : UInt<2052> connect c_opcodes_set, UInt<2052>(0h0) wire c_sizes_set : UInt<4104> connect c_sizes_set, UInt<4104>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<10>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1801 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<10>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1802 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1803 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1804 = and(_T_1802, _T_1803) node _T_1805 = and(_T_1801, _T_1804) when _T_1805 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<10>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1806 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1807 = and(_T_1806, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<10>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1808 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1809 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1810 = and(_T_1808, _T_1809) node _T_1811 = and(_T_1807, _T_1810) when _T_1811 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<10>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<10>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1812 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1813 = bits(_T_1812, 0, 0) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) node _T_1815 = asUInt(reset) node _T_1816 = eq(_T_1815, UInt<1>(0h0)) when _T_1816 : node _T_1817 = eq(_T_1814, UInt<1>(0h0)) when _T_1817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1814, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<513> connect d_clr_1, UInt<513>(0h0) wire d_clr_wo_ready_1 : UInt<513> connect d_clr_wo_ready_1, UInt<513>(0h0) wire d_opcodes_clr_1 : UInt<2052> connect d_opcodes_clr_1, UInt<2052>(0h0) wire d_sizes_clr_1 : UInt<4104> connect d_sizes_clr_1, UInt<4104>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1818 = and(io.in.d.valid, d_first_2) node _T_1819 = and(_T_1818, UInt<1>(0h1)) node _T_1820 = and(_T_1819, d_release_ack_1) when _T_1820 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1821 = and(io.in.d.ready, io.in.d.valid) node _T_1822 = and(_T_1821, d_first_2) node _T_1823 = and(_T_1822, UInt<1>(0h1)) node _T_1824 = and(_T_1823, d_release_ack_1) when _T_1824 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1825 = and(io.in.d.valid, d_first_2) node _T_1826 = and(_T_1825, UInt<1>(0h1)) node _T_1827 = and(_T_1826, d_release_ack_1) when _T_1827 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1828 = dshr(inflight_1, io.in.d.bits.source) node _T_1829 = bits(_T_1828, 0, 0) node _T_1830 = or(_T_1829, same_cycle_resp_1) node _T_1831 = asUInt(reset) node _T_1832 = eq(_T_1831, UInt<1>(0h0)) when _T_1832 : node _T_1833 = eq(_T_1830, UInt<1>(0h0)) when _T_1833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1830, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<10>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1834 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_109 else : node _T_1838 = eq(io.in.d.bits.size, c_size_lookup) node _T_1839 = asUInt(reset) node _T_1840 = eq(_T_1839, UInt<1>(0h0)) when _T_1840 : node _T_1841 = eq(_T_1838, UInt<1>(0h0)) when _T_1841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1838, UInt<1>(0h1), "") : assert_110 node _T_1842 = and(io.in.d.valid, d_first_2) node _T_1843 = and(_T_1842, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<10>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1844 = and(_T_1843, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<10>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1845 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1846 = and(_T_1844, _T_1845) node _T_1847 = and(_T_1846, d_release_ack_1) node _T_1848 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1849 = and(_T_1847, _T_1848) when _T_1849 : node _T_1850 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<10>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1851 = or(_T_1850, _WIRE_27.ready) node _T_1852 = asUInt(reset) node _T_1853 = eq(_T_1852, UInt<1>(0h0)) when _T_1853 : node _T_1854 = eq(_T_1851, UInt<1>(0h0)) when _T_1854 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1851, UInt<1>(0h1), "") : assert_111 node _T_1855 = orr(c_set_wo_ready) when _T_1855 : node _T_1856 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_57 node _T_1860 = orr(inflight_1) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) node _T_1862 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1863 = or(_T_1861, _T_1862) node _T_1864 = lt(watchdog_1, plusarg_reader_1.out) node _T_1865 = or(_T_1863, _T_1864) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:46:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<10>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1869 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1870 = and(io.in.d.ready, io.in.d.valid) node _T_1871 = or(_T_1869, _T_1870) when _T_1871 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_28( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [9:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [9:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [9:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [512:0] inflight; // @[Monitor.scala:614:27] reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4103:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Monitor.scala:36:7] wire [1023:0] _GEN_0 = {1014'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1023:0] _GEN_3 = {1014'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [512:0] inflight_1; // @[Monitor.scala:726:35] reg [4103:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Monitor.scala:36:7] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module ZstdRawLiteralEncoder : input clock : Clock input reset : Reset output io : { l2io_read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, flip dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, l2io_write : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, bytes_written : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}} inst memloader of MemLoader_1 connect memloader.clock, clock connect memloader.reset, reset connect memloader.io.l2helperUser.no_memops_inflight, io.l2io_read.no_memops_inflight connect memloader.io.l2helperUser.resp, io.l2io_read.resp connect io.l2io_read.req.bits, memloader.io.l2helperUser.req.bits connect io.l2io_read.req.valid, memloader.io.l2helperUser.req.valid connect memloader.io.l2helperUser.req.ready, io.l2io_read.req.ready inst src_size_q of Queue4_UInt64_10 connect src_size_q.clock, clock connect src_size_q.reset, reset inst send_done_q of Queue4_Bool_1 connect send_done_q.clock, clock connect send_done_q.reset, reset connect memloader.io.src_info.bits.isize, io.src_info.bits.isize connect memloader.io.src_info.bits.ip, io.src_info.bits.ip node _memloader_io_src_info_valid_T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _memloader_io_src_info_valid_T_1 = and(_memloader_io_src_info_valid_T, io.src_info.valid) connect memloader.io.src_info.valid, _memloader_io_src_info_valid_T_1 connect src_size_q.io.enq.bits, io.src_info.bits.isize node _src_size_q_io_enq_valid_T = and(send_done_q.io.enq.ready, memloader.io.src_info.ready) node _src_size_q_io_enq_valid_T_1 = and(_src_size_q_io_enq_valid_T, io.src_info.valid) connect src_size_q.io.enq.valid, _src_size_q_io_enq_valid_T_1 connect send_done_q.io.enq.bits, UInt<1>(0h1) node _send_done_q_io_enq_valid_T = and(src_size_q.io.enq.ready, memloader.io.src_info.ready) node _send_done_q_io_enq_valid_T_1 = and(_send_done_q_io_enq_valid_T, io.src_info.valid) connect send_done_q.io.enq.valid, _send_done_q_io_enq_valid_T_1 node _io_src_info_ready_T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _io_src_info_ready_T_1 = and(_io_src_info_ready_T, memloader.io.src_info.ready) connect io.src_info.ready, _io_src_info_ready_T_1 regreset input_copy_req_count : UInt<64>, clock, reset, UInt<64>(0h0) node _T = and(send_done_q.io.enq.ready, src_size_q.io.enq.ready) node _T_1 = and(_T, memloader.io.src_info.ready) node _T_2 = and(_T_1, io.src_info.valid) when _T_2 : node _nxt_input_copy_req_cnt_T = add(input_copy_req_count, UInt<1>(0h1)) node nxt_input_copy_req_cnt = tail(_nxt_input_copy_req_cnt_T, 1) connect input_copy_req_count, nxt_input_copy_req_cnt regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "MEMCPY_SRC_FIRE, input_copy_req_count: %d, src_addr: 0x%x, src_size: %d\n", nxt_input_copy_req_cnt, io.src_info.bits.ip, io.src_info.bits.isize) : printf_1 node _flSize_T = gt(src_size_q.io.deq.bits, UInt<5>(0h1f)) node _flSize_T_1 = mux(_flSize_T, UInt<1>(0h1), UInt<1>(0h0)) node _flSize_T_2 = add(UInt<1>(0h1), _flSize_T_1) node _flSize_T_3 = tail(_flSize_T_2, 1) node _flSize_T_4 = gt(src_size_q.io.deq.bits, UInt<12>(0hfff)) node _flSize_T_5 = mux(_flSize_T_4, UInt<1>(0h1), UInt<1>(0h0)) node _flSize_T_6 = add(_flSize_T_3, _flSize_T_5) node flSize = tail(_flSize_T_6, 1) wire header : UInt<24> node _header_T = eq(flSize, UInt<1>(0h1)) node _header_T_1 = dshl(src_size_q.io.deq.bits, UInt<2>(0h3)) node _header_T_2 = add(UInt<1>(0h0), _header_T_1) node _header_T_3 = tail(_header_T_2, 1) node _header_T_4 = eq(flSize, UInt<2>(0h2)) node _header_T_5 = add(UInt<1>(0h0), UInt<3>(0h4)) node _header_T_6 = tail(_header_T_5, 1) node _header_T_7 = dshl(src_size_q.io.deq.bits, UInt<3>(0h4)) node _header_T_8 = add(_header_T_6, _header_T_7) node _header_T_9 = tail(_header_T_8, 1) node _header_T_10 = add(UInt<1>(0h0), UInt<4>(0hc)) node _header_T_11 = tail(_header_T_10, 1) node _header_T_12 = dshl(src_size_q.io.deq.bits, UInt<3>(0h4)) node _header_T_13 = add(_header_T_11, _header_T_12) node _header_T_14 = tail(_header_T_13, 1) node _header_T_15 = mux(_header_T_4, _header_T_9, _header_T_14) node _header_T_16 = mux(_header_T, _header_T_3, _header_T_15) connect header, _header_T_16 inst memwriter of ZstdCompressorMemWriter_2 connect memwriter.clock, clock connect memwriter.reset, reset connect memwriter.io.l2io.no_memops_inflight, io.l2io_write.no_memops_inflight connect memwriter.io.l2io.resp, io.l2io_write.resp connect io.l2io_write.req.bits, memwriter.io.l2io.req.bits connect io.l2io_write.req.valid, memwriter.io.l2io.req.valid connect memwriter.io.l2io.req.ready, io.l2io_write.req.ready connect memwriter.io.dest_info, io.dst_info regreset header_written : UInt<1>, clock, reset, UInt<1>(0h0) node _T_7 = eq(header_written, UInt<1>(0h0)) node _T_8 = and(src_size_q.io.deq.valid, _T_7) node _T_9 = and(_T_8, memwriter.io.memwrites_in.ready) when _T_9 : connect header_written, UInt<1>(0h1) node _src_size_q_io_deq_ready_T = and(_T_7, memwriter.io.memwrites_in.ready) connect src_size_q.io.deq.ready, _src_size_q_io_deq_ready_T node _header_fire_T = and(src_size_q.io.deq.valid, _T_7) node header_fire = and(_header_fire_T, memwriter.io.memwrites_in.ready) node _memwriter_io_memwrites_in_valid_T = and(src_size_q.io.deq.valid, _T_7) node _memwriter_io_memwrites_in_valid_T_1 = and(memloader.io.consumer.output_valid, header_written) node _memwriter_io_memwrites_in_valid_T_2 = or(_memwriter_io_memwrites_in_valid_T, _memwriter_io_memwrites_in_valid_T_1) connect memwriter.io.memwrites_in.valid, _memwriter_io_memwrites_in_valid_T_2 node _memwriter_io_memwrites_in_bits_data_T = mux(header_fire, header, memloader.io.consumer.output_data) connect memwriter.io.memwrites_in.bits.data, _memwriter_io_memwrites_in_bits_data_T node _memwriter_io_memwrites_in_bits_validbytes_T = mux(header_fire, flSize, memloader.io.consumer.available_output_bytes) connect memwriter.io.memwrites_in.bits.validbytes, _memwriter_io_memwrites_in_bits_validbytes_T node _memwriter_io_memwrites_in_bits_end_of_message_T = mux(header_fire, UInt<1>(0h0), memloader.io.consumer.output_last_chunk) connect memwriter.io.memwrites_in.bits.end_of_message, _memwriter_io_memwrites_in_bits_end_of_message_T node _memloader_io_consumer_output_ready_T = and(memwriter.io.memwrites_in.ready, header_written) connect memloader.io.consumer.output_ready, _memloader_io_consumer_output_ready_T connect memloader.io.consumer.user_consumed_bytes, memloader.io.consumer.available_output_bytes regreset bytes_written : UInt<64>, clock, reset, UInt<64>(0h0) node _T_10 = and(memwriter.io.memwrites_in.ready, memwriter.io.memwrites_in.valid) when _T_10 : node _bytes_written_T = add(bytes_written, memwriter.io.memwrites_in.bits.validbytes) node _bytes_written_T_1 = tail(_bytes_written_T, 1) connect bytes_written, _bytes_written_T_1 node _T_11 = eq(memwriter.io.bufs_completed, input_copy_req_count) node _io_bytes_written_valid_T = and(_T_11, memwriter.io.no_writes_inflight) node _io_bytes_written_valid_T_1 = and(_io_bytes_written_valid_T, send_done_q.io.deq.valid) connect io.bytes_written.valid, _io_bytes_written_valid_T_1 connect io.bytes_written.bits, bytes_written node _send_done_q_io_deq_ready_T = and(_T_11, memwriter.io.no_writes_inflight) node _send_done_q_io_deq_ready_T_1 = and(_send_done_q_io_deq_ready_T, io.bytes_written.ready) connect send_done_q.io.deq.ready, _send_done_q_io_deq_ready_T_1 node _T_12 = and(_T_11, memwriter.io.no_writes_inflight) node _T_13 = and(_T_12, io.bytes_written.ready) node _T_14 = and(_T_13, send_done_q.io.deq.valid) when _T_14 : connect header_written, UInt<1>(0h0) connect bytes_written, UInt<1>(0h0) regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "MEMCPY_DONE_FIRE, bytes_written: %d\n", bytes_written) : printf_3

module ZstdRawLiteralEncoder( // @[ZstdRawLiteralEncoder.scala:23:7] input clock, // @[ZstdRawLiteralEncoder.scala:23:7] input reset, // @[ZstdRawLiteralEncoder.scala:23:7] input io_l2io_read_req_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_read_req_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [70:0] io_l2io_read_req_bits_addr, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_read_resp_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_read_resp_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [255:0] io_l2io_read_resp_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_read_no_memops_inflight, // @[ZstdRawLiteralEncoder.scala:24:14] output io_src_info_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_src_info_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_src_info_bits_ip, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_src_info_bits_isize, // @[ZstdRawLiteralEncoder.scala:24:14] output io_dst_info_ready, // @[ZstdRawLiteralEncoder.scala:24:14] input io_dst_info_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_op, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_cmpflag, // @[ZstdRawLiteralEncoder.scala:24:14] input [63:0] io_dst_info_bits_cmpval, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_req_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_l2io_write_req_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [63:0] io_l2io_write_req_bits_addr, // @[ZstdRawLiteralEncoder.scala:24:14] output [2:0] io_l2io_write_req_bits_size, // @[ZstdRawLiteralEncoder.scala:24:14] output [255:0] io_l2io_write_req_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_resp_valid, // @[ZstdRawLiteralEncoder.scala:24:14] input [255:0] io_l2io_write_resp_bits_data, // @[ZstdRawLiteralEncoder.scala:24:14] input io_l2io_write_no_memops_inflight, // @[ZstdRawLiteralEncoder.scala:24:14] input io_bytes_written_ready, // @[ZstdRawLiteralEncoder.scala:24:14] output io_bytes_written_valid, // @[ZstdRawLiteralEncoder.scala:24:14] output [63:0] io_bytes_written_bits // @[ZstdRawLiteralEncoder.scala:24:14] ); wire _memwriter_io_memwrites_in_ready; // @[ZstdRawLiteralEncoder.scala:68:25] wire [63:0] _memwriter_io_bufs_completed; // @[ZstdRawLiteralEncoder.scala:68:25] wire _memwriter_io_no_writes_inflight; // @[ZstdRawLiteralEncoder.scala:68:25] wire _send_done_q_io_enq_ready; // @[ZstdRawLiteralEncoder.scala:30:27] wire _send_done_q_io_deq_valid; // @[ZstdRawLiteralEncoder.scala:30:27] wire _src_size_q_io_enq_ready; // @[ZstdRawLiteralEncoder.scala:29:26] wire _src_size_q_io_deq_valid; // @[ZstdRawLiteralEncoder.scala:29:26] wire [63:0] _src_size_q_io_deq_bits; // @[ZstdRawLiteralEncoder.scala:29:26] wire _memloader_io_src_info_ready; // @[ZstdRawLiteralEncoder.scala:26:25] wire [5:0] _memloader_io_consumer_available_output_bytes; // @[ZstdRawLiteralEncoder.scala:26:25] wire _memloader_io_consumer_output_valid; // @[ZstdRawLiteralEncoder.scala:26:25] wire [255:0] _memloader_io_consumer_output_data; // @[ZstdRawLiteralEncoder.scala:26:25] wire _memloader_io_consumer_output_last_chunk; // @[ZstdRawLiteralEncoder.scala:26:25] wire io_l2io_read_req_ready_0 = io_l2io_read_req_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_resp_valid_0 = io_l2io_read_resp_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_read_resp_bits_data_0 = io_l2io_read_resp_bits_data; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_no_memops_inflight_0 = io_l2io_read_no_memops_inflight; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_src_info_valid_0 = io_src_info_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_dst_info_valid_0 = io_dst_info_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_op_0 = io_dst_info_bits_op; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_cmpflag_0 = io_dst_info_bits_cmpflag; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_dst_info_bits_cmpval_0 = io_dst_info_bits_cmpval; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_req_ready_0 = io_l2io_write_req_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_resp_valid_0 = io_l2io_write_resp_valid; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_write_resp_bits_data_0 = io_l2io_write_resp_bits_data; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_no_memops_inflight_0 = io_l2io_write_no_memops_inflight; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_bytes_written_ready_0 = io_bytes_written_ready; // @[ZstdRawLiteralEncoder.scala:23:7] wire [2:0] io_l2io_read_req_bits_size = 3'h5; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_read_req_bits_data = 256'h0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_req_bits_cmd = 1'h0; // @[ZstdRawLiteralEncoder.scala:23:7] wire _header_T_4 = 1'h0; // @[ZstdRawLiteralEncoder.scala:65:26] wire io_l2io_write_req_bits_cmd = 1'h1; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_resp_ready = 1'h1; // @[ZstdRawLiteralEncoder.scala:23:7] wire [3:0] _header_T_11 = 4'hC; // @[ZstdRawLiteralEncoder.scala:66:27] wire [2:0] _header_T_6 = 3'h4; // @[ZstdRawLiteralEncoder.scala:65:45] wire [4:0] _header_T_10 = 5'hC; // @[ZstdRawLiteralEncoder.scala:66:27] wire [3:0] _header_T_5 = 4'h4; // @[ZstdRawLiteralEncoder.scala:65:45] wire _io_src_info_ready_T_1; // @[Misc.scala:26:53] wire _io_bytes_written_valid_T_1; // @[Misc.scala:26:53] wire [70:0] io_l2io_read_req_bits_addr_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_req_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_read_resp_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_src_info_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_dst_info_ready_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_l2io_write_req_bits_addr_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [2:0] io_l2io_write_req_bits_size_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [255:0] io_l2io_write_req_bits_data_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_l2io_write_req_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire io_bytes_written_valid_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire [63:0] io_bytes_written_bits_0; // @[ZstdRawLiteralEncoder.scala:23:7] wire _T = _send_done_q_io_enq_ready & _src_size_q_io_enq_ready; // @[Misc.scala:26:53] wire _memloader_io_src_info_valid_T; // @[Misc.scala:26:53] assign _memloader_io_src_info_valid_T = _T; // @[Misc.scala:26:53] wire _io_src_info_ready_T; // @[Misc.scala:26:53] assign _io_src_info_ready_T = _T; // @[Misc.scala:26:53] wire _memloader_io_src_info_valid_T_1 = _memloader_io_src_info_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] wire _src_size_q_io_enq_valid_T = _send_done_q_io_enq_ready & _memloader_io_src_info_ready; // @[Misc.scala:26:53] wire _src_size_q_io_enq_valid_T_1 = _src_size_q_io_enq_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] wire _send_done_q_io_enq_valid_T = _src_size_q_io_enq_ready & _memloader_io_src_info_ready; // @[Misc.scala:26:53] wire _send_done_q_io_enq_valid_T_1 = _send_done_q_io_enq_valid_T & io_src_info_valid_0; // @[Misc.scala:26:53] assign _io_src_info_ready_T_1 = _io_src_info_ready_T & _memloader_io_src_info_ready; // @[Misc.scala:26:53] assign io_src_info_ready_0 = _io_src_info_ready_T_1; // @[Misc.scala:26:53] reg [63:0] input_copy_req_count; // @[ZstdRawLiteralEncoder.scala:49:37] wire _T_2 = _T & _memloader_io_src_info_ready & io_src_info_valid_0; // @[Misc.scala:26:53, :29:18] wire [64:0] _nxt_input_copy_req_cnt_T = {1'h0, input_copy_req_count} + 65'h1; // @[ZstdRawLiteralEncoder.scala:49:37, :51:55] wire [63:0] nxt_input_copy_req_cnt = _nxt_input_copy_req_cnt_T[63:0]; // @[ZstdRawLiteralEncoder.scala:51:55] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] wire _flSize_T = |(_src_size_q_io_deq_bits[63:5]); // @[ZstdRawLiteralEncoder.scala:29:26, :62:41] wire _flSize_T_1 = _flSize_T; // @[ZstdRawLiteralEncoder.scala:62:{25,41}] wire [1:0] _flSize_T_2 = {1'h0, _flSize_T_1} + 2'h1; // @[ZstdRawLiteralEncoder.scala:62:{20,25}] wire _flSize_T_3 = _flSize_T_2[0]; // @[ZstdRawLiteralEncoder.scala:62:20] wire _flSize_T_4 = |(_src_size_q_io_deq_bits[63:12]); // @[ZstdRawLiteralEncoder.scala:29:26, :62:80] wire _flSize_T_5 = _flSize_T_4; // @[ZstdRawLiteralEncoder.scala:62:{64,80}] wire [1:0] _flSize_T_6 = {1'h0, _flSize_T_3} + {1'h0, _flSize_T_5}; // @[ZstdRawLiteralEncoder.scala:62:{20,59,64}] wire flSize = _flSize_T_6[0]; // @[ZstdRawLiteralEncoder.scala:62:59] wire _header_T = flSize; // @[ZstdRawLiteralEncoder.scala:62:59, :64:24] wire [23:0] header; // @[ZstdRawLiteralEncoder.scala:63:20] wire [66:0] _header_T_1 = {_src_size_q_io_deq_bits, 3'h0}; // @[ZstdRawLiteralEncoder.scala:29:26, :64:61] wire [67:0] _header_T_2 = {1'h0, _header_T_1}; // @[ZstdRawLiteralEncoder.scala:64:{43,61}] wire [66:0] _header_T_3 = _header_T_2[66:0]; // @[ZstdRawLiteralEncoder.scala:64:43] wire [70:0] _GEN = {3'h0, _src_size_q_io_deq_bits, 4'h0}; // @[ZstdRawLiteralEncoder.scala:29:26, :64:61, :65:76] wire [70:0] _header_T_7; // @[ZstdRawLiteralEncoder.scala:65:76] assign _header_T_7 = _GEN; // @[ZstdRawLiteralEncoder.scala:65:76] wire [70:0] _header_T_12; // @[ZstdRawLiteralEncoder.scala:66:58] assign _header_T_12 = _GEN; // @[ZstdRawLiteralEncoder.scala:65:76, :66:58] wire [71:0] _header_T_8 = {1'h0, _header_T_7} + 72'h4; // @[ZstdRawLiteralEncoder.scala:65:{58,76}] wire [70:0] _header_T_9 = _header_T_8[70:0]; // @[ZstdRawLiteralEncoder.scala:65:58] wire [71:0] _header_T_13 = {1'h0, _header_T_12} + 72'hC; // @[ZstdRawLiteralEncoder.scala:66:{40,58}] wire [70:0] _header_T_14 = _header_T_13[70:0]; // @[ZstdRawLiteralEncoder.scala:66:40] wire [70:0] _header_T_15 = _header_T_4 ? _header_T_9 : _header_T_14; // @[ZstdRawLiteralEncoder.scala:65:{18,26,58}, :66:40] wire [70:0] _header_T_16 = _header_T ? {4'h0, _header_T_3} : _header_T_15; // @[ZstdRawLiteralEncoder.scala:64:{16,24,43}, :65:{18,76}] assign header = _header_T_16[23:0]; // @[ZstdRawLiteralEncoder.scala:63:20, :64:{10,16}] reg header_written; // @[ZstdRawLiteralEncoder.scala:72:31] wire _T_8 = _src_size_q_io_deq_valid & ~header_written; // @[Misc.scala:29:18] wire _header_fire_T; // @[Misc.scala:29:18] assign _header_fire_T = _T_8; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_valid_T; // @[Misc.scala:26:53] assign _memwriter_io_memwrites_in_valid_T = _T_8; // @[Misc.scala:26:53, :29:18] wire _src_size_q_io_deq_ready_T = ~header_written & _memwriter_io_memwrites_in_ready; // @[Misc.scala:26:53] wire header_fire = _header_fire_T & _memwriter_io_memwrites_in_ready; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_valid_T_1 = _memloader_io_consumer_output_valid & header_written; // @[Misc.scala:26:53] wire _memwriter_io_memwrites_in_valid_T_2 = _memwriter_io_memwrites_in_valid_T | _memwriter_io_memwrites_in_valid_T_1; // @[Misc.scala:26:53] wire [255:0] _memwriter_io_memwrites_in_bits_data_T = header_fire ? {232'h0, header} : _memloader_io_consumer_output_data; // @[Misc.scala:29:18] wire [5:0] _memwriter_io_memwrites_in_bits_validbytes_T = header_fire ? {5'h0, flSize} : _memloader_io_consumer_available_output_bytes; // @[Misc.scala:29:18] wire _memwriter_io_memwrites_in_bits_end_of_message_T = ~header_fire & _memloader_io_consumer_output_last_chunk; // @[Misc.scala:29:18] wire _memloader_io_consumer_output_ready_T = _memwriter_io_memwrites_in_ready & header_written; // @[Misc.scala:26:53] reg [63:0] bytes_written; // @[ZstdRawLiteralEncoder.scala:104:30] assign io_bytes_written_bits_0 = bytes_written; // @[ZstdRawLiteralEncoder.scala:23:7, :104:30] wire [64:0] _bytes_written_T = {1'h0, bytes_written} + {59'h0, _memwriter_io_memwrites_in_bits_validbytes_T}; // @[ZstdRawLiteralEncoder.scala:96:51, :104:30, :106:36] wire [63:0] _bytes_written_T_1 = _bytes_written_T[63:0]; // @[ZstdRawLiteralEncoder.scala:106:36] wire _T_12 = _memwriter_io_bufs_completed == input_copy_req_count & _memwriter_io_no_writes_inflight; // @[Misc.scala:26:53] wire _io_bytes_written_valid_T; // @[Misc.scala:26:53] assign _io_bytes_written_valid_T = _T_12; // @[Misc.scala:26:53] wire _send_done_q_io_deq_ready_T; // @[Misc.scala:26:53] assign _send_done_q_io_deq_ready_T = _T_12; // @[Misc.scala:26:53] assign _io_bytes_written_valid_T_1 = _io_bytes_written_valid_T & _send_done_q_io_deq_valid; // @[Misc.scala:26:53] assign io_bytes_written_valid_0 = _io_bytes_written_valid_T_1; // @[Misc.scala:26:53] wire _send_done_q_io_deq_ready_T_1 = _send_done_q_io_deq_ready_T & io_bytes_written_ready_0; // @[Misc.scala:26:53] wire _T_14 = _T_12 & io_bytes_written_ready_0 & _send_done_q_io_deq_valid; // @[Misc.scala:26:53, :29:18] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]

Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e5_s11_1 : input clock : Clock input reset : Reset output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>, validout : UInt<1>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e5_s11_1 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e5_s11_1 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) wire valid_stage0 : UInt<1> wire roundingMode_stage0 : UInt<3> wire detectTininess_stage0 : UInt<1> regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}} connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<23>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<23>} connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock when io.validin : connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundingMode_stage0_pipe_v, io.validin reg roundingMode_stage0_pipe_b : UInt<3>, clock when io.validin : connect roundingMode_stage0_pipe_b, io.roundingMode wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect detectTininess_stage0_pipe_v, io.validin reg detectTininess_stage0_pipe_b : UInt<1>, clock when io.validin : connect detectTininess_stage0_pipe_b, io.detectTininess wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect valid_stage0_pipe_v, io.validin reg valid_stage0_pipe_b : UInt<1>, clock when io.validin : connect valid_stage0_pipe_b, UInt<1>(0h0) wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b connect valid_stage0, valid_stage0_pipe_out.valid inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_2 regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, clock when valid_stage0 : connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock when valid_stage0 : connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0 wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>} connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0 reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock when valid_stage0 : connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0 wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect io_validout_pipe_v, valid_stage0 reg io_validout_pipe_b : UInt<1>, clock when valid_stage0 : connect io_validout_pipe_b, UInt<1>(0h0) wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect io_validout_pipe_out.valid, io_validout_pipe_v connect io_validout_pipe_out.bits, io_validout_pipe_b connect io.validout, io_validout_pipe_out.valid connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags

module MulAddRecFNPipe_l2_e5_s11_1( // @[FPU.scala:633:7] input clock, // @[FPU.scala:633:7] input reset, // @[FPU.scala:633:7] input io_validin, // @[FPU.scala:638:16] input [1:0] io_op, // @[FPU.scala:638:16] input [16:0] io_a, // @[FPU.scala:638:16] input [16:0] io_b, // @[FPU.scala:638:16] input [16:0] io_c, // @[FPU.scala:638:16] input [2:0] io_roundingMode, // @[FPU.scala:638:16] output [16:0] io_out, // @[FPU.scala:638:16] output [4:0] io_exceptionFlags, // @[FPU.scala:638:16] output io_validout // @[FPU.scala:638:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42] wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42] wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41] wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41] wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41] wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41] wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41] wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41] wire io_validin_0 = io_validin; // @[FPU.scala:633:7] wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7] wire [16:0] io_a_0 = io_a; // @[FPU.scala:633:7] wire [16:0] io_b_0 = io_b; // @[FPU.scala:633:7] wire [16:0] io_c_0 = io_c; // @[FPU.scala:633:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7] wire io_detectTininess = 1'h1; // @[FPU.scala:633:7] wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37] wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21] wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21] wire io_validout_pipe_out_valid; // @[Valid.scala:135:21] wire [16:0] io_out_0; // @[FPU.scala:633:7] wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7] wire io_validout_0; // @[FPU.scala:633:7] wire [21:0] _mulAddResult_T = {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45] wire [22:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50] wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] wire valid_stage0; // @[FPU.scala:667:28] wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26] reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26] wire [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26] reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26] wire [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26] reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26] wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26] wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24] reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26] wire [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26] reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24] wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26] assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26] assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21] reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24] wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] reg valid_stage0_pipe_v; // @[Valid.scala:141:24] assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24] assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21] reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26] reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26] wire [6:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26] reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26] wire [13:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24] reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26] wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26] reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24] wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24] reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26] reg io_validout_pipe_v; // @[Valid.scala:141:24] assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24] assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:633:7] if (reset) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24] roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24] io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24] end if (io_validin_0) begin // @[FPU.scala:633:7] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26] end if (valid_stage0) begin // @[FPU.scala:667:28] roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26] roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26] roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26] end roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26] always @(posedge) MulAddRecFNToRaw_preMul_e5_s11_1 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41] .io_op (io_op_0), // @[FPU.scala:633:7] .io_a (io_a_0), // @[FPU.scala:633:7] .io_b (io_b_0), // @[FPU.scala:633:7] .io_c (io_c_0), // @[FPU.scala:633:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[FPU.scala:654:41] MulAddRecFNToRaw_postMul_e5_s11_1 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42] .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21] .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21] .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21] .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21] .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21] .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21] .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21] .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21] .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21] .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21] .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21] .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21] .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21] .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21] .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21] .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21] .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21] .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[FPU.scala:655:42] RoundRawFNToRecFN_e5_s11_2 roundRawFNToRecFN ( // @[FPU.scala:682:35] .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21] .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21] .io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21] .io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21] .io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21] .io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21] .io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21] .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21] .io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[FPU.scala:682:35] assign io_out = io_out_0; // @[FPU.scala:633:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7] assign io_validout = io_validout_0; // @[FPU.scala:633:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module LSU : input clock : Clock input reset : Reset output io : { ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, core : { flip agen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[1], flip dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[3], iwakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1], iresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], fresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip dis_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], dis_ldq_idx : UInt<5>[3], dis_stq_idx : UInt<5>[3], ldq_full : UInt<1>[3], stq_full : UInt<1>[3], flip commit : { valids : UInt<1>[3], arch_valids : UInt<1>[3], uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[3], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[3], debug_wdata : UInt<64>[3]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<7>}[3], clr_unsafe : { valid : UInt<1>, bits : UInt<7>}[1], flip fence_dmem : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip tsc_reg : UInt, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt, flip scontext : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1]}, s1_kill : UInt<1>[1], flip s1_nack_advisory : UInt<1>[1], flip resp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}[1], flip store_ack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip nack : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1], flip ll_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, is_hella : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, exception : UInt<1>, rob_pnr_idx : UInt<7>, rob_head_idx : UInt<7>, flip release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, force_order : UInt<1>, flip ordered : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>}}, flip hellacache : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}} reg ldq_valid : UInt<1>[24], clock reg ldq_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock reg ldq_addr : { valid : UInt<1>, bits : UInt<40>}[24], clock reg ldq_addr_is_virtual : UInt<1>[24], clock reg ldq_addr_is_uncacheable : UInt<1>[24], clock reg ldq_executed : UInt<1>[24], clock reg ldq_succeeded : UInt<1>[24], clock reg ldq_order_fail : UInt<1>[24], clock reg ldq_observed : UInt<1>[24], clock reg ldq_st_dep_mask : UInt<24>[24], clock reg ldq_ld_byte_mask : UInt<8>[24], clock reg ldq_forward_std_val : UInt<1>[24], clock reg ldq_forward_stq_idx : UInt<5>[24], clock reg ldq_debug_wb_data : UInt<64>[24], clock reg stq_valid : UInt<1>[24], clock reg stq_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[24], clock reg stq_addr : { valid : UInt<1>, bits : UInt<40>}[24], clock reg stq_addr_is_virtual : UInt<1>[24], clock reg stq_data : { valid : UInt<1>, bits : UInt<64>}[24], clock reg stq_committed : UInt<1>[24], clock reg stq_succeeded : UInt<1>[24], clock reg stq_can_execute : UInt<1>[24], clock reg stq_cleared : UInt<1>[24], clock reg stq_debug_wb_data : UInt<64>[24], clock reg ldq_head : UInt<5>, clock reg ldq_tail : UInt<5>, clock reg stq_head : UInt<5>, clock reg stq_tail : UInt<5>, clock reg stq_commit_head : UInt<5>, clock reg stq_execute_head : UInt<5>, clock regreset hella_state : UInt<3>, clock, reset, UInt<3>(0h0) reg hella_req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock reg hella_data : { data : UInt<64>, mask : UInt<8>}, clock reg hella_paddr : UInt<32>, clock reg hella_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, clock inst dtlb of NBDTLB connect dtlb.clock, clock connect dtlb.reset, reset connect dtlb.io.ptw.customCSRs, io.ptw.customCSRs connect dtlb.io.ptw.pmp[0], io.ptw.pmp[0] connect dtlb.io.ptw.pmp[1], io.ptw.pmp[1] connect dtlb.io.ptw.pmp[2], io.ptw.pmp[2] connect dtlb.io.ptw.pmp[3], io.ptw.pmp[3] connect dtlb.io.ptw.pmp[4], io.ptw.pmp[4] connect dtlb.io.ptw.pmp[5], io.ptw.pmp[5] connect dtlb.io.ptw.pmp[6], io.ptw.pmp[6] connect dtlb.io.ptw.pmp[7], io.ptw.pmp[7] connect dtlb.io.ptw.gstatus, io.ptw.gstatus connect dtlb.io.ptw.hstatus, io.ptw.hstatus connect dtlb.io.ptw.status, io.ptw.status connect dtlb.io.ptw.vsatp, io.ptw.vsatp connect dtlb.io.ptw.hgatp, io.ptw.hgatp connect dtlb.io.ptw.ptbr, io.ptw.ptbr connect dtlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, dtlb.io.ptw.req.bits connect io.ptw.req.valid, dtlb.io.ptw.req.valid connect dtlb.io.ptw.req.ready, io.ptw.req.ready node _io_core_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.core.perf.tlbMiss, _io_core_perf_tlbMiss_T connect io.core.perf.acquire, io.dmem.perf.acquire connect io.core.perf.release, io.dmem.perf.release wire clear_store : UInt<1> connect clear_store, UInt<1>(0h0) wire ldq_will_succeed : UInt<1>[24] connect ldq_will_succeed, ldq_succeeded connect ldq_succeeded, ldq_will_succeed when clear_store : node _ldq_st_dep_mask_0_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_0_T_1 = not(_ldq_st_dep_mask_0_T) node _ldq_st_dep_mask_0_T_2 = and(ldq_st_dep_mask[0], _ldq_st_dep_mask_0_T_1) connect ldq_st_dep_mask[0], _ldq_st_dep_mask_0_T_2 when clear_store : node _ldq_st_dep_mask_1_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_1_T_1 = not(_ldq_st_dep_mask_1_T) node _ldq_st_dep_mask_1_T_2 = and(ldq_st_dep_mask[1], _ldq_st_dep_mask_1_T_1) connect ldq_st_dep_mask[1], _ldq_st_dep_mask_1_T_2 when clear_store : node _ldq_st_dep_mask_2_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_2_T_1 = not(_ldq_st_dep_mask_2_T) node _ldq_st_dep_mask_2_T_2 = and(ldq_st_dep_mask[2], _ldq_st_dep_mask_2_T_1) connect ldq_st_dep_mask[2], _ldq_st_dep_mask_2_T_2 when clear_store : node _ldq_st_dep_mask_3_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_3_T_1 = not(_ldq_st_dep_mask_3_T) node _ldq_st_dep_mask_3_T_2 = and(ldq_st_dep_mask[3], _ldq_st_dep_mask_3_T_1) connect ldq_st_dep_mask[3], _ldq_st_dep_mask_3_T_2 when clear_store : node _ldq_st_dep_mask_4_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_4_T_1 = not(_ldq_st_dep_mask_4_T) node _ldq_st_dep_mask_4_T_2 = and(ldq_st_dep_mask[4], _ldq_st_dep_mask_4_T_1) connect ldq_st_dep_mask[4], _ldq_st_dep_mask_4_T_2 when clear_store : node _ldq_st_dep_mask_5_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_5_T_1 = not(_ldq_st_dep_mask_5_T) node _ldq_st_dep_mask_5_T_2 = and(ldq_st_dep_mask[5], _ldq_st_dep_mask_5_T_1) connect ldq_st_dep_mask[5], _ldq_st_dep_mask_5_T_2 when clear_store : node _ldq_st_dep_mask_6_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_6_T_1 = not(_ldq_st_dep_mask_6_T) node _ldq_st_dep_mask_6_T_2 = and(ldq_st_dep_mask[6], _ldq_st_dep_mask_6_T_1) connect ldq_st_dep_mask[6], _ldq_st_dep_mask_6_T_2 when clear_store : node _ldq_st_dep_mask_7_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_7_T_1 = not(_ldq_st_dep_mask_7_T) node _ldq_st_dep_mask_7_T_2 = and(ldq_st_dep_mask[7], _ldq_st_dep_mask_7_T_1) connect ldq_st_dep_mask[7], _ldq_st_dep_mask_7_T_2 when clear_store : node _ldq_st_dep_mask_8_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_8_T_1 = not(_ldq_st_dep_mask_8_T) node _ldq_st_dep_mask_8_T_2 = and(ldq_st_dep_mask[8], _ldq_st_dep_mask_8_T_1) connect ldq_st_dep_mask[8], _ldq_st_dep_mask_8_T_2 when clear_store : node _ldq_st_dep_mask_9_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_9_T_1 = not(_ldq_st_dep_mask_9_T) node _ldq_st_dep_mask_9_T_2 = and(ldq_st_dep_mask[9], _ldq_st_dep_mask_9_T_1) connect ldq_st_dep_mask[9], _ldq_st_dep_mask_9_T_2 when clear_store : node _ldq_st_dep_mask_10_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_10_T_1 = not(_ldq_st_dep_mask_10_T) node _ldq_st_dep_mask_10_T_2 = and(ldq_st_dep_mask[10], _ldq_st_dep_mask_10_T_1) connect ldq_st_dep_mask[10], _ldq_st_dep_mask_10_T_2 when clear_store : node _ldq_st_dep_mask_11_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_11_T_1 = not(_ldq_st_dep_mask_11_T) node _ldq_st_dep_mask_11_T_2 = and(ldq_st_dep_mask[11], _ldq_st_dep_mask_11_T_1) connect ldq_st_dep_mask[11], _ldq_st_dep_mask_11_T_2 when clear_store : node _ldq_st_dep_mask_12_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_12_T_1 = not(_ldq_st_dep_mask_12_T) node _ldq_st_dep_mask_12_T_2 = and(ldq_st_dep_mask[12], _ldq_st_dep_mask_12_T_1) connect ldq_st_dep_mask[12], _ldq_st_dep_mask_12_T_2 when clear_store : node _ldq_st_dep_mask_13_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_13_T_1 = not(_ldq_st_dep_mask_13_T) node _ldq_st_dep_mask_13_T_2 = and(ldq_st_dep_mask[13], _ldq_st_dep_mask_13_T_1) connect ldq_st_dep_mask[13], _ldq_st_dep_mask_13_T_2 when clear_store : node _ldq_st_dep_mask_14_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_14_T_1 = not(_ldq_st_dep_mask_14_T) node _ldq_st_dep_mask_14_T_2 = and(ldq_st_dep_mask[14], _ldq_st_dep_mask_14_T_1) connect ldq_st_dep_mask[14], _ldq_st_dep_mask_14_T_2 when clear_store : node _ldq_st_dep_mask_15_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_15_T_1 = not(_ldq_st_dep_mask_15_T) node _ldq_st_dep_mask_15_T_2 = and(ldq_st_dep_mask[15], _ldq_st_dep_mask_15_T_1) connect ldq_st_dep_mask[15], _ldq_st_dep_mask_15_T_2 when clear_store : node _ldq_st_dep_mask_16_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_16_T_1 = not(_ldq_st_dep_mask_16_T) node _ldq_st_dep_mask_16_T_2 = and(ldq_st_dep_mask[16], _ldq_st_dep_mask_16_T_1) connect ldq_st_dep_mask[16], _ldq_st_dep_mask_16_T_2 when clear_store : node _ldq_st_dep_mask_17_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_17_T_1 = not(_ldq_st_dep_mask_17_T) node _ldq_st_dep_mask_17_T_2 = and(ldq_st_dep_mask[17], _ldq_st_dep_mask_17_T_1) connect ldq_st_dep_mask[17], _ldq_st_dep_mask_17_T_2 when clear_store : node _ldq_st_dep_mask_18_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_18_T_1 = not(_ldq_st_dep_mask_18_T) node _ldq_st_dep_mask_18_T_2 = and(ldq_st_dep_mask[18], _ldq_st_dep_mask_18_T_1) connect ldq_st_dep_mask[18], _ldq_st_dep_mask_18_T_2 when clear_store : node _ldq_st_dep_mask_19_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_19_T_1 = not(_ldq_st_dep_mask_19_T) node _ldq_st_dep_mask_19_T_2 = and(ldq_st_dep_mask[19], _ldq_st_dep_mask_19_T_1) connect ldq_st_dep_mask[19], _ldq_st_dep_mask_19_T_2 when clear_store : node _ldq_st_dep_mask_20_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_20_T_1 = not(_ldq_st_dep_mask_20_T) node _ldq_st_dep_mask_20_T_2 = and(ldq_st_dep_mask[20], _ldq_st_dep_mask_20_T_1) connect ldq_st_dep_mask[20], _ldq_st_dep_mask_20_T_2 when clear_store : node _ldq_st_dep_mask_21_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_21_T_1 = not(_ldq_st_dep_mask_21_T) node _ldq_st_dep_mask_21_T_2 = and(ldq_st_dep_mask[21], _ldq_st_dep_mask_21_T_1) connect ldq_st_dep_mask[21], _ldq_st_dep_mask_21_T_2 when clear_store : node _ldq_st_dep_mask_22_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_22_T_1 = not(_ldq_st_dep_mask_22_T) node _ldq_st_dep_mask_22_T_2 = and(ldq_st_dep_mask[22], _ldq_st_dep_mask_22_T_1) connect ldq_st_dep_mask[22], _ldq_st_dep_mask_22_T_2 when clear_store : node _ldq_st_dep_mask_23_T = dshl(UInt<1>(0h1), stq_head) node _ldq_st_dep_mask_23_T_1 = not(_ldq_st_dep_mask_23_T) node _ldq_st_dep_mask_23_T_2 = and(ldq_st_dep_mask[23], _ldq_st_dep_mask_23_T_1) connect ldq_st_dep_mask[23], _ldq_st_dep_mask_23_T_2 reg dis_ldq_oh : UInt<1>[24], clock reg dis_stq_oh : UInt<1>[24], clock connect dis_ldq_oh[0], UInt<1>(0h0) connect dis_ldq_oh[1], UInt<1>(0h0) connect dis_ldq_oh[2], UInt<1>(0h0) connect dis_ldq_oh[3], UInt<1>(0h0) connect dis_ldq_oh[4], UInt<1>(0h0) connect dis_ldq_oh[5], UInt<1>(0h0) connect dis_ldq_oh[6], UInt<1>(0h0) connect dis_ldq_oh[7], UInt<1>(0h0) connect dis_ldq_oh[8], UInt<1>(0h0) connect dis_ldq_oh[9], UInt<1>(0h0) connect dis_ldq_oh[10], UInt<1>(0h0) connect dis_ldq_oh[11], UInt<1>(0h0) connect dis_ldq_oh[12], UInt<1>(0h0) connect dis_ldq_oh[13], UInt<1>(0h0) connect dis_ldq_oh[14], UInt<1>(0h0) connect dis_ldq_oh[15], UInt<1>(0h0) connect dis_ldq_oh[16], UInt<1>(0h0) connect dis_ldq_oh[17], UInt<1>(0h0) connect dis_ldq_oh[18], UInt<1>(0h0) connect dis_ldq_oh[19], UInt<1>(0h0) connect dis_ldq_oh[20], UInt<1>(0h0) connect dis_ldq_oh[21], UInt<1>(0h0) connect dis_ldq_oh[22], UInt<1>(0h0) connect dis_ldq_oh[23], UInt<1>(0h0) connect dis_stq_oh[0], UInt<1>(0h0) connect dis_stq_oh[1], UInt<1>(0h0) connect dis_stq_oh[2], UInt<1>(0h0) connect dis_stq_oh[3], UInt<1>(0h0) connect dis_stq_oh[4], UInt<1>(0h0) connect dis_stq_oh[5], UInt<1>(0h0) connect dis_stq_oh[6], UInt<1>(0h0) connect dis_stq_oh[7], UInt<1>(0h0) connect dis_stq_oh[8], UInt<1>(0h0) connect dis_stq_oh[9], UInt<1>(0h0) connect dis_stq_oh[10], UInt<1>(0h0) connect dis_stq_oh[11], UInt<1>(0h0) connect dis_stq_oh[12], UInt<1>(0h0) connect dis_stq_oh[13], UInt<1>(0h0) connect dis_stq_oh[14], UInt<1>(0h0) connect dis_stq_oh[15], UInt<1>(0h0) connect dis_stq_oh[16], UInt<1>(0h0) connect dis_stq_oh[17], UInt<1>(0h0) connect dis_stq_oh[18], UInt<1>(0h0) connect dis_stq_oh[19], UInt<1>(0h0) connect dis_stq_oh[20], UInt<1>(0h0) connect dis_stq_oh[21], UInt<1>(0h0) connect dis_stq_oh[22], UInt<1>(0h0) connect dis_stq_oh[23], UInt<1>(0h0) reg dis_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], clock node live_store_mask_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node live_store_mask_lo_lo_lo = cat(live_store_mask_lo_lo_lo_hi, stq_valid[0]) node live_store_mask_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node live_store_mask_lo_lo_hi = cat(live_store_mask_lo_lo_hi_hi, stq_valid[3]) node live_store_mask_lo_lo = cat(live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo) node live_store_mask_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node live_store_mask_lo_hi_lo = cat(live_store_mask_lo_hi_lo_hi, stq_valid[6]) node live_store_mask_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node live_store_mask_lo_hi_hi = cat(live_store_mask_lo_hi_hi_hi, stq_valid[9]) node live_store_mask_lo_hi = cat(live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo) node live_store_mask_lo = cat(live_store_mask_lo_hi, live_store_mask_lo_lo) node live_store_mask_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node live_store_mask_hi_lo_lo = cat(live_store_mask_hi_lo_lo_hi, stq_valid[12]) node live_store_mask_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node live_store_mask_hi_lo_hi = cat(live_store_mask_hi_lo_hi_hi, stq_valid[15]) node live_store_mask_hi_lo = cat(live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo) node live_store_mask_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node live_store_mask_hi_hi_lo = cat(live_store_mask_hi_hi_lo_hi, stq_valid[18]) node live_store_mask_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node live_store_mask_hi_hi_hi = cat(live_store_mask_hi_hi_hi_hi, stq_valid[21]) node live_store_mask_hi_hi = cat(live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo) node live_store_mask_hi = cat(live_store_mask_hi_hi, live_store_mask_hi_lo) node _live_store_mask_T = cat(live_store_mask_hi, live_store_mask_lo) node live_store_mask_lo_lo_lo_hi_1 = cat(dis_stq_oh[2], dis_stq_oh[1]) node live_store_mask_lo_lo_lo_1 = cat(live_store_mask_lo_lo_lo_hi_1, dis_stq_oh[0]) node live_store_mask_lo_lo_hi_hi_1 = cat(dis_stq_oh[5], dis_stq_oh[4]) node live_store_mask_lo_lo_hi_1 = cat(live_store_mask_lo_lo_hi_hi_1, dis_stq_oh[3]) node live_store_mask_lo_lo_1 = cat(live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1) node live_store_mask_lo_hi_lo_hi_1 = cat(dis_stq_oh[8], dis_stq_oh[7]) node live_store_mask_lo_hi_lo_1 = cat(live_store_mask_lo_hi_lo_hi_1, dis_stq_oh[6]) node live_store_mask_lo_hi_hi_hi_1 = cat(dis_stq_oh[11], dis_stq_oh[10]) node live_store_mask_lo_hi_hi_1 = cat(live_store_mask_lo_hi_hi_hi_1, dis_stq_oh[9]) node live_store_mask_lo_hi_1 = cat(live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1) node live_store_mask_lo_1 = cat(live_store_mask_lo_hi_1, live_store_mask_lo_lo_1) node live_store_mask_hi_lo_lo_hi_1 = cat(dis_stq_oh[14], dis_stq_oh[13]) node live_store_mask_hi_lo_lo_1 = cat(live_store_mask_hi_lo_lo_hi_1, dis_stq_oh[12]) node live_store_mask_hi_lo_hi_hi_1 = cat(dis_stq_oh[17], dis_stq_oh[16]) node live_store_mask_hi_lo_hi_1 = cat(live_store_mask_hi_lo_hi_hi_1, dis_stq_oh[15]) node live_store_mask_hi_lo_1 = cat(live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1) node live_store_mask_hi_hi_lo_hi_1 = cat(dis_stq_oh[20], dis_stq_oh[19]) node live_store_mask_hi_hi_lo_1 = cat(live_store_mask_hi_hi_lo_hi_1, dis_stq_oh[18]) node live_store_mask_hi_hi_hi_hi_1 = cat(dis_stq_oh[23], dis_stq_oh[22]) node live_store_mask_hi_hi_hi_1 = cat(live_store_mask_hi_hi_hi_hi_1, dis_stq_oh[21]) node live_store_mask_hi_hi_1 = cat(live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1) node live_store_mask_hi_1 = cat(live_store_mask_hi_hi_1, live_store_mask_hi_lo_1) node _live_store_mask_T_1 = cat(live_store_mask_hi_1, live_store_mask_lo_1) node live_store_mask = or(_live_store_mask_T, _live_store_mask_T_1) node _next_live_store_mask_T = dshl(UInt<1>(0h1), stq_head) node _next_live_store_mask_T_1 = not(_next_live_store_mask_T) node _next_live_store_mask_T_2 = and(live_store_mask, _next_live_store_mask_T_1) node next_live_store_mask = mux(clear_store, _next_live_store_mask_T_2, live_store_mask) node _ldq_tail_oh_T = dshl(UInt<1>(0h1), ldq_tail) node ldq_tail_oh = bits(_ldq_tail_oh_T, 23, 0) node ldq_valids_lo_lo_lo_hi = cat(ldq_valid[2], ldq_valid[1]) node ldq_valids_lo_lo_lo = cat(ldq_valids_lo_lo_lo_hi, ldq_valid[0]) node ldq_valids_lo_lo_hi_hi = cat(ldq_valid[5], ldq_valid[4]) node ldq_valids_lo_lo_hi = cat(ldq_valids_lo_lo_hi_hi, ldq_valid[3]) node ldq_valids_lo_lo = cat(ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo) node ldq_valids_lo_hi_lo_hi = cat(ldq_valid[8], ldq_valid[7]) node ldq_valids_lo_hi_lo = cat(ldq_valids_lo_hi_lo_hi, ldq_valid[6]) node ldq_valids_lo_hi_hi_hi = cat(ldq_valid[11], ldq_valid[10]) node ldq_valids_lo_hi_hi = cat(ldq_valids_lo_hi_hi_hi, ldq_valid[9]) node ldq_valids_lo_hi = cat(ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo) node ldq_valids_lo = cat(ldq_valids_lo_hi, ldq_valids_lo_lo) node ldq_valids_hi_lo_lo_hi = cat(ldq_valid[14], ldq_valid[13]) node ldq_valids_hi_lo_lo = cat(ldq_valids_hi_lo_lo_hi, ldq_valid[12]) node ldq_valids_hi_lo_hi_hi = cat(ldq_valid[17], ldq_valid[16]) node ldq_valids_hi_lo_hi = cat(ldq_valids_hi_lo_hi_hi, ldq_valid[15]) node ldq_valids_hi_lo = cat(ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo) node ldq_valids_hi_hi_lo_hi = cat(ldq_valid[20], ldq_valid[19]) node ldq_valids_hi_hi_lo = cat(ldq_valids_hi_hi_lo_hi, ldq_valid[18]) node ldq_valids_hi_hi_hi_hi = cat(ldq_valid[23], ldq_valid[22]) node ldq_valids_hi_hi_hi = cat(ldq_valids_hi_hi_hi_hi, ldq_valid[21]) node ldq_valids_hi_hi = cat(ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo) node ldq_valids_hi = cat(ldq_valids_hi_hi, ldq_valids_hi_lo) node _ldq_valids_T = cat(ldq_valids_hi, ldq_valids_lo) node ldq_valids_lo_lo_lo_hi_1 = cat(dis_ldq_oh[2], dis_ldq_oh[1]) node ldq_valids_lo_lo_lo_1 = cat(ldq_valids_lo_lo_lo_hi_1, dis_ldq_oh[0]) node ldq_valids_lo_lo_hi_hi_1 = cat(dis_ldq_oh[5], dis_ldq_oh[4]) node ldq_valids_lo_lo_hi_1 = cat(ldq_valids_lo_lo_hi_hi_1, dis_ldq_oh[3]) node ldq_valids_lo_lo_1 = cat(ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1) node ldq_valids_lo_hi_lo_hi_1 = cat(dis_ldq_oh[8], dis_ldq_oh[7]) node ldq_valids_lo_hi_lo_1 = cat(ldq_valids_lo_hi_lo_hi_1, dis_ldq_oh[6]) node ldq_valids_lo_hi_hi_hi_1 = cat(dis_ldq_oh[11], dis_ldq_oh[10]) node ldq_valids_lo_hi_hi_1 = cat(ldq_valids_lo_hi_hi_hi_1, dis_ldq_oh[9]) node ldq_valids_lo_hi_1 = cat(ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1) node ldq_valids_lo_1 = cat(ldq_valids_lo_hi_1, ldq_valids_lo_lo_1) node ldq_valids_hi_lo_lo_hi_1 = cat(dis_ldq_oh[14], dis_ldq_oh[13]) node ldq_valids_hi_lo_lo_1 = cat(ldq_valids_hi_lo_lo_hi_1, dis_ldq_oh[12]) node ldq_valids_hi_lo_hi_hi_1 = cat(dis_ldq_oh[17], dis_ldq_oh[16]) node ldq_valids_hi_lo_hi_1 = cat(ldq_valids_hi_lo_hi_hi_1, dis_ldq_oh[15]) node ldq_valids_hi_lo_1 = cat(ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1) node ldq_valids_hi_hi_lo_hi_1 = cat(dis_ldq_oh[20], dis_ldq_oh[19]) node ldq_valids_hi_hi_lo_1 = cat(ldq_valids_hi_hi_lo_hi_1, dis_ldq_oh[18]) node ldq_valids_hi_hi_hi_hi_1 = cat(dis_ldq_oh[23], dis_ldq_oh[22]) node ldq_valids_hi_hi_hi_1 = cat(ldq_valids_hi_hi_hi_hi_1, dis_ldq_oh[21]) node ldq_valids_hi_hi_1 = cat(ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1) node ldq_valids_hi_1 = cat(ldq_valids_hi_hi_1, ldq_valids_hi_lo_1) node _ldq_valids_T_1 = cat(ldq_valids_hi_1, ldq_valids_lo_1) node ldq_valids = or(_ldq_valids_T, _ldq_valids_T_1) node _stq_tail_oh_T = dshl(UInt<1>(0h1), stq_tail) node stq_tail_oh = bits(_stq_tail_oh_T, 23, 0) node stq_valids_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node stq_valids_lo_lo_lo = cat(stq_valids_lo_lo_lo_hi, stq_valid[0]) node stq_valids_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node stq_valids_lo_lo_hi = cat(stq_valids_lo_lo_hi_hi, stq_valid[3]) node stq_valids_lo_lo = cat(stq_valids_lo_lo_hi, stq_valids_lo_lo_lo) node stq_valids_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node stq_valids_lo_hi_lo = cat(stq_valids_lo_hi_lo_hi, stq_valid[6]) node stq_valids_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node stq_valids_lo_hi_hi = cat(stq_valids_lo_hi_hi_hi, stq_valid[9]) node stq_valids_lo_hi = cat(stq_valids_lo_hi_hi, stq_valids_lo_hi_lo) node stq_valids_lo = cat(stq_valids_lo_hi, stq_valids_lo_lo) node stq_valids_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node stq_valids_hi_lo_lo = cat(stq_valids_hi_lo_lo_hi, stq_valid[12]) node stq_valids_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node stq_valids_hi_lo_hi = cat(stq_valids_hi_lo_hi_hi, stq_valid[15]) node stq_valids_hi_lo = cat(stq_valids_hi_lo_hi, stq_valids_hi_lo_lo) node stq_valids_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node stq_valids_hi_hi_lo = cat(stq_valids_hi_hi_lo_hi, stq_valid[18]) node stq_valids_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node stq_valids_hi_hi_hi = cat(stq_valids_hi_hi_hi_hi, stq_valid[21]) node stq_valids_hi_hi = cat(stq_valids_hi_hi_hi, stq_valids_hi_hi_lo) node stq_valids_hi = cat(stq_valids_hi_hi, stq_valids_hi_lo) node _stq_valids_T = cat(stq_valids_hi, stq_valids_lo) node stq_valids_lo_lo_lo_hi_1 = cat(dis_stq_oh[2], dis_stq_oh[1]) node stq_valids_lo_lo_lo_1 = cat(stq_valids_lo_lo_lo_hi_1, dis_stq_oh[0]) node stq_valids_lo_lo_hi_hi_1 = cat(dis_stq_oh[5], dis_stq_oh[4]) node stq_valids_lo_lo_hi_1 = cat(stq_valids_lo_lo_hi_hi_1, dis_stq_oh[3]) node stq_valids_lo_lo_1 = cat(stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1) node stq_valids_lo_hi_lo_hi_1 = cat(dis_stq_oh[8], dis_stq_oh[7]) node stq_valids_lo_hi_lo_1 = cat(stq_valids_lo_hi_lo_hi_1, dis_stq_oh[6]) node stq_valids_lo_hi_hi_hi_1 = cat(dis_stq_oh[11], dis_stq_oh[10]) node stq_valids_lo_hi_hi_1 = cat(stq_valids_lo_hi_hi_hi_1, dis_stq_oh[9]) node stq_valids_lo_hi_1 = cat(stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1) node stq_valids_lo_1 = cat(stq_valids_lo_hi_1, stq_valids_lo_lo_1) node stq_valids_hi_lo_lo_hi_1 = cat(dis_stq_oh[14], dis_stq_oh[13]) node stq_valids_hi_lo_lo_1 = cat(stq_valids_hi_lo_lo_hi_1, dis_stq_oh[12]) node stq_valids_hi_lo_hi_hi_1 = cat(dis_stq_oh[17], dis_stq_oh[16]) node stq_valids_hi_lo_hi_1 = cat(stq_valids_hi_lo_hi_hi_1, dis_stq_oh[15]) node stq_valids_hi_lo_1 = cat(stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1) node stq_valids_hi_hi_lo_hi_1 = cat(dis_stq_oh[20], dis_stq_oh[19]) node stq_valids_hi_hi_lo_1 = cat(stq_valids_hi_hi_lo_hi_1, dis_stq_oh[18]) node stq_valids_hi_hi_hi_hi_1 = cat(dis_stq_oh[23], dis_stq_oh[22]) node stq_valids_hi_hi_hi_1 = cat(stq_valids_hi_hi_hi_hi_1, dis_stq_oh[21]) node stq_valids_hi_hi_1 = cat(stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1) node stq_valids_hi_1 = cat(stq_valids_hi_hi_1, stq_valids_hi_lo_1) node _stq_valids_T_1 = cat(stq_valids_hi_1, stq_valids_lo_1) node stq_valids = or(_stq_valids_T, _stq_valids_T_1) node _stq_nonempty_T = or(stq_valid[0], stq_valid[1]) node _stq_nonempty_T_1 = or(_stq_nonempty_T, stq_valid[2]) node _stq_nonempty_T_2 = or(_stq_nonempty_T_1, stq_valid[3]) node _stq_nonempty_T_3 = or(_stq_nonempty_T_2, stq_valid[4]) node _stq_nonempty_T_4 = or(_stq_nonempty_T_3, stq_valid[5]) node _stq_nonempty_T_5 = or(_stq_nonempty_T_4, stq_valid[6]) node _stq_nonempty_T_6 = or(_stq_nonempty_T_5, stq_valid[7]) node _stq_nonempty_T_7 = or(_stq_nonempty_T_6, stq_valid[8]) node _stq_nonempty_T_8 = or(_stq_nonempty_T_7, stq_valid[9]) node _stq_nonempty_T_9 = or(_stq_nonempty_T_8, stq_valid[10]) node _stq_nonempty_T_10 = or(_stq_nonempty_T_9, stq_valid[11]) node _stq_nonempty_T_11 = or(_stq_nonempty_T_10, stq_valid[12]) node _stq_nonempty_T_12 = or(_stq_nonempty_T_11, stq_valid[13]) node _stq_nonempty_T_13 = or(_stq_nonempty_T_12, stq_valid[14]) node _stq_nonempty_T_14 = or(_stq_nonempty_T_13, stq_valid[15]) node _stq_nonempty_T_15 = or(_stq_nonempty_T_14, stq_valid[16]) node _stq_nonempty_T_16 = or(_stq_nonempty_T_15, stq_valid[17]) node _stq_nonempty_T_17 = or(_stq_nonempty_T_16, stq_valid[18]) node _stq_nonempty_T_18 = or(_stq_nonempty_T_17, stq_valid[19]) node _stq_nonempty_T_19 = or(_stq_nonempty_T_18, stq_valid[20]) node _stq_nonempty_T_20 = or(_stq_nonempty_T_19, stq_valid[21]) node _stq_nonempty_T_21 = or(_stq_nonempty_T_20, stq_valid[22]) node stq_nonempty = or(_stq_nonempty_T_21, stq_valid[23]) node _ldq_full_T = and(ldq_tail_oh, ldq_valids) node ldq_full = orr(_ldq_full_T) connect io.core.ldq_full[0], ldq_full connect io.core.dis_ldq_idx[0], ldq_tail node _stq_full_T = and(stq_tail_oh, stq_valids) node stq_full = orr(_stq_full_T) connect io.core.stq_full[0], stq_full connect io.core.dis_stq_idx[0], stq_tail node _dis_ld_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_ldq) node _dis_ld_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node dis_ld_val = and(_dis_ld_val_T, _dis_ld_val_T_1) node _dis_st_val_T = and(io.core.dis_uops[0].valid, io.core.dis_uops[0].bits.uses_stq) node _dis_st_val_T_1 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node dis_st_val = and(_dis_st_val_T, _dis_st_val_T_1) node _dis_uops_0_valid_T = or(dis_ld_val, dis_st_val) connect dis_uops[0].valid, _dis_uops_0_valid_T connect dis_uops[0].bits, io.core.dis_uops[0].bits when dis_ld_val : connect dis_ldq_oh[ldq_tail], UInt<1>(0h1) connect ldq_st_dep_mask[ldq_tail], next_live_store_mask node _T = eq(ldq_tail, io.core.dis_uops[0].bits.ldq_idx) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _T_4 = eq(ldq_valid[ldq_tail], UInt<1>(0h0)) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_1 assert(clock, _T_4, UInt<1>(0h1), "") : assert_1 when dis_st_val : connect dis_stq_oh[stq_tail], UInt<1>(0h1) node _T_8 = eq(stq_tail, io.core.dis_uops[0].bits.stq_idx) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_2 assert(clock, _T_8, UInt<1>(0h1), "") : assert_2 node _T_12 = eq(stq_valid[stq_tail], UInt<1>(0h0)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_3 assert(clock, _T_12, UInt<1>(0h1), "") : assert_3 node _T_16 = and(dis_uops[0].valid, dis_uops[0].bits.uses_ldq) when _T_16 : node _ldq_valid_T = and(io.core.brupdate.b1.mispredict_mask, dis_uops[0].bits.br_mask) node _ldq_valid_T_1 = neq(_ldq_valid_T, UInt<1>(0h0)) node _ldq_valid_T_2 = or(_ldq_valid_T_1, io.core.exception) node _ldq_valid_T_3 = eq(_ldq_valid_T_2, UInt<1>(0h0)) connect ldq_valid[dis_uops[0].bits.ldq_idx], _ldq_valid_T_3 wire ldq_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out, dis_uops[0].bits node _ldq_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_1 = and(dis_uops[0].bits.br_mask, _ldq_uop_out_br_mask_T) connect ldq_uop_out.br_mask, _ldq_uop_out_br_mask_T_1 connect ldq_uop[dis_uops[0].bits.ldq_idx], ldq_uop_out connect ldq_addr[dis_uops[0].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[0].bits.ldq_idx], UInt<1>(0h0) node _T_17 = and(dis_uops[0].valid, dis_uops[0].bits.uses_stq) when _T_17 : node _stq_valid_T = and(io.core.brupdate.b1.mispredict_mask, dis_uops[0].bits.br_mask) node _stq_valid_T_1 = neq(_stq_valid_T, UInt<1>(0h0)) node _stq_valid_T_2 = or(_stq_valid_T_1, io.core.exception) node _stq_valid_T_3 = eq(_stq_valid_T_2, UInt<1>(0h0)) connect stq_valid[dis_uops[0].bits.stq_idx], _stq_valid_T_3 wire stq_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out, dis_uops[0].bits node _stq_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_1 = and(dis_uops[0].bits.br_mask, _stq_uop_out_br_mask_T) connect stq_uop_out.br_mask, _stq_uop_out_br_mask_T_1 connect stq_uop[dis_uops[0].bits.stq_idx], stq_uop_out connect stq_addr[dis_uops[0].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[0].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[0].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[0].bits.stq_idx], UInt<1>(0h0) node wrap = eq(ldq_tail, UInt<5>(0h17)) node _T_18 = add(ldq_tail, UInt<1>(0h1)) node _T_19 = tail(_T_18, 1) node _T_20 = mux(wrap, UInt<1>(0h0), _T_19) node _T_21 = mux(dis_ld_val, _T_20, ldq_tail) node _T_22 = dshl(UInt<1>(0h1), stq_tail) node _T_23 = or(next_live_store_mask, _T_22) node _T_24 = mux(dis_st_val, _T_23, next_live_store_mask) node wrap_1 = eq(stq_tail, UInt<5>(0h17)) node _T_25 = add(stq_tail, UInt<1>(0h1)) node _T_26 = tail(_T_25, 1) node _T_27 = mux(wrap_1, UInt<1>(0h0), _T_26) node _T_28 = mux(dis_st_val, _T_27, stq_tail) node _T_29 = and(dis_ld_val, dis_st_val) node _T_30 = eq(_T_29, UInt<1>(0h0)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_4 assert(clock, _T_30, UInt<1>(0h1), "") : assert_4 node _T_34 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node _T_35 = and(io.core.dis_uops[0].bits.uses_ldq, _T_34) node _T_36 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_37 = or(_T_35, _T_36) node _out_T = bits(ldq_tail_oh, 22, 0) node _out_T_1 = bits(ldq_tail_oh, 23, 23) node out = cat(_out_T, _out_T_1) node _T_38 = mux(_T_37, out, ldq_tail_oh) node _T_39 = eq(io.core.dis_uops[0].bits.exception, UInt<1>(0h0)) node _T_40 = and(io.core.dis_uops[0].bits.uses_stq, _T_39) node _T_41 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _out_T_2 = bits(stq_tail_oh, 22, 0) node _out_T_3 = bits(stq_tail_oh, 23, 23) node out_1 = cat(_out_T_2, _out_T_3) node _T_43 = mux(_T_42, out_1, stq_tail_oh) node _ldq_full_T_1 = and(_T_38, ldq_valids) node ldq_full_1 = orr(_ldq_full_T_1) connect io.core.ldq_full[1], ldq_full_1 connect io.core.dis_ldq_idx[1], _T_21 node _stq_full_T_1 = and(_T_43, stq_valids) node stq_full_1 = orr(_stq_full_T_1) connect io.core.stq_full[1], stq_full_1 connect io.core.dis_stq_idx[1], _T_28 node _dis_ld_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_ldq) node _dis_ld_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node dis_ld_val_1 = and(_dis_ld_val_T_2, _dis_ld_val_T_3) node _dis_st_val_T_2 = and(io.core.dis_uops[1].valid, io.core.dis_uops[1].bits.uses_stq) node _dis_st_val_T_3 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node dis_st_val_1 = and(_dis_st_val_T_2, _dis_st_val_T_3) node _dis_uops_1_valid_T = or(dis_ld_val_1, dis_st_val_1) connect dis_uops[1].valid, _dis_uops_1_valid_T connect dis_uops[1].bits, io.core.dis_uops[1].bits when dis_ld_val_1 : connect dis_ldq_oh[_T_21], UInt<1>(0h1) connect ldq_st_dep_mask[_T_21], _T_24 node _T_44 = eq(_T_21, io.core.dis_uops[1].bits.ldq_idx) node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : node _T_47 = eq(_T_44, UInt<1>(0h0)) when _T_47 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_5 assert(clock, _T_44, UInt<1>(0h1), "") : assert_5 node _T_48 = eq(ldq_valid[_T_21], UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_6 assert(clock, _T_48, UInt<1>(0h1), "") : assert_6 when dis_st_val_1 : connect dis_stq_oh[_T_28], UInt<1>(0h1) node _T_52 = eq(_T_28, io.core.dis_uops[1].bits.stq_idx) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 node _T_56 = eq(stq_valid[_T_28], UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_8 assert(clock, _T_56, UInt<1>(0h1), "") : assert_8 node _T_60 = and(dis_uops[1].valid, dis_uops[1].bits.uses_ldq) when _T_60 : node _ldq_valid_T_4 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[1].bits.br_mask) node _ldq_valid_T_5 = neq(_ldq_valid_T_4, UInt<1>(0h0)) node _ldq_valid_T_6 = or(_ldq_valid_T_5, io.core.exception) node _ldq_valid_T_7 = eq(_ldq_valid_T_6, UInt<1>(0h0)) connect ldq_valid[dis_uops[1].bits.ldq_idx], _ldq_valid_T_7 wire ldq_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out_1, dis_uops[1].bits node _ldq_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_3 = and(dis_uops[1].bits.br_mask, _ldq_uop_out_br_mask_T_2) connect ldq_uop_out_1.br_mask, _ldq_uop_out_br_mask_T_3 connect ldq_uop[dis_uops[1].bits.ldq_idx], ldq_uop_out_1 connect ldq_addr[dis_uops[1].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[1].bits.ldq_idx], UInt<1>(0h0) node _T_61 = and(dis_uops[1].valid, dis_uops[1].bits.uses_stq) when _T_61 : node _stq_valid_T_4 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[1].bits.br_mask) node _stq_valid_T_5 = neq(_stq_valid_T_4, UInt<1>(0h0)) node _stq_valid_T_6 = or(_stq_valid_T_5, io.core.exception) node _stq_valid_T_7 = eq(_stq_valid_T_6, UInt<1>(0h0)) connect stq_valid[dis_uops[1].bits.stq_idx], _stq_valid_T_7 wire stq_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out_1, dis_uops[1].bits node _stq_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_3 = and(dis_uops[1].bits.br_mask, _stq_uop_out_br_mask_T_2) connect stq_uop_out_1.br_mask, _stq_uop_out_br_mask_T_3 connect stq_uop[dis_uops[1].bits.stq_idx], stq_uop_out_1 connect stq_addr[dis_uops[1].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[1].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[1].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[1].bits.stq_idx], UInt<1>(0h0) node wrap_2 = eq(_T_21, UInt<5>(0h17)) node _T_62 = add(_T_21, UInt<1>(0h1)) node _T_63 = tail(_T_62, 1) node _T_64 = mux(wrap_2, UInt<1>(0h0), _T_63) node _T_65 = mux(dis_ld_val_1, _T_64, _T_21) node _T_66 = dshl(UInt<1>(0h1), _T_28) node _T_67 = or(_T_24, _T_66) node _T_68 = mux(dis_st_val_1, _T_67, _T_24) node wrap_3 = eq(_T_28, UInt<5>(0h17)) node _T_69 = add(_T_28, UInt<1>(0h1)) node _T_70 = tail(_T_69, 1) node _T_71 = mux(wrap_3, UInt<1>(0h0), _T_70) node _T_72 = mux(dis_st_val_1, _T_71, _T_28) node _T_73 = and(dis_ld_val_1, dis_st_val_1) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_9 assert(clock, _T_74, UInt<1>(0h1), "") : assert_9 node _T_78 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node _T_79 = and(io.core.dis_uops[1].bits.uses_ldq, _T_78) node _T_80 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_81 = or(_T_79, _T_80) node _out_T_4 = bits(_T_38, 22, 0) node _out_T_5 = bits(_T_38, 23, 23) node out_2 = cat(_out_T_4, _out_T_5) node _T_82 = mux(_T_81, out_2, _T_38) node _T_83 = eq(io.core.dis_uops[1].bits.exception, UInt<1>(0h0)) node _T_84 = and(io.core.dis_uops[1].bits.uses_stq, _T_83) node _T_85 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_86 = or(_T_84, _T_85) node _out_T_6 = bits(_T_43, 22, 0) node _out_T_7 = bits(_T_43, 23, 23) node out_3 = cat(_out_T_6, _out_T_7) node _T_87 = mux(_T_86, out_3, _T_43) node _ldq_full_T_2 = and(_T_82, ldq_valids) node ldq_full_2 = orr(_ldq_full_T_2) connect io.core.ldq_full[2], ldq_full_2 connect io.core.dis_ldq_idx[2], _T_65 node _stq_full_T_2 = and(_T_87, stq_valids) node stq_full_2 = orr(_stq_full_T_2) connect io.core.stq_full[2], stq_full_2 connect io.core.dis_stq_idx[2], _T_72 node _dis_ld_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_ldq) node _dis_ld_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node dis_ld_val_2 = and(_dis_ld_val_T_4, _dis_ld_val_T_5) node _dis_st_val_T_4 = and(io.core.dis_uops[2].valid, io.core.dis_uops[2].bits.uses_stq) node _dis_st_val_T_5 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node dis_st_val_2 = and(_dis_st_val_T_4, _dis_st_val_T_5) node _dis_uops_2_valid_T = or(dis_ld_val_2, dis_st_val_2) connect dis_uops[2].valid, _dis_uops_2_valid_T connect dis_uops[2].bits, io.core.dis_uops[2].bits when dis_ld_val_2 : connect dis_ldq_oh[_T_65], UInt<1>(0h1) connect ldq_st_dep_mask[_T_65], _T_68 node _T_88 = eq(_T_65, io.core.dis_uops[2].bits.ldq_idx) node _T_89 = asUInt(reset) node _T_90 = eq(_T_89, UInt<1>(0h0)) when _T_90 : node _T_91 = eq(_T_88, UInt<1>(0h0)) when _T_91 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq load tag.\n at lsu.scala:386 assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n") : printf_10 assert(clock, _T_88, UInt<1>(0h1), "") : assert_10 node _T_92 = eq(ldq_valid[_T_65], UInt<1>(0h0)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting ldq entries\n at lsu.scala:387 assert (!ldq_valid(ld_enq_idx), \"[lsu] Enqueuing uop is overwriting ldq entries\")\n") : printf_11 assert(clock, _T_92, UInt<1>(0h1), "") : assert_11 when dis_st_val_2 : connect dis_stq_oh[_T_72], UInt<1>(0h1) node _T_96 = eq(_T_72, io.core.dis_uops[2].bits.stq_idx) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] mismatch enq store tag.\n at lsu.scala:391 assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n") : printf_12 assert(clock, _T_96, UInt<1>(0h1), "") : assert_12 node _T_100 = eq(stq_valid[_T_72], UInt<1>(0h0)) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Enqueuing uop is overwriting stq entries\n at lsu.scala:392 assert (!stq_valid(st_enq_idx), \"[lsu] Enqueuing uop is overwriting stq entries\")\n") : printf_13 assert(clock, _T_100, UInt<1>(0h1), "") : assert_13 node _T_104 = and(dis_uops[2].valid, dis_uops[2].bits.uses_ldq) when _T_104 : node _ldq_valid_T_8 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[2].bits.br_mask) node _ldq_valid_T_9 = neq(_ldq_valid_T_8, UInt<1>(0h0)) node _ldq_valid_T_10 = or(_ldq_valid_T_9, io.core.exception) node _ldq_valid_T_11 = eq(_ldq_valid_T_10, UInt<1>(0h0)) connect ldq_valid[dis_uops[2].bits.ldq_idx], _ldq_valid_T_11 wire ldq_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ldq_uop_out_2, dis_uops[2].bits node _ldq_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_out_br_mask_T_5 = and(dis_uops[2].bits.br_mask, _ldq_uop_out_br_mask_T_4) connect ldq_uop_out_2.br_mask, _ldq_uop_out_br_mask_T_5 connect ldq_uop[dis_uops[2].bits.ldq_idx], ldq_uop_out_2 connect ldq_addr[dis_uops[2].bits.ldq_idx].valid, UInt<1>(0h0) connect ldq_executed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_will_succeed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_order_fail[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_observed[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) connect ldq_forward_std_val[dis_uops[2].bits.ldq_idx], UInt<1>(0h0) node _T_105 = and(dis_uops[2].valid, dis_uops[2].bits.uses_stq) when _T_105 : node _stq_valid_T_8 = and(io.core.brupdate.b1.mispredict_mask, dis_uops[2].bits.br_mask) node _stq_valid_T_9 = neq(_stq_valid_T_8, UInt<1>(0h0)) node _stq_valid_T_10 = or(_stq_valid_T_9, io.core.exception) node _stq_valid_T_11 = eq(_stq_valid_T_10, UInt<1>(0h0)) connect stq_valid[dis_uops[2].bits.stq_idx], _stq_valid_T_11 wire stq_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect stq_uop_out_2, dis_uops[2].bits node _stq_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_out_br_mask_T_5 = and(dis_uops[2].bits.br_mask, _stq_uop_out_br_mask_T_4) connect stq_uop_out_2.br_mask, _stq_uop_out_br_mask_T_5 connect stq_uop[dis_uops[2].bits.stq_idx], stq_uop_out_2 connect stq_addr[dis_uops[2].bits.stq_idx].valid, UInt<1>(0h0) connect stq_data[dis_uops[2].bits.stq_idx].valid, UInt<1>(0h0) connect stq_committed[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_can_execute[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_succeeded[dis_uops[2].bits.stq_idx], UInt<1>(0h0) connect stq_cleared[dis_uops[2].bits.stq_idx], UInt<1>(0h0) node wrap_4 = eq(_T_65, UInt<5>(0h17)) node _T_106 = add(_T_65, UInt<1>(0h1)) node _T_107 = tail(_T_106, 1) node _T_108 = mux(wrap_4, UInt<1>(0h0), _T_107) node _T_109 = mux(dis_ld_val_2, _T_108, _T_65) node _T_110 = dshl(UInt<1>(0h1), _T_72) node _T_111 = or(_T_68, _T_110) node _T_112 = mux(dis_st_val_2, _T_111, _T_68) node wrap_5 = eq(_T_72, UInt<5>(0h17)) node _T_113 = add(_T_72, UInt<1>(0h1)) node _T_114 = tail(_T_113, 1) node _T_115 = mux(wrap_5, UInt<1>(0h0), _T_114) node _T_116 = mux(dis_st_val_2, _T_115, _T_72) node _T_117 = and(dis_ld_val_2, dis_st_val_2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: A UOP is trying to go into both the LDQ and the STQ\n at lsu.scala:426 assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n") : printf_14 assert(clock, _T_118, UInt<1>(0h1), "") : assert_14 node _T_122 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node _T_123 = and(io.core.dis_uops[2].bits.uses_ldq, _T_122) node _T_124 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_125 = or(_T_123, _T_124) node _out_T_8 = bits(_T_82, 22, 0) node _out_T_9 = bits(_T_82, 23, 23) node out_4 = cat(_out_T_8, _out_T_9) node _T_126 = mux(_T_125, out_4, _T_82) node _T_127 = eq(io.core.dis_uops[2].bits.exception, UInt<1>(0h0)) node _T_128 = and(io.core.dis_uops[2].bits.uses_stq, _T_127) node _T_129 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_130 = or(_T_128, _T_129) node _out_T_10 = bits(_T_87, 22, 0) node _out_T_11 = bits(_T_87, 23, 23) node out_5 = cat(_out_T_10, _out_T_11) node _T_131 = mux(_T_130, out_5, _T_87) connect ldq_tail, _T_109 connect stq_tail, _T_116 node _T_132 = or(io.core.brupdate.b2.mispredict, stq_valid[stq_execute_head]) node _T_133 = or(_T_132, dis_stq_oh[stq_execute_head]) node _T_134 = eq(stq_head, stq_execute_head) node _T_135 = or(_T_133, _T_134) node _T_136 = eq(stq_tail, stq_execute_head) node _T_137 = or(_T_135, _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: stq_execute_head got off track.\n at lsu.scala:438 assert (io.core.brupdate.b2.mispredict ||\n") : printf_15 assert(clock, _T_137, UInt<1>(0h1), "") : assert_15 connect io.dmem.force_order, io.core.fence_dmem node _io_core_fencei_rdy_T = eq(stq_nonempty, UInt<1>(0h0)) node _io_core_fencei_rdy_T_1 = and(_io_core_fencei_rdy_T, io.dmem.ordered) connect io.core.fencei_rdy, _io_core_fencei_rdy_T_1 wire mem_xcpt_valid : UInt<1> wire mem_xcpt_cause : UInt wire mem_xcpt_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire mem_xcpt_vaddr : UInt wire will_fire_load_agen_exec : UInt<1>[1] wire will_fire_load_agen : UInt<1>[1] wire will_fire_store_agen : UInt<1>[1] wire will_fire_sfence : UInt<1>[1] wire will_fire_hella_incoming : UInt<1>[1] wire will_fire_hella_wakeup : UInt<1>[1] wire will_fire_release : UInt<1>[1] wire will_fire_load_retry : UInt<1>[1] wire will_fire_store_retry : UInt<1>[1] wire will_fire_store_commit_fast : UInt<1>[1] wire will_fire_store_commit_slow : UInt<1>[1] wire will_fire_load_wakeup : UInt<1>[1] wire _block_load_mask_WIRE : UInt<1>[24] connect _block_load_mask_WIRE[0], UInt<1>(0h0) connect _block_load_mask_WIRE[1], UInt<1>(0h0) connect _block_load_mask_WIRE[2], UInt<1>(0h0) connect _block_load_mask_WIRE[3], UInt<1>(0h0) connect _block_load_mask_WIRE[4], UInt<1>(0h0) connect _block_load_mask_WIRE[5], UInt<1>(0h0) connect _block_load_mask_WIRE[6], UInt<1>(0h0) connect _block_load_mask_WIRE[7], UInt<1>(0h0) connect _block_load_mask_WIRE[8], UInt<1>(0h0) connect _block_load_mask_WIRE[9], UInt<1>(0h0) connect _block_load_mask_WIRE[10], UInt<1>(0h0) connect _block_load_mask_WIRE[11], UInt<1>(0h0) connect _block_load_mask_WIRE[12], UInt<1>(0h0) connect _block_load_mask_WIRE[13], UInt<1>(0h0) connect _block_load_mask_WIRE[14], UInt<1>(0h0) connect _block_load_mask_WIRE[15], UInt<1>(0h0) connect _block_load_mask_WIRE[16], UInt<1>(0h0) connect _block_load_mask_WIRE[17], UInt<1>(0h0) connect _block_load_mask_WIRE[18], UInt<1>(0h0) connect _block_load_mask_WIRE[19], UInt<1>(0h0) connect _block_load_mask_WIRE[20], UInt<1>(0h0) connect _block_load_mask_WIRE[21], UInt<1>(0h0) connect _block_load_mask_WIRE[22], UInt<1>(0h0) connect _block_load_mask_WIRE[23], UInt<1>(0h0) wire block_load_mask : UInt<1>[24] connect block_load_mask, _block_load_mask_WIRE reg p1_block_load_mask : UInt<1>[24], clock connect p1_block_load_mask, block_load_mask reg p2_block_load_mask : UInt<1>[24], clock connect p2_block_load_mask, p1_block_load_mask node _stq_tail_plus_sum_T = cat(UInt<1>(0h0), stq_tail) node _stq_tail_plus_sum_T_1 = cat(UInt<1>(0h0), UInt<3>(0h6)) node _stq_tail_plus_sum_T_2 = add(_stq_tail_plus_sum_T, _stq_tail_plus_sum_T_1) node stq_tail_plus_sum = tail(_stq_tail_plus_sum_T_2, 1) node _stq_tail_plus_T = geq(stq_tail_plus_sum, UInt<5>(0h18)) node _stq_tail_plus_T_1 = sub(stq_tail_plus_sum, UInt<5>(0h18)) node _stq_tail_plus_T_2 = tail(_stq_tail_plus_T_1, 1) node stq_tail_plus = mux(_stq_tail_plus_T, _stq_tail_plus_T_2, stq_tail_plus_sum) node _stq_almost_full_T = lt(stq_head, stq_tail_plus) node _stq_almost_full_T_1 = lt(stq_head, stq_tail) node _stq_almost_full_T_2 = xor(_stq_almost_full_T, _stq_almost_full_T_1) node _stq_almost_full_T_3 = lt(stq_tail_plus, stq_tail) node _stq_almost_full_T_4 = xor(_stq_almost_full_T_2, _stq_almost_full_T_3) reg stq_almost_full : UInt<1>, clock connect stq_almost_full, _stq_almost_full_T_4 wire store_needs_order : UInt<1> connect store_needs_order, UInt<1>(0h0) wire ldq_incoming_idx : UInt<5>[1] connect ldq_incoming_idx[0], io.core.agen[0].bits.uop.ldq_idx wire ldq_incoming_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_incoming_e_e.valid, ldq_valid[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.uop, ldq_uop[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr, ldq_addr[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.executed, ldq_executed[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.succeeded, ldq_succeeded[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.order_fail, ldq_order_fail[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.observed, ldq_observed[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.st_dep_mask, ldq_st_dep_mask[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.forward_std_val, ldq_forward_std_val[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[ldq_incoming_idx[0]] connect ldq_incoming_e_e.bits.debug_wb_data, ldq_debug_wb_data[ldq_incoming_idx[0]] wire _ldq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect _ldq_incoming_e_WIRE, ldq_incoming_e_e wire ldq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect ldq_incoming_e[0], _ldq_incoming_e_WIRE wire stq_incoming_idx : UInt<5>[1] connect stq_incoming_idx[0], io.core.agen[0].bits.uop.stq_idx wire stq_incoming_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_incoming_e_e.valid, stq_valid[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.uop, stq_uop[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.addr, stq_addr[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.data, stq_data[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.committed, stq_committed[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.succeeded, stq_succeeded[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.can_execute, stq_can_execute[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.cleared, stq_cleared[stq_incoming_idx[0]] connect stq_incoming_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_incoming_idx[0]] wire _stq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect _stq_incoming_e_WIRE, stq_incoming_e_e wire stq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect stq_incoming_e[0], _stq_incoming_e_WIRE node ldq_wakeup_idx_block = or(block_load_mask[0], p1_block_load_mask[0]) node _ldq_wakeup_idx_T = eq(ldq_executed[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_1 = and(ldq_addr[0].valid, _ldq_wakeup_idx_T) node _ldq_wakeup_idx_T_2 = eq(ldq_succeeded[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_3 = and(_ldq_wakeup_idx_T_1, _ldq_wakeup_idx_T_2) node _ldq_wakeup_idx_T_4 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _ldq_wakeup_idx_T_5 = and(_ldq_wakeup_idx_T_3, _ldq_wakeup_idx_T_4) node _ldq_wakeup_idx_T_6 = eq(ldq_wakeup_idx_block, UInt<1>(0h0)) node _ldq_wakeup_idx_T_7 = and(_ldq_wakeup_idx_T_5, _ldq_wakeup_idx_T_6) node ldq_wakeup_idx_block_1 = or(block_load_mask[1], p1_block_load_mask[1]) node _ldq_wakeup_idx_T_8 = eq(ldq_executed[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_9 = and(ldq_addr[1].valid, _ldq_wakeup_idx_T_8) node _ldq_wakeup_idx_T_10 = eq(ldq_succeeded[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_11 = and(_ldq_wakeup_idx_T_9, _ldq_wakeup_idx_T_10) node _ldq_wakeup_idx_T_12 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _ldq_wakeup_idx_T_13 = and(_ldq_wakeup_idx_T_11, _ldq_wakeup_idx_T_12) node _ldq_wakeup_idx_T_14 = eq(ldq_wakeup_idx_block_1, UInt<1>(0h0)) node _ldq_wakeup_idx_T_15 = and(_ldq_wakeup_idx_T_13, _ldq_wakeup_idx_T_14) node ldq_wakeup_idx_block_2 = or(block_load_mask[2], p1_block_load_mask[2]) node _ldq_wakeup_idx_T_16 = eq(ldq_executed[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_17 = and(ldq_addr[2].valid, _ldq_wakeup_idx_T_16) node _ldq_wakeup_idx_T_18 = eq(ldq_succeeded[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_19 = and(_ldq_wakeup_idx_T_17, _ldq_wakeup_idx_T_18) node _ldq_wakeup_idx_T_20 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _ldq_wakeup_idx_T_21 = and(_ldq_wakeup_idx_T_19, _ldq_wakeup_idx_T_20) node _ldq_wakeup_idx_T_22 = eq(ldq_wakeup_idx_block_2, UInt<1>(0h0)) node _ldq_wakeup_idx_T_23 = and(_ldq_wakeup_idx_T_21, _ldq_wakeup_idx_T_22) node ldq_wakeup_idx_block_3 = or(block_load_mask[3], p1_block_load_mask[3]) node _ldq_wakeup_idx_T_24 = eq(ldq_executed[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_25 = and(ldq_addr[3].valid, _ldq_wakeup_idx_T_24) node _ldq_wakeup_idx_T_26 = eq(ldq_succeeded[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_27 = and(_ldq_wakeup_idx_T_25, _ldq_wakeup_idx_T_26) node _ldq_wakeup_idx_T_28 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _ldq_wakeup_idx_T_29 = and(_ldq_wakeup_idx_T_27, _ldq_wakeup_idx_T_28) node _ldq_wakeup_idx_T_30 = eq(ldq_wakeup_idx_block_3, UInt<1>(0h0)) node _ldq_wakeup_idx_T_31 = and(_ldq_wakeup_idx_T_29, _ldq_wakeup_idx_T_30) node ldq_wakeup_idx_block_4 = or(block_load_mask[4], p1_block_load_mask[4]) node _ldq_wakeup_idx_T_32 = eq(ldq_executed[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_33 = and(ldq_addr[4].valid, _ldq_wakeup_idx_T_32) node _ldq_wakeup_idx_T_34 = eq(ldq_succeeded[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_35 = and(_ldq_wakeup_idx_T_33, _ldq_wakeup_idx_T_34) node _ldq_wakeup_idx_T_36 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _ldq_wakeup_idx_T_37 = and(_ldq_wakeup_idx_T_35, _ldq_wakeup_idx_T_36) node _ldq_wakeup_idx_T_38 = eq(ldq_wakeup_idx_block_4, UInt<1>(0h0)) node _ldq_wakeup_idx_T_39 = and(_ldq_wakeup_idx_T_37, _ldq_wakeup_idx_T_38) node ldq_wakeup_idx_block_5 = or(block_load_mask[5], p1_block_load_mask[5]) node _ldq_wakeup_idx_T_40 = eq(ldq_executed[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_41 = and(ldq_addr[5].valid, _ldq_wakeup_idx_T_40) node _ldq_wakeup_idx_T_42 = eq(ldq_succeeded[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_43 = and(_ldq_wakeup_idx_T_41, _ldq_wakeup_idx_T_42) node _ldq_wakeup_idx_T_44 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _ldq_wakeup_idx_T_45 = and(_ldq_wakeup_idx_T_43, _ldq_wakeup_idx_T_44) node _ldq_wakeup_idx_T_46 = eq(ldq_wakeup_idx_block_5, UInt<1>(0h0)) node _ldq_wakeup_idx_T_47 = and(_ldq_wakeup_idx_T_45, _ldq_wakeup_idx_T_46) node ldq_wakeup_idx_block_6 = or(block_load_mask[6], p1_block_load_mask[6]) node _ldq_wakeup_idx_T_48 = eq(ldq_executed[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_49 = and(ldq_addr[6].valid, _ldq_wakeup_idx_T_48) node _ldq_wakeup_idx_T_50 = eq(ldq_succeeded[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_51 = and(_ldq_wakeup_idx_T_49, _ldq_wakeup_idx_T_50) node _ldq_wakeup_idx_T_52 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _ldq_wakeup_idx_T_53 = and(_ldq_wakeup_idx_T_51, _ldq_wakeup_idx_T_52) node _ldq_wakeup_idx_T_54 = eq(ldq_wakeup_idx_block_6, UInt<1>(0h0)) node _ldq_wakeup_idx_T_55 = and(_ldq_wakeup_idx_T_53, _ldq_wakeup_idx_T_54) node ldq_wakeup_idx_block_7 = or(block_load_mask[7], p1_block_load_mask[7]) node _ldq_wakeup_idx_T_56 = eq(ldq_executed[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_57 = and(ldq_addr[7].valid, _ldq_wakeup_idx_T_56) node _ldq_wakeup_idx_T_58 = eq(ldq_succeeded[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_59 = and(_ldq_wakeup_idx_T_57, _ldq_wakeup_idx_T_58) node _ldq_wakeup_idx_T_60 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _ldq_wakeup_idx_T_61 = and(_ldq_wakeup_idx_T_59, _ldq_wakeup_idx_T_60) node _ldq_wakeup_idx_T_62 = eq(ldq_wakeup_idx_block_7, UInt<1>(0h0)) node _ldq_wakeup_idx_T_63 = and(_ldq_wakeup_idx_T_61, _ldq_wakeup_idx_T_62) node ldq_wakeup_idx_block_8 = or(block_load_mask[8], p1_block_load_mask[8]) node _ldq_wakeup_idx_T_64 = eq(ldq_executed[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_65 = and(ldq_addr[8].valid, _ldq_wakeup_idx_T_64) node _ldq_wakeup_idx_T_66 = eq(ldq_succeeded[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_67 = and(_ldq_wakeup_idx_T_65, _ldq_wakeup_idx_T_66) node _ldq_wakeup_idx_T_68 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _ldq_wakeup_idx_T_69 = and(_ldq_wakeup_idx_T_67, _ldq_wakeup_idx_T_68) node _ldq_wakeup_idx_T_70 = eq(ldq_wakeup_idx_block_8, UInt<1>(0h0)) node _ldq_wakeup_idx_T_71 = and(_ldq_wakeup_idx_T_69, _ldq_wakeup_idx_T_70) node ldq_wakeup_idx_block_9 = or(block_load_mask[9], p1_block_load_mask[9]) node _ldq_wakeup_idx_T_72 = eq(ldq_executed[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_73 = and(ldq_addr[9].valid, _ldq_wakeup_idx_T_72) node _ldq_wakeup_idx_T_74 = eq(ldq_succeeded[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_75 = and(_ldq_wakeup_idx_T_73, _ldq_wakeup_idx_T_74) node _ldq_wakeup_idx_T_76 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _ldq_wakeup_idx_T_77 = and(_ldq_wakeup_idx_T_75, _ldq_wakeup_idx_T_76) node _ldq_wakeup_idx_T_78 = eq(ldq_wakeup_idx_block_9, UInt<1>(0h0)) node _ldq_wakeup_idx_T_79 = and(_ldq_wakeup_idx_T_77, _ldq_wakeup_idx_T_78) node ldq_wakeup_idx_block_10 = or(block_load_mask[10], p1_block_load_mask[10]) node _ldq_wakeup_idx_T_80 = eq(ldq_executed[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_81 = and(ldq_addr[10].valid, _ldq_wakeup_idx_T_80) node _ldq_wakeup_idx_T_82 = eq(ldq_succeeded[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_83 = and(_ldq_wakeup_idx_T_81, _ldq_wakeup_idx_T_82) node _ldq_wakeup_idx_T_84 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _ldq_wakeup_idx_T_85 = and(_ldq_wakeup_idx_T_83, _ldq_wakeup_idx_T_84) node _ldq_wakeup_idx_T_86 = eq(ldq_wakeup_idx_block_10, UInt<1>(0h0)) node _ldq_wakeup_idx_T_87 = and(_ldq_wakeup_idx_T_85, _ldq_wakeup_idx_T_86) node ldq_wakeup_idx_block_11 = or(block_load_mask[11], p1_block_load_mask[11]) node _ldq_wakeup_idx_T_88 = eq(ldq_executed[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_89 = and(ldq_addr[11].valid, _ldq_wakeup_idx_T_88) node _ldq_wakeup_idx_T_90 = eq(ldq_succeeded[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_91 = and(_ldq_wakeup_idx_T_89, _ldq_wakeup_idx_T_90) node _ldq_wakeup_idx_T_92 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _ldq_wakeup_idx_T_93 = and(_ldq_wakeup_idx_T_91, _ldq_wakeup_idx_T_92) node _ldq_wakeup_idx_T_94 = eq(ldq_wakeup_idx_block_11, UInt<1>(0h0)) node _ldq_wakeup_idx_T_95 = and(_ldq_wakeup_idx_T_93, _ldq_wakeup_idx_T_94) node ldq_wakeup_idx_block_12 = or(block_load_mask[12], p1_block_load_mask[12]) node _ldq_wakeup_idx_T_96 = eq(ldq_executed[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_97 = and(ldq_addr[12].valid, _ldq_wakeup_idx_T_96) node _ldq_wakeup_idx_T_98 = eq(ldq_succeeded[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_99 = and(_ldq_wakeup_idx_T_97, _ldq_wakeup_idx_T_98) node _ldq_wakeup_idx_T_100 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _ldq_wakeup_idx_T_101 = and(_ldq_wakeup_idx_T_99, _ldq_wakeup_idx_T_100) node _ldq_wakeup_idx_T_102 = eq(ldq_wakeup_idx_block_12, UInt<1>(0h0)) node _ldq_wakeup_idx_T_103 = and(_ldq_wakeup_idx_T_101, _ldq_wakeup_idx_T_102) node ldq_wakeup_idx_block_13 = or(block_load_mask[13], p1_block_load_mask[13]) node _ldq_wakeup_idx_T_104 = eq(ldq_executed[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_105 = and(ldq_addr[13].valid, _ldq_wakeup_idx_T_104) node _ldq_wakeup_idx_T_106 = eq(ldq_succeeded[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_107 = and(_ldq_wakeup_idx_T_105, _ldq_wakeup_idx_T_106) node _ldq_wakeup_idx_T_108 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _ldq_wakeup_idx_T_109 = and(_ldq_wakeup_idx_T_107, _ldq_wakeup_idx_T_108) node _ldq_wakeup_idx_T_110 = eq(ldq_wakeup_idx_block_13, UInt<1>(0h0)) node _ldq_wakeup_idx_T_111 = and(_ldq_wakeup_idx_T_109, _ldq_wakeup_idx_T_110) node ldq_wakeup_idx_block_14 = or(block_load_mask[14], p1_block_load_mask[14]) node _ldq_wakeup_idx_T_112 = eq(ldq_executed[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_113 = and(ldq_addr[14].valid, _ldq_wakeup_idx_T_112) node _ldq_wakeup_idx_T_114 = eq(ldq_succeeded[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_115 = and(_ldq_wakeup_idx_T_113, _ldq_wakeup_idx_T_114) node _ldq_wakeup_idx_T_116 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _ldq_wakeup_idx_T_117 = and(_ldq_wakeup_idx_T_115, _ldq_wakeup_idx_T_116) node _ldq_wakeup_idx_T_118 = eq(ldq_wakeup_idx_block_14, UInt<1>(0h0)) node _ldq_wakeup_idx_T_119 = and(_ldq_wakeup_idx_T_117, _ldq_wakeup_idx_T_118) node ldq_wakeup_idx_block_15 = or(block_load_mask[15], p1_block_load_mask[15]) node _ldq_wakeup_idx_T_120 = eq(ldq_executed[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_121 = and(ldq_addr[15].valid, _ldq_wakeup_idx_T_120) node _ldq_wakeup_idx_T_122 = eq(ldq_succeeded[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_123 = and(_ldq_wakeup_idx_T_121, _ldq_wakeup_idx_T_122) node _ldq_wakeup_idx_T_124 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _ldq_wakeup_idx_T_125 = and(_ldq_wakeup_idx_T_123, _ldq_wakeup_idx_T_124) node _ldq_wakeup_idx_T_126 = eq(ldq_wakeup_idx_block_15, UInt<1>(0h0)) node _ldq_wakeup_idx_T_127 = and(_ldq_wakeup_idx_T_125, _ldq_wakeup_idx_T_126) node ldq_wakeup_idx_block_16 = or(block_load_mask[16], p1_block_load_mask[16]) node _ldq_wakeup_idx_T_128 = eq(ldq_executed[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_129 = and(ldq_addr[16].valid, _ldq_wakeup_idx_T_128) node _ldq_wakeup_idx_T_130 = eq(ldq_succeeded[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_131 = and(_ldq_wakeup_idx_T_129, _ldq_wakeup_idx_T_130) node _ldq_wakeup_idx_T_132 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _ldq_wakeup_idx_T_133 = and(_ldq_wakeup_idx_T_131, _ldq_wakeup_idx_T_132) node _ldq_wakeup_idx_T_134 = eq(ldq_wakeup_idx_block_16, UInt<1>(0h0)) node _ldq_wakeup_idx_T_135 = and(_ldq_wakeup_idx_T_133, _ldq_wakeup_idx_T_134) node ldq_wakeup_idx_block_17 = or(block_load_mask[17], p1_block_load_mask[17]) node _ldq_wakeup_idx_T_136 = eq(ldq_executed[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_137 = and(ldq_addr[17].valid, _ldq_wakeup_idx_T_136) node _ldq_wakeup_idx_T_138 = eq(ldq_succeeded[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_139 = and(_ldq_wakeup_idx_T_137, _ldq_wakeup_idx_T_138) node _ldq_wakeup_idx_T_140 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _ldq_wakeup_idx_T_141 = and(_ldq_wakeup_idx_T_139, _ldq_wakeup_idx_T_140) node _ldq_wakeup_idx_T_142 = eq(ldq_wakeup_idx_block_17, UInt<1>(0h0)) node _ldq_wakeup_idx_T_143 = and(_ldq_wakeup_idx_T_141, _ldq_wakeup_idx_T_142) node ldq_wakeup_idx_block_18 = or(block_load_mask[18], p1_block_load_mask[18]) node _ldq_wakeup_idx_T_144 = eq(ldq_executed[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_145 = and(ldq_addr[18].valid, _ldq_wakeup_idx_T_144) node _ldq_wakeup_idx_T_146 = eq(ldq_succeeded[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_147 = and(_ldq_wakeup_idx_T_145, _ldq_wakeup_idx_T_146) node _ldq_wakeup_idx_T_148 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _ldq_wakeup_idx_T_149 = and(_ldq_wakeup_idx_T_147, _ldq_wakeup_idx_T_148) node _ldq_wakeup_idx_T_150 = eq(ldq_wakeup_idx_block_18, UInt<1>(0h0)) node _ldq_wakeup_idx_T_151 = and(_ldq_wakeup_idx_T_149, _ldq_wakeup_idx_T_150) node ldq_wakeup_idx_block_19 = or(block_load_mask[19], p1_block_load_mask[19]) node _ldq_wakeup_idx_T_152 = eq(ldq_executed[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_153 = and(ldq_addr[19].valid, _ldq_wakeup_idx_T_152) node _ldq_wakeup_idx_T_154 = eq(ldq_succeeded[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_155 = and(_ldq_wakeup_idx_T_153, _ldq_wakeup_idx_T_154) node _ldq_wakeup_idx_T_156 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _ldq_wakeup_idx_T_157 = and(_ldq_wakeup_idx_T_155, _ldq_wakeup_idx_T_156) node _ldq_wakeup_idx_T_158 = eq(ldq_wakeup_idx_block_19, UInt<1>(0h0)) node _ldq_wakeup_idx_T_159 = and(_ldq_wakeup_idx_T_157, _ldq_wakeup_idx_T_158) node ldq_wakeup_idx_block_20 = or(block_load_mask[20], p1_block_load_mask[20]) node _ldq_wakeup_idx_T_160 = eq(ldq_executed[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_161 = and(ldq_addr[20].valid, _ldq_wakeup_idx_T_160) node _ldq_wakeup_idx_T_162 = eq(ldq_succeeded[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_163 = and(_ldq_wakeup_idx_T_161, _ldq_wakeup_idx_T_162) node _ldq_wakeup_idx_T_164 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _ldq_wakeup_idx_T_165 = and(_ldq_wakeup_idx_T_163, _ldq_wakeup_idx_T_164) node _ldq_wakeup_idx_T_166 = eq(ldq_wakeup_idx_block_20, UInt<1>(0h0)) node _ldq_wakeup_idx_T_167 = and(_ldq_wakeup_idx_T_165, _ldq_wakeup_idx_T_166) node ldq_wakeup_idx_block_21 = or(block_load_mask[21], p1_block_load_mask[21]) node _ldq_wakeup_idx_T_168 = eq(ldq_executed[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_169 = and(ldq_addr[21].valid, _ldq_wakeup_idx_T_168) node _ldq_wakeup_idx_T_170 = eq(ldq_succeeded[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_171 = and(_ldq_wakeup_idx_T_169, _ldq_wakeup_idx_T_170) node _ldq_wakeup_idx_T_172 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _ldq_wakeup_idx_T_173 = and(_ldq_wakeup_idx_T_171, _ldq_wakeup_idx_T_172) node _ldq_wakeup_idx_T_174 = eq(ldq_wakeup_idx_block_21, UInt<1>(0h0)) node _ldq_wakeup_idx_T_175 = and(_ldq_wakeup_idx_T_173, _ldq_wakeup_idx_T_174) node ldq_wakeup_idx_block_22 = or(block_load_mask[22], p1_block_load_mask[22]) node _ldq_wakeup_idx_T_176 = eq(ldq_executed[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_177 = and(ldq_addr[22].valid, _ldq_wakeup_idx_T_176) node _ldq_wakeup_idx_T_178 = eq(ldq_succeeded[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_179 = and(_ldq_wakeup_idx_T_177, _ldq_wakeup_idx_T_178) node _ldq_wakeup_idx_T_180 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _ldq_wakeup_idx_T_181 = and(_ldq_wakeup_idx_T_179, _ldq_wakeup_idx_T_180) node _ldq_wakeup_idx_T_182 = eq(ldq_wakeup_idx_block_22, UInt<1>(0h0)) node _ldq_wakeup_idx_T_183 = and(_ldq_wakeup_idx_T_181, _ldq_wakeup_idx_T_182) node ldq_wakeup_idx_block_23 = or(block_load_mask[23], p1_block_load_mask[23]) node _ldq_wakeup_idx_T_184 = eq(ldq_executed[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_185 = and(ldq_addr[23].valid, _ldq_wakeup_idx_T_184) node _ldq_wakeup_idx_T_186 = eq(ldq_succeeded[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_187 = and(_ldq_wakeup_idx_T_185, _ldq_wakeup_idx_T_186) node _ldq_wakeup_idx_T_188 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _ldq_wakeup_idx_T_189 = and(_ldq_wakeup_idx_T_187, _ldq_wakeup_idx_T_188) node _ldq_wakeup_idx_T_190 = eq(ldq_wakeup_idx_block_23, UInt<1>(0h0)) node _ldq_wakeup_idx_T_191 = and(_ldq_wakeup_idx_T_189, _ldq_wakeup_idx_T_190) node _ldq_wakeup_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node ldq_wakeup_idx_temp_vec_0 = and(_ldq_wakeup_idx_T_7, _ldq_wakeup_idx_temp_vec_T) node _ldq_wakeup_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node ldq_wakeup_idx_temp_vec_1 = and(_ldq_wakeup_idx_T_15, _ldq_wakeup_idx_temp_vec_T_1) node _ldq_wakeup_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node ldq_wakeup_idx_temp_vec_2 = and(_ldq_wakeup_idx_T_23, _ldq_wakeup_idx_temp_vec_T_2) node _ldq_wakeup_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node ldq_wakeup_idx_temp_vec_3 = and(_ldq_wakeup_idx_T_31, _ldq_wakeup_idx_temp_vec_T_3) node _ldq_wakeup_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node ldq_wakeup_idx_temp_vec_4 = and(_ldq_wakeup_idx_T_39, _ldq_wakeup_idx_temp_vec_T_4) node _ldq_wakeup_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node ldq_wakeup_idx_temp_vec_5 = and(_ldq_wakeup_idx_T_47, _ldq_wakeup_idx_temp_vec_T_5) node _ldq_wakeup_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node ldq_wakeup_idx_temp_vec_6 = and(_ldq_wakeup_idx_T_55, _ldq_wakeup_idx_temp_vec_T_6) node _ldq_wakeup_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node ldq_wakeup_idx_temp_vec_7 = and(_ldq_wakeup_idx_T_63, _ldq_wakeup_idx_temp_vec_T_7) node _ldq_wakeup_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node ldq_wakeup_idx_temp_vec_8 = and(_ldq_wakeup_idx_T_71, _ldq_wakeup_idx_temp_vec_T_8) node _ldq_wakeup_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node ldq_wakeup_idx_temp_vec_9 = and(_ldq_wakeup_idx_T_79, _ldq_wakeup_idx_temp_vec_T_9) node _ldq_wakeup_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node ldq_wakeup_idx_temp_vec_10 = and(_ldq_wakeup_idx_T_87, _ldq_wakeup_idx_temp_vec_T_10) node _ldq_wakeup_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node ldq_wakeup_idx_temp_vec_11 = and(_ldq_wakeup_idx_T_95, _ldq_wakeup_idx_temp_vec_T_11) node _ldq_wakeup_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node ldq_wakeup_idx_temp_vec_12 = and(_ldq_wakeup_idx_T_103, _ldq_wakeup_idx_temp_vec_T_12) node _ldq_wakeup_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node ldq_wakeup_idx_temp_vec_13 = and(_ldq_wakeup_idx_T_111, _ldq_wakeup_idx_temp_vec_T_13) node _ldq_wakeup_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node ldq_wakeup_idx_temp_vec_14 = and(_ldq_wakeup_idx_T_119, _ldq_wakeup_idx_temp_vec_T_14) node _ldq_wakeup_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node ldq_wakeup_idx_temp_vec_15 = and(_ldq_wakeup_idx_T_127, _ldq_wakeup_idx_temp_vec_T_15) node _ldq_wakeup_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node ldq_wakeup_idx_temp_vec_16 = and(_ldq_wakeup_idx_T_135, _ldq_wakeup_idx_temp_vec_T_16) node _ldq_wakeup_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node ldq_wakeup_idx_temp_vec_17 = and(_ldq_wakeup_idx_T_143, _ldq_wakeup_idx_temp_vec_T_17) node _ldq_wakeup_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node ldq_wakeup_idx_temp_vec_18 = and(_ldq_wakeup_idx_T_151, _ldq_wakeup_idx_temp_vec_T_18) node _ldq_wakeup_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node ldq_wakeup_idx_temp_vec_19 = and(_ldq_wakeup_idx_T_159, _ldq_wakeup_idx_temp_vec_T_19) node _ldq_wakeup_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node ldq_wakeup_idx_temp_vec_20 = and(_ldq_wakeup_idx_T_167, _ldq_wakeup_idx_temp_vec_T_20) node _ldq_wakeup_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node ldq_wakeup_idx_temp_vec_21 = and(_ldq_wakeup_idx_T_175, _ldq_wakeup_idx_temp_vec_T_21) node _ldq_wakeup_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node ldq_wakeup_idx_temp_vec_22 = and(_ldq_wakeup_idx_T_183, _ldq_wakeup_idx_temp_vec_T_22) node _ldq_wakeup_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node ldq_wakeup_idx_temp_vec_23 = and(_ldq_wakeup_idx_T_191, _ldq_wakeup_idx_temp_vec_T_23) node _ldq_wakeup_idx_idx_T = mux(_ldq_wakeup_idx_T_183, UInt<6>(0h36), UInt<6>(0h37)) node _ldq_wakeup_idx_idx_T_1 = mux(_ldq_wakeup_idx_T_175, UInt<6>(0h35), _ldq_wakeup_idx_idx_T) node _ldq_wakeup_idx_idx_T_2 = mux(_ldq_wakeup_idx_T_167, UInt<6>(0h34), _ldq_wakeup_idx_idx_T_1) node _ldq_wakeup_idx_idx_T_3 = mux(_ldq_wakeup_idx_T_159, UInt<6>(0h33), _ldq_wakeup_idx_idx_T_2) node _ldq_wakeup_idx_idx_T_4 = mux(_ldq_wakeup_idx_T_151, UInt<6>(0h32), _ldq_wakeup_idx_idx_T_3) node _ldq_wakeup_idx_idx_T_5 = mux(_ldq_wakeup_idx_T_143, UInt<6>(0h31), _ldq_wakeup_idx_idx_T_4) node _ldq_wakeup_idx_idx_T_6 = mux(_ldq_wakeup_idx_T_135, UInt<6>(0h30), _ldq_wakeup_idx_idx_T_5) node _ldq_wakeup_idx_idx_T_7 = mux(_ldq_wakeup_idx_T_127, UInt<6>(0h2f), _ldq_wakeup_idx_idx_T_6) node _ldq_wakeup_idx_idx_T_8 = mux(_ldq_wakeup_idx_T_119, UInt<6>(0h2e), _ldq_wakeup_idx_idx_T_7) node _ldq_wakeup_idx_idx_T_9 = mux(_ldq_wakeup_idx_T_111, UInt<6>(0h2d), _ldq_wakeup_idx_idx_T_8) node _ldq_wakeup_idx_idx_T_10 = mux(_ldq_wakeup_idx_T_103, UInt<6>(0h2c), _ldq_wakeup_idx_idx_T_9) node _ldq_wakeup_idx_idx_T_11 = mux(_ldq_wakeup_idx_T_95, UInt<6>(0h2b), _ldq_wakeup_idx_idx_T_10) node _ldq_wakeup_idx_idx_T_12 = mux(_ldq_wakeup_idx_T_87, UInt<6>(0h2a), _ldq_wakeup_idx_idx_T_11) node _ldq_wakeup_idx_idx_T_13 = mux(_ldq_wakeup_idx_T_79, UInt<6>(0h29), _ldq_wakeup_idx_idx_T_12) node _ldq_wakeup_idx_idx_T_14 = mux(_ldq_wakeup_idx_T_71, UInt<6>(0h28), _ldq_wakeup_idx_idx_T_13) node _ldq_wakeup_idx_idx_T_15 = mux(_ldq_wakeup_idx_T_63, UInt<6>(0h27), _ldq_wakeup_idx_idx_T_14) node _ldq_wakeup_idx_idx_T_16 = mux(_ldq_wakeup_idx_T_55, UInt<6>(0h26), _ldq_wakeup_idx_idx_T_15) node _ldq_wakeup_idx_idx_T_17 = mux(_ldq_wakeup_idx_T_47, UInt<6>(0h25), _ldq_wakeup_idx_idx_T_16) node _ldq_wakeup_idx_idx_T_18 = mux(_ldq_wakeup_idx_T_39, UInt<6>(0h24), _ldq_wakeup_idx_idx_T_17) node _ldq_wakeup_idx_idx_T_19 = mux(_ldq_wakeup_idx_T_31, UInt<6>(0h23), _ldq_wakeup_idx_idx_T_18) node _ldq_wakeup_idx_idx_T_20 = mux(_ldq_wakeup_idx_T_23, UInt<6>(0h22), _ldq_wakeup_idx_idx_T_19) node _ldq_wakeup_idx_idx_T_21 = mux(_ldq_wakeup_idx_T_15, UInt<6>(0h21), _ldq_wakeup_idx_idx_T_20) node _ldq_wakeup_idx_idx_T_22 = mux(_ldq_wakeup_idx_T_7, UInt<6>(0h20), _ldq_wakeup_idx_idx_T_21) node _ldq_wakeup_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_wakeup_idx_idx_T_22) node _ldq_wakeup_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_wakeup_idx_idx_T_23) node _ldq_wakeup_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_wakeup_idx_idx_T_24) node _ldq_wakeup_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_wakeup_idx_idx_T_25) node _ldq_wakeup_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_wakeup_idx_idx_T_26) node _ldq_wakeup_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_wakeup_idx_idx_T_27) node _ldq_wakeup_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_wakeup_idx_idx_T_28) node _ldq_wakeup_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_wakeup_idx_idx_T_29) node _ldq_wakeup_idx_idx_T_31 = mux(ldq_wakeup_idx_temp_vec_23, UInt<5>(0h17), _ldq_wakeup_idx_idx_T_30) node _ldq_wakeup_idx_idx_T_32 = mux(ldq_wakeup_idx_temp_vec_22, UInt<5>(0h16), _ldq_wakeup_idx_idx_T_31) node _ldq_wakeup_idx_idx_T_33 = mux(ldq_wakeup_idx_temp_vec_21, UInt<5>(0h15), _ldq_wakeup_idx_idx_T_32) node _ldq_wakeup_idx_idx_T_34 = mux(ldq_wakeup_idx_temp_vec_20, UInt<5>(0h14), _ldq_wakeup_idx_idx_T_33) node _ldq_wakeup_idx_idx_T_35 = mux(ldq_wakeup_idx_temp_vec_19, UInt<5>(0h13), _ldq_wakeup_idx_idx_T_34) node _ldq_wakeup_idx_idx_T_36 = mux(ldq_wakeup_idx_temp_vec_18, UInt<5>(0h12), _ldq_wakeup_idx_idx_T_35) node _ldq_wakeup_idx_idx_T_37 = mux(ldq_wakeup_idx_temp_vec_17, UInt<5>(0h11), _ldq_wakeup_idx_idx_T_36) node _ldq_wakeup_idx_idx_T_38 = mux(ldq_wakeup_idx_temp_vec_16, UInt<5>(0h10), _ldq_wakeup_idx_idx_T_37) node _ldq_wakeup_idx_idx_T_39 = mux(ldq_wakeup_idx_temp_vec_15, UInt<4>(0hf), _ldq_wakeup_idx_idx_T_38) node _ldq_wakeup_idx_idx_T_40 = mux(ldq_wakeup_idx_temp_vec_14, UInt<4>(0he), _ldq_wakeup_idx_idx_T_39) node _ldq_wakeup_idx_idx_T_41 = mux(ldq_wakeup_idx_temp_vec_13, UInt<4>(0hd), _ldq_wakeup_idx_idx_T_40) node _ldq_wakeup_idx_idx_T_42 = mux(ldq_wakeup_idx_temp_vec_12, UInt<4>(0hc), _ldq_wakeup_idx_idx_T_41) node _ldq_wakeup_idx_idx_T_43 = mux(ldq_wakeup_idx_temp_vec_11, UInt<4>(0hb), _ldq_wakeup_idx_idx_T_42) node _ldq_wakeup_idx_idx_T_44 = mux(ldq_wakeup_idx_temp_vec_10, UInt<4>(0ha), _ldq_wakeup_idx_idx_T_43) node _ldq_wakeup_idx_idx_T_45 = mux(ldq_wakeup_idx_temp_vec_9, UInt<4>(0h9), _ldq_wakeup_idx_idx_T_44) node _ldq_wakeup_idx_idx_T_46 = mux(ldq_wakeup_idx_temp_vec_8, UInt<4>(0h8), _ldq_wakeup_idx_idx_T_45) node _ldq_wakeup_idx_idx_T_47 = mux(ldq_wakeup_idx_temp_vec_7, UInt<3>(0h7), _ldq_wakeup_idx_idx_T_46) node _ldq_wakeup_idx_idx_T_48 = mux(ldq_wakeup_idx_temp_vec_6, UInt<3>(0h6), _ldq_wakeup_idx_idx_T_47) node _ldq_wakeup_idx_idx_T_49 = mux(ldq_wakeup_idx_temp_vec_5, UInt<3>(0h5), _ldq_wakeup_idx_idx_T_48) node _ldq_wakeup_idx_idx_T_50 = mux(ldq_wakeup_idx_temp_vec_4, UInt<3>(0h4), _ldq_wakeup_idx_idx_T_49) node _ldq_wakeup_idx_idx_T_51 = mux(ldq_wakeup_idx_temp_vec_3, UInt<2>(0h3), _ldq_wakeup_idx_idx_T_50) node _ldq_wakeup_idx_idx_T_52 = mux(ldq_wakeup_idx_temp_vec_2, UInt<2>(0h2), _ldq_wakeup_idx_idx_T_51) node _ldq_wakeup_idx_idx_T_53 = mux(ldq_wakeup_idx_temp_vec_1, UInt<1>(0h1), _ldq_wakeup_idx_idx_T_52) node ldq_wakeup_idx_idx = mux(ldq_wakeup_idx_temp_vec_0, UInt<1>(0h0), _ldq_wakeup_idx_idx_T_53) node _ldq_wakeup_idx_T_192 = bits(ldq_wakeup_idx_idx, 4, 0) reg ldq_wakeup_idx : UInt, clock connect ldq_wakeup_idx, _ldq_wakeup_idx_T_192 wire ldq_wakeup_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} node _ldq_wakeup_e_e_valid_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_valid_T_1 = bits(_ldq_wakeup_e_e_valid_T, 4, 0) connect ldq_wakeup_e_e.valid, ldq_valid[_ldq_wakeup_e_e_valid_T_1] node _ldq_wakeup_e_e_bits_uop_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_uop_T_1 = bits(_ldq_wakeup_e_e_bits_uop_T, 4, 0) connect ldq_wakeup_e_e.bits.uop, ldq_uop[_ldq_wakeup_e_e_bits_uop_T_1] node _ldq_wakeup_e_e_bits_addr_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_T_1 = bits(_ldq_wakeup_e_e_bits_addr_T, 4, 0) connect ldq_wakeup_e_e.bits.addr, ldq_addr[_ldq_wakeup_e_e_bits_addr_T_1] node _ldq_wakeup_e_e_bits_addr_is_virtual_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = bits(_ldq_wakeup_e_e_bits_addr_is_virtual_T, 4, 0) connect ldq_wakeup_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1] node _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = bits(_ldq_wakeup_e_e_bits_addr_is_uncacheable_T, 4, 0) connect ldq_wakeup_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1] node _ldq_wakeup_e_e_bits_executed_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_executed_T_1 = bits(_ldq_wakeup_e_e_bits_executed_T, 4, 0) connect ldq_wakeup_e_e.bits.executed, ldq_executed[_ldq_wakeup_e_e_bits_executed_T_1] node _ldq_wakeup_e_e_bits_succeeded_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_succeeded_T_1 = bits(_ldq_wakeup_e_e_bits_succeeded_T, 4, 0) connect ldq_wakeup_e_e.bits.succeeded, ldq_succeeded[_ldq_wakeup_e_e_bits_succeeded_T_1] node _ldq_wakeup_e_e_bits_order_fail_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_order_fail_T_1 = bits(_ldq_wakeup_e_e_bits_order_fail_T, 4, 0) connect ldq_wakeup_e_e.bits.order_fail, ldq_order_fail[_ldq_wakeup_e_e_bits_order_fail_T_1] node _ldq_wakeup_e_e_bits_observed_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_observed_T_1 = bits(_ldq_wakeup_e_e_bits_observed_T, 4, 0) connect ldq_wakeup_e_e.bits.observed, ldq_observed[_ldq_wakeup_e_e_bits_observed_T_1] node _ldq_wakeup_e_e_bits_st_dep_mask_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = bits(_ldq_wakeup_e_e_bits_st_dep_mask_T, 4, 0) connect ldq_wakeup_e_e.bits.st_dep_mask, ldq_st_dep_mask[_ldq_wakeup_e_e_bits_st_dep_mask_T_1] node _ldq_wakeup_e_e_bits_ld_byte_mask_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = bits(_ldq_wakeup_e_e_bits_ld_byte_mask_T, 4, 0) connect ldq_wakeup_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1] node _ldq_wakeup_e_e_bits_forward_std_val_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_forward_std_val_T_1 = bits(_ldq_wakeup_e_e_bits_forward_std_val_T, 4, 0) connect ldq_wakeup_e_e.bits.forward_std_val, ldq_forward_std_val[_ldq_wakeup_e_e_bits_forward_std_val_T_1] node _ldq_wakeup_e_e_bits_forward_stq_idx_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = bits(_ldq_wakeup_e_e_bits_forward_stq_idx_T, 4, 0) connect ldq_wakeup_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1] node _ldq_wakeup_e_e_bits_debug_wb_data_T = or(ldq_wakeup_idx, UInt<5>(0h0)) node _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = bits(_ldq_wakeup_e_e_bits_debug_wb_data_T, 4, 0) connect ldq_wakeup_e_e.bits.debug_wb_data, ldq_debug_wb_data[_ldq_wakeup_e_e_bits_debug_wb_data_T_1] wire ldq_wakeup_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_wakeup_e, ldq_wakeup_e_e reg ldq_enq_retry_idx : UInt<5>, clock node _ldq_enq_retry_idx_T = and(ldq_addr[0].valid, ldq_addr_is_virtual[0]) node _ldq_enq_retry_idx_T_1 = neq(UInt<1>(0h0), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_2 = and(_ldq_enq_retry_idx_T, _ldq_enq_retry_idx_T_1) node _ldq_enq_retry_idx_T_3 = and(ldq_addr[1].valid, ldq_addr_is_virtual[1]) node _ldq_enq_retry_idx_T_4 = neq(UInt<1>(0h1), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_5 = and(_ldq_enq_retry_idx_T_3, _ldq_enq_retry_idx_T_4) node _ldq_enq_retry_idx_T_6 = and(ldq_addr[2].valid, ldq_addr_is_virtual[2]) node _ldq_enq_retry_idx_T_7 = neq(UInt<2>(0h2), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_8 = and(_ldq_enq_retry_idx_T_6, _ldq_enq_retry_idx_T_7) node _ldq_enq_retry_idx_T_9 = and(ldq_addr[3].valid, ldq_addr_is_virtual[3]) node _ldq_enq_retry_idx_T_10 = neq(UInt<2>(0h3), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_11 = and(_ldq_enq_retry_idx_T_9, _ldq_enq_retry_idx_T_10) node _ldq_enq_retry_idx_T_12 = and(ldq_addr[4].valid, ldq_addr_is_virtual[4]) node _ldq_enq_retry_idx_T_13 = neq(UInt<3>(0h4), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_14 = and(_ldq_enq_retry_idx_T_12, _ldq_enq_retry_idx_T_13) node _ldq_enq_retry_idx_T_15 = and(ldq_addr[5].valid, ldq_addr_is_virtual[5]) node _ldq_enq_retry_idx_T_16 = neq(UInt<3>(0h5), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_17 = and(_ldq_enq_retry_idx_T_15, _ldq_enq_retry_idx_T_16) node _ldq_enq_retry_idx_T_18 = and(ldq_addr[6].valid, ldq_addr_is_virtual[6]) node _ldq_enq_retry_idx_T_19 = neq(UInt<3>(0h6), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_20 = and(_ldq_enq_retry_idx_T_18, _ldq_enq_retry_idx_T_19) node _ldq_enq_retry_idx_T_21 = and(ldq_addr[7].valid, ldq_addr_is_virtual[7]) node _ldq_enq_retry_idx_T_22 = neq(UInt<3>(0h7), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_23 = and(_ldq_enq_retry_idx_T_21, _ldq_enq_retry_idx_T_22) node _ldq_enq_retry_idx_T_24 = and(ldq_addr[8].valid, ldq_addr_is_virtual[8]) node _ldq_enq_retry_idx_T_25 = neq(UInt<4>(0h8), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_26 = and(_ldq_enq_retry_idx_T_24, _ldq_enq_retry_idx_T_25) node _ldq_enq_retry_idx_T_27 = and(ldq_addr[9].valid, ldq_addr_is_virtual[9]) node _ldq_enq_retry_idx_T_28 = neq(UInt<4>(0h9), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_29 = and(_ldq_enq_retry_idx_T_27, _ldq_enq_retry_idx_T_28) node _ldq_enq_retry_idx_T_30 = and(ldq_addr[10].valid, ldq_addr_is_virtual[10]) node _ldq_enq_retry_idx_T_31 = neq(UInt<4>(0ha), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_32 = and(_ldq_enq_retry_idx_T_30, _ldq_enq_retry_idx_T_31) node _ldq_enq_retry_idx_T_33 = and(ldq_addr[11].valid, ldq_addr_is_virtual[11]) node _ldq_enq_retry_idx_T_34 = neq(UInt<4>(0hb), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_35 = and(_ldq_enq_retry_idx_T_33, _ldq_enq_retry_idx_T_34) node _ldq_enq_retry_idx_T_36 = and(ldq_addr[12].valid, ldq_addr_is_virtual[12]) node _ldq_enq_retry_idx_T_37 = neq(UInt<4>(0hc), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_38 = and(_ldq_enq_retry_idx_T_36, _ldq_enq_retry_idx_T_37) node _ldq_enq_retry_idx_T_39 = and(ldq_addr[13].valid, ldq_addr_is_virtual[13]) node _ldq_enq_retry_idx_T_40 = neq(UInt<4>(0hd), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_41 = and(_ldq_enq_retry_idx_T_39, _ldq_enq_retry_idx_T_40) node _ldq_enq_retry_idx_T_42 = and(ldq_addr[14].valid, ldq_addr_is_virtual[14]) node _ldq_enq_retry_idx_T_43 = neq(UInt<4>(0he), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_44 = and(_ldq_enq_retry_idx_T_42, _ldq_enq_retry_idx_T_43) node _ldq_enq_retry_idx_T_45 = and(ldq_addr[15].valid, ldq_addr_is_virtual[15]) node _ldq_enq_retry_idx_T_46 = neq(UInt<4>(0hf), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_47 = and(_ldq_enq_retry_idx_T_45, _ldq_enq_retry_idx_T_46) node _ldq_enq_retry_idx_T_48 = and(ldq_addr[16].valid, ldq_addr_is_virtual[16]) node _ldq_enq_retry_idx_T_49 = neq(UInt<5>(0h10), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_50 = and(_ldq_enq_retry_idx_T_48, _ldq_enq_retry_idx_T_49) node _ldq_enq_retry_idx_T_51 = and(ldq_addr[17].valid, ldq_addr_is_virtual[17]) node _ldq_enq_retry_idx_T_52 = neq(UInt<5>(0h11), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_53 = and(_ldq_enq_retry_idx_T_51, _ldq_enq_retry_idx_T_52) node _ldq_enq_retry_idx_T_54 = and(ldq_addr[18].valid, ldq_addr_is_virtual[18]) node _ldq_enq_retry_idx_T_55 = neq(UInt<5>(0h12), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_56 = and(_ldq_enq_retry_idx_T_54, _ldq_enq_retry_idx_T_55) node _ldq_enq_retry_idx_T_57 = and(ldq_addr[19].valid, ldq_addr_is_virtual[19]) node _ldq_enq_retry_idx_T_58 = neq(UInt<5>(0h13), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_59 = and(_ldq_enq_retry_idx_T_57, _ldq_enq_retry_idx_T_58) node _ldq_enq_retry_idx_T_60 = and(ldq_addr[20].valid, ldq_addr_is_virtual[20]) node _ldq_enq_retry_idx_T_61 = neq(UInt<5>(0h14), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_62 = and(_ldq_enq_retry_idx_T_60, _ldq_enq_retry_idx_T_61) node _ldq_enq_retry_idx_T_63 = and(ldq_addr[21].valid, ldq_addr_is_virtual[21]) node _ldq_enq_retry_idx_T_64 = neq(UInt<5>(0h15), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_65 = and(_ldq_enq_retry_idx_T_63, _ldq_enq_retry_idx_T_64) node _ldq_enq_retry_idx_T_66 = and(ldq_addr[22].valid, ldq_addr_is_virtual[22]) node _ldq_enq_retry_idx_T_67 = neq(UInt<5>(0h16), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_68 = and(_ldq_enq_retry_idx_T_66, _ldq_enq_retry_idx_T_67) node _ldq_enq_retry_idx_T_69 = and(ldq_addr[23].valid, ldq_addr_is_virtual[23]) node _ldq_enq_retry_idx_T_70 = neq(UInt<5>(0h17), ldq_enq_retry_idx) node _ldq_enq_retry_idx_T_71 = and(_ldq_enq_retry_idx_T_69, _ldq_enq_retry_idx_T_70) node _ldq_enq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node ldq_enq_retry_idx_temp_vec_0 = and(_ldq_enq_retry_idx_T_2, _ldq_enq_retry_idx_temp_vec_T) node _ldq_enq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node ldq_enq_retry_idx_temp_vec_1 = and(_ldq_enq_retry_idx_T_5, _ldq_enq_retry_idx_temp_vec_T_1) node _ldq_enq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node ldq_enq_retry_idx_temp_vec_2 = and(_ldq_enq_retry_idx_T_8, _ldq_enq_retry_idx_temp_vec_T_2) node _ldq_enq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node ldq_enq_retry_idx_temp_vec_3 = and(_ldq_enq_retry_idx_T_11, _ldq_enq_retry_idx_temp_vec_T_3) node _ldq_enq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node ldq_enq_retry_idx_temp_vec_4 = and(_ldq_enq_retry_idx_T_14, _ldq_enq_retry_idx_temp_vec_T_4) node _ldq_enq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node ldq_enq_retry_idx_temp_vec_5 = and(_ldq_enq_retry_idx_T_17, _ldq_enq_retry_idx_temp_vec_T_5) node _ldq_enq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node ldq_enq_retry_idx_temp_vec_6 = and(_ldq_enq_retry_idx_T_20, _ldq_enq_retry_idx_temp_vec_T_6) node _ldq_enq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node ldq_enq_retry_idx_temp_vec_7 = and(_ldq_enq_retry_idx_T_23, _ldq_enq_retry_idx_temp_vec_T_7) node _ldq_enq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node ldq_enq_retry_idx_temp_vec_8 = and(_ldq_enq_retry_idx_T_26, _ldq_enq_retry_idx_temp_vec_T_8) node _ldq_enq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node ldq_enq_retry_idx_temp_vec_9 = and(_ldq_enq_retry_idx_T_29, _ldq_enq_retry_idx_temp_vec_T_9) node _ldq_enq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node ldq_enq_retry_idx_temp_vec_10 = and(_ldq_enq_retry_idx_T_32, _ldq_enq_retry_idx_temp_vec_T_10) node _ldq_enq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node ldq_enq_retry_idx_temp_vec_11 = and(_ldq_enq_retry_idx_T_35, _ldq_enq_retry_idx_temp_vec_T_11) node _ldq_enq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node ldq_enq_retry_idx_temp_vec_12 = and(_ldq_enq_retry_idx_T_38, _ldq_enq_retry_idx_temp_vec_T_12) node _ldq_enq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node ldq_enq_retry_idx_temp_vec_13 = and(_ldq_enq_retry_idx_T_41, _ldq_enq_retry_idx_temp_vec_T_13) node _ldq_enq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node ldq_enq_retry_idx_temp_vec_14 = and(_ldq_enq_retry_idx_T_44, _ldq_enq_retry_idx_temp_vec_T_14) node _ldq_enq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node ldq_enq_retry_idx_temp_vec_15 = and(_ldq_enq_retry_idx_T_47, _ldq_enq_retry_idx_temp_vec_T_15) node _ldq_enq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node ldq_enq_retry_idx_temp_vec_16 = and(_ldq_enq_retry_idx_T_50, _ldq_enq_retry_idx_temp_vec_T_16) node _ldq_enq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node ldq_enq_retry_idx_temp_vec_17 = and(_ldq_enq_retry_idx_T_53, _ldq_enq_retry_idx_temp_vec_T_17) node _ldq_enq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node ldq_enq_retry_idx_temp_vec_18 = and(_ldq_enq_retry_idx_T_56, _ldq_enq_retry_idx_temp_vec_T_18) node _ldq_enq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node ldq_enq_retry_idx_temp_vec_19 = and(_ldq_enq_retry_idx_T_59, _ldq_enq_retry_idx_temp_vec_T_19) node _ldq_enq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node ldq_enq_retry_idx_temp_vec_20 = and(_ldq_enq_retry_idx_T_62, _ldq_enq_retry_idx_temp_vec_T_20) node _ldq_enq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node ldq_enq_retry_idx_temp_vec_21 = and(_ldq_enq_retry_idx_T_65, _ldq_enq_retry_idx_temp_vec_T_21) node _ldq_enq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node ldq_enq_retry_idx_temp_vec_22 = and(_ldq_enq_retry_idx_T_68, _ldq_enq_retry_idx_temp_vec_T_22) node _ldq_enq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node ldq_enq_retry_idx_temp_vec_23 = and(_ldq_enq_retry_idx_T_71, _ldq_enq_retry_idx_temp_vec_T_23) node _ldq_enq_retry_idx_idx_T = mux(_ldq_enq_retry_idx_T_68, UInt<6>(0h36), UInt<6>(0h37)) node _ldq_enq_retry_idx_idx_T_1 = mux(_ldq_enq_retry_idx_T_65, UInt<6>(0h35), _ldq_enq_retry_idx_idx_T) node _ldq_enq_retry_idx_idx_T_2 = mux(_ldq_enq_retry_idx_T_62, UInt<6>(0h34), _ldq_enq_retry_idx_idx_T_1) node _ldq_enq_retry_idx_idx_T_3 = mux(_ldq_enq_retry_idx_T_59, UInt<6>(0h33), _ldq_enq_retry_idx_idx_T_2) node _ldq_enq_retry_idx_idx_T_4 = mux(_ldq_enq_retry_idx_T_56, UInt<6>(0h32), _ldq_enq_retry_idx_idx_T_3) node _ldq_enq_retry_idx_idx_T_5 = mux(_ldq_enq_retry_idx_T_53, UInt<6>(0h31), _ldq_enq_retry_idx_idx_T_4) node _ldq_enq_retry_idx_idx_T_6 = mux(_ldq_enq_retry_idx_T_50, UInt<6>(0h30), _ldq_enq_retry_idx_idx_T_5) node _ldq_enq_retry_idx_idx_T_7 = mux(_ldq_enq_retry_idx_T_47, UInt<6>(0h2f), _ldq_enq_retry_idx_idx_T_6) node _ldq_enq_retry_idx_idx_T_8 = mux(_ldq_enq_retry_idx_T_44, UInt<6>(0h2e), _ldq_enq_retry_idx_idx_T_7) node _ldq_enq_retry_idx_idx_T_9 = mux(_ldq_enq_retry_idx_T_41, UInt<6>(0h2d), _ldq_enq_retry_idx_idx_T_8) node _ldq_enq_retry_idx_idx_T_10 = mux(_ldq_enq_retry_idx_T_38, UInt<6>(0h2c), _ldq_enq_retry_idx_idx_T_9) node _ldq_enq_retry_idx_idx_T_11 = mux(_ldq_enq_retry_idx_T_35, UInt<6>(0h2b), _ldq_enq_retry_idx_idx_T_10) node _ldq_enq_retry_idx_idx_T_12 = mux(_ldq_enq_retry_idx_T_32, UInt<6>(0h2a), _ldq_enq_retry_idx_idx_T_11) node _ldq_enq_retry_idx_idx_T_13 = mux(_ldq_enq_retry_idx_T_29, UInt<6>(0h29), _ldq_enq_retry_idx_idx_T_12) node _ldq_enq_retry_idx_idx_T_14 = mux(_ldq_enq_retry_idx_T_26, UInt<6>(0h28), _ldq_enq_retry_idx_idx_T_13) node _ldq_enq_retry_idx_idx_T_15 = mux(_ldq_enq_retry_idx_T_23, UInt<6>(0h27), _ldq_enq_retry_idx_idx_T_14) node _ldq_enq_retry_idx_idx_T_16 = mux(_ldq_enq_retry_idx_T_20, UInt<6>(0h26), _ldq_enq_retry_idx_idx_T_15) node _ldq_enq_retry_idx_idx_T_17 = mux(_ldq_enq_retry_idx_T_17, UInt<6>(0h25), _ldq_enq_retry_idx_idx_T_16) node _ldq_enq_retry_idx_idx_T_18 = mux(_ldq_enq_retry_idx_T_14, UInt<6>(0h24), _ldq_enq_retry_idx_idx_T_17) node _ldq_enq_retry_idx_idx_T_19 = mux(_ldq_enq_retry_idx_T_11, UInt<6>(0h23), _ldq_enq_retry_idx_idx_T_18) node _ldq_enq_retry_idx_idx_T_20 = mux(_ldq_enq_retry_idx_T_8, UInt<6>(0h22), _ldq_enq_retry_idx_idx_T_19) node _ldq_enq_retry_idx_idx_T_21 = mux(_ldq_enq_retry_idx_T_5, UInt<6>(0h21), _ldq_enq_retry_idx_idx_T_20) node _ldq_enq_retry_idx_idx_T_22 = mux(_ldq_enq_retry_idx_T_2, UInt<6>(0h20), _ldq_enq_retry_idx_idx_T_21) node _ldq_enq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _ldq_enq_retry_idx_idx_T_22) node _ldq_enq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _ldq_enq_retry_idx_idx_T_23) node _ldq_enq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _ldq_enq_retry_idx_idx_T_24) node _ldq_enq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _ldq_enq_retry_idx_idx_T_25) node _ldq_enq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _ldq_enq_retry_idx_idx_T_26) node _ldq_enq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _ldq_enq_retry_idx_idx_T_27) node _ldq_enq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _ldq_enq_retry_idx_idx_T_28) node _ldq_enq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _ldq_enq_retry_idx_idx_T_29) node _ldq_enq_retry_idx_idx_T_31 = mux(ldq_enq_retry_idx_temp_vec_23, UInt<5>(0h17), _ldq_enq_retry_idx_idx_T_30) node _ldq_enq_retry_idx_idx_T_32 = mux(ldq_enq_retry_idx_temp_vec_22, UInt<5>(0h16), _ldq_enq_retry_idx_idx_T_31) node _ldq_enq_retry_idx_idx_T_33 = mux(ldq_enq_retry_idx_temp_vec_21, UInt<5>(0h15), _ldq_enq_retry_idx_idx_T_32) node _ldq_enq_retry_idx_idx_T_34 = mux(ldq_enq_retry_idx_temp_vec_20, UInt<5>(0h14), _ldq_enq_retry_idx_idx_T_33) node _ldq_enq_retry_idx_idx_T_35 = mux(ldq_enq_retry_idx_temp_vec_19, UInt<5>(0h13), _ldq_enq_retry_idx_idx_T_34) node _ldq_enq_retry_idx_idx_T_36 = mux(ldq_enq_retry_idx_temp_vec_18, UInt<5>(0h12), _ldq_enq_retry_idx_idx_T_35) node _ldq_enq_retry_idx_idx_T_37 = mux(ldq_enq_retry_idx_temp_vec_17, UInt<5>(0h11), _ldq_enq_retry_idx_idx_T_36) node _ldq_enq_retry_idx_idx_T_38 = mux(ldq_enq_retry_idx_temp_vec_16, UInt<5>(0h10), _ldq_enq_retry_idx_idx_T_37) node _ldq_enq_retry_idx_idx_T_39 = mux(ldq_enq_retry_idx_temp_vec_15, UInt<4>(0hf), _ldq_enq_retry_idx_idx_T_38) node _ldq_enq_retry_idx_idx_T_40 = mux(ldq_enq_retry_idx_temp_vec_14, UInt<4>(0he), _ldq_enq_retry_idx_idx_T_39) node _ldq_enq_retry_idx_idx_T_41 = mux(ldq_enq_retry_idx_temp_vec_13, UInt<4>(0hd), _ldq_enq_retry_idx_idx_T_40) node _ldq_enq_retry_idx_idx_T_42 = mux(ldq_enq_retry_idx_temp_vec_12, UInt<4>(0hc), _ldq_enq_retry_idx_idx_T_41) node _ldq_enq_retry_idx_idx_T_43 = mux(ldq_enq_retry_idx_temp_vec_11, UInt<4>(0hb), _ldq_enq_retry_idx_idx_T_42) node _ldq_enq_retry_idx_idx_T_44 = mux(ldq_enq_retry_idx_temp_vec_10, UInt<4>(0ha), _ldq_enq_retry_idx_idx_T_43) node _ldq_enq_retry_idx_idx_T_45 = mux(ldq_enq_retry_idx_temp_vec_9, UInt<4>(0h9), _ldq_enq_retry_idx_idx_T_44) node _ldq_enq_retry_idx_idx_T_46 = mux(ldq_enq_retry_idx_temp_vec_8, UInt<4>(0h8), _ldq_enq_retry_idx_idx_T_45) node _ldq_enq_retry_idx_idx_T_47 = mux(ldq_enq_retry_idx_temp_vec_7, UInt<3>(0h7), _ldq_enq_retry_idx_idx_T_46) node _ldq_enq_retry_idx_idx_T_48 = mux(ldq_enq_retry_idx_temp_vec_6, UInt<3>(0h6), _ldq_enq_retry_idx_idx_T_47) node _ldq_enq_retry_idx_idx_T_49 = mux(ldq_enq_retry_idx_temp_vec_5, UInt<3>(0h5), _ldq_enq_retry_idx_idx_T_48) node _ldq_enq_retry_idx_idx_T_50 = mux(ldq_enq_retry_idx_temp_vec_4, UInt<3>(0h4), _ldq_enq_retry_idx_idx_T_49) node _ldq_enq_retry_idx_idx_T_51 = mux(ldq_enq_retry_idx_temp_vec_3, UInt<2>(0h3), _ldq_enq_retry_idx_idx_T_50) node _ldq_enq_retry_idx_idx_T_52 = mux(ldq_enq_retry_idx_temp_vec_2, UInt<2>(0h2), _ldq_enq_retry_idx_idx_T_51) node _ldq_enq_retry_idx_idx_T_53 = mux(ldq_enq_retry_idx_temp_vec_1, UInt<1>(0h1), _ldq_enq_retry_idx_idx_T_52) node ldq_enq_retry_idx_idx = mux(ldq_enq_retry_idx_temp_vec_0, UInt<1>(0h0), _ldq_enq_retry_idx_idx_T_53) node _ldq_enq_retry_idx_T_72 = bits(ldq_enq_retry_idx_idx, 4, 0) connect ldq_enq_retry_idx, _ldq_enq_retry_idx_T_72 wire ldq_enq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_enq_retry_e_e.valid, ldq_valid[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.uop, ldq_uop[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr, ldq_addr[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.executed, ldq_executed[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.succeeded, ldq_succeeded[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.order_fail, ldq_order_fail[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.observed, ldq_observed[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.st_dep_mask, ldq_st_dep_mask[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.forward_std_val, ldq_forward_std_val[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[ldq_enq_retry_idx] connect ldq_enq_retry_e_e.bits.debug_wb_data, ldq_debug_wb_data[ldq_enq_retry_idx] wire ldq_enq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect ldq_enq_retry_e, ldq_enq_retry_e_e reg stq_enq_retry_idx : UInt<5>, clock node _stq_enq_retry_idx_T = and(stq_addr[0].valid, stq_addr_is_virtual[0]) node _stq_enq_retry_idx_T_1 = neq(UInt<1>(0h0), stq_enq_retry_idx) node _stq_enq_retry_idx_T_2 = and(_stq_enq_retry_idx_T, _stq_enq_retry_idx_T_1) node _stq_enq_retry_idx_T_3 = and(stq_addr[1].valid, stq_addr_is_virtual[1]) node _stq_enq_retry_idx_T_4 = neq(UInt<1>(0h1), stq_enq_retry_idx) node _stq_enq_retry_idx_T_5 = and(_stq_enq_retry_idx_T_3, _stq_enq_retry_idx_T_4) node _stq_enq_retry_idx_T_6 = and(stq_addr[2].valid, stq_addr_is_virtual[2]) node _stq_enq_retry_idx_T_7 = neq(UInt<2>(0h2), stq_enq_retry_idx) node _stq_enq_retry_idx_T_8 = and(_stq_enq_retry_idx_T_6, _stq_enq_retry_idx_T_7) node _stq_enq_retry_idx_T_9 = and(stq_addr[3].valid, stq_addr_is_virtual[3]) node _stq_enq_retry_idx_T_10 = neq(UInt<2>(0h3), stq_enq_retry_idx) node _stq_enq_retry_idx_T_11 = and(_stq_enq_retry_idx_T_9, _stq_enq_retry_idx_T_10) node _stq_enq_retry_idx_T_12 = and(stq_addr[4].valid, stq_addr_is_virtual[4]) node _stq_enq_retry_idx_T_13 = neq(UInt<3>(0h4), stq_enq_retry_idx) node _stq_enq_retry_idx_T_14 = and(_stq_enq_retry_idx_T_12, _stq_enq_retry_idx_T_13) node _stq_enq_retry_idx_T_15 = and(stq_addr[5].valid, stq_addr_is_virtual[5]) node _stq_enq_retry_idx_T_16 = neq(UInt<3>(0h5), stq_enq_retry_idx) node _stq_enq_retry_idx_T_17 = and(_stq_enq_retry_idx_T_15, _stq_enq_retry_idx_T_16) node _stq_enq_retry_idx_T_18 = and(stq_addr[6].valid, stq_addr_is_virtual[6]) node _stq_enq_retry_idx_T_19 = neq(UInt<3>(0h6), stq_enq_retry_idx) node _stq_enq_retry_idx_T_20 = and(_stq_enq_retry_idx_T_18, _stq_enq_retry_idx_T_19) node _stq_enq_retry_idx_T_21 = and(stq_addr[7].valid, stq_addr_is_virtual[7]) node _stq_enq_retry_idx_T_22 = neq(UInt<3>(0h7), stq_enq_retry_idx) node _stq_enq_retry_idx_T_23 = and(_stq_enq_retry_idx_T_21, _stq_enq_retry_idx_T_22) node _stq_enq_retry_idx_T_24 = and(stq_addr[8].valid, stq_addr_is_virtual[8]) node _stq_enq_retry_idx_T_25 = neq(UInt<4>(0h8), stq_enq_retry_idx) node _stq_enq_retry_idx_T_26 = and(_stq_enq_retry_idx_T_24, _stq_enq_retry_idx_T_25) node _stq_enq_retry_idx_T_27 = and(stq_addr[9].valid, stq_addr_is_virtual[9]) node _stq_enq_retry_idx_T_28 = neq(UInt<4>(0h9), stq_enq_retry_idx) node _stq_enq_retry_idx_T_29 = and(_stq_enq_retry_idx_T_27, _stq_enq_retry_idx_T_28) node _stq_enq_retry_idx_T_30 = and(stq_addr[10].valid, stq_addr_is_virtual[10]) node _stq_enq_retry_idx_T_31 = neq(UInt<4>(0ha), stq_enq_retry_idx) node _stq_enq_retry_idx_T_32 = and(_stq_enq_retry_idx_T_30, _stq_enq_retry_idx_T_31) node _stq_enq_retry_idx_T_33 = and(stq_addr[11].valid, stq_addr_is_virtual[11]) node _stq_enq_retry_idx_T_34 = neq(UInt<4>(0hb), stq_enq_retry_idx) node _stq_enq_retry_idx_T_35 = and(_stq_enq_retry_idx_T_33, _stq_enq_retry_idx_T_34) node _stq_enq_retry_idx_T_36 = and(stq_addr[12].valid, stq_addr_is_virtual[12]) node _stq_enq_retry_idx_T_37 = neq(UInt<4>(0hc), stq_enq_retry_idx) node _stq_enq_retry_idx_T_38 = and(_stq_enq_retry_idx_T_36, _stq_enq_retry_idx_T_37) node _stq_enq_retry_idx_T_39 = and(stq_addr[13].valid, stq_addr_is_virtual[13]) node _stq_enq_retry_idx_T_40 = neq(UInt<4>(0hd), stq_enq_retry_idx) node _stq_enq_retry_idx_T_41 = and(_stq_enq_retry_idx_T_39, _stq_enq_retry_idx_T_40) node _stq_enq_retry_idx_T_42 = and(stq_addr[14].valid, stq_addr_is_virtual[14]) node _stq_enq_retry_idx_T_43 = neq(UInt<4>(0he), stq_enq_retry_idx) node _stq_enq_retry_idx_T_44 = and(_stq_enq_retry_idx_T_42, _stq_enq_retry_idx_T_43) node _stq_enq_retry_idx_T_45 = and(stq_addr[15].valid, stq_addr_is_virtual[15]) node _stq_enq_retry_idx_T_46 = neq(UInt<4>(0hf), stq_enq_retry_idx) node _stq_enq_retry_idx_T_47 = and(_stq_enq_retry_idx_T_45, _stq_enq_retry_idx_T_46) node _stq_enq_retry_idx_T_48 = and(stq_addr[16].valid, stq_addr_is_virtual[16]) node _stq_enq_retry_idx_T_49 = neq(UInt<5>(0h10), stq_enq_retry_idx) node _stq_enq_retry_idx_T_50 = and(_stq_enq_retry_idx_T_48, _stq_enq_retry_idx_T_49) node _stq_enq_retry_idx_T_51 = and(stq_addr[17].valid, stq_addr_is_virtual[17]) node _stq_enq_retry_idx_T_52 = neq(UInt<5>(0h11), stq_enq_retry_idx) node _stq_enq_retry_idx_T_53 = and(_stq_enq_retry_idx_T_51, _stq_enq_retry_idx_T_52) node _stq_enq_retry_idx_T_54 = and(stq_addr[18].valid, stq_addr_is_virtual[18]) node _stq_enq_retry_idx_T_55 = neq(UInt<5>(0h12), stq_enq_retry_idx) node _stq_enq_retry_idx_T_56 = and(_stq_enq_retry_idx_T_54, _stq_enq_retry_idx_T_55) node _stq_enq_retry_idx_T_57 = and(stq_addr[19].valid, stq_addr_is_virtual[19]) node _stq_enq_retry_idx_T_58 = neq(UInt<5>(0h13), stq_enq_retry_idx) node _stq_enq_retry_idx_T_59 = and(_stq_enq_retry_idx_T_57, _stq_enq_retry_idx_T_58) node _stq_enq_retry_idx_T_60 = and(stq_addr[20].valid, stq_addr_is_virtual[20]) node _stq_enq_retry_idx_T_61 = neq(UInt<5>(0h14), stq_enq_retry_idx) node _stq_enq_retry_idx_T_62 = and(_stq_enq_retry_idx_T_60, _stq_enq_retry_idx_T_61) node _stq_enq_retry_idx_T_63 = and(stq_addr[21].valid, stq_addr_is_virtual[21]) node _stq_enq_retry_idx_T_64 = neq(UInt<5>(0h15), stq_enq_retry_idx) node _stq_enq_retry_idx_T_65 = and(_stq_enq_retry_idx_T_63, _stq_enq_retry_idx_T_64) node _stq_enq_retry_idx_T_66 = and(stq_addr[22].valid, stq_addr_is_virtual[22]) node _stq_enq_retry_idx_T_67 = neq(UInt<5>(0h16), stq_enq_retry_idx) node _stq_enq_retry_idx_T_68 = and(_stq_enq_retry_idx_T_66, _stq_enq_retry_idx_T_67) node _stq_enq_retry_idx_T_69 = and(stq_addr[23].valid, stq_addr_is_virtual[23]) node _stq_enq_retry_idx_T_70 = neq(UInt<5>(0h17), stq_enq_retry_idx) node _stq_enq_retry_idx_T_71 = and(_stq_enq_retry_idx_T_69, _stq_enq_retry_idx_T_70) node _stq_enq_retry_idx_temp_vec_T = geq(UInt<1>(0h0), stq_commit_head) node stq_enq_retry_idx_temp_vec_0 = and(_stq_enq_retry_idx_T_2, _stq_enq_retry_idx_temp_vec_T) node _stq_enq_retry_idx_temp_vec_T_1 = geq(UInt<1>(0h1), stq_commit_head) node stq_enq_retry_idx_temp_vec_1 = and(_stq_enq_retry_idx_T_5, _stq_enq_retry_idx_temp_vec_T_1) node _stq_enq_retry_idx_temp_vec_T_2 = geq(UInt<2>(0h2), stq_commit_head) node stq_enq_retry_idx_temp_vec_2 = and(_stq_enq_retry_idx_T_8, _stq_enq_retry_idx_temp_vec_T_2) node _stq_enq_retry_idx_temp_vec_T_3 = geq(UInt<2>(0h3), stq_commit_head) node stq_enq_retry_idx_temp_vec_3 = and(_stq_enq_retry_idx_T_11, _stq_enq_retry_idx_temp_vec_T_3) node _stq_enq_retry_idx_temp_vec_T_4 = geq(UInt<3>(0h4), stq_commit_head) node stq_enq_retry_idx_temp_vec_4 = and(_stq_enq_retry_idx_T_14, _stq_enq_retry_idx_temp_vec_T_4) node _stq_enq_retry_idx_temp_vec_T_5 = geq(UInt<3>(0h5), stq_commit_head) node stq_enq_retry_idx_temp_vec_5 = and(_stq_enq_retry_idx_T_17, _stq_enq_retry_idx_temp_vec_T_5) node _stq_enq_retry_idx_temp_vec_T_6 = geq(UInt<3>(0h6), stq_commit_head) node stq_enq_retry_idx_temp_vec_6 = and(_stq_enq_retry_idx_T_20, _stq_enq_retry_idx_temp_vec_T_6) node _stq_enq_retry_idx_temp_vec_T_7 = geq(UInt<3>(0h7), stq_commit_head) node stq_enq_retry_idx_temp_vec_7 = and(_stq_enq_retry_idx_T_23, _stq_enq_retry_idx_temp_vec_T_7) node _stq_enq_retry_idx_temp_vec_T_8 = geq(UInt<4>(0h8), stq_commit_head) node stq_enq_retry_idx_temp_vec_8 = and(_stq_enq_retry_idx_T_26, _stq_enq_retry_idx_temp_vec_T_8) node _stq_enq_retry_idx_temp_vec_T_9 = geq(UInt<4>(0h9), stq_commit_head) node stq_enq_retry_idx_temp_vec_9 = and(_stq_enq_retry_idx_T_29, _stq_enq_retry_idx_temp_vec_T_9) node _stq_enq_retry_idx_temp_vec_T_10 = geq(UInt<4>(0ha), stq_commit_head) node stq_enq_retry_idx_temp_vec_10 = and(_stq_enq_retry_idx_T_32, _stq_enq_retry_idx_temp_vec_T_10) node _stq_enq_retry_idx_temp_vec_T_11 = geq(UInt<4>(0hb), stq_commit_head) node stq_enq_retry_idx_temp_vec_11 = and(_stq_enq_retry_idx_T_35, _stq_enq_retry_idx_temp_vec_T_11) node _stq_enq_retry_idx_temp_vec_T_12 = geq(UInt<4>(0hc), stq_commit_head) node stq_enq_retry_idx_temp_vec_12 = and(_stq_enq_retry_idx_T_38, _stq_enq_retry_idx_temp_vec_T_12) node _stq_enq_retry_idx_temp_vec_T_13 = geq(UInt<4>(0hd), stq_commit_head) node stq_enq_retry_idx_temp_vec_13 = and(_stq_enq_retry_idx_T_41, _stq_enq_retry_idx_temp_vec_T_13) node _stq_enq_retry_idx_temp_vec_T_14 = geq(UInt<4>(0he), stq_commit_head) node stq_enq_retry_idx_temp_vec_14 = and(_stq_enq_retry_idx_T_44, _stq_enq_retry_idx_temp_vec_T_14) node _stq_enq_retry_idx_temp_vec_T_15 = geq(UInt<4>(0hf), stq_commit_head) node stq_enq_retry_idx_temp_vec_15 = and(_stq_enq_retry_idx_T_47, _stq_enq_retry_idx_temp_vec_T_15) node _stq_enq_retry_idx_temp_vec_T_16 = geq(UInt<5>(0h10), stq_commit_head) node stq_enq_retry_idx_temp_vec_16 = and(_stq_enq_retry_idx_T_50, _stq_enq_retry_idx_temp_vec_T_16) node _stq_enq_retry_idx_temp_vec_T_17 = geq(UInt<5>(0h11), stq_commit_head) node stq_enq_retry_idx_temp_vec_17 = and(_stq_enq_retry_idx_T_53, _stq_enq_retry_idx_temp_vec_T_17) node _stq_enq_retry_idx_temp_vec_T_18 = geq(UInt<5>(0h12), stq_commit_head) node stq_enq_retry_idx_temp_vec_18 = and(_stq_enq_retry_idx_T_56, _stq_enq_retry_idx_temp_vec_T_18) node _stq_enq_retry_idx_temp_vec_T_19 = geq(UInt<5>(0h13), stq_commit_head) node stq_enq_retry_idx_temp_vec_19 = and(_stq_enq_retry_idx_T_59, _stq_enq_retry_idx_temp_vec_T_19) node _stq_enq_retry_idx_temp_vec_T_20 = geq(UInt<5>(0h14), stq_commit_head) node stq_enq_retry_idx_temp_vec_20 = and(_stq_enq_retry_idx_T_62, _stq_enq_retry_idx_temp_vec_T_20) node _stq_enq_retry_idx_temp_vec_T_21 = geq(UInt<5>(0h15), stq_commit_head) node stq_enq_retry_idx_temp_vec_21 = and(_stq_enq_retry_idx_T_65, _stq_enq_retry_idx_temp_vec_T_21) node _stq_enq_retry_idx_temp_vec_T_22 = geq(UInt<5>(0h16), stq_commit_head) node stq_enq_retry_idx_temp_vec_22 = and(_stq_enq_retry_idx_T_68, _stq_enq_retry_idx_temp_vec_T_22) node _stq_enq_retry_idx_temp_vec_T_23 = geq(UInt<5>(0h17), stq_commit_head) node stq_enq_retry_idx_temp_vec_23 = and(_stq_enq_retry_idx_T_71, _stq_enq_retry_idx_temp_vec_T_23) node _stq_enq_retry_idx_idx_T = mux(_stq_enq_retry_idx_T_68, UInt<6>(0h36), UInt<6>(0h37)) node _stq_enq_retry_idx_idx_T_1 = mux(_stq_enq_retry_idx_T_65, UInt<6>(0h35), _stq_enq_retry_idx_idx_T) node _stq_enq_retry_idx_idx_T_2 = mux(_stq_enq_retry_idx_T_62, UInt<6>(0h34), _stq_enq_retry_idx_idx_T_1) node _stq_enq_retry_idx_idx_T_3 = mux(_stq_enq_retry_idx_T_59, UInt<6>(0h33), _stq_enq_retry_idx_idx_T_2) node _stq_enq_retry_idx_idx_T_4 = mux(_stq_enq_retry_idx_T_56, UInt<6>(0h32), _stq_enq_retry_idx_idx_T_3) node _stq_enq_retry_idx_idx_T_5 = mux(_stq_enq_retry_idx_T_53, UInt<6>(0h31), _stq_enq_retry_idx_idx_T_4) node _stq_enq_retry_idx_idx_T_6 = mux(_stq_enq_retry_idx_T_50, UInt<6>(0h30), _stq_enq_retry_idx_idx_T_5) node _stq_enq_retry_idx_idx_T_7 = mux(_stq_enq_retry_idx_T_47, UInt<6>(0h2f), _stq_enq_retry_idx_idx_T_6) node _stq_enq_retry_idx_idx_T_8 = mux(_stq_enq_retry_idx_T_44, UInt<6>(0h2e), _stq_enq_retry_idx_idx_T_7) node _stq_enq_retry_idx_idx_T_9 = mux(_stq_enq_retry_idx_T_41, UInt<6>(0h2d), _stq_enq_retry_idx_idx_T_8) node _stq_enq_retry_idx_idx_T_10 = mux(_stq_enq_retry_idx_T_38, UInt<6>(0h2c), _stq_enq_retry_idx_idx_T_9) node _stq_enq_retry_idx_idx_T_11 = mux(_stq_enq_retry_idx_T_35, UInt<6>(0h2b), _stq_enq_retry_idx_idx_T_10) node _stq_enq_retry_idx_idx_T_12 = mux(_stq_enq_retry_idx_T_32, UInt<6>(0h2a), _stq_enq_retry_idx_idx_T_11) node _stq_enq_retry_idx_idx_T_13 = mux(_stq_enq_retry_idx_T_29, UInt<6>(0h29), _stq_enq_retry_idx_idx_T_12) node _stq_enq_retry_idx_idx_T_14 = mux(_stq_enq_retry_idx_T_26, UInt<6>(0h28), _stq_enq_retry_idx_idx_T_13) node _stq_enq_retry_idx_idx_T_15 = mux(_stq_enq_retry_idx_T_23, UInt<6>(0h27), _stq_enq_retry_idx_idx_T_14) node _stq_enq_retry_idx_idx_T_16 = mux(_stq_enq_retry_idx_T_20, UInt<6>(0h26), _stq_enq_retry_idx_idx_T_15) node _stq_enq_retry_idx_idx_T_17 = mux(_stq_enq_retry_idx_T_17, UInt<6>(0h25), _stq_enq_retry_idx_idx_T_16) node _stq_enq_retry_idx_idx_T_18 = mux(_stq_enq_retry_idx_T_14, UInt<6>(0h24), _stq_enq_retry_idx_idx_T_17) node _stq_enq_retry_idx_idx_T_19 = mux(_stq_enq_retry_idx_T_11, UInt<6>(0h23), _stq_enq_retry_idx_idx_T_18) node _stq_enq_retry_idx_idx_T_20 = mux(_stq_enq_retry_idx_T_8, UInt<6>(0h22), _stq_enq_retry_idx_idx_T_19) node _stq_enq_retry_idx_idx_T_21 = mux(_stq_enq_retry_idx_T_5, UInt<6>(0h21), _stq_enq_retry_idx_idx_T_20) node _stq_enq_retry_idx_idx_T_22 = mux(_stq_enq_retry_idx_T_2, UInt<6>(0h20), _stq_enq_retry_idx_idx_T_21) node _stq_enq_retry_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _stq_enq_retry_idx_idx_T_22) node _stq_enq_retry_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _stq_enq_retry_idx_idx_T_23) node _stq_enq_retry_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _stq_enq_retry_idx_idx_T_24) node _stq_enq_retry_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _stq_enq_retry_idx_idx_T_25) node _stq_enq_retry_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _stq_enq_retry_idx_idx_T_26) node _stq_enq_retry_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _stq_enq_retry_idx_idx_T_27) node _stq_enq_retry_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _stq_enq_retry_idx_idx_T_28) node _stq_enq_retry_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _stq_enq_retry_idx_idx_T_29) node _stq_enq_retry_idx_idx_T_31 = mux(stq_enq_retry_idx_temp_vec_23, UInt<5>(0h17), _stq_enq_retry_idx_idx_T_30) node _stq_enq_retry_idx_idx_T_32 = mux(stq_enq_retry_idx_temp_vec_22, UInt<5>(0h16), _stq_enq_retry_idx_idx_T_31) node _stq_enq_retry_idx_idx_T_33 = mux(stq_enq_retry_idx_temp_vec_21, UInt<5>(0h15), _stq_enq_retry_idx_idx_T_32) node _stq_enq_retry_idx_idx_T_34 = mux(stq_enq_retry_idx_temp_vec_20, UInt<5>(0h14), _stq_enq_retry_idx_idx_T_33) node _stq_enq_retry_idx_idx_T_35 = mux(stq_enq_retry_idx_temp_vec_19, UInt<5>(0h13), _stq_enq_retry_idx_idx_T_34) node _stq_enq_retry_idx_idx_T_36 = mux(stq_enq_retry_idx_temp_vec_18, UInt<5>(0h12), _stq_enq_retry_idx_idx_T_35) node _stq_enq_retry_idx_idx_T_37 = mux(stq_enq_retry_idx_temp_vec_17, UInt<5>(0h11), _stq_enq_retry_idx_idx_T_36) node _stq_enq_retry_idx_idx_T_38 = mux(stq_enq_retry_idx_temp_vec_16, UInt<5>(0h10), _stq_enq_retry_idx_idx_T_37) node _stq_enq_retry_idx_idx_T_39 = mux(stq_enq_retry_idx_temp_vec_15, UInt<4>(0hf), _stq_enq_retry_idx_idx_T_38) node _stq_enq_retry_idx_idx_T_40 = mux(stq_enq_retry_idx_temp_vec_14, UInt<4>(0he), _stq_enq_retry_idx_idx_T_39) node _stq_enq_retry_idx_idx_T_41 = mux(stq_enq_retry_idx_temp_vec_13, UInt<4>(0hd), _stq_enq_retry_idx_idx_T_40) node _stq_enq_retry_idx_idx_T_42 = mux(stq_enq_retry_idx_temp_vec_12, UInt<4>(0hc), _stq_enq_retry_idx_idx_T_41) node _stq_enq_retry_idx_idx_T_43 = mux(stq_enq_retry_idx_temp_vec_11, UInt<4>(0hb), _stq_enq_retry_idx_idx_T_42) node _stq_enq_retry_idx_idx_T_44 = mux(stq_enq_retry_idx_temp_vec_10, UInt<4>(0ha), _stq_enq_retry_idx_idx_T_43) node _stq_enq_retry_idx_idx_T_45 = mux(stq_enq_retry_idx_temp_vec_9, UInt<4>(0h9), _stq_enq_retry_idx_idx_T_44) node _stq_enq_retry_idx_idx_T_46 = mux(stq_enq_retry_idx_temp_vec_8, UInt<4>(0h8), _stq_enq_retry_idx_idx_T_45) node _stq_enq_retry_idx_idx_T_47 = mux(stq_enq_retry_idx_temp_vec_7, UInt<3>(0h7), _stq_enq_retry_idx_idx_T_46) node _stq_enq_retry_idx_idx_T_48 = mux(stq_enq_retry_idx_temp_vec_6, UInt<3>(0h6), _stq_enq_retry_idx_idx_T_47) node _stq_enq_retry_idx_idx_T_49 = mux(stq_enq_retry_idx_temp_vec_5, UInt<3>(0h5), _stq_enq_retry_idx_idx_T_48) node _stq_enq_retry_idx_idx_T_50 = mux(stq_enq_retry_idx_temp_vec_4, UInt<3>(0h4), _stq_enq_retry_idx_idx_T_49) node _stq_enq_retry_idx_idx_T_51 = mux(stq_enq_retry_idx_temp_vec_3, UInt<2>(0h3), _stq_enq_retry_idx_idx_T_50) node _stq_enq_retry_idx_idx_T_52 = mux(stq_enq_retry_idx_temp_vec_2, UInt<2>(0h2), _stq_enq_retry_idx_idx_T_51) node _stq_enq_retry_idx_idx_T_53 = mux(stq_enq_retry_idx_temp_vec_1, UInt<1>(0h1), _stq_enq_retry_idx_idx_T_52) node stq_enq_retry_idx_idx = mux(stq_enq_retry_idx_temp_vec_0, UInt<1>(0h0), _stq_enq_retry_idx_idx_T_53) node _stq_enq_retry_idx_T_72 = bits(stq_enq_retry_idx_idx, 4, 0) connect stq_enq_retry_idx, _stq_enq_retry_idx_T_72 wire stq_enq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_retry_e_e.valid, stq_valid[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.uop, stq_uop[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.addr, stq_addr[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.data, stq_data[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.committed, stq_committed[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.succeeded, stq_succeeded[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.can_execute, stq_can_execute[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.cleared, stq_cleared[stq_enq_retry_idx] connect stq_enq_retry_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_enq_retry_idx] wire stq_enq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_retry_e, stq_enq_retry_e_e node _can_enq_load_retry_T = and(ldq_enq_retry_e.valid, ldq_enq_retry_e.bits.addr.valid) node can_enq_load_retry = and(_can_enq_load_retry_T, ldq_enq_retry_e.bits.addr_is_virtual) node _can_enq_store_retry_T = and(stq_enq_retry_e.valid, stq_enq_retry_e.bits.addr.valid) node can_enq_store_retry = and(_can_enq_store_retry_T, stq_enq_retry_e.bits.addr_is_virtual) inst retry_queue of BranchKillableQueue_11 connect retry_queue.clock, clock connect retry_queue.reset, reset connect retry_queue.io.brupdate.b2.target_offset, io.core.brupdate.b2.target_offset connect retry_queue.io.brupdate.b2.jalr_target, io.core.brupdate.b2.jalr_target connect retry_queue.io.brupdate.b2.pc_sel, io.core.brupdate.b2.pc_sel connect retry_queue.io.brupdate.b2.cfi_type, io.core.brupdate.b2.cfi_type connect retry_queue.io.brupdate.b2.taken, io.core.brupdate.b2.taken connect retry_queue.io.brupdate.b2.mispredict, io.core.brupdate.b2.mispredict connect retry_queue.io.brupdate.b2.uop.debug_tsrc, io.core.brupdate.b2.uop.debug_tsrc connect retry_queue.io.brupdate.b2.uop.debug_fsrc, io.core.brupdate.b2.uop.debug_fsrc connect retry_queue.io.brupdate.b2.uop.bp_xcpt_if, io.core.brupdate.b2.uop.bp_xcpt_if connect retry_queue.io.brupdate.b2.uop.bp_debug_if, io.core.brupdate.b2.uop.bp_debug_if connect retry_queue.io.brupdate.b2.uop.xcpt_ma_if, io.core.brupdate.b2.uop.xcpt_ma_if connect retry_queue.io.brupdate.b2.uop.xcpt_ae_if, io.core.brupdate.b2.uop.xcpt_ae_if connect retry_queue.io.brupdate.b2.uop.xcpt_pf_if, io.core.brupdate.b2.uop.xcpt_pf_if connect retry_queue.io.brupdate.b2.uop.fp_typ, io.core.brupdate.b2.uop.fp_typ connect retry_queue.io.brupdate.b2.uop.fp_rm, io.core.brupdate.b2.uop.fp_rm connect retry_queue.io.brupdate.b2.uop.fp_val, io.core.brupdate.b2.uop.fp_val connect retry_queue.io.brupdate.b2.uop.fcn_op, io.core.brupdate.b2.uop.fcn_op connect retry_queue.io.brupdate.b2.uop.fcn_dw, io.core.brupdate.b2.uop.fcn_dw connect retry_queue.io.brupdate.b2.uop.frs3_en, io.core.brupdate.b2.uop.frs3_en connect retry_queue.io.brupdate.b2.uop.lrs2_rtype, io.core.brupdate.b2.uop.lrs2_rtype connect retry_queue.io.brupdate.b2.uop.lrs1_rtype, io.core.brupdate.b2.uop.lrs1_rtype connect retry_queue.io.brupdate.b2.uop.dst_rtype, io.core.brupdate.b2.uop.dst_rtype connect retry_queue.io.brupdate.b2.uop.lrs3, io.core.brupdate.b2.uop.lrs3 connect retry_queue.io.brupdate.b2.uop.lrs2, io.core.brupdate.b2.uop.lrs2 connect retry_queue.io.brupdate.b2.uop.lrs1, io.core.brupdate.b2.uop.lrs1 connect retry_queue.io.brupdate.b2.uop.ldst, io.core.brupdate.b2.uop.ldst connect retry_queue.io.brupdate.b2.uop.ldst_is_rs1, io.core.brupdate.b2.uop.ldst_is_rs1 connect retry_queue.io.brupdate.b2.uop.csr_cmd, io.core.brupdate.b2.uop.csr_cmd connect retry_queue.io.brupdate.b2.uop.flush_on_commit, io.core.brupdate.b2.uop.flush_on_commit connect retry_queue.io.brupdate.b2.uop.is_unique, io.core.brupdate.b2.uop.is_unique connect retry_queue.io.brupdate.b2.uop.uses_stq, io.core.brupdate.b2.uop.uses_stq connect retry_queue.io.brupdate.b2.uop.uses_ldq, io.core.brupdate.b2.uop.uses_ldq connect retry_queue.io.brupdate.b2.uop.mem_signed, io.core.brupdate.b2.uop.mem_signed connect retry_queue.io.brupdate.b2.uop.mem_size, io.core.brupdate.b2.uop.mem_size connect retry_queue.io.brupdate.b2.uop.mem_cmd, io.core.brupdate.b2.uop.mem_cmd connect retry_queue.io.brupdate.b2.uop.exc_cause, io.core.brupdate.b2.uop.exc_cause connect retry_queue.io.brupdate.b2.uop.exception, io.core.brupdate.b2.uop.exception connect retry_queue.io.brupdate.b2.uop.stale_pdst, io.core.brupdate.b2.uop.stale_pdst connect retry_queue.io.brupdate.b2.uop.ppred_busy, io.core.brupdate.b2.uop.ppred_busy connect retry_queue.io.brupdate.b2.uop.prs3_busy, io.core.brupdate.b2.uop.prs3_busy connect retry_queue.io.brupdate.b2.uop.prs2_busy, io.core.brupdate.b2.uop.prs2_busy connect retry_queue.io.brupdate.b2.uop.prs1_busy, io.core.brupdate.b2.uop.prs1_busy connect retry_queue.io.brupdate.b2.uop.ppred, io.core.brupdate.b2.uop.ppred connect retry_queue.io.brupdate.b2.uop.prs3, io.core.brupdate.b2.uop.prs3 connect retry_queue.io.brupdate.b2.uop.prs2, io.core.brupdate.b2.uop.prs2 connect retry_queue.io.brupdate.b2.uop.prs1, io.core.brupdate.b2.uop.prs1 connect retry_queue.io.brupdate.b2.uop.pdst, io.core.brupdate.b2.uop.pdst connect retry_queue.io.brupdate.b2.uop.rxq_idx, io.core.brupdate.b2.uop.rxq_idx connect retry_queue.io.brupdate.b2.uop.stq_idx, io.core.brupdate.b2.uop.stq_idx connect retry_queue.io.brupdate.b2.uop.ldq_idx, io.core.brupdate.b2.uop.ldq_idx connect retry_queue.io.brupdate.b2.uop.rob_idx, io.core.brupdate.b2.uop.rob_idx connect retry_queue.io.brupdate.b2.uop.fp_ctrl.vec, io.core.brupdate.b2.uop.fp_ctrl.vec connect retry_queue.io.brupdate.b2.uop.fp_ctrl.wflags, io.core.brupdate.b2.uop.fp_ctrl.wflags connect retry_queue.io.brupdate.b2.uop.fp_ctrl.sqrt, io.core.brupdate.b2.uop.fp_ctrl.sqrt connect retry_queue.io.brupdate.b2.uop.fp_ctrl.div, io.core.brupdate.b2.uop.fp_ctrl.div connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fma, io.core.brupdate.b2.uop.fp_ctrl.fma connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fastpipe, io.core.brupdate.b2.uop.fp_ctrl.fastpipe connect retry_queue.io.brupdate.b2.uop.fp_ctrl.toint, io.core.brupdate.b2.uop.fp_ctrl.toint connect retry_queue.io.brupdate.b2.uop.fp_ctrl.fromint, io.core.brupdate.b2.uop.fp_ctrl.fromint connect retry_queue.io.brupdate.b2.uop.fp_ctrl.typeTagOut, io.core.brupdate.b2.uop.fp_ctrl.typeTagOut connect retry_queue.io.brupdate.b2.uop.fp_ctrl.typeTagIn, io.core.brupdate.b2.uop.fp_ctrl.typeTagIn connect retry_queue.io.brupdate.b2.uop.fp_ctrl.swap23, io.core.brupdate.b2.uop.fp_ctrl.swap23 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.swap12, io.core.brupdate.b2.uop.fp_ctrl.swap12 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren3, io.core.brupdate.b2.uop.fp_ctrl.ren3 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren2, io.core.brupdate.b2.uop.fp_ctrl.ren2 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ren1, io.core.brupdate.b2.uop.fp_ctrl.ren1 connect retry_queue.io.brupdate.b2.uop.fp_ctrl.wen, io.core.brupdate.b2.uop.fp_ctrl.wen connect retry_queue.io.brupdate.b2.uop.fp_ctrl.ldst, io.core.brupdate.b2.uop.fp_ctrl.ldst connect retry_queue.io.brupdate.b2.uop.op2_sel, io.core.brupdate.b2.uop.op2_sel connect retry_queue.io.brupdate.b2.uop.op1_sel, io.core.brupdate.b2.uop.op1_sel connect retry_queue.io.brupdate.b2.uop.imm_packed, io.core.brupdate.b2.uop.imm_packed connect retry_queue.io.brupdate.b2.uop.pimm, io.core.brupdate.b2.uop.pimm connect retry_queue.io.brupdate.b2.uop.imm_sel, io.core.brupdate.b2.uop.imm_sel connect retry_queue.io.brupdate.b2.uop.imm_rename, io.core.brupdate.b2.uop.imm_rename connect retry_queue.io.brupdate.b2.uop.taken, io.core.brupdate.b2.uop.taken connect retry_queue.io.brupdate.b2.uop.pc_lob, io.core.brupdate.b2.uop.pc_lob connect retry_queue.io.brupdate.b2.uop.edge_inst, io.core.brupdate.b2.uop.edge_inst connect retry_queue.io.brupdate.b2.uop.ftq_idx, io.core.brupdate.b2.uop.ftq_idx connect retry_queue.io.brupdate.b2.uop.is_mov, io.core.brupdate.b2.uop.is_mov connect retry_queue.io.brupdate.b2.uop.is_rocc, io.core.brupdate.b2.uop.is_rocc connect retry_queue.io.brupdate.b2.uop.is_sys_pc2epc, io.core.brupdate.b2.uop.is_sys_pc2epc connect retry_queue.io.brupdate.b2.uop.is_eret, io.core.brupdate.b2.uop.is_eret connect retry_queue.io.brupdate.b2.uop.is_amo, io.core.brupdate.b2.uop.is_amo connect retry_queue.io.brupdate.b2.uop.is_sfence, io.core.brupdate.b2.uop.is_sfence connect retry_queue.io.brupdate.b2.uop.is_fencei, io.core.brupdate.b2.uop.is_fencei connect retry_queue.io.brupdate.b2.uop.is_fence, io.core.brupdate.b2.uop.is_fence connect retry_queue.io.brupdate.b2.uop.is_sfb, io.core.brupdate.b2.uop.is_sfb connect retry_queue.io.brupdate.b2.uop.br_type, io.core.brupdate.b2.uop.br_type connect retry_queue.io.brupdate.b2.uop.br_tag, io.core.brupdate.b2.uop.br_tag connect retry_queue.io.brupdate.b2.uop.br_mask, io.core.brupdate.b2.uop.br_mask connect retry_queue.io.brupdate.b2.uop.dis_col_sel, io.core.brupdate.b2.uop.dis_col_sel connect retry_queue.io.brupdate.b2.uop.iw_p3_bypass_hint, io.core.brupdate.b2.uop.iw_p3_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p2_bypass_hint, io.core.brupdate.b2.uop.iw_p2_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p1_bypass_hint, io.core.brupdate.b2.uop.iw_p1_bypass_hint connect retry_queue.io.brupdate.b2.uop.iw_p2_speculative_child, io.core.brupdate.b2.uop.iw_p2_speculative_child connect retry_queue.io.brupdate.b2.uop.iw_p1_speculative_child, io.core.brupdate.b2.uop.iw_p1_speculative_child connect retry_queue.io.brupdate.b2.uop.iw_issued_partial_dgen, io.core.brupdate.b2.uop.iw_issued_partial_dgen connect retry_queue.io.brupdate.b2.uop.iw_issued_partial_agen, io.core.brupdate.b2.uop.iw_issued_partial_agen connect retry_queue.io.brupdate.b2.uop.iw_issued, io.core.brupdate.b2.uop.iw_issued connect retry_queue.io.brupdate.b2.uop.fu_code[0], io.core.brupdate.b2.uop.fu_code[0] connect retry_queue.io.brupdate.b2.uop.fu_code[1], io.core.brupdate.b2.uop.fu_code[1] connect retry_queue.io.brupdate.b2.uop.fu_code[2], io.core.brupdate.b2.uop.fu_code[2] connect retry_queue.io.brupdate.b2.uop.fu_code[3], io.core.brupdate.b2.uop.fu_code[3] connect retry_queue.io.brupdate.b2.uop.fu_code[4], io.core.brupdate.b2.uop.fu_code[4] connect retry_queue.io.brupdate.b2.uop.fu_code[5], io.core.brupdate.b2.uop.fu_code[5] connect retry_queue.io.brupdate.b2.uop.fu_code[6], io.core.brupdate.b2.uop.fu_code[6] connect retry_queue.io.brupdate.b2.uop.fu_code[7], io.core.brupdate.b2.uop.fu_code[7] connect retry_queue.io.brupdate.b2.uop.fu_code[8], io.core.brupdate.b2.uop.fu_code[8] connect retry_queue.io.brupdate.b2.uop.fu_code[9], io.core.brupdate.b2.uop.fu_code[9] connect retry_queue.io.brupdate.b2.uop.iq_type[0], io.core.brupdate.b2.uop.iq_type[0] connect retry_queue.io.brupdate.b2.uop.iq_type[1], io.core.brupdate.b2.uop.iq_type[1] connect retry_queue.io.brupdate.b2.uop.iq_type[2], io.core.brupdate.b2.uop.iq_type[2] connect retry_queue.io.brupdate.b2.uop.iq_type[3], io.core.brupdate.b2.uop.iq_type[3] connect retry_queue.io.brupdate.b2.uop.debug_pc, io.core.brupdate.b2.uop.debug_pc connect retry_queue.io.brupdate.b2.uop.is_rvc, io.core.brupdate.b2.uop.is_rvc connect retry_queue.io.brupdate.b2.uop.debug_inst, io.core.brupdate.b2.uop.debug_inst connect retry_queue.io.brupdate.b2.uop.inst, io.core.brupdate.b2.uop.inst connect retry_queue.io.brupdate.b1.mispredict_mask, io.core.brupdate.b1.mispredict_mask connect retry_queue.io.brupdate.b1.resolve_mask, io.core.brupdate.b1.resolve_mask connect retry_queue.io.flush, io.core.exception node _retry_queue_io_enq_valid_T = or(can_enq_store_retry, can_enq_load_retry) connect retry_queue.io.enq.valid, _retry_queue_io_enq_valid_T invalidate retry_queue.io.enq.bits.data invalidate retry_queue.io.enq.bits.uop.debug_tsrc invalidate retry_queue.io.enq.bits.uop.debug_fsrc invalidate retry_queue.io.enq.bits.uop.bp_xcpt_if invalidate retry_queue.io.enq.bits.uop.bp_debug_if invalidate retry_queue.io.enq.bits.uop.xcpt_ma_if invalidate retry_queue.io.enq.bits.uop.xcpt_ae_if invalidate retry_queue.io.enq.bits.uop.xcpt_pf_if invalidate retry_queue.io.enq.bits.uop.fp_typ invalidate retry_queue.io.enq.bits.uop.fp_rm invalidate retry_queue.io.enq.bits.uop.fp_val invalidate retry_queue.io.enq.bits.uop.fcn_op invalidate retry_queue.io.enq.bits.uop.fcn_dw invalidate retry_queue.io.enq.bits.uop.frs3_en invalidate retry_queue.io.enq.bits.uop.lrs2_rtype invalidate retry_queue.io.enq.bits.uop.lrs1_rtype invalidate retry_queue.io.enq.bits.uop.dst_rtype invalidate retry_queue.io.enq.bits.uop.lrs3 invalidate retry_queue.io.enq.bits.uop.lrs2 invalidate retry_queue.io.enq.bits.uop.lrs1 invalidate retry_queue.io.enq.bits.uop.ldst invalidate retry_queue.io.enq.bits.uop.ldst_is_rs1 invalidate retry_queue.io.enq.bits.uop.csr_cmd invalidate retry_queue.io.enq.bits.uop.flush_on_commit invalidate retry_queue.io.enq.bits.uop.is_unique invalidate retry_queue.io.enq.bits.uop.uses_stq invalidate retry_queue.io.enq.bits.uop.uses_ldq invalidate retry_queue.io.enq.bits.uop.mem_signed invalidate retry_queue.io.enq.bits.uop.mem_size invalidate retry_queue.io.enq.bits.uop.mem_cmd invalidate retry_queue.io.enq.bits.uop.exc_cause invalidate retry_queue.io.enq.bits.uop.exception invalidate retry_queue.io.enq.bits.uop.stale_pdst invalidate retry_queue.io.enq.bits.uop.ppred_busy invalidate retry_queue.io.enq.bits.uop.prs3_busy invalidate retry_queue.io.enq.bits.uop.prs2_busy invalidate retry_queue.io.enq.bits.uop.prs1_busy invalidate retry_queue.io.enq.bits.uop.ppred invalidate retry_queue.io.enq.bits.uop.prs3 invalidate retry_queue.io.enq.bits.uop.prs2 invalidate retry_queue.io.enq.bits.uop.prs1 invalidate retry_queue.io.enq.bits.uop.pdst invalidate retry_queue.io.enq.bits.uop.rxq_idx invalidate retry_queue.io.enq.bits.uop.stq_idx invalidate retry_queue.io.enq.bits.uop.ldq_idx invalidate retry_queue.io.enq.bits.uop.rob_idx invalidate retry_queue.io.enq.bits.uop.fp_ctrl.vec invalidate retry_queue.io.enq.bits.uop.fp_ctrl.wflags invalidate retry_queue.io.enq.bits.uop.fp_ctrl.sqrt invalidate retry_queue.io.enq.bits.uop.fp_ctrl.div invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fma invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fastpipe invalidate retry_queue.io.enq.bits.uop.fp_ctrl.toint invalidate retry_queue.io.enq.bits.uop.fp_ctrl.fromint invalidate retry_queue.io.enq.bits.uop.fp_ctrl.typeTagOut invalidate retry_queue.io.enq.bits.uop.fp_ctrl.typeTagIn invalidate retry_queue.io.enq.bits.uop.fp_ctrl.swap23 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.swap12 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren3 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren2 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ren1 invalidate retry_queue.io.enq.bits.uop.fp_ctrl.wen invalidate retry_queue.io.enq.bits.uop.fp_ctrl.ldst invalidate retry_queue.io.enq.bits.uop.op2_sel invalidate retry_queue.io.enq.bits.uop.op1_sel invalidate retry_queue.io.enq.bits.uop.imm_packed invalidate retry_queue.io.enq.bits.uop.pimm invalidate retry_queue.io.enq.bits.uop.imm_sel invalidate retry_queue.io.enq.bits.uop.imm_rename invalidate retry_queue.io.enq.bits.uop.taken invalidate retry_queue.io.enq.bits.uop.pc_lob invalidate retry_queue.io.enq.bits.uop.edge_inst invalidate retry_queue.io.enq.bits.uop.ftq_idx invalidate retry_queue.io.enq.bits.uop.is_mov invalidate retry_queue.io.enq.bits.uop.is_rocc invalidate retry_queue.io.enq.bits.uop.is_sys_pc2epc invalidate retry_queue.io.enq.bits.uop.is_eret invalidate retry_queue.io.enq.bits.uop.is_amo invalidate retry_queue.io.enq.bits.uop.is_sfence invalidate retry_queue.io.enq.bits.uop.is_fencei invalidate retry_queue.io.enq.bits.uop.is_fence invalidate retry_queue.io.enq.bits.uop.is_sfb invalidate retry_queue.io.enq.bits.uop.br_type invalidate retry_queue.io.enq.bits.uop.br_tag invalidate retry_queue.io.enq.bits.uop.br_mask invalidate retry_queue.io.enq.bits.uop.dis_col_sel invalidate retry_queue.io.enq.bits.uop.iw_p3_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p2_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p1_bypass_hint invalidate retry_queue.io.enq.bits.uop.iw_p2_speculative_child invalidate retry_queue.io.enq.bits.uop.iw_p1_speculative_child invalidate retry_queue.io.enq.bits.uop.iw_issued_partial_dgen invalidate retry_queue.io.enq.bits.uop.iw_issued_partial_agen invalidate retry_queue.io.enq.bits.uop.iw_issued invalidate retry_queue.io.enq.bits.uop.fu_code[0] invalidate retry_queue.io.enq.bits.uop.fu_code[1] invalidate retry_queue.io.enq.bits.uop.fu_code[2] invalidate retry_queue.io.enq.bits.uop.fu_code[3] invalidate retry_queue.io.enq.bits.uop.fu_code[4] invalidate retry_queue.io.enq.bits.uop.fu_code[5] invalidate retry_queue.io.enq.bits.uop.fu_code[6] invalidate retry_queue.io.enq.bits.uop.fu_code[7] invalidate retry_queue.io.enq.bits.uop.fu_code[8] invalidate retry_queue.io.enq.bits.uop.fu_code[9] invalidate retry_queue.io.enq.bits.uop.iq_type[0] invalidate retry_queue.io.enq.bits.uop.iq_type[1] invalidate retry_queue.io.enq.bits.uop.iq_type[2] invalidate retry_queue.io.enq.bits.uop.iq_type[3] invalidate retry_queue.io.enq.bits.uop.debug_pc invalidate retry_queue.io.enq.bits.uop.is_rvc invalidate retry_queue.io.enq.bits.uop.debug_inst invalidate retry_queue.io.enq.bits.uop.inst node _retry_queue_io_enq_bits_data_T = mux(can_enq_store_retry, stq_enq_retry_e.bits.addr.bits, ldq_enq_retry_e.bits.addr.bits) connect retry_queue.io.enq.bits.data, _retry_queue_io_enq_bits_data_T node _retry_queue_io_enq_bits_uop_T = mux(can_enq_store_retry, stq_enq_retry_e.bits.uop, ldq_enq_retry_e.bits.uop) connect retry_queue.io.enq.bits.uop.debug_tsrc, _retry_queue_io_enq_bits_uop_T.debug_tsrc connect retry_queue.io.enq.bits.uop.debug_fsrc, _retry_queue_io_enq_bits_uop_T.debug_fsrc connect retry_queue.io.enq.bits.uop.bp_xcpt_if, _retry_queue_io_enq_bits_uop_T.bp_xcpt_if connect retry_queue.io.enq.bits.uop.bp_debug_if, _retry_queue_io_enq_bits_uop_T.bp_debug_if connect retry_queue.io.enq.bits.uop.xcpt_ma_if, _retry_queue_io_enq_bits_uop_T.xcpt_ma_if connect retry_queue.io.enq.bits.uop.xcpt_ae_if, _retry_queue_io_enq_bits_uop_T.xcpt_ae_if connect retry_queue.io.enq.bits.uop.xcpt_pf_if, _retry_queue_io_enq_bits_uop_T.xcpt_pf_if connect retry_queue.io.enq.bits.uop.fp_typ, _retry_queue_io_enq_bits_uop_T.fp_typ connect retry_queue.io.enq.bits.uop.fp_rm, _retry_queue_io_enq_bits_uop_T.fp_rm connect retry_queue.io.enq.bits.uop.fp_val, _retry_queue_io_enq_bits_uop_T.fp_val connect retry_queue.io.enq.bits.uop.fcn_op, _retry_queue_io_enq_bits_uop_T.fcn_op connect retry_queue.io.enq.bits.uop.fcn_dw, _retry_queue_io_enq_bits_uop_T.fcn_dw connect retry_queue.io.enq.bits.uop.frs3_en, _retry_queue_io_enq_bits_uop_T.frs3_en connect retry_queue.io.enq.bits.uop.lrs2_rtype, _retry_queue_io_enq_bits_uop_T.lrs2_rtype connect retry_queue.io.enq.bits.uop.lrs1_rtype, _retry_queue_io_enq_bits_uop_T.lrs1_rtype connect retry_queue.io.enq.bits.uop.dst_rtype, _retry_queue_io_enq_bits_uop_T.dst_rtype connect retry_queue.io.enq.bits.uop.lrs3, _retry_queue_io_enq_bits_uop_T.lrs3 connect retry_queue.io.enq.bits.uop.lrs2, _retry_queue_io_enq_bits_uop_T.lrs2 connect retry_queue.io.enq.bits.uop.lrs1, _retry_queue_io_enq_bits_uop_T.lrs1 connect retry_queue.io.enq.bits.uop.ldst, _retry_queue_io_enq_bits_uop_T.ldst connect retry_queue.io.enq.bits.uop.ldst_is_rs1, _retry_queue_io_enq_bits_uop_T.ldst_is_rs1 connect retry_queue.io.enq.bits.uop.csr_cmd, _retry_queue_io_enq_bits_uop_T.csr_cmd connect retry_queue.io.enq.bits.uop.flush_on_commit, _retry_queue_io_enq_bits_uop_T.flush_on_commit connect retry_queue.io.enq.bits.uop.is_unique, _retry_queue_io_enq_bits_uop_T.is_unique connect retry_queue.io.enq.bits.uop.uses_stq, _retry_queue_io_enq_bits_uop_T.uses_stq connect retry_queue.io.enq.bits.uop.uses_ldq, _retry_queue_io_enq_bits_uop_T.uses_ldq connect retry_queue.io.enq.bits.uop.mem_signed, _retry_queue_io_enq_bits_uop_T.mem_signed connect retry_queue.io.enq.bits.uop.mem_size, _retry_queue_io_enq_bits_uop_T.mem_size connect retry_queue.io.enq.bits.uop.mem_cmd, _retry_queue_io_enq_bits_uop_T.mem_cmd connect retry_queue.io.enq.bits.uop.exc_cause, _retry_queue_io_enq_bits_uop_T.exc_cause connect retry_queue.io.enq.bits.uop.exception, _retry_queue_io_enq_bits_uop_T.exception connect retry_queue.io.enq.bits.uop.stale_pdst, _retry_queue_io_enq_bits_uop_T.stale_pdst connect retry_queue.io.enq.bits.uop.ppred_busy, _retry_queue_io_enq_bits_uop_T.ppred_busy connect retry_queue.io.enq.bits.uop.prs3_busy, _retry_queue_io_enq_bits_uop_T.prs3_busy connect retry_queue.io.enq.bits.uop.prs2_busy, _retry_queue_io_enq_bits_uop_T.prs2_busy connect retry_queue.io.enq.bits.uop.prs1_busy, _retry_queue_io_enq_bits_uop_T.prs1_busy connect retry_queue.io.enq.bits.uop.ppred, _retry_queue_io_enq_bits_uop_T.ppred connect retry_queue.io.enq.bits.uop.prs3, _retry_queue_io_enq_bits_uop_T.prs3 connect retry_queue.io.enq.bits.uop.prs2, _retry_queue_io_enq_bits_uop_T.prs2 connect retry_queue.io.enq.bits.uop.prs1, _retry_queue_io_enq_bits_uop_T.prs1 connect retry_queue.io.enq.bits.uop.pdst, _retry_queue_io_enq_bits_uop_T.pdst connect retry_queue.io.enq.bits.uop.rxq_idx, _retry_queue_io_enq_bits_uop_T.rxq_idx connect retry_queue.io.enq.bits.uop.stq_idx, _retry_queue_io_enq_bits_uop_T.stq_idx connect retry_queue.io.enq.bits.uop.ldq_idx, _retry_queue_io_enq_bits_uop_T.ldq_idx connect retry_queue.io.enq.bits.uop.rob_idx, _retry_queue_io_enq_bits_uop_T.rob_idx connect retry_queue.io.enq.bits.uop.fp_ctrl.vec, _retry_queue_io_enq_bits_uop_T.fp_ctrl.vec connect retry_queue.io.enq.bits.uop.fp_ctrl.wflags, _retry_queue_io_enq_bits_uop_T.fp_ctrl.wflags connect retry_queue.io.enq.bits.uop.fp_ctrl.sqrt, _retry_queue_io_enq_bits_uop_T.fp_ctrl.sqrt connect retry_queue.io.enq.bits.uop.fp_ctrl.div, _retry_queue_io_enq_bits_uop_T.fp_ctrl.div connect retry_queue.io.enq.bits.uop.fp_ctrl.fma, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fma connect retry_queue.io.enq.bits.uop.fp_ctrl.fastpipe, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fastpipe connect retry_queue.io.enq.bits.uop.fp_ctrl.toint, _retry_queue_io_enq_bits_uop_T.fp_ctrl.toint connect retry_queue.io.enq.bits.uop.fp_ctrl.fromint, _retry_queue_io_enq_bits_uop_T.fp_ctrl.fromint connect retry_queue.io.enq.bits.uop.fp_ctrl.typeTagOut, _retry_queue_io_enq_bits_uop_T.fp_ctrl.typeTagOut connect retry_queue.io.enq.bits.uop.fp_ctrl.typeTagIn, _retry_queue_io_enq_bits_uop_T.fp_ctrl.typeTagIn connect retry_queue.io.enq.bits.uop.fp_ctrl.swap23, _retry_queue_io_enq_bits_uop_T.fp_ctrl.swap23 connect retry_queue.io.enq.bits.uop.fp_ctrl.swap12, _retry_queue_io_enq_bits_uop_T.fp_ctrl.swap12 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren3, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren3 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren2, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren2 connect retry_queue.io.enq.bits.uop.fp_ctrl.ren1, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ren1 connect retry_queue.io.enq.bits.uop.fp_ctrl.wen, _retry_queue_io_enq_bits_uop_T.fp_ctrl.wen connect retry_queue.io.enq.bits.uop.fp_ctrl.ldst, _retry_queue_io_enq_bits_uop_T.fp_ctrl.ldst connect retry_queue.io.enq.bits.uop.op2_sel, _retry_queue_io_enq_bits_uop_T.op2_sel connect retry_queue.io.enq.bits.uop.op1_sel, _retry_queue_io_enq_bits_uop_T.op1_sel connect retry_queue.io.enq.bits.uop.imm_packed, _retry_queue_io_enq_bits_uop_T.imm_packed connect retry_queue.io.enq.bits.uop.pimm, _retry_queue_io_enq_bits_uop_T.pimm connect retry_queue.io.enq.bits.uop.imm_sel, _retry_queue_io_enq_bits_uop_T.imm_sel connect retry_queue.io.enq.bits.uop.imm_rename, _retry_queue_io_enq_bits_uop_T.imm_rename connect retry_queue.io.enq.bits.uop.taken, _retry_queue_io_enq_bits_uop_T.taken connect retry_queue.io.enq.bits.uop.pc_lob, _retry_queue_io_enq_bits_uop_T.pc_lob connect retry_queue.io.enq.bits.uop.edge_inst, _retry_queue_io_enq_bits_uop_T.edge_inst connect retry_queue.io.enq.bits.uop.ftq_idx, _retry_queue_io_enq_bits_uop_T.ftq_idx connect retry_queue.io.enq.bits.uop.is_mov, _retry_queue_io_enq_bits_uop_T.is_mov connect retry_queue.io.enq.bits.uop.is_rocc, _retry_queue_io_enq_bits_uop_T.is_rocc connect retry_queue.io.enq.bits.uop.is_sys_pc2epc, _retry_queue_io_enq_bits_uop_T.is_sys_pc2epc connect retry_queue.io.enq.bits.uop.is_eret, _retry_queue_io_enq_bits_uop_T.is_eret connect retry_queue.io.enq.bits.uop.is_amo, _retry_queue_io_enq_bits_uop_T.is_amo connect retry_queue.io.enq.bits.uop.is_sfence, _retry_queue_io_enq_bits_uop_T.is_sfence connect retry_queue.io.enq.bits.uop.is_fencei, _retry_queue_io_enq_bits_uop_T.is_fencei connect retry_queue.io.enq.bits.uop.is_fence, _retry_queue_io_enq_bits_uop_T.is_fence connect retry_queue.io.enq.bits.uop.is_sfb, _retry_queue_io_enq_bits_uop_T.is_sfb connect retry_queue.io.enq.bits.uop.br_type, _retry_queue_io_enq_bits_uop_T.br_type connect retry_queue.io.enq.bits.uop.br_tag, _retry_queue_io_enq_bits_uop_T.br_tag connect retry_queue.io.enq.bits.uop.br_mask, _retry_queue_io_enq_bits_uop_T.br_mask connect retry_queue.io.enq.bits.uop.dis_col_sel, _retry_queue_io_enq_bits_uop_T.dis_col_sel connect retry_queue.io.enq.bits.uop.iw_p3_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p3_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p2_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p2_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p1_bypass_hint, _retry_queue_io_enq_bits_uop_T.iw_p1_bypass_hint connect retry_queue.io.enq.bits.uop.iw_p2_speculative_child, _retry_queue_io_enq_bits_uop_T.iw_p2_speculative_child connect retry_queue.io.enq.bits.uop.iw_p1_speculative_child, _retry_queue_io_enq_bits_uop_T.iw_p1_speculative_child connect retry_queue.io.enq.bits.uop.iw_issued_partial_dgen, _retry_queue_io_enq_bits_uop_T.iw_issued_partial_dgen connect retry_queue.io.enq.bits.uop.iw_issued_partial_agen, _retry_queue_io_enq_bits_uop_T.iw_issued_partial_agen connect retry_queue.io.enq.bits.uop.iw_issued, _retry_queue_io_enq_bits_uop_T.iw_issued connect retry_queue.io.enq.bits.uop.fu_code[0], _retry_queue_io_enq_bits_uop_T.fu_code[0] connect retry_queue.io.enq.bits.uop.fu_code[1], _retry_queue_io_enq_bits_uop_T.fu_code[1] connect retry_queue.io.enq.bits.uop.fu_code[2], _retry_queue_io_enq_bits_uop_T.fu_code[2] connect retry_queue.io.enq.bits.uop.fu_code[3], _retry_queue_io_enq_bits_uop_T.fu_code[3] connect retry_queue.io.enq.bits.uop.fu_code[4], _retry_queue_io_enq_bits_uop_T.fu_code[4] connect retry_queue.io.enq.bits.uop.fu_code[5], _retry_queue_io_enq_bits_uop_T.fu_code[5] connect retry_queue.io.enq.bits.uop.fu_code[6], _retry_queue_io_enq_bits_uop_T.fu_code[6] connect retry_queue.io.enq.bits.uop.fu_code[7], _retry_queue_io_enq_bits_uop_T.fu_code[7] connect retry_queue.io.enq.bits.uop.fu_code[8], _retry_queue_io_enq_bits_uop_T.fu_code[8] connect retry_queue.io.enq.bits.uop.fu_code[9], _retry_queue_io_enq_bits_uop_T.fu_code[9] connect retry_queue.io.enq.bits.uop.iq_type[0], _retry_queue_io_enq_bits_uop_T.iq_type[0] connect retry_queue.io.enq.bits.uop.iq_type[1], _retry_queue_io_enq_bits_uop_T.iq_type[1] connect retry_queue.io.enq.bits.uop.iq_type[2], _retry_queue_io_enq_bits_uop_T.iq_type[2] connect retry_queue.io.enq.bits.uop.iq_type[3], _retry_queue_io_enq_bits_uop_T.iq_type[3] connect retry_queue.io.enq.bits.uop.debug_pc, _retry_queue_io_enq_bits_uop_T.debug_pc connect retry_queue.io.enq.bits.uop.is_rvc, _retry_queue_io_enq_bits_uop_T.is_rvc connect retry_queue.io.enq.bits.uop.debug_inst, _retry_queue_io_enq_bits_uop_T.debug_inst connect retry_queue.io.enq.bits.uop.inst, _retry_queue_io_enq_bits_uop_T.inst node _retry_queue_io_enq_bits_uop_uses_ldq_T = eq(can_enq_store_retry, UInt<1>(0h0)) node _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = and(can_enq_load_retry, _retry_queue_io_enq_bits_uop_uses_ldq_T) connect retry_queue.io.enq.bits.uop.uses_ldq, _retry_queue_io_enq_bits_uop_uses_ldq_T_1 connect retry_queue.io.enq.bits.uop.ldq_idx, ldq_enq_retry_idx connect retry_queue.io.enq.bits.uop.uses_stq, can_enq_store_retry connect retry_queue.io.enq.bits.uop.stq_idx, stq_enq_retry_idx node _T_141 = and(retry_queue.io.enq.ready, retry_queue.io.enq.valid) node _T_142 = and(can_enq_store_retry, _T_141) when _T_142 : connect stq_addr[stq_enq_retry_idx].valid, UInt<1>(0h0) else : node _T_143 = and(retry_queue.io.enq.ready, retry_queue.io.enq.valid) node _T_144 = and(can_enq_load_retry, _T_143) when _T_144 : connect ldq_addr[ldq_enq_retry_idx].valid, UInt<1>(0h0) node _retry_queue_io_deq_ready_T = or(will_fire_load_retry[0], will_fire_store_retry[0]) connect retry_queue.io.deq.ready, _retry_queue_io_deq_ready_T wire stq_execute_queue_flush : UInt<1> connect stq_execute_queue_flush, UInt<1>(0h0) node _T_145 = asUInt(reset) node _T_146 = or(_T_145, stq_execute_queue_flush) inst stq_execute_queue of Queue4_STQEntry connect stq_execute_queue.clock, clock connect stq_execute_queue.reset, _T_146 wire stq_enq_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_e_e.valid, stq_valid[stq_execute_head] connect stq_enq_e_e.bits.uop, stq_uop[stq_execute_head] connect stq_enq_e_e.bits.addr, stq_addr[stq_execute_head] connect stq_enq_e_e.bits.addr_is_virtual, stq_addr_is_virtual[stq_execute_head] connect stq_enq_e_e.bits.data, stq_data[stq_execute_head] connect stq_enq_e_e.bits.committed, stq_committed[stq_execute_head] connect stq_enq_e_e.bits.succeeded, stq_succeeded[stq_execute_head] connect stq_enq_e_e.bits.can_execute, stq_can_execute[stq_execute_head] connect stq_enq_e_e.bits.cleared, stq_cleared[stq_execute_head] connect stq_enq_e_e.bits.debug_wb_data, stq_debug_wb_data[stq_execute_head] wire stq_enq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect stq_enq_e, stq_enq_e_e connect stq_execute_queue.io.enq.bits.debug_wb_data, stq_enq_e.bits.debug_wb_data connect stq_execute_queue.io.enq.bits.cleared, stq_enq_e.bits.cleared connect stq_execute_queue.io.enq.bits.can_execute, stq_enq_e.bits.can_execute connect stq_execute_queue.io.enq.bits.succeeded, stq_enq_e.bits.succeeded connect stq_execute_queue.io.enq.bits.committed, stq_enq_e.bits.committed connect stq_execute_queue.io.enq.bits.data.bits, stq_enq_e.bits.data.bits connect stq_execute_queue.io.enq.bits.data.valid, stq_enq_e.bits.data.valid connect stq_execute_queue.io.enq.bits.addr_is_virtual, stq_enq_e.bits.addr_is_virtual connect stq_execute_queue.io.enq.bits.addr.bits, stq_enq_e.bits.addr.bits connect stq_execute_queue.io.enq.bits.addr.valid, stq_enq_e.bits.addr.valid connect stq_execute_queue.io.enq.bits.uop.debug_tsrc, stq_enq_e.bits.uop.debug_tsrc connect stq_execute_queue.io.enq.bits.uop.debug_fsrc, stq_enq_e.bits.uop.debug_fsrc connect stq_execute_queue.io.enq.bits.uop.bp_xcpt_if, stq_enq_e.bits.uop.bp_xcpt_if connect stq_execute_queue.io.enq.bits.uop.bp_debug_if, stq_enq_e.bits.uop.bp_debug_if connect stq_execute_queue.io.enq.bits.uop.xcpt_ma_if, stq_enq_e.bits.uop.xcpt_ma_if connect stq_execute_queue.io.enq.bits.uop.xcpt_ae_if, stq_enq_e.bits.uop.xcpt_ae_if connect stq_execute_queue.io.enq.bits.uop.xcpt_pf_if, stq_enq_e.bits.uop.xcpt_pf_if connect stq_execute_queue.io.enq.bits.uop.fp_typ, stq_enq_e.bits.uop.fp_typ connect stq_execute_queue.io.enq.bits.uop.fp_rm, stq_enq_e.bits.uop.fp_rm connect stq_execute_queue.io.enq.bits.uop.fp_val, stq_enq_e.bits.uop.fp_val connect stq_execute_queue.io.enq.bits.uop.fcn_op, stq_enq_e.bits.uop.fcn_op connect stq_execute_queue.io.enq.bits.uop.fcn_dw, stq_enq_e.bits.uop.fcn_dw connect stq_execute_queue.io.enq.bits.uop.frs3_en, stq_enq_e.bits.uop.frs3_en connect stq_execute_queue.io.enq.bits.uop.lrs2_rtype, stq_enq_e.bits.uop.lrs2_rtype connect stq_execute_queue.io.enq.bits.uop.lrs1_rtype, stq_enq_e.bits.uop.lrs1_rtype connect stq_execute_queue.io.enq.bits.uop.dst_rtype, stq_enq_e.bits.uop.dst_rtype connect stq_execute_queue.io.enq.bits.uop.lrs3, stq_enq_e.bits.uop.lrs3 connect stq_execute_queue.io.enq.bits.uop.lrs2, stq_enq_e.bits.uop.lrs2 connect stq_execute_queue.io.enq.bits.uop.lrs1, stq_enq_e.bits.uop.lrs1 connect stq_execute_queue.io.enq.bits.uop.ldst, stq_enq_e.bits.uop.ldst connect stq_execute_queue.io.enq.bits.uop.ldst_is_rs1, stq_enq_e.bits.uop.ldst_is_rs1 connect stq_execute_queue.io.enq.bits.uop.csr_cmd, stq_enq_e.bits.uop.csr_cmd connect stq_execute_queue.io.enq.bits.uop.flush_on_commit, stq_enq_e.bits.uop.flush_on_commit connect stq_execute_queue.io.enq.bits.uop.is_unique, stq_enq_e.bits.uop.is_unique connect stq_execute_queue.io.enq.bits.uop.uses_stq, stq_enq_e.bits.uop.uses_stq connect stq_execute_queue.io.enq.bits.uop.uses_ldq, stq_enq_e.bits.uop.uses_ldq connect stq_execute_queue.io.enq.bits.uop.mem_signed, stq_enq_e.bits.uop.mem_signed connect stq_execute_queue.io.enq.bits.uop.mem_size, stq_enq_e.bits.uop.mem_size connect stq_execute_queue.io.enq.bits.uop.mem_cmd, stq_enq_e.bits.uop.mem_cmd connect stq_execute_queue.io.enq.bits.uop.exc_cause, stq_enq_e.bits.uop.exc_cause connect stq_execute_queue.io.enq.bits.uop.exception, stq_enq_e.bits.uop.exception connect stq_execute_queue.io.enq.bits.uop.stale_pdst, stq_enq_e.bits.uop.stale_pdst connect stq_execute_queue.io.enq.bits.uop.ppred_busy, stq_enq_e.bits.uop.ppred_busy connect stq_execute_queue.io.enq.bits.uop.prs3_busy, stq_enq_e.bits.uop.prs3_busy connect stq_execute_queue.io.enq.bits.uop.prs2_busy, stq_enq_e.bits.uop.prs2_busy connect stq_execute_queue.io.enq.bits.uop.prs1_busy, stq_enq_e.bits.uop.prs1_busy connect stq_execute_queue.io.enq.bits.uop.ppred, stq_enq_e.bits.uop.ppred connect stq_execute_queue.io.enq.bits.uop.prs3, stq_enq_e.bits.uop.prs3 connect stq_execute_queue.io.enq.bits.uop.prs2, stq_enq_e.bits.uop.prs2 connect stq_execute_queue.io.enq.bits.uop.prs1, stq_enq_e.bits.uop.prs1 connect stq_execute_queue.io.enq.bits.uop.pdst, stq_enq_e.bits.uop.pdst connect stq_execute_queue.io.enq.bits.uop.rxq_idx, stq_enq_e.bits.uop.rxq_idx connect stq_execute_queue.io.enq.bits.uop.stq_idx, stq_enq_e.bits.uop.stq_idx connect stq_execute_queue.io.enq.bits.uop.ldq_idx, stq_enq_e.bits.uop.ldq_idx connect stq_execute_queue.io.enq.bits.uop.rob_idx, stq_enq_e.bits.uop.rob_idx connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.vec, stq_enq_e.bits.uop.fp_ctrl.vec connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.wflags, stq_enq_e.bits.uop.fp_ctrl.wflags connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.sqrt, stq_enq_e.bits.uop.fp_ctrl.sqrt connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.div, stq_enq_e.bits.uop.fp_ctrl.div connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fma, stq_enq_e.bits.uop.fp_ctrl.fma connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fastpipe, stq_enq_e.bits.uop.fp_ctrl.fastpipe connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.toint, stq_enq_e.bits.uop.fp_ctrl.toint connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.fromint, stq_enq_e.bits.uop.fp_ctrl.fromint connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.typeTagOut, stq_enq_e.bits.uop.fp_ctrl.typeTagOut connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.typeTagIn, stq_enq_e.bits.uop.fp_ctrl.typeTagIn connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.swap23, stq_enq_e.bits.uop.fp_ctrl.swap23 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.swap12, stq_enq_e.bits.uop.fp_ctrl.swap12 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren3, stq_enq_e.bits.uop.fp_ctrl.ren3 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren2, stq_enq_e.bits.uop.fp_ctrl.ren2 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ren1, stq_enq_e.bits.uop.fp_ctrl.ren1 connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.wen, stq_enq_e.bits.uop.fp_ctrl.wen connect stq_execute_queue.io.enq.bits.uop.fp_ctrl.ldst, stq_enq_e.bits.uop.fp_ctrl.ldst connect stq_execute_queue.io.enq.bits.uop.op2_sel, stq_enq_e.bits.uop.op2_sel connect stq_execute_queue.io.enq.bits.uop.op1_sel, stq_enq_e.bits.uop.op1_sel connect stq_execute_queue.io.enq.bits.uop.imm_packed, stq_enq_e.bits.uop.imm_packed connect stq_execute_queue.io.enq.bits.uop.pimm, stq_enq_e.bits.uop.pimm connect stq_execute_queue.io.enq.bits.uop.imm_sel, stq_enq_e.bits.uop.imm_sel connect stq_execute_queue.io.enq.bits.uop.imm_rename, stq_enq_e.bits.uop.imm_rename connect stq_execute_queue.io.enq.bits.uop.taken, stq_enq_e.bits.uop.taken connect stq_execute_queue.io.enq.bits.uop.pc_lob, stq_enq_e.bits.uop.pc_lob connect stq_execute_queue.io.enq.bits.uop.edge_inst, stq_enq_e.bits.uop.edge_inst connect stq_execute_queue.io.enq.bits.uop.ftq_idx, stq_enq_e.bits.uop.ftq_idx connect stq_execute_queue.io.enq.bits.uop.is_mov, stq_enq_e.bits.uop.is_mov connect stq_execute_queue.io.enq.bits.uop.is_rocc, stq_enq_e.bits.uop.is_rocc connect stq_execute_queue.io.enq.bits.uop.is_sys_pc2epc, stq_enq_e.bits.uop.is_sys_pc2epc connect stq_execute_queue.io.enq.bits.uop.is_eret, stq_enq_e.bits.uop.is_eret connect stq_execute_queue.io.enq.bits.uop.is_amo, stq_enq_e.bits.uop.is_amo connect stq_execute_queue.io.enq.bits.uop.is_sfence, stq_enq_e.bits.uop.is_sfence connect stq_execute_queue.io.enq.bits.uop.is_fencei, stq_enq_e.bits.uop.is_fencei connect stq_execute_queue.io.enq.bits.uop.is_fence, stq_enq_e.bits.uop.is_fence connect stq_execute_queue.io.enq.bits.uop.is_sfb, stq_enq_e.bits.uop.is_sfb connect stq_execute_queue.io.enq.bits.uop.br_type, stq_enq_e.bits.uop.br_type connect stq_execute_queue.io.enq.bits.uop.br_tag, stq_enq_e.bits.uop.br_tag connect stq_execute_queue.io.enq.bits.uop.br_mask, stq_enq_e.bits.uop.br_mask connect stq_execute_queue.io.enq.bits.uop.dis_col_sel, stq_enq_e.bits.uop.dis_col_sel connect stq_execute_queue.io.enq.bits.uop.iw_p3_bypass_hint, stq_enq_e.bits.uop.iw_p3_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p2_bypass_hint, stq_enq_e.bits.uop.iw_p2_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p1_bypass_hint, stq_enq_e.bits.uop.iw_p1_bypass_hint connect stq_execute_queue.io.enq.bits.uop.iw_p2_speculative_child, stq_enq_e.bits.uop.iw_p2_speculative_child connect stq_execute_queue.io.enq.bits.uop.iw_p1_speculative_child, stq_enq_e.bits.uop.iw_p1_speculative_child connect stq_execute_queue.io.enq.bits.uop.iw_issued_partial_dgen, stq_enq_e.bits.uop.iw_issued_partial_dgen connect stq_execute_queue.io.enq.bits.uop.iw_issued_partial_agen, stq_enq_e.bits.uop.iw_issued_partial_agen connect stq_execute_queue.io.enq.bits.uop.iw_issued, stq_enq_e.bits.uop.iw_issued connect stq_execute_queue.io.enq.bits.uop.fu_code[0], stq_enq_e.bits.uop.fu_code[0] connect stq_execute_queue.io.enq.bits.uop.fu_code[1], stq_enq_e.bits.uop.fu_code[1] connect stq_execute_queue.io.enq.bits.uop.fu_code[2], stq_enq_e.bits.uop.fu_code[2] connect stq_execute_queue.io.enq.bits.uop.fu_code[3], stq_enq_e.bits.uop.fu_code[3] connect stq_execute_queue.io.enq.bits.uop.fu_code[4], stq_enq_e.bits.uop.fu_code[4] connect stq_execute_queue.io.enq.bits.uop.fu_code[5], stq_enq_e.bits.uop.fu_code[5] connect stq_execute_queue.io.enq.bits.uop.fu_code[6], stq_enq_e.bits.uop.fu_code[6] connect stq_execute_queue.io.enq.bits.uop.fu_code[7], stq_enq_e.bits.uop.fu_code[7] connect stq_execute_queue.io.enq.bits.uop.fu_code[8], stq_enq_e.bits.uop.fu_code[8] connect stq_execute_queue.io.enq.bits.uop.fu_code[9], stq_enq_e.bits.uop.fu_code[9] connect stq_execute_queue.io.enq.bits.uop.iq_type[0], stq_enq_e.bits.uop.iq_type[0] connect stq_execute_queue.io.enq.bits.uop.iq_type[1], stq_enq_e.bits.uop.iq_type[1] connect stq_execute_queue.io.enq.bits.uop.iq_type[2], stq_enq_e.bits.uop.iq_type[2] connect stq_execute_queue.io.enq.bits.uop.iq_type[3], stq_enq_e.bits.uop.iq_type[3] connect stq_execute_queue.io.enq.bits.uop.debug_pc, stq_enq_e.bits.uop.debug_pc connect stq_execute_queue.io.enq.bits.uop.is_rvc, stq_enq_e.bits.uop.is_rvc connect stq_execute_queue.io.enq.bits.uop.debug_inst, stq_enq_e.bits.uop.debug_inst connect stq_execute_queue.io.enq.bits.uop.inst, stq_enq_e.bits.uop.inst connect stq_execute_queue.io.enq.bits.uop.stq_idx, stq_execute_head node _stq_execute_queue_io_deq_ready_T = or(will_fire_store_commit_fast[0], will_fire_store_commit_slow[0]) connect stq_execute_queue.io.deq.ready, _stq_execute_queue_io_deq_ready_T node _can_enq_store_execute_T = and(stq_enq_e.valid, stq_enq_e.bits.addr.valid) node _can_enq_store_execute_T_1 = and(_can_enq_store_execute_T, stq_enq_e.bits.data.valid) node _can_enq_store_execute_T_2 = eq(stq_enq_e.bits.addr_is_virtual, UInt<1>(0h0)) node _can_enq_store_execute_T_3 = and(_can_enq_store_execute_T_1, _can_enq_store_execute_T_2) node _can_enq_store_execute_T_4 = eq(stq_enq_e.bits.uop.exception, UInt<1>(0h0)) node _can_enq_store_execute_T_5 = and(_can_enq_store_execute_T_3, _can_enq_store_execute_T_4) node _can_enq_store_execute_T_6 = eq(stq_enq_e.bits.uop.is_fence, UInt<1>(0h0)) node _can_enq_store_execute_T_7 = and(_can_enq_store_execute_T_5, _can_enq_store_execute_T_6) node _can_enq_store_execute_T_8 = or(stq_enq_e.bits.committed, stq_enq_e.bits.uop.is_amo) node can_enq_store_execute = and(_can_enq_store_execute_T_7, _can_enq_store_execute_T_8) connect stq_execute_queue.io.enq.valid, can_enq_store_execute node _T_147 = and(stq_execute_queue.io.enq.ready, stq_execute_queue.io.enq.valid) node _T_148 = and(can_enq_store_execute, _T_147) when _T_148 : node stq_execute_head_wrap = eq(stq_execute_head, UInt<5>(0h17)) node _stq_execute_head_T = add(stq_execute_head, UInt<1>(0h1)) node _stq_execute_head_T_1 = tail(_stq_execute_head_T, 1) node _stq_execute_head_T_2 = mux(stq_execute_head_wrap, UInt<1>(0h0), _stq_execute_head_T_1) connect stq_execute_head, _stq_execute_head_T_2 node _can_fire_load_agen_exec_T = and(io.core.agen[0].valid, io.core.agen[0].bits.uop.uses_ldq) wire can_fire_load_agen_exec : UInt<1>[1] connect can_fire_load_agen_exec[0], _can_fire_load_agen_exec_T node _can_fire_store_agen_T = and(io.core.agen[0].valid, io.core.agen[0].bits.uop.uses_stq) wire can_fire_store_agen : UInt<1>[1] connect can_fire_store_agen[0], _can_fire_store_agen_T wire can_fire_sfence : UInt<1>[1] connect can_fire_sfence[0], io.core.sfence.valid node _can_fire_release_T = and(UInt<1>(0h1), io.dmem.release.valid) wire can_fire_release : UInt<1>[1] connect can_fire_release[0], _can_fire_release_T connect io.dmem.release.ready, will_fire_release[0] node _can_fire_load_retry_T = and(retry_queue.io.deq.valid, retry_queue.io.deq.bits.uop.uses_ldq) reg can_fire_load_retry_REG : UInt<1>, clock connect can_fire_load_retry_REG, store_needs_order node _can_fire_load_retry_T_1 = eq(can_fire_load_retry_REG, UInt<1>(0h0)) node _can_fire_load_retry_T_2 = and(_can_fire_load_retry_T, _can_fire_load_retry_T_1) node _can_fire_load_retry_T_3 = and(_can_fire_load_retry_T_2, UInt<1>(0h1)) wire can_fire_load_retry : UInt<1>[1] connect can_fire_load_retry[0], _can_fire_load_retry_T_3 node _can_fire_store_retry_T = and(retry_queue.io.deq.valid, retry_queue.io.deq.bits.uop.uses_stq) node _can_fire_store_retry_T_1 = and(_can_fire_store_retry_T, UInt<1>(0h1)) wire can_fire_store_retry : UInt<1>[1] connect can_fire_store_retry[0], _can_fire_store_retry_T_1 node _can_fire_store_commit_slow_T = eq(mem_xcpt_valid, UInt<1>(0h0)) node _can_fire_store_commit_slow_T_1 = and(stq_execute_queue.io.deq.valid, _can_fire_store_commit_slow_T) node _can_fire_store_commit_slow_T_2 = and(_can_fire_store_commit_slow_T_1, UInt<1>(0h1)) wire can_fire_store_commit_slow : UInt<1>[1] connect can_fire_store_commit_slow[0], _can_fire_store_commit_slow_T_2 node _can_fire_store_commit_fast_T = and(can_fire_store_commit_slow[0], stq_almost_full) wire can_fire_store_commit_fast : UInt<1>[1] connect can_fire_store_commit_fast[0], _can_fire_store_commit_fast_T wire block_load_wakeup : UInt<1> connect block_load_wakeup, UInt<1>(0h0) node _can_fire_load_wakeup_T = and(ldq_wakeup_e.valid, ldq_wakeup_e.bits.addr.valid) node _can_fire_load_wakeup_T_1 = eq(ldq_wakeup_e.bits.succeeded, UInt<1>(0h0)) node _can_fire_load_wakeup_T_2 = and(_can_fire_load_wakeup_T, _can_fire_load_wakeup_T_1) node _can_fire_load_wakeup_T_3 = eq(ldq_wakeup_e.bits.addr_is_virtual, UInt<1>(0h0)) node _can_fire_load_wakeup_T_4 = and(_can_fire_load_wakeup_T_2, _can_fire_load_wakeup_T_3) node _can_fire_load_wakeup_T_5 = eq(ldq_wakeup_e.bits.executed, UInt<1>(0h0)) node _can_fire_load_wakeup_T_6 = and(_can_fire_load_wakeup_T_4, _can_fire_load_wakeup_T_5) node _can_fire_load_wakeup_T_7 = eq(ldq_wakeup_e.bits.order_fail, UInt<1>(0h0)) node _can_fire_load_wakeup_T_8 = and(_can_fire_load_wakeup_T_6, _can_fire_load_wakeup_T_7) node _can_fire_load_wakeup_T_9 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _can_fire_load_wakeup_T_10 = bits(_can_fire_load_wakeup_T_9, 4, 0) node _can_fire_load_wakeup_T_11 = eq(p1_block_load_mask[_can_fire_load_wakeup_T_10], UInt<1>(0h0)) node _can_fire_load_wakeup_T_12 = and(_can_fire_load_wakeup_T_8, _can_fire_load_wakeup_T_11) node _can_fire_load_wakeup_T_13 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _can_fire_load_wakeup_T_14 = bits(_can_fire_load_wakeup_T_13, 4, 0) node _can_fire_load_wakeup_T_15 = eq(p2_block_load_mask[_can_fire_load_wakeup_T_14], UInt<1>(0h0)) node _can_fire_load_wakeup_T_16 = and(_can_fire_load_wakeup_T_12, _can_fire_load_wakeup_T_15) reg can_fire_load_wakeup_REG : UInt<1>, clock connect can_fire_load_wakeup_REG, store_needs_order node _can_fire_load_wakeup_T_17 = eq(can_fire_load_wakeup_REG, UInt<1>(0h0)) node _can_fire_load_wakeup_T_18 = and(_can_fire_load_wakeup_T_16, _can_fire_load_wakeup_T_17) node _can_fire_load_wakeup_T_19 = eq(block_load_wakeup, UInt<1>(0h0)) node _can_fire_load_wakeup_T_20 = and(_can_fire_load_wakeup_T_18, _can_fire_load_wakeup_T_19) node _can_fire_load_wakeup_T_21 = and(_can_fire_load_wakeup_T_20, UInt<1>(0h1)) node _can_fire_load_wakeup_T_22 = eq(ldq_wakeup_e.bits.addr_is_uncacheable, UInt<1>(0h0)) node _can_fire_load_wakeup_T_23 = eq(ldq_head, ldq_wakeup_idx) node _can_fire_load_wakeup_T_24 = and(io.core.commit_load_at_rob_head, _can_fire_load_wakeup_T_23) node _can_fire_load_wakeup_T_25 = eq(ldq_wakeup_e.bits.st_dep_mask, UInt<1>(0h0)) node _can_fire_load_wakeup_T_26 = and(_can_fire_load_wakeup_T_24, _can_fire_load_wakeup_T_25) node _can_fire_load_wakeup_T_27 = or(_can_fire_load_wakeup_T_22, _can_fire_load_wakeup_T_26) node _can_fire_load_wakeup_T_28 = and(_can_fire_load_wakeup_T_21, _can_fire_load_wakeup_T_27) wire can_fire_load_wakeup : UInt<1>[1] connect can_fire_load_wakeup[0], _can_fire_load_wakeup_T_28 wire _can_fire_hella_incoming_WIRE : UInt<1>[1] connect _can_fire_hella_incoming_WIRE[0], UInt<1>(0h0) wire can_fire_hella_incoming : UInt<1>[1] connect can_fire_hella_incoming, _can_fire_hella_incoming_WIRE wire _can_fire_hella_wakeup_WIRE : UInt<1>[1] connect _can_fire_hella_wakeup_WIRE[0], UInt<1>(0h0) wire can_fire_hella_wakeup : UInt<1>[1] connect can_fire_hella_wakeup, _can_fire_hella_wakeup_WIRE wire exe_tlb_valid : UInt<1>[1] node _will_fire_sfence_0_will_fire_T = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_sfence_0_will_fire_T) node _will_fire_sfence_0_will_fire_T_2 = eq(_will_fire_sfence_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_3 = and(can_fire_sfence[0], _will_fire_sfence_0_will_fire_T_2) node _will_fire_sfence_0_will_fire_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_4) node _will_fire_sfence_0_will_fire_T_6 = eq(_will_fire_sfence_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_7 = and(_will_fire_sfence_0_will_fire_T_3, _will_fire_sfence_0_will_fire_T_6) node _will_fire_sfence_0_will_fire_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _will_fire_sfence_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_sfence_0_will_fire_T_8) node _will_fire_sfence_0_will_fire_T_10 = eq(_will_fire_sfence_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_sfence_0_will_fire = and(_will_fire_sfence_0_will_fire_T_7, _will_fire_sfence_0_will_fire_T_10) node _will_fire_sfence_0_T = and(will_fire_sfence_0_will_fire, UInt<1>(0h1)) node _will_fire_sfence_0_T_1 = eq(_will_fire_sfence_0_T, UInt<1>(0h0)) node _will_fire_sfence_0_T_2 = and(UInt<1>(0h1), _will_fire_sfence_0_T_1) node _will_fire_sfence_0_T_3 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0)) node _will_fire_sfence_0_T_4 = eq(_will_fire_sfence_0_T_3, UInt<1>(0h0)) node _will_fire_sfence_0_T_5 = and(UInt<1>(0h1), _will_fire_sfence_0_T_4) node _will_fire_sfence_0_T_6 = and(will_fire_sfence_0_will_fire, UInt<1>(0h0)) node _will_fire_sfence_0_T_7 = eq(_will_fire_sfence_0_T_6, UInt<1>(0h0)) node _will_fire_sfence_0_T_8 = and(UInt<1>(0h1), _will_fire_sfence_0_T_7) connect will_fire_sfence[0], will_fire_sfence_0_will_fire node _will_fire_store_commit_fast_0_will_fire_T = eq(_will_fire_sfence_0_T_2, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_store_commit_fast_0_will_fire_T) node _will_fire_store_commit_fast_0_will_fire_T_2 = eq(_will_fire_store_commit_fast_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_3 = and(can_fire_store_commit_fast[0], _will_fire_store_commit_fast_0_will_fire_T_2) node _will_fire_store_commit_fast_0_will_fire_T_4 = eq(_will_fire_sfence_0_T_5, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_store_commit_fast_0_will_fire_T_4) node _will_fire_store_commit_fast_0_will_fire_T_6 = eq(_will_fire_store_commit_fast_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_7 = and(_will_fire_store_commit_fast_0_will_fire_T_3, _will_fire_store_commit_fast_0_will_fire_T_6) node _will_fire_store_commit_fast_0_will_fire_T_8 = eq(_will_fire_sfence_0_T_8, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_store_commit_fast_0_will_fire_T_8) node _will_fire_store_commit_fast_0_will_fire_T_10 = eq(_will_fire_store_commit_fast_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_commit_fast_0_will_fire = and(_will_fire_store_commit_fast_0_will_fire_T_7, _will_fire_store_commit_fast_0_will_fire_T_10) node _will_fire_store_commit_fast_0_T = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_1 = eq(_will_fire_store_commit_fast_0_T, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_2 = and(_will_fire_sfence_0_T_2, _will_fire_store_commit_fast_0_T_1) node _will_fire_store_commit_fast_0_T_3 = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_4 = eq(_will_fire_store_commit_fast_0_T_3, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_5 = and(_will_fire_sfence_0_T_5, _will_fire_store_commit_fast_0_T_4) node _will_fire_store_commit_fast_0_T_6 = and(will_fire_store_commit_fast_0_will_fire, UInt<1>(0h1)) node _will_fire_store_commit_fast_0_T_7 = eq(_will_fire_store_commit_fast_0_T_6, UInt<1>(0h0)) node _will_fire_store_commit_fast_0_T_8 = and(_will_fire_sfence_0_T_8, _will_fire_store_commit_fast_0_T_7) connect will_fire_store_commit_fast[0], will_fire_store_commit_fast_0_will_fire node _will_fire_load_agen_exec_0_will_fire_T = eq(_will_fire_store_commit_fast_0_T_2, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T) node _will_fire_load_agen_exec_0_will_fire_T_2 = eq(_will_fire_load_agen_exec_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_3 = and(can_fire_load_agen_exec[0], _will_fire_load_agen_exec_0_will_fire_T_2) node _will_fire_load_agen_exec_0_will_fire_T_4 = eq(_will_fire_store_commit_fast_0_T_5, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T_4) node _will_fire_load_agen_exec_0_will_fire_T_6 = eq(_will_fire_load_agen_exec_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_7 = and(_will_fire_load_agen_exec_0_will_fire_T_3, _will_fire_load_agen_exec_0_will_fire_T_6) node _will_fire_load_agen_exec_0_will_fire_T_8 = eq(_will_fire_store_commit_fast_0_T_8, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_agen_exec_0_will_fire_T_8) node _will_fire_load_agen_exec_0_will_fire_T_10 = eq(_will_fire_load_agen_exec_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_agen_exec_0_will_fire = and(_will_fire_load_agen_exec_0_will_fire_T_7, _will_fire_load_agen_exec_0_will_fire_T_10) node _will_fire_load_agen_exec_0_T = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_1 = eq(_will_fire_load_agen_exec_0_T, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_2 = and(_will_fire_store_commit_fast_0_T_2, _will_fire_load_agen_exec_0_T_1) node _will_fire_load_agen_exec_0_T_3 = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_4 = eq(_will_fire_load_agen_exec_0_T_3, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_5 = and(_will_fire_store_commit_fast_0_T_5, _will_fire_load_agen_exec_0_T_4) node _will_fire_load_agen_exec_0_T_6 = and(will_fire_load_agen_exec_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_exec_0_T_7 = eq(_will_fire_load_agen_exec_0_T_6, UInt<1>(0h0)) node _will_fire_load_agen_exec_0_T_8 = and(_will_fire_store_commit_fast_0_T_8, _will_fire_load_agen_exec_0_T_7) connect will_fire_load_agen_exec[0], will_fire_load_agen_exec_0_will_fire node _will_fire_load_agen_0_will_fire_T = eq(_will_fire_load_agen_exec_0_T_2, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_agen_0_will_fire_T) node _will_fire_load_agen_0_will_fire_T_2 = eq(_will_fire_load_agen_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_3 = and(can_fire_load_agen_exec[0], _will_fire_load_agen_0_will_fire_T_2) node _will_fire_load_agen_0_will_fire_T_4 = eq(_will_fire_load_agen_exec_0_T_5, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_agen_0_will_fire_T_4) node _will_fire_load_agen_0_will_fire_T_6 = eq(_will_fire_load_agen_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_7 = and(_will_fire_load_agen_0_will_fire_T_3, _will_fire_load_agen_0_will_fire_T_6) node _will_fire_load_agen_0_will_fire_T_8 = eq(_will_fire_load_agen_exec_0_T_8, UInt<1>(0h0)) node _will_fire_load_agen_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_load_agen_0_will_fire_T_8) node _will_fire_load_agen_0_will_fire_T_10 = eq(_will_fire_load_agen_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_agen_0_will_fire = and(_will_fire_load_agen_0_will_fire_T_7, _will_fire_load_agen_0_will_fire_T_10) node _will_fire_load_agen_0_T = and(will_fire_load_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_0_T_1 = eq(_will_fire_load_agen_0_T, UInt<1>(0h0)) node _will_fire_load_agen_0_T_2 = and(_will_fire_load_agen_exec_0_T_2, _will_fire_load_agen_0_T_1) node _will_fire_load_agen_0_T_3 = and(will_fire_load_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_load_agen_0_T_4 = eq(_will_fire_load_agen_0_T_3, UInt<1>(0h0)) node _will_fire_load_agen_0_T_5 = and(_will_fire_load_agen_exec_0_T_5, _will_fire_load_agen_0_T_4) node _will_fire_load_agen_0_T_6 = and(will_fire_load_agen_0_will_fire, UInt<1>(0h0)) node _will_fire_load_agen_0_T_7 = eq(_will_fire_load_agen_0_T_6, UInt<1>(0h0)) node _will_fire_load_agen_0_T_8 = and(_will_fire_load_agen_exec_0_T_8, _will_fire_load_agen_0_T_7) connect will_fire_load_agen[0], will_fire_load_agen_0_will_fire node _will_fire_store_agen_0_will_fire_T = eq(_will_fire_load_agen_0_T_2, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_store_agen_0_will_fire_T) node _will_fire_store_agen_0_will_fire_T_2 = eq(_will_fire_store_agen_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_3 = and(can_fire_store_agen[0], _will_fire_store_agen_0_will_fire_T_2) node _will_fire_store_agen_0_will_fire_T_4 = eq(_will_fire_load_agen_0_T_5, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_store_agen_0_will_fire_T_4) node _will_fire_store_agen_0_will_fire_T_6 = eq(_will_fire_store_agen_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_7 = and(_will_fire_store_agen_0_will_fire_T_3, _will_fire_store_agen_0_will_fire_T_6) node _will_fire_store_agen_0_will_fire_T_8 = eq(_will_fire_load_agen_0_T_8, UInt<1>(0h0)) node _will_fire_store_agen_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_store_agen_0_will_fire_T_8) node _will_fire_store_agen_0_will_fire_T_10 = eq(_will_fire_store_agen_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_agen_0_will_fire = and(_will_fire_store_agen_0_will_fire_T_7, _will_fire_store_agen_0_will_fire_T_10) node _will_fire_store_agen_0_T = and(will_fire_store_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_store_agen_0_T_1 = eq(_will_fire_store_agen_0_T, UInt<1>(0h0)) node _will_fire_store_agen_0_T_2 = and(_will_fire_load_agen_0_T_2, _will_fire_store_agen_0_T_1) node _will_fire_store_agen_0_T_3 = and(will_fire_store_agen_0_will_fire, UInt<1>(0h1)) node _will_fire_store_agen_0_T_4 = eq(_will_fire_store_agen_0_T_3, UInt<1>(0h0)) node _will_fire_store_agen_0_T_5 = and(_will_fire_load_agen_0_T_5, _will_fire_store_agen_0_T_4) node _will_fire_store_agen_0_T_6 = and(will_fire_store_agen_0_will_fire, UInt<1>(0h0)) node _will_fire_store_agen_0_T_7 = eq(_will_fire_store_agen_0_T_6, UInt<1>(0h0)) node _will_fire_store_agen_0_T_8 = and(_will_fire_load_agen_0_T_8, _will_fire_store_agen_0_T_7) connect will_fire_store_agen[0], will_fire_store_agen_0_will_fire node _will_fire_release_0_will_fire_T = eq(_will_fire_store_agen_0_T_2, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T) node _will_fire_release_0_will_fire_T_2 = eq(_will_fire_release_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_3 = and(can_fire_release[0], _will_fire_release_0_will_fire_T_2) node _will_fire_release_0_will_fire_T_4 = eq(_will_fire_store_agen_0_T_5, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_release_0_will_fire_T_4) node _will_fire_release_0_will_fire_T_6 = eq(_will_fire_release_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_7 = and(_will_fire_release_0_will_fire_T_3, _will_fire_release_0_will_fire_T_6) node _will_fire_release_0_will_fire_T_8 = eq(_will_fire_store_agen_0_T_8, UInt<1>(0h0)) node _will_fire_release_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_release_0_will_fire_T_8) node _will_fire_release_0_will_fire_T_10 = eq(_will_fire_release_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_release_0_will_fire = and(_will_fire_release_0_will_fire_T_7, _will_fire_release_0_will_fire_T_10) node _will_fire_release_0_T = and(will_fire_release_0_will_fire, UInt<1>(0h0)) node _will_fire_release_0_T_1 = eq(_will_fire_release_0_T, UInt<1>(0h0)) node _will_fire_release_0_T_2 = and(_will_fire_store_agen_0_T_2, _will_fire_release_0_T_1) node _will_fire_release_0_T_3 = and(will_fire_release_0_will_fire, UInt<1>(0h1)) node _will_fire_release_0_T_4 = eq(_will_fire_release_0_T_3, UInt<1>(0h0)) node _will_fire_release_0_T_5 = and(_will_fire_store_agen_0_T_5, _will_fire_release_0_T_4) node _will_fire_release_0_T_6 = and(will_fire_release_0_will_fire, UInt<1>(0h0)) node _will_fire_release_0_T_7 = eq(_will_fire_release_0_T_6, UInt<1>(0h0)) node _will_fire_release_0_T_8 = and(_will_fire_store_agen_0_T_8, _will_fire_release_0_T_7) connect will_fire_release[0], will_fire_release_0_will_fire node _will_fire_hella_incoming_0_will_fire_T = eq(_will_fire_release_0_T_2, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T) node _will_fire_hella_incoming_0_will_fire_T_2 = eq(_will_fire_hella_incoming_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_3 = and(can_fire_hella_incoming[0], _will_fire_hella_incoming_0_will_fire_T_2) node _will_fire_hella_incoming_0_will_fire_T_4 = eq(_will_fire_release_0_T_5, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_incoming_0_will_fire_T_4) node _will_fire_hella_incoming_0_will_fire_T_6 = eq(_will_fire_hella_incoming_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_7 = and(_will_fire_hella_incoming_0_will_fire_T_3, _will_fire_hella_incoming_0_will_fire_T_6) node _will_fire_hella_incoming_0_will_fire_T_8 = eq(_will_fire_release_0_T_8, UInt<1>(0h0)) node _will_fire_hella_incoming_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_incoming_0_will_fire_T_8) node _will_fire_hella_incoming_0_will_fire_T_10 = eq(_will_fire_hella_incoming_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_hella_incoming_0_will_fire = and(_will_fire_hella_incoming_0_will_fire_T_7, _will_fire_hella_incoming_0_will_fire_T_10) node _will_fire_hella_incoming_0_T = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_incoming_0_T_1 = eq(_will_fire_hella_incoming_0_T, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_2 = and(_will_fire_release_0_T_2, _will_fire_hella_incoming_0_T_1) node _will_fire_hella_incoming_0_T_3 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_4 = eq(_will_fire_hella_incoming_0_T_3, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_5 = and(_will_fire_release_0_T_5, _will_fire_hella_incoming_0_T_4) node _will_fire_hella_incoming_0_T_6 = and(will_fire_hella_incoming_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_incoming_0_T_7 = eq(_will_fire_hella_incoming_0_T_6, UInt<1>(0h0)) node _will_fire_hella_incoming_0_T_8 = and(_will_fire_release_0_T_8, _will_fire_hella_incoming_0_T_7) connect will_fire_hella_incoming[0], will_fire_hella_incoming_0_will_fire node _will_fire_hella_wakeup_0_will_fire_T = eq(_will_fire_hella_incoming_0_T_2, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T) node _will_fire_hella_wakeup_0_will_fire_T_2 = eq(_will_fire_hella_wakeup_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_3 = and(can_fire_hella_wakeup[0], _will_fire_hella_wakeup_0_will_fire_T_2) node _will_fire_hella_wakeup_0_will_fire_T_4 = eq(_will_fire_hella_incoming_0_T_5, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_hella_wakeup_0_will_fire_T_4) node _will_fire_hella_wakeup_0_will_fire_T_6 = eq(_will_fire_hella_wakeup_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_7 = and(_will_fire_hella_wakeup_0_will_fire_T_3, _will_fire_hella_wakeup_0_will_fire_T_6) node _will_fire_hella_wakeup_0_will_fire_T_8 = eq(_will_fire_hella_incoming_0_T_8, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_hella_wakeup_0_will_fire_T_8) node _will_fire_hella_wakeup_0_will_fire_T_10 = eq(_will_fire_hella_wakeup_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_hella_wakeup_0_will_fire = and(_will_fire_hella_wakeup_0_will_fire_T_7, _will_fire_hella_wakeup_0_will_fire_T_10) node _will_fire_hella_wakeup_0_T = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_1 = eq(_will_fire_hella_wakeup_0_T, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_2 = and(_will_fire_hella_incoming_0_T_2, _will_fire_hella_wakeup_0_T_1) node _will_fire_hella_wakeup_0_T_3 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_4 = eq(_will_fire_hella_wakeup_0_T_3, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_5 = and(_will_fire_hella_incoming_0_T_5, _will_fire_hella_wakeup_0_T_4) node _will_fire_hella_wakeup_0_T_6 = and(will_fire_hella_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_hella_wakeup_0_T_7 = eq(_will_fire_hella_wakeup_0_T_6, UInt<1>(0h0)) node _will_fire_hella_wakeup_0_T_8 = and(_will_fire_hella_incoming_0_T_8, _will_fire_hella_wakeup_0_T_7) connect will_fire_hella_wakeup[0], will_fire_hella_wakeup_0_will_fire node _will_fire_store_retry_0_will_fire_T = eq(_will_fire_hella_wakeup_0_T_2, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_store_retry_0_will_fire_T) node _will_fire_store_retry_0_will_fire_T_2 = eq(_will_fire_store_retry_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_3 = and(can_fire_store_retry[0], _will_fire_store_retry_0_will_fire_T_2) node _will_fire_store_retry_0_will_fire_T_4 = eq(_will_fire_hella_wakeup_0_T_5, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_store_retry_0_will_fire_T_4) node _will_fire_store_retry_0_will_fire_T_6 = eq(_will_fire_store_retry_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_7 = and(_will_fire_store_retry_0_will_fire_T_3, _will_fire_store_retry_0_will_fire_T_6) node _will_fire_store_retry_0_will_fire_T_8 = eq(_will_fire_hella_wakeup_0_T_8, UInt<1>(0h0)) node _will_fire_store_retry_0_will_fire_T_9 = and(UInt<1>(0h0), _will_fire_store_retry_0_will_fire_T_8) node _will_fire_store_retry_0_will_fire_T_10 = eq(_will_fire_store_retry_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_retry_0_will_fire = and(_will_fire_store_retry_0_will_fire_T_7, _will_fire_store_retry_0_will_fire_T_10) node _will_fire_store_retry_0_T = and(will_fire_store_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_store_retry_0_T_1 = eq(_will_fire_store_retry_0_T, UInt<1>(0h0)) node _will_fire_store_retry_0_T_2 = and(_will_fire_hella_wakeup_0_T_2, _will_fire_store_retry_0_T_1) node _will_fire_store_retry_0_T_3 = and(will_fire_store_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_store_retry_0_T_4 = eq(_will_fire_store_retry_0_T_3, UInt<1>(0h0)) node _will_fire_store_retry_0_T_5 = and(_will_fire_hella_wakeup_0_T_5, _will_fire_store_retry_0_T_4) node _will_fire_store_retry_0_T_6 = and(will_fire_store_retry_0_will_fire, UInt<1>(0h0)) node _will_fire_store_retry_0_T_7 = eq(_will_fire_store_retry_0_T_6, UInt<1>(0h0)) node _will_fire_store_retry_0_T_8 = and(_will_fire_hella_wakeup_0_T_8, _will_fire_store_retry_0_T_7) connect will_fire_store_retry[0], will_fire_store_retry_0_will_fire node _will_fire_load_retry_0_will_fire_T = eq(_will_fire_store_retry_0_T_2, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_1 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T) node _will_fire_load_retry_0_will_fire_T_2 = eq(_will_fire_load_retry_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_3 = and(can_fire_load_retry[0], _will_fire_load_retry_0_will_fire_T_2) node _will_fire_load_retry_0_will_fire_T_4 = eq(_will_fire_store_retry_0_T_5, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_4) node _will_fire_load_retry_0_will_fire_T_6 = eq(_will_fire_load_retry_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_7 = and(_will_fire_load_retry_0_will_fire_T_3, _will_fire_load_retry_0_will_fire_T_6) node _will_fire_load_retry_0_will_fire_T_8 = eq(_will_fire_store_retry_0_T_8, UInt<1>(0h0)) node _will_fire_load_retry_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_retry_0_will_fire_T_8) node _will_fire_load_retry_0_will_fire_T_10 = eq(_will_fire_load_retry_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_retry_0_will_fire = and(_will_fire_load_retry_0_will_fire_T_7, _will_fire_load_retry_0_will_fire_T_10) node _will_fire_load_retry_0_T = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_1 = eq(_will_fire_load_retry_0_T, UInt<1>(0h0)) node _will_fire_load_retry_0_T_2 = and(_will_fire_store_retry_0_T_2, _will_fire_load_retry_0_T_1) node _will_fire_load_retry_0_T_3 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_4 = eq(_will_fire_load_retry_0_T_3, UInt<1>(0h0)) node _will_fire_load_retry_0_T_5 = and(_will_fire_store_retry_0_T_5, _will_fire_load_retry_0_T_4) node _will_fire_load_retry_0_T_6 = and(will_fire_load_retry_0_will_fire, UInt<1>(0h1)) node _will_fire_load_retry_0_T_7 = eq(_will_fire_load_retry_0_T_6, UInt<1>(0h0)) node _will_fire_load_retry_0_T_8 = and(_will_fire_store_retry_0_T_8, _will_fire_load_retry_0_T_7) connect will_fire_load_retry[0], will_fire_load_retry_0_will_fire node _will_fire_load_wakeup_0_will_fire_T = eq(_will_fire_load_retry_0_T_2, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_load_wakeup_0_will_fire_T) node _will_fire_load_wakeup_0_will_fire_T_2 = eq(_will_fire_load_wakeup_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_3 = and(can_fire_load_wakeup[0], _will_fire_load_wakeup_0_will_fire_T_2) node _will_fire_load_wakeup_0_will_fire_T_4 = eq(_will_fire_load_retry_0_T_5, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_5 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_4) node _will_fire_load_wakeup_0_will_fire_T_6 = eq(_will_fire_load_wakeup_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_7 = and(_will_fire_load_wakeup_0_will_fire_T_3, _will_fire_load_wakeup_0_will_fire_T_6) node _will_fire_load_wakeup_0_will_fire_T_8 = eq(_will_fire_load_retry_0_T_8, UInt<1>(0h0)) node _will_fire_load_wakeup_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_load_wakeup_0_will_fire_T_8) node _will_fire_load_wakeup_0_will_fire_T_10 = eq(_will_fire_load_wakeup_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_load_wakeup_0_will_fire = and(_will_fire_load_wakeup_0_will_fire_T_7, _will_fire_load_wakeup_0_will_fire_T_10) node _will_fire_load_wakeup_0_T = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_1 = eq(_will_fire_load_wakeup_0_T, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_2 = and(_will_fire_load_retry_0_T_2, _will_fire_load_wakeup_0_T_1) node _will_fire_load_wakeup_0_T_3 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_load_wakeup_0_T_4 = eq(_will_fire_load_wakeup_0_T_3, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_5 = and(_will_fire_load_retry_0_T_5, _will_fire_load_wakeup_0_T_4) node _will_fire_load_wakeup_0_T_6 = and(will_fire_load_wakeup_0_will_fire, UInt<1>(0h1)) node _will_fire_load_wakeup_0_T_7 = eq(_will_fire_load_wakeup_0_T_6, UInt<1>(0h0)) node _will_fire_load_wakeup_0_T_8 = and(_will_fire_load_retry_0_T_8, _will_fire_load_wakeup_0_T_7) connect will_fire_load_wakeup[0], will_fire_load_wakeup_0_will_fire node _will_fire_store_commit_slow_0_will_fire_T = eq(_will_fire_load_wakeup_0_T_2, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_1 = and(UInt<1>(0h0), _will_fire_store_commit_slow_0_will_fire_T) node _will_fire_store_commit_slow_0_will_fire_T_2 = eq(_will_fire_store_commit_slow_0_will_fire_T_1, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_3 = and(can_fire_store_commit_slow[0], _will_fire_store_commit_slow_0_will_fire_T_2) node _will_fire_store_commit_slow_0_will_fire_T_4 = eq(_will_fire_load_wakeup_0_T_5, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_5 = and(UInt<1>(0h0), _will_fire_store_commit_slow_0_will_fire_T_4) node _will_fire_store_commit_slow_0_will_fire_T_6 = eq(_will_fire_store_commit_slow_0_will_fire_T_5, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_7 = and(_will_fire_store_commit_slow_0_will_fire_T_3, _will_fire_store_commit_slow_0_will_fire_T_6) node _will_fire_store_commit_slow_0_will_fire_T_8 = eq(_will_fire_load_wakeup_0_T_8, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_will_fire_T_9 = and(UInt<1>(0h1), _will_fire_store_commit_slow_0_will_fire_T_8) node _will_fire_store_commit_slow_0_will_fire_T_10 = eq(_will_fire_store_commit_slow_0_will_fire_T_9, UInt<1>(0h0)) node will_fire_store_commit_slow_0_will_fire = and(_will_fire_store_commit_slow_0_will_fire_T_7, _will_fire_store_commit_slow_0_will_fire_T_10) node _will_fire_store_commit_slow_0_T = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_1 = eq(_will_fire_store_commit_slow_0_T, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_2 = and(_will_fire_load_wakeup_0_T_2, _will_fire_store_commit_slow_0_T_1) node _will_fire_store_commit_slow_0_T_3 = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_4 = eq(_will_fire_store_commit_slow_0_T_3, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_5 = and(_will_fire_load_wakeup_0_T_5, _will_fire_store_commit_slow_0_T_4) node _will_fire_store_commit_slow_0_T_6 = and(will_fire_store_commit_slow_0_will_fire, UInt<1>(0h1)) node _will_fire_store_commit_slow_0_T_7 = eq(_will_fire_store_commit_slow_0_T_6, UInt<1>(0h0)) node _will_fire_store_commit_slow_0_T_8 = and(_will_fire_load_wakeup_0_T_8, _will_fire_store_commit_slow_0_T_7) connect will_fire_store_commit_slow[0], will_fire_store_commit_slow_0_will_fire node _T_149 = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _T_150 = or(_T_149, will_fire_store_agen[0]) node _T_151 = eq(_T_150, UInt<1>(0h0)) node _T_152 = and(io.core.agen[0].valid, _T_151) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:687 assert(!(agen(w).valid && !(will_fire_load_agen_exec(w) || will_fire_load_agen(w) || will_fire_store_agen(w))))\n") : printf_16 assert(clock, _T_153, UInt<1>(0h1), "") : assert_16 when will_fire_load_wakeup[0] : node _T_157 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _T_158 = bits(_T_157, 4, 0) connect block_load_mask[_T_158], UInt<1>(0h1) else : node _T_159 = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) when _T_159 : connect block_load_mask[io.core.agen[0].bits.uop.ldq_idx], UInt<1>(0h1) else : when will_fire_load_retry[0] : connect block_load_mask[retry_queue.io.deq.bits.uop.ldq_idx], UInt<1>(0h1) node _exe_tlb_valid_0_T = eq(_will_fire_store_commit_slow_0_T_2, UInt<1>(0h0)) connect exe_tlb_valid[0], _exe_tlb_valid_0_T node _T_160 = eq(will_fire_hella_incoming[0], UInt<1>(0h0)) node _T_161 = eq(will_fire_hella_wakeup[0], UInt<1>(0h0)) node _T_162 = and(_T_160, _T_161) node _T_163 = eq(will_fire_load_retry[0], UInt<1>(0h0)) node _T_164 = and(_T_162, _T_163) node _T_165 = eq(will_fire_store_retry[0], UInt<1>(0h0)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(will_fire_store_commit_fast[0], UInt<1>(0h0)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(will_fire_store_commit_slow[0], UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = eq(will_fire_load_wakeup[0], UInt<1>(0h0)) node _T_172 = and(_T_170, _T_171) node _T_173 = or(UInt<1>(0h1), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: Some operations is proceeding down multiple pipes\n at lsu.scala:698 assert((lsuWidth == 1).B ||\n") : printf_17 assert(clock, _T_173, UInt<1>(0h1), "") : assert_17 node _T_177 = neq(hella_state, UInt<3>(0h0)) node _T_178 = eq(hella_req.cmd, UInt<5>(0h14)) node _T_179 = and(_T_177, _T_178) node _T_180 = eq(_T_179, UInt<1>(0h0)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: SFENCE through hella interface not supported\n at lsu.scala:713 assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),\n") : printf_18 assert(clock, _T_180, UInt<1>(0h1), "") : assert_18 node _exe_tlb_uop_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_tlb_uop_T_1 = or(will_fire_load_retry[0], will_fire_store_retry[0]) wire _exe_tlb_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _exe_tlb_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_typ, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_rm, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.fp_val, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fcn_op, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.frs3_en, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.lrs3, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.lrs2, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.lrs1, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.ldst, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_unique, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.uses_stq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.mem_signed, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.mem_size, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.exc_cause, UInt<64>(0h0) connect _exe_tlb_uop_WIRE.exception, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.ppred, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.prs3, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.prs2, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.prs1, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.stq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.rob_idx, UInt<7>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.op2_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.op1_sel, UInt<2>(0h0) connect _exe_tlb_uop_WIRE.imm_packed, UInt<20>(0h0) connect _exe_tlb_uop_WIRE.pimm, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.imm_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.imm_rename, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.taken, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.pc_lob, UInt<6>(0h0) connect _exe_tlb_uop_WIRE.edge_inst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE.is_mov, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_rocc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_eret, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_amo, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sfence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_fencei, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_fence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.is_sfb, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.br_type, UInt<4>(0h0) connect _exe_tlb_uop_WIRE.br_tag, UInt<4>(0h0) connect _exe_tlb_uop_WIRE.br_mask, UInt<16>(0h0) connect _exe_tlb_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iw_issued, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE.debug_pc, UInt<40>(0h0) connect _exe_tlb_uop_WIRE.is_rvc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE.debug_inst, UInt<32>(0h0) connect _exe_tlb_uop_WIRE.inst, UInt<32>(0h0) wire _exe_tlb_uop_WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _exe_tlb_uop_WIRE_1.debug_tsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.debug_fsrc, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.bp_xcpt_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.bp_debug_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_ma_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_ae_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.xcpt_pf_if, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_typ, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_rm, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.fp_val, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fcn_op, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.fcn_dw, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.frs3_en, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.lrs2_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.lrs1_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.dst_rtype, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.lrs3, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.lrs2, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.lrs1, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.ldst, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.ldst_is_rs1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.csr_cmd, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.flush_on_commit, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_unique, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.uses_stq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.uses_ldq, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.mem_signed, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.mem_size, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.mem_cmd, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.exc_cause, UInt<64>(0h0) connect _exe_tlb_uop_WIRE_1.exception, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.stale_pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.ppred_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs3_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs2_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.prs1_busy, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.ppred, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.prs3, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.prs2, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.prs1, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.pdst, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.rxq_idx, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.stq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.ldq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.rob_idx, UInt<7>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.vec, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.wflags, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.sqrt, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.div, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fma, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fastpipe, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.toint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.fromint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.swap23, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.swap12, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren3, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren2, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ren1, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.wen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fp_ctrl.ldst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.op2_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.op1_sel, UInt<2>(0h0) connect _exe_tlb_uop_WIRE_1.imm_packed, UInt<20>(0h0) connect _exe_tlb_uop_WIRE_1.pimm, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.imm_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.imm_rename, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.taken, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.pc_lob, UInt<6>(0h0) connect _exe_tlb_uop_WIRE_1.edge_inst, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.ftq_idx, UInt<5>(0h0) connect _exe_tlb_uop_WIRE_1.is_mov, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_rocc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sys_pc2epc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_eret, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_amo, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sfence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_fencei, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_fence, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.is_sfb, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.br_type, UInt<4>(0h0) connect _exe_tlb_uop_WIRE_1.br_tag, UInt<4>(0h0) connect _exe_tlb_uop_WIRE_1.br_mask, UInt<16>(0h0) connect _exe_tlb_uop_WIRE_1.dis_col_sel, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p2_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_p1_speculative_child, UInt<3>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iw_issued, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[4], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[5], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[6], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[7], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[8], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.fu_code[9], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[0], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[1], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[2], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.iq_type[3], UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.debug_pc, UInt<40>(0h0) connect _exe_tlb_uop_WIRE_1.is_rvc, UInt<1>(0h0) connect _exe_tlb_uop_WIRE_1.debug_inst, UInt<32>(0h0) connect _exe_tlb_uop_WIRE_1.inst, UInt<32>(0h0) node _exe_tlb_uop_T_2 = mux(will_fire_hella_incoming[0], _exe_tlb_uop_WIRE, _exe_tlb_uop_WIRE_1) node _exe_tlb_uop_T_3 = mux(_exe_tlb_uop_T_1, retry_queue.io.deq.bits.uop, _exe_tlb_uop_T_2) node _exe_tlb_uop_T_4 = mux(will_fire_store_agen[0], stq_incoming_e[0].bits.uop, _exe_tlb_uop_T_3) node _exe_tlb_uop_T_5 = mux(_exe_tlb_uop_T, ldq_incoming_e[0].bits.uop, _exe_tlb_uop_T_4) wire exe_tlb_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect exe_tlb_uop[0], _exe_tlb_uop_T_5 node _exe_tlb_vaddr_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_tlb_vaddr_T_1 = or(_exe_tlb_vaddr_T, will_fire_store_agen[0]) node _exe_tlb_vaddr_T_2 = or(will_fire_load_retry[0], will_fire_store_retry[0]) node _exe_tlb_vaddr_T_3 = mux(will_fire_hella_incoming[0], hella_req.addr, UInt<1>(0h0)) node _exe_tlb_vaddr_T_4 = mux(_exe_tlb_vaddr_T_2, retry_queue.io.deq.bits.data, _exe_tlb_vaddr_T_3) node _exe_tlb_vaddr_T_5 = mux(will_fire_sfence[0], io.core.sfence.bits.addr, _exe_tlb_vaddr_T_4) node _exe_tlb_vaddr_T_6 = mux(_exe_tlb_vaddr_T_1, io.core.agen[0].bits.data, _exe_tlb_vaddr_T_5) wire exe_tlb_vaddr : UInt<64>[1] connect exe_tlb_vaddr[0], _exe_tlb_vaddr_T_6 node _exe_size_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_size_T_1 = or(_exe_size_T, will_fire_store_agen[0]) node _exe_size_T_2 = or(_exe_size_T_1, will_fire_load_retry[0]) node _exe_size_T_3 = or(_exe_size_T_2, will_fire_store_retry[0]) node _exe_size_T_4 = mux(will_fire_hella_incoming[0], hella_req.size, UInt<1>(0h0)) node _exe_size_T_5 = mux(_exe_size_T_3, exe_tlb_uop[0].mem_size, _exe_size_T_4) wire exe_size : UInt<2>[1] connect exe_size[0], _exe_size_T_5 node _exe_cmd_T = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _exe_cmd_T_1 = or(_exe_cmd_T, will_fire_store_agen[0]) node _exe_cmd_T_2 = or(_exe_cmd_T_1, will_fire_load_retry[0]) node _exe_cmd_T_3 = or(_exe_cmd_T_2, will_fire_store_retry[0]) node _exe_cmd_T_4 = mux(will_fire_sfence[0], UInt<5>(0h14), UInt<1>(0h0)) node _exe_cmd_T_5 = mux(will_fire_hella_incoming[0], hella_req.cmd, _exe_cmd_T_4) node _exe_cmd_T_6 = mux(_exe_cmd_T_3, exe_tlb_uop[0].mem_cmd, _exe_cmd_T_5) wire exe_cmd : UInt<5>[1] connect exe_cmd[0], _exe_cmd_T_6 node _exe_passthr_T = mux(will_fire_hella_incoming[0], hella_req.phys, UInt<1>(0h0)) wire exe_passthr : UInt<1>[1] connect exe_passthr[0], _exe_passthr_T node _exe_kill_T = mux(will_fire_hella_incoming[0], io.hellacache.s1_kill, UInt<1>(0h0)) wire exe_kill : UInt<1>[1] connect exe_kill[0], _exe_kill_T inst bkptu_0 of BreakpointUnit_8 connect bkptu_0.clock, clock connect bkptu_0.reset, reset connect dtlb.io.req[0].valid, exe_tlb_valid[0] connect dtlb.io.req[0].bits.vaddr, exe_tlb_vaddr[0] connect dtlb.io.req[0].bits.size, exe_size[0] connect dtlb.io.req[0].bits.cmd, exe_cmd[0] connect dtlb.io.req[0].bits.passthrough, exe_passthr[0] connect dtlb.io.req[0].bits.prv, io.ptw.status.prv connect dtlb.io.req[0].bits.v, io.ptw.status.v connect bkptu_0.io.status.uie, io.core.status.uie connect bkptu_0.io.status.sie, io.core.status.sie connect bkptu_0.io.status.hie, io.core.status.hie connect bkptu_0.io.status.mie, io.core.status.mie connect bkptu_0.io.status.upie, io.core.status.upie connect bkptu_0.io.status.spie, io.core.status.spie connect bkptu_0.io.status.ube, io.core.status.ube connect bkptu_0.io.status.mpie, io.core.status.mpie connect bkptu_0.io.status.spp, io.core.status.spp connect bkptu_0.io.status.vs, io.core.status.vs connect bkptu_0.io.status.mpp, io.core.status.mpp connect bkptu_0.io.status.fs, io.core.status.fs connect bkptu_0.io.status.xs, io.core.status.xs connect bkptu_0.io.status.mprv, io.core.status.mprv connect bkptu_0.io.status.sum, io.core.status.sum connect bkptu_0.io.status.mxr, io.core.status.mxr connect bkptu_0.io.status.tvm, io.core.status.tvm connect bkptu_0.io.status.tw, io.core.status.tw connect bkptu_0.io.status.tsr, io.core.status.tsr connect bkptu_0.io.status.zero1, io.core.status.zero1 connect bkptu_0.io.status.sd_rv32, io.core.status.sd_rv32 connect bkptu_0.io.status.uxl, io.core.status.uxl connect bkptu_0.io.status.sxl, io.core.status.sxl connect bkptu_0.io.status.sbe, io.core.status.sbe connect bkptu_0.io.status.mbe, io.core.status.mbe connect bkptu_0.io.status.gva, io.core.status.gva connect bkptu_0.io.status.mpv, io.core.status.mpv connect bkptu_0.io.status.zero2, io.core.status.zero2 connect bkptu_0.io.status.sd, io.core.status.sd connect bkptu_0.io.status.v, io.core.status.v connect bkptu_0.io.status.prv, io.core.status.prv connect bkptu_0.io.status.dv, io.core.status.dv connect bkptu_0.io.status.dprv, io.core.status.dprv connect bkptu_0.io.status.isa, io.core.status.isa connect bkptu_0.io.status.wfi, io.core.status.wfi connect bkptu_0.io.status.cease, io.core.status.cease connect bkptu_0.io.status.debug, io.core.status.debug invalidate bkptu_0.io.pc connect bkptu_0.io.ea, exe_tlb_vaddr[0] connect bkptu_0.io.mcontext, io.core.mcontext connect bkptu_0.io.scontext, io.core.scontext connect dtlb.io.kill, exe_kill[0] connect dtlb.io.sfence.bits.hg, io.core.sfence.bits.hg connect dtlb.io.sfence.bits.hv, io.core.sfence.bits.hv connect dtlb.io.sfence.bits.asid, io.core.sfence.bits.asid connect dtlb.io.sfence.bits.addr, io.core.sfence.bits.addr connect dtlb.io.sfence.bits.rs2, io.core.sfence.bits.rs2 connect dtlb.io.sfence.bits.rs1, io.core.sfence.bits.rs1 connect dtlb.io.sfence.valid, io.core.sfence.valid node _ma_ld_T = and(dtlb.io.resp[0].ma.ld, exe_tlb_uop[0].uses_ldq) wire ma_ld : UInt<1>[1] connect ma_ld[0], _ma_ld_T node _ma_st_T = and(dtlb.io.resp[0].ma.st, exe_tlb_uop[0].uses_stq) node _ma_st_T_1 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _ma_st_T_2 = and(_ma_st_T, _ma_st_T_1) wire ma_st : UInt<1>[1] connect ma_st[0], _ma_st_T_2 node _pf_ld_T = and(dtlb.io.resp[0].pf.ld, exe_tlb_uop[0].uses_ldq) wire pf_ld : UInt<1>[1] connect pf_ld[0], _pf_ld_T node _pf_st_T = and(dtlb.io.resp[0].pf.st, exe_tlb_uop[0].uses_stq) wire pf_st : UInt<1>[1] connect pf_st[0], _pf_st_T node _ae_ld_T = and(dtlb.io.resp[0].ae.ld, exe_tlb_uop[0].uses_ldq) wire ae_ld : UInt<1>[1] connect ae_ld[0], _ae_ld_T node _ae_st_T = and(dtlb.io.resp[0].ae.st, exe_tlb_uop[0].uses_stq) wire ae_st : UInt<1>[1] connect ae_st[0], _ae_st_T node _dbg_bp_T = and(exe_tlb_uop[0].uses_ldq, bkptu_0.io.debug_ld) node _dbg_bp_T_1 = and(exe_tlb_uop[0].uses_stq, bkptu_0.io.debug_st) node _dbg_bp_T_2 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _dbg_bp_T_3 = and(_dbg_bp_T_1, _dbg_bp_T_2) node _dbg_bp_T_4 = or(_dbg_bp_T, _dbg_bp_T_3) node _dbg_bp_T_5 = and(bkptu_0.io.debug_st, _dbg_bp_T_4) wire dbg_bp : UInt<1>[1] connect dbg_bp[0], _dbg_bp_T_5 node _bp_T = and(exe_tlb_uop[0].uses_ldq, bkptu_0.io.xcpt_ld) node _bp_T_1 = and(exe_tlb_uop[0].uses_stq, bkptu_0.io.xcpt_st) node _bp_T_2 = eq(exe_tlb_uop[0].is_fence, UInt<1>(0h0)) node _bp_T_3 = and(_bp_T_1, _bp_T_2) node _bp_T_4 = or(_bp_T, _bp_T_3) node _bp_T_5 = and(bkptu_0.io.debug_st, _bp_T_4) wire bp : UInt<1>[1] connect bp[0], _bp_T_5 node _mem_xcpt_valids_T = or(pf_ld[0], pf_st[0]) node _mem_xcpt_valids_T_1 = or(_mem_xcpt_valids_T, ae_ld[0]) node _mem_xcpt_valids_T_2 = or(_mem_xcpt_valids_T_1, ae_st[0]) node _mem_xcpt_valids_T_3 = or(_mem_xcpt_valids_T_2, ma_ld[0]) node _mem_xcpt_valids_T_4 = or(_mem_xcpt_valids_T_3, ma_st[0]) node _mem_xcpt_valids_T_5 = or(_mem_xcpt_valids_T_4, dbg_bp[0]) node _mem_xcpt_valids_T_6 = or(_mem_xcpt_valids_T_5, bp[0]) node _mem_xcpt_valids_T_7 = and(exe_tlb_valid[0], _mem_xcpt_valids_T_6) node _mem_xcpt_valids_T_8 = and(io.core.brupdate.b1.mispredict_mask, exe_tlb_uop[0].br_mask) node _mem_xcpt_valids_T_9 = neq(_mem_xcpt_valids_T_8, UInt<1>(0h0)) node _mem_xcpt_valids_T_10 = or(_mem_xcpt_valids_T_9, io.core.exception) node _mem_xcpt_valids_T_11 = eq(_mem_xcpt_valids_T_10, UInt<1>(0h0)) node _mem_xcpt_valids_T_12 = and(_mem_xcpt_valids_T_7, _mem_xcpt_valids_T_11) wire _mem_xcpt_valids_WIRE : UInt<1>[1] connect _mem_xcpt_valids_WIRE[0], _mem_xcpt_valids_T_12 reg mem_xcpt_valids : UInt<1>[1], clock connect mem_xcpt_valids, _mem_xcpt_valids_WIRE wire mem_xcpt_uops_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect mem_xcpt_uops_out, exe_tlb_uop[0] node _mem_xcpt_uops_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_xcpt_uops_out_br_mask_T_1 = and(exe_tlb_uop[0].br_mask, _mem_xcpt_uops_out_br_mask_T) connect mem_xcpt_uops_out.br_mask, _mem_xcpt_uops_out_br_mask_T_1 wire _mem_xcpt_uops_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect _mem_xcpt_uops_WIRE[0], mem_xcpt_uops_out reg mem_xcpt_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1], clock connect mem_xcpt_uops, _mem_xcpt_uops_WIRE node _mem_xcpt_causes_T = mux(ae_ld[0], UInt<3>(0h5), UInt<1>(0h0)) node _mem_xcpt_causes_T_1 = mux(ae_st[0], UInt<3>(0h7), _mem_xcpt_causes_T) node _mem_xcpt_causes_T_2 = mux(pf_ld[0], UInt<4>(0hd), _mem_xcpt_causes_T_1) node _mem_xcpt_causes_T_3 = mux(pf_st[0], UInt<4>(0hf), _mem_xcpt_causes_T_2) node _mem_xcpt_causes_T_4 = mux(ma_ld[0], UInt<3>(0h4), _mem_xcpt_causes_T_3) node _mem_xcpt_causes_T_5 = mux(ma_st[0], UInt<3>(0h6), _mem_xcpt_causes_T_4) node _mem_xcpt_causes_T_6 = mux(bp[0], UInt<2>(0h3), _mem_xcpt_causes_T_5) node _mem_xcpt_causes_T_7 = mux(dbg_bp[0], UInt<4>(0he), _mem_xcpt_causes_T_6) wire _mem_xcpt_causes_WIRE : UInt<4>[1] connect _mem_xcpt_causes_WIRE[0], _mem_xcpt_causes_T_7 reg mem_xcpt_causes : UInt<4>[1], clock connect mem_xcpt_causes, _mem_xcpt_causes_WIRE reg mem_xcpt_vaddrs : UInt<64>[1], clock connect mem_xcpt_vaddrs, exe_tlb_vaddr node _T_184 = and(dtlb.io.req[0].valid, exe_tlb_uop[0].is_fence) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: Fence is pretending to talk to the TLB\n at lsu.scala:813 assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), \"Fence is pretending to talk to the TLB\")\n") : printf_19 assert(clock, _T_185, UInt<1>(0h1), "") : assert_19 connect mem_xcpt_valid, mem_xcpt_valids[0] connect mem_xcpt_cause, mem_xcpt_causes[0] connect mem_xcpt_uop, mem_xcpt_uops[0] connect mem_xcpt_vaddr, mem_xcpt_vaddrs[0] node _exe_tlb_miss_T = eq(dtlb.io.req[0].ready, UInt<1>(0h0)) node _exe_tlb_miss_T_1 = or(dtlb.io.resp[0].miss, _exe_tlb_miss_T) node _exe_tlb_miss_T_2 = and(dtlb.io.req[0].valid, _exe_tlb_miss_T_1) wire exe_tlb_miss : UInt<1>[1] connect exe_tlb_miss[0], _exe_tlb_miss_T_2 node _exe_tlb_paddr_T = bits(dtlb.io.resp[0].paddr, 31, 12) node _exe_tlb_paddr_T_1 = bits(exe_tlb_vaddr[0], 11, 0) node _exe_tlb_paddr_T_2 = cat(_exe_tlb_paddr_T, _exe_tlb_paddr_T_1) wire exe_tlb_paddr : UInt<32>[1] connect exe_tlb_paddr[0], _exe_tlb_paddr_T_2 node _exe_tlb_uncacheable_T = eq(dtlb.io.resp[0].cacheable, UInt<1>(0h0)) wire exe_tlb_uncacheable : UInt<1>[1] connect exe_tlb_uncacheable[0], _exe_tlb_uncacheable_T node _T_189 = eq(exe_tlb_paddr[0], dtlb.io.resp[0].paddr) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] paddrs should match.\n at lsu.scala:841 assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr, \"[lsu] paddrs should match.\")\n") : printf_20 assert(clock, _T_189, UInt<1>(0h1), "") : assert_20 when mem_xcpt_valids[0] : node _T_193 = or(will_fire_load_agen_exec[0], will_fire_load_agen[0]) node _T_194 = or(_T_193, will_fire_store_agen[0]) node _T_195 = or(_T_194, will_fire_load_retry[0]) node _T_196 = or(_T_195, will_fire_store_retry[0]) reg REG : UInt<1>, clock connect REG, _T_196 node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(REG, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:845 assert(RegNext(will_fire_load_agen_exec(w) || will_fire_load_agen(w) || will_fire_store_agen(w) ||\n") : printf_21 assert(clock, REG, UInt<1>(0h1), "") : assert_21 node _T_200 = xor(mem_xcpt_uops[0].uses_ldq, mem_xcpt_uops[0].uses_stq) node _T_201 = asUInt(reset) node _T_202 = eq(_T_201, UInt<1>(0h0)) when _T_202 : node _T_203 = eq(_T_200, UInt<1>(0h0)) when _T_203 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:848 assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)\n") : printf_22 assert(clock, _T_200, UInt<1>(0h1), "") : assert_22 when mem_xcpt_uops[0].uses_ldq : connect ldq_uop[mem_xcpt_uops[0].ldq_idx].exception, UInt<1>(0h1) else : connect stq_uop[mem_xcpt_uops[0].stq_idx].exception, UInt<1>(0h1) node _exe_agen_killed_T = and(io.core.brupdate.b1.mispredict_mask, io.core.agen[0].bits.uop.br_mask) node _exe_agen_killed_T_1 = neq(_exe_agen_killed_T, UInt<1>(0h0)) node _exe_agen_killed_T_2 = or(_exe_agen_killed_T_1, io.core.exception) wire exe_agen_killed : UInt<1>[1] connect exe_agen_killed[0], _exe_agen_killed_T_2 connect io.dmem.brupdate, io.core.brupdate connect io.dmem.exception, io.core.exception connect io.dmem.rob_head_idx, io.core.rob_head_idx connect io.dmem.rob_pnr_idx, io.core.rob_pnr_idx wire dmem_req : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}[1] connect io.dmem.req.valid, dmem_req[0].valid connect io.dmem.req.bits, dmem_req node _dmem_req_fire_T = and(io.dmem.req.ready, io.dmem.req.valid) node _dmem_req_fire_T_1 = and(dmem_req[0].valid, _dmem_req_fire_T) wire dmem_req_fire : UInt<1>[1] connect dmem_req_fire[0], _dmem_req_fire_T_1 wire _s0_executing_loads_WIRE : UInt<1>[24] connect _s0_executing_loads_WIRE[0], UInt<1>(0h0) connect _s0_executing_loads_WIRE[1], UInt<1>(0h0) connect _s0_executing_loads_WIRE[2], UInt<1>(0h0) connect _s0_executing_loads_WIRE[3], UInt<1>(0h0) connect _s0_executing_loads_WIRE[4], UInt<1>(0h0) connect _s0_executing_loads_WIRE[5], UInt<1>(0h0) connect _s0_executing_loads_WIRE[6], UInt<1>(0h0) connect _s0_executing_loads_WIRE[7], UInt<1>(0h0) connect _s0_executing_loads_WIRE[8], UInt<1>(0h0) connect _s0_executing_loads_WIRE[9], UInt<1>(0h0) connect _s0_executing_loads_WIRE[10], UInt<1>(0h0) connect _s0_executing_loads_WIRE[11], UInt<1>(0h0) connect _s0_executing_loads_WIRE[12], UInt<1>(0h0) connect _s0_executing_loads_WIRE[13], UInt<1>(0h0) connect _s0_executing_loads_WIRE[14], UInt<1>(0h0) connect _s0_executing_loads_WIRE[15], UInt<1>(0h0) connect _s0_executing_loads_WIRE[16], UInt<1>(0h0) connect _s0_executing_loads_WIRE[17], UInt<1>(0h0) connect _s0_executing_loads_WIRE[18], UInt<1>(0h0) connect _s0_executing_loads_WIRE[19], UInt<1>(0h0) connect _s0_executing_loads_WIRE[20], UInt<1>(0h0) connect _s0_executing_loads_WIRE[21], UInt<1>(0h0) connect _s0_executing_loads_WIRE[22], UInt<1>(0h0) connect _s0_executing_loads_WIRE[23], UInt<1>(0h0) wire s0_executing_loads : UInt<1>[24] connect s0_executing_loads, _s0_executing_loads_WIRE wire s0_kills : UInt<1>[1] connect dmem_req[0].valid, UInt<1>(0h0) wire _dmem_req_0_bits_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _dmem_req_0_bits_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_typ, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_rm, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_val, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fcn_op, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.frs3_en, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs3, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs2, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.lrs1, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldst, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_unique, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.uses_stq, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_signed, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_size, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.exc_cause, UInt<64>(0h0) connect _dmem_req_0_bits_uop_WIRE.exception, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.ppred, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs3, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs2, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.prs1, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.pdst, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.stq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.rob_idx, UInt<7>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.op2_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.op1_sel, UInt<2>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_packed, UInt<20>(0h0) connect _dmem_req_0_bits_uop_WIRE.pimm, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.imm_rename, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.taken, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.pc_lob, UInt<6>(0h0) connect _dmem_req_0_bits_uop_WIRE.edge_inst, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_mov, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_rocc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_eret, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_amo, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sfence, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_fencei, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_fence, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_sfb, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_type, UInt<4>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_tag, UInt<4>(0h0) connect _dmem_req_0_bits_uop_WIRE.br_mask, UInt<16>(0h0) connect _dmem_req_0_bits_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iw_issued, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_pc, UInt<40>(0h0) connect _dmem_req_0_bits_uop_WIRE.is_rvc, UInt<1>(0h0) connect _dmem_req_0_bits_uop_WIRE.debug_inst, UInt<32>(0h0) connect _dmem_req_0_bits_uop_WIRE.inst, UInt<32>(0h0) connect dmem_req[0].bits.uop, _dmem_req_0_bits_uop_WIRE connect dmem_req[0].bits.addr, UInt<1>(0h0) connect dmem_req[0].bits.data, UInt<1>(0h0) connect dmem_req[0].bits.is_hella, UInt<1>(0h0) connect s0_kills[0], UInt<1>(0h0) node _io_dmem_s1_kill_0_T = and(s0_kills[0], dmem_req_fire[0]) reg io_dmem_s1_kill_0_REG : UInt<1>, clock connect io_dmem_s1_kill_0_REG, _io_dmem_s1_kill_0_T connect io.dmem.s1_kill[0], io_dmem_s1_kill_0_REG when will_fire_load_agen_exec[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, exe_tlb_paddr[0] connect dmem_req[0].bits.uop, exe_tlb_uop[0] node _s0_kills_0_T = or(exe_tlb_miss[0], exe_tlb_uncacheable[0]) node _s0_kills_0_T_1 = or(_s0_kills_0_T, ma_ld[0]) node _s0_kills_0_T_2 = or(_s0_kills_0_T_1, ae_ld[0]) node _s0_kills_0_T_3 = or(_s0_kills_0_T_2, pf_ld[0]) connect s0_kills[0], _s0_kills_0_T_3 node _s0_executing_loads_T = eq(s0_kills[0], UInt<1>(0h0)) node _s0_executing_loads_T_1 = and(dmem_req_fire[0], _s0_executing_loads_T) connect s0_executing_loads[ldq_incoming_idx[0]], _s0_executing_loads_T_1 node _T_204 = eq(ldq_incoming_e[0].bits.executed, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:903 assert(!ldq_incoming_e(w).bits.executed)\n") : printf_23 assert(clock, _T_204, UInt<1>(0h1), "") : assert_23 else : when will_fire_load_retry[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, exe_tlb_paddr[0] connect dmem_req[0].bits.uop, exe_tlb_uop[0] node _s0_kills_0_T_4 = or(exe_tlb_miss[0], exe_tlb_uncacheable[0]) node _s0_kills_0_T_5 = or(_s0_kills_0_T_4, ma_ld[0]) node _s0_kills_0_T_6 = or(_s0_kills_0_T_5, ae_ld[0]) node _s0_kills_0_T_7 = or(_s0_kills_0_T_6, pf_ld[0]) connect s0_kills[0], _s0_kills_0_T_7 node _s0_executing_loads_T_2 = eq(s0_kills[0], UInt<1>(0h0)) node _s0_executing_loads_T_3 = and(dmem_req_fire[0], _s0_executing_loads_T_2) connect s0_executing_loads[retry_queue.io.deq.bits.uop.ldq_idx], _s0_executing_loads_T_3 else : node _T_208 = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) when _T_208 : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, stq_execute_queue.io.deq.bits.addr.bits wire dmem_req_0_bits_data_size : UInt<2> connect dmem_req_0_bits_data_size, stq_execute_queue.io.deq.bits.uop.mem_size node _dmem_req_0_bits_data_T = eq(dmem_req_0_bits_data_size, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_1 = bits(stq_execute_queue.io.deq.bits.data.bits, 7, 0) node _dmem_req_0_bits_data_T_2 = cat(_dmem_req_0_bits_data_T_1, _dmem_req_0_bits_data_T_1) node _dmem_req_0_bits_data_T_3 = cat(_dmem_req_0_bits_data_T_2, _dmem_req_0_bits_data_T_2) node _dmem_req_0_bits_data_T_4 = cat(_dmem_req_0_bits_data_T_3, _dmem_req_0_bits_data_T_3) node _dmem_req_0_bits_data_T_5 = eq(dmem_req_0_bits_data_size, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_6 = bits(stq_execute_queue.io.deq.bits.data.bits, 15, 0) node _dmem_req_0_bits_data_T_7 = cat(_dmem_req_0_bits_data_T_6, _dmem_req_0_bits_data_T_6) node _dmem_req_0_bits_data_T_8 = cat(_dmem_req_0_bits_data_T_7, _dmem_req_0_bits_data_T_7) node _dmem_req_0_bits_data_T_9 = eq(dmem_req_0_bits_data_size, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_10 = bits(stq_execute_queue.io.deq.bits.data.bits, 31, 0) node _dmem_req_0_bits_data_T_11 = cat(_dmem_req_0_bits_data_T_10, _dmem_req_0_bits_data_T_10) node _dmem_req_0_bits_data_T_12 = mux(_dmem_req_0_bits_data_T_9, _dmem_req_0_bits_data_T_11, stq_execute_queue.io.deq.bits.data.bits) node _dmem_req_0_bits_data_T_13 = mux(_dmem_req_0_bits_data_T_5, _dmem_req_0_bits_data_T_8, _dmem_req_0_bits_data_T_12) node _dmem_req_0_bits_data_T_14 = mux(_dmem_req_0_bits_data_T, _dmem_req_0_bits_data_T_4, _dmem_req_0_bits_data_T_13) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_14 connect dmem_req[0].bits.uop, stq_execute_queue.io.deq.bits.uop node _T_209 = eq(dmem_req_fire[0], UInt<1>(0h0)) when _T_209 : connect stq_execute_queue_flush, UInt<1>(0h1) connect stq_execute_head, stq_execute_queue.io.deq.bits.uop.stq_idx connect stq_succeeded[stq_execute_queue.io.deq.bits.uop.stq_idx], UInt<1>(0h0) else : when will_fire_load_wakeup[0] : connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, ldq_wakeup_e.bits.addr.bits connect dmem_req[0].bits.uop, ldq_wakeup_e.bits.uop node _T_210 = or(ldq_wakeup_idx, UInt<5>(0h0)) node _T_211 = bits(_T_210, 4, 0) connect s0_executing_loads[_T_211], dmem_req_fire[0] node _T_212 = eq(ldq_wakeup_e.bits.executed, UInt<1>(0h0)) node _T_213 = eq(ldq_wakeup_e.bits.addr_is_virtual, UInt<1>(0h0)) node _T_214 = and(_T_212, _T_213) node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_T_214, UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:933 assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)\n") : printf_24 assert(clock, _T_214, UInt<1>(0h1), "") : assert_24 else : when will_fire_hella_incoming[0] : node _T_218 = eq(hella_state, UInt<3>(0h1)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:935 assert(hella_state === h_s1)\n") : printf_25 assert(clock, _T_218, UInt<1>(0h1), "") : assert_25 node _dmem_req_0_valid_T = eq(io.hellacache.s1_kill, UInt<1>(0h0)) node _dmem_req_0_valid_T_1 = eq(exe_tlb_miss[0], UInt<1>(0h0)) node _dmem_req_0_valid_T_2 = or(_dmem_req_0_valid_T_1, hella_req.phys) node _dmem_req_0_valid_T_3 = and(_dmem_req_0_valid_T, _dmem_req_0_valid_T_2) connect dmem_req[0].valid, _dmem_req_0_valid_T_3 connect dmem_req[0].bits.addr, exe_tlb_paddr[0] wire dmem_req_0_bits_data_size_1 : UInt<2> connect dmem_req_0_bits_data_size_1, hella_req.size node _dmem_req_0_bits_data_T_15 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_16 = bits(io.hellacache.s1_data.data, 7, 0) node _dmem_req_0_bits_data_T_17 = cat(_dmem_req_0_bits_data_T_16, _dmem_req_0_bits_data_T_16) node _dmem_req_0_bits_data_T_18 = cat(_dmem_req_0_bits_data_T_17, _dmem_req_0_bits_data_T_17) node _dmem_req_0_bits_data_T_19 = cat(_dmem_req_0_bits_data_T_18, _dmem_req_0_bits_data_T_18) node _dmem_req_0_bits_data_T_20 = eq(dmem_req_0_bits_data_size_1, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_21 = bits(io.hellacache.s1_data.data, 15, 0) node _dmem_req_0_bits_data_T_22 = cat(_dmem_req_0_bits_data_T_21, _dmem_req_0_bits_data_T_21) node _dmem_req_0_bits_data_T_23 = cat(_dmem_req_0_bits_data_T_22, _dmem_req_0_bits_data_T_22) node _dmem_req_0_bits_data_T_24 = eq(dmem_req_0_bits_data_size_1, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_25 = bits(io.hellacache.s1_data.data, 31, 0) node _dmem_req_0_bits_data_T_26 = cat(_dmem_req_0_bits_data_T_25, _dmem_req_0_bits_data_T_25) node _dmem_req_0_bits_data_T_27 = mux(_dmem_req_0_bits_data_T_24, _dmem_req_0_bits_data_T_26, io.hellacache.s1_data.data) node _dmem_req_0_bits_data_T_28 = mux(_dmem_req_0_bits_data_T_20, _dmem_req_0_bits_data_T_23, _dmem_req_0_bits_data_T_27) node _dmem_req_0_bits_data_T_29 = mux(_dmem_req_0_bits_data_T_15, _dmem_req_0_bits_data_T_19, _dmem_req_0_bits_data_T_28) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_29 connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd connect dmem_req[0].bits.uop.mem_size, hella_req.size connect dmem_req[0].bits.uop.mem_signed, hella_req.signed connect dmem_req[0].bits.is_hella, UInt<1>(0h1) connect hella_paddr, exe_tlb_paddr[0] else : when will_fire_hella_wakeup[0] : node _T_222 = eq(hella_state, UInt<3>(0h5)) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:952 assert(hella_state === h_replay)\n") : printf_26 assert(clock, _T_222, UInt<1>(0h1), "") : assert_26 connect dmem_req[0].valid, UInt<1>(0h1) connect dmem_req[0].bits.addr, hella_paddr wire dmem_req_0_bits_data_size_2 : UInt<2> connect dmem_req_0_bits_data_size_2, hella_req.size node _dmem_req_0_bits_data_T_30 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h0)) node _dmem_req_0_bits_data_T_31 = bits(hella_data.data, 7, 0) node _dmem_req_0_bits_data_T_32 = cat(_dmem_req_0_bits_data_T_31, _dmem_req_0_bits_data_T_31) node _dmem_req_0_bits_data_T_33 = cat(_dmem_req_0_bits_data_T_32, _dmem_req_0_bits_data_T_32) node _dmem_req_0_bits_data_T_34 = cat(_dmem_req_0_bits_data_T_33, _dmem_req_0_bits_data_T_33) node _dmem_req_0_bits_data_T_35 = eq(dmem_req_0_bits_data_size_2, UInt<1>(0h1)) node _dmem_req_0_bits_data_T_36 = bits(hella_data.data, 15, 0) node _dmem_req_0_bits_data_T_37 = cat(_dmem_req_0_bits_data_T_36, _dmem_req_0_bits_data_T_36) node _dmem_req_0_bits_data_T_38 = cat(_dmem_req_0_bits_data_T_37, _dmem_req_0_bits_data_T_37) node _dmem_req_0_bits_data_T_39 = eq(dmem_req_0_bits_data_size_2, UInt<2>(0h2)) node _dmem_req_0_bits_data_T_40 = bits(hella_data.data, 31, 0) node _dmem_req_0_bits_data_T_41 = cat(_dmem_req_0_bits_data_T_40, _dmem_req_0_bits_data_T_40) node _dmem_req_0_bits_data_T_42 = mux(_dmem_req_0_bits_data_T_39, _dmem_req_0_bits_data_T_41, hella_data.data) node _dmem_req_0_bits_data_T_43 = mux(_dmem_req_0_bits_data_T_35, _dmem_req_0_bits_data_T_38, _dmem_req_0_bits_data_T_42) node _dmem_req_0_bits_data_T_44 = mux(_dmem_req_0_bits_data_T_30, _dmem_req_0_bits_data_T_34, _dmem_req_0_bits_data_T_43) connect dmem_req[0].bits.data, _dmem_req_0_bits_data_T_44 connect dmem_req[0].bits.uop.mem_cmd, hella_req.cmd connect dmem_req[0].bits.uop.mem_size, hella_req.size connect dmem_req[0].bits.uop.mem_signed, hella_req.signed connect dmem_req[0].bits.is_hella, UInt<1>(0h1) node _T_226 = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) node _T_227 = or(_T_226, will_fire_load_retry[0]) when _T_227 : node _ldq_idx_T = or(will_fire_load_agen[0], will_fire_load_agen_exec[0]) node ldq_idx = mux(_ldq_idx_T, ldq_incoming_idx[0], retry_queue.io.deq.bits.uop.ldq_idx) node _ldq_addr_valid_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _ldq_addr_valid_T_1 = or(_ldq_addr_valid_T, will_fire_load_retry[0]) connect ldq_addr[ldq_idx].valid, _ldq_addr_valid_T_1 node _ldq_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0]) connect ldq_addr[ldq_idx].bits, _ldq_addr_bits_T wire ldq_ld_byte_mask_mask : UInt<8> node _ldq_ld_byte_mask_mask_T = eq(exe_tlb_uop[0].mem_size, UInt<1>(0h0)) node _ldq_ld_byte_mask_mask_T_1 = bits(exe_tlb_vaddr[0], 2, 0) node _ldq_ld_byte_mask_mask_T_2 = dshl(UInt<8>(0h1), _ldq_ld_byte_mask_mask_T_1) node _ldq_ld_byte_mask_mask_T_3 = eq(exe_tlb_uop[0].mem_size, UInt<1>(0h1)) node _ldq_ld_byte_mask_mask_T_4 = bits(exe_tlb_vaddr[0], 2, 1) node _ldq_ld_byte_mask_mask_T_5 = dshl(_ldq_ld_byte_mask_mask_T_4, UInt<1>(0h1)) node _ldq_ld_byte_mask_mask_T_6 = dshl(UInt<8>(0h3), _ldq_ld_byte_mask_mask_T_5) node _ldq_ld_byte_mask_mask_T_7 = eq(exe_tlb_uop[0].mem_size, UInt<2>(0h2)) node _ldq_ld_byte_mask_mask_T_8 = bits(exe_tlb_vaddr[0], 2, 2) node _ldq_ld_byte_mask_mask_T_9 = mux(_ldq_ld_byte_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _ldq_ld_byte_mask_mask_T_10 = eq(exe_tlb_uop[0].mem_size, UInt<2>(0h3)) node _ldq_ld_byte_mask_mask_T_11 = mux(_ldq_ld_byte_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _ldq_ld_byte_mask_mask_T_12 = mux(_ldq_ld_byte_mask_mask_T_7, _ldq_ld_byte_mask_mask_T_9, _ldq_ld_byte_mask_mask_T_11) node _ldq_ld_byte_mask_mask_T_13 = mux(_ldq_ld_byte_mask_mask_T_3, _ldq_ld_byte_mask_mask_T_6, _ldq_ld_byte_mask_mask_T_12) node _ldq_ld_byte_mask_mask_T_14 = mux(_ldq_ld_byte_mask_mask_T, _ldq_ld_byte_mask_mask_T_2, _ldq_ld_byte_mask_mask_T_13) connect ldq_ld_byte_mask_mask, _ldq_ld_byte_mask_mask_T_14 connect ldq_ld_byte_mask[ldq_idx], ldq_ld_byte_mask_mask connect ldq_uop[ldq_idx].pdst, exe_tlb_uop[0].pdst connect ldq_addr_is_virtual[ldq_idx], exe_tlb_miss[0] node _ldq_addr_is_uncacheable_T = eq(exe_tlb_miss[0], UInt<1>(0h0)) node _ldq_addr_is_uncacheable_T_1 = and(exe_tlb_uncacheable[0], _ldq_addr_is_uncacheable_T) connect ldq_addr_is_uncacheable[ldq_idx], _ldq_addr_is_uncacheable_T_1 node _T_228 = eq(ldq_addr[ldq_idx].valid, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Translating load is overwriting a valid address\n at lsu.scala:977 assert(!ldq_addr(ldq_idx).valid,\n") : printf_27 assert(clock, _T_228, UInt<1>(0h1), "") : assert_27 node _T_232 = or(will_fire_store_agen[0], will_fire_store_retry[0]) when _T_232 : node stq_idx = mux(will_fire_store_agen[0], stq_incoming_idx[0], retry_queue.io.deq.bits.uop.stq_idx) node _stq_addr_valid_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _stq_addr_valid_T_1 = or(_stq_addr_valid_T, will_fire_store_retry[0]) node _stq_addr_valid_T_2 = eq(pf_st[0], UInt<1>(0h0)) node _stq_addr_valid_T_3 = and(_stq_addr_valid_T_1, _stq_addr_valid_T_2) connect stq_addr[stq_idx].valid, _stq_addr_valid_T_3 node _stq_addr_bits_T = mux(exe_tlb_miss[0], exe_tlb_vaddr[0], exe_tlb_paddr[0]) connect stq_addr[stq_idx].bits, _stq_addr_bits_T connect stq_uop[stq_idx].pdst, exe_tlb_uop[0].pdst connect stq_addr_is_virtual[stq_idx], exe_tlb_miss[0] node _T_233 = eq(stq_addr[stq_idx].valid, UInt<1>(0h0)) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] Translating store is overwriting a valid address\n at lsu.scala:991 assert(!stq_addr(stq_idx).valid,\n") : printf_28 assert(clock, _T_233, UInt<1>(0h1), "") : assert_28 when io.core.dgen[0].valid : connect stq_data[io.core.dgen[0].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[0].bits.uop.stq_idx].bits, io.core.dgen[0].bits.data node _T_237 = eq(stq_data[io.core.dgen[0].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_238 = eq(stq_data[io.core.dgen[0].bits.uop.stq_idx].bits, io.core.dgen[0].bits.data) node _T_239 = or(_T_237, _T_238) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid || (stq_data(sidx).bits === dgen.bits.data))\n") : printf_29 assert(clock, _T_239, UInt<1>(0h1), "") : assert_29 when io.core.dgen[1].valid : connect stq_data[io.core.dgen[1].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[1].bits.uop.stq_idx].bits, io.core.dgen[1].bits.data node _T_243 = eq(stq_data[io.core.dgen[1].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_244 = eq(stq_data[io.core.dgen[1].bits.uop.stq_idx].bits, io.core.dgen[1].bits.data) node _T_245 = or(_T_243, _T_244) node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(_T_245, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid || (stq_data(sidx).bits === dgen.bits.data))\n") : printf_30 assert(clock, _T_245, UInt<1>(0h1), "") : assert_30 when io.core.dgen[2].valid : connect stq_data[io.core.dgen[2].bits.uop.stq_idx].valid, UInt<1>(0h1) connect stq_data[io.core.dgen[2].bits.uop.stq_idx].bits, io.core.dgen[2].bits.data node _T_249 = eq(stq_data[io.core.dgen[2].bits.uop.stq_idx].valid, UInt<1>(0h0)) node _T_250 = eq(stq_data[io.core.dgen[2].bits.uop.stq_idx].bits, io.core.dgen[2].bits.data) node _T_251 = or(_T_249, _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1006 assert(!stq_data(sidx).valid || (stq_data(sidx).bits === dgen.bits.data))\n") : printf_31 assert(clock, _T_251, UInt<1>(0h1), "") : assert_31 inst wakeupArbs_0 of Arbiter2_Wakeup connect wakeupArbs_0.clock, clock connect wakeupArbs_0.reset, reset connect wakeupArbs_0.io.out.ready, UInt<1>(0h1) invalidate wakeupArbs_0.io.in[0].bits.rebusy invalidate wakeupArbs_0.io.in[0].bits.speculative_mask invalidate wakeupArbs_0.io.in[0].bits.bypassable invalidate wakeupArbs_0.io.in[0].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[0].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[0].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[0].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[0].bits.uop.fp_val invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[0].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[0].bits.uop.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[0].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[0].bits.uop.is_unique invalidate wakeupArbs_0.io.in[0].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[0].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[0].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[0].bits.uop.mem_size invalidate wakeupArbs_0.io.in[0].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[0].bits.uop.exception invalidate wakeupArbs_0.io.in[0].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[0].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[0].bits.uop.ppred invalidate wakeupArbs_0.io.in[0].bits.uop.prs3 invalidate wakeupArbs_0.io.in[0].bits.uop.prs2 invalidate wakeupArbs_0.io.in[0].bits.uop.prs1 invalidate wakeupArbs_0.io.in[0].bits.uop.pdst invalidate wakeupArbs_0.io.in[0].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[0].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[0].bits.uop.pimm invalidate wakeupArbs_0.io.in[0].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[0].bits.uop.taken invalidate wakeupArbs_0.io.in[0].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[0].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[0].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.is_mov invalidate wakeupArbs_0.io.in[0].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[0].bits.uop.is_eret invalidate wakeupArbs_0.io.in[0].bits.uop.is_amo invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[0].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[0].bits.uop.is_fence invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[0].bits.uop.br_type invalidate wakeupArbs_0.io.in[0].bits.uop.br_tag invalidate wakeupArbs_0.io.in[0].bits.uop.br_mask invalidate wakeupArbs_0.io.in[0].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[0].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[0].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[0].bits.uop.inst invalidate wakeupArbs_0.io.in[0].valid invalidate wakeupArbs_0.io.in[0].ready invalidate wakeupArbs_0.io.in[1].bits.rebusy invalidate wakeupArbs_0.io.in[1].bits.speculative_mask invalidate wakeupArbs_0.io.in[1].bits.bypassable invalidate wakeupArbs_0.io.in[1].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[1].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[1].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[1].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[1].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[1].bits.uop.fp_val invalidate wakeupArbs_0.io.in[1].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[1].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[1].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[1].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[1].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[1].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[1].bits.uop.ldst invalidate wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[1].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[1].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[1].bits.uop.is_unique invalidate wakeupArbs_0.io.in[1].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[1].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[1].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[1].bits.uop.mem_size invalidate wakeupArbs_0.io.in[1].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[1].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[1].bits.uop.exception invalidate wakeupArbs_0.io.in[1].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[1].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[1].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[1].bits.uop.ppred invalidate wakeupArbs_0.io.in[1].bits.uop.prs3 invalidate wakeupArbs_0.io.in[1].bits.uop.prs2 invalidate wakeupArbs_0.io.in[1].bits.uop.prs1 invalidate wakeupArbs_0.io.in[1].bits.uop.pdst invalidate wakeupArbs_0.io.in[1].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[1].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[1].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[1].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[1].bits.uop.pimm invalidate wakeupArbs_0.io.in[1].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[1].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[1].bits.uop.taken invalidate wakeupArbs_0.io.in[1].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[1].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[1].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[1].bits.uop.is_mov invalidate wakeupArbs_0.io.in[1].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[1].bits.uop.is_eret invalidate wakeupArbs_0.io.in[1].bits.uop.is_amo invalidate wakeupArbs_0.io.in[1].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[1].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[1].bits.uop.is_fence invalidate wakeupArbs_0.io.in[1].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[1].bits.uop.br_type invalidate wakeupArbs_0.io.in[1].bits.uop.br_tag invalidate wakeupArbs_0.io.in[1].bits.uop.br_mask invalidate wakeupArbs_0.io.in[1].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[1].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[1].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[1].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[1].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[1].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[1].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[1].bits.uop.inst invalidate wakeupArbs_0.io.in[1].valid invalidate wakeupArbs_0.io.in[1].ready connect io.core.iwakeups[0].bits, wakeupArbs_0.io.out.bits connect io.core.iwakeups[0].valid, wakeupArbs_0.io.out.valid node _fired_load_agen_exec_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_load_agen_exec_T_1 = and(will_fire_load_agen_exec[0], _fired_load_agen_exec_T) reg fired_load_agen_exec_REG : UInt<1>, clock connect fired_load_agen_exec_REG, _fired_load_agen_exec_T_1 wire fired_load_agen_exec : UInt<1>[1] connect fired_load_agen_exec[0], fired_load_agen_exec_REG node _fired_load_agen_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_load_agen_T_1 = and(will_fire_load_agen[0], _fired_load_agen_T) reg fired_load_agen_REG : UInt<1>, clock connect fired_load_agen_REG, _fired_load_agen_T_1 wire fired_load_agen : UInt<1>[1] connect fired_load_agen[0], fired_load_agen_REG node _fired_store_agen_T = eq(exe_agen_killed[0], UInt<1>(0h0)) node _fired_store_agen_T_1 = and(will_fire_store_agen[0], _fired_store_agen_T) reg fired_store_agen_REG : UInt<1>, clock connect fired_store_agen_REG, _fired_store_agen_T_1 wire fired_store_agen : UInt<1>[1] connect fired_store_agen[0], fired_store_agen_REG reg fired_sfence : UInt<1>[1], clock connect fired_sfence, will_fire_sfence reg fired_release : UInt<1>[1], clock connect fired_release, will_fire_release node _fired_load_retry_T = and(io.core.brupdate.b1.mispredict_mask, retry_queue.io.deq.bits.uop.br_mask) node _fired_load_retry_T_1 = neq(_fired_load_retry_T, UInt<1>(0h0)) node _fired_load_retry_T_2 = or(_fired_load_retry_T_1, io.core.exception) node _fired_load_retry_T_3 = eq(_fired_load_retry_T_2, UInt<1>(0h0)) node _fired_load_retry_T_4 = and(will_fire_load_retry[0], _fired_load_retry_T_3) reg fired_load_retry_REG : UInt<1>, clock connect fired_load_retry_REG, _fired_load_retry_T_4 wire fired_load_retry : UInt<1>[1] connect fired_load_retry[0], fired_load_retry_REG node _fired_store_retry_T = and(io.core.brupdate.b1.mispredict_mask, retry_queue.io.deq.bits.uop.br_mask) node _fired_store_retry_T_1 = neq(_fired_store_retry_T, UInt<1>(0h0)) node _fired_store_retry_T_2 = or(_fired_store_retry_T_1, io.core.exception) node _fired_store_retry_T_3 = eq(_fired_store_retry_T_2, UInt<1>(0h0)) node _fired_store_retry_T_4 = and(will_fire_store_retry[0], _fired_store_retry_T_3) reg fired_store_retry_REG : UInt<1>, clock connect fired_store_retry_REG, _fired_store_retry_T_4 wire fired_store_retry : UInt<1>[1] connect fired_store_retry[0], fired_store_retry_REG node _fired_store_commit_T = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) reg fired_store_commit_REG : UInt<1>, clock connect fired_store_commit_REG, _fired_store_commit_T wire fired_store_commit : UInt<1>[1] connect fired_store_commit[0], fired_store_commit_REG node _fired_load_wakeup_T = and(io.core.brupdate.b1.mispredict_mask, ldq_wakeup_e.bits.uop.br_mask) node _fired_load_wakeup_T_1 = neq(_fired_load_wakeup_T, UInt<1>(0h0)) node _fired_load_wakeup_T_2 = or(_fired_load_wakeup_T_1, io.core.exception) node _fired_load_wakeup_T_3 = eq(_fired_load_wakeup_T_2, UInt<1>(0h0)) node _fired_load_wakeup_T_4 = and(will_fire_load_wakeup[0], _fired_load_wakeup_T_3) reg fired_load_wakeup_REG : UInt<1>, clock connect fired_load_wakeup_REG, _fired_load_wakeup_T_4 wire fired_load_wakeup : UInt<1>[1] connect fired_load_wakeup[0], fired_load_wakeup_REG reg fired_hella_incoming : UInt<1>[1], clock connect fired_hella_incoming, will_fire_hella_incoming reg fired_hella_wakeup : UInt<1>[1], clock connect fired_hella_wakeup, will_fire_hella_wakeup wire mem_incoming_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect mem_incoming_uop_out, io.core.agen[0].bits.uop node _mem_incoming_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_incoming_uop_out_br_mask_T_1 = and(io.core.agen[0].bits.uop.br_mask, _mem_incoming_uop_out_br_mask_T) connect mem_incoming_uop_out.br_mask, _mem_incoming_uop_out_br_mask_T_1 wire _mem_incoming_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect _mem_incoming_uop_WIRE[0], mem_incoming_uop_out reg mem_incoming_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1], clock connect mem_incoming_uop, _mem_incoming_uop_WIRE wire mem_ldq_incoming_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_incoming_e_out, ldq_incoming_e[0] node _mem_ldq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = and(ldq_incoming_e[0].bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T) connect mem_ldq_incoming_e_out.bits.uop.br_mask, _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 node _mem_ldq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq_incoming_e[0].bits.uop.br_mask) node _mem_ldq_incoming_e_out_valid_T_1 = neq(_mem_ldq_incoming_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_incoming_e_out_valid_T_2 = or(_mem_ldq_incoming_e_out_valid_T_1, io.core.exception) node _mem_ldq_incoming_e_out_valid_T_3 = eq(_mem_ldq_incoming_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_incoming_e_out_valid_T_4 = and(ldq_incoming_e[0].valid, _mem_ldq_incoming_e_out_valid_T_3) connect mem_ldq_incoming_e_out.valid, _mem_ldq_incoming_e_out_valid_T_4 wire _mem_ldq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect _mem_ldq_incoming_e_WIRE[0], mem_ldq_incoming_e_out reg mem_ldq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1], clock connect mem_ldq_incoming_e, _mem_ldq_incoming_e_WIRE wire mem_stq_incoming_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_incoming_e_out, stq_incoming_e[0] node _mem_stq_incoming_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = and(stq_incoming_e[0].bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T) connect mem_stq_incoming_e_out.bits.uop.br_mask, _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 node _mem_stq_incoming_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, stq_incoming_e[0].bits.uop.br_mask) node _mem_stq_incoming_e_out_valid_T_1 = neq(_mem_stq_incoming_e_out_valid_T, UInt<1>(0h0)) node _mem_stq_incoming_e_out_valid_T_2 = or(_mem_stq_incoming_e_out_valid_T_1, io.core.exception) node _mem_stq_incoming_e_out_valid_T_3 = eq(_mem_stq_incoming_e_out_valid_T_2, UInt<1>(0h0)) node _mem_stq_incoming_e_out_valid_T_4 = and(stq_incoming_e[0].valid, _mem_stq_incoming_e_out_valid_T_3) connect mem_stq_incoming_e_out.valid, _mem_stq_incoming_e_out_valid_T_4 wire _mem_stq_incoming_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect _mem_stq_incoming_e_WIRE[0], mem_stq_incoming_e_out reg mem_stq_incoming_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1], clock connect mem_stq_incoming_e, _mem_stq_incoming_e_WIRE wire mem_ldq_wakeup_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_wakeup_e_out, ldq_wakeup_e node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = and(ldq_wakeup_e.bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T) connect mem_ldq_wakeup_e_out.bits.uop.br_mask, _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 node _mem_ldq_wakeup_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, ldq_wakeup_e.bits.uop.br_mask) node _mem_ldq_wakeup_e_out_valid_T_1 = neq(_mem_ldq_wakeup_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_wakeup_e_out_valid_T_2 = or(_mem_ldq_wakeup_e_out_valid_T_1, io.core.exception) node _mem_ldq_wakeup_e_out_valid_T_3 = eq(_mem_ldq_wakeup_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_wakeup_e_out_valid_T_4 = and(ldq_wakeup_e.valid, _mem_ldq_wakeup_e_out_valid_T_3) connect mem_ldq_wakeup_e_out.valid, _mem_ldq_wakeup_e_out_valid_T_4 reg mem_ldq_wakeup_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock connect mem_ldq_wakeup_e, mem_ldq_wakeup_e_out wire mem_ldq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_retry_e_e.valid, ldq_valid[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.uop, ldq_uop[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr, ldq_addr[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.executed, ldq_executed[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.succeeded, ldq_succeeded[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.order_fail, ldq_order_fail[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.observed, ldq_observed[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.st_dep_mask, ldq_st_dep_mask[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.forward_std_val, ldq_forward_std_val[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[retry_queue.io.deq.bits.uop.ldq_idx] connect mem_ldq_retry_e_e.bits.debug_wb_data, ldq_debug_wb_data[retry_queue.io.deq.bits.uop.ldq_idx] wire mem_ldq_retry_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect mem_ldq_retry_e_out, mem_ldq_retry_e_e node _mem_ldq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = and(mem_ldq_retry_e_e.bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T) connect mem_ldq_retry_e_out.bits.uop.br_mask, _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 node _mem_ldq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, mem_ldq_retry_e_e.bits.uop.br_mask) node _mem_ldq_retry_e_out_valid_T_1 = neq(_mem_ldq_retry_e_out_valid_T, UInt<1>(0h0)) node _mem_ldq_retry_e_out_valid_T_2 = or(_mem_ldq_retry_e_out_valid_T_1, io.core.exception) node _mem_ldq_retry_e_out_valid_T_3 = eq(_mem_ldq_retry_e_out_valid_T_2, UInt<1>(0h0)) node _mem_ldq_retry_e_out_valid_T_4 = and(mem_ldq_retry_e_e.valid, _mem_ldq_retry_e_out_valid_T_3) connect mem_ldq_retry_e_out.valid, _mem_ldq_retry_e_out_valid_T_4 reg mem_ldq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}, clock connect mem_ldq_retry_e, mem_ldq_retry_e_out wire mem_stq_retry_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_retry_e_e.valid, stq_valid[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.uop, stq_uop[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.addr, stq_addr[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.addr_is_virtual, stq_addr_is_virtual[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.data, stq_data[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.committed, stq_committed[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.succeeded, stq_succeeded[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.can_execute, stq_can_execute[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.cleared, stq_cleared[retry_queue.io.deq.bits.uop.stq_idx] connect mem_stq_retry_e_e.bits.debug_wb_data, stq_debug_wb_data[retry_queue.io.deq.bits.uop.stq_idx] wire mem_stq_retry_e_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect mem_stq_retry_e_out, mem_stq_retry_e_e node _mem_stq_retry_e_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = and(mem_stq_retry_e_e.bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T) connect mem_stq_retry_e_out.bits.uop.br_mask, _mem_stq_retry_e_out_bits_uop_br_mask_T_1 node _mem_stq_retry_e_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, mem_stq_retry_e_e.bits.uop.br_mask) node _mem_stq_retry_e_out_valid_T_1 = neq(_mem_stq_retry_e_out_valid_T, UInt<1>(0h0)) node _mem_stq_retry_e_out_valid_T_2 = or(_mem_stq_retry_e_out_valid_T_1, io.core.exception) node _mem_stq_retry_e_out_valid_T_3 = eq(_mem_stq_retry_e_out_valid_T_2, UInt<1>(0h0)) node _mem_stq_retry_e_out_valid_T_4 = and(mem_stq_retry_e_e.valid, _mem_stq_retry_e_out_valid_T_3) connect mem_stq_retry_e_out.valid, _mem_stq_retry_e_out_valid_T_4 reg mem_stq_retry_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}, clock connect mem_stq_retry_e, mem_stq_retry_e_out node _mem_ldq_e_T = or(fired_load_agen[0], fired_load_agen_exec[0]) wire _mem_ldq_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} connect _mem_ldq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0) connect _mem_ldq_e_WIRE.bits.forward_stq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.forward_std_val, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.ld_byte_mask, UInt<8>(0h0) connect _mem_ldq_e_WIRE.bits.st_dep_mask, UInt<24>(0h0) connect _mem_ldq_e_WIRE.bits.observed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.order_fail, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.succeeded, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.executed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr_is_uncacheable, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.addr.bits, UInt<40>(0h0) connect _mem_ldq_e_WIRE.bits.addr.valid, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_tsrc, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_fsrc, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_typ, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_rm, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fcn_op, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fcn_dw, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldst, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.csr_cmd, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0) connect _mem_ldq_e_WIRE.bits.uop.exception, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ppred, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs3, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs2, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.prs1, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pdst, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.vec, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.wflags, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.sqrt, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.div, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fma, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fastpipe, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.toint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.fromint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.swap23, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.swap12, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren3, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren2, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ren1, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.wen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fp_ctrl.ldst, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.op2_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.op1_sel, UInt<2>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pimm, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.imm_rename, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.taken, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0) connect _mem_ldq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_mov, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_rocc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_eret, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sfence, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_type, UInt<4>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0) connect _mem_ldq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0) connect _mem_ldq_e_WIRE.bits.uop.dis_col_sel, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p3_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p2_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p1_bypass_hint, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p2_speculative_child, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_p1_speculative_child, UInt<3>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued_partial_dgen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued_partial_agen, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iw_issued, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[0], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[1], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[2], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[3], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[4], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[5], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[6], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[7], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[8], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.fu_code[9], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[0], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[1], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[2], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.iq_type[3], UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0) connect _mem_ldq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0) connect _mem_ldq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0) connect _mem_ldq_e_WIRE.bits.uop.inst, UInt<32>(0h0) connect _mem_ldq_e_WIRE.valid, UInt<1>(0h0) node _mem_ldq_e_T_1 = mux(fired_load_wakeup[0], mem_ldq_wakeup_e, _mem_ldq_e_WIRE) node _mem_ldq_e_T_2 = mux(fired_load_retry[0], mem_ldq_retry_e, _mem_ldq_e_T_1) node _mem_ldq_e_T_3 = mux(_mem_ldq_e_T, mem_ldq_incoming_e[0], _mem_ldq_e_T_2) wire mem_ldq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}}[1] connect mem_ldq_e[0], _mem_ldq_e_T_3 wire _mem_stq_e_WIRE : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}} connect _mem_stq_e_WIRE.bits.debug_wb_data, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.cleared, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.can_execute, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.succeeded, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.committed, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.data.bits, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.data.valid, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.addr_is_virtual, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.addr.bits, UInt<40>(0h0) connect _mem_stq_e_WIRE.bits.addr.valid, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_tsrc, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_fsrc, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.bp_xcpt_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.bp_debug_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_ma_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_ae_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.xcpt_pf_if, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_typ, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_rm, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_val, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fcn_op, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.fcn_dw, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.frs3_en, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs2_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs1_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.dst_rtype, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs3, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs2, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.lrs1, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldst, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldst_is_rs1, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.csr_cmd, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.flush_on_commit, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_unique, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.uses_stq, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.uses_ldq, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_signed, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_size, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.mem_cmd, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.exc_cause, UInt<64>(0h0) connect _mem_stq_e_WIRE.bits.uop.exception, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.stale_pdst, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.ppred_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs3_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs2_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs1_busy, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.ppred, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs3, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs2, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.prs1, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.pdst, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.rxq_idx, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.stq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.ldq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.rob_idx, UInt<7>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.vec, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.wflags, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.sqrt, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.div, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fma, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fastpipe, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.toint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.fromint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.swap23, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.swap12, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren3, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren2, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ren1, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.wen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fp_ctrl.ldst, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.op2_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.op1_sel, UInt<2>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_packed, UInt<20>(0h0) connect _mem_stq_e_WIRE.bits.uop.pimm, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.imm_rename, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.taken, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.pc_lob, UInt<6>(0h0) connect _mem_stq_e_WIRE.bits.uop.edge_inst, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.ftq_idx, UInt<5>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_mov, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_rocc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sys_pc2epc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_eret, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_amo, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sfence, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_fencei, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_fence, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_sfb, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_type, UInt<4>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_tag, UInt<4>(0h0) connect _mem_stq_e_WIRE.bits.uop.br_mask, UInt<16>(0h0) connect _mem_stq_e_WIRE.bits.uop.dis_col_sel, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p3_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p2_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p1_bypass_hint, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p2_speculative_child, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_p1_speculative_child, UInt<3>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued_partial_dgen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued_partial_agen, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iw_issued, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[0], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[1], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[2], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[3], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[4], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[5], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[6], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[7], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[8], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.fu_code[9], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[0], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[1], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[2], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.iq_type[3], UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_pc, UInt<40>(0h0) connect _mem_stq_e_WIRE.bits.uop.is_rvc, UInt<1>(0h0) connect _mem_stq_e_WIRE.bits.uop.debug_inst, UInt<32>(0h0) connect _mem_stq_e_WIRE.bits.uop.inst, UInt<32>(0h0) connect _mem_stq_e_WIRE.valid, UInt<1>(0h0) node _mem_stq_e_T = mux(fired_store_retry[0], mem_stq_retry_e, _mem_stq_e_WIRE) node _mem_stq_e_T_1 = mux(fired_store_agen[0], mem_stq_incoming_e[0], _mem_stq_e_T) wire mem_stq_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, data : { valid : UInt<1>, bits : UInt<64>}, committed : UInt<1>, succeeded : UInt<1>, can_execute : UInt<1>, cleared : UInt<1>, debug_wb_data : UInt<64>}}[1] connect mem_stq_e[0], _mem_stq_e_T_1 reg mem_tlb_miss : UInt<1>[1], clock connect mem_tlb_miss, exe_tlb_miss reg mem_tlb_uncacheable : UInt<1>[1], clock connect mem_tlb_uncacheable, exe_tlb_uncacheable wire _mem_paddr_WIRE : UInt<40>[1] connect _mem_paddr_WIRE[0], dmem_req[0].bits.addr reg mem_paddr : UInt<40>[1], clock connect mem_paddr, _mem_paddr_WIRE node _stq_clr_head_idx_T = eq(stq_cleared[0], UInt<1>(0h0)) node _stq_clr_head_idx_T_1 = and(stq_valid[0], _stq_clr_head_idx_T) node _stq_clr_head_idx_T_2 = eq(stq_cleared[1], UInt<1>(0h0)) node _stq_clr_head_idx_T_3 = and(stq_valid[1], _stq_clr_head_idx_T_2) node _stq_clr_head_idx_T_4 = eq(stq_cleared[2], UInt<1>(0h0)) node _stq_clr_head_idx_T_5 = and(stq_valid[2], _stq_clr_head_idx_T_4) node _stq_clr_head_idx_T_6 = eq(stq_cleared[3], UInt<1>(0h0)) node _stq_clr_head_idx_T_7 = and(stq_valid[3], _stq_clr_head_idx_T_6) node _stq_clr_head_idx_T_8 = eq(stq_cleared[4], UInt<1>(0h0)) node _stq_clr_head_idx_T_9 = and(stq_valid[4], _stq_clr_head_idx_T_8) node _stq_clr_head_idx_T_10 = eq(stq_cleared[5], UInt<1>(0h0)) node _stq_clr_head_idx_T_11 = and(stq_valid[5], _stq_clr_head_idx_T_10) node _stq_clr_head_idx_T_12 = eq(stq_cleared[6], UInt<1>(0h0)) node _stq_clr_head_idx_T_13 = and(stq_valid[6], _stq_clr_head_idx_T_12) node _stq_clr_head_idx_T_14 = eq(stq_cleared[7], UInt<1>(0h0)) node _stq_clr_head_idx_T_15 = and(stq_valid[7], _stq_clr_head_idx_T_14) node _stq_clr_head_idx_T_16 = eq(stq_cleared[8], UInt<1>(0h0)) node _stq_clr_head_idx_T_17 = and(stq_valid[8], _stq_clr_head_idx_T_16) node _stq_clr_head_idx_T_18 = eq(stq_cleared[9], UInt<1>(0h0)) node _stq_clr_head_idx_T_19 = and(stq_valid[9], _stq_clr_head_idx_T_18) node _stq_clr_head_idx_T_20 = eq(stq_cleared[10], UInt<1>(0h0)) node _stq_clr_head_idx_T_21 = and(stq_valid[10], _stq_clr_head_idx_T_20) node _stq_clr_head_idx_T_22 = eq(stq_cleared[11], UInt<1>(0h0)) node _stq_clr_head_idx_T_23 = and(stq_valid[11], _stq_clr_head_idx_T_22) node _stq_clr_head_idx_T_24 = eq(stq_cleared[12], UInt<1>(0h0)) node _stq_clr_head_idx_T_25 = and(stq_valid[12], _stq_clr_head_idx_T_24) node _stq_clr_head_idx_T_26 = eq(stq_cleared[13], UInt<1>(0h0)) node _stq_clr_head_idx_T_27 = and(stq_valid[13], _stq_clr_head_idx_T_26) node _stq_clr_head_idx_T_28 = eq(stq_cleared[14], UInt<1>(0h0)) node _stq_clr_head_idx_T_29 = and(stq_valid[14], _stq_clr_head_idx_T_28) node _stq_clr_head_idx_T_30 = eq(stq_cleared[15], UInt<1>(0h0)) node _stq_clr_head_idx_T_31 = and(stq_valid[15], _stq_clr_head_idx_T_30) node _stq_clr_head_idx_T_32 = eq(stq_cleared[16], UInt<1>(0h0)) node _stq_clr_head_idx_T_33 = and(stq_valid[16], _stq_clr_head_idx_T_32) node _stq_clr_head_idx_T_34 = eq(stq_cleared[17], UInt<1>(0h0)) node _stq_clr_head_idx_T_35 = and(stq_valid[17], _stq_clr_head_idx_T_34) node _stq_clr_head_idx_T_36 = eq(stq_cleared[18], UInt<1>(0h0)) node _stq_clr_head_idx_T_37 = and(stq_valid[18], _stq_clr_head_idx_T_36) node _stq_clr_head_idx_T_38 = eq(stq_cleared[19], UInt<1>(0h0)) node _stq_clr_head_idx_T_39 = and(stq_valid[19], _stq_clr_head_idx_T_38) node _stq_clr_head_idx_T_40 = eq(stq_cleared[20], UInt<1>(0h0)) node _stq_clr_head_idx_T_41 = and(stq_valid[20], _stq_clr_head_idx_T_40) node _stq_clr_head_idx_T_42 = eq(stq_cleared[21], UInt<1>(0h0)) node _stq_clr_head_idx_T_43 = and(stq_valid[21], _stq_clr_head_idx_T_42) node _stq_clr_head_idx_T_44 = eq(stq_cleared[22], UInt<1>(0h0)) node _stq_clr_head_idx_T_45 = and(stq_valid[22], _stq_clr_head_idx_T_44) node _stq_clr_head_idx_T_46 = eq(stq_cleared[23], UInt<1>(0h0)) node _stq_clr_head_idx_T_47 = and(stq_valid[23], _stq_clr_head_idx_T_46) node _stq_clr_head_idx_temp_vec_T = geq(UInt<1>(0h0), stq_commit_head) node stq_clr_head_idx_temp_vec_0 = and(_stq_clr_head_idx_T_1, _stq_clr_head_idx_temp_vec_T) node _stq_clr_head_idx_temp_vec_T_1 = geq(UInt<1>(0h1), stq_commit_head) node stq_clr_head_idx_temp_vec_1 = and(_stq_clr_head_idx_T_3, _stq_clr_head_idx_temp_vec_T_1) node _stq_clr_head_idx_temp_vec_T_2 = geq(UInt<2>(0h2), stq_commit_head) node stq_clr_head_idx_temp_vec_2 = and(_stq_clr_head_idx_T_5, _stq_clr_head_idx_temp_vec_T_2) node _stq_clr_head_idx_temp_vec_T_3 = geq(UInt<2>(0h3), stq_commit_head) node stq_clr_head_idx_temp_vec_3 = and(_stq_clr_head_idx_T_7, _stq_clr_head_idx_temp_vec_T_3) node _stq_clr_head_idx_temp_vec_T_4 = geq(UInt<3>(0h4), stq_commit_head) node stq_clr_head_idx_temp_vec_4 = and(_stq_clr_head_idx_T_9, _stq_clr_head_idx_temp_vec_T_4) node _stq_clr_head_idx_temp_vec_T_5 = geq(UInt<3>(0h5), stq_commit_head) node stq_clr_head_idx_temp_vec_5 = and(_stq_clr_head_idx_T_11, _stq_clr_head_idx_temp_vec_T_5) node _stq_clr_head_idx_temp_vec_T_6 = geq(UInt<3>(0h6), stq_commit_head) node stq_clr_head_idx_temp_vec_6 = and(_stq_clr_head_idx_T_13, _stq_clr_head_idx_temp_vec_T_6) node _stq_clr_head_idx_temp_vec_T_7 = geq(UInt<3>(0h7), stq_commit_head) node stq_clr_head_idx_temp_vec_7 = and(_stq_clr_head_idx_T_15, _stq_clr_head_idx_temp_vec_T_7) node _stq_clr_head_idx_temp_vec_T_8 = geq(UInt<4>(0h8), stq_commit_head) node stq_clr_head_idx_temp_vec_8 = and(_stq_clr_head_idx_T_17, _stq_clr_head_idx_temp_vec_T_8) node _stq_clr_head_idx_temp_vec_T_9 = geq(UInt<4>(0h9), stq_commit_head) node stq_clr_head_idx_temp_vec_9 = and(_stq_clr_head_idx_T_19, _stq_clr_head_idx_temp_vec_T_9) node _stq_clr_head_idx_temp_vec_T_10 = geq(UInt<4>(0ha), stq_commit_head) node stq_clr_head_idx_temp_vec_10 = and(_stq_clr_head_idx_T_21, _stq_clr_head_idx_temp_vec_T_10) node _stq_clr_head_idx_temp_vec_T_11 = geq(UInt<4>(0hb), stq_commit_head) node stq_clr_head_idx_temp_vec_11 = and(_stq_clr_head_idx_T_23, _stq_clr_head_idx_temp_vec_T_11) node _stq_clr_head_idx_temp_vec_T_12 = geq(UInt<4>(0hc), stq_commit_head) node stq_clr_head_idx_temp_vec_12 = and(_stq_clr_head_idx_T_25, _stq_clr_head_idx_temp_vec_T_12) node _stq_clr_head_idx_temp_vec_T_13 = geq(UInt<4>(0hd), stq_commit_head) node stq_clr_head_idx_temp_vec_13 = and(_stq_clr_head_idx_T_27, _stq_clr_head_idx_temp_vec_T_13) node _stq_clr_head_idx_temp_vec_T_14 = geq(UInt<4>(0he), stq_commit_head) node stq_clr_head_idx_temp_vec_14 = and(_stq_clr_head_idx_T_29, _stq_clr_head_idx_temp_vec_T_14) node _stq_clr_head_idx_temp_vec_T_15 = geq(UInt<4>(0hf), stq_commit_head) node stq_clr_head_idx_temp_vec_15 = and(_stq_clr_head_idx_T_31, _stq_clr_head_idx_temp_vec_T_15) node _stq_clr_head_idx_temp_vec_T_16 = geq(UInt<5>(0h10), stq_commit_head) node stq_clr_head_idx_temp_vec_16 = and(_stq_clr_head_idx_T_33, _stq_clr_head_idx_temp_vec_T_16) node _stq_clr_head_idx_temp_vec_T_17 = geq(UInt<5>(0h11), stq_commit_head) node stq_clr_head_idx_temp_vec_17 = and(_stq_clr_head_idx_T_35, _stq_clr_head_idx_temp_vec_T_17) node _stq_clr_head_idx_temp_vec_T_18 = geq(UInt<5>(0h12), stq_commit_head) node stq_clr_head_idx_temp_vec_18 = and(_stq_clr_head_idx_T_37, _stq_clr_head_idx_temp_vec_T_18) node _stq_clr_head_idx_temp_vec_T_19 = geq(UInt<5>(0h13), stq_commit_head) node stq_clr_head_idx_temp_vec_19 = and(_stq_clr_head_idx_T_39, _stq_clr_head_idx_temp_vec_T_19) node _stq_clr_head_idx_temp_vec_T_20 = geq(UInt<5>(0h14), stq_commit_head) node stq_clr_head_idx_temp_vec_20 = and(_stq_clr_head_idx_T_41, _stq_clr_head_idx_temp_vec_T_20) node _stq_clr_head_idx_temp_vec_T_21 = geq(UInt<5>(0h15), stq_commit_head) node stq_clr_head_idx_temp_vec_21 = and(_stq_clr_head_idx_T_43, _stq_clr_head_idx_temp_vec_T_21) node _stq_clr_head_idx_temp_vec_T_22 = geq(UInt<5>(0h16), stq_commit_head) node stq_clr_head_idx_temp_vec_22 = and(_stq_clr_head_idx_T_45, _stq_clr_head_idx_temp_vec_T_22) node _stq_clr_head_idx_temp_vec_T_23 = geq(UInt<5>(0h17), stq_commit_head) node stq_clr_head_idx_temp_vec_23 = and(_stq_clr_head_idx_T_47, _stq_clr_head_idx_temp_vec_T_23) node _stq_clr_head_idx_idx_T = mux(_stq_clr_head_idx_T_45, UInt<6>(0h36), UInt<6>(0h37)) node _stq_clr_head_idx_idx_T_1 = mux(_stq_clr_head_idx_T_43, UInt<6>(0h35), _stq_clr_head_idx_idx_T) node _stq_clr_head_idx_idx_T_2 = mux(_stq_clr_head_idx_T_41, UInt<6>(0h34), _stq_clr_head_idx_idx_T_1) node _stq_clr_head_idx_idx_T_3 = mux(_stq_clr_head_idx_T_39, UInt<6>(0h33), _stq_clr_head_idx_idx_T_2) node _stq_clr_head_idx_idx_T_4 = mux(_stq_clr_head_idx_T_37, UInt<6>(0h32), _stq_clr_head_idx_idx_T_3) node _stq_clr_head_idx_idx_T_5 = mux(_stq_clr_head_idx_T_35, UInt<6>(0h31), _stq_clr_head_idx_idx_T_4) node _stq_clr_head_idx_idx_T_6 = mux(_stq_clr_head_idx_T_33, UInt<6>(0h30), _stq_clr_head_idx_idx_T_5) node _stq_clr_head_idx_idx_T_7 = mux(_stq_clr_head_idx_T_31, UInt<6>(0h2f), _stq_clr_head_idx_idx_T_6) node _stq_clr_head_idx_idx_T_8 = mux(_stq_clr_head_idx_T_29, UInt<6>(0h2e), _stq_clr_head_idx_idx_T_7) node _stq_clr_head_idx_idx_T_9 = mux(_stq_clr_head_idx_T_27, UInt<6>(0h2d), _stq_clr_head_idx_idx_T_8) node _stq_clr_head_idx_idx_T_10 = mux(_stq_clr_head_idx_T_25, UInt<6>(0h2c), _stq_clr_head_idx_idx_T_9) node _stq_clr_head_idx_idx_T_11 = mux(_stq_clr_head_idx_T_23, UInt<6>(0h2b), _stq_clr_head_idx_idx_T_10) node _stq_clr_head_idx_idx_T_12 = mux(_stq_clr_head_idx_T_21, UInt<6>(0h2a), _stq_clr_head_idx_idx_T_11) node _stq_clr_head_idx_idx_T_13 = mux(_stq_clr_head_idx_T_19, UInt<6>(0h29), _stq_clr_head_idx_idx_T_12) node _stq_clr_head_idx_idx_T_14 = mux(_stq_clr_head_idx_T_17, UInt<6>(0h28), _stq_clr_head_idx_idx_T_13) node _stq_clr_head_idx_idx_T_15 = mux(_stq_clr_head_idx_T_15, UInt<6>(0h27), _stq_clr_head_idx_idx_T_14) node _stq_clr_head_idx_idx_T_16 = mux(_stq_clr_head_idx_T_13, UInt<6>(0h26), _stq_clr_head_idx_idx_T_15) node _stq_clr_head_idx_idx_T_17 = mux(_stq_clr_head_idx_T_11, UInt<6>(0h25), _stq_clr_head_idx_idx_T_16) node _stq_clr_head_idx_idx_T_18 = mux(_stq_clr_head_idx_T_9, UInt<6>(0h24), _stq_clr_head_idx_idx_T_17) node _stq_clr_head_idx_idx_T_19 = mux(_stq_clr_head_idx_T_7, UInt<6>(0h23), _stq_clr_head_idx_idx_T_18) node _stq_clr_head_idx_idx_T_20 = mux(_stq_clr_head_idx_T_5, UInt<6>(0h22), _stq_clr_head_idx_idx_T_19) node _stq_clr_head_idx_idx_T_21 = mux(_stq_clr_head_idx_T_3, UInt<6>(0h21), _stq_clr_head_idx_idx_T_20) node _stq_clr_head_idx_idx_T_22 = mux(_stq_clr_head_idx_T_1, UInt<6>(0h20), _stq_clr_head_idx_idx_T_21) node _stq_clr_head_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _stq_clr_head_idx_idx_T_22) node _stq_clr_head_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _stq_clr_head_idx_idx_T_23) node _stq_clr_head_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _stq_clr_head_idx_idx_T_24) node _stq_clr_head_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _stq_clr_head_idx_idx_T_25) node _stq_clr_head_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _stq_clr_head_idx_idx_T_26) node _stq_clr_head_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _stq_clr_head_idx_idx_T_27) node _stq_clr_head_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _stq_clr_head_idx_idx_T_28) node _stq_clr_head_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _stq_clr_head_idx_idx_T_29) node _stq_clr_head_idx_idx_T_31 = mux(stq_clr_head_idx_temp_vec_23, UInt<5>(0h17), _stq_clr_head_idx_idx_T_30) node _stq_clr_head_idx_idx_T_32 = mux(stq_clr_head_idx_temp_vec_22, UInt<5>(0h16), _stq_clr_head_idx_idx_T_31) node _stq_clr_head_idx_idx_T_33 = mux(stq_clr_head_idx_temp_vec_21, UInt<5>(0h15), _stq_clr_head_idx_idx_T_32) node _stq_clr_head_idx_idx_T_34 = mux(stq_clr_head_idx_temp_vec_20, UInt<5>(0h14), _stq_clr_head_idx_idx_T_33) node _stq_clr_head_idx_idx_T_35 = mux(stq_clr_head_idx_temp_vec_19, UInt<5>(0h13), _stq_clr_head_idx_idx_T_34) node _stq_clr_head_idx_idx_T_36 = mux(stq_clr_head_idx_temp_vec_18, UInt<5>(0h12), _stq_clr_head_idx_idx_T_35) node _stq_clr_head_idx_idx_T_37 = mux(stq_clr_head_idx_temp_vec_17, UInt<5>(0h11), _stq_clr_head_idx_idx_T_36) node _stq_clr_head_idx_idx_T_38 = mux(stq_clr_head_idx_temp_vec_16, UInt<5>(0h10), _stq_clr_head_idx_idx_T_37) node _stq_clr_head_idx_idx_T_39 = mux(stq_clr_head_idx_temp_vec_15, UInt<4>(0hf), _stq_clr_head_idx_idx_T_38) node _stq_clr_head_idx_idx_T_40 = mux(stq_clr_head_idx_temp_vec_14, UInt<4>(0he), _stq_clr_head_idx_idx_T_39) node _stq_clr_head_idx_idx_T_41 = mux(stq_clr_head_idx_temp_vec_13, UInt<4>(0hd), _stq_clr_head_idx_idx_T_40) node _stq_clr_head_idx_idx_T_42 = mux(stq_clr_head_idx_temp_vec_12, UInt<4>(0hc), _stq_clr_head_idx_idx_T_41) node _stq_clr_head_idx_idx_T_43 = mux(stq_clr_head_idx_temp_vec_11, UInt<4>(0hb), _stq_clr_head_idx_idx_T_42) node _stq_clr_head_idx_idx_T_44 = mux(stq_clr_head_idx_temp_vec_10, UInt<4>(0ha), _stq_clr_head_idx_idx_T_43) node _stq_clr_head_idx_idx_T_45 = mux(stq_clr_head_idx_temp_vec_9, UInt<4>(0h9), _stq_clr_head_idx_idx_T_44) node _stq_clr_head_idx_idx_T_46 = mux(stq_clr_head_idx_temp_vec_8, UInt<4>(0h8), _stq_clr_head_idx_idx_T_45) node _stq_clr_head_idx_idx_T_47 = mux(stq_clr_head_idx_temp_vec_7, UInt<3>(0h7), _stq_clr_head_idx_idx_T_46) node _stq_clr_head_idx_idx_T_48 = mux(stq_clr_head_idx_temp_vec_6, UInt<3>(0h6), _stq_clr_head_idx_idx_T_47) node _stq_clr_head_idx_idx_T_49 = mux(stq_clr_head_idx_temp_vec_5, UInt<3>(0h5), _stq_clr_head_idx_idx_T_48) node _stq_clr_head_idx_idx_T_50 = mux(stq_clr_head_idx_temp_vec_4, UInt<3>(0h4), _stq_clr_head_idx_idx_T_49) node _stq_clr_head_idx_idx_T_51 = mux(stq_clr_head_idx_temp_vec_3, UInt<2>(0h3), _stq_clr_head_idx_idx_T_50) node _stq_clr_head_idx_idx_T_52 = mux(stq_clr_head_idx_temp_vec_2, UInt<2>(0h2), _stq_clr_head_idx_idx_T_51) node _stq_clr_head_idx_idx_T_53 = mux(stq_clr_head_idx_temp_vec_1, UInt<1>(0h1), _stq_clr_head_idx_idx_T_52) node stq_clr_head_idx_idx = mux(stq_clr_head_idx_temp_vec_0, UInt<1>(0h0), _stq_clr_head_idx_idx_T_53) node _stq_clr_head_idx_T_48 = bits(stq_clr_head_idx_idx, 4, 0) reg stq_clr_head_idx : UInt, clock connect stq_clr_head_idx, _stq_clr_head_idx_T_48 reg clr_valid : UInt<1>, clock connect clr_valid, UInt<1>(0h0) reg clr_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop.br_mask) node _clr_valid_1_T_1 = neq(_clr_valid_1_T, UInt<1>(0h0)) node _clr_valid_1_T_2 = or(_clr_valid_1_T_1, io.core.exception) node _clr_valid_1_T_3 = eq(_clr_valid_1_T_2, UInt<1>(0h0)) node _clr_valid_1_T_4 = and(clr_valid, _clr_valid_1_T_3) reg clr_valid_1 : UInt<1>, clock connect clr_valid_1, _clr_valid_1_T_4 wire clr_uop_1_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out, clr_uop node _clr_uop_1_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_1 = and(clr_uop.br_mask, _clr_uop_1_out_br_mask_T) connect clr_uop_1_out.br_mask, _clr_uop_1_out_br_mask_T_1 reg clr_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1, clr_uop_1_out node _s_uop_T = or(stq_clr_head_idx, UInt<5>(0h0)) node _s_uop_T_1 = bits(_s_uop_T, 4, 0) wire s_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop, stq_uop[_s_uop_T_1] node _T_255 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_256 = bits(_T_255, 4, 0) node _T_257 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_258 = bits(_T_257, 4, 0) node _T_259 = and(stq_valid[_T_256], stq_addr[_T_258].valid) node _T_260 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_261 = bits(_T_260, 4, 0) node _T_262 = and(_T_259, stq_data[_T_261].valid) node _T_263 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_264 = bits(_T_263, 4, 0) node _T_265 = eq(stq_addr_is_virtual[_T_264], UInt<1>(0h0)) node _T_266 = and(_T_262, _T_265) node _T_267 = eq(s_uop.is_amo, UInt<1>(0h0)) node _T_268 = and(_T_266, _T_267) node _T_269 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_270 = bits(_T_269, 4, 0) node _T_271 = eq(stq_cleared[_T_270], UInt<1>(0h0)) node _T_272 = and(_T_268, _T_271) node _T_273 = and(io.core.brupdate.b1.mispredict_mask, s_uop.br_mask) node _T_274 = neq(_T_273, UInt<1>(0h0)) node _T_275 = or(_T_274, io.core.exception) node _T_276 = eq(_T_275, UInt<1>(0h0)) node _T_277 = and(_T_272, _T_276) when _T_277 : connect clr_valid, UInt<1>(0h1) wire clr_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out, s_uop node _clr_uop_out_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_1 = and(s_uop.br_mask, _clr_uop_out_br_mask_T) connect clr_uop_out.br_mask, _clr_uop_out_br_mask_T_1 connect clr_uop, clr_uop_out node _T_278 = or(stq_clr_head_idx, UInt<5>(0h0)) node _T_279 = bits(_T_278, 4, 0) connect stq_cleared[_T_279], UInt<1>(0h1) node _io_core_clr_bsy_0_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1.br_mask) node _io_core_clr_bsy_0_valid_T_1 = neq(_io_core_clr_bsy_0_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_0_valid_T_2 = or(_io_core_clr_bsy_0_valid_T_1, io.core.exception) node _io_core_clr_bsy_0_valid_T_3 = eq(_io_core_clr_bsy_0_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_0_valid_T_4 = and(clr_valid_1, _io_core_clr_bsy_0_valid_T_3) connect io.core.clr_bsy[0].valid, _io_core_clr_bsy_0_valid_T_4 connect io.core.clr_bsy[0].bits, clr_uop_1.rob_idx node wrap_6 = eq(stq_clr_head_idx, UInt<5>(0h17)) node _T_280 = add(stq_clr_head_idx, UInt<1>(0h1)) node _T_281 = tail(_T_280, 1) node _T_282 = mux(wrap_6, UInt<1>(0h0), _T_281) reg clr_valid_2 : UInt<1>, clock connect clr_valid_2, UInt<1>(0h0) reg clr_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T_5 = and(io.core.brupdate.b1.mispredict_mask, clr_uop_2.br_mask) node _clr_valid_1_T_6 = neq(_clr_valid_1_T_5, UInt<1>(0h0)) node _clr_valid_1_T_7 = or(_clr_valid_1_T_6, io.core.exception) node _clr_valid_1_T_8 = eq(_clr_valid_1_T_7, UInt<1>(0h0)) node _clr_valid_1_T_9 = and(clr_valid_2, _clr_valid_1_T_8) reg clr_valid_1_1 : UInt<1>, clock connect clr_valid_1_1, _clr_valid_1_T_9 wire clr_uop_1_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out_1, clr_uop_2 node _clr_uop_1_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_3 = and(clr_uop_2.br_mask, _clr_uop_1_out_br_mask_T_2) connect clr_uop_1_out_1.br_mask, _clr_uop_1_out_br_mask_T_3 reg clr_uop_1_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1_1, clr_uop_1_out_1 node _s_uop_T_2 = or(_T_282, UInt<5>(0h0)) node _s_uop_T_3 = bits(_s_uop_T_2, 4, 0) wire s_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_1, stq_uop[_s_uop_T_3] node _T_283 = or(_T_282, UInt<5>(0h0)) node _T_284 = bits(_T_283, 4, 0) node _T_285 = or(_T_282, UInt<5>(0h0)) node _T_286 = bits(_T_285, 4, 0) node _T_287 = and(stq_valid[_T_284], stq_addr[_T_286].valid) node _T_288 = or(_T_282, UInt<5>(0h0)) node _T_289 = bits(_T_288, 4, 0) node _T_290 = and(_T_287, stq_data[_T_289].valid) node _T_291 = or(_T_282, UInt<5>(0h0)) node _T_292 = bits(_T_291, 4, 0) node _T_293 = eq(stq_addr_is_virtual[_T_292], UInt<1>(0h0)) node _T_294 = and(_T_290, _T_293) node _T_295 = eq(s_uop_1.is_amo, UInt<1>(0h0)) node _T_296 = and(_T_294, _T_295) node _T_297 = or(_T_282, UInt<5>(0h0)) node _T_298 = bits(_T_297, 4, 0) node _T_299 = eq(stq_cleared[_T_298], UInt<1>(0h0)) node _T_300 = and(_T_296, _T_299) node _T_301 = and(io.core.brupdate.b1.mispredict_mask, s_uop_1.br_mask) node _T_302 = neq(_T_301, UInt<1>(0h0)) node _T_303 = or(_T_302, io.core.exception) node _T_304 = eq(_T_303, UInt<1>(0h0)) node _T_305 = and(_T_300, _T_304) when _T_305 : connect clr_valid_2, UInt<1>(0h1) wire clr_uop_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out_1, s_uop_1 node _clr_uop_out_br_mask_T_2 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_3 = and(s_uop_1.br_mask, _clr_uop_out_br_mask_T_2) connect clr_uop_out_1.br_mask, _clr_uop_out_br_mask_T_3 connect clr_uop_2, clr_uop_out_1 node _T_306 = or(_T_282, UInt<5>(0h0)) node _T_307 = bits(_T_306, 4, 0) connect stq_cleared[_T_307], UInt<1>(0h1) node _io_core_clr_bsy_1_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1_1.br_mask) node _io_core_clr_bsy_1_valid_T_1 = neq(_io_core_clr_bsy_1_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_1_valid_T_2 = or(_io_core_clr_bsy_1_valid_T_1, io.core.exception) node _io_core_clr_bsy_1_valid_T_3 = eq(_io_core_clr_bsy_1_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_1_valid_T_4 = and(clr_valid_1_1, _io_core_clr_bsy_1_valid_T_3) connect io.core.clr_bsy[1].valid, _io_core_clr_bsy_1_valid_T_4 connect io.core.clr_bsy[1].bits, clr_uop_1_1.rob_idx node wrap_7 = eq(_T_282, UInt<5>(0h17)) node _T_308 = add(_T_282, UInt<1>(0h1)) node _T_309 = tail(_T_308, 1) node _T_310 = mux(wrap_7, UInt<1>(0h0), _T_309) reg clr_valid_3 : UInt<1>, clock connect clr_valid_3, UInt<1>(0h0) reg clr_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock node _clr_valid_1_T_10 = and(io.core.brupdate.b1.mispredict_mask, clr_uop_3.br_mask) node _clr_valid_1_T_11 = neq(_clr_valid_1_T_10, UInt<1>(0h0)) node _clr_valid_1_T_12 = or(_clr_valid_1_T_11, io.core.exception) node _clr_valid_1_T_13 = eq(_clr_valid_1_T_12, UInt<1>(0h0)) node _clr_valid_1_T_14 = and(clr_valid_3, _clr_valid_1_T_13) reg clr_valid_1_2 : UInt<1>, clock connect clr_valid_1_2, _clr_valid_1_T_14 wire clr_uop_1_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_1_out_2, clr_uop_3 node _clr_uop_1_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_1_out_br_mask_T_5 = and(clr_uop_3.br_mask, _clr_uop_1_out_br_mask_T_4) connect clr_uop_1_out_2.br_mask, _clr_uop_1_out_br_mask_T_5 reg clr_uop_1_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect clr_uop_1_2, clr_uop_1_out_2 node _s_uop_T_4 = or(_T_310, UInt<5>(0h0)) node _s_uop_T_5 = bits(_s_uop_T_4, 4, 0) wire s_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_2, stq_uop[_s_uop_T_5] node _T_311 = or(_T_310, UInt<5>(0h0)) node _T_312 = bits(_T_311, 4, 0) node _T_313 = or(_T_310, UInt<5>(0h0)) node _T_314 = bits(_T_313, 4, 0) node _T_315 = and(stq_valid[_T_312], stq_addr[_T_314].valid) node _T_316 = or(_T_310, UInt<5>(0h0)) node _T_317 = bits(_T_316, 4, 0) node _T_318 = and(_T_315, stq_data[_T_317].valid) node _T_319 = or(_T_310, UInt<5>(0h0)) node _T_320 = bits(_T_319, 4, 0) node _T_321 = eq(stq_addr_is_virtual[_T_320], UInt<1>(0h0)) node _T_322 = and(_T_318, _T_321) node _T_323 = eq(s_uop_2.is_amo, UInt<1>(0h0)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(_T_310, UInt<5>(0h0)) node _T_326 = bits(_T_325, 4, 0) node _T_327 = eq(stq_cleared[_T_326], UInt<1>(0h0)) node _T_328 = and(_T_324, _T_327) node _T_329 = and(io.core.brupdate.b1.mispredict_mask, s_uop_2.br_mask) node _T_330 = neq(_T_329, UInt<1>(0h0)) node _T_331 = or(_T_330, io.core.exception) node _T_332 = eq(_T_331, UInt<1>(0h0)) node _T_333 = and(_T_328, _T_332) when _T_333 : connect clr_valid_3, UInt<1>(0h1) wire clr_uop_out_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect clr_uop_out_2, s_uop_2 node _clr_uop_out_br_mask_T_4 = not(io.core.brupdate.b1.resolve_mask) node _clr_uop_out_br_mask_T_5 = and(s_uop_2.br_mask, _clr_uop_out_br_mask_T_4) connect clr_uop_out_2.br_mask, _clr_uop_out_br_mask_T_5 connect clr_uop_3, clr_uop_out_2 node _T_334 = or(_T_310, UInt<5>(0h0)) node _T_335 = bits(_T_334, 4, 0) connect stq_cleared[_T_335], UInt<1>(0h1) node _io_core_clr_bsy_2_valid_T = and(io.core.brupdate.b1.mispredict_mask, clr_uop_1_2.br_mask) node _io_core_clr_bsy_2_valid_T_1 = neq(_io_core_clr_bsy_2_valid_T, UInt<1>(0h0)) node _io_core_clr_bsy_2_valid_T_2 = or(_io_core_clr_bsy_2_valid_T_1, io.core.exception) node _io_core_clr_bsy_2_valid_T_3 = eq(_io_core_clr_bsy_2_valid_T_2, UInt<1>(0h0)) node _io_core_clr_bsy_2_valid_T_4 = and(clr_valid_1_2, _io_core_clr_bsy_2_valid_T_3) connect io.core.clr_bsy[2].valid, _io_core_clr_bsy_2_valid_T_4 connect io.core.clr_bsy[2].bits, clr_uop_1_2.rob_idx node wrap_8 = eq(_T_310, UInt<5>(0h17)) node _T_336 = add(_T_310, UInt<1>(0h1)) node _T_337 = tail(_T_336, 1) node _T_338 = mux(wrap_8, UInt<1>(0h0), _T_337) node _do_st_search_T = or(fired_store_agen[0], fired_store_retry[0]) node _do_st_search_T_1 = eq(mem_tlb_miss[0], UInt<1>(0h0)) node _do_st_search_T_2 = and(_do_st_search_T, _do_st_search_T_1) wire do_st_search : UInt<1>[1] connect do_st_search[0], _do_st_search_T_2 node _do_ld_search_T = or(fired_load_agen[0], fired_load_agen_exec[0]) node _do_ld_search_T_1 = or(_do_ld_search_T, fired_load_retry[0]) node _do_ld_search_T_2 = eq(mem_tlb_miss[0], UInt<1>(0h0)) node _do_ld_search_T_3 = and(_do_ld_search_T_1, _do_ld_search_T_2) node _do_ld_search_T_4 = or(_do_ld_search_T_3, fired_load_wakeup[0]) wire do_ld_search : UInt<1>[1] connect do_ld_search[0], _do_ld_search_T_4 wire do_release_search : UInt<1>[1] connect do_release_search[0], fired_release[0] node _lcam_addr_T = or(fired_store_agen[0], fired_store_retry[0]) node _lcam_addr_T_1 = or(_lcam_addr_T, fired_load_agen[0]) node _lcam_addr_T_2 = or(_lcam_addr_T_1, fired_load_agen_exec[0]) reg lcam_addr_REG : UInt, clock connect lcam_addr_REG, exe_tlb_paddr[0] reg lcam_addr_REG_1 : UInt, clock connect lcam_addr_REG_1, io.dmem.release.bits.address node _lcam_addr_T_3 = mux(fired_release[0], lcam_addr_REG_1, mem_paddr[0]) node _lcam_addr_T_4 = mux(_lcam_addr_T_2, lcam_addr_REG, _lcam_addr_T_3) wire lcam_addr : UInt[1] connect lcam_addr[0], _lcam_addr_T_4 wire _lcam_uop_WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _lcam_uop_WIRE.debug_tsrc, UInt<3>(0h0) connect _lcam_uop_WIRE.debug_fsrc, UInt<3>(0h0) connect _lcam_uop_WIRE.bp_xcpt_if, UInt<1>(0h0) connect _lcam_uop_WIRE.bp_debug_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_ma_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_ae_if, UInt<1>(0h0) connect _lcam_uop_WIRE.xcpt_pf_if, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_typ, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_rm, UInt<3>(0h0) connect _lcam_uop_WIRE.fp_val, UInt<1>(0h0) connect _lcam_uop_WIRE.fcn_op, UInt<5>(0h0) connect _lcam_uop_WIRE.fcn_dw, UInt<1>(0h0) connect _lcam_uop_WIRE.frs3_en, UInt<1>(0h0) connect _lcam_uop_WIRE.lrs2_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.lrs1_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.dst_rtype, UInt<2>(0h0) connect _lcam_uop_WIRE.lrs3, UInt<6>(0h0) connect _lcam_uop_WIRE.lrs2, UInt<6>(0h0) connect _lcam_uop_WIRE.lrs1, UInt<6>(0h0) connect _lcam_uop_WIRE.ldst, UInt<6>(0h0) connect _lcam_uop_WIRE.ldst_is_rs1, UInt<1>(0h0) connect _lcam_uop_WIRE.csr_cmd, UInt<3>(0h0) connect _lcam_uop_WIRE.flush_on_commit, UInt<1>(0h0) connect _lcam_uop_WIRE.is_unique, UInt<1>(0h0) connect _lcam_uop_WIRE.uses_stq, UInt<1>(0h0) connect _lcam_uop_WIRE.uses_ldq, UInt<1>(0h0) connect _lcam_uop_WIRE.mem_signed, UInt<1>(0h0) connect _lcam_uop_WIRE.mem_size, UInt<2>(0h0) connect _lcam_uop_WIRE.mem_cmd, UInt<5>(0h0) connect _lcam_uop_WIRE.exc_cause, UInt<64>(0h0) connect _lcam_uop_WIRE.exception, UInt<1>(0h0) connect _lcam_uop_WIRE.stale_pdst, UInt<7>(0h0) connect _lcam_uop_WIRE.ppred_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs3_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs2_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.prs1_busy, UInt<1>(0h0) connect _lcam_uop_WIRE.ppred, UInt<5>(0h0) connect _lcam_uop_WIRE.prs3, UInt<7>(0h0) connect _lcam_uop_WIRE.prs2, UInt<7>(0h0) connect _lcam_uop_WIRE.prs1, UInt<7>(0h0) connect _lcam_uop_WIRE.pdst, UInt<7>(0h0) connect _lcam_uop_WIRE.rxq_idx, UInt<2>(0h0) connect _lcam_uop_WIRE.stq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.ldq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.rob_idx, UInt<7>(0h0) connect _lcam_uop_WIRE.fp_ctrl.vec, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.wflags, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.sqrt, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.div, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fma, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fastpipe, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.toint, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.fromint, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.typeTagOut, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_ctrl.typeTagIn, UInt<2>(0h0) connect _lcam_uop_WIRE.fp_ctrl.swap23, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.swap12, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren3, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren2, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ren1, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.wen, UInt<1>(0h0) connect _lcam_uop_WIRE.fp_ctrl.ldst, UInt<1>(0h0) connect _lcam_uop_WIRE.op2_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.op1_sel, UInt<2>(0h0) connect _lcam_uop_WIRE.imm_packed, UInt<20>(0h0) connect _lcam_uop_WIRE.pimm, UInt<5>(0h0) connect _lcam_uop_WIRE.imm_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.imm_rename, UInt<1>(0h0) connect _lcam_uop_WIRE.taken, UInt<1>(0h0) connect _lcam_uop_WIRE.pc_lob, UInt<6>(0h0) connect _lcam_uop_WIRE.edge_inst, UInt<1>(0h0) connect _lcam_uop_WIRE.ftq_idx, UInt<5>(0h0) connect _lcam_uop_WIRE.is_mov, UInt<1>(0h0) connect _lcam_uop_WIRE.is_rocc, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sys_pc2epc, UInt<1>(0h0) connect _lcam_uop_WIRE.is_eret, UInt<1>(0h0) connect _lcam_uop_WIRE.is_amo, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sfence, UInt<1>(0h0) connect _lcam_uop_WIRE.is_fencei, UInt<1>(0h0) connect _lcam_uop_WIRE.is_fence, UInt<1>(0h0) connect _lcam_uop_WIRE.is_sfb, UInt<1>(0h0) connect _lcam_uop_WIRE.br_type, UInt<4>(0h0) connect _lcam_uop_WIRE.br_tag, UInt<4>(0h0) connect _lcam_uop_WIRE.br_mask, UInt<16>(0h0) connect _lcam_uop_WIRE.dis_col_sel, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_p3_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_p2_speculative_child, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_p1_speculative_child, UInt<3>(0h0) connect _lcam_uop_WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _lcam_uop_WIRE.iw_issued, UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[0], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[1], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[2], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[3], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[4], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[5], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[6], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[7], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[8], UInt<1>(0h0) connect _lcam_uop_WIRE.fu_code[9], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[0], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[1], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[2], UInt<1>(0h0) connect _lcam_uop_WIRE.iq_type[3], UInt<1>(0h0) connect _lcam_uop_WIRE.debug_pc, UInt<40>(0h0) connect _lcam_uop_WIRE.is_rvc, UInt<1>(0h0) connect _lcam_uop_WIRE.debug_inst, UInt<32>(0h0) connect _lcam_uop_WIRE.inst, UInt<32>(0h0) node _lcam_uop_T = mux(do_ld_search[0], mem_ldq_e[0].bits.uop, _lcam_uop_WIRE) node _lcam_uop_T_1 = mux(do_st_search[0], mem_stq_e[0].bits.uop, _lcam_uop_T) wire lcam_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[1] connect lcam_uop[0], _lcam_uop_T_1 wire lcam_mask_mask : UInt<8> node _lcam_mask_mask_T = eq(lcam_uop[0].mem_size, UInt<1>(0h0)) node _lcam_mask_mask_T_1 = bits(lcam_addr[0], 2, 0) node _lcam_mask_mask_T_2 = dshl(UInt<8>(0h1), _lcam_mask_mask_T_1) node _lcam_mask_mask_T_3 = eq(lcam_uop[0].mem_size, UInt<1>(0h1)) node _lcam_mask_mask_T_4 = bits(lcam_addr[0], 2, 1) node _lcam_mask_mask_T_5 = dshl(_lcam_mask_mask_T_4, UInt<1>(0h1)) node _lcam_mask_mask_T_6 = dshl(UInt<8>(0h3), _lcam_mask_mask_T_5) node _lcam_mask_mask_T_7 = eq(lcam_uop[0].mem_size, UInt<2>(0h2)) node _lcam_mask_mask_T_8 = bits(lcam_addr[0], 2, 2) node _lcam_mask_mask_T_9 = mux(_lcam_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _lcam_mask_mask_T_10 = eq(lcam_uop[0].mem_size, UInt<2>(0h3)) node _lcam_mask_mask_T_11 = mux(_lcam_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _lcam_mask_mask_T_12 = mux(_lcam_mask_mask_T_7, _lcam_mask_mask_T_9, _lcam_mask_mask_T_11) node _lcam_mask_mask_T_13 = mux(_lcam_mask_mask_T_3, _lcam_mask_mask_T_6, _lcam_mask_mask_T_12) node _lcam_mask_mask_T_14 = mux(_lcam_mask_mask_T, _lcam_mask_mask_T_2, _lcam_mask_mask_T_13) connect lcam_mask_mask, _lcam_mask_mask_T_14 wire lcam_mask : UInt<8>[1] connect lcam_mask[0], lcam_mask_mask wire lcam_st_dep_mask : UInt<24>[1] connect lcam_st_dep_mask[0], mem_ldq_e[0].bits.st_dep_mask wire lcam_is_release : UInt<1>[1] connect lcam_is_release[0], fired_release[0] node _lcam_ldq_idx_T = or(fired_load_agen[0], fired_load_agen_exec[0]) reg lcam_ldq_idx_REG : UInt, clock connect lcam_ldq_idx_REG, ldq_wakeup_idx reg lcam_ldq_idx_REG_1 : UInt, clock connect lcam_ldq_idx_REG_1, retry_queue.io.deq.bits.uop.ldq_idx node _lcam_ldq_idx_T_1 = mux(fired_load_retry[0], lcam_ldq_idx_REG_1, UInt<1>(0h0)) node _lcam_ldq_idx_T_2 = mux(fired_load_wakeup[0], lcam_ldq_idx_REG, _lcam_ldq_idx_T_1) node _lcam_ldq_idx_T_3 = mux(_lcam_ldq_idx_T, mem_incoming_uop[0].ldq_idx, _lcam_ldq_idx_T_2) wire lcam_ldq_idx : UInt[1] connect lcam_ldq_idx[0], _lcam_ldq_idx_T_3 reg lcam_stq_idx_REG : UInt, clock connect lcam_stq_idx_REG, retry_queue.io.deq.bits.uop.stq_idx node _lcam_stq_idx_T = mux(fired_store_retry[0], lcam_stq_idx_REG, UInt<1>(0h0)) node _lcam_stq_idx_T_1 = mux(fired_store_agen[0], mem_incoming_uop[0].stq_idx, _lcam_stq_idx_T) wire lcam_stq_idx : UInt[1] connect lcam_stq_idx[0], _lcam_stq_idx_T_1 node _lcam_younger_load_mask_hi_mask_T = dshl(UInt<1>(0h1), lcam_ldq_idx[0]) node _lcam_younger_load_mask_hi_mask_T_1 = bits(_lcam_younger_load_mask_hi_mask_T, 23, 0) node _lcam_younger_load_mask_hi_mask_T_2 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<1>(0h0)) node _lcam_younger_load_mask_hi_mask_T_3 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<1>(0h1)) node _lcam_younger_load_mask_hi_mask_T_4 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<2>(0h2)) node _lcam_younger_load_mask_hi_mask_T_5 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<2>(0h3)) node _lcam_younger_load_mask_hi_mask_T_6 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h4)) node _lcam_younger_load_mask_hi_mask_T_7 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h5)) node _lcam_younger_load_mask_hi_mask_T_8 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h6)) node _lcam_younger_load_mask_hi_mask_T_9 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<3>(0h7)) node _lcam_younger_load_mask_hi_mask_T_10 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0h8)) node _lcam_younger_load_mask_hi_mask_T_11 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0h9)) node _lcam_younger_load_mask_hi_mask_T_12 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0ha)) node _lcam_younger_load_mask_hi_mask_T_13 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hb)) node _lcam_younger_load_mask_hi_mask_T_14 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hc)) node _lcam_younger_load_mask_hi_mask_T_15 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hd)) node _lcam_younger_load_mask_hi_mask_T_16 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0he)) node _lcam_younger_load_mask_hi_mask_T_17 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<4>(0hf)) node _lcam_younger_load_mask_hi_mask_T_18 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h10)) node _lcam_younger_load_mask_hi_mask_T_19 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h11)) node _lcam_younger_load_mask_hi_mask_T_20 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h12)) node _lcam_younger_load_mask_hi_mask_T_21 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h13)) node _lcam_younger_load_mask_hi_mask_T_22 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h14)) node _lcam_younger_load_mask_hi_mask_T_23 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h15)) node _lcam_younger_load_mask_hi_mask_T_24 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h16)) node _lcam_younger_load_mask_hi_mask_T_25 = dshr(_lcam_younger_load_mask_hi_mask_T_1, UInt<5>(0h17)) node _lcam_younger_load_mask_hi_mask_T_26 = or(_lcam_younger_load_mask_hi_mask_T_2, _lcam_younger_load_mask_hi_mask_T_3) node _lcam_younger_load_mask_hi_mask_T_27 = or(_lcam_younger_load_mask_hi_mask_T_26, _lcam_younger_load_mask_hi_mask_T_4) node _lcam_younger_load_mask_hi_mask_T_28 = or(_lcam_younger_load_mask_hi_mask_T_27, _lcam_younger_load_mask_hi_mask_T_5) node _lcam_younger_load_mask_hi_mask_T_29 = or(_lcam_younger_load_mask_hi_mask_T_28, _lcam_younger_load_mask_hi_mask_T_6) node _lcam_younger_load_mask_hi_mask_T_30 = or(_lcam_younger_load_mask_hi_mask_T_29, _lcam_younger_load_mask_hi_mask_T_7) node _lcam_younger_load_mask_hi_mask_T_31 = or(_lcam_younger_load_mask_hi_mask_T_30, _lcam_younger_load_mask_hi_mask_T_8) node _lcam_younger_load_mask_hi_mask_T_32 = or(_lcam_younger_load_mask_hi_mask_T_31, _lcam_younger_load_mask_hi_mask_T_9) node _lcam_younger_load_mask_hi_mask_T_33 = or(_lcam_younger_load_mask_hi_mask_T_32, _lcam_younger_load_mask_hi_mask_T_10) node _lcam_younger_load_mask_hi_mask_T_34 = or(_lcam_younger_load_mask_hi_mask_T_33, _lcam_younger_load_mask_hi_mask_T_11) node _lcam_younger_load_mask_hi_mask_T_35 = or(_lcam_younger_load_mask_hi_mask_T_34, _lcam_younger_load_mask_hi_mask_T_12) node _lcam_younger_load_mask_hi_mask_T_36 = or(_lcam_younger_load_mask_hi_mask_T_35, _lcam_younger_load_mask_hi_mask_T_13) node _lcam_younger_load_mask_hi_mask_T_37 = or(_lcam_younger_load_mask_hi_mask_T_36, _lcam_younger_load_mask_hi_mask_T_14) node _lcam_younger_load_mask_hi_mask_T_38 = or(_lcam_younger_load_mask_hi_mask_T_37, _lcam_younger_load_mask_hi_mask_T_15) node _lcam_younger_load_mask_hi_mask_T_39 = or(_lcam_younger_load_mask_hi_mask_T_38, _lcam_younger_load_mask_hi_mask_T_16) node _lcam_younger_load_mask_hi_mask_T_40 = or(_lcam_younger_load_mask_hi_mask_T_39, _lcam_younger_load_mask_hi_mask_T_17) node _lcam_younger_load_mask_hi_mask_T_41 = or(_lcam_younger_load_mask_hi_mask_T_40, _lcam_younger_load_mask_hi_mask_T_18) node _lcam_younger_load_mask_hi_mask_T_42 = or(_lcam_younger_load_mask_hi_mask_T_41, _lcam_younger_load_mask_hi_mask_T_19) node _lcam_younger_load_mask_hi_mask_T_43 = or(_lcam_younger_load_mask_hi_mask_T_42, _lcam_younger_load_mask_hi_mask_T_20) node _lcam_younger_load_mask_hi_mask_T_44 = or(_lcam_younger_load_mask_hi_mask_T_43, _lcam_younger_load_mask_hi_mask_T_21) node _lcam_younger_load_mask_hi_mask_T_45 = or(_lcam_younger_load_mask_hi_mask_T_44, _lcam_younger_load_mask_hi_mask_T_22) node _lcam_younger_load_mask_hi_mask_T_46 = or(_lcam_younger_load_mask_hi_mask_T_45, _lcam_younger_load_mask_hi_mask_T_23) node _lcam_younger_load_mask_hi_mask_T_47 = or(_lcam_younger_load_mask_hi_mask_T_46, _lcam_younger_load_mask_hi_mask_T_24) node _lcam_younger_load_mask_hi_mask_T_48 = or(_lcam_younger_load_mask_hi_mask_T_47, _lcam_younger_load_mask_hi_mask_T_25) node lcam_younger_load_mask_hi_mask = not(_lcam_younger_load_mask_hi_mask_T_48) node _lcam_younger_load_mask_lo_mask_T = dshl(UInt<1>(0h1), ldq_head) node _lcam_younger_load_mask_lo_mask_T_1 = bits(_lcam_younger_load_mask_lo_mask_T, 23, 0) node _lcam_younger_load_mask_lo_mask_T_2 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<1>(0h0)) node _lcam_younger_load_mask_lo_mask_T_3 = bits(_lcam_younger_load_mask_lo_mask_T_2, 23, 0) node _lcam_younger_load_mask_lo_mask_T_4 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<1>(0h1)) node _lcam_younger_load_mask_lo_mask_T_5 = bits(_lcam_younger_load_mask_lo_mask_T_4, 23, 0) node _lcam_younger_load_mask_lo_mask_T_6 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<2>(0h2)) node _lcam_younger_load_mask_lo_mask_T_7 = bits(_lcam_younger_load_mask_lo_mask_T_6, 23, 0) node _lcam_younger_load_mask_lo_mask_T_8 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<2>(0h3)) node _lcam_younger_load_mask_lo_mask_T_9 = bits(_lcam_younger_load_mask_lo_mask_T_8, 23, 0) node _lcam_younger_load_mask_lo_mask_T_10 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h4)) node _lcam_younger_load_mask_lo_mask_T_11 = bits(_lcam_younger_load_mask_lo_mask_T_10, 23, 0) node _lcam_younger_load_mask_lo_mask_T_12 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h5)) node _lcam_younger_load_mask_lo_mask_T_13 = bits(_lcam_younger_load_mask_lo_mask_T_12, 23, 0) node _lcam_younger_load_mask_lo_mask_T_14 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h6)) node _lcam_younger_load_mask_lo_mask_T_15 = bits(_lcam_younger_load_mask_lo_mask_T_14, 23, 0) node _lcam_younger_load_mask_lo_mask_T_16 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<3>(0h7)) node _lcam_younger_load_mask_lo_mask_T_17 = bits(_lcam_younger_load_mask_lo_mask_T_16, 23, 0) node _lcam_younger_load_mask_lo_mask_T_18 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0h8)) node _lcam_younger_load_mask_lo_mask_T_19 = bits(_lcam_younger_load_mask_lo_mask_T_18, 23, 0) node _lcam_younger_load_mask_lo_mask_T_20 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0h9)) node _lcam_younger_load_mask_lo_mask_T_21 = bits(_lcam_younger_load_mask_lo_mask_T_20, 23, 0) node _lcam_younger_load_mask_lo_mask_T_22 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0ha)) node _lcam_younger_load_mask_lo_mask_T_23 = bits(_lcam_younger_load_mask_lo_mask_T_22, 23, 0) node _lcam_younger_load_mask_lo_mask_T_24 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hb)) node _lcam_younger_load_mask_lo_mask_T_25 = bits(_lcam_younger_load_mask_lo_mask_T_24, 23, 0) node _lcam_younger_load_mask_lo_mask_T_26 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hc)) node _lcam_younger_load_mask_lo_mask_T_27 = bits(_lcam_younger_load_mask_lo_mask_T_26, 23, 0) node _lcam_younger_load_mask_lo_mask_T_28 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hd)) node _lcam_younger_load_mask_lo_mask_T_29 = bits(_lcam_younger_load_mask_lo_mask_T_28, 23, 0) node _lcam_younger_load_mask_lo_mask_T_30 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0he)) node _lcam_younger_load_mask_lo_mask_T_31 = bits(_lcam_younger_load_mask_lo_mask_T_30, 23, 0) node _lcam_younger_load_mask_lo_mask_T_32 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<4>(0hf)) node _lcam_younger_load_mask_lo_mask_T_33 = bits(_lcam_younger_load_mask_lo_mask_T_32, 23, 0) node _lcam_younger_load_mask_lo_mask_T_34 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h10)) node _lcam_younger_load_mask_lo_mask_T_35 = bits(_lcam_younger_load_mask_lo_mask_T_34, 23, 0) node _lcam_younger_load_mask_lo_mask_T_36 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h11)) node _lcam_younger_load_mask_lo_mask_T_37 = bits(_lcam_younger_load_mask_lo_mask_T_36, 23, 0) node _lcam_younger_load_mask_lo_mask_T_38 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h12)) node _lcam_younger_load_mask_lo_mask_T_39 = bits(_lcam_younger_load_mask_lo_mask_T_38, 23, 0) node _lcam_younger_load_mask_lo_mask_T_40 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h13)) node _lcam_younger_load_mask_lo_mask_T_41 = bits(_lcam_younger_load_mask_lo_mask_T_40, 23, 0) node _lcam_younger_load_mask_lo_mask_T_42 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h14)) node _lcam_younger_load_mask_lo_mask_T_43 = bits(_lcam_younger_load_mask_lo_mask_T_42, 23, 0) node _lcam_younger_load_mask_lo_mask_T_44 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h15)) node _lcam_younger_load_mask_lo_mask_T_45 = bits(_lcam_younger_load_mask_lo_mask_T_44, 23, 0) node _lcam_younger_load_mask_lo_mask_T_46 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h16)) node _lcam_younger_load_mask_lo_mask_T_47 = bits(_lcam_younger_load_mask_lo_mask_T_46, 23, 0) node _lcam_younger_load_mask_lo_mask_T_48 = dshl(_lcam_younger_load_mask_lo_mask_T_1, UInt<5>(0h17)) node _lcam_younger_load_mask_lo_mask_T_49 = bits(_lcam_younger_load_mask_lo_mask_T_48, 23, 0) node _lcam_younger_load_mask_lo_mask_T_50 = or(_lcam_younger_load_mask_lo_mask_T_3, _lcam_younger_load_mask_lo_mask_T_5) node _lcam_younger_load_mask_lo_mask_T_51 = or(_lcam_younger_load_mask_lo_mask_T_50, _lcam_younger_load_mask_lo_mask_T_7) node _lcam_younger_load_mask_lo_mask_T_52 = or(_lcam_younger_load_mask_lo_mask_T_51, _lcam_younger_load_mask_lo_mask_T_9) node _lcam_younger_load_mask_lo_mask_T_53 = or(_lcam_younger_load_mask_lo_mask_T_52, _lcam_younger_load_mask_lo_mask_T_11) node _lcam_younger_load_mask_lo_mask_T_54 = or(_lcam_younger_load_mask_lo_mask_T_53, _lcam_younger_load_mask_lo_mask_T_13) node _lcam_younger_load_mask_lo_mask_T_55 = or(_lcam_younger_load_mask_lo_mask_T_54, _lcam_younger_load_mask_lo_mask_T_15) node _lcam_younger_load_mask_lo_mask_T_56 = or(_lcam_younger_load_mask_lo_mask_T_55, _lcam_younger_load_mask_lo_mask_T_17) node _lcam_younger_load_mask_lo_mask_T_57 = or(_lcam_younger_load_mask_lo_mask_T_56, _lcam_younger_load_mask_lo_mask_T_19) node _lcam_younger_load_mask_lo_mask_T_58 = or(_lcam_younger_load_mask_lo_mask_T_57, _lcam_younger_load_mask_lo_mask_T_21) node _lcam_younger_load_mask_lo_mask_T_59 = or(_lcam_younger_load_mask_lo_mask_T_58, _lcam_younger_load_mask_lo_mask_T_23) node _lcam_younger_load_mask_lo_mask_T_60 = or(_lcam_younger_load_mask_lo_mask_T_59, _lcam_younger_load_mask_lo_mask_T_25) node _lcam_younger_load_mask_lo_mask_T_61 = or(_lcam_younger_load_mask_lo_mask_T_60, _lcam_younger_load_mask_lo_mask_T_27) node _lcam_younger_load_mask_lo_mask_T_62 = or(_lcam_younger_load_mask_lo_mask_T_61, _lcam_younger_load_mask_lo_mask_T_29) node _lcam_younger_load_mask_lo_mask_T_63 = or(_lcam_younger_load_mask_lo_mask_T_62, _lcam_younger_load_mask_lo_mask_T_31) node _lcam_younger_load_mask_lo_mask_T_64 = or(_lcam_younger_load_mask_lo_mask_T_63, _lcam_younger_load_mask_lo_mask_T_33) node _lcam_younger_load_mask_lo_mask_T_65 = or(_lcam_younger_load_mask_lo_mask_T_64, _lcam_younger_load_mask_lo_mask_T_35) node _lcam_younger_load_mask_lo_mask_T_66 = or(_lcam_younger_load_mask_lo_mask_T_65, _lcam_younger_load_mask_lo_mask_T_37) node _lcam_younger_load_mask_lo_mask_T_67 = or(_lcam_younger_load_mask_lo_mask_T_66, _lcam_younger_load_mask_lo_mask_T_39) node _lcam_younger_load_mask_lo_mask_T_68 = or(_lcam_younger_load_mask_lo_mask_T_67, _lcam_younger_load_mask_lo_mask_T_41) node _lcam_younger_load_mask_lo_mask_T_69 = or(_lcam_younger_load_mask_lo_mask_T_68, _lcam_younger_load_mask_lo_mask_T_43) node _lcam_younger_load_mask_lo_mask_T_70 = or(_lcam_younger_load_mask_lo_mask_T_69, _lcam_younger_load_mask_lo_mask_T_45) node _lcam_younger_load_mask_lo_mask_T_71 = or(_lcam_younger_load_mask_lo_mask_T_70, _lcam_younger_load_mask_lo_mask_T_47) node _lcam_younger_load_mask_lo_mask_T_72 = or(_lcam_younger_load_mask_lo_mask_T_71, _lcam_younger_load_mask_lo_mask_T_49) node lcam_younger_load_mask_lo_mask = not(_lcam_younger_load_mask_lo_mask_T_72) node _lcam_younger_load_mask_T = lt(lcam_ldq_idx[0], ldq_head) node _lcam_younger_load_mask_T_1 = and(lcam_younger_load_mask_hi_mask, lcam_younger_load_mask_lo_mask) node _lcam_younger_load_mask_T_2 = or(lcam_younger_load_mask_hi_mask, lcam_younger_load_mask_lo_mask) node _lcam_younger_load_mask_T_3 = mux(_lcam_younger_load_mask_T, _lcam_younger_load_mask_T_1, _lcam_younger_load_mask_T_2) node _lcam_younger_load_mask_T_4 = bits(_lcam_younger_load_mask_T_3, 23, 0) wire lcam_younger_load_mask : UInt<24>[1] connect lcam_younger_load_mask[0], _lcam_younger_load_mask_T_4 node _can_forward_T = or(fired_load_agen[0], fired_load_agen_exec[0]) node _can_forward_T_1 = or(_can_forward_T, fired_load_retry[0]) node _can_forward_T_2 = eq(mem_tlb_uncacheable[0], UInt<1>(0h0)) node _can_forward_T_3 = eq(mem_ldq_wakeup_e.bits.addr_is_uncacheable, UInt<1>(0h0)) node _can_forward_T_4 = mux(_can_forward_T_1, _can_forward_T_2, _can_forward_T_3) wire can_forward : UInt<1>[1] connect can_forward[0], _can_forward_T_4 wire _kill_forward_WIRE : UInt<1>[1] connect _kill_forward_WIRE[0], UInt<1>(0h0) wire kill_forward : UInt<1>[1] connect kill_forward, _kill_forward_WIRE wire ldst_addr_matches : UInt<24>[1] wire ldst_forward_matches : UInt<24>[1] wire stld_prs2_matches : UInt<24>[1] reg s1_executing_loads : UInt<1>[24], clock connect s1_executing_loads, s0_executing_loads wire s1_set_execute : UInt<1>[24] connect s1_set_execute, s1_executing_loads reg wb_ldst_forward_matches : UInt<24>[1], clock connect wb_ldst_forward_matches, ldst_forward_matches wire wb_ldst_forward_valid : UInt<1>[1] wire wb_ldst_forward_e_e : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}} node _wb_ldst_forward_e_e_valid_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_valid_T_1 = bits(_wb_ldst_forward_e_e_valid_T, 4, 0) connect wb_ldst_forward_e_e.valid, ldq_valid[_wb_ldst_forward_e_e_valid_T_1] node _wb_ldst_forward_e_e_bits_uop_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_uop_T_1 = bits(_wb_ldst_forward_e_e_bits_uop_T, 4, 0) connect wb_ldst_forward_e_e.bits.uop, ldq_uop[_wb_ldst_forward_e_e_bits_uop_T_1] node _wb_ldst_forward_e_e_bits_addr_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr, ldq_addr[_wb_ldst_forward_e_e_bits_addr_T_1] node _wb_ldst_forward_e_e_bits_addr_is_virtual_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_is_virtual_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr_is_virtual, ldq_addr_is_virtual[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1] node _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = bits(_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T, 4, 0) connect wb_ldst_forward_e_e.bits.addr_is_uncacheable, ldq_addr_is_uncacheable[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1] node _wb_ldst_forward_e_e_bits_executed_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_executed_T_1 = bits(_wb_ldst_forward_e_e_bits_executed_T, 4, 0) connect wb_ldst_forward_e_e.bits.executed, ldq_executed[_wb_ldst_forward_e_e_bits_executed_T_1] node _wb_ldst_forward_e_e_bits_succeeded_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_succeeded_T_1 = bits(_wb_ldst_forward_e_e_bits_succeeded_T, 4, 0) connect wb_ldst_forward_e_e.bits.succeeded, ldq_succeeded[_wb_ldst_forward_e_e_bits_succeeded_T_1] node _wb_ldst_forward_e_e_bits_order_fail_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_order_fail_T_1 = bits(_wb_ldst_forward_e_e_bits_order_fail_T, 4, 0) connect wb_ldst_forward_e_e.bits.order_fail, ldq_order_fail[_wb_ldst_forward_e_e_bits_order_fail_T_1] node _wb_ldst_forward_e_e_bits_observed_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_observed_T_1 = bits(_wb_ldst_forward_e_e_bits_observed_T, 4, 0) connect wb_ldst_forward_e_e.bits.observed, ldq_observed[_wb_ldst_forward_e_e_bits_observed_T_1] node _wb_ldst_forward_e_e_bits_st_dep_mask_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = bits(_wb_ldst_forward_e_e_bits_st_dep_mask_T, 4, 0) connect wb_ldst_forward_e_e.bits.st_dep_mask, ldq_st_dep_mask[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1] node _wb_ldst_forward_e_e_bits_ld_byte_mask_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = bits(_wb_ldst_forward_e_e_bits_ld_byte_mask_T, 4, 0) connect wb_ldst_forward_e_e.bits.ld_byte_mask, ldq_ld_byte_mask[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1] node _wb_ldst_forward_e_e_bits_forward_std_val_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = bits(_wb_ldst_forward_e_e_bits_forward_std_val_T, 4, 0) connect wb_ldst_forward_e_e.bits.forward_std_val, ldq_forward_std_val[_wb_ldst_forward_e_e_bits_forward_std_val_T_1] node _wb_ldst_forward_e_e_bits_forward_stq_idx_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = bits(_wb_ldst_forward_e_e_bits_forward_stq_idx_T, 4, 0) connect wb_ldst_forward_e_e.bits.forward_stq_idx, ldq_forward_stq_idx[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1] node _wb_ldst_forward_e_e_bits_debug_wb_data_T = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = bits(_wb_ldst_forward_e_e_bits_debug_wb_data_T, 4, 0) connect wb_ldst_forward_e_e.bits.debug_wb_data, ldq_debug_wb_data[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1] wire wb_ldst_forward_e_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>} connect wb_ldst_forward_e_out, wb_ldst_forward_e_e.bits node _wb_ldst_forward_e_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _wb_ldst_forward_e_out_uop_br_mask_T_1 = and(wb_ldst_forward_e_e.bits.uop.br_mask, _wb_ldst_forward_e_out_uop_br_mask_T) connect wb_ldst_forward_e_out.uop.br_mask, _wb_ldst_forward_e_out_uop_br_mask_T_1 reg wb_ldst_forward_e_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}, clock connect wb_ldst_forward_e_REG, wb_ldst_forward_e_out wire wb_ldst_forward_e : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, addr : { valid : UInt<1>, bits : UInt<40>}, addr_is_virtual : UInt<1>, addr_is_uncacheable : UInt<1>, executed : UInt<1>, succeeded : UInt<1>, order_fail : UInt<1>, observed : UInt<1>, st_dep_mask : UInt<24>, ld_byte_mask : UInt<8>, forward_std_val : UInt<1>, forward_stq_idx : UInt<5>, debug_wb_data : UInt<64>}[1] connect wb_ldst_forward_e[0], wb_ldst_forward_e_REG reg wb_ldst_forward_ldq_idx : UInt[1], clock connect wb_ldst_forward_ldq_idx, lcam_ldq_idx reg wb_ldst_forward_ld_addr : UInt[1], clock connect wb_ldst_forward_ld_addr, lcam_addr wire wb_ldst_forward_stq_idx : UInt<5>[1] wire failed_load : UInt<1> connect failed_load, UInt<1>(0h0) wire l_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop, ldq_uop[0] node _block_addr_matches_T = shr(lcam_addr[0], 6) node _block_addr_matches_T_1 = shr(ldq_addr[0].bits, 6) node _block_addr_matches_T_2 = eq(_block_addr_matches_T, _block_addr_matches_T_1) wire block_addr_matches : UInt<1>[1] connect block_addr_matches[0], _block_addr_matches_T_2 node _dword_addr_matches_T = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_1 = bits(ldq_addr[0].bits, 5, 3) node _dword_addr_matches_T_2 = eq(_dword_addr_matches_T, _dword_addr_matches_T_1) node _dword_addr_matches_T_3 = and(block_addr_matches[0], _dword_addr_matches_T_2) wire dword_addr_matches : UInt<1>[1] connect dword_addr_matches[0], _dword_addr_matches_T_3 node _mask_match_T = and(ldq_ld_byte_mask[0], lcam_mask[0]) node _mask_match_T_1 = eq(_mask_match_T, ldq_ld_byte_mask[0]) wire mask_match : UInt<1>[1] connect mask_match[0], _mask_match_T_1 node _mask_overlap_T = and(ldq_ld_byte_mask[0], lcam_mask[0]) node _mask_overlap_T_1 = orr(_mask_overlap_T) wire mask_overlap : UInt<1>[1] connect mask_overlap[0], _mask_overlap_T_1 node _T_339 = and(do_release_search[0], ldq_valid[0]) node _T_340 = and(_T_339, ldq_addr[0].valid) node _T_341 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_342 = and(_T_340, _T_341) node _T_343 = and(_T_342, block_addr_matches[0]) when _T_343 : connect ldq_observed[0], UInt<1>(0h1) node _T_344 = and(do_st_search[0], ldq_valid[0]) node _T_345 = and(_T_344, ldq_addr[0].valid) node _T_346 = or(ldq_executed[0], ldq_succeeded[0]) node _T_347 = and(_T_345, _T_346) node _T_348 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_349 = and(_T_347, _T_348) node _T_350 = dshr(ldq_st_dep_mask[0], lcam_stq_idx[0]) node _T_351 = bits(_T_350, 0, 0) node _T_352 = and(_T_349, _T_351) node _T_353 = and(_T_352, dword_addr_matches[0]) node _T_354 = and(_T_353, mask_overlap[0]) when _T_354 : node _forwarded_is_older_T = lt(ldq_forward_stq_idx[0], lcam_stq_idx[0]) node _forwarded_is_older_T_1 = lt(ldq_forward_stq_idx[0], l_uop.stq_idx) node _forwarded_is_older_T_2 = xor(_forwarded_is_older_T, _forwarded_is_older_T_1) node _forwarded_is_older_T_3 = lt(lcam_stq_idx[0], l_uop.stq_idx) node forwarded_is_older = xor(_forwarded_is_older_T_2, _forwarded_is_older_T_3) node _T_355 = eq(ldq_forward_std_val[0], UInt<1>(0h0)) node _T_356 = neq(ldq_forward_stq_idx[0], lcam_stq_idx[0]) node _T_357 = and(_T_356, forwarded_is_older) node _T_358 = or(_T_355, _T_357) when _T_358 : connect ldq_order_fail[0], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_359 = and(do_ld_search[0], ldq_valid[0]) node _T_360 = and(_T_359, ldq_addr[0].valid) node _T_361 = eq(ldq_addr_is_virtual[0], UInt<1>(0h0)) node _T_362 = and(_T_360, _T_361) node _T_363 = and(_T_362, dword_addr_matches[0]) node _T_364 = and(_T_363, mask_overlap[0]) when _T_364 : node searcher_is_older = bits(lcam_younger_load_mask[0], 0, 0) node _T_365 = lt(lcam_ldq_idx[0], UInt<1>(0h0)) node _T_366 = lt(lcam_ldq_idx[0], ldq_head) node _T_367 = xor(_T_365, _T_366) node _T_368 = lt(UInt<1>(0h0), ldq_head) node _T_369 = xor(_T_367, _T_368) node _T_370 = eq(_T_369, searcher_is_older) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_32 assert(clock, _T_370, UInt<1>(0h1), "") : assert_32 when searcher_is_older : node _T_374 = or(ldq_executed[0], ldq_succeeded[0]) node _T_375 = eq(s1_executing_loads[0], UInt<1>(0h0)) node _T_376 = and(_T_374, _T_375) node _T_377 = and(_T_376, ldq_observed[0]) when _T_377 : node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_33 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_33 else : node _T_381 = neq(lcam_ldq_idx[0], UInt<1>(0h0)) when _T_381 : node _T_382 = or(ldq_succeeded[0], ldq_will_succeed[0]) node _T_383 = and(ldq_executed[0], _T_382) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_386 = bits(_T_385, 4, 0) connect s1_set_execute[_T_386], UInt<1>(0h0) node _T_387 = eq(s0_kills[0], UInt<1>(0h0)) node _T_388 = and(dmem_req_fire[0], _T_387) reg REG_1 : UInt<1>, clock connect REG_1, _T_388 node _T_389 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_390 = and(REG_1, _T_389) when _T_390 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_1, ldq_uop[1] node _block_addr_matches_T_3 = shr(lcam_addr[0], 6) node _block_addr_matches_T_4 = shr(ldq_addr[1].bits, 6) node _block_addr_matches_T_5 = eq(_block_addr_matches_T_3, _block_addr_matches_T_4) wire block_addr_matches_1 : UInt<1>[1] connect block_addr_matches_1[0], _block_addr_matches_T_5 node _dword_addr_matches_T_4 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_5 = bits(ldq_addr[1].bits, 5, 3) node _dword_addr_matches_T_6 = eq(_dword_addr_matches_T_4, _dword_addr_matches_T_5) node _dword_addr_matches_T_7 = and(block_addr_matches_1[0], _dword_addr_matches_T_6) wire dword_addr_matches_1 : UInt<1>[1] connect dword_addr_matches_1[0], _dword_addr_matches_T_7 node _mask_match_T_2 = and(ldq_ld_byte_mask[1], lcam_mask[0]) node _mask_match_T_3 = eq(_mask_match_T_2, ldq_ld_byte_mask[1]) wire mask_match_1 : UInt<1>[1] connect mask_match_1[0], _mask_match_T_3 node _mask_overlap_T_2 = and(ldq_ld_byte_mask[1], lcam_mask[0]) node _mask_overlap_T_3 = orr(_mask_overlap_T_2) wire mask_overlap_1 : UInt<1>[1] connect mask_overlap_1[0], _mask_overlap_T_3 node _T_391 = and(do_release_search[0], ldq_valid[1]) node _T_392 = and(_T_391, ldq_addr[1].valid) node _T_393 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_394 = and(_T_392, _T_393) node _T_395 = and(_T_394, block_addr_matches_1[0]) when _T_395 : connect ldq_observed[1], UInt<1>(0h1) node _T_396 = and(do_st_search[0], ldq_valid[1]) node _T_397 = and(_T_396, ldq_addr[1].valid) node _T_398 = or(ldq_executed[1], ldq_succeeded[1]) node _T_399 = and(_T_397, _T_398) node _T_400 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_401 = and(_T_399, _T_400) node _T_402 = dshr(ldq_st_dep_mask[1], lcam_stq_idx[0]) node _T_403 = bits(_T_402, 0, 0) node _T_404 = and(_T_401, _T_403) node _T_405 = and(_T_404, dword_addr_matches_1[0]) node _T_406 = and(_T_405, mask_overlap_1[0]) when _T_406 : node _forwarded_is_older_T_4 = lt(ldq_forward_stq_idx[1], lcam_stq_idx[0]) node _forwarded_is_older_T_5 = lt(ldq_forward_stq_idx[1], l_uop_1.stq_idx) node _forwarded_is_older_T_6 = xor(_forwarded_is_older_T_4, _forwarded_is_older_T_5) node _forwarded_is_older_T_7 = lt(lcam_stq_idx[0], l_uop_1.stq_idx) node forwarded_is_older_1 = xor(_forwarded_is_older_T_6, _forwarded_is_older_T_7) node _T_407 = eq(ldq_forward_std_val[1], UInt<1>(0h0)) node _T_408 = neq(ldq_forward_stq_idx[1], lcam_stq_idx[0]) node _T_409 = and(_T_408, forwarded_is_older_1) node _T_410 = or(_T_407, _T_409) when _T_410 : connect ldq_order_fail[1], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_411 = and(do_ld_search[0], ldq_valid[1]) node _T_412 = and(_T_411, ldq_addr[1].valid) node _T_413 = eq(ldq_addr_is_virtual[1], UInt<1>(0h0)) node _T_414 = and(_T_412, _T_413) node _T_415 = and(_T_414, dword_addr_matches_1[0]) node _T_416 = and(_T_415, mask_overlap_1[0]) when _T_416 : node searcher_is_older_1 = bits(lcam_younger_load_mask[0], 1, 1) node _T_417 = lt(lcam_ldq_idx[0], UInt<1>(0h1)) node _T_418 = lt(lcam_ldq_idx[0], ldq_head) node _T_419 = xor(_T_417, _T_418) node _T_420 = lt(UInt<1>(0h1), ldq_head) node _T_421 = xor(_T_419, _T_420) node _T_422 = eq(_T_421, searcher_is_older_1) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_34 assert(clock, _T_422, UInt<1>(0h1), "") : assert_34 when searcher_is_older_1 : node _T_426 = or(ldq_executed[1], ldq_succeeded[1]) node _T_427 = eq(s1_executing_loads[1], UInt<1>(0h0)) node _T_428 = and(_T_426, _T_427) node _T_429 = and(_T_428, ldq_observed[1]) when _T_429 : node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_35 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_35 else : node _T_433 = neq(lcam_ldq_idx[0], UInt<1>(0h1)) when _T_433 : node _T_434 = or(ldq_succeeded[1], ldq_will_succeed[1]) node _T_435 = and(ldq_executed[1], _T_434) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_438 = bits(_T_437, 4, 0) connect s1_set_execute[_T_438], UInt<1>(0h0) node _T_439 = eq(s0_kills[0], UInt<1>(0h0)) node _T_440 = and(dmem_req_fire[0], _T_439) reg REG_2 : UInt<1>, clock connect REG_2, _T_440 node _T_441 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_442 = and(REG_2, _T_441) when _T_442 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_2, ldq_uop[2] node _block_addr_matches_T_6 = shr(lcam_addr[0], 6) node _block_addr_matches_T_7 = shr(ldq_addr[2].bits, 6) node _block_addr_matches_T_8 = eq(_block_addr_matches_T_6, _block_addr_matches_T_7) wire block_addr_matches_2 : UInt<1>[1] connect block_addr_matches_2[0], _block_addr_matches_T_8 node _dword_addr_matches_T_8 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_9 = bits(ldq_addr[2].bits, 5, 3) node _dword_addr_matches_T_10 = eq(_dword_addr_matches_T_8, _dword_addr_matches_T_9) node _dword_addr_matches_T_11 = and(block_addr_matches_2[0], _dword_addr_matches_T_10) wire dword_addr_matches_2 : UInt<1>[1] connect dword_addr_matches_2[0], _dword_addr_matches_T_11 node _mask_match_T_4 = and(ldq_ld_byte_mask[2], lcam_mask[0]) node _mask_match_T_5 = eq(_mask_match_T_4, ldq_ld_byte_mask[2]) wire mask_match_2 : UInt<1>[1] connect mask_match_2[0], _mask_match_T_5 node _mask_overlap_T_4 = and(ldq_ld_byte_mask[2], lcam_mask[0]) node _mask_overlap_T_5 = orr(_mask_overlap_T_4) wire mask_overlap_2 : UInt<1>[1] connect mask_overlap_2[0], _mask_overlap_T_5 node _T_443 = and(do_release_search[0], ldq_valid[2]) node _T_444 = and(_T_443, ldq_addr[2].valid) node _T_445 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_446 = and(_T_444, _T_445) node _T_447 = and(_T_446, block_addr_matches_2[0]) when _T_447 : connect ldq_observed[2], UInt<1>(0h1) node _T_448 = and(do_st_search[0], ldq_valid[2]) node _T_449 = and(_T_448, ldq_addr[2].valid) node _T_450 = or(ldq_executed[2], ldq_succeeded[2]) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_453 = and(_T_451, _T_452) node _T_454 = dshr(ldq_st_dep_mask[2], lcam_stq_idx[0]) node _T_455 = bits(_T_454, 0, 0) node _T_456 = and(_T_453, _T_455) node _T_457 = and(_T_456, dword_addr_matches_2[0]) node _T_458 = and(_T_457, mask_overlap_2[0]) when _T_458 : node _forwarded_is_older_T_8 = lt(ldq_forward_stq_idx[2], lcam_stq_idx[0]) node _forwarded_is_older_T_9 = lt(ldq_forward_stq_idx[2], l_uop_2.stq_idx) node _forwarded_is_older_T_10 = xor(_forwarded_is_older_T_8, _forwarded_is_older_T_9) node _forwarded_is_older_T_11 = lt(lcam_stq_idx[0], l_uop_2.stq_idx) node forwarded_is_older_2 = xor(_forwarded_is_older_T_10, _forwarded_is_older_T_11) node _T_459 = eq(ldq_forward_std_val[2], UInt<1>(0h0)) node _T_460 = neq(ldq_forward_stq_idx[2], lcam_stq_idx[0]) node _T_461 = and(_T_460, forwarded_is_older_2) node _T_462 = or(_T_459, _T_461) when _T_462 : connect ldq_order_fail[2], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_463 = and(do_ld_search[0], ldq_valid[2]) node _T_464 = and(_T_463, ldq_addr[2].valid) node _T_465 = eq(ldq_addr_is_virtual[2], UInt<1>(0h0)) node _T_466 = and(_T_464, _T_465) node _T_467 = and(_T_466, dword_addr_matches_2[0]) node _T_468 = and(_T_467, mask_overlap_2[0]) when _T_468 : node searcher_is_older_2 = bits(lcam_younger_load_mask[0], 2, 2) node _T_469 = lt(lcam_ldq_idx[0], UInt<2>(0h2)) node _T_470 = lt(lcam_ldq_idx[0], ldq_head) node _T_471 = xor(_T_469, _T_470) node _T_472 = lt(UInt<2>(0h2), ldq_head) node _T_473 = xor(_T_471, _T_472) node _T_474 = eq(_T_473, searcher_is_older_2) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_36 assert(clock, _T_474, UInt<1>(0h1), "") : assert_36 when searcher_is_older_2 : node _T_478 = or(ldq_executed[2], ldq_succeeded[2]) node _T_479 = eq(s1_executing_loads[2], UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = and(_T_480, ldq_observed[2]) when _T_481 : node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_37 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_37 else : node _T_485 = neq(lcam_ldq_idx[0], UInt<2>(0h2)) when _T_485 : node _T_486 = or(ldq_succeeded[2], ldq_will_succeed[2]) node _T_487 = and(ldq_executed[2], _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_490 = bits(_T_489, 4, 0) connect s1_set_execute[_T_490], UInt<1>(0h0) node _T_491 = eq(s0_kills[0], UInt<1>(0h0)) node _T_492 = and(dmem_req_fire[0], _T_491) reg REG_3 : UInt<1>, clock connect REG_3, _T_492 node _T_493 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_494 = and(REG_3, _T_493) when _T_494 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_3, ldq_uop[3] node _block_addr_matches_T_9 = shr(lcam_addr[0], 6) node _block_addr_matches_T_10 = shr(ldq_addr[3].bits, 6) node _block_addr_matches_T_11 = eq(_block_addr_matches_T_9, _block_addr_matches_T_10) wire block_addr_matches_3 : UInt<1>[1] connect block_addr_matches_3[0], _block_addr_matches_T_11 node _dword_addr_matches_T_12 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_13 = bits(ldq_addr[3].bits, 5, 3) node _dword_addr_matches_T_14 = eq(_dword_addr_matches_T_12, _dword_addr_matches_T_13) node _dword_addr_matches_T_15 = and(block_addr_matches_3[0], _dword_addr_matches_T_14) wire dword_addr_matches_3 : UInt<1>[1] connect dword_addr_matches_3[0], _dword_addr_matches_T_15 node _mask_match_T_6 = and(ldq_ld_byte_mask[3], lcam_mask[0]) node _mask_match_T_7 = eq(_mask_match_T_6, ldq_ld_byte_mask[3]) wire mask_match_3 : UInt<1>[1] connect mask_match_3[0], _mask_match_T_7 node _mask_overlap_T_6 = and(ldq_ld_byte_mask[3], lcam_mask[0]) node _mask_overlap_T_7 = orr(_mask_overlap_T_6) wire mask_overlap_3 : UInt<1>[1] connect mask_overlap_3[0], _mask_overlap_T_7 node _T_495 = and(do_release_search[0], ldq_valid[3]) node _T_496 = and(_T_495, ldq_addr[3].valid) node _T_497 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_498 = and(_T_496, _T_497) node _T_499 = and(_T_498, block_addr_matches_3[0]) when _T_499 : connect ldq_observed[3], UInt<1>(0h1) node _T_500 = and(do_st_search[0], ldq_valid[3]) node _T_501 = and(_T_500, ldq_addr[3].valid) node _T_502 = or(ldq_executed[3], ldq_succeeded[3]) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_505 = and(_T_503, _T_504) node _T_506 = dshr(ldq_st_dep_mask[3], lcam_stq_idx[0]) node _T_507 = bits(_T_506, 0, 0) node _T_508 = and(_T_505, _T_507) node _T_509 = and(_T_508, dword_addr_matches_3[0]) node _T_510 = and(_T_509, mask_overlap_3[0]) when _T_510 : node _forwarded_is_older_T_12 = lt(ldq_forward_stq_idx[3], lcam_stq_idx[0]) node _forwarded_is_older_T_13 = lt(ldq_forward_stq_idx[3], l_uop_3.stq_idx) node _forwarded_is_older_T_14 = xor(_forwarded_is_older_T_12, _forwarded_is_older_T_13) node _forwarded_is_older_T_15 = lt(lcam_stq_idx[0], l_uop_3.stq_idx) node forwarded_is_older_3 = xor(_forwarded_is_older_T_14, _forwarded_is_older_T_15) node _T_511 = eq(ldq_forward_std_val[3], UInt<1>(0h0)) node _T_512 = neq(ldq_forward_stq_idx[3], lcam_stq_idx[0]) node _T_513 = and(_T_512, forwarded_is_older_3) node _T_514 = or(_T_511, _T_513) when _T_514 : connect ldq_order_fail[3], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_515 = and(do_ld_search[0], ldq_valid[3]) node _T_516 = and(_T_515, ldq_addr[3].valid) node _T_517 = eq(ldq_addr_is_virtual[3], UInt<1>(0h0)) node _T_518 = and(_T_516, _T_517) node _T_519 = and(_T_518, dword_addr_matches_3[0]) node _T_520 = and(_T_519, mask_overlap_3[0]) when _T_520 : node searcher_is_older_3 = bits(lcam_younger_load_mask[0], 3, 3) node _T_521 = lt(lcam_ldq_idx[0], UInt<2>(0h3)) node _T_522 = lt(lcam_ldq_idx[0], ldq_head) node _T_523 = xor(_T_521, _T_522) node _T_524 = lt(UInt<2>(0h3), ldq_head) node _T_525 = xor(_T_523, _T_524) node _T_526 = eq(_T_525, searcher_is_older_3) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_38 assert(clock, _T_526, UInt<1>(0h1), "") : assert_38 when searcher_is_older_3 : node _T_530 = or(ldq_executed[3], ldq_succeeded[3]) node _T_531 = eq(s1_executing_loads[3], UInt<1>(0h0)) node _T_532 = and(_T_530, _T_531) node _T_533 = and(_T_532, ldq_observed[3]) when _T_533 : node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_39 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_39 else : node _T_537 = neq(lcam_ldq_idx[0], UInt<2>(0h3)) when _T_537 : node _T_538 = or(ldq_succeeded[3], ldq_will_succeed[3]) node _T_539 = and(ldq_executed[3], _T_538) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_542 = bits(_T_541, 4, 0) connect s1_set_execute[_T_542], UInt<1>(0h0) node _T_543 = eq(s0_kills[0], UInt<1>(0h0)) node _T_544 = and(dmem_req_fire[0], _T_543) reg REG_4 : UInt<1>, clock connect REG_4, _T_544 node _T_545 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_546 = and(REG_4, _T_545) when _T_546 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_4, ldq_uop[4] node _block_addr_matches_T_12 = shr(lcam_addr[0], 6) node _block_addr_matches_T_13 = shr(ldq_addr[4].bits, 6) node _block_addr_matches_T_14 = eq(_block_addr_matches_T_12, _block_addr_matches_T_13) wire block_addr_matches_4 : UInt<1>[1] connect block_addr_matches_4[0], _block_addr_matches_T_14 node _dword_addr_matches_T_16 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_17 = bits(ldq_addr[4].bits, 5, 3) node _dword_addr_matches_T_18 = eq(_dword_addr_matches_T_16, _dword_addr_matches_T_17) node _dword_addr_matches_T_19 = and(block_addr_matches_4[0], _dword_addr_matches_T_18) wire dword_addr_matches_4 : UInt<1>[1] connect dword_addr_matches_4[0], _dword_addr_matches_T_19 node _mask_match_T_8 = and(ldq_ld_byte_mask[4], lcam_mask[0]) node _mask_match_T_9 = eq(_mask_match_T_8, ldq_ld_byte_mask[4]) wire mask_match_4 : UInt<1>[1] connect mask_match_4[0], _mask_match_T_9 node _mask_overlap_T_8 = and(ldq_ld_byte_mask[4], lcam_mask[0]) node _mask_overlap_T_9 = orr(_mask_overlap_T_8) wire mask_overlap_4 : UInt<1>[1] connect mask_overlap_4[0], _mask_overlap_T_9 node _T_547 = and(do_release_search[0], ldq_valid[4]) node _T_548 = and(_T_547, ldq_addr[4].valid) node _T_549 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) node _T_551 = and(_T_550, block_addr_matches_4[0]) when _T_551 : connect ldq_observed[4], UInt<1>(0h1) node _T_552 = and(do_st_search[0], ldq_valid[4]) node _T_553 = and(_T_552, ldq_addr[4].valid) node _T_554 = or(ldq_executed[4], ldq_succeeded[4]) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_557 = and(_T_555, _T_556) node _T_558 = dshr(ldq_st_dep_mask[4], lcam_stq_idx[0]) node _T_559 = bits(_T_558, 0, 0) node _T_560 = and(_T_557, _T_559) node _T_561 = and(_T_560, dword_addr_matches_4[0]) node _T_562 = and(_T_561, mask_overlap_4[0]) when _T_562 : node _forwarded_is_older_T_16 = lt(ldq_forward_stq_idx[4], lcam_stq_idx[0]) node _forwarded_is_older_T_17 = lt(ldq_forward_stq_idx[4], l_uop_4.stq_idx) node _forwarded_is_older_T_18 = xor(_forwarded_is_older_T_16, _forwarded_is_older_T_17) node _forwarded_is_older_T_19 = lt(lcam_stq_idx[0], l_uop_4.stq_idx) node forwarded_is_older_4 = xor(_forwarded_is_older_T_18, _forwarded_is_older_T_19) node _T_563 = eq(ldq_forward_std_val[4], UInt<1>(0h0)) node _T_564 = neq(ldq_forward_stq_idx[4], lcam_stq_idx[0]) node _T_565 = and(_T_564, forwarded_is_older_4) node _T_566 = or(_T_563, _T_565) when _T_566 : connect ldq_order_fail[4], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_567 = and(do_ld_search[0], ldq_valid[4]) node _T_568 = and(_T_567, ldq_addr[4].valid) node _T_569 = eq(ldq_addr_is_virtual[4], UInt<1>(0h0)) node _T_570 = and(_T_568, _T_569) node _T_571 = and(_T_570, dword_addr_matches_4[0]) node _T_572 = and(_T_571, mask_overlap_4[0]) when _T_572 : node searcher_is_older_4 = bits(lcam_younger_load_mask[0], 4, 4) node _T_573 = lt(lcam_ldq_idx[0], UInt<3>(0h4)) node _T_574 = lt(lcam_ldq_idx[0], ldq_head) node _T_575 = xor(_T_573, _T_574) node _T_576 = lt(UInt<3>(0h4), ldq_head) node _T_577 = xor(_T_575, _T_576) node _T_578 = eq(_T_577, searcher_is_older_4) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_40 assert(clock, _T_578, UInt<1>(0h1), "") : assert_40 when searcher_is_older_4 : node _T_582 = or(ldq_executed[4], ldq_succeeded[4]) node _T_583 = eq(s1_executing_loads[4], UInt<1>(0h0)) node _T_584 = and(_T_582, _T_583) node _T_585 = and(_T_584, ldq_observed[4]) when _T_585 : node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_41 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_41 else : node _T_589 = neq(lcam_ldq_idx[0], UInt<3>(0h4)) when _T_589 : node _T_590 = or(ldq_succeeded[4], ldq_will_succeed[4]) node _T_591 = and(ldq_executed[4], _T_590) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_594 = bits(_T_593, 4, 0) connect s1_set_execute[_T_594], UInt<1>(0h0) node _T_595 = eq(s0_kills[0], UInt<1>(0h0)) node _T_596 = and(dmem_req_fire[0], _T_595) reg REG_5 : UInt<1>, clock connect REG_5, _T_596 node _T_597 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_598 = and(REG_5, _T_597) when _T_598 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_5, ldq_uop[5] node _block_addr_matches_T_15 = shr(lcam_addr[0], 6) node _block_addr_matches_T_16 = shr(ldq_addr[5].bits, 6) node _block_addr_matches_T_17 = eq(_block_addr_matches_T_15, _block_addr_matches_T_16) wire block_addr_matches_5 : UInt<1>[1] connect block_addr_matches_5[0], _block_addr_matches_T_17 node _dword_addr_matches_T_20 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_21 = bits(ldq_addr[5].bits, 5, 3) node _dword_addr_matches_T_22 = eq(_dword_addr_matches_T_20, _dword_addr_matches_T_21) node _dword_addr_matches_T_23 = and(block_addr_matches_5[0], _dword_addr_matches_T_22) wire dword_addr_matches_5 : UInt<1>[1] connect dword_addr_matches_5[0], _dword_addr_matches_T_23 node _mask_match_T_10 = and(ldq_ld_byte_mask[5], lcam_mask[0]) node _mask_match_T_11 = eq(_mask_match_T_10, ldq_ld_byte_mask[5]) wire mask_match_5 : UInt<1>[1] connect mask_match_5[0], _mask_match_T_11 node _mask_overlap_T_10 = and(ldq_ld_byte_mask[5], lcam_mask[0]) node _mask_overlap_T_11 = orr(_mask_overlap_T_10) wire mask_overlap_5 : UInt<1>[1] connect mask_overlap_5[0], _mask_overlap_T_11 node _T_599 = and(do_release_search[0], ldq_valid[5]) node _T_600 = and(_T_599, ldq_addr[5].valid) node _T_601 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) node _T_603 = and(_T_602, block_addr_matches_5[0]) when _T_603 : connect ldq_observed[5], UInt<1>(0h1) node _T_604 = and(do_st_search[0], ldq_valid[5]) node _T_605 = and(_T_604, ldq_addr[5].valid) node _T_606 = or(ldq_executed[5], ldq_succeeded[5]) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_609 = and(_T_607, _T_608) node _T_610 = dshr(ldq_st_dep_mask[5], lcam_stq_idx[0]) node _T_611 = bits(_T_610, 0, 0) node _T_612 = and(_T_609, _T_611) node _T_613 = and(_T_612, dword_addr_matches_5[0]) node _T_614 = and(_T_613, mask_overlap_5[0]) when _T_614 : node _forwarded_is_older_T_20 = lt(ldq_forward_stq_idx[5], lcam_stq_idx[0]) node _forwarded_is_older_T_21 = lt(ldq_forward_stq_idx[5], l_uop_5.stq_idx) node _forwarded_is_older_T_22 = xor(_forwarded_is_older_T_20, _forwarded_is_older_T_21) node _forwarded_is_older_T_23 = lt(lcam_stq_idx[0], l_uop_5.stq_idx) node forwarded_is_older_5 = xor(_forwarded_is_older_T_22, _forwarded_is_older_T_23) node _T_615 = eq(ldq_forward_std_val[5], UInt<1>(0h0)) node _T_616 = neq(ldq_forward_stq_idx[5], lcam_stq_idx[0]) node _T_617 = and(_T_616, forwarded_is_older_5) node _T_618 = or(_T_615, _T_617) when _T_618 : connect ldq_order_fail[5], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_619 = and(do_ld_search[0], ldq_valid[5]) node _T_620 = and(_T_619, ldq_addr[5].valid) node _T_621 = eq(ldq_addr_is_virtual[5], UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) node _T_623 = and(_T_622, dword_addr_matches_5[0]) node _T_624 = and(_T_623, mask_overlap_5[0]) when _T_624 : node searcher_is_older_5 = bits(lcam_younger_load_mask[0], 5, 5) node _T_625 = lt(lcam_ldq_idx[0], UInt<3>(0h5)) node _T_626 = lt(lcam_ldq_idx[0], ldq_head) node _T_627 = xor(_T_625, _T_626) node _T_628 = lt(UInt<3>(0h5), ldq_head) node _T_629 = xor(_T_627, _T_628) node _T_630 = eq(_T_629, searcher_is_older_5) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_42 assert(clock, _T_630, UInt<1>(0h1), "") : assert_42 when searcher_is_older_5 : node _T_634 = or(ldq_executed[5], ldq_succeeded[5]) node _T_635 = eq(s1_executing_loads[5], UInt<1>(0h0)) node _T_636 = and(_T_634, _T_635) node _T_637 = and(_T_636, ldq_observed[5]) when _T_637 : node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_43 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_43 else : node _T_641 = neq(lcam_ldq_idx[0], UInt<3>(0h5)) when _T_641 : node _T_642 = or(ldq_succeeded[5], ldq_will_succeed[5]) node _T_643 = and(ldq_executed[5], _T_642) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_646 = bits(_T_645, 4, 0) connect s1_set_execute[_T_646], UInt<1>(0h0) node _T_647 = eq(s0_kills[0], UInt<1>(0h0)) node _T_648 = and(dmem_req_fire[0], _T_647) reg REG_6 : UInt<1>, clock connect REG_6, _T_648 node _T_649 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_650 = and(REG_6, _T_649) when _T_650 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_6, ldq_uop[6] node _block_addr_matches_T_18 = shr(lcam_addr[0], 6) node _block_addr_matches_T_19 = shr(ldq_addr[6].bits, 6) node _block_addr_matches_T_20 = eq(_block_addr_matches_T_18, _block_addr_matches_T_19) wire block_addr_matches_6 : UInt<1>[1] connect block_addr_matches_6[0], _block_addr_matches_T_20 node _dword_addr_matches_T_24 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_25 = bits(ldq_addr[6].bits, 5, 3) node _dword_addr_matches_T_26 = eq(_dword_addr_matches_T_24, _dword_addr_matches_T_25) node _dword_addr_matches_T_27 = and(block_addr_matches_6[0], _dword_addr_matches_T_26) wire dword_addr_matches_6 : UInt<1>[1] connect dword_addr_matches_6[0], _dword_addr_matches_T_27 node _mask_match_T_12 = and(ldq_ld_byte_mask[6], lcam_mask[0]) node _mask_match_T_13 = eq(_mask_match_T_12, ldq_ld_byte_mask[6]) wire mask_match_6 : UInt<1>[1] connect mask_match_6[0], _mask_match_T_13 node _mask_overlap_T_12 = and(ldq_ld_byte_mask[6], lcam_mask[0]) node _mask_overlap_T_13 = orr(_mask_overlap_T_12) wire mask_overlap_6 : UInt<1>[1] connect mask_overlap_6[0], _mask_overlap_T_13 node _T_651 = and(do_release_search[0], ldq_valid[6]) node _T_652 = and(_T_651, ldq_addr[6].valid) node _T_653 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_654 = and(_T_652, _T_653) node _T_655 = and(_T_654, block_addr_matches_6[0]) when _T_655 : connect ldq_observed[6], UInt<1>(0h1) node _T_656 = and(do_st_search[0], ldq_valid[6]) node _T_657 = and(_T_656, ldq_addr[6].valid) node _T_658 = or(ldq_executed[6], ldq_succeeded[6]) node _T_659 = and(_T_657, _T_658) node _T_660 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_661 = and(_T_659, _T_660) node _T_662 = dshr(ldq_st_dep_mask[6], lcam_stq_idx[0]) node _T_663 = bits(_T_662, 0, 0) node _T_664 = and(_T_661, _T_663) node _T_665 = and(_T_664, dword_addr_matches_6[0]) node _T_666 = and(_T_665, mask_overlap_6[0]) when _T_666 : node _forwarded_is_older_T_24 = lt(ldq_forward_stq_idx[6], lcam_stq_idx[0]) node _forwarded_is_older_T_25 = lt(ldq_forward_stq_idx[6], l_uop_6.stq_idx) node _forwarded_is_older_T_26 = xor(_forwarded_is_older_T_24, _forwarded_is_older_T_25) node _forwarded_is_older_T_27 = lt(lcam_stq_idx[0], l_uop_6.stq_idx) node forwarded_is_older_6 = xor(_forwarded_is_older_T_26, _forwarded_is_older_T_27) node _T_667 = eq(ldq_forward_std_val[6], UInt<1>(0h0)) node _T_668 = neq(ldq_forward_stq_idx[6], lcam_stq_idx[0]) node _T_669 = and(_T_668, forwarded_is_older_6) node _T_670 = or(_T_667, _T_669) when _T_670 : connect ldq_order_fail[6], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_671 = and(do_ld_search[0], ldq_valid[6]) node _T_672 = and(_T_671, ldq_addr[6].valid) node _T_673 = eq(ldq_addr_is_virtual[6], UInt<1>(0h0)) node _T_674 = and(_T_672, _T_673) node _T_675 = and(_T_674, dword_addr_matches_6[0]) node _T_676 = and(_T_675, mask_overlap_6[0]) when _T_676 : node searcher_is_older_6 = bits(lcam_younger_load_mask[0], 6, 6) node _T_677 = lt(lcam_ldq_idx[0], UInt<3>(0h6)) node _T_678 = lt(lcam_ldq_idx[0], ldq_head) node _T_679 = xor(_T_677, _T_678) node _T_680 = lt(UInt<3>(0h6), ldq_head) node _T_681 = xor(_T_679, _T_680) node _T_682 = eq(_T_681, searcher_is_older_6) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_44 assert(clock, _T_682, UInt<1>(0h1), "") : assert_44 when searcher_is_older_6 : node _T_686 = or(ldq_executed[6], ldq_succeeded[6]) node _T_687 = eq(s1_executing_loads[6], UInt<1>(0h0)) node _T_688 = and(_T_686, _T_687) node _T_689 = and(_T_688, ldq_observed[6]) when _T_689 : node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_45 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_45 else : node _T_693 = neq(lcam_ldq_idx[0], UInt<3>(0h6)) when _T_693 : node _T_694 = or(ldq_succeeded[6], ldq_will_succeed[6]) node _T_695 = and(ldq_executed[6], _T_694) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_698 = bits(_T_697, 4, 0) connect s1_set_execute[_T_698], UInt<1>(0h0) node _T_699 = eq(s0_kills[0], UInt<1>(0h0)) node _T_700 = and(dmem_req_fire[0], _T_699) reg REG_7 : UInt<1>, clock connect REG_7, _T_700 node _T_701 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_702 = and(REG_7, _T_701) when _T_702 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_7, ldq_uop[7] node _block_addr_matches_T_21 = shr(lcam_addr[0], 6) node _block_addr_matches_T_22 = shr(ldq_addr[7].bits, 6) node _block_addr_matches_T_23 = eq(_block_addr_matches_T_21, _block_addr_matches_T_22) wire block_addr_matches_7 : UInt<1>[1] connect block_addr_matches_7[0], _block_addr_matches_T_23 node _dword_addr_matches_T_28 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_29 = bits(ldq_addr[7].bits, 5, 3) node _dword_addr_matches_T_30 = eq(_dword_addr_matches_T_28, _dword_addr_matches_T_29) node _dword_addr_matches_T_31 = and(block_addr_matches_7[0], _dword_addr_matches_T_30) wire dword_addr_matches_7 : UInt<1>[1] connect dword_addr_matches_7[0], _dword_addr_matches_T_31 node _mask_match_T_14 = and(ldq_ld_byte_mask[7], lcam_mask[0]) node _mask_match_T_15 = eq(_mask_match_T_14, ldq_ld_byte_mask[7]) wire mask_match_7 : UInt<1>[1] connect mask_match_7[0], _mask_match_T_15 node _mask_overlap_T_14 = and(ldq_ld_byte_mask[7], lcam_mask[0]) node _mask_overlap_T_15 = orr(_mask_overlap_T_14) wire mask_overlap_7 : UInt<1>[1] connect mask_overlap_7[0], _mask_overlap_T_15 node _T_703 = and(do_release_search[0], ldq_valid[7]) node _T_704 = and(_T_703, ldq_addr[7].valid) node _T_705 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, block_addr_matches_7[0]) when _T_707 : connect ldq_observed[7], UInt<1>(0h1) node _T_708 = and(do_st_search[0], ldq_valid[7]) node _T_709 = and(_T_708, ldq_addr[7].valid) node _T_710 = or(ldq_executed[7], ldq_succeeded[7]) node _T_711 = and(_T_709, _T_710) node _T_712 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_713 = and(_T_711, _T_712) node _T_714 = dshr(ldq_st_dep_mask[7], lcam_stq_idx[0]) node _T_715 = bits(_T_714, 0, 0) node _T_716 = and(_T_713, _T_715) node _T_717 = and(_T_716, dword_addr_matches_7[0]) node _T_718 = and(_T_717, mask_overlap_7[0]) when _T_718 : node _forwarded_is_older_T_28 = lt(ldq_forward_stq_idx[7], lcam_stq_idx[0]) node _forwarded_is_older_T_29 = lt(ldq_forward_stq_idx[7], l_uop_7.stq_idx) node _forwarded_is_older_T_30 = xor(_forwarded_is_older_T_28, _forwarded_is_older_T_29) node _forwarded_is_older_T_31 = lt(lcam_stq_idx[0], l_uop_7.stq_idx) node forwarded_is_older_7 = xor(_forwarded_is_older_T_30, _forwarded_is_older_T_31) node _T_719 = eq(ldq_forward_std_val[7], UInt<1>(0h0)) node _T_720 = neq(ldq_forward_stq_idx[7], lcam_stq_idx[0]) node _T_721 = and(_T_720, forwarded_is_older_7) node _T_722 = or(_T_719, _T_721) when _T_722 : connect ldq_order_fail[7], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_723 = and(do_ld_search[0], ldq_valid[7]) node _T_724 = and(_T_723, ldq_addr[7].valid) node _T_725 = eq(ldq_addr_is_virtual[7], UInt<1>(0h0)) node _T_726 = and(_T_724, _T_725) node _T_727 = and(_T_726, dword_addr_matches_7[0]) node _T_728 = and(_T_727, mask_overlap_7[0]) when _T_728 : node searcher_is_older_7 = bits(lcam_younger_load_mask[0], 7, 7) node _T_729 = lt(lcam_ldq_idx[0], UInt<3>(0h7)) node _T_730 = lt(lcam_ldq_idx[0], ldq_head) node _T_731 = xor(_T_729, _T_730) node _T_732 = lt(UInt<3>(0h7), ldq_head) node _T_733 = xor(_T_731, _T_732) node _T_734 = eq(_T_733, searcher_is_older_7) node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_T_734, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_46 assert(clock, _T_734, UInt<1>(0h1), "") : assert_46 when searcher_is_older_7 : node _T_738 = or(ldq_executed[7], ldq_succeeded[7]) node _T_739 = eq(s1_executing_loads[7], UInt<1>(0h0)) node _T_740 = and(_T_738, _T_739) node _T_741 = and(_T_740, ldq_observed[7]) when _T_741 : node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_47 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_47 else : node _T_745 = neq(lcam_ldq_idx[0], UInt<3>(0h7)) when _T_745 : node _T_746 = or(ldq_succeeded[7], ldq_will_succeed[7]) node _T_747 = and(ldq_executed[7], _T_746) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_750 = bits(_T_749, 4, 0) connect s1_set_execute[_T_750], UInt<1>(0h0) node _T_751 = eq(s0_kills[0], UInt<1>(0h0)) node _T_752 = and(dmem_req_fire[0], _T_751) reg REG_8 : UInt<1>, clock connect REG_8, _T_752 node _T_753 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_754 = and(REG_8, _T_753) when _T_754 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_8, ldq_uop[8] node _block_addr_matches_T_24 = shr(lcam_addr[0], 6) node _block_addr_matches_T_25 = shr(ldq_addr[8].bits, 6) node _block_addr_matches_T_26 = eq(_block_addr_matches_T_24, _block_addr_matches_T_25) wire block_addr_matches_8 : UInt<1>[1] connect block_addr_matches_8[0], _block_addr_matches_T_26 node _dword_addr_matches_T_32 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_33 = bits(ldq_addr[8].bits, 5, 3) node _dword_addr_matches_T_34 = eq(_dword_addr_matches_T_32, _dword_addr_matches_T_33) node _dword_addr_matches_T_35 = and(block_addr_matches_8[0], _dword_addr_matches_T_34) wire dword_addr_matches_8 : UInt<1>[1] connect dword_addr_matches_8[0], _dword_addr_matches_T_35 node _mask_match_T_16 = and(ldq_ld_byte_mask[8], lcam_mask[0]) node _mask_match_T_17 = eq(_mask_match_T_16, ldq_ld_byte_mask[8]) wire mask_match_8 : UInt<1>[1] connect mask_match_8[0], _mask_match_T_17 node _mask_overlap_T_16 = and(ldq_ld_byte_mask[8], lcam_mask[0]) node _mask_overlap_T_17 = orr(_mask_overlap_T_16) wire mask_overlap_8 : UInt<1>[1] connect mask_overlap_8[0], _mask_overlap_T_17 node _T_755 = and(do_release_search[0], ldq_valid[8]) node _T_756 = and(_T_755, ldq_addr[8].valid) node _T_757 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_758 = and(_T_756, _T_757) node _T_759 = and(_T_758, block_addr_matches_8[0]) when _T_759 : connect ldq_observed[8], UInt<1>(0h1) node _T_760 = and(do_st_search[0], ldq_valid[8]) node _T_761 = and(_T_760, ldq_addr[8].valid) node _T_762 = or(ldq_executed[8], ldq_succeeded[8]) node _T_763 = and(_T_761, _T_762) node _T_764 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_765 = and(_T_763, _T_764) node _T_766 = dshr(ldq_st_dep_mask[8], lcam_stq_idx[0]) node _T_767 = bits(_T_766, 0, 0) node _T_768 = and(_T_765, _T_767) node _T_769 = and(_T_768, dword_addr_matches_8[0]) node _T_770 = and(_T_769, mask_overlap_8[0]) when _T_770 : node _forwarded_is_older_T_32 = lt(ldq_forward_stq_idx[8], lcam_stq_idx[0]) node _forwarded_is_older_T_33 = lt(ldq_forward_stq_idx[8], l_uop_8.stq_idx) node _forwarded_is_older_T_34 = xor(_forwarded_is_older_T_32, _forwarded_is_older_T_33) node _forwarded_is_older_T_35 = lt(lcam_stq_idx[0], l_uop_8.stq_idx) node forwarded_is_older_8 = xor(_forwarded_is_older_T_34, _forwarded_is_older_T_35) node _T_771 = eq(ldq_forward_std_val[8], UInt<1>(0h0)) node _T_772 = neq(ldq_forward_stq_idx[8], lcam_stq_idx[0]) node _T_773 = and(_T_772, forwarded_is_older_8) node _T_774 = or(_T_771, _T_773) when _T_774 : connect ldq_order_fail[8], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_775 = and(do_ld_search[0], ldq_valid[8]) node _T_776 = and(_T_775, ldq_addr[8].valid) node _T_777 = eq(ldq_addr_is_virtual[8], UInt<1>(0h0)) node _T_778 = and(_T_776, _T_777) node _T_779 = and(_T_778, dword_addr_matches_8[0]) node _T_780 = and(_T_779, mask_overlap_8[0]) when _T_780 : node searcher_is_older_8 = bits(lcam_younger_load_mask[0], 8, 8) node _T_781 = lt(lcam_ldq_idx[0], UInt<4>(0h8)) node _T_782 = lt(lcam_ldq_idx[0], ldq_head) node _T_783 = xor(_T_781, _T_782) node _T_784 = lt(UInt<4>(0h8), ldq_head) node _T_785 = xor(_T_783, _T_784) node _T_786 = eq(_T_785, searcher_is_older_8) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_48 assert(clock, _T_786, UInt<1>(0h1), "") : assert_48 when searcher_is_older_8 : node _T_790 = or(ldq_executed[8], ldq_succeeded[8]) node _T_791 = eq(s1_executing_loads[8], UInt<1>(0h0)) node _T_792 = and(_T_790, _T_791) node _T_793 = and(_T_792, ldq_observed[8]) when _T_793 : node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_49 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_49 else : node _T_797 = neq(lcam_ldq_idx[0], UInt<4>(0h8)) when _T_797 : node _T_798 = or(ldq_succeeded[8], ldq_will_succeed[8]) node _T_799 = and(ldq_executed[8], _T_798) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_802 = bits(_T_801, 4, 0) connect s1_set_execute[_T_802], UInt<1>(0h0) node _T_803 = eq(s0_kills[0], UInt<1>(0h0)) node _T_804 = and(dmem_req_fire[0], _T_803) reg REG_9 : UInt<1>, clock connect REG_9, _T_804 node _T_805 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_806 = and(REG_9, _T_805) when _T_806 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_9, ldq_uop[9] node _block_addr_matches_T_27 = shr(lcam_addr[0], 6) node _block_addr_matches_T_28 = shr(ldq_addr[9].bits, 6) node _block_addr_matches_T_29 = eq(_block_addr_matches_T_27, _block_addr_matches_T_28) wire block_addr_matches_9 : UInt<1>[1] connect block_addr_matches_9[0], _block_addr_matches_T_29 node _dword_addr_matches_T_36 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_37 = bits(ldq_addr[9].bits, 5, 3) node _dword_addr_matches_T_38 = eq(_dword_addr_matches_T_36, _dword_addr_matches_T_37) node _dword_addr_matches_T_39 = and(block_addr_matches_9[0], _dword_addr_matches_T_38) wire dword_addr_matches_9 : UInt<1>[1] connect dword_addr_matches_9[0], _dword_addr_matches_T_39 node _mask_match_T_18 = and(ldq_ld_byte_mask[9], lcam_mask[0]) node _mask_match_T_19 = eq(_mask_match_T_18, ldq_ld_byte_mask[9]) wire mask_match_9 : UInt<1>[1] connect mask_match_9[0], _mask_match_T_19 node _mask_overlap_T_18 = and(ldq_ld_byte_mask[9], lcam_mask[0]) node _mask_overlap_T_19 = orr(_mask_overlap_T_18) wire mask_overlap_9 : UInt<1>[1] connect mask_overlap_9[0], _mask_overlap_T_19 node _T_807 = and(do_release_search[0], ldq_valid[9]) node _T_808 = and(_T_807, ldq_addr[9].valid) node _T_809 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_810 = and(_T_808, _T_809) node _T_811 = and(_T_810, block_addr_matches_9[0]) when _T_811 : connect ldq_observed[9], UInt<1>(0h1) node _T_812 = and(do_st_search[0], ldq_valid[9]) node _T_813 = and(_T_812, ldq_addr[9].valid) node _T_814 = or(ldq_executed[9], ldq_succeeded[9]) node _T_815 = and(_T_813, _T_814) node _T_816 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_817 = and(_T_815, _T_816) node _T_818 = dshr(ldq_st_dep_mask[9], lcam_stq_idx[0]) node _T_819 = bits(_T_818, 0, 0) node _T_820 = and(_T_817, _T_819) node _T_821 = and(_T_820, dword_addr_matches_9[0]) node _T_822 = and(_T_821, mask_overlap_9[0]) when _T_822 : node _forwarded_is_older_T_36 = lt(ldq_forward_stq_idx[9], lcam_stq_idx[0]) node _forwarded_is_older_T_37 = lt(ldq_forward_stq_idx[9], l_uop_9.stq_idx) node _forwarded_is_older_T_38 = xor(_forwarded_is_older_T_36, _forwarded_is_older_T_37) node _forwarded_is_older_T_39 = lt(lcam_stq_idx[0], l_uop_9.stq_idx) node forwarded_is_older_9 = xor(_forwarded_is_older_T_38, _forwarded_is_older_T_39) node _T_823 = eq(ldq_forward_std_val[9], UInt<1>(0h0)) node _T_824 = neq(ldq_forward_stq_idx[9], lcam_stq_idx[0]) node _T_825 = and(_T_824, forwarded_is_older_9) node _T_826 = or(_T_823, _T_825) when _T_826 : connect ldq_order_fail[9], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_827 = and(do_ld_search[0], ldq_valid[9]) node _T_828 = and(_T_827, ldq_addr[9].valid) node _T_829 = eq(ldq_addr_is_virtual[9], UInt<1>(0h0)) node _T_830 = and(_T_828, _T_829) node _T_831 = and(_T_830, dword_addr_matches_9[0]) node _T_832 = and(_T_831, mask_overlap_9[0]) when _T_832 : node searcher_is_older_9 = bits(lcam_younger_load_mask[0], 9, 9) node _T_833 = lt(lcam_ldq_idx[0], UInt<4>(0h9)) node _T_834 = lt(lcam_ldq_idx[0], ldq_head) node _T_835 = xor(_T_833, _T_834) node _T_836 = lt(UInt<4>(0h9), ldq_head) node _T_837 = xor(_T_835, _T_836) node _T_838 = eq(_T_837, searcher_is_older_9) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_50 assert(clock, _T_838, UInt<1>(0h1), "") : assert_50 when searcher_is_older_9 : node _T_842 = or(ldq_executed[9], ldq_succeeded[9]) node _T_843 = eq(s1_executing_loads[9], UInt<1>(0h0)) node _T_844 = and(_T_842, _T_843) node _T_845 = and(_T_844, ldq_observed[9]) when _T_845 : node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_51 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_51 else : node _T_849 = neq(lcam_ldq_idx[0], UInt<4>(0h9)) when _T_849 : node _T_850 = or(ldq_succeeded[9], ldq_will_succeed[9]) node _T_851 = and(ldq_executed[9], _T_850) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_854 = bits(_T_853, 4, 0) connect s1_set_execute[_T_854], UInt<1>(0h0) node _T_855 = eq(s0_kills[0], UInt<1>(0h0)) node _T_856 = and(dmem_req_fire[0], _T_855) reg REG_10 : UInt<1>, clock connect REG_10, _T_856 node _T_857 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_858 = and(REG_10, _T_857) when _T_858 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_10, ldq_uop[10] node _block_addr_matches_T_30 = shr(lcam_addr[0], 6) node _block_addr_matches_T_31 = shr(ldq_addr[10].bits, 6) node _block_addr_matches_T_32 = eq(_block_addr_matches_T_30, _block_addr_matches_T_31) wire block_addr_matches_10 : UInt<1>[1] connect block_addr_matches_10[0], _block_addr_matches_T_32 node _dword_addr_matches_T_40 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_41 = bits(ldq_addr[10].bits, 5, 3) node _dword_addr_matches_T_42 = eq(_dword_addr_matches_T_40, _dword_addr_matches_T_41) node _dword_addr_matches_T_43 = and(block_addr_matches_10[0], _dword_addr_matches_T_42) wire dword_addr_matches_10 : UInt<1>[1] connect dword_addr_matches_10[0], _dword_addr_matches_T_43 node _mask_match_T_20 = and(ldq_ld_byte_mask[10], lcam_mask[0]) node _mask_match_T_21 = eq(_mask_match_T_20, ldq_ld_byte_mask[10]) wire mask_match_10 : UInt<1>[1] connect mask_match_10[0], _mask_match_T_21 node _mask_overlap_T_20 = and(ldq_ld_byte_mask[10], lcam_mask[0]) node _mask_overlap_T_21 = orr(_mask_overlap_T_20) wire mask_overlap_10 : UInt<1>[1] connect mask_overlap_10[0], _mask_overlap_T_21 node _T_859 = and(do_release_search[0], ldq_valid[10]) node _T_860 = and(_T_859, ldq_addr[10].valid) node _T_861 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_862 = and(_T_860, _T_861) node _T_863 = and(_T_862, block_addr_matches_10[0]) when _T_863 : connect ldq_observed[10], UInt<1>(0h1) node _T_864 = and(do_st_search[0], ldq_valid[10]) node _T_865 = and(_T_864, ldq_addr[10].valid) node _T_866 = or(ldq_executed[10], ldq_succeeded[10]) node _T_867 = and(_T_865, _T_866) node _T_868 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_869 = and(_T_867, _T_868) node _T_870 = dshr(ldq_st_dep_mask[10], lcam_stq_idx[0]) node _T_871 = bits(_T_870, 0, 0) node _T_872 = and(_T_869, _T_871) node _T_873 = and(_T_872, dword_addr_matches_10[0]) node _T_874 = and(_T_873, mask_overlap_10[0]) when _T_874 : node _forwarded_is_older_T_40 = lt(ldq_forward_stq_idx[10], lcam_stq_idx[0]) node _forwarded_is_older_T_41 = lt(ldq_forward_stq_idx[10], l_uop_10.stq_idx) node _forwarded_is_older_T_42 = xor(_forwarded_is_older_T_40, _forwarded_is_older_T_41) node _forwarded_is_older_T_43 = lt(lcam_stq_idx[0], l_uop_10.stq_idx) node forwarded_is_older_10 = xor(_forwarded_is_older_T_42, _forwarded_is_older_T_43) node _T_875 = eq(ldq_forward_std_val[10], UInt<1>(0h0)) node _T_876 = neq(ldq_forward_stq_idx[10], lcam_stq_idx[0]) node _T_877 = and(_T_876, forwarded_is_older_10) node _T_878 = or(_T_875, _T_877) when _T_878 : connect ldq_order_fail[10], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_879 = and(do_ld_search[0], ldq_valid[10]) node _T_880 = and(_T_879, ldq_addr[10].valid) node _T_881 = eq(ldq_addr_is_virtual[10], UInt<1>(0h0)) node _T_882 = and(_T_880, _T_881) node _T_883 = and(_T_882, dword_addr_matches_10[0]) node _T_884 = and(_T_883, mask_overlap_10[0]) when _T_884 : node searcher_is_older_10 = bits(lcam_younger_load_mask[0], 10, 10) node _T_885 = lt(lcam_ldq_idx[0], UInt<4>(0ha)) node _T_886 = lt(lcam_ldq_idx[0], ldq_head) node _T_887 = xor(_T_885, _T_886) node _T_888 = lt(UInt<4>(0ha), ldq_head) node _T_889 = xor(_T_887, _T_888) node _T_890 = eq(_T_889, searcher_is_older_10) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_52 assert(clock, _T_890, UInt<1>(0h1), "") : assert_52 when searcher_is_older_10 : node _T_894 = or(ldq_executed[10], ldq_succeeded[10]) node _T_895 = eq(s1_executing_loads[10], UInt<1>(0h0)) node _T_896 = and(_T_894, _T_895) node _T_897 = and(_T_896, ldq_observed[10]) when _T_897 : node _T_898 = asUInt(reset) node _T_899 = eq(_T_898, UInt<1>(0h0)) when _T_899 : node _T_900 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_900 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_53 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_53 else : node _T_901 = neq(lcam_ldq_idx[0], UInt<4>(0ha)) when _T_901 : node _T_902 = or(ldq_succeeded[10], ldq_will_succeed[10]) node _T_903 = and(ldq_executed[10], _T_902) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_906 = bits(_T_905, 4, 0) connect s1_set_execute[_T_906], UInt<1>(0h0) node _T_907 = eq(s0_kills[0], UInt<1>(0h0)) node _T_908 = and(dmem_req_fire[0], _T_907) reg REG_11 : UInt<1>, clock connect REG_11, _T_908 node _T_909 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_910 = and(REG_11, _T_909) when _T_910 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_11, ldq_uop[11] node _block_addr_matches_T_33 = shr(lcam_addr[0], 6) node _block_addr_matches_T_34 = shr(ldq_addr[11].bits, 6) node _block_addr_matches_T_35 = eq(_block_addr_matches_T_33, _block_addr_matches_T_34) wire block_addr_matches_11 : UInt<1>[1] connect block_addr_matches_11[0], _block_addr_matches_T_35 node _dword_addr_matches_T_44 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_45 = bits(ldq_addr[11].bits, 5, 3) node _dword_addr_matches_T_46 = eq(_dword_addr_matches_T_44, _dword_addr_matches_T_45) node _dword_addr_matches_T_47 = and(block_addr_matches_11[0], _dword_addr_matches_T_46) wire dword_addr_matches_11 : UInt<1>[1] connect dword_addr_matches_11[0], _dword_addr_matches_T_47 node _mask_match_T_22 = and(ldq_ld_byte_mask[11], lcam_mask[0]) node _mask_match_T_23 = eq(_mask_match_T_22, ldq_ld_byte_mask[11]) wire mask_match_11 : UInt<1>[1] connect mask_match_11[0], _mask_match_T_23 node _mask_overlap_T_22 = and(ldq_ld_byte_mask[11], lcam_mask[0]) node _mask_overlap_T_23 = orr(_mask_overlap_T_22) wire mask_overlap_11 : UInt<1>[1] connect mask_overlap_11[0], _mask_overlap_T_23 node _T_911 = and(do_release_search[0], ldq_valid[11]) node _T_912 = and(_T_911, ldq_addr[11].valid) node _T_913 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_914 = and(_T_912, _T_913) node _T_915 = and(_T_914, block_addr_matches_11[0]) when _T_915 : connect ldq_observed[11], UInt<1>(0h1) node _T_916 = and(do_st_search[0], ldq_valid[11]) node _T_917 = and(_T_916, ldq_addr[11].valid) node _T_918 = or(ldq_executed[11], ldq_succeeded[11]) node _T_919 = and(_T_917, _T_918) node _T_920 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) node _T_922 = dshr(ldq_st_dep_mask[11], lcam_stq_idx[0]) node _T_923 = bits(_T_922, 0, 0) node _T_924 = and(_T_921, _T_923) node _T_925 = and(_T_924, dword_addr_matches_11[0]) node _T_926 = and(_T_925, mask_overlap_11[0]) when _T_926 : node _forwarded_is_older_T_44 = lt(ldq_forward_stq_idx[11], lcam_stq_idx[0]) node _forwarded_is_older_T_45 = lt(ldq_forward_stq_idx[11], l_uop_11.stq_idx) node _forwarded_is_older_T_46 = xor(_forwarded_is_older_T_44, _forwarded_is_older_T_45) node _forwarded_is_older_T_47 = lt(lcam_stq_idx[0], l_uop_11.stq_idx) node forwarded_is_older_11 = xor(_forwarded_is_older_T_46, _forwarded_is_older_T_47) node _T_927 = eq(ldq_forward_std_val[11], UInt<1>(0h0)) node _T_928 = neq(ldq_forward_stq_idx[11], lcam_stq_idx[0]) node _T_929 = and(_T_928, forwarded_is_older_11) node _T_930 = or(_T_927, _T_929) when _T_930 : connect ldq_order_fail[11], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_931 = and(do_ld_search[0], ldq_valid[11]) node _T_932 = and(_T_931, ldq_addr[11].valid) node _T_933 = eq(ldq_addr_is_virtual[11], UInt<1>(0h0)) node _T_934 = and(_T_932, _T_933) node _T_935 = and(_T_934, dword_addr_matches_11[0]) node _T_936 = and(_T_935, mask_overlap_11[0]) when _T_936 : node searcher_is_older_11 = bits(lcam_younger_load_mask[0], 11, 11) node _T_937 = lt(lcam_ldq_idx[0], UInt<4>(0hb)) node _T_938 = lt(lcam_ldq_idx[0], ldq_head) node _T_939 = xor(_T_937, _T_938) node _T_940 = lt(UInt<4>(0hb), ldq_head) node _T_941 = xor(_T_939, _T_940) node _T_942 = eq(_T_941, searcher_is_older_11) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_54 assert(clock, _T_942, UInt<1>(0h1), "") : assert_54 when searcher_is_older_11 : node _T_946 = or(ldq_executed[11], ldq_succeeded[11]) node _T_947 = eq(s1_executing_loads[11], UInt<1>(0h0)) node _T_948 = and(_T_946, _T_947) node _T_949 = and(_T_948, ldq_observed[11]) when _T_949 : node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_55 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_55 else : node _T_953 = neq(lcam_ldq_idx[0], UInt<4>(0hb)) when _T_953 : node _T_954 = or(ldq_succeeded[11], ldq_will_succeed[11]) node _T_955 = and(ldq_executed[11], _T_954) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_958 = bits(_T_957, 4, 0) connect s1_set_execute[_T_958], UInt<1>(0h0) node _T_959 = eq(s0_kills[0], UInt<1>(0h0)) node _T_960 = and(dmem_req_fire[0], _T_959) reg REG_12 : UInt<1>, clock connect REG_12, _T_960 node _T_961 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_962 = and(REG_12, _T_961) when _T_962 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_12, ldq_uop[12] node _block_addr_matches_T_36 = shr(lcam_addr[0], 6) node _block_addr_matches_T_37 = shr(ldq_addr[12].bits, 6) node _block_addr_matches_T_38 = eq(_block_addr_matches_T_36, _block_addr_matches_T_37) wire block_addr_matches_12 : UInt<1>[1] connect block_addr_matches_12[0], _block_addr_matches_T_38 node _dword_addr_matches_T_48 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_49 = bits(ldq_addr[12].bits, 5, 3) node _dword_addr_matches_T_50 = eq(_dword_addr_matches_T_48, _dword_addr_matches_T_49) node _dword_addr_matches_T_51 = and(block_addr_matches_12[0], _dword_addr_matches_T_50) wire dword_addr_matches_12 : UInt<1>[1] connect dword_addr_matches_12[0], _dword_addr_matches_T_51 node _mask_match_T_24 = and(ldq_ld_byte_mask[12], lcam_mask[0]) node _mask_match_T_25 = eq(_mask_match_T_24, ldq_ld_byte_mask[12]) wire mask_match_12 : UInt<1>[1] connect mask_match_12[0], _mask_match_T_25 node _mask_overlap_T_24 = and(ldq_ld_byte_mask[12], lcam_mask[0]) node _mask_overlap_T_25 = orr(_mask_overlap_T_24) wire mask_overlap_12 : UInt<1>[1] connect mask_overlap_12[0], _mask_overlap_T_25 node _T_963 = and(do_release_search[0], ldq_valid[12]) node _T_964 = and(_T_963, ldq_addr[12].valid) node _T_965 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_966 = and(_T_964, _T_965) node _T_967 = and(_T_966, block_addr_matches_12[0]) when _T_967 : connect ldq_observed[12], UInt<1>(0h1) node _T_968 = and(do_st_search[0], ldq_valid[12]) node _T_969 = and(_T_968, ldq_addr[12].valid) node _T_970 = or(ldq_executed[12], ldq_succeeded[12]) node _T_971 = and(_T_969, _T_970) node _T_972 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_973 = and(_T_971, _T_972) node _T_974 = dshr(ldq_st_dep_mask[12], lcam_stq_idx[0]) node _T_975 = bits(_T_974, 0, 0) node _T_976 = and(_T_973, _T_975) node _T_977 = and(_T_976, dword_addr_matches_12[0]) node _T_978 = and(_T_977, mask_overlap_12[0]) when _T_978 : node _forwarded_is_older_T_48 = lt(ldq_forward_stq_idx[12], lcam_stq_idx[0]) node _forwarded_is_older_T_49 = lt(ldq_forward_stq_idx[12], l_uop_12.stq_idx) node _forwarded_is_older_T_50 = xor(_forwarded_is_older_T_48, _forwarded_is_older_T_49) node _forwarded_is_older_T_51 = lt(lcam_stq_idx[0], l_uop_12.stq_idx) node forwarded_is_older_12 = xor(_forwarded_is_older_T_50, _forwarded_is_older_T_51) node _T_979 = eq(ldq_forward_std_val[12], UInt<1>(0h0)) node _T_980 = neq(ldq_forward_stq_idx[12], lcam_stq_idx[0]) node _T_981 = and(_T_980, forwarded_is_older_12) node _T_982 = or(_T_979, _T_981) when _T_982 : connect ldq_order_fail[12], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_983 = and(do_ld_search[0], ldq_valid[12]) node _T_984 = and(_T_983, ldq_addr[12].valid) node _T_985 = eq(ldq_addr_is_virtual[12], UInt<1>(0h0)) node _T_986 = and(_T_984, _T_985) node _T_987 = and(_T_986, dword_addr_matches_12[0]) node _T_988 = and(_T_987, mask_overlap_12[0]) when _T_988 : node searcher_is_older_12 = bits(lcam_younger_load_mask[0], 12, 12) node _T_989 = lt(lcam_ldq_idx[0], UInt<4>(0hc)) node _T_990 = lt(lcam_ldq_idx[0], ldq_head) node _T_991 = xor(_T_989, _T_990) node _T_992 = lt(UInt<4>(0hc), ldq_head) node _T_993 = xor(_T_991, _T_992) node _T_994 = eq(_T_993, searcher_is_older_12) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_56 assert(clock, _T_994, UInt<1>(0h1), "") : assert_56 when searcher_is_older_12 : node _T_998 = or(ldq_executed[12], ldq_succeeded[12]) node _T_999 = eq(s1_executing_loads[12], UInt<1>(0h0)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = and(_T_1000, ldq_observed[12]) when _T_1001 : node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_57 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_57 else : node _T_1005 = neq(lcam_ldq_idx[0], UInt<4>(0hc)) when _T_1005 : node _T_1006 = or(ldq_succeeded[12], ldq_will_succeed[12]) node _T_1007 = and(ldq_executed[12], _T_1006) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1010 = bits(_T_1009, 4, 0) connect s1_set_execute[_T_1010], UInt<1>(0h0) node _T_1011 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1012 = and(dmem_req_fire[0], _T_1011) reg REG_13 : UInt<1>, clock connect REG_13, _T_1012 node _T_1013 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1014 = and(REG_13, _T_1013) when _T_1014 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_13, ldq_uop[13] node _block_addr_matches_T_39 = shr(lcam_addr[0], 6) node _block_addr_matches_T_40 = shr(ldq_addr[13].bits, 6) node _block_addr_matches_T_41 = eq(_block_addr_matches_T_39, _block_addr_matches_T_40) wire block_addr_matches_13 : UInt<1>[1] connect block_addr_matches_13[0], _block_addr_matches_T_41 node _dword_addr_matches_T_52 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_53 = bits(ldq_addr[13].bits, 5, 3) node _dword_addr_matches_T_54 = eq(_dword_addr_matches_T_52, _dword_addr_matches_T_53) node _dword_addr_matches_T_55 = and(block_addr_matches_13[0], _dword_addr_matches_T_54) wire dword_addr_matches_13 : UInt<1>[1] connect dword_addr_matches_13[0], _dword_addr_matches_T_55 node _mask_match_T_26 = and(ldq_ld_byte_mask[13], lcam_mask[0]) node _mask_match_T_27 = eq(_mask_match_T_26, ldq_ld_byte_mask[13]) wire mask_match_13 : UInt<1>[1] connect mask_match_13[0], _mask_match_T_27 node _mask_overlap_T_26 = and(ldq_ld_byte_mask[13], lcam_mask[0]) node _mask_overlap_T_27 = orr(_mask_overlap_T_26) wire mask_overlap_13 : UInt<1>[1] connect mask_overlap_13[0], _mask_overlap_T_27 node _T_1015 = and(do_release_search[0], ldq_valid[13]) node _T_1016 = and(_T_1015, ldq_addr[13].valid) node _T_1017 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = and(_T_1018, block_addr_matches_13[0]) when _T_1019 : connect ldq_observed[13], UInt<1>(0h1) node _T_1020 = and(do_st_search[0], ldq_valid[13]) node _T_1021 = and(_T_1020, ldq_addr[13].valid) node _T_1022 = or(ldq_executed[13], ldq_succeeded[13]) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1025 = and(_T_1023, _T_1024) node _T_1026 = dshr(ldq_st_dep_mask[13], lcam_stq_idx[0]) node _T_1027 = bits(_T_1026, 0, 0) node _T_1028 = and(_T_1025, _T_1027) node _T_1029 = and(_T_1028, dword_addr_matches_13[0]) node _T_1030 = and(_T_1029, mask_overlap_13[0]) when _T_1030 : node _forwarded_is_older_T_52 = lt(ldq_forward_stq_idx[13], lcam_stq_idx[0]) node _forwarded_is_older_T_53 = lt(ldq_forward_stq_idx[13], l_uop_13.stq_idx) node _forwarded_is_older_T_54 = xor(_forwarded_is_older_T_52, _forwarded_is_older_T_53) node _forwarded_is_older_T_55 = lt(lcam_stq_idx[0], l_uop_13.stq_idx) node forwarded_is_older_13 = xor(_forwarded_is_older_T_54, _forwarded_is_older_T_55) node _T_1031 = eq(ldq_forward_std_val[13], UInt<1>(0h0)) node _T_1032 = neq(ldq_forward_stq_idx[13], lcam_stq_idx[0]) node _T_1033 = and(_T_1032, forwarded_is_older_13) node _T_1034 = or(_T_1031, _T_1033) when _T_1034 : connect ldq_order_fail[13], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1035 = and(do_ld_search[0], ldq_valid[13]) node _T_1036 = and(_T_1035, ldq_addr[13].valid) node _T_1037 = eq(ldq_addr_is_virtual[13], UInt<1>(0h0)) node _T_1038 = and(_T_1036, _T_1037) node _T_1039 = and(_T_1038, dword_addr_matches_13[0]) node _T_1040 = and(_T_1039, mask_overlap_13[0]) when _T_1040 : node searcher_is_older_13 = bits(lcam_younger_load_mask[0], 13, 13) node _T_1041 = lt(lcam_ldq_idx[0], UInt<4>(0hd)) node _T_1042 = lt(lcam_ldq_idx[0], ldq_head) node _T_1043 = xor(_T_1041, _T_1042) node _T_1044 = lt(UInt<4>(0hd), ldq_head) node _T_1045 = xor(_T_1043, _T_1044) node _T_1046 = eq(_T_1045, searcher_is_older_13) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_58 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_58 when searcher_is_older_13 : node _T_1050 = or(ldq_executed[13], ldq_succeeded[13]) node _T_1051 = eq(s1_executing_loads[13], UInt<1>(0h0)) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = and(_T_1052, ldq_observed[13]) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_59 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_59 else : node _T_1057 = neq(lcam_ldq_idx[0], UInt<4>(0hd)) when _T_1057 : node _T_1058 = or(ldq_succeeded[13], ldq_will_succeed[13]) node _T_1059 = and(ldq_executed[13], _T_1058) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1062 = bits(_T_1061, 4, 0) connect s1_set_execute[_T_1062], UInt<1>(0h0) node _T_1063 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1064 = and(dmem_req_fire[0], _T_1063) reg REG_14 : UInt<1>, clock connect REG_14, _T_1064 node _T_1065 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1066 = and(REG_14, _T_1065) when _T_1066 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_14, ldq_uop[14] node _block_addr_matches_T_42 = shr(lcam_addr[0], 6) node _block_addr_matches_T_43 = shr(ldq_addr[14].bits, 6) node _block_addr_matches_T_44 = eq(_block_addr_matches_T_42, _block_addr_matches_T_43) wire block_addr_matches_14 : UInt<1>[1] connect block_addr_matches_14[0], _block_addr_matches_T_44 node _dword_addr_matches_T_56 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_57 = bits(ldq_addr[14].bits, 5, 3) node _dword_addr_matches_T_58 = eq(_dword_addr_matches_T_56, _dword_addr_matches_T_57) node _dword_addr_matches_T_59 = and(block_addr_matches_14[0], _dword_addr_matches_T_58) wire dword_addr_matches_14 : UInt<1>[1] connect dword_addr_matches_14[0], _dword_addr_matches_T_59 node _mask_match_T_28 = and(ldq_ld_byte_mask[14], lcam_mask[0]) node _mask_match_T_29 = eq(_mask_match_T_28, ldq_ld_byte_mask[14]) wire mask_match_14 : UInt<1>[1] connect mask_match_14[0], _mask_match_T_29 node _mask_overlap_T_28 = and(ldq_ld_byte_mask[14], lcam_mask[0]) node _mask_overlap_T_29 = orr(_mask_overlap_T_28) wire mask_overlap_14 : UInt<1>[1] connect mask_overlap_14[0], _mask_overlap_T_29 node _T_1067 = and(do_release_search[0], ldq_valid[14]) node _T_1068 = and(_T_1067, ldq_addr[14].valid) node _T_1069 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = and(_T_1070, block_addr_matches_14[0]) when _T_1071 : connect ldq_observed[14], UInt<1>(0h1) node _T_1072 = and(do_st_search[0], ldq_valid[14]) node _T_1073 = and(_T_1072, ldq_addr[14].valid) node _T_1074 = or(ldq_executed[14], ldq_succeeded[14]) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = dshr(ldq_st_dep_mask[14], lcam_stq_idx[0]) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = and(_T_1077, _T_1079) node _T_1081 = and(_T_1080, dword_addr_matches_14[0]) node _T_1082 = and(_T_1081, mask_overlap_14[0]) when _T_1082 : node _forwarded_is_older_T_56 = lt(ldq_forward_stq_idx[14], lcam_stq_idx[0]) node _forwarded_is_older_T_57 = lt(ldq_forward_stq_idx[14], l_uop_14.stq_idx) node _forwarded_is_older_T_58 = xor(_forwarded_is_older_T_56, _forwarded_is_older_T_57) node _forwarded_is_older_T_59 = lt(lcam_stq_idx[0], l_uop_14.stq_idx) node forwarded_is_older_14 = xor(_forwarded_is_older_T_58, _forwarded_is_older_T_59) node _T_1083 = eq(ldq_forward_std_val[14], UInt<1>(0h0)) node _T_1084 = neq(ldq_forward_stq_idx[14], lcam_stq_idx[0]) node _T_1085 = and(_T_1084, forwarded_is_older_14) node _T_1086 = or(_T_1083, _T_1085) when _T_1086 : connect ldq_order_fail[14], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1087 = and(do_ld_search[0], ldq_valid[14]) node _T_1088 = and(_T_1087, ldq_addr[14].valid) node _T_1089 = eq(ldq_addr_is_virtual[14], UInt<1>(0h0)) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = and(_T_1090, dword_addr_matches_14[0]) node _T_1092 = and(_T_1091, mask_overlap_14[0]) when _T_1092 : node searcher_is_older_14 = bits(lcam_younger_load_mask[0], 14, 14) node _T_1093 = lt(lcam_ldq_idx[0], UInt<4>(0he)) node _T_1094 = lt(lcam_ldq_idx[0], ldq_head) node _T_1095 = xor(_T_1093, _T_1094) node _T_1096 = lt(UInt<4>(0he), ldq_head) node _T_1097 = xor(_T_1095, _T_1096) node _T_1098 = eq(_T_1097, searcher_is_older_14) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_60 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_60 when searcher_is_older_14 : node _T_1102 = or(ldq_executed[14], ldq_succeeded[14]) node _T_1103 = eq(s1_executing_loads[14], UInt<1>(0h0)) node _T_1104 = and(_T_1102, _T_1103) node _T_1105 = and(_T_1104, ldq_observed[14]) when _T_1105 : node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_61 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_61 else : node _T_1109 = neq(lcam_ldq_idx[0], UInt<4>(0he)) when _T_1109 : node _T_1110 = or(ldq_succeeded[14], ldq_will_succeed[14]) node _T_1111 = and(ldq_executed[14], _T_1110) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1114 = bits(_T_1113, 4, 0) connect s1_set_execute[_T_1114], UInt<1>(0h0) node _T_1115 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1116 = and(dmem_req_fire[0], _T_1115) reg REG_15 : UInt<1>, clock connect REG_15, _T_1116 node _T_1117 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1118 = and(REG_15, _T_1117) when _T_1118 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_15, ldq_uop[15] node _block_addr_matches_T_45 = shr(lcam_addr[0], 6) node _block_addr_matches_T_46 = shr(ldq_addr[15].bits, 6) node _block_addr_matches_T_47 = eq(_block_addr_matches_T_45, _block_addr_matches_T_46) wire block_addr_matches_15 : UInt<1>[1] connect block_addr_matches_15[0], _block_addr_matches_T_47 node _dword_addr_matches_T_60 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_61 = bits(ldq_addr[15].bits, 5, 3) node _dword_addr_matches_T_62 = eq(_dword_addr_matches_T_60, _dword_addr_matches_T_61) node _dword_addr_matches_T_63 = and(block_addr_matches_15[0], _dword_addr_matches_T_62) wire dword_addr_matches_15 : UInt<1>[1] connect dword_addr_matches_15[0], _dword_addr_matches_T_63 node _mask_match_T_30 = and(ldq_ld_byte_mask[15], lcam_mask[0]) node _mask_match_T_31 = eq(_mask_match_T_30, ldq_ld_byte_mask[15]) wire mask_match_15 : UInt<1>[1] connect mask_match_15[0], _mask_match_T_31 node _mask_overlap_T_30 = and(ldq_ld_byte_mask[15], lcam_mask[0]) node _mask_overlap_T_31 = orr(_mask_overlap_T_30) wire mask_overlap_15 : UInt<1>[1] connect mask_overlap_15[0], _mask_overlap_T_31 node _T_1119 = and(do_release_search[0], ldq_valid[15]) node _T_1120 = and(_T_1119, ldq_addr[15].valid) node _T_1121 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1122 = and(_T_1120, _T_1121) node _T_1123 = and(_T_1122, block_addr_matches_15[0]) when _T_1123 : connect ldq_observed[15], UInt<1>(0h1) node _T_1124 = and(do_st_search[0], ldq_valid[15]) node _T_1125 = and(_T_1124, ldq_addr[15].valid) node _T_1126 = or(ldq_executed[15], ldq_succeeded[15]) node _T_1127 = and(_T_1125, _T_1126) node _T_1128 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = dshr(ldq_st_dep_mask[15], lcam_stq_idx[0]) node _T_1131 = bits(_T_1130, 0, 0) node _T_1132 = and(_T_1129, _T_1131) node _T_1133 = and(_T_1132, dword_addr_matches_15[0]) node _T_1134 = and(_T_1133, mask_overlap_15[0]) when _T_1134 : node _forwarded_is_older_T_60 = lt(ldq_forward_stq_idx[15], lcam_stq_idx[0]) node _forwarded_is_older_T_61 = lt(ldq_forward_stq_idx[15], l_uop_15.stq_idx) node _forwarded_is_older_T_62 = xor(_forwarded_is_older_T_60, _forwarded_is_older_T_61) node _forwarded_is_older_T_63 = lt(lcam_stq_idx[0], l_uop_15.stq_idx) node forwarded_is_older_15 = xor(_forwarded_is_older_T_62, _forwarded_is_older_T_63) node _T_1135 = eq(ldq_forward_std_val[15], UInt<1>(0h0)) node _T_1136 = neq(ldq_forward_stq_idx[15], lcam_stq_idx[0]) node _T_1137 = and(_T_1136, forwarded_is_older_15) node _T_1138 = or(_T_1135, _T_1137) when _T_1138 : connect ldq_order_fail[15], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1139 = and(do_ld_search[0], ldq_valid[15]) node _T_1140 = and(_T_1139, ldq_addr[15].valid) node _T_1141 = eq(ldq_addr_is_virtual[15], UInt<1>(0h0)) node _T_1142 = and(_T_1140, _T_1141) node _T_1143 = and(_T_1142, dword_addr_matches_15[0]) node _T_1144 = and(_T_1143, mask_overlap_15[0]) when _T_1144 : node searcher_is_older_15 = bits(lcam_younger_load_mask[0], 15, 15) node _T_1145 = lt(lcam_ldq_idx[0], UInt<4>(0hf)) node _T_1146 = lt(lcam_ldq_idx[0], ldq_head) node _T_1147 = xor(_T_1145, _T_1146) node _T_1148 = lt(UInt<4>(0hf), ldq_head) node _T_1149 = xor(_T_1147, _T_1148) node _T_1150 = eq(_T_1149, searcher_is_older_15) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_62 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_62 when searcher_is_older_15 : node _T_1154 = or(ldq_executed[15], ldq_succeeded[15]) node _T_1155 = eq(s1_executing_loads[15], UInt<1>(0h0)) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = and(_T_1156, ldq_observed[15]) when _T_1157 : node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_63 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_63 else : node _T_1161 = neq(lcam_ldq_idx[0], UInt<4>(0hf)) when _T_1161 : node _T_1162 = or(ldq_succeeded[15], ldq_will_succeed[15]) node _T_1163 = and(ldq_executed[15], _T_1162) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1166 = bits(_T_1165, 4, 0) connect s1_set_execute[_T_1166], UInt<1>(0h0) node _T_1167 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1168 = and(dmem_req_fire[0], _T_1167) reg REG_16 : UInt<1>, clock connect REG_16, _T_1168 node _T_1169 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1170 = and(REG_16, _T_1169) when _T_1170 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_16, ldq_uop[16] node _block_addr_matches_T_48 = shr(lcam_addr[0], 6) node _block_addr_matches_T_49 = shr(ldq_addr[16].bits, 6) node _block_addr_matches_T_50 = eq(_block_addr_matches_T_48, _block_addr_matches_T_49) wire block_addr_matches_16 : UInt<1>[1] connect block_addr_matches_16[0], _block_addr_matches_T_50 node _dword_addr_matches_T_64 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_65 = bits(ldq_addr[16].bits, 5, 3) node _dword_addr_matches_T_66 = eq(_dword_addr_matches_T_64, _dword_addr_matches_T_65) node _dword_addr_matches_T_67 = and(block_addr_matches_16[0], _dword_addr_matches_T_66) wire dword_addr_matches_16 : UInt<1>[1] connect dword_addr_matches_16[0], _dword_addr_matches_T_67 node _mask_match_T_32 = and(ldq_ld_byte_mask[16], lcam_mask[0]) node _mask_match_T_33 = eq(_mask_match_T_32, ldq_ld_byte_mask[16]) wire mask_match_16 : UInt<1>[1] connect mask_match_16[0], _mask_match_T_33 node _mask_overlap_T_32 = and(ldq_ld_byte_mask[16], lcam_mask[0]) node _mask_overlap_T_33 = orr(_mask_overlap_T_32) wire mask_overlap_16 : UInt<1>[1] connect mask_overlap_16[0], _mask_overlap_T_33 node _T_1171 = and(do_release_search[0], ldq_valid[16]) node _T_1172 = and(_T_1171, ldq_addr[16].valid) node _T_1173 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1174 = and(_T_1172, _T_1173) node _T_1175 = and(_T_1174, block_addr_matches_16[0]) when _T_1175 : connect ldq_observed[16], UInt<1>(0h1) node _T_1176 = and(do_st_search[0], ldq_valid[16]) node _T_1177 = and(_T_1176, ldq_addr[16].valid) node _T_1178 = or(ldq_executed[16], ldq_succeeded[16]) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1181 = and(_T_1179, _T_1180) node _T_1182 = dshr(ldq_st_dep_mask[16], lcam_stq_idx[0]) node _T_1183 = bits(_T_1182, 0, 0) node _T_1184 = and(_T_1181, _T_1183) node _T_1185 = and(_T_1184, dword_addr_matches_16[0]) node _T_1186 = and(_T_1185, mask_overlap_16[0]) when _T_1186 : node _forwarded_is_older_T_64 = lt(ldq_forward_stq_idx[16], lcam_stq_idx[0]) node _forwarded_is_older_T_65 = lt(ldq_forward_stq_idx[16], l_uop_16.stq_idx) node _forwarded_is_older_T_66 = xor(_forwarded_is_older_T_64, _forwarded_is_older_T_65) node _forwarded_is_older_T_67 = lt(lcam_stq_idx[0], l_uop_16.stq_idx) node forwarded_is_older_16 = xor(_forwarded_is_older_T_66, _forwarded_is_older_T_67) node _T_1187 = eq(ldq_forward_std_val[16], UInt<1>(0h0)) node _T_1188 = neq(ldq_forward_stq_idx[16], lcam_stq_idx[0]) node _T_1189 = and(_T_1188, forwarded_is_older_16) node _T_1190 = or(_T_1187, _T_1189) when _T_1190 : connect ldq_order_fail[16], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1191 = and(do_ld_search[0], ldq_valid[16]) node _T_1192 = and(_T_1191, ldq_addr[16].valid) node _T_1193 = eq(ldq_addr_is_virtual[16], UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) node _T_1195 = and(_T_1194, dword_addr_matches_16[0]) node _T_1196 = and(_T_1195, mask_overlap_16[0]) when _T_1196 : node searcher_is_older_16 = bits(lcam_younger_load_mask[0], 16, 16) node _T_1197 = lt(lcam_ldq_idx[0], UInt<5>(0h10)) node _T_1198 = lt(lcam_ldq_idx[0], ldq_head) node _T_1199 = xor(_T_1197, _T_1198) node _T_1200 = lt(UInt<5>(0h10), ldq_head) node _T_1201 = xor(_T_1199, _T_1200) node _T_1202 = eq(_T_1201, searcher_is_older_16) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_64 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_64 when searcher_is_older_16 : node _T_1206 = or(ldq_executed[16], ldq_succeeded[16]) node _T_1207 = eq(s1_executing_loads[16], UInt<1>(0h0)) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = and(_T_1208, ldq_observed[16]) when _T_1209 : node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_65 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_65 else : node _T_1213 = neq(lcam_ldq_idx[0], UInt<5>(0h10)) when _T_1213 : node _T_1214 = or(ldq_succeeded[16], ldq_will_succeed[16]) node _T_1215 = and(ldq_executed[16], _T_1214) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1218 = bits(_T_1217, 4, 0) connect s1_set_execute[_T_1218], UInt<1>(0h0) node _T_1219 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1220 = and(dmem_req_fire[0], _T_1219) reg REG_17 : UInt<1>, clock connect REG_17, _T_1220 node _T_1221 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1222 = and(REG_17, _T_1221) when _T_1222 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_17, ldq_uop[17] node _block_addr_matches_T_51 = shr(lcam_addr[0], 6) node _block_addr_matches_T_52 = shr(ldq_addr[17].bits, 6) node _block_addr_matches_T_53 = eq(_block_addr_matches_T_51, _block_addr_matches_T_52) wire block_addr_matches_17 : UInt<1>[1] connect block_addr_matches_17[0], _block_addr_matches_T_53 node _dword_addr_matches_T_68 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_69 = bits(ldq_addr[17].bits, 5, 3) node _dword_addr_matches_T_70 = eq(_dword_addr_matches_T_68, _dword_addr_matches_T_69) node _dword_addr_matches_T_71 = and(block_addr_matches_17[0], _dword_addr_matches_T_70) wire dword_addr_matches_17 : UInt<1>[1] connect dword_addr_matches_17[0], _dword_addr_matches_T_71 node _mask_match_T_34 = and(ldq_ld_byte_mask[17], lcam_mask[0]) node _mask_match_T_35 = eq(_mask_match_T_34, ldq_ld_byte_mask[17]) wire mask_match_17 : UInt<1>[1] connect mask_match_17[0], _mask_match_T_35 node _mask_overlap_T_34 = and(ldq_ld_byte_mask[17], lcam_mask[0]) node _mask_overlap_T_35 = orr(_mask_overlap_T_34) wire mask_overlap_17 : UInt<1>[1] connect mask_overlap_17[0], _mask_overlap_T_35 node _T_1223 = and(do_release_search[0], ldq_valid[17]) node _T_1224 = and(_T_1223, ldq_addr[17].valid) node _T_1225 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) node _T_1227 = and(_T_1226, block_addr_matches_17[0]) when _T_1227 : connect ldq_observed[17], UInt<1>(0h1) node _T_1228 = and(do_st_search[0], ldq_valid[17]) node _T_1229 = and(_T_1228, ldq_addr[17].valid) node _T_1230 = or(ldq_executed[17], ldq_succeeded[17]) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = dshr(ldq_st_dep_mask[17], lcam_stq_idx[0]) node _T_1235 = bits(_T_1234, 0, 0) node _T_1236 = and(_T_1233, _T_1235) node _T_1237 = and(_T_1236, dword_addr_matches_17[0]) node _T_1238 = and(_T_1237, mask_overlap_17[0]) when _T_1238 : node _forwarded_is_older_T_68 = lt(ldq_forward_stq_idx[17], lcam_stq_idx[0]) node _forwarded_is_older_T_69 = lt(ldq_forward_stq_idx[17], l_uop_17.stq_idx) node _forwarded_is_older_T_70 = xor(_forwarded_is_older_T_68, _forwarded_is_older_T_69) node _forwarded_is_older_T_71 = lt(lcam_stq_idx[0], l_uop_17.stq_idx) node forwarded_is_older_17 = xor(_forwarded_is_older_T_70, _forwarded_is_older_T_71) node _T_1239 = eq(ldq_forward_std_val[17], UInt<1>(0h0)) node _T_1240 = neq(ldq_forward_stq_idx[17], lcam_stq_idx[0]) node _T_1241 = and(_T_1240, forwarded_is_older_17) node _T_1242 = or(_T_1239, _T_1241) when _T_1242 : connect ldq_order_fail[17], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1243 = and(do_ld_search[0], ldq_valid[17]) node _T_1244 = and(_T_1243, ldq_addr[17].valid) node _T_1245 = eq(ldq_addr_is_virtual[17], UInt<1>(0h0)) node _T_1246 = and(_T_1244, _T_1245) node _T_1247 = and(_T_1246, dword_addr_matches_17[0]) node _T_1248 = and(_T_1247, mask_overlap_17[0]) when _T_1248 : node searcher_is_older_17 = bits(lcam_younger_load_mask[0], 17, 17) node _T_1249 = lt(lcam_ldq_idx[0], UInt<5>(0h11)) node _T_1250 = lt(lcam_ldq_idx[0], ldq_head) node _T_1251 = xor(_T_1249, _T_1250) node _T_1252 = lt(UInt<5>(0h11), ldq_head) node _T_1253 = xor(_T_1251, _T_1252) node _T_1254 = eq(_T_1253, searcher_is_older_17) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_66 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_66 when searcher_is_older_17 : node _T_1258 = or(ldq_executed[17], ldq_succeeded[17]) node _T_1259 = eq(s1_executing_loads[17], UInt<1>(0h0)) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, ldq_observed[17]) when _T_1261 : node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_67 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_67 else : node _T_1265 = neq(lcam_ldq_idx[0], UInt<5>(0h11)) when _T_1265 : node _T_1266 = or(ldq_succeeded[17], ldq_will_succeed[17]) node _T_1267 = and(ldq_executed[17], _T_1266) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1270 = bits(_T_1269, 4, 0) connect s1_set_execute[_T_1270], UInt<1>(0h0) node _T_1271 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1272 = and(dmem_req_fire[0], _T_1271) reg REG_18 : UInt<1>, clock connect REG_18, _T_1272 node _T_1273 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1274 = and(REG_18, _T_1273) when _T_1274 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_18, ldq_uop[18] node _block_addr_matches_T_54 = shr(lcam_addr[0], 6) node _block_addr_matches_T_55 = shr(ldq_addr[18].bits, 6) node _block_addr_matches_T_56 = eq(_block_addr_matches_T_54, _block_addr_matches_T_55) wire block_addr_matches_18 : UInt<1>[1] connect block_addr_matches_18[0], _block_addr_matches_T_56 node _dword_addr_matches_T_72 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_73 = bits(ldq_addr[18].bits, 5, 3) node _dword_addr_matches_T_74 = eq(_dword_addr_matches_T_72, _dword_addr_matches_T_73) node _dword_addr_matches_T_75 = and(block_addr_matches_18[0], _dword_addr_matches_T_74) wire dword_addr_matches_18 : UInt<1>[1] connect dword_addr_matches_18[0], _dword_addr_matches_T_75 node _mask_match_T_36 = and(ldq_ld_byte_mask[18], lcam_mask[0]) node _mask_match_T_37 = eq(_mask_match_T_36, ldq_ld_byte_mask[18]) wire mask_match_18 : UInt<1>[1] connect mask_match_18[0], _mask_match_T_37 node _mask_overlap_T_36 = and(ldq_ld_byte_mask[18], lcam_mask[0]) node _mask_overlap_T_37 = orr(_mask_overlap_T_36) wire mask_overlap_18 : UInt<1>[1] connect mask_overlap_18[0], _mask_overlap_T_37 node _T_1275 = and(do_release_search[0], ldq_valid[18]) node _T_1276 = and(_T_1275, ldq_addr[18].valid) node _T_1277 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1278 = and(_T_1276, _T_1277) node _T_1279 = and(_T_1278, block_addr_matches_18[0]) when _T_1279 : connect ldq_observed[18], UInt<1>(0h1) node _T_1280 = and(do_st_search[0], ldq_valid[18]) node _T_1281 = and(_T_1280, ldq_addr[18].valid) node _T_1282 = or(ldq_executed[18], ldq_succeeded[18]) node _T_1283 = and(_T_1281, _T_1282) node _T_1284 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1285 = and(_T_1283, _T_1284) node _T_1286 = dshr(ldq_st_dep_mask[18], lcam_stq_idx[0]) node _T_1287 = bits(_T_1286, 0, 0) node _T_1288 = and(_T_1285, _T_1287) node _T_1289 = and(_T_1288, dword_addr_matches_18[0]) node _T_1290 = and(_T_1289, mask_overlap_18[0]) when _T_1290 : node _forwarded_is_older_T_72 = lt(ldq_forward_stq_idx[18], lcam_stq_idx[0]) node _forwarded_is_older_T_73 = lt(ldq_forward_stq_idx[18], l_uop_18.stq_idx) node _forwarded_is_older_T_74 = xor(_forwarded_is_older_T_72, _forwarded_is_older_T_73) node _forwarded_is_older_T_75 = lt(lcam_stq_idx[0], l_uop_18.stq_idx) node forwarded_is_older_18 = xor(_forwarded_is_older_T_74, _forwarded_is_older_T_75) node _T_1291 = eq(ldq_forward_std_val[18], UInt<1>(0h0)) node _T_1292 = neq(ldq_forward_stq_idx[18], lcam_stq_idx[0]) node _T_1293 = and(_T_1292, forwarded_is_older_18) node _T_1294 = or(_T_1291, _T_1293) when _T_1294 : connect ldq_order_fail[18], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1295 = and(do_ld_search[0], ldq_valid[18]) node _T_1296 = and(_T_1295, ldq_addr[18].valid) node _T_1297 = eq(ldq_addr_is_virtual[18], UInt<1>(0h0)) node _T_1298 = and(_T_1296, _T_1297) node _T_1299 = and(_T_1298, dword_addr_matches_18[0]) node _T_1300 = and(_T_1299, mask_overlap_18[0]) when _T_1300 : node searcher_is_older_18 = bits(lcam_younger_load_mask[0], 18, 18) node _T_1301 = lt(lcam_ldq_idx[0], UInt<5>(0h12)) node _T_1302 = lt(lcam_ldq_idx[0], ldq_head) node _T_1303 = xor(_T_1301, _T_1302) node _T_1304 = lt(UInt<5>(0h12), ldq_head) node _T_1305 = xor(_T_1303, _T_1304) node _T_1306 = eq(_T_1305, searcher_is_older_18) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_68 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_68 when searcher_is_older_18 : node _T_1310 = or(ldq_executed[18], ldq_succeeded[18]) node _T_1311 = eq(s1_executing_loads[18], UInt<1>(0h0)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = and(_T_1312, ldq_observed[18]) when _T_1313 : node _T_1314 = asUInt(reset) node _T_1315 = eq(_T_1314, UInt<1>(0h0)) when _T_1315 : node _T_1316 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1316 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_69 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_69 else : node _T_1317 = neq(lcam_ldq_idx[0], UInt<5>(0h12)) when _T_1317 : node _T_1318 = or(ldq_succeeded[18], ldq_will_succeed[18]) node _T_1319 = and(ldq_executed[18], _T_1318) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1322 = bits(_T_1321, 4, 0) connect s1_set_execute[_T_1322], UInt<1>(0h0) node _T_1323 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1324 = and(dmem_req_fire[0], _T_1323) reg REG_19 : UInt<1>, clock connect REG_19, _T_1324 node _T_1325 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1326 = and(REG_19, _T_1325) when _T_1326 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_19, ldq_uop[19] node _block_addr_matches_T_57 = shr(lcam_addr[0], 6) node _block_addr_matches_T_58 = shr(ldq_addr[19].bits, 6) node _block_addr_matches_T_59 = eq(_block_addr_matches_T_57, _block_addr_matches_T_58) wire block_addr_matches_19 : UInt<1>[1] connect block_addr_matches_19[0], _block_addr_matches_T_59 node _dword_addr_matches_T_76 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_77 = bits(ldq_addr[19].bits, 5, 3) node _dword_addr_matches_T_78 = eq(_dword_addr_matches_T_76, _dword_addr_matches_T_77) node _dword_addr_matches_T_79 = and(block_addr_matches_19[0], _dword_addr_matches_T_78) wire dword_addr_matches_19 : UInt<1>[1] connect dword_addr_matches_19[0], _dword_addr_matches_T_79 node _mask_match_T_38 = and(ldq_ld_byte_mask[19], lcam_mask[0]) node _mask_match_T_39 = eq(_mask_match_T_38, ldq_ld_byte_mask[19]) wire mask_match_19 : UInt<1>[1] connect mask_match_19[0], _mask_match_T_39 node _mask_overlap_T_38 = and(ldq_ld_byte_mask[19], lcam_mask[0]) node _mask_overlap_T_39 = orr(_mask_overlap_T_38) wire mask_overlap_19 : UInt<1>[1] connect mask_overlap_19[0], _mask_overlap_T_39 node _T_1327 = and(do_release_search[0], ldq_valid[19]) node _T_1328 = and(_T_1327, ldq_addr[19].valid) node _T_1329 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = and(_T_1330, block_addr_matches_19[0]) when _T_1331 : connect ldq_observed[19], UInt<1>(0h1) node _T_1332 = and(do_st_search[0], ldq_valid[19]) node _T_1333 = and(_T_1332, ldq_addr[19].valid) node _T_1334 = or(ldq_executed[19], ldq_succeeded[19]) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1337 = and(_T_1335, _T_1336) node _T_1338 = dshr(ldq_st_dep_mask[19], lcam_stq_idx[0]) node _T_1339 = bits(_T_1338, 0, 0) node _T_1340 = and(_T_1337, _T_1339) node _T_1341 = and(_T_1340, dword_addr_matches_19[0]) node _T_1342 = and(_T_1341, mask_overlap_19[0]) when _T_1342 : node _forwarded_is_older_T_76 = lt(ldq_forward_stq_idx[19], lcam_stq_idx[0]) node _forwarded_is_older_T_77 = lt(ldq_forward_stq_idx[19], l_uop_19.stq_idx) node _forwarded_is_older_T_78 = xor(_forwarded_is_older_T_76, _forwarded_is_older_T_77) node _forwarded_is_older_T_79 = lt(lcam_stq_idx[0], l_uop_19.stq_idx) node forwarded_is_older_19 = xor(_forwarded_is_older_T_78, _forwarded_is_older_T_79) node _T_1343 = eq(ldq_forward_std_val[19], UInt<1>(0h0)) node _T_1344 = neq(ldq_forward_stq_idx[19], lcam_stq_idx[0]) node _T_1345 = and(_T_1344, forwarded_is_older_19) node _T_1346 = or(_T_1343, _T_1345) when _T_1346 : connect ldq_order_fail[19], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1347 = and(do_ld_search[0], ldq_valid[19]) node _T_1348 = and(_T_1347, ldq_addr[19].valid) node _T_1349 = eq(ldq_addr_is_virtual[19], UInt<1>(0h0)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = and(_T_1350, dword_addr_matches_19[0]) node _T_1352 = and(_T_1351, mask_overlap_19[0]) when _T_1352 : node searcher_is_older_19 = bits(lcam_younger_load_mask[0], 19, 19) node _T_1353 = lt(lcam_ldq_idx[0], UInt<5>(0h13)) node _T_1354 = lt(lcam_ldq_idx[0], ldq_head) node _T_1355 = xor(_T_1353, _T_1354) node _T_1356 = lt(UInt<5>(0h13), ldq_head) node _T_1357 = xor(_T_1355, _T_1356) node _T_1358 = eq(_T_1357, searcher_is_older_19) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_70 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_70 when searcher_is_older_19 : node _T_1362 = or(ldq_executed[19], ldq_succeeded[19]) node _T_1363 = eq(s1_executing_loads[19], UInt<1>(0h0)) node _T_1364 = and(_T_1362, _T_1363) node _T_1365 = and(_T_1364, ldq_observed[19]) when _T_1365 : node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_71 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_71 else : node _T_1369 = neq(lcam_ldq_idx[0], UInt<5>(0h13)) when _T_1369 : node _T_1370 = or(ldq_succeeded[19], ldq_will_succeed[19]) node _T_1371 = and(ldq_executed[19], _T_1370) node _T_1372 = eq(_T_1371, UInt<1>(0h0)) when _T_1372 : node _T_1373 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1374 = bits(_T_1373, 4, 0) connect s1_set_execute[_T_1374], UInt<1>(0h0) node _T_1375 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1376 = and(dmem_req_fire[0], _T_1375) reg REG_20 : UInt<1>, clock connect REG_20, _T_1376 node _T_1377 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1378 = and(REG_20, _T_1377) when _T_1378 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_20, ldq_uop[20] node _block_addr_matches_T_60 = shr(lcam_addr[0], 6) node _block_addr_matches_T_61 = shr(ldq_addr[20].bits, 6) node _block_addr_matches_T_62 = eq(_block_addr_matches_T_60, _block_addr_matches_T_61) wire block_addr_matches_20 : UInt<1>[1] connect block_addr_matches_20[0], _block_addr_matches_T_62 node _dword_addr_matches_T_80 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_81 = bits(ldq_addr[20].bits, 5, 3) node _dword_addr_matches_T_82 = eq(_dword_addr_matches_T_80, _dword_addr_matches_T_81) node _dword_addr_matches_T_83 = and(block_addr_matches_20[0], _dword_addr_matches_T_82) wire dword_addr_matches_20 : UInt<1>[1] connect dword_addr_matches_20[0], _dword_addr_matches_T_83 node _mask_match_T_40 = and(ldq_ld_byte_mask[20], lcam_mask[0]) node _mask_match_T_41 = eq(_mask_match_T_40, ldq_ld_byte_mask[20]) wire mask_match_20 : UInt<1>[1] connect mask_match_20[0], _mask_match_T_41 node _mask_overlap_T_40 = and(ldq_ld_byte_mask[20], lcam_mask[0]) node _mask_overlap_T_41 = orr(_mask_overlap_T_40) wire mask_overlap_20 : UInt<1>[1] connect mask_overlap_20[0], _mask_overlap_T_41 node _T_1379 = and(do_release_search[0], ldq_valid[20]) node _T_1380 = and(_T_1379, ldq_addr[20].valid) node _T_1381 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1382 = and(_T_1380, _T_1381) node _T_1383 = and(_T_1382, block_addr_matches_20[0]) when _T_1383 : connect ldq_observed[20], UInt<1>(0h1) node _T_1384 = and(do_st_search[0], ldq_valid[20]) node _T_1385 = and(_T_1384, ldq_addr[20].valid) node _T_1386 = or(ldq_executed[20], ldq_succeeded[20]) node _T_1387 = and(_T_1385, _T_1386) node _T_1388 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1389 = and(_T_1387, _T_1388) node _T_1390 = dshr(ldq_st_dep_mask[20], lcam_stq_idx[0]) node _T_1391 = bits(_T_1390, 0, 0) node _T_1392 = and(_T_1389, _T_1391) node _T_1393 = and(_T_1392, dword_addr_matches_20[0]) node _T_1394 = and(_T_1393, mask_overlap_20[0]) when _T_1394 : node _forwarded_is_older_T_80 = lt(ldq_forward_stq_idx[20], lcam_stq_idx[0]) node _forwarded_is_older_T_81 = lt(ldq_forward_stq_idx[20], l_uop_20.stq_idx) node _forwarded_is_older_T_82 = xor(_forwarded_is_older_T_80, _forwarded_is_older_T_81) node _forwarded_is_older_T_83 = lt(lcam_stq_idx[0], l_uop_20.stq_idx) node forwarded_is_older_20 = xor(_forwarded_is_older_T_82, _forwarded_is_older_T_83) node _T_1395 = eq(ldq_forward_std_val[20], UInt<1>(0h0)) node _T_1396 = neq(ldq_forward_stq_idx[20], lcam_stq_idx[0]) node _T_1397 = and(_T_1396, forwarded_is_older_20) node _T_1398 = or(_T_1395, _T_1397) when _T_1398 : connect ldq_order_fail[20], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1399 = and(do_ld_search[0], ldq_valid[20]) node _T_1400 = and(_T_1399, ldq_addr[20].valid) node _T_1401 = eq(ldq_addr_is_virtual[20], UInt<1>(0h0)) node _T_1402 = and(_T_1400, _T_1401) node _T_1403 = and(_T_1402, dword_addr_matches_20[0]) node _T_1404 = and(_T_1403, mask_overlap_20[0]) when _T_1404 : node searcher_is_older_20 = bits(lcam_younger_load_mask[0], 20, 20) node _T_1405 = lt(lcam_ldq_idx[0], UInt<5>(0h14)) node _T_1406 = lt(lcam_ldq_idx[0], ldq_head) node _T_1407 = xor(_T_1405, _T_1406) node _T_1408 = lt(UInt<5>(0h14), ldq_head) node _T_1409 = xor(_T_1407, _T_1408) node _T_1410 = eq(_T_1409, searcher_is_older_20) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_72 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_72 when searcher_is_older_20 : node _T_1414 = or(ldq_executed[20], ldq_succeeded[20]) node _T_1415 = eq(s1_executing_loads[20], UInt<1>(0h0)) node _T_1416 = and(_T_1414, _T_1415) node _T_1417 = and(_T_1416, ldq_observed[20]) when _T_1417 : node _T_1418 = asUInt(reset) node _T_1419 = eq(_T_1418, UInt<1>(0h0)) when _T_1419 : node _T_1420 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1420 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_73 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_73 else : node _T_1421 = neq(lcam_ldq_idx[0], UInt<5>(0h14)) when _T_1421 : node _T_1422 = or(ldq_succeeded[20], ldq_will_succeed[20]) node _T_1423 = and(ldq_executed[20], _T_1422) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1426 = bits(_T_1425, 4, 0) connect s1_set_execute[_T_1426], UInt<1>(0h0) node _T_1427 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1428 = and(dmem_req_fire[0], _T_1427) reg REG_21 : UInt<1>, clock connect REG_21, _T_1428 node _T_1429 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1430 = and(REG_21, _T_1429) when _T_1430 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_21, ldq_uop[21] node _block_addr_matches_T_63 = shr(lcam_addr[0], 6) node _block_addr_matches_T_64 = shr(ldq_addr[21].bits, 6) node _block_addr_matches_T_65 = eq(_block_addr_matches_T_63, _block_addr_matches_T_64) wire block_addr_matches_21 : UInt<1>[1] connect block_addr_matches_21[0], _block_addr_matches_T_65 node _dword_addr_matches_T_84 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_85 = bits(ldq_addr[21].bits, 5, 3) node _dword_addr_matches_T_86 = eq(_dword_addr_matches_T_84, _dword_addr_matches_T_85) node _dword_addr_matches_T_87 = and(block_addr_matches_21[0], _dword_addr_matches_T_86) wire dword_addr_matches_21 : UInt<1>[1] connect dword_addr_matches_21[0], _dword_addr_matches_T_87 node _mask_match_T_42 = and(ldq_ld_byte_mask[21], lcam_mask[0]) node _mask_match_T_43 = eq(_mask_match_T_42, ldq_ld_byte_mask[21]) wire mask_match_21 : UInt<1>[1] connect mask_match_21[0], _mask_match_T_43 node _mask_overlap_T_42 = and(ldq_ld_byte_mask[21], lcam_mask[0]) node _mask_overlap_T_43 = orr(_mask_overlap_T_42) wire mask_overlap_21 : UInt<1>[1] connect mask_overlap_21[0], _mask_overlap_T_43 node _T_1431 = and(do_release_search[0], ldq_valid[21]) node _T_1432 = and(_T_1431, ldq_addr[21].valid) node _T_1433 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1434 = and(_T_1432, _T_1433) node _T_1435 = and(_T_1434, block_addr_matches_21[0]) when _T_1435 : connect ldq_observed[21], UInt<1>(0h1) node _T_1436 = and(do_st_search[0], ldq_valid[21]) node _T_1437 = and(_T_1436, ldq_addr[21].valid) node _T_1438 = or(ldq_executed[21], ldq_succeeded[21]) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1441 = and(_T_1439, _T_1440) node _T_1442 = dshr(ldq_st_dep_mask[21], lcam_stq_idx[0]) node _T_1443 = bits(_T_1442, 0, 0) node _T_1444 = and(_T_1441, _T_1443) node _T_1445 = and(_T_1444, dword_addr_matches_21[0]) node _T_1446 = and(_T_1445, mask_overlap_21[0]) when _T_1446 : node _forwarded_is_older_T_84 = lt(ldq_forward_stq_idx[21], lcam_stq_idx[0]) node _forwarded_is_older_T_85 = lt(ldq_forward_stq_idx[21], l_uop_21.stq_idx) node _forwarded_is_older_T_86 = xor(_forwarded_is_older_T_84, _forwarded_is_older_T_85) node _forwarded_is_older_T_87 = lt(lcam_stq_idx[0], l_uop_21.stq_idx) node forwarded_is_older_21 = xor(_forwarded_is_older_T_86, _forwarded_is_older_T_87) node _T_1447 = eq(ldq_forward_std_val[21], UInt<1>(0h0)) node _T_1448 = neq(ldq_forward_stq_idx[21], lcam_stq_idx[0]) node _T_1449 = and(_T_1448, forwarded_is_older_21) node _T_1450 = or(_T_1447, _T_1449) when _T_1450 : connect ldq_order_fail[21], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1451 = and(do_ld_search[0], ldq_valid[21]) node _T_1452 = and(_T_1451, ldq_addr[21].valid) node _T_1453 = eq(ldq_addr_is_virtual[21], UInt<1>(0h0)) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = and(_T_1454, dword_addr_matches_21[0]) node _T_1456 = and(_T_1455, mask_overlap_21[0]) when _T_1456 : node searcher_is_older_21 = bits(lcam_younger_load_mask[0], 21, 21) node _T_1457 = lt(lcam_ldq_idx[0], UInt<5>(0h15)) node _T_1458 = lt(lcam_ldq_idx[0], ldq_head) node _T_1459 = xor(_T_1457, _T_1458) node _T_1460 = lt(UInt<5>(0h15), ldq_head) node _T_1461 = xor(_T_1459, _T_1460) node _T_1462 = eq(_T_1461, searcher_is_older_21) node _T_1463 = asUInt(reset) node _T_1464 = eq(_T_1463, UInt<1>(0h0)) when _T_1464 : node _T_1465 = eq(_T_1462, UInt<1>(0h0)) when _T_1465 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_74 assert(clock, _T_1462, UInt<1>(0h1), "") : assert_74 when searcher_is_older_21 : node _T_1466 = or(ldq_executed[21], ldq_succeeded[21]) node _T_1467 = eq(s1_executing_loads[21], UInt<1>(0h0)) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = and(_T_1468, ldq_observed[21]) when _T_1469 : node _T_1470 = asUInt(reset) node _T_1471 = eq(_T_1470, UInt<1>(0h0)) when _T_1471 : node _T_1472 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1472 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_75 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_75 else : node _T_1473 = neq(lcam_ldq_idx[0], UInt<5>(0h15)) when _T_1473 : node _T_1474 = or(ldq_succeeded[21], ldq_will_succeed[21]) node _T_1475 = and(ldq_executed[21], _T_1474) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1478 = bits(_T_1477, 4, 0) connect s1_set_execute[_T_1478], UInt<1>(0h0) node _T_1479 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1480 = and(dmem_req_fire[0], _T_1479) reg REG_22 : UInt<1>, clock connect REG_22, _T_1480 node _T_1481 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1482 = and(REG_22, _T_1481) when _T_1482 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_22, ldq_uop[22] node _block_addr_matches_T_66 = shr(lcam_addr[0], 6) node _block_addr_matches_T_67 = shr(ldq_addr[22].bits, 6) node _block_addr_matches_T_68 = eq(_block_addr_matches_T_66, _block_addr_matches_T_67) wire block_addr_matches_22 : UInt<1>[1] connect block_addr_matches_22[0], _block_addr_matches_T_68 node _dword_addr_matches_T_88 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_89 = bits(ldq_addr[22].bits, 5, 3) node _dword_addr_matches_T_90 = eq(_dword_addr_matches_T_88, _dword_addr_matches_T_89) node _dword_addr_matches_T_91 = and(block_addr_matches_22[0], _dword_addr_matches_T_90) wire dword_addr_matches_22 : UInt<1>[1] connect dword_addr_matches_22[0], _dword_addr_matches_T_91 node _mask_match_T_44 = and(ldq_ld_byte_mask[22], lcam_mask[0]) node _mask_match_T_45 = eq(_mask_match_T_44, ldq_ld_byte_mask[22]) wire mask_match_22 : UInt<1>[1] connect mask_match_22[0], _mask_match_T_45 node _mask_overlap_T_44 = and(ldq_ld_byte_mask[22], lcam_mask[0]) node _mask_overlap_T_45 = orr(_mask_overlap_T_44) wire mask_overlap_22 : UInt<1>[1] connect mask_overlap_22[0], _mask_overlap_T_45 node _T_1483 = and(do_release_search[0], ldq_valid[22]) node _T_1484 = and(_T_1483, ldq_addr[22].valid) node _T_1485 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1486 = and(_T_1484, _T_1485) node _T_1487 = and(_T_1486, block_addr_matches_22[0]) when _T_1487 : connect ldq_observed[22], UInt<1>(0h1) node _T_1488 = and(do_st_search[0], ldq_valid[22]) node _T_1489 = and(_T_1488, ldq_addr[22].valid) node _T_1490 = or(ldq_executed[22], ldq_succeeded[22]) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = dshr(ldq_st_dep_mask[22], lcam_stq_idx[0]) node _T_1495 = bits(_T_1494, 0, 0) node _T_1496 = and(_T_1493, _T_1495) node _T_1497 = and(_T_1496, dword_addr_matches_22[0]) node _T_1498 = and(_T_1497, mask_overlap_22[0]) when _T_1498 : node _forwarded_is_older_T_88 = lt(ldq_forward_stq_idx[22], lcam_stq_idx[0]) node _forwarded_is_older_T_89 = lt(ldq_forward_stq_idx[22], l_uop_22.stq_idx) node _forwarded_is_older_T_90 = xor(_forwarded_is_older_T_88, _forwarded_is_older_T_89) node _forwarded_is_older_T_91 = lt(lcam_stq_idx[0], l_uop_22.stq_idx) node forwarded_is_older_22 = xor(_forwarded_is_older_T_90, _forwarded_is_older_T_91) node _T_1499 = eq(ldq_forward_std_val[22], UInt<1>(0h0)) node _T_1500 = neq(ldq_forward_stq_idx[22], lcam_stq_idx[0]) node _T_1501 = and(_T_1500, forwarded_is_older_22) node _T_1502 = or(_T_1499, _T_1501) when _T_1502 : connect ldq_order_fail[22], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1503 = and(do_ld_search[0], ldq_valid[22]) node _T_1504 = and(_T_1503, ldq_addr[22].valid) node _T_1505 = eq(ldq_addr_is_virtual[22], UInt<1>(0h0)) node _T_1506 = and(_T_1504, _T_1505) node _T_1507 = and(_T_1506, dword_addr_matches_22[0]) node _T_1508 = and(_T_1507, mask_overlap_22[0]) when _T_1508 : node searcher_is_older_22 = bits(lcam_younger_load_mask[0], 22, 22) node _T_1509 = lt(lcam_ldq_idx[0], UInt<5>(0h16)) node _T_1510 = lt(lcam_ldq_idx[0], ldq_head) node _T_1511 = xor(_T_1509, _T_1510) node _T_1512 = lt(UInt<5>(0h16), ldq_head) node _T_1513 = xor(_T_1511, _T_1512) node _T_1514 = eq(_T_1513, searcher_is_older_22) node _T_1515 = asUInt(reset) node _T_1516 = eq(_T_1515, UInt<1>(0h0)) when _T_1516 : node _T_1517 = eq(_T_1514, UInt<1>(0h0)) when _T_1517 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_76 assert(clock, _T_1514, UInt<1>(0h1), "") : assert_76 when searcher_is_older_22 : node _T_1518 = or(ldq_executed[22], ldq_succeeded[22]) node _T_1519 = eq(s1_executing_loads[22], UInt<1>(0h0)) node _T_1520 = and(_T_1518, _T_1519) node _T_1521 = and(_T_1520, ldq_observed[22]) when _T_1521 : node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_77 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_77 else : node _T_1525 = neq(lcam_ldq_idx[0], UInt<5>(0h16)) when _T_1525 : node _T_1526 = or(ldq_succeeded[22], ldq_will_succeed[22]) node _T_1527 = and(ldq_executed[22], _T_1526) node _T_1528 = eq(_T_1527, UInt<1>(0h0)) when _T_1528 : node _T_1529 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1530 = bits(_T_1529, 4, 0) connect s1_set_execute[_T_1530], UInt<1>(0h0) node _T_1531 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1532 = and(dmem_req_fire[0], _T_1531) reg REG_23 : UInt<1>, clock connect REG_23, _T_1532 node _T_1533 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1534 = and(REG_23, _T_1533) when _T_1534 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) wire l_uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_23, ldq_uop[23] node _block_addr_matches_T_69 = shr(lcam_addr[0], 6) node _block_addr_matches_T_70 = shr(ldq_addr[23].bits, 6) node _block_addr_matches_T_71 = eq(_block_addr_matches_T_69, _block_addr_matches_T_70) wire block_addr_matches_23 : UInt<1>[1] connect block_addr_matches_23[0], _block_addr_matches_T_71 node _dword_addr_matches_T_92 = bits(lcam_addr[0], 5, 3) node _dword_addr_matches_T_93 = bits(ldq_addr[23].bits, 5, 3) node _dword_addr_matches_T_94 = eq(_dword_addr_matches_T_92, _dword_addr_matches_T_93) node _dword_addr_matches_T_95 = and(block_addr_matches_23[0], _dword_addr_matches_T_94) wire dword_addr_matches_23 : UInt<1>[1] connect dword_addr_matches_23[0], _dword_addr_matches_T_95 node _mask_match_T_46 = and(ldq_ld_byte_mask[23], lcam_mask[0]) node _mask_match_T_47 = eq(_mask_match_T_46, ldq_ld_byte_mask[23]) wire mask_match_23 : UInt<1>[1] connect mask_match_23[0], _mask_match_T_47 node _mask_overlap_T_46 = and(ldq_ld_byte_mask[23], lcam_mask[0]) node _mask_overlap_T_47 = orr(_mask_overlap_T_46) wire mask_overlap_23 : UInt<1>[1] connect mask_overlap_23[0], _mask_overlap_T_47 node _T_1535 = and(do_release_search[0], ldq_valid[23]) node _T_1536 = and(_T_1535, ldq_addr[23].valid) node _T_1537 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1538 = and(_T_1536, _T_1537) node _T_1539 = and(_T_1538, block_addr_matches_23[0]) when _T_1539 : connect ldq_observed[23], UInt<1>(0h1) node _T_1540 = and(do_st_search[0], ldq_valid[23]) node _T_1541 = and(_T_1540, ldq_addr[23].valid) node _T_1542 = or(ldq_executed[23], ldq_succeeded[23]) node _T_1543 = and(_T_1541, _T_1542) node _T_1544 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1545 = and(_T_1543, _T_1544) node _T_1546 = dshr(ldq_st_dep_mask[23], lcam_stq_idx[0]) node _T_1547 = bits(_T_1546, 0, 0) node _T_1548 = and(_T_1545, _T_1547) node _T_1549 = and(_T_1548, dword_addr_matches_23[0]) node _T_1550 = and(_T_1549, mask_overlap_23[0]) when _T_1550 : node _forwarded_is_older_T_92 = lt(ldq_forward_stq_idx[23], lcam_stq_idx[0]) node _forwarded_is_older_T_93 = lt(ldq_forward_stq_idx[23], l_uop_23.stq_idx) node _forwarded_is_older_T_94 = xor(_forwarded_is_older_T_92, _forwarded_is_older_T_93) node _forwarded_is_older_T_95 = lt(lcam_stq_idx[0], l_uop_23.stq_idx) node forwarded_is_older_23 = xor(_forwarded_is_older_T_94, _forwarded_is_older_T_95) node _T_1551 = eq(ldq_forward_std_val[23], UInt<1>(0h0)) node _T_1552 = neq(ldq_forward_stq_idx[23], lcam_stq_idx[0]) node _T_1553 = and(_T_1552, forwarded_is_older_23) node _T_1554 = or(_T_1551, _T_1553) when _T_1554 : connect ldq_order_fail[23], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _T_1555 = and(do_ld_search[0], ldq_valid[23]) node _T_1556 = and(_T_1555, ldq_addr[23].valid) node _T_1557 = eq(ldq_addr_is_virtual[23], UInt<1>(0h0)) node _T_1558 = and(_T_1556, _T_1557) node _T_1559 = and(_T_1558, dword_addr_matches_23[0]) node _T_1560 = and(_T_1559, mask_overlap_23[0]) when _T_1560 : node searcher_is_older_23 = bits(lcam_younger_load_mask[0], 23, 23) node _T_1561 = lt(lcam_ldq_idx[0], UInt<5>(0h17)) node _T_1562 = lt(lcam_ldq_idx[0], ldq_head) node _T_1563 = xor(_T_1561, _T_1562) node _T_1564 = lt(UInt<5>(0h17), ldq_head) node _T_1565 = xor(_T_1563, _T_1564) node _T_1566 = eq(_T_1565, searcher_is_older_23) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1238 assert(IsOlder(lcam_ldq_idx(w), i.U, ldq_head) === searcher_is_older)\n") : printf_78 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_78 when searcher_is_older_23 : node _T_1570 = or(ldq_executed[23], ldq_succeeded[23]) node _T_1571 = eq(s1_executing_loads[23], UInt<1>(0h0)) node _T_1572 = and(_T_1570, _T_1571) node _T_1573 = and(_T_1572, ldq_observed[23]) when _T_1573 : node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1247 assert(false.B)\n") : printf_79 assert(clock, UInt<1>(0h0), UInt<1>(0h1), "") : assert_79 else : node _T_1577 = neq(lcam_ldq_idx[0], UInt<5>(0h17)) when _T_1577 : node _T_1578 = or(ldq_succeeded[23], ldq_will_succeed[23]) node _T_1579 = and(ldq_executed[23], _T_1578) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1582 = bits(_T_1581, 4, 0) connect s1_set_execute[_T_1582], UInt<1>(0h0) node _T_1583 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1584 = and(dmem_req_fire[0], _T_1583) reg REG_24 : UInt<1>, clock connect REG_24, _T_1584 node _T_1585 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1586 = and(REG_24, _T_1585) when _T_1586 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) node _nack_dword_addr_matches_T = shr(lcam_addr[0], 3) node _nack_dword_addr_matches_T_1 = shr(io.dmem.nack[0].bits.addr, 3) node nack_dword_addr_matches = eq(_nack_dword_addr_matches_T, _nack_dword_addr_matches_T_1) wire nack_mask : UInt<8> node _nack_mask_mask_T = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<1>(0h0)) node _nack_mask_mask_T_1 = bits(io.dmem.nack[0].bits.addr, 2, 0) node _nack_mask_mask_T_2 = dshl(UInt<8>(0h1), _nack_mask_mask_T_1) node _nack_mask_mask_T_3 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<1>(0h1)) node _nack_mask_mask_T_4 = bits(io.dmem.nack[0].bits.addr, 2, 1) node _nack_mask_mask_T_5 = dshl(_nack_mask_mask_T_4, UInt<1>(0h1)) node _nack_mask_mask_T_6 = dshl(UInt<8>(0h3), _nack_mask_mask_T_5) node _nack_mask_mask_T_7 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<2>(0h2)) node _nack_mask_mask_T_8 = bits(io.dmem.nack[0].bits.addr, 2, 2) node _nack_mask_mask_T_9 = mux(_nack_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _nack_mask_mask_T_10 = eq(io.dmem.nack[0].bits.uop.mem_size, UInt<2>(0h3)) node _nack_mask_mask_T_11 = mux(_nack_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _nack_mask_mask_T_12 = mux(_nack_mask_mask_T_7, _nack_mask_mask_T_9, _nack_mask_mask_T_11) node _nack_mask_mask_T_13 = mux(_nack_mask_mask_T_3, _nack_mask_mask_T_6, _nack_mask_mask_T_12) node _nack_mask_mask_T_14 = mux(_nack_mask_mask_T, _nack_mask_mask_T_2, _nack_mask_mask_T_13) connect nack_mask, _nack_mask_mask_T_14 node _nack_mask_overlap_T = and(nack_mask, lcam_mask[0]) node nack_mask_overlap = neq(_nack_mask_overlap_T, UInt<1>(0h0)) node _T_1587 = and(do_ld_search[0], io.dmem.nack[0].valid) node _T_1588 = and(_T_1587, io.dmem.nack[0].bits.uop.uses_ldq) node _T_1589 = and(_T_1588, nack_dword_addr_matches) node _T_1590 = and(_T_1589, nack_mask_overlap) node _T_1591 = lt(io.dmem.nack[0].bits.uop.ldq_idx, lcam_ldq_idx[0]) node _T_1592 = lt(io.dmem.nack[0].bits.uop.ldq_idx, ldq_head) node _T_1593 = xor(_T_1591, _T_1592) node _T_1594 = lt(lcam_ldq_idx[0], ldq_head) node _T_1595 = xor(_T_1593, _T_1594) node _T_1596 = and(_T_1590, _T_1595) when _T_1596 : node _T_1597 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1598 = bits(_T_1597, 4, 0) connect s1_set_execute[_T_1598], UInt<1>(0h0) node _T_1599 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1600 = and(dmem_req_fire[0], _T_1599) reg REG_25 : UInt<1>, clock connect REG_25, _T_1600 node _T_1601 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1602 = and(REG_25, _T_1601) when _T_1602 : connect io.dmem.s1_kill[0], UInt<1>(0h1) connect kill_forward[0], UInt<1>(0h1) node _forward_dword_addr_matches_T = shr(lcam_addr[0], 3) node _forward_dword_addr_matches_T_1 = shr(wb_ldst_forward_ld_addr[0], 3) node forward_dword_addr_matches = eq(_forward_dword_addr_matches_T, _forward_dword_addr_matches_T_1) wire forward_mask : UInt<8> node _forward_mask_mask_T = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<1>(0h0)) node _forward_mask_mask_T_1 = bits(wb_ldst_forward_ld_addr[0], 2, 0) node _forward_mask_mask_T_2 = dshl(UInt<8>(0h1), _forward_mask_mask_T_1) node _forward_mask_mask_T_3 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<1>(0h1)) node _forward_mask_mask_T_4 = bits(wb_ldst_forward_ld_addr[0], 2, 1) node _forward_mask_mask_T_5 = dshl(_forward_mask_mask_T_4, UInt<1>(0h1)) node _forward_mask_mask_T_6 = dshl(UInt<8>(0h3), _forward_mask_mask_T_5) node _forward_mask_mask_T_7 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<2>(0h2)) node _forward_mask_mask_T_8 = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _forward_mask_mask_T_9 = mux(_forward_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _forward_mask_mask_T_10 = eq(wb_ldst_forward_e[0].uop.mem_size, UInt<2>(0h3)) node _forward_mask_mask_T_11 = mux(_forward_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _forward_mask_mask_T_12 = mux(_forward_mask_mask_T_7, _forward_mask_mask_T_9, _forward_mask_mask_T_11) node _forward_mask_mask_T_13 = mux(_forward_mask_mask_T_3, _forward_mask_mask_T_6, _forward_mask_mask_T_12) node _forward_mask_mask_T_14 = mux(_forward_mask_mask_T, _forward_mask_mask_T_2, _forward_mask_mask_T_13) connect forward_mask, _forward_mask_mask_T_14 node _forward_mask_overlap_T = and(forward_mask, lcam_mask[0]) node forward_mask_overlap = neq(_forward_mask_overlap_T, UInt<1>(0h0)) node _T_1603 = and(do_ld_search[0], wb_ldst_forward_valid[0]) node _T_1604 = and(_T_1603, forward_dword_addr_matches) node _T_1605 = and(_T_1604, forward_mask_overlap) node _T_1606 = and(_T_1605, wb_ldst_forward_e[0].observed) node _T_1607 = lt(lcam_ldq_idx[0], wb_ldst_forward_ldq_idx[0]) node _T_1608 = lt(lcam_ldq_idx[0], ldq_head) node _T_1609 = xor(_T_1607, _T_1608) node _T_1610 = lt(wb_ldst_forward_ldq_idx[0], ldq_head) node _T_1611 = xor(_T_1609, _T_1610) node _T_1612 = and(_T_1606, _T_1611) when _T_1612 : node _T_1613 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1614 = bits(_T_1613, 4, 0) connect ldq_order_fail[_T_1614], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) node _forwarded_is_older_T_96 = lt(wb_ldst_forward_stq_idx[0], lcam_stq_idx[0]) node _forwarded_is_older_T_97 = lt(wb_ldst_forward_stq_idx[0], wb_ldst_forward_e[0].uop.stq_idx) node _forwarded_is_older_T_98 = xor(_forwarded_is_older_T_96, _forwarded_is_older_T_97) node _forwarded_is_older_T_99 = lt(lcam_stq_idx[0], wb_ldst_forward_e[0].uop.stq_idx) node forwarded_is_older_24 = xor(_forwarded_is_older_T_98, _forwarded_is_older_T_99) node _T_1615 = and(do_st_search[0], wb_ldst_forward_valid[0]) node _T_1616 = and(_T_1615, forward_dword_addr_matches) node _T_1617 = and(_T_1616, forward_mask_overlap) node _T_1618 = dshr(wb_ldst_forward_e[0].st_dep_mask, lcam_stq_idx[0]) node _T_1619 = bits(_T_1618, 0, 0) node _T_1620 = and(_T_1617, _T_1619) node _T_1621 = and(_T_1620, forwarded_is_older_24) when _T_1621 : node _T_1622 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1623 = bits(_T_1622, 4, 0) connect ldq_order_fail[_T_1623], UInt<1>(0h1) connect failed_load, UInt<1>(0h1) wire addr_matches : UInt<1>[24][1] wire forward_matches : UInt<1>[24][1] wire prs2_matches : UInt<1>[24][1] wire s_uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_3, stq_uop[0] wire write_mask : UInt<8> node _write_mask_mask_T = eq(s_uop_3.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_1 = bits(stq_addr[0].bits, 2, 0) node _write_mask_mask_T_2 = dshl(UInt<8>(0h1), _write_mask_mask_T_1) node _write_mask_mask_T_3 = eq(s_uop_3.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_4 = bits(stq_addr[0].bits, 2, 1) node _write_mask_mask_T_5 = dshl(_write_mask_mask_T_4, UInt<1>(0h1)) node _write_mask_mask_T_6 = dshl(UInt<8>(0h3), _write_mask_mask_T_5) node _write_mask_mask_T_7 = eq(s_uop_3.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_8 = bits(stq_addr[0].bits, 2, 2) node _write_mask_mask_T_9 = mux(_write_mask_mask_T_8, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_10 = eq(s_uop_3.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_11 = mux(_write_mask_mask_T_10, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_12 = mux(_write_mask_mask_T_7, _write_mask_mask_T_9, _write_mask_mask_T_11) node _write_mask_mask_T_13 = mux(_write_mask_mask_T_3, _write_mask_mask_T_6, _write_mask_mask_T_12) node _write_mask_mask_T_14 = mux(_write_mask_mask_T, _write_mask_mask_T_2, _write_mask_mask_T_13) connect write_mask, _write_mask_mask_T_14 node _dword_addr_matches_T_96 = eq(s_uop_3.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_97 = and(stq_addr[0].valid, _dword_addr_matches_T_96) node _dword_addr_matches_T_98 = eq(stq_addr_is_virtual[0], UInt<1>(0h0)) node _dword_addr_matches_T_99 = and(_dword_addr_matches_T_97, _dword_addr_matches_T_98) node _dword_addr_matches_T_100 = bits(stq_addr[0].bits, 31, 3) node _dword_addr_matches_T_101 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_102 = eq(_dword_addr_matches_T_100, _dword_addr_matches_T_101) node dword_addr_matches_24 = and(_dword_addr_matches_T_99, _dword_addr_matches_T_102) node mask_union = and(lcam_mask[0], write_mask) node _addr_matches_0_0_T = neq(mask_union, UInt<1>(0h0)) node _addr_matches_0_0_T_1 = and(_addr_matches_0_0_T, dword_addr_matches_24) connect addr_matches[0][0], _addr_matches_0_0_T_1 node _forward_matches_0_0_T = and(addr_matches[0][0], stq_data[0].valid) node _forward_matches_0_0_T_1 = eq(mask_union, lcam_mask[0]) node _forward_matches_0_0_T_2 = and(_forward_matches_0_0_T, _forward_matches_0_0_T_1) connect forward_matches[0][0], _forward_matches_0_0_T_2 node _prs2_matches_0_0_T = eq(s_uop_3.prs2, lcam_uop[0].pdst) node _prs2_matches_0_0_T_1 = eq(s_uop_3.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_0_T_2 = and(_prs2_matches_0_0_T, _prs2_matches_0_0_T_1) node _prs2_matches_0_0_T_3 = and(_prs2_matches_0_0_T_2, UInt<1>(0h1)) connect prs2_matches[0][0], _prs2_matches_0_0_T_3 wire s_uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_4, stq_uop[1] wire write_mask_1 : UInt<8> node _write_mask_mask_T_15 = eq(s_uop_4.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_16 = bits(stq_addr[1].bits, 2, 0) node _write_mask_mask_T_17 = dshl(UInt<8>(0h1), _write_mask_mask_T_16) node _write_mask_mask_T_18 = eq(s_uop_4.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_19 = bits(stq_addr[1].bits, 2, 1) node _write_mask_mask_T_20 = dshl(_write_mask_mask_T_19, UInt<1>(0h1)) node _write_mask_mask_T_21 = dshl(UInt<8>(0h3), _write_mask_mask_T_20) node _write_mask_mask_T_22 = eq(s_uop_4.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_23 = bits(stq_addr[1].bits, 2, 2) node _write_mask_mask_T_24 = mux(_write_mask_mask_T_23, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_25 = eq(s_uop_4.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_26 = mux(_write_mask_mask_T_25, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_27 = mux(_write_mask_mask_T_22, _write_mask_mask_T_24, _write_mask_mask_T_26) node _write_mask_mask_T_28 = mux(_write_mask_mask_T_18, _write_mask_mask_T_21, _write_mask_mask_T_27) node _write_mask_mask_T_29 = mux(_write_mask_mask_T_15, _write_mask_mask_T_17, _write_mask_mask_T_28) connect write_mask_1, _write_mask_mask_T_29 node _dword_addr_matches_T_103 = eq(s_uop_4.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_104 = and(stq_addr[1].valid, _dword_addr_matches_T_103) node _dword_addr_matches_T_105 = eq(stq_addr_is_virtual[1], UInt<1>(0h0)) node _dword_addr_matches_T_106 = and(_dword_addr_matches_T_104, _dword_addr_matches_T_105) node _dword_addr_matches_T_107 = bits(stq_addr[1].bits, 31, 3) node _dword_addr_matches_T_108 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_109 = eq(_dword_addr_matches_T_107, _dword_addr_matches_T_108) node dword_addr_matches_25 = and(_dword_addr_matches_T_106, _dword_addr_matches_T_109) node mask_union_1 = and(lcam_mask[0], write_mask_1) node _addr_matches_0_1_T = neq(mask_union_1, UInt<1>(0h0)) node _addr_matches_0_1_T_1 = and(_addr_matches_0_1_T, dword_addr_matches_25) connect addr_matches[0][1], _addr_matches_0_1_T_1 node _forward_matches_0_1_T = and(addr_matches[0][1], stq_data[1].valid) node _forward_matches_0_1_T_1 = eq(mask_union_1, lcam_mask[0]) node _forward_matches_0_1_T_2 = and(_forward_matches_0_1_T, _forward_matches_0_1_T_1) connect forward_matches[0][1], _forward_matches_0_1_T_2 node _prs2_matches_0_1_T = eq(s_uop_4.prs2, lcam_uop[0].pdst) node _prs2_matches_0_1_T_1 = eq(s_uop_4.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_1_T_2 = and(_prs2_matches_0_1_T, _prs2_matches_0_1_T_1) node _prs2_matches_0_1_T_3 = and(_prs2_matches_0_1_T_2, UInt<1>(0h1)) connect prs2_matches[0][1], _prs2_matches_0_1_T_3 wire s_uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_5, stq_uop[2] wire write_mask_2 : UInt<8> node _write_mask_mask_T_30 = eq(s_uop_5.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_31 = bits(stq_addr[2].bits, 2, 0) node _write_mask_mask_T_32 = dshl(UInt<8>(0h1), _write_mask_mask_T_31) node _write_mask_mask_T_33 = eq(s_uop_5.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_34 = bits(stq_addr[2].bits, 2, 1) node _write_mask_mask_T_35 = dshl(_write_mask_mask_T_34, UInt<1>(0h1)) node _write_mask_mask_T_36 = dshl(UInt<8>(0h3), _write_mask_mask_T_35) node _write_mask_mask_T_37 = eq(s_uop_5.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_38 = bits(stq_addr[2].bits, 2, 2) node _write_mask_mask_T_39 = mux(_write_mask_mask_T_38, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_40 = eq(s_uop_5.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_41 = mux(_write_mask_mask_T_40, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_42 = mux(_write_mask_mask_T_37, _write_mask_mask_T_39, _write_mask_mask_T_41) node _write_mask_mask_T_43 = mux(_write_mask_mask_T_33, _write_mask_mask_T_36, _write_mask_mask_T_42) node _write_mask_mask_T_44 = mux(_write_mask_mask_T_30, _write_mask_mask_T_32, _write_mask_mask_T_43) connect write_mask_2, _write_mask_mask_T_44 node _dword_addr_matches_T_110 = eq(s_uop_5.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_111 = and(stq_addr[2].valid, _dword_addr_matches_T_110) node _dword_addr_matches_T_112 = eq(stq_addr_is_virtual[2], UInt<1>(0h0)) node _dword_addr_matches_T_113 = and(_dword_addr_matches_T_111, _dword_addr_matches_T_112) node _dword_addr_matches_T_114 = bits(stq_addr[2].bits, 31, 3) node _dword_addr_matches_T_115 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_116 = eq(_dword_addr_matches_T_114, _dword_addr_matches_T_115) node dword_addr_matches_26 = and(_dword_addr_matches_T_113, _dword_addr_matches_T_116) node mask_union_2 = and(lcam_mask[0], write_mask_2) node _addr_matches_0_2_T = neq(mask_union_2, UInt<1>(0h0)) node _addr_matches_0_2_T_1 = and(_addr_matches_0_2_T, dword_addr_matches_26) connect addr_matches[0][2], _addr_matches_0_2_T_1 node _forward_matches_0_2_T = and(addr_matches[0][2], stq_data[2].valid) node _forward_matches_0_2_T_1 = eq(mask_union_2, lcam_mask[0]) node _forward_matches_0_2_T_2 = and(_forward_matches_0_2_T, _forward_matches_0_2_T_1) connect forward_matches[0][2], _forward_matches_0_2_T_2 node _prs2_matches_0_2_T = eq(s_uop_5.prs2, lcam_uop[0].pdst) node _prs2_matches_0_2_T_1 = eq(s_uop_5.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_2_T_2 = and(_prs2_matches_0_2_T, _prs2_matches_0_2_T_1) node _prs2_matches_0_2_T_3 = and(_prs2_matches_0_2_T_2, UInt<1>(0h1)) connect prs2_matches[0][2], _prs2_matches_0_2_T_3 wire s_uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_6, stq_uop[3] wire write_mask_3 : UInt<8> node _write_mask_mask_T_45 = eq(s_uop_6.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_46 = bits(stq_addr[3].bits, 2, 0) node _write_mask_mask_T_47 = dshl(UInt<8>(0h1), _write_mask_mask_T_46) node _write_mask_mask_T_48 = eq(s_uop_6.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_49 = bits(stq_addr[3].bits, 2, 1) node _write_mask_mask_T_50 = dshl(_write_mask_mask_T_49, UInt<1>(0h1)) node _write_mask_mask_T_51 = dshl(UInt<8>(0h3), _write_mask_mask_T_50) node _write_mask_mask_T_52 = eq(s_uop_6.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_53 = bits(stq_addr[3].bits, 2, 2) node _write_mask_mask_T_54 = mux(_write_mask_mask_T_53, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_55 = eq(s_uop_6.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_56 = mux(_write_mask_mask_T_55, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_57 = mux(_write_mask_mask_T_52, _write_mask_mask_T_54, _write_mask_mask_T_56) node _write_mask_mask_T_58 = mux(_write_mask_mask_T_48, _write_mask_mask_T_51, _write_mask_mask_T_57) node _write_mask_mask_T_59 = mux(_write_mask_mask_T_45, _write_mask_mask_T_47, _write_mask_mask_T_58) connect write_mask_3, _write_mask_mask_T_59 node _dword_addr_matches_T_117 = eq(s_uop_6.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_118 = and(stq_addr[3].valid, _dword_addr_matches_T_117) node _dword_addr_matches_T_119 = eq(stq_addr_is_virtual[3], UInt<1>(0h0)) node _dword_addr_matches_T_120 = and(_dword_addr_matches_T_118, _dword_addr_matches_T_119) node _dword_addr_matches_T_121 = bits(stq_addr[3].bits, 31, 3) node _dword_addr_matches_T_122 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_123 = eq(_dword_addr_matches_T_121, _dword_addr_matches_T_122) node dword_addr_matches_27 = and(_dword_addr_matches_T_120, _dword_addr_matches_T_123) node mask_union_3 = and(lcam_mask[0], write_mask_3) node _addr_matches_0_3_T = neq(mask_union_3, UInt<1>(0h0)) node _addr_matches_0_3_T_1 = and(_addr_matches_0_3_T, dword_addr_matches_27) connect addr_matches[0][3], _addr_matches_0_3_T_1 node _forward_matches_0_3_T = and(addr_matches[0][3], stq_data[3].valid) node _forward_matches_0_3_T_1 = eq(mask_union_3, lcam_mask[0]) node _forward_matches_0_3_T_2 = and(_forward_matches_0_3_T, _forward_matches_0_3_T_1) connect forward_matches[0][3], _forward_matches_0_3_T_2 node _prs2_matches_0_3_T = eq(s_uop_6.prs2, lcam_uop[0].pdst) node _prs2_matches_0_3_T_1 = eq(s_uop_6.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_3_T_2 = and(_prs2_matches_0_3_T, _prs2_matches_0_3_T_1) node _prs2_matches_0_3_T_3 = and(_prs2_matches_0_3_T_2, UInt<1>(0h1)) connect prs2_matches[0][3], _prs2_matches_0_3_T_3 wire s_uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_7, stq_uop[4] wire write_mask_4 : UInt<8> node _write_mask_mask_T_60 = eq(s_uop_7.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_61 = bits(stq_addr[4].bits, 2, 0) node _write_mask_mask_T_62 = dshl(UInt<8>(0h1), _write_mask_mask_T_61) node _write_mask_mask_T_63 = eq(s_uop_7.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_64 = bits(stq_addr[4].bits, 2, 1) node _write_mask_mask_T_65 = dshl(_write_mask_mask_T_64, UInt<1>(0h1)) node _write_mask_mask_T_66 = dshl(UInt<8>(0h3), _write_mask_mask_T_65) node _write_mask_mask_T_67 = eq(s_uop_7.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_68 = bits(stq_addr[4].bits, 2, 2) node _write_mask_mask_T_69 = mux(_write_mask_mask_T_68, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_70 = eq(s_uop_7.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_71 = mux(_write_mask_mask_T_70, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_72 = mux(_write_mask_mask_T_67, _write_mask_mask_T_69, _write_mask_mask_T_71) node _write_mask_mask_T_73 = mux(_write_mask_mask_T_63, _write_mask_mask_T_66, _write_mask_mask_T_72) node _write_mask_mask_T_74 = mux(_write_mask_mask_T_60, _write_mask_mask_T_62, _write_mask_mask_T_73) connect write_mask_4, _write_mask_mask_T_74 node _dword_addr_matches_T_124 = eq(s_uop_7.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_125 = and(stq_addr[4].valid, _dword_addr_matches_T_124) node _dword_addr_matches_T_126 = eq(stq_addr_is_virtual[4], UInt<1>(0h0)) node _dword_addr_matches_T_127 = and(_dword_addr_matches_T_125, _dword_addr_matches_T_126) node _dword_addr_matches_T_128 = bits(stq_addr[4].bits, 31, 3) node _dword_addr_matches_T_129 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_130 = eq(_dword_addr_matches_T_128, _dword_addr_matches_T_129) node dword_addr_matches_28 = and(_dword_addr_matches_T_127, _dword_addr_matches_T_130) node mask_union_4 = and(lcam_mask[0], write_mask_4) node _addr_matches_0_4_T = neq(mask_union_4, UInt<1>(0h0)) node _addr_matches_0_4_T_1 = and(_addr_matches_0_4_T, dword_addr_matches_28) connect addr_matches[0][4], _addr_matches_0_4_T_1 node _forward_matches_0_4_T = and(addr_matches[0][4], stq_data[4].valid) node _forward_matches_0_4_T_1 = eq(mask_union_4, lcam_mask[0]) node _forward_matches_0_4_T_2 = and(_forward_matches_0_4_T, _forward_matches_0_4_T_1) connect forward_matches[0][4], _forward_matches_0_4_T_2 node _prs2_matches_0_4_T = eq(s_uop_7.prs2, lcam_uop[0].pdst) node _prs2_matches_0_4_T_1 = eq(s_uop_7.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_4_T_2 = and(_prs2_matches_0_4_T, _prs2_matches_0_4_T_1) node _prs2_matches_0_4_T_3 = and(_prs2_matches_0_4_T_2, UInt<1>(0h1)) connect prs2_matches[0][4], _prs2_matches_0_4_T_3 wire s_uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_8, stq_uop[5] wire write_mask_5 : UInt<8> node _write_mask_mask_T_75 = eq(s_uop_8.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_76 = bits(stq_addr[5].bits, 2, 0) node _write_mask_mask_T_77 = dshl(UInt<8>(0h1), _write_mask_mask_T_76) node _write_mask_mask_T_78 = eq(s_uop_8.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_79 = bits(stq_addr[5].bits, 2, 1) node _write_mask_mask_T_80 = dshl(_write_mask_mask_T_79, UInt<1>(0h1)) node _write_mask_mask_T_81 = dshl(UInt<8>(0h3), _write_mask_mask_T_80) node _write_mask_mask_T_82 = eq(s_uop_8.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_83 = bits(stq_addr[5].bits, 2, 2) node _write_mask_mask_T_84 = mux(_write_mask_mask_T_83, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_85 = eq(s_uop_8.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_86 = mux(_write_mask_mask_T_85, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_87 = mux(_write_mask_mask_T_82, _write_mask_mask_T_84, _write_mask_mask_T_86) node _write_mask_mask_T_88 = mux(_write_mask_mask_T_78, _write_mask_mask_T_81, _write_mask_mask_T_87) node _write_mask_mask_T_89 = mux(_write_mask_mask_T_75, _write_mask_mask_T_77, _write_mask_mask_T_88) connect write_mask_5, _write_mask_mask_T_89 node _dword_addr_matches_T_131 = eq(s_uop_8.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_132 = and(stq_addr[5].valid, _dword_addr_matches_T_131) node _dword_addr_matches_T_133 = eq(stq_addr_is_virtual[5], UInt<1>(0h0)) node _dword_addr_matches_T_134 = and(_dword_addr_matches_T_132, _dword_addr_matches_T_133) node _dword_addr_matches_T_135 = bits(stq_addr[5].bits, 31, 3) node _dword_addr_matches_T_136 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_137 = eq(_dword_addr_matches_T_135, _dword_addr_matches_T_136) node dword_addr_matches_29 = and(_dword_addr_matches_T_134, _dword_addr_matches_T_137) node mask_union_5 = and(lcam_mask[0], write_mask_5) node _addr_matches_0_5_T = neq(mask_union_5, UInt<1>(0h0)) node _addr_matches_0_5_T_1 = and(_addr_matches_0_5_T, dword_addr_matches_29) connect addr_matches[0][5], _addr_matches_0_5_T_1 node _forward_matches_0_5_T = and(addr_matches[0][5], stq_data[5].valid) node _forward_matches_0_5_T_1 = eq(mask_union_5, lcam_mask[0]) node _forward_matches_0_5_T_2 = and(_forward_matches_0_5_T, _forward_matches_0_5_T_1) connect forward_matches[0][5], _forward_matches_0_5_T_2 node _prs2_matches_0_5_T = eq(s_uop_8.prs2, lcam_uop[0].pdst) node _prs2_matches_0_5_T_1 = eq(s_uop_8.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_5_T_2 = and(_prs2_matches_0_5_T, _prs2_matches_0_5_T_1) node _prs2_matches_0_5_T_3 = and(_prs2_matches_0_5_T_2, UInt<1>(0h1)) connect prs2_matches[0][5], _prs2_matches_0_5_T_3 wire s_uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_9, stq_uop[6] wire write_mask_6 : UInt<8> node _write_mask_mask_T_90 = eq(s_uop_9.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_91 = bits(stq_addr[6].bits, 2, 0) node _write_mask_mask_T_92 = dshl(UInt<8>(0h1), _write_mask_mask_T_91) node _write_mask_mask_T_93 = eq(s_uop_9.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_94 = bits(stq_addr[6].bits, 2, 1) node _write_mask_mask_T_95 = dshl(_write_mask_mask_T_94, UInt<1>(0h1)) node _write_mask_mask_T_96 = dshl(UInt<8>(0h3), _write_mask_mask_T_95) node _write_mask_mask_T_97 = eq(s_uop_9.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_98 = bits(stq_addr[6].bits, 2, 2) node _write_mask_mask_T_99 = mux(_write_mask_mask_T_98, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_100 = eq(s_uop_9.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_101 = mux(_write_mask_mask_T_100, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_102 = mux(_write_mask_mask_T_97, _write_mask_mask_T_99, _write_mask_mask_T_101) node _write_mask_mask_T_103 = mux(_write_mask_mask_T_93, _write_mask_mask_T_96, _write_mask_mask_T_102) node _write_mask_mask_T_104 = mux(_write_mask_mask_T_90, _write_mask_mask_T_92, _write_mask_mask_T_103) connect write_mask_6, _write_mask_mask_T_104 node _dword_addr_matches_T_138 = eq(s_uop_9.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_139 = and(stq_addr[6].valid, _dword_addr_matches_T_138) node _dword_addr_matches_T_140 = eq(stq_addr_is_virtual[6], UInt<1>(0h0)) node _dword_addr_matches_T_141 = and(_dword_addr_matches_T_139, _dword_addr_matches_T_140) node _dword_addr_matches_T_142 = bits(stq_addr[6].bits, 31, 3) node _dword_addr_matches_T_143 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_144 = eq(_dword_addr_matches_T_142, _dword_addr_matches_T_143) node dword_addr_matches_30 = and(_dword_addr_matches_T_141, _dword_addr_matches_T_144) node mask_union_6 = and(lcam_mask[0], write_mask_6) node _addr_matches_0_6_T = neq(mask_union_6, UInt<1>(0h0)) node _addr_matches_0_6_T_1 = and(_addr_matches_0_6_T, dword_addr_matches_30) connect addr_matches[0][6], _addr_matches_0_6_T_1 node _forward_matches_0_6_T = and(addr_matches[0][6], stq_data[6].valid) node _forward_matches_0_6_T_1 = eq(mask_union_6, lcam_mask[0]) node _forward_matches_0_6_T_2 = and(_forward_matches_0_6_T, _forward_matches_0_6_T_1) connect forward_matches[0][6], _forward_matches_0_6_T_2 node _prs2_matches_0_6_T = eq(s_uop_9.prs2, lcam_uop[0].pdst) node _prs2_matches_0_6_T_1 = eq(s_uop_9.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_6_T_2 = and(_prs2_matches_0_6_T, _prs2_matches_0_6_T_1) node _prs2_matches_0_6_T_3 = and(_prs2_matches_0_6_T_2, UInt<1>(0h1)) connect prs2_matches[0][6], _prs2_matches_0_6_T_3 wire s_uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_10, stq_uop[7] wire write_mask_7 : UInt<8> node _write_mask_mask_T_105 = eq(s_uop_10.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_106 = bits(stq_addr[7].bits, 2, 0) node _write_mask_mask_T_107 = dshl(UInt<8>(0h1), _write_mask_mask_T_106) node _write_mask_mask_T_108 = eq(s_uop_10.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_109 = bits(stq_addr[7].bits, 2, 1) node _write_mask_mask_T_110 = dshl(_write_mask_mask_T_109, UInt<1>(0h1)) node _write_mask_mask_T_111 = dshl(UInt<8>(0h3), _write_mask_mask_T_110) node _write_mask_mask_T_112 = eq(s_uop_10.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_113 = bits(stq_addr[7].bits, 2, 2) node _write_mask_mask_T_114 = mux(_write_mask_mask_T_113, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_115 = eq(s_uop_10.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_116 = mux(_write_mask_mask_T_115, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_117 = mux(_write_mask_mask_T_112, _write_mask_mask_T_114, _write_mask_mask_T_116) node _write_mask_mask_T_118 = mux(_write_mask_mask_T_108, _write_mask_mask_T_111, _write_mask_mask_T_117) node _write_mask_mask_T_119 = mux(_write_mask_mask_T_105, _write_mask_mask_T_107, _write_mask_mask_T_118) connect write_mask_7, _write_mask_mask_T_119 node _dword_addr_matches_T_145 = eq(s_uop_10.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_146 = and(stq_addr[7].valid, _dword_addr_matches_T_145) node _dword_addr_matches_T_147 = eq(stq_addr_is_virtual[7], UInt<1>(0h0)) node _dword_addr_matches_T_148 = and(_dword_addr_matches_T_146, _dword_addr_matches_T_147) node _dword_addr_matches_T_149 = bits(stq_addr[7].bits, 31, 3) node _dword_addr_matches_T_150 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_151 = eq(_dword_addr_matches_T_149, _dword_addr_matches_T_150) node dword_addr_matches_31 = and(_dword_addr_matches_T_148, _dword_addr_matches_T_151) node mask_union_7 = and(lcam_mask[0], write_mask_7) node _addr_matches_0_7_T = neq(mask_union_7, UInt<1>(0h0)) node _addr_matches_0_7_T_1 = and(_addr_matches_0_7_T, dword_addr_matches_31) connect addr_matches[0][7], _addr_matches_0_7_T_1 node _forward_matches_0_7_T = and(addr_matches[0][7], stq_data[7].valid) node _forward_matches_0_7_T_1 = eq(mask_union_7, lcam_mask[0]) node _forward_matches_0_7_T_2 = and(_forward_matches_0_7_T, _forward_matches_0_7_T_1) connect forward_matches[0][7], _forward_matches_0_7_T_2 node _prs2_matches_0_7_T = eq(s_uop_10.prs2, lcam_uop[0].pdst) node _prs2_matches_0_7_T_1 = eq(s_uop_10.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_7_T_2 = and(_prs2_matches_0_7_T, _prs2_matches_0_7_T_1) node _prs2_matches_0_7_T_3 = and(_prs2_matches_0_7_T_2, UInt<1>(0h1)) connect prs2_matches[0][7], _prs2_matches_0_7_T_3 wire s_uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_11, stq_uop[8] wire write_mask_8 : UInt<8> node _write_mask_mask_T_120 = eq(s_uop_11.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_121 = bits(stq_addr[8].bits, 2, 0) node _write_mask_mask_T_122 = dshl(UInt<8>(0h1), _write_mask_mask_T_121) node _write_mask_mask_T_123 = eq(s_uop_11.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_124 = bits(stq_addr[8].bits, 2, 1) node _write_mask_mask_T_125 = dshl(_write_mask_mask_T_124, UInt<1>(0h1)) node _write_mask_mask_T_126 = dshl(UInt<8>(0h3), _write_mask_mask_T_125) node _write_mask_mask_T_127 = eq(s_uop_11.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_128 = bits(stq_addr[8].bits, 2, 2) node _write_mask_mask_T_129 = mux(_write_mask_mask_T_128, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_130 = eq(s_uop_11.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_131 = mux(_write_mask_mask_T_130, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_132 = mux(_write_mask_mask_T_127, _write_mask_mask_T_129, _write_mask_mask_T_131) node _write_mask_mask_T_133 = mux(_write_mask_mask_T_123, _write_mask_mask_T_126, _write_mask_mask_T_132) node _write_mask_mask_T_134 = mux(_write_mask_mask_T_120, _write_mask_mask_T_122, _write_mask_mask_T_133) connect write_mask_8, _write_mask_mask_T_134 node _dword_addr_matches_T_152 = eq(s_uop_11.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_153 = and(stq_addr[8].valid, _dword_addr_matches_T_152) node _dword_addr_matches_T_154 = eq(stq_addr_is_virtual[8], UInt<1>(0h0)) node _dword_addr_matches_T_155 = and(_dword_addr_matches_T_153, _dword_addr_matches_T_154) node _dword_addr_matches_T_156 = bits(stq_addr[8].bits, 31, 3) node _dword_addr_matches_T_157 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_158 = eq(_dword_addr_matches_T_156, _dword_addr_matches_T_157) node dword_addr_matches_32 = and(_dword_addr_matches_T_155, _dword_addr_matches_T_158) node mask_union_8 = and(lcam_mask[0], write_mask_8) node _addr_matches_0_8_T = neq(mask_union_8, UInt<1>(0h0)) node _addr_matches_0_8_T_1 = and(_addr_matches_0_8_T, dword_addr_matches_32) connect addr_matches[0][8], _addr_matches_0_8_T_1 node _forward_matches_0_8_T = and(addr_matches[0][8], stq_data[8].valid) node _forward_matches_0_8_T_1 = eq(mask_union_8, lcam_mask[0]) node _forward_matches_0_8_T_2 = and(_forward_matches_0_8_T, _forward_matches_0_8_T_1) connect forward_matches[0][8], _forward_matches_0_8_T_2 node _prs2_matches_0_8_T = eq(s_uop_11.prs2, lcam_uop[0].pdst) node _prs2_matches_0_8_T_1 = eq(s_uop_11.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_8_T_2 = and(_prs2_matches_0_8_T, _prs2_matches_0_8_T_1) node _prs2_matches_0_8_T_3 = and(_prs2_matches_0_8_T_2, UInt<1>(0h1)) connect prs2_matches[0][8], _prs2_matches_0_8_T_3 wire s_uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_12, stq_uop[9] wire write_mask_9 : UInt<8> node _write_mask_mask_T_135 = eq(s_uop_12.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_136 = bits(stq_addr[9].bits, 2, 0) node _write_mask_mask_T_137 = dshl(UInt<8>(0h1), _write_mask_mask_T_136) node _write_mask_mask_T_138 = eq(s_uop_12.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_139 = bits(stq_addr[9].bits, 2, 1) node _write_mask_mask_T_140 = dshl(_write_mask_mask_T_139, UInt<1>(0h1)) node _write_mask_mask_T_141 = dshl(UInt<8>(0h3), _write_mask_mask_T_140) node _write_mask_mask_T_142 = eq(s_uop_12.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_143 = bits(stq_addr[9].bits, 2, 2) node _write_mask_mask_T_144 = mux(_write_mask_mask_T_143, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_145 = eq(s_uop_12.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_146 = mux(_write_mask_mask_T_145, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_147 = mux(_write_mask_mask_T_142, _write_mask_mask_T_144, _write_mask_mask_T_146) node _write_mask_mask_T_148 = mux(_write_mask_mask_T_138, _write_mask_mask_T_141, _write_mask_mask_T_147) node _write_mask_mask_T_149 = mux(_write_mask_mask_T_135, _write_mask_mask_T_137, _write_mask_mask_T_148) connect write_mask_9, _write_mask_mask_T_149 node _dword_addr_matches_T_159 = eq(s_uop_12.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_160 = and(stq_addr[9].valid, _dword_addr_matches_T_159) node _dword_addr_matches_T_161 = eq(stq_addr_is_virtual[9], UInt<1>(0h0)) node _dword_addr_matches_T_162 = and(_dword_addr_matches_T_160, _dword_addr_matches_T_161) node _dword_addr_matches_T_163 = bits(stq_addr[9].bits, 31, 3) node _dword_addr_matches_T_164 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_165 = eq(_dword_addr_matches_T_163, _dword_addr_matches_T_164) node dword_addr_matches_33 = and(_dword_addr_matches_T_162, _dword_addr_matches_T_165) node mask_union_9 = and(lcam_mask[0], write_mask_9) node _addr_matches_0_9_T = neq(mask_union_9, UInt<1>(0h0)) node _addr_matches_0_9_T_1 = and(_addr_matches_0_9_T, dword_addr_matches_33) connect addr_matches[0][9], _addr_matches_0_9_T_1 node _forward_matches_0_9_T = and(addr_matches[0][9], stq_data[9].valid) node _forward_matches_0_9_T_1 = eq(mask_union_9, lcam_mask[0]) node _forward_matches_0_9_T_2 = and(_forward_matches_0_9_T, _forward_matches_0_9_T_1) connect forward_matches[0][9], _forward_matches_0_9_T_2 node _prs2_matches_0_9_T = eq(s_uop_12.prs2, lcam_uop[0].pdst) node _prs2_matches_0_9_T_1 = eq(s_uop_12.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_9_T_2 = and(_prs2_matches_0_9_T, _prs2_matches_0_9_T_1) node _prs2_matches_0_9_T_3 = and(_prs2_matches_0_9_T_2, UInt<1>(0h1)) connect prs2_matches[0][9], _prs2_matches_0_9_T_3 wire s_uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_13, stq_uop[10] wire write_mask_10 : UInt<8> node _write_mask_mask_T_150 = eq(s_uop_13.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_151 = bits(stq_addr[10].bits, 2, 0) node _write_mask_mask_T_152 = dshl(UInt<8>(0h1), _write_mask_mask_T_151) node _write_mask_mask_T_153 = eq(s_uop_13.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_154 = bits(stq_addr[10].bits, 2, 1) node _write_mask_mask_T_155 = dshl(_write_mask_mask_T_154, UInt<1>(0h1)) node _write_mask_mask_T_156 = dshl(UInt<8>(0h3), _write_mask_mask_T_155) node _write_mask_mask_T_157 = eq(s_uop_13.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_158 = bits(stq_addr[10].bits, 2, 2) node _write_mask_mask_T_159 = mux(_write_mask_mask_T_158, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_160 = eq(s_uop_13.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_161 = mux(_write_mask_mask_T_160, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_162 = mux(_write_mask_mask_T_157, _write_mask_mask_T_159, _write_mask_mask_T_161) node _write_mask_mask_T_163 = mux(_write_mask_mask_T_153, _write_mask_mask_T_156, _write_mask_mask_T_162) node _write_mask_mask_T_164 = mux(_write_mask_mask_T_150, _write_mask_mask_T_152, _write_mask_mask_T_163) connect write_mask_10, _write_mask_mask_T_164 node _dword_addr_matches_T_166 = eq(s_uop_13.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_167 = and(stq_addr[10].valid, _dword_addr_matches_T_166) node _dword_addr_matches_T_168 = eq(stq_addr_is_virtual[10], UInt<1>(0h0)) node _dword_addr_matches_T_169 = and(_dword_addr_matches_T_167, _dword_addr_matches_T_168) node _dword_addr_matches_T_170 = bits(stq_addr[10].bits, 31, 3) node _dword_addr_matches_T_171 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_172 = eq(_dword_addr_matches_T_170, _dword_addr_matches_T_171) node dword_addr_matches_34 = and(_dword_addr_matches_T_169, _dword_addr_matches_T_172) node mask_union_10 = and(lcam_mask[0], write_mask_10) node _addr_matches_0_10_T = neq(mask_union_10, UInt<1>(0h0)) node _addr_matches_0_10_T_1 = and(_addr_matches_0_10_T, dword_addr_matches_34) connect addr_matches[0][10], _addr_matches_0_10_T_1 node _forward_matches_0_10_T = and(addr_matches[0][10], stq_data[10].valid) node _forward_matches_0_10_T_1 = eq(mask_union_10, lcam_mask[0]) node _forward_matches_0_10_T_2 = and(_forward_matches_0_10_T, _forward_matches_0_10_T_1) connect forward_matches[0][10], _forward_matches_0_10_T_2 node _prs2_matches_0_10_T = eq(s_uop_13.prs2, lcam_uop[0].pdst) node _prs2_matches_0_10_T_1 = eq(s_uop_13.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_10_T_2 = and(_prs2_matches_0_10_T, _prs2_matches_0_10_T_1) node _prs2_matches_0_10_T_3 = and(_prs2_matches_0_10_T_2, UInt<1>(0h1)) connect prs2_matches[0][10], _prs2_matches_0_10_T_3 wire s_uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_14, stq_uop[11] wire write_mask_11 : UInt<8> node _write_mask_mask_T_165 = eq(s_uop_14.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_166 = bits(stq_addr[11].bits, 2, 0) node _write_mask_mask_T_167 = dshl(UInt<8>(0h1), _write_mask_mask_T_166) node _write_mask_mask_T_168 = eq(s_uop_14.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_169 = bits(stq_addr[11].bits, 2, 1) node _write_mask_mask_T_170 = dshl(_write_mask_mask_T_169, UInt<1>(0h1)) node _write_mask_mask_T_171 = dshl(UInt<8>(0h3), _write_mask_mask_T_170) node _write_mask_mask_T_172 = eq(s_uop_14.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_173 = bits(stq_addr[11].bits, 2, 2) node _write_mask_mask_T_174 = mux(_write_mask_mask_T_173, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_175 = eq(s_uop_14.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_176 = mux(_write_mask_mask_T_175, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_177 = mux(_write_mask_mask_T_172, _write_mask_mask_T_174, _write_mask_mask_T_176) node _write_mask_mask_T_178 = mux(_write_mask_mask_T_168, _write_mask_mask_T_171, _write_mask_mask_T_177) node _write_mask_mask_T_179 = mux(_write_mask_mask_T_165, _write_mask_mask_T_167, _write_mask_mask_T_178) connect write_mask_11, _write_mask_mask_T_179 node _dword_addr_matches_T_173 = eq(s_uop_14.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_174 = and(stq_addr[11].valid, _dword_addr_matches_T_173) node _dword_addr_matches_T_175 = eq(stq_addr_is_virtual[11], UInt<1>(0h0)) node _dword_addr_matches_T_176 = and(_dword_addr_matches_T_174, _dword_addr_matches_T_175) node _dword_addr_matches_T_177 = bits(stq_addr[11].bits, 31, 3) node _dword_addr_matches_T_178 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_179 = eq(_dword_addr_matches_T_177, _dword_addr_matches_T_178) node dword_addr_matches_35 = and(_dword_addr_matches_T_176, _dword_addr_matches_T_179) node mask_union_11 = and(lcam_mask[0], write_mask_11) node _addr_matches_0_11_T = neq(mask_union_11, UInt<1>(0h0)) node _addr_matches_0_11_T_1 = and(_addr_matches_0_11_T, dword_addr_matches_35) connect addr_matches[0][11], _addr_matches_0_11_T_1 node _forward_matches_0_11_T = and(addr_matches[0][11], stq_data[11].valid) node _forward_matches_0_11_T_1 = eq(mask_union_11, lcam_mask[0]) node _forward_matches_0_11_T_2 = and(_forward_matches_0_11_T, _forward_matches_0_11_T_1) connect forward_matches[0][11], _forward_matches_0_11_T_2 node _prs2_matches_0_11_T = eq(s_uop_14.prs2, lcam_uop[0].pdst) node _prs2_matches_0_11_T_1 = eq(s_uop_14.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_11_T_2 = and(_prs2_matches_0_11_T, _prs2_matches_0_11_T_1) node _prs2_matches_0_11_T_3 = and(_prs2_matches_0_11_T_2, UInt<1>(0h1)) connect prs2_matches[0][11], _prs2_matches_0_11_T_3 wire s_uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_15, stq_uop[12] wire write_mask_12 : UInt<8> node _write_mask_mask_T_180 = eq(s_uop_15.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_181 = bits(stq_addr[12].bits, 2, 0) node _write_mask_mask_T_182 = dshl(UInt<8>(0h1), _write_mask_mask_T_181) node _write_mask_mask_T_183 = eq(s_uop_15.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_184 = bits(stq_addr[12].bits, 2, 1) node _write_mask_mask_T_185 = dshl(_write_mask_mask_T_184, UInt<1>(0h1)) node _write_mask_mask_T_186 = dshl(UInt<8>(0h3), _write_mask_mask_T_185) node _write_mask_mask_T_187 = eq(s_uop_15.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_188 = bits(stq_addr[12].bits, 2, 2) node _write_mask_mask_T_189 = mux(_write_mask_mask_T_188, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_190 = eq(s_uop_15.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_191 = mux(_write_mask_mask_T_190, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_192 = mux(_write_mask_mask_T_187, _write_mask_mask_T_189, _write_mask_mask_T_191) node _write_mask_mask_T_193 = mux(_write_mask_mask_T_183, _write_mask_mask_T_186, _write_mask_mask_T_192) node _write_mask_mask_T_194 = mux(_write_mask_mask_T_180, _write_mask_mask_T_182, _write_mask_mask_T_193) connect write_mask_12, _write_mask_mask_T_194 node _dword_addr_matches_T_180 = eq(s_uop_15.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_181 = and(stq_addr[12].valid, _dword_addr_matches_T_180) node _dword_addr_matches_T_182 = eq(stq_addr_is_virtual[12], UInt<1>(0h0)) node _dword_addr_matches_T_183 = and(_dword_addr_matches_T_181, _dword_addr_matches_T_182) node _dword_addr_matches_T_184 = bits(stq_addr[12].bits, 31, 3) node _dword_addr_matches_T_185 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_186 = eq(_dword_addr_matches_T_184, _dword_addr_matches_T_185) node dword_addr_matches_36 = and(_dword_addr_matches_T_183, _dword_addr_matches_T_186) node mask_union_12 = and(lcam_mask[0], write_mask_12) node _addr_matches_0_12_T = neq(mask_union_12, UInt<1>(0h0)) node _addr_matches_0_12_T_1 = and(_addr_matches_0_12_T, dword_addr_matches_36) connect addr_matches[0][12], _addr_matches_0_12_T_1 node _forward_matches_0_12_T = and(addr_matches[0][12], stq_data[12].valid) node _forward_matches_0_12_T_1 = eq(mask_union_12, lcam_mask[0]) node _forward_matches_0_12_T_2 = and(_forward_matches_0_12_T, _forward_matches_0_12_T_1) connect forward_matches[0][12], _forward_matches_0_12_T_2 node _prs2_matches_0_12_T = eq(s_uop_15.prs2, lcam_uop[0].pdst) node _prs2_matches_0_12_T_1 = eq(s_uop_15.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_12_T_2 = and(_prs2_matches_0_12_T, _prs2_matches_0_12_T_1) node _prs2_matches_0_12_T_3 = and(_prs2_matches_0_12_T_2, UInt<1>(0h1)) connect prs2_matches[0][12], _prs2_matches_0_12_T_3 wire s_uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_16, stq_uop[13] wire write_mask_13 : UInt<8> node _write_mask_mask_T_195 = eq(s_uop_16.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_196 = bits(stq_addr[13].bits, 2, 0) node _write_mask_mask_T_197 = dshl(UInt<8>(0h1), _write_mask_mask_T_196) node _write_mask_mask_T_198 = eq(s_uop_16.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_199 = bits(stq_addr[13].bits, 2, 1) node _write_mask_mask_T_200 = dshl(_write_mask_mask_T_199, UInt<1>(0h1)) node _write_mask_mask_T_201 = dshl(UInt<8>(0h3), _write_mask_mask_T_200) node _write_mask_mask_T_202 = eq(s_uop_16.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_203 = bits(stq_addr[13].bits, 2, 2) node _write_mask_mask_T_204 = mux(_write_mask_mask_T_203, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_205 = eq(s_uop_16.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_206 = mux(_write_mask_mask_T_205, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_207 = mux(_write_mask_mask_T_202, _write_mask_mask_T_204, _write_mask_mask_T_206) node _write_mask_mask_T_208 = mux(_write_mask_mask_T_198, _write_mask_mask_T_201, _write_mask_mask_T_207) node _write_mask_mask_T_209 = mux(_write_mask_mask_T_195, _write_mask_mask_T_197, _write_mask_mask_T_208) connect write_mask_13, _write_mask_mask_T_209 node _dword_addr_matches_T_187 = eq(s_uop_16.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_188 = and(stq_addr[13].valid, _dword_addr_matches_T_187) node _dword_addr_matches_T_189 = eq(stq_addr_is_virtual[13], UInt<1>(0h0)) node _dword_addr_matches_T_190 = and(_dword_addr_matches_T_188, _dword_addr_matches_T_189) node _dword_addr_matches_T_191 = bits(stq_addr[13].bits, 31, 3) node _dword_addr_matches_T_192 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_193 = eq(_dword_addr_matches_T_191, _dword_addr_matches_T_192) node dword_addr_matches_37 = and(_dword_addr_matches_T_190, _dword_addr_matches_T_193) node mask_union_13 = and(lcam_mask[0], write_mask_13) node _addr_matches_0_13_T = neq(mask_union_13, UInt<1>(0h0)) node _addr_matches_0_13_T_1 = and(_addr_matches_0_13_T, dword_addr_matches_37) connect addr_matches[0][13], _addr_matches_0_13_T_1 node _forward_matches_0_13_T = and(addr_matches[0][13], stq_data[13].valid) node _forward_matches_0_13_T_1 = eq(mask_union_13, lcam_mask[0]) node _forward_matches_0_13_T_2 = and(_forward_matches_0_13_T, _forward_matches_0_13_T_1) connect forward_matches[0][13], _forward_matches_0_13_T_2 node _prs2_matches_0_13_T = eq(s_uop_16.prs2, lcam_uop[0].pdst) node _prs2_matches_0_13_T_1 = eq(s_uop_16.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_13_T_2 = and(_prs2_matches_0_13_T, _prs2_matches_0_13_T_1) node _prs2_matches_0_13_T_3 = and(_prs2_matches_0_13_T_2, UInt<1>(0h1)) connect prs2_matches[0][13], _prs2_matches_0_13_T_3 wire s_uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_17, stq_uop[14] wire write_mask_14 : UInt<8> node _write_mask_mask_T_210 = eq(s_uop_17.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_211 = bits(stq_addr[14].bits, 2, 0) node _write_mask_mask_T_212 = dshl(UInt<8>(0h1), _write_mask_mask_T_211) node _write_mask_mask_T_213 = eq(s_uop_17.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_214 = bits(stq_addr[14].bits, 2, 1) node _write_mask_mask_T_215 = dshl(_write_mask_mask_T_214, UInt<1>(0h1)) node _write_mask_mask_T_216 = dshl(UInt<8>(0h3), _write_mask_mask_T_215) node _write_mask_mask_T_217 = eq(s_uop_17.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_218 = bits(stq_addr[14].bits, 2, 2) node _write_mask_mask_T_219 = mux(_write_mask_mask_T_218, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_220 = eq(s_uop_17.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_221 = mux(_write_mask_mask_T_220, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_222 = mux(_write_mask_mask_T_217, _write_mask_mask_T_219, _write_mask_mask_T_221) node _write_mask_mask_T_223 = mux(_write_mask_mask_T_213, _write_mask_mask_T_216, _write_mask_mask_T_222) node _write_mask_mask_T_224 = mux(_write_mask_mask_T_210, _write_mask_mask_T_212, _write_mask_mask_T_223) connect write_mask_14, _write_mask_mask_T_224 node _dword_addr_matches_T_194 = eq(s_uop_17.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_195 = and(stq_addr[14].valid, _dword_addr_matches_T_194) node _dword_addr_matches_T_196 = eq(stq_addr_is_virtual[14], UInt<1>(0h0)) node _dword_addr_matches_T_197 = and(_dword_addr_matches_T_195, _dword_addr_matches_T_196) node _dword_addr_matches_T_198 = bits(stq_addr[14].bits, 31, 3) node _dword_addr_matches_T_199 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_200 = eq(_dword_addr_matches_T_198, _dword_addr_matches_T_199) node dword_addr_matches_38 = and(_dword_addr_matches_T_197, _dword_addr_matches_T_200) node mask_union_14 = and(lcam_mask[0], write_mask_14) node _addr_matches_0_14_T = neq(mask_union_14, UInt<1>(0h0)) node _addr_matches_0_14_T_1 = and(_addr_matches_0_14_T, dword_addr_matches_38) connect addr_matches[0][14], _addr_matches_0_14_T_1 node _forward_matches_0_14_T = and(addr_matches[0][14], stq_data[14].valid) node _forward_matches_0_14_T_1 = eq(mask_union_14, lcam_mask[0]) node _forward_matches_0_14_T_2 = and(_forward_matches_0_14_T, _forward_matches_0_14_T_1) connect forward_matches[0][14], _forward_matches_0_14_T_2 node _prs2_matches_0_14_T = eq(s_uop_17.prs2, lcam_uop[0].pdst) node _prs2_matches_0_14_T_1 = eq(s_uop_17.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_14_T_2 = and(_prs2_matches_0_14_T, _prs2_matches_0_14_T_1) node _prs2_matches_0_14_T_3 = and(_prs2_matches_0_14_T_2, UInt<1>(0h1)) connect prs2_matches[0][14], _prs2_matches_0_14_T_3 wire s_uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_18, stq_uop[15] wire write_mask_15 : UInt<8> node _write_mask_mask_T_225 = eq(s_uop_18.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_226 = bits(stq_addr[15].bits, 2, 0) node _write_mask_mask_T_227 = dshl(UInt<8>(0h1), _write_mask_mask_T_226) node _write_mask_mask_T_228 = eq(s_uop_18.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_229 = bits(stq_addr[15].bits, 2, 1) node _write_mask_mask_T_230 = dshl(_write_mask_mask_T_229, UInt<1>(0h1)) node _write_mask_mask_T_231 = dshl(UInt<8>(0h3), _write_mask_mask_T_230) node _write_mask_mask_T_232 = eq(s_uop_18.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_233 = bits(stq_addr[15].bits, 2, 2) node _write_mask_mask_T_234 = mux(_write_mask_mask_T_233, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_235 = eq(s_uop_18.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_236 = mux(_write_mask_mask_T_235, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_237 = mux(_write_mask_mask_T_232, _write_mask_mask_T_234, _write_mask_mask_T_236) node _write_mask_mask_T_238 = mux(_write_mask_mask_T_228, _write_mask_mask_T_231, _write_mask_mask_T_237) node _write_mask_mask_T_239 = mux(_write_mask_mask_T_225, _write_mask_mask_T_227, _write_mask_mask_T_238) connect write_mask_15, _write_mask_mask_T_239 node _dword_addr_matches_T_201 = eq(s_uop_18.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_202 = and(stq_addr[15].valid, _dword_addr_matches_T_201) node _dword_addr_matches_T_203 = eq(stq_addr_is_virtual[15], UInt<1>(0h0)) node _dword_addr_matches_T_204 = and(_dword_addr_matches_T_202, _dword_addr_matches_T_203) node _dword_addr_matches_T_205 = bits(stq_addr[15].bits, 31, 3) node _dword_addr_matches_T_206 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_207 = eq(_dword_addr_matches_T_205, _dword_addr_matches_T_206) node dword_addr_matches_39 = and(_dword_addr_matches_T_204, _dword_addr_matches_T_207) node mask_union_15 = and(lcam_mask[0], write_mask_15) node _addr_matches_0_15_T = neq(mask_union_15, UInt<1>(0h0)) node _addr_matches_0_15_T_1 = and(_addr_matches_0_15_T, dword_addr_matches_39) connect addr_matches[0][15], _addr_matches_0_15_T_1 node _forward_matches_0_15_T = and(addr_matches[0][15], stq_data[15].valid) node _forward_matches_0_15_T_1 = eq(mask_union_15, lcam_mask[0]) node _forward_matches_0_15_T_2 = and(_forward_matches_0_15_T, _forward_matches_0_15_T_1) connect forward_matches[0][15], _forward_matches_0_15_T_2 node _prs2_matches_0_15_T = eq(s_uop_18.prs2, lcam_uop[0].pdst) node _prs2_matches_0_15_T_1 = eq(s_uop_18.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_15_T_2 = and(_prs2_matches_0_15_T, _prs2_matches_0_15_T_1) node _prs2_matches_0_15_T_3 = and(_prs2_matches_0_15_T_2, UInt<1>(0h1)) connect prs2_matches[0][15], _prs2_matches_0_15_T_3 wire s_uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_19, stq_uop[16] wire write_mask_16 : UInt<8> node _write_mask_mask_T_240 = eq(s_uop_19.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_241 = bits(stq_addr[16].bits, 2, 0) node _write_mask_mask_T_242 = dshl(UInt<8>(0h1), _write_mask_mask_T_241) node _write_mask_mask_T_243 = eq(s_uop_19.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_244 = bits(stq_addr[16].bits, 2, 1) node _write_mask_mask_T_245 = dshl(_write_mask_mask_T_244, UInt<1>(0h1)) node _write_mask_mask_T_246 = dshl(UInt<8>(0h3), _write_mask_mask_T_245) node _write_mask_mask_T_247 = eq(s_uop_19.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_248 = bits(stq_addr[16].bits, 2, 2) node _write_mask_mask_T_249 = mux(_write_mask_mask_T_248, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_250 = eq(s_uop_19.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_251 = mux(_write_mask_mask_T_250, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_252 = mux(_write_mask_mask_T_247, _write_mask_mask_T_249, _write_mask_mask_T_251) node _write_mask_mask_T_253 = mux(_write_mask_mask_T_243, _write_mask_mask_T_246, _write_mask_mask_T_252) node _write_mask_mask_T_254 = mux(_write_mask_mask_T_240, _write_mask_mask_T_242, _write_mask_mask_T_253) connect write_mask_16, _write_mask_mask_T_254 node _dword_addr_matches_T_208 = eq(s_uop_19.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_209 = and(stq_addr[16].valid, _dword_addr_matches_T_208) node _dword_addr_matches_T_210 = eq(stq_addr_is_virtual[16], UInt<1>(0h0)) node _dword_addr_matches_T_211 = and(_dword_addr_matches_T_209, _dword_addr_matches_T_210) node _dword_addr_matches_T_212 = bits(stq_addr[16].bits, 31, 3) node _dword_addr_matches_T_213 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_214 = eq(_dword_addr_matches_T_212, _dword_addr_matches_T_213) node dword_addr_matches_40 = and(_dword_addr_matches_T_211, _dword_addr_matches_T_214) node mask_union_16 = and(lcam_mask[0], write_mask_16) node _addr_matches_0_16_T = neq(mask_union_16, UInt<1>(0h0)) node _addr_matches_0_16_T_1 = and(_addr_matches_0_16_T, dword_addr_matches_40) connect addr_matches[0][16], _addr_matches_0_16_T_1 node _forward_matches_0_16_T = and(addr_matches[0][16], stq_data[16].valid) node _forward_matches_0_16_T_1 = eq(mask_union_16, lcam_mask[0]) node _forward_matches_0_16_T_2 = and(_forward_matches_0_16_T, _forward_matches_0_16_T_1) connect forward_matches[0][16], _forward_matches_0_16_T_2 node _prs2_matches_0_16_T = eq(s_uop_19.prs2, lcam_uop[0].pdst) node _prs2_matches_0_16_T_1 = eq(s_uop_19.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_16_T_2 = and(_prs2_matches_0_16_T, _prs2_matches_0_16_T_1) node _prs2_matches_0_16_T_3 = and(_prs2_matches_0_16_T_2, UInt<1>(0h1)) connect prs2_matches[0][16], _prs2_matches_0_16_T_3 wire s_uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_20, stq_uop[17] wire write_mask_17 : UInt<8> node _write_mask_mask_T_255 = eq(s_uop_20.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_256 = bits(stq_addr[17].bits, 2, 0) node _write_mask_mask_T_257 = dshl(UInt<8>(0h1), _write_mask_mask_T_256) node _write_mask_mask_T_258 = eq(s_uop_20.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_259 = bits(stq_addr[17].bits, 2, 1) node _write_mask_mask_T_260 = dshl(_write_mask_mask_T_259, UInt<1>(0h1)) node _write_mask_mask_T_261 = dshl(UInt<8>(0h3), _write_mask_mask_T_260) node _write_mask_mask_T_262 = eq(s_uop_20.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_263 = bits(stq_addr[17].bits, 2, 2) node _write_mask_mask_T_264 = mux(_write_mask_mask_T_263, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_265 = eq(s_uop_20.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_266 = mux(_write_mask_mask_T_265, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_267 = mux(_write_mask_mask_T_262, _write_mask_mask_T_264, _write_mask_mask_T_266) node _write_mask_mask_T_268 = mux(_write_mask_mask_T_258, _write_mask_mask_T_261, _write_mask_mask_T_267) node _write_mask_mask_T_269 = mux(_write_mask_mask_T_255, _write_mask_mask_T_257, _write_mask_mask_T_268) connect write_mask_17, _write_mask_mask_T_269 node _dword_addr_matches_T_215 = eq(s_uop_20.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_216 = and(stq_addr[17].valid, _dword_addr_matches_T_215) node _dword_addr_matches_T_217 = eq(stq_addr_is_virtual[17], UInt<1>(0h0)) node _dword_addr_matches_T_218 = and(_dword_addr_matches_T_216, _dword_addr_matches_T_217) node _dword_addr_matches_T_219 = bits(stq_addr[17].bits, 31, 3) node _dword_addr_matches_T_220 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_221 = eq(_dword_addr_matches_T_219, _dword_addr_matches_T_220) node dword_addr_matches_41 = and(_dword_addr_matches_T_218, _dword_addr_matches_T_221) node mask_union_17 = and(lcam_mask[0], write_mask_17) node _addr_matches_0_17_T = neq(mask_union_17, UInt<1>(0h0)) node _addr_matches_0_17_T_1 = and(_addr_matches_0_17_T, dword_addr_matches_41) connect addr_matches[0][17], _addr_matches_0_17_T_1 node _forward_matches_0_17_T = and(addr_matches[0][17], stq_data[17].valid) node _forward_matches_0_17_T_1 = eq(mask_union_17, lcam_mask[0]) node _forward_matches_0_17_T_2 = and(_forward_matches_0_17_T, _forward_matches_0_17_T_1) connect forward_matches[0][17], _forward_matches_0_17_T_2 node _prs2_matches_0_17_T = eq(s_uop_20.prs2, lcam_uop[0].pdst) node _prs2_matches_0_17_T_1 = eq(s_uop_20.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_17_T_2 = and(_prs2_matches_0_17_T, _prs2_matches_0_17_T_1) node _prs2_matches_0_17_T_3 = and(_prs2_matches_0_17_T_2, UInt<1>(0h1)) connect prs2_matches[0][17], _prs2_matches_0_17_T_3 wire s_uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_21, stq_uop[18] wire write_mask_18 : UInt<8> node _write_mask_mask_T_270 = eq(s_uop_21.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_271 = bits(stq_addr[18].bits, 2, 0) node _write_mask_mask_T_272 = dshl(UInt<8>(0h1), _write_mask_mask_T_271) node _write_mask_mask_T_273 = eq(s_uop_21.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_274 = bits(stq_addr[18].bits, 2, 1) node _write_mask_mask_T_275 = dshl(_write_mask_mask_T_274, UInt<1>(0h1)) node _write_mask_mask_T_276 = dshl(UInt<8>(0h3), _write_mask_mask_T_275) node _write_mask_mask_T_277 = eq(s_uop_21.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_278 = bits(stq_addr[18].bits, 2, 2) node _write_mask_mask_T_279 = mux(_write_mask_mask_T_278, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_280 = eq(s_uop_21.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_281 = mux(_write_mask_mask_T_280, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_282 = mux(_write_mask_mask_T_277, _write_mask_mask_T_279, _write_mask_mask_T_281) node _write_mask_mask_T_283 = mux(_write_mask_mask_T_273, _write_mask_mask_T_276, _write_mask_mask_T_282) node _write_mask_mask_T_284 = mux(_write_mask_mask_T_270, _write_mask_mask_T_272, _write_mask_mask_T_283) connect write_mask_18, _write_mask_mask_T_284 node _dword_addr_matches_T_222 = eq(s_uop_21.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_223 = and(stq_addr[18].valid, _dword_addr_matches_T_222) node _dword_addr_matches_T_224 = eq(stq_addr_is_virtual[18], UInt<1>(0h0)) node _dword_addr_matches_T_225 = and(_dword_addr_matches_T_223, _dword_addr_matches_T_224) node _dword_addr_matches_T_226 = bits(stq_addr[18].bits, 31, 3) node _dword_addr_matches_T_227 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_228 = eq(_dword_addr_matches_T_226, _dword_addr_matches_T_227) node dword_addr_matches_42 = and(_dword_addr_matches_T_225, _dword_addr_matches_T_228) node mask_union_18 = and(lcam_mask[0], write_mask_18) node _addr_matches_0_18_T = neq(mask_union_18, UInt<1>(0h0)) node _addr_matches_0_18_T_1 = and(_addr_matches_0_18_T, dword_addr_matches_42) connect addr_matches[0][18], _addr_matches_0_18_T_1 node _forward_matches_0_18_T = and(addr_matches[0][18], stq_data[18].valid) node _forward_matches_0_18_T_1 = eq(mask_union_18, lcam_mask[0]) node _forward_matches_0_18_T_2 = and(_forward_matches_0_18_T, _forward_matches_0_18_T_1) connect forward_matches[0][18], _forward_matches_0_18_T_2 node _prs2_matches_0_18_T = eq(s_uop_21.prs2, lcam_uop[0].pdst) node _prs2_matches_0_18_T_1 = eq(s_uop_21.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_18_T_2 = and(_prs2_matches_0_18_T, _prs2_matches_0_18_T_1) node _prs2_matches_0_18_T_3 = and(_prs2_matches_0_18_T_2, UInt<1>(0h1)) connect prs2_matches[0][18], _prs2_matches_0_18_T_3 wire s_uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_22, stq_uop[19] wire write_mask_19 : UInt<8> node _write_mask_mask_T_285 = eq(s_uop_22.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_286 = bits(stq_addr[19].bits, 2, 0) node _write_mask_mask_T_287 = dshl(UInt<8>(0h1), _write_mask_mask_T_286) node _write_mask_mask_T_288 = eq(s_uop_22.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_289 = bits(stq_addr[19].bits, 2, 1) node _write_mask_mask_T_290 = dshl(_write_mask_mask_T_289, UInt<1>(0h1)) node _write_mask_mask_T_291 = dshl(UInt<8>(0h3), _write_mask_mask_T_290) node _write_mask_mask_T_292 = eq(s_uop_22.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_293 = bits(stq_addr[19].bits, 2, 2) node _write_mask_mask_T_294 = mux(_write_mask_mask_T_293, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_295 = eq(s_uop_22.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_296 = mux(_write_mask_mask_T_295, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_297 = mux(_write_mask_mask_T_292, _write_mask_mask_T_294, _write_mask_mask_T_296) node _write_mask_mask_T_298 = mux(_write_mask_mask_T_288, _write_mask_mask_T_291, _write_mask_mask_T_297) node _write_mask_mask_T_299 = mux(_write_mask_mask_T_285, _write_mask_mask_T_287, _write_mask_mask_T_298) connect write_mask_19, _write_mask_mask_T_299 node _dword_addr_matches_T_229 = eq(s_uop_22.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_230 = and(stq_addr[19].valid, _dword_addr_matches_T_229) node _dword_addr_matches_T_231 = eq(stq_addr_is_virtual[19], UInt<1>(0h0)) node _dword_addr_matches_T_232 = and(_dword_addr_matches_T_230, _dword_addr_matches_T_231) node _dword_addr_matches_T_233 = bits(stq_addr[19].bits, 31, 3) node _dword_addr_matches_T_234 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_235 = eq(_dword_addr_matches_T_233, _dword_addr_matches_T_234) node dword_addr_matches_43 = and(_dword_addr_matches_T_232, _dword_addr_matches_T_235) node mask_union_19 = and(lcam_mask[0], write_mask_19) node _addr_matches_0_19_T = neq(mask_union_19, UInt<1>(0h0)) node _addr_matches_0_19_T_1 = and(_addr_matches_0_19_T, dword_addr_matches_43) connect addr_matches[0][19], _addr_matches_0_19_T_1 node _forward_matches_0_19_T = and(addr_matches[0][19], stq_data[19].valid) node _forward_matches_0_19_T_1 = eq(mask_union_19, lcam_mask[0]) node _forward_matches_0_19_T_2 = and(_forward_matches_0_19_T, _forward_matches_0_19_T_1) connect forward_matches[0][19], _forward_matches_0_19_T_2 node _prs2_matches_0_19_T = eq(s_uop_22.prs2, lcam_uop[0].pdst) node _prs2_matches_0_19_T_1 = eq(s_uop_22.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_19_T_2 = and(_prs2_matches_0_19_T, _prs2_matches_0_19_T_1) node _prs2_matches_0_19_T_3 = and(_prs2_matches_0_19_T_2, UInt<1>(0h1)) connect prs2_matches[0][19], _prs2_matches_0_19_T_3 wire s_uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_23, stq_uop[20] wire write_mask_20 : UInt<8> node _write_mask_mask_T_300 = eq(s_uop_23.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_301 = bits(stq_addr[20].bits, 2, 0) node _write_mask_mask_T_302 = dshl(UInt<8>(0h1), _write_mask_mask_T_301) node _write_mask_mask_T_303 = eq(s_uop_23.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_304 = bits(stq_addr[20].bits, 2, 1) node _write_mask_mask_T_305 = dshl(_write_mask_mask_T_304, UInt<1>(0h1)) node _write_mask_mask_T_306 = dshl(UInt<8>(0h3), _write_mask_mask_T_305) node _write_mask_mask_T_307 = eq(s_uop_23.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_308 = bits(stq_addr[20].bits, 2, 2) node _write_mask_mask_T_309 = mux(_write_mask_mask_T_308, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_310 = eq(s_uop_23.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_311 = mux(_write_mask_mask_T_310, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_312 = mux(_write_mask_mask_T_307, _write_mask_mask_T_309, _write_mask_mask_T_311) node _write_mask_mask_T_313 = mux(_write_mask_mask_T_303, _write_mask_mask_T_306, _write_mask_mask_T_312) node _write_mask_mask_T_314 = mux(_write_mask_mask_T_300, _write_mask_mask_T_302, _write_mask_mask_T_313) connect write_mask_20, _write_mask_mask_T_314 node _dword_addr_matches_T_236 = eq(s_uop_23.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_237 = and(stq_addr[20].valid, _dword_addr_matches_T_236) node _dword_addr_matches_T_238 = eq(stq_addr_is_virtual[20], UInt<1>(0h0)) node _dword_addr_matches_T_239 = and(_dword_addr_matches_T_237, _dword_addr_matches_T_238) node _dword_addr_matches_T_240 = bits(stq_addr[20].bits, 31, 3) node _dword_addr_matches_T_241 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_242 = eq(_dword_addr_matches_T_240, _dword_addr_matches_T_241) node dword_addr_matches_44 = and(_dword_addr_matches_T_239, _dword_addr_matches_T_242) node mask_union_20 = and(lcam_mask[0], write_mask_20) node _addr_matches_0_20_T = neq(mask_union_20, UInt<1>(0h0)) node _addr_matches_0_20_T_1 = and(_addr_matches_0_20_T, dword_addr_matches_44) connect addr_matches[0][20], _addr_matches_0_20_T_1 node _forward_matches_0_20_T = and(addr_matches[0][20], stq_data[20].valid) node _forward_matches_0_20_T_1 = eq(mask_union_20, lcam_mask[0]) node _forward_matches_0_20_T_2 = and(_forward_matches_0_20_T, _forward_matches_0_20_T_1) connect forward_matches[0][20], _forward_matches_0_20_T_2 node _prs2_matches_0_20_T = eq(s_uop_23.prs2, lcam_uop[0].pdst) node _prs2_matches_0_20_T_1 = eq(s_uop_23.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_20_T_2 = and(_prs2_matches_0_20_T, _prs2_matches_0_20_T_1) node _prs2_matches_0_20_T_3 = and(_prs2_matches_0_20_T_2, UInt<1>(0h1)) connect prs2_matches[0][20], _prs2_matches_0_20_T_3 wire s_uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_24, stq_uop[21] wire write_mask_21 : UInt<8> node _write_mask_mask_T_315 = eq(s_uop_24.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_316 = bits(stq_addr[21].bits, 2, 0) node _write_mask_mask_T_317 = dshl(UInt<8>(0h1), _write_mask_mask_T_316) node _write_mask_mask_T_318 = eq(s_uop_24.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_319 = bits(stq_addr[21].bits, 2, 1) node _write_mask_mask_T_320 = dshl(_write_mask_mask_T_319, UInt<1>(0h1)) node _write_mask_mask_T_321 = dshl(UInt<8>(0h3), _write_mask_mask_T_320) node _write_mask_mask_T_322 = eq(s_uop_24.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_323 = bits(stq_addr[21].bits, 2, 2) node _write_mask_mask_T_324 = mux(_write_mask_mask_T_323, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_325 = eq(s_uop_24.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_326 = mux(_write_mask_mask_T_325, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_327 = mux(_write_mask_mask_T_322, _write_mask_mask_T_324, _write_mask_mask_T_326) node _write_mask_mask_T_328 = mux(_write_mask_mask_T_318, _write_mask_mask_T_321, _write_mask_mask_T_327) node _write_mask_mask_T_329 = mux(_write_mask_mask_T_315, _write_mask_mask_T_317, _write_mask_mask_T_328) connect write_mask_21, _write_mask_mask_T_329 node _dword_addr_matches_T_243 = eq(s_uop_24.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_244 = and(stq_addr[21].valid, _dword_addr_matches_T_243) node _dword_addr_matches_T_245 = eq(stq_addr_is_virtual[21], UInt<1>(0h0)) node _dword_addr_matches_T_246 = and(_dword_addr_matches_T_244, _dword_addr_matches_T_245) node _dword_addr_matches_T_247 = bits(stq_addr[21].bits, 31, 3) node _dword_addr_matches_T_248 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_249 = eq(_dword_addr_matches_T_247, _dword_addr_matches_T_248) node dword_addr_matches_45 = and(_dword_addr_matches_T_246, _dword_addr_matches_T_249) node mask_union_21 = and(lcam_mask[0], write_mask_21) node _addr_matches_0_21_T = neq(mask_union_21, UInt<1>(0h0)) node _addr_matches_0_21_T_1 = and(_addr_matches_0_21_T, dword_addr_matches_45) connect addr_matches[0][21], _addr_matches_0_21_T_1 node _forward_matches_0_21_T = and(addr_matches[0][21], stq_data[21].valid) node _forward_matches_0_21_T_1 = eq(mask_union_21, lcam_mask[0]) node _forward_matches_0_21_T_2 = and(_forward_matches_0_21_T, _forward_matches_0_21_T_1) connect forward_matches[0][21], _forward_matches_0_21_T_2 node _prs2_matches_0_21_T = eq(s_uop_24.prs2, lcam_uop[0].pdst) node _prs2_matches_0_21_T_1 = eq(s_uop_24.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_21_T_2 = and(_prs2_matches_0_21_T, _prs2_matches_0_21_T_1) node _prs2_matches_0_21_T_3 = and(_prs2_matches_0_21_T_2, UInt<1>(0h1)) connect prs2_matches[0][21], _prs2_matches_0_21_T_3 wire s_uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_25, stq_uop[22] wire write_mask_22 : UInt<8> node _write_mask_mask_T_330 = eq(s_uop_25.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_331 = bits(stq_addr[22].bits, 2, 0) node _write_mask_mask_T_332 = dshl(UInt<8>(0h1), _write_mask_mask_T_331) node _write_mask_mask_T_333 = eq(s_uop_25.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_334 = bits(stq_addr[22].bits, 2, 1) node _write_mask_mask_T_335 = dshl(_write_mask_mask_T_334, UInt<1>(0h1)) node _write_mask_mask_T_336 = dshl(UInt<8>(0h3), _write_mask_mask_T_335) node _write_mask_mask_T_337 = eq(s_uop_25.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_338 = bits(stq_addr[22].bits, 2, 2) node _write_mask_mask_T_339 = mux(_write_mask_mask_T_338, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_340 = eq(s_uop_25.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_341 = mux(_write_mask_mask_T_340, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_342 = mux(_write_mask_mask_T_337, _write_mask_mask_T_339, _write_mask_mask_T_341) node _write_mask_mask_T_343 = mux(_write_mask_mask_T_333, _write_mask_mask_T_336, _write_mask_mask_T_342) node _write_mask_mask_T_344 = mux(_write_mask_mask_T_330, _write_mask_mask_T_332, _write_mask_mask_T_343) connect write_mask_22, _write_mask_mask_T_344 node _dword_addr_matches_T_250 = eq(s_uop_25.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_251 = and(stq_addr[22].valid, _dword_addr_matches_T_250) node _dword_addr_matches_T_252 = eq(stq_addr_is_virtual[22], UInt<1>(0h0)) node _dword_addr_matches_T_253 = and(_dword_addr_matches_T_251, _dword_addr_matches_T_252) node _dword_addr_matches_T_254 = bits(stq_addr[22].bits, 31, 3) node _dword_addr_matches_T_255 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_256 = eq(_dword_addr_matches_T_254, _dword_addr_matches_T_255) node dword_addr_matches_46 = and(_dword_addr_matches_T_253, _dword_addr_matches_T_256) node mask_union_22 = and(lcam_mask[0], write_mask_22) node _addr_matches_0_22_T = neq(mask_union_22, UInt<1>(0h0)) node _addr_matches_0_22_T_1 = and(_addr_matches_0_22_T, dword_addr_matches_46) connect addr_matches[0][22], _addr_matches_0_22_T_1 node _forward_matches_0_22_T = and(addr_matches[0][22], stq_data[22].valid) node _forward_matches_0_22_T_1 = eq(mask_union_22, lcam_mask[0]) node _forward_matches_0_22_T_2 = and(_forward_matches_0_22_T, _forward_matches_0_22_T_1) connect forward_matches[0][22], _forward_matches_0_22_T_2 node _prs2_matches_0_22_T = eq(s_uop_25.prs2, lcam_uop[0].pdst) node _prs2_matches_0_22_T_1 = eq(s_uop_25.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_22_T_2 = and(_prs2_matches_0_22_T, _prs2_matches_0_22_T_1) node _prs2_matches_0_22_T_3 = and(_prs2_matches_0_22_T_2, UInt<1>(0h1)) connect prs2_matches[0][22], _prs2_matches_0_22_T_3 wire s_uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_26, stq_uop[23] wire write_mask_23 : UInt<8> node _write_mask_mask_T_345 = eq(s_uop_26.mem_size, UInt<1>(0h0)) node _write_mask_mask_T_346 = bits(stq_addr[23].bits, 2, 0) node _write_mask_mask_T_347 = dshl(UInt<8>(0h1), _write_mask_mask_T_346) node _write_mask_mask_T_348 = eq(s_uop_26.mem_size, UInt<1>(0h1)) node _write_mask_mask_T_349 = bits(stq_addr[23].bits, 2, 1) node _write_mask_mask_T_350 = dshl(_write_mask_mask_T_349, UInt<1>(0h1)) node _write_mask_mask_T_351 = dshl(UInt<8>(0h3), _write_mask_mask_T_350) node _write_mask_mask_T_352 = eq(s_uop_26.mem_size, UInt<2>(0h2)) node _write_mask_mask_T_353 = bits(stq_addr[23].bits, 2, 2) node _write_mask_mask_T_354 = mux(_write_mask_mask_T_353, UInt<8>(0hf0), UInt<8>(0hf)) node _write_mask_mask_T_355 = eq(s_uop_26.mem_size, UInt<2>(0h3)) node _write_mask_mask_T_356 = mux(_write_mask_mask_T_355, UInt<8>(0hff), UInt<8>(0hff)) node _write_mask_mask_T_357 = mux(_write_mask_mask_T_352, _write_mask_mask_T_354, _write_mask_mask_T_356) node _write_mask_mask_T_358 = mux(_write_mask_mask_T_348, _write_mask_mask_T_351, _write_mask_mask_T_357) node _write_mask_mask_T_359 = mux(_write_mask_mask_T_345, _write_mask_mask_T_347, _write_mask_mask_T_358) connect write_mask_23, _write_mask_mask_T_359 node _dword_addr_matches_T_257 = eq(s_uop_26.is_amo, UInt<1>(0h0)) node _dword_addr_matches_T_258 = and(stq_addr[23].valid, _dword_addr_matches_T_257) node _dword_addr_matches_T_259 = eq(stq_addr_is_virtual[23], UInt<1>(0h0)) node _dword_addr_matches_T_260 = and(_dword_addr_matches_T_258, _dword_addr_matches_T_259) node _dword_addr_matches_T_261 = bits(stq_addr[23].bits, 31, 3) node _dword_addr_matches_T_262 = bits(lcam_addr[0], 31, 3) node _dword_addr_matches_T_263 = eq(_dword_addr_matches_T_261, _dword_addr_matches_T_262) node dword_addr_matches_47 = and(_dword_addr_matches_T_260, _dword_addr_matches_T_263) node mask_union_23 = and(lcam_mask[0], write_mask_23) node _addr_matches_0_23_T = neq(mask_union_23, UInt<1>(0h0)) node _addr_matches_0_23_T_1 = and(_addr_matches_0_23_T, dword_addr_matches_47) connect addr_matches[0][23], _addr_matches_0_23_T_1 node _forward_matches_0_23_T = and(addr_matches[0][23], stq_data[23].valid) node _forward_matches_0_23_T_1 = eq(mask_union_23, lcam_mask[0]) node _forward_matches_0_23_T_2 = and(_forward_matches_0_23_T, _forward_matches_0_23_T_1) connect forward_matches[0][23], _forward_matches_0_23_T_2 node _prs2_matches_0_23_T = eq(s_uop_26.prs2, lcam_uop[0].pdst) node _prs2_matches_0_23_T_1 = eq(s_uop_26.lrs2_rtype, UInt<2>(0h0)) node _prs2_matches_0_23_T_2 = and(_prs2_matches_0_23_T, _prs2_matches_0_23_T_1) node _prs2_matches_0_23_T_3 = and(_prs2_matches_0_23_T_2, UInt<1>(0h1)) connect prs2_matches[0][23], _prs2_matches_0_23_T_3 node fast_stq_valids_lo_lo_lo_hi = cat(stq_valid[2], stq_valid[1]) node fast_stq_valids_lo_lo_lo = cat(fast_stq_valids_lo_lo_lo_hi, stq_valid[0]) node fast_stq_valids_lo_lo_hi_hi = cat(stq_valid[5], stq_valid[4]) node fast_stq_valids_lo_lo_hi = cat(fast_stq_valids_lo_lo_hi_hi, stq_valid[3]) node fast_stq_valids_lo_lo = cat(fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo) node fast_stq_valids_lo_hi_lo_hi = cat(stq_valid[8], stq_valid[7]) node fast_stq_valids_lo_hi_lo = cat(fast_stq_valids_lo_hi_lo_hi, stq_valid[6]) node fast_stq_valids_lo_hi_hi_hi = cat(stq_valid[11], stq_valid[10]) node fast_stq_valids_lo_hi_hi = cat(fast_stq_valids_lo_hi_hi_hi, stq_valid[9]) node fast_stq_valids_lo_hi = cat(fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo) node fast_stq_valids_lo = cat(fast_stq_valids_lo_hi, fast_stq_valids_lo_lo) node fast_stq_valids_hi_lo_lo_hi = cat(stq_valid[14], stq_valid[13]) node fast_stq_valids_hi_lo_lo = cat(fast_stq_valids_hi_lo_lo_hi, stq_valid[12]) node fast_stq_valids_hi_lo_hi_hi = cat(stq_valid[17], stq_valid[16]) node fast_stq_valids_hi_lo_hi = cat(fast_stq_valids_hi_lo_hi_hi, stq_valid[15]) node fast_stq_valids_hi_lo = cat(fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo) node fast_stq_valids_hi_hi_lo_hi = cat(stq_valid[20], stq_valid[19]) node fast_stq_valids_hi_hi_lo = cat(fast_stq_valids_hi_hi_lo_hi, stq_valid[18]) node fast_stq_valids_hi_hi_hi_hi = cat(stq_valid[23], stq_valid[22]) node fast_stq_valids_hi_hi_hi = cat(fast_stq_valids_hi_hi_hi_hi, stq_valid[21]) node fast_stq_valids_hi_hi = cat(fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo) node fast_stq_valids_hi = cat(fast_stq_valids_hi_hi, fast_stq_valids_hi_lo) node fast_stq_valids = cat(fast_stq_valids_hi, fast_stq_valids_lo) node ldst_addr_matches_0_lo_lo_lo_hi = cat(addr_matches[0][2], addr_matches[0][1]) node ldst_addr_matches_0_lo_lo_lo = cat(ldst_addr_matches_0_lo_lo_lo_hi, addr_matches[0][0]) node ldst_addr_matches_0_lo_lo_hi_hi = cat(addr_matches[0][5], addr_matches[0][4]) node ldst_addr_matches_0_lo_lo_hi = cat(ldst_addr_matches_0_lo_lo_hi_hi, addr_matches[0][3]) node ldst_addr_matches_0_lo_lo = cat(ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo) node ldst_addr_matches_0_lo_hi_lo_hi = cat(addr_matches[0][8], addr_matches[0][7]) node ldst_addr_matches_0_lo_hi_lo = cat(ldst_addr_matches_0_lo_hi_lo_hi, addr_matches[0][6]) node ldst_addr_matches_0_lo_hi_hi_hi = cat(addr_matches[0][11], addr_matches[0][10]) node ldst_addr_matches_0_lo_hi_hi = cat(ldst_addr_matches_0_lo_hi_hi_hi, addr_matches[0][9]) node ldst_addr_matches_0_lo_hi = cat(ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo) node ldst_addr_matches_0_lo = cat(ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo) node ldst_addr_matches_0_hi_lo_lo_hi = cat(addr_matches[0][14], addr_matches[0][13]) node ldst_addr_matches_0_hi_lo_lo = cat(ldst_addr_matches_0_hi_lo_lo_hi, addr_matches[0][12]) node ldst_addr_matches_0_hi_lo_hi_hi = cat(addr_matches[0][17], addr_matches[0][16]) node ldst_addr_matches_0_hi_lo_hi = cat(ldst_addr_matches_0_hi_lo_hi_hi, addr_matches[0][15]) node ldst_addr_matches_0_hi_lo = cat(ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo) node ldst_addr_matches_0_hi_hi_lo_hi = cat(addr_matches[0][20], addr_matches[0][19]) node ldst_addr_matches_0_hi_hi_lo = cat(ldst_addr_matches_0_hi_hi_lo_hi, addr_matches[0][18]) node ldst_addr_matches_0_hi_hi_hi_hi = cat(addr_matches[0][23], addr_matches[0][22]) node ldst_addr_matches_0_hi_hi_hi = cat(ldst_addr_matches_0_hi_hi_hi_hi, addr_matches[0][21]) node ldst_addr_matches_0_hi_hi = cat(ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo) node ldst_addr_matches_0_hi = cat(ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo) node _ldst_addr_matches_0_T = cat(ldst_addr_matches_0_hi, ldst_addr_matches_0_lo) node _ldst_addr_matches_0_T_1 = and(_ldst_addr_matches_0_T, lcam_st_dep_mask[0]) node _ldst_addr_matches_0_T_2 = and(_ldst_addr_matches_0_T_1, fast_stq_valids) connect ldst_addr_matches[0], _ldst_addr_matches_0_T_2 node ldst_forward_matches_0_lo_lo_lo_hi = cat(forward_matches[0][2], forward_matches[0][1]) node ldst_forward_matches_0_lo_lo_lo = cat(ldst_forward_matches_0_lo_lo_lo_hi, forward_matches[0][0]) node ldst_forward_matches_0_lo_lo_hi_hi = cat(forward_matches[0][5], forward_matches[0][4]) node ldst_forward_matches_0_lo_lo_hi = cat(ldst_forward_matches_0_lo_lo_hi_hi, forward_matches[0][3]) node ldst_forward_matches_0_lo_lo = cat(ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo) node ldst_forward_matches_0_lo_hi_lo_hi = cat(forward_matches[0][8], forward_matches[0][7]) node ldst_forward_matches_0_lo_hi_lo = cat(ldst_forward_matches_0_lo_hi_lo_hi, forward_matches[0][6]) node ldst_forward_matches_0_lo_hi_hi_hi = cat(forward_matches[0][11], forward_matches[0][10]) node ldst_forward_matches_0_lo_hi_hi = cat(ldst_forward_matches_0_lo_hi_hi_hi, forward_matches[0][9]) node ldst_forward_matches_0_lo_hi = cat(ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo) node ldst_forward_matches_0_lo = cat(ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo) node ldst_forward_matches_0_hi_lo_lo_hi = cat(forward_matches[0][14], forward_matches[0][13]) node ldst_forward_matches_0_hi_lo_lo = cat(ldst_forward_matches_0_hi_lo_lo_hi, forward_matches[0][12]) node ldst_forward_matches_0_hi_lo_hi_hi = cat(forward_matches[0][17], forward_matches[0][16]) node ldst_forward_matches_0_hi_lo_hi = cat(ldst_forward_matches_0_hi_lo_hi_hi, forward_matches[0][15]) node ldst_forward_matches_0_hi_lo = cat(ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo) node ldst_forward_matches_0_hi_hi_lo_hi = cat(forward_matches[0][20], forward_matches[0][19]) node ldst_forward_matches_0_hi_hi_lo = cat(ldst_forward_matches_0_hi_hi_lo_hi, forward_matches[0][18]) node ldst_forward_matches_0_hi_hi_hi_hi = cat(forward_matches[0][23], forward_matches[0][22]) node ldst_forward_matches_0_hi_hi_hi = cat(ldst_forward_matches_0_hi_hi_hi_hi, forward_matches[0][21]) node ldst_forward_matches_0_hi_hi = cat(ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo) node ldst_forward_matches_0_hi = cat(ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo) node _ldst_forward_matches_0_T = cat(ldst_forward_matches_0_hi, ldst_forward_matches_0_lo) node _ldst_forward_matches_0_T_1 = and(_ldst_forward_matches_0_T, lcam_st_dep_mask[0]) node _ldst_forward_matches_0_T_2 = and(_ldst_forward_matches_0_T_1, fast_stq_valids) connect ldst_forward_matches[0], _ldst_forward_matches_0_T_2 node stld_prs2_matches_0_lo_lo_lo_hi = cat(prs2_matches[0][2], prs2_matches[0][1]) node stld_prs2_matches_0_lo_lo_lo = cat(stld_prs2_matches_0_lo_lo_lo_hi, prs2_matches[0][0]) node stld_prs2_matches_0_lo_lo_hi_hi = cat(prs2_matches[0][5], prs2_matches[0][4]) node stld_prs2_matches_0_lo_lo_hi = cat(stld_prs2_matches_0_lo_lo_hi_hi, prs2_matches[0][3]) node stld_prs2_matches_0_lo_lo = cat(stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo) node stld_prs2_matches_0_lo_hi_lo_hi = cat(prs2_matches[0][8], prs2_matches[0][7]) node stld_prs2_matches_0_lo_hi_lo = cat(stld_prs2_matches_0_lo_hi_lo_hi, prs2_matches[0][6]) node stld_prs2_matches_0_lo_hi_hi_hi = cat(prs2_matches[0][11], prs2_matches[0][10]) node stld_prs2_matches_0_lo_hi_hi = cat(stld_prs2_matches_0_lo_hi_hi_hi, prs2_matches[0][9]) node stld_prs2_matches_0_lo_hi = cat(stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo) node stld_prs2_matches_0_lo = cat(stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo) node stld_prs2_matches_0_hi_lo_lo_hi = cat(prs2_matches[0][14], prs2_matches[0][13]) node stld_prs2_matches_0_hi_lo_lo = cat(stld_prs2_matches_0_hi_lo_lo_hi, prs2_matches[0][12]) node stld_prs2_matches_0_hi_lo_hi_hi = cat(prs2_matches[0][17], prs2_matches[0][16]) node stld_prs2_matches_0_hi_lo_hi = cat(stld_prs2_matches_0_hi_lo_hi_hi, prs2_matches[0][15]) node stld_prs2_matches_0_hi_lo = cat(stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo) node stld_prs2_matches_0_hi_hi_lo_hi = cat(prs2_matches[0][20], prs2_matches[0][19]) node stld_prs2_matches_0_hi_hi_lo = cat(stld_prs2_matches_0_hi_hi_lo_hi, prs2_matches[0][18]) node stld_prs2_matches_0_hi_hi_hi_hi = cat(prs2_matches[0][23], prs2_matches[0][22]) node stld_prs2_matches_0_hi_hi_hi = cat(stld_prs2_matches_0_hi_hi_hi_hi, prs2_matches[0][21]) node stld_prs2_matches_0_hi_hi = cat(stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo) node stld_prs2_matches_0_hi = cat(stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo) node _stld_prs2_matches_0_T = cat(stld_prs2_matches_0_hi, stld_prs2_matches_0_lo) node _stld_prs2_matches_0_T_1 = not(lcam_st_dep_mask[0]) node _stld_prs2_matches_0_T_2 = and(_stld_prs2_matches_0_T, _stld_prs2_matches_0_T_1) node _stld_prs2_matches_0_T_3 = and(_stld_prs2_matches_0_T_2, fast_stq_valids) connect stld_prs2_matches[0], _stld_prs2_matches_0_T_3 node _stq_amos_T = or(stq_uop[0].is_fence, stq_uop[0].is_amo) node _stq_amos_T_1 = or(stq_uop[1].is_fence, stq_uop[1].is_amo) node _stq_amos_T_2 = or(stq_uop[2].is_fence, stq_uop[2].is_amo) node _stq_amos_T_3 = or(stq_uop[3].is_fence, stq_uop[3].is_amo) node _stq_amos_T_4 = or(stq_uop[4].is_fence, stq_uop[4].is_amo) node _stq_amos_T_5 = or(stq_uop[5].is_fence, stq_uop[5].is_amo) node _stq_amos_T_6 = or(stq_uop[6].is_fence, stq_uop[6].is_amo) node _stq_amos_T_7 = or(stq_uop[7].is_fence, stq_uop[7].is_amo) node _stq_amos_T_8 = or(stq_uop[8].is_fence, stq_uop[8].is_amo) node _stq_amos_T_9 = or(stq_uop[9].is_fence, stq_uop[9].is_amo) node _stq_amos_T_10 = or(stq_uop[10].is_fence, stq_uop[10].is_amo) node _stq_amos_T_11 = or(stq_uop[11].is_fence, stq_uop[11].is_amo) node _stq_amos_T_12 = or(stq_uop[12].is_fence, stq_uop[12].is_amo) node _stq_amos_T_13 = or(stq_uop[13].is_fence, stq_uop[13].is_amo) node _stq_amos_T_14 = or(stq_uop[14].is_fence, stq_uop[14].is_amo) node _stq_amos_T_15 = or(stq_uop[15].is_fence, stq_uop[15].is_amo) node _stq_amos_T_16 = or(stq_uop[16].is_fence, stq_uop[16].is_amo) node _stq_amos_T_17 = or(stq_uop[17].is_fence, stq_uop[17].is_amo) node _stq_amos_T_18 = or(stq_uop[18].is_fence, stq_uop[18].is_amo) node _stq_amos_T_19 = or(stq_uop[19].is_fence, stq_uop[19].is_amo) node _stq_amos_T_20 = or(stq_uop[20].is_fence, stq_uop[20].is_amo) node _stq_amos_T_21 = or(stq_uop[21].is_fence, stq_uop[21].is_amo) node _stq_amos_T_22 = or(stq_uop[22].is_fence, stq_uop[22].is_amo) node _stq_amos_T_23 = or(stq_uop[23].is_fence, stq_uop[23].is_amo) wire stq_amos : UInt<1>[24] connect stq_amos[0], _stq_amos_T connect stq_amos[1], _stq_amos_T_1 connect stq_amos[2], _stq_amos_T_2 connect stq_amos[3], _stq_amos_T_3 connect stq_amos[4], _stq_amos_T_4 connect stq_amos[5], _stq_amos_T_5 connect stq_amos[6], _stq_amos_T_6 connect stq_amos[7], _stq_amos_T_7 connect stq_amos[8], _stq_amos_T_8 connect stq_amos[9], _stq_amos_T_9 connect stq_amos[10], _stq_amos_T_10 connect stq_amos[11], _stq_amos_T_11 connect stq_amos[12], _stq_amos_T_12 connect stq_amos[13], _stq_amos_T_13 connect stq_amos[14], _stq_amos_T_14 connect stq_amos[15], _stq_amos_T_15 connect stq_amos[16], _stq_amos_T_16 connect stq_amos[17], _stq_amos_T_17 connect stq_amos[18], _stq_amos_T_18 connect stq_amos[19], _stq_amos_T_19 connect stq_amos[20], _stq_amos_T_20 connect stq_amos[21], _stq_amos_T_21 connect stq_amos[22], _stq_amos_T_22 connect stq_amos[23], _stq_amos_T_23 node has_older_amo_lo_lo_lo_hi = cat(stq_amos[2], stq_amos[1]) node has_older_amo_lo_lo_lo = cat(has_older_amo_lo_lo_lo_hi, stq_amos[0]) node has_older_amo_lo_lo_hi_hi = cat(stq_amos[5], stq_amos[4]) node has_older_amo_lo_lo_hi = cat(has_older_amo_lo_lo_hi_hi, stq_amos[3]) node has_older_amo_lo_lo = cat(has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo) node has_older_amo_lo_hi_lo_hi = cat(stq_amos[8], stq_amos[7]) node has_older_amo_lo_hi_lo = cat(has_older_amo_lo_hi_lo_hi, stq_amos[6]) node has_older_amo_lo_hi_hi_hi = cat(stq_amos[11], stq_amos[10]) node has_older_amo_lo_hi_hi = cat(has_older_amo_lo_hi_hi_hi, stq_amos[9]) node has_older_amo_lo_hi = cat(has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo) node has_older_amo_lo = cat(has_older_amo_lo_hi, has_older_amo_lo_lo) node has_older_amo_hi_lo_lo_hi = cat(stq_amos[14], stq_amos[13]) node has_older_amo_hi_lo_lo = cat(has_older_amo_hi_lo_lo_hi, stq_amos[12]) node has_older_amo_hi_lo_hi_hi = cat(stq_amos[17], stq_amos[16]) node has_older_amo_hi_lo_hi = cat(has_older_amo_hi_lo_hi_hi, stq_amos[15]) node has_older_amo_hi_lo = cat(has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo) node has_older_amo_hi_hi_lo_hi = cat(stq_amos[20], stq_amos[19]) node has_older_amo_hi_hi_lo = cat(has_older_amo_hi_hi_lo_hi, stq_amos[18]) node has_older_amo_hi_hi_hi_hi = cat(stq_amos[23], stq_amos[22]) node has_older_amo_hi_hi_hi = cat(has_older_amo_hi_hi_hi_hi, stq_amos[21]) node has_older_amo_hi_hi = cat(has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo) node has_older_amo_hi = cat(has_older_amo_hi_hi, has_older_amo_hi_lo) node _has_older_amo_T = cat(has_older_amo_hi, has_older_amo_lo) node _has_older_amo_T_1 = and(_has_older_amo_T, lcam_st_dep_mask[0]) node has_older_amo = neq(_has_older_amo_T_1, UInt<1>(0h0)) node _T_1624 = neq(ldst_addr_matches[0], UInt<1>(0h0)) node _T_1625 = or(has_older_amo, _T_1624) node _T_1626 = and(do_ld_search[0], _T_1625) when _T_1626 : node _T_1627 = eq(s0_kills[0], UInt<1>(0h0)) node _T_1628 = and(dmem_req_fire[0], _T_1627) reg REG_26 : UInt<1>, clock connect REG_26, _T_1628 node _T_1629 = eq(fired_load_agen[0], UInt<1>(0h0)) node _T_1630 = and(REG_26, _T_1629) when _T_1630 : connect io.dmem.s1_kill[0], UInt<1>(0h1) node _T_1631 = or(lcam_ldq_idx[0], UInt<5>(0h0)) node _T_1632 = bits(_T_1631, 4, 0) connect s1_set_execute[_T_1632], UInt<1>(0h0) when has_older_amo : connect kill_forward[0], UInt<1>(0h1) when s1_set_execute[0] : connect ldq_executed[0], UInt<1>(0h1) when s1_set_execute[1] : connect ldq_executed[1], UInt<1>(0h1) when s1_set_execute[2] : connect ldq_executed[2], UInt<1>(0h1) when s1_set_execute[3] : connect ldq_executed[3], UInt<1>(0h1) when s1_set_execute[4] : connect ldq_executed[4], UInt<1>(0h1) when s1_set_execute[5] : connect ldq_executed[5], UInt<1>(0h1) when s1_set_execute[6] : connect ldq_executed[6], UInt<1>(0h1) when s1_set_execute[7] : connect ldq_executed[7], UInt<1>(0h1) when s1_set_execute[8] : connect ldq_executed[8], UInt<1>(0h1) when s1_set_execute[9] : connect ldq_executed[9], UInt<1>(0h1) when s1_set_execute[10] : connect ldq_executed[10], UInt<1>(0h1) when s1_set_execute[11] : connect ldq_executed[11], UInt<1>(0h1) when s1_set_execute[12] : connect ldq_executed[12], UInt<1>(0h1) when s1_set_execute[13] : connect ldq_executed[13], UInt<1>(0h1) when s1_set_execute[14] : connect ldq_executed[14], UInt<1>(0h1) when s1_set_execute[15] : connect ldq_executed[15], UInt<1>(0h1) when s1_set_execute[16] : connect ldq_executed[16], UInt<1>(0h1) when s1_set_execute[17] : connect ldq_executed[17], UInt<1>(0h1) when s1_set_execute[18] : connect ldq_executed[18], UInt<1>(0h1) when s1_set_execute[19] : connect ldq_executed[19], UInt<1>(0h1) when s1_set_execute[20] : connect ldq_executed[20], UInt<1>(0h1) when s1_set_execute[21] : connect ldq_executed[21], UInt<1>(0h1) when s1_set_execute[22] : connect ldq_executed[22], UInt<1>(0h1) when s1_set_execute[23] : connect ldq_executed[23], UInt<1>(0h1) inst logic of ForwardingAgeLogic connect logic.clock, clock connect logic.reset, reset connect logic.io.matches, ldst_addr_matches[0] connect logic.io.youngest, lcam_uop[0].stq_idx inst logic_1 of ForwardingAgeLogic_1 connect logic_1.clock, clock connect logic_1.reset, reset connect logic_1.io.matches, ldst_forward_matches[0] connect logic_1.io.youngest, lcam_uop[0].stq_idx connect wb_ldst_forward_stq_idx[0], logic_1.io.found_idx node _wb_ldst_forward_valid_0_T = eq(logic.io.found_idx, logic_1.io.found_idx) node _wb_ldst_forward_valid_0_T_1 = and(_wb_ldst_forward_valid_0_T, logic.io.found) node _wb_ldst_forward_valid_0_T_2 = and(_wb_ldst_forward_valid_0_T_1, logic_1.io.found) node _wb_ldst_forward_valid_0_T_3 = eq(kill_forward[0], UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_4 = and(can_forward[0], _wb_ldst_forward_valid_0_T_3) node _wb_ldst_forward_valid_0_T_5 = and(_wb_ldst_forward_valid_0_T_4, do_ld_search[0]) reg wb_ldst_forward_valid_0_REG : UInt<1>, clock connect wb_ldst_forward_valid_0_REG, _wb_ldst_forward_valid_0_T_5 node _wb_ldst_forward_valid_0_T_6 = and(_wb_ldst_forward_valid_0_T_2, wb_ldst_forward_valid_0_REG) node _wb_ldst_forward_valid_0_T_7 = and(io.core.brupdate.b1.mispredict_mask, lcam_uop[0].br_mask) node _wb_ldst_forward_valid_0_T_8 = neq(_wb_ldst_forward_valid_0_T_7, UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_9 = or(_wb_ldst_forward_valid_0_T_8, io.core.exception) reg wb_ldst_forward_valid_0_REG_1 : UInt<1>, clock connect wb_ldst_forward_valid_0_REG_1, _wb_ldst_forward_valid_0_T_9 node _wb_ldst_forward_valid_0_T_10 = eq(wb_ldst_forward_valid_0_REG_1, UInt<1>(0h0)) node _wb_ldst_forward_valid_0_T_11 = and(_wb_ldst_forward_valid_0_T_6, _wb_ldst_forward_valid_0_T_10) connect wb_ldst_forward_valid[0], _wb_ldst_forward_valid_0_T_11 node _T_1633 = neq(ldst_addr_matches[0], UInt<1>(0h0)) reg REG_27 : UInt<1>, clock connect REG_27, _T_1633 node _T_1634 = eq(wb_ldst_forward_valid[0], UInt<1>(0h0)) node _T_1635 = and(REG_27, _T_1634) when _T_1635 : connect block_load_wakeup, UInt<1>(0h1) reg store_blocked_counter : UInt<4>, clock node _T_1636 = or(will_fire_store_commit_fast[0], will_fire_store_commit_slow[0]) node _T_1637 = eq(can_fire_store_commit_slow[0], UInt<1>(0h0)) node _T_1638 = or(_T_1636, _T_1637) when _T_1638 : connect store_blocked_counter, UInt<1>(0h0) else : node _T_1639 = or(will_fire_store_commit_slow[0], will_fire_store_commit_fast[0]) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) node _T_1641 = and(can_fire_store_commit_slow[0], _T_1640) when _T_1641 : node _store_blocked_counter_T = eq(store_blocked_counter, UInt<4>(0hf)) node _store_blocked_counter_T_1 = add(store_blocked_counter, UInt<1>(0h1)) node _store_blocked_counter_T_2 = tail(_store_blocked_counter_T_1, 1) node _store_blocked_counter_T_3 = mux(_store_blocked_counter_T, UInt<4>(0hf), _store_blocked_counter_T_2) connect store_blocked_counter, _store_blocked_counter_T_3 node _T_1642 = eq(store_blocked_counter, UInt<4>(0hf)) when _T_1642 : connect block_load_wakeup, UInt<1>(0h1) node _mem_stld_forward_stq_idx_T = bits(stld_prs2_matches[0], 0, 0) node _mem_stld_forward_stq_idx_T_1 = bits(stld_prs2_matches[0], 1, 1) node _mem_stld_forward_stq_idx_T_2 = bits(stld_prs2_matches[0], 2, 2) node _mem_stld_forward_stq_idx_T_3 = bits(stld_prs2_matches[0], 3, 3) node _mem_stld_forward_stq_idx_T_4 = bits(stld_prs2_matches[0], 4, 4) node _mem_stld_forward_stq_idx_T_5 = bits(stld_prs2_matches[0], 5, 5) node _mem_stld_forward_stq_idx_T_6 = bits(stld_prs2_matches[0], 6, 6) node _mem_stld_forward_stq_idx_T_7 = bits(stld_prs2_matches[0], 7, 7) node _mem_stld_forward_stq_idx_T_8 = bits(stld_prs2_matches[0], 8, 8) node _mem_stld_forward_stq_idx_T_9 = bits(stld_prs2_matches[0], 9, 9) node _mem_stld_forward_stq_idx_T_10 = bits(stld_prs2_matches[0], 10, 10) node _mem_stld_forward_stq_idx_T_11 = bits(stld_prs2_matches[0], 11, 11) node _mem_stld_forward_stq_idx_T_12 = bits(stld_prs2_matches[0], 12, 12) node _mem_stld_forward_stq_idx_T_13 = bits(stld_prs2_matches[0], 13, 13) node _mem_stld_forward_stq_idx_T_14 = bits(stld_prs2_matches[0], 14, 14) node _mem_stld_forward_stq_idx_T_15 = bits(stld_prs2_matches[0], 15, 15) node _mem_stld_forward_stq_idx_T_16 = bits(stld_prs2_matches[0], 16, 16) node _mem_stld_forward_stq_idx_T_17 = bits(stld_prs2_matches[0], 17, 17) node _mem_stld_forward_stq_idx_T_18 = bits(stld_prs2_matches[0], 18, 18) node _mem_stld_forward_stq_idx_T_19 = bits(stld_prs2_matches[0], 19, 19) node _mem_stld_forward_stq_idx_T_20 = bits(stld_prs2_matches[0], 20, 20) node _mem_stld_forward_stq_idx_T_21 = bits(stld_prs2_matches[0], 21, 21) node _mem_stld_forward_stq_idx_T_22 = bits(stld_prs2_matches[0], 22, 22) node _mem_stld_forward_stq_idx_T_23 = bits(stld_prs2_matches[0], 23, 23) node _mem_stld_forward_stq_idx_temp_vec_T = geq(UInt<1>(0h0), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_0 = and(_mem_stld_forward_stq_idx_T, _mem_stld_forward_stq_idx_temp_vec_T) node _mem_stld_forward_stq_idx_temp_vec_T_1 = geq(UInt<1>(0h1), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_1 = and(_mem_stld_forward_stq_idx_T_1, _mem_stld_forward_stq_idx_temp_vec_T_1) node _mem_stld_forward_stq_idx_temp_vec_T_2 = geq(UInt<2>(0h2), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_2 = and(_mem_stld_forward_stq_idx_T_2, _mem_stld_forward_stq_idx_temp_vec_T_2) node _mem_stld_forward_stq_idx_temp_vec_T_3 = geq(UInt<2>(0h3), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_3 = and(_mem_stld_forward_stq_idx_T_3, _mem_stld_forward_stq_idx_temp_vec_T_3) node _mem_stld_forward_stq_idx_temp_vec_T_4 = geq(UInt<3>(0h4), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_4 = and(_mem_stld_forward_stq_idx_T_4, _mem_stld_forward_stq_idx_temp_vec_T_4) node _mem_stld_forward_stq_idx_temp_vec_T_5 = geq(UInt<3>(0h5), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_5 = and(_mem_stld_forward_stq_idx_T_5, _mem_stld_forward_stq_idx_temp_vec_T_5) node _mem_stld_forward_stq_idx_temp_vec_T_6 = geq(UInt<3>(0h6), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_6 = and(_mem_stld_forward_stq_idx_T_6, _mem_stld_forward_stq_idx_temp_vec_T_6) node _mem_stld_forward_stq_idx_temp_vec_T_7 = geq(UInt<3>(0h7), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_7 = and(_mem_stld_forward_stq_idx_T_7, _mem_stld_forward_stq_idx_temp_vec_T_7) node _mem_stld_forward_stq_idx_temp_vec_T_8 = geq(UInt<4>(0h8), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_8 = and(_mem_stld_forward_stq_idx_T_8, _mem_stld_forward_stq_idx_temp_vec_T_8) node _mem_stld_forward_stq_idx_temp_vec_T_9 = geq(UInt<4>(0h9), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_9 = and(_mem_stld_forward_stq_idx_T_9, _mem_stld_forward_stq_idx_temp_vec_T_9) node _mem_stld_forward_stq_idx_temp_vec_T_10 = geq(UInt<4>(0ha), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_10 = and(_mem_stld_forward_stq_idx_T_10, _mem_stld_forward_stq_idx_temp_vec_T_10) node _mem_stld_forward_stq_idx_temp_vec_T_11 = geq(UInt<4>(0hb), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_11 = and(_mem_stld_forward_stq_idx_T_11, _mem_stld_forward_stq_idx_temp_vec_T_11) node _mem_stld_forward_stq_idx_temp_vec_T_12 = geq(UInt<4>(0hc), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_12 = and(_mem_stld_forward_stq_idx_T_12, _mem_stld_forward_stq_idx_temp_vec_T_12) node _mem_stld_forward_stq_idx_temp_vec_T_13 = geq(UInt<4>(0hd), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_13 = and(_mem_stld_forward_stq_idx_T_13, _mem_stld_forward_stq_idx_temp_vec_T_13) node _mem_stld_forward_stq_idx_temp_vec_T_14 = geq(UInt<4>(0he), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_14 = and(_mem_stld_forward_stq_idx_T_14, _mem_stld_forward_stq_idx_temp_vec_T_14) node _mem_stld_forward_stq_idx_temp_vec_T_15 = geq(UInt<4>(0hf), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_15 = and(_mem_stld_forward_stq_idx_T_15, _mem_stld_forward_stq_idx_temp_vec_T_15) node _mem_stld_forward_stq_idx_temp_vec_T_16 = geq(UInt<5>(0h10), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_16 = and(_mem_stld_forward_stq_idx_T_16, _mem_stld_forward_stq_idx_temp_vec_T_16) node _mem_stld_forward_stq_idx_temp_vec_T_17 = geq(UInt<5>(0h11), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_17 = and(_mem_stld_forward_stq_idx_T_17, _mem_stld_forward_stq_idx_temp_vec_T_17) node _mem_stld_forward_stq_idx_temp_vec_T_18 = geq(UInt<5>(0h12), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_18 = and(_mem_stld_forward_stq_idx_T_18, _mem_stld_forward_stq_idx_temp_vec_T_18) node _mem_stld_forward_stq_idx_temp_vec_T_19 = geq(UInt<5>(0h13), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_19 = and(_mem_stld_forward_stq_idx_T_19, _mem_stld_forward_stq_idx_temp_vec_T_19) node _mem_stld_forward_stq_idx_temp_vec_T_20 = geq(UInt<5>(0h14), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_20 = and(_mem_stld_forward_stq_idx_T_20, _mem_stld_forward_stq_idx_temp_vec_T_20) node _mem_stld_forward_stq_idx_temp_vec_T_21 = geq(UInt<5>(0h15), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_21 = and(_mem_stld_forward_stq_idx_T_21, _mem_stld_forward_stq_idx_temp_vec_T_21) node _mem_stld_forward_stq_idx_temp_vec_T_22 = geq(UInt<5>(0h16), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_22 = and(_mem_stld_forward_stq_idx_T_22, _mem_stld_forward_stq_idx_temp_vec_T_22) node _mem_stld_forward_stq_idx_temp_vec_T_23 = geq(UInt<5>(0h17), lcam_uop[0].stq_idx) node mem_stld_forward_stq_idx_temp_vec_23 = and(_mem_stld_forward_stq_idx_T_23, _mem_stld_forward_stq_idx_temp_vec_T_23) node _mem_stld_forward_stq_idx_idx_T = mux(_mem_stld_forward_stq_idx_T_22, UInt<6>(0h36), UInt<6>(0h37)) node _mem_stld_forward_stq_idx_idx_T_1 = mux(_mem_stld_forward_stq_idx_T_21, UInt<6>(0h35), _mem_stld_forward_stq_idx_idx_T) node _mem_stld_forward_stq_idx_idx_T_2 = mux(_mem_stld_forward_stq_idx_T_20, UInt<6>(0h34), _mem_stld_forward_stq_idx_idx_T_1) node _mem_stld_forward_stq_idx_idx_T_3 = mux(_mem_stld_forward_stq_idx_T_19, UInt<6>(0h33), _mem_stld_forward_stq_idx_idx_T_2) node _mem_stld_forward_stq_idx_idx_T_4 = mux(_mem_stld_forward_stq_idx_T_18, UInt<6>(0h32), _mem_stld_forward_stq_idx_idx_T_3) node _mem_stld_forward_stq_idx_idx_T_5 = mux(_mem_stld_forward_stq_idx_T_17, UInt<6>(0h31), _mem_stld_forward_stq_idx_idx_T_4) node _mem_stld_forward_stq_idx_idx_T_6 = mux(_mem_stld_forward_stq_idx_T_16, UInt<6>(0h30), _mem_stld_forward_stq_idx_idx_T_5) node _mem_stld_forward_stq_idx_idx_T_7 = mux(_mem_stld_forward_stq_idx_T_15, UInt<6>(0h2f), _mem_stld_forward_stq_idx_idx_T_6) node _mem_stld_forward_stq_idx_idx_T_8 = mux(_mem_stld_forward_stq_idx_T_14, UInt<6>(0h2e), _mem_stld_forward_stq_idx_idx_T_7) node _mem_stld_forward_stq_idx_idx_T_9 = mux(_mem_stld_forward_stq_idx_T_13, UInt<6>(0h2d), _mem_stld_forward_stq_idx_idx_T_8) node _mem_stld_forward_stq_idx_idx_T_10 = mux(_mem_stld_forward_stq_idx_T_12, UInt<6>(0h2c), _mem_stld_forward_stq_idx_idx_T_9) node _mem_stld_forward_stq_idx_idx_T_11 = mux(_mem_stld_forward_stq_idx_T_11, UInt<6>(0h2b), _mem_stld_forward_stq_idx_idx_T_10) node _mem_stld_forward_stq_idx_idx_T_12 = mux(_mem_stld_forward_stq_idx_T_10, UInt<6>(0h2a), _mem_stld_forward_stq_idx_idx_T_11) node _mem_stld_forward_stq_idx_idx_T_13 = mux(_mem_stld_forward_stq_idx_T_9, UInt<6>(0h29), _mem_stld_forward_stq_idx_idx_T_12) node _mem_stld_forward_stq_idx_idx_T_14 = mux(_mem_stld_forward_stq_idx_T_8, UInt<6>(0h28), _mem_stld_forward_stq_idx_idx_T_13) node _mem_stld_forward_stq_idx_idx_T_15 = mux(_mem_stld_forward_stq_idx_T_7, UInt<6>(0h27), _mem_stld_forward_stq_idx_idx_T_14) node _mem_stld_forward_stq_idx_idx_T_16 = mux(_mem_stld_forward_stq_idx_T_6, UInt<6>(0h26), _mem_stld_forward_stq_idx_idx_T_15) node _mem_stld_forward_stq_idx_idx_T_17 = mux(_mem_stld_forward_stq_idx_T_5, UInt<6>(0h25), _mem_stld_forward_stq_idx_idx_T_16) node _mem_stld_forward_stq_idx_idx_T_18 = mux(_mem_stld_forward_stq_idx_T_4, UInt<6>(0h24), _mem_stld_forward_stq_idx_idx_T_17) node _mem_stld_forward_stq_idx_idx_T_19 = mux(_mem_stld_forward_stq_idx_T_3, UInt<6>(0h23), _mem_stld_forward_stq_idx_idx_T_18) node _mem_stld_forward_stq_idx_idx_T_20 = mux(_mem_stld_forward_stq_idx_T_2, UInt<6>(0h22), _mem_stld_forward_stq_idx_idx_T_19) node _mem_stld_forward_stq_idx_idx_T_21 = mux(_mem_stld_forward_stq_idx_T_1, UInt<6>(0h21), _mem_stld_forward_stq_idx_idx_T_20) node _mem_stld_forward_stq_idx_idx_T_22 = mux(_mem_stld_forward_stq_idx_T, UInt<6>(0h20), _mem_stld_forward_stq_idx_idx_T_21) node _mem_stld_forward_stq_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _mem_stld_forward_stq_idx_idx_T_22) node _mem_stld_forward_stq_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _mem_stld_forward_stq_idx_idx_T_23) node _mem_stld_forward_stq_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _mem_stld_forward_stq_idx_idx_T_24) node _mem_stld_forward_stq_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _mem_stld_forward_stq_idx_idx_T_25) node _mem_stld_forward_stq_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _mem_stld_forward_stq_idx_idx_T_26) node _mem_stld_forward_stq_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _mem_stld_forward_stq_idx_idx_T_27) node _mem_stld_forward_stq_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _mem_stld_forward_stq_idx_idx_T_28) node _mem_stld_forward_stq_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _mem_stld_forward_stq_idx_idx_T_29) node _mem_stld_forward_stq_idx_idx_T_31 = mux(mem_stld_forward_stq_idx_temp_vec_23, UInt<5>(0h17), _mem_stld_forward_stq_idx_idx_T_30) node _mem_stld_forward_stq_idx_idx_T_32 = mux(mem_stld_forward_stq_idx_temp_vec_22, UInt<5>(0h16), _mem_stld_forward_stq_idx_idx_T_31) node _mem_stld_forward_stq_idx_idx_T_33 = mux(mem_stld_forward_stq_idx_temp_vec_21, UInt<5>(0h15), _mem_stld_forward_stq_idx_idx_T_32) node _mem_stld_forward_stq_idx_idx_T_34 = mux(mem_stld_forward_stq_idx_temp_vec_20, UInt<5>(0h14), _mem_stld_forward_stq_idx_idx_T_33) node _mem_stld_forward_stq_idx_idx_T_35 = mux(mem_stld_forward_stq_idx_temp_vec_19, UInt<5>(0h13), _mem_stld_forward_stq_idx_idx_T_34) node _mem_stld_forward_stq_idx_idx_T_36 = mux(mem_stld_forward_stq_idx_temp_vec_18, UInt<5>(0h12), _mem_stld_forward_stq_idx_idx_T_35) node _mem_stld_forward_stq_idx_idx_T_37 = mux(mem_stld_forward_stq_idx_temp_vec_17, UInt<5>(0h11), _mem_stld_forward_stq_idx_idx_T_36) node _mem_stld_forward_stq_idx_idx_T_38 = mux(mem_stld_forward_stq_idx_temp_vec_16, UInt<5>(0h10), _mem_stld_forward_stq_idx_idx_T_37) node _mem_stld_forward_stq_idx_idx_T_39 = mux(mem_stld_forward_stq_idx_temp_vec_15, UInt<4>(0hf), _mem_stld_forward_stq_idx_idx_T_38) node _mem_stld_forward_stq_idx_idx_T_40 = mux(mem_stld_forward_stq_idx_temp_vec_14, UInt<4>(0he), _mem_stld_forward_stq_idx_idx_T_39) node _mem_stld_forward_stq_idx_idx_T_41 = mux(mem_stld_forward_stq_idx_temp_vec_13, UInt<4>(0hd), _mem_stld_forward_stq_idx_idx_T_40) node _mem_stld_forward_stq_idx_idx_T_42 = mux(mem_stld_forward_stq_idx_temp_vec_12, UInt<4>(0hc), _mem_stld_forward_stq_idx_idx_T_41) node _mem_stld_forward_stq_idx_idx_T_43 = mux(mem_stld_forward_stq_idx_temp_vec_11, UInt<4>(0hb), _mem_stld_forward_stq_idx_idx_T_42) node _mem_stld_forward_stq_idx_idx_T_44 = mux(mem_stld_forward_stq_idx_temp_vec_10, UInt<4>(0ha), _mem_stld_forward_stq_idx_idx_T_43) node _mem_stld_forward_stq_idx_idx_T_45 = mux(mem_stld_forward_stq_idx_temp_vec_9, UInt<4>(0h9), _mem_stld_forward_stq_idx_idx_T_44) node _mem_stld_forward_stq_idx_idx_T_46 = mux(mem_stld_forward_stq_idx_temp_vec_8, UInt<4>(0h8), _mem_stld_forward_stq_idx_idx_T_45) node _mem_stld_forward_stq_idx_idx_T_47 = mux(mem_stld_forward_stq_idx_temp_vec_7, UInt<3>(0h7), _mem_stld_forward_stq_idx_idx_T_46) node _mem_stld_forward_stq_idx_idx_T_48 = mux(mem_stld_forward_stq_idx_temp_vec_6, UInt<3>(0h6), _mem_stld_forward_stq_idx_idx_T_47) node _mem_stld_forward_stq_idx_idx_T_49 = mux(mem_stld_forward_stq_idx_temp_vec_5, UInt<3>(0h5), _mem_stld_forward_stq_idx_idx_T_48) node _mem_stld_forward_stq_idx_idx_T_50 = mux(mem_stld_forward_stq_idx_temp_vec_4, UInt<3>(0h4), _mem_stld_forward_stq_idx_idx_T_49) node _mem_stld_forward_stq_idx_idx_T_51 = mux(mem_stld_forward_stq_idx_temp_vec_3, UInt<2>(0h3), _mem_stld_forward_stq_idx_idx_T_50) node _mem_stld_forward_stq_idx_idx_T_52 = mux(mem_stld_forward_stq_idx_temp_vec_2, UInt<2>(0h2), _mem_stld_forward_stq_idx_idx_T_51) node _mem_stld_forward_stq_idx_idx_T_53 = mux(mem_stld_forward_stq_idx_temp_vec_1, UInt<1>(0h1), _mem_stld_forward_stq_idx_idx_T_52) node mem_stld_forward_stq_idx_idx = mux(mem_stld_forward_stq_idx_temp_vec_0, UInt<1>(0h0), _mem_stld_forward_stq_idx_idx_T_53) node _mem_stld_forward_stq_idx_T_24 = bits(mem_stld_forward_stq_idx_idx, 4, 0) wire mem_stld_forward_stq_idx : UInt<5>[1] connect mem_stld_forward_stq_idx[0], _mem_stld_forward_stq_idx_T_24 node _mem_stld_forward_valid_T = dshr(stld_prs2_matches[0], mem_stld_forward_stq_idx[0]) node _mem_stld_forward_valid_T_1 = bits(_mem_stld_forward_valid_T, 0, 0) node _mem_stld_forward_valid_T_2 = and(do_ld_search[0], _mem_stld_forward_valid_T_1) wire mem_stld_forward_valid : UInt<1>[1] connect mem_stld_forward_valid[0], _mem_stld_forward_valid_T_2 reg io_core_clr_unsafe_0_valid_REG : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG, do_st_search[0] node _io_core_clr_unsafe_0_valid_T = eq(io.dmem.nack[0].valid, UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_1 = eq(fired_load_agen[0], UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_2 = and(do_ld_search[0], _io_core_clr_unsafe_0_valid_T_1) node _io_core_clr_unsafe_0_valid_T_3 = eq(io.dmem.s1_kill[0], UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_4 = and(_io_core_clr_unsafe_0_valid_T_2, _io_core_clr_unsafe_0_valid_T_3) reg io_core_clr_unsafe_0_valid_REG_1 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_1, dmem_req_fire[0] node _io_core_clr_unsafe_0_valid_T_5 = and(_io_core_clr_unsafe_0_valid_T_4, io_core_clr_unsafe_0_valid_REG_1) reg io_core_clr_unsafe_0_valid_REG_2 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_2, _io_core_clr_unsafe_0_valid_T_5 node _io_core_clr_unsafe_0_valid_T_6 = and(_io_core_clr_unsafe_0_valid_T, io_core_clr_unsafe_0_valid_REG_2) node _io_core_clr_unsafe_0_valid_T_7 = or(io_core_clr_unsafe_0_valid_REG, _io_core_clr_unsafe_0_valid_T_6) reg io_core_clr_unsafe_0_valid_REG_3 : UInt<1>, clock connect io_core_clr_unsafe_0_valid_REG_3, failed_load node _io_core_clr_unsafe_0_valid_T_8 = eq(io_core_clr_unsafe_0_valid_REG_3, UInt<1>(0h0)) node _io_core_clr_unsafe_0_valid_T_9 = and(_io_core_clr_unsafe_0_valid_T_7, _io_core_clr_unsafe_0_valid_T_8) connect io.core.clr_unsafe[0].valid, _io_core_clr_unsafe_0_valid_T_9 reg io_core_clr_unsafe_0_bits_REG : UInt, clock connect io_core_clr_unsafe_0_bits_REG, lcam_uop[0].rob_idx connect io.core.clr_unsafe[0].bits, io_core_clr_unsafe_0_bits_REG node _l_idx_T = and(ldq_valid[0], ldq_order_fail[0]) node _l_idx_T_1 = and(ldq_valid[1], ldq_order_fail[1]) node _l_idx_T_2 = and(ldq_valid[2], ldq_order_fail[2]) node _l_idx_T_3 = and(ldq_valid[3], ldq_order_fail[3]) node _l_idx_T_4 = and(ldq_valid[4], ldq_order_fail[4]) node _l_idx_T_5 = and(ldq_valid[5], ldq_order_fail[5]) node _l_idx_T_6 = and(ldq_valid[6], ldq_order_fail[6]) node _l_idx_T_7 = and(ldq_valid[7], ldq_order_fail[7]) node _l_idx_T_8 = and(ldq_valid[8], ldq_order_fail[8]) node _l_idx_T_9 = and(ldq_valid[9], ldq_order_fail[9]) node _l_idx_T_10 = and(ldq_valid[10], ldq_order_fail[10]) node _l_idx_T_11 = and(ldq_valid[11], ldq_order_fail[11]) node _l_idx_T_12 = and(ldq_valid[12], ldq_order_fail[12]) node _l_idx_T_13 = and(ldq_valid[13], ldq_order_fail[13]) node _l_idx_T_14 = and(ldq_valid[14], ldq_order_fail[14]) node _l_idx_T_15 = and(ldq_valid[15], ldq_order_fail[15]) node _l_idx_T_16 = and(ldq_valid[16], ldq_order_fail[16]) node _l_idx_T_17 = and(ldq_valid[17], ldq_order_fail[17]) node _l_idx_T_18 = and(ldq_valid[18], ldq_order_fail[18]) node _l_idx_T_19 = and(ldq_valid[19], ldq_order_fail[19]) node _l_idx_T_20 = and(ldq_valid[20], ldq_order_fail[20]) node _l_idx_T_21 = and(ldq_valid[21], ldq_order_fail[21]) node _l_idx_T_22 = and(ldq_valid[22], ldq_order_fail[22]) node _l_idx_T_23 = and(ldq_valid[23], ldq_order_fail[23]) node _l_idx_temp_vec_T = geq(UInt<1>(0h0), ldq_head) node l_idx_temp_vec_0 = and(_l_idx_T, _l_idx_temp_vec_T) node _l_idx_temp_vec_T_1 = geq(UInt<1>(0h1), ldq_head) node l_idx_temp_vec_1 = and(_l_idx_T_1, _l_idx_temp_vec_T_1) node _l_idx_temp_vec_T_2 = geq(UInt<2>(0h2), ldq_head) node l_idx_temp_vec_2 = and(_l_idx_T_2, _l_idx_temp_vec_T_2) node _l_idx_temp_vec_T_3 = geq(UInt<2>(0h3), ldq_head) node l_idx_temp_vec_3 = and(_l_idx_T_3, _l_idx_temp_vec_T_3) node _l_idx_temp_vec_T_4 = geq(UInt<3>(0h4), ldq_head) node l_idx_temp_vec_4 = and(_l_idx_T_4, _l_idx_temp_vec_T_4) node _l_idx_temp_vec_T_5 = geq(UInt<3>(0h5), ldq_head) node l_idx_temp_vec_5 = and(_l_idx_T_5, _l_idx_temp_vec_T_5) node _l_idx_temp_vec_T_6 = geq(UInt<3>(0h6), ldq_head) node l_idx_temp_vec_6 = and(_l_idx_T_6, _l_idx_temp_vec_T_6) node _l_idx_temp_vec_T_7 = geq(UInt<3>(0h7), ldq_head) node l_idx_temp_vec_7 = and(_l_idx_T_7, _l_idx_temp_vec_T_7) node _l_idx_temp_vec_T_8 = geq(UInt<4>(0h8), ldq_head) node l_idx_temp_vec_8 = and(_l_idx_T_8, _l_idx_temp_vec_T_8) node _l_idx_temp_vec_T_9 = geq(UInt<4>(0h9), ldq_head) node l_idx_temp_vec_9 = and(_l_idx_T_9, _l_idx_temp_vec_T_9) node _l_idx_temp_vec_T_10 = geq(UInt<4>(0ha), ldq_head) node l_idx_temp_vec_10 = and(_l_idx_T_10, _l_idx_temp_vec_T_10) node _l_idx_temp_vec_T_11 = geq(UInt<4>(0hb), ldq_head) node l_idx_temp_vec_11 = and(_l_idx_T_11, _l_idx_temp_vec_T_11) node _l_idx_temp_vec_T_12 = geq(UInt<4>(0hc), ldq_head) node l_idx_temp_vec_12 = and(_l_idx_T_12, _l_idx_temp_vec_T_12) node _l_idx_temp_vec_T_13 = geq(UInt<4>(0hd), ldq_head) node l_idx_temp_vec_13 = and(_l_idx_T_13, _l_idx_temp_vec_T_13) node _l_idx_temp_vec_T_14 = geq(UInt<4>(0he), ldq_head) node l_idx_temp_vec_14 = and(_l_idx_T_14, _l_idx_temp_vec_T_14) node _l_idx_temp_vec_T_15 = geq(UInt<4>(0hf), ldq_head) node l_idx_temp_vec_15 = and(_l_idx_T_15, _l_idx_temp_vec_T_15) node _l_idx_temp_vec_T_16 = geq(UInt<5>(0h10), ldq_head) node l_idx_temp_vec_16 = and(_l_idx_T_16, _l_idx_temp_vec_T_16) node _l_idx_temp_vec_T_17 = geq(UInt<5>(0h11), ldq_head) node l_idx_temp_vec_17 = and(_l_idx_T_17, _l_idx_temp_vec_T_17) node _l_idx_temp_vec_T_18 = geq(UInt<5>(0h12), ldq_head) node l_idx_temp_vec_18 = and(_l_idx_T_18, _l_idx_temp_vec_T_18) node _l_idx_temp_vec_T_19 = geq(UInt<5>(0h13), ldq_head) node l_idx_temp_vec_19 = and(_l_idx_T_19, _l_idx_temp_vec_T_19) node _l_idx_temp_vec_T_20 = geq(UInt<5>(0h14), ldq_head) node l_idx_temp_vec_20 = and(_l_idx_T_20, _l_idx_temp_vec_T_20) node _l_idx_temp_vec_T_21 = geq(UInt<5>(0h15), ldq_head) node l_idx_temp_vec_21 = and(_l_idx_T_21, _l_idx_temp_vec_T_21) node _l_idx_temp_vec_T_22 = geq(UInt<5>(0h16), ldq_head) node l_idx_temp_vec_22 = and(_l_idx_T_22, _l_idx_temp_vec_T_22) node _l_idx_temp_vec_T_23 = geq(UInt<5>(0h17), ldq_head) node l_idx_temp_vec_23 = and(_l_idx_T_23, _l_idx_temp_vec_T_23) node _l_idx_idx_T = mux(_l_idx_T_22, UInt<6>(0h36), UInt<6>(0h37)) node _l_idx_idx_T_1 = mux(_l_idx_T_21, UInt<6>(0h35), _l_idx_idx_T) node _l_idx_idx_T_2 = mux(_l_idx_T_20, UInt<6>(0h34), _l_idx_idx_T_1) node _l_idx_idx_T_3 = mux(_l_idx_T_19, UInt<6>(0h33), _l_idx_idx_T_2) node _l_idx_idx_T_4 = mux(_l_idx_T_18, UInt<6>(0h32), _l_idx_idx_T_3) node _l_idx_idx_T_5 = mux(_l_idx_T_17, UInt<6>(0h31), _l_idx_idx_T_4) node _l_idx_idx_T_6 = mux(_l_idx_T_16, UInt<6>(0h30), _l_idx_idx_T_5) node _l_idx_idx_T_7 = mux(_l_idx_T_15, UInt<6>(0h2f), _l_idx_idx_T_6) node _l_idx_idx_T_8 = mux(_l_idx_T_14, UInt<6>(0h2e), _l_idx_idx_T_7) node _l_idx_idx_T_9 = mux(_l_idx_T_13, UInt<6>(0h2d), _l_idx_idx_T_8) node _l_idx_idx_T_10 = mux(_l_idx_T_12, UInt<6>(0h2c), _l_idx_idx_T_9) node _l_idx_idx_T_11 = mux(_l_idx_T_11, UInt<6>(0h2b), _l_idx_idx_T_10) node _l_idx_idx_T_12 = mux(_l_idx_T_10, UInt<6>(0h2a), _l_idx_idx_T_11) node _l_idx_idx_T_13 = mux(_l_idx_T_9, UInt<6>(0h29), _l_idx_idx_T_12) node _l_idx_idx_T_14 = mux(_l_idx_T_8, UInt<6>(0h28), _l_idx_idx_T_13) node _l_idx_idx_T_15 = mux(_l_idx_T_7, UInt<6>(0h27), _l_idx_idx_T_14) node _l_idx_idx_T_16 = mux(_l_idx_T_6, UInt<6>(0h26), _l_idx_idx_T_15) node _l_idx_idx_T_17 = mux(_l_idx_T_5, UInt<6>(0h25), _l_idx_idx_T_16) node _l_idx_idx_T_18 = mux(_l_idx_T_4, UInt<6>(0h24), _l_idx_idx_T_17) node _l_idx_idx_T_19 = mux(_l_idx_T_3, UInt<6>(0h23), _l_idx_idx_T_18) node _l_idx_idx_T_20 = mux(_l_idx_T_2, UInt<6>(0h22), _l_idx_idx_T_19) node _l_idx_idx_T_21 = mux(_l_idx_T_1, UInt<6>(0h21), _l_idx_idx_T_20) node _l_idx_idx_T_22 = mux(_l_idx_T, UInt<6>(0h20), _l_idx_idx_T_21) node _l_idx_idx_T_23 = mux(UInt<1>(0h0), UInt<5>(0h1f), _l_idx_idx_T_22) node _l_idx_idx_T_24 = mux(UInt<1>(0h0), UInt<5>(0h1e), _l_idx_idx_T_23) node _l_idx_idx_T_25 = mux(UInt<1>(0h0), UInt<5>(0h1d), _l_idx_idx_T_24) node _l_idx_idx_T_26 = mux(UInt<1>(0h0), UInt<5>(0h1c), _l_idx_idx_T_25) node _l_idx_idx_T_27 = mux(UInt<1>(0h0), UInt<5>(0h1b), _l_idx_idx_T_26) node _l_idx_idx_T_28 = mux(UInt<1>(0h0), UInt<5>(0h1a), _l_idx_idx_T_27) node _l_idx_idx_T_29 = mux(UInt<1>(0h0), UInt<5>(0h19), _l_idx_idx_T_28) node _l_idx_idx_T_30 = mux(UInt<1>(0h0), UInt<5>(0h18), _l_idx_idx_T_29) node _l_idx_idx_T_31 = mux(l_idx_temp_vec_23, UInt<5>(0h17), _l_idx_idx_T_30) node _l_idx_idx_T_32 = mux(l_idx_temp_vec_22, UInt<5>(0h16), _l_idx_idx_T_31) node _l_idx_idx_T_33 = mux(l_idx_temp_vec_21, UInt<5>(0h15), _l_idx_idx_T_32) node _l_idx_idx_T_34 = mux(l_idx_temp_vec_20, UInt<5>(0h14), _l_idx_idx_T_33) node _l_idx_idx_T_35 = mux(l_idx_temp_vec_19, UInt<5>(0h13), _l_idx_idx_T_34) node _l_idx_idx_T_36 = mux(l_idx_temp_vec_18, UInt<5>(0h12), _l_idx_idx_T_35) node _l_idx_idx_T_37 = mux(l_idx_temp_vec_17, UInt<5>(0h11), _l_idx_idx_T_36) node _l_idx_idx_T_38 = mux(l_idx_temp_vec_16, UInt<5>(0h10), _l_idx_idx_T_37) node _l_idx_idx_T_39 = mux(l_idx_temp_vec_15, UInt<4>(0hf), _l_idx_idx_T_38) node _l_idx_idx_T_40 = mux(l_idx_temp_vec_14, UInt<4>(0he), _l_idx_idx_T_39) node _l_idx_idx_T_41 = mux(l_idx_temp_vec_13, UInt<4>(0hd), _l_idx_idx_T_40) node _l_idx_idx_T_42 = mux(l_idx_temp_vec_12, UInt<4>(0hc), _l_idx_idx_T_41) node _l_idx_idx_T_43 = mux(l_idx_temp_vec_11, UInt<4>(0hb), _l_idx_idx_T_42) node _l_idx_idx_T_44 = mux(l_idx_temp_vec_10, UInt<4>(0ha), _l_idx_idx_T_43) node _l_idx_idx_T_45 = mux(l_idx_temp_vec_9, UInt<4>(0h9), _l_idx_idx_T_44) node _l_idx_idx_T_46 = mux(l_idx_temp_vec_8, UInt<4>(0h8), _l_idx_idx_T_45) node _l_idx_idx_T_47 = mux(l_idx_temp_vec_7, UInt<3>(0h7), _l_idx_idx_T_46) node _l_idx_idx_T_48 = mux(l_idx_temp_vec_6, UInt<3>(0h6), _l_idx_idx_T_47) node _l_idx_idx_T_49 = mux(l_idx_temp_vec_5, UInt<3>(0h5), _l_idx_idx_T_48) node _l_idx_idx_T_50 = mux(l_idx_temp_vec_4, UInt<3>(0h4), _l_idx_idx_T_49) node _l_idx_idx_T_51 = mux(l_idx_temp_vec_3, UInt<2>(0h3), _l_idx_idx_T_50) node _l_idx_idx_T_52 = mux(l_idx_temp_vec_2, UInt<2>(0h2), _l_idx_idx_T_51) node _l_idx_idx_T_53 = mux(l_idx_temp_vec_1, UInt<1>(0h1), _l_idx_idx_T_52) node l_idx_idx = mux(l_idx_temp_vec_0, UInt<1>(0h0), _l_idx_idx_T_53) node l_idx = bits(l_idx_idx, 4, 0) regreset r_xcpt_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg r_xcpt : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, cause : UInt<5>, badvaddr : UInt<40>}, clock node ld_xcpt_valid_lo_lo_lo_hi = cat(ldq_order_fail[2], ldq_order_fail[1]) node ld_xcpt_valid_lo_lo_lo = cat(ld_xcpt_valid_lo_lo_lo_hi, ldq_order_fail[0]) node ld_xcpt_valid_lo_lo_hi_hi = cat(ldq_order_fail[5], ldq_order_fail[4]) node ld_xcpt_valid_lo_lo_hi = cat(ld_xcpt_valid_lo_lo_hi_hi, ldq_order_fail[3]) node ld_xcpt_valid_lo_lo = cat(ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo) node ld_xcpt_valid_lo_hi_lo_hi = cat(ldq_order_fail[8], ldq_order_fail[7]) node ld_xcpt_valid_lo_hi_lo = cat(ld_xcpt_valid_lo_hi_lo_hi, ldq_order_fail[6]) node ld_xcpt_valid_lo_hi_hi_hi = cat(ldq_order_fail[11], ldq_order_fail[10]) node ld_xcpt_valid_lo_hi_hi = cat(ld_xcpt_valid_lo_hi_hi_hi, ldq_order_fail[9]) node ld_xcpt_valid_lo_hi = cat(ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo) node ld_xcpt_valid_lo = cat(ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo) node ld_xcpt_valid_hi_lo_lo_hi = cat(ldq_order_fail[14], ldq_order_fail[13]) node ld_xcpt_valid_hi_lo_lo = cat(ld_xcpt_valid_hi_lo_lo_hi, ldq_order_fail[12]) node ld_xcpt_valid_hi_lo_hi_hi = cat(ldq_order_fail[17], ldq_order_fail[16]) node ld_xcpt_valid_hi_lo_hi = cat(ld_xcpt_valid_hi_lo_hi_hi, ldq_order_fail[15]) node ld_xcpt_valid_hi_lo = cat(ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo) node ld_xcpt_valid_hi_hi_lo_hi = cat(ldq_order_fail[20], ldq_order_fail[19]) node ld_xcpt_valid_hi_hi_lo = cat(ld_xcpt_valid_hi_hi_lo_hi, ldq_order_fail[18]) node ld_xcpt_valid_hi_hi_hi_hi = cat(ldq_order_fail[23], ldq_order_fail[22]) node ld_xcpt_valid_hi_hi_hi = cat(ld_xcpt_valid_hi_hi_hi_hi, ldq_order_fail[21]) node ld_xcpt_valid_hi_hi = cat(ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo) node ld_xcpt_valid_hi = cat(ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo) node _ld_xcpt_valid_T = cat(ld_xcpt_valid_hi, ld_xcpt_valid_lo) node ld_xcpt_valid_lo_lo_lo_hi_1 = cat(ldq_valid[2], ldq_valid[1]) node ld_xcpt_valid_lo_lo_lo_1 = cat(ld_xcpt_valid_lo_lo_lo_hi_1, ldq_valid[0]) node ld_xcpt_valid_lo_lo_hi_hi_1 = cat(ldq_valid[5], ldq_valid[4]) node ld_xcpt_valid_lo_lo_hi_1 = cat(ld_xcpt_valid_lo_lo_hi_hi_1, ldq_valid[3]) node ld_xcpt_valid_lo_lo_1 = cat(ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1) node ld_xcpt_valid_lo_hi_lo_hi_1 = cat(ldq_valid[8], ldq_valid[7]) node ld_xcpt_valid_lo_hi_lo_1 = cat(ld_xcpt_valid_lo_hi_lo_hi_1, ldq_valid[6]) node ld_xcpt_valid_lo_hi_hi_hi_1 = cat(ldq_valid[11], ldq_valid[10]) node ld_xcpt_valid_lo_hi_hi_1 = cat(ld_xcpt_valid_lo_hi_hi_hi_1, ldq_valid[9]) node ld_xcpt_valid_lo_hi_1 = cat(ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1) node ld_xcpt_valid_lo_1 = cat(ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1) node ld_xcpt_valid_hi_lo_lo_hi_1 = cat(ldq_valid[14], ldq_valid[13]) node ld_xcpt_valid_hi_lo_lo_1 = cat(ld_xcpt_valid_hi_lo_lo_hi_1, ldq_valid[12]) node ld_xcpt_valid_hi_lo_hi_hi_1 = cat(ldq_valid[17], ldq_valid[16]) node ld_xcpt_valid_hi_lo_hi_1 = cat(ld_xcpt_valid_hi_lo_hi_hi_1, ldq_valid[15]) node ld_xcpt_valid_hi_lo_1 = cat(ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1) node ld_xcpt_valid_hi_hi_lo_hi_1 = cat(ldq_valid[20], ldq_valid[19]) node ld_xcpt_valid_hi_hi_lo_1 = cat(ld_xcpt_valid_hi_hi_lo_hi_1, ldq_valid[18]) node ld_xcpt_valid_hi_hi_hi_hi_1 = cat(ldq_valid[23], ldq_valid[22]) node ld_xcpt_valid_hi_hi_hi_1 = cat(ld_xcpt_valid_hi_hi_hi_hi_1, ldq_valid[21]) node ld_xcpt_valid_hi_hi_1 = cat(ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1) node ld_xcpt_valid_hi_1 = cat(ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1) node _ld_xcpt_valid_T_1 = cat(ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1) node _ld_xcpt_valid_T_2 = and(_ld_xcpt_valid_T, _ld_xcpt_valid_T_1) node ld_xcpt_valid = neq(_ld_xcpt_valid_T_2, UInt<1>(0h0)) node _ld_xcpt_uop_T = geq(l_idx, UInt<5>(0h18)) node _ld_xcpt_uop_T_1 = sub(l_idx, UInt<5>(0h18)) node _ld_xcpt_uop_T_2 = tail(_ld_xcpt_uop_T_1, 1) node _ld_xcpt_uop_T_3 = mux(_ld_xcpt_uop_T, _ld_xcpt_uop_T_2, l_idx) wire ld_xcpt_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect ld_xcpt_uop, ldq_uop[_ld_xcpt_uop_T_3] node _use_mem_xcpt_T = lt(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx) node _use_mem_xcpt_T_1 = lt(mem_xcpt_uop.rob_idx, io.core.rob_head_idx) node _use_mem_xcpt_T_2 = xor(_use_mem_xcpt_T, _use_mem_xcpt_T_1) node _use_mem_xcpt_T_3 = lt(ld_xcpt_uop.rob_idx, io.core.rob_head_idx) node _use_mem_xcpt_T_4 = xor(_use_mem_xcpt_T_2, _use_mem_xcpt_T_3) node _use_mem_xcpt_T_5 = and(mem_xcpt_valid, _use_mem_xcpt_T_4) node _use_mem_xcpt_T_6 = eq(ld_xcpt_valid, UInt<1>(0h0)) node use_mem_xcpt = or(_use_mem_xcpt_T_5, _use_mem_xcpt_T_6) node xcpt_uop = mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop) node _r_xcpt_valid_T = or(ld_xcpt_valid, mem_xcpt_valid) node _r_xcpt_valid_T_1 = and(io.core.brupdate.b1.mispredict_mask, xcpt_uop.br_mask) node _r_xcpt_valid_T_2 = neq(_r_xcpt_valid_T_1, UInt<1>(0h0)) node _r_xcpt_valid_T_3 = or(_r_xcpt_valid_T_2, io.core.exception) node _r_xcpt_valid_T_4 = eq(_r_xcpt_valid_T_3, UInt<1>(0h0)) node _r_xcpt_valid_T_5 = and(_r_xcpt_valid_T, _r_xcpt_valid_T_4) connect r_xcpt_valid, _r_xcpt_valid_T_5 connect r_xcpt.uop, xcpt_uop node _r_xcpt_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _r_xcpt_uop_br_mask_T_1 = and(xcpt_uop.br_mask, _r_xcpt_uop_br_mask_T) connect r_xcpt.uop.br_mask, _r_xcpt_uop_br_mask_T_1 node _r_xcpt_cause_T = mux(use_mem_xcpt, mem_xcpt_cause, UInt<5>(0h10)) connect r_xcpt.cause, _r_xcpt_cause_T connect r_xcpt.badvaddr, mem_xcpt_vaddr node _io_core_lxcpt_valid_T = and(io.core.brupdate.b1.mispredict_mask, r_xcpt.uop.br_mask) node _io_core_lxcpt_valid_T_1 = neq(_io_core_lxcpt_valid_T, UInt<1>(0h0)) node _io_core_lxcpt_valid_T_2 = or(_io_core_lxcpt_valid_T_1, io.core.exception) node _io_core_lxcpt_valid_T_3 = eq(_io_core_lxcpt_valid_T_2, UInt<1>(0h0)) node _io_core_lxcpt_valid_T_4 = and(r_xcpt_valid, _io_core_lxcpt_valid_T_3) connect io.core.lxcpt.valid, _io_core_lxcpt_valid_T_4 connect io.core.lxcpt.bits, r_xcpt reg wakeupArbs_0_io_in_1_valid_REG : UInt<1>, clock connect wakeupArbs_0_io_in_1_valid_REG, dmem_req_fire[0] node _wakeupArbs_0_io_in_1_valid_T = and(fired_load_agen_exec[0], wakeupArbs_0_io_in_1_valid_REG) node _wakeupArbs_0_io_in_1_valid_T_1 = eq(io.dmem.s1_nack_advisory[0], UInt<1>(0h0)) node _wakeupArbs_0_io_in_1_valid_T_2 = and(_wakeupArbs_0_io_in_1_valid_T, _wakeupArbs_0_io_in_1_valid_T_1) node _wakeupArbs_0_io_in_1_valid_T_3 = eq(mem_incoming_uop[0].fp_val, UInt<1>(0h0)) node _wakeupArbs_0_io_in_1_valid_T_4 = and(_wakeupArbs_0_io_in_1_valid_T_2, _wakeupArbs_0_io_in_1_valid_T_3) connect wakeupArbs_0.io.in[1].valid, _wakeupArbs_0_io_in_1_valid_T_4 connect wakeupArbs_0.io.in[1].bits.uop.debug_tsrc, mem_incoming_uop[0].debug_tsrc connect wakeupArbs_0.io.in[1].bits.uop.debug_fsrc, mem_incoming_uop[0].debug_fsrc connect wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if, mem_incoming_uop[0].bp_xcpt_if connect wakeupArbs_0.io.in[1].bits.uop.bp_debug_if, mem_incoming_uop[0].bp_debug_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if, mem_incoming_uop[0].xcpt_ma_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if, mem_incoming_uop[0].xcpt_ae_if connect wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if, mem_incoming_uop[0].xcpt_pf_if connect wakeupArbs_0.io.in[1].bits.uop.fp_typ, mem_incoming_uop[0].fp_typ connect wakeupArbs_0.io.in[1].bits.uop.fp_rm, mem_incoming_uop[0].fp_rm connect wakeupArbs_0.io.in[1].bits.uop.fp_val, mem_incoming_uop[0].fp_val connect wakeupArbs_0.io.in[1].bits.uop.fcn_op, mem_incoming_uop[0].fcn_op connect wakeupArbs_0.io.in[1].bits.uop.fcn_dw, mem_incoming_uop[0].fcn_dw connect wakeupArbs_0.io.in[1].bits.uop.frs3_en, mem_incoming_uop[0].frs3_en connect wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype, mem_incoming_uop[0].lrs2_rtype connect wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype, mem_incoming_uop[0].lrs1_rtype connect wakeupArbs_0.io.in[1].bits.uop.dst_rtype, mem_incoming_uop[0].dst_rtype connect wakeupArbs_0.io.in[1].bits.uop.lrs3, mem_incoming_uop[0].lrs3 connect wakeupArbs_0.io.in[1].bits.uop.lrs2, mem_incoming_uop[0].lrs2 connect wakeupArbs_0.io.in[1].bits.uop.lrs1, mem_incoming_uop[0].lrs1 connect wakeupArbs_0.io.in[1].bits.uop.ldst, mem_incoming_uop[0].ldst connect wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1, mem_incoming_uop[0].ldst_is_rs1 connect wakeupArbs_0.io.in[1].bits.uop.csr_cmd, mem_incoming_uop[0].csr_cmd connect wakeupArbs_0.io.in[1].bits.uop.flush_on_commit, mem_incoming_uop[0].flush_on_commit connect wakeupArbs_0.io.in[1].bits.uop.is_unique, mem_incoming_uop[0].is_unique connect wakeupArbs_0.io.in[1].bits.uop.uses_stq, mem_incoming_uop[0].uses_stq connect wakeupArbs_0.io.in[1].bits.uop.uses_ldq, mem_incoming_uop[0].uses_ldq connect wakeupArbs_0.io.in[1].bits.uop.mem_signed, mem_incoming_uop[0].mem_signed connect wakeupArbs_0.io.in[1].bits.uop.mem_size, mem_incoming_uop[0].mem_size connect wakeupArbs_0.io.in[1].bits.uop.mem_cmd, mem_incoming_uop[0].mem_cmd connect wakeupArbs_0.io.in[1].bits.uop.exc_cause, mem_incoming_uop[0].exc_cause connect wakeupArbs_0.io.in[1].bits.uop.exception, mem_incoming_uop[0].exception connect wakeupArbs_0.io.in[1].bits.uop.stale_pdst, mem_incoming_uop[0].stale_pdst connect wakeupArbs_0.io.in[1].bits.uop.ppred_busy, mem_incoming_uop[0].ppred_busy connect wakeupArbs_0.io.in[1].bits.uop.prs3_busy, mem_incoming_uop[0].prs3_busy connect wakeupArbs_0.io.in[1].bits.uop.prs2_busy, mem_incoming_uop[0].prs2_busy connect wakeupArbs_0.io.in[1].bits.uop.prs1_busy, mem_incoming_uop[0].prs1_busy connect wakeupArbs_0.io.in[1].bits.uop.ppred, mem_incoming_uop[0].ppred connect wakeupArbs_0.io.in[1].bits.uop.prs3, mem_incoming_uop[0].prs3 connect wakeupArbs_0.io.in[1].bits.uop.prs2, mem_incoming_uop[0].prs2 connect wakeupArbs_0.io.in[1].bits.uop.prs1, mem_incoming_uop[0].prs1 connect wakeupArbs_0.io.in[1].bits.uop.pdst, mem_incoming_uop[0].pdst connect wakeupArbs_0.io.in[1].bits.uop.rxq_idx, mem_incoming_uop[0].rxq_idx connect wakeupArbs_0.io.in[1].bits.uop.stq_idx, mem_incoming_uop[0].stq_idx connect wakeupArbs_0.io.in[1].bits.uop.ldq_idx, mem_incoming_uop[0].ldq_idx connect wakeupArbs_0.io.in[1].bits.uop.rob_idx, mem_incoming_uop[0].rob_idx connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec, mem_incoming_uop[0].fp_ctrl.vec connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags, mem_incoming_uop[0].fp_ctrl.wflags connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt, mem_incoming_uop[0].fp_ctrl.sqrt connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div, mem_incoming_uop[0].fp_ctrl.div connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma, mem_incoming_uop[0].fp_ctrl.fma connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe, mem_incoming_uop[0].fp_ctrl.fastpipe connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint, mem_incoming_uop[0].fp_ctrl.toint connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint, mem_incoming_uop[0].fp_ctrl.fromint connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut, mem_incoming_uop[0].fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn, mem_incoming_uop[0].fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23, mem_incoming_uop[0].fp_ctrl.swap23 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12, mem_incoming_uop[0].fp_ctrl.swap12 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3, mem_incoming_uop[0].fp_ctrl.ren3 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2, mem_incoming_uop[0].fp_ctrl.ren2 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1, mem_incoming_uop[0].fp_ctrl.ren1 connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen, mem_incoming_uop[0].fp_ctrl.wen connect wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst, mem_incoming_uop[0].fp_ctrl.ldst connect wakeupArbs_0.io.in[1].bits.uop.op2_sel, mem_incoming_uop[0].op2_sel connect wakeupArbs_0.io.in[1].bits.uop.op1_sel, mem_incoming_uop[0].op1_sel connect wakeupArbs_0.io.in[1].bits.uop.imm_packed, mem_incoming_uop[0].imm_packed connect wakeupArbs_0.io.in[1].bits.uop.pimm, mem_incoming_uop[0].pimm connect wakeupArbs_0.io.in[1].bits.uop.imm_sel, mem_incoming_uop[0].imm_sel connect wakeupArbs_0.io.in[1].bits.uop.imm_rename, mem_incoming_uop[0].imm_rename connect wakeupArbs_0.io.in[1].bits.uop.taken, mem_incoming_uop[0].taken connect wakeupArbs_0.io.in[1].bits.uop.pc_lob, mem_incoming_uop[0].pc_lob connect wakeupArbs_0.io.in[1].bits.uop.edge_inst, mem_incoming_uop[0].edge_inst connect wakeupArbs_0.io.in[1].bits.uop.ftq_idx, mem_incoming_uop[0].ftq_idx connect wakeupArbs_0.io.in[1].bits.uop.is_mov, mem_incoming_uop[0].is_mov connect wakeupArbs_0.io.in[1].bits.uop.is_rocc, mem_incoming_uop[0].is_rocc connect wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc, mem_incoming_uop[0].is_sys_pc2epc connect wakeupArbs_0.io.in[1].bits.uop.is_eret, mem_incoming_uop[0].is_eret connect wakeupArbs_0.io.in[1].bits.uop.is_amo, mem_incoming_uop[0].is_amo connect wakeupArbs_0.io.in[1].bits.uop.is_sfence, mem_incoming_uop[0].is_sfence connect wakeupArbs_0.io.in[1].bits.uop.is_fencei, mem_incoming_uop[0].is_fencei connect wakeupArbs_0.io.in[1].bits.uop.is_fence, mem_incoming_uop[0].is_fence connect wakeupArbs_0.io.in[1].bits.uop.is_sfb, mem_incoming_uop[0].is_sfb connect wakeupArbs_0.io.in[1].bits.uop.br_type, mem_incoming_uop[0].br_type connect wakeupArbs_0.io.in[1].bits.uop.br_tag, mem_incoming_uop[0].br_tag connect wakeupArbs_0.io.in[1].bits.uop.br_mask, mem_incoming_uop[0].br_mask connect wakeupArbs_0.io.in[1].bits.uop.dis_col_sel, mem_incoming_uop[0].dis_col_sel connect wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint, mem_incoming_uop[0].iw_p3_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint, mem_incoming_uop[0].iw_p2_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint, mem_incoming_uop[0].iw_p1_bypass_hint connect wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child, mem_incoming_uop[0].iw_p2_speculative_child connect wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child, mem_incoming_uop[0].iw_p1_speculative_child connect wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen, mem_incoming_uop[0].iw_issued_partial_dgen connect wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen, mem_incoming_uop[0].iw_issued_partial_agen connect wakeupArbs_0.io.in[1].bits.uop.iw_issued, mem_incoming_uop[0].iw_issued connect wakeupArbs_0.io.in[1].bits.uop.fu_code[0], mem_incoming_uop[0].fu_code[0] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[1], mem_incoming_uop[0].fu_code[1] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[2], mem_incoming_uop[0].fu_code[2] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[3], mem_incoming_uop[0].fu_code[3] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[4], mem_incoming_uop[0].fu_code[4] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[5], mem_incoming_uop[0].fu_code[5] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[6], mem_incoming_uop[0].fu_code[6] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[7], mem_incoming_uop[0].fu_code[7] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[8], mem_incoming_uop[0].fu_code[8] connect wakeupArbs_0.io.in[1].bits.uop.fu_code[9], mem_incoming_uop[0].fu_code[9] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[0], mem_incoming_uop[0].iq_type[0] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[1], mem_incoming_uop[0].iq_type[1] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[2], mem_incoming_uop[0].iq_type[2] connect wakeupArbs_0.io.in[1].bits.uop.iq_type[3], mem_incoming_uop[0].iq_type[3] connect wakeupArbs_0.io.in[1].bits.uop.debug_pc, mem_incoming_uop[0].debug_pc connect wakeupArbs_0.io.in[1].bits.uop.is_rvc, mem_incoming_uop[0].is_rvc connect wakeupArbs_0.io.in[1].bits.uop.debug_inst, mem_incoming_uop[0].debug_inst connect wakeupArbs_0.io.in[1].bits.uop.inst, mem_incoming_uop[0].inst connect wakeupArbs_0.io.in[1].bits.bypassable, UInt<1>(0h1) connect wakeupArbs_0.io.in[1].bits.speculative_mask, UInt<1>(0h0) connect wakeupArbs_0.io.in[1].bits.rebusy, UInt<1>(0h0) wire iresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1] wire fresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1] connect iresp[0].valid, UInt<1>(0h0) invalidate iresp[0].bits.fflags.bits invalidate iresp[0].bits.fflags.valid invalidate iresp[0].bits.predicated invalidate iresp[0].bits.data invalidate iresp[0].bits.uop.debug_tsrc invalidate iresp[0].bits.uop.debug_fsrc invalidate iresp[0].bits.uop.bp_xcpt_if invalidate iresp[0].bits.uop.bp_debug_if invalidate iresp[0].bits.uop.xcpt_ma_if invalidate iresp[0].bits.uop.xcpt_ae_if invalidate iresp[0].bits.uop.xcpt_pf_if invalidate iresp[0].bits.uop.fp_typ invalidate iresp[0].bits.uop.fp_rm invalidate iresp[0].bits.uop.fp_val invalidate iresp[0].bits.uop.fcn_op invalidate iresp[0].bits.uop.fcn_dw invalidate iresp[0].bits.uop.frs3_en invalidate iresp[0].bits.uop.lrs2_rtype invalidate iresp[0].bits.uop.lrs1_rtype invalidate iresp[0].bits.uop.dst_rtype invalidate iresp[0].bits.uop.lrs3 invalidate iresp[0].bits.uop.lrs2 invalidate iresp[0].bits.uop.lrs1 invalidate iresp[0].bits.uop.ldst invalidate iresp[0].bits.uop.ldst_is_rs1 invalidate iresp[0].bits.uop.csr_cmd invalidate iresp[0].bits.uop.flush_on_commit invalidate iresp[0].bits.uop.is_unique invalidate iresp[0].bits.uop.uses_stq invalidate iresp[0].bits.uop.uses_ldq invalidate iresp[0].bits.uop.mem_signed invalidate iresp[0].bits.uop.mem_size invalidate iresp[0].bits.uop.mem_cmd invalidate iresp[0].bits.uop.exc_cause invalidate iresp[0].bits.uop.exception invalidate iresp[0].bits.uop.stale_pdst invalidate iresp[0].bits.uop.ppred_busy invalidate iresp[0].bits.uop.prs3_busy invalidate iresp[0].bits.uop.prs2_busy invalidate iresp[0].bits.uop.prs1_busy invalidate iresp[0].bits.uop.ppred invalidate iresp[0].bits.uop.prs3 invalidate iresp[0].bits.uop.prs2 invalidate iresp[0].bits.uop.prs1 invalidate iresp[0].bits.uop.pdst invalidate iresp[0].bits.uop.rxq_idx invalidate iresp[0].bits.uop.stq_idx invalidate iresp[0].bits.uop.ldq_idx invalidate iresp[0].bits.uop.rob_idx invalidate iresp[0].bits.uop.fp_ctrl.vec invalidate iresp[0].bits.uop.fp_ctrl.wflags invalidate iresp[0].bits.uop.fp_ctrl.sqrt invalidate iresp[0].bits.uop.fp_ctrl.div invalidate iresp[0].bits.uop.fp_ctrl.fma invalidate iresp[0].bits.uop.fp_ctrl.fastpipe invalidate iresp[0].bits.uop.fp_ctrl.toint invalidate iresp[0].bits.uop.fp_ctrl.fromint invalidate iresp[0].bits.uop.fp_ctrl.typeTagOut invalidate iresp[0].bits.uop.fp_ctrl.typeTagIn invalidate iresp[0].bits.uop.fp_ctrl.swap23 invalidate iresp[0].bits.uop.fp_ctrl.swap12 invalidate iresp[0].bits.uop.fp_ctrl.ren3 invalidate iresp[0].bits.uop.fp_ctrl.ren2 invalidate iresp[0].bits.uop.fp_ctrl.ren1 invalidate iresp[0].bits.uop.fp_ctrl.wen invalidate iresp[0].bits.uop.fp_ctrl.ldst invalidate iresp[0].bits.uop.op2_sel invalidate iresp[0].bits.uop.op1_sel invalidate iresp[0].bits.uop.imm_packed invalidate iresp[0].bits.uop.pimm invalidate iresp[0].bits.uop.imm_sel invalidate iresp[0].bits.uop.imm_rename invalidate iresp[0].bits.uop.taken invalidate iresp[0].bits.uop.pc_lob invalidate iresp[0].bits.uop.edge_inst invalidate iresp[0].bits.uop.ftq_idx invalidate iresp[0].bits.uop.is_mov invalidate iresp[0].bits.uop.is_rocc invalidate iresp[0].bits.uop.is_sys_pc2epc invalidate iresp[0].bits.uop.is_eret invalidate iresp[0].bits.uop.is_amo invalidate iresp[0].bits.uop.is_sfence invalidate iresp[0].bits.uop.is_fencei invalidate iresp[0].bits.uop.is_fence invalidate iresp[0].bits.uop.is_sfb invalidate iresp[0].bits.uop.br_type invalidate iresp[0].bits.uop.br_tag invalidate iresp[0].bits.uop.br_mask invalidate iresp[0].bits.uop.dis_col_sel invalidate iresp[0].bits.uop.iw_p3_bypass_hint invalidate iresp[0].bits.uop.iw_p2_bypass_hint invalidate iresp[0].bits.uop.iw_p1_bypass_hint invalidate iresp[0].bits.uop.iw_p2_speculative_child invalidate iresp[0].bits.uop.iw_p1_speculative_child invalidate iresp[0].bits.uop.iw_issued_partial_dgen invalidate iresp[0].bits.uop.iw_issued_partial_agen invalidate iresp[0].bits.uop.iw_issued invalidate iresp[0].bits.uop.fu_code[0] invalidate iresp[0].bits.uop.fu_code[1] invalidate iresp[0].bits.uop.fu_code[2] invalidate iresp[0].bits.uop.fu_code[3] invalidate iresp[0].bits.uop.fu_code[4] invalidate iresp[0].bits.uop.fu_code[5] invalidate iresp[0].bits.uop.fu_code[6] invalidate iresp[0].bits.uop.fu_code[7] invalidate iresp[0].bits.uop.fu_code[8] invalidate iresp[0].bits.uop.fu_code[9] invalidate iresp[0].bits.uop.iq_type[0] invalidate iresp[0].bits.uop.iq_type[1] invalidate iresp[0].bits.uop.iq_type[2] invalidate iresp[0].bits.uop.iq_type[3] invalidate iresp[0].bits.uop.debug_pc invalidate iresp[0].bits.uop.is_rvc invalidate iresp[0].bits.uop.debug_inst invalidate iresp[0].bits.uop.inst connect fresp[0].valid, UInt<1>(0h0) invalidate fresp[0].bits.fflags.bits invalidate fresp[0].bits.fflags.valid invalidate fresp[0].bits.predicated invalidate fresp[0].bits.data invalidate fresp[0].bits.uop.debug_tsrc invalidate fresp[0].bits.uop.debug_fsrc invalidate fresp[0].bits.uop.bp_xcpt_if invalidate fresp[0].bits.uop.bp_debug_if invalidate fresp[0].bits.uop.xcpt_ma_if invalidate fresp[0].bits.uop.xcpt_ae_if invalidate fresp[0].bits.uop.xcpt_pf_if invalidate fresp[0].bits.uop.fp_typ invalidate fresp[0].bits.uop.fp_rm invalidate fresp[0].bits.uop.fp_val invalidate fresp[0].bits.uop.fcn_op invalidate fresp[0].bits.uop.fcn_dw invalidate fresp[0].bits.uop.frs3_en invalidate fresp[0].bits.uop.lrs2_rtype invalidate fresp[0].bits.uop.lrs1_rtype invalidate fresp[0].bits.uop.dst_rtype invalidate fresp[0].bits.uop.lrs3 invalidate fresp[0].bits.uop.lrs2 invalidate fresp[0].bits.uop.lrs1 invalidate fresp[0].bits.uop.ldst invalidate fresp[0].bits.uop.ldst_is_rs1 invalidate fresp[0].bits.uop.csr_cmd invalidate fresp[0].bits.uop.flush_on_commit invalidate fresp[0].bits.uop.is_unique invalidate fresp[0].bits.uop.uses_stq invalidate fresp[0].bits.uop.uses_ldq invalidate fresp[0].bits.uop.mem_signed invalidate fresp[0].bits.uop.mem_size invalidate fresp[0].bits.uop.mem_cmd invalidate fresp[0].bits.uop.exc_cause invalidate fresp[0].bits.uop.exception invalidate fresp[0].bits.uop.stale_pdst invalidate fresp[0].bits.uop.ppred_busy invalidate fresp[0].bits.uop.prs3_busy invalidate fresp[0].bits.uop.prs2_busy invalidate fresp[0].bits.uop.prs1_busy invalidate fresp[0].bits.uop.ppred invalidate fresp[0].bits.uop.prs3 invalidate fresp[0].bits.uop.prs2 invalidate fresp[0].bits.uop.prs1 invalidate fresp[0].bits.uop.pdst invalidate fresp[0].bits.uop.rxq_idx invalidate fresp[0].bits.uop.stq_idx invalidate fresp[0].bits.uop.ldq_idx invalidate fresp[0].bits.uop.rob_idx invalidate fresp[0].bits.uop.fp_ctrl.vec invalidate fresp[0].bits.uop.fp_ctrl.wflags invalidate fresp[0].bits.uop.fp_ctrl.sqrt invalidate fresp[0].bits.uop.fp_ctrl.div invalidate fresp[0].bits.uop.fp_ctrl.fma invalidate fresp[0].bits.uop.fp_ctrl.fastpipe invalidate fresp[0].bits.uop.fp_ctrl.toint invalidate fresp[0].bits.uop.fp_ctrl.fromint invalidate fresp[0].bits.uop.fp_ctrl.typeTagOut invalidate fresp[0].bits.uop.fp_ctrl.typeTagIn invalidate fresp[0].bits.uop.fp_ctrl.swap23 invalidate fresp[0].bits.uop.fp_ctrl.swap12 invalidate fresp[0].bits.uop.fp_ctrl.ren3 invalidate fresp[0].bits.uop.fp_ctrl.ren2 invalidate fresp[0].bits.uop.fp_ctrl.ren1 invalidate fresp[0].bits.uop.fp_ctrl.wen invalidate fresp[0].bits.uop.fp_ctrl.ldst invalidate fresp[0].bits.uop.op2_sel invalidate fresp[0].bits.uop.op1_sel invalidate fresp[0].bits.uop.imm_packed invalidate fresp[0].bits.uop.pimm invalidate fresp[0].bits.uop.imm_sel invalidate fresp[0].bits.uop.imm_rename invalidate fresp[0].bits.uop.taken invalidate fresp[0].bits.uop.pc_lob invalidate fresp[0].bits.uop.edge_inst invalidate fresp[0].bits.uop.ftq_idx invalidate fresp[0].bits.uop.is_mov invalidate fresp[0].bits.uop.is_rocc invalidate fresp[0].bits.uop.is_sys_pc2epc invalidate fresp[0].bits.uop.is_eret invalidate fresp[0].bits.uop.is_amo invalidate fresp[0].bits.uop.is_sfence invalidate fresp[0].bits.uop.is_fencei invalidate fresp[0].bits.uop.is_fence invalidate fresp[0].bits.uop.is_sfb invalidate fresp[0].bits.uop.br_type invalidate fresp[0].bits.uop.br_tag invalidate fresp[0].bits.uop.br_mask invalidate fresp[0].bits.uop.dis_col_sel invalidate fresp[0].bits.uop.iw_p3_bypass_hint invalidate fresp[0].bits.uop.iw_p2_bypass_hint invalidate fresp[0].bits.uop.iw_p1_bypass_hint invalidate fresp[0].bits.uop.iw_p2_speculative_child invalidate fresp[0].bits.uop.iw_p1_speculative_child invalidate fresp[0].bits.uop.iw_issued_partial_dgen invalidate fresp[0].bits.uop.iw_issued_partial_agen invalidate fresp[0].bits.uop.iw_issued invalidate fresp[0].bits.uop.fu_code[0] invalidate fresp[0].bits.uop.fu_code[1] invalidate fresp[0].bits.uop.fu_code[2] invalidate fresp[0].bits.uop.fu_code[3] invalidate fresp[0].bits.uop.fu_code[4] invalidate fresp[0].bits.uop.fu_code[5] invalidate fresp[0].bits.uop.fu_code[6] invalidate fresp[0].bits.uop.fu_code[7] invalidate fresp[0].bits.uop.fu_code[8] invalidate fresp[0].bits.uop.fu_code[9] invalidate fresp[0].bits.uop.iq_type[0] invalidate fresp[0].bits.uop.iq_type[1] invalidate fresp[0].bits.uop.iq_type[2] invalidate fresp[0].bits.uop.iq_type[3] invalidate fresp[0].bits.uop.debug_pc invalidate fresp[0].bits.uop.is_rvc invalidate fresp[0].bits.uop.debug_inst invalidate fresp[0].bits.uop.inst wire io_core_iresp_0_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}} connect io_core_iresp_0_out, iresp[0] node _io_core_iresp_0_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _io_core_iresp_0_out_bits_uop_br_mask_T_1 = and(iresp[0].bits.uop.br_mask, _io_core_iresp_0_out_bits_uop_br_mask_T) connect io_core_iresp_0_out.bits.uop.br_mask, _io_core_iresp_0_out_bits_uop_br_mask_T_1 node _io_core_iresp_0_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, iresp[0].bits.uop.br_mask) node _io_core_iresp_0_out_valid_T_1 = neq(_io_core_iresp_0_out_valid_T, UInt<1>(0h0)) node _io_core_iresp_0_out_valid_T_2 = or(_io_core_iresp_0_out_valid_T_1, io.core.exception) node _io_core_iresp_0_out_valid_T_3 = eq(_io_core_iresp_0_out_valid_T_2, UInt<1>(0h0)) node _io_core_iresp_0_out_valid_T_4 = and(iresp[0].valid, _io_core_iresp_0_out_valid_T_3) connect io_core_iresp_0_out.valid, _io_core_iresp_0_out_valid_T_4 reg io_core_iresp_0_REG : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, clock connect io_core_iresp_0_REG, io_core_iresp_0_out connect io.core.iresp[0], io_core_iresp_0_REG connect io.core.fresp[0], fresp[0] wire wb_spec_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire spec_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire wb_slow_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire slow_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1] wire _dmem_resp_fired_WIRE : UInt<1>[1] connect _dmem_resp_fired_WIRE[0], UInt<1>(0h0) wire dmem_resp_fired : UInt<1>[1] connect dmem_resp_fired, _dmem_resp_fired_WIRE reg w1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock node _w1_valid_T = and(wakeupArbs_0.io.in[1].ready, wakeupArbs_0.io.in[1].valid) node _w1_valid_T_1 = and(io.core.brupdate.b1.mispredict_mask, wakeupArbs_0.io.in[1].bits.uop.br_mask) node _w1_valid_T_2 = neq(_w1_valid_T_1, UInt<1>(0h0)) node _w1_valid_T_3 = or(_w1_valid_T_2, io.core.exception) node _w1_valid_T_4 = eq(_w1_valid_T_3, UInt<1>(0h0)) node _w1_valid_T_5 = and(_w1_valid_T, _w1_valid_T_4) connect w1.valid, _w1_valid_T_5 wire w1_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>} connect w1_bits_out.rebusy, wakeupArbs_0.io.in[1].bits.rebusy connect w1_bits_out.speculative_mask, wakeupArbs_0.io.in[1].bits.speculative_mask connect w1_bits_out.bypassable, wakeupArbs_0.io.in[1].bits.bypassable connect w1_bits_out.uop.debug_tsrc, wakeupArbs_0.io.in[1].bits.uop.debug_tsrc connect w1_bits_out.uop.debug_fsrc, wakeupArbs_0.io.in[1].bits.uop.debug_fsrc connect w1_bits_out.uop.bp_xcpt_if, wakeupArbs_0.io.in[1].bits.uop.bp_xcpt_if connect w1_bits_out.uop.bp_debug_if, wakeupArbs_0.io.in[1].bits.uop.bp_debug_if connect w1_bits_out.uop.xcpt_ma_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_ma_if connect w1_bits_out.uop.xcpt_ae_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_ae_if connect w1_bits_out.uop.xcpt_pf_if, wakeupArbs_0.io.in[1].bits.uop.xcpt_pf_if connect w1_bits_out.uop.fp_typ, wakeupArbs_0.io.in[1].bits.uop.fp_typ connect w1_bits_out.uop.fp_rm, wakeupArbs_0.io.in[1].bits.uop.fp_rm connect w1_bits_out.uop.fp_val, wakeupArbs_0.io.in[1].bits.uop.fp_val connect w1_bits_out.uop.fcn_op, wakeupArbs_0.io.in[1].bits.uop.fcn_op connect w1_bits_out.uop.fcn_dw, wakeupArbs_0.io.in[1].bits.uop.fcn_dw connect w1_bits_out.uop.frs3_en, wakeupArbs_0.io.in[1].bits.uop.frs3_en connect w1_bits_out.uop.lrs2_rtype, wakeupArbs_0.io.in[1].bits.uop.lrs2_rtype connect w1_bits_out.uop.lrs1_rtype, wakeupArbs_0.io.in[1].bits.uop.lrs1_rtype connect w1_bits_out.uop.dst_rtype, wakeupArbs_0.io.in[1].bits.uop.dst_rtype connect w1_bits_out.uop.lrs3, wakeupArbs_0.io.in[1].bits.uop.lrs3 connect w1_bits_out.uop.lrs2, wakeupArbs_0.io.in[1].bits.uop.lrs2 connect w1_bits_out.uop.lrs1, wakeupArbs_0.io.in[1].bits.uop.lrs1 connect w1_bits_out.uop.ldst, wakeupArbs_0.io.in[1].bits.uop.ldst connect w1_bits_out.uop.ldst_is_rs1, wakeupArbs_0.io.in[1].bits.uop.ldst_is_rs1 connect w1_bits_out.uop.csr_cmd, wakeupArbs_0.io.in[1].bits.uop.csr_cmd connect w1_bits_out.uop.flush_on_commit, wakeupArbs_0.io.in[1].bits.uop.flush_on_commit connect w1_bits_out.uop.is_unique, wakeupArbs_0.io.in[1].bits.uop.is_unique connect w1_bits_out.uop.uses_stq, wakeupArbs_0.io.in[1].bits.uop.uses_stq connect w1_bits_out.uop.uses_ldq, wakeupArbs_0.io.in[1].bits.uop.uses_ldq connect w1_bits_out.uop.mem_signed, wakeupArbs_0.io.in[1].bits.uop.mem_signed connect w1_bits_out.uop.mem_size, wakeupArbs_0.io.in[1].bits.uop.mem_size connect w1_bits_out.uop.mem_cmd, wakeupArbs_0.io.in[1].bits.uop.mem_cmd connect w1_bits_out.uop.exc_cause, wakeupArbs_0.io.in[1].bits.uop.exc_cause connect w1_bits_out.uop.exception, wakeupArbs_0.io.in[1].bits.uop.exception connect w1_bits_out.uop.stale_pdst, wakeupArbs_0.io.in[1].bits.uop.stale_pdst connect w1_bits_out.uop.ppred_busy, wakeupArbs_0.io.in[1].bits.uop.ppred_busy connect w1_bits_out.uop.prs3_busy, wakeupArbs_0.io.in[1].bits.uop.prs3_busy connect w1_bits_out.uop.prs2_busy, wakeupArbs_0.io.in[1].bits.uop.prs2_busy connect w1_bits_out.uop.prs1_busy, wakeupArbs_0.io.in[1].bits.uop.prs1_busy connect w1_bits_out.uop.ppred, wakeupArbs_0.io.in[1].bits.uop.ppred connect w1_bits_out.uop.prs3, wakeupArbs_0.io.in[1].bits.uop.prs3 connect w1_bits_out.uop.prs2, wakeupArbs_0.io.in[1].bits.uop.prs2 connect w1_bits_out.uop.prs1, wakeupArbs_0.io.in[1].bits.uop.prs1 connect w1_bits_out.uop.pdst, wakeupArbs_0.io.in[1].bits.uop.pdst connect w1_bits_out.uop.rxq_idx, wakeupArbs_0.io.in[1].bits.uop.rxq_idx connect w1_bits_out.uop.stq_idx, wakeupArbs_0.io.in[1].bits.uop.stq_idx connect w1_bits_out.uop.ldq_idx, wakeupArbs_0.io.in[1].bits.uop.ldq_idx connect w1_bits_out.uop.rob_idx, wakeupArbs_0.io.in[1].bits.uop.rob_idx connect w1_bits_out.uop.fp_ctrl.vec, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.vec connect w1_bits_out.uop.fp_ctrl.wflags, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wflags connect w1_bits_out.uop.fp_ctrl.sqrt, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.sqrt connect w1_bits_out.uop.fp_ctrl.div, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.div connect w1_bits_out.uop.fp_ctrl.fma, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fma connect w1_bits_out.uop.fp_ctrl.fastpipe, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fastpipe connect w1_bits_out.uop.fp_ctrl.toint, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.toint connect w1_bits_out.uop.fp_ctrl.fromint, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.fromint connect w1_bits_out.uop.fp_ctrl.typeTagOut, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagOut connect w1_bits_out.uop.fp_ctrl.typeTagIn, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.typeTagIn connect w1_bits_out.uop.fp_ctrl.swap23, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap23 connect w1_bits_out.uop.fp_ctrl.swap12, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.swap12 connect w1_bits_out.uop.fp_ctrl.ren3, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren3 connect w1_bits_out.uop.fp_ctrl.ren2, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren2 connect w1_bits_out.uop.fp_ctrl.ren1, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ren1 connect w1_bits_out.uop.fp_ctrl.wen, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.wen connect w1_bits_out.uop.fp_ctrl.ldst, wakeupArbs_0.io.in[1].bits.uop.fp_ctrl.ldst connect w1_bits_out.uop.op2_sel, wakeupArbs_0.io.in[1].bits.uop.op2_sel connect w1_bits_out.uop.op1_sel, wakeupArbs_0.io.in[1].bits.uop.op1_sel connect w1_bits_out.uop.imm_packed, wakeupArbs_0.io.in[1].bits.uop.imm_packed connect w1_bits_out.uop.pimm, wakeupArbs_0.io.in[1].bits.uop.pimm connect w1_bits_out.uop.imm_sel, wakeupArbs_0.io.in[1].bits.uop.imm_sel connect w1_bits_out.uop.imm_rename, wakeupArbs_0.io.in[1].bits.uop.imm_rename connect w1_bits_out.uop.taken, wakeupArbs_0.io.in[1].bits.uop.taken connect w1_bits_out.uop.pc_lob, wakeupArbs_0.io.in[1].bits.uop.pc_lob connect w1_bits_out.uop.edge_inst, wakeupArbs_0.io.in[1].bits.uop.edge_inst connect w1_bits_out.uop.ftq_idx, wakeupArbs_0.io.in[1].bits.uop.ftq_idx connect w1_bits_out.uop.is_mov, wakeupArbs_0.io.in[1].bits.uop.is_mov connect w1_bits_out.uop.is_rocc, wakeupArbs_0.io.in[1].bits.uop.is_rocc connect w1_bits_out.uop.is_sys_pc2epc, wakeupArbs_0.io.in[1].bits.uop.is_sys_pc2epc connect w1_bits_out.uop.is_eret, wakeupArbs_0.io.in[1].bits.uop.is_eret connect w1_bits_out.uop.is_amo, wakeupArbs_0.io.in[1].bits.uop.is_amo connect w1_bits_out.uop.is_sfence, wakeupArbs_0.io.in[1].bits.uop.is_sfence connect w1_bits_out.uop.is_fencei, wakeupArbs_0.io.in[1].bits.uop.is_fencei connect w1_bits_out.uop.is_fence, wakeupArbs_0.io.in[1].bits.uop.is_fence connect w1_bits_out.uop.is_sfb, wakeupArbs_0.io.in[1].bits.uop.is_sfb connect w1_bits_out.uop.br_type, wakeupArbs_0.io.in[1].bits.uop.br_type connect w1_bits_out.uop.br_tag, wakeupArbs_0.io.in[1].bits.uop.br_tag connect w1_bits_out.uop.br_mask, wakeupArbs_0.io.in[1].bits.uop.br_mask connect w1_bits_out.uop.dis_col_sel, wakeupArbs_0.io.in[1].bits.uop.dis_col_sel connect w1_bits_out.uop.iw_p3_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p3_bypass_hint connect w1_bits_out.uop.iw_p2_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p2_bypass_hint connect w1_bits_out.uop.iw_p1_bypass_hint, wakeupArbs_0.io.in[1].bits.uop.iw_p1_bypass_hint connect w1_bits_out.uop.iw_p2_speculative_child, wakeupArbs_0.io.in[1].bits.uop.iw_p2_speculative_child connect w1_bits_out.uop.iw_p1_speculative_child, wakeupArbs_0.io.in[1].bits.uop.iw_p1_speculative_child connect w1_bits_out.uop.iw_issued_partial_dgen, wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_dgen connect w1_bits_out.uop.iw_issued_partial_agen, wakeupArbs_0.io.in[1].bits.uop.iw_issued_partial_agen connect w1_bits_out.uop.iw_issued, wakeupArbs_0.io.in[1].bits.uop.iw_issued connect w1_bits_out.uop.fu_code[0], wakeupArbs_0.io.in[1].bits.uop.fu_code[0] connect w1_bits_out.uop.fu_code[1], wakeupArbs_0.io.in[1].bits.uop.fu_code[1] connect w1_bits_out.uop.fu_code[2], wakeupArbs_0.io.in[1].bits.uop.fu_code[2] connect w1_bits_out.uop.fu_code[3], wakeupArbs_0.io.in[1].bits.uop.fu_code[3] connect w1_bits_out.uop.fu_code[4], wakeupArbs_0.io.in[1].bits.uop.fu_code[4] connect w1_bits_out.uop.fu_code[5], wakeupArbs_0.io.in[1].bits.uop.fu_code[5] connect w1_bits_out.uop.fu_code[6], wakeupArbs_0.io.in[1].bits.uop.fu_code[6] connect w1_bits_out.uop.fu_code[7], wakeupArbs_0.io.in[1].bits.uop.fu_code[7] connect w1_bits_out.uop.fu_code[8], wakeupArbs_0.io.in[1].bits.uop.fu_code[8] connect w1_bits_out.uop.fu_code[9], wakeupArbs_0.io.in[1].bits.uop.fu_code[9] connect w1_bits_out.uop.iq_type[0], wakeupArbs_0.io.in[1].bits.uop.iq_type[0] connect w1_bits_out.uop.iq_type[1], wakeupArbs_0.io.in[1].bits.uop.iq_type[1] connect w1_bits_out.uop.iq_type[2], wakeupArbs_0.io.in[1].bits.uop.iq_type[2] connect w1_bits_out.uop.iq_type[3], wakeupArbs_0.io.in[1].bits.uop.iq_type[3] connect w1_bits_out.uop.debug_pc, wakeupArbs_0.io.in[1].bits.uop.debug_pc connect w1_bits_out.uop.is_rvc, wakeupArbs_0.io.in[1].bits.uop.is_rvc connect w1_bits_out.uop.debug_inst, wakeupArbs_0.io.in[1].bits.uop.debug_inst connect w1_bits_out.uop.inst, wakeupArbs_0.io.in[1].bits.uop.inst node _w1_bits_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _w1_bits_out_uop_br_mask_T_1 = and(wakeupArbs_0.io.in[1].bits.uop.br_mask, _w1_bits_out_uop_br_mask_T) connect w1_bits_out.uop.br_mask, _w1_bits_out_uop_br_mask_T_1 connect w1.bits, w1_bits_out reg w2 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock node _w2_valid_T = and(io.core.brupdate.b1.mispredict_mask, w1.bits.uop.br_mask) node _w2_valid_T_1 = neq(_w2_valid_T, UInt<1>(0h0)) node _w2_valid_T_2 = or(_w2_valid_T_1, io.core.exception) node _w2_valid_T_3 = eq(_w2_valid_T_2, UInt<1>(0h0)) node _w2_valid_T_4 = and(w1.valid, _w2_valid_T_3) connect w2.valid, _w2_valid_T_4 wire w2_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>} connect w2_bits_out, w1.bits node _w2_bits_out_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _w2_bits_out_uop_br_mask_T_1 = and(w1.bits.uop.br_mask, _w2_bits_out_uop_br_mask_T) connect w2_bits_out.uop.br_mask, _w2_bits_out_uop_br_mask_T_1 connect w2.bits, w2_bits_out connect spec_wakeups[0].valid, w2.valid connect spec_wakeups[0].bits, w2.bits connect wb_spec_wakeups[0], w1 connect wb_slow_wakeups[0].valid, UInt<1>(0h0) invalidate wb_slow_wakeups[0].bits.rebusy invalidate wb_slow_wakeups[0].bits.speculative_mask invalidate wb_slow_wakeups[0].bits.bypassable invalidate wb_slow_wakeups[0].bits.uop.debug_tsrc invalidate wb_slow_wakeups[0].bits.uop.debug_fsrc invalidate wb_slow_wakeups[0].bits.uop.bp_xcpt_if invalidate wb_slow_wakeups[0].bits.uop.bp_debug_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_ma_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_ae_if invalidate wb_slow_wakeups[0].bits.uop.xcpt_pf_if invalidate wb_slow_wakeups[0].bits.uop.fp_typ invalidate wb_slow_wakeups[0].bits.uop.fp_rm invalidate wb_slow_wakeups[0].bits.uop.fp_val invalidate wb_slow_wakeups[0].bits.uop.fcn_op invalidate wb_slow_wakeups[0].bits.uop.fcn_dw invalidate wb_slow_wakeups[0].bits.uop.frs3_en invalidate wb_slow_wakeups[0].bits.uop.lrs2_rtype invalidate wb_slow_wakeups[0].bits.uop.lrs1_rtype invalidate wb_slow_wakeups[0].bits.uop.dst_rtype invalidate wb_slow_wakeups[0].bits.uop.lrs3 invalidate wb_slow_wakeups[0].bits.uop.lrs2 invalidate wb_slow_wakeups[0].bits.uop.lrs1 invalidate wb_slow_wakeups[0].bits.uop.ldst invalidate wb_slow_wakeups[0].bits.uop.ldst_is_rs1 invalidate wb_slow_wakeups[0].bits.uop.csr_cmd invalidate wb_slow_wakeups[0].bits.uop.flush_on_commit invalidate wb_slow_wakeups[0].bits.uop.is_unique invalidate wb_slow_wakeups[0].bits.uop.uses_stq invalidate wb_slow_wakeups[0].bits.uop.uses_ldq invalidate wb_slow_wakeups[0].bits.uop.mem_signed invalidate wb_slow_wakeups[0].bits.uop.mem_size invalidate wb_slow_wakeups[0].bits.uop.mem_cmd invalidate wb_slow_wakeups[0].bits.uop.exc_cause invalidate wb_slow_wakeups[0].bits.uop.exception invalidate wb_slow_wakeups[0].bits.uop.stale_pdst invalidate wb_slow_wakeups[0].bits.uop.ppred_busy invalidate wb_slow_wakeups[0].bits.uop.prs3_busy invalidate wb_slow_wakeups[0].bits.uop.prs2_busy invalidate wb_slow_wakeups[0].bits.uop.prs1_busy invalidate wb_slow_wakeups[0].bits.uop.ppred invalidate wb_slow_wakeups[0].bits.uop.prs3 invalidate wb_slow_wakeups[0].bits.uop.prs2 invalidate wb_slow_wakeups[0].bits.uop.prs1 invalidate wb_slow_wakeups[0].bits.uop.pdst invalidate wb_slow_wakeups[0].bits.uop.rxq_idx invalidate wb_slow_wakeups[0].bits.uop.stq_idx invalidate wb_slow_wakeups[0].bits.uop.ldq_idx invalidate wb_slow_wakeups[0].bits.uop.rob_idx invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.vec invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.wflags invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.sqrt invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.div invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fma invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fastpipe invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.toint invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.fromint invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.typeTagOut invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.typeTagIn invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.swap23 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.swap12 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren3 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren2 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ren1 invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.wen invalidate wb_slow_wakeups[0].bits.uop.fp_ctrl.ldst invalidate wb_slow_wakeups[0].bits.uop.op2_sel invalidate wb_slow_wakeups[0].bits.uop.op1_sel invalidate wb_slow_wakeups[0].bits.uop.imm_packed invalidate wb_slow_wakeups[0].bits.uop.pimm invalidate wb_slow_wakeups[0].bits.uop.imm_sel invalidate wb_slow_wakeups[0].bits.uop.imm_rename invalidate wb_slow_wakeups[0].bits.uop.taken invalidate wb_slow_wakeups[0].bits.uop.pc_lob invalidate wb_slow_wakeups[0].bits.uop.edge_inst invalidate wb_slow_wakeups[0].bits.uop.ftq_idx invalidate wb_slow_wakeups[0].bits.uop.is_mov invalidate wb_slow_wakeups[0].bits.uop.is_rocc invalidate wb_slow_wakeups[0].bits.uop.is_sys_pc2epc invalidate wb_slow_wakeups[0].bits.uop.is_eret invalidate wb_slow_wakeups[0].bits.uop.is_amo invalidate wb_slow_wakeups[0].bits.uop.is_sfence invalidate wb_slow_wakeups[0].bits.uop.is_fencei invalidate wb_slow_wakeups[0].bits.uop.is_fence invalidate wb_slow_wakeups[0].bits.uop.is_sfb invalidate wb_slow_wakeups[0].bits.uop.br_type invalidate wb_slow_wakeups[0].bits.uop.br_tag invalidate wb_slow_wakeups[0].bits.uop.br_mask invalidate wb_slow_wakeups[0].bits.uop.dis_col_sel invalidate wb_slow_wakeups[0].bits.uop.iw_p3_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p2_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p1_bypass_hint invalidate wb_slow_wakeups[0].bits.uop.iw_p2_speculative_child invalidate wb_slow_wakeups[0].bits.uop.iw_p1_speculative_child invalidate wb_slow_wakeups[0].bits.uop.iw_issued_partial_dgen invalidate wb_slow_wakeups[0].bits.uop.iw_issued_partial_agen invalidate wb_slow_wakeups[0].bits.uop.iw_issued invalidate wb_slow_wakeups[0].bits.uop.fu_code[0] invalidate wb_slow_wakeups[0].bits.uop.fu_code[1] invalidate wb_slow_wakeups[0].bits.uop.fu_code[2] invalidate wb_slow_wakeups[0].bits.uop.fu_code[3] invalidate wb_slow_wakeups[0].bits.uop.fu_code[4] invalidate wb_slow_wakeups[0].bits.uop.fu_code[5] invalidate wb_slow_wakeups[0].bits.uop.fu_code[6] invalidate wb_slow_wakeups[0].bits.uop.fu_code[7] invalidate wb_slow_wakeups[0].bits.uop.fu_code[8] invalidate wb_slow_wakeups[0].bits.uop.fu_code[9] invalidate wb_slow_wakeups[0].bits.uop.iq_type[0] invalidate wb_slow_wakeups[0].bits.uop.iq_type[1] invalidate wb_slow_wakeups[0].bits.uop.iq_type[2] invalidate wb_slow_wakeups[0].bits.uop.iq_type[3] invalidate wb_slow_wakeups[0].bits.uop.debug_pc invalidate wb_slow_wakeups[0].bits.uop.is_rvc invalidate wb_slow_wakeups[0].bits.uop.debug_inst invalidate wb_slow_wakeups[0].bits.uop.inst when io.dmem.nack[0].valid : when io.dmem.nack[0].bits.is_hella : node _T_1643 = eq(hella_state, UInt<3>(0h4)) node _T_1644 = eq(hella_state, UInt<3>(0h6)) node _T_1645 = or(_T_1643, _T_1644) node _T_1646 = asUInt(reset) node _T_1647 = eq(_T_1646, UInt<1>(0h0)) when _T_1647 : node _T_1648 = eq(_T_1645, UInt<1>(0h0)) when _T_1648 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1521 assert(hella_state === h_wait || hella_state === h_dead)\n") : printf_80 assert(clock, _T_1645, UInt<1>(0h1), "") : assert_80 else : when io.dmem.nack[0].bits.uop.uses_ldq : node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1523 assert(ldq_executed(io.dmem.nack(w).bits.uop.ldq_idx))\n") : printf_81 assert(clock, ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h1), "") : assert_81 connect ldq_executed[io.dmem.nack[0].bits.uop.ldq_idx], UInt<1>(0h0) else : node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1526 assert(io.dmem.nack(w).bits.uop.uses_stq)\n") : printf_82 assert(clock, io.dmem.nack[0].bits.uop.uses_stq, UInt<1>(0h1), "") : assert_82 node _T_1655 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_execute_head) node _T_1656 = lt(io.dmem.nack[0].bits.uop.stq_idx, stq_head) node _T_1657 = xor(_T_1655, _T_1656) node _T_1658 = lt(stq_execute_head, stq_head) node _T_1659 = xor(_T_1657, _T_1658) when _T_1659 : connect stq_execute_queue_flush, UInt<1>(0h1) connect stq_execute_head, io.dmem.nack[0].bits.uop.stq_idx node _resp_T = eq(io.dmem.resp[0].valid, UInt<1>(0h0)) node _resp_T_1 = and(_resp_T, UInt<1>(0h1)) node resp = mux(_resp_T_1, io.dmem.ll_resp.bits, io.dmem.resp[0].bits) node _io_dmem_ll_resp_ready_T = eq(io.dmem.resp[0].valid, UInt<1>(0h0)) node _io_dmem_ll_resp_ready_T_1 = eq(wb_spec_wakeups[0].valid, UInt<1>(0h0)) node _io_dmem_ll_resp_ready_T_2 = and(_io_dmem_ll_resp_ready_T, _io_dmem_ll_resp_ready_T_1) connect io.dmem.ll_resp.ready, _io_dmem_ll_resp_ready_T_2 node _T_1660 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_1661 = and(UInt<1>(0h1), _T_1660) node _T_1662 = or(io.dmem.resp[0].valid, _T_1661) when _T_1662 : when resp.uop.uses_ldq : node _T_1663 = eq(resp.is_hella, UInt<1>(0h0)) node _T_1664 = asUInt(reset) node _T_1665 = eq(_T_1664, UInt<1>(0h0)) when _T_1665 : node _T_1666 = eq(_T_1663, UInt<1>(0h0)) when _T_1666 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1541 assert(!resp.is_hella)\n") : printf_83 assert(clock, _T_1663, UInt<1>(0h1), "") : assert_83 wire uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop, ldq_uop[resp.uop.ldq_idx] node send_iresp = eq(uop.dst_rtype, UInt<2>(0h0)) node send_fresp = eq(uop.dst_rtype, UInt<2>(0h1)) connect iresp[0].bits.uop, uop connect fresp[0].bits.uop, uop connect iresp[0].valid, send_iresp connect iresp[0].bits.data, resp.data connect fresp[0].valid, send_fresp connect fresp[0].bits.data, resp.data node _T_1667 = xor(send_iresp, send_fresp) node _T_1668 = asUInt(reset) node _T_1669 = eq(_T_1668, UInt<1>(0h0)) when _T_1669 : node _T_1670 = eq(_T_1667, UInt<1>(0h0)) when _T_1670 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1557 assert(send_iresp ^ send_fresp)\n") : printf_84 assert(clock, _T_1667, UInt<1>(0h1), "") : assert_84 connect dmem_resp_fired[0], UInt<1>(0h1) node _ldq_will_succeed_T = or(iresp[0].valid, fresp[0].valid) connect ldq_will_succeed[resp.uop.ldq_idx], _ldq_will_succeed_T connect ldq_debug_wb_data[resp.uop.ldq_idx], resp.data connect wb_slow_wakeups[0].valid, send_iresp connect wb_slow_wakeups[0].bits.uop, uop connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) when resp.uop.uses_stq : node _T_1671 = eq(resp.is_hella, UInt<1>(0h0)) node _T_1672 = and(_T_1671, resp.uop.is_amo) node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(_T_1672, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1573 assert(!resp.is_hella && resp.uop.is_amo)\n") : printf_85 assert(clock, _T_1672, UInt<1>(0h1), "") : assert_85 connect dmem_resp_fired[0], UInt<1>(0h1) connect iresp[0].valid, UInt<1>(0h1) connect iresp[0].bits.uop, stq_uop[resp.uop.stq_idx] connect iresp[0].bits.data, resp.data connect wb_slow_wakeups[0].valid, UInt<1>(0h1) connect wb_slow_wakeups[0].bits.uop, stq_uop[resp.uop.stq_idx] connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) connect stq_debug_wb_data[resp.uop.stq_idx], resp.data when io.dmem.store_ack[0].valid : connect stq_succeeded[io.dmem.store_ack[0].bits.uop.stq_idx], UInt<1>(0h1) node _T_1676 = and(dmem_resp_fired[0], wb_ldst_forward_valid[0]) when _T_1676 : skip else : node _T_1677 = eq(dmem_resp_fired[0], UInt<1>(0h0)) node _T_1678 = and(_T_1677, wb_ldst_forward_valid[0]) when _T_1678 : wire size : UInt<2> connect size, stq_uop[wb_ldst_forward_stq_idx[0]].mem_size node _T_1679 = eq(size, UInt<1>(0h0)) node _T_1680 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 7, 0) node _T_1681 = cat(_T_1680, _T_1680) node _T_1682 = cat(_T_1681, _T_1681) node _T_1683 = cat(_T_1682, _T_1682) node _T_1684 = eq(size, UInt<1>(0h1)) node _T_1685 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 15, 0) node _T_1686 = cat(_T_1685, _T_1685) node _T_1687 = cat(_T_1686, _T_1686) node _T_1688 = eq(size, UInt<2>(0h2)) node _T_1689 = bits(stq_data[wb_ldst_forward_stq_idx[0]].bits, 31, 0) node _T_1690 = cat(_T_1689, _T_1689) node _T_1691 = mux(_T_1688, _T_1690, stq_data[wb_ldst_forward_stq_idx[0]].bits) node _T_1692 = mux(_T_1684, _T_1687, _T_1691) node _T_1693 = mux(_T_1679, _T_1683, _T_1692) wire size_1 : UInt<2> connect size_1, wb_ldst_forward_e[0].uop.mem_size node _wb_slow_wakeups_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h0)) connect wb_slow_wakeups[0].valid, _wb_slow_wakeups_0_valid_T connect wb_slow_wakeups[0].bits.uop, wb_ldst_forward_e[0].uop connect wb_slow_wakeups[0].bits.speculative_mask, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.rebusy, UInt<1>(0h0) connect wb_slow_wakeups[0].bits.bypassable, UInt<1>(0h0) node _iresp_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h0)) connect iresp[0].valid, _iresp_0_valid_T node _fresp_0_valid_T = eq(wb_ldst_forward_e[0].uop.dst_rtype, UInt<2>(0h1)) connect fresp[0].valid, _fresp_0_valid_T connect iresp[0].bits.uop, wb_ldst_forward_e[0].uop connect fresp[0].bits.uop, wb_ldst_forward_e[0].uop node _iresp_0_bits_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _iresp_0_bits_data_shifted_T_1 = bits(_T_1693, 63, 32) node _iresp_0_bits_data_shifted_T_2 = bits(_T_1693, 31, 0) node iresp_0_bits_data_shifted = mux(_iresp_0_bits_data_shifted_T, _iresp_0_bits_data_shifted_T_1, _iresp_0_bits_data_shifted_T_2) node iresp_0_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node iresp_0_bits_data_zeroed = mux(iresp_0_bits_data_doZero, UInt<1>(0h0), iresp_0_bits_data_shifted) node _iresp_0_bits_data_T = eq(size_1, UInt<2>(0h2)) node _iresp_0_bits_data_T_1 = or(_iresp_0_bits_data_T, iresp_0_bits_data_doZero) node _iresp_0_bits_data_T_2 = bits(iresp_0_bits_data_zeroed, 31, 31) node _iresp_0_bits_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_2) node _iresp_0_bits_data_T_4 = mux(_iresp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _iresp_0_bits_data_T_5 = bits(_T_1693, 63, 32) node _iresp_0_bits_data_T_6 = mux(_iresp_0_bits_data_T_1, _iresp_0_bits_data_T_4, _iresp_0_bits_data_T_5) node _iresp_0_bits_data_T_7 = cat(_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed) node _iresp_0_bits_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _iresp_0_bits_data_shifted_T_4 = bits(_iresp_0_bits_data_T_7, 31, 16) node _iresp_0_bits_data_shifted_T_5 = bits(_iresp_0_bits_data_T_7, 15, 0) node iresp_0_bits_data_shifted_1 = mux(_iresp_0_bits_data_shifted_T_3, _iresp_0_bits_data_shifted_T_4, _iresp_0_bits_data_shifted_T_5) node iresp_0_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node iresp_0_bits_data_zeroed_1 = mux(iresp_0_bits_data_doZero_1, UInt<1>(0h0), iresp_0_bits_data_shifted_1) node _iresp_0_bits_data_T_8 = eq(size_1, UInt<1>(0h1)) node _iresp_0_bits_data_T_9 = or(_iresp_0_bits_data_T_8, iresp_0_bits_data_doZero_1) node _iresp_0_bits_data_T_10 = bits(iresp_0_bits_data_zeroed_1, 15, 15) node _iresp_0_bits_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_10) node _iresp_0_bits_data_T_12 = mux(_iresp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _iresp_0_bits_data_T_13 = bits(_iresp_0_bits_data_T_7, 63, 16) node _iresp_0_bits_data_T_14 = mux(_iresp_0_bits_data_T_9, _iresp_0_bits_data_T_12, _iresp_0_bits_data_T_13) node _iresp_0_bits_data_T_15 = cat(_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1) node _iresp_0_bits_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _iresp_0_bits_data_shifted_T_7 = bits(_iresp_0_bits_data_T_15, 15, 8) node _iresp_0_bits_data_shifted_T_8 = bits(_iresp_0_bits_data_T_15, 7, 0) node iresp_0_bits_data_shifted_2 = mux(_iresp_0_bits_data_shifted_T_6, _iresp_0_bits_data_shifted_T_7, _iresp_0_bits_data_shifted_T_8) node iresp_0_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node iresp_0_bits_data_zeroed_2 = mux(iresp_0_bits_data_doZero_2, UInt<1>(0h0), iresp_0_bits_data_shifted_2) node _iresp_0_bits_data_T_16 = eq(size_1, UInt<1>(0h0)) node _iresp_0_bits_data_T_17 = or(_iresp_0_bits_data_T_16, iresp_0_bits_data_doZero_2) node _iresp_0_bits_data_T_18 = bits(iresp_0_bits_data_zeroed_2, 7, 7) node _iresp_0_bits_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _iresp_0_bits_data_T_18) node _iresp_0_bits_data_T_20 = mux(_iresp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _iresp_0_bits_data_T_21 = bits(_iresp_0_bits_data_T_15, 63, 8) node _iresp_0_bits_data_T_22 = mux(_iresp_0_bits_data_T_17, _iresp_0_bits_data_T_20, _iresp_0_bits_data_T_21) node _iresp_0_bits_data_T_23 = cat(_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2) connect iresp[0].bits.data, _iresp_0_bits_data_T_23 node _fresp_0_bits_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _fresp_0_bits_data_shifted_T_1 = bits(_T_1693, 63, 32) node _fresp_0_bits_data_shifted_T_2 = bits(_T_1693, 31, 0) node fresp_0_bits_data_shifted = mux(_fresp_0_bits_data_shifted_T, _fresp_0_bits_data_shifted_T_1, _fresp_0_bits_data_shifted_T_2) node fresp_0_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node fresp_0_bits_data_zeroed = mux(fresp_0_bits_data_doZero, UInt<1>(0h0), fresp_0_bits_data_shifted) node _fresp_0_bits_data_T = eq(size_1, UInt<2>(0h2)) node _fresp_0_bits_data_T_1 = or(_fresp_0_bits_data_T, fresp_0_bits_data_doZero) node _fresp_0_bits_data_T_2 = bits(fresp_0_bits_data_zeroed, 31, 31) node _fresp_0_bits_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_2) node _fresp_0_bits_data_T_4 = mux(_fresp_0_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _fresp_0_bits_data_T_5 = bits(_T_1693, 63, 32) node _fresp_0_bits_data_T_6 = mux(_fresp_0_bits_data_T_1, _fresp_0_bits_data_T_4, _fresp_0_bits_data_T_5) node _fresp_0_bits_data_T_7 = cat(_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed) node _fresp_0_bits_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _fresp_0_bits_data_shifted_T_4 = bits(_fresp_0_bits_data_T_7, 31, 16) node _fresp_0_bits_data_shifted_T_5 = bits(_fresp_0_bits_data_T_7, 15, 0) node fresp_0_bits_data_shifted_1 = mux(_fresp_0_bits_data_shifted_T_3, _fresp_0_bits_data_shifted_T_4, _fresp_0_bits_data_shifted_T_5) node fresp_0_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node fresp_0_bits_data_zeroed_1 = mux(fresp_0_bits_data_doZero_1, UInt<1>(0h0), fresp_0_bits_data_shifted_1) node _fresp_0_bits_data_T_8 = eq(size_1, UInt<1>(0h1)) node _fresp_0_bits_data_T_9 = or(_fresp_0_bits_data_T_8, fresp_0_bits_data_doZero_1) node _fresp_0_bits_data_T_10 = bits(fresp_0_bits_data_zeroed_1, 15, 15) node _fresp_0_bits_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_10) node _fresp_0_bits_data_T_12 = mux(_fresp_0_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _fresp_0_bits_data_T_13 = bits(_fresp_0_bits_data_T_7, 63, 16) node _fresp_0_bits_data_T_14 = mux(_fresp_0_bits_data_T_9, _fresp_0_bits_data_T_12, _fresp_0_bits_data_T_13) node _fresp_0_bits_data_T_15 = cat(_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1) node _fresp_0_bits_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _fresp_0_bits_data_shifted_T_7 = bits(_fresp_0_bits_data_T_15, 15, 8) node _fresp_0_bits_data_shifted_T_8 = bits(_fresp_0_bits_data_T_15, 7, 0) node fresp_0_bits_data_shifted_2 = mux(_fresp_0_bits_data_shifted_T_6, _fresp_0_bits_data_shifted_T_7, _fresp_0_bits_data_shifted_T_8) node fresp_0_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node fresp_0_bits_data_zeroed_2 = mux(fresp_0_bits_data_doZero_2, UInt<1>(0h0), fresp_0_bits_data_shifted_2) node _fresp_0_bits_data_T_16 = eq(size_1, UInt<1>(0h0)) node _fresp_0_bits_data_T_17 = or(_fresp_0_bits_data_T_16, fresp_0_bits_data_doZero_2) node _fresp_0_bits_data_T_18 = bits(fresp_0_bits_data_zeroed_2, 7, 7) node _fresp_0_bits_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _fresp_0_bits_data_T_18) node _fresp_0_bits_data_T_20 = mux(_fresp_0_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _fresp_0_bits_data_T_21 = bits(_fresp_0_bits_data_T_15, 63, 8) node _fresp_0_bits_data_T_22 = mux(_fresp_0_bits_data_T_17, _fresp_0_bits_data_T_20, _fresp_0_bits_data_T_21) node _fresp_0_bits_data_T_23 = cat(_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2) connect fresp[0].bits.data, _fresp_0_bits_data_T_23 node _T_1694 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1695 = bits(_T_1694, 4, 0) connect ldq_will_succeed[_T_1695], UInt<1>(0h1) node _T_1696 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1697 = bits(_T_1696, 4, 0) connect ldq_forward_std_val[_T_1697], UInt<1>(0h1) node _T_1698 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1699 = bits(_T_1698, 4, 0) connect ldq_forward_stq_idx[_T_1699], wb_ldst_forward_stq_idx[0] node _T_1700 = or(wb_ldst_forward_ldq_idx[0], UInt<5>(0h0)) node _T_1701 = bits(_T_1700, 4, 0) node _ldq_debug_wb_data_shifted_T = bits(wb_ldst_forward_ld_addr[0], 2, 2) node _ldq_debug_wb_data_shifted_T_1 = bits(_T_1693, 63, 32) node _ldq_debug_wb_data_shifted_T_2 = bits(_T_1693, 31, 0) node ldq_debug_wb_data_shifted = mux(_ldq_debug_wb_data_shifted_T, _ldq_debug_wb_data_shifted_T_1, _ldq_debug_wb_data_shifted_T_2) node ldq_debug_wb_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed = mux(ldq_debug_wb_data_doZero, UInt<1>(0h0), ldq_debug_wb_data_shifted) node _ldq_debug_wb_data_T = eq(size_1, UInt<2>(0h2)) node _ldq_debug_wb_data_T_1 = or(_ldq_debug_wb_data_T, ldq_debug_wb_data_doZero) node _ldq_debug_wb_data_T_2 = bits(ldq_debug_wb_data_zeroed, 31, 31) node _ldq_debug_wb_data_T_3 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_2) node _ldq_debug_wb_data_T_4 = mux(_ldq_debug_wb_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0)) node _ldq_debug_wb_data_T_5 = bits(_T_1693, 63, 32) node _ldq_debug_wb_data_T_6 = mux(_ldq_debug_wb_data_T_1, _ldq_debug_wb_data_T_4, _ldq_debug_wb_data_T_5) node _ldq_debug_wb_data_T_7 = cat(_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed) node _ldq_debug_wb_data_shifted_T_3 = bits(wb_ldst_forward_ld_addr[0], 1, 1) node _ldq_debug_wb_data_shifted_T_4 = bits(_ldq_debug_wb_data_T_7, 31, 16) node _ldq_debug_wb_data_shifted_T_5 = bits(_ldq_debug_wb_data_T_7, 15, 0) node ldq_debug_wb_data_shifted_1 = mux(_ldq_debug_wb_data_shifted_T_3, _ldq_debug_wb_data_shifted_T_4, _ldq_debug_wb_data_shifted_T_5) node ldq_debug_wb_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed_1 = mux(ldq_debug_wb_data_doZero_1, UInt<1>(0h0), ldq_debug_wb_data_shifted_1) node _ldq_debug_wb_data_T_8 = eq(size_1, UInt<1>(0h1)) node _ldq_debug_wb_data_T_9 = or(_ldq_debug_wb_data_T_8, ldq_debug_wb_data_doZero_1) node _ldq_debug_wb_data_T_10 = bits(ldq_debug_wb_data_zeroed_1, 15, 15) node _ldq_debug_wb_data_T_11 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_10) node _ldq_debug_wb_data_T_12 = mux(_ldq_debug_wb_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0)) node _ldq_debug_wb_data_T_13 = bits(_ldq_debug_wb_data_T_7, 63, 16) node _ldq_debug_wb_data_T_14 = mux(_ldq_debug_wb_data_T_9, _ldq_debug_wb_data_T_12, _ldq_debug_wb_data_T_13) node _ldq_debug_wb_data_T_15 = cat(_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1) node _ldq_debug_wb_data_shifted_T_6 = bits(wb_ldst_forward_ld_addr[0], 0, 0) node _ldq_debug_wb_data_shifted_T_7 = bits(_ldq_debug_wb_data_T_15, 15, 8) node _ldq_debug_wb_data_shifted_T_8 = bits(_ldq_debug_wb_data_T_15, 7, 0) node ldq_debug_wb_data_shifted_2 = mux(_ldq_debug_wb_data_shifted_T_6, _ldq_debug_wb_data_shifted_T_7, _ldq_debug_wb_data_shifted_T_8) node ldq_debug_wb_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0)) node ldq_debug_wb_data_zeroed_2 = mux(ldq_debug_wb_data_doZero_2, UInt<1>(0h0), ldq_debug_wb_data_shifted_2) node _ldq_debug_wb_data_T_16 = eq(size_1, UInt<1>(0h0)) node _ldq_debug_wb_data_T_17 = or(_ldq_debug_wb_data_T_16, ldq_debug_wb_data_doZero_2) node _ldq_debug_wb_data_T_18 = bits(ldq_debug_wb_data_zeroed_2, 7, 7) node _ldq_debug_wb_data_T_19 = and(wb_ldst_forward_e[0].uop.mem_signed, _ldq_debug_wb_data_T_18) node _ldq_debug_wb_data_T_20 = mux(_ldq_debug_wb_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0)) node _ldq_debug_wb_data_T_21 = bits(_ldq_debug_wb_data_T_15, 63, 8) node _ldq_debug_wb_data_T_22 = mux(_ldq_debug_wb_data_T_17, _ldq_debug_wb_data_T_20, _ldq_debug_wb_data_T_21) node _ldq_debug_wb_data_T_23 = cat(_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2) connect ldq_debug_wb_data[_T_1701], _ldq_debug_wb_data_T_23 connect wakeupArbs_0.io.in[0].valid, UInt<1>(0h0) invalidate wakeupArbs_0.io.in[0].bits.rebusy invalidate wakeupArbs_0.io.in[0].bits.speculative_mask invalidate wakeupArbs_0.io.in[0].bits.bypassable invalidate wakeupArbs_0.io.in[0].bits.uop.debug_tsrc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_fsrc invalidate wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if invalidate wakeupArbs_0.io.in[0].bits.uop.bp_debug_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if invalidate wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if invalidate wakeupArbs_0.io.in[0].bits.uop.fp_typ invalidate wakeupArbs_0.io.in[0].bits.uop.fp_rm invalidate wakeupArbs_0.io.in[0].bits.uop.fp_val invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_op invalidate wakeupArbs_0.io.in[0].bits.uop.fcn_dw invalidate wakeupArbs_0.io.in[0].bits.uop.frs3_en invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.dst_rtype invalidate wakeupArbs_0.io.in[0].bits.uop.lrs3 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs2 invalidate wakeupArbs_0.io.in[0].bits.uop.lrs1 invalidate wakeupArbs_0.io.in[0].bits.uop.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1 invalidate wakeupArbs_0.io.in[0].bits.uop.csr_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.flush_on_commit invalidate wakeupArbs_0.io.in[0].bits.uop.is_unique invalidate wakeupArbs_0.io.in[0].bits.uop.uses_stq invalidate wakeupArbs_0.io.in[0].bits.uop.uses_ldq invalidate wakeupArbs_0.io.in[0].bits.uop.mem_signed invalidate wakeupArbs_0.io.in[0].bits.uop.mem_size invalidate wakeupArbs_0.io.in[0].bits.uop.mem_cmd invalidate wakeupArbs_0.io.in[0].bits.uop.exc_cause invalidate wakeupArbs_0.io.in[0].bits.uop.exception invalidate wakeupArbs_0.io.in[0].bits.uop.stale_pdst invalidate wakeupArbs_0.io.in[0].bits.uop.ppred_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs3_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs2_busy invalidate wakeupArbs_0.io.in[0].bits.uop.prs1_busy invalidate wakeupArbs_0.io.in[0].bits.uop.ppred invalidate wakeupArbs_0.io.in[0].bits.uop.prs3 invalidate wakeupArbs_0.io.in[0].bits.uop.prs2 invalidate wakeupArbs_0.io.in[0].bits.uop.prs1 invalidate wakeupArbs_0.io.in[0].bits.uop.pdst invalidate wakeupArbs_0.io.in[0].bits.uop.rxq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.stq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.ldq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.rob_idx invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1 invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen invalidate wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst invalidate wakeupArbs_0.io.in[0].bits.uop.op2_sel invalidate wakeupArbs_0.io.in[0].bits.uop.op1_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_packed invalidate wakeupArbs_0.io.in[0].bits.uop.pimm invalidate wakeupArbs_0.io.in[0].bits.uop.imm_sel invalidate wakeupArbs_0.io.in[0].bits.uop.imm_rename invalidate wakeupArbs_0.io.in[0].bits.uop.taken invalidate wakeupArbs_0.io.in[0].bits.uop.pc_lob invalidate wakeupArbs_0.io.in[0].bits.uop.edge_inst invalidate wakeupArbs_0.io.in[0].bits.uop.ftq_idx invalidate wakeupArbs_0.io.in[0].bits.uop.is_mov invalidate wakeupArbs_0.io.in[0].bits.uop.is_rocc invalidate wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc invalidate wakeupArbs_0.io.in[0].bits.uop.is_eret invalidate wakeupArbs_0.io.in[0].bits.uop.is_amo invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfence invalidate wakeupArbs_0.io.in[0].bits.uop.is_fencei invalidate wakeupArbs_0.io.in[0].bits.uop.is_fence invalidate wakeupArbs_0.io.in[0].bits.uop.is_sfb invalidate wakeupArbs_0.io.in[0].bits.uop.br_type invalidate wakeupArbs_0.io.in[0].bits.uop.br_tag invalidate wakeupArbs_0.io.in[0].bits.uop.br_mask invalidate wakeupArbs_0.io.in[0].bits.uop.dis_col_sel invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen invalidate wakeupArbs_0.io.in[0].bits.uop.iw_issued invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[0] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[1] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[2] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[3] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[4] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[5] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[6] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[7] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[8] invalidate wakeupArbs_0.io.in[0].bits.uop.fu_code[9] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[0] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[1] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[2] invalidate wakeupArbs_0.io.in[0].bits.uop.iq_type[3] invalidate wakeupArbs_0.io.in[0].bits.uop.debug_pc invalidate wakeupArbs_0.io.in[0].bits.uop.is_rvc invalidate wakeupArbs_0.io.in[0].bits.uop.debug_inst invalidate wakeupArbs_0.io.in[0].bits.uop.inst wire slow_wakeups_0_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}} connect slow_wakeups_0_out, wb_slow_wakeups[0] node _slow_wakeups_0_out_bits_uop_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _slow_wakeups_0_out_bits_uop_br_mask_T_1 = and(wb_slow_wakeups[0].bits.uop.br_mask, _slow_wakeups_0_out_bits_uop_br_mask_T) connect slow_wakeups_0_out.bits.uop.br_mask, _slow_wakeups_0_out_bits_uop_br_mask_T_1 node _slow_wakeups_0_out_valid_T = and(io.core.brupdate.b1.mispredict_mask, wb_slow_wakeups[0].bits.uop.br_mask) node _slow_wakeups_0_out_valid_T_1 = neq(_slow_wakeups_0_out_valid_T, UInt<1>(0h0)) node _slow_wakeups_0_out_valid_T_2 = or(_slow_wakeups_0_out_valid_T_1, io.core.exception) node _slow_wakeups_0_out_valid_T_3 = eq(_slow_wakeups_0_out_valid_T_2, UInt<1>(0h0)) node _slow_wakeups_0_out_valid_T_4 = and(wb_slow_wakeups[0].valid, _slow_wakeups_0_out_valid_T_3) connect slow_wakeups_0_out.valid, _slow_wakeups_0_out_valid_T_4 reg slow_wakeups_0_REG : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}, clock connect slow_wakeups_0_REG, slow_wakeups_0_out connect slow_wakeups[0], slow_wakeups_0_REG when slow_wakeups[0].valid : when spec_wakeups[0].valid : node _T_1702 = eq(slow_wakeups[0].bits.uop.ldq_idx, spec_wakeups[0].bits.uop.ldq_idx) node _T_1703 = asUInt(reset) node _T_1704 = eq(_T_1703, UInt<1>(0h0)) when _T_1704 : node _T_1705 = eq(_T_1702, UInt<1>(0h0)) when _T_1705 : printf(clock, UInt<1>(0h1), "Assertion failed\n at lsu.scala:1651 assert(slow_wakeups(w).bits.uop.ldq_idx === spec_wakeups(w).bits.uop.ldq_idx)\n") : printf_86 assert(clock, _T_1702, UInt<1>(0h1), "") : assert_86 else : connect wakeupArbs_0.io.in[0].valid, slow_wakeups[0].valid connect wakeupArbs_0.io.in[0].bits.rebusy, slow_wakeups[0].bits.rebusy connect wakeupArbs_0.io.in[0].bits.speculative_mask, slow_wakeups[0].bits.speculative_mask connect wakeupArbs_0.io.in[0].bits.bypassable, slow_wakeups[0].bits.bypassable connect wakeupArbs_0.io.in[0].bits.uop.debug_tsrc, slow_wakeups[0].bits.uop.debug_tsrc connect wakeupArbs_0.io.in[0].bits.uop.debug_fsrc, slow_wakeups[0].bits.uop.debug_fsrc connect wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if, slow_wakeups[0].bits.uop.bp_xcpt_if connect wakeupArbs_0.io.in[0].bits.uop.bp_debug_if, slow_wakeups[0].bits.uop.bp_debug_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if, slow_wakeups[0].bits.uop.xcpt_ma_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if, slow_wakeups[0].bits.uop.xcpt_ae_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if, slow_wakeups[0].bits.uop.xcpt_pf_if connect wakeupArbs_0.io.in[0].bits.uop.fp_typ, slow_wakeups[0].bits.uop.fp_typ connect wakeupArbs_0.io.in[0].bits.uop.fp_rm, slow_wakeups[0].bits.uop.fp_rm connect wakeupArbs_0.io.in[0].bits.uop.fp_val, slow_wakeups[0].bits.uop.fp_val connect wakeupArbs_0.io.in[0].bits.uop.fcn_op, slow_wakeups[0].bits.uop.fcn_op connect wakeupArbs_0.io.in[0].bits.uop.fcn_dw, slow_wakeups[0].bits.uop.fcn_dw connect wakeupArbs_0.io.in[0].bits.uop.frs3_en, slow_wakeups[0].bits.uop.frs3_en connect wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype, slow_wakeups[0].bits.uop.lrs2_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype, slow_wakeups[0].bits.uop.lrs1_rtype connect wakeupArbs_0.io.in[0].bits.uop.dst_rtype, slow_wakeups[0].bits.uop.dst_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs3, slow_wakeups[0].bits.uop.lrs3 connect wakeupArbs_0.io.in[0].bits.uop.lrs2, slow_wakeups[0].bits.uop.lrs2 connect wakeupArbs_0.io.in[0].bits.uop.lrs1, slow_wakeups[0].bits.uop.lrs1 connect wakeupArbs_0.io.in[0].bits.uop.ldst, slow_wakeups[0].bits.uop.ldst connect wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1, slow_wakeups[0].bits.uop.ldst_is_rs1 connect wakeupArbs_0.io.in[0].bits.uop.csr_cmd, slow_wakeups[0].bits.uop.csr_cmd connect wakeupArbs_0.io.in[0].bits.uop.flush_on_commit, slow_wakeups[0].bits.uop.flush_on_commit connect wakeupArbs_0.io.in[0].bits.uop.is_unique, slow_wakeups[0].bits.uop.is_unique connect wakeupArbs_0.io.in[0].bits.uop.uses_stq, slow_wakeups[0].bits.uop.uses_stq connect wakeupArbs_0.io.in[0].bits.uop.uses_ldq, slow_wakeups[0].bits.uop.uses_ldq connect wakeupArbs_0.io.in[0].bits.uop.mem_signed, slow_wakeups[0].bits.uop.mem_signed connect wakeupArbs_0.io.in[0].bits.uop.mem_size, slow_wakeups[0].bits.uop.mem_size connect wakeupArbs_0.io.in[0].bits.uop.mem_cmd, slow_wakeups[0].bits.uop.mem_cmd connect wakeupArbs_0.io.in[0].bits.uop.exc_cause, slow_wakeups[0].bits.uop.exc_cause connect wakeupArbs_0.io.in[0].bits.uop.exception, slow_wakeups[0].bits.uop.exception connect wakeupArbs_0.io.in[0].bits.uop.stale_pdst, slow_wakeups[0].bits.uop.stale_pdst connect wakeupArbs_0.io.in[0].bits.uop.ppred_busy, slow_wakeups[0].bits.uop.ppred_busy connect wakeupArbs_0.io.in[0].bits.uop.prs3_busy, slow_wakeups[0].bits.uop.prs3_busy connect wakeupArbs_0.io.in[0].bits.uop.prs2_busy, slow_wakeups[0].bits.uop.prs2_busy connect wakeupArbs_0.io.in[0].bits.uop.prs1_busy, slow_wakeups[0].bits.uop.prs1_busy connect wakeupArbs_0.io.in[0].bits.uop.ppred, slow_wakeups[0].bits.uop.ppred connect wakeupArbs_0.io.in[0].bits.uop.prs3, slow_wakeups[0].bits.uop.prs3 connect wakeupArbs_0.io.in[0].bits.uop.prs2, slow_wakeups[0].bits.uop.prs2 connect wakeupArbs_0.io.in[0].bits.uop.prs1, slow_wakeups[0].bits.uop.prs1 connect wakeupArbs_0.io.in[0].bits.uop.pdst, slow_wakeups[0].bits.uop.pdst connect wakeupArbs_0.io.in[0].bits.uop.rxq_idx, slow_wakeups[0].bits.uop.rxq_idx connect wakeupArbs_0.io.in[0].bits.uop.stq_idx, slow_wakeups[0].bits.uop.stq_idx connect wakeupArbs_0.io.in[0].bits.uop.ldq_idx, slow_wakeups[0].bits.uop.ldq_idx connect wakeupArbs_0.io.in[0].bits.uop.rob_idx, slow_wakeups[0].bits.uop.rob_idx connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec, slow_wakeups[0].bits.uop.fp_ctrl.vec connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags, slow_wakeups[0].bits.uop.fp_ctrl.wflags connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt, slow_wakeups[0].bits.uop.fp_ctrl.sqrt connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div, slow_wakeups[0].bits.uop.fp_ctrl.div connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma, slow_wakeups[0].bits.uop.fp_ctrl.fma connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe, slow_wakeups[0].bits.uop.fp_ctrl.fastpipe connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint, slow_wakeups[0].bits.uop.fp_ctrl.toint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint, slow_wakeups[0].bits.uop.fp_ctrl.fromint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut, slow_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn, slow_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23, slow_wakeups[0].bits.uop.fp_ctrl.swap23 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12, slow_wakeups[0].bits.uop.fp_ctrl.swap12 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3, slow_wakeups[0].bits.uop.fp_ctrl.ren3 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2, slow_wakeups[0].bits.uop.fp_ctrl.ren2 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1, slow_wakeups[0].bits.uop.fp_ctrl.ren1 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen, slow_wakeups[0].bits.uop.fp_ctrl.wen connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst, slow_wakeups[0].bits.uop.fp_ctrl.ldst connect wakeupArbs_0.io.in[0].bits.uop.op2_sel, slow_wakeups[0].bits.uop.op2_sel connect wakeupArbs_0.io.in[0].bits.uop.op1_sel, slow_wakeups[0].bits.uop.op1_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_packed, slow_wakeups[0].bits.uop.imm_packed connect wakeupArbs_0.io.in[0].bits.uop.pimm, slow_wakeups[0].bits.uop.pimm connect wakeupArbs_0.io.in[0].bits.uop.imm_sel, slow_wakeups[0].bits.uop.imm_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_rename, slow_wakeups[0].bits.uop.imm_rename connect wakeupArbs_0.io.in[0].bits.uop.taken, slow_wakeups[0].bits.uop.taken connect wakeupArbs_0.io.in[0].bits.uop.pc_lob, slow_wakeups[0].bits.uop.pc_lob connect wakeupArbs_0.io.in[0].bits.uop.edge_inst, slow_wakeups[0].bits.uop.edge_inst connect wakeupArbs_0.io.in[0].bits.uop.ftq_idx, slow_wakeups[0].bits.uop.ftq_idx connect wakeupArbs_0.io.in[0].bits.uop.is_mov, slow_wakeups[0].bits.uop.is_mov connect wakeupArbs_0.io.in[0].bits.uop.is_rocc, slow_wakeups[0].bits.uop.is_rocc connect wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc, slow_wakeups[0].bits.uop.is_sys_pc2epc connect wakeupArbs_0.io.in[0].bits.uop.is_eret, slow_wakeups[0].bits.uop.is_eret connect wakeupArbs_0.io.in[0].bits.uop.is_amo, slow_wakeups[0].bits.uop.is_amo connect wakeupArbs_0.io.in[0].bits.uop.is_sfence, slow_wakeups[0].bits.uop.is_sfence connect wakeupArbs_0.io.in[0].bits.uop.is_fencei, slow_wakeups[0].bits.uop.is_fencei connect wakeupArbs_0.io.in[0].bits.uop.is_fence, slow_wakeups[0].bits.uop.is_fence connect wakeupArbs_0.io.in[0].bits.uop.is_sfb, slow_wakeups[0].bits.uop.is_sfb connect wakeupArbs_0.io.in[0].bits.uop.br_type, slow_wakeups[0].bits.uop.br_type connect wakeupArbs_0.io.in[0].bits.uop.br_tag, slow_wakeups[0].bits.uop.br_tag connect wakeupArbs_0.io.in[0].bits.uop.br_mask, slow_wakeups[0].bits.uop.br_mask connect wakeupArbs_0.io.in[0].bits.uop.dis_col_sel, slow_wakeups[0].bits.uop.dis_col_sel connect wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint, slow_wakeups[0].bits.uop.iw_p3_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint, slow_wakeups[0].bits.uop.iw_p2_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint, slow_wakeups[0].bits.uop.iw_p1_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child, slow_wakeups[0].bits.uop.iw_p2_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child, slow_wakeups[0].bits.uop.iw_p1_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen, slow_wakeups[0].bits.uop.iw_issued_partial_dgen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen, slow_wakeups[0].bits.uop.iw_issued_partial_agen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued, slow_wakeups[0].bits.uop.iw_issued connect wakeupArbs_0.io.in[0].bits.uop.fu_code[0], slow_wakeups[0].bits.uop.fu_code[0] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[1], slow_wakeups[0].bits.uop.fu_code[1] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[2], slow_wakeups[0].bits.uop.fu_code[2] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[3], slow_wakeups[0].bits.uop.fu_code[3] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[4], slow_wakeups[0].bits.uop.fu_code[4] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[5], slow_wakeups[0].bits.uop.fu_code[5] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[6], slow_wakeups[0].bits.uop.fu_code[6] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[7], slow_wakeups[0].bits.uop.fu_code[7] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[8], slow_wakeups[0].bits.uop.fu_code[8] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[9], slow_wakeups[0].bits.uop.fu_code[9] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[0], slow_wakeups[0].bits.uop.iq_type[0] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[1], slow_wakeups[0].bits.uop.iq_type[1] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[2], slow_wakeups[0].bits.uop.iq_type[2] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[3], slow_wakeups[0].bits.uop.iq_type[3] connect wakeupArbs_0.io.in[0].bits.uop.debug_pc, slow_wakeups[0].bits.uop.debug_pc connect wakeupArbs_0.io.in[0].bits.uop.is_rvc, slow_wakeups[0].bits.uop.is_rvc connect wakeupArbs_0.io.in[0].bits.uop.debug_inst, slow_wakeups[0].bits.uop.debug_inst connect wakeupArbs_0.io.in[0].bits.uop.inst, slow_wakeups[0].bits.uop.inst else : when spec_wakeups[0].valid : connect wakeupArbs_0.io.in[0].valid, spec_wakeups[0].valid connect wakeupArbs_0.io.in[0].bits.rebusy, spec_wakeups[0].bits.rebusy connect wakeupArbs_0.io.in[0].bits.speculative_mask, spec_wakeups[0].bits.speculative_mask connect wakeupArbs_0.io.in[0].bits.bypassable, spec_wakeups[0].bits.bypassable connect wakeupArbs_0.io.in[0].bits.uop.debug_tsrc, spec_wakeups[0].bits.uop.debug_tsrc connect wakeupArbs_0.io.in[0].bits.uop.debug_fsrc, spec_wakeups[0].bits.uop.debug_fsrc connect wakeupArbs_0.io.in[0].bits.uop.bp_xcpt_if, spec_wakeups[0].bits.uop.bp_xcpt_if connect wakeupArbs_0.io.in[0].bits.uop.bp_debug_if, spec_wakeups[0].bits.uop.bp_debug_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ma_if, spec_wakeups[0].bits.uop.xcpt_ma_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_ae_if, spec_wakeups[0].bits.uop.xcpt_ae_if connect wakeupArbs_0.io.in[0].bits.uop.xcpt_pf_if, spec_wakeups[0].bits.uop.xcpt_pf_if connect wakeupArbs_0.io.in[0].bits.uop.fp_typ, spec_wakeups[0].bits.uop.fp_typ connect wakeupArbs_0.io.in[0].bits.uop.fp_rm, spec_wakeups[0].bits.uop.fp_rm connect wakeupArbs_0.io.in[0].bits.uop.fp_val, spec_wakeups[0].bits.uop.fp_val connect wakeupArbs_0.io.in[0].bits.uop.fcn_op, spec_wakeups[0].bits.uop.fcn_op connect wakeupArbs_0.io.in[0].bits.uop.fcn_dw, spec_wakeups[0].bits.uop.fcn_dw connect wakeupArbs_0.io.in[0].bits.uop.frs3_en, spec_wakeups[0].bits.uop.frs3_en connect wakeupArbs_0.io.in[0].bits.uop.lrs2_rtype, spec_wakeups[0].bits.uop.lrs2_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs1_rtype, spec_wakeups[0].bits.uop.lrs1_rtype connect wakeupArbs_0.io.in[0].bits.uop.dst_rtype, spec_wakeups[0].bits.uop.dst_rtype connect wakeupArbs_0.io.in[0].bits.uop.lrs3, spec_wakeups[0].bits.uop.lrs3 connect wakeupArbs_0.io.in[0].bits.uop.lrs2, spec_wakeups[0].bits.uop.lrs2 connect wakeupArbs_0.io.in[0].bits.uop.lrs1, spec_wakeups[0].bits.uop.lrs1 connect wakeupArbs_0.io.in[0].bits.uop.ldst, spec_wakeups[0].bits.uop.ldst connect wakeupArbs_0.io.in[0].bits.uop.ldst_is_rs1, spec_wakeups[0].bits.uop.ldst_is_rs1 connect wakeupArbs_0.io.in[0].bits.uop.csr_cmd, spec_wakeups[0].bits.uop.csr_cmd connect wakeupArbs_0.io.in[0].bits.uop.flush_on_commit, spec_wakeups[0].bits.uop.flush_on_commit connect wakeupArbs_0.io.in[0].bits.uop.is_unique, spec_wakeups[0].bits.uop.is_unique connect wakeupArbs_0.io.in[0].bits.uop.uses_stq, spec_wakeups[0].bits.uop.uses_stq connect wakeupArbs_0.io.in[0].bits.uop.uses_ldq, spec_wakeups[0].bits.uop.uses_ldq connect wakeupArbs_0.io.in[0].bits.uop.mem_signed, spec_wakeups[0].bits.uop.mem_signed connect wakeupArbs_0.io.in[0].bits.uop.mem_size, spec_wakeups[0].bits.uop.mem_size connect wakeupArbs_0.io.in[0].bits.uop.mem_cmd, spec_wakeups[0].bits.uop.mem_cmd connect wakeupArbs_0.io.in[0].bits.uop.exc_cause, spec_wakeups[0].bits.uop.exc_cause connect wakeupArbs_0.io.in[0].bits.uop.exception, spec_wakeups[0].bits.uop.exception connect wakeupArbs_0.io.in[0].bits.uop.stale_pdst, spec_wakeups[0].bits.uop.stale_pdst connect wakeupArbs_0.io.in[0].bits.uop.ppred_busy, spec_wakeups[0].bits.uop.ppred_busy connect wakeupArbs_0.io.in[0].bits.uop.prs3_busy, spec_wakeups[0].bits.uop.prs3_busy connect wakeupArbs_0.io.in[0].bits.uop.prs2_busy, spec_wakeups[0].bits.uop.prs2_busy connect wakeupArbs_0.io.in[0].bits.uop.prs1_busy, spec_wakeups[0].bits.uop.prs1_busy connect wakeupArbs_0.io.in[0].bits.uop.ppred, spec_wakeups[0].bits.uop.ppred connect wakeupArbs_0.io.in[0].bits.uop.prs3, spec_wakeups[0].bits.uop.prs3 connect wakeupArbs_0.io.in[0].bits.uop.prs2, spec_wakeups[0].bits.uop.prs2 connect wakeupArbs_0.io.in[0].bits.uop.prs1, spec_wakeups[0].bits.uop.prs1 connect wakeupArbs_0.io.in[0].bits.uop.pdst, spec_wakeups[0].bits.uop.pdst connect wakeupArbs_0.io.in[0].bits.uop.rxq_idx, spec_wakeups[0].bits.uop.rxq_idx connect wakeupArbs_0.io.in[0].bits.uop.stq_idx, spec_wakeups[0].bits.uop.stq_idx connect wakeupArbs_0.io.in[0].bits.uop.ldq_idx, spec_wakeups[0].bits.uop.ldq_idx connect wakeupArbs_0.io.in[0].bits.uop.rob_idx, spec_wakeups[0].bits.uop.rob_idx connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.vec, spec_wakeups[0].bits.uop.fp_ctrl.vec connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wflags, spec_wakeups[0].bits.uop.fp_ctrl.wflags connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.sqrt, spec_wakeups[0].bits.uop.fp_ctrl.sqrt connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.div, spec_wakeups[0].bits.uop.fp_ctrl.div connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fma, spec_wakeups[0].bits.uop.fp_ctrl.fma connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fastpipe, spec_wakeups[0].bits.uop.fp_ctrl.fastpipe connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.toint, spec_wakeups[0].bits.uop.fp_ctrl.toint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.fromint, spec_wakeups[0].bits.uop.fp_ctrl.fromint connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagOut, spec_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.typeTagIn, spec_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap23, spec_wakeups[0].bits.uop.fp_ctrl.swap23 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.swap12, spec_wakeups[0].bits.uop.fp_ctrl.swap12 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren3, spec_wakeups[0].bits.uop.fp_ctrl.ren3 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren2, spec_wakeups[0].bits.uop.fp_ctrl.ren2 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ren1, spec_wakeups[0].bits.uop.fp_ctrl.ren1 connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.wen, spec_wakeups[0].bits.uop.fp_ctrl.wen connect wakeupArbs_0.io.in[0].bits.uop.fp_ctrl.ldst, spec_wakeups[0].bits.uop.fp_ctrl.ldst connect wakeupArbs_0.io.in[0].bits.uop.op2_sel, spec_wakeups[0].bits.uop.op2_sel connect wakeupArbs_0.io.in[0].bits.uop.op1_sel, spec_wakeups[0].bits.uop.op1_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_packed, spec_wakeups[0].bits.uop.imm_packed connect wakeupArbs_0.io.in[0].bits.uop.pimm, spec_wakeups[0].bits.uop.pimm connect wakeupArbs_0.io.in[0].bits.uop.imm_sel, spec_wakeups[0].bits.uop.imm_sel connect wakeupArbs_0.io.in[0].bits.uop.imm_rename, spec_wakeups[0].bits.uop.imm_rename connect wakeupArbs_0.io.in[0].bits.uop.taken, spec_wakeups[0].bits.uop.taken connect wakeupArbs_0.io.in[0].bits.uop.pc_lob, spec_wakeups[0].bits.uop.pc_lob connect wakeupArbs_0.io.in[0].bits.uop.edge_inst, spec_wakeups[0].bits.uop.edge_inst connect wakeupArbs_0.io.in[0].bits.uop.ftq_idx, spec_wakeups[0].bits.uop.ftq_idx connect wakeupArbs_0.io.in[0].bits.uop.is_mov, spec_wakeups[0].bits.uop.is_mov connect wakeupArbs_0.io.in[0].bits.uop.is_rocc, spec_wakeups[0].bits.uop.is_rocc connect wakeupArbs_0.io.in[0].bits.uop.is_sys_pc2epc, spec_wakeups[0].bits.uop.is_sys_pc2epc connect wakeupArbs_0.io.in[0].bits.uop.is_eret, spec_wakeups[0].bits.uop.is_eret connect wakeupArbs_0.io.in[0].bits.uop.is_amo, spec_wakeups[0].bits.uop.is_amo connect wakeupArbs_0.io.in[0].bits.uop.is_sfence, spec_wakeups[0].bits.uop.is_sfence connect wakeupArbs_0.io.in[0].bits.uop.is_fencei, spec_wakeups[0].bits.uop.is_fencei connect wakeupArbs_0.io.in[0].bits.uop.is_fence, spec_wakeups[0].bits.uop.is_fence connect wakeupArbs_0.io.in[0].bits.uop.is_sfb, spec_wakeups[0].bits.uop.is_sfb connect wakeupArbs_0.io.in[0].bits.uop.br_type, spec_wakeups[0].bits.uop.br_type connect wakeupArbs_0.io.in[0].bits.uop.br_tag, spec_wakeups[0].bits.uop.br_tag connect wakeupArbs_0.io.in[0].bits.uop.br_mask, spec_wakeups[0].bits.uop.br_mask connect wakeupArbs_0.io.in[0].bits.uop.dis_col_sel, spec_wakeups[0].bits.uop.dis_col_sel connect wakeupArbs_0.io.in[0].bits.uop.iw_p3_bypass_hint, spec_wakeups[0].bits.uop.iw_p3_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_bypass_hint, spec_wakeups[0].bits.uop.iw_p2_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_bypass_hint, spec_wakeups[0].bits.uop.iw_p1_bypass_hint connect wakeupArbs_0.io.in[0].bits.uop.iw_p2_speculative_child, spec_wakeups[0].bits.uop.iw_p2_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_p1_speculative_child, spec_wakeups[0].bits.uop.iw_p1_speculative_child connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_dgen, spec_wakeups[0].bits.uop.iw_issued_partial_dgen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued_partial_agen, spec_wakeups[0].bits.uop.iw_issued_partial_agen connect wakeupArbs_0.io.in[0].bits.uop.iw_issued, spec_wakeups[0].bits.uop.iw_issued connect wakeupArbs_0.io.in[0].bits.uop.fu_code[0], spec_wakeups[0].bits.uop.fu_code[0] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[1], spec_wakeups[0].bits.uop.fu_code[1] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[2], spec_wakeups[0].bits.uop.fu_code[2] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[3], spec_wakeups[0].bits.uop.fu_code[3] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[4], spec_wakeups[0].bits.uop.fu_code[4] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[5], spec_wakeups[0].bits.uop.fu_code[5] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[6], spec_wakeups[0].bits.uop.fu_code[6] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[7], spec_wakeups[0].bits.uop.fu_code[7] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[8], spec_wakeups[0].bits.uop.fu_code[8] connect wakeupArbs_0.io.in[0].bits.uop.fu_code[9], spec_wakeups[0].bits.uop.fu_code[9] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[0], spec_wakeups[0].bits.uop.iq_type[0] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[1], spec_wakeups[0].bits.uop.iq_type[1] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[2], spec_wakeups[0].bits.uop.iq_type[2] connect wakeupArbs_0.io.in[0].bits.uop.iq_type[3], spec_wakeups[0].bits.uop.iq_type[3] connect wakeupArbs_0.io.in[0].bits.uop.debug_pc, spec_wakeups[0].bits.uop.debug_pc connect wakeupArbs_0.io.in[0].bits.uop.is_rvc, spec_wakeups[0].bits.uop.is_rvc connect wakeupArbs_0.io.in[0].bits.uop.debug_inst, spec_wakeups[0].bits.uop.debug_inst connect wakeupArbs_0.io.in[0].bits.uop.inst, spec_wakeups[0].bits.uop.inst connect wakeupArbs_0.io.in[0].bits.rebusy, UInt<1>(0h1) when stq_valid[0] : wire uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_1, stq_uop[0] node _stq_uop_0_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_0_br_mask_T_1 = and(uop_1.br_mask, _stq_uop_0_br_mask_T) connect stq_uop[0].br_mask, _stq_uop_0_br_mask_T_1 node _T_1706 = and(io.core.brupdate.b1.mispredict_mask, uop_1.br_mask) node _T_1707 = neq(_T_1706, UInt<1>(0h0)) node _T_1708 = or(_T_1707, UInt<1>(0h0)) when _T_1708 : connect stq_valid[0], UInt<1>(0h0) connect stq_addr[0].valid, UInt<1>(0h0) connect stq_data[0].valid, UInt<1>(0h0) node _T_1709 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[0].br_mask) node _T_1710 = neq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1710, UInt<1>(0h0)) node _T_1712 = and(_T_1711, stq_valid[0]) node _T_1713 = and(_T_1712, stq_committed[0]) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_87 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_87 when stq_valid[1] : wire uop_2 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_2, stq_uop[1] node _stq_uop_1_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_1_br_mask_T_1 = and(uop_2.br_mask, _stq_uop_1_br_mask_T) connect stq_uop[1].br_mask, _stq_uop_1_br_mask_T_1 node _T_1718 = and(io.core.brupdate.b1.mispredict_mask, uop_2.br_mask) node _T_1719 = neq(_T_1718, UInt<1>(0h0)) node _T_1720 = or(_T_1719, UInt<1>(0h0)) when _T_1720 : connect stq_valid[1], UInt<1>(0h0) connect stq_addr[1].valid, UInt<1>(0h0) connect stq_data[1].valid, UInt<1>(0h0) node _T_1721 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[1].br_mask) node _T_1722 = neq(_T_1721, UInt<1>(0h0)) node _T_1723 = or(_T_1722, UInt<1>(0h0)) node _T_1724 = and(_T_1723, stq_valid[1]) node _T_1725 = and(_T_1724, stq_committed[1]) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) node _T_1727 = asUInt(reset) node _T_1728 = eq(_T_1727, UInt<1>(0h0)) when _T_1728 : node _T_1729 = eq(_T_1726, UInt<1>(0h0)) when _T_1729 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_88 assert(clock, _T_1726, UInt<1>(0h1), "") : assert_88 when stq_valid[2] : wire uop_3 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_3, stq_uop[2] node _stq_uop_2_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_2_br_mask_T_1 = and(uop_3.br_mask, _stq_uop_2_br_mask_T) connect stq_uop[2].br_mask, _stq_uop_2_br_mask_T_1 node _T_1730 = and(io.core.brupdate.b1.mispredict_mask, uop_3.br_mask) node _T_1731 = neq(_T_1730, UInt<1>(0h0)) node _T_1732 = or(_T_1731, UInt<1>(0h0)) when _T_1732 : connect stq_valid[2], UInt<1>(0h0) connect stq_addr[2].valid, UInt<1>(0h0) connect stq_data[2].valid, UInt<1>(0h0) node _T_1733 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[2].br_mask) node _T_1734 = neq(_T_1733, UInt<1>(0h0)) node _T_1735 = or(_T_1734, UInt<1>(0h0)) node _T_1736 = and(_T_1735, stq_valid[2]) node _T_1737 = and(_T_1736, stq_committed[2]) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(_T_1738, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_89 assert(clock, _T_1738, UInt<1>(0h1), "") : assert_89 when stq_valid[3] : wire uop_4 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_4, stq_uop[3] node _stq_uop_3_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_3_br_mask_T_1 = and(uop_4.br_mask, _stq_uop_3_br_mask_T) connect stq_uop[3].br_mask, _stq_uop_3_br_mask_T_1 node _T_1742 = and(io.core.brupdate.b1.mispredict_mask, uop_4.br_mask) node _T_1743 = neq(_T_1742, UInt<1>(0h0)) node _T_1744 = or(_T_1743, UInt<1>(0h0)) when _T_1744 : connect stq_valid[3], UInt<1>(0h0) connect stq_addr[3].valid, UInt<1>(0h0) connect stq_data[3].valid, UInt<1>(0h0) node _T_1745 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[3].br_mask) node _T_1746 = neq(_T_1745, UInt<1>(0h0)) node _T_1747 = or(_T_1746, UInt<1>(0h0)) node _T_1748 = and(_T_1747, stq_valid[3]) node _T_1749 = and(_T_1748, stq_committed[3]) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) node _T_1751 = asUInt(reset) node _T_1752 = eq(_T_1751, UInt<1>(0h0)) when _T_1752 : node _T_1753 = eq(_T_1750, UInt<1>(0h0)) when _T_1753 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_90 assert(clock, _T_1750, UInt<1>(0h1), "") : assert_90 when stq_valid[4] : wire uop_5 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_5, stq_uop[4] node _stq_uop_4_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_4_br_mask_T_1 = and(uop_5.br_mask, _stq_uop_4_br_mask_T) connect stq_uop[4].br_mask, _stq_uop_4_br_mask_T_1 node _T_1754 = and(io.core.brupdate.b1.mispredict_mask, uop_5.br_mask) node _T_1755 = neq(_T_1754, UInt<1>(0h0)) node _T_1756 = or(_T_1755, UInt<1>(0h0)) when _T_1756 : connect stq_valid[4], UInt<1>(0h0) connect stq_addr[4].valid, UInt<1>(0h0) connect stq_data[4].valid, UInt<1>(0h0) node _T_1757 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[4].br_mask) node _T_1758 = neq(_T_1757, UInt<1>(0h0)) node _T_1759 = or(_T_1758, UInt<1>(0h0)) node _T_1760 = and(_T_1759, stq_valid[4]) node _T_1761 = and(_T_1760, stq_committed[4]) node _T_1762 = eq(_T_1761, UInt<1>(0h0)) node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(_T_1762, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_91 assert(clock, _T_1762, UInt<1>(0h1), "") : assert_91 when stq_valid[5] : wire uop_6 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_6, stq_uop[5] node _stq_uop_5_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_5_br_mask_T_1 = and(uop_6.br_mask, _stq_uop_5_br_mask_T) connect stq_uop[5].br_mask, _stq_uop_5_br_mask_T_1 node _T_1766 = and(io.core.brupdate.b1.mispredict_mask, uop_6.br_mask) node _T_1767 = neq(_T_1766, UInt<1>(0h0)) node _T_1768 = or(_T_1767, UInt<1>(0h0)) when _T_1768 : connect stq_valid[5], UInt<1>(0h0) connect stq_addr[5].valid, UInt<1>(0h0) connect stq_data[5].valid, UInt<1>(0h0) node _T_1769 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[5].br_mask) node _T_1770 = neq(_T_1769, UInt<1>(0h0)) node _T_1771 = or(_T_1770, UInt<1>(0h0)) node _T_1772 = and(_T_1771, stq_valid[5]) node _T_1773 = and(_T_1772, stq_committed[5]) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = asUInt(reset) node _T_1776 = eq(_T_1775, UInt<1>(0h0)) when _T_1776 : node _T_1777 = eq(_T_1774, UInt<1>(0h0)) when _T_1777 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_92 assert(clock, _T_1774, UInt<1>(0h1), "") : assert_92 when stq_valid[6] : wire uop_7 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_7, stq_uop[6] node _stq_uop_6_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_6_br_mask_T_1 = and(uop_7.br_mask, _stq_uop_6_br_mask_T) connect stq_uop[6].br_mask, _stq_uop_6_br_mask_T_1 node _T_1778 = and(io.core.brupdate.b1.mispredict_mask, uop_7.br_mask) node _T_1779 = neq(_T_1778, UInt<1>(0h0)) node _T_1780 = or(_T_1779, UInt<1>(0h0)) when _T_1780 : connect stq_valid[6], UInt<1>(0h0) connect stq_addr[6].valid, UInt<1>(0h0) connect stq_data[6].valid, UInt<1>(0h0) node _T_1781 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[6].br_mask) node _T_1782 = neq(_T_1781, UInt<1>(0h0)) node _T_1783 = or(_T_1782, UInt<1>(0h0)) node _T_1784 = and(_T_1783, stq_valid[6]) node _T_1785 = and(_T_1784, stq_committed[6]) node _T_1786 = eq(_T_1785, UInt<1>(0h0)) node _T_1787 = asUInt(reset) node _T_1788 = eq(_T_1787, UInt<1>(0h0)) when _T_1788 : node _T_1789 = eq(_T_1786, UInt<1>(0h0)) when _T_1789 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_93 assert(clock, _T_1786, UInt<1>(0h1), "") : assert_93 when stq_valid[7] : wire uop_8 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_8, stq_uop[7] node _stq_uop_7_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_7_br_mask_T_1 = and(uop_8.br_mask, _stq_uop_7_br_mask_T) connect stq_uop[7].br_mask, _stq_uop_7_br_mask_T_1 node _T_1790 = and(io.core.brupdate.b1.mispredict_mask, uop_8.br_mask) node _T_1791 = neq(_T_1790, UInt<1>(0h0)) node _T_1792 = or(_T_1791, UInt<1>(0h0)) when _T_1792 : connect stq_valid[7], UInt<1>(0h0) connect stq_addr[7].valid, UInt<1>(0h0) connect stq_data[7].valid, UInt<1>(0h0) node _T_1793 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[7].br_mask) node _T_1794 = neq(_T_1793, UInt<1>(0h0)) node _T_1795 = or(_T_1794, UInt<1>(0h0)) node _T_1796 = and(_T_1795, stq_valid[7]) node _T_1797 = and(_T_1796, stq_committed[7]) node _T_1798 = eq(_T_1797, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_94 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_94 when stq_valid[8] : wire uop_9 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_9, stq_uop[8] node _stq_uop_8_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_8_br_mask_T_1 = and(uop_9.br_mask, _stq_uop_8_br_mask_T) connect stq_uop[8].br_mask, _stq_uop_8_br_mask_T_1 node _T_1802 = and(io.core.brupdate.b1.mispredict_mask, uop_9.br_mask) node _T_1803 = neq(_T_1802, UInt<1>(0h0)) node _T_1804 = or(_T_1803, UInt<1>(0h0)) when _T_1804 : connect stq_valid[8], UInt<1>(0h0) connect stq_addr[8].valid, UInt<1>(0h0) connect stq_data[8].valid, UInt<1>(0h0) node _T_1805 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[8].br_mask) node _T_1806 = neq(_T_1805, UInt<1>(0h0)) node _T_1807 = or(_T_1806, UInt<1>(0h0)) node _T_1808 = and(_T_1807, stq_valid[8]) node _T_1809 = and(_T_1808, stq_committed[8]) node _T_1810 = eq(_T_1809, UInt<1>(0h0)) node _T_1811 = asUInt(reset) node _T_1812 = eq(_T_1811, UInt<1>(0h0)) when _T_1812 : node _T_1813 = eq(_T_1810, UInt<1>(0h0)) when _T_1813 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_95 assert(clock, _T_1810, UInt<1>(0h1), "") : assert_95 when stq_valid[9] : wire uop_10 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_10, stq_uop[9] node _stq_uop_9_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_9_br_mask_T_1 = and(uop_10.br_mask, _stq_uop_9_br_mask_T) connect stq_uop[9].br_mask, _stq_uop_9_br_mask_T_1 node _T_1814 = and(io.core.brupdate.b1.mispredict_mask, uop_10.br_mask) node _T_1815 = neq(_T_1814, UInt<1>(0h0)) node _T_1816 = or(_T_1815, UInt<1>(0h0)) when _T_1816 : connect stq_valid[9], UInt<1>(0h0) connect stq_addr[9].valid, UInt<1>(0h0) connect stq_data[9].valid, UInt<1>(0h0) node _T_1817 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[9].br_mask) node _T_1818 = neq(_T_1817, UInt<1>(0h0)) node _T_1819 = or(_T_1818, UInt<1>(0h0)) node _T_1820 = and(_T_1819, stq_valid[9]) node _T_1821 = and(_T_1820, stq_committed[9]) node _T_1822 = eq(_T_1821, UInt<1>(0h0)) node _T_1823 = asUInt(reset) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) when _T_1824 : node _T_1825 = eq(_T_1822, UInt<1>(0h0)) when _T_1825 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_96 assert(clock, _T_1822, UInt<1>(0h1), "") : assert_96 when stq_valid[10] : wire uop_11 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_11, stq_uop[10] node _stq_uop_10_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_10_br_mask_T_1 = and(uop_11.br_mask, _stq_uop_10_br_mask_T) connect stq_uop[10].br_mask, _stq_uop_10_br_mask_T_1 node _T_1826 = and(io.core.brupdate.b1.mispredict_mask, uop_11.br_mask) node _T_1827 = neq(_T_1826, UInt<1>(0h0)) node _T_1828 = or(_T_1827, UInt<1>(0h0)) when _T_1828 : connect stq_valid[10], UInt<1>(0h0) connect stq_addr[10].valid, UInt<1>(0h0) connect stq_data[10].valid, UInt<1>(0h0) node _T_1829 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[10].br_mask) node _T_1830 = neq(_T_1829, UInt<1>(0h0)) node _T_1831 = or(_T_1830, UInt<1>(0h0)) node _T_1832 = and(_T_1831, stq_valid[10]) node _T_1833 = and(_T_1832, stq_committed[10]) node _T_1834 = eq(_T_1833, UInt<1>(0h0)) node _T_1835 = asUInt(reset) node _T_1836 = eq(_T_1835, UInt<1>(0h0)) when _T_1836 : node _T_1837 = eq(_T_1834, UInt<1>(0h0)) when _T_1837 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_97 assert(clock, _T_1834, UInt<1>(0h1), "") : assert_97 when stq_valid[11] : wire uop_12 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_12, stq_uop[11] node _stq_uop_11_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_11_br_mask_T_1 = and(uop_12.br_mask, _stq_uop_11_br_mask_T) connect stq_uop[11].br_mask, _stq_uop_11_br_mask_T_1 node _T_1838 = and(io.core.brupdate.b1.mispredict_mask, uop_12.br_mask) node _T_1839 = neq(_T_1838, UInt<1>(0h0)) node _T_1840 = or(_T_1839, UInt<1>(0h0)) when _T_1840 : connect stq_valid[11], UInt<1>(0h0) connect stq_addr[11].valid, UInt<1>(0h0) connect stq_data[11].valid, UInt<1>(0h0) node _T_1841 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[11].br_mask) node _T_1842 = neq(_T_1841, UInt<1>(0h0)) node _T_1843 = or(_T_1842, UInt<1>(0h0)) node _T_1844 = and(_T_1843, stq_valid[11]) node _T_1845 = and(_T_1844, stq_committed[11]) node _T_1846 = eq(_T_1845, UInt<1>(0h0)) node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(_T_1846, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_98 assert(clock, _T_1846, UInt<1>(0h1), "") : assert_98 when stq_valid[12] : wire uop_13 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_13, stq_uop[12] node _stq_uop_12_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_12_br_mask_T_1 = and(uop_13.br_mask, _stq_uop_12_br_mask_T) connect stq_uop[12].br_mask, _stq_uop_12_br_mask_T_1 node _T_1850 = and(io.core.brupdate.b1.mispredict_mask, uop_13.br_mask) node _T_1851 = neq(_T_1850, UInt<1>(0h0)) node _T_1852 = or(_T_1851, UInt<1>(0h0)) when _T_1852 : connect stq_valid[12], UInt<1>(0h0) connect stq_addr[12].valid, UInt<1>(0h0) connect stq_data[12].valid, UInt<1>(0h0) node _T_1853 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[12].br_mask) node _T_1854 = neq(_T_1853, UInt<1>(0h0)) node _T_1855 = or(_T_1854, UInt<1>(0h0)) node _T_1856 = and(_T_1855, stq_valid[12]) node _T_1857 = and(_T_1856, stq_committed[12]) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) node _T_1859 = asUInt(reset) node _T_1860 = eq(_T_1859, UInt<1>(0h0)) when _T_1860 : node _T_1861 = eq(_T_1858, UInt<1>(0h0)) when _T_1861 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_99 assert(clock, _T_1858, UInt<1>(0h1), "") : assert_99 when stq_valid[13] : wire uop_14 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_14, stq_uop[13] node _stq_uop_13_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_13_br_mask_T_1 = and(uop_14.br_mask, _stq_uop_13_br_mask_T) connect stq_uop[13].br_mask, _stq_uop_13_br_mask_T_1 node _T_1862 = and(io.core.brupdate.b1.mispredict_mask, uop_14.br_mask) node _T_1863 = neq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(_T_1863, UInt<1>(0h0)) when _T_1864 : connect stq_valid[13], UInt<1>(0h0) connect stq_addr[13].valid, UInt<1>(0h0) connect stq_data[13].valid, UInt<1>(0h0) node _T_1865 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[13].br_mask) node _T_1866 = neq(_T_1865, UInt<1>(0h0)) node _T_1867 = or(_T_1866, UInt<1>(0h0)) node _T_1868 = and(_T_1867, stq_valid[13]) node _T_1869 = and(_T_1868, stq_committed[13]) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_100 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_100 when stq_valid[14] : wire uop_15 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_15, stq_uop[14] node _stq_uop_14_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_14_br_mask_T_1 = and(uop_15.br_mask, _stq_uop_14_br_mask_T) connect stq_uop[14].br_mask, _stq_uop_14_br_mask_T_1 node _T_1874 = and(io.core.brupdate.b1.mispredict_mask, uop_15.br_mask) node _T_1875 = neq(_T_1874, UInt<1>(0h0)) node _T_1876 = or(_T_1875, UInt<1>(0h0)) when _T_1876 : connect stq_valid[14], UInt<1>(0h0) connect stq_addr[14].valid, UInt<1>(0h0) connect stq_data[14].valid, UInt<1>(0h0) node _T_1877 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[14].br_mask) node _T_1878 = neq(_T_1877, UInt<1>(0h0)) node _T_1879 = or(_T_1878, UInt<1>(0h0)) node _T_1880 = and(_T_1879, stq_valid[14]) node _T_1881 = and(_T_1880, stq_committed[14]) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) node _T_1883 = asUInt(reset) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) when _T_1884 : node _T_1885 = eq(_T_1882, UInt<1>(0h0)) when _T_1885 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_101 assert(clock, _T_1882, UInt<1>(0h1), "") : assert_101 when stq_valid[15] : wire uop_16 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_16, stq_uop[15] node _stq_uop_15_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_15_br_mask_T_1 = and(uop_16.br_mask, _stq_uop_15_br_mask_T) connect stq_uop[15].br_mask, _stq_uop_15_br_mask_T_1 node _T_1886 = and(io.core.brupdate.b1.mispredict_mask, uop_16.br_mask) node _T_1887 = neq(_T_1886, UInt<1>(0h0)) node _T_1888 = or(_T_1887, UInt<1>(0h0)) when _T_1888 : connect stq_valid[15], UInt<1>(0h0) connect stq_addr[15].valid, UInt<1>(0h0) connect stq_data[15].valid, UInt<1>(0h0) node _T_1889 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[15].br_mask) node _T_1890 = neq(_T_1889, UInt<1>(0h0)) node _T_1891 = or(_T_1890, UInt<1>(0h0)) node _T_1892 = and(_T_1891, stq_valid[15]) node _T_1893 = and(_T_1892, stq_committed[15]) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_102 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_102 when stq_valid[16] : wire uop_17 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_17, stq_uop[16] node _stq_uop_16_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_16_br_mask_T_1 = and(uop_17.br_mask, _stq_uop_16_br_mask_T) connect stq_uop[16].br_mask, _stq_uop_16_br_mask_T_1 node _T_1898 = and(io.core.brupdate.b1.mispredict_mask, uop_17.br_mask) node _T_1899 = neq(_T_1898, UInt<1>(0h0)) node _T_1900 = or(_T_1899, UInt<1>(0h0)) when _T_1900 : connect stq_valid[16], UInt<1>(0h0) connect stq_addr[16].valid, UInt<1>(0h0) connect stq_data[16].valid, UInt<1>(0h0) node _T_1901 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[16].br_mask) node _T_1902 = neq(_T_1901, UInt<1>(0h0)) node _T_1903 = or(_T_1902, UInt<1>(0h0)) node _T_1904 = and(_T_1903, stq_valid[16]) node _T_1905 = and(_T_1904, stq_committed[16]) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_103 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_103 when stq_valid[17] : wire uop_18 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_18, stq_uop[17] node _stq_uop_17_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_17_br_mask_T_1 = and(uop_18.br_mask, _stq_uop_17_br_mask_T) connect stq_uop[17].br_mask, _stq_uop_17_br_mask_T_1 node _T_1910 = and(io.core.brupdate.b1.mispredict_mask, uop_18.br_mask) node _T_1911 = neq(_T_1910, UInt<1>(0h0)) node _T_1912 = or(_T_1911, UInt<1>(0h0)) when _T_1912 : connect stq_valid[17], UInt<1>(0h0) connect stq_addr[17].valid, UInt<1>(0h0) connect stq_data[17].valid, UInt<1>(0h0) node _T_1913 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[17].br_mask) node _T_1914 = neq(_T_1913, UInt<1>(0h0)) node _T_1915 = or(_T_1914, UInt<1>(0h0)) node _T_1916 = and(_T_1915, stq_valid[17]) node _T_1917 = and(_T_1916, stq_committed[17]) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) node _T_1919 = asUInt(reset) node _T_1920 = eq(_T_1919, UInt<1>(0h0)) when _T_1920 : node _T_1921 = eq(_T_1918, UInt<1>(0h0)) when _T_1921 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_104 assert(clock, _T_1918, UInt<1>(0h1), "") : assert_104 when stq_valid[18] : wire uop_19 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_19, stq_uop[18] node _stq_uop_18_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_18_br_mask_T_1 = and(uop_19.br_mask, _stq_uop_18_br_mask_T) connect stq_uop[18].br_mask, _stq_uop_18_br_mask_T_1 node _T_1922 = and(io.core.brupdate.b1.mispredict_mask, uop_19.br_mask) node _T_1923 = neq(_T_1922, UInt<1>(0h0)) node _T_1924 = or(_T_1923, UInt<1>(0h0)) when _T_1924 : connect stq_valid[18], UInt<1>(0h0) connect stq_addr[18].valid, UInt<1>(0h0) connect stq_data[18].valid, UInt<1>(0h0) node _T_1925 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[18].br_mask) node _T_1926 = neq(_T_1925, UInt<1>(0h0)) node _T_1927 = or(_T_1926, UInt<1>(0h0)) node _T_1928 = and(_T_1927, stq_valid[18]) node _T_1929 = and(_T_1928, stq_committed[18]) node _T_1930 = eq(_T_1929, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_105 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_105 when stq_valid[19] : wire uop_20 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_20, stq_uop[19] node _stq_uop_19_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_19_br_mask_T_1 = and(uop_20.br_mask, _stq_uop_19_br_mask_T) connect stq_uop[19].br_mask, _stq_uop_19_br_mask_T_1 node _T_1934 = and(io.core.brupdate.b1.mispredict_mask, uop_20.br_mask) node _T_1935 = neq(_T_1934, UInt<1>(0h0)) node _T_1936 = or(_T_1935, UInt<1>(0h0)) when _T_1936 : connect stq_valid[19], UInt<1>(0h0) connect stq_addr[19].valid, UInt<1>(0h0) connect stq_data[19].valid, UInt<1>(0h0) node _T_1937 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[19].br_mask) node _T_1938 = neq(_T_1937, UInt<1>(0h0)) node _T_1939 = or(_T_1938, UInt<1>(0h0)) node _T_1940 = and(_T_1939, stq_valid[19]) node _T_1941 = and(_T_1940, stq_committed[19]) node _T_1942 = eq(_T_1941, UInt<1>(0h0)) node _T_1943 = asUInt(reset) node _T_1944 = eq(_T_1943, UInt<1>(0h0)) when _T_1944 : node _T_1945 = eq(_T_1942, UInt<1>(0h0)) when _T_1945 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_106 assert(clock, _T_1942, UInt<1>(0h1), "") : assert_106 when stq_valid[20] : wire uop_21 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_21, stq_uop[20] node _stq_uop_20_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_20_br_mask_T_1 = and(uop_21.br_mask, _stq_uop_20_br_mask_T) connect stq_uop[20].br_mask, _stq_uop_20_br_mask_T_1 node _T_1946 = and(io.core.brupdate.b1.mispredict_mask, uop_21.br_mask) node _T_1947 = neq(_T_1946, UInt<1>(0h0)) node _T_1948 = or(_T_1947, UInt<1>(0h0)) when _T_1948 : connect stq_valid[20], UInt<1>(0h0) connect stq_addr[20].valid, UInt<1>(0h0) connect stq_data[20].valid, UInt<1>(0h0) node _T_1949 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[20].br_mask) node _T_1950 = neq(_T_1949, UInt<1>(0h0)) node _T_1951 = or(_T_1950, UInt<1>(0h0)) node _T_1952 = and(_T_1951, stq_valid[20]) node _T_1953 = and(_T_1952, stq_committed[20]) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_107 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_107 when stq_valid[21] : wire uop_22 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_22, stq_uop[21] node _stq_uop_21_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_21_br_mask_T_1 = and(uop_22.br_mask, _stq_uop_21_br_mask_T) connect stq_uop[21].br_mask, _stq_uop_21_br_mask_T_1 node _T_1958 = and(io.core.brupdate.b1.mispredict_mask, uop_22.br_mask) node _T_1959 = neq(_T_1958, UInt<1>(0h0)) node _T_1960 = or(_T_1959, UInt<1>(0h0)) when _T_1960 : connect stq_valid[21], UInt<1>(0h0) connect stq_addr[21].valid, UInt<1>(0h0) connect stq_data[21].valid, UInt<1>(0h0) node _T_1961 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[21].br_mask) node _T_1962 = neq(_T_1961, UInt<1>(0h0)) node _T_1963 = or(_T_1962, UInt<1>(0h0)) node _T_1964 = and(_T_1963, stq_valid[21]) node _T_1965 = and(_T_1964, stq_committed[21]) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = asUInt(reset) node _T_1968 = eq(_T_1967, UInt<1>(0h0)) when _T_1968 : node _T_1969 = eq(_T_1966, UInt<1>(0h0)) when _T_1969 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_108 assert(clock, _T_1966, UInt<1>(0h1), "") : assert_108 when stq_valid[22] : wire uop_23 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_23, stq_uop[22] node _stq_uop_22_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_22_br_mask_T_1 = and(uop_23.br_mask, _stq_uop_22_br_mask_T) connect stq_uop[22].br_mask, _stq_uop_22_br_mask_T_1 node _T_1970 = and(io.core.brupdate.b1.mispredict_mask, uop_23.br_mask) node _T_1971 = neq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(_T_1971, UInt<1>(0h0)) when _T_1972 : connect stq_valid[22], UInt<1>(0h0) connect stq_addr[22].valid, UInt<1>(0h0) connect stq_data[22].valid, UInt<1>(0h0) node _T_1973 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[22].br_mask) node _T_1974 = neq(_T_1973, UInt<1>(0h0)) node _T_1975 = or(_T_1974, UInt<1>(0h0)) node _T_1976 = and(_T_1975, stq_valid[22]) node _T_1977 = and(_T_1976, stq_committed[22]) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_109 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_109 when stq_valid[23] : wire uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_24, stq_uop[23] node _stq_uop_23_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _stq_uop_23_br_mask_T_1 = and(uop_24.br_mask, _stq_uop_23_br_mask_T) connect stq_uop[23].br_mask, _stq_uop_23_br_mask_T_1 node _T_1982 = and(io.core.brupdate.b1.mispredict_mask, uop_24.br_mask) node _T_1983 = neq(_T_1982, UInt<1>(0h0)) node _T_1984 = or(_T_1983, UInt<1>(0h0)) when _T_1984 : connect stq_valid[23], UInt<1>(0h0) connect stq_addr[23].valid, UInt<1>(0h0) connect stq_data[23].valid, UInt<1>(0h0) node _T_1985 = and(io.core.brupdate.b1.mispredict_mask, stq_uop[23].br_mask) node _T_1986 = neq(_T_1985, UInt<1>(0h0)) node _T_1987 = or(_T_1986, UInt<1>(0h0)) node _T_1988 = and(_T_1987, stq_valid[23]) node _T_1989 = and(_T_1988, stq_committed[23]) node _T_1990 = eq(_T_1989, UInt<1>(0h0)) node _T_1991 = asUInt(reset) node _T_1992 = eq(_T_1991, UInt<1>(0h0)) when _T_1992 : node _T_1993 = eq(_T_1990, UInt<1>(0h0)) when _T_1993 : printf(clock, UInt<1>(0h1), "Assertion failed: Branch is trying to clear a committed store.\n at lsu.scala:1689 assert (!(IsKilledByBranch(io.core.brupdate, false.B, stq_uop(i)) && stq_valid(i) && stq_committed(i)),\n") : printf_110 assert(clock, _T_1990, UInt<1>(0h1), "") : assert_110 when ldq_valid[0] : wire uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_25, ldq_uop[0] node _ldq_uop_0_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_0_br_mask_T_1 = and(uop_25.br_mask, _ldq_uop_0_br_mask_T) connect ldq_uop[0].br_mask, _ldq_uop_0_br_mask_T_1 node _T_1994 = and(io.core.brupdate.b1.mispredict_mask, uop_25.br_mask) node _T_1995 = neq(_T_1994, UInt<1>(0h0)) node _T_1996 = or(_T_1995, io.core.exception) when _T_1996 : connect ldq_valid[0], UInt<1>(0h0) connect ldq_addr[0].valid, UInt<1>(0h0) when ldq_valid[1] : wire uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_26, ldq_uop[1] node _ldq_uop_1_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_1_br_mask_T_1 = and(uop_26.br_mask, _ldq_uop_1_br_mask_T) connect ldq_uop[1].br_mask, _ldq_uop_1_br_mask_T_1 node _T_1997 = and(io.core.brupdate.b1.mispredict_mask, uop_26.br_mask) node _T_1998 = neq(_T_1997, UInt<1>(0h0)) node _T_1999 = or(_T_1998, io.core.exception) when _T_1999 : connect ldq_valid[1], UInt<1>(0h0) connect ldq_addr[1].valid, UInt<1>(0h0) when ldq_valid[2] : wire uop_27 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_27, ldq_uop[2] node _ldq_uop_2_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_2_br_mask_T_1 = and(uop_27.br_mask, _ldq_uop_2_br_mask_T) connect ldq_uop[2].br_mask, _ldq_uop_2_br_mask_T_1 node _T_2000 = and(io.core.brupdate.b1.mispredict_mask, uop_27.br_mask) node _T_2001 = neq(_T_2000, UInt<1>(0h0)) node _T_2002 = or(_T_2001, io.core.exception) when _T_2002 : connect ldq_valid[2], UInt<1>(0h0) connect ldq_addr[2].valid, UInt<1>(0h0) when ldq_valid[3] : wire uop_28 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_28, ldq_uop[3] node _ldq_uop_3_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_3_br_mask_T_1 = and(uop_28.br_mask, _ldq_uop_3_br_mask_T) connect ldq_uop[3].br_mask, _ldq_uop_3_br_mask_T_1 node _T_2003 = and(io.core.brupdate.b1.mispredict_mask, uop_28.br_mask) node _T_2004 = neq(_T_2003, UInt<1>(0h0)) node _T_2005 = or(_T_2004, io.core.exception) when _T_2005 : connect ldq_valid[3], UInt<1>(0h0) connect ldq_addr[3].valid, UInt<1>(0h0) when ldq_valid[4] : wire uop_29 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_29, ldq_uop[4] node _ldq_uop_4_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_4_br_mask_T_1 = and(uop_29.br_mask, _ldq_uop_4_br_mask_T) connect ldq_uop[4].br_mask, _ldq_uop_4_br_mask_T_1 node _T_2006 = and(io.core.brupdate.b1.mispredict_mask, uop_29.br_mask) node _T_2007 = neq(_T_2006, UInt<1>(0h0)) node _T_2008 = or(_T_2007, io.core.exception) when _T_2008 : connect ldq_valid[4], UInt<1>(0h0) connect ldq_addr[4].valid, UInt<1>(0h0) when ldq_valid[5] : wire uop_30 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_30, ldq_uop[5] node _ldq_uop_5_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_5_br_mask_T_1 = and(uop_30.br_mask, _ldq_uop_5_br_mask_T) connect ldq_uop[5].br_mask, _ldq_uop_5_br_mask_T_1 node _T_2009 = and(io.core.brupdate.b1.mispredict_mask, uop_30.br_mask) node _T_2010 = neq(_T_2009, UInt<1>(0h0)) node _T_2011 = or(_T_2010, io.core.exception) when _T_2011 : connect ldq_valid[5], UInt<1>(0h0) connect ldq_addr[5].valid, UInt<1>(0h0) when ldq_valid[6] : wire uop_31 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_31, ldq_uop[6] node _ldq_uop_6_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_6_br_mask_T_1 = and(uop_31.br_mask, _ldq_uop_6_br_mask_T) connect ldq_uop[6].br_mask, _ldq_uop_6_br_mask_T_1 node _T_2012 = and(io.core.brupdate.b1.mispredict_mask, uop_31.br_mask) node _T_2013 = neq(_T_2012, UInt<1>(0h0)) node _T_2014 = or(_T_2013, io.core.exception) when _T_2014 : connect ldq_valid[6], UInt<1>(0h0) connect ldq_addr[6].valid, UInt<1>(0h0) when ldq_valid[7] : wire uop_32 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_32, ldq_uop[7] node _ldq_uop_7_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_7_br_mask_T_1 = and(uop_32.br_mask, _ldq_uop_7_br_mask_T) connect ldq_uop[7].br_mask, _ldq_uop_7_br_mask_T_1 node _T_2015 = and(io.core.brupdate.b1.mispredict_mask, uop_32.br_mask) node _T_2016 = neq(_T_2015, UInt<1>(0h0)) node _T_2017 = or(_T_2016, io.core.exception) when _T_2017 : connect ldq_valid[7], UInt<1>(0h0) connect ldq_addr[7].valid, UInt<1>(0h0) when ldq_valid[8] : wire uop_33 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_33, ldq_uop[8] node _ldq_uop_8_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_8_br_mask_T_1 = and(uop_33.br_mask, _ldq_uop_8_br_mask_T) connect ldq_uop[8].br_mask, _ldq_uop_8_br_mask_T_1 node _T_2018 = and(io.core.brupdate.b1.mispredict_mask, uop_33.br_mask) node _T_2019 = neq(_T_2018, UInt<1>(0h0)) node _T_2020 = or(_T_2019, io.core.exception) when _T_2020 : connect ldq_valid[8], UInt<1>(0h0) connect ldq_addr[8].valid, UInt<1>(0h0) when ldq_valid[9] : wire uop_34 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_34, ldq_uop[9] node _ldq_uop_9_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_9_br_mask_T_1 = and(uop_34.br_mask, _ldq_uop_9_br_mask_T) connect ldq_uop[9].br_mask, _ldq_uop_9_br_mask_T_1 node _T_2021 = and(io.core.brupdate.b1.mispredict_mask, uop_34.br_mask) node _T_2022 = neq(_T_2021, UInt<1>(0h0)) node _T_2023 = or(_T_2022, io.core.exception) when _T_2023 : connect ldq_valid[9], UInt<1>(0h0) connect ldq_addr[9].valid, UInt<1>(0h0) when ldq_valid[10] : wire uop_35 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_35, ldq_uop[10] node _ldq_uop_10_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_10_br_mask_T_1 = and(uop_35.br_mask, _ldq_uop_10_br_mask_T) connect ldq_uop[10].br_mask, _ldq_uop_10_br_mask_T_1 node _T_2024 = and(io.core.brupdate.b1.mispredict_mask, uop_35.br_mask) node _T_2025 = neq(_T_2024, UInt<1>(0h0)) node _T_2026 = or(_T_2025, io.core.exception) when _T_2026 : connect ldq_valid[10], UInt<1>(0h0) connect ldq_addr[10].valid, UInt<1>(0h0) when ldq_valid[11] : wire uop_36 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_36, ldq_uop[11] node _ldq_uop_11_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_11_br_mask_T_1 = and(uop_36.br_mask, _ldq_uop_11_br_mask_T) connect ldq_uop[11].br_mask, _ldq_uop_11_br_mask_T_1 node _T_2027 = and(io.core.brupdate.b1.mispredict_mask, uop_36.br_mask) node _T_2028 = neq(_T_2027, UInt<1>(0h0)) node _T_2029 = or(_T_2028, io.core.exception) when _T_2029 : connect ldq_valid[11], UInt<1>(0h0) connect ldq_addr[11].valid, UInt<1>(0h0) when ldq_valid[12] : wire uop_37 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_37, ldq_uop[12] node _ldq_uop_12_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_12_br_mask_T_1 = and(uop_37.br_mask, _ldq_uop_12_br_mask_T) connect ldq_uop[12].br_mask, _ldq_uop_12_br_mask_T_1 node _T_2030 = and(io.core.brupdate.b1.mispredict_mask, uop_37.br_mask) node _T_2031 = neq(_T_2030, UInt<1>(0h0)) node _T_2032 = or(_T_2031, io.core.exception) when _T_2032 : connect ldq_valid[12], UInt<1>(0h0) connect ldq_addr[12].valid, UInt<1>(0h0) when ldq_valid[13] : wire uop_38 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_38, ldq_uop[13] node _ldq_uop_13_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_13_br_mask_T_1 = and(uop_38.br_mask, _ldq_uop_13_br_mask_T) connect ldq_uop[13].br_mask, _ldq_uop_13_br_mask_T_1 node _T_2033 = and(io.core.brupdate.b1.mispredict_mask, uop_38.br_mask) node _T_2034 = neq(_T_2033, UInt<1>(0h0)) node _T_2035 = or(_T_2034, io.core.exception) when _T_2035 : connect ldq_valid[13], UInt<1>(0h0) connect ldq_addr[13].valid, UInt<1>(0h0) when ldq_valid[14] : wire uop_39 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_39, ldq_uop[14] node _ldq_uop_14_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_14_br_mask_T_1 = and(uop_39.br_mask, _ldq_uop_14_br_mask_T) connect ldq_uop[14].br_mask, _ldq_uop_14_br_mask_T_1 node _T_2036 = and(io.core.brupdate.b1.mispredict_mask, uop_39.br_mask) node _T_2037 = neq(_T_2036, UInt<1>(0h0)) node _T_2038 = or(_T_2037, io.core.exception) when _T_2038 : connect ldq_valid[14], UInt<1>(0h0) connect ldq_addr[14].valid, UInt<1>(0h0) when ldq_valid[15] : wire uop_40 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_40, ldq_uop[15] node _ldq_uop_15_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_15_br_mask_T_1 = and(uop_40.br_mask, _ldq_uop_15_br_mask_T) connect ldq_uop[15].br_mask, _ldq_uop_15_br_mask_T_1 node _T_2039 = and(io.core.brupdate.b1.mispredict_mask, uop_40.br_mask) node _T_2040 = neq(_T_2039, UInt<1>(0h0)) node _T_2041 = or(_T_2040, io.core.exception) when _T_2041 : connect ldq_valid[15], UInt<1>(0h0) connect ldq_addr[15].valid, UInt<1>(0h0) when ldq_valid[16] : wire uop_41 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_41, ldq_uop[16] node _ldq_uop_16_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_16_br_mask_T_1 = and(uop_41.br_mask, _ldq_uop_16_br_mask_T) connect ldq_uop[16].br_mask, _ldq_uop_16_br_mask_T_1 node _T_2042 = and(io.core.brupdate.b1.mispredict_mask, uop_41.br_mask) node _T_2043 = neq(_T_2042, UInt<1>(0h0)) node _T_2044 = or(_T_2043, io.core.exception) when _T_2044 : connect ldq_valid[16], UInt<1>(0h0) connect ldq_addr[16].valid, UInt<1>(0h0) when ldq_valid[17] : wire uop_42 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_42, ldq_uop[17] node _ldq_uop_17_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_17_br_mask_T_1 = and(uop_42.br_mask, _ldq_uop_17_br_mask_T) connect ldq_uop[17].br_mask, _ldq_uop_17_br_mask_T_1 node _T_2045 = and(io.core.brupdate.b1.mispredict_mask, uop_42.br_mask) node _T_2046 = neq(_T_2045, UInt<1>(0h0)) node _T_2047 = or(_T_2046, io.core.exception) when _T_2047 : connect ldq_valid[17], UInt<1>(0h0) connect ldq_addr[17].valid, UInt<1>(0h0) when ldq_valid[18] : wire uop_43 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_43, ldq_uop[18] node _ldq_uop_18_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_18_br_mask_T_1 = and(uop_43.br_mask, _ldq_uop_18_br_mask_T) connect ldq_uop[18].br_mask, _ldq_uop_18_br_mask_T_1 node _T_2048 = and(io.core.brupdate.b1.mispredict_mask, uop_43.br_mask) node _T_2049 = neq(_T_2048, UInt<1>(0h0)) node _T_2050 = or(_T_2049, io.core.exception) when _T_2050 : connect ldq_valid[18], UInt<1>(0h0) connect ldq_addr[18].valid, UInt<1>(0h0) when ldq_valid[19] : wire uop_44 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_44, ldq_uop[19] node _ldq_uop_19_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_19_br_mask_T_1 = and(uop_44.br_mask, _ldq_uop_19_br_mask_T) connect ldq_uop[19].br_mask, _ldq_uop_19_br_mask_T_1 node _T_2051 = and(io.core.brupdate.b1.mispredict_mask, uop_44.br_mask) node _T_2052 = neq(_T_2051, UInt<1>(0h0)) node _T_2053 = or(_T_2052, io.core.exception) when _T_2053 : connect ldq_valid[19], UInt<1>(0h0) connect ldq_addr[19].valid, UInt<1>(0h0) when ldq_valid[20] : wire uop_45 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_45, ldq_uop[20] node _ldq_uop_20_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_20_br_mask_T_1 = and(uop_45.br_mask, _ldq_uop_20_br_mask_T) connect ldq_uop[20].br_mask, _ldq_uop_20_br_mask_T_1 node _T_2054 = and(io.core.brupdate.b1.mispredict_mask, uop_45.br_mask) node _T_2055 = neq(_T_2054, UInt<1>(0h0)) node _T_2056 = or(_T_2055, io.core.exception) when _T_2056 : connect ldq_valid[20], UInt<1>(0h0) connect ldq_addr[20].valid, UInt<1>(0h0) when ldq_valid[21] : wire uop_46 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_46, ldq_uop[21] node _ldq_uop_21_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_21_br_mask_T_1 = and(uop_46.br_mask, _ldq_uop_21_br_mask_T) connect ldq_uop[21].br_mask, _ldq_uop_21_br_mask_T_1 node _T_2057 = and(io.core.brupdate.b1.mispredict_mask, uop_46.br_mask) node _T_2058 = neq(_T_2057, UInt<1>(0h0)) node _T_2059 = or(_T_2058, io.core.exception) when _T_2059 : connect ldq_valid[21], UInt<1>(0h0) connect ldq_addr[21].valid, UInt<1>(0h0) when ldq_valid[22] : wire uop_47 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_47, ldq_uop[22] node _ldq_uop_22_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_22_br_mask_T_1 = and(uop_47.br_mask, _ldq_uop_22_br_mask_T) connect ldq_uop[22].br_mask, _ldq_uop_22_br_mask_T_1 node _T_2060 = and(io.core.brupdate.b1.mispredict_mask, uop_47.br_mask) node _T_2061 = neq(_T_2060, UInt<1>(0h0)) node _T_2062 = or(_T_2061, io.core.exception) when _T_2062 : connect ldq_valid[22], UInt<1>(0h0) connect ldq_addr[22].valid, UInt<1>(0h0) when ldq_valid[23] : wire uop_48 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect uop_48, ldq_uop[23] node _ldq_uop_23_br_mask_T = not(io.core.brupdate.b1.resolve_mask) node _ldq_uop_23_br_mask_T_1 = and(uop_48.br_mask, _ldq_uop_23_br_mask_T) connect ldq_uop[23].br_mask, _ldq_uop_23_br_mask_T_1 node _T_2063 = and(io.core.brupdate.b1.mispredict_mask, uop_48.br_mask) node _T_2064 = neq(_T_2063, UInt<1>(0h0)) node _T_2065 = or(_T_2064, io.core.exception) when _T_2065 : connect ldq_valid[23], UInt<1>(0h0) connect ldq_addr[23].valid, UInt<1>(0h0) node _T_2066 = eq(io.core.exception, UInt<1>(0h0)) node _T_2067 = and(io.core.brupdate.b2.mispredict, _T_2066) when _T_2067 : connect stq_tail, io.core.brupdate.b2.uop.stq_idx connect ldq_tail, io.core.brupdate.b2.uop.ldq_idx node commit_store = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_stq) node commit_load = and(io.core.commit.valids[0], io.core.commit.uops[0].uses_ldq) wire l_uop_24 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_24, ldq_uop[ldq_head] wire s_uop_27 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_27, stq_uop[stq_commit_head] when commit_store : connect stq_committed[stq_commit_head], UInt<1>(0h1) connect stq_can_execute[stq_commit_head], UInt<1>(0h1) else : when commit_load : node _T_2068 = asUInt(reset) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) when _T_2069 : node _T_2070 = eq(ldq_valid[ldq_head], UInt<1>(0h0)) when _T_2070 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_111 assert(clock, ldq_valid[ldq_head], UInt<1>(0h1), "") : assert_111 node _T_2071 = or(ldq_executed[ldq_head], ldq_forward_std_val[ldq_head]) node _T_2072 = and(_T_2071, ldq_succeeded[ldq_head]) node _T_2073 = asUInt(reset) node _T_2074 = eq(_T_2073, UInt<1>(0h0)) when _T_2074 : node _T_2075 = eq(_T_2072, UInt<1>(0h0)) when _T_2075 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) || ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_112 assert(clock, _T_2072, UInt<1>(0h1), "") : assert_112 connect ldq_valid[ldq_head], UInt<1>(0h0) node wrap_9 = eq(stq_commit_head, UInt<5>(0h17)) node _T_2076 = add(stq_commit_head, UInt<1>(0h1)) node _T_2077 = tail(_T_2076, 1) node _T_2078 = mux(wrap_9, UInt<1>(0h0), _T_2077) node _T_2079 = mux(commit_store, _T_2078, stq_commit_head) node wrap_10 = eq(ldq_head, UInt<5>(0h17)) node _T_2080 = add(ldq_head, UInt<1>(0h1)) node _T_2081 = tail(_T_2080, 1) node _T_2082 = mux(wrap_10, UInt<1>(0h0), _T_2081) node _T_2083 = mux(commit_load, _T_2082, ldq_head) node commit_store_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_stq) node commit_load_1 = and(io.core.commit.valids[1], io.core.commit.uops[1].uses_ldq) wire l_uop_25 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_25, ldq_uop[_T_2083] wire s_uop_28 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_28, stq_uop[_T_2079] when commit_store_1 : connect stq_committed[_T_2079], UInt<1>(0h1) connect stq_can_execute[_T_2079], UInt<1>(0h1) else : when commit_load_1 : node _T_2084 = asUInt(reset) node _T_2085 = eq(_T_2084, UInt<1>(0h0)) when _T_2085 : node _T_2086 = eq(ldq_valid[_T_2083], UInt<1>(0h0)) when _T_2086 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_113 assert(clock, ldq_valid[_T_2083], UInt<1>(0h1), "") : assert_113 node _T_2087 = or(ldq_executed[_T_2083], ldq_forward_std_val[_T_2083]) node _T_2088 = and(_T_2087, ldq_succeeded[_T_2083]) node _T_2089 = asUInt(reset) node _T_2090 = eq(_T_2089, UInt<1>(0h0)) when _T_2090 : node _T_2091 = eq(_T_2088, UInt<1>(0h0)) when _T_2091 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) || ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_114 assert(clock, _T_2088, UInt<1>(0h1), "") : assert_114 connect ldq_valid[_T_2083], UInt<1>(0h0) node wrap_11 = eq(_T_2079, UInt<5>(0h17)) node _T_2092 = add(_T_2079, UInt<1>(0h1)) node _T_2093 = tail(_T_2092, 1) node _T_2094 = mux(wrap_11, UInt<1>(0h0), _T_2093) node _T_2095 = mux(commit_store_1, _T_2094, _T_2079) node wrap_12 = eq(_T_2083, UInt<5>(0h17)) node _T_2096 = add(_T_2083, UInt<1>(0h1)) node _T_2097 = tail(_T_2096, 1) node _T_2098 = mux(wrap_12, UInt<1>(0h0), _T_2097) node _T_2099 = mux(commit_load_1, _T_2098, _T_2083) node commit_store_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_stq) node commit_load_2 = and(io.core.commit.valids[2], io.core.commit.uops[2].uses_ldq) wire l_uop_26 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect l_uop_26, ldq_uop[_T_2099] wire s_uop_29 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect s_uop_29, stq_uop[_T_2095] when commit_store_2 : connect stq_committed[_T_2095], UInt<1>(0h1) connect stq_can_execute[_T_2095], UInt<1>(0h1) else : when commit_load_2 : node _T_2100 = asUInt(reset) node _T_2101 = eq(_T_2100, UInt<1>(0h0)) when _T_2101 : node _T_2102 = eq(ldq_valid[_T_2099], UInt<1>(0h0)) when _T_2102 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-allocated load entry.\n at lsu.scala:1736 assert (ldq_valid(temp_ldq_head), \"[lsu] trying to commit an un-allocated load entry.\")\n") : printf_115 assert(clock, ldq_valid[_T_2099], UInt<1>(0h1), "") : assert_115 node _T_2103 = or(ldq_executed[_T_2099], ldq_forward_std_val[_T_2099]) node _T_2104 = and(_T_2103, ldq_succeeded[_T_2099]) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: [lsu] trying to commit an un-executed load entry.\n at lsu.scala:1737 assert ((ldq_executed(temp_ldq_head) || ldq_forward_std_val(temp_ldq_head)) && ldq_succeeded(temp_ldq_head),\n") : printf_116 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_116 connect ldq_valid[_T_2099], UInt<1>(0h0) node wrap_13 = eq(_T_2095, UInt<5>(0h17)) node _T_2108 = add(_T_2095, UInt<1>(0h1)) node _T_2109 = tail(_T_2108, 1) node _T_2110 = mux(wrap_13, UInt<1>(0h0), _T_2109) node _T_2111 = mux(commit_store_2, _T_2110, _T_2095) node wrap_14 = eq(_T_2099, UInt<5>(0h17)) node _T_2112 = add(_T_2099, UInt<1>(0h1)) node _T_2113 = tail(_T_2112, 1) node _T_2114 = mux(wrap_14, UInt<1>(0h0), _T_2113) node _T_2115 = mux(commit_load_2, _T_2114, _T_2099) connect stq_commit_head, _T_2111 connect ldq_head, _T_2115 node _T_2116 = and(stq_valid[stq_head], stq_committed[stq_head]) when _T_2116 : node _T_2117 = eq(io.dmem.ordered, UInt<1>(0h0)) node _T_2118 = and(stq_uop[stq_head].is_fence, _T_2117) when _T_2118 : connect io.dmem.force_order, UInt<1>(0h1) connect store_needs_order, UInt<1>(0h1) node _clear_store_T = mux(stq_uop[stq_head].is_fence, io.dmem.ordered, stq_succeeded[stq_head]) connect clear_store, _clear_store_T when clear_store : connect stq_valid[stq_head], UInt<1>(0h0) node stq_head_wrap = eq(stq_head, UInt<5>(0h17)) node _stq_head_T = add(stq_head, UInt<1>(0h1)) node _stq_head_T_1 = tail(_stq_head_T, 1) node _stq_head_T_2 = mux(stq_head_wrap, UInt<1>(0h0), _stq_head_T_1) connect stq_head, _stq_head_T_2 when stq_uop[stq_head].is_fence : node stq_execute_head_wrap_1 = eq(stq_execute_head, UInt<5>(0h17)) node _stq_execute_head_T_3 = add(stq_execute_head, UInt<1>(0h1)) node _stq_execute_head_T_4 = tail(_stq_execute_head_T_3, 1) node _stq_execute_head_T_5 = mux(stq_execute_head_wrap_1, UInt<1>(0h0), _stq_execute_head_T_4) connect stq_execute_head, _stq_execute_head_T_5 connect io.hellacache.req.ready, UInt<1>(0h0) connect io.hellacache.s2_nack, UInt<1>(0h0) connect io.hellacache.s2_nack_cause_raw, UInt<1>(0h0) invalidate io.hellacache.s2_uncached invalidate io.hellacache.s2_paddr wire _io_hellacache_s2_xcpt_WIRE : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}} connect _io_hellacache_s2_xcpt_WIRE.ae.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.gf.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.pf.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ma.st, UInt<1>(0h0) connect _io_hellacache_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0) connect io.hellacache.s2_xcpt, _io_hellacache_s2_xcpt_WIRE connect io.hellacache.replay_next, UInt<1>(0h0) invalidate io.hellacache.s2_gpa invalidate io.hellacache.s2_gpa_is_pte invalidate io.hellacache.ordered invalidate io.hellacache.perf.storeBufferEmptyAfterStore invalidate io.hellacache.perf.storeBufferEmptyAfterLoad invalidate io.hellacache.perf.canAcceptLoadThenLoad invalidate io.hellacache.perf.canAcceptStoreThenRMW invalidate io.hellacache.perf.canAcceptStoreThenLoad invalidate io.hellacache.perf.blocked invalidate io.hellacache.perf.tlbMiss invalidate io.hellacache.perf.grant invalidate io.hellacache.perf.release invalidate io.hellacache.perf.acquire connect io.hellacache.clock_enabled, UInt<1>(0h1) node _io_hellacache_store_pending_T = or(stq_valid[0], stq_valid[1]) node _io_hellacache_store_pending_T_1 = or(_io_hellacache_store_pending_T, stq_valid[2]) node _io_hellacache_store_pending_T_2 = or(_io_hellacache_store_pending_T_1, stq_valid[3]) node _io_hellacache_store_pending_T_3 = or(_io_hellacache_store_pending_T_2, stq_valid[4]) node _io_hellacache_store_pending_T_4 = or(_io_hellacache_store_pending_T_3, stq_valid[5]) node _io_hellacache_store_pending_T_5 = or(_io_hellacache_store_pending_T_4, stq_valid[6]) node _io_hellacache_store_pending_T_6 = or(_io_hellacache_store_pending_T_5, stq_valid[7]) node _io_hellacache_store_pending_T_7 = or(_io_hellacache_store_pending_T_6, stq_valid[8]) node _io_hellacache_store_pending_T_8 = or(_io_hellacache_store_pending_T_7, stq_valid[9]) node _io_hellacache_store_pending_T_9 = or(_io_hellacache_store_pending_T_8, stq_valid[10]) node _io_hellacache_store_pending_T_10 = or(_io_hellacache_store_pending_T_9, stq_valid[11]) node _io_hellacache_store_pending_T_11 = or(_io_hellacache_store_pending_T_10, stq_valid[12]) node _io_hellacache_store_pending_T_12 = or(_io_hellacache_store_pending_T_11, stq_valid[13]) node _io_hellacache_store_pending_T_13 = or(_io_hellacache_store_pending_T_12, stq_valid[14]) node _io_hellacache_store_pending_T_14 = or(_io_hellacache_store_pending_T_13, stq_valid[15]) node _io_hellacache_store_pending_T_15 = or(_io_hellacache_store_pending_T_14, stq_valid[16]) node _io_hellacache_store_pending_T_16 = or(_io_hellacache_store_pending_T_15, stq_valid[17]) node _io_hellacache_store_pending_T_17 = or(_io_hellacache_store_pending_T_16, stq_valid[18]) node _io_hellacache_store_pending_T_18 = or(_io_hellacache_store_pending_T_17, stq_valid[19]) node _io_hellacache_store_pending_T_19 = or(_io_hellacache_store_pending_T_18, stq_valid[20]) node _io_hellacache_store_pending_T_20 = or(_io_hellacache_store_pending_T_19, stq_valid[21]) node _io_hellacache_store_pending_T_21 = or(_io_hellacache_store_pending_T_20, stq_valid[22]) node _io_hellacache_store_pending_T_22 = or(_io_hellacache_store_pending_T_21, stq_valid[23]) connect io.hellacache.store_pending, _io_hellacache_store_pending_T_22 connect io.hellacache.resp.valid, UInt<1>(0h0) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.mask, hella_req.mask connect io.hellacache.resp.bits.replay, UInt<1>(0h0) connect io.hellacache.resp.bits.has_data, UInt<1>(0h1) connect io.hellacache.resp.bits.data_word_bypass, io.dmem.ll_resp.bits.data connect io.hellacache.resp.bits.data_raw, io.dmem.ll_resp.bits.data connect io.hellacache.resp.bits.store_data, hella_req.data connect io.hellacache.resp.bits.dprv, io.ptw.status.prv connect io.hellacache.resp.bits.dv, io.ptw.status.v connect io.hellacache.resp.bits.data, io.dmem.ll_resp.bits.data node _T_2119 = eq(hella_state, UInt<3>(0h0)) when _T_2119 : connect io.hellacache.req.ready, UInt<1>(0h1) node _T_2120 = and(io.hellacache.req.ready, io.hellacache.req.valid) when _T_2120 : connect hella_req, io.hellacache.req.bits connect hella_state, UInt<3>(0h1) else : node _T_2121 = eq(hella_state, UInt<3>(0h1)) when _T_2121 : connect can_fire_hella_incoming[0], UInt<1>(0h1) connect hella_data, io.hellacache.s1_data connect hella_xcpt.ae.st, dtlb.io.resp[0].ae.st connect hella_xcpt.ae.ld, dtlb.io.resp[0].ae.ld connect hella_xcpt.gf.st, dtlb.io.resp[0].gf.st connect hella_xcpt.gf.ld, dtlb.io.resp[0].gf.ld connect hella_xcpt.pf.st, dtlb.io.resp[0].pf.st connect hella_xcpt.pf.ld, dtlb.io.resp[0].pf.ld connect hella_xcpt.ma.st, dtlb.io.resp[0].ma.st connect hella_xcpt.ma.ld, dtlb.io.resp[0].ma.ld when io.hellacache.s1_kill : node _T_2122 = and(will_fire_hella_incoming[0], dmem_req_fire[0]) when _T_2122 : connect hella_state, UInt<3>(0h6) else : connect hella_state, UInt<3>(0h0) else : node _T_2123 = and(will_fire_hella_incoming[0], dmem_req_fire[0]) when _T_2123 : connect hella_state, UInt<3>(0h2) else : connect hella_state, UInt<3>(0h3) else : node _T_2124 = eq(hella_state, UInt<3>(0h3)) when _T_2124 : connect io.hellacache.s2_nack, UInt<1>(0h1) connect hella_state, UInt<3>(0h0) else : node _T_2125 = eq(hella_state, UInt<3>(0h2)) when _T_2125 : connect io.hellacache.s2_xcpt, hella_xcpt node _T_2126 = cat(hella_xcpt.ae.ld, hella_xcpt.ae.st) node _T_2127 = cat(hella_xcpt.gf.ld, hella_xcpt.gf.st) node _T_2128 = cat(hella_xcpt.pf.ld, hella_xcpt.pf.st) node _T_2129 = cat(hella_xcpt.ma.ld, hella_xcpt.ma.st) node lo = cat(_T_2127, _T_2126) node hi = cat(_T_2129, _T_2128) node _T_2130 = cat(hi, lo) node _T_2131 = neq(_T_2130, UInt<1>(0h0)) node _T_2132 = or(io.hellacache.s2_kill, _T_2131) when _T_2132 : connect hella_state, UInt<3>(0h6) else : connect hella_state, UInt<3>(0h4) else : node _T_2133 = eq(hella_state, UInt<3>(0h4)) when _T_2133 : node _T_2134 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_2135 = and(_T_2134, io.dmem.ll_resp.bits.is_hella) when _T_2135 : connect hella_state, UInt<3>(0h0) connect io.hellacache.resp.valid, UInt<1>(0h1) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.data, io.dmem.ll_resp.bits.data node _T_2136 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella) node _T_2137 = and(io.dmem.store_ack[0].valid, io.dmem.store_ack[0].bits.is_hella) node _T_2138 = or(_T_2136, _T_2137) when _T_2138 : connect hella_state, UInt<3>(0h0) connect io.hellacache.resp.valid, UInt<1>(0h1) connect io.hellacache.resp.bits.addr, hella_req.addr connect io.hellacache.resp.bits.tag, hella_req.tag connect io.hellacache.resp.bits.cmd, hella_req.cmd connect io.hellacache.resp.bits.signed, hella_req.signed connect io.hellacache.resp.bits.size, hella_req.size connect io.hellacache.resp.bits.data, io.dmem.resp[0].bits.data node _T_2139 = and(io.dmem.nack[0].valid, io.dmem.nack[0].bits.is_hella) when _T_2139 : connect hella_state, UInt<3>(0h5) else : node _T_2140 = eq(hella_state, UInt<3>(0h5)) when _T_2140 : connect can_fire_hella_wakeup[0], UInt<1>(0h1) node _T_2141 = and(will_fire_hella_wakeup[0], dmem_req_fire[0]) when _T_2141 : connect hella_state, UInt<3>(0h4) else : node _T_2142 = eq(hella_state, UInt<3>(0h6)) when _T_2142 : node _T_2143 = and(io.dmem.ll_resp.ready, io.dmem.ll_resp.valid) node _T_2144 = and(_T_2143, io.dmem.ll_resp.bits.is_hella) when _T_2144 : connect hella_state, UInt<3>(0h0) node _T_2145 = and(io.dmem.resp[0].valid, io.dmem.resp[0].bits.is_hella) when _T_2145 : connect hella_state, UInt<3>(0h0) node _T_2146 = asUInt(reset) node _T_2147 = or(_T_2146, io.core.exception) when _T_2147 : connect ldq_head, UInt<1>(0h0) connect ldq_tail, UInt<1>(0h0) node _T_2148 = asUInt(reset) when _T_2148 : connect stq_head, UInt<1>(0h0) connect stq_tail, UInt<1>(0h0) connect stq_commit_head, UInt<1>(0h0) connect stq_execute_head, UInt<1>(0h0) connect stq_valid[0], UInt<1>(0h0) connect stq_valid[1], UInt<1>(0h0) connect stq_valid[2], UInt<1>(0h0) connect stq_valid[3], UInt<1>(0h0) connect stq_valid[4], UInt<1>(0h0) connect stq_valid[5], UInt<1>(0h0) connect stq_valid[6], UInt<1>(0h0) connect stq_valid[7], UInt<1>(0h0) connect stq_valid[8], UInt<1>(0h0) connect stq_valid[9], UInt<1>(0h0) connect stq_valid[10], UInt<1>(0h0) connect stq_valid[11], UInt<1>(0h0) connect stq_valid[12], UInt<1>(0h0) connect stq_valid[13], UInt<1>(0h0) connect stq_valid[14], UInt<1>(0h0) connect stq_valid[15], UInt<1>(0h0) connect stq_valid[16], UInt<1>(0h0) connect stq_valid[17], UInt<1>(0h0) connect stq_valid[18], UInt<1>(0h0) connect stq_valid[19], UInt<1>(0h0) connect stq_valid[20], UInt<1>(0h0) connect stq_valid[21], UInt<1>(0h0) connect stq_valid[22], UInt<1>(0h0) connect stq_valid[23], UInt<1>(0h0) else : connect stq_tail, stq_commit_head node _T_2149 = eq(stq_committed[0], UInt<1>(0h0)) node _T_2150 = eq(stq_succeeded[0], UInt<1>(0h0)) node _T_2151 = and(_T_2149, _T_2150) when _T_2151 : connect stq_valid[0], UInt<1>(0h0) node _T_2152 = eq(stq_committed[1], UInt<1>(0h0)) node _T_2153 = eq(stq_succeeded[1], UInt<1>(0h0)) node _T_2154 = and(_T_2152, _T_2153) when _T_2154 : connect stq_valid[1], UInt<1>(0h0) node _T_2155 = eq(stq_committed[2], UInt<1>(0h0)) node _T_2156 = eq(stq_succeeded[2], UInt<1>(0h0)) node _T_2157 = and(_T_2155, _T_2156) when _T_2157 : connect stq_valid[2], UInt<1>(0h0) node _T_2158 = eq(stq_committed[3], UInt<1>(0h0)) node _T_2159 = eq(stq_succeeded[3], UInt<1>(0h0)) node _T_2160 = and(_T_2158, _T_2159) when _T_2160 : connect stq_valid[3], UInt<1>(0h0) node _T_2161 = eq(stq_committed[4], UInt<1>(0h0)) node _T_2162 = eq(stq_succeeded[4], UInt<1>(0h0)) node _T_2163 = and(_T_2161, _T_2162) when _T_2163 : connect stq_valid[4], UInt<1>(0h0) node _T_2164 = eq(stq_committed[5], UInt<1>(0h0)) node _T_2165 = eq(stq_succeeded[5], UInt<1>(0h0)) node _T_2166 = and(_T_2164, _T_2165) when _T_2166 : connect stq_valid[5], UInt<1>(0h0) node _T_2167 = eq(stq_committed[6], UInt<1>(0h0)) node _T_2168 = eq(stq_succeeded[6], UInt<1>(0h0)) node _T_2169 = and(_T_2167, _T_2168) when _T_2169 : connect stq_valid[6], UInt<1>(0h0) node _T_2170 = eq(stq_committed[7], UInt<1>(0h0)) node _T_2171 = eq(stq_succeeded[7], UInt<1>(0h0)) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : connect stq_valid[7], UInt<1>(0h0) node _T_2173 = eq(stq_committed[8], UInt<1>(0h0)) node _T_2174 = eq(stq_succeeded[8], UInt<1>(0h0)) node _T_2175 = and(_T_2173, _T_2174) when _T_2175 : connect stq_valid[8], UInt<1>(0h0) node _T_2176 = eq(stq_committed[9], UInt<1>(0h0)) node _T_2177 = eq(stq_succeeded[9], UInt<1>(0h0)) node _T_2178 = and(_T_2176, _T_2177) when _T_2178 : connect stq_valid[9], UInt<1>(0h0) node _T_2179 = eq(stq_committed[10], UInt<1>(0h0)) node _T_2180 = eq(stq_succeeded[10], UInt<1>(0h0)) node _T_2181 = and(_T_2179, _T_2180) when _T_2181 : connect stq_valid[10], UInt<1>(0h0) node _T_2182 = eq(stq_committed[11], UInt<1>(0h0)) node _T_2183 = eq(stq_succeeded[11], UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : connect stq_valid[11], UInt<1>(0h0) node _T_2185 = eq(stq_committed[12], UInt<1>(0h0)) node _T_2186 = eq(stq_succeeded[12], UInt<1>(0h0)) node _T_2187 = and(_T_2185, _T_2186) when _T_2187 : connect stq_valid[12], UInt<1>(0h0) node _T_2188 = eq(stq_committed[13], UInt<1>(0h0)) node _T_2189 = eq(stq_succeeded[13], UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : connect stq_valid[13], UInt<1>(0h0) node _T_2191 = eq(stq_committed[14], UInt<1>(0h0)) node _T_2192 = eq(stq_succeeded[14], UInt<1>(0h0)) node _T_2193 = and(_T_2191, _T_2192) when _T_2193 : connect stq_valid[14], UInt<1>(0h0) node _T_2194 = eq(stq_committed[15], UInt<1>(0h0)) node _T_2195 = eq(stq_succeeded[15], UInt<1>(0h0)) node _T_2196 = and(_T_2194, _T_2195) when _T_2196 : connect stq_valid[15], UInt<1>(0h0) node _T_2197 = eq(stq_committed[16], UInt<1>(0h0)) node _T_2198 = eq(stq_succeeded[16], UInt<1>(0h0)) node _T_2199 = and(_T_2197, _T_2198) when _T_2199 : connect stq_valid[16], UInt<1>(0h0) node _T_2200 = eq(stq_committed[17], UInt<1>(0h0)) node _T_2201 = eq(stq_succeeded[17], UInt<1>(0h0)) node _T_2202 = and(_T_2200, _T_2201) when _T_2202 : connect stq_valid[17], UInt<1>(0h0) node _T_2203 = eq(stq_committed[18], UInt<1>(0h0)) node _T_2204 = eq(stq_succeeded[18], UInt<1>(0h0)) node _T_2205 = and(_T_2203, _T_2204) when _T_2205 : connect stq_valid[18], UInt<1>(0h0) node _T_2206 = eq(stq_committed[19], UInt<1>(0h0)) node _T_2207 = eq(stq_succeeded[19], UInt<1>(0h0)) node _T_2208 = and(_T_2206, _T_2207) when _T_2208 : connect stq_valid[19], UInt<1>(0h0) node _T_2209 = eq(stq_committed[20], UInt<1>(0h0)) node _T_2210 = eq(stq_succeeded[20], UInt<1>(0h0)) node _T_2211 = and(_T_2209, _T_2210) when _T_2211 : connect stq_valid[20], UInt<1>(0h0) node _T_2212 = eq(stq_committed[21], UInt<1>(0h0)) node _T_2213 = eq(stq_succeeded[21], UInt<1>(0h0)) node _T_2214 = and(_T_2212, _T_2213) when _T_2214 : connect stq_valid[21], UInt<1>(0h0) node _T_2215 = eq(stq_committed[22], UInt<1>(0h0)) node _T_2216 = eq(stq_succeeded[22], UInt<1>(0h0)) node _T_2217 = and(_T_2215, _T_2216) when _T_2217 : connect stq_valid[22], UInt<1>(0h0) node _T_2218 = eq(stq_committed[23], UInt<1>(0h0)) node _T_2219 = eq(stq_succeeded[23], UInt<1>(0h0)) node _T_2220 = and(_T_2218, _T_2219) when _T_2220 : connect stq_valid[23], UInt<1>(0h0) connect ldq_valid[0], UInt<1>(0h0) connect ldq_valid[1], UInt<1>(0h0) connect ldq_valid[2], UInt<1>(0h0) connect ldq_valid[3], UInt<1>(0h0) connect ldq_valid[4], UInt<1>(0h0) connect ldq_valid[5], UInt<1>(0h0) connect ldq_valid[6], UInt<1>(0h0) connect ldq_valid[7], UInt<1>(0h0) connect ldq_valid[8], UInt<1>(0h0) connect ldq_valid[9], UInt<1>(0h0) connect ldq_valid[10], UInt<1>(0h0) connect ldq_valid[11], UInt<1>(0h0) connect ldq_valid[12], UInt<1>(0h0) connect ldq_valid[13], UInt<1>(0h0) connect ldq_valid[14], UInt<1>(0h0) connect ldq_valid[15], UInt<1>(0h0) connect ldq_valid[16], UInt<1>(0h0) connect ldq_valid[17], UInt<1>(0h0) connect ldq_valid[18], UInt<1>(0h0) connect ldq_valid[19], UInt<1>(0h0) connect ldq_valid[20], UInt<1>(0h0) connect ldq_valid[21], UInt<1>(0h0) connect ldq_valid[22], UInt<1>(0h0) connect ldq_valid[23], UInt<1>(0h0)

module LSU( // @[lsu.scala:211:7] input clock, // @[lsu.scala:211:7] input reset, // @[lsu.scala:211:7] input io_ptw_req_ready, // @[lsu.scala:214:14] output io_ptw_req_valid, // @[lsu.scala:214:14] output io_ptw_req_bits_valid, // @[lsu.scala:214:14] output [26:0] io_ptw_req_bits_bits_addr, // @[lsu.scala:214:14] input io_ptw_resp_valid, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_ptw, // @[lsu.scala:214:14] input io_ptw_resp_bits_ae_final, // @[lsu.scala:214:14] input io_ptw_resp_bits_pf, // @[lsu.scala:214:14] input io_ptw_resp_bits_gf, // @[lsu.scala:214:14] input io_ptw_resp_bits_hr, // @[lsu.scala:214:14] input io_ptw_resp_bits_hw, // @[lsu.scala:214:14] input io_ptw_resp_bits_hx, // @[lsu.scala:214:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[lsu.scala:214:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_d, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_a, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_g, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_u, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_x, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_w, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_r, // @[lsu.scala:214:14] input io_ptw_resp_bits_pte_v, // @[lsu.scala:214:14] input [1:0] io_ptw_resp_bits_level, // @[lsu.scala:214:14] input io_ptw_resp_bits_homogeneous, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_valid, // @[lsu.scala:214:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[lsu.scala:214:14] input io_ptw_resp_bits_gpa_is_pte, // @[lsu.scala:214:14] input [3:0] io_ptw_ptbr_mode, // @[lsu.scala:214:14] input [43:0] io_ptw_ptbr_ppn, // @[lsu.scala:214:14] input io_ptw_status_debug, // @[lsu.scala:214:14] input io_ptw_status_cease, // @[lsu.scala:214:14] input io_ptw_status_wfi, // @[lsu.scala:214:14] input [1:0] io_ptw_status_dprv, // @[lsu.scala:214:14] input io_ptw_status_dv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_prv, // @[lsu.scala:214:14] input io_ptw_status_v, // @[lsu.scala:214:14] input io_ptw_status_sd, // @[lsu.scala:214:14] input io_ptw_status_mpv, // @[lsu.scala:214:14] input io_ptw_status_gva, // @[lsu.scala:214:14] input io_ptw_status_tsr, // @[lsu.scala:214:14] input io_ptw_status_tw, // @[lsu.scala:214:14] input io_ptw_status_tvm, // @[lsu.scala:214:14] input io_ptw_status_mxr, // @[lsu.scala:214:14] input io_ptw_status_sum, // @[lsu.scala:214:14] input io_ptw_status_mprv, // @[lsu.scala:214:14] input [1:0] io_ptw_status_fs, // @[lsu.scala:214:14] input [1:0] io_ptw_status_mpp, // @[lsu.scala:214:14] input io_ptw_status_spp, // @[lsu.scala:214:14] input io_ptw_status_mpie, // @[lsu.scala:214:14] input io_ptw_status_spie, // @[lsu.scala:214:14] input io_ptw_status_mie, // @[lsu.scala:214:14] input io_ptw_status_sie, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_0_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_0_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_0_mask, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_1_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_1_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_1_mask, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_2_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_2_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_2_mask, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_3_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_3_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_3_mask, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_4_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_4_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_4_mask, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_5_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_5_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_5_mask, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_6_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_6_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_6_mask, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_l, // @[lsu.scala:214:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_x, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_w, // @[lsu.scala:214:14] input io_ptw_pmp_7_cfg_r, // @[lsu.scala:214:14] input [29:0] io_ptw_pmp_7_addr, // @[lsu.scala:214:14] input [31:0] io_ptw_pmp_7_mask, // @[lsu.scala:214:14] input io_core_agen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_agen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_agen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_agen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_agen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_agen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_agen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_agen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_agen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_agen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_agen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_agen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_agen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_0_bits_data, // @[lsu.scala:214:14] input io_core_dgen_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_1_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_1_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_1_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_1_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_1_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_1_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_1_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_1_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_1_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_1_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_1_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_1_bits_data, // @[lsu.scala:214:14] input io_core_dgen_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_dgen_2_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dgen_2_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dgen_2_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dgen_2_bits_uop_br_type, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_amo, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_eret, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_taken, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dgen_2_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_ppred, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dgen_2_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_mem_size, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_is_unique, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dgen_2_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dgen_2_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dgen_2_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_dgen_2_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dgen_2_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_core_dgen_2_bits_data, // @[lsu.scala:214:14] output io_core_iwakeups_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iwakeups_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iwakeups_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_iwakeups_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iwakeups_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iwakeups_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iwakeups_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iwakeups_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iwakeups_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iwakeups_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iwakeups_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_bypassable, // @[lsu.scala:214:14] output [2:0] io_core_iwakeups_0_bits_speculative_mask, // @[lsu.scala:214:14] output io_core_iwakeups_0_bits_rebusy, // @[lsu.scala:214:14] output io_core_iresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_iresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_iresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_iresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_iresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_iresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_iresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_iresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_iresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_iresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_iresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_iresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_iresp_0_bits_data, // @[lsu.scala:214:14] output io_core_fresp_0_valid, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_fresp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_fresp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_fresp_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_fresp_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_taken, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_fresp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_fresp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_fresp_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_fresp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_fresp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_fresp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_fresp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [63:0] io_core_fresp_0_bits_data, // @[lsu.scala:214:14] input io_core_sfence_valid, // @[lsu.scala:214:14] input io_core_sfence_bits_rs1, // @[lsu.scala:214:14] input io_core_sfence_bits_rs2, // @[lsu.scala:214:14] input [38:0] io_core_sfence_bits_addr, // @[lsu.scala:214:14] input io_core_sfence_bits_asid, // @[lsu.scala:214:14] input io_core_sfence_bits_hv, // @[lsu.scala:214:14] input io_core_sfence_bits_hg, // @[lsu.scala:214:14] input io_core_dis_uops_0_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_0_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_0_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_0_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_0_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_0_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_0_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_0_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_0_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_0_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_0_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_0_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_0_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_1_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_1_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_1_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_1_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_1_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_1_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_1_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_1_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_1_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_1_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_1_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_1_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_1_bits_debug_tsrc, // @[lsu.scala:214:14] input io_core_dis_uops_2_valid, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_2_bits_inst, // @[lsu.scala:214:14] input [31:0] io_core_dis_uops_2_bits_debug_inst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_dis_uops_2_bits_debug_pc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_0, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iq_type_3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_0, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_4, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_5, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_6, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_7, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_8, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fu_code_9, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_dis_uops_2_bits_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_2_bits_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_dis_uops_2_bits_br_type, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sfb, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_fence, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_fencei, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sfence, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_amo, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_eret, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_rocc, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ftq_idx, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_pc_lob, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_taken, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_pimm, // @[lsu.scala:214:14] input [19:0] io_core_dis_uops_2_bits_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_op2_sel, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_pdst, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs1, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs2, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_prs3, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_ppred, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs1_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs2_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_prs3_busy, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_dis_uops_2_bits_stale_pdst, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_exception, // @[lsu.scala:214:14] input [63:0] io_core_dis_uops_2_bits_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_mem_size, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_mem_signed, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_uses_ldq, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_uses_stq, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_is_unique, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_csr_cmd, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_ldst, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_dis_uops_2_bits_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_lrs2_rtype, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_frs3_en, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_dis_uops_2_bits_fcn_op, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_dis_uops_2_bits_fp_typ, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_bp_debug_if, // @[lsu.scala:214:14] input io_core_dis_uops_2_bits_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_dis_uops_2_bits_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_0, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_1, // @[lsu.scala:214:14] output [4:0] io_core_dis_ldq_idx_2, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_0, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_1, // @[lsu.scala:214:14] output [4:0] io_core_dis_stq_idx_2, // @[lsu.scala:214:14] output io_core_ldq_full_0, // @[lsu.scala:214:14] output io_core_ldq_full_1, // @[lsu.scala:214:14] output io_core_ldq_full_2, // @[lsu.scala:214:14] output io_core_stq_full_0, // @[lsu.scala:214:14] output io_core_stq_full_1, // @[lsu.scala:214:14] output io_core_stq_full_2, // @[lsu.scala:214:14] input io_core_commit_valids_0, // @[lsu.scala:214:14] input io_core_commit_valids_1, // @[lsu.scala:214:14] input io_core_commit_valids_2, // @[lsu.scala:214:14] input io_core_commit_arch_valids_0, // @[lsu.scala:214:14] input io_core_commit_arch_valids_1, // @[lsu.scala:214:14] input io_core_commit_arch_valids_2, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_0_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_0_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_0_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_0_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_0_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_0_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_0_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_0_taken, // @[lsu.scala:214:14] input io_core_commit_uops_0_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_0_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_0_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_0_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_0_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_0_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_0_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_0_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_0_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_0_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_0_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_0_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_0_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_0_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_0_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_0_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_0_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_0_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_0_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_1_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_1_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_1_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_1_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_1_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_1_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_1_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_1_taken, // @[lsu.scala:214:14] input io_core_commit_uops_1_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_1_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_1_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_1_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_1_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_1_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_1_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_1_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_1_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_1_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_1_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_1_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_1_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_1_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_1_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_1_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_1_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_1_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_1_debug_tsrc, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_2_inst, // @[lsu.scala:214:14] input [31:0] io_core_commit_uops_2_debug_inst, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_commit_uops_2_debug_pc, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_0, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_1, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_2, // @[lsu.scala:214:14] input io_core_commit_uops_2_iq_type_3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_0, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_1, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_2, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_4, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_5, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_6, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_7, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_8, // @[lsu.scala:214:14] input io_core_commit_uops_2_fu_code_9, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_commit_uops_2_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_commit_uops_2_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_2_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_commit_uops_2_br_type, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sfb, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_fence, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_fencei, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sfence, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_amo, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_eret, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_rocc, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ftq_idx, // @[lsu.scala:214:14] input io_core_commit_uops_2_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_pc_lob, // @[lsu.scala:214:14] input io_core_commit_uops_2_taken, // @[lsu.scala:214:14] input io_core_commit_uops_2_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_pimm, // @[lsu.scala:214:14] input [19:0] io_core_commit_uops_2_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_op2_sel, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_pdst, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs1, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs2, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_prs3, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_ppred, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs1_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs2_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_prs3_busy, // @[lsu.scala:214:14] input io_core_commit_uops_2_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_commit_uops_2_stale_pdst, // @[lsu.scala:214:14] input io_core_commit_uops_2_exception, // @[lsu.scala:214:14] input [63:0] io_core_commit_uops_2_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_mem_size, // @[lsu.scala:214:14] input io_core_commit_uops_2_mem_signed, // @[lsu.scala:214:14] input io_core_commit_uops_2_uses_ldq, // @[lsu.scala:214:14] input io_core_commit_uops_2_uses_stq, // @[lsu.scala:214:14] input io_core_commit_uops_2_is_unique, // @[lsu.scala:214:14] input io_core_commit_uops_2_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_csr_cmd, // @[lsu.scala:214:14] input io_core_commit_uops_2_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_ldst, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_commit_uops_2_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_lrs2_rtype, // @[lsu.scala:214:14] input io_core_commit_uops_2_frs3_en, // @[lsu.scala:214:14] input io_core_commit_uops_2_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_commit_uops_2_fcn_op, // @[lsu.scala:214:14] input io_core_commit_uops_2_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_commit_uops_2_fp_typ, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_bp_debug_if, // @[lsu.scala:214:14] input io_core_commit_uops_2_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_commit_uops_2_debug_tsrc, // @[lsu.scala:214:14] input io_core_commit_fflags_valid, // @[lsu.scala:214:14] input [4:0] io_core_commit_fflags_bits, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_0, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_1, // @[lsu.scala:214:14] input [63:0] io_core_commit_debug_wdata_2, // @[lsu.scala:214:14] input io_core_commit_load_at_rob_head, // @[lsu.scala:214:14] output io_core_clr_bsy_0_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_0_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_1_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_1_bits, // @[lsu.scala:214:14] output io_core_clr_bsy_2_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_bsy_2_bits, // @[lsu.scala:214:14] output io_core_clr_unsafe_0_valid, // @[lsu.scala:214:14] output [6:0] io_core_clr_unsafe_0_bits, // @[lsu.scala:214:14] input io_core_fence_dmem, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_inst, // @[lsu.scala:214:14] input [31:0] io_core_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_core_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_core_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_taken, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_core_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_core_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_exception, // @[lsu.scala:214:14] input [63:0] io_core_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_core_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_core_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] input io_core_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] input io_core_brupdate_b2_mispredict, // @[lsu.scala:214:14] input io_core_brupdate_b2_taken, // @[lsu.scala:214:14] input [2:0] io_core_brupdate_b2_cfi_type, // @[lsu.scala:214:14] input [1:0] io_core_brupdate_b2_pc_sel, // @[lsu.scala:214:14] input [39:0] io_core_brupdate_b2_jalr_target, // @[lsu.scala:214:14] input [20:0] io_core_brupdate_b2_target_offset, // @[lsu.scala:214:14] input [6:0] io_core_rob_pnr_idx, // @[lsu.scala:214:14] input [6:0] io_core_rob_head_idx, // @[lsu.scala:214:14] input io_core_exception, // @[lsu.scala:214:14] output io_core_fencei_rdy, // @[lsu.scala:214:14] output io_core_lxcpt_valid, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_core_lxcpt_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_core_lxcpt_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_core_lxcpt_bits_uop_br_type, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_amo, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_eret, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_taken, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_core_lxcpt_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_ppred, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_core_lxcpt_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_core_lxcpt_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_mem_size, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_is_unique, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_core_lxcpt_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_core_lxcpt_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_core_lxcpt_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_core_lxcpt_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [4:0] io_core_lxcpt_bits_cause, // @[lsu.scala:214:14] output [39:0] io_core_lxcpt_bits_badvaddr, // @[lsu.scala:214:14] input [63:0] io_core_tsc_reg, // @[lsu.scala:214:14] input io_core_status_debug, // @[lsu.scala:214:14] input io_core_status_cease, // @[lsu.scala:214:14] input io_core_status_wfi, // @[lsu.scala:214:14] input [1:0] io_core_status_dprv, // @[lsu.scala:214:14] input io_core_status_dv, // @[lsu.scala:214:14] input [1:0] io_core_status_prv, // @[lsu.scala:214:14] input io_core_status_v, // @[lsu.scala:214:14] input io_core_status_sd, // @[lsu.scala:214:14] input io_core_status_mpv, // @[lsu.scala:214:14] input io_core_status_gva, // @[lsu.scala:214:14] input io_core_status_tsr, // @[lsu.scala:214:14] input io_core_status_tw, // @[lsu.scala:214:14] input io_core_status_tvm, // @[lsu.scala:214:14] input io_core_status_mxr, // @[lsu.scala:214:14] input io_core_status_sum, // @[lsu.scala:214:14] input io_core_status_mprv, // @[lsu.scala:214:14] input [1:0] io_core_status_fs, // @[lsu.scala:214:14] input [1:0] io_core_status_mpp, // @[lsu.scala:214:14] input io_core_status_spp, // @[lsu.scala:214:14] input io_core_status_mpie, // @[lsu.scala:214:14] input io_core_status_spie, // @[lsu.scala:214:14] input io_core_status_mie, // @[lsu.scala:214:14] input io_core_status_sie, // @[lsu.scala:214:14] output io_core_perf_acquire, // @[lsu.scala:214:14] output io_core_perf_release, // @[lsu.scala:214:14] output io_core_perf_tlbMiss, // @[lsu.scala:214:14] input io_dmem_req_ready, // @[lsu.scala:214:14] output io_dmem_req_valid, // @[lsu.scala:214:14] output io_dmem_req_bits_0_valid, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_dmem_req_bits_0_bits_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_req_bits_0_bits_uop_br_type, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_taken, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_ppred, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_req_bits_0_bits_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_req_bits_0_bits_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_req_bits_0_bits_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] output [39:0] io_dmem_req_bits_0_bits_addr, // @[lsu.scala:214:14] output [63:0] io_dmem_req_bits_0_bits_data, // @[lsu.scala:214:14] output io_dmem_req_bits_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_s1_kill_0, // @[lsu.scala:214:14] input io_dmem_resp_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_resp_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_resp_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_resp_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_resp_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_resp_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_resp_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_resp_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_resp_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_resp_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_resp_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_resp_0_bits_data, // @[lsu.scala:214:14] input io_dmem_resp_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_store_ack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_store_ack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_store_ack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_store_ack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_store_ack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_store_ack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_store_ack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_store_ack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_store_ack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_store_ack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_store_ack_0_bits_is_hella, // @[lsu.scala:214:14] input io_dmem_nack_0_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_nack_0_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_nack_0_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_nack_0_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_nack_0_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_nack_0_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_nack_0_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_nack_0_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_nack_0_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_nack_0_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [39:0] io_dmem_nack_0_bits_addr, // @[lsu.scala:214:14] input [63:0] io_dmem_nack_0_bits_data, // @[lsu.scala:214:14] input io_dmem_nack_0_bits_is_hella, // @[lsu.scala:214:14] output io_dmem_ll_resp_ready, // @[lsu.scala:214:14] input io_dmem_ll_resp_valid, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_inst, // @[lsu.scala:214:14] input [31:0] io_dmem_ll_resp_bits_uop_debug_inst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rvc, // @[lsu.scala:214:14] input [39:0] io_dmem_ll_resp_bits_uop_debug_pc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iq_type_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_0, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_4, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_5, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_6, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_7, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_8, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fu_code_9, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_dis_col_sel, // @[lsu.scala:214:14] input [15:0] io_dmem_ll_resp_bits_uop_br_mask, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_tag, // @[lsu.scala:214:14] input [3:0] io_dmem_ll_resp_bits_uop_br_type, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfb, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_fencei, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sfence, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_amo, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_eret, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_sys_pc2epc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_rocc, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_mov, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ftq_idx, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_edge_inst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_pc_lob, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_taken, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_imm_rename, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_imm_sel, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_pimm, // @[lsu.scala:214:14] input [19:0] io_dmem_ll_resp_bits_uop_imm_packed, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_op1_sel, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_op2_sel, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wen, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_toint, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_fma, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_div, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_ctrl_vec, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_rob_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ldq_idx, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_stq_idx, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_rxq_idx, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_pdst, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs1, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs2, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_prs3, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_ppred, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs1_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs2_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_prs3_busy, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ppred_busy, // @[lsu.scala:214:14] input [6:0] io_dmem_ll_resp_bits_uop_stale_pdst, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_exception, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_uop_exc_cause, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_mem_cmd, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_mem_size, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_mem_signed, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_ldq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_uses_stq, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_is_unique, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_flush_on_commit, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_csr_cmd, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_ldst_is_rs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_ldst, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs1, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs2, // @[lsu.scala:214:14] input [5:0] io_dmem_ll_resp_bits_uop_lrs3, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_dst_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_frs3_en, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fcn_dw, // @[lsu.scala:214:14] input [4:0] io_dmem_ll_resp_bits_uop_fcn_op, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_fp_val, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_fp_rm, // @[lsu.scala:214:14] input [1:0] io_dmem_ll_resp_bits_uop_fp_typ, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_pf_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ae_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_xcpt_ma_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_debug_if, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_uop_bp_xcpt_if, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc, // @[lsu.scala:214:14] input [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc, // @[lsu.scala:214:14] input [63:0] io_dmem_ll_resp_bits_data, // @[lsu.scala:214:14] input io_dmem_ll_resp_bits_is_hella, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b1_resolve_mask, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b1_mispredict_mask, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_inst, // @[lsu.scala:214:14] output [31:0] io_dmem_brupdate_b2_uop_debug_inst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rvc, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_uop_debug_pc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iq_type_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_0, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_4, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_5, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_6, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_7, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_8, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fu_code_9, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_agen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_issued_partial_dgen, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p1_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p2_bypass_hint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_iw_p3_bypass_hint, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_dis_col_sel, // @[lsu.scala:214:14] output [15:0] io_dmem_brupdate_b2_uop_br_mask, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_tag, // @[lsu.scala:214:14] output [3:0] io_dmem_brupdate_b2_uop_br_type, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfb, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_fencei, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sfence, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_amo, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_eret, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_sys_pc2epc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_rocc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_mov, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ftq_idx, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_edge_inst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_pc_lob, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_taken, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_imm_rename, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_imm_sel, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_pimm, // @[lsu.scala:214:14] output [19:0] io_dmem_brupdate_b2_uop_imm_packed, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_op1_sel, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_op2_sel, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ldst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wen, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren1, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren2, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_ren3, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap12, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_swap23, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fromint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_toint, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_fma, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_div, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_sqrt, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_wflags, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_ctrl_vec, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_rob_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ldq_idx, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_stq_idx, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_rxq_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_pdst, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs1, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs2, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_prs3, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_ppred, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs1_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs2_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_prs3_busy, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ppred_busy, // @[lsu.scala:214:14] output [6:0] io_dmem_brupdate_b2_uop_stale_pdst, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_exception, // @[lsu.scala:214:14] output [63:0] io_dmem_brupdate_b2_uop_exc_cause, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_mem_cmd, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_mem_size, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_mem_signed, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_ldq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_uses_stq, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_is_unique, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_flush_on_commit, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_csr_cmd, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_ldst_is_rs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_ldst, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs1, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs2, // @[lsu.scala:214:14] output [5:0] io_dmem_brupdate_b2_uop_lrs3, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_dst_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_frs3_en, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fcn_dw, // @[lsu.scala:214:14] output [4:0] io_dmem_brupdate_b2_uop_fcn_op, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_fp_val, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_fp_rm, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_uop_fp_typ, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_pf_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ae_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_xcpt_ma_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_debug_if, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_uop_bp_xcpt_if, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_fsrc, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_uop_debug_tsrc, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_mispredict, // @[lsu.scala:214:14] output io_dmem_brupdate_b2_taken, // @[lsu.scala:214:14] output [2:0] io_dmem_brupdate_b2_cfi_type, // @[lsu.scala:214:14] output [1:0] io_dmem_brupdate_b2_pc_sel, // @[lsu.scala:214:14] output [39:0] io_dmem_brupdate_b2_jalr_target, // @[lsu.scala:214:14] output [20:0] io_dmem_brupdate_b2_target_offset, // @[lsu.scala:214:14] output io_dmem_exception, // @[lsu.scala:214:14] output [6:0] io_dmem_rob_pnr_idx, // @[lsu.scala:214:14] output [6:0] io_dmem_rob_head_idx, // @[lsu.scala:214:14] output io_dmem_release_ready, // @[lsu.scala:214:14] input io_dmem_release_valid, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_opcode, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_param, // @[lsu.scala:214:14] input [3:0] io_dmem_release_bits_size, // @[lsu.scala:214:14] input [2:0] io_dmem_release_bits_source, // @[lsu.scala:214:14] input [31:0] io_dmem_release_bits_address, // @[lsu.scala:214:14] input [127:0] io_dmem_release_bits_data, // @[lsu.scala:214:14] output io_dmem_force_order, // @[lsu.scala:214:14] input io_dmem_ordered, // @[lsu.scala:214:14] input io_dmem_perf_acquire, // @[lsu.scala:214:14] input io_dmem_perf_release, // @[lsu.scala:214:14] output io_hellacache_req_ready, // @[lsu.scala:214:14] input io_hellacache_req_valid, // @[lsu.scala:214:14] input [39:0] io_hellacache_req_bits_addr, // @[lsu.scala:214:14] input io_hellacache_req_bits_dv, // @[lsu.scala:214:14] input io_hellacache_s1_kill, // @[lsu.scala:214:14] output io_hellacache_s2_nack, // @[lsu.scala:214:14] output io_hellacache_resp_valid, // @[lsu.scala:214:14] output [39:0] io_hellacache_resp_bits_addr, // @[lsu.scala:214:14] output [1:0] io_hellacache_resp_bits_dprv, // @[lsu.scala:214:14] output io_hellacache_resp_bits_dv, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_word_bypass, // @[lsu.scala:214:14] output [63:0] io_hellacache_resp_bits_data_raw, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ma_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_pf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_gf_st, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_ld, // @[lsu.scala:214:14] output io_hellacache_s2_xcpt_ae_st, // @[lsu.scala:214:14] output io_hellacache_store_pending // @[lsu.scala:214:14] ); wire [2:0] wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1494:29] wire [63:0] wb_slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1494:29] wire [6:0] wb_slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1494:29] wire [19:0] wb_slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1494:29] wire [5:0] wb_slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1494:29] wire [4:0] wb_slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1494:29] wire [3:0] wb_slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1494:29] wire [2:0] wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1494:29] wire [39:0] wb_slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1494:29] wire [31:0] wb_slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1494:29] wire [1:0] wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1494:29] wire [63:0] iresp_0_bits_data; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_typ; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_fp_rm; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_val; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_fcn_op; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fcn_dw; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_frs3_en; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_dst_rtype; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs3; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs2; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_lrs1; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_csr_cmd; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_unique; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_stq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_uses_ldq; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_mem_signed; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_mem_size; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_mem_cmd; // @[lsu.scala:1477:19] wire [63:0] iresp_0_bits_uop_exc_cause; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_exception; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_stale_pdst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_ppred_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs3_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs2_busy; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_prs1_busy; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ppred; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs3; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs2; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_prs1; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_pdst; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_rxq_idx; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_stq_idx; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ldq_idx; // @[lsu.scala:1477:19] wire [6:0] iresp_0_bits_uop_rob_idx; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_op2_sel; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_op1_sel; // @[lsu.scala:1477:19] wire [19:0] iresp_0_bits_uop_imm_packed; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_pimm; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_imm_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_imm_rename; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_taken; // @[lsu.scala:1477:19] wire [5:0] iresp_0_bits_uop_pc_lob; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_edge_inst; // @[lsu.scala:1477:19] wire [4:0] iresp_0_bits_uop_ftq_idx; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_mov; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rocc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_eret; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_amo; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fencei; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_fence; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_sfb; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_type; // @[lsu.scala:1477:19] wire [3:0] iresp_0_bits_uop_br_tag; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1477:19] wire [2:0] iresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iw_issued; // @[lsu.scala:1477:19] wire [39:0] iresp_0_bits_uop_debug_pc; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_is_rvc; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_debug_inst; // @[lsu.scala:1477:19] wire [31:0] iresp_0_bits_uop_inst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1477:19] wire [1:0] iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_9; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_8; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_7; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_6; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_5; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_4; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_fu_code_0; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_3; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_2; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_1; // @[lsu.scala:1477:19] wire iresp_0_bits_uop_iq_type_0; // @[lsu.scala:1477:19] wire [63:0] wb_ldst_forward_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] wb_ldst_forward_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] wb_ldst_forward_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_observed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_order_fail; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_succeeded; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_executed; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] wb_ldst_forward_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] wb_ldst_forward_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] wb_ldst_forward_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] wb_ldst_forward_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] wb_ldst_forward_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] wb_ldst_forward_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] wb_ldst_forward_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire [2:0] s_uop_2_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_2_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_2_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_2_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_fp_rm; // @[lsu.scala:1093:25] wire s_uop_2_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_fcn_op; // @[lsu.scala:1093:25] wire s_uop_2_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_2_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_ldst; // @[lsu.scala:1093:25] wire s_uop_2_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_2_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_2_is_unique; // @[lsu.scala:1093:25] wire s_uop_2_uses_stq; // @[lsu.scala:1093:25] wire s_uop_2_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_2_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_2_exc_cause; // @[lsu.scala:1093:25] wire s_uop_2_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_2_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_2_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_2_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_2_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_imm_sel; // @[lsu.scala:1093:25] wire s_uop_2_imm_rename; // @[lsu.scala:1093:25] wire s_uop_2_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_2_pc_lob; // @[lsu.scala:1093:25] wire s_uop_2_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_2_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_2_is_mov; // @[lsu.scala:1093:25] wire s_uop_2_is_rocc; // @[lsu.scala:1093:25] wire s_uop_2_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_2_is_eret; // @[lsu.scala:1093:25] wire s_uop_2_is_amo; // @[lsu.scala:1093:25] wire s_uop_2_is_sfence; // @[lsu.scala:1093:25] wire s_uop_2_is_fencei; // @[lsu.scala:1093:25] wire s_uop_2_is_fence; // @[lsu.scala:1093:25] wire s_uop_2_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_2_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_2_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_2_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_2_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_2_debug_pc; // @[lsu.scala:1093:25] wire s_uop_2_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_2_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_2_inst; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_2_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_2_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_2_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_1_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_1_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_1_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_fp_rm; // @[lsu.scala:1093:25] wire s_uop_1_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_fcn_op; // @[lsu.scala:1093:25] wire s_uop_1_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_1_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_ldst; // @[lsu.scala:1093:25] wire s_uop_1_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_1_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_1_is_unique; // @[lsu.scala:1093:25] wire s_uop_1_uses_stq; // @[lsu.scala:1093:25] wire s_uop_1_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_1_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_1_exc_cause; // @[lsu.scala:1093:25] wire s_uop_1_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_1_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_1_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_1_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_1_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_imm_sel; // @[lsu.scala:1093:25] wire s_uop_1_imm_rename; // @[lsu.scala:1093:25] wire s_uop_1_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_1_pc_lob; // @[lsu.scala:1093:25] wire s_uop_1_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_1_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_1_is_mov; // @[lsu.scala:1093:25] wire s_uop_1_is_rocc; // @[lsu.scala:1093:25] wire s_uop_1_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_1_is_eret; // @[lsu.scala:1093:25] wire s_uop_1_is_amo; // @[lsu.scala:1093:25] wire s_uop_1_is_sfence; // @[lsu.scala:1093:25] wire s_uop_1_is_fencei; // @[lsu.scala:1093:25] wire s_uop_1_is_fence; // @[lsu.scala:1093:25] wire s_uop_1_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_1_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_1_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_1_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_1_debug_pc; // @[lsu.scala:1093:25] wire s_uop_1_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_1_inst; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_1_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_1_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_1_iq_type_0; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_tsrc; // @[lsu.scala:1093:25] wire [2:0] s_uop_debug_fsrc; // @[lsu.scala:1093:25] wire s_uop_bp_xcpt_if; // @[lsu.scala:1093:25] wire s_uop_bp_debug_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ma_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_ae_if; // @[lsu.scala:1093:25] wire s_uop_xcpt_pf_if; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_typ; // @[lsu.scala:1093:25] wire [2:0] s_uop_fp_rm; // @[lsu.scala:1093:25] wire s_uop_fp_val; // @[lsu.scala:1093:25] wire [4:0] s_uop_fcn_op; // @[lsu.scala:1093:25] wire s_uop_fcn_dw; // @[lsu.scala:1093:25] wire s_uop_frs3_en; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs2_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_lrs1_rtype; // @[lsu.scala:1093:25] wire [1:0] s_uop_dst_rtype; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs3; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs2; // @[lsu.scala:1093:25] wire [5:0] s_uop_lrs1; // @[lsu.scala:1093:25] wire [5:0] s_uop_ldst; // @[lsu.scala:1093:25] wire s_uop_ldst_is_rs1; // @[lsu.scala:1093:25] wire [2:0] s_uop_csr_cmd; // @[lsu.scala:1093:25] wire s_uop_flush_on_commit; // @[lsu.scala:1093:25] wire s_uop_is_unique; // @[lsu.scala:1093:25] wire s_uop_uses_stq; // @[lsu.scala:1093:25] wire s_uop_uses_ldq; // @[lsu.scala:1093:25] wire s_uop_mem_signed; // @[lsu.scala:1093:25] wire [1:0] s_uop_mem_size; // @[lsu.scala:1093:25] wire [4:0] s_uop_mem_cmd; // @[lsu.scala:1093:25] wire [63:0] s_uop_exc_cause; // @[lsu.scala:1093:25] wire s_uop_exception; // @[lsu.scala:1093:25] wire [6:0] s_uop_stale_pdst; // @[lsu.scala:1093:25] wire s_uop_ppred_busy; // @[lsu.scala:1093:25] wire s_uop_prs3_busy; // @[lsu.scala:1093:25] wire s_uop_prs2_busy; // @[lsu.scala:1093:25] wire s_uop_prs1_busy; // @[lsu.scala:1093:25] wire [4:0] s_uop_ppred; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs3; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs2; // @[lsu.scala:1093:25] wire [6:0] s_uop_prs1; // @[lsu.scala:1093:25] wire [6:0] s_uop_pdst; // @[lsu.scala:1093:25] wire [1:0] s_uop_rxq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_stq_idx; // @[lsu.scala:1093:25] wire [4:0] s_uop_ldq_idx; // @[lsu.scala:1093:25] wire [6:0] s_uop_rob_idx; // @[lsu.scala:1093:25] wire [2:0] s_uop_op2_sel; // @[lsu.scala:1093:25] wire [1:0] s_uop_op1_sel; // @[lsu.scala:1093:25] wire [19:0] s_uop_imm_packed; // @[lsu.scala:1093:25] wire [4:0] s_uop_pimm; // @[lsu.scala:1093:25] wire [2:0] s_uop_imm_sel; // @[lsu.scala:1093:25] wire s_uop_imm_rename; // @[lsu.scala:1093:25] wire s_uop_taken; // @[lsu.scala:1093:25] wire [5:0] s_uop_pc_lob; // @[lsu.scala:1093:25] wire s_uop_edge_inst; // @[lsu.scala:1093:25] wire [4:0] s_uop_ftq_idx; // @[lsu.scala:1093:25] wire s_uop_is_mov; // @[lsu.scala:1093:25] wire s_uop_is_rocc; // @[lsu.scala:1093:25] wire s_uop_is_sys_pc2epc; // @[lsu.scala:1093:25] wire s_uop_is_eret; // @[lsu.scala:1093:25] wire s_uop_is_amo; // @[lsu.scala:1093:25] wire s_uop_is_sfence; // @[lsu.scala:1093:25] wire s_uop_is_fencei; // @[lsu.scala:1093:25] wire s_uop_is_fence; // @[lsu.scala:1093:25] wire s_uop_is_sfb; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_type; // @[lsu.scala:1093:25] wire [3:0] s_uop_br_tag; // @[lsu.scala:1093:25] wire [2:0] s_uop_dis_col_sel; // @[lsu.scala:1093:25] wire s_uop_iw_p3_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p2_bypass_hint; // @[lsu.scala:1093:25] wire s_uop_iw_p1_bypass_hint; // @[lsu.scala:1093:25] wire [2:0] s_uop_iw_p2_speculative_child; // @[lsu.scala:1093:25] wire [2:0] s_uop_iw_p1_speculative_child; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_dgen; // @[lsu.scala:1093:25] wire s_uop_iw_issued_partial_agen; // @[lsu.scala:1093:25] wire s_uop_iw_issued; // @[lsu.scala:1093:25] wire [39:0] s_uop_debug_pc; // @[lsu.scala:1093:25] wire s_uop_is_rvc; // @[lsu.scala:1093:25] wire [31:0] s_uop_debug_inst; // @[lsu.scala:1093:25] wire [31:0] s_uop_inst; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_vec; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wflags; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_sqrt; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_div; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fma; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fastpipe; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_toint; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_fromint; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1093:25] wire [1:0] s_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap23; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_swap12; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren3; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren2; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ren1; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_wen; // @[lsu.scala:1093:25] wire s_uop_fp_ctrl_ldst; // @[lsu.scala:1093:25] wire s_uop_fu_code_9; // @[lsu.scala:1093:25] wire s_uop_fu_code_8; // @[lsu.scala:1093:25] wire s_uop_fu_code_7; // @[lsu.scala:1093:25] wire s_uop_fu_code_6; // @[lsu.scala:1093:25] wire s_uop_fu_code_5; // @[lsu.scala:1093:25] wire s_uop_fu_code_4; // @[lsu.scala:1093:25] wire s_uop_fu_code_3; // @[lsu.scala:1093:25] wire s_uop_fu_code_2; // @[lsu.scala:1093:25] wire s_uop_fu_code_1; // @[lsu.scala:1093:25] wire s_uop_fu_code_0; // @[lsu.scala:1093:25] wire s_uop_iq_type_3; // @[lsu.scala:1093:25] wire s_uop_iq_type_2; // @[lsu.scala:1093:25] wire s_uop_iq_type_1; // @[lsu.scala:1093:25] wire s_uop_iq_type_0; // @[lsu.scala:1093:25] wire [63:0] mem_stq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] mem_stq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] mem_stq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] mem_stq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] mem_stq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] mem_stq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] mem_stq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] mem_stq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] mem_stq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire [63:0] mem_ldq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] mem_ldq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] mem_ldq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] mem_ldq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] mem_ldq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] mem_ldq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] mem_ldq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] mem_ldq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] mem_ldq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] mem_ldq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [15:0] mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [15:0] mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [15:0] mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [63:0] stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire stq_incoming_e_e_valid; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17] wire [63:0] stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17] wire [6:0] stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17] wire [19:0] stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17] wire [5:0] stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17] wire [4:0] stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17] wire [3:0] stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17] wire [15:0] stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17] wire [2:0] stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17] wire [39:0] stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17] wire [31:0] stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17] wire [1:0] stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17] wire stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17] wire ldq_incoming_e_e_valid; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17] wire [7:0] ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17] wire [23:0] ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17] wire [63:0] ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17] wire [6:0] ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17] wire [19:0] ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17] wire [5:0] ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17] wire [4:0] ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17] wire [3:0] ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17] wire [15:0] ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17] wire [2:0] ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17] wire [39:0] ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17] wire [31:0] ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17] wire [1:0] ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17] wire ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17] wire _logic_1_io_found; // @[lsu.scala:1965:23] wire [4:0] _logic_1_io_found_idx; // @[lsu.scala:1965:23] wire _logic_io_found; // @[lsu.scala:1965:23] wire [4:0] _logic_io_found_idx; // @[lsu.scala:1965:23] wire _wakeupArbs_0_io_in_1_ready; // @[lsu.scala:1016:47] wire _stq_execute_queue_io_enq_ready; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_valid; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_inst; // @[lsu.scala:558:11] wire [31:0] _stq_execute_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:558:11] wire [15:0] _stq_execute_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:558:11] wire [3:0] _stq_execute_queue_io_deq_bits_uop_br_type; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_taken; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_pimm; // @[lsu.scala:558:11] wire [19:0] _stq_execute_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_pdst; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs1; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs2; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_prs3; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_ppred; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:558:11] wire [6:0] _stq_execute_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_exception; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_ldst; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:558:11] wire [5:0] _stq_execute_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:558:11] wire [4:0] _stq_execute_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:558:11] wire [1:0] _stq_execute_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:558:11] wire _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:558:11] wire [2:0] _stq_execute_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:558:11] wire [39:0] _stq_execute_queue_io_deq_bits_addr_bits; // @[lsu.scala:558:11] wire [63:0] _stq_execute_queue_io_deq_bits_data_bits; // @[lsu.scala:558:11] wire _retry_queue_io_enq_ready; // @[lsu.scala:533:27] wire _retry_queue_io_deq_valid; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_inst; // @[lsu.scala:533:27] wire [31:0] _retry_queue_io_deq_bits_uop_debug_inst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27] wire [39:0] _retry_queue_io_deq_bits_uop_debug_pc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_iw_p1_speculative_child; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_iw_p2_speculative_child; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_dis_col_sel; // @[lsu.scala:533:27] wire [15:0] _retry_queue_io_deq_bits_uop_br_mask; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_tag; // @[lsu.scala:533:27] wire [3:0] _retry_queue_io_deq_bits_uop_br_type; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ftq_idx; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_pc_lob; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_imm_sel; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_pimm; // @[lsu.scala:533:27] wire [19:0] _retry_queue_io_deq_bits_uop_imm_packed; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_op1_sel; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_op2_sel; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_rob_idx; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_rxq_idx; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_pdst; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs1; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs2; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_prs3; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_ppred; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27] wire [6:0] _retry_queue_io_deq_bits_uop_stale_pdst; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_uop_exc_cause; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_mem_cmd; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_mem_size; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_csr_cmd; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_ldst; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs1; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs2; // @[lsu.scala:533:27] wire [5:0] _retry_queue_io_deq_bits_uop_lrs3; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_dst_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs1_rtype; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_lrs2_rtype; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27] wire [4:0] _retry_queue_io_deq_bits_uop_fcn_op; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_fp_rm; // @[lsu.scala:533:27] wire [1:0] _retry_queue_io_deq_bits_uop_fp_typ; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27] wire _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_fsrc; // @[lsu.scala:533:27] wire [2:0] _retry_queue_io_deq_bits_uop_debug_tsrc; // @[lsu.scala:533:27] wire [63:0] _retry_queue_io_deq_bits_data; // @[lsu.scala:533:27] wire [31:0] _dtlb_io_resp_0_paddr; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_pf_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ae_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_ld; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_ma_st; // @[lsu.scala:308:20] wire _dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[lsu.scala:211:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[lsu.scala:211:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[lsu.scala:211:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[lsu.scala:211:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[lsu.scala:211:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[lsu.scala:211:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[lsu.scala:211:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[lsu.scala:211:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[lsu.scala:211:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[lsu.scala:211:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[lsu.scala:211:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[lsu.scala:211:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[lsu.scala:211:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[lsu.scala:211:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[lsu.scala:211:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[lsu.scala:211:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[lsu.scala:211:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[lsu.scala:211:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[lsu.scala:211:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[lsu.scala:211:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[lsu.scala:211:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[lsu.scala:211:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[lsu.scala:211:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[lsu.scala:211:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[lsu.scala:211:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[lsu.scala:211:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[lsu.scala:211:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[lsu.scala:211:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[lsu.scala:211:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[lsu.scala:211:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[lsu.scala:211:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[lsu.scala:211:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[lsu.scala:211:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[lsu.scala:211:7] wire io_core_agen_0_valid_0 = io_core_agen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_inst_0 = io_core_agen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_agen_0_bits_uop_debug_inst_0 = io_core_agen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rvc_0 = io_core_agen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_agen_0_bits_uop_debug_pc_0 = io_core_agen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_0_0 = io_core_agen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_1_0 = io_core_agen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_2_0 = io_core_agen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iq_type_3_0 = io_core_agen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_0_0 = io_core_agen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_1_0 = io_core_agen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_2_0 = io_core_agen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_3_0 = io_core_agen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_4_0 = io_core_agen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_5_0 = io_core_agen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_6_0 = io_core_agen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_7_0 = io_core_agen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_8_0 = io_core_agen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fu_code_9_0 = io_core_agen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_0 = io_core_agen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_agen_0 = io_core_agen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_agen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_iw_p1_speculative_child_0 = io_core_agen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_iw_p2_speculative_child_0 = io_core_agen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_agen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_dis_col_sel_0 = io_core_agen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_agen_0_bits_uop_br_mask_0 = io_core_agen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_tag_0 = io_core_agen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_agen_0_bits_uop_br_type_0 = io_core_agen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfb_0 = io_core_agen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fence_0 = io_core_agen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_fencei_0 = io_core_agen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sfence_0 = io_core_agen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_amo_0 = io_core_agen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_eret_0 = io_core_agen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_sys_pc2epc_0 = io_core_agen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_rocc_0 = io_core_agen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_mov_0 = io_core_agen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ftq_idx_0 = io_core_agen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_edge_inst_0 = io_core_agen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_pc_lob_0 = io_core_agen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_taken_0 = io_core_agen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_imm_rename_0 = io_core_agen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_imm_sel_0 = io_core_agen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_pimm_0 = io_core_agen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_agen_0_bits_uop_imm_packed_0 = io_core_agen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_op1_sel_0 = io_core_agen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_op2_sel_0 = io_core_agen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ldst_0 = io_core_agen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wen_0 = io_core_agen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren1_0 = io_core_agen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren2_0 = io_core_agen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_ren3_0 = io_core_agen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap12_0 = io_core_agen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_swap23_0 = io_core_agen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fromint_0 = io_core_agen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_toint_0 = io_core_agen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_agen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_fma_0 = io_core_agen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_div_0 = io_core_agen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_agen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_wflags_0 = io_core_agen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_ctrl_vec_0 = io_core_agen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_rob_idx_0 = io_core_agen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ldq_idx_0 = io_core_agen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_stq_idx_0 = io_core_agen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_rxq_idx_0 = io_core_agen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_pdst_0 = io_core_agen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs1_0 = io_core_agen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs2_0 = io_core_agen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_prs3_0 = io_core_agen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_ppred_0 = io_core_agen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs1_busy_0 = io_core_agen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs2_busy_0 = io_core_agen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_prs3_busy_0 = io_core_agen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ppred_busy_0 = io_core_agen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_agen_0_bits_uop_stale_pdst_0 = io_core_agen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_exception_0 = io_core_agen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_uop_exc_cause_0 = io_core_agen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_mem_cmd_0 = io_core_agen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_mem_size_0 = io_core_agen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_mem_signed_0 = io_core_agen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_ldq_0 = io_core_agen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_uses_stq_0 = io_core_agen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_is_unique_0 = io_core_agen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_flush_on_commit_0 = io_core_agen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_csr_cmd_0 = io_core_agen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_ldst_is_rs1_0 = io_core_agen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_ldst_0 = io_core_agen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs1_0 = io_core_agen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs2_0 = io_core_agen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_agen_0_bits_uop_lrs3_0 = io_core_agen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_dst_rtype_0 = io_core_agen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs1_rtype_0 = io_core_agen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_lrs2_rtype_0 = io_core_agen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_frs3_en_0 = io_core_agen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fcn_dw_0 = io_core_agen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_agen_0_bits_uop_fcn_op_0 = io_core_agen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_fp_val_0 = io_core_agen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_fp_rm_0 = io_core_agen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_agen_0_bits_uop_fp_typ_0 = io_core_agen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_pf_if_0 = io_core_agen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ae_if_0 = io_core_agen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_xcpt_ma_if_0 = io_core_agen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_debug_if_0 = io_core_agen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_agen_0_bits_uop_bp_xcpt_if_0 = io_core_agen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_fsrc_0 = io_core_agen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_agen_0_bits_uop_debug_tsrc_0 = io_core_agen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_agen_0_bits_data_0 = io_core_agen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_0_valid_0 = io_core_dgen_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_inst_0 = io_core_dgen_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_0_bits_uop_debug_inst_0 = io_core_dgen_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rvc_0 = io_core_dgen_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_0_bits_uop_debug_pc_0 = io_core_dgen_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_0_0 = io_core_dgen_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_1_0 = io_core_dgen_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_2_0 = io_core_dgen_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iq_type_3_0 = io_core_dgen_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_0_0 = io_core_dgen_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_1_0 = io_core_dgen_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_2_0 = io_core_dgen_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_3_0 = io_core_dgen_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_4_0 = io_core_dgen_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_5_0 = io_core_dgen_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_6_0 = io_core_dgen_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_7_0 = io_core_dgen_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_8_0 = io_core_dgen_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fu_code_9_0 = io_core_dgen_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_0 = io_core_dgen_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_dis_col_sel_0 = io_core_dgen_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_0_bits_uop_br_mask_0 = io_core_dgen_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_tag_0 = io_core_dgen_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_0_bits_uop_br_type_0 = io_core_dgen_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfb_0 = io_core_dgen_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fence_0 = io_core_dgen_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_fencei_0 = io_core_dgen_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sfence_0 = io_core_dgen_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_amo_0 = io_core_dgen_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_eret_0 = io_core_dgen_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_sys_pc2epc_0 = io_core_dgen_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_rocc_0 = io_core_dgen_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_mov_0 = io_core_dgen_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ftq_idx_0 = io_core_dgen_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_edge_inst_0 = io_core_dgen_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_pc_lob_0 = io_core_dgen_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_taken_0 = io_core_dgen_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_imm_rename_0 = io_core_dgen_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_imm_sel_0 = io_core_dgen_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_pimm_0 = io_core_dgen_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_0_bits_uop_imm_packed_0 = io_core_dgen_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_op1_sel_0 = io_core_dgen_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_op2_sel_0 = io_core_dgen_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wen_0 = io_core_dgen_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_toint_0 = io_core_dgen_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_fma_0 = io_core_dgen_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_div_0 = io_core_dgen_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_ctrl_vec_0 = io_core_dgen_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_rob_idx_0 = io_core_dgen_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ldq_idx_0 = io_core_dgen_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_stq_idx_0 = io_core_dgen_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_rxq_idx_0 = io_core_dgen_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_pdst_0 = io_core_dgen_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs1_0 = io_core_dgen_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs2_0 = io_core_dgen_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_prs3_0 = io_core_dgen_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_ppred_0 = io_core_dgen_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs1_busy_0 = io_core_dgen_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs2_busy_0 = io_core_dgen_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_prs3_busy_0 = io_core_dgen_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ppred_busy_0 = io_core_dgen_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_0_bits_uop_stale_pdst_0 = io_core_dgen_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_exception_0 = io_core_dgen_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_uop_exc_cause_0 = io_core_dgen_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_mem_cmd_0 = io_core_dgen_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_mem_size_0 = io_core_dgen_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_mem_signed_0 = io_core_dgen_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_ldq_0 = io_core_dgen_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_uses_stq_0 = io_core_dgen_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_is_unique_0 = io_core_dgen_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_flush_on_commit_0 = io_core_dgen_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_csr_cmd_0 = io_core_dgen_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_ldst_is_rs1_0 = io_core_dgen_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_ldst_0 = io_core_dgen_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs1_0 = io_core_dgen_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs2_0 = io_core_dgen_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_0_bits_uop_lrs3_0 = io_core_dgen_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_dst_rtype_0 = io_core_dgen_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs1_rtype_0 = io_core_dgen_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_lrs2_rtype_0 = io_core_dgen_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_frs3_en_0 = io_core_dgen_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fcn_dw_0 = io_core_dgen_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_0_bits_uop_fcn_op_0 = io_core_dgen_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_fp_val_0 = io_core_dgen_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_fp_rm_0 = io_core_dgen_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_0_bits_uop_fp_typ_0 = io_core_dgen_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_pf_if_0 = io_core_dgen_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ae_if_0 = io_core_dgen_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_xcpt_ma_if_0 = io_core_dgen_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_debug_if_0 = io_core_dgen_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_0_bits_uop_bp_xcpt_if_0 = io_core_dgen_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_fsrc_0 = io_core_dgen_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_0_bits_uop_debug_tsrc_0 = io_core_dgen_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_0_bits_data_0 = io_core_dgen_0_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_1_valid_0 = io_core_dgen_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_inst_0 = io_core_dgen_1_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_1_bits_uop_debug_inst_0 = io_core_dgen_1_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rvc_0 = io_core_dgen_1_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_1_bits_uop_debug_pc_0 = io_core_dgen_1_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_0_0 = io_core_dgen_1_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_1_0 = io_core_dgen_1_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_2_0 = io_core_dgen_1_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iq_type_3_0 = io_core_dgen_1_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_0_0 = io_core_dgen_1_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_1_0 = io_core_dgen_1_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_2_0 = io_core_dgen_1_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_3_0 = io_core_dgen_1_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_4_0 = io_core_dgen_1_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_5_0 = io_core_dgen_1_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_6_0 = io_core_dgen_1_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_7_0 = io_core_dgen_1_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_8_0 = io_core_dgen_1_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fu_code_9_0 = io_core_dgen_1_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_0 = io_core_dgen_1_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_dis_col_sel_0 = io_core_dgen_1_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_1_bits_uop_br_mask_0 = io_core_dgen_1_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_tag_0 = io_core_dgen_1_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_1_bits_uop_br_type_0 = io_core_dgen_1_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfb_0 = io_core_dgen_1_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fence_0 = io_core_dgen_1_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_fencei_0 = io_core_dgen_1_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sfence_0 = io_core_dgen_1_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_amo_0 = io_core_dgen_1_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_eret_0 = io_core_dgen_1_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_sys_pc2epc_0 = io_core_dgen_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_rocc_0 = io_core_dgen_1_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_mov_0 = io_core_dgen_1_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ftq_idx_0 = io_core_dgen_1_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_edge_inst_0 = io_core_dgen_1_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_pc_lob_0 = io_core_dgen_1_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_taken_0 = io_core_dgen_1_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_imm_rename_0 = io_core_dgen_1_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_imm_sel_0 = io_core_dgen_1_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_pimm_0 = io_core_dgen_1_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_1_bits_uop_imm_packed_0 = io_core_dgen_1_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_op1_sel_0 = io_core_dgen_1_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_op2_sel_0 = io_core_dgen_1_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wen_0 = io_core_dgen_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_toint_0 = io_core_dgen_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_fma_0 = io_core_dgen_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_div_0 = io_core_dgen_1_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_ctrl_vec_0 = io_core_dgen_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_rob_idx_0 = io_core_dgen_1_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ldq_idx_0 = io_core_dgen_1_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_stq_idx_0 = io_core_dgen_1_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_rxq_idx_0 = io_core_dgen_1_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_pdst_0 = io_core_dgen_1_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs1_0 = io_core_dgen_1_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs2_0 = io_core_dgen_1_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_prs3_0 = io_core_dgen_1_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_ppred_0 = io_core_dgen_1_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs1_busy_0 = io_core_dgen_1_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs2_busy_0 = io_core_dgen_1_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_prs3_busy_0 = io_core_dgen_1_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ppred_busy_0 = io_core_dgen_1_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_1_bits_uop_stale_pdst_0 = io_core_dgen_1_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_exception_0 = io_core_dgen_1_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_uop_exc_cause_0 = io_core_dgen_1_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_mem_cmd_0 = io_core_dgen_1_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_mem_size_0 = io_core_dgen_1_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_mem_signed_0 = io_core_dgen_1_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_ldq_0 = io_core_dgen_1_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_uses_stq_0 = io_core_dgen_1_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_is_unique_0 = io_core_dgen_1_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_flush_on_commit_0 = io_core_dgen_1_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_csr_cmd_0 = io_core_dgen_1_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_ldst_is_rs1_0 = io_core_dgen_1_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_ldst_0 = io_core_dgen_1_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs1_0 = io_core_dgen_1_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs2_0 = io_core_dgen_1_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_1_bits_uop_lrs3_0 = io_core_dgen_1_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_dst_rtype_0 = io_core_dgen_1_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs1_rtype_0 = io_core_dgen_1_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_lrs2_rtype_0 = io_core_dgen_1_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_frs3_en_0 = io_core_dgen_1_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fcn_dw_0 = io_core_dgen_1_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_1_bits_uop_fcn_op_0 = io_core_dgen_1_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_fp_val_0 = io_core_dgen_1_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_fp_rm_0 = io_core_dgen_1_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_1_bits_uop_fp_typ_0 = io_core_dgen_1_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_pf_if_0 = io_core_dgen_1_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ae_if_0 = io_core_dgen_1_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_xcpt_ma_if_0 = io_core_dgen_1_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_debug_if_0 = io_core_dgen_1_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_1_bits_uop_bp_xcpt_if_0 = io_core_dgen_1_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_fsrc_0 = io_core_dgen_1_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_1_bits_uop_debug_tsrc_0 = io_core_dgen_1_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_1_bits_data_0 = io_core_dgen_1_bits_data; // @[lsu.scala:211:7] wire io_core_dgen_2_valid_0 = io_core_dgen_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_inst_0 = io_core_dgen_2_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dgen_2_bits_uop_debug_inst_0 = io_core_dgen_2_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rvc_0 = io_core_dgen_2_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dgen_2_bits_uop_debug_pc_0 = io_core_dgen_2_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_0_0 = io_core_dgen_2_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_1_0 = io_core_dgen_2_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_2_0 = io_core_dgen_2_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iq_type_3_0 = io_core_dgen_2_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_0_0 = io_core_dgen_2_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_1_0 = io_core_dgen_2_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_2_0 = io_core_dgen_2_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_3_0 = io_core_dgen_2_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_4_0 = io_core_dgen_2_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_5_0 = io_core_dgen_2_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_6_0 = io_core_dgen_2_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_7_0 = io_core_dgen_2_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_8_0 = io_core_dgen_2_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fu_code_9_0 = io_core_dgen_2_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_0 = io_core_dgen_2_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_agen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_issued_partial_dgen_0 = io_core_dgen_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_iw_p1_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_iw_p2_speculative_child_0 = io_core_dgen_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p1_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p2_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_iw_p3_bypass_hint_0 = io_core_dgen_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_dis_col_sel_0 = io_core_dgen_2_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dgen_2_bits_uop_br_mask_0 = io_core_dgen_2_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_tag_0 = io_core_dgen_2_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dgen_2_bits_uop_br_type_0 = io_core_dgen_2_bits_uop_br_type; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfb_0 = io_core_dgen_2_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fence_0 = io_core_dgen_2_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_fencei_0 = io_core_dgen_2_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sfence_0 = io_core_dgen_2_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_amo_0 = io_core_dgen_2_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_eret_0 = io_core_dgen_2_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_sys_pc2epc_0 = io_core_dgen_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_rocc_0 = io_core_dgen_2_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_mov_0 = io_core_dgen_2_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ftq_idx_0 = io_core_dgen_2_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_edge_inst_0 = io_core_dgen_2_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_pc_lob_0 = io_core_dgen_2_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_taken_0 = io_core_dgen_2_bits_uop_taken; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_imm_rename_0 = io_core_dgen_2_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_imm_sel_0 = io_core_dgen_2_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_pimm_0 = io_core_dgen_2_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dgen_2_bits_uop_imm_packed_0 = io_core_dgen_2_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_op1_sel_0 = io_core_dgen_2_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_op2_sel_0 = io_core_dgen_2_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ldst_0 = io_core_dgen_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wen_0 = io_core_dgen_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren1_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren2_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_ren3_0 = io_core_dgen_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap12_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_swap23_0 = io_core_dgen_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut_0 = io_core_dgen_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fromint_0 = io_core_dgen_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_toint_0 = io_core_dgen_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fastpipe_0 = io_core_dgen_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_fma_0 = io_core_dgen_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_div_0 = io_core_dgen_2_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_sqrt_0 = io_core_dgen_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_wflags_0 = io_core_dgen_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_ctrl_vec_0 = io_core_dgen_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_rob_idx_0 = io_core_dgen_2_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ldq_idx_0 = io_core_dgen_2_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_stq_idx_0 = io_core_dgen_2_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_rxq_idx_0 = io_core_dgen_2_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_pdst_0 = io_core_dgen_2_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs1_0 = io_core_dgen_2_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs2_0 = io_core_dgen_2_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_prs3_0 = io_core_dgen_2_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_ppred_0 = io_core_dgen_2_bits_uop_ppred; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs1_busy_0 = io_core_dgen_2_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs2_busy_0 = io_core_dgen_2_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_prs3_busy_0 = io_core_dgen_2_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ppred_busy_0 = io_core_dgen_2_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dgen_2_bits_uop_stale_pdst_0 = io_core_dgen_2_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_exception_0 = io_core_dgen_2_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_uop_exc_cause_0 = io_core_dgen_2_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_mem_cmd_0 = io_core_dgen_2_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_mem_size_0 = io_core_dgen_2_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_mem_signed_0 = io_core_dgen_2_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_ldq_0 = io_core_dgen_2_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_uses_stq_0 = io_core_dgen_2_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_is_unique_0 = io_core_dgen_2_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_flush_on_commit_0 = io_core_dgen_2_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_csr_cmd_0 = io_core_dgen_2_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_ldst_is_rs1_0 = io_core_dgen_2_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_ldst_0 = io_core_dgen_2_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs1_0 = io_core_dgen_2_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs2_0 = io_core_dgen_2_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dgen_2_bits_uop_lrs3_0 = io_core_dgen_2_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_dst_rtype_0 = io_core_dgen_2_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs1_rtype_0 = io_core_dgen_2_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_lrs2_rtype_0 = io_core_dgen_2_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_frs3_en_0 = io_core_dgen_2_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fcn_dw_0 = io_core_dgen_2_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dgen_2_bits_uop_fcn_op_0 = io_core_dgen_2_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_fp_val_0 = io_core_dgen_2_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_fp_rm_0 = io_core_dgen_2_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dgen_2_bits_uop_fp_typ_0 = io_core_dgen_2_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_pf_if_0 = io_core_dgen_2_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ae_if_0 = io_core_dgen_2_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_xcpt_ma_if_0 = io_core_dgen_2_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_debug_if_0 = io_core_dgen_2_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dgen_2_bits_uop_bp_xcpt_if_0 = io_core_dgen_2_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_fsrc_0 = io_core_dgen_2_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dgen_2_bits_uop_debug_tsrc_0 = io_core_dgen_2_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_core_dgen_2_bits_data_0 = io_core_dgen_2_bits_data; // @[lsu.scala:211:7] wire io_core_sfence_valid_0 = io_core_sfence_valid; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs1_0 = io_core_sfence_bits_rs1; // @[lsu.scala:211:7] wire io_core_sfence_bits_rs2_0 = io_core_sfence_bits_rs2; // @[lsu.scala:211:7] wire [38:0] io_core_sfence_bits_addr_0 = io_core_sfence_bits_addr; // @[lsu.scala:211:7] wire io_core_sfence_bits_asid_0 = io_core_sfence_bits_asid; // @[lsu.scala:211:7] wire io_core_sfence_bits_hv_0 = io_core_sfence_bits_hv; // @[lsu.scala:211:7] wire io_core_sfence_bits_hg_0 = io_core_sfence_bits_hg; // @[lsu.scala:211:7] wire io_core_dis_uops_0_valid_0 = io_core_dis_uops_0_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_inst_0 = io_core_dis_uops_0_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_0_bits_debug_inst_0 = io_core_dis_uops_0_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rvc_0 = io_core_dis_uops_0_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_0_bits_debug_pc_0 = io_core_dis_uops_0_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_0_0 = io_core_dis_uops_0_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_1_0 = io_core_dis_uops_0_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_2_0 = io_core_dis_uops_0_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iq_type_3_0 = io_core_dis_uops_0_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_0_0 = io_core_dis_uops_0_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_1_0 = io_core_dis_uops_0_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_2_0 = io_core_dis_uops_0_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_3_0 = io_core_dis_uops_0_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_4_0 = io_core_dis_uops_0_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_5_0 = io_core_dis_uops_0_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_6_0 = io_core_dis_uops_0_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_7_0 = io_core_dis_uops_0_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_8_0 = io_core_dis_uops_0_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fu_code_9_0 = io_core_dis_uops_0_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_0 = io_core_dis_uops_0_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_agen_0 = io_core_dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_iw_p1_speculative_child_0 = io_core_dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_iw_p2_speculative_child_0 = io_core_dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_dis_col_sel_0 = io_core_dis_uops_0_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_0_bits_br_mask_0 = io_core_dis_uops_0_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_tag_0 = io_core_dis_uops_0_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_0_bits_br_type_0 = io_core_dis_uops_0_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfb_0 = io_core_dis_uops_0_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fence_0 = io_core_dis_uops_0_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_fencei_0 = io_core_dis_uops_0_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sfence_0 = io_core_dis_uops_0_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_amo_0 = io_core_dis_uops_0_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_eret_0 = io_core_dis_uops_0_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_sys_pc2epc_0 = io_core_dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_rocc_0 = io_core_dis_uops_0_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_mov_0 = io_core_dis_uops_0_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ftq_idx_0 = io_core_dis_uops_0_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_edge_inst_0 = io_core_dis_uops_0_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_pc_lob_0 = io_core_dis_uops_0_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_taken_0 = io_core_dis_uops_0_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_imm_rename_0 = io_core_dis_uops_0_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_imm_sel_0 = io_core_dis_uops_0_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_pimm_0 = io_core_dis_uops_0_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_0_bits_imm_packed_0 = io_core_dis_uops_0_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_op1_sel_0 = io_core_dis_uops_0_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_op2_sel_0 = io_core_dis_uops_0_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ldst_0 = io_core_dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wen_0 = io_core_dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren1_0 = io_core_dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren2_0 = io_core_dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_ren3_0 = io_core_dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap12_0 = io_core_dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_swap23_0 = io_core_dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fromint_0 = io_core_dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_toint_0 = io_core_dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_fma_0 = io_core_dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_div_0 = io_core_dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_wflags_0 = io_core_dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_ctrl_vec_0 = io_core_dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_rob_idx_0 = io_core_dis_uops_0_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ldq_idx_0 = io_core_dis_uops_0_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_stq_idx_0 = io_core_dis_uops_0_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_rxq_idx_0 = io_core_dis_uops_0_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_pdst_0 = io_core_dis_uops_0_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs1_0 = io_core_dis_uops_0_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs2_0 = io_core_dis_uops_0_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_prs3_0 = io_core_dis_uops_0_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_ppred_0 = io_core_dis_uops_0_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs1_busy_0 = io_core_dis_uops_0_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs2_busy_0 = io_core_dis_uops_0_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_prs3_busy_0 = io_core_dis_uops_0_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ppred_busy_0 = io_core_dis_uops_0_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_0_bits_stale_pdst_0 = io_core_dis_uops_0_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_exception_0 = io_core_dis_uops_0_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_0_bits_exc_cause_0 = io_core_dis_uops_0_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_mem_cmd_0 = io_core_dis_uops_0_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_mem_size_0 = io_core_dis_uops_0_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_mem_signed_0 = io_core_dis_uops_0_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_ldq_0 = io_core_dis_uops_0_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_uses_stq_0 = io_core_dis_uops_0_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_is_unique_0 = io_core_dis_uops_0_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_flush_on_commit_0 = io_core_dis_uops_0_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_csr_cmd_0 = io_core_dis_uops_0_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_ldst_is_rs1_0 = io_core_dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_ldst_0 = io_core_dis_uops_0_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs1_0 = io_core_dis_uops_0_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs2_0 = io_core_dis_uops_0_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_0_bits_lrs3_0 = io_core_dis_uops_0_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_dst_rtype_0 = io_core_dis_uops_0_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs1_rtype_0 = io_core_dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_lrs2_rtype_0 = io_core_dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_frs3_en_0 = io_core_dis_uops_0_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fcn_dw_0 = io_core_dis_uops_0_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_0_bits_fcn_op_0 = io_core_dis_uops_0_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_fp_val_0 = io_core_dis_uops_0_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_fp_rm_0 = io_core_dis_uops_0_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_0_bits_fp_typ_0 = io_core_dis_uops_0_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_pf_if_0 = io_core_dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ae_if_0 = io_core_dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_xcpt_ma_if_0 = io_core_dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_debug_if_0 = io_core_dis_uops_0_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_0_bits_bp_xcpt_if_0 = io_core_dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_fsrc_0 = io_core_dis_uops_0_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_0_bits_debug_tsrc_0 = io_core_dis_uops_0_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_valid_0 = io_core_dis_uops_1_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_inst_0 = io_core_dis_uops_1_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_1_bits_debug_inst_0 = io_core_dis_uops_1_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rvc_0 = io_core_dis_uops_1_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_1_bits_debug_pc_0 = io_core_dis_uops_1_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_0_0 = io_core_dis_uops_1_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_1_0 = io_core_dis_uops_1_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_2_0 = io_core_dis_uops_1_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iq_type_3_0 = io_core_dis_uops_1_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_0_0 = io_core_dis_uops_1_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_1_0 = io_core_dis_uops_1_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_2_0 = io_core_dis_uops_1_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_3_0 = io_core_dis_uops_1_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_4_0 = io_core_dis_uops_1_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_5_0 = io_core_dis_uops_1_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_6_0 = io_core_dis_uops_1_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_7_0 = io_core_dis_uops_1_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_8_0 = io_core_dis_uops_1_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fu_code_9_0 = io_core_dis_uops_1_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_0 = io_core_dis_uops_1_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_agen_0 = io_core_dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_iw_p1_speculative_child_0 = io_core_dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_iw_p2_speculative_child_0 = io_core_dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_dis_col_sel_0 = io_core_dis_uops_1_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_1_bits_br_mask_0 = io_core_dis_uops_1_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_tag_0 = io_core_dis_uops_1_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_1_bits_br_type_0 = io_core_dis_uops_1_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfb_0 = io_core_dis_uops_1_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fence_0 = io_core_dis_uops_1_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_fencei_0 = io_core_dis_uops_1_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sfence_0 = io_core_dis_uops_1_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_amo_0 = io_core_dis_uops_1_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_eret_0 = io_core_dis_uops_1_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_sys_pc2epc_0 = io_core_dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_rocc_0 = io_core_dis_uops_1_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_mov_0 = io_core_dis_uops_1_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ftq_idx_0 = io_core_dis_uops_1_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_edge_inst_0 = io_core_dis_uops_1_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_pc_lob_0 = io_core_dis_uops_1_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_taken_0 = io_core_dis_uops_1_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_imm_rename_0 = io_core_dis_uops_1_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_imm_sel_0 = io_core_dis_uops_1_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_pimm_0 = io_core_dis_uops_1_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_1_bits_imm_packed_0 = io_core_dis_uops_1_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_op1_sel_0 = io_core_dis_uops_1_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_op2_sel_0 = io_core_dis_uops_1_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ldst_0 = io_core_dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wen_0 = io_core_dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren1_0 = io_core_dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren2_0 = io_core_dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_ren3_0 = io_core_dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap12_0 = io_core_dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_swap23_0 = io_core_dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fromint_0 = io_core_dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_toint_0 = io_core_dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_fma_0 = io_core_dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_div_0 = io_core_dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_wflags_0 = io_core_dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_ctrl_vec_0 = io_core_dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_rob_idx_0 = io_core_dis_uops_1_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ldq_idx_0 = io_core_dis_uops_1_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_stq_idx_0 = io_core_dis_uops_1_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_rxq_idx_0 = io_core_dis_uops_1_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_pdst_0 = io_core_dis_uops_1_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs1_0 = io_core_dis_uops_1_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs2_0 = io_core_dis_uops_1_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_prs3_0 = io_core_dis_uops_1_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_ppred_0 = io_core_dis_uops_1_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs1_busy_0 = io_core_dis_uops_1_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs2_busy_0 = io_core_dis_uops_1_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_prs3_busy_0 = io_core_dis_uops_1_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ppred_busy_0 = io_core_dis_uops_1_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_1_bits_stale_pdst_0 = io_core_dis_uops_1_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_exception_0 = io_core_dis_uops_1_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_1_bits_exc_cause_0 = io_core_dis_uops_1_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_mem_cmd_0 = io_core_dis_uops_1_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_mem_size_0 = io_core_dis_uops_1_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_mem_signed_0 = io_core_dis_uops_1_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_ldq_0 = io_core_dis_uops_1_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_uses_stq_0 = io_core_dis_uops_1_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_is_unique_0 = io_core_dis_uops_1_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_flush_on_commit_0 = io_core_dis_uops_1_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_csr_cmd_0 = io_core_dis_uops_1_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_ldst_is_rs1_0 = io_core_dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_ldst_0 = io_core_dis_uops_1_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs1_0 = io_core_dis_uops_1_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs2_0 = io_core_dis_uops_1_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_1_bits_lrs3_0 = io_core_dis_uops_1_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_dst_rtype_0 = io_core_dis_uops_1_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs1_rtype_0 = io_core_dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_lrs2_rtype_0 = io_core_dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_frs3_en_0 = io_core_dis_uops_1_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fcn_dw_0 = io_core_dis_uops_1_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_1_bits_fcn_op_0 = io_core_dis_uops_1_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_fp_val_0 = io_core_dis_uops_1_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_fp_rm_0 = io_core_dis_uops_1_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_1_bits_fp_typ_0 = io_core_dis_uops_1_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_pf_if_0 = io_core_dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ae_if_0 = io_core_dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_xcpt_ma_if_0 = io_core_dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_debug_if_0 = io_core_dis_uops_1_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_1_bits_bp_xcpt_if_0 = io_core_dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_fsrc_0 = io_core_dis_uops_1_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_1_bits_debug_tsrc_0 = io_core_dis_uops_1_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_valid_0 = io_core_dis_uops_2_valid; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_2_bits_inst_0 = io_core_dis_uops_2_bits_inst; // @[lsu.scala:211:7] wire [31:0] io_core_dis_uops_2_bits_debug_inst_0 = io_core_dis_uops_2_bits_debug_inst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_rvc_0 = io_core_dis_uops_2_bits_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_dis_uops_2_bits_debug_pc_0 = io_core_dis_uops_2_bits_debug_pc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_0_0 = io_core_dis_uops_2_bits_iq_type_0; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_1_0 = io_core_dis_uops_2_bits_iq_type_1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_2_0 = io_core_dis_uops_2_bits_iq_type_2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iq_type_3_0 = io_core_dis_uops_2_bits_iq_type_3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_0_0 = io_core_dis_uops_2_bits_fu_code_0; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_1_0 = io_core_dis_uops_2_bits_fu_code_1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_2_0 = io_core_dis_uops_2_bits_fu_code_2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_3_0 = io_core_dis_uops_2_bits_fu_code_3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_4_0 = io_core_dis_uops_2_bits_fu_code_4; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_5_0 = io_core_dis_uops_2_bits_fu_code_5; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_6_0 = io_core_dis_uops_2_bits_fu_code_6; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_7_0 = io_core_dis_uops_2_bits_fu_code_7; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_8_0 = io_core_dis_uops_2_bits_fu_code_8; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fu_code_9_0 = io_core_dis_uops_2_bits_fu_code_9; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_0 = io_core_dis_uops_2_bits_iw_issued; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_partial_agen_0 = io_core_dis_uops_2_bits_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_core_dis_uops_2_bits_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_iw_p1_speculative_child_0 = io_core_dis_uops_2_bits_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_iw_p2_speculative_child_0 = io_core_dis_uops_2_bits_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_core_dis_uops_2_bits_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_dis_col_sel_0 = io_core_dis_uops_2_bits_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_dis_uops_2_bits_br_mask_0 = io_core_dis_uops_2_bits_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_2_bits_br_tag_0 = io_core_dis_uops_2_bits_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_dis_uops_2_bits_br_type_0 = io_core_dis_uops_2_bits_br_type; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sfb_0 = io_core_dis_uops_2_bits_is_sfb; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_fence_0 = io_core_dis_uops_2_bits_is_fence; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_fencei_0 = io_core_dis_uops_2_bits_is_fencei; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sfence_0 = io_core_dis_uops_2_bits_is_sfence; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_amo_0 = io_core_dis_uops_2_bits_is_amo; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_eret_0 = io_core_dis_uops_2_bits_is_eret; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_sys_pc2epc_0 = io_core_dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_rocc_0 = io_core_dis_uops_2_bits_is_rocc; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_mov_0 = io_core_dis_uops_2_bits_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ftq_idx_0 = io_core_dis_uops_2_bits_ftq_idx; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_edge_inst_0 = io_core_dis_uops_2_bits_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_pc_lob_0 = io_core_dis_uops_2_bits_pc_lob; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_taken_0 = io_core_dis_uops_2_bits_taken; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_imm_rename_0 = io_core_dis_uops_2_bits_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_imm_sel_0 = io_core_dis_uops_2_bits_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_pimm_0 = io_core_dis_uops_2_bits_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_dis_uops_2_bits_imm_packed_0 = io_core_dis_uops_2_bits_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_op1_sel_0 = io_core_dis_uops_2_bits_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_op2_sel_0 = io_core_dis_uops_2_bits_op2_sel; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ldst_0 = io_core_dis_uops_2_bits_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_wen_0 = io_core_dis_uops_2_bits_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren1_0 = io_core_dis_uops_2_bits_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren2_0 = io_core_dis_uops_2_bits_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_ren3_0 = io_core_dis_uops_2_bits_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_swap12_0 = io_core_dis_uops_2_bits_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_swap23_0 = io_core_dis_uops_2_bits_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_core_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_core_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fromint_0 = io_core_dis_uops_2_bits_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_toint_0 = io_core_dis_uops_2_bits_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_core_dis_uops_2_bits_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_fma_0 = io_core_dis_uops_2_bits_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_div_0 = io_core_dis_uops_2_bits_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_core_dis_uops_2_bits_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_wflags_0 = io_core_dis_uops_2_bits_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_ctrl_vec_0 = io_core_dis_uops_2_bits_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_rob_idx_0 = io_core_dis_uops_2_bits_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ldq_idx_0 = io_core_dis_uops_2_bits_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_stq_idx_0 = io_core_dis_uops_2_bits_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_rxq_idx_0 = io_core_dis_uops_2_bits_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_pdst_0 = io_core_dis_uops_2_bits_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs1_0 = io_core_dis_uops_2_bits_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs2_0 = io_core_dis_uops_2_bits_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_prs3_0 = io_core_dis_uops_2_bits_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_ppred_0 = io_core_dis_uops_2_bits_ppred; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs1_busy_0 = io_core_dis_uops_2_bits_prs1_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs2_busy_0 = io_core_dis_uops_2_bits_prs2_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_prs3_busy_0 = io_core_dis_uops_2_bits_prs3_busy; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_ppred_busy_0 = io_core_dis_uops_2_bits_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_dis_uops_2_bits_stale_pdst_0 = io_core_dis_uops_2_bits_stale_pdst; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_exception_0 = io_core_dis_uops_2_bits_exception; // @[lsu.scala:211:7] wire [63:0] io_core_dis_uops_2_bits_exc_cause_0 = io_core_dis_uops_2_bits_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_mem_cmd_0 = io_core_dis_uops_2_bits_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_mem_size_0 = io_core_dis_uops_2_bits_mem_size; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_mem_signed_0 = io_core_dis_uops_2_bits_mem_signed; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_uses_ldq_0 = io_core_dis_uops_2_bits_uses_ldq; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_uses_stq_0 = io_core_dis_uops_2_bits_uses_stq; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_is_unique_0 = io_core_dis_uops_2_bits_is_unique; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_flush_on_commit_0 = io_core_dis_uops_2_bits_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_csr_cmd_0 = io_core_dis_uops_2_bits_csr_cmd; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_ldst_is_rs1_0 = io_core_dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_ldst_0 = io_core_dis_uops_2_bits_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs1_0 = io_core_dis_uops_2_bits_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs2_0 = io_core_dis_uops_2_bits_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_dis_uops_2_bits_lrs3_0 = io_core_dis_uops_2_bits_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_dst_rtype_0 = io_core_dis_uops_2_bits_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_lrs1_rtype_0 = io_core_dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_lrs2_rtype_0 = io_core_dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_frs3_en_0 = io_core_dis_uops_2_bits_frs3_en; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fcn_dw_0 = io_core_dis_uops_2_bits_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_dis_uops_2_bits_fcn_op_0 = io_core_dis_uops_2_bits_fcn_op; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_fp_val_0 = io_core_dis_uops_2_bits_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_fp_rm_0 = io_core_dis_uops_2_bits_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_dis_uops_2_bits_fp_typ_0 = io_core_dis_uops_2_bits_fp_typ; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_pf_if_0 = io_core_dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_ae_if_0 = io_core_dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_xcpt_ma_if_0 = io_core_dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_bp_debug_if_0 = io_core_dis_uops_2_bits_bp_debug_if; // @[lsu.scala:211:7] wire io_core_dis_uops_2_bits_bp_xcpt_if_0 = io_core_dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_debug_fsrc_0 = io_core_dis_uops_2_bits_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_dis_uops_2_bits_debug_tsrc_0 = io_core_dis_uops_2_bits_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_valids_0_0 = io_core_commit_valids_0; // @[lsu.scala:211:7] wire io_core_commit_valids_1_0 = io_core_commit_valids_1; // @[lsu.scala:211:7] wire io_core_commit_valids_2_0 = io_core_commit_valids_2; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_0_0 = io_core_commit_arch_valids_0; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_1_0 = io_core_commit_arch_valids_1; // @[lsu.scala:211:7] wire io_core_commit_arch_valids_2_0 = io_core_commit_arch_valids_2; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_inst_0 = io_core_commit_uops_0_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_0_debug_inst_0 = io_core_commit_uops_0_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rvc_0 = io_core_commit_uops_0_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_0_debug_pc_0 = io_core_commit_uops_0_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_0_0 = io_core_commit_uops_0_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_1_0 = io_core_commit_uops_0_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_2_0 = io_core_commit_uops_0_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iq_type_3_0 = io_core_commit_uops_0_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_0_0 = io_core_commit_uops_0_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_1_0 = io_core_commit_uops_0_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_2_0 = io_core_commit_uops_0_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_3_0 = io_core_commit_uops_0_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_4_0 = io_core_commit_uops_0_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_5_0 = io_core_commit_uops_0_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_6_0 = io_core_commit_uops_0_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_7_0 = io_core_commit_uops_0_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_8_0 = io_core_commit_uops_0_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fu_code_9_0 = io_core_commit_uops_0_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_0 = io_core_commit_uops_0_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_agen_0 = io_core_commit_uops_0_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_issued_partial_dgen_0 = io_core_commit_uops_0_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_iw_p1_speculative_child_0 = io_core_commit_uops_0_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_iw_p2_speculative_child_0 = io_core_commit_uops_0_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p1_bypass_hint_0 = io_core_commit_uops_0_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p2_bypass_hint_0 = io_core_commit_uops_0_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_iw_p3_bypass_hint_0 = io_core_commit_uops_0_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_dis_col_sel_0 = io_core_commit_uops_0_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_0_br_mask_0 = io_core_commit_uops_0_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_tag_0 = io_core_commit_uops_0_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_0_br_type_0 = io_core_commit_uops_0_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfb_0 = io_core_commit_uops_0_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fence_0 = io_core_commit_uops_0_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_fencei_0 = io_core_commit_uops_0_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sfence_0 = io_core_commit_uops_0_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_amo_0 = io_core_commit_uops_0_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_eret_0 = io_core_commit_uops_0_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_sys_pc2epc_0 = io_core_commit_uops_0_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_rocc_0 = io_core_commit_uops_0_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_mov_0 = io_core_commit_uops_0_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ftq_idx_0 = io_core_commit_uops_0_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_0_edge_inst_0 = io_core_commit_uops_0_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_pc_lob_0 = io_core_commit_uops_0_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_0_taken_0 = io_core_commit_uops_0_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_0_imm_rename_0 = io_core_commit_uops_0_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_imm_sel_0 = io_core_commit_uops_0_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_pimm_0 = io_core_commit_uops_0_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_0_imm_packed_0 = io_core_commit_uops_0_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_op1_sel_0 = io_core_commit_uops_0_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_op2_sel_0 = io_core_commit_uops_0_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ldst_0 = io_core_commit_uops_0_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wen_0 = io_core_commit_uops_0_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren1_0 = io_core_commit_uops_0_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren2_0 = io_core_commit_uops_0_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_ren3_0 = io_core_commit_uops_0_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap12_0 = io_core_commit_uops_0_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_swap23_0 = io_core_commit_uops_0_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagIn_0 = io_core_commit_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_ctrl_typeTagOut_0 = io_core_commit_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fromint_0 = io_core_commit_uops_0_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_toint_0 = io_core_commit_uops_0_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fastpipe_0 = io_core_commit_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_fma_0 = io_core_commit_uops_0_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_div_0 = io_core_commit_uops_0_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_sqrt_0 = io_core_commit_uops_0_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_wflags_0 = io_core_commit_uops_0_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_ctrl_vec_0 = io_core_commit_uops_0_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_rob_idx_0 = io_core_commit_uops_0_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ldq_idx_0 = io_core_commit_uops_0_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_stq_idx_0 = io_core_commit_uops_0_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_rxq_idx_0 = io_core_commit_uops_0_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_pdst_0 = io_core_commit_uops_0_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs1_0 = io_core_commit_uops_0_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs2_0 = io_core_commit_uops_0_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_prs3_0 = io_core_commit_uops_0_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_ppred_0 = io_core_commit_uops_0_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs1_busy_0 = io_core_commit_uops_0_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs2_busy_0 = io_core_commit_uops_0_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_prs3_busy_0 = io_core_commit_uops_0_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ppred_busy_0 = io_core_commit_uops_0_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_0_stale_pdst_0 = io_core_commit_uops_0_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_0_exception_0 = io_core_commit_uops_0_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_0_exc_cause_0 = io_core_commit_uops_0_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_mem_cmd_0 = io_core_commit_uops_0_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_mem_size_0 = io_core_commit_uops_0_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_0_mem_signed_0 = io_core_commit_uops_0_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_ldq_0 = io_core_commit_uops_0_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_uses_stq_0 = io_core_commit_uops_0_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_0_is_unique_0 = io_core_commit_uops_0_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_0_flush_on_commit_0 = io_core_commit_uops_0_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_csr_cmd_0 = io_core_commit_uops_0_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_0_ldst_is_rs1_0 = io_core_commit_uops_0_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_ldst_0 = io_core_commit_uops_0_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs1_0 = io_core_commit_uops_0_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs2_0 = io_core_commit_uops_0_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_0_lrs3_0 = io_core_commit_uops_0_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_dst_rtype_0 = io_core_commit_uops_0_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs1_rtype_0 = io_core_commit_uops_0_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_lrs2_rtype_0 = io_core_commit_uops_0_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_0_frs3_en_0 = io_core_commit_uops_0_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fcn_dw_0 = io_core_commit_uops_0_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_0_fcn_op_0 = io_core_commit_uops_0_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_0_fp_val_0 = io_core_commit_uops_0_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_fp_rm_0 = io_core_commit_uops_0_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_0_fp_typ_0 = io_core_commit_uops_0_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_pf_if_0 = io_core_commit_uops_0_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ae_if_0 = io_core_commit_uops_0_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_xcpt_ma_if_0 = io_core_commit_uops_0_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_debug_if_0 = io_core_commit_uops_0_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_0_bp_xcpt_if_0 = io_core_commit_uops_0_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_fsrc_0 = io_core_commit_uops_0_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_0_debug_tsrc_0 = io_core_commit_uops_0_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_inst_0 = io_core_commit_uops_1_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_1_debug_inst_0 = io_core_commit_uops_1_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rvc_0 = io_core_commit_uops_1_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_1_debug_pc_0 = io_core_commit_uops_1_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_0_0 = io_core_commit_uops_1_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_1_0 = io_core_commit_uops_1_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_2_0 = io_core_commit_uops_1_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iq_type_3_0 = io_core_commit_uops_1_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_0_0 = io_core_commit_uops_1_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_1_0 = io_core_commit_uops_1_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_2_0 = io_core_commit_uops_1_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_3_0 = io_core_commit_uops_1_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_4_0 = io_core_commit_uops_1_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_5_0 = io_core_commit_uops_1_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_6_0 = io_core_commit_uops_1_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_7_0 = io_core_commit_uops_1_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_8_0 = io_core_commit_uops_1_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fu_code_9_0 = io_core_commit_uops_1_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_0 = io_core_commit_uops_1_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_agen_0 = io_core_commit_uops_1_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_issued_partial_dgen_0 = io_core_commit_uops_1_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_iw_p1_speculative_child_0 = io_core_commit_uops_1_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_iw_p2_speculative_child_0 = io_core_commit_uops_1_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p1_bypass_hint_0 = io_core_commit_uops_1_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p2_bypass_hint_0 = io_core_commit_uops_1_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_iw_p3_bypass_hint_0 = io_core_commit_uops_1_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_dis_col_sel_0 = io_core_commit_uops_1_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_1_br_mask_0 = io_core_commit_uops_1_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_tag_0 = io_core_commit_uops_1_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_1_br_type_0 = io_core_commit_uops_1_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfb_0 = io_core_commit_uops_1_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fence_0 = io_core_commit_uops_1_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_fencei_0 = io_core_commit_uops_1_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sfence_0 = io_core_commit_uops_1_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_amo_0 = io_core_commit_uops_1_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_eret_0 = io_core_commit_uops_1_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_sys_pc2epc_0 = io_core_commit_uops_1_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_rocc_0 = io_core_commit_uops_1_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_mov_0 = io_core_commit_uops_1_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ftq_idx_0 = io_core_commit_uops_1_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_1_edge_inst_0 = io_core_commit_uops_1_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_pc_lob_0 = io_core_commit_uops_1_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_1_taken_0 = io_core_commit_uops_1_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_1_imm_rename_0 = io_core_commit_uops_1_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_imm_sel_0 = io_core_commit_uops_1_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_pimm_0 = io_core_commit_uops_1_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_1_imm_packed_0 = io_core_commit_uops_1_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_op1_sel_0 = io_core_commit_uops_1_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_op2_sel_0 = io_core_commit_uops_1_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ldst_0 = io_core_commit_uops_1_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wen_0 = io_core_commit_uops_1_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren1_0 = io_core_commit_uops_1_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren2_0 = io_core_commit_uops_1_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_ren3_0 = io_core_commit_uops_1_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap12_0 = io_core_commit_uops_1_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_swap23_0 = io_core_commit_uops_1_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagIn_0 = io_core_commit_uops_1_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_ctrl_typeTagOut_0 = io_core_commit_uops_1_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fromint_0 = io_core_commit_uops_1_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_toint_0 = io_core_commit_uops_1_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fastpipe_0 = io_core_commit_uops_1_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_fma_0 = io_core_commit_uops_1_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_div_0 = io_core_commit_uops_1_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_sqrt_0 = io_core_commit_uops_1_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_wflags_0 = io_core_commit_uops_1_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_ctrl_vec_0 = io_core_commit_uops_1_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_rob_idx_0 = io_core_commit_uops_1_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ldq_idx_0 = io_core_commit_uops_1_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_stq_idx_0 = io_core_commit_uops_1_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_rxq_idx_0 = io_core_commit_uops_1_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_pdst_0 = io_core_commit_uops_1_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs1_0 = io_core_commit_uops_1_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs2_0 = io_core_commit_uops_1_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_prs3_0 = io_core_commit_uops_1_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_ppred_0 = io_core_commit_uops_1_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs1_busy_0 = io_core_commit_uops_1_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs2_busy_0 = io_core_commit_uops_1_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_prs3_busy_0 = io_core_commit_uops_1_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ppred_busy_0 = io_core_commit_uops_1_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_1_stale_pdst_0 = io_core_commit_uops_1_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_1_exception_0 = io_core_commit_uops_1_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_1_exc_cause_0 = io_core_commit_uops_1_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_mem_cmd_0 = io_core_commit_uops_1_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_mem_size_0 = io_core_commit_uops_1_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_1_mem_signed_0 = io_core_commit_uops_1_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_ldq_0 = io_core_commit_uops_1_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_uses_stq_0 = io_core_commit_uops_1_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_1_is_unique_0 = io_core_commit_uops_1_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_1_flush_on_commit_0 = io_core_commit_uops_1_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_csr_cmd_0 = io_core_commit_uops_1_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_1_ldst_is_rs1_0 = io_core_commit_uops_1_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_ldst_0 = io_core_commit_uops_1_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs1_0 = io_core_commit_uops_1_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs2_0 = io_core_commit_uops_1_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_1_lrs3_0 = io_core_commit_uops_1_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_dst_rtype_0 = io_core_commit_uops_1_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs1_rtype_0 = io_core_commit_uops_1_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_lrs2_rtype_0 = io_core_commit_uops_1_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_1_frs3_en_0 = io_core_commit_uops_1_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fcn_dw_0 = io_core_commit_uops_1_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_1_fcn_op_0 = io_core_commit_uops_1_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_1_fp_val_0 = io_core_commit_uops_1_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_fp_rm_0 = io_core_commit_uops_1_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_1_fp_typ_0 = io_core_commit_uops_1_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_pf_if_0 = io_core_commit_uops_1_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ae_if_0 = io_core_commit_uops_1_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_xcpt_ma_if_0 = io_core_commit_uops_1_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_debug_if_0 = io_core_commit_uops_1_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_1_bp_xcpt_if_0 = io_core_commit_uops_1_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_fsrc_0 = io_core_commit_uops_1_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_1_debug_tsrc_0 = io_core_commit_uops_1_debug_tsrc; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_2_inst_0 = io_core_commit_uops_2_inst; // @[lsu.scala:211:7] wire [31:0] io_core_commit_uops_2_debug_inst_0 = io_core_commit_uops_2_debug_inst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_rvc_0 = io_core_commit_uops_2_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_commit_uops_2_debug_pc_0 = io_core_commit_uops_2_debug_pc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_0_0 = io_core_commit_uops_2_iq_type_0; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_1_0 = io_core_commit_uops_2_iq_type_1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_2_0 = io_core_commit_uops_2_iq_type_2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iq_type_3_0 = io_core_commit_uops_2_iq_type_3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_0_0 = io_core_commit_uops_2_fu_code_0; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_1_0 = io_core_commit_uops_2_fu_code_1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_2_0 = io_core_commit_uops_2_fu_code_2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_3_0 = io_core_commit_uops_2_fu_code_3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_4_0 = io_core_commit_uops_2_fu_code_4; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_5_0 = io_core_commit_uops_2_fu_code_5; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_6_0 = io_core_commit_uops_2_fu_code_6; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_7_0 = io_core_commit_uops_2_fu_code_7; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_8_0 = io_core_commit_uops_2_fu_code_8; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fu_code_9_0 = io_core_commit_uops_2_fu_code_9; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_0 = io_core_commit_uops_2_iw_issued; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_partial_agen_0 = io_core_commit_uops_2_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_issued_partial_dgen_0 = io_core_commit_uops_2_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_iw_p1_speculative_child_0 = io_core_commit_uops_2_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_iw_p2_speculative_child_0 = io_core_commit_uops_2_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p1_bypass_hint_0 = io_core_commit_uops_2_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p2_bypass_hint_0 = io_core_commit_uops_2_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_iw_p3_bypass_hint_0 = io_core_commit_uops_2_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_dis_col_sel_0 = io_core_commit_uops_2_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_commit_uops_2_br_mask_0 = io_core_commit_uops_2_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_2_br_tag_0 = io_core_commit_uops_2_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_commit_uops_2_br_type_0 = io_core_commit_uops_2_br_type; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sfb_0 = io_core_commit_uops_2_is_sfb; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_fence_0 = io_core_commit_uops_2_is_fence; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_fencei_0 = io_core_commit_uops_2_is_fencei; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sfence_0 = io_core_commit_uops_2_is_sfence; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_amo_0 = io_core_commit_uops_2_is_amo; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_eret_0 = io_core_commit_uops_2_is_eret; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_sys_pc2epc_0 = io_core_commit_uops_2_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_rocc_0 = io_core_commit_uops_2_is_rocc; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_mov_0 = io_core_commit_uops_2_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ftq_idx_0 = io_core_commit_uops_2_ftq_idx; // @[lsu.scala:211:7] wire io_core_commit_uops_2_edge_inst_0 = io_core_commit_uops_2_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_pc_lob_0 = io_core_commit_uops_2_pc_lob; // @[lsu.scala:211:7] wire io_core_commit_uops_2_taken_0 = io_core_commit_uops_2_taken; // @[lsu.scala:211:7] wire io_core_commit_uops_2_imm_rename_0 = io_core_commit_uops_2_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_imm_sel_0 = io_core_commit_uops_2_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_pimm_0 = io_core_commit_uops_2_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_commit_uops_2_imm_packed_0 = io_core_commit_uops_2_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_op1_sel_0 = io_core_commit_uops_2_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_op2_sel_0 = io_core_commit_uops_2_op2_sel; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ldst_0 = io_core_commit_uops_2_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_wen_0 = io_core_commit_uops_2_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren1_0 = io_core_commit_uops_2_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren2_0 = io_core_commit_uops_2_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_ren3_0 = io_core_commit_uops_2_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_swap12_0 = io_core_commit_uops_2_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_swap23_0 = io_core_commit_uops_2_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_ctrl_typeTagIn_0 = io_core_commit_uops_2_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_ctrl_typeTagOut_0 = io_core_commit_uops_2_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fromint_0 = io_core_commit_uops_2_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_toint_0 = io_core_commit_uops_2_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fastpipe_0 = io_core_commit_uops_2_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_fma_0 = io_core_commit_uops_2_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_div_0 = io_core_commit_uops_2_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_sqrt_0 = io_core_commit_uops_2_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_wflags_0 = io_core_commit_uops_2_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_ctrl_vec_0 = io_core_commit_uops_2_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_rob_idx_0 = io_core_commit_uops_2_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ldq_idx_0 = io_core_commit_uops_2_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_stq_idx_0 = io_core_commit_uops_2_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_rxq_idx_0 = io_core_commit_uops_2_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_pdst_0 = io_core_commit_uops_2_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs1_0 = io_core_commit_uops_2_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs2_0 = io_core_commit_uops_2_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_prs3_0 = io_core_commit_uops_2_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_ppred_0 = io_core_commit_uops_2_ppred; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs1_busy_0 = io_core_commit_uops_2_prs1_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs2_busy_0 = io_core_commit_uops_2_prs2_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_prs3_busy_0 = io_core_commit_uops_2_prs3_busy; // @[lsu.scala:211:7] wire io_core_commit_uops_2_ppred_busy_0 = io_core_commit_uops_2_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_commit_uops_2_stale_pdst_0 = io_core_commit_uops_2_stale_pdst; // @[lsu.scala:211:7] wire io_core_commit_uops_2_exception_0 = io_core_commit_uops_2_exception; // @[lsu.scala:211:7] wire [63:0] io_core_commit_uops_2_exc_cause_0 = io_core_commit_uops_2_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_mem_cmd_0 = io_core_commit_uops_2_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_mem_size_0 = io_core_commit_uops_2_mem_size; // @[lsu.scala:211:7] wire io_core_commit_uops_2_mem_signed_0 = io_core_commit_uops_2_mem_signed; // @[lsu.scala:211:7] wire io_core_commit_uops_2_uses_ldq_0 = io_core_commit_uops_2_uses_ldq; // @[lsu.scala:211:7] wire io_core_commit_uops_2_uses_stq_0 = io_core_commit_uops_2_uses_stq; // @[lsu.scala:211:7] wire io_core_commit_uops_2_is_unique_0 = io_core_commit_uops_2_is_unique; // @[lsu.scala:211:7] wire io_core_commit_uops_2_flush_on_commit_0 = io_core_commit_uops_2_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_csr_cmd_0 = io_core_commit_uops_2_csr_cmd; // @[lsu.scala:211:7] wire io_core_commit_uops_2_ldst_is_rs1_0 = io_core_commit_uops_2_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_ldst_0 = io_core_commit_uops_2_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs1_0 = io_core_commit_uops_2_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs2_0 = io_core_commit_uops_2_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_commit_uops_2_lrs3_0 = io_core_commit_uops_2_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_dst_rtype_0 = io_core_commit_uops_2_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_lrs1_rtype_0 = io_core_commit_uops_2_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_lrs2_rtype_0 = io_core_commit_uops_2_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_commit_uops_2_frs3_en_0 = io_core_commit_uops_2_frs3_en; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fcn_dw_0 = io_core_commit_uops_2_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_commit_uops_2_fcn_op_0 = io_core_commit_uops_2_fcn_op; // @[lsu.scala:211:7] wire io_core_commit_uops_2_fp_val_0 = io_core_commit_uops_2_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_fp_rm_0 = io_core_commit_uops_2_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_commit_uops_2_fp_typ_0 = io_core_commit_uops_2_fp_typ; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_pf_if_0 = io_core_commit_uops_2_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_ae_if_0 = io_core_commit_uops_2_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_xcpt_ma_if_0 = io_core_commit_uops_2_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_bp_debug_if_0 = io_core_commit_uops_2_bp_debug_if; // @[lsu.scala:211:7] wire io_core_commit_uops_2_bp_xcpt_if_0 = io_core_commit_uops_2_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_debug_fsrc_0 = io_core_commit_uops_2_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_commit_uops_2_debug_tsrc_0 = io_core_commit_uops_2_debug_tsrc; // @[lsu.scala:211:7] wire io_core_commit_fflags_valid_0 = io_core_commit_fflags_valid; // @[lsu.scala:211:7] wire [4:0] io_core_commit_fflags_bits_0 = io_core_commit_fflags_bits; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_0_0 = io_core_commit_debug_wdata_0; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_1_0 = io_core_commit_debug_wdata_1; // @[lsu.scala:211:7] wire [63:0] io_core_commit_debug_wdata_2_0 = io_core_commit_debug_wdata_2; // @[lsu.scala:211:7] wire io_core_commit_load_at_rob_head_0 = io_core_commit_load_at_rob_head; // @[lsu.scala:211:7] wire io_core_fence_dmem_0 = io_core_fence_dmem; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_core_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_core_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_core_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_core_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_core_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_core_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_core_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_core_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_core_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc; // @[lsu.scala:211:7] wire io_core_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict; // @[lsu.scala:211:7] wire io_core_brupdate_b2_taken_0 = io_core_brupdate_b2_taken; // @[lsu.scala:211:7] wire [2:0] io_core_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type; // @[lsu.scala:211:7] wire [1:0] io_core_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel; // @[lsu.scala:211:7] wire [39:0] io_core_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target; // @[lsu.scala:211:7] wire [20:0] io_core_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset; // @[lsu.scala:211:7] wire [6:0] io_core_rob_pnr_idx_0 = io_core_rob_pnr_idx; // @[lsu.scala:211:7] wire [6:0] io_core_rob_head_idx_0 = io_core_rob_head_idx; // @[lsu.scala:211:7] wire io_core_exception_0 = io_core_exception; // @[lsu.scala:211:7] wire [63:0] io_core_tsc_reg_0 = io_core_tsc_reg; // @[lsu.scala:211:7] wire io_core_status_debug_0 = io_core_status_debug; // @[lsu.scala:211:7] wire io_core_status_cease_0 = io_core_status_cease; // @[lsu.scala:211:7] wire io_core_status_wfi_0 = io_core_status_wfi; // @[lsu.scala:211:7] wire [1:0] io_core_status_dprv_0 = io_core_status_dprv; // @[lsu.scala:211:7] wire io_core_status_dv_0 = io_core_status_dv; // @[lsu.scala:211:7] wire [1:0] io_core_status_prv_0 = io_core_status_prv; // @[lsu.scala:211:7] wire io_core_status_v_0 = io_core_status_v; // @[lsu.scala:211:7] wire io_core_status_sd_0 = io_core_status_sd; // @[lsu.scala:211:7] wire io_core_status_mpv_0 = io_core_status_mpv; // @[lsu.scala:211:7] wire io_core_status_gva_0 = io_core_status_gva; // @[lsu.scala:211:7] wire io_core_status_tsr_0 = io_core_status_tsr; // @[lsu.scala:211:7] wire io_core_status_tw_0 = io_core_status_tw; // @[lsu.scala:211:7] wire io_core_status_tvm_0 = io_core_status_tvm; // @[lsu.scala:211:7] wire io_core_status_mxr_0 = io_core_status_mxr; // @[lsu.scala:211:7] wire io_core_status_sum_0 = io_core_status_sum; // @[lsu.scala:211:7] wire io_core_status_mprv_0 = io_core_status_mprv; // @[lsu.scala:211:7] wire [1:0] io_core_status_fs_0 = io_core_status_fs; // @[lsu.scala:211:7] wire [1:0] io_core_status_mpp_0 = io_core_status_mpp; // @[lsu.scala:211:7] wire io_core_status_spp_0 = io_core_status_spp; // @[lsu.scala:211:7] wire io_core_status_mpie_0 = io_core_status_mpie; // @[lsu.scala:211:7] wire io_core_status_spie_0 = io_core_status_spie; // @[lsu.scala:211:7] wire io_core_status_mie_0 = io_core_status_mie; // @[lsu.scala:211:7] wire io_core_status_sie_0 = io_core_status_sie; // @[lsu.scala:211:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[lsu.scala:211:7] wire io_dmem_resp_0_valid_0 = io_dmem_resp_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_inst_0 = io_dmem_resp_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_resp_0_bits_uop_debug_inst_0 = io_dmem_resp_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rvc_0 = io_dmem_resp_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_resp_0_bits_uop_debug_pc_0 = io_dmem_resp_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_0_0 = io_dmem_resp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_1_0 = io_dmem_resp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_2_0 = io_dmem_resp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iq_type_3_0 = io_dmem_resp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_0_0 = io_dmem_resp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_1_0 = io_dmem_resp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_2_0 = io_dmem_resp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_3_0 = io_dmem_resp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_4_0 = io_dmem_resp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_5_0 = io_dmem_resp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_6_0 = io_dmem_resp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_7_0 = io_dmem_resp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_8_0 = io_dmem_resp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fu_code_9_0 = io_dmem_resp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_0 = io_dmem_resp_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_resp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_resp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_resp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_dis_col_sel_0 = io_dmem_resp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_resp_0_bits_uop_br_mask_0 = io_dmem_resp_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_tag_0 = io_dmem_resp_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_resp_0_bits_uop_br_type_0 = io_dmem_resp_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfb_0 = io_dmem_resp_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fence_0 = io_dmem_resp_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_fencei_0 = io_dmem_resp_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sfence_0 = io_dmem_resp_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_amo_0 = io_dmem_resp_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_eret_0 = io_dmem_resp_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_sys_pc2epc_0 = io_dmem_resp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_rocc_0 = io_dmem_resp_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_mov_0 = io_dmem_resp_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ftq_idx_0 = io_dmem_resp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_edge_inst_0 = io_dmem_resp_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_pc_lob_0 = io_dmem_resp_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_taken_0 = io_dmem_resp_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_imm_rename_0 = io_dmem_resp_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_imm_sel_0 = io_dmem_resp_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_pimm_0 = io_dmem_resp_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_resp_0_bits_uop_imm_packed_0 = io_dmem_resp_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_op1_sel_0 = io_dmem_resp_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_op2_sel_0 = io_dmem_resp_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wen_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_resp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_resp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_toint_0 = io_dmem_resp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_fma_0 = io_dmem_resp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_div_0 = io_dmem_resp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_resp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_resp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_ctrl_vec_0 = io_dmem_resp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_rob_idx_0 = io_dmem_resp_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ldq_idx_0 = io_dmem_resp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_stq_idx_0 = io_dmem_resp_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_rxq_idx_0 = io_dmem_resp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_pdst_0 = io_dmem_resp_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs1_0 = io_dmem_resp_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs2_0 = io_dmem_resp_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_prs3_0 = io_dmem_resp_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_ppred_0 = io_dmem_resp_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs1_busy_0 = io_dmem_resp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs2_busy_0 = io_dmem_resp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_prs3_busy_0 = io_dmem_resp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ppred_busy_0 = io_dmem_resp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_resp_0_bits_uop_stale_pdst_0 = io_dmem_resp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_exception_0 = io_dmem_resp_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_uop_exc_cause_0 = io_dmem_resp_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_mem_cmd_0 = io_dmem_resp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_mem_size_0 = io_dmem_resp_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_mem_signed_0 = io_dmem_resp_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_ldq_0 = io_dmem_resp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_uses_stq_0 = io_dmem_resp_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_is_unique_0 = io_dmem_resp_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_flush_on_commit_0 = io_dmem_resp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_csr_cmd_0 = io_dmem_resp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_ldst_is_rs1_0 = io_dmem_resp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_ldst_0 = io_dmem_resp_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs1_0 = io_dmem_resp_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs2_0 = io_dmem_resp_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_resp_0_bits_uop_lrs3_0 = io_dmem_resp_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_dst_rtype_0 = io_dmem_resp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs1_rtype_0 = io_dmem_resp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_lrs2_rtype_0 = io_dmem_resp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_frs3_en_0 = io_dmem_resp_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fcn_dw_0 = io_dmem_resp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_resp_0_bits_uop_fcn_op_0 = io_dmem_resp_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_fp_val_0 = io_dmem_resp_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_fp_rm_0 = io_dmem_resp_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_resp_0_bits_uop_fp_typ_0 = io_dmem_resp_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_pf_if_0 = io_dmem_resp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ae_if_0 = io_dmem_resp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_xcpt_ma_if_0 = io_dmem_resp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_debug_if_0 = io_dmem_resp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_uop_bp_xcpt_if_0 = io_dmem_resp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_fsrc_0 = io_dmem_resp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_resp_0_bits_uop_debug_tsrc_0 = io_dmem_resp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_resp_0_bits_data_0 = io_dmem_resp_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_resp_0_bits_is_hella_0 = io_dmem_resp_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_valid_0 = io_dmem_store_ack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_inst_0 = io_dmem_store_ack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_store_ack_0_bits_uop_debug_inst_0 = io_dmem_store_ack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rvc_0 = io_dmem_store_ack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_uop_debug_pc_0 = io_dmem_store_ack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_0_0 = io_dmem_store_ack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_1_0 = io_dmem_store_ack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_2_0 = io_dmem_store_ack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iq_type_3_0 = io_dmem_store_ack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_0_0 = io_dmem_store_ack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_1_0 = io_dmem_store_ack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_2_0 = io_dmem_store_ack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_3_0 = io_dmem_store_ack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_4_0 = io_dmem_store_ack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_5_0 = io_dmem_store_ack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_6_0 = io_dmem_store_ack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_7_0 = io_dmem_store_ack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_8_0 = io_dmem_store_ack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fu_code_9_0 = io_dmem_store_ack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_0 = io_dmem_store_ack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_store_ack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_store_ack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_store_ack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_dis_col_sel_0 = io_dmem_store_ack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_store_ack_0_bits_uop_br_mask_0 = io_dmem_store_ack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_tag_0 = io_dmem_store_ack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_store_ack_0_bits_uop_br_type_0 = io_dmem_store_ack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfb_0 = io_dmem_store_ack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fence_0 = io_dmem_store_ack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_fencei_0 = io_dmem_store_ack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sfence_0 = io_dmem_store_ack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_amo_0 = io_dmem_store_ack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_eret_0 = io_dmem_store_ack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_store_ack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_rocc_0 = io_dmem_store_ack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_mov_0 = io_dmem_store_ack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ftq_idx_0 = io_dmem_store_ack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_edge_inst_0 = io_dmem_store_ack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_pc_lob_0 = io_dmem_store_ack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_taken_0 = io_dmem_store_ack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_imm_rename_0 = io_dmem_store_ack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_imm_sel_0 = io_dmem_store_ack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_pimm_0 = io_dmem_store_ack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_store_ack_0_bits_uop_imm_packed_0 = io_dmem_store_ack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_op1_sel_0 = io_dmem_store_ack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_op2_sel_0 = io_dmem_store_ack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_div_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_store_ack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_rob_idx_0 = io_dmem_store_ack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ldq_idx_0 = io_dmem_store_ack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_stq_idx_0 = io_dmem_store_ack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_rxq_idx_0 = io_dmem_store_ack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_pdst_0 = io_dmem_store_ack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs1_0 = io_dmem_store_ack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs2_0 = io_dmem_store_ack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_prs3_0 = io_dmem_store_ack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_ppred_0 = io_dmem_store_ack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs1_busy_0 = io_dmem_store_ack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs2_busy_0 = io_dmem_store_ack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_prs3_busy_0 = io_dmem_store_ack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ppred_busy_0 = io_dmem_store_ack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_store_ack_0_bits_uop_stale_pdst_0 = io_dmem_store_ack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_exception_0 = io_dmem_store_ack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_uop_exc_cause_0 = io_dmem_store_ack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_mem_cmd_0 = io_dmem_store_ack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_mem_size_0 = io_dmem_store_ack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_mem_signed_0 = io_dmem_store_ack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_ldq_0 = io_dmem_store_ack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_uses_stq_0 = io_dmem_store_ack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_is_unique_0 = io_dmem_store_ack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_flush_on_commit_0 = io_dmem_store_ack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_csr_cmd_0 = io_dmem_store_ack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_ldst_is_rs1_0 = io_dmem_store_ack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_ldst_0 = io_dmem_store_ack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs1_0 = io_dmem_store_ack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs2_0 = io_dmem_store_ack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_store_ack_0_bits_uop_lrs3_0 = io_dmem_store_ack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_dst_rtype_0 = io_dmem_store_ack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs1_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_lrs2_rtype_0 = io_dmem_store_ack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_frs3_en_0 = io_dmem_store_ack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fcn_dw_0 = io_dmem_store_ack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_store_ack_0_bits_uop_fcn_op_0 = io_dmem_store_ack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_fp_val_0 = io_dmem_store_ack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_fp_rm_0 = io_dmem_store_ack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_store_ack_0_bits_uop_fp_typ_0 = io_dmem_store_ack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_pf_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ae_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_xcpt_ma_if_0 = io_dmem_store_ack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_debug_if_0 = io_dmem_store_ack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_uop_bp_xcpt_if_0 = io_dmem_store_ack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_fsrc_0 = io_dmem_store_ack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_store_ack_0_bits_uop_debug_tsrc_0 = io_dmem_store_ack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_store_ack_0_bits_addr_0 = io_dmem_store_ack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_store_ack_0_bits_data_0 = io_dmem_store_ack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_store_ack_0_bits_is_hella_0 = io_dmem_store_ack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_nack_0_valid_0 = io_dmem_nack_0_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_inst_0 = io_dmem_nack_0_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_nack_0_bits_uop_debug_inst_0 = io_dmem_nack_0_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rvc_0 = io_dmem_nack_0_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_uop_debug_pc_0 = io_dmem_nack_0_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_0_0 = io_dmem_nack_0_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_1_0 = io_dmem_nack_0_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_2_0 = io_dmem_nack_0_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iq_type_3_0 = io_dmem_nack_0_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_0_0 = io_dmem_nack_0_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_1_0 = io_dmem_nack_0_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_2_0 = io_dmem_nack_0_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_3_0 = io_dmem_nack_0_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_4_0 = io_dmem_nack_0_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_5_0 = io_dmem_nack_0_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_6_0 = io_dmem_nack_0_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_7_0 = io_dmem_nack_0_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_8_0 = io_dmem_nack_0_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fu_code_9_0 = io_dmem_nack_0_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_0 = io_dmem_nack_0_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_agen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_issued_partial_dgen_0 = io_dmem_nack_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_iw_p1_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_iw_p2_speculative_child_0 = io_dmem_nack_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p1_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p2_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_iw_p3_bypass_hint_0 = io_dmem_nack_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_dis_col_sel_0 = io_dmem_nack_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_nack_0_bits_uop_br_mask_0 = io_dmem_nack_0_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_tag_0 = io_dmem_nack_0_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_nack_0_bits_uop_br_type_0 = io_dmem_nack_0_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfb_0 = io_dmem_nack_0_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fence_0 = io_dmem_nack_0_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_fencei_0 = io_dmem_nack_0_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sfence_0 = io_dmem_nack_0_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_amo_0 = io_dmem_nack_0_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_eret_0 = io_dmem_nack_0_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_sys_pc2epc_0 = io_dmem_nack_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_rocc_0 = io_dmem_nack_0_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_mov_0 = io_dmem_nack_0_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ftq_idx_0 = io_dmem_nack_0_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_edge_inst_0 = io_dmem_nack_0_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_pc_lob_0 = io_dmem_nack_0_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_taken_0 = io_dmem_nack_0_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_imm_rename_0 = io_dmem_nack_0_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_imm_sel_0 = io_dmem_nack_0_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_pimm_0 = io_dmem_nack_0_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_nack_0_bits_uop_imm_packed_0 = io_dmem_nack_0_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_op1_sel_0 = io_dmem_nack_0_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_op2_sel_0 = io_dmem_nack_0_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ldst_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wen_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren1_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren2_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_ren3_0 = io_dmem_nack_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap12_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_swap23_0 = io_dmem_nack_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_nack_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fromint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_toint_0 = io_dmem_nack_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_fma_0 = io_dmem_nack_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_div_0 = io_dmem_nack_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_sqrt_0 = io_dmem_nack_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_wflags_0 = io_dmem_nack_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_ctrl_vec_0 = io_dmem_nack_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_rob_idx_0 = io_dmem_nack_0_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ldq_idx_0 = io_dmem_nack_0_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_stq_idx_0 = io_dmem_nack_0_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_rxq_idx_0 = io_dmem_nack_0_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_pdst_0 = io_dmem_nack_0_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs1_0 = io_dmem_nack_0_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs2_0 = io_dmem_nack_0_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_prs3_0 = io_dmem_nack_0_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_ppred_0 = io_dmem_nack_0_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs1_busy_0 = io_dmem_nack_0_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs2_busy_0 = io_dmem_nack_0_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_prs3_busy_0 = io_dmem_nack_0_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ppred_busy_0 = io_dmem_nack_0_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_nack_0_bits_uop_stale_pdst_0 = io_dmem_nack_0_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_exception_0 = io_dmem_nack_0_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_uop_exc_cause_0 = io_dmem_nack_0_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_mem_cmd_0 = io_dmem_nack_0_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_mem_size_0 = io_dmem_nack_0_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_mem_signed_0 = io_dmem_nack_0_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_ldq_0 = io_dmem_nack_0_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_uses_stq_0 = io_dmem_nack_0_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_is_unique_0 = io_dmem_nack_0_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_flush_on_commit_0 = io_dmem_nack_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_csr_cmd_0 = io_dmem_nack_0_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_ldst_is_rs1_0 = io_dmem_nack_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_ldst_0 = io_dmem_nack_0_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs1_0 = io_dmem_nack_0_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs2_0 = io_dmem_nack_0_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_nack_0_bits_uop_lrs3_0 = io_dmem_nack_0_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_dst_rtype_0 = io_dmem_nack_0_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs1_rtype_0 = io_dmem_nack_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_lrs2_rtype_0 = io_dmem_nack_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_frs3_en_0 = io_dmem_nack_0_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fcn_dw_0 = io_dmem_nack_0_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_nack_0_bits_uop_fcn_op_0 = io_dmem_nack_0_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_fp_val_0 = io_dmem_nack_0_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_fp_rm_0 = io_dmem_nack_0_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_nack_0_bits_uop_fp_typ_0 = io_dmem_nack_0_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_pf_if_0 = io_dmem_nack_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ae_if_0 = io_dmem_nack_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_xcpt_ma_if_0 = io_dmem_nack_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_debug_if_0 = io_dmem_nack_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_uop_bp_xcpt_if_0 = io_dmem_nack_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_fsrc_0 = io_dmem_nack_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_nack_0_bits_uop_debug_tsrc_0 = io_dmem_nack_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [39:0] io_dmem_nack_0_bits_addr_0 = io_dmem_nack_0_bits_addr; // @[lsu.scala:211:7] wire [63:0] io_dmem_nack_0_bits_data_0 = io_dmem_nack_0_bits_data; // @[lsu.scala:211:7] wire io_dmem_nack_0_bits_is_hella_0 = io_dmem_nack_0_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_ll_resp_valid_0 = io_dmem_ll_resp_valid; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_inst_0 = io_dmem_ll_resp_bits_uop_inst; // @[lsu.scala:211:7] wire [31:0] io_dmem_ll_resp_bits_uop_debug_inst_0 = io_dmem_ll_resp_bits_uop_debug_inst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rvc_0 = io_dmem_ll_resp_bits_uop_is_rvc; // @[lsu.scala:211:7] wire [39:0] io_dmem_ll_resp_bits_uop_debug_pc_0 = io_dmem_ll_resp_bits_uop_debug_pc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_0_0 = io_dmem_ll_resp_bits_uop_iq_type_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_1_0 = io_dmem_ll_resp_bits_uop_iq_type_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_2_0 = io_dmem_ll_resp_bits_uop_iq_type_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iq_type_3_0 = io_dmem_ll_resp_bits_uop_iq_type_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_0_0 = io_dmem_ll_resp_bits_uop_fu_code_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_1_0 = io_dmem_ll_resp_bits_uop_fu_code_1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_2_0 = io_dmem_ll_resp_bits_uop_fu_code_2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_3_0 = io_dmem_ll_resp_bits_uop_fu_code_3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_4_0 = io_dmem_ll_resp_bits_uop_fu_code_4; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_5_0 = io_dmem_ll_resp_bits_uop_fu_code_5; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_6_0 = io_dmem_ll_resp_bits_uop_fu_code_6; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_7_0 = io_dmem_ll_resp_bits_uop_fu_code_7; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_8_0 = io_dmem_ll_resp_bits_uop_fu_code_8; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fu_code_9_0 = io_dmem_ll_resp_bits_uop_fu_code_9; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_0 = io_dmem_ll_resp_bits_uop_iw_issued; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 = io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 = io_dmem_ll_resp_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 = io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_dis_col_sel_0 = io_dmem_ll_resp_bits_uop_dis_col_sel; // @[lsu.scala:211:7] wire [15:0] io_dmem_ll_resp_bits_uop_br_mask_0 = io_dmem_ll_resp_bits_uop_br_mask; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_tag_0 = io_dmem_ll_resp_bits_uop_br_tag; // @[lsu.scala:211:7] wire [3:0] io_dmem_ll_resp_bits_uop_br_type_0 = io_dmem_ll_resp_bits_uop_br_type; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfb_0 = io_dmem_ll_resp_bits_uop_is_sfb; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fence_0 = io_dmem_ll_resp_bits_uop_is_fence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_fencei_0 = io_dmem_ll_resp_bits_uop_is_fencei; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sfence_0 = io_dmem_ll_resp_bits_uop_is_sfence; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_amo_0 = io_dmem_ll_resp_bits_uop_is_amo; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_eret_0 = io_dmem_ll_resp_bits_uop_is_eret; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 = io_dmem_ll_resp_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_rocc_0 = io_dmem_ll_resp_bits_uop_is_rocc; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_mov_0 = io_dmem_ll_resp_bits_uop_is_mov; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ftq_idx_0 = io_dmem_ll_resp_bits_uop_ftq_idx; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_edge_inst_0 = io_dmem_ll_resp_bits_uop_edge_inst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_pc_lob_0 = io_dmem_ll_resp_bits_uop_pc_lob; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_taken_0 = io_dmem_ll_resp_bits_uop_taken; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_imm_rename_0 = io_dmem_ll_resp_bits_uop_imm_rename; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_imm_sel_0 = io_dmem_ll_resp_bits_uop_imm_sel; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_pimm_0 = io_dmem_ll_resp_bits_uop_pimm; // @[lsu.scala:211:7] wire [19:0] io_dmem_ll_resp_bits_uop_imm_packed_0 = io_dmem_ll_resp_bits_uop_imm_packed; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_op1_sel_0 = io_dmem_ll_resp_bits_uop_op1_sel; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_op2_sel_0 = io_dmem_ll_resp_bits_uop_op2_sel; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 = io_dmem_ll_resp_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_rob_idx_0 = io_dmem_ll_resp_bits_uop_rob_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ldq_idx_0 = io_dmem_ll_resp_bits_uop_ldq_idx; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_stq_idx_0 = io_dmem_ll_resp_bits_uop_stq_idx; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_rxq_idx_0 = io_dmem_ll_resp_bits_uop_rxq_idx; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_pdst_0 = io_dmem_ll_resp_bits_uop_pdst; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs1_0 = io_dmem_ll_resp_bits_uop_prs1; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs2_0 = io_dmem_ll_resp_bits_uop_prs2; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_prs3_0 = io_dmem_ll_resp_bits_uop_prs3; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_ppred_0 = io_dmem_ll_resp_bits_uop_ppred; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs1_busy_0 = io_dmem_ll_resp_bits_uop_prs1_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs2_busy_0 = io_dmem_ll_resp_bits_uop_prs2_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_prs3_busy_0 = io_dmem_ll_resp_bits_uop_prs3_busy; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ppred_busy_0 = io_dmem_ll_resp_bits_uop_ppred_busy; // @[lsu.scala:211:7] wire [6:0] io_dmem_ll_resp_bits_uop_stale_pdst_0 = io_dmem_ll_resp_bits_uop_stale_pdst; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_exception_0 = io_dmem_ll_resp_bits_uop_exception; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_uop_exc_cause_0 = io_dmem_ll_resp_bits_uop_exc_cause; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_mem_cmd_0 = io_dmem_ll_resp_bits_uop_mem_cmd; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_mem_size_0 = io_dmem_ll_resp_bits_uop_mem_size; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_mem_signed_0 = io_dmem_ll_resp_bits_uop_mem_signed; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_ldq_0 = io_dmem_ll_resp_bits_uop_uses_ldq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_uses_stq_0 = io_dmem_ll_resp_bits_uop_uses_stq; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_is_unique_0 = io_dmem_ll_resp_bits_uop_is_unique; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_flush_on_commit_0 = io_dmem_ll_resp_bits_uop_flush_on_commit; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_csr_cmd_0 = io_dmem_ll_resp_bits_uop_csr_cmd; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 = io_dmem_ll_resp_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_ldst_0 = io_dmem_ll_resp_bits_uop_ldst; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs1_0 = io_dmem_ll_resp_bits_uop_lrs1; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs2_0 = io_dmem_ll_resp_bits_uop_lrs2; // @[lsu.scala:211:7] wire [5:0] io_dmem_ll_resp_bits_uop_lrs3_0 = io_dmem_ll_resp_bits_uop_lrs3; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_dst_rtype_0 = io_dmem_ll_resp_bits_uop_dst_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs1_rtype_0 = io_dmem_ll_resp_bits_uop_lrs1_rtype; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_lrs2_rtype_0 = io_dmem_ll_resp_bits_uop_lrs2_rtype; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_frs3_en_0 = io_dmem_ll_resp_bits_uop_frs3_en; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fcn_dw_0 = io_dmem_ll_resp_bits_uop_fcn_dw; // @[lsu.scala:211:7] wire [4:0] io_dmem_ll_resp_bits_uop_fcn_op_0 = io_dmem_ll_resp_bits_uop_fcn_op; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_fp_val_0 = io_dmem_ll_resp_bits_uop_fp_val; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_fp_rm_0 = io_dmem_ll_resp_bits_uop_fp_rm; // @[lsu.scala:211:7] wire [1:0] io_dmem_ll_resp_bits_uop_fp_typ_0 = io_dmem_ll_resp_bits_uop_fp_typ; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 = io_dmem_ll_resp_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 = io_dmem_ll_resp_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_debug_if_0 = io_dmem_ll_resp_bits_uop_bp_debug_if; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 = io_dmem_ll_resp_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_fsrc_0 = io_dmem_ll_resp_bits_uop_debug_fsrc; // @[lsu.scala:211:7] wire [2:0] io_dmem_ll_resp_bits_uop_debug_tsrc_0 = io_dmem_ll_resp_bits_uop_debug_tsrc; // @[lsu.scala:211:7] wire [63:0] io_dmem_ll_resp_bits_data_0 = io_dmem_ll_resp_bits_data; // @[lsu.scala:211:7] wire io_dmem_ll_resp_bits_is_hella_0 = io_dmem_ll_resp_bits_is_hella; // @[lsu.scala:211:7] wire io_dmem_release_valid_0 = io_dmem_release_valid; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_opcode_0 = io_dmem_release_bits_opcode; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_param_0 = io_dmem_release_bits_param; // @[lsu.scala:211:7] wire [3:0] io_dmem_release_bits_size_0 = io_dmem_release_bits_size; // @[lsu.scala:211:7] wire [2:0] io_dmem_release_bits_source_0 = io_dmem_release_bits_source; // @[lsu.scala:211:7] wire [31:0] io_dmem_release_bits_address_0 = io_dmem_release_bits_address; // @[lsu.scala:211:7] wire [127:0] io_dmem_release_bits_data_0 = io_dmem_release_bits_data; // @[lsu.scala:211:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[lsu.scala:211:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[lsu.scala:211:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[lsu.scala:211:7] wire io_hellacache_req_valid_0 = io_hellacache_req_valid; // @[lsu.scala:211:7] wire [39:0] io_hellacache_req_bits_addr_0 = io_hellacache_req_bits_addr; // @[lsu.scala:211:7] wire io_hellacache_req_bits_dv_0 = io_hellacache_req_bits_dv; // @[lsu.scala:211:7] wire io_hellacache_s1_kill_0 = io_hellacache_s1_kill; // @[lsu.scala:211:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[lsu.scala:211:7] wire [15:0] _exe_tlb_uop_WIRE_br_mask = 16'h0; // @[lsu.scala:722:68] wire [15:0] _exe_tlb_uop_WIRE_1_br_mask = 16'h0; // @[lsu.scala:723:68] wire [15:0] _exe_tlb_uop_T_2_br_mask = 16'h0; // @[lsu.scala:722:24] wire [15:0] _dmem_req_0_bits_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [15:0] _dmem_req_0_bits_data_T_17 = 16'h0; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_21 = 16'h0; // @[AMOALU.scala:29:69] wire [15:0] _mem_ldq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:1064:73] wire [15:0] _mem_stq_e_WIRE_bits_uop_br_mask = 16'h0; // @[lsu.scala:1067:87] wire [15:0] _lcam_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [31:0] io_core_status_isa = 32'h14112D; // @[lsu.scala:211:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[lsu.scala:211:7] wire [22:0] io_core_status_zero2 = 23'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_hu = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spvp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_spv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_debug = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_cease = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_wfi = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_dv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_v = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_gva = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sbe = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tsr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tw = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_tvm = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mxr = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sum = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mprv = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spp = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mpie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_ube = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_spie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_upie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_mie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_hie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_sie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_gstatus_uie = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[lsu.scala:211:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_predicated = 1'h0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:211:7] wire io_core_status_mbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sbe = 1'h0; // @[lsu.scala:211:7] wire io_core_status_sd_rv32 = 1'h0; // @[lsu.scala:211:7] wire io_core_status_ube = 1'h0; // @[lsu.scala:211:7] wire io_core_status_upie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_hie = 1'h0; // @[lsu.scala:211:7] wire io_core_status_uie = 1'h0; // @[lsu.scala:211:7] wire io_dmem_s1_nack_advisory_0 = 1'h0; // @[lsu.scala:211:7] wire io_dmem_release_bits_corrupt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_resp = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_alloc = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_req_bits_no_xcpt = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_cause_raw = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_kill = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_uncached = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_signed = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_replay = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_replay_next = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_s2_gpa_is_pte = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_ordered = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_acquire = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_release = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_grant = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_tlbMiss = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_blocked = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptStoreThenRMW = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_canAcceptLoadThenLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterLoad = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_perf_storeBufferEmptyAfterStore = 1'h0; // @[lsu.scala:211:7] wire io_hellacache_keep_clock_enabled = 1'h0; // @[lsu.scala:211:7] wire _block_load_mask_WIRE_0 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_1 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_2 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_3 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_4 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_5 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_6 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_7 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_8 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_9 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_10 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_11 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_12 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_13 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_14 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_15 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_16 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_17 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_18 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_19 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_20 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_21 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_22 = 1'h0; // @[lsu.scala:488:44] wire _block_load_mask_WIRE_23 = 1'h0; // @[lsu.scala:488:44] wire _can_fire_hella_incoming_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _can_fire_hella_wakeup_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire _will_fire_sfence_0_will_fire_T = 1'h0; // @[lsu.scala:656:51] wire _will_fire_sfence_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_sfence_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_sfence_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_sfence_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_sfence_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_sfence_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_sfence_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_commit_fast_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_fast_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_store_commit_fast_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_fast_0_will_fire_T_8 = 1'h0; // @[lsu.scala:658:50] wire _will_fire_store_commit_fast_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_commit_fast_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_fast_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_load_agen_exec_0_will_fire_T_4 = 1'h0; // @[lsu.scala:657:52] wire _will_fire_load_agen_exec_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_load_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_load_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_store_agen_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_agen_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_release_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_release_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_release_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_release_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_hella_incoming_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_incoming_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_hella_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_hella_wakeup_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_hella_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_hella_wakeup_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _will_fire_store_retry_0_will_fire_T_9 = 1'h0; // @[lsu.scala:658:47] wire _will_fire_store_retry_0_T_6 = 1'h0; // @[lsu.scala:661:46] wire _will_fire_load_wakeup_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_load_wakeup_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_will_fire_T_1 = 1'h0; // @[lsu.scala:656:48] wire _will_fire_store_commit_slow_0_will_fire_T_5 = 1'h0; // @[lsu.scala:657:49] wire _will_fire_store_commit_slow_0_T = 1'h0; // @[lsu.scala:659:46] wire _will_fire_store_commit_slow_0_T_3 = 1'h0; // @[lsu.scala:660:46] wire _exe_tlb_uop_WIRE_is_rvc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iq_type_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_0 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_4 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_5 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_6 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_7 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_8 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fu_code_9 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfb = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_fencei = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sfence = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_amo = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_eret = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_rocc = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_mov = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_edge_inst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_taken = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_imm_rename = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_div = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs1_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs2_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_prs3_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ppred_busy = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_exception = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_mem_signed = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_ldq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_uses_stq = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_is_unique = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_flush_on_commit = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_frs3_en = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fcn_dw = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_fp_val = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_pf_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ae_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_xcpt_ma_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_debug_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_bp_xcpt_if = 1'h0; // @[lsu.scala:722:68] wire _exe_tlb_uop_WIRE_1_is_rvc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iq_type_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_0 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_4 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_5 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_6 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_7 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_8 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fu_code_9 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_agen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfb = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_fencei = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sfence = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_amo = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_eret = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_sys_pc2epc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_rocc = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_mov = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_edge_inst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_taken = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_imm_rename = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ldst = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wen = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fromint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_toint = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_fma = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_div = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_wflags = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_ctrl_vec = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs1_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs2_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_prs3_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ppred_busy = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_exception = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_mem_signed = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_ldq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_uses_stq = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_is_unique = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_flush_on_commit = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_ldst_is_rs1 = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_frs3_en = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fcn_dw = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_fp_val = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_pf_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ae_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_xcpt_ma_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_debug_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_WIRE_1_bp_xcpt_if = 1'h0; // @[lsu.scala:723:68] wire _exe_tlb_uop_T_2_is_rvc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iq_type_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_0 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_4 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_5 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_6 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_7 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_8 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fu_code_9 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_agen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfb = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_fencei = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sfence = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_amo = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_eret = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_sys_pc2epc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_rocc = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_mov = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_edge_inst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_taken = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_imm_rename = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ldst = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wen = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fromint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_toint = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_fma = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_div = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_wflags = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_ctrl_vec = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs1_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs2_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_prs3_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ppred_busy = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_exception = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_mem_signed = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_ldq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_uses_stq = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_is_unique = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_flush_on_commit = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_ldst_is_rs1 = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_frs3_en = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fcn_dw = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_fp_val = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_pf_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ae_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_xcpt_ma_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_debug_if = 1'h0; // @[lsu.scala:722:24] wire _exe_tlb_uop_T_2_bp_xcpt_if = 1'h0; // @[lsu.scala:722:24] wire _dbg_bp_T = 1'h0; // @[lsu.scala:788:80] wire _dbg_bp_T_1 = 1'h0; // @[lsu.scala:789:80] wire _dbg_bp_T_3 = 1'h0; // @[lsu.scala:789:104] wire _dbg_bp_T_4 = 1'h0; // @[lsu.scala:788:105] wire _dbg_bp_T_5 = 1'h0; // @[lsu.scala:788:51] wire dbg_bp_0 = 1'h0; // @[lsu.scala:321:49] wire _bp_T = 1'h0; // @[lsu.scala:790:80] wire _bp_T_1 = 1'h0; // @[lsu.scala:791:80] wire _bp_T_3 = 1'h0; // @[lsu.scala:791:103] wire _bp_T_4 = 1'h0; // @[lsu.scala:790:104] wire _bp_T_5 = 1'h0; // @[lsu.scala:790:51] wire bp_0 = 1'h0; // @[lsu.scala:321:49] wire _exe_tlb_miss_T = 1'h0; // @[lsu.scala:835:86] wire _s0_executing_loads_WIRE_0 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_1 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_2 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_3 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_4 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_5 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_6 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_7 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_8 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_9 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_10 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_11 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_12 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_13 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_14 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_15 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_16 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_17 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_18 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_19 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_20 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_21 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_22 = 1'h0; // @[lsu.scala:882:44] wire _s0_executing_loads_WIRE_23 = 1'h0; // @[lsu.scala:882:44] wire _dmem_req_0_bits_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _dmem_req_0_bits_data_T_15 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_20 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_24 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_30 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_35 = 1'h0; // @[AMOALU.scala:29:19] wire _dmem_req_0_bits_data_T_39 = 1'h0; // @[AMOALU.scala:29:19] wire _mem_ldq_e_WIRE_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_addr_is_uncacheable = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_executed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_order_fail = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_observed = 1'h0; // @[lsu.scala:1064:73] wire _mem_ldq_e_WIRE_bits_forward_std_val = 1'h0; // @[lsu.scala:1064:73] wire _mem_stq_e_WIRE_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rvc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iq_type_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_0 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_4 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_5 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_6 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_7 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_8 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fu_code_9 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_agen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_issued_partial_dgen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p1_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p2_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_iw_p3_bypass_hint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfb = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_fencei = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sfence = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_amo = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_eret = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_sys_pc2epc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_rocc = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_mov = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_edge_inst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_taken = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_imm_rename = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ldst = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wen = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren2 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_ren3 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap12 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_swap23 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fromint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_toint = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_fma = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_div = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_sqrt = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_wflags = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_ctrl_vec = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs1_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs2_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_prs3_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ppred_busy = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_exception = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_mem_signed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_ldq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_uses_stq = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_is_unique = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_flush_on_commit = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_ldst_is_rs1 = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_frs3_en = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fcn_dw = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_fp_val = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_pf_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ae_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_xcpt_ma_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_debug_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_uop_bp_xcpt_if = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_addr_is_virtual = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_data_valid = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_committed = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_succeeded = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_can_execute = 1'h0; // @[lsu.scala:1067:87] wire _mem_stq_e_WIRE_bits_cleared = 1'h0; // @[lsu.scala:1067:87] wire _lcam_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _lcam_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire _kill_forward_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire iresp_0_bits_predicated = 1'h0; // @[lsu.scala:1477:19] wire iresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1477:19] wire fresp_0_bits_predicated = 1'h0; // @[lsu.scala:1478:19] wire fresp_0_bits_fflags_valid = 1'h0; // @[lsu.scala:1478:19] wire io_core_iresp_0_out_bits_predicated = 1'h0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_fflags_valid = 1'h0; // @[util.scala:114:23] wire wb_spec_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1491:29] wire wb_slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_bypassable = 1'h0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_rebusy = 1'h0; // @[lsu.scala:1495:26] wire _dmem_resp_fired_WIRE_0 = 1'h0; // @[lsu.scala:321:49] wire w1_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire w2_bits_out_rebusy = 1'h0; // @[util.scala:109:23] wire iresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire iresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire fresp_0_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire ldq_debug_wb_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire slow_wakeups_0_out_bits_bypassable = 1'h0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_rebusy = 1'h0; // @[util.scala:114:23] wire _io_hellacache_s2_xcpt_WIRE_ma_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ma_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_pf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_gf_st = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_ld = 1'h0; // @[lsu.scala:1797:44] wire _io_hellacache_s2_xcpt_WIRE_ae_st = 1'h0; // @[lsu.scala:1797:44] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_core_status_zero1 = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_req_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_s1_data_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] io_hellacache_resp_bits_mask = 8'h0; // @[lsu.scala:211:7] wire [7:0] _dmem_req_0_bits_data_T_16 = 8'h0; // @[AMOALU.scala:29:69] wire [7:0] _mem_ldq_e_WIRE_bits_ld_byte_mask = 8'h0; // @[lsu.scala:1064:73] wire [1:0] io_ptw_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_xs = 2'h0; // @[lsu.scala:211:7] wire [1:0] io_core_status_vs = 2'h0; // @[lsu.scala:211:7] wire [1:0] _exe_tlb_uop_WIRE_op1_sel = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_rxq_idx = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_mem_size = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_dst_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs1_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_lrs2_rtype = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_fp_typ = 2'h0; // @[lsu.scala:722:68] wire [1:0] _exe_tlb_uop_WIRE_1_op1_sel = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_rxq_idx = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_mem_size = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_dst_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs1_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_lrs2_rtype = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_WIRE_1_fp_typ = 2'h0; // @[lsu.scala:723:68] wire [1:0] _exe_tlb_uop_T_2_op1_sel = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_rxq_idx = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_mem_size = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_dst_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs1_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_lrs2_rtype = 2'h0; // @[lsu.scala:722:24] wire [1:0] _exe_tlb_uop_T_2_fp_typ = 2'h0; // @[lsu.scala:722:24] wire [1:0] _dmem_req_0_bits_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _dmem_req_0_bits_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] _mem_ldq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_ldq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1064:73] wire [1:0] _mem_stq_e_WIRE_bits_uop_op1_sel = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_rxq_idx = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_mem_size = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_dst_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs1_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_lrs2_rtype = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _mem_stq_e_WIRE_bits_uop_fp_typ = 2'h0; // @[lsu.scala:1067:87] wire [1:0] _lcam_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _lcam_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_req_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] io_hellacache_resp_bits_cmd = 5'h0; // @[lsu.scala:211:7] wire [4:0] _exe_tlb_uop_WIRE_ftq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_pimm = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ldq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_stq_idx = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_ppred = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_mem_cmd = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_fcn_op = 5'h0; // @[lsu.scala:722:68] wire [4:0] _exe_tlb_uop_WIRE_1_ftq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_pimm = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ldq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_stq_idx = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_ppred = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_mem_cmd = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_WIRE_1_fcn_op = 5'h0; // @[lsu.scala:723:68] wire [4:0] _exe_tlb_uop_T_2_ftq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_pimm = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ldq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_stq_idx = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_ppred = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_mem_cmd = 5'h0; // @[lsu.scala:722:24] wire [4:0] _exe_tlb_uop_T_2_fcn_op = 5'h0; // @[lsu.scala:722:24] wire [4:0] _dmem_req_0_bits_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _dmem_req_0_bits_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_ldq_e_WIRE_bits_forward_stq_idx = 5'h0; // @[lsu.scala:1064:73] wire [4:0] _mem_stq_e_WIRE_bits_uop_ftq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_pimm = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ldq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_stq_idx = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_ppred = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_mem_cmd = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _mem_stq_e_WIRE_bits_uop_fcn_op = 5'h0; // @[lsu.scala:1067:87] wire [4:0] _lcam_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _lcam_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] iresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1477:19] wire [4:0] fresp_0_bits_fflags_bits = 5'h0; // @[lsu.scala:1478:19] wire [4:0] io_core_iresp_0_out_bits_fflags_bits = 5'h0; // @[util.scala:114:23] wire [6:0] io_hellacache_req_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] io_hellacache_resp_bits_tag = 7'h0; // @[lsu.scala:211:7] wire [6:0] _exe_tlb_uop_WIRE_rob_idx = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs1 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs2 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_prs3 = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_stale_pdst = 7'h0; // @[lsu.scala:722:68] wire [6:0] _exe_tlb_uop_WIRE_1_rob_idx = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs1 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs2 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_prs3 = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_WIRE_1_stale_pdst = 7'h0; // @[lsu.scala:723:68] wire [6:0] _exe_tlb_uop_T_2_rob_idx = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs1 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs2 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_prs3 = 7'h0; // @[lsu.scala:722:24] wire [6:0] _exe_tlb_uop_T_2_stale_pdst = 7'h0; // @[lsu.scala:722:24] wire [6:0] _dmem_req_0_bits_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _dmem_req_0_bits_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _mem_ldq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_ldq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1064:73] wire [6:0] _mem_stq_e_WIRE_bits_uop_rob_idx = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs1 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs2 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_prs3 = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _mem_stq_e_WIRE_bits_uop_stale_pdst = 7'h0; // @[lsu.scala:1067:87] wire [6:0] _lcam_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _lcam_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [1:0] io_hellacache_req_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] io_hellacache_resp_bits_size = 2'h3; // @[lsu.scala:211:7] wire [1:0] dmem_req_0_bits_data_size_1 = 2'h3; // @[AMOALU.scala:11:18] wire [1:0] dmem_req_0_bits_data_size_2 = 2'h3; // @[AMOALU.scala:11:18] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_req_bits_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_s1_data_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_store_data = 64'h0; // @[lsu.scala:211:7] wire [63:0] _exe_tlb_uop_WIRE_exc_cause = 64'h0; // @[lsu.scala:722:68] wire [63:0] _exe_tlb_uop_WIRE_1_exc_cause = 64'h0; // @[lsu.scala:723:68] wire [63:0] _exe_tlb_uop_T_2_exc_cause = 64'h0; // @[lsu.scala:722:24] wire [63:0] _dmem_req_0_bits_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] _dmem_req_0_bits_data_T_19 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_23 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_26 = 64'h0; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_27 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_28 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_29 = 64'h0; // @[AMOALU.scala:29:13] wire [63:0] _mem_ldq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_ldq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1064:73] wire [63:0] _mem_stq_e_WIRE_bits_uop_exc_cause = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_data_bits = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _mem_stq_e_WIRE_bits_debug_wb_data = 64'h0; // @[lsu.scala:1067:87] wire [63:0] _lcam_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [2:0] _exe_tlb_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_dis_col_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_imm_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_op2_sel = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_csr_cmd = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_fp_rm = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_fsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_debug_tsrc = 3'h0; // @[lsu.scala:722:68] wire [2:0] _exe_tlb_uop_WIRE_1_iw_p1_speculative_child = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_iw_p2_speculative_child = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_dis_col_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_imm_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_op2_sel = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_csr_cmd = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_fp_rm = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_fsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_WIRE_1_debug_tsrc = 3'h0; // @[lsu.scala:723:68] wire [2:0] _exe_tlb_uop_T_2_iw_p1_speculative_child = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_iw_p2_speculative_child = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_dis_col_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_imm_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_op2_sel = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_csr_cmd = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_fp_rm = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_fsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _exe_tlb_uop_T_2_debug_tsrc = 3'h0; // @[lsu.scala:722:24] wire [2:0] _dmem_req_0_bits_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _dmem_req_0_bits_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iw_p1_speculative_child = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_iw_p2_speculative_child = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_dis_col_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_ldq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1064:73] wire [2:0] _mem_stq_e_WIRE_bits_uop_iw_p1_speculative_child = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_iw_p2_speculative_child = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_dis_col_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_imm_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_op2_sel = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_csr_cmd = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_fp_rm = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_fsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _mem_stq_e_WIRE_bits_uop_debug_tsrc = 3'h0; // @[lsu.scala:1067:87] wire [2:0] _lcam_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _lcam_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] wb_spec_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1491:29] wire [2:0] wb_slow_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1494:29] wire [2:0] slow_wakeups_0_bits_speculative_mask = 3'h0; // @[lsu.scala:1495:26] wire [2:0] w1_bits_out_speculative_mask = 3'h0; // @[util.scala:109:23] wire [2:0] w2_bits_out_speculative_mask = 3'h0; // @[util.scala:109:23] wire [2:0] slow_wakeups_0_out_bits_speculative_mask = 3'h0; // @[util.scala:114:23] wire io_hellacache_req_bits_phys = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_has_data = 1'h1; // @[lsu.scala:211:7] wire io_hellacache_clock_enabled = 1'h1; // @[lsu.scala:211:7] wire _will_fire_sfence_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_sfence_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_sfence_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_sfence_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_sfence_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_sfence_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_sfence_0_T_8 = 1'h1; // @[lsu.scala:661:31] wire _will_fire_store_commit_fast_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_fast_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_fast_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_commit_fast_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_fast_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_commit_fast_0_T_5 = 1'h1; // @[lsu.scala:660:31] wire _will_fire_load_agen_exec_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_load_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_load_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_store_agen_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_agen_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_release_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_release_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_release_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_release_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_hella_incoming_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_incoming_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_hella_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_hella_wakeup_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_hella_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_hella_wakeup_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _will_fire_store_retry_0_will_fire_T_10 = 1'h1; // @[lsu.scala:658:35] wire _will_fire_store_retry_0_T_7 = 1'h1; // @[lsu.scala:661:34] wire _will_fire_load_wakeup_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_load_wakeup_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_will_fire_T_2 = 1'h1; // @[lsu.scala:656:35] wire _will_fire_store_commit_slow_0_will_fire_T_6 = 1'h1; // @[lsu.scala:657:35] wire _will_fire_store_commit_slow_0_T_1 = 1'h1; // @[lsu.scala:659:34] wire _will_fire_store_commit_slow_0_T_4 = 1'h1; // @[lsu.scala:660:34] wire _dmem_req_0_valid_T_2 = 1'h1; // @[lsu.scala:937:86] wire _wakeupArbs_0_io_in_1_valid_T_1 = 1'h1; // @[lsu.scala:1459:40] wire wb_spec_wakeups_0_bits_bypassable = 1'h1; // @[lsu.scala:1491:29] wire w1_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire w2_bits_out_bypassable = 1'h1; // @[util.scala:109:23] wire [1:0] io_hellacache_req_bits_dprv = 2'h1; // @[lsu.scala:211:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[lsu.scala:211:7] wire [3:0] _exe_tlb_uop_WIRE_br_tag = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_br_type = 4'h0; // @[lsu.scala:722:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_tag = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_WIRE_1_br_type = 4'h0; // @[lsu.scala:723:68] wire [3:0] _exe_tlb_uop_T_2_br_tag = 4'h0; // @[lsu.scala:722:24] wire [3:0] _exe_tlb_uop_T_2_br_type = 4'h0; // @[lsu.scala:722:24] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _dmem_req_0_bits_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_ldq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1064:73] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_tag = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _mem_stq_e_WIRE_bits_uop_br_type = 4'h0; // @[lsu.scala:1067:87] wire [3:0] _lcam_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _lcam_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_sxl = 2'h2; // @[lsu.scala:211:7] wire [1:0] io_core_status_uxl = 2'h2; // @[lsu.scala:211:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[lsu.scala:211:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[lsu.scala:211:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[lsu.scala:211:7] wire [5:0] _exe_tlb_uop_WIRE_pc_lob = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_ldst = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs1 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs2 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_lrs3 = 6'h0; // @[lsu.scala:722:68] wire [5:0] _exe_tlb_uop_WIRE_1_pc_lob = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_ldst = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs1 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs2 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_WIRE_1_lrs3 = 6'h0; // @[lsu.scala:723:68] wire [5:0] _exe_tlb_uop_T_2_pc_lob = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_ldst = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs1 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs2 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _exe_tlb_uop_T_2_lrs3 = 6'h0; // @[lsu.scala:722:24] wire [5:0] _dmem_req_0_bits_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _dmem_req_0_bits_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mem_ldq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_ldq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1064:73] wire [5:0] _mem_stq_e_WIRE_bits_uop_pc_lob = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_ldst = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs1 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs2 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _mem_stq_e_WIRE_bits_uop_lrs3 = 6'h0; // @[lsu.scala:1067:87] wire [5:0] _lcam_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _lcam_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_0 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_1 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_core_commit_debug_insts_2 = 32'h0; // @[lsu.scala:211:7] wire [31:0] io_hellacache_s2_paddr = 32'h0; // @[lsu.scala:211:7] wire [31:0] _exe_tlb_uop_WIRE_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_debug_inst = 32'h0; // @[lsu.scala:722:68] wire [31:0] _exe_tlb_uop_WIRE_1_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_WIRE_1_debug_inst = 32'h0; // @[lsu.scala:723:68] wire [31:0] _exe_tlb_uop_T_2_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _exe_tlb_uop_T_2_debug_inst = 32'h0; // @[lsu.scala:722:24] wire [31:0] _dmem_req_0_bits_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _dmem_req_0_bits_data_T_18 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_22 = 32'h0; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_25 = 32'h0; // @[AMOALU.scala:29:69] wire [31:0] _mem_ldq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_ldq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1064:73] wire [31:0] _mem_stq_e_WIRE_bits_uop_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _mem_stq_e_WIRE_bits_uop_debug_inst = 32'h0; // @[lsu.scala:1067:87] wire [31:0] _lcam_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _lcam_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [39:0] io_hellacache_s2_gpa = 40'h0; // @[lsu.scala:211:7] wire [39:0] _exe_tlb_uop_WIRE_debug_pc = 40'h0; // @[lsu.scala:722:68] wire [39:0] _exe_tlb_uop_WIRE_1_debug_pc = 40'h0; // @[lsu.scala:723:68] wire [39:0] _exe_tlb_uop_T_2_debug_pc = 40'h0; // @[lsu.scala:722:24] wire [39:0] _dmem_req_0_bits_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] _mem_ldq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_ldq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1064:73] wire [39:0] _mem_stq_e_WIRE_bits_uop_debug_pc = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _mem_stq_e_WIRE_bits_addr_bits = 40'h0; // @[lsu.scala:1067:87] wire [39:0] _lcam_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [7:0] _ldq_ld_byte_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _lcam_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _nack_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _forward_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_11 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_26 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_41 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_56 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_71 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_86 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_101 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_116 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_131 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_146 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_161 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_176 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_191 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_206 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_221 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_236 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_251 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_266 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_281 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_296 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_311 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_326 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_341 = 8'hFF; // @[Mux.scala:126:16] wire [7:0] _write_mask_mask_T_356 = 8'hFF; // @[Mux.scala:126:16] wire [19:0] _exe_tlb_uop_WIRE_imm_packed = 20'h0; // @[lsu.scala:722:68] wire [19:0] _exe_tlb_uop_WIRE_1_imm_packed = 20'h0; // @[lsu.scala:723:68] wire [19:0] _exe_tlb_uop_T_2_imm_packed = 20'h0; // @[lsu.scala:722:24] wire [19:0] _dmem_req_0_bits_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] _mem_ldq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1064:73] wire [19:0] _mem_stq_e_WIRE_bits_uop_imm_packed = 20'h0; // @[lsu.scala:1067:87] wire [19:0] _lcam_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [23:0] _mem_ldq_e_WIRE_bits_st_dep_mask = 24'h0; // @[lsu.scala:1064:73] wire [3:0] _stq_tail_plus_sum_T_1 = 4'h6; // @[util.scala:174:43] wire [1:0] io_hellacache_resp_bits_dprv_0 = io_ptw_status_prv_0; // @[lsu.scala:211:7] wire io_hellacache_resp_bits_dv_0 = io_ptw_status_v_0; // @[lsu.scala:211:7] wire [31:0] mem_incoming_uop_out_inst = io_core_agen_0_bits_uop_inst_0; // @[util.scala:104:23] wire [31:0] mem_incoming_uop_out_debug_inst = io_core_agen_0_bits_uop_debug_inst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rvc = io_core_agen_0_bits_uop_is_rvc_0; // @[util.scala:104:23] wire [39:0] mem_incoming_uop_out_debug_pc = io_core_agen_0_bits_uop_debug_pc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_0 = io_core_agen_0_bits_uop_iq_type_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_1 = io_core_agen_0_bits_uop_iq_type_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_2 = io_core_agen_0_bits_uop_iq_type_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iq_type_3 = io_core_agen_0_bits_uop_iq_type_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_0 = io_core_agen_0_bits_uop_fu_code_0_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_1 = io_core_agen_0_bits_uop_fu_code_1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_2 = io_core_agen_0_bits_uop_fu_code_2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_3 = io_core_agen_0_bits_uop_fu_code_3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_4 = io_core_agen_0_bits_uop_fu_code_4_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_5 = io_core_agen_0_bits_uop_fu_code_5_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_6 = io_core_agen_0_bits_uop_fu_code_6_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_7 = io_core_agen_0_bits_uop_fu_code_7_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_8 = io_core_agen_0_bits_uop_fu_code_8_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fu_code_9 = io_core_agen_0_bits_uop_fu_code_9_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued = io_core_agen_0_bits_uop_iw_issued_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_agen = io_core_agen_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_issued_partial_dgen = io_core_agen_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_iw_p1_speculative_child = io_core_agen_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_iw_p2_speculative_child = io_core_agen_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p1_bypass_hint = io_core_agen_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p2_bypass_hint = io_core_agen_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_iw_p3_bypass_hint = io_core_agen_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_dis_col_sel = io_core_agen_0_bits_uop_dis_col_sel_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_tag = io_core_agen_0_bits_uop_br_tag_0; // @[util.scala:104:23] wire [3:0] mem_incoming_uop_out_br_type = io_core_agen_0_bits_uop_br_type_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfb = io_core_agen_0_bits_uop_is_sfb_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fence = io_core_agen_0_bits_uop_is_fence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_fencei = io_core_agen_0_bits_uop_is_fencei_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sfence = io_core_agen_0_bits_uop_is_sfence_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_amo = io_core_agen_0_bits_uop_is_amo_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_eret = io_core_agen_0_bits_uop_is_eret_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_sys_pc2epc = io_core_agen_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_rocc = io_core_agen_0_bits_uop_is_rocc_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_mov = io_core_agen_0_bits_uop_is_mov_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ftq_idx = io_core_agen_0_bits_uop_ftq_idx_0; // @[util.scala:104:23] wire mem_incoming_uop_out_edge_inst = io_core_agen_0_bits_uop_edge_inst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_pc_lob = io_core_agen_0_bits_uop_pc_lob_0; // @[util.scala:104:23] wire mem_incoming_uop_out_taken = io_core_agen_0_bits_uop_taken_0; // @[util.scala:104:23] wire mem_incoming_uop_out_imm_rename = io_core_agen_0_bits_uop_imm_rename_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_imm_sel = io_core_agen_0_bits_uop_imm_sel_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_pimm = io_core_agen_0_bits_uop_pimm_0; // @[util.scala:104:23] wire [19:0] mem_incoming_uop_out_imm_packed = io_core_agen_0_bits_uop_imm_packed_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_op1_sel = io_core_agen_0_bits_uop_op1_sel_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_op2_sel = io_core_agen_0_bits_uop_op2_sel_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ldst = io_core_agen_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wen = io_core_agen_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren1 = io_core_agen_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren2 = io_core_agen_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_ren3 = io_core_agen_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap12 = io_core_agen_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_swap23 = io_core_agen_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagIn = io_core_agen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_ctrl_typeTagOut = io_core_agen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fromint = io_core_agen_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_toint = io_core_agen_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fastpipe = io_core_agen_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_fma = io_core_agen_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_div = io_core_agen_0_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_sqrt = io_core_agen_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_wflags = io_core_agen_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_ctrl_vec = io_core_agen_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_rob_idx = io_core_agen_0_bits_uop_rob_idx_0; // @[util.scala:104:23] wire [4:0] ldq_incoming_idx_0 = io_core_agen_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :321:49] wire [4:0] mem_incoming_uop_out_ldq_idx = io_core_agen_0_bits_uop_ldq_idx_0; // @[util.scala:104:23] wire [4:0] stq_incoming_idx_0 = io_core_agen_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :321:49] wire [4:0] mem_incoming_uop_out_stq_idx = io_core_agen_0_bits_uop_stq_idx_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_rxq_idx = io_core_agen_0_bits_uop_rxq_idx_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_pdst = io_core_agen_0_bits_uop_pdst_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs1 = io_core_agen_0_bits_uop_prs1_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs2 = io_core_agen_0_bits_uop_prs2_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_prs3 = io_core_agen_0_bits_uop_prs3_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_ppred = io_core_agen_0_bits_uop_ppred_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs1_busy = io_core_agen_0_bits_uop_prs1_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs2_busy = io_core_agen_0_bits_uop_prs2_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_prs3_busy = io_core_agen_0_bits_uop_prs3_busy_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ppred_busy = io_core_agen_0_bits_uop_ppred_busy_0; // @[util.scala:104:23] wire [6:0] mem_incoming_uop_out_stale_pdst = io_core_agen_0_bits_uop_stale_pdst_0; // @[util.scala:104:23] wire mem_incoming_uop_out_exception = io_core_agen_0_bits_uop_exception_0; // @[util.scala:104:23] wire [63:0] mem_incoming_uop_out_exc_cause = io_core_agen_0_bits_uop_exc_cause_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_mem_cmd = io_core_agen_0_bits_uop_mem_cmd_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_mem_size = io_core_agen_0_bits_uop_mem_size_0; // @[util.scala:104:23] wire mem_incoming_uop_out_mem_signed = io_core_agen_0_bits_uop_mem_signed_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_ldq = io_core_agen_0_bits_uop_uses_ldq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_uses_stq = io_core_agen_0_bits_uop_uses_stq_0; // @[util.scala:104:23] wire mem_incoming_uop_out_is_unique = io_core_agen_0_bits_uop_is_unique_0; // @[util.scala:104:23] wire mem_incoming_uop_out_flush_on_commit = io_core_agen_0_bits_uop_flush_on_commit_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_csr_cmd = io_core_agen_0_bits_uop_csr_cmd_0; // @[util.scala:104:23] wire mem_incoming_uop_out_ldst_is_rs1 = io_core_agen_0_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_ldst = io_core_agen_0_bits_uop_ldst_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs1 = io_core_agen_0_bits_uop_lrs1_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs2 = io_core_agen_0_bits_uop_lrs2_0; // @[util.scala:104:23] wire [5:0] mem_incoming_uop_out_lrs3 = io_core_agen_0_bits_uop_lrs3_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_dst_rtype = io_core_agen_0_bits_uop_dst_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs1_rtype = io_core_agen_0_bits_uop_lrs1_rtype_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_lrs2_rtype = io_core_agen_0_bits_uop_lrs2_rtype_0; // @[util.scala:104:23] wire mem_incoming_uop_out_frs3_en = io_core_agen_0_bits_uop_frs3_en_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fcn_dw = io_core_agen_0_bits_uop_fcn_dw_0; // @[util.scala:104:23] wire [4:0] mem_incoming_uop_out_fcn_op = io_core_agen_0_bits_uop_fcn_op_0; // @[util.scala:104:23] wire mem_incoming_uop_out_fp_val = io_core_agen_0_bits_uop_fp_val_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_fp_rm = io_core_agen_0_bits_uop_fp_rm_0; // @[util.scala:104:23] wire [1:0] mem_incoming_uop_out_fp_typ = io_core_agen_0_bits_uop_fp_typ_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_pf_if = io_core_agen_0_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ae_if = io_core_agen_0_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_xcpt_ma_if = io_core_agen_0_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_debug_if = io_core_agen_0_bits_uop_bp_debug_if_0; // @[util.scala:104:23] wire mem_incoming_uop_out_bp_xcpt_if = io_core_agen_0_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_fsrc = io_core_agen_0_bits_uop_debug_fsrc_0; // @[util.scala:104:23] wire [2:0] mem_incoming_uop_out_debug_tsrc = io_core_agen_0_bits_uop_debug_tsrc_0; // @[util.scala:104:23] wire fresp_0_valid; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_inst; // @[lsu.scala:1478:19] wire [31:0] fresp_0_bits_uop_debug_inst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rvc; // @[lsu.scala:1478:19] wire [39:0] fresp_0_bits_uop_debug_pc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iq_type_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_0; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_4; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_5; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_6; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_7; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_8; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fu_code_9; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:1478:19] wire [15:0] fresp_0_bits_uop_br_mask; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_tag; // @[lsu.scala:1478:19] wire [3:0] fresp_0_bits_uop_br_type; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfb; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_fencei; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sfence; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_amo; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_eret; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_rocc; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_mov; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ftq_idx; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_edge_inst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_pc_lob; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_taken; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_imm_rename; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_imm_sel; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_pimm; // @[lsu.scala:1478:19] wire [19:0] fresp_0_bits_uop_imm_packed; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_op1_sel; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_op2_sel; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_rob_idx; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ldq_idx; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_stq_idx; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_rxq_idx; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_pdst; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs1; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs2; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_prs3; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_ppred; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs1_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs2_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_prs3_busy; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ppred_busy; // @[lsu.scala:1478:19] wire [6:0] fresp_0_bits_uop_stale_pdst; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_exception; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_uop_exc_cause; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_mem_cmd; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_mem_size; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_mem_signed; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_ldq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_uses_stq; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_is_unique; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_csr_cmd; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_ldst; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs1; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs2; // @[lsu.scala:1478:19] wire [5:0] fresp_0_bits_uop_lrs3; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_dst_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_frs3_en; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fcn_dw; // @[lsu.scala:1478:19] wire [4:0] fresp_0_bits_uop_fcn_op; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_fp_val; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_fp_rm; // @[lsu.scala:1478:19] wire [1:0] fresp_0_bits_uop_fp_typ; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:1478:19] wire fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:1478:19] wire [2:0] fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:1478:19] wire [63:0] fresp_0_bits_data; // @[lsu.scala:1478:19] wire can_fire_sfence_0 = io_core_sfence_valid_0; // @[lsu.scala:211:7, :321:49] wire ldq_full; // @[lsu.scala:369:47] wire ldq_full_1; // @[lsu.scala:369:47] wire ldq_full_2; // @[lsu.scala:369:47] wire stq_full; // @[lsu.scala:373:47] wire stq_full_1; // @[lsu.scala:373:47] wire stq_full_2; // @[lsu.scala:373:47] wire _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_bsy_2_valid_T_4; // @[lsu.scala:1107:45] wire _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:1423:7] wire [15:0] io_dmem_brupdate_b1_resolve_mask_0 = io_core_brupdate_b1_resolve_mask_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_brupdate_b1_mispredict_mask_0 = io_core_brupdate_b1_mispredict_mask_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_inst_0 = io_core_brupdate_b2_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_brupdate_b2_uop_debug_inst_0 = io_core_brupdate_b2_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rvc_0 = io_core_brupdate_b2_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_uop_debug_pc_0 = io_core_brupdate_b2_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_0_0 = io_core_brupdate_b2_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_1_0 = io_core_brupdate_b2_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_2_0 = io_core_brupdate_b2_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iq_type_3_0 = io_core_brupdate_b2_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_0_0 = io_core_brupdate_b2_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_1_0 = io_core_brupdate_b2_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_2_0 = io_core_brupdate_b2_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_3_0 = io_core_brupdate_b2_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_4_0 = io_core_brupdate_b2_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_5_0 = io_core_brupdate_b2_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_6_0 = io_core_brupdate_b2_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_7_0 = io_core_brupdate_b2_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_8_0 = io_core_brupdate_b2_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fu_code_9_0 = io_core_brupdate_b2_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_0 = io_core_brupdate_b2_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_agen_0 = io_core_brupdate_b2_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_core_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_iw_p1_speculative_child_0 = io_core_brupdate_b2_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_iw_p2_speculative_child_0 = io_core_brupdate_b2_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_core_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_dis_col_sel_0 = io_core_brupdate_b2_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_brupdate_b2_uop_br_mask_0 = io_core_brupdate_b2_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_tag_0 = io_core_brupdate_b2_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_brupdate_b2_uop_br_type_0 = io_core_brupdate_b2_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfb_0 = io_core_brupdate_b2_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fence_0 = io_core_brupdate_b2_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_fencei_0 = io_core_brupdate_b2_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sfence_0 = io_core_brupdate_b2_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_amo_0 = io_core_brupdate_b2_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_eret_0 = io_core_brupdate_b2_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_sys_pc2epc_0 = io_core_brupdate_b2_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_rocc_0 = io_core_brupdate_b2_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_mov_0 = io_core_brupdate_b2_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ftq_idx_0 = io_core_brupdate_b2_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_edge_inst_0 = io_core_brupdate_b2_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_pc_lob_0 = io_core_brupdate_b2_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_taken_0 = io_core_brupdate_b2_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_imm_rename_0 = io_core_brupdate_b2_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_imm_sel_0 = io_core_brupdate_b2_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_pimm_0 = io_core_brupdate_b2_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_brupdate_b2_uop_imm_packed_0 = io_core_brupdate_b2_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_op1_sel_0 = io_core_brupdate_b2_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_op2_sel_0 = io_core_brupdate_b2_uop_op2_sel_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ldst_0 = io_core_brupdate_b2_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wen_0 = io_core_brupdate_b2_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren1_0 = io_core_brupdate_b2_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren2_0 = io_core_brupdate_b2_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_ren3_0 = io_core_brupdate_b2_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap12_0 = io_core_brupdate_b2_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_swap23_0 = io_core_brupdate_b2_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_core_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fromint_0 = io_core_brupdate_b2_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_toint_0 = io_core_brupdate_b2_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_core_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_fma_0 = io_core_brupdate_b2_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_div_0 = io_core_brupdate_b2_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_core_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_wflags_0 = io_core_brupdate_b2_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_ctrl_vec_0 = io_core_brupdate_b2_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_rob_idx_0 = io_core_brupdate_b2_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ldq_idx_0 = io_core_brupdate_b2_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_stq_idx_0 = io_core_brupdate_b2_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_rxq_idx_0 = io_core_brupdate_b2_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_pdst_0 = io_core_brupdate_b2_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs1_0 = io_core_brupdate_b2_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs2_0 = io_core_brupdate_b2_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_prs3_0 = io_core_brupdate_b2_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_ppred_0 = io_core_brupdate_b2_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs1_busy_0 = io_core_brupdate_b2_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs2_busy_0 = io_core_brupdate_b2_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_prs3_busy_0 = io_core_brupdate_b2_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ppred_busy_0 = io_core_brupdate_b2_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_brupdate_b2_uop_stale_pdst_0 = io_core_brupdate_b2_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_exception_0 = io_core_brupdate_b2_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_brupdate_b2_uop_exc_cause_0 = io_core_brupdate_b2_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_mem_cmd_0 = io_core_brupdate_b2_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_mem_size_0 = io_core_brupdate_b2_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_mem_signed_0 = io_core_brupdate_b2_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_ldq_0 = io_core_brupdate_b2_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_uses_stq_0 = io_core_brupdate_b2_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_is_unique_0 = io_core_brupdate_b2_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_flush_on_commit_0 = io_core_brupdate_b2_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_csr_cmd_0 = io_core_brupdate_b2_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_ldst_is_rs1_0 = io_core_brupdate_b2_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_ldst_0 = io_core_brupdate_b2_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs1_0 = io_core_brupdate_b2_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs2_0 = io_core_brupdate_b2_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_brupdate_b2_uop_lrs3_0 = io_core_brupdate_b2_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_dst_rtype_0 = io_core_brupdate_b2_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs1_rtype_0 = io_core_brupdate_b2_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_lrs2_rtype_0 = io_core_brupdate_b2_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_frs3_en_0 = io_core_brupdate_b2_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fcn_dw_0 = io_core_brupdate_b2_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_brupdate_b2_uop_fcn_op_0 = io_core_brupdate_b2_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_fp_val_0 = io_core_brupdate_b2_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_fp_rm_0 = io_core_brupdate_b2_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_uop_fp_typ_0 = io_core_brupdate_b2_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_pf_if_0 = io_core_brupdate_b2_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ae_if_0 = io_core_brupdate_b2_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_xcpt_ma_if_0 = io_core_brupdate_b2_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_debug_if_0 = io_core_brupdate_b2_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_uop_bp_xcpt_if_0 = io_core_brupdate_b2_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_fsrc_0 = io_core_brupdate_b2_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_uop_debug_tsrc_0 = io_core_brupdate_b2_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_mispredict_0 = io_core_brupdate_b2_mispredict_0; // @[lsu.scala:211:7] wire io_dmem_brupdate_b2_taken_0 = io_core_brupdate_b2_taken_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_brupdate_b2_cfi_type_0 = io_core_brupdate_b2_cfi_type_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_brupdate_b2_pc_sel_0 = io_core_brupdate_b2_pc_sel_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_brupdate_b2_jalr_target_0 = io_core_brupdate_b2_jalr_target_0; // @[lsu.scala:211:7] wire [20:0] io_dmem_brupdate_b2_target_offset_0 = io_core_brupdate_b2_target_offset_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_rob_pnr_idx_0 = io_core_rob_pnr_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_rob_head_idx_0 = io_core_rob_head_idx_0; // @[lsu.scala:211:7] wire io_dmem_exception_0 = io_core_exception_0; // @[lsu.scala:211:7] wire _io_core_fencei_rdy_T_1; // @[lsu.scala:446:42] wire _io_core_lxcpt_valid_T_4; // @[lsu.scala:1450:39] wire _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire dmem_req_0_valid; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_inst; // @[lsu.scala:877:22] wire [31:0] dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:877:22] wire [15:0] dmem_req_0_bits_uop_br_mask; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_tag; // @[lsu.scala:877:22] wire [3:0] dmem_req_0_bits_uop_br_type; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_amo; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_eret; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_mov; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_taken; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_pimm; // @[lsu.scala:877:22] wire [19:0] dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_pdst; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs1; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs2; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_prs3; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_ppred; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:877:22] wire [6:0] dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_exception; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_mem_size; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_is_unique; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_ldst; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs1; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs2; // @[lsu.scala:877:22] wire [5:0] dmem_req_0_bits_uop_lrs3; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:877:22] wire [4:0] dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_fp_val; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:877:22] wire [1:0] dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:877:22] wire dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:877:22] wire [2:0] dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:877:22] wire [39:0] dmem_req_0_bits_addr; // @[lsu.scala:877:22] wire [63:0] dmem_req_0_bits_data; // @[lsu.scala:877:22] wire dmem_req_0_bits_is_hella; // @[lsu.scala:877:22] wire _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:1537:55] wire [63:0] io_hellacache_resp_bits_data_word_bypass_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_raw_0 = io_dmem_ll_resp_bits_data_0; // @[lsu.scala:211:7] wire will_fire_release_0; // @[lsu.scala:475:41] wire _can_fire_release_T = io_dmem_release_valid_0; // @[lsu.scala:211:7, :598:66] wire io_core_perf_acquire_0 = io_dmem_perf_acquire_0; // @[lsu.scala:211:7] wire io_core_perf_release_0 = io_dmem_perf_release_0; // @[lsu.scala:211:7] wire _io_hellacache_store_pending_T_22; // @[lsu.scala:1804:52] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[lsu.scala:211:7] wire io_ptw_req_bits_valid_0; // @[lsu.scala:211:7] wire io_ptw_req_valid_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iwakeups_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iwakeups_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_iwakeups_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iwakeups_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iwakeups_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iwakeups_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iwakeups_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iwakeups_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iwakeups_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iwakeups_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_bypassable_0; // @[lsu.scala:211:7] wire [2:0] io_core_iwakeups_0_bits_speculative_mask_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_bits_rebusy_0; // @[lsu.scala:211:7] wire io_core_iwakeups_0_valid_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_iresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_iresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_iresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_iresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_iresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_iresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_iresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_iresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_iresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_iresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_iresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_iresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_iresp_0_valid_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_fresp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_fresp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_fresp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_fresp_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_fresp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_fresp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_fresp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_fresp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_fresp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_fresp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_fresp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [63:0] io_core_fresp_0_bits_data_0; // @[lsu.scala:211:7] wire io_core_fresp_0_valid_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_0_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_1_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_ldq_idx_2_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_0_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_1_0; // @[lsu.scala:211:7] wire [4:0] io_core_dis_stq_idx_2_0; // @[lsu.scala:211:7] wire io_core_ldq_full_0_0; // @[lsu.scala:211:7] wire io_core_ldq_full_1_0; // @[lsu.scala:211:7] wire io_core_ldq_full_2_0; // @[lsu.scala:211:7] wire io_core_stq_full_0_0; // @[lsu.scala:211:7] wire io_core_stq_full_1_0; // @[lsu.scala:211:7] wire io_core_stq_full_2_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_0_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_0_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_1_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_1_bits_0; // @[lsu.scala:211:7] wire io_core_clr_bsy_2_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_bsy_2_bits_0; // @[lsu.scala:211:7] wire io_core_clr_unsafe_0_valid_0; // @[lsu.scala:211:7] wire [6:0] io_core_clr_unsafe_0_bits_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_core_lxcpt_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_core_lxcpt_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_core_lxcpt_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_core_lxcpt_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_core_lxcpt_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_core_lxcpt_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_core_lxcpt_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_core_lxcpt_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_core_lxcpt_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_core_lxcpt_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [4:0] io_core_lxcpt_bits_cause_0; // @[lsu.scala:211:7] wire [39:0] io_core_lxcpt_bits_badvaddr_0; // @[lsu.scala:211:7] wire io_core_lxcpt_valid_0; // @[lsu.scala:211:7] wire io_core_perf_tlbMiss_0; // @[lsu.scala:211:7] wire io_core_fencei_rdy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_inst_0; // @[lsu.scala:211:7] wire [31:0] io_dmem_req_bits_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7] wire [15:0] io_dmem_req_bits_0_bits_uop_br_mask_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_tag_0; // @[lsu.scala:211:7] wire [3:0] io_dmem_req_bits_0_bits_uop_br_type_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_amo_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_eret_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_mov_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_taken_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_pimm_0; // @[lsu.scala:211:7] wire [19:0] io_dmem_req_bits_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_pdst_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs1_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs2_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_prs3_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_ppred_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7] wire [6:0] io_dmem_req_bits_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_exception_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_mem_size_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_is_unique_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_ldst_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs1_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs2_0; // @[lsu.scala:211:7] wire [5:0] io_dmem_req_bits_0_bits_uop_lrs3_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7] wire [4:0] io_dmem_req_bits_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_fp_val_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7] wire [1:0] io_dmem_req_bits_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7] wire [2:0] io_dmem_req_bits_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7] wire [39:0] io_dmem_req_bits_0_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_dmem_req_bits_0_bits_data_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_bits_is_hella_0; // @[lsu.scala:211:7] wire io_dmem_req_bits_0_valid_0; // @[lsu.scala:211:7] wire io_dmem_req_valid_0; // @[lsu.scala:211:7] wire io_dmem_s1_kill_0_0; // @[lsu.scala:211:7] wire io_dmem_ll_resp_ready_0; // @[lsu.scala:211:7] wire io_dmem_release_ready_0; // @[lsu.scala:211:7] wire io_dmem_force_order_0; // @[lsu.scala:211:7] wire io_hellacache_req_ready_0; // @[lsu.scala:211:7] wire [39:0] io_hellacache_resp_bits_addr_0; // @[lsu.scala:211:7] wire [63:0] io_hellacache_resp_bits_data_0; // @[lsu.scala:211:7] wire io_hellacache_resp_valid_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ma_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_pf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_gf_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_ld_0; // @[lsu.scala:211:7] wire io_hellacache_s2_xcpt_ae_st_0; // @[lsu.scala:211:7] wire io_hellacache_s2_nack_0; // @[lsu.scala:211:7] wire io_hellacache_store_pending_0; // @[lsu.scala:211:7] reg ldq_valid_0; // @[lsu.scala:218:36] reg ldq_valid_1; // @[lsu.scala:218:36] reg ldq_valid_2; // @[lsu.scala:218:36] reg ldq_valid_3; // @[lsu.scala:218:36] reg ldq_valid_4; // @[lsu.scala:218:36] reg ldq_valid_5; // @[lsu.scala:218:36] reg ldq_valid_6; // @[lsu.scala:218:36] reg ldq_valid_7; // @[lsu.scala:218:36] reg ldq_valid_8; // @[lsu.scala:218:36] reg ldq_valid_9; // @[lsu.scala:218:36] reg ldq_valid_10; // @[lsu.scala:218:36] reg ldq_valid_11; // @[lsu.scala:218:36] reg ldq_valid_12; // @[lsu.scala:218:36] reg ldq_valid_13; // @[lsu.scala:218:36] reg ldq_valid_14; // @[lsu.scala:218:36] reg ldq_valid_15; // @[lsu.scala:218:36] reg ldq_valid_16; // @[lsu.scala:218:36] reg ldq_valid_17; // @[lsu.scala:218:36] reg ldq_valid_18; // @[lsu.scala:218:36] reg ldq_valid_19; // @[lsu.scala:218:36] reg ldq_valid_20; // @[lsu.scala:218:36] reg ldq_valid_21; // @[lsu.scala:218:36] reg ldq_valid_22; // @[lsu.scala:218:36] reg ldq_valid_23; // @[lsu.scala:218:36] reg [31:0] ldq_uop_0_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_inst = ldq_uop_0_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_0_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_25_debug_inst = ldq_uop_0_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rvc; // @[lsu.scala:219:36] wire l_uop_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rvc = ldq_uop_0_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_0_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_25_debug_pc = ldq_uop_0_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_0; // @[lsu.scala:219:36] wire l_uop_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_0 = ldq_uop_0_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_1; // @[lsu.scala:219:36] wire l_uop_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_1 = ldq_uop_0_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_2; // @[lsu.scala:219:36] wire l_uop_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_2 = ldq_uop_0_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iq_type_3; // @[lsu.scala:219:36] wire l_uop_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_iq_type_3 = ldq_uop_0_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_0; // @[lsu.scala:219:36] wire l_uop_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_0 = ldq_uop_0_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_1; // @[lsu.scala:219:36] wire l_uop_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_1 = ldq_uop_0_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_2; // @[lsu.scala:219:36] wire l_uop_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_2 = ldq_uop_0_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_3; // @[lsu.scala:219:36] wire l_uop_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_3 = ldq_uop_0_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_4; // @[lsu.scala:219:36] wire l_uop_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_4 = ldq_uop_0_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_5; // @[lsu.scala:219:36] wire l_uop_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_5 = ldq_uop_0_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_6; // @[lsu.scala:219:36] wire l_uop_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_6 = ldq_uop_0_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_7; // @[lsu.scala:219:36] wire l_uop_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_7 = ldq_uop_0_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_8; // @[lsu.scala:219:36] wire l_uop_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_8 = ldq_uop_0_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fu_code_9; // @[lsu.scala:219:36] wire l_uop_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_25_fu_code_9 = ldq_uop_0_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued; // @[lsu.scala:219:36] wire l_uop_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued = ldq_uop_0_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_agen = ldq_uop_0_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_issued_partial_dgen = ldq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_iw_p1_speculative_child = ldq_uop_0_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_iw_p2_speculative_child = ldq_uop_0_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p1_bypass_hint = ldq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p2_bypass_hint = ldq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_25_iw_p3_bypass_hint = ldq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_dis_col_sel = ldq_uop_0_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_0_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_25_br_mask = ldq_uop_0_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_tag = ldq_uop_0_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_0_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_25_br_type = ldq_uop_0_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfb; // @[lsu.scala:219:36] wire l_uop_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfb = ldq_uop_0_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fence; // @[lsu.scala:219:36] wire l_uop_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fence = ldq_uop_0_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_fencei; // @[lsu.scala:219:36] wire l_uop_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_fencei = ldq_uop_0_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sfence; // @[lsu.scala:219:36] wire l_uop_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sfence = ldq_uop_0_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_amo; // @[lsu.scala:219:36] wire l_uop_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_amo = ldq_uop_0_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_eret; // @[lsu.scala:219:36] wire l_uop_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_eret = ldq_uop_0_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_sys_pc2epc = ldq_uop_0_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_rocc; // @[lsu.scala:219:36] wire l_uop_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_rocc = ldq_uop_0_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_mov; // @[lsu.scala:219:36] wire l_uop_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_mov = ldq_uop_0_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ftq_idx = ldq_uop_0_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_edge_inst; // @[lsu.scala:219:36] wire l_uop_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_25_edge_inst = ldq_uop_0_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_pc_lob = ldq_uop_0_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_taken; // @[lsu.scala:219:36] wire l_uop_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1191:37] wire uop_25_taken = ldq_uop_0_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_imm_rename; // @[lsu.scala:219:36] wire l_uop_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_25_imm_rename = ldq_uop_0_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_imm_sel = ldq_uop_0_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_pimm = ldq_uop_0_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_0_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_25_imm_packed = ldq_uop_0_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_op1_sel = ldq_uop_0_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_op2_sel = ldq_uop_0_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ldst = ldq_uop_0_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wen = ldq_uop_0_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren1 = ldq_uop_0_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren2 = ldq_uop_0_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_ren3 = ldq_uop_0_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap12 = ldq_uop_0_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_swap23 = ldq_uop_0_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagIn = ldq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_ctrl_typeTagOut = ldq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fromint = ldq_uop_0_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_toint = ldq_uop_0_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fastpipe = ldq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_fma = ldq_uop_0_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_div = ldq_uop_0_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_sqrt = ldq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_wflags = ldq_uop_0_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_ctrl_vec = ldq_uop_0_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_rob_idx = ldq_uop_0_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ldq_idx = ldq_uop_0_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_stq_idx = ldq_uop_0_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_rxq_idx = ldq_uop_0_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_pdst = ldq_uop_0_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs1 = ldq_uop_0_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs2 = ldq_uop_0_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_prs3 = ldq_uop_0_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_ppred = ldq_uop_0_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs1_busy; // @[lsu.scala:219:36] wire l_uop_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs1_busy = ldq_uop_0_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs2_busy; // @[lsu.scala:219:36] wire l_uop_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs2_busy = ldq_uop_0_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_prs3_busy; // @[lsu.scala:219:36] wire l_uop_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_prs3_busy = ldq_uop_0_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ppred_busy; // @[lsu.scala:219:36] wire l_uop_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_25_ppred_busy = ldq_uop_0_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_0_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_25_stale_pdst = ldq_uop_0_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_exception; // @[lsu.scala:219:36] wire l_uop_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1191:37] wire uop_25_exception = ldq_uop_0_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_0_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_25_exc_cause = ldq_uop_0_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_mem_cmd = ldq_uop_0_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_mem_size = ldq_uop_0_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_mem_signed; // @[lsu.scala:219:36] wire l_uop_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_25_mem_signed = ldq_uop_0_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_ldq; // @[lsu.scala:219:36] wire l_uop_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_ldq = ldq_uop_0_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_uses_stq; // @[lsu.scala:219:36] wire l_uop_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_25_uses_stq = ldq_uop_0_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_is_unique; // @[lsu.scala:219:36] wire l_uop_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_25_is_unique = ldq_uop_0_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_25_flush_on_commit = ldq_uop_0_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_csr_cmd = ldq_uop_0_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_25_ldst_is_rs1 = ldq_uop_0_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_ldst = ldq_uop_0_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs1 = ldq_uop_0_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs2 = ldq_uop_0_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_0_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_25_lrs3 = ldq_uop_0_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_dst_rtype = ldq_uop_0_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs1_rtype = ldq_uop_0_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_lrs2_rtype = ldq_uop_0_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_frs3_en; // @[lsu.scala:219:36] wire l_uop_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_25_frs3_en = ldq_uop_0_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fcn_dw; // @[lsu.scala:219:36] wire l_uop_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_25_fcn_dw = ldq_uop_0_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_0_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_25_fcn_op = ldq_uop_0_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_fp_val; // @[lsu.scala:219:36] wire l_uop_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_25_fp_val = ldq_uop_0_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_fp_rm = ldq_uop_0_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_0_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_25_fp_typ = ldq_uop_0_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_pf_if = ldq_uop_0_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ae_if = ldq_uop_0_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_xcpt_ma_if = ldq_uop_0_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_debug_if = ldq_uop_0_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_25_bp_xcpt_if = ldq_uop_0_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_fsrc = ldq_uop_0_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_25_debug_tsrc = ldq_uop_0_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_inst = ldq_uop_1_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_1_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_1_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_26_debug_inst = ldq_uop_1_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rvc; // @[lsu.scala:219:36] wire l_uop_1_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rvc = ldq_uop_1_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_1_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_1_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_26_debug_pc = ldq_uop_1_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_0; // @[lsu.scala:219:36] wire l_uop_1_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_0 = ldq_uop_1_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_1; // @[lsu.scala:219:36] wire l_uop_1_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_1 = ldq_uop_1_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_2; // @[lsu.scala:219:36] wire l_uop_1_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_2 = ldq_uop_1_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iq_type_3; // @[lsu.scala:219:36] wire l_uop_1_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_iq_type_3 = ldq_uop_1_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_0; // @[lsu.scala:219:36] wire l_uop_1_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_0 = ldq_uop_1_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_1; // @[lsu.scala:219:36] wire l_uop_1_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_1 = ldq_uop_1_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_2; // @[lsu.scala:219:36] wire l_uop_1_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_2 = ldq_uop_1_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_3; // @[lsu.scala:219:36] wire l_uop_1_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_3 = ldq_uop_1_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_4; // @[lsu.scala:219:36] wire l_uop_1_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_4 = ldq_uop_1_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_5; // @[lsu.scala:219:36] wire l_uop_1_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_5 = ldq_uop_1_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_6; // @[lsu.scala:219:36] wire l_uop_1_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_6 = ldq_uop_1_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_7; // @[lsu.scala:219:36] wire l_uop_1_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_7 = ldq_uop_1_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_8; // @[lsu.scala:219:36] wire l_uop_1_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_8 = ldq_uop_1_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fu_code_9; // @[lsu.scala:219:36] wire l_uop_1_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_26_fu_code_9 = ldq_uop_1_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued; // @[lsu.scala:219:36] wire l_uop_1_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued = ldq_uop_1_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_agen = ldq_uop_1_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_1_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_issued_partial_dgen = ldq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_1_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_iw_p1_speculative_child = ldq_uop_1_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_1_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_iw_p2_speculative_child = ldq_uop_1_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p1_bypass_hint = ldq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p2_bypass_hint = ldq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_1_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_26_iw_p3_bypass_hint = ldq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_dis_col_sel = ldq_uop_1_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_1_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_1_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_26_br_mask = ldq_uop_1_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_tag = ldq_uop_1_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_1_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_1_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_26_br_type = ldq_uop_1_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfb; // @[lsu.scala:219:36] wire l_uop_1_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfb = ldq_uop_1_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fence; // @[lsu.scala:219:36] wire l_uop_1_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fence = ldq_uop_1_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_fencei; // @[lsu.scala:219:36] wire l_uop_1_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_fencei = ldq_uop_1_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sfence; // @[lsu.scala:219:36] wire l_uop_1_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sfence = ldq_uop_1_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_amo; // @[lsu.scala:219:36] wire l_uop_1_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_amo = ldq_uop_1_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_eret; // @[lsu.scala:219:36] wire l_uop_1_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_eret = ldq_uop_1_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_1_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_sys_pc2epc = ldq_uop_1_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_rocc; // @[lsu.scala:219:36] wire l_uop_1_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_rocc = ldq_uop_1_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_mov; // @[lsu.scala:219:36] wire l_uop_1_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_mov = ldq_uop_1_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ftq_idx = ldq_uop_1_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_edge_inst; // @[lsu.scala:219:36] wire l_uop_1_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_26_edge_inst = ldq_uop_1_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_1_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_pc_lob = ldq_uop_1_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_taken; // @[lsu.scala:219:36] wire l_uop_1_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1191:37] wire uop_26_taken = ldq_uop_1_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_imm_rename; // @[lsu.scala:219:36] wire l_uop_1_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_26_imm_rename = ldq_uop_1_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_imm_sel = ldq_uop_1_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_1_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_pimm = ldq_uop_1_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_1_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_1_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_26_imm_packed = ldq_uop_1_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_1_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_op1_sel = ldq_uop_1_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_1_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_op2_sel = ldq_uop_1_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ldst = ldq_uop_1_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wen = ldq_uop_1_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren1 = ldq_uop_1_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren2 = ldq_uop_1_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_ren3 = ldq_uop_1_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap12 = ldq_uop_1_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_swap23 = ldq_uop_1_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagIn = ldq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_ctrl_typeTagOut = ldq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fromint = ldq_uop_1_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_toint = ldq_uop_1_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fastpipe = ldq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_fma = ldq_uop_1_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_div = ldq_uop_1_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_sqrt = ldq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_wflags = ldq_uop_1_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_1_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_ctrl_vec = ldq_uop_1_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_1_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_rob_idx = ldq_uop_1_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ldq_idx = ldq_uop_1_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_1_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_stq_idx = ldq_uop_1_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_1_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_rxq_idx = ldq_uop_1_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_pdst = ldq_uop_1_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs1 = ldq_uop_1_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs2 = ldq_uop_1_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_1_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_prs3 = ldq_uop_1_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_1_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_ppred = ldq_uop_1_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs1_busy; // @[lsu.scala:219:36] wire l_uop_1_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs1_busy = ldq_uop_1_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs2_busy; // @[lsu.scala:219:36] wire l_uop_1_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs2_busy = ldq_uop_1_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_prs3_busy; // @[lsu.scala:219:36] wire l_uop_1_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_prs3_busy = ldq_uop_1_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ppred_busy; // @[lsu.scala:219:36] wire l_uop_1_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_26_ppred_busy = ldq_uop_1_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_1_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_1_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_26_stale_pdst = ldq_uop_1_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_exception; // @[lsu.scala:219:36] wire l_uop_1_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1191:37] wire uop_26_exception = ldq_uop_1_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_1_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_1_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_26_exc_cause = ldq_uop_1_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_1_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_mem_cmd = ldq_uop_1_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_1_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_mem_size = ldq_uop_1_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_mem_signed; // @[lsu.scala:219:36] wire l_uop_1_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_26_mem_signed = ldq_uop_1_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_ldq; // @[lsu.scala:219:36] wire l_uop_1_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_ldq = ldq_uop_1_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_uses_stq; // @[lsu.scala:219:36] wire l_uop_1_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_26_uses_stq = ldq_uop_1_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_is_unique; // @[lsu.scala:219:36] wire l_uop_1_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_26_is_unique = ldq_uop_1_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_1_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_26_flush_on_commit = ldq_uop_1_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_1_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_csr_cmd = ldq_uop_1_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_1_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_26_ldst_is_rs1 = ldq_uop_1_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_1_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_ldst = ldq_uop_1_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs1 = ldq_uop_1_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs2 = ldq_uop_1_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_1_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_1_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_26_lrs3 = ldq_uop_1_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_dst_rtype = ldq_uop_1_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs1_rtype = ldq_uop_1_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_1_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_lrs2_rtype = ldq_uop_1_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_frs3_en; // @[lsu.scala:219:36] wire l_uop_1_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_26_frs3_en = ldq_uop_1_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fcn_dw; // @[lsu.scala:219:36] wire l_uop_1_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_26_fcn_dw = ldq_uop_1_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_1_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_1_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_26_fcn_op = ldq_uop_1_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_fp_val; // @[lsu.scala:219:36] wire l_uop_1_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_26_fp_val = ldq_uop_1_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_1_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_fp_rm = ldq_uop_1_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_1_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_1_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_26_fp_typ = ldq_uop_1_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_pf_if = ldq_uop_1_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ae_if = ldq_uop_1_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_1_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_xcpt_ma_if = ldq_uop_1_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_1_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_debug_if = ldq_uop_1_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_1_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_26_bp_xcpt_if = ldq_uop_1_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_fsrc = ldq_uop_1_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_1_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_26_debug_tsrc = ldq_uop_1_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_inst = ldq_uop_2_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_2_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_2_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_27_debug_inst = ldq_uop_2_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rvc; // @[lsu.scala:219:36] wire l_uop_2_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rvc = ldq_uop_2_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_2_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_2_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_27_debug_pc = ldq_uop_2_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_0; // @[lsu.scala:219:36] wire l_uop_2_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_0 = ldq_uop_2_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_1; // @[lsu.scala:219:36] wire l_uop_2_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_1 = ldq_uop_2_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_2; // @[lsu.scala:219:36] wire l_uop_2_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_2 = ldq_uop_2_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iq_type_3; // @[lsu.scala:219:36] wire l_uop_2_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_iq_type_3 = ldq_uop_2_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_0; // @[lsu.scala:219:36] wire l_uop_2_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_0 = ldq_uop_2_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_1; // @[lsu.scala:219:36] wire l_uop_2_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_1 = ldq_uop_2_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_2; // @[lsu.scala:219:36] wire l_uop_2_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_2 = ldq_uop_2_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_3; // @[lsu.scala:219:36] wire l_uop_2_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_3 = ldq_uop_2_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_4; // @[lsu.scala:219:36] wire l_uop_2_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_4 = ldq_uop_2_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_5; // @[lsu.scala:219:36] wire l_uop_2_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_5 = ldq_uop_2_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_6; // @[lsu.scala:219:36] wire l_uop_2_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_6 = ldq_uop_2_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_7; // @[lsu.scala:219:36] wire l_uop_2_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_7 = ldq_uop_2_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_8; // @[lsu.scala:219:36] wire l_uop_2_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_8 = ldq_uop_2_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fu_code_9; // @[lsu.scala:219:36] wire l_uop_2_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_27_fu_code_9 = ldq_uop_2_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued; // @[lsu.scala:219:36] wire l_uop_2_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued = ldq_uop_2_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_agen = ldq_uop_2_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_2_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_issued_partial_dgen = ldq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_2_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_iw_p1_speculative_child = ldq_uop_2_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_2_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_iw_p2_speculative_child = ldq_uop_2_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p1_bypass_hint = ldq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p2_bypass_hint = ldq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_2_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_27_iw_p3_bypass_hint = ldq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_dis_col_sel = ldq_uop_2_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_2_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_2_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_27_br_mask = ldq_uop_2_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_tag = ldq_uop_2_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_2_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_2_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_27_br_type = ldq_uop_2_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfb; // @[lsu.scala:219:36] wire l_uop_2_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfb = ldq_uop_2_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fence; // @[lsu.scala:219:36] wire l_uop_2_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fence = ldq_uop_2_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_fencei; // @[lsu.scala:219:36] wire l_uop_2_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_fencei = ldq_uop_2_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sfence; // @[lsu.scala:219:36] wire l_uop_2_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sfence = ldq_uop_2_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_amo; // @[lsu.scala:219:36] wire l_uop_2_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_amo = ldq_uop_2_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_eret; // @[lsu.scala:219:36] wire l_uop_2_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_eret = ldq_uop_2_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_2_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_sys_pc2epc = ldq_uop_2_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_rocc; // @[lsu.scala:219:36] wire l_uop_2_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_rocc = ldq_uop_2_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_mov; // @[lsu.scala:219:36] wire l_uop_2_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_mov = ldq_uop_2_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ftq_idx = ldq_uop_2_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_edge_inst; // @[lsu.scala:219:36] wire l_uop_2_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_27_edge_inst = ldq_uop_2_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_2_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_pc_lob = ldq_uop_2_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_taken; // @[lsu.scala:219:36] wire l_uop_2_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1191:37] wire uop_27_taken = ldq_uop_2_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_imm_rename; // @[lsu.scala:219:36] wire l_uop_2_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_27_imm_rename = ldq_uop_2_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_imm_sel = ldq_uop_2_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_2_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_pimm = ldq_uop_2_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_2_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_2_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_27_imm_packed = ldq_uop_2_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_2_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_op1_sel = ldq_uop_2_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_2_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_op2_sel = ldq_uop_2_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ldst = ldq_uop_2_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wen = ldq_uop_2_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren1 = ldq_uop_2_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren2 = ldq_uop_2_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_ren3 = ldq_uop_2_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap12 = ldq_uop_2_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_swap23 = ldq_uop_2_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagIn = ldq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_ctrl_typeTagOut = ldq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fromint = ldq_uop_2_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_toint = ldq_uop_2_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fastpipe = ldq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_fma = ldq_uop_2_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_div = ldq_uop_2_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_sqrt = ldq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_wflags = ldq_uop_2_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_2_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_ctrl_vec = ldq_uop_2_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_2_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_rob_idx = ldq_uop_2_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ldq_idx = ldq_uop_2_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_2_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_stq_idx = ldq_uop_2_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_2_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_rxq_idx = ldq_uop_2_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_pdst = ldq_uop_2_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs1 = ldq_uop_2_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs2 = ldq_uop_2_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_2_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_prs3 = ldq_uop_2_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_2_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_ppred = ldq_uop_2_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs1_busy; // @[lsu.scala:219:36] wire l_uop_2_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs1_busy = ldq_uop_2_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs2_busy; // @[lsu.scala:219:36] wire l_uop_2_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs2_busy = ldq_uop_2_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_prs3_busy; // @[lsu.scala:219:36] wire l_uop_2_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_prs3_busy = ldq_uop_2_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ppred_busy; // @[lsu.scala:219:36] wire l_uop_2_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_27_ppred_busy = ldq_uop_2_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_2_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_2_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_27_stale_pdst = ldq_uop_2_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_exception; // @[lsu.scala:219:36] wire l_uop_2_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1191:37] wire uop_27_exception = ldq_uop_2_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_2_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_2_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_27_exc_cause = ldq_uop_2_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_2_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_mem_cmd = ldq_uop_2_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_2_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_mem_size = ldq_uop_2_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_mem_signed; // @[lsu.scala:219:36] wire l_uop_2_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_27_mem_signed = ldq_uop_2_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_ldq; // @[lsu.scala:219:36] wire l_uop_2_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_ldq = ldq_uop_2_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_uses_stq; // @[lsu.scala:219:36] wire l_uop_2_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_27_uses_stq = ldq_uop_2_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_is_unique; // @[lsu.scala:219:36] wire l_uop_2_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_27_is_unique = ldq_uop_2_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_2_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_27_flush_on_commit = ldq_uop_2_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_2_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_csr_cmd = ldq_uop_2_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_2_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_27_ldst_is_rs1 = ldq_uop_2_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_2_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_ldst = ldq_uop_2_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs1 = ldq_uop_2_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs2 = ldq_uop_2_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_2_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_2_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_27_lrs3 = ldq_uop_2_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_dst_rtype = ldq_uop_2_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs1_rtype = ldq_uop_2_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_2_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_lrs2_rtype = ldq_uop_2_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_frs3_en; // @[lsu.scala:219:36] wire l_uop_2_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_27_frs3_en = ldq_uop_2_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fcn_dw; // @[lsu.scala:219:36] wire l_uop_2_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_27_fcn_dw = ldq_uop_2_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_2_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_2_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_27_fcn_op = ldq_uop_2_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_fp_val; // @[lsu.scala:219:36] wire l_uop_2_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_27_fp_val = ldq_uop_2_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_2_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_fp_rm = ldq_uop_2_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_2_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_2_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_27_fp_typ = ldq_uop_2_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_pf_if = ldq_uop_2_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ae_if = ldq_uop_2_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_2_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_xcpt_ma_if = ldq_uop_2_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_2_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_debug_if = ldq_uop_2_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_2_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_27_bp_xcpt_if = ldq_uop_2_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_fsrc = ldq_uop_2_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_2_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_27_debug_tsrc = ldq_uop_2_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_inst = ldq_uop_3_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_3_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_3_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_28_debug_inst = ldq_uop_3_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rvc; // @[lsu.scala:219:36] wire l_uop_3_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rvc = ldq_uop_3_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_3_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_3_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_28_debug_pc = ldq_uop_3_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_0; // @[lsu.scala:219:36] wire l_uop_3_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_0 = ldq_uop_3_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_1; // @[lsu.scala:219:36] wire l_uop_3_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_1 = ldq_uop_3_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_2; // @[lsu.scala:219:36] wire l_uop_3_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_2 = ldq_uop_3_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iq_type_3; // @[lsu.scala:219:36] wire l_uop_3_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_iq_type_3 = ldq_uop_3_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_0; // @[lsu.scala:219:36] wire l_uop_3_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_0 = ldq_uop_3_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_1; // @[lsu.scala:219:36] wire l_uop_3_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_1 = ldq_uop_3_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_2; // @[lsu.scala:219:36] wire l_uop_3_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_2 = ldq_uop_3_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_3; // @[lsu.scala:219:36] wire l_uop_3_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_3 = ldq_uop_3_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_4; // @[lsu.scala:219:36] wire l_uop_3_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_4 = ldq_uop_3_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_5; // @[lsu.scala:219:36] wire l_uop_3_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_5 = ldq_uop_3_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_6; // @[lsu.scala:219:36] wire l_uop_3_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_6 = ldq_uop_3_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_7; // @[lsu.scala:219:36] wire l_uop_3_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_7 = ldq_uop_3_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_8; // @[lsu.scala:219:36] wire l_uop_3_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_8 = ldq_uop_3_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fu_code_9; // @[lsu.scala:219:36] wire l_uop_3_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_28_fu_code_9 = ldq_uop_3_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued; // @[lsu.scala:219:36] wire l_uop_3_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued = ldq_uop_3_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_agen = ldq_uop_3_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_3_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_issued_partial_dgen = ldq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_3_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_iw_p1_speculative_child = ldq_uop_3_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_3_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_iw_p2_speculative_child = ldq_uop_3_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p1_bypass_hint = ldq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p2_bypass_hint = ldq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_3_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_28_iw_p3_bypass_hint = ldq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_dis_col_sel = ldq_uop_3_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_3_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_3_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_28_br_mask = ldq_uop_3_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_tag = ldq_uop_3_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_3_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_3_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_28_br_type = ldq_uop_3_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfb; // @[lsu.scala:219:36] wire l_uop_3_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfb = ldq_uop_3_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fence; // @[lsu.scala:219:36] wire l_uop_3_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fence = ldq_uop_3_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_fencei; // @[lsu.scala:219:36] wire l_uop_3_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_fencei = ldq_uop_3_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sfence; // @[lsu.scala:219:36] wire l_uop_3_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sfence = ldq_uop_3_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_amo; // @[lsu.scala:219:36] wire l_uop_3_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_amo = ldq_uop_3_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_eret; // @[lsu.scala:219:36] wire l_uop_3_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_eret = ldq_uop_3_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_3_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_sys_pc2epc = ldq_uop_3_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_rocc; // @[lsu.scala:219:36] wire l_uop_3_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_rocc = ldq_uop_3_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_mov; // @[lsu.scala:219:36] wire l_uop_3_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_mov = ldq_uop_3_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ftq_idx = ldq_uop_3_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_edge_inst; // @[lsu.scala:219:36] wire l_uop_3_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_28_edge_inst = ldq_uop_3_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_3_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_pc_lob = ldq_uop_3_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_taken; // @[lsu.scala:219:36] wire l_uop_3_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1191:37] wire uop_28_taken = ldq_uop_3_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_imm_rename; // @[lsu.scala:219:36] wire l_uop_3_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_28_imm_rename = ldq_uop_3_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_imm_sel = ldq_uop_3_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_3_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_pimm = ldq_uop_3_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_3_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_3_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_28_imm_packed = ldq_uop_3_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_3_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_op1_sel = ldq_uop_3_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_3_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_op2_sel = ldq_uop_3_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ldst = ldq_uop_3_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wen = ldq_uop_3_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren1 = ldq_uop_3_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren2 = ldq_uop_3_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_ren3 = ldq_uop_3_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap12 = ldq_uop_3_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_swap23 = ldq_uop_3_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagIn = ldq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_ctrl_typeTagOut = ldq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fromint = ldq_uop_3_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_toint = ldq_uop_3_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fastpipe = ldq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_fma = ldq_uop_3_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_div = ldq_uop_3_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_sqrt = ldq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_wflags = ldq_uop_3_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_3_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_ctrl_vec = ldq_uop_3_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_3_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_rob_idx = ldq_uop_3_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ldq_idx = ldq_uop_3_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_3_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_stq_idx = ldq_uop_3_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_3_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_rxq_idx = ldq_uop_3_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_pdst = ldq_uop_3_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs1 = ldq_uop_3_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs2 = ldq_uop_3_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_3_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_prs3 = ldq_uop_3_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_3_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_ppred = ldq_uop_3_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs1_busy; // @[lsu.scala:219:36] wire l_uop_3_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs1_busy = ldq_uop_3_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs2_busy; // @[lsu.scala:219:36] wire l_uop_3_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs2_busy = ldq_uop_3_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_prs3_busy; // @[lsu.scala:219:36] wire l_uop_3_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_prs3_busy = ldq_uop_3_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ppred_busy; // @[lsu.scala:219:36] wire l_uop_3_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_28_ppred_busy = ldq_uop_3_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_3_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_3_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_28_stale_pdst = ldq_uop_3_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_exception; // @[lsu.scala:219:36] wire l_uop_3_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1191:37] wire uop_28_exception = ldq_uop_3_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_3_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_3_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_28_exc_cause = ldq_uop_3_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_3_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_mem_cmd = ldq_uop_3_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_3_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_mem_size = ldq_uop_3_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_mem_signed; // @[lsu.scala:219:36] wire l_uop_3_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_28_mem_signed = ldq_uop_3_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_ldq; // @[lsu.scala:219:36] wire l_uop_3_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_ldq = ldq_uop_3_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_uses_stq; // @[lsu.scala:219:36] wire l_uop_3_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_28_uses_stq = ldq_uop_3_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_is_unique; // @[lsu.scala:219:36] wire l_uop_3_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_28_is_unique = ldq_uop_3_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_3_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_28_flush_on_commit = ldq_uop_3_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_3_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_csr_cmd = ldq_uop_3_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_3_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_28_ldst_is_rs1 = ldq_uop_3_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_3_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_ldst = ldq_uop_3_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs1 = ldq_uop_3_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs2 = ldq_uop_3_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_3_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_3_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_28_lrs3 = ldq_uop_3_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_dst_rtype = ldq_uop_3_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs1_rtype = ldq_uop_3_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_3_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_lrs2_rtype = ldq_uop_3_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_frs3_en; // @[lsu.scala:219:36] wire l_uop_3_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_28_frs3_en = ldq_uop_3_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fcn_dw; // @[lsu.scala:219:36] wire l_uop_3_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_28_fcn_dw = ldq_uop_3_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_3_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_3_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_28_fcn_op = ldq_uop_3_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_fp_val; // @[lsu.scala:219:36] wire l_uop_3_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_28_fp_val = ldq_uop_3_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_3_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_fp_rm = ldq_uop_3_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_3_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_3_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_28_fp_typ = ldq_uop_3_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_pf_if = ldq_uop_3_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ae_if = ldq_uop_3_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_3_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_xcpt_ma_if = ldq_uop_3_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_3_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_debug_if = ldq_uop_3_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_3_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_28_bp_xcpt_if = ldq_uop_3_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_fsrc = ldq_uop_3_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_3_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_28_debug_tsrc = ldq_uop_3_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_inst = ldq_uop_4_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_4_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_4_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_29_debug_inst = ldq_uop_4_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rvc; // @[lsu.scala:219:36] wire l_uop_4_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rvc = ldq_uop_4_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_4_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_4_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_29_debug_pc = ldq_uop_4_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_0; // @[lsu.scala:219:36] wire l_uop_4_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_0 = ldq_uop_4_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_1; // @[lsu.scala:219:36] wire l_uop_4_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_1 = ldq_uop_4_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_2; // @[lsu.scala:219:36] wire l_uop_4_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_2 = ldq_uop_4_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iq_type_3; // @[lsu.scala:219:36] wire l_uop_4_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_iq_type_3 = ldq_uop_4_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_0; // @[lsu.scala:219:36] wire l_uop_4_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_0 = ldq_uop_4_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_1; // @[lsu.scala:219:36] wire l_uop_4_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_1 = ldq_uop_4_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_2; // @[lsu.scala:219:36] wire l_uop_4_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_2 = ldq_uop_4_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_3; // @[lsu.scala:219:36] wire l_uop_4_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_3 = ldq_uop_4_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_4; // @[lsu.scala:219:36] wire l_uop_4_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_4 = ldq_uop_4_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_5; // @[lsu.scala:219:36] wire l_uop_4_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_5 = ldq_uop_4_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_6; // @[lsu.scala:219:36] wire l_uop_4_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_6 = ldq_uop_4_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_7; // @[lsu.scala:219:36] wire l_uop_4_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_7 = ldq_uop_4_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_8; // @[lsu.scala:219:36] wire l_uop_4_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_8 = ldq_uop_4_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fu_code_9; // @[lsu.scala:219:36] wire l_uop_4_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_29_fu_code_9 = ldq_uop_4_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued; // @[lsu.scala:219:36] wire l_uop_4_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued = ldq_uop_4_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_agen = ldq_uop_4_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_4_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_issued_partial_dgen = ldq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_4_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_iw_p1_speculative_child = ldq_uop_4_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_4_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_iw_p2_speculative_child = ldq_uop_4_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p1_bypass_hint = ldq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p2_bypass_hint = ldq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_4_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_29_iw_p3_bypass_hint = ldq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_dis_col_sel = ldq_uop_4_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_4_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_4_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_29_br_mask = ldq_uop_4_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_tag = ldq_uop_4_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_4_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_4_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_29_br_type = ldq_uop_4_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfb; // @[lsu.scala:219:36] wire l_uop_4_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfb = ldq_uop_4_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fence; // @[lsu.scala:219:36] wire l_uop_4_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fence = ldq_uop_4_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_fencei; // @[lsu.scala:219:36] wire l_uop_4_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_fencei = ldq_uop_4_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sfence; // @[lsu.scala:219:36] wire l_uop_4_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sfence = ldq_uop_4_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_amo; // @[lsu.scala:219:36] wire l_uop_4_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_amo = ldq_uop_4_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_eret; // @[lsu.scala:219:36] wire l_uop_4_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_eret = ldq_uop_4_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_4_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_sys_pc2epc = ldq_uop_4_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_rocc; // @[lsu.scala:219:36] wire l_uop_4_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_rocc = ldq_uop_4_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_mov; // @[lsu.scala:219:36] wire l_uop_4_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_mov = ldq_uop_4_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ftq_idx = ldq_uop_4_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_edge_inst; // @[lsu.scala:219:36] wire l_uop_4_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_29_edge_inst = ldq_uop_4_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_4_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_pc_lob = ldq_uop_4_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_taken; // @[lsu.scala:219:36] wire l_uop_4_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1191:37] wire uop_29_taken = ldq_uop_4_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_imm_rename; // @[lsu.scala:219:36] wire l_uop_4_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_29_imm_rename = ldq_uop_4_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_imm_sel = ldq_uop_4_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_4_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_pimm = ldq_uop_4_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_4_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_4_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_29_imm_packed = ldq_uop_4_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_4_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_op1_sel = ldq_uop_4_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_4_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_op2_sel = ldq_uop_4_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ldst = ldq_uop_4_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wen = ldq_uop_4_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren1 = ldq_uop_4_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren2 = ldq_uop_4_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_ren3 = ldq_uop_4_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap12 = ldq_uop_4_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_swap23 = ldq_uop_4_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagIn = ldq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_ctrl_typeTagOut = ldq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fromint = ldq_uop_4_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_toint = ldq_uop_4_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fastpipe = ldq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_fma = ldq_uop_4_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_div = ldq_uop_4_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_sqrt = ldq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_wflags = ldq_uop_4_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_4_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_ctrl_vec = ldq_uop_4_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_4_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_rob_idx = ldq_uop_4_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ldq_idx = ldq_uop_4_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_4_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_stq_idx = ldq_uop_4_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_4_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_rxq_idx = ldq_uop_4_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_pdst = ldq_uop_4_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs1 = ldq_uop_4_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs2 = ldq_uop_4_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_4_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_prs3 = ldq_uop_4_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_4_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_ppred = ldq_uop_4_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs1_busy; // @[lsu.scala:219:36] wire l_uop_4_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs1_busy = ldq_uop_4_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs2_busy; // @[lsu.scala:219:36] wire l_uop_4_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs2_busy = ldq_uop_4_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_prs3_busy; // @[lsu.scala:219:36] wire l_uop_4_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_prs3_busy = ldq_uop_4_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ppred_busy; // @[lsu.scala:219:36] wire l_uop_4_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_29_ppred_busy = ldq_uop_4_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_4_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_4_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_29_stale_pdst = ldq_uop_4_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_exception; // @[lsu.scala:219:36] wire l_uop_4_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1191:37] wire uop_29_exception = ldq_uop_4_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_4_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_4_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_29_exc_cause = ldq_uop_4_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_4_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_mem_cmd = ldq_uop_4_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_4_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_mem_size = ldq_uop_4_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_mem_signed; // @[lsu.scala:219:36] wire l_uop_4_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_29_mem_signed = ldq_uop_4_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_ldq; // @[lsu.scala:219:36] wire l_uop_4_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_ldq = ldq_uop_4_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_uses_stq; // @[lsu.scala:219:36] wire l_uop_4_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_29_uses_stq = ldq_uop_4_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_is_unique; // @[lsu.scala:219:36] wire l_uop_4_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_29_is_unique = ldq_uop_4_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_4_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_29_flush_on_commit = ldq_uop_4_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_4_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_csr_cmd = ldq_uop_4_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_4_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_29_ldst_is_rs1 = ldq_uop_4_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_4_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_ldst = ldq_uop_4_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs1 = ldq_uop_4_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs2 = ldq_uop_4_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_4_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_4_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_29_lrs3 = ldq_uop_4_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_dst_rtype = ldq_uop_4_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs1_rtype = ldq_uop_4_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_4_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_lrs2_rtype = ldq_uop_4_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_frs3_en; // @[lsu.scala:219:36] wire l_uop_4_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_29_frs3_en = ldq_uop_4_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fcn_dw; // @[lsu.scala:219:36] wire l_uop_4_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_29_fcn_dw = ldq_uop_4_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_4_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_4_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_29_fcn_op = ldq_uop_4_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_fp_val; // @[lsu.scala:219:36] wire l_uop_4_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_29_fp_val = ldq_uop_4_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_4_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_fp_rm = ldq_uop_4_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_4_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_4_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_29_fp_typ = ldq_uop_4_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_pf_if = ldq_uop_4_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ae_if = ldq_uop_4_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_4_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_xcpt_ma_if = ldq_uop_4_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_4_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_debug_if = ldq_uop_4_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_4_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_29_bp_xcpt_if = ldq_uop_4_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_fsrc = ldq_uop_4_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_4_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_29_debug_tsrc = ldq_uop_4_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_inst = ldq_uop_5_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_5_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_5_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_30_debug_inst = ldq_uop_5_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rvc; // @[lsu.scala:219:36] wire l_uop_5_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rvc = ldq_uop_5_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_5_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_5_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_30_debug_pc = ldq_uop_5_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_0; // @[lsu.scala:219:36] wire l_uop_5_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_0 = ldq_uop_5_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_1; // @[lsu.scala:219:36] wire l_uop_5_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_1 = ldq_uop_5_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_2; // @[lsu.scala:219:36] wire l_uop_5_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_2 = ldq_uop_5_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iq_type_3; // @[lsu.scala:219:36] wire l_uop_5_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_iq_type_3 = ldq_uop_5_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_0; // @[lsu.scala:219:36] wire l_uop_5_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_0 = ldq_uop_5_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_1; // @[lsu.scala:219:36] wire l_uop_5_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_1 = ldq_uop_5_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_2; // @[lsu.scala:219:36] wire l_uop_5_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_2 = ldq_uop_5_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_3; // @[lsu.scala:219:36] wire l_uop_5_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_3 = ldq_uop_5_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_4; // @[lsu.scala:219:36] wire l_uop_5_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_4 = ldq_uop_5_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_5; // @[lsu.scala:219:36] wire l_uop_5_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_5 = ldq_uop_5_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_6; // @[lsu.scala:219:36] wire l_uop_5_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_6 = ldq_uop_5_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_7; // @[lsu.scala:219:36] wire l_uop_5_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_7 = ldq_uop_5_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_8; // @[lsu.scala:219:36] wire l_uop_5_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_8 = ldq_uop_5_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fu_code_9; // @[lsu.scala:219:36] wire l_uop_5_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_30_fu_code_9 = ldq_uop_5_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued; // @[lsu.scala:219:36] wire l_uop_5_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued = ldq_uop_5_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_agen = ldq_uop_5_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_5_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_issued_partial_dgen = ldq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_5_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_iw_p1_speculative_child = ldq_uop_5_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_5_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_iw_p2_speculative_child = ldq_uop_5_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p1_bypass_hint = ldq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p2_bypass_hint = ldq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_5_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_30_iw_p3_bypass_hint = ldq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_dis_col_sel = ldq_uop_5_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_5_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_5_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_30_br_mask = ldq_uop_5_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_tag = ldq_uop_5_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_5_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_5_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_30_br_type = ldq_uop_5_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfb; // @[lsu.scala:219:36] wire l_uop_5_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfb = ldq_uop_5_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fence; // @[lsu.scala:219:36] wire l_uop_5_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fence = ldq_uop_5_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_fencei; // @[lsu.scala:219:36] wire l_uop_5_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_fencei = ldq_uop_5_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sfence; // @[lsu.scala:219:36] wire l_uop_5_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sfence = ldq_uop_5_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_amo; // @[lsu.scala:219:36] wire l_uop_5_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_amo = ldq_uop_5_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_eret; // @[lsu.scala:219:36] wire l_uop_5_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_eret = ldq_uop_5_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_5_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_sys_pc2epc = ldq_uop_5_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_rocc; // @[lsu.scala:219:36] wire l_uop_5_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_rocc = ldq_uop_5_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_mov; // @[lsu.scala:219:36] wire l_uop_5_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_mov = ldq_uop_5_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ftq_idx = ldq_uop_5_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_edge_inst; // @[lsu.scala:219:36] wire l_uop_5_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_30_edge_inst = ldq_uop_5_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_5_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_pc_lob = ldq_uop_5_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_taken; // @[lsu.scala:219:36] wire l_uop_5_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1191:37] wire uop_30_taken = ldq_uop_5_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_imm_rename; // @[lsu.scala:219:36] wire l_uop_5_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_30_imm_rename = ldq_uop_5_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_imm_sel = ldq_uop_5_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_5_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_pimm = ldq_uop_5_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_5_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_5_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_30_imm_packed = ldq_uop_5_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_5_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_op1_sel = ldq_uop_5_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_5_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_op2_sel = ldq_uop_5_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ldst = ldq_uop_5_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wen = ldq_uop_5_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren1 = ldq_uop_5_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren2 = ldq_uop_5_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_ren3 = ldq_uop_5_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap12 = ldq_uop_5_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_swap23 = ldq_uop_5_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagIn = ldq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_ctrl_typeTagOut = ldq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fromint = ldq_uop_5_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_toint = ldq_uop_5_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fastpipe = ldq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_fma = ldq_uop_5_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_div = ldq_uop_5_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_sqrt = ldq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_wflags = ldq_uop_5_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_5_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_ctrl_vec = ldq_uop_5_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_5_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_rob_idx = ldq_uop_5_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ldq_idx = ldq_uop_5_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_5_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_stq_idx = ldq_uop_5_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_5_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_rxq_idx = ldq_uop_5_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_pdst = ldq_uop_5_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs1 = ldq_uop_5_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs2 = ldq_uop_5_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_5_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_prs3 = ldq_uop_5_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_5_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_ppred = ldq_uop_5_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs1_busy; // @[lsu.scala:219:36] wire l_uop_5_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs1_busy = ldq_uop_5_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs2_busy; // @[lsu.scala:219:36] wire l_uop_5_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs2_busy = ldq_uop_5_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_prs3_busy; // @[lsu.scala:219:36] wire l_uop_5_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_prs3_busy = ldq_uop_5_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ppred_busy; // @[lsu.scala:219:36] wire l_uop_5_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_30_ppred_busy = ldq_uop_5_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_5_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_5_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_30_stale_pdst = ldq_uop_5_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_exception; // @[lsu.scala:219:36] wire l_uop_5_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1191:37] wire uop_30_exception = ldq_uop_5_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_5_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_5_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_30_exc_cause = ldq_uop_5_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_5_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_mem_cmd = ldq_uop_5_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_5_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_mem_size = ldq_uop_5_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_mem_signed; // @[lsu.scala:219:36] wire l_uop_5_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_30_mem_signed = ldq_uop_5_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_ldq; // @[lsu.scala:219:36] wire l_uop_5_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_ldq = ldq_uop_5_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_uses_stq; // @[lsu.scala:219:36] wire l_uop_5_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_30_uses_stq = ldq_uop_5_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_is_unique; // @[lsu.scala:219:36] wire l_uop_5_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_30_is_unique = ldq_uop_5_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_5_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_30_flush_on_commit = ldq_uop_5_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_5_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_csr_cmd = ldq_uop_5_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_5_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_30_ldst_is_rs1 = ldq_uop_5_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_5_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_ldst = ldq_uop_5_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs1 = ldq_uop_5_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs2 = ldq_uop_5_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_5_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_5_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_30_lrs3 = ldq_uop_5_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_dst_rtype = ldq_uop_5_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs1_rtype = ldq_uop_5_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_5_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_lrs2_rtype = ldq_uop_5_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_frs3_en; // @[lsu.scala:219:36] wire l_uop_5_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_30_frs3_en = ldq_uop_5_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fcn_dw; // @[lsu.scala:219:36] wire l_uop_5_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_30_fcn_dw = ldq_uop_5_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_5_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_5_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_30_fcn_op = ldq_uop_5_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_fp_val; // @[lsu.scala:219:36] wire l_uop_5_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_30_fp_val = ldq_uop_5_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_5_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_fp_rm = ldq_uop_5_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_5_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_5_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_30_fp_typ = ldq_uop_5_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_pf_if = ldq_uop_5_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ae_if = ldq_uop_5_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_5_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_xcpt_ma_if = ldq_uop_5_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_5_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_debug_if = ldq_uop_5_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_5_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_30_bp_xcpt_if = ldq_uop_5_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_fsrc = ldq_uop_5_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_5_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_30_debug_tsrc = ldq_uop_5_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_inst = ldq_uop_6_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_6_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_6_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_31_debug_inst = ldq_uop_6_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rvc; // @[lsu.scala:219:36] wire l_uop_6_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rvc = ldq_uop_6_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_6_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_6_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_31_debug_pc = ldq_uop_6_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_0; // @[lsu.scala:219:36] wire l_uop_6_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_0 = ldq_uop_6_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_1; // @[lsu.scala:219:36] wire l_uop_6_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_1 = ldq_uop_6_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_2; // @[lsu.scala:219:36] wire l_uop_6_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_2 = ldq_uop_6_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iq_type_3; // @[lsu.scala:219:36] wire l_uop_6_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_iq_type_3 = ldq_uop_6_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_0; // @[lsu.scala:219:36] wire l_uop_6_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_0 = ldq_uop_6_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_1; // @[lsu.scala:219:36] wire l_uop_6_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_1 = ldq_uop_6_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_2; // @[lsu.scala:219:36] wire l_uop_6_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_2 = ldq_uop_6_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_3; // @[lsu.scala:219:36] wire l_uop_6_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_3 = ldq_uop_6_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_4; // @[lsu.scala:219:36] wire l_uop_6_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_4 = ldq_uop_6_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_5; // @[lsu.scala:219:36] wire l_uop_6_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_5 = ldq_uop_6_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_6; // @[lsu.scala:219:36] wire l_uop_6_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_6 = ldq_uop_6_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_7; // @[lsu.scala:219:36] wire l_uop_6_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_7 = ldq_uop_6_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_8; // @[lsu.scala:219:36] wire l_uop_6_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_8 = ldq_uop_6_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fu_code_9; // @[lsu.scala:219:36] wire l_uop_6_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_31_fu_code_9 = ldq_uop_6_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued; // @[lsu.scala:219:36] wire l_uop_6_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued = ldq_uop_6_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_agen = ldq_uop_6_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_6_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_issued_partial_dgen = ldq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_6_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_iw_p1_speculative_child = ldq_uop_6_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_6_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_iw_p2_speculative_child = ldq_uop_6_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p1_bypass_hint = ldq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p2_bypass_hint = ldq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_6_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_31_iw_p3_bypass_hint = ldq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_dis_col_sel = ldq_uop_6_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_6_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_6_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_31_br_mask = ldq_uop_6_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_tag = ldq_uop_6_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_6_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_6_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_31_br_type = ldq_uop_6_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfb; // @[lsu.scala:219:36] wire l_uop_6_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfb = ldq_uop_6_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fence; // @[lsu.scala:219:36] wire l_uop_6_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fence = ldq_uop_6_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_fencei; // @[lsu.scala:219:36] wire l_uop_6_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_fencei = ldq_uop_6_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sfence; // @[lsu.scala:219:36] wire l_uop_6_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sfence = ldq_uop_6_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_amo; // @[lsu.scala:219:36] wire l_uop_6_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_amo = ldq_uop_6_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_eret; // @[lsu.scala:219:36] wire l_uop_6_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_eret = ldq_uop_6_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_6_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_sys_pc2epc = ldq_uop_6_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_rocc; // @[lsu.scala:219:36] wire l_uop_6_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_rocc = ldq_uop_6_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_mov; // @[lsu.scala:219:36] wire l_uop_6_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_mov = ldq_uop_6_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ftq_idx = ldq_uop_6_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_edge_inst; // @[lsu.scala:219:36] wire l_uop_6_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_31_edge_inst = ldq_uop_6_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_6_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_pc_lob = ldq_uop_6_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_taken; // @[lsu.scala:219:36] wire l_uop_6_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1191:37] wire uop_31_taken = ldq_uop_6_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_imm_rename; // @[lsu.scala:219:36] wire l_uop_6_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_31_imm_rename = ldq_uop_6_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_imm_sel = ldq_uop_6_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_6_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_pimm = ldq_uop_6_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_6_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_6_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_31_imm_packed = ldq_uop_6_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_6_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_op1_sel = ldq_uop_6_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_6_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_op2_sel = ldq_uop_6_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ldst = ldq_uop_6_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wen = ldq_uop_6_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren1 = ldq_uop_6_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren2 = ldq_uop_6_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_ren3 = ldq_uop_6_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap12 = ldq_uop_6_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_swap23 = ldq_uop_6_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagIn = ldq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_ctrl_typeTagOut = ldq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fromint = ldq_uop_6_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_toint = ldq_uop_6_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fastpipe = ldq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_fma = ldq_uop_6_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_div = ldq_uop_6_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_sqrt = ldq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_wflags = ldq_uop_6_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_6_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_ctrl_vec = ldq_uop_6_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_6_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_rob_idx = ldq_uop_6_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ldq_idx = ldq_uop_6_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_6_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_stq_idx = ldq_uop_6_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_6_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_rxq_idx = ldq_uop_6_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_pdst = ldq_uop_6_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs1 = ldq_uop_6_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs2 = ldq_uop_6_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_6_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_prs3 = ldq_uop_6_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_6_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_ppred = ldq_uop_6_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs1_busy; // @[lsu.scala:219:36] wire l_uop_6_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs1_busy = ldq_uop_6_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs2_busy; // @[lsu.scala:219:36] wire l_uop_6_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs2_busy = ldq_uop_6_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_prs3_busy; // @[lsu.scala:219:36] wire l_uop_6_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_prs3_busy = ldq_uop_6_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ppred_busy; // @[lsu.scala:219:36] wire l_uop_6_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_31_ppred_busy = ldq_uop_6_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_6_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_6_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_31_stale_pdst = ldq_uop_6_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_exception; // @[lsu.scala:219:36] wire l_uop_6_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1191:37] wire uop_31_exception = ldq_uop_6_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_6_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_6_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_31_exc_cause = ldq_uop_6_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_6_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_mem_cmd = ldq_uop_6_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_6_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_mem_size = ldq_uop_6_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_mem_signed; // @[lsu.scala:219:36] wire l_uop_6_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_31_mem_signed = ldq_uop_6_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_ldq; // @[lsu.scala:219:36] wire l_uop_6_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_ldq = ldq_uop_6_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_uses_stq; // @[lsu.scala:219:36] wire l_uop_6_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_31_uses_stq = ldq_uop_6_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_is_unique; // @[lsu.scala:219:36] wire l_uop_6_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_31_is_unique = ldq_uop_6_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_6_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_31_flush_on_commit = ldq_uop_6_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_6_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_csr_cmd = ldq_uop_6_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_6_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_31_ldst_is_rs1 = ldq_uop_6_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_6_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_ldst = ldq_uop_6_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs1 = ldq_uop_6_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs2 = ldq_uop_6_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_6_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_6_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_31_lrs3 = ldq_uop_6_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_dst_rtype = ldq_uop_6_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs1_rtype = ldq_uop_6_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_6_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_lrs2_rtype = ldq_uop_6_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_frs3_en; // @[lsu.scala:219:36] wire l_uop_6_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_31_frs3_en = ldq_uop_6_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fcn_dw; // @[lsu.scala:219:36] wire l_uop_6_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_31_fcn_dw = ldq_uop_6_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_6_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_6_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_31_fcn_op = ldq_uop_6_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_fp_val; // @[lsu.scala:219:36] wire l_uop_6_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_31_fp_val = ldq_uop_6_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_6_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_fp_rm = ldq_uop_6_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_6_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_6_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_31_fp_typ = ldq_uop_6_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_pf_if = ldq_uop_6_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ae_if = ldq_uop_6_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_6_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_xcpt_ma_if = ldq_uop_6_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_6_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_debug_if = ldq_uop_6_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_6_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_31_bp_xcpt_if = ldq_uop_6_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_fsrc = ldq_uop_6_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_6_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_31_debug_tsrc = ldq_uop_6_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_inst = ldq_uop_7_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_7_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_7_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_32_debug_inst = ldq_uop_7_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rvc; // @[lsu.scala:219:36] wire l_uop_7_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rvc = ldq_uop_7_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_7_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_7_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_32_debug_pc = ldq_uop_7_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_0; // @[lsu.scala:219:36] wire l_uop_7_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_0 = ldq_uop_7_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_1; // @[lsu.scala:219:36] wire l_uop_7_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_1 = ldq_uop_7_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_2; // @[lsu.scala:219:36] wire l_uop_7_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_2 = ldq_uop_7_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iq_type_3; // @[lsu.scala:219:36] wire l_uop_7_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_iq_type_3 = ldq_uop_7_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_0; // @[lsu.scala:219:36] wire l_uop_7_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_0 = ldq_uop_7_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_1; // @[lsu.scala:219:36] wire l_uop_7_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_1 = ldq_uop_7_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_2; // @[lsu.scala:219:36] wire l_uop_7_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_2 = ldq_uop_7_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_3; // @[lsu.scala:219:36] wire l_uop_7_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_3 = ldq_uop_7_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_4; // @[lsu.scala:219:36] wire l_uop_7_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_4 = ldq_uop_7_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_5; // @[lsu.scala:219:36] wire l_uop_7_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_5 = ldq_uop_7_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_6; // @[lsu.scala:219:36] wire l_uop_7_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_6 = ldq_uop_7_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_7; // @[lsu.scala:219:36] wire l_uop_7_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_7 = ldq_uop_7_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_8; // @[lsu.scala:219:36] wire l_uop_7_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_8 = ldq_uop_7_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fu_code_9; // @[lsu.scala:219:36] wire l_uop_7_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_32_fu_code_9 = ldq_uop_7_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued; // @[lsu.scala:219:36] wire l_uop_7_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued = ldq_uop_7_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_agen = ldq_uop_7_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_7_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_issued_partial_dgen = ldq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_7_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_iw_p1_speculative_child = ldq_uop_7_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_7_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_iw_p2_speculative_child = ldq_uop_7_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p1_bypass_hint = ldq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p2_bypass_hint = ldq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_7_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_32_iw_p3_bypass_hint = ldq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_dis_col_sel = ldq_uop_7_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_7_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_7_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_32_br_mask = ldq_uop_7_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_tag = ldq_uop_7_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_7_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_7_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_32_br_type = ldq_uop_7_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfb; // @[lsu.scala:219:36] wire l_uop_7_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfb = ldq_uop_7_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fence; // @[lsu.scala:219:36] wire l_uop_7_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fence = ldq_uop_7_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_fencei; // @[lsu.scala:219:36] wire l_uop_7_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_fencei = ldq_uop_7_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sfence; // @[lsu.scala:219:36] wire l_uop_7_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sfence = ldq_uop_7_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_amo; // @[lsu.scala:219:36] wire l_uop_7_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_amo = ldq_uop_7_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_eret; // @[lsu.scala:219:36] wire l_uop_7_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_eret = ldq_uop_7_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_7_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_sys_pc2epc = ldq_uop_7_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_rocc; // @[lsu.scala:219:36] wire l_uop_7_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_rocc = ldq_uop_7_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_mov; // @[lsu.scala:219:36] wire l_uop_7_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_mov = ldq_uop_7_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ftq_idx = ldq_uop_7_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_edge_inst; // @[lsu.scala:219:36] wire l_uop_7_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_32_edge_inst = ldq_uop_7_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_7_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_pc_lob = ldq_uop_7_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_taken; // @[lsu.scala:219:36] wire l_uop_7_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1191:37] wire uop_32_taken = ldq_uop_7_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_imm_rename; // @[lsu.scala:219:36] wire l_uop_7_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_32_imm_rename = ldq_uop_7_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_imm_sel = ldq_uop_7_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_7_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_pimm = ldq_uop_7_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_7_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_7_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_32_imm_packed = ldq_uop_7_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_7_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_op1_sel = ldq_uop_7_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_7_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_op2_sel = ldq_uop_7_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ldst = ldq_uop_7_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wen = ldq_uop_7_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren1 = ldq_uop_7_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren2 = ldq_uop_7_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_ren3 = ldq_uop_7_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap12 = ldq_uop_7_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_swap23 = ldq_uop_7_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagIn = ldq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_ctrl_typeTagOut = ldq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fromint = ldq_uop_7_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_toint = ldq_uop_7_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fastpipe = ldq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_fma = ldq_uop_7_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_div = ldq_uop_7_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_sqrt = ldq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_wflags = ldq_uop_7_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_7_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_ctrl_vec = ldq_uop_7_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_7_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_rob_idx = ldq_uop_7_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ldq_idx = ldq_uop_7_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_7_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_stq_idx = ldq_uop_7_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_7_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_rxq_idx = ldq_uop_7_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_pdst = ldq_uop_7_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs1 = ldq_uop_7_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs2 = ldq_uop_7_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_7_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_prs3 = ldq_uop_7_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_7_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_ppred = ldq_uop_7_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs1_busy; // @[lsu.scala:219:36] wire l_uop_7_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs1_busy = ldq_uop_7_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs2_busy; // @[lsu.scala:219:36] wire l_uop_7_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs2_busy = ldq_uop_7_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_prs3_busy; // @[lsu.scala:219:36] wire l_uop_7_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_prs3_busy = ldq_uop_7_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ppred_busy; // @[lsu.scala:219:36] wire l_uop_7_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_32_ppred_busy = ldq_uop_7_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_7_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_7_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_32_stale_pdst = ldq_uop_7_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_exception; // @[lsu.scala:219:36] wire l_uop_7_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1191:37] wire uop_32_exception = ldq_uop_7_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_7_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_7_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_32_exc_cause = ldq_uop_7_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_7_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_mem_cmd = ldq_uop_7_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_7_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_mem_size = ldq_uop_7_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_mem_signed; // @[lsu.scala:219:36] wire l_uop_7_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_32_mem_signed = ldq_uop_7_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_ldq; // @[lsu.scala:219:36] wire l_uop_7_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_ldq = ldq_uop_7_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_uses_stq; // @[lsu.scala:219:36] wire l_uop_7_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_32_uses_stq = ldq_uop_7_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_is_unique; // @[lsu.scala:219:36] wire l_uop_7_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_32_is_unique = ldq_uop_7_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_7_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_32_flush_on_commit = ldq_uop_7_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_7_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_csr_cmd = ldq_uop_7_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_7_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_32_ldst_is_rs1 = ldq_uop_7_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_7_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_ldst = ldq_uop_7_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs1 = ldq_uop_7_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs2 = ldq_uop_7_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_7_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_7_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_32_lrs3 = ldq_uop_7_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_dst_rtype = ldq_uop_7_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs1_rtype = ldq_uop_7_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_7_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_lrs2_rtype = ldq_uop_7_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_frs3_en; // @[lsu.scala:219:36] wire l_uop_7_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_32_frs3_en = ldq_uop_7_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fcn_dw; // @[lsu.scala:219:36] wire l_uop_7_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_32_fcn_dw = ldq_uop_7_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_7_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_7_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_32_fcn_op = ldq_uop_7_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_fp_val; // @[lsu.scala:219:36] wire l_uop_7_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_32_fp_val = ldq_uop_7_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_7_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_fp_rm = ldq_uop_7_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_7_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_7_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_32_fp_typ = ldq_uop_7_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_pf_if = ldq_uop_7_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ae_if = ldq_uop_7_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_7_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_xcpt_ma_if = ldq_uop_7_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_7_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_debug_if = ldq_uop_7_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_7_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_32_bp_xcpt_if = ldq_uop_7_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_fsrc = ldq_uop_7_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_7_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_32_debug_tsrc = ldq_uop_7_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_33_inst = ldq_uop_8_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_8_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_8_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_33_debug_inst = ldq_uop_8_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rvc; // @[lsu.scala:219:36] wire l_uop_8_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_rvc = ldq_uop_8_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_8_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_8_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_33_debug_pc = ldq_uop_8_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_0; // @[lsu.scala:219:36] wire l_uop_8_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_0 = ldq_uop_8_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_1; // @[lsu.scala:219:36] wire l_uop_8_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_1 = ldq_uop_8_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_2; // @[lsu.scala:219:36] wire l_uop_8_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_2 = ldq_uop_8_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iq_type_3; // @[lsu.scala:219:36] wire l_uop_8_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_33_iq_type_3 = ldq_uop_8_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_0; // @[lsu.scala:219:36] wire l_uop_8_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_0 = ldq_uop_8_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_1; // @[lsu.scala:219:36] wire l_uop_8_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_1 = ldq_uop_8_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_2; // @[lsu.scala:219:36] wire l_uop_8_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_2 = ldq_uop_8_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_3; // @[lsu.scala:219:36] wire l_uop_8_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_3 = ldq_uop_8_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_4; // @[lsu.scala:219:36] wire l_uop_8_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_4 = ldq_uop_8_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_5; // @[lsu.scala:219:36] wire l_uop_8_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_5 = ldq_uop_8_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_6; // @[lsu.scala:219:36] wire l_uop_8_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_6 = ldq_uop_8_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_7; // @[lsu.scala:219:36] wire l_uop_8_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_7 = ldq_uop_8_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_8; // @[lsu.scala:219:36] wire l_uop_8_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_8 = ldq_uop_8_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fu_code_9; // @[lsu.scala:219:36] wire l_uop_8_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_33_fu_code_9 = ldq_uop_8_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued; // @[lsu.scala:219:36] wire l_uop_8_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued = ldq_uop_8_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued_partial_agen = ldq_uop_8_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_8_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_issued_partial_dgen = ldq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_8_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_iw_p1_speculative_child = ldq_uop_8_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_8_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_iw_p2_speculative_child = ldq_uop_8_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p1_bypass_hint = ldq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p2_bypass_hint = ldq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_8_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_33_iw_p3_bypass_hint = ldq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_dis_col_sel = ldq_uop_8_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_8_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_8_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_33_br_mask = ldq_uop_8_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_33_br_tag = ldq_uop_8_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_8_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_8_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_33_br_type = ldq_uop_8_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfb; // @[lsu.scala:219:36] wire l_uop_8_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sfb = ldq_uop_8_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fence; // @[lsu.scala:219:36] wire l_uop_8_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_fence = ldq_uop_8_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_fencei; // @[lsu.scala:219:36] wire l_uop_8_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_fencei = ldq_uop_8_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sfence; // @[lsu.scala:219:36] wire l_uop_8_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sfence = ldq_uop_8_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_amo; // @[lsu.scala:219:36] wire l_uop_8_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_amo = ldq_uop_8_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_eret; // @[lsu.scala:219:36] wire l_uop_8_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_eret = ldq_uop_8_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_8_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_sys_pc2epc = ldq_uop_8_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_rocc; // @[lsu.scala:219:36] wire l_uop_8_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_rocc = ldq_uop_8_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_mov; // @[lsu.scala:219:36] wire l_uop_8_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_mov = ldq_uop_8_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ftq_idx = ldq_uop_8_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_edge_inst; // @[lsu.scala:219:36] wire l_uop_8_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_33_edge_inst = ldq_uop_8_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_8_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_pc_lob = ldq_uop_8_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_taken; // @[lsu.scala:219:36] wire l_uop_8_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1191:37] wire uop_33_taken = ldq_uop_8_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_imm_rename; // @[lsu.scala:219:36] wire l_uop_8_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_33_imm_rename = ldq_uop_8_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_imm_sel = ldq_uop_8_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_8_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_pimm = ldq_uop_8_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_8_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_8_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_33_imm_packed = ldq_uop_8_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_8_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_op1_sel = ldq_uop_8_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_8_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_op2_sel = ldq_uop_8_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ldst = ldq_uop_8_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_wen = ldq_uop_8_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren1 = ldq_uop_8_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren2 = ldq_uop_8_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_ren3 = ldq_uop_8_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_swap12 = ldq_uop_8_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_swap23 = ldq_uop_8_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_ctrl_typeTagIn = ldq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_ctrl_typeTagOut = ldq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fromint = ldq_uop_8_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_toint = ldq_uop_8_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fastpipe = ldq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_fma = ldq_uop_8_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_div = ldq_uop_8_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_sqrt = ldq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_wflags = ldq_uop_8_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_8_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_ctrl_vec = ldq_uop_8_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_8_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_rob_idx = ldq_uop_8_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ldq_idx = ldq_uop_8_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_8_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_stq_idx = ldq_uop_8_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_8_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_rxq_idx = ldq_uop_8_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_pdst = ldq_uop_8_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs1 = ldq_uop_8_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs2 = ldq_uop_8_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_8_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_prs3 = ldq_uop_8_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_8_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_ppred = ldq_uop_8_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs1_busy; // @[lsu.scala:219:36] wire l_uop_8_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs1_busy = ldq_uop_8_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs2_busy; // @[lsu.scala:219:36] wire l_uop_8_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs2_busy = ldq_uop_8_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_prs3_busy; // @[lsu.scala:219:36] wire l_uop_8_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_prs3_busy = ldq_uop_8_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ppred_busy; // @[lsu.scala:219:36] wire l_uop_8_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_33_ppred_busy = ldq_uop_8_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_8_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_8_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_33_stale_pdst = ldq_uop_8_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_exception; // @[lsu.scala:219:36] wire l_uop_8_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1191:37] wire uop_33_exception = ldq_uop_8_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_8_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_8_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_33_exc_cause = ldq_uop_8_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_8_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_mem_cmd = ldq_uop_8_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_8_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_mem_size = ldq_uop_8_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_mem_signed; // @[lsu.scala:219:36] wire l_uop_8_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_33_mem_signed = ldq_uop_8_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_ldq; // @[lsu.scala:219:36] wire l_uop_8_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_33_uses_ldq = ldq_uop_8_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_uses_stq; // @[lsu.scala:219:36] wire l_uop_8_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_33_uses_stq = ldq_uop_8_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_is_unique; // @[lsu.scala:219:36] wire l_uop_8_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_33_is_unique = ldq_uop_8_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_8_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_33_flush_on_commit = ldq_uop_8_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_8_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_csr_cmd = ldq_uop_8_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_8_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_33_ldst_is_rs1 = ldq_uop_8_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_8_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_ldst = ldq_uop_8_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs1 = ldq_uop_8_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs2 = ldq_uop_8_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_8_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_8_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_33_lrs3 = ldq_uop_8_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_dst_rtype = ldq_uop_8_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_lrs1_rtype = ldq_uop_8_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_8_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_lrs2_rtype = ldq_uop_8_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_frs3_en; // @[lsu.scala:219:36] wire l_uop_8_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_33_frs3_en = ldq_uop_8_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fcn_dw; // @[lsu.scala:219:36] wire l_uop_8_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_33_fcn_dw = ldq_uop_8_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_8_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_8_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_33_fcn_op = ldq_uop_8_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_fp_val; // @[lsu.scala:219:36] wire l_uop_8_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_33_fp_val = ldq_uop_8_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_8_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_fp_rm = ldq_uop_8_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_8_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_8_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_33_fp_typ = ldq_uop_8_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_pf_if = ldq_uop_8_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_ae_if = ldq_uop_8_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_8_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_xcpt_ma_if = ldq_uop_8_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_8_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_bp_debug_if = ldq_uop_8_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_8_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_33_bp_xcpt_if = ldq_uop_8_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_debug_fsrc = ldq_uop_8_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_8_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_33_debug_tsrc = ldq_uop_8_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_34_inst = ldq_uop_9_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_9_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_9_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_34_debug_inst = ldq_uop_9_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rvc; // @[lsu.scala:219:36] wire l_uop_9_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_rvc = ldq_uop_9_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_9_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_9_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_34_debug_pc = ldq_uop_9_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_0; // @[lsu.scala:219:36] wire l_uop_9_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_0 = ldq_uop_9_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_1; // @[lsu.scala:219:36] wire l_uop_9_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_1 = ldq_uop_9_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_2; // @[lsu.scala:219:36] wire l_uop_9_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_2 = ldq_uop_9_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iq_type_3; // @[lsu.scala:219:36] wire l_uop_9_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_34_iq_type_3 = ldq_uop_9_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_0; // @[lsu.scala:219:36] wire l_uop_9_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_0 = ldq_uop_9_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_1; // @[lsu.scala:219:36] wire l_uop_9_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_1 = ldq_uop_9_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_2; // @[lsu.scala:219:36] wire l_uop_9_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_2 = ldq_uop_9_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_3; // @[lsu.scala:219:36] wire l_uop_9_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_3 = ldq_uop_9_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_4; // @[lsu.scala:219:36] wire l_uop_9_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_4 = ldq_uop_9_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_5; // @[lsu.scala:219:36] wire l_uop_9_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_5 = ldq_uop_9_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_6; // @[lsu.scala:219:36] wire l_uop_9_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_6 = ldq_uop_9_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_7; // @[lsu.scala:219:36] wire l_uop_9_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_7 = ldq_uop_9_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_8; // @[lsu.scala:219:36] wire l_uop_9_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_8 = ldq_uop_9_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fu_code_9; // @[lsu.scala:219:36] wire l_uop_9_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_34_fu_code_9 = ldq_uop_9_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued; // @[lsu.scala:219:36] wire l_uop_9_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued = ldq_uop_9_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued_partial_agen = ldq_uop_9_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_9_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_issued_partial_dgen = ldq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_9_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_iw_p1_speculative_child = ldq_uop_9_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_9_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_iw_p2_speculative_child = ldq_uop_9_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p1_bypass_hint = ldq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p2_bypass_hint = ldq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_9_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_34_iw_p3_bypass_hint = ldq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_dis_col_sel = ldq_uop_9_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_9_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_9_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_34_br_mask = ldq_uop_9_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_34_br_tag = ldq_uop_9_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_9_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_9_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_34_br_type = ldq_uop_9_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfb; // @[lsu.scala:219:36] wire l_uop_9_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sfb = ldq_uop_9_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fence; // @[lsu.scala:219:36] wire l_uop_9_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_fence = ldq_uop_9_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_fencei; // @[lsu.scala:219:36] wire l_uop_9_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_fencei = ldq_uop_9_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sfence; // @[lsu.scala:219:36] wire l_uop_9_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sfence = ldq_uop_9_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_amo; // @[lsu.scala:219:36] wire l_uop_9_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_amo = ldq_uop_9_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_eret; // @[lsu.scala:219:36] wire l_uop_9_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_eret = ldq_uop_9_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_9_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_sys_pc2epc = ldq_uop_9_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_rocc; // @[lsu.scala:219:36] wire l_uop_9_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_rocc = ldq_uop_9_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_mov; // @[lsu.scala:219:36] wire l_uop_9_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_mov = ldq_uop_9_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ftq_idx = ldq_uop_9_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_edge_inst; // @[lsu.scala:219:36] wire l_uop_9_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_34_edge_inst = ldq_uop_9_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_9_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_pc_lob = ldq_uop_9_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_taken; // @[lsu.scala:219:36] wire l_uop_9_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1191:37] wire uop_34_taken = ldq_uop_9_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_imm_rename; // @[lsu.scala:219:36] wire l_uop_9_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_34_imm_rename = ldq_uop_9_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_imm_sel = ldq_uop_9_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_9_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_pimm = ldq_uop_9_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_9_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_9_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_34_imm_packed = ldq_uop_9_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_9_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_op1_sel = ldq_uop_9_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_9_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_op2_sel = ldq_uop_9_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ldst = ldq_uop_9_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_wen = ldq_uop_9_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren1 = ldq_uop_9_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren2 = ldq_uop_9_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_ren3 = ldq_uop_9_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_swap12 = ldq_uop_9_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_swap23 = ldq_uop_9_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_ctrl_typeTagIn = ldq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_ctrl_typeTagOut = ldq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fromint = ldq_uop_9_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_toint = ldq_uop_9_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fastpipe = ldq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_fma = ldq_uop_9_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_div = ldq_uop_9_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_sqrt = ldq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_wflags = ldq_uop_9_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_9_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_ctrl_vec = ldq_uop_9_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_9_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_rob_idx = ldq_uop_9_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ldq_idx = ldq_uop_9_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_9_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_stq_idx = ldq_uop_9_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_9_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_rxq_idx = ldq_uop_9_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_pdst = ldq_uop_9_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs1 = ldq_uop_9_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs2 = ldq_uop_9_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_9_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_prs3 = ldq_uop_9_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_9_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_ppred = ldq_uop_9_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs1_busy; // @[lsu.scala:219:36] wire l_uop_9_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs1_busy = ldq_uop_9_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs2_busy; // @[lsu.scala:219:36] wire l_uop_9_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs2_busy = ldq_uop_9_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_prs3_busy; // @[lsu.scala:219:36] wire l_uop_9_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_prs3_busy = ldq_uop_9_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ppred_busy; // @[lsu.scala:219:36] wire l_uop_9_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_34_ppred_busy = ldq_uop_9_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_9_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_9_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_34_stale_pdst = ldq_uop_9_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_exception; // @[lsu.scala:219:36] wire l_uop_9_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1191:37] wire uop_34_exception = ldq_uop_9_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_9_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_9_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_34_exc_cause = ldq_uop_9_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_9_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_mem_cmd = ldq_uop_9_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_9_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_mem_size = ldq_uop_9_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_mem_signed; // @[lsu.scala:219:36] wire l_uop_9_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_34_mem_signed = ldq_uop_9_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_ldq; // @[lsu.scala:219:36] wire l_uop_9_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_34_uses_ldq = ldq_uop_9_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_uses_stq; // @[lsu.scala:219:36] wire l_uop_9_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_34_uses_stq = ldq_uop_9_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_is_unique; // @[lsu.scala:219:36] wire l_uop_9_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_34_is_unique = ldq_uop_9_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_9_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_34_flush_on_commit = ldq_uop_9_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_9_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_csr_cmd = ldq_uop_9_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_9_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_34_ldst_is_rs1 = ldq_uop_9_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_9_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_ldst = ldq_uop_9_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs1 = ldq_uop_9_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs2 = ldq_uop_9_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_9_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_9_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_34_lrs3 = ldq_uop_9_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_dst_rtype = ldq_uop_9_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_lrs1_rtype = ldq_uop_9_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_9_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_lrs2_rtype = ldq_uop_9_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_frs3_en; // @[lsu.scala:219:36] wire l_uop_9_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_34_frs3_en = ldq_uop_9_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fcn_dw; // @[lsu.scala:219:36] wire l_uop_9_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_34_fcn_dw = ldq_uop_9_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_9_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_9_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_34_fcn_op = ldq_uop_9_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_fp_val; // @[lsu.scala:219:36] wire l_uop_9_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_34_fp_val = ldq_uop_9_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_9_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_fp_rm = ldq_uop_9_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_9_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_9_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_34_fp_typ = ldq_uop_9_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_pf_if = ldq_uop_9_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_ae_if = ldq_uop_9_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_9_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_xcpt_ma_if = ldq_uop_9_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_9_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_bp_debug_if = ldq_uop_9_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_9_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_34_bp_xcpt_if = ldq_uop_9_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_debug_fsrc = ldq_uop_9_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_9_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_34_debug_tsrc = ldq_uop_9_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_35_inst = ldq_uop_10_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_10_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_10_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_35_debug_inst = ldq_uop_10_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rvc; // @[lsu.scala:219:36] wire l_uop_10_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_rvc = ldq_uop_10_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_10_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_10_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_35_debug_pc = ldq_uop_10_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_0; // @[lsu.scala:219:36] wire l_uop_10_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_0 = ldq_uop_10_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_1; // @[lsu.scala:219:36] wire l_uop_10_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_1 = ldq_uop_10_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_2; // @[lsu.scala:219:36] wire l_uop_10_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_2 = ldq_uop_10_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iq_type_3; // @[lsu.scala:219:36] wire l_uop_10_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_35_iq_type_3 = ldq_uop_10_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_0; // @[lsu.scala:219:36] wire l_uop_10_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_0 = ldq_uop_10_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_1; // @[lsu.scala:219:36] wire l_uop_10_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_1 = ldq_uop_10_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_2; // @[lsu.scala:219:36] wire l_uop_10_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_2 = ldq_uop_10_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_3; // @[lsu.scala:219:36] wire l_uop_10_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_3 = ldq_uop_10_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_4; // @[lsu.scala:219:36] wire l_uop_10_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_4 = ldq_uop_10_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_5; // @[lsu.scala:219:36] wire l_uop_10_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_5 = ldq_uop_10_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_6; // @[lsu.scala:219:36] wire l_uop_10_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_6 = ldq_uop_10_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_7; // @[lsu.scala:219:36] wire l_uop_10_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_7 = ldq_uop_10_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_8; // @[lsu.scala:219:36] wire l_uop_10_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_8 = ldq_uop_10_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fu_code_9; // @[lsu.scala:219:36] wire l_uop_10_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_35_fu_code_9 = ldq_uop_10_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued; // @[lsu.scala:219:36] wire l_uop_10_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued = ldq_uop_10_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued_partial_agen = ldq_uop_10_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_10_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_issued_partial_dgen = ldq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_10_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_iw_p1_speculative_child = ldq_uop_10_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_10_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_iw_p2_speculative_child = ldq_uop_10_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p1_bypass_hint = ldq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p2_bypass_hint = ldq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_10_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_35_iw_p3_bypass_hint = ldq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_dis_col_sel = ldq_uop_10_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_10_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_10_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_35_br_mask = ldq_uop_10_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_35_br_tag = ldq_uop_10_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_10_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_10_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_35_br_type = ldq_uop_10_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfb; // @[lsu.scala:219:36] wire l_uop_10_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sfb = ldq_uop_10_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fence; // @[lsu.scala:219:36] wire l_uop_10_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_fence = ldq_uop_10_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_fencei; // @[lsu.scala:219:36] wire l_uop_10_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_fencei = ldq_uop_10_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sfence; // @[lsu.scala:219:36] wire l_uop_10_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sfence = ldq_uop_10_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_amo; // @[lsu.scala:219:36] wire l_uop_10_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_amo = ldq_uop_10_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_eret; // @[lsu.scala:219:36] wire l_uop_10_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_eret = ldq_uop_10_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_10_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_sys_pc2epc = ldq_uop_10_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_rocc; // @[lsu.scala:219:36] wire l_uop_10_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_rocc = ldq_uop_10_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_mov; // @[lsu.scala:219:36] wire l_uop_10_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_mov = ldq_uop_10_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ftq_idx = ldq_uop_10_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_edge_inst; // @[lsu.scala:219:36] wire l_uop_10_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_35_edge_inst = ldq_uop_10_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_10_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_pc_lob = ldq_uop_10_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_taken; // @[lsu.scala:219:36] wire l_uop_10_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1191:37] wire uop_35_taken = ldq_uop_10_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_imm_rename; // @[lsu.scala:219:36] wire l_uop_10_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_35_imm_rename = ldq_uop_10_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_imm_sel = ldq_uop_10_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_10_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_pimm = ldq_uop_10_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_10_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_10_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_35_imm_packed = ldq_uop_10_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_10_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_op1_sel = ldq_uop_10_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_10_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_op2_sel = ldq_uop_10_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ldst = ldq_uop_10_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_wen = ldq_uop_10_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren1 = ldq_uop_10_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren2 = ldq_uop_10_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_ren3 = ldq_uop_10_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_swap12 = ldq_uop_10_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_swap23 = ldq_uop_10_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_ctrl_typeTagIn = ldq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_ctrl_typeTagOut = ldq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fromint = ldq_uop_10_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_toint = ldq_uop_10_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fastpipe = ldq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_fma = ldq_uop_10_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_div = ldq_uop_10_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_sqrt = ldq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_wflags = ldq_uop_10_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_10_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_ctrl_vec = ldq_uop_10_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_10_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_rob_idx = ldq_uop_10_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ldq_idx = ldq_uop_10_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_10_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_stq_idx = ldq_uop_10_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_10_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_rxq_idx = ldq_uop_10_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_pdst = ldq_uop_10_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs1 = ldq_uop_10_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs2 = ldq_uop_10_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_10_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_prs3 = ldq_uop_10_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_10_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_ppred = ldq_uop_10_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs1_busy; // @[lsu.scala:219:36] wire l_uop_10_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs1_busy = ldq_uop_10_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs2_busy; // @[lsu.scala:219:36] wire l_uop_10_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs2_busy = ldq_uop_10_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_prs3_busy; // @[lsu.scala:219:36] wire l_uop_10_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_prs3_busy = ldq_uop_10_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ppred_busy; // @[lsu.scala:219:36] wire l_uop_10_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_35_ppred_busy = ldq_uop_10_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_10_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_10_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_35_stale_pdst = ldq_uop_10_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_exception; // @[lsu.scala:219:36] wire l_uop_10_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1191:37] wire uop_35_exception = ldq_uop_10_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_10_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_10_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_35_exc_cause = ldq_uop_10_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_10_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_mem_cmd = ldq_uop_10_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_10_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_mem_size = ldq_uop_10_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_mem_signed; // @[lsu.scala:219:36] wire l_uop_10_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_35_mem_signed = ldq_uop_10_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_ldq; // @[lsu.scala:219:36] wire l_uop_10_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_35_uses_ldq = ldq_uop_10_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_uses_stq; // @[lsu.scala:219:36] wire l_uop_10_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_35_uses_stq = ldq_uop_10_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_is_unique; // @[lsu.scala:219:36] wire l_uop_10_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_35_is_unique = ldq_uop_10_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_10_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_35_flush_on_commit = ldq_uop_10_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_10_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_csr_cmd = ldq_uop_10_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_10_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_35_ldst_is_rs1 = ldq_uop_10_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_10_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_ldst = ldq_uop_10_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs1 = ldq_uop_10_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs2 = ldq_uop_10_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_10_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_10_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_35_lrs3 = ldq_uop_10_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_dst_rtype = ldq_uop_10_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_lrs1_rtype = ldq_uop_10_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_10_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_lrs2_rtype = ldq_uop_10_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_frs3_en; // @[lsu.scala:219:36] wire l_uop_10_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_35_frs3_en = ldq_uop_10_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fcn_dw; // @[lsu.scala:219:36] wire l_uop_10_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_35_fcn_dw = ldq_uop_10_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_10_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_10_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_35_fcn_op = ldq_uop_10_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_fp_val; // @[lsu.scala:219:36] wire l_uop_10_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_35_fp_val = ldq_uop_10_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_10_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_fp_rm = ldq_uop_10_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_10_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_10_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_35_fp_typ = ldq_uop_10_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_pf_if = ldq_uop_10_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_ae_if = ldq_uop_10_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_10_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_xcpt_ma_if = ldq_uop_10_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_10_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_bp_debug_if = ldq_uop_10_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_10_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_35_bp_xcpt_if = ldq_uop_10_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_debug_fsrc = ldq_uop_10_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_10_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_35_debug_tsrc = ldq_uop_10_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_36_inst = ldq_uop_11_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_11_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_11_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_36_debug_inst = ldq_uop_11_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rvc; // @[lsu.scala:219:36] wire l_uop_11_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_rvc = ldq_uop_11_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_11_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_11_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_36_debug_pc = ldq_uop_11_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_0; // @[lsu.scala:219:36] wire l_uop_11_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_0 = ldq_uop_11_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_1; // @[lsu.scala:219:36] wire l_uop_11_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_1 = ldq_uop_11_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_2; // @[lsu.scala:219:36] wire l_uop_11_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_2 = ldq_uop_11_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iq_type_3; // @[lsu.scala:219:36] wire l_uop_11_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_36_iq_type_3 = ldq_uop_11_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_0; // @[lsu.scala:219:36] wire l_uop_11_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_0 = ldq_uop_11_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_1; // @[lsu.scala:219:36] wire l_uop_11_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_1 = ldq_uop_11_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_2; // @[lsu.scala:219:36] wire l_uop_11_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_2 = ldq_uop_11_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_3; // @[lsu.scala:219:36] wire l_uop_11_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_3 = ldq_uop_11_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_4; // @[lsu.scala:219:36] wire l_uop_11_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_4 = ldq_uop_11_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_5; // @[lsu.scala:219:36] wire l_uop_11_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_5 = ldq_uop_11_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_6; // @[lsu.scala:219:36] wire l_uop_11_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_6 = ldq_uop_11_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_7; // @[lsu.scala:219:36] wire l_uop_11_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_7 = ldq_uop_11_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_8; // @[lsu.scala:219:36] wire l_uop_11_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_8 = ldq_uop_11_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fu_code_9; // @[lsu.scala:219:36] wire l_uop_11_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_36_fu_code_9 = ldq_uop_11_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued; // @[lsu.scala:219:36] wire l_uop_11_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued = ldq_uop_11_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued_partial_agen = ldq_uop_11_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_11_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_issued_partial_dgen = ldq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_11_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_iw_p1_speculative_child = ldq_uop_11_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_11_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_iw_p2_speculative_child = ldq_uop_11_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p1_bypass_hint = ldq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p2_bypass_hint = ldq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_11_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_36_iw_p3_bypass_hint = ldq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_dis_col_sel = ldq_uop_11_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_11_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_11_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_36_br_mask = ldq_uop_11_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_36_br_tag = ldq_uop_11_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_11_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_11_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_36_br_type = ldq_uop_11_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfb; // @[lsu.scala:219:36] wire l_uop_11_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sfb = ldq_uop_11_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fence; // @[lsu.scala:219:36] wire l_uop_11_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_fence = ldq_uop_11_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_fencei; // @[lsu.scala:219:36] wire l_uop_11_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_fencei = ldq_uop_11_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sfence; // @[lsu.scala:219:36] wire l_uop_11_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sfence = ldq_uop_11_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_amo; // @[lsu.scala:219:36] wire l_uop_11_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_amo = ldq_uop_11_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_eret; // @[lsu.scala:219:36] wire l_uop_11_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_eret = ldq_uop_11_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_11_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_sys_pc2epc = ldq_uop_11_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_rocc; // @[lsu.scala:219:36] wire l_uop_11_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_rocc = ldq_uop_11_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_mov; // @[lsu.scala:219:36] wire l_uop_11_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_mov = ldq_uop_11_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ftq_idx = ldq_uop_11_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_edge_inst; // @[lsu.scala:219:36] wire l_uop_11_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_36_edge_inst = ldq_uop_11_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_11_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_pc_lob = ldq_uop_11_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_taken; // @[lsu.scala:219:36] wire l_uop_11_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1191:37] wire uop_36_taken = ldq_uop_11_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_imm_rename; // @[lsu.scala:219:36] wire l_uop_11_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_36_imm_rename = ldq_uop_11_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_imm_sel = ldq_uop_11_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_11_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_pimm = ldq_uop_11_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_11_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_11_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_36_imm_packed = ldq_uop_11_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_11_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_op1_sel = ldq_uop_11_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_11_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_op2_sel = ldq_uop_11_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ldst = ldq_uop_11_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_wen = ldq_uop_11_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren1 = ldq_uop_11_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren2 = ldq_uop_11_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_ren3 = ldq_uop_11_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_swap12 = ldq_uop_11_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_swap23 = ldq_uop_11_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_ctrl_typeTagIn = ldq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_ctrl_typeTagOut = ldq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fromint = ldq_uop_11_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_toint = ldq_uop_11_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fastpipe = ldq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_fma = ldq_uop_11_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_div = ldq_uop_11_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_sqrt = ldq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_wflags = ldq_uop_11_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_11_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_ctrl_vec = ldq_uop_11_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_11_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_rob_idx = ldq_uop_11_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ldq_idx = ldq_uop_11_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_11_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_stq_idx = ldq_uop_11_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_11_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_rxq_idx = ldq_uop_11_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_pdst = ldq_uop_11_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs1 = ldq_uop_11_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs2 = ldq_uop_11_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_11_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_prs3 = ldq_uop_11_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_11_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_ppred = ldq_uop_11_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs1_busy; // @[lsu.scala:219:36] wire l_uop_11_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs1_busy = ldq_uop_11_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs2_busy; // @[lsu.scala:219:36] wire l_uop_11_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs2_busy = ldq_uop_11_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_prs3_busy; // @[lsu.scala:219:36] wire l_uop_11_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_prs3_busy = ldq_uop_11_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ppred_busy; // @[lsu.scala:219:36] wire l_uop_11_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_36_ppred_busy = ldq_uop_11_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_11_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_11_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_36_stale_pdst = ldq_uop_11_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_exception; // @[lsu.scala:219:36] wire l_uop_11_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1191:37] wire uop_36_exception = ldq_uop_11_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_11_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_11_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_36_exc_cause = ldq_uop_11_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_11_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_mem_cmd = ldq_uop_11_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_11_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_mem_size = ldq_uop_11_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_mem_signed; // @[lsu.scala:219:36] wire l_uop_11_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_36_mem_signed = ldq_uop_11_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_ldq; // @[lsu.scala:219:36] wire l_uop_11_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_36_uses_ldq = ldq_uop_11_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_uses_stq; // @[lsu.scala:219:36] wire l_uop_11_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_36_uses_stq = ldq_uop_11_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_is_unique; // @[lsu.scala:219:36] wire l_uop_11_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_36_is_unique = ldq_uop_11_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_11_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_36_flush_on_commit = ldq_uop_11_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_11_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_csr_cmd = ldq_uop_11_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_11_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_36_ldst_is_rs1 = ldq_uop_11_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_11_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_ldst = ldq_uop_11_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs1 = ldq_uop_11_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs2 = ldq_uop_11_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_11_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_11_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_36_lrs3 = ldq_uop_11_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_dst_rtype = ldq_uop_11_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_lrs1_rtype = ldq_uop_11_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_11_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_lrs2_rtype = ldq_uop_11_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_frs3_en; // @[lsu.scala:219:36] wire l_uop_11_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_36_frs3_en = ldq_uop_11_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fcn_dw; // @[lsu.scala:219:36] wire l_uop_11_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_36_fcn_dw = ldq_uop_11_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_11_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_11_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_36_fcn_op = ldq_uop_11_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_fp_val; // @[lsu.scala:219:36] wire l_uop_11_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_36_fp_val = ldq_uop_11_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_11_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_fp_rm = ldq_uop_11_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_11_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_11_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_36_fp_typ = ldq_uop_11_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_pf_if = ldq_uop_11_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_ae_if = ldq_uop_11_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_11_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_xcpt_ma_if = ldq_uop_11_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_11_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_bp_debug_if = ldq_uop_11_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_11_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_36_bp_xcpt_if = ldq_uop_11_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_debug_fsrc = ldq_uop_11_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_11_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_36_debug_tsrc = ldq_uop_11_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_37_inst = ldq_uop_12_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_12_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_12_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_37_debug_inst = ldq_uop_12_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rvc; // @[lsu.scala:219:36] wire l_uop_12_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_rvc = ldq_uop_12_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_12_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_12_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_37_debug_pc = ldq_uop_12_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_0; // @[lsu.scala:219:36] wire l_uop_12_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_0 = ldq_uop_12_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_1; // @[lsu.scala:219:36] wire l_uop_12_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_1 = ldq_uop_12_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_2; // @[lsu.scala:219:36] wire l_uop_12_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_2 = ldq_uop_12_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iq_type_3; // @[lsu.scala:219:36] wire l_uop_12_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_37_iq_type_3 = ldq_uop_12_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_0; // @[lsu.scala:219:36] wire l_uop_12_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_0 = ldq_uop_12_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_1; // @[lsu.scala:219:36] wire l_uop_12_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_1 = ldq_uop_12_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_2; // @[lsu.scala:219:36] wire l_uop_12_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_2 = ldq_uop_12_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_3; // @[lsu.scala:219:36] wire l_uop_12_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_3 = ldq_uop_12_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_4; // @[lsu.scala:219:36] wire l_uop_12_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_4 = ldq_uop_12_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_5; // @[lsu.scala:219:36] wire l_uop_12_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_5 = ldq_uop_12_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_6; // @[lsu.scala:219:36] wire l_uop_12_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_6 = ldq_uop_12_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_7; // @[lsu.scala:219:36] wire l_uop_12_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_7 = ldq_uop_12_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_8; // @[lsu.scala:219:36] wire l_uop_12_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_8 = ldq_uop_12_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fu_code_9; // @[lsu.scala:219:36] wire l_uop_12_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_37_fu_code_9 = ldq_uop_12_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued; // @[lsu.scala:219:36] wire l_uop_12_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued = ldq_uop_12_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued_partial_agen = ldq_uop_12_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_12_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_issued_partial_dgen = ldq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_12_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_iw_p1_speculative_child = ldq_uop_12_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_12_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_iw_p2_speculative_child = ldq_uop_12_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p1_bypass_hint = ldq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p2_bypass_hint = ldq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_12_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_37_iw_p3_bypass_hint = ldq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_dis_col_sel = ldq_uop_12_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_12_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_12_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_37_br_mask = ldq_uop_12_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_37_br_tag = ldq_uop_12_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_12_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_12_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_37_br_type = ldq_uop_12_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfb; // @[lsu.scala:219:36] wire l_uop_12_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sfb = ldq_uop_12_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fence; // @[lsu.scala:219:36] wire l_uop_12_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_fence = ldq_uop_12_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_fencei; // @[lsu.scala:219:36] wire l_uop_12_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_fencei = ldq_uop_12_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sfence; // @[lsu.scala:219:36] wire l_uop_12_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sfence = ldq_uop_12_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_amo; // @[lsu.scala:219:36] wire l_uop_12_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_amo = ldq_uop_12_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_eret; // @[lsu.scala:219:36] wire l_uop_12_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_eret = ldq_uop_12_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_12_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_sys_pc2epc = ldq_uop_12_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_rocc; // @[lsu.scala:219:36] wire l_uop_12_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_rocc = ldq_uop_12_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_mov; // @[lsu.scala:219:36] wire l_uop_12_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_mov = ldq_uop_12_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ftq_idx = ldq_uop_12_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_edge_inst; // @[lsu.scala:219:36] wire l_uop_12_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_37_edge_inst = ldq_uop_12_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_12_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_pc_lob = ldq_uop_12_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_taken; // @[lsu.scala:219:36] wire l_uop_12_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1191:37] wire uop_37_taken = ldq_uop_12_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_imm_rename; // @[lsu.scala:219:36] wire l_uop_12_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_37_imm_rename = ldq_uop_12_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_imm_sel = ldq_uop_12_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_12_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_pimm = ldq_uop_12_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_12_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_12_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_37_imm_packed = ldq_uop_12_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_12_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_op1_sel = ldq_uop_12_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_12_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_op2_sel = ldq_uop_12_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ldst = ldq_uop_12_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_wen = ldq_uop_12_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren1 = ldq_uop_12_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren2 = ldq_uop_12_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_ren3 = ldq_uop_12_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_swap12 = ldq_uop_12_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_swap23 = ldq_uop_12_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_ctrl_typeTagIn = ldq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_ctrl_typeTagOut = ldq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fromint = ldq_uop_12_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_toint = ldq_uop_12_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fastpipe = ldq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_fma = ldq_uop_12_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_div = ldq_uop_12_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_sqrt = ldq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_wflags = ldq_uop_12_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_12_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_ctrl_vec = ldq_uop_12_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_12_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_rob_idx = ldq_uop_12_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ldq_idx = ldq_uop_12_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_12_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_stq_idx = ldq_uop_12_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_12_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_rxq_idx = ldq_uop_12_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_pdst = ldq_uop_12_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs1 = ldq_uop_12_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs2 = ldq_uop_12_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_12_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_prs3 = ldq_uop_12_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_12_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_ppred = ldq_uop_12_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs1_busy; // @[lsu.scala:219:36] wire l_uop_12_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs1_busy = ldq_uop_12_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs2_busy; // @[lsu.scala:219:36] wire l_uop_12_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs2_busy = ldq_uop_12_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_prs3_busy; // @[lsu.scala:219:36] wire l_uop_12_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_prs3_busy = ldq_uop_12_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ppred_busy; // @[lsu.scala:219:36] wire l_uop_12_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_37_ppred_busy = ldq_uop_12_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_12_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_12_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_37_stale_pdst = ldq_uop_12_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_exception; // @[lsu.scala:219:36] wire l_uop_12_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1191:37] wire uop_37_exception = ldq_uop_12_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_12_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_12_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_37_exc_cause = ldq_uop_12_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_12_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_mem_cmd = ldq_uop_12_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_12_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_mem_size = ldq_uop_12_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_mem_signed; // @[lsu.scala:219:36] wire l_uop_12_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_37_mem_signed = ldq_uop_12_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_ldq; // @[lsu.scala:219:36] wire l_uop_12_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_37_uses_ldq = ldq_uop_12_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_uses_stq; // @[lsu.scala:219:36] wire l_uop_12_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_37_uses_stq = ldq_uop_12_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_is_unique; // @[lsu.scala:219:36] wire l_uop_12_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_37_is_unique = ldq_uop_12_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_12_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_37_flush_on_commit = ldq_uop_12_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_12_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_csr_cmd = ldq_uop_12_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_12_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_37_ldst_is_rs1 = ldq_uop_12_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_12_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_ldst = ldq_uop_12_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs1 = ldq_uop_12_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs2 = ldq_uop_12_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_12_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_12_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_37_lrs3 = ldq_uop_12_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_dst_rtype = ldq_uop_12_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_lrs1_rtype = ldq_uop_12_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_12_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_lrs2_rtype = ldq_uop_12_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_frs3_en; // @[lsu.scala:219:36] wire l_uop_12_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_37_frs3_en = ldq_uop_12_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fcn_dw; // @[lsu.scala:219:36] wire l_uop_12_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_37_fcn_dw = ldq_uop_12_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_12_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_12_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_37_fcn_op = ldq_uop_12_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_fp_val; // @[lsu.scala:219:36] wire l_uop_12_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_37_fp_val = ldq_uop_12_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_12_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_fp_rm = ldq_uop_12_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_12_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_12_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_37_fp_typ = ldq_uop_12_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_pf_if = ldq_uop_12_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_ae_if = ldq_uop_12_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_12_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_xcpt_ma_if = ldq_uop_12_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_12_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_bp_debug_if = ldq_uop_12_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_12_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_37_bp_xcpt_if = ldq_uop_12_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_debug_fsrc = ldq_uop_12_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_12_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_37_debug_tsrc = ldq_uop_12_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_38_inst = ldq_uop_13_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_13_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_13_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_38_debug_inst = ldq_uop_13_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rvc; // @[lsu.scala:219:36] wire l_uop_13_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_rvc = ldq_uop_13_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_13_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_13_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_38_debug_pc = ldq_uop_13_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_0; // @[lsu.scala:219:36] wire l_uop_13_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_0 = ldq_uop_13_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_1; // @[lsu.scala:219:36] wire l_uop_13_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_1 = ldq_uop_13_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_2; // @[lsu.scala:219:36] wire l_uop_13_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_2 = ldq_uop_13_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iq_type_3; // @[lsu.scala:219:36] wire l_uop_13_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_38_iq_type_3 = ldq_uop_13_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_0; // @[lsu.scala:219:36] wire l_uop_13_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_0 = ldq_uop_13_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_1; // @[lsu.scala:219:36] wire l_uop_13_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_1 = ldq_uop_13_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_2; // @[lsu.scala:219:36] wire l_uop_13_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_2 = ldq_uop_13_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_3; // @[lsu.scala:219:36] wire l_uop_13_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_3 = ldq_uop_13_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_4; // @[lsu.scala:219:36] wire l_uop_13_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_4 = ldq_uop_13_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_5; // @[lsu.scala:219:36] wire l_uop_13_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_5 = ldq_uop_13_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_6; // @[lsu.scala:219:36] wire l_uop_13_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_6 = ldq_uop_13_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_7; // @[lsu.scala:219:36] wire l_uop_13_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_7 = ldq_uop_13_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_8; // @[lsu.scala:219:36] wire l_uop_13_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_8 = ldq_uop_13_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fu_code_9; // @[lsu.scala:219:36] wire l_uop_13_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_38_fu_code_9 = ldq_uop_13_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued; // @[lsu.scala:219:36] wire l_uop_13_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued = ldq_uop_13_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued_partial_agen = ldq_uop_13_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_13_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_issued_partial_dgen = ldq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_13_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_iw_p1_speculative_child = ldq_uop_13_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_13_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_iw_p2_speculative_child = ldq_uop_13_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p1_bypass_hint = ldq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p2_bypass_hint = ldq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_13_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_38_iw_p3_bypass_hint = ldq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_dis_col_sel = ldq_uop_13_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_13_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_13_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_38_br_mask = ldq_uop_13_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_38_br_tag = ldq_uop_13_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_13_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_13_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_38_br_type = ldq_uop_13_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfb; // @[lsu.scala:219:36] wire l_uop_13_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sfb = ldq_uop_13_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fence; // @[lsu.scala:219:36] wire l_uop_13_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_fence = ldq_uop_13_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_fencei; // @[lsu.scala:219:36] wire l_uop_13_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_fencei = ldq_uop_13_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sfence; // @[lsu.scala:219:36] wire l_uop_13_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sfence = ldq_uop_13_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_amo; // @[lsu.scala:219:36] wire l_uop_13_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_amo = ldq_uop_13_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_eret; // @[lsu.scala:219:36] wire l_uop_13_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_eret = ldq_uop_13_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_13_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_sys_pc2epc = ldq_uop_13_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_rocc; // @[lsu.scala:219:36] wire l_uop_13_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_rocc = ldq_uop_13_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_mov; // @[lsu.scala:219:36] wire l_uop_13_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_mov = ldq_uop_13_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ftq_idx = ldq_uop_13_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_edge_inst; // @[lsu.scala:219:36] wire l_uop_13_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_38_edge_inst = ldq_uop_13_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_13_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_pc_lob = ldq_uop_13_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_taken; // @[lsu.scala:219:36] wire l_uop_13_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1191:37] wire uop_38_taken = ldq_uop_13_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_imm_rename; // @[lsu.scala:219:36] wire l_uop_13_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_38_imm_rename = ldq_uop_13_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_imm_sel = ldq_uop_13_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_13_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_pimm = ldq_uop_13_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_13_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_13_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_38_imm_packed = ldq_uop_13_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_13_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_op1_sel = ldq_uop_13_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_13_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_op2_sel = ldq_uop_13_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ldst = ldq_uop_13_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_wen = ldq_uop_13_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren1 = ldq_uop_13_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren2 = ldq_uop_13_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_ren3 = ldq_uop_13_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_swap12 = ldq_uop_13_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_swap23 = ldq_uop_13_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_ctrl_typeTagIn = ldq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_ctrl_typeTagOut = ldq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fromint = ldq_uop_13_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_toint = ldq_uop_13_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fastpipe = ldq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_fma = ldq_uop_13_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_div = ldq_uop_13_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_sqrt = ldq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_wflags = ldq_uop_13_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_13_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_ctrl_vec = ldq_uop_13_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_13_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_rob_idx = ldq_uop_13_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ldq_idx = ldq_uop_13_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_13_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_stq_idx = ldq_uop_13_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_13_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_rxq_idx = ldq_uop_13_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_pdst = ldq_uop_13_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs1 = ldq_uop_13_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs2 = ldq_uop_13_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_13_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_prs3 = ldq_uop_13_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_13_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_ppred = ldq_uop_13_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs1_busy; // @[lsu.scala:219:36] wire l_uop_13_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs1_busy = ldq_uop_13_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs2_busy; // @[lsu.scala:219:36] wire l_uop_13_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs2_busy = ldq_uop_13_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_prs3_busy; // @[lsu.scala:219:36] wire l_uop_13_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_prs3_busy = ldq_uop_13_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ppred_busy; // @[lsu.scala:219:36] wire l_uop_13_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_38_ppred_busy = ldq_uop_13_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_13_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_13_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_38_stale_pdst = ldq_uop_13_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_exception; // @[lsu.scala:219:36] wire l_uop_13_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1191:37] wire uop_38_exception = ldq_uop_13_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_13_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_13_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_38_exc_cause = ldq_uop_13_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_13_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_mem_cmd = ldq_uop_13_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_13_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_mem_size = ldq_uop_13_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_mem_signed; // @[lsu.scala:219:36] wire l_uop_13_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_38_mem_signed = ldq_uop_13_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_ldq; // @[lsu.scala:219:36] wire l_uop_13_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_38_uses_ldq = ldq_uop_13_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_uses_stq; // @[lsu.scala:219:36] wire l_uop_13_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_38_uses_stq = ldq_uop_13_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_is_unique; // @[lsu.scala:219:36] wire l_uop_13_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_38_is_unique = ldq_uop_13_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_13_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_38_flush_on_commit = ldq_uop_13_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_13_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_csr_cmd = ldq_uop_13_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_13_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_38_ldst_is_rs1 = ldq_uop_13_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_13_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_ldst = ldq_uop_13_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs1 = ldq_uop_13_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs2 = ldq_uop_13_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_13_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_13_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_38_lrs3 = ldq_uop_13_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_dst_rtype = ldq_uop_13_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_lrs1_rtype = ldq_uop_13_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_13_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_lrs2_rtype = ldq_uop_13_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_frs3_en; // @[lsu.scala:219:36] wire l_uop_13_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_38_frs3_en = ldq_uop_13_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fcn_dw; // @[lsu.scala:219:36] wire l_uop_13_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_38_fcn_dw = ldq_uop_13_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_13_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_13_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_38_fcn_op = ldq_uop_13_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_fp_val; // @[lsu.scala:219:36] wire l_uop_13_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_38_fp_val = ldq_uop_13_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_13_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_fp_rm = ldq_uop_13_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_13_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_13_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_38_fp_typ = ldq_uop_13_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_pf_if = ldq_uop_13_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_ae_if = ldq_uop_13_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_13_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_xcpt_ma_if = ldq_uop_13_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_13_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_bp_debug_if = ldq_uop_13_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_13_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_38_bp_xcpt_if = ldq_uop_13_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_debug_fsrc = ldq_uop_13_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_13_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_38_debug_tsrc = ldq_uop_13_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_39_inst = ldq_uop_14_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_14_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_14_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_39_debug_inst = ldq_uop_14_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rvc; // @[lsu.scala:219:36] wire l_uop_14_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_rvc = ldq_uop_14_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_14_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_14_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_39_debug_pc = ldq_uop_14_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_0; // @[lsu.scala:219:36] wire l_uop_14_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_0 = ldq_uop_14_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_1; // @[lsu.scala:219:36] wire l_uop_14_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_1 = ldq_uop_14_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_2; // @[lsu.scala:219:36] wire l_uop_14_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_2 = ldq_uop_14_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iq_type_3; // @[lsu.scala:219:36] wire l_uop_14_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_39_iq_type_3 = ldq_uop_14_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_0; // @[lsu.scala:219:36] wire l_uop_14_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_0 = ldq_uop_14_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_1; // @[lsu.scala:219:36] wire l_uop_14_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_1 = ldq_uop_14_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_2; // @[lsu.scala:219:36] wire l_uop_14_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_2 = ldq_uop_14_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_3; // @[lsu.scala:219:36] wire l_uop_14_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_3 = ldq_uop_14_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_4; // @[lsu.scala:219:36] wire l_uop_14_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_4 = ldq_uop_14_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_5; // @[lsu.scala:219:36] wire l_uop_14_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_5 = ldq_uop_14_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_6; // @[lsu.scala:219:36] wire l_uop_14_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_6 = ldq_uop_14_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_7; // @[lsu.scala:219:36] wire l_uop_14_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_7 = ldq_uop_14_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_8; // @[lsu.scala:219:36] wire l_uop_14_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_8 = ldq_uop_14_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fu_code_9; // @[lsu.scala:219:36] wire l_uop_14_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_39_fu_code_9 = ldq_uop_14_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued; // @[lsu.scala:219:36] wire l_uop_14_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued = ldq_uop_14_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued_partial_agen = ldq_uop_14_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_14_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_issued_partial_dgen = ldq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_14_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_iw_p1_speculative_child = ldq_uop_14_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_14_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_iw_p2_speculative_child = ldq_uop_14_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p1_bypass_hint = ldq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p2_bypass_hint = ldq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_14_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_39_iw_p3_bypass_hint = ldq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_dis_col_sel = ldq_uop_14_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_14_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_14_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_39_br_mask = ldq_uop_14_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_39_br_tag = ldq_uop_14_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_14_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_14_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_39_br_type = ldq_uop_14_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfb; // @[lsu.scala:219:36] wire l_uop_14_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sfb = ldq_uop_14_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fence; // @[lsu.scala:219:36] wire l_uop_14_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_fence = ldq_uop_14_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_fencei; // @[lsu.scala:219:36] wire l_uop_14_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_fencei = ldq_uop_14_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sfence; // @[lsu.scala:219:36] wire l_uop_14_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sfence = ldq_uop_14_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_amo; // @[lsu.scala:219:36] wire l_uop_14_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_amo = ldq_uop_14_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_eret; // @[lsu.scala:219:36] wire l_uop_14_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_eret = ldq_uop_14_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_14_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_sys_pc2epc = ldq_uop_14_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_rocc; // @[lsu.scala:219:36] wire l_uop_14_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_rocc = ldq_uop_14_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_mov; // @[lsu.scala:219:36] wire l_uop_14_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_mov = ldq_uop_14_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ftq_idx = ldq_uop_14_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_edge_inst; // @[lsu.scala:219:36] wire l_uop_14_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_39_edge_inst = ldq_uop_14_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_14_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_pc_lob = ldq_uop_14_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_taken; // @[lsu.scala:219:36] wire l_uop_14_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1191:37] wire uop_39_taken = ldq_uop_14_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_imm_rename; // @[lsu.scala:219:36] wire l_uop_14_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_39_imm_rename = ldq_uop_14_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_imm_sel = ldq_uop_14_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_14_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_pimm = ldq_uop_14_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_14_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_14_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_39_imm_packed = ldq_uop_14_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_14_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_op1_sel = ldq_uop_14_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_14_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_op2_sel = ldq_uop_14_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ldst = ldq_uop_14_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_wen = ldq_uop_14_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren1 = ldq_uop_14_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren2 = ldq_uop_14_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_ren3 = ldq_uop_14_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_swap12 = ldq_uop_14_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_swap23 = ldq_uop_14_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_ctrl_typeTagIn = ldq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_ctrl_typeTagOut = ldq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fromint = ldq_uop_14_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_toint = ldq_uop_14_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fastpipe = ldq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_fma = ldq_uop_14_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_div = ldq_uop_14_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_sqrt = ldq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_wflags = ldq_uop_14_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_14_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_ctrl_vec = ldq_uop_14_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_14_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_rob_idx = ldq_uop_14_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ldq_idx = ldq_uop_14_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_14_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_stq_idx = ldq_uop_14_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_14_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_rxq_idx = ldq_uop_14_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_pdst = ldq_uop_14_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs1 = ldq_uop_14_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs2 = ldq_uop_14_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_14_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_prs3 = ldq_uop_14_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_14_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_ppred = ldq_uop_14_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs1_busy; // @[lsu.scala:219:36] wire l_uop_14_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs1_busy = ldq_uop_14_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs2_busy; // @[lsu.scala:219:36] wire l_uop_14_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs2_busy = ldq_uop_14_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_prs3_busy; // @[lsu.scala:219:36] wire l_uop_14_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_prs3_busy = ldq_uop_14_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ppred_busy; // @[lsu.scala:219:36] wire l_uop_14_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_39_ppred_busy = ldq_uop_14_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_14_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_14_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_39_stale_pdst = ldq_uop_14_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_exception; // @[lsu.scala:219:36] wire l_uop_14_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1191:37] wire uop_39_exception = ldq_uop_14_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_14_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_14_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_39_exc_cause = ldq_uop_14_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_14_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_mem_cmd = ldq_uop_14_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_14_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_mem_size = ldq_uop_14_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_mem_signed; // @[lsu.scala:219:36] wire l_uop_14_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_39_mem_signed = ldq_uop_14_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_ldq; // @[lsu.scala:219:36] wire l_uop_14_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_39_uses_ldq = ldq_uop_14_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_uses_stq; // @[lsu.scala:219:36] wire l_uop_14_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_39_uses_stq = ldq_uop_14_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_is_unique; // @[lsu.scala:219:36] wire l_uop_14_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_39_is_unique = ldq_uop_14_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_14_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_39_flush_on_commit = ldq_uop_14_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_14_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_csr_cmd = ldq_uop_14_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_14_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_39_ldst_is_rs1 = ldq_uop_14_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_14_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_ldst = ldq_uop_14_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs1 = ldq_uop_14_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs2 = ldq_uop_14_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_14_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_14_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_39_lrs3 = ldq_uop_14_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_dst_rtype = ldq_uop_14_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_lrs1_rtype = ldq_uop_14_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_14_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_lrs2_rtype = ldq_uop_14_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_frs3_en; // @[lsu.scala:219:36] wire l_uop_14_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_39_frs3_en = ldq_uop_14_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fcn_dw; // @[lsu.scala:219:36] wire l_uop_14_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_39_fcn_dw = ldq_uop_14_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_14_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_14_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_39_fcn_op = ldq_uop_14_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_fp_val; // @[lsu.scala:219:36] wire l_uop_14_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_39_fp_val = ldq_uop_14_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_14_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_fp_rm = ldq_uop_14_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_14_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_14_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_39_fp_typ = ldq_uop_14_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_pf_if = ldq_uop_14_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_ae_if = ldq_uop_14_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_14_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_xcpt_ma_if = ldq_uop_14_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_14_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_bp_debug_if = ldq_uop_14_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_14_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_39_bp_xcpt_if = ldq_uop_14_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_debug_fsrc = ldq_uop_14_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_14_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_39_debug_tsrc = ldq_uop_14_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_40_inst = ldq_uop_15_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_15_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_15_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_40_debug_inst = ldq_uop_15_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rvc; // @[lsu.scala:219:36] wire l_uop_15_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_rvc = ldq_uop_15_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_15_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_15_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_40_debug_pc = ldq_uop_15_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_0; // @[lsu.scala:219:36] wire l_uop_15_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_0 = ldq_uop_15_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_1; // @[lsu.scala:219:36] wire l_uop_15_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_1 = ldq_uop_15_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_2; // @[lsu.scala:219:36] wire l_uop_15_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_2 = ldq_uop_15_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iq_type_3; // @[lsu.scala:219:36] wire l_uop_15_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_40_iq_type_3 = ldq_uop_15_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_0; // @[lsu.scala:219:36] wire l_uop_15_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_0 = ldq_uop_15_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_1; // @[lsu.scala:219:36] wire l_uop_15_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_1 = ldq_uop_15_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_2; // @[lsu.scala:219:36] wire l_uop_15_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_2 = ldq_uop_15_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_3; // @[lsu.scala:219:36] wire l_uop_15_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_3 = ldq_uop_15_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_4; // @[lsu.scala:219:36] wire l_uop_15_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_4 = ldq_uop_15_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_5; // @[lsu.scala:219:36] wire l_uop_15_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_5 = ldq_uop_15_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_6; // @[lsu.scala:219:36] wire l_uop_15_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_6 = ldq_uop_15_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_7; // @[lsu.scala:219:36] wire l_uop_15_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_7 = ldq_uop_15_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_8; // @[lsu.scala:219:36] wire l_uop_15_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_8 = ldq_uop_15_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fu_code_9; // @[lsu.scala:219:36] wire l_uop_15_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_40_fu_code_9 = ldq_uop_15_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued; // @[lsu.scala:219:36] wire l_uop_15_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued = ldq_uop_15_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued_partial_agen = ldq_uop_15_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_15_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_issued_partial_dgen = ldq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_15_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_iw_p1_speculative_child = ldq_uop_15_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_15_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_iw_p2_speculative_child = ldq_uop_15_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p1_bypass_hint = ldq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p2_bypass_hint = ldq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_15_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_40_iw_p3_bypass_hint = ldq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_dis_col_sel = ldq_uop_15_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_15_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_15_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_40_br_mask = ldq_uop_15_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_40_br_tag = ldq_uop_15_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_15_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_15_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_40_br_type = ldq_uop_15_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfb; // @[lsu.scala:219:36] wire l_uop_15_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sfb = ldq_uop_15_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fence; // @[lsu.scala:219:36] wire l_uop_15_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_fence = ldq_uop_15_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_fencei; // @[lsu.scala:219:36] wire l_uop_15_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_fencei = ldq_uop_15_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sfence; // @[lsu.scala:219:36] wire l_uop_15_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sfence = ldq_uop_15_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_amo; // @[lsu.scala:219:36] wire l_uop_15_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_amo = ldq_uop_15_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_eret; // @[lsu.scala:219:36] wire l_uop_15_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_eret = ldq_uop_15_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_15_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_sys_pc2epc = ldq_uop_15_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_rocc; // @[lsu.scala:219:36] wire l_uop_15_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_rocc = ldq_uop_15_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_mov; // @[lsu.scala:219:36] wire l_uop_15_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_mov = ldq_uop_15_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ftq_idx = ldq_uop_15_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_edge_inst; // @[lsu.scala:219:36] wire l_uop_15_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_40_edge_inst = ldq_uop_15_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_15_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_pc_lob = ldq_uop_15_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_taken; // @[lsu.scala:219:36] wire l_uop_15_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1191:37] wire uop_40_taken = ldq_uop_15_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_imm_rename; // @[lsu.scala:219:36] wire l_uop_15_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_40_imm_rename = ldq_uop_15_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_imm_sel = ldq_uop_15_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_15_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_pimm = ldq_uop_15_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_15_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_15_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_40_imm_packed = ldq_uop_15_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_15_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_op1_sel = ldq_uop_15_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_15_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_op2_sel = ldq_uop_15_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ldst = ldq_uop_15_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_wen = ldq_uop_15_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren1 = ldq_uop_15_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren2 = ldq_uop_15_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_ren3 = ldq_uop_15_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_swap12 = ldq_uop_15_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_swap23 = ldq_uop_15_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_ctrl_typeTagIn = ldq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_ctrl_typeTagOut = ldq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fromint = ldq_uop_15_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_toint = ldq_uop_15_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fastpipe = ldq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_fma = ldq_uop_15_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_div = ldq_uop_15_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_sqrt = ldq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_wflags = ldq_uop_15_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_15_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_ctrl_vec = ldq_uop_15_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_15_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_rob_idx = ldq_uop_15_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ldq_idx = ldq_uop_15_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_15_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_stq_idx = ldq_uop_15_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_15_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_rxq_idx = ldq_uop_15_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_pdst = ldq_uop_15_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs1 = ldq_uop_15_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs2 = ldq_uop_15_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_15_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_prs3 = ldq_uop_15_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_15_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_ppred = ldq_uop_15_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs1_busy; // @[lsu.scala:219:36] wire l_uop_15_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs1_busy = ldq_uop_15_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs2_busy; // @[lsu.scala:219:36] wire l_uop_15_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs2_busy = ldq_uop_15_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_prs3_busy; // @[lsu.scala:219:36] wire l_uop_15_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_prs3_busy = ldq_uop_15_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ppred_busy; // @[lsu.scala:219:36] wire l_uop_15_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_40_ppred_busy = ldq_uop_15_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_15_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_15_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_40_stale_pdst = ldq_uop_15_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_exception; // @[lsu.scala:219:36] wire l_uop_15_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1191:37] wire uop_40_exception = ldq_uop_15_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_15_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_15_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_40_exc_cause = ldq_uop_15_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_15_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_mem_cmd = ldq_uop_15_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_15_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_mem_size = ldq_uop_15_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_mem_signed; // @[lsu.scala:219:36] wire l_uop_15_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_40_mem_signed = ldq_uop_15_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_ldq; // @[lsu.scala:219:36] wire l_uop_15_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_40_uses_ldq = ldq_uop_15_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_uses_stq; // @[lsu.scala:219:36] wire l_uop_15_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_40_uses_stq = ldq_uop_15_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_is_unique; // @[lsu.scala:219:36] wire l_uop_15_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_40_is_unique = ldq_uop_15_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_15_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_40_flush_on_commit = ldq_uop_15_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_15_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_csr_cmd = ldq_uop_15_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_15_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_40_ldst_is_rs1 = ldq_uop_15_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_15_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_ldst = ldq_uop_15_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs1 = ldq_uop_15_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs2 = ldq_uop_15_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_15_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_15_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_40_lrs3 = ldq_uop_15_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_dst_rtype = ldq_uop_15_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_lrs1_rtype = ldq_uop_15_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_15_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_lrs2_rtype = ldq_uop_15_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_frs3_en; // @[lsu.scala:219:36] wire l_uop_15_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_40_frs3_en = ldq_uop_15_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fcn_dw; // @[lsu.scala:219:36] wire l_uop_15_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_40_fcn_dw = ldq_uop_15_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_15_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_15_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_40_fcn_op = ldq_uop_15_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_fp_val; // @[lsu.scala:219:36] wire l_uop_15_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_40_fp_val = ldq_uop_15_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_15_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_fp_rm = ldq_uop_15_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_15_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_15_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_40_fp_typ = ldq_uop_15_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_pf_if = ldq_uop_15_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_ae_if = ldq_uop_15_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_15_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_xcpt_ma_if = ldq_uop_15_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_15_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_bp_debug_if = ldq_uop_15_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_15_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_40_bp_xcpt_if = ldq_uop_15_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_debug_fsrc = ldq_uop_15_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_15_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_40_debug_tsrc = ldq_uop_15_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_16_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_16_inst = ldq_uop_16_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_41_inst = ldq_uop_16_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_16_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_16_debug_inst = ldq_uop_16_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_41_debug_inst = ldq_uop_16_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_rvc; // @[lsu.scala:219:36] wire l_uop_16_is_rvc = ldq_uop_16_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_rvc = ldq_uop_16_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_16_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_16_debug_pc = ldq_uop_16_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_41_debug_pc = ldq_uop_16_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_0; // @[lsu.scala:219:36] wire l_uop_16_iq_type_0 = ldq_uop_16_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_0 = ldq_uop_16_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_1; // @[lsu.scala:219:36] wire l_uop_16_iq_type_1 = ldq_uop_16_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_1 = ldq_uop_16_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_2; // @[lsu.scala:219:36] wire l_uop_16_iq_type_2 = ldq_uop_16_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_2 = ldq_uop_16_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iq_type_3; // @[lsu.scala:219:36] wire l_uop_16_iq_type_3 = ldq_uop_16_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_41_iq_type_3 = ldq_uop_16_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_0; // @[lsu.scala:219:36] wire l_uop_16_fu_code_0 = ldq_uop_16_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_0 = ldq_uop_16_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_1; // @[lsu.scala:219:36] wire l_uop_16_fu_code_1 = ldq_uop_16_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_1 = ldq_uop_16_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_2; // @[lsu.scala:219:36] wire l_uop_16_fu_code_2 = ldq_uop_16_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_2 = ldq_uop_16_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_3; // @[lsu.scala:219:36] wire l_uop_16_fu_code_3 = ldq_uop_16_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_3 = ldq_uop_16_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_4; // @[lsu.scala:219:36] wire l_uop_16_fu_code_4 = ldq_uop_16_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_4 = ldq_uop_16_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_5; // @[lsu.scala:219:36] wire l_uop_16_fu_code_5 = ldq_uop_16_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_5 = ldq_uop_16_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_6; // @[lsu.scala:219:36] wire l_uop_16_fu_code_6 = ldq_uop_16_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_6 = ldq_uop_16_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_7; // @[lsu.scala:219:36] wire l_uop_16_fu_code_7 = ldq_uop_16_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_7 = ldq_uop_16_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_8; // @[lsu.scala:219:36] wire l_uop_16_fu_code_8 = ldq_uop_16_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_8 = ldq_uop_16_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fu_code_9; // @[lsu.scala:219:36] wire l_uop_16_fu_code_9 = ldq_uop_16_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_41_fu_code_9 = ldq_uop_16_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued; // @[lsu.scala:219:36] wire l_uop_16_iw_issued = ldq_uop_16_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued = ldq_uop_16_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_16_iw_issued_partial_agen = ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued_partial_agen = ldq_uop_16_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_16_iw_issued_partial_dgen = ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_issued_partial_dgen = ldq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_16_iw_p1_speculative_child = ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_iw_p1_speculative_child = ldq_uop_16_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_16_iw_p2_speculative_child = ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_iw_p2_speculative_child = ldq_uop_16_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p1_bypass_hint = ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p1_bypass_hint = ldq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p2_bypass_hint = ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p2_bypass_hint = ldq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_16_iw_p3_bypass_hint = ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_41_iw_p3_bypass_hint = ldq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_dis_col_sel = ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_dis_col_sel = ldq_uop_16_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_16_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_16_br_mask = ldq_uop_16_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_41_br_mask = ldq_uop_16_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_16_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_16_br_tag = ldq_uop_16_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_41_br_tag = ldq_uop_16_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_16_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_16_br_type = ldq_uop_16_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_41_br_type = ldq_uop_16_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sfb; // @[lsu.scala:219:36] wire l_uop_16_is_sfb = ldq_uop_16_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sfb = ldq_uop_16_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_fence; // @[lsu.scala:219:36] wire l_uop_16_is_fence = ldq_uop_16_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_fence = ldq_uop_16_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_fencei; // @[lsu.scala:219:36] wire l_uop_16_is_fencei = ldq_uop_16_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_fencei = ldq_uop_16_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sfence; // @[lsu.scala:219:36] wire l_uop_16_is_sfence = ldq_uop_16_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sfence = ldq_uop_16_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_amo; // @[lsu.scala:219:36] wire l_uop_16_is_amo = ldq_uop_16_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_amo = ldq_uop_16_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_eret; // @[lsu.scala:219:36] wire l_uop_16_is_eret = ldq_uop_16_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_eret = ldq_uop_16_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_16_is_sys_pc2epc = ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_sys_pc2epc = ldq_uop_16_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_rocc; // @[lsu.scala:219:36] wire l_uop_16_is_rocc = ldq_uop_16_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_rocc = ldq_uop_16_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_mov; // @[lsu.scala:219:36] wire l_uop_16_is_mov = ldq_uop_16_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_mov = ldq_uop_16_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ftq_idx = ldq_uop_16_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ftq_idx = ldq_uop_16_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_edge_inst; // @[lsu.scala:219:36] wire l_uop_16_edge_inst = ldq_uop_16_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_41_edge_inst = ldq_uop_16_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_16_pc_lob = ldq_uop_16_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_pc_lob = ldq_uop_16_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_taken; // @[lsu.scala:219:36] wire l_uop_16_taken = ldq_uop_16_taken; // @[lsu.scala:219:36, :1191:37] wire uop_41_taken = ldq_uop_16_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_imm_rename; // @[lsu.scala:219:36] wire l_uop_16_imm_rename = ldq_uop_16_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_41_imm_rename = ldq_uop_16_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_imm_sel = ldq_uop_16_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_imm_sel = ldq_uop_16_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_16_pimm = ldq_uop_16_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_pimm = ldq_uop_16_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_16_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_16_imm_packed = ldq_uop_16_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_41_imm_packed = ldq_uop_16_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_16_op1_sel = ldq_uop_16_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_op1_sel = ldq_uop_16_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_16_op2_sel = ldq_uop_16_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_op2_sel = ldq_uop_16_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ldst = ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ldst = ldq_uop_16_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_wen = ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_wen = ldq_uop_16_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren1 = ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren1 = ldq_uop_16_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren2 = ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren2 = ldq_uop_16_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_ren3 = ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_ren3 = ldq_uop_16_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_swap12 = ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_swap12 = ldq_uop_16_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_swap23 = ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_swap23 = ldq_uop_16_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_ctrl_typeTagIn = ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_ctrl_typeTagIn = ldq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_ctrl_typeTagOut = ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_ctrl_typeTagOut = ldq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fromint = ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fromint = ldq_uop_16_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_toint = ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_toint = ldq_uop_16_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fastpipe = ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fastpipe = ldq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_fma = ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_fma = ldq_uop_16_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_div = ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_div = ldq_uop_16_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_sqrt = ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_sqrt = ldq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_wflags = ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_wflags = ldq_uop_16_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_16_fp_ctrl_vec = ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_ctrl_vec = ldq_uop_16_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_16_rob_idx = ldq_uop_16_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_rob_idx = ldq_uop_16_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ldq_idx = ldq_uop_16_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ldq_idx = ldq_uop_16_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_16_stq_idx = ldq_uop_16_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_stq_idx = ldq_uop_16_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_16_rxq_idx = ldq_uop_16_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_rxq_idx = ldq_uop_16_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_16_pdst = ldq_uop_16_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_pdst = ldq_uop_16_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs1 = ldq_uop_16_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs1 = ldq_uop_16_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs2 = ldq_uop_16_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs2 = ldq_uop_16_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_16_prs3 = ldq_uop_16_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_prs3 = ldq_uop_16_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_16_ppred = ldq_uop_16_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_ppred = ldq_uop_16_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs1_busy; // @[lsu.scala:219:36] wire l_uop_16_prs1_busy = ldq_uop_16_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs1_busy = ldq_uop_16_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs2_busy; // @[lsu.scala:219:36] wire l_uop_16_prs2_busy = ldq_uop_16_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs2_busy = ldq_uop_16_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_prs3_busy; // @[lsu.scala:219:36] wire l_uop_16_prs3_busy = ldq_uop_16_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_prs3_busy = ldq_uop_16_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_ppred_busy; // @[lsu.scala:219:36] wire l_uop_16_ppred_busy = ldq_uop_16_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_41_ppred_busy = ldq_uop_16_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_16_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_16_stale_pdst = ldq_uop_16_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_41_stale_pdst = ldq_uop_16_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_exception; // @[lsu.scala:219:36] wire l_uop_16_exception = ldq_uop_16_exception; // @[lsu.scala:219:36, :1191:37] wire uop_41_exception = ldq_uop_16_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_16_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_16_exc_cause = ldq_uop_16_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_41_exc_cause = ldq_uop_16_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_16_mem_cmd = ldq_uop_16_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_mem_cmd = ldq_uop_16_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_16_mem_size = ldq_uop_16_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_mem_size = ldq_uop_16_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_mem_signed; // @[lsu.scala:219:36] wire l_uop_16_mem_signed = ldq_uop_16_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_41_mem_signed = ldq_uop_16_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_uses_ldq; // @[lsu.scala:219:36] wire l_uop_16_uses_ldq = ldq_uop_16_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_41_uses_ldq = ldq_uop_16_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_uses_stq; // @[lsu.scala:219:36] wire l_uop_16_uses_stq = ldq_uop_16_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_41_uses_stq = ldq_uop_16_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_is_unique; // @[lsu.scala:219:36] wire l_uop_16_is_unique = ldq_uop_16_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_41_is_unique = ldq_uop_16_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_16_flush_on_commit = ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_41_flush_on_commit = ldq_uop_16_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_16_csr_cmd = ldq_uop_16_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_csr_cmd = ldq_uop_16_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_16_ldst_is_rs1 = ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_41_ldst_is_rs1 = ldq_uop_16_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_16_ldst = ldq_uop_16_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_ldst = ldq_uop_16_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs1 = ldq_uop_16_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs1 = ldq_uop_16_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs2 = ldq_uop_16_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs2 = ldq_uop_16_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_16_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_16_lrs3 = ldq_uop_16_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_41_lrs3 = ldq_uop_16_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_dst_rtype = ldq_uop_16_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_dst_rtype = ldq_uop_16_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_lrs1_rtype = ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_lrs1_rtype = ldq_uop_16_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_16_lrs2_rtype = ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_lrs2_rtype = ldq_uop_16_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_frs3_en; // @[lsu.scala:219:36] wire l_uop_16_frs3_en = ldq_uop_16_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_41_frs3_en = ldq_uop_16_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fcn_dw; // @[lsu.scala:219:36] wire l_uop_16_fcn_dw = ldq_uop_16_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_41_fcn_dw = ldq_uop_16_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_16_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_16_fcn_op = ldq_uop_16_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_41_fcn_op = ldq_uop_16_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_fp_val; // @[lsu.scala:219:36] wire l_uop_16_fp_val = ldq_uop_16_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_41_fp_val = ldq_uop_16_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_16_fp_rm = ldq_uop_16_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_fp_rm = ldq_uop_16_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_16_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_16_fp_typ = ldq_uop_16_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_41_fp_typ = ldq_uop_16_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_pf_if = ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_pf_if = ldq_uop_16_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_ae_if = ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_ae_if = ldq_uop_16_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_16_xcpt_ma_if = ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_xcpt_ma_if = ldq_uop_16_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_16_bp_debug_if = ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_bp_debug_if = ldq_uop_16_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_16_bp_xcpt_if = ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_41_bp_xcpt_if = ldq_uop_16_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_16_debug_fsrc = ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_debug_fsrc = ldq_uop_16_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_16_debug_tsrc = ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_41_debug_tsrc = ldq_uop_16_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_17_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_17_inst = ldq_uop_17_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_42_inst = ldq_uop_17_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_17_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_17_debug_inst = ldq_uop_17_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_42_debug_inst = ldq_uop_17_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_rvc; // @[lsu.scala:219:36] wire l_uop_17_is_rvc = ldq_uop_17_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_rvc = ldq_uop_17_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_17_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_17_debug_pc = ldq_uop_17_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_42_debug_pc = ldq_uop_17_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_0; // @[lsu.scala:219:36] wire l_uop_17_iq_type_0 = ldq_uop_17_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_0 = ldq_uop_17_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_1; // @[lsu.scala:219:36] wire l_uop_17_iq_type_1 = ldq_uop_17_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_1 = ldq_uop_17_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_2; // @[lsu.scala:219:36] wire l_uop_17_iq_type_2 = ldq_uop_17_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_2 = ldq_uop_17_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iq_type_3; // @[lsu.scala:219:36] wire l_uop_17_iq_type_3 = ldq_uop_17_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_42_iq_type_3 = ldq_uop_17_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_0; // @[lsu.scala:219:36] wire l_uop_17_fu_code_0 = ldq_uop_17_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_0 = ldq_uop_17_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_1; // @[lsu.scala:219:36] wire l_uop_17_fu_code_1 = ldq_uop_17_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_1 = ldq_uop_17_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_2; // @[lsu.scala:219:36] wire l_uop_17_fu_code_2 = ldq_uop_17_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_2 = ldq_uop_17_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_3; // @[lsu.scala:219:36] wire l_uop_17_fu_code_3 = ldq_uop_17_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_3 = ldq_uop_17_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_4; // @[lsu.scala:219:36] wire l_uop_17_fu_code_4 = ldq_uop_17_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_4 = ldq_uop_17_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_5; // @[lsu.scala:219:36] wire l_uop_17_fu_code_5 = ldq_uop_17_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_5 = ldq_uop_17_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_6; // @[lsu.scala:219:36] wire l_uop_17_fu_code_6 = ldq_uop_17_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_6 = ldq_uop_17_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_7; // @[lsu.scala:219:36] wire l_uop_17_fu_code_7 = ldq_uop_17_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_7 = ldq_uop_17_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_8; // @[lsu.scala:219:36] wire l_uop_17_fu_code_8 = ldq_uop_17_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_8 = ldq_uop_17_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fu_code_9; // @[lsu.scala:219:36] wire l_uop_17_fu_code_9 = ldq_uop_17_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_42_fu_code_9 = ldq_uop_17_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued; // @[lsu.scala:219:36] wire l_uop_17_iw_issued = ldq_uop_17_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued = ldq_uop_17_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_17_iw_issued_partial_agen = ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued_partial_agen = ldq_uop_17_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_17_iw_issued_partial_dgen = ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_issued_partial_dgen = ldq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_17_iw_p1_speculative_child = ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_iw_p1_speculative_child = ldq_uop_17_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_17_iw_p2_speculative_child = ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_iw_p2_speculative_child = ldq_uop_17_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p1_bypass_hint = ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p1_bypass_hint = ldq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p2_bypass_hint = ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p2_bypass_hint = ldq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_17_iw_p3_bypass_hint = ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_42_iw_p3_bypass_hint = ldq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_dis_col_sel = ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_dis_col_sel = ldq_uop_17_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_17_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_17_br_mask = ldq_uop_17_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_42_br_mask = ldq_uop_17_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_17_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_17_br_tag = ldq_uop_17_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_42_br_tag = ldq_uop_17_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_17_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_17_br_type = ldq_uop_17_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_42_br_type = ldq_uop_17_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sfb; // @[lsu.scala:219:36] wire l_uop_17_is_sfb = ldq_uop_17_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sfb = ldq_uop_17_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_fence; // @[lsu.scala:219:36] wire l_uop_17_is_fence = ldq_uop_17_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_fence = ldq_uop_17_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_fencei; // @[lsu.scala:219:36] wire l_uop_17_is_fencei = ldq_uop_17_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_fencei = ldq_uop_17_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sfence; // @[lsu.scala:219:36] wire l_uop_17_is_sfence = ldq_uop_17_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sfence = ldq_uop_17_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_amo; // @[lsu.scala:219:36] wire l_uop_17_is_amo = ldq_uop_17_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_amo = ldq_uop_17_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_eret; // @[lsu.scala:219:36] wire l_uop_17_is_eret = ldq_uop_17_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_eret = ldq_uop_17_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_17_is_sys_pc2epc = ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_sys_pc2epc = ldq_uop_17_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_rocc; // @[lsu.scala:219:36] wire l_uop_17_is_rocc = ldq_uop_17_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_rocc = ldq_uop_17_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_mov; // @[lsu.scala:219:36] wire l_uop_17_is_mov = ldq_uop_17_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_mov = ldq_uop_17_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ftq_idx = ldq_uop_17_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ftq_idx = ldq_uop_17_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_edge_inst; // @[lsu.scala:219:36] wire l_uop_17_edge_inst = ldq_uop_17_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_42_edge_inst = ldq_uop_17_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_17_pc_lob = ldq_uop_17_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_pc_lob = ldq_uop_17_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_taken; // @[lsu.scala:219:36] wire l_uop_17_taken = ldq_uop_17_taken; // @[lsu.scala:219:36, :1191:37] wire uop_42_taken = ldq_uop_17_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_imm_rename; // @[lsu.scala:219:36] wire l_uop_17_imm_rename = ldq_uop_17_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_42_imm_rename = ldq_uop_17_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_imm_sel = ldq_uop_17_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_imm_sel = ldq_uop_17_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_17_pimm = ldq_uop_17_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_pimm = ldq_uop_17_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_17_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_17_imm_packed = ldq_uop_17_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_42_imm_packed = ldq_uop_17_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_17_op1_sel = ldq_uop_17_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_op1_sel = ldq_uop_17_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_17_op2_sel = ldq_uop_17_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_op2_sel = ldq_uop_17_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ldst = ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ldst = ldq_uop_17_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_wen = ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_wen = ldq_uop_17_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren1 = ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren1 = ldq_uop_17_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren2 = ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren2 = ldq_uop_17_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_ren3 = ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_ren3 = ldq_uop_17_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_swap12 = ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_swap12 = ldq_uop_17_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_swap23 = ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_swap23 = ldq_uop_17_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_ctrl_typeTagIn = ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_ctrl_typeTagIn = ldq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_ctrl_typeTagOut = ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_ctrl_typeTagOut = ldq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fromint = ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fromint = ldq_uop_17_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_toint = ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_toint = ldq_uop_17_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fastpipe = ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fastpipe = ldq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_fma = ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_fma = ldq_uop_17_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_div = ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_div = ldq_uop_17_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_sqrt = ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_sqrt = ldq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_wflags = ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_wflags = ldq_uop_17_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_17_fp_ctrl_vec = ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_ctrl_vec = ldq_uop_17_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_17_rob_idx = ldq_uop_17_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_rob_idx = ldq_uop_17_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ldq_idx = ldq_uop_17_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ldq_idx = ldq_uop_17_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_17_stq_idx = ldq_uop_17_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_stq_idx = ldq_uop_17_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_17_rxq_idx = ldq_uop_17_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_rxq_idx = ldq_uop_17_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_17_pdst = ldq_uop_17_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_pdst = ldq_uop_17_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs1 = ldq_uop_17_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs1 = ldq_uop_17_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs2 = ldq_uop_17_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs2 = ldq_uop_17_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_17_prs3 = ldq_uop_17_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_prs3 = ldq_uop_17_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_17_ppred = ldq_uop_17_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_ppred = ldq_uop_17_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs1_busy; // @[lsu.scala:219:36] wire l_uop_17_prs1_busy = ldq_uop_17_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs1_busy = ldq_uop_17_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs2_busy; // @[lsu.scala:219:36] wire l_uop_17_prs2_busy = ldq_uop_17_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs2_busy = ldq_uop_17_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_prs3_busy; // @[lsu.scala:219:36] wire l_uop_17_prs3_busy = ldq_uop_17_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_prs3_busy = ldq_uop_17_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_ppred_busy; // @[lsu.scala:219:36] wire l_uop_17_ppred_busy = ldq_uop_17_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_42_ppred_busy = ldq_uop_17_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_17_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_17_stale_pdst = ldq_uop_17_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_42_stale_pdst = ldq_uop_17_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_exception; // @[lsu.scala:219:36] wire l_uop_17_exception = ldq_uop_17_exception; // @[lsu.scala:219:36, :1191:37] wire uop_42_exception = ldq_uop_17_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_17_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_17_exc_cause = ldq_uop_17_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_42_exc_cause = ldq_uop_17_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_17_mem_cmd = ldq_uop_17_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_mem_cmd = ldq_uop_17_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_17_mem_size = ldq_uop_17_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_mem_size = ldq_uop_17_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_mem_signed; // @[lsu.scala:219:36] wire l_uop_17_mem_signed = ldq_uop_17_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_42_mem_signed = ldq_uop_17_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_uses_ldq; // @[lsu.scala:219:36] wire l_uop_17_uses_ldq = ldq_uop_17_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_42_uses_ldq = ldq_uop_17_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_uses_stq; // @[lsu.scala:219:36] wire l_uop_17_uses_stq = ldq_uop_17_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_42_uses_stq = ldq_uop_17_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_is_unique; // @[lsu.scala:219:36] wire l_uop_17_is_unique = ldq_uop_17_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_42_is_unique = ldq_uop_17_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_17_flush_on_commit = ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_42_flush_on_commit = ldq_uop_17_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_17_csr_cmd = ldq_uop_17_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_csr_cmd = ldq_uop_17_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_17_ldst_is_rs1 = ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_42_ldst_is_rs1 = ldq_uop_17_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_17_ldst = ldq_uop_17_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_ldst = ldq_uop_17_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs1 = ldq_uop_17_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs1 = ldq_uop_17_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs2 = ldq_uop_17_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs2 = ldq_uop_17_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_17_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_17_lrs3 = ldq_uop_17_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_42_lrs3 = ldq_uop_17_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_dst_rtype = ldq_uop_17_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_dst_rtype = ldq_uop_17_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_lrs1_rtype = ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_lrs1_rtype = ldq_uop_17_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_17_lrs2_rtype = ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_lrs2_rtype = ldq_uop_17_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_frs3_en; // @[lsu.scala:219:36] wire l_uop_17_frs3_en = ldq_uop_17_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_42_frs3_en = ldq_uop_17_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fcn_dw; // @[lsu.scala:219:36] wire l_uop_17_fcn_dw = ldq_uop_17_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_42_fcn_dw = ldq_uop_17_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_17_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_17_fcn_op = ldq_uop_17_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_42_fcn_op = ldq_uop_17_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_fp_val; // @[lsu.scala:219:36] wire l_uop_17_fp_val = ldq_uop_17_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_42_fp_val = ldq_uop_17_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_17_fp_rm = ldq_uop_17_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_fp_rm = ldq_uop_17_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_17_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_17_fp_typ = ldq_uop_17_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_42_fp_typ = ldq_uop_17_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_pf_if = ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_pf_if = ldq_uop_17_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_ae_if = ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_ae_if = ldq_uop_17_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_17_xcpt_ma_if = ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_xcpt_ma_if = ldq_uop_17_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_17_bp_debug_if = ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_bp_debug_if = ldq_uop_17_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_17_bp_xcpt_if = ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_42_bp_xcpt_if = ldq_uop_17_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_17_debug_fsrc = ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_debug_fsrc = ldq_uop_17_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_17_debug_tsrc = ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_42_debug_tsrc = ldq_uop_17_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_18_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_18_inst = ldq_uop_18_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_43_inst = ldq_uop_18_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_18_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_18_debug_inst = ldq_uop_18_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_43_debug_inst = ldq_uop_18_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_rvc; // @[lsu.scala:219:36] wire l_uop_18_is_rvc = ldq_uop_18_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_rvc = ldq_uop_18_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_18_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_18_debug_pc = ldq_uop_18_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_43_debug_pc = ldq_uop_18_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_0; // @[lsu.scala:219:36] wire l_uop_18_iq_type_0 = ldq_uop_18_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_0 = ldq_uop_18_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_1; // @[lsu.scala:219:36] wire l_uop_18_iq_type_1 = ldq_uop_18_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_1 = ldq_uop_18_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_2; // @[lsu.scala:219:36] wire l_uop_18_iq_type_2 = ldq_uop_18_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_2 = ldq_uop_18_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iq_type_3; // @[lsu.scala:219:36] wire l_uop_18_iq_type_3 = ldq_uop_18_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_43_iq_type_3 = ldq_uop_18_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_0; // @[lsu.scala:219:36] wire l_uop_18_fu_code_0 = ldq_uop_18_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_0 = ldq_uop_18_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_1; // @[lsu.scala:219:36] wire l_uop_18_fu_code_1 = ldq_uop_18_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_1 = ldq_uop_18_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_2; // @[lsu.scala:219:36] wire l_uop_18_fu_code_2 = ldq_uop_18_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_2 = ldq_uop_18_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_3; // @[lsu.scala:219:36] wire l_uop_18_fu_code_3 = ldq_uop_18_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_3 = ldq_uop_18_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_4; // @[lsu.scala:219:36] wire l_uop_18_fu_code_4 = ldq_uop_18_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_4 = ldq_uop_18_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_5; // @[lsu.scala:219:36] wire l_uop_18_fu_code_5 = ldq_uop_18_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_5 = ldq_uop_18_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_6; // @[lsu.scala:219:36] wire l_uop_18_fu_code_6 = ldq_uop_18_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_6 = ldq_uop_18_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_7; // @[lsu.scala:219:36] wire l_uop_18_fu_code_7 = ldq_uop_18_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_7 = ldq_uop_18_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_8; // @[lsu.scala:219:36] wire l_uop_18_fu_code_8 = ldq_uop_18_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_8 = ldq_uop_18_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fu_code_9; // @[lsu.scala:219:36] wire l_uop_18_fu_code_9 = ldq_uop_18_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_43_fu_code_9 = ldq_uop_18_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued; // @[lsu.scala:219:36] wire l_uop_18_iw_issued = ldq_uop_18_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued = ldq_uop_18_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_18_iw_issued_partial_agen = ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued_partial_agen = ldq_uop_18_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_18_iw_issued_partial_dgen = ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_issued_partial_dgen = ldq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_18_iw_p1_speculative_child = ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_iw_p1_speculative_child = ldq_uop_18_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_18_iw_p2_speculative_child = ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_iw_p2_speculative_child = ldq_uop_18_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p1_bypass_hint = ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p1_bypass_hint = ldq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p2_bypass_hint = ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p2_bypass_hint = ldq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_18_iw_p3_bypass_hint = ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_43_iw_p3_bypass_hint = ldq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_dis_col_sel = ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_dis_col_sel = ldq_uop_18_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_18_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_18_br_mask = ldq_uop_18_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_43_br_mask = ldq_uop_18_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_18_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_18_br_tag = ldq_uop_18_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_43_br_tag = ldq_uop_18_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_18_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_18_br_type = ldq_uop_18_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_43_br_type = ldq_uop_18_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sfb; // @[lsu.scala:219:36] wire l_uop_18_is_sfb = ldq_uop_18_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sfb = ldq_uop_18_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_fence; // @[lsu.scala:219:36] wire l_uop_18_is_fence = ldq_uop_18_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_fence = ldq_uop_18_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_fencei; // @[lsu.scala:219:36] wire l_uop_18_is_fencei = ldq_uop_18_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_fencei = ldq_uop_18_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sfence; // @[lsu.scala:219:36] wire l_uop_18_is_sfence = ldq_uop_18_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sfence = ldq_uop_18_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_amo; // @[lsu.scala:219:36] wire l_uop_18_is_amo = ldq_uop_18_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_amo = ldq_uop_18_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_eret; // @[lsu.scala:219:36] wire l_uop_18_is_eret = ldq_uop_18_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_eret = ldq_uop_18_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_18_is_sys_pc2epc = ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_sys_pc2epc = ldq_uop_18_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_rocc; // @[lsu.scala:219:36] wire l_uop_18_is_rocc = ldq_uop_18_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_rocc = ldq_uop_18_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_mov; // @[lsu.scala:219:36] wire l_uop_18_is_mov = ldq_uop_18_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_mov = ldq_uop_18_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ftq_idx = ldq_uop_18_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ftq_idx = ldq_uop_18_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_edge_inst; // @[lsu.scala:219:36] wire l_uop_18_edge_inst = ldq_uop_18_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_43_edge_inst = ldq_uop_18_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_18_pc_lob = ldq_uop_18_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_pc_lob = ldq_uop_18_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_taken; // @[lsu.scala:219:36] wire l_uop_18_taken = ldq_uop_18_taken; // @[lsu.scala:219:36, :1191:37] wire uop_43_taken = ldq_uop_18_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_imm_rename; // @[lsu.scala:219:36] wire l_uop_18_imm_rename = ldq_uop_18_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_43_imm_rename = ldq_uop_18_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_imm_sel = ldq_uop_18_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_imm_sel = ldq_uop_18_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_18_pimm = ldq_uop_18_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_pimm = ldq_uop_18_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_18_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_18_imm_packed = ldq_uop_18_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_43_imm_packed = ldq_uop_18_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_18_op1_sel = ldq_uop_18_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_op1_sel = ldq_uop_18_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_18_op2_sel = ldq_uop_18_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_op2_sel = ldq_uop_18_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ldst = ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ldst = ldq_uop_18_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_wen = ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_wen = ldq_uop_18_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren1 = ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren1 = ldq_uop_18_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren2 = ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren2 = ldq_uop_18_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_ren3 = ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_ren3 = ldq_uop_18_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_swap12 = ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_swap12 = ldq_uop_18_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_swap23 = ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_swap23 = ldq_uop_18_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_ctrl_typeTagIn = ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_ctrl_typeTagIn = ldq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_ctrl_typeTagOut = ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_ctrl_typeTagOut = ldq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fromint = ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fromint = ldq_uop_18_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_toint = ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_toint = ldq_uop_18_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fastpipe = ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fastpipe = ldq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_fma = ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_fma = ldq_uop_18_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_div = ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_div = ldq_uop_18_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_sqrt = ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_sqrt = ldq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_wflags = ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_wflags = ldq_uop_18_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_18_fp_ctrl_vec = ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_ctrl_vec = ldq_uop_18_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_18_rob_idx = ldq_uop_18_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_rob_idx = ldq_uop_18_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ldq_idx = ldq_uop_18_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ldq_idx = ldq_uop_18_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_18_stq_idx = ldq_uop_18_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_stq_idx = ldq_uop_18_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_18_rxq_idx = ldq_uop_18_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_rxq_idx = ldq_uop_18_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_18_pdst = ldq_uop_18_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_pdst = ldq_uop_18_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs1 = ldq_uop_18_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs1 = ldq_uop_18_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs2 = ldq_uop_18_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs2 = ldq_uop_18_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_18_prs3 = ldq_uop_18_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_prs3 = ldq_uop_18_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_18_ppred = ldq_uop_18_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_ppred = ldq_uop_18_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs1_busy; // @[lsu.scala:219:36] wire l_uop_18_prs1_busy = ldq_uop_18_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs1_busy = ldq_uop_18_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs2_busy; // @[lsu.scala:219:36] wire l_uop_18_prs2_busy = ldq_uop_18_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs2_busy = ldq_uop_18_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_prs3_busy; // @[lsu.scala:219:36] wire l_uop_18_prs3_busy = ldq_uop_18_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_prs3_busy = ldq_uop_18_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_ppred_busy; // @[lsu.scala:219:36] wire l_uop_18_ppred_busy = ldq_uop_18_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_43_ppred_busy = ldq_uop_18_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_18_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_18_stale_pdst = ldq_uop_18_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_43_stale_pdst = ldq_uop_18_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_exception; // @[lsu.scala:219:36] wire l_uop_18_exception = ldq_uop_18_exception; // @[lsu.scala:219:36, :1191:37] wire uop_43_exception = ldq_uop_18_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_18_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_18_exc_cause = ldq_uop_18_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_43_exc_cause = ldq_uop_18_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_18_mem_cmd = ldq_uop_18_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_mem_cmd = ldq_uop_18_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_18_mem_size = ldq_uop_18_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_mem_size = ldq_uop_18_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_mem_signed; // @[lsu.scala:219:36] wire l_uop_18_mem_signed = ldq_uop_18_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_43_mem_signed = ldq_uop_18_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_uses_ldq; // @[lsu.scala:219:36] wire l_uop_18_uses_ldq = ldq_uop_18_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_43_uses_ldq = ldq_uop_18_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_uses_stq; // @[lsu.scala:219:36] wire l_uop_18_uses_stq = ldq_uop_18_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_43_uses_stq = ldq_uop_18_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_is_unique; // @[lsu.scala:219:36] wire l_uop_18_is_unique = ldq_uop_18_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_43_is_unique = ldq_uop_18_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_18_flush_on_commit = ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_43_flush_on_commit = ldq_uop_18_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_18_csr_cmd = ldq_uop_18_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_csr_cmd = ldq_uop_18_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_18_ldst_is_rs1 = ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_43_ldst_is_rs1 = ldq_uop_18_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_18_ldst = ldq_uop_18_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_ldst = ldq_uop_18_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs1 = ldq_uop_18_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs1 = ldq_uop_18_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs2 = ldq_uop_18_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs2 = ldq_uop_18_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_18_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_18_lrs3 = ldq_uop_18_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_43_lrs3 = ldq_uop_18_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_dst_rtype = ldq_uop_18_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_dst_rtype = ldq_uop_18_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_lrs1_rtype = ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_lrs1_rtype = ldq_uop_18_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_18_lrs2_rtype = ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_lrs2_rtype = ldq_uop_18_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_frs3_en; // @[lsu.scala:219:36] wire l_uop_18_frs3_en = ldq_uop_18_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_43_frs3_en = ldq_uop_18_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fcn_dw; // @[lsu.scala:219:36] wire l_uop_18_fcn_dw = ldq_uop_18_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_43_fcn_dw = ldq_uop_18_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_18_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_18_fcn_op = ldq_uop_18_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_43_fcn_op = ldq_uop_18_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_fp_val; // @[lsu.scala:219:36] wire l_uop_18_fp_val = ldq_uop_18_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_43_fp_val = ldq_uop_18_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_18_fp_rm = ldq_uop_18_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_fp_rm = ldq_uop_18_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_18_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_18_fp_typ = ldq_uop_18_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_43_fp_typ = ldq_uop_18_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_pf_if = ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_pf_if = ldq_uop_18_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_ae_if = ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_ae_if = ldq_uop_18_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_18_xcpt_ma_if = ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_xcpt_ma_if = ldq_uop_18_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_18_bp_debug_if = ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_bp_debug_if = ldq_uop_18_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_18_bp_xcpt_if = ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_43_bp_xcpt_if = ldq_uop_18_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_18_debug_fsrc = ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_debug_fsrc = ldq_uop_18_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_18_debug_tsrc = ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_43_debug_tsrc = ldq_uop_18_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_19_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_19_inst = ldq_uop_19_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_44_inst = ldq_uop_19_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_19_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_19_debug_inst = ldq_uop_19_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_44_debug_inst = ldq_uop_19_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_rvc; // @[lsu.scala:219:36] wire l_uop_19_is_rvc = ldq_uop_19_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_rvc = ldq_uop_19_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_19_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_19_debug_pc = ldq_uop_19_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_44_debug_pc = ldq_uop_19_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_0; // @[lsu.scala:219:36] wire l_uop_19_iq_type_0 = ldq_uop_19_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_0 = ldq_uop_19_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_1; // @[lsu.scala:219:36] wire l_uop_19_iq_type_1 = ldq_uop_19_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_1 = ldq_uop_19_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_2; // @[lsu.scala:219:36] wire l_uop_19_iq_type_2 = ldq_uop_19_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_2 = ldq_uop_19_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iq_type_3; // @[lsu.scala:219:36] wire l_uop_19_iq_type_3 = ldq_uop_19_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_44_iq_type_3 = ldq_uop_19_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_0; // @[lsu.scala:219:36] wire l_uop_19_fu_code_0 = ldq_uop_19_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_0 = ldq_uop_19_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_1; // @[lsu.scala:219:36] wire l_uop_19_fu_code_1 = ldq_uop_19_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_1 = ldq_uop_19_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_2; // @[lsu.scala:219:36] wire l_uop_19_fu_code_2 = ldq_uop_19_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_2 = ldq_uop_19_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_3; // @[lsu.scala:219:36] wire l_uop_19_fu_code_3 = ldq_uop_19_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_3 = ldq_uop_19_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_4; // @[lsu.scala:219:36] wire l_uop_19_fu_code_4 = ldq_uop_19_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_4 = ldq_uop_19_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_5; // @[lsu.scala:219:36] wire l_uop_19_fu_code_5 = ldq_uop_19_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_5 = ldq_uop_19_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_6; // @[lsu.scala:219:36] wire l_uop_19_fu_code_6 = ldq_uop_19_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_6 = ldq_uop_19_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_7; // @[lsu.scala:219:36] wire l_uop_19_fu_code_7 = ldq_uop_19_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_7 = ldq_uop_19_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_8; // @[lsu.scala:219:36] wire l_uop_19_fu_code_8 = ldq_uop_19_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_8 = ldq_uop_19_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fu_code_9; // @[lsu.scala:219:36] wire l_uop_19_fu_code_9 = ldq_uop_19_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_44_fu_code_9 = ldq_uop_19_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued; // @[lsu.scala:219:36] wire l_uop_19_iw_issued = ldq_uop_19_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued = ldq_uop_19_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_19_iw_issued_partial_agen = ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued_partial_agen = ldq_uop_19_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_19_iw_issued_partial_dgen = ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_issued_partial_dgen = ldq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_19_iw_p1_speculative_child = ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_iw_p1_speculative_child = ldq_uop_19_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_19_iw_p2_speculative_child = ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_iw_p2_speculative_child = ldq_uop_19_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p1_bypass_hint = ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p1_bypass_hint = ldq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p2_bypass_hint = ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p2_bypass_hint = ldq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_19_iw_p3_bypass_hint = ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_44_iw_p3_bypass_hint = ldq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_dis_col_sel = ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_dis_col_sel = ldq_uop_19_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_19_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_19_br_mask = ldq_uop_19_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_44_br_mask = ldq_uop_19_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_19_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_19_br_tag = ldq_uop_19_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_44_br_tag = ldq_uop_19_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_19_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_19_br_type = ldq_uop_19_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_44_br_type = ldq_uop_19_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sfb; // @[lsu.scala:219:36] wire l_uop_19_is_sfb = ldq_uop_19_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sfb = ldq_uop_19_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_fence; // @[lsu.scala:219:36] wire l_uop_19_is_fence = ldq_uop_19_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_fence = ldq_uop_19_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_fencei; // @[lsu.scala:219:36] wire l_uop_19_is_fencei = ldq_uop_19_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_fencei = ldq_uop_19_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sfence; // @[lsu.scala:219:36] wire l_uop_19_is_sfence = ldq_uop_19_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sfence = ldq_uop_19_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_amo; // @[lsu.scala:219:36] wire l_uop_19_is_amo = ldq_uop_19_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_amo = ldq_uop_19_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_eret; // @[lsu.scala:219:36] wire l_uop_19_is_eret = ldq_uop_19_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_eret = ldq_uop_19_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_19_is_sys_pc2epc = ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_sys_pc2epc = ldq_uop_19_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_rocc; // @[lsu.scala:219:36] wire l_uop_19_is_rocc = ldq_uop_19_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_rocc = ldq_uop_19_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_mov; // @[lsu.scala:219:36] wire l_uop_19_is_mov = ldq_uop_19_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_mov = ldq_uop_19_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ftq_idx = ldq_uop_19_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ftq_idx = ldq_uop_19_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_edge_inst; // @[lsu.scala:219:36] wire l_uop_19_edge_inst = ldq_uop_19_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_44_edge_inst = ldq_uop_19_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_19_pc_lob = ldq_uop_19_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_pc_lob = ldq_uop_19_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_taken; // @[lsu.scala:219:36] wire l_uop_19_taken = ldq_uop_19_taken; // @[lsu.scala:219:36, :1191:37] wire uop_44_taken = ldq_uop_19_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_imm_rename; // @[lsu.scala:219:36] wire l_uop_19_imm_rename = ldq_uop_19_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_44_imm_rename = ldq_uop_19_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_imm_sel = ldq_uop_19_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_imm_sel = ldq_uop_19_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_19_pimm = ldq_uop_19_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_pimm = ldq_uop_19_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_19_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_19_imm_packed = ldq_uop_19_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_44_imm_packed = ldq_uop_19_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_19_op1_sel = ldq_uop_19_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_op1_sel = ldq_uop_19_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_19_op2_sel = ldq_uop_19_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_op2_sel = ldq_uop_19_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ldst = ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ldst = ldq_uop_19_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_wen = ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_wen = ldq_uop_19_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren1 = ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren1 = ldq_uop_19_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren2 = ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren2 = ldq_uop_19_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_ren3 = ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_ren3 = ldq_uop_19_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_swap12 = ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_swap12 = ldq_uop_19_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_swap23 = ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_swap23 = ldq_uop_19_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_ctrl_typeTagIn = ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_ctrl_typeTagIn = ldq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_ctrl_typeTagOut = ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_ctrl_typeTagOut = ldq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fromint = ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fromint = ldq_uop_19_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_toint = ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_toint = ldq_uop_19_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fastpipe = ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fastpipe = ldq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_fma = ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_fma = ldq_uop_19_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_div = ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_div = ldq_uop_19_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_sqrt = ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_sqrt = ldq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_wflags = ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_wflags = ldq_uop_19_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_19_fp_ctrl_vec = ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_ctrl_vec = ldq_uop_19_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_19_rob_idx = ldq_uop_19_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_rob_idx = ldq_uop_19_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ldq_idx = ldq_uop_19_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ldq_idx = ldq_uop_19_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_19_stq_idx = ldq_uop_19_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_stq_idx = ldq_uop_19_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_19_rxq_idx = ldq_uop_19_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_rxq_idx = ldq_uop_19_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_19_pdst = ldq_uop_19_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_pdst = ldq_uop_19_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs1 = ldq_uop_19_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs1 = ldq_uop_19_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs2 = ldq_uop_19_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs2 = ldq_uop_19_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_19_prs3 = ldq_uop_19_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_prs3 = ldq_uop_19_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_19_ppred = ldq_uop_19_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_ppred = ldq_uop_19_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs1_busy; // @[lsu.scala:219:36] wire l_uop_19_prs1_busy = ldq_uop_19_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs1_busy = ldq_uop_19_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs2_busy; // @[lsu.scala:219:36] wire l_uop_19_prs2_busy = ldq_uop_19_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs2_busy = ldq_uop_19_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_prs3_busy; // @[lsu.scala:219:36] wire l_uop_19_prs3_busy = ldq_uop_19_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_prs3_busy = ldq_uop_19_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_ppred_busy; // @[lsu.scala:219:36] wire l_uop_19_ppred_busy = ldq_uop_19_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_44_ppred_busy = ldq_uop_19_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_19_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_19_stale_pdst = ldq_uop_19_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_44_stale_pdst = ldq_uop_19_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_exception; // @[lsu.scala:219:36] wire l_uop_19_exception = ldq_uop_19_exception; // @[lsu.scala:219:36, :1191:37] wire uop_44_exception = ldq_uop_19_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_19_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_19_exc_cause = ldq_uop_19_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_44_exc_cause = ldq_uop_19_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_19_mem_cmd = ldq_uop_19_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_mem_cmd = ldq_uop_19_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_19_mem_size = ldq_uop_19_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_mem_size = ldq_uop_19_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_mem_signed; // @[lsu.scala:219:36] wire l_uop_19_mem_signed = ldq_uop_19_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_44_mem_signed = ldq_uop_19_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_uses_ldq; // @[lsu.scala:219:36] wire l_uop_19_uses_ldq = ldq_uop_19_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_44_uses_ldq = ldq_uop_19_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_uses_stq; // @[lsu.scala:219:36] wire l_uop_19_uses_stq = ldq_uop_19_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_44_uses_stq = ldq_uop_19_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_is_unique; // @[lsu.scala:219:36] wire l_uop_19_is_unique = ldq_uop_19_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_44_is_unique = ldq_uop_19_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_19_flush_on_commit = ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_44_flush_on_commit = ldq_uop_19_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_19_csr_cmd = ldq_uop_19_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_csr_cmd = ldq_uop_19_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_19_ldst_is_rs1 = ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_44_ldst_is_rs1 = ldq_uop_19_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_19_ldst = ldq_uop_19_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_ldst = ldq_uop_19_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs1 = ldq_uop_19_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs1 = ldq_uop_19_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs2 = ldq_uop_19_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs2 = ldq_uop_19_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_19_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_19_lrs3 = ldq_uop_19_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_44_lrs3 = ldq_uop_19_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_dst_rtype = ldq_uop_19_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_dst_rtype = ldq_uop_19_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_lrs1_rtype = ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_lrs1_rtype = ldq_uop_19_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_19_lrs2_rtype = ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_lrs2_rtype = ldq_uop_19_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_frs3_en; // @[lsu.scala:219:36] wire l_uop_19_frs3_en = ldq_uop_19_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_44_frs3_en = ldq_uop_19_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fcn_dw; // @[lsu.scala:219:36] wire l_uop_19_fcn_dw = ldq_uop_19_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_44_fcn_dw = ldq_uop_19_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_19_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_19_fcn_op = ldq_uop_19_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_44_fcn_op = ldq_uop_19_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_fp_val; // @[lsu.scala:219:36] wire l_uop_19_fp_val = ldq_uop_19_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_44_fp_val = ldq_uop_19_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_19_fp_rm = ldq_uop_19_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_fp_rm = ldq_uop_19_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_19_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_19_fp_typ = ldq_uop_19_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_44_fp_typ = ldq_uop_19_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_pf_if = ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_pf_if = ldq_uop_19_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_ae_if = ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_ae_if = ldq_uop_19_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_19_xcpt_ma_if = ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_xcpt_ma_if = ldq_uop_19_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_19_bp_debug_if = ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_bp_debug_if = ldq_uop_19_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_19_bp_xcpt_if = ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_44_bp_xcpt_if = ldq_uop_19_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_19_debug_fsrc = ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_debug_fsrc = ldq_uop_19_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_19_debug_tsrc = ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_44_debug_tsrc = ldq_uop_19_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_20_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_20_inst = ldq_uop_20_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_45_inst = ldq_uop_20_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_20_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_20_debug_inst = ldq_uop_20_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_45_debug_inst = ldq_uop_20_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_rvc; // @[lsu.scala:219:36] wire l_uop_20_is_rvc = ldq_uop_20_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_rvc = ldq_uop_20_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_20_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_20_debug_pc = ldq_uop_20_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_45_debug_pc = ldq_uop_20_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_0; // @[lsu.scala:219:36] wire l_uop_20_iq_type_0 = ldq_uop_20_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_0 = ldq_uop_20_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_1; // @[lsu.scala:219:36] wire l_uop_20_iq_type_1 = ldq_uop_20_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_1 = ldq_uop_20_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_2; // @[lsu.scala:219:36] wire l_uop_20_iq_type_2 = ldq_uop_20_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_2 = ldq_uop_20_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iq_type_3; // @[lsu.scala:219:36] wire l_uop_20_iq_type_3 = ldq_uop_20_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_45_iq_type_3 = ldq_uop_20_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_0; // @[lsu.scala:219:36] wire l_uop_20_fu_code_0 = ldq_uop_20_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_0 = ldq_uop_20_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_1; // @[lsu.scala:219:36] wire l_uop_20_fu_code_1 = ldq_uop_20_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_1 = ldq_uop_20_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_2; // @[lsu.scala:219:36] wire l_uop_20_fu_code_2 = ldq_uop_20_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_2 = ldq_uop_20_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_3; // @[lsu.scala:219:36] wire l_uop_20_fu_code_3 = ldq_uop_20_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_3 = ldq_uop_20_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_4; // @[lsu.scala:219:36] wire l_uop_20_fu_code_4 = ldq_uop_20_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_4 = ldq_uop_20_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_5; // @[lsu.scala:219:36] wire l_uop_20_fu_code_5 = ldq_uop_20_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_5 = ldq_uop_20_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_6; // @[lsu.scala:219:36] wire l_uop_20_fu_code_6 = ldq_uop_20_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_6 = ldq_uop_20_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_7; // @[lsu.scala:219:36] wire l_uop_20_fu_code_7 = ldq_uop_20_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_7 = ldq_uop_20_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_8; // @[lsu.scala:219:36] wire l_uop_20_fu_code_8 = ldq_uop_20_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_8 = ldq_uop_20_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fu_code_9; // @[lsu.scala:219:36] wire l_uop_20_fu_code_9 = ldq_uop_20_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_45_fu_code_9 = ldq_uop_20_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued; // @[lsu.scala:219:36] wire l_uop_20_iw_issued = ldq_uop_20_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued = ldq_uop_20_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_20_iw_issued_partial_agen = ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued_partial_agen = ldq_uop_20_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_20_iw_issued_partial_dgen = ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_issued_partial_dgen = ldq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_20_iw_p1_speculative_child = ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_iw_p1_speculative_child = ldq_uop_20_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_20_iw_p2_speculative_child = ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_iw_p2_speculative_child = ldq_uop_20_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p1_bypass_hint = ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p1_bypass_hint = ldq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p2_bypass_hint = ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p2_bypass_hint = ldq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_20_iw_p3_bypass_hint = ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_45_iw_p3_bypass_hint = ldq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_dis_col_sel = ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_dis_col_sel = ldq_uop_20_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_20_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_20_br_mask = ldq_uop_20_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_45_br_mask = ldq_uop_20_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_20_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_20_br_tag = ldq_uop_20_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_45_br_tag = ldq_uop_20_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_20_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_20_br_type = ldq_uop_20_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_45_br_type = ldq_uop_20_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sfb; // @[lsu.scala:219:36] wire l_uop_20_is_sfb = ldq_uop_20_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sfb = ldq_uop_20_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_fence; // @[lsu.scala:219:36] wire l_uop_20_is_fence = ldq_uop_20_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_fence = ldq_uop_20_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_fencei; // @[lsu.scala:219:36] wire l_uop_20_is_fencei = ldq_uop_20_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_fencei = ldq_uop_20_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sfence; // @[lsu.scala:219:36] wire l_uop_20_is_sfence = ldq_uop_20_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sfence = ldq_uop_20_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_amo; // @[lsu.scala:219:36] wire l_uop_20_is_amo = ldq_uop_20_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_amo = ldq_uop_20_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_eret; // @[lsu.scala:219:36] wire l_uop_20_is_eret = ldq_uop_20_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_eret = ldq_uop_20_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_20_is_sys_pc2epc = ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_sys_pc2epc = ldq_uop_20_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_rocc; // @[lsu.scala:219:36] wire l_uop_20_is_rocc = ldq_uop_20_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_rocc = ldq_uop_20_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_mov; // @[lsu.scala:219:36] wire l_uop_20_is_mov = ldq_uop_20_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_mov = ldq_uop_20_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ftq_idx = ldq_uop_20_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ftq_idx = ldq_uop_20_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_edge_inst; // @[lsu.scala:219:36] wire l_uop_20_edge_inst = ldq_uop_20_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_45_edge_inst = ldq_uop_20_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_20_pc_lob = ldq_uop_20_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_pc_lob = ldq_uop_20_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_taken; // @[lsu.scala:219:36] wire l_uop_20_taken = ldq_uop_20_taken; // @[lsu.scala:219:36, :1191:37] wire uop_45_taken = ldq_uop_20_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_imm_rename; // @[lsu.scala:219:36] wire l_uop_20_imm_rename = ldq_uop_20_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_45_imm_rename = ldq_uop_20_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_imm_sel = ldq_uop_20_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_imm_sel = ldq_uop_20_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_20_pimm = ldq_uop_20_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_pimm = ldq_uop_20_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_20_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_20_imm_packed = ldq_uop_20_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_45_imm_packed = ldq_uop_20_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_20_op1_sel = ldq_uop_20_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_op1_sel = ldq_uop_20_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_20_op2_sel = ldq_uop_20_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_op2_sel = ldq_uop_20_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ldst = ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ldst = ldq_uop_20_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_wen = ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_wen = ldq_uop_20_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren1 = ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren1 = ldq_uop_20_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren2 = ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren2 = ldq_uop_20_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_ren3 = ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_ren3 = ldq_uop_20_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_swap12 = ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_swap12 = ldq_uop_20_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_swap23 = ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_swap23 = ldq_uop_20_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_ctrl_typeTagIn = ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_ctrl_typeTagIn = ldq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_ctrl_typeTagOut = ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_ctrl_typeTagOut = ldq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fromint = ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fromint = ldq_uop_20_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_toint = ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_toint = ldq_uop_20_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fastpipe = ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fastpipe = ldq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_fma = ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_fma = ldq_uop_20_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_div = ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_div = ldq_uop_20_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_sqrt = ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_sqrt = ldq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_wflags = ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_wflags = ldq_uop_20_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_20_fp_ctrl_vec = ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_ctrl_vec = ldq_uop_20_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_20_rob_idx = ldq_uop_20_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_rob_idx = ldq_uop_20_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ldq_idx = ldq_uop_20_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ldq_idx = ldq_uop_20_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_20_stq_idx = ldq_uop_20_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_stq_idx = ldq_uop_20_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_20_rxq_idx = ldq_uop_20_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_rxq_idx = ldq_uop_20_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_20_pdst = ldq_uop_20_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_pdst = ldq_uop_20_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs1 = ldq_uop_20_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs1 = ldq_uop_20_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs2 = ldq_uop_20_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs2 = ldq_uop_20_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_20_prs3 = ldq_uop_20_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_prs3 = ldq_uop_20_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_20_ppred = ldq_uop_20_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_ppred = ldq_uop_20_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs1_busy; // @[lsu.scala:219:36] wire l_uop_20_prs1_busy = ldq_uop_20_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs1_busy = ldq_uop_20_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs2_busy; // @[lsu.scala:219:36] wire l_uop_20_prs2_busy = ldq_uop_20_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs2_busy = ldq_uop_20_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_prs3_busy; // @[lsu.scala:219:36] wire l_uop_20_prs3_busy = ldq_uop_20_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_prs3_busy = ldq_uop_20_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_ppred_busy; // @[lsu.scala:219:36] wire l_uop_20_ppred_busy = ldq_uop_20_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_45_ppred_busy = ldq_uop_20_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_20_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_20_stale_pdst = ldq_uop_20_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_45_stale_pdst = ldq_uop_20_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_exception; // @[lsu.scala:219:36] wire l_uop_20_exception = ldq_uop_20_exception; // @[lsu.scala:219:36, :1191:37] wire uop_45_exception = ldq_uop_20_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_20_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_20_exc_cause = ldq_uop_20_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_45_exc_cause = ldq_uop_20_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_20_mem_cmd = ldq_uop_20_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_mem_cmd = ldq_uop_20_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_20_mem_size = ldq_uop_20_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_mem_size = ldq_uop_20_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_mem_signed; // @[lsu.scala:219:36] wire l_uop_20_mem_signed = ldq_uop_20_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_45_mem_signed = ldq_uop_20_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_uses_ldq; // @[lsu.scala:219:36] wire l_uop_20_uses_ldq = ldq_uop_20_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_45_uses_ldq = ldq_uop_20_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_uses_stq; // @[lsu.scala:219:36] wire l_uop_20_uses_stq = ldq_uop_20_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_45_uses_stq = ldq_uop_20_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_is_unique; // @[lsu.scala:219:36] wire l_uop_20_is_unique = ldq_uop_20_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_45_is_unique = ldq_uop_20_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_20_flush_on_commit = ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_45_flush_on_commit = ldq_uop_20_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_20_csr_cmd = ldq_uop_20_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_csr_cmd = ldq_uop_20_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_20_ldst_is_rs1 = ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_45_ldst_is_rs1 = ldq_uop_20_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_20_ldst = ldq_uop_20_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_ldst = ldq_uop_20_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs1 = ldq_uop_20_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs1 = ldq_uop_20_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs2 = ldq_uop_20_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs2 = ldq_uop_20_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_20_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_20_lrs3 = ldq_uop_20_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_45_lrs3 = ldq_uop_20_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_dst_rtype = ldq_uop_20_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_dst_rtype = ldq_uop_20_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_lrs1_rtype = ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_lrs1_rtype = ldq_uop_20_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_20_lrs2_rtype = ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_lrs2_rtype = ldq_uop_20_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_frs3_en; // @[lsu.scala:219:36] wire l_uop_20_frs3_en = ldq_uop_20_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_45_frs3_en = ldq_uop_20_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fcn_dw; // @[lsu.scala:219:36] wire l_uop_20_fcn_dw = ldq_uop_20_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_45_fcn_dw = ldq_uop_20_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_20_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_20_fcn_op = ldq_uop_20_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_45_fcn_op = ldq_uop_20_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_fp_val; // @[lsu.scala:219:36] wire l_uop_20_fp_val = ldq_uop_20_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_45_fp_val = ldq_uop_20_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_20_fp_rm = ldq_uop_20_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_fp_rm = ldq_uop_20_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_20_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_20_fp_typ = ldq_uop_20_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_45_fp_typ = ldq_uop_20_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_pf_if = ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_pf_if = ldq_uop_20_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_ae_if = ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_ae_if = ldq_uop_20_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_20_xcpt_ma_if = ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_xcpt_ma_if = ldq_uop_20_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_20_bp_debug_if = ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_bp_debug_if = ldq_uop_20_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_20_bp_xcpt_if = ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_45_bp_xcpt_if = ldq_uop_20_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_20_debug_fsrc = ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_debug_fsrc = ldq_uop_20_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_20_debug_tsrc = ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_45_debug_tsrc = ldq_uop_20_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_21_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_21_inst = ldq_uop_21_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_46_inst = ldq_uop_21_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_21_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_21_debug_inst = ldq_uop_21_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_46_debug_inst = ldq_uop_21_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_rvc; // @[lsu.scala:219:36] wire l_uop_21_is_rvc = ldq_uop_21_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_rvc = ldq_uop_21_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_21_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_21_debug_pc = ldq_uop_21_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_46_debug_pc = ldq_uop_21_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_0; // @[lsu.scala:219:36] wire l_uop_21_iq_type_0 = ldq_uop_21_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_0 = ldq_uop_21_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_1; // @[lsu.scala:219:36] wire l_uop_21_iq_type_1 = ldq_uop_21_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_1 = ldq_uop_21_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_2; // @[lsu.scala:219:36] wire l_uop_21_iq_type_2 = ldq_uop_21_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_2 = ldq_uop_21_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iq_type_3; // @[lsu.scala:219:36] wire l_uop_21_iq_type_3 = ldq_uop_21_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_46_iq_type_3 = ldq_uop_21_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_0; // @[lsu.scala:219:36] wire l_uop_21_fu_code_0 = ldq_uop_21_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_0 = ldq_uop_21_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_1; // @[lsu.scala:219:36] wire l_uop_21_fu_code_1 = ldq_uop_21_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_1 = ldq_uop_21_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_2; // @[lsu.scala:219:36] wire l_uop_21_fu_code_2 = ldq_uop_21_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_2 = ldq_uop_21_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_3; // @[lsu.scala:219:36] wire l_uop_21_fu_code_3 = ldq_uop_21_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_3 = ldq_uop_21_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_4; // @[lsu.scala:219:36] wire l_uop_21_fu_code_4 = ldq_uop_21_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_4 = ldq_uop_21_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_5; // @[lsu.scala:219:36] wire l_uop_21_fu_code_5 = ldq_uop_21_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_5 = ldq_uop_21_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_6; // @[lsu.scala:219:36] wire l_uop_21_fu_code_6 = ldq_uop_21_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_6 = ldq_uop_21_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_7; // @[lsu.scala:219:36] wire l_uop_21_fu_code_7 = ldq_uop_21_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_7 = ldq_uop_21_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_8; // @[lsu.scala:219:36] wire l_uop_21_fu_code_8 = ldq_uop_21_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_8 = ldq_uop_21_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fu_code_9; // @[lsu.scala:219:36] wire l_uop_21_fu_code_9 = ldq_uop_21_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_46_fu_code_9 = ldq_uop_21_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued; // @[lsu.scala:219:36] wire l_uop_21_iw_issued = ldq_uop_21_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued = ldq_uop_21_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_21_iw_issued_partial_agen = ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued_partial_agen = ldq_uop_21_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_21_iw_issued_partial_dgen = ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_issued_partial_dgen = ldq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_21_iw_p1_speculative_child = ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_iw_p1_speculative_child = ldq_uop_21_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_21_iw_p2_speculative_child = ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_iw_p2_speculative_child = ldq_uop_21_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p1_bypass_hint = ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p1_bypass_hint = ldq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p2_bypass_hint = ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p2_bypass_hint = ldq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_21_iw_p3_bypass_hint = ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_46_iw_p3_bypass_hint = ldq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_dis_col_sel = ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_dis_col_sel = ldq_uop_21_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_21_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_21_br_mask = ldq_uop_21_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_46_br_mask = ldq_uop_21_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_21_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_21_br_tag = ldq_uop_21_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_46_br_tag = ldq_uop_21_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_21_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_21_br_type = ldq_uop_21_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_46_br_type = ldq_uop_21_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sfb; // @[lsu.scala:219:36] wire l_uop_21_is_sfb = ldq_uop_21_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sfb = ldq_uop_21_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_fence; // @[lsu.scala:219:36] wire l_uop_21_is_fence = ldq_uop_21_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_fence = ldq_uop_21_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_fencei; // @[lsu.scala:219:36] wire l_uop_21_is_fencei = ldq_uop_21_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_fencei = ldq_uop_21_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sfence; // @[lsu.scala:219:36] wire l_uop_21_is_sfence = ldq_uop_21_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sfence = ldq_uop_21_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_amo; // @[lsu.scala:219:36] wire l_uop_21_is_amo = ldq_uop_21_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_amo = ldq_uop_21_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_eret; // @[lsu.scala:219:36] wire l_uop_21_is_eret = ldq_uop_21_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_eret = ldq_uop_21_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_21_is_sys_pc2epc = ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_sys_pc2epc = ldq_uop_21_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_rocc; // @[lsu.scala:219:36] wire l_uop_21_is_rocc = ldq_uop_21_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_rocc = ldq_uop_21_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_mov; // @[lsu.scala:219:36] wire l_uop_21_is_mov = ldq_uop_21_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_mov = ldq_uop_21_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ftq_idx = ldq_uop_21_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ftq_idx = ldq_uop_21_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_edge_inst; // @[lsu.scala:219:36] wire l_uop_21_edge_inst = ldq_uop_21_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_46_edge_inst = ldq_uop_21_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_21_pc_lob = ldq_uop_21_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_pc_lob = ldq_uop_21_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_taken; // @[lsu.scala:219:36] wire l_uop_21_taken = ldq_uop_21_taken; // @[lsu.scala:219:36, :1191:37] wire uop_46_taken = ldq_uop_21_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_imm_rename; // @[lsu.scala:219:36] wire l_uop_21_imm_rename = ldq_uop_21_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_46_imm_rename = ldq_uop_21_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_imm_sel = ldq_uop_21_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_imm_sel = ldq_uop_21_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_21_pimm = ldq_uop_21_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_pimm = ldq_uop_21_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_21_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_21_imm_packed = ldq_uop_21_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_46_imm_packed = ldq_uop_21_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_21_op1_sel = ldq_uop_21_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_op1_sel = ldq_uop_21_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_21_op2_sel = ldq_uop_21_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_op2_sel = ldq_uop_21_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ldst = ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ldst = ldq_uop_21_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_wen = ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_wen = ldq_uop_21_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren1 = ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren1 = ldq_uop_21_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren2 = ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren2 = ldq_uop_21_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_ren3 = ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_ren3 = ldq_uop_21_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_swap12 = ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_swap12 = ldq_uop_21_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_swap23 = ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_swap23 = ldq_uop_21_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_ctrl_typeTagIn = ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_ctrl_typeTagIn = ldq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_ctrl_typeTagOut = ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_ctrl_typeTagOut = ldq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fromint = ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fromint = ldq_uop_21_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_toint = ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_toint = ldq_uop_21_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fastpipe = ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fastpipe = ldq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_fma = ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_fma = ldq_uop_21_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_div = ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_div = ldq_uop_21_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_sqrt = ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_sqrt = ldq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_wflags = ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_wflags = ldq_uop_21_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_21_fp_ctrl_vec = ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_ctrl_vec = ldq_uop_21_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_21_rob_idx = ldq_uop_21_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_rob_idx = ldq_uop_21_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ldq_idx = ldq_uop_21_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ldq_idx = ldq_uop_21_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_21_stq_idx = ldq_uop_21_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_stq_idx = ldq_uop_21_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_21_rxq_idx = ldq_uop_21_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_rxq_idx = ldq_uop_21_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_21_pdst = ldq_uop_21_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_pdst = ldq_uop_21_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs1 = ldq_uop_21_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs1 = ldq_uop_21_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs2 = ldq_uop_21_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs2 = ldq_uop_21_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_21_prs3 = ldq_uop_21_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_prs3 = ldq_uop_21_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_21_ppred = ldq_uop_21_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_ppred = ldq_uop_21_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs1_busy; // @[lsu.scala:219:36] wire l_uop_21_prs1_busy = ldq_uop_21_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs1_busy = ldq_uop_21_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs2_busy; // @[lsu.scala:219:36] wire l_uop_21_prs2_busy = ldq_uop_21_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs2_busy = ldq_uop_21_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_prs3_busy; // @[lsu.scala:219:36] wire l_uop_21_prs3_busy = ldq_uop_21_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_prs3_busy = ldq_uop_21_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_ppred_busy; // @[lsu.scala:219:36] wire l_uop_21_ppred_busy = ldq_uop_21_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_46_ppred_busy = ldq_uop_21_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_21_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_21_stale_pdst = ldq_uop_21_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_46_stale_pdst = ldq_uop_21_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_exception; // @[lsu.scala:219:36] wire l_uop_21_exception = ldq_uop_21_exception; // @[lsu.scala:219:36, :1191:37] wire uop_46_exception = ldq_uop_21_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_21_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_21_exc_cause = ldq_uop_21_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_46_exc_cause = ldq_uop_21_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_21_mem_cmd = ldq_uop_21_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_mem_cmd = ldq_uop_21_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_21_mem_size = ldq_uop_21_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_mem_size = ldq_uop_21_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_mem_signed; // @[lsu.scala:219:36] wire l_uop_21_mem_signed = ldq_uop_21_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_46_mem_signed = ldq_uop_21_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_uses_ldq; // @[lsu.scala:219:36] wire l_uop_21_uses_ldq = ldq_uop_21_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_46_uses_ldq = ldq_uop_21_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_uses_stq; // @[lsu.scala:219:36] wire l_uop_21_uses_stq = ldq_uop_21_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_46_uses_stq = ldq_uop_21_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_is_unique; // @[lsu.scala:219:36] wire l_uop_21_is_unique = ldq_uop_21_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_46_is_unique = ldq_uop_21_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_21_flush_on_commit = ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_46_flush_on_commit = ldq_uop_21_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_21_csr_cmd = ldq_uop_21_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_csr_cmd = ldq_uop_21_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_21_ldst_is_rs1 = ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_46_ldst_is_rs1 = ldq_uop_21_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_21_ldst = ldq_uop_21_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_ldst = ldq_uop_21_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs1 = ldq_uop_21_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs1 = ldq_uop_21_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs2 = ldq_uop_21_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs2 = ldq_uop_21_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_21_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_21_lrs3 = ldq_uop_21_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_46_lrs3 = ldq_uop_21_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_dst_rtype = ldq_uop_21_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_dst_rtype = ldq_uop_21_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_lrs1_rtype = ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_lrs1_rtype = ldq_uop_21_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_21_lrs2_rtype = ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_lrs2_rtype = ldq_uop_21_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_frs3_en; // @[lsu.scala:219:36] wire l_uop_21_frs3_en = ldq_uop_21_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_46_frs3_en = ldq_uop_21_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fcn_dw; // @[lsu.scala:219:36] wire l_uop_21_fcn_dw = ldq_uop_21_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_46_fcn_dw = ldq_uop_21_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_21_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_21_fcn_op = ldq_uop_21_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_46_fcn_op = ldq_uop_21_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_fp_val; // @[lsu.scala:219:36] wire l_uop_21_fp_val = ldq_uop_21_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_46_fp_val = ldq_uop_21_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_21_fp_rm = ldq_uop_21_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_fp_rm = ldq_uop_21_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_21_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_21_fp_typ = ldq_uop_21_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_46_fp_typ = ldq_uop_21_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_pf_if = ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_pf_if = ldq_uop_21_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_ae_if = ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_ae_if = ldq_uop_21_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_21_xcpt_ma_if = ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_xcpt_ma_if = ldq_uop_21_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_21_bp_debug_if = ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_bp_debug_if = ldq_uop_21_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_21_bp_xcpt_if = ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_46_bp_xcpt_if = ldq_uop_21_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_21_debug_fsrc = ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_debug_fsrc = ldq_uop_21_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_21_debug_tsrc = ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_46_debug_tsrc = ldq_uop_21_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_22_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_22_inst = ldq_uop_22_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_47_inst = ldq_uop_22_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_22_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_22_debug_inst = ldq_uop_22_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_47_debug_inst = ldq_uop_22_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_rvc; // @[lsu.scala:219:36] wire l_uop_22_is_rvc = ldq_uop_22_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_rvc = ldq_uop_22_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_22_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_22_debug_pc = ldq_uop_22_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_47_debug_pc = ldq_uop_22_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_0; // @[lsu.scala:219:36] wire l_uop_22_iq_type_0 = ldq_uop_22_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_0 = ldq_uop_22_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_1; // @[lsu.scala:219:36] wire l_uop_22_iq_type_1 = ldq_uop_22_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_1 = ldq_uop_22_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_2; // @[lsu.scala:219:36] wire l_uop_22_iq_type_2 = ldq_uop_22_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_2 = ldq_uop_22_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iq_type_3; // @[lsu.scala:219:36] wire l_uop_22_iq_type_3 = ldq_uop_22_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_47_iq_type_3 = ldq_uop_22_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_0; // @[lsu.scala:219:36] wire l_uop_22_fu_code_0 = ldq_uop_22_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_0 = ldq_uop_22_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_1; // @[lsu.scala:219:36] wire l_uop_22_fu_code_1 = ldq_uop_22_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_1 = ldq_uop_22_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_2; // @[lsu.scala:219:36] wire l_uop_22_fu_code_2 = ldq_uop_22_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_2 = ldq_uop_22_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_3; // @[lsu.scala:219:36] wire l_uop_22_fu_code_3 = ldq_uop_22_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_3 = ldq_uop_22_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_4; // @[lsu.scala:219:36] wire l_uop_22_fu_code_4 = ldq_uop_22_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_4 = ldq_uop_22_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_5; // @[lsu.scala:219:36] wire l_uop_22_fu_code_5 = ldq_uop_22_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_5 = ldq_uop_22_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_6; // @[lsu.scala:219:36] wire l_uop_22_fu_code_6 = ldq_uop_22_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_6 = ldq_uop_22_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_7; // @[lsu.scala:219:36] wire l_uop_22_fu_code_7 = ldq_uop_22_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_7 = ldq_uop_22_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_8; // @[lsu.scala:219:36] wire l_uop_22_fu_code_8 = ldq_uop_22_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_8 = ldq_uop_22_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fu_code_9; // @[lsu.scala:219:36] wire l_uop_22_fu_code_9 = ldq_uop_22_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_47_fu_code_9 = ldq_uop_22_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued; // @[lsu.scala:219:36] wire l_uop_22_iw_issued = ldq_uop_22_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued = ldq_uop_22_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_22_iw_issued_partial_agen = ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued_partial_agen = ldq_uop_22_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_22_iw_issued_partial_dgen = ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_issued_partial_dgen = ldq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_22_iw_p1_speculative_child = ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_iw_p1_speculative_child = ldq_uop_22_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_22_iw_p2_speculative_child = ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_iw_p2_speculative_child = ldq_uop_22_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p1_bypass_hint = ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p1_bypass_hint = ldq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p2_bypass_hint = ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p2_bypass_hint = ldq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_22_iw_p3_bypass_hint = ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_47_iw_p3_bypass_hint = ldq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_dis_col_sel = ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_dis_col_sel = ldq_uop_22_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_22_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_22_br_mask = ldq_uop_22_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_47_br_mask = ldq_uop_22_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_22_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_22_br_tag = ldq_uop_22_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_47_br_tag = ldq_uop_22_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_22_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_22_br_type = ldq_uop_22_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_47_br_type = ldq_uop_22_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sfb; // @[lsu.scala:219:36] wire l_uop_22_is_sfb = ldq_uop_22_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sfb = ldq_uop_22_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_fence; // @[lsu.scala:219:36] wire l_uop_22_is_fence = ldq_uop_22_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_fence = ldq_uop_22_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_fencei; // @[lsu.scala:219:36] wire l_uop_22_is_fencei = ldq_uop_22_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_fencei = ldq_uop_22_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sfence; // @[lsu.scala:219:36] wire l_uop_22_is_sfence = ldq_uop_22_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sfence = ldq_uop_22_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_amo; // @[lsu.scala:219:36] wire l_uop_22_is_amo = ldq_uop_22_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_amo = ldq_uop_22_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_eret; // @[lsu.scala:219:36] wire l_uop_22_is_eret = ldq_uop_22_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_eret = ldq_uop_22_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_22_is_sys_pc2epc = ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_sys_pc2epc = ldq_uop_22_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_rocc; // @[lsu.scala:219:36] wire l_uop_22_is_rocc = ldq_uop_22_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_rocc = ldq_uop_22_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_mov; // @[lsu.scala:219:36] wire l_uop_22_is_mov = ldq_uop_22_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_mov = ldq_uop_22_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ftq_idx = ldq_uop_22_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ftq_idx = ldq_uop_22_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_edge_inst; // @[lsu.scala:219:36] wire l_uop_22_edge_inst = ldq_uop_22_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_47_edge_inst = ldq_uop_22_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_22_pc_lob = ldq_uop_22_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_pc_lob = ldq_uop_22_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_taken; // @[lsu.scala:219:36] wire l_uop_22_taken = ldq_uop_22_taken; // @[lsu.scala:219:36, :1191:37] wire uop_47_taken = ldq_uop_22_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_imm_rename; // @[lsu.scala:219:36] wire l_uop_22_imm_rename = ldq_uop_22_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_47_imm_rename = ldq_uop_22_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_imm_sel = ldq_uop_22_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_imm_sel = ldq_uop_22_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_22_pimm = ldq_uop_22_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_pimm = ldq_uop_22_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_22_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_22_imm_packed = ldq_uop_22_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_47_imm_packed = ldq_uop_22_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_22_op1_sel = ldq_uop_22_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_op1_sel = ldq_uop_22_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_22_op2_sel = ldq_uop_22_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_op2_sel = ldq_uop_22_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ldst = ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ldst = ldq_uop_22_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_wen = ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_wen = ldq_uop_22_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren1 = ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren1 = ldq_uop_22_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren2 = ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren2 = ldq_uop_22_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_ren3 = ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_ren3 = ldq_uop_22_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_swap12 = ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_swap12 = ldq_uop_22_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_swap23 = ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_swap23 = ldq_uop_22_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_ctrl_typeTagIn = ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_ctrl_typeTagIn = ldq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_ctrl_typeTagOut = ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_ctrl_typeTagOut = ldq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fromint = ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fromint = ldq_uop_22_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_toint = ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_toint = ldq_uop_22_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fastpipe = ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fastpipe = ldq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_fma = ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_fma = ldq_uop_22_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_div = ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_div = ldq_uop_22_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_sqrt = ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_sqrt = ldq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_wflags = ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_wflags = ldq_uop_22_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_22_fp_ctrl_vec = ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_ctrl_vec = ldq_uop_22_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_22_rob_idx = ldq_uop_22_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_rob_idx = ldq_uop_22_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ldq_idx = ldq_uop_22_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ldq_idx = ldq_uop_22_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_22_stq_idx = ldq_uop_22_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_stq_idx = ldq_uop_22_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_22_rxq_idx = ldq_uop_22_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_rxq_idx = ldq_uop_22_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_22_pdst = ldq_uop_22_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_pdst = ldq_uop_22_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs1 = ldq_uop_22_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs1 = ldq_uop_22_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs2 = ldq_uop_22_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs2 = ldq_uop_22_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_22_prs3 = ldq_uop_22_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_prs3 = ldq_uop_22_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_22_ppred = ldq_uop_22_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_ppred = ldq_uop_22_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs1_busy; // @[lsu.scala:219:36] wire l_uop_22_prs1_busy = ldq_uop_22_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs1_busy = ldq_uop_22_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs2_busy; // @[lsu.scala:219:36] wire l_uop_22_prs2_busy = ldq_uop_22_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs2_busy = ldq_uop_22_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_prs3_busy; // @[lsu.scala:219:36] wire l_uop_22_prs3_busy = ldq_uop_22_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_prs3_busy = ldq_uop_22_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_ppred_busy; // @[lsu.scala:219:36] wire l_uop_22_ppred_busy = ldq_uop_22_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_47_ppred_busy = ldq_uop_22_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_22_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_22_stale_pdst = ldq_uop_22_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_47_stale_pdst = ldq_uop_22_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_exception; // @[lsu.scala:219:36] wire l_uop_22_exception = ldq_uop_22_exception; // @[lsu.scala:219:36, :1191:37] wire uop_47_exception = ldq_uop_22_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_22_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_22_exc_cause = ldq_uop_22_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_47_exc_cause = ldq_uop_22_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_22_mem_cmd = ldq_uop_22_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_mem_cmd = ldq_uop_22_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_22_mem_size = ldq_uop_22_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_mem_size = ldq_uop_22_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_mem_signed; // @[lsu.scala:219:36] wire l_uop_22_mem_signed = ldq_uop_22_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_47_mem_signed = ldq_uop_22_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_uses_ldq; // @[lsu.scala:219:36] wire l_uop_22_uses_ldq = ldq_uop_22_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_47_uses_ldq = ldq_uop_22_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_uses_stq; // @[lsu.scala:219:36] wire l_uop_22_uses_stq = ldq_uop_22_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_47_uses_stq = ldq_uop_22_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_is_unique; // @[lsu.scala:219:36] wire l_uop_22_is_unique = ldq_uop_22_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_47_is_unique = ldq_uop_22_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_22_flush_on_commit = ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_47_flush_on_commit = ldq_uop_22_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_22_csr_cmd = ldq_uop_22_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_csr_cmd = ldq_uop_22_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_22_ldst_is_rs1 = ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_47_ldst_is_rs1 = ldq_uop_22_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_22_ldst = ldq_uop_22_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_ldst = ldq_uop_22_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs1 = ldq_uop_22_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs1 = ldq_uop_22_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs2 = ldq_uop_22_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs2 = ldq_uop_22_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_22_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_22_lrs3 = ldq_uop_22_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_47_lrs3 = ldq_uop_22_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_dst_rtype = ldq_uop_22_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_dst_rtype = ldq_uop_22_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_lrs1_rtype = ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_lrs1_rtype = ldq_uop_22_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_22_lrs2_rtype = ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_lrs2_rtype = ldq_uop_22_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_frs3_en; // @[lsu.scala:219:36] wire l_uop_22_frs3_en = ldq_uop_22_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_47_frs3_en = ldq_uop_22_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fcn_dw; // @[lsu.scala:219:36] wire l_uop_22_fcn_dw = ldq_uop_22_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_47_fcn_dw = ldq_uop_22_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_22_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_22_fcn_op = ldq_uop_22_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_47_fcn_op = ldq_uop_22_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_fp_val; // @[lsu.scala:219:36] wire l_uop_22_fp_val = ldq_uop_22_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_47_fp_val = ldq_uop_22_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_22_fp_rm = ldq_uop_22_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_fp_rm = ldq_uop_22_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_22_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_22_fp_typ = ldq_uop_22_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_47_fp_typ = ldq_uop_22_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_pf_if = ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_pf_if = ldq_uop_22_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_ae_if = ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_ae_if = ldq_uop_22_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_22_xcpt_ma_if = ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_xcpt_ma_if = ldq_uop_22_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_22_bp_debug_if = ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_bp_debug_if = ldq_uop_22_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_22_bp_xcpt_if = ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_47_bp_xcpt_if = ldq_uop_22_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_22_debug_fsrc = ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_debug_fsrc = ldq_uop_22_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_22_debug_tsrc = ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_47_debug_tsrc = ldq_uop_22_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_23_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_23_inst = ldq_uop_23_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_48_inst = ldq_uop_23_inst; // @[lsu.scala:219:36, :1697:25] reg [31:0] ldq_uop_23_debug_inst; // @[lsu.scala:219:36] wire [31:0] l_uop_23_debug_inst = ldq_uop_23_debug_inst; // @[lsu.scala:219:36, :1191:37] wire [31:0] uop_48_debug_inst = ldq_uop_23_debug_inst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_rvc; // @[lsu.scala:219:36] wire l_uop_23_is_rvc = ldq_uop_23_is_rvc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_rvc = ldq_uop_23_is_rvc; // @[lsu.scala:219:36, :1697:25] reg [39:0] ldq_uop_23_debug_pc; // @[lsu.scala:219:36] wire [39:0] l_uop_23_debug_pc = ldq_uop_23_debug_pc; // @[lsu.scala:219:36, :1191:37] wire [39:0] uop_48_debug_pc = ldq_uop_23_debug_pc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_0; // @[lsu.scala:219:36] wire l_uop_23_iq_type_0 = ldq_uop_23_iq_type_0; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_0 = ldq_uop_23_iq_type_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_1; // @[lsu.scala:219:36] wire l_uop_23_iq_type_1 = ldq_uop_23_iq_type_1; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_1 = ldq_uop_23_iq_type_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_2; // @[lsu.scala:219:36] wire l_uop_23_iq_type_2 = ldq_uop_23_iq_type_2; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_2 = ldq_uop_23_iq_type_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iq_type_3; // @[lsu.scala:219:36] wire l_uop_23_iq_type_3 = ldq_uop_23_iq_type_3; // @[lsu.scala:219:36, :1191:37] wire uop_48_iq_type_3 = ldq_uop_23_iq_type_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_0; // @[lsu.scala:219:36] wire l_uop_23_fu_code_0 = ldq_uop_23_fu_code_0; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_0 = ldq_uop_23_fu_code_0; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_1; // @[lsu.scala:219:36] wire l_uop_23_fu_code_1 = ldq_uop_23_fu_code_1; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_1 = ldq_uop_23_fu_code_1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_2; // @[lsu.scala:219:36] wire l_uop_23_fu_code_2 = ldq_uop_23_fu_code_2; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_2 = ldq_uop_23_fu_code_2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_3; // @[lsu.scala:219:36] wire l_uop_23_fu_code_3 = ldq_uop_23_fu_code_3; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_3 = ldq_uop_23_fu_code_3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_4; // @[lsu.scala:219:36] wire l_uop_23_fu_code_4 = ldq_uop_23_fu_code_4; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_4 = ldq_uop_23_fu_code_4; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_5; // @[lsu.scala:219:36] wire l_uop_23_fu_code_5 = ldq_uop_23_fu_code_5; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_5 = ldq_uop_23_fu_code_5; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_6; // @[lsu.scala:219:36] wire l_uop_23_fu_code_6 = ldq_uop_23_fu_code_6; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_6 = ldq_uop_23_fu_code_6; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_7; // @[lsu.scala:219:36] wire l_uop_23_fu_code_7 = ldq_uop_23_fu_code_7; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_7 = ldq_uop_23_fu_code_7; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_8; // @[lsu.scala:219:36] wire l_uop_23_fu_code_8 = ldq_uop_23_fu_code_8; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_8 = ldq_uop_23_fu_code_8; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fu_code_9; // @[lsu.scala:219:36] wire l_uop_23_fu_code_9 = ldq_uop_23_fu_code_9; // @[lsu.scala:219:36, :1191:37] wire uop_48_fu_code_9 = ldq_uop_23_fu_code_9; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued; // @[lsu.scala:219:36] wire l_uop_23_iw_issued = ldq_uop_23_iw_issued; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued = ldq_uop_23_iw_issued; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36] wire l_uop_23_iw_issued_partial_agen = ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued_partial_agen = ldq_uop_23_iw_issued_partial_agen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36] wire l_uop_23_iw_issued_partial_dgen = ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_issued_partial_dgen = ldq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_23_iw_p1_speculative_child = ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_iw_p1_speculative_child = ldq_uop_23_iw_p1_speculative_child; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36] wire [2:0] l_uop_23_iw_p2_speculative_child = ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_iw_p2_speculative_child = ldq_uop_23_iw_p2_speculative_child; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p1_bypass_hint = ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p1_bypass_hint = ldq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p2_bypass_hint = ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p2_bypass_hint = ldq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36] wire l_uop_23_iw_p3_bypass_hint = ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1191:37] wire uop_48_iw_p3_bypass_hint = ldq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_dis_col_sel = ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_dis_col_sel = ldq_uop_23_dis_col_sel; // @[lsu.scala:219:36, :1697:25] reg [15:0] ldq_uop_23_br_mask; // @[lsu.scala:219:36] wire [15:0] l_uop_23_br_mask = ldq_uop_23_br_mask; // @[lsu.scala:219:36, :1191:37] wire [15:0] uop_48_br_mask = ldq_uop_23_br_mask; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_23_br_tag; // @[lsu.scala:219:36] wire [3:0] l_uop_23_br_tag = ldq_uop_23_br_tag; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_48_br_tag = ldq_uop_23_br_tag; // @[lsu.scala:219:36, :1697:25] reg [3:0] ldq_uop_23_br_type; // @[lsu.scala:219:36] wire [3:0] l_uop_23_br_type = ldq_uop_23_br_type; // @[lsu.scala:219:36, :1191:37] wire [3:0] uop_48_br_type = ldq_uop_23_br_type; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sfb; // @[lsu.scala:219:36] wire l_uop_23_is_sfb = ldq_uop_23_is_sfb; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sfb = ldq_uop_23_is_sfb; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_fence; // @[lsu.scala:219:36] wire l_uop_23_is_fence = ldq_uop_23_is_fence; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_fence = ldq_uop_23_is_fence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_fencei; // @[lsu.scala:219:36] wire l_uop_23_is_fencei = ldq_uop_23_is_fencei; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_fencei = ldq_uop_23_is_fencei; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sfence; // @[lsu.scala:219:36] wire l_uop_23_is_sfence = ldq_uop_23_is_sfence; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sfence = ldq_uop_23_is_sfence; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_amo; // @[lsu.scala:219:36] wire l_uop_23_is_amo = ldq_uop_23_is_amo; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_amo = ldq_uop_23_is_amo; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_eret; // @[lsu.scala:219:36] wire l_uop_23_is_eret = ldq_uop_23_is_eret; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_eret = ldq_uop_23_is_eret; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36] wire l_uop_23_is_sys_pc2epc = ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_sys_pc2epc = ldq_uop_23_is_sys_pc2epc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_rocc; // @[lsu.scala:219:36] wire l_uop_23_is_rocc = ldq_uop_23_is_rocc; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_rocc = ldq_uop_23_is_rocc; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_mov; // @[lsu.scala:219:36] wire l_uop_23_is_mov = ldq_uop_23_is_mov; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_mov = ldq_uop_23_is_mov; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ftq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ftq_idx = ldq_uop_23_ftq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ftq_idx = ldq_uop_23_ftq_idx; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_edge_inst; // @[lsu.scala:219:36] wire l_uop_23_edge_inst = ldq_uop_23_edge_inst; // @[lsu.scala:219:36, :1191:37] wire uop_48_edge_inst = ldq_uop_23_edge_inst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_pc_lob; // @[lsu.scala:219:36] wire [5:0] l_uop_23_pc_lob = ldq_uop_23_pc_lob; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_pc_lob = ldq_uop_23_pc_lob; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_taken; // @[lsu.scala:219:36] wire l_uop_23_taken = ldq_uop_23_taken; // @[lsu.scala:219:36, :1191:37] wire uop_48_taken = ldq_uop_23_taken; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_imm_rename; // @[lsu.scala:219:36] wire l_uop_23_imm_rename = ldq_uop_23_imm_rename; // @[lsu.scala:219:36, :1191:37] wire uop_48_imm_rename = ldq_uop_23_imm_rename; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_imm_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_imm_sel = ldq_uop_23_imm_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_imm_sel = ldq_uop_23_imm_sel; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_pimm; // @[lsu.scala:219:36] wire [4:0] l_uop_23_pimm = ldq_uop_23_pimm; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_pimm = ldq_uop_23_pimm; // @[lsu.scala:219:36, :1697:25] reg [19:0] ldq_uop_23_imm_packed; // @[lsu.scala:219:36] wire [19:0] l_uop_23_imm_packed = ldq_uop_23_imm_packed; // @[lsu.scala:219:36, :1191:37] wire [19:0] uop_48_imm_packed = ldq_uop_23_imm_packed; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_op1_sel; // @[lsu.scala:219:36] wire [1:0] l_uop_23_op1_sel = ldq_uop_23_op1_sel; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_op1_sel = ldq_uop_23_op1_sel; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_op2_sel; // @[lsu.scala:219:36] wire [2:0] l_uop_23_op2_sel = ldq_uop_23_op2_sel; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_op2_sel = ldq_uop_23_op2_sel; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ldst = ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ldst = ldq_uop_23_fp_ctrl_ldst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_wen = ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_wen = ldq_uop_23_fp_ctrl_wen; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren1 = ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren1 = ldq_uop_23_fp_ctrl_ren1; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren2 = ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren2 = ldq_uop_23_fp_ctrl_ren2; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_ren3 = ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_ren3 = ldq_uop_23_fp_ctrl_ren3; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_swap12 = ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_swap12 = ldq_uop_23_fp_ctrl_swap12; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_swap23 = ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_swap23 = ldq_uop_23_fp_ctrl_swap23; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_ctrl_typeTagIn = ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_ctrl_typeTagIn = ldq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_ctrl_typeTagOut = ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_ctrl_typeTagOut = ldq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fromint = ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fromint = ldq_uop_23_fp_ctrl_fromint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_toint = ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_toint = ldq_uop_23_fp_ctrl_toint; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fastpipe = ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fastpipe = ldq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_fma = ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_fma = ldq_uop_23_fp_ctrl_fma; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_div = ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_div = ldq_uop_23_fp_ctrl_div; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_sqrt = ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_sqrt = ldq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_wflags = ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_wflags = ldq_uop_23_fp_ctrl_wflags; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36] wire l_uop_23_fp_ctrl_vec = ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_ctrl_vec = ldq_uop_23_fp_ctrl_vec; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_rob_idx; // @[lsu.scala:219:36] wire [6:0] l_uop_23_rob_idx = ldq_uop_23_rob_idx; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_rob_idx = ldq_uop_23_rob_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ldq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ldq_idx = ldq_uop_23_ldq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ldq_idx = ldq_uop_23_ldq_idx; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_stq_idx; // @[lsu.scala:219:36] wire [4:0] l_uop_23_stq_idx = ldq_uop_23_stq_idx; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_stq_idx = ldq_uop_23_stq_idx; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_rxq_idx; // @[lsu.scala:219:36] wire [1:0] l_uop_23_rxq_idx = ldq_uop_23_rxq_idx; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_rxq_idx = ldq_uop_23_rxq_idx; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_23_pdst = ldq_uop_23_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_pdst = ldq_uop_23_pdst; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs1; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs1 = ldq_uop_23_prs1; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs1 = ldq_uop_23_prs1; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs2; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs2 = ldq_uop_23_prs2; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs2 = ldq_uop_23_prs2; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_prs3; // @[lsu.scala:219:36] wire [6:0] l_uop_23_prs3 = ldq_uop_23_prs3; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_prs3 = ldq_uop_23_prs3; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_ppred; // @[lsu.scala:219:36] wire [4:0] l_uop_23_ppred = ldq_uop_23_ppred; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_ppred = ldq_uop_23_ppred; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs1_busy; // @[lsu.scala:219:36] wire l_uop_23_prs1_busy = ldq_uop_23_prs1_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs1_busy = ldq_uop_23_prs1_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs2_busy; // @[lsu.scala:219:36] wire l_uop_23_prs2_busy = ldq_uop_23_prs2_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs2_busy = ldq_uop_23_prs2_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_prs3_busy; // @[lsu.scala:219:36] wire l_uop_23_prs3_busy = ldq_uop_23_prs3_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_prs3_busy = ldq_uop_23_prs3_busy; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_ppred_busy; // @[lsu.scala:219:36] wire l_uop_23_ppred_busy = ldq_uop_23_ppred_busy; // @[lsu.scala:219:36, :1191:37] wire uop_48_ppred_busy = ldq_uop_23_ppred_busy; // @[lsu.scala:219:36, :1697:25] reg [6:0] ldq_uop_23_stale_pdst; // @[lsu.scala:219:36] wire [6:0] l_uop_23_stale_pdst = ldq_uop_23_stale_pdst; // @[lsu.scala:219:36, :1191:37] wire [6:0] uop_48_stale_pdst = ldq_uop_23_stale_pdst; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_exception; // @[lsu.scala:219:36] wire l_uop_23_exception = ldq_uop_23_exception; // @[lsu.scala:219:36, :1191:37] wire uop_48_exception = ldq_uop_23_exception; // @[lsu.scala:219:36, :1697:25] reg [63:0] ldq_uop_23_exc_cause; // @[lsu.scala:219:36] wire [63:0] l_uop_23_exc_cause = ldq_uop_23_exc_cause; // @[lsu.scala:219:36, :1191:37] wire [63:0] uop_48_exc_cause = ldq_uop_23_exc_cause; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_mem_cmd; // @[lsu.scala:219:36] wire [4:0] l_uop_23_mem_cmd = ldq_uop_23_mem_cmd; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_mem_cmd = ldq_uop_23_mem_cmd; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_mem_size; // @[lsu.scala:219:36] wire [1:0] l_uop_23_mem_size = ldq_uop_23_mem_size; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_mem_size = ldq_uop_23_mem_size; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_mem_signed; // @[lsu.scala:219:36] wire l_uop_23_mem_signed = ldq_uop_23_mem_signed; // @[lsu.scala:219:36, :1191:37] wire uop_48_mem_signed = ldq_uop_23_mem_signed; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_uses_ldq; // @[lsu.scala:219:36] wire l_uop_23_uses_ldq = ldq_uop_23_uses_ldq; // @[lsu.scala:219:36, :1191:37] wire uop_48_uses_ldq = ldq_uop_23_uses_ldq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_uses_stq; // @[lsu.scala:219:36] wire l_uop_23_uses_stq = ldq_uop_23_uses_stq; // @[lsu.scala:219:36, :1191:37] wire uop_48_uses_stq = ldq_uop_23_uses_stq; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_is_unique; // @[lsu.scala:219:36] wire l_uop_23_is_unique = ldq_uop_23_is_unique; // @[lsu.scala:219:36, :1191:37] wire uop_48_is_unique = ldq_uop_23_is_unique; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36] wire l_uop_23_flush_on_commit = ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36, :1191:37] wire uop_48_flush_on_commit = ldq_uop_23_flush_on_commit; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_csr_cmd; // @[lsu.scala:219:36] wire [2:0] l_uop_23_csr_cmd = ldq_uop_23_csr_cmd; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_csr_cmd = ldq_uop_23_csr_cmd; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36] wire l_uop_23_ldst_is_rs1 = ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36, :1191:37] wire uop_48_ldst_is_rs1 = ldq_uop_23_ldst_is_rs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_ldst; // @[lsu.scala:219:36] wire [5:0] l_uop_23_ldst = ldq_uop_23_ldst; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_ldst = ldq_uop_23_ldst; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs1; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs1 = ldq_uop_23_lrs1; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs1 = ldq_uop_23_lrs1; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs2; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs2 = ldq_uop_23_lrs2; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs2 = ldq_uop_23_lrs2; // @[lsu.scala:219:36, :1697:25] reg [5:0] ldq_uop_23_lrs3; // @[lsu.scala:219:36] wire [5:0] l_uop_23_lrs3 = ldq_uop_23_lrs3; // @[lsu.scala:219:36, :1191:37] wire [5:0] uop_48_lrs3 = ldq_uop_23_lrs3; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_dst_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_dst_rtype = ldq_uop_23_dst_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_dst_rtype = ldq_uop_23_dst_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_lrs1_rtype = ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_lrs1_rtype = ldq_uop_23_lrs1_rtype; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36] wire [1:0] l_uop_23_lrs2_rtype = ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_lrs2_rtype = ldq_uop_23_lrs2_rtype; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_frs3_en; // @[lsu.scala:219:36] wire l_uop_23_frs3_en = ldq_uop_23_frs3_en; // @[lsu.scala:219:36, :1191:37] wire uop_48_frs3_en = ldq_uop_23_frs3_en; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fcn_dw; // @[lsu.scala:219:36] wire l_uop_23_fcn_dw = ldq_uop_23_fcn_dw; // @[lsu.scala:219:36, :1191:37] wire uop_48_fcn_dw = ldq_uop_23_fcn_dw; // @[lsu.scala:219:36, :1697:25] reg [4:0] ldq_uop_23_fcn_op; // @[lsu.scala:219:36] wire [4:0] l_uop_23_fcn_op = ldq_uop_23_fcn_op; // @[lsu.scala:219:36, :1191:37] wire [4:0] uop_48_fcn_op = ldq_uop_23_fcn_op; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_fp_val; // @[lsu.scala:219:36] wire l_uop_23_fp_val = ldq_uop_23_fp_val; // @[lsu.scala:219:36, :1191:37] wire uop_48_fp_val = ldq_uop_23_fp_val; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_fp_rm; // @[lsu.scala:219:36] wire [2:0] l_uop_23_fp_rm = ldq_uop_23_fp_rm; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_fp_rm = ldq_uop_23_fp_rm; // @[lsu.scala:219:36, :1697:25] reg [1:0] ldq_uop_23_fp_typ; // @[lsu.scala:219:36] wire [1:0] l_uop_23_fp_typ = ldq_uop_23_fp_typ; // @[lsu.scala:219:36, :1191:37] wire [1:0] uop_48_fp_typ = ldq_uop_23_fp_typ; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_pf_if = ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_pf_if = ldq_uop_23_xcpt_pf_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_ae_if = ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_ae_if = ldq_uop_23_xcpt_ae_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36] wire l_uop_23_xcpt_ma_if = ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_xcpt_ma_if = ldq_uop_23_xcpt_ma_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36] wire l_uop_23_bp_debug_if = ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_bp_debug_if = ldq_uop_23_bp_debug_if; // @[lsu.scala:219:36, :1697:25] reg ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36] wire l_uop_23_bp_xcpt_if = ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36, :1191:37] wire uop_48_bp_xcpt_if = ldq_uop_23_bp_xcpt_if; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_23_debug_fsrc = ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_debug_fsrc = ldq_uop_23_debug_fsrc; // @[lsu.scala:219:36, :1697:25] reg [2:0] ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36] wire [2:0] l_uop_23_debug_tsrc = ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36, :1191:37] wire [2:0] uop_48_debug_tsrc = ldq_uop_23_debug_tsrc; // @[lsu.scala:219:36, :1697:25] reg ldq_addr_0_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_0_bits; // @[lsu.scala:220:36] reg ldq_addr_1_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_1_bits; // @[lsu.scala:220:36] reg ldq_addr_2_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_2_bits; // @[lsu.scala:220:36] reg ldq_addr_3_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_3_bits; // @[lsu.scala:220:36] reg ldq_addr_4_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_4_bits; // @[lsu.scala:220:36] reg ldq_addr_5_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_5_bits; // @[lsu.scala:220:36] reg ldq_addr_6_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_6_bits; // @[lsu.scala:220:36] reg ldq_addr_7_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_7_bits; // @[lsu.scala:220:36] reg ldq_addr_8_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_8_bits; // @[lsu.scala:220:36] reg ldq_addr_9_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_9_bits; // @[lsu.scala:220:36] reg ldq_addr_10_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_10_bits; // @[lsu.scala:220:36] reg ldq_addr_11_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_11_bits; // @[lsu.scala:220:36] reg ldq_addr_12_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_12_bits; // @[lsu.scala:220:36] reg ldq_addr_13_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_13_bits; // @[lsu.scala:220:36] reg ldq_addr_14_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_14_bits; // @[lsu.scala:220:36] reg ldq_addr_15_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_15_bits; // @[lsu.scala:220:36] reg ldq_addr_16_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_16_bits; // @[lsu.scala:220:36] reg ldq_addr_17_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_17_bits; // @[lsu.scala:220:36] reg ldq_addr_18_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_18_bits; // @[lsu.scala:220:36] reg ldq_addr_19_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_19_bits; // @[lsu.scala:220:36] reg ldq_addr_20_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_20_bits; // @[lsu.scala:220:36] reg ldq_addr_21_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_21_bits; // @[lsu.scala:220:36] reg ldq_addr_22_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_22_bits; // @[lsu.scala:220:36] reg ldq_addr_23_valid; // @[lsu.scala:220:36] reg [39:0] ldq_addr_23_bits; // @[lsu.scala:220:36] reg ldq_addr_is_virtual_0; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_1; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_2; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_3; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_4; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_5; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_6; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_7; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_8; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_9; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_10; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_11; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_12; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_13; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_14; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_15; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_16; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_17; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_18; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_19; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_20; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_21; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_22; // @[lsu.scala:221:36] reg ldq_addr_is_virtual_23; // @[lsu.scala:221:36] reg ldq_addr_is_uncacheable_0; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_1; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_2; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_3; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_4; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_5; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_6; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_7; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_8; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_9; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_10; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_11; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_12; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_13; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_14; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_15; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_16; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_17; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_18; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_19; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_20; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_21; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_22; // @[lsu.scala:222:36] reg ldq_addr_is_uncacheable_23; // @[lsu.scala:222:36] reg ldq_executed_0; // @[lsu.scala:223:36] reg ldq_executed_1; // @[lsu.scala:223:36] reg ldq_executed_2; // @[lsu.scala:223:36] reg ldq_executed_3; // @[lsu.scala:223:36] reg ldq_executed_4; // @[lsu.scala:223:36] reg ldq_executed_5; // @[lsu.scala:223:36] reg ldq_executed_6; // @[lsu.scala:223:36] reg ldq_executed_7; // @[lsu.scala:223:36] reg ldq_executed_8; // @[lsu.scala:223:36] reg ldq_executed_9; // @[lsu.scala:223:36] reg ldq_executed_10; // @[lsu.scala:223:36] reg ldq_executed_11; // @[lsu.scala:223:36] reg ldq_executed_12; // @[lsu.scala:223:36] reg ldq_executed_13; // @[lsu.scala:223:36] reg ldq_executed_14; // @[lsu.scala:223:36] reg ldq_executed_15; // @[lsu.scala:223:36] reg ldq_executed_16; // @[lsu.scala:223:36] reg ldq_executed_17; // @[lsu.scala:223:36] reg ldq_executed_18; // @[lsu.scala:223:36] reg ldq_executed_19; // @[lsu.scala:223:36] reg ldq_executed_20; // @[lsu.scala:223:36] reg ldq_executed_21; // @[lsu.scala:223:36] reg ldq_executed_22; // @[lsu.scala:223:36] reg ldq_executed_23; // @[lsu.scala:223:36] reg ldq_succeeded_0; // @[lsu.scala:224:36] reg ldq_succeeded_1; // @[lsu.scala:224:36] reg ldq_succeeded_2; // @[lsu.scala:224:36] reg ldq_succeeded_3; // @[lsu.scala:224:36] reg ldq_succeeded_4; // @[lsu.scala:224:36] reg ldq_succeeded_5; // @[lsu.scala:224:36] reg ldq_succeeded_6; // @[lsu.scala:224:36] reg ldq_succeeded_7; // @[lsu.scala:224:36] reg ldq_succeeded_8; // @[lsu.scala:224:36] reg ldq_succeeded_9; // @[lsu.scala:224:36] reg ldq_succeeded_10; // @[lsu.scala:224:36] reg ldq_succeeded_11; // @[lsu.scala:224:36] reg ldq_succeeded_12; // @[lsu.scala:224:36] reg ldq_succeeded_13; // @[lsu.scala:224:36] reg ldq_succeeded_14; // @[lsu.scala:224:36] reg ldq_succeeded_15; // @[lsu.scala:224:36] reg ldq_succeeded_16; // @[lsu.scala:224:36] reg ldq_succeeded_17; // @[lsu.scala:224:36] reg ldq_succeeded_18; // @[lsu.scala:224:36] reg ldq_succeeded_19; // @[lsu.scala:224:36] reg ldq_succeeded_20; // @[lsu.scala:224:36] reg ldq_succeeded_21; // @[lsu.scala:224:36] reg ldq_succeeded_22; // @[lsu.scala:224:36] reg ldq_succeeded_23; // @[lsu.scala:224:36] reg ldq_order_fail_0; // @[lsu.scala:225:36] reg ldq_order_fail_1; // @[lsu.scala:225:36] reg ldq_order_fail_2; // @[lsu.scala:225:36] reg ldq_order_fail_3; // @[lsu.scala:225:36] reg ldq_order_fail_4; // @[lsu.scala:225:36] reg ldq_order_fail_5; // @[lsu.scala:225:36] reg ldq_order_fail_6; // @[lsu.scala:225:36] reg ldq_order_fail_7; // @[lsu.scala:225:36] reg ldq_order_fail_8; // @[lsu.scala:225:36] reg ldq_order_fail_9; // @[lsu.scala:225:36] reg ldq_order_fail_10; // @[lsu.scala:225:36] reg ldq_order_fail_11; // @[lsu.scala:225:36] reg ldq_order_fail_12; // @[lsu.scala:225:36] reg ldq_order_fail_13; // @[lsu.scala:225:36] reg ldq_order_fail_14; // @[lsu.scala:225:36] reg ldq_order_fail_15; // @[lsu.scala:225:36] reg ldq_order_fail_16; // @[lsu.scala:225:36] reg ldq_order_fail_17; // @[lsu.scala:225:36] reg ldq_order_fail_18; // @[lsu.scala:225:36] reg ldq_order_fail_19; // @[lsu.scala:225:36] reg ldq_order_fail_20; // @[lsu.scala:225:36] reg ldq_order_fail_21; // @[lsu.scala:225:36] reg ldq_order_fail_22; // @[lsu.scala:225:36] reg ldq_order_fail_23; // @[lsu.scala:225:36] reg ldq_observed_0; // @[lsu.scala:226:36] reg ldq_observed_1; // @[lsu.scala:226:36] reg ldq_observed_2; // @[lsu.scala:226:36] reg ldq_observed_3; // @[lsu.scala:226:36] reg ldq_observed_4; // @[lsu.scala:226:36] reg ldq_observed_5; // @[lsu.scala:226:36] reg ldq_observed_6; // @[lsu.scala:226:36] reg ldq_observed_7; // @[lsu.scala:226:36] reg ldq_observed_8; // @[lsu.scala:226:36] reg ldq_observed_9; // @[lsu.scala:226:36] reg ldq_observed_10; // @[lsu.scala:226:36] reg ldq_observed_11; // @[lsu.scala:226:36] reg ldq_observed_12; // @[lsu.scala:226:36] reg ldq_observed_13; // @[lsu.scala:226:36] reg ldq_observed_14; // @[lsu.scala:226:36] reg ldq_observed_15; // @[lsu.scala:226:36] reg ldq_observed_16; // @[lsu.scala:226:36] reg ldq_observed_17; // @[lsu.scala:226:36] reg ldq_observed_18; // @[lsu.scala:226:36] reg ldq_observed_19; // @[lsu.scala:226:36] reg ldq_observed_20; // @[lsu.scala:226:36] reg ldq_observed_21; // @[lsu.scala:226:36] reg ldq_observed_22; // @[lsu.scala:226:36] reg ldq_observed_23; // @[lsu.scala:226:36] reg [23:0] ldq_st_dep_mask_0; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_1; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_2; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_3; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_4; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_5; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_6; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_7; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_8; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_9; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_10; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_11; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_12; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_13; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_14; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_15; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_16; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_17; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_18; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_19; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_20; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_21; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_22; // @[lsu.scala:227:36] reg [23:0] ldq_st_dep_mask_23; // @[lsu.scala:227:36] reg [7:0] ldq_ld_byte_mask_0; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_1; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_2; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_3; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_4; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_5; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_6; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_7; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_8; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_9; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_10; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_11; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_12; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_13; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_14; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_15; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_16; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_17; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_18; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_19; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_20; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_21; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_22; // @[lsu.scala:228:36] reg [7:0] ldq_ld_byte_mask_23; // @[lsu.scala:228:36] reg ldq_forward_std_val_0; // @[lsu.scala:229:36] reg ldq_forward_std_val_1; // @[lsu.scala:229:36] reg ldq_forward_std_val_2; // @[lsu.scala:229:36] reg ldq_forward_std_val_3; // @[lsu.scala:229:36] reg ldq_forward_std_val_4; // @[lsu.scala:229:36] reg ldq_forward_std_val_5; // @[lsu.scala:229:36] reg ldq_forward_std_val_6; // @[lsu.scala:229:36] reg ldq_forward_std_val_7; // @[lsu.scala:229:36] reg ldq_forward_std_val_8; // @[lsu.scala:229:36] reg ldq_forward_std_val_9; // @[lsu.scala:229:36] reg ldq_forward_std_val_10; // @[lsu.scala:229:36] reg ldq_forward_std_val_11; // @[lsu.scala:229:36] reg ldq_forward_std_val_12; // @[lsu.scala:229:36] reg ldq_forward_std_val_13; // @[lsu.scala:229:36] reg ldq_forward_std_val_14; // @[lsu.scala:229:36] reg ldq_forward_std_val_15; // @[lsu.scala:229:36] reg ldq_forward_std_val_16; // @[lsu.scala:229:36] reg ldq_forward_std_val_17; // @[lsu.scala:229:36] reg ldq_forward_std_val_18; // @[lsu.scala:229:36] reg ldq_forward_std_val_19; // @[lsu.scala:229:36] reg ldq_forward_std_val_20; // @[lsu.scala:229:36] reg ldq_forward_std_val_21; // @[lsu.scala:229:36] reg ldq_forward_std_val_22; // @[lsu.scala:229:36] reg ldq_forward_std_val_23; // @[lsu.scala:229:36] reg [4:0] ldq_forward_stq_idx_0; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_1; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_2; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_3; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_4; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_5; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_6; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_7; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_8; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_9; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_10; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_11; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_12; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_13; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_14; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_15; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_16; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_17; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_18; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_19; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_20; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_21; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_22; // @[lsu.scala:230:36] reg [4:0] ldq_forward_stq_idx_23; // @[lsu.scala:230:36] reg [63:0] ldq_debug_wb_data_0; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_1; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_2; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_3; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_4; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_5; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_6; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_7; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_8; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_9; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_10; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_11; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_12; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_13; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_14; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_15; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_16; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_17; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_18; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_19; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_20; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_21; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_22; // @[lsu.scala:231:36] reg [63:0] ldq_debug_wb_data_23; // @[lsu.scala:231:36] reg stq_valid_0; // @[lsu.scala:251:32] reg stq_valid_1; // @[lsu.scala:251:32] reg stq_valid_2; // @[lsu.scala:251:32] reg stq_valid_3; // @[lsu.scala:251:32] reg stq_valid_4; // @[lsu.scala:251:32] reg stq_valid_5; // @[lsu.scala:251:32] reg stq_valid_6; // @[lsu.scala:251:32] reg stq_valid_7; // @[lsu.scala:251:32] reg stq_valid_8; // @[lsu.scala:251:32] reg stq_valid_9; // @[lsu.scala:251:32] reg stq_valid_10; // @[lsu.scala:251:32] reg stq_valid_11; // @[lsu.scala:251:32] reg stq_valid_12; // @[lsu.scala:251:32] reg stq_valid_13; // @[lsu.scala:251:32] reg stq_valid_14; // @[lsu.scala:251:32] reg stq_valid_15; // @[lsu.scala:251:32] reg stq_valid_16; // @[lsu.scala:251:32] reg stq_valid_17; // @[lsu.scala:251:32] reg stq_valid_18; // @[lsu.scala:251:32] reg stq_valid_19; // @[lsu.scala:251:32] reg stq_valid_20; // @[lsu.scala:251:32] reg stq_valid_21; // @[lsu.scala:251:32] reg stq_valid_22; // @[lsu.scala:251:32] reg stq_valid_23; // @[lsu.scala:251:32] reg [31:0] stq_uop_0_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_inst = stq_uop_0_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_0_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_3_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_1_debug_inst = stq_uop_0_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rvc; // @[lsu.scala:252:32] wire s_uop_3_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rvc = stq_uop_0_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_0_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_3_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_1_debug_pc = stq_uop_0_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_0; // @[lsu.scala:252:32] wire s_uop_3_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_0 = stq_uop_0_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_1; // @[lsu.scala:252:32] wire s_uop_3_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_1 = stq_uop_0_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_2; // @[lsu.scala:252:32] wire s_uop_3_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_2 = stq_uop_0_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iq_type_3; // @[lsu.scala:252:32] wire s_uop_3_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_iq_type_3 = stq_uop_0_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_0; // @[lsu.scala:252:32] wire s_uop_3_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_0 = stq_uop_0_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_1; // @[lsu.scala:252:32] wire s_uop_3_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_1 = stq_uop_0_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_2; // @[lsu.scala:252:32] wire s_uop_3_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_2 = stq_uop_0_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_3; // @[lsu.scala:252:32] wire s_uop_3_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_3 = stq_uop_0_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_4; // @[lsu.scala:252:32] wire s_uop_3_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_4 = stq_uop_0_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_5; // @[lsu.scala:252:32] wire s_uop_3_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_5 = stq_uop_0_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_6; // @[lsu.scala:252:32] wire s_uop_3_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_6 = stq_uop_0_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_7; // @[lsu.scala:252:32] wire s_uop_3_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_7 = stq_uop_0_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_8; // @[lsu.scala:252:32] wire s_uop_3_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_8 = stq_uop_0_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fu_code_9; // @[lsu.scala:252:32] wire s_uop_3_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_1_fu_code_9 = stq_uop_0_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued; // @[lsu.scala:252:32] wire s_uop_3_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued = stq_uop_0_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_agen = stq_uop_0_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_3_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_issued_partial_dgen = stq_uop_0_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_3_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_iw_p1_speculative_child = stq_uop_0_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_3_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_iw_p2_speculative_child = stq_uop_0_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p1_bypass_hint = stq_uop_0_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p2_bypass_hint = stq_uop_0_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_3_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_1_iw_p3_bypass_hint = stq_uop_0_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_dis_col_sel = stq_uop_0_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_0_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_3_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_1_br_mask = stq_uop_0_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_tag = stq_uop_0_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_0_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_3_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_1_br_type = stq_uop_0_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfb; // @[lsu.scala:252:32] wire s_uop_3_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfb = stq_uop_0_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fence; // @[lsu.scala:252:32] wire s_uop_3_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fence = stq_uop_0_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_fencei; // @[lsu.scala:252:32] wire s_uop_3_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_fencei = stq_uop_0_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sfence; // @[lsu.scala:252:32] wire s_uop_3_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sfence = stq_uop_0_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_amo; // @[lsu.scala:252:32] wire s_uop_3_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_amo = stq_uop_0_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_eret; // @[lsu.scala:252:32] wire s_uop_3_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_eret = stq_uop_0_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_3_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_sys_pc2epc = stq_uop_0_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_rocc; // @[lsu.scala:252:32] wire s_uop_3_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_rocc = stq_uop_0_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_mov; // @[lsu.scala:252:32] wire s_uop_3_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_mov = stq_uop_0_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ftq_idx = stq_uop_0_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_edge_inst; // @[lsu.scala:252:32] wire s_uop_3_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_1_edge_inst = stq_uop_0_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_3_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_pc_lob = stq_uop_0_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_taken; // @[lsu.scala:252:32] wire s_uop_3_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1324:37] wire uop_1_taken = stq_uop_0_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_imm_rename; // @[lsu.scala:252:32] wire s_uop_3_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_1_imm_rename = stq_uop_0_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_imm_sel = stq_uop_0_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_3_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_pimm = stq_uop_0_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_0_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_3_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_1_imm_packed = stq_uop_0_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_3_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_op1_sel = stq_uop_0_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_3_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_op2_sel = stq_uop_0_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ldst = stq_uop_0_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wen = stq_uop_0_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren1 = stq_uop_0_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren2 = stq_uop_0_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_ren3 = stq_uop_0_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap12 = stq_uop_0_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_swap23 = stq_uop_0_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagIn = stq_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_ctrl_typeTagOut = stq_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fromint = stq_uop_0_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_toint = stq_uop_0_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fastpipe = stq_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_fma = stq_uop_0_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_div = stq_uop_0_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_sqrt = stq_uop_0_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_wflags = stq_uop_0_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_3_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_ctrl_vec = stq_uop_0_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_3_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_rob_idx = stq_uop_0_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ldq_idx = stq_uop_0_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_3_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_stq_idx = stq_uop_0_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_3_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_rxq_idx = stq_uop_0_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_pdst = stq_uop_0_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs1 = stq_uop_0_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs2 = stq_uop_0_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_3_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_prs3 = stq_uop_0_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_3_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_ppred = stq_uop_0_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs1_busy; // @[lsu.scala:252:32] wire s_uop_3_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs1_busy = stq_uop_0_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs2_busy; // @[lsu.scala:252:32] wire s_uop_3_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs2_busy = stq_uop_0_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_prs3_busy; // @[lsu.scala:252:32] wire s_uop_3_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_prs3_busy = stq_uop_0_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ppred_busy; // @[lsu.scala:252:32] wire s_uop_3_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_1_ppred_busy = stq_uop_0_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_0_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_3_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_1_stale_pdst = stq_uop_0_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_exception; // @[lsu.scala:252:32] wire s_uop_3_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1324:37] wire uop_1_exception = stq_uop_0_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_0_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_3_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_1_exc_cause = stq_uop_0_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_3_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_mem_cmd = stq_uop_0_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_3_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_mem_size = stq_uop_0_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_mem_signed; // @[lsu.scala:252:32] wire s_uop_3_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_1_mem_signed = stq_uop_0_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_ldq; // @[lsu.scala:252:32] wire s_uop_3_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_ldq = stq_uop_0_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_uses_stq; // @[lsu.scala:252:32] wire s_uop_3_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_1_uses_stq = stq_uop_0_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_is_unique; // @[lsu.scala:252:32] wire s_uop_3_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_1_is_unique = stq_uop_0_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_3_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_1_flush_on_commit = stq_uop_0_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_3_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_csr_cmd = stq_uop_0_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_3_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_1_ldst_is_rs1 = stq_uop_0_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_3_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_ldst = stq_uop_0_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs1 = stq_uop_0_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs2 = stq_uop_0_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_0_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_3_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_1_lrs3 = stq_uop_0_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_dst_rtype = stq_uop_0_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs1_rtype = stq_uop_0_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_3_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_lrs2_rtype = stq_uop_0_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_frs3_en; // @[lsu.scala:252:32] wire s_uop_3_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_1_frs3_en = stq_uop_0_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fcn_dw; // @[lsu.scala:252:32] wire s_uop_3_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_1_fcn_dw = stq_uop_0_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_0_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_3_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_1_fcn_op = stq_uop_0_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_fp_val; // @[lsu.scala:252:32] wire s_uop_3_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_1_fp_val = stq_uop_0_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_3_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_fp_rm = stq_uop_0_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_0_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_3_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_1_fp_typ = stq_uop_0_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_pf_if = stq_uop_0_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ae_if = stq_uop_0_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_3_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_xcpt_ma_if = stq_uop_0_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_3_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_debug_if = stq_uop_0_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_3_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_1_bp_xcpt_if = stq_uop_0_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_fsrc = stq_uop_0_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_0_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_3_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_1_debug_tsrc = stq_uop_0_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_inst = stq_uop_1_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_1_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_4_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_2_debug_inst = stq_uop_1_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rvc; // @[lsu.scala:252:32] wire s_uop_4_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rvc = stq_uop_1_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_1_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_4_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_2_debug_pc = stq_uop_1_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_0; // @[lsu.scala:252:32] wire s_uop_4_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_0 = stq_uop_1_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_1; // @[lsu.scala:252:32] wire s_uop_4_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_1 = stq_uop_1_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_2; // @[lsu.scala:252:32] wire s_uop_4_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_2 = stq_uop_1_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iq_type_3; // @[lsu.scala:252:32] wire s_uop_4_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_iq_type_3 = stq_uop_1_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_0; // @[lsu.scala:252:32] wire s_uop_4_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_0 = stq_uop_1_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_1; // @[lsu.scala:252:32] wire s_uop_4_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_1 = stq_uop_1_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_2; // @[lsu.scala:252:32] wire s_uop_4_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_2 = stq_uop_1_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_3; // @[lsu.scala:252:32] wire s_uop_4_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_3 = stq_uop_1_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_4; // @[lsu.scala:252:32] wire s_uop_4_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_4 = stq_uop_1_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_5; // @[lsu.scala:252:32] wire s_uop_4_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_5 = stq_uop_1_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_6; // @[lsu.scala:252:32] wire s_uop_4_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_6 = stq_uop_1_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_7; // @[lsu.scala:252:32] wire s_uop_4_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_7 = stq_uop_1_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_8; // @[lsu.scala:252:32] wire s_uop_4_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_8 = stq_uop_1_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fu_code_9; // @[lsu.scala:252:32] wire s_uop_4_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_2_fu_code_9 = stq_uop_1_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued; // @[lsu.scala:252:32] wire s_uop_4_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued = stq_uop_1_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_agen = stq_uop_1_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_4_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_issued_partial_dgen = stq_uop_1_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_4_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_iw_p1_speculative_child = stq_uop_1_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_4_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_iw_p2_speculative_child = stq_uop_1_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p1_bypass_hint = stq_uop_1_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p2_bypass_hint = stq_uop_1_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_4_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_2_iw_p3_bypass_hint = stq_uop_1_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_dis_col_sel = stq_uop_1_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_1_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_4_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_2_br_mask = stq_uop_1_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_tag = stq_uop_1_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_1_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_4_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_2_br_type = stq_uop_1_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfb; // @[lsu.scala:252:32] wire s_uop_4_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfb = stq_uop_1_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fence; // @[lsu.scala:252:32] wire s_uop_4_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fence = stq_uop_1_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_fencei; // @[lsu.scala:252:32] wire s_uop_4_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_fencei = stq_uop_1_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sfence; // @[lsu.scala:252:32] wire s_uop_4_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sfence = stq_uop_1_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_amo; // @[lsu.scala:252:32] wire s_uop_4_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_amo = stq_uop_1_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_eret; // @[lsu.scala:252:32] wire s_uop_4_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_eret = stq_uop_1_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_4_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_sys_pc2epc = stq_uop_1_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_rocc; // @[lsu.scala:252:32] wire s_uop_4_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_rocc = stq_uop_1_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_mov; // @[lsu.scala:252:32] wire s_uop_4_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_mov = stq_uop_1_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ftq_idx = stq_uop_1_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_edge_inst; // @[lsu.scala:252:32] wire s_uop_4_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_2_edge_inst = stq_uop_1_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_4_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_pc_lob = stq_uop_1_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_taken; // @[lsu.scala:252:32] wire s_uop_4_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1324:37] wire uop_2_taken = stq_uop_1_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_imm_rename; // @[lsu.scala:252:32] wire s_uop_4_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_2_imm_rename = stq_uop_1_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_imm_sel = stq_uop_1_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_4_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_pimm = stq_uop_1_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_1_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_4_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_2_imm_packed = stq_uop_1_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_4_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_op1_sel = stq_uop_1_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_4_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_op2_sel = stq_uop_1_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ldst = stq_uop_1_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wen = stq_uop_1_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren1 = stq_uop_1_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren2 = stq_uop_1_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_ren3 = stq_uop_1_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap12 = stq_uop_1_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_swap23 = stq_uop_1_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagIn = stq_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_ctrl_typeTagOut = stq_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fromint = stq_uop_1_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_toint = stq_uop_1_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fastpipe = stq_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_fma = stq_uop_1_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_div = stq_uop_1_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_sqrt = stq_uop_1_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_wflags = stq_uop_1_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_4_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_ctrl_vec = stq_uop_1_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_4_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_rob_idx = stq_uop_1_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ldq_idx = stq_uop_1_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_4_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_stq_idx = stq_uop_1_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_4_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_rxq_idx = stq_uop_1_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_pdst = stq_uop_1_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs1 = stq_uop_1_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs2 = stq_uop_1_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_4_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_prs3 = stq_uop_1_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_4_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_ppred = stq_uop_1_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs1_busy; // @[lsu.scala:252:32] wire s_uop_4_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs1_busy = stq_uop_1_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs2_busy; // @[lsu.scala:252:32] wire s_uop_4_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs2_busy = stq_uop_1_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_prs3_busy; // @[lsu.scala:252:32] wire s_uop_4_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_prs3_busy = stq_uop_1_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ppred_busy; // @[lsu.scala:252:32] wire s_uop_4_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_2_ppred_busy = stq_uop_1_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_1_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_4_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_2_stale_pdst = stq_uop_1_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_exception; // @[lsu.scala:252:32] wire s_uop_4_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1324:37] wire uop_2_exception = stq_uop_1_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_1_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_4_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_2_exc_cause = stq_uop_1_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_4_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_mem_cmd = stq_uop_1_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_4_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_mem_size = stq_uop_1_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_mem_signed; // @[lsu.scala:252:32] wire s_uop_4_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_2_mem_signed = stq_uop_1_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_ldq; // @[lsu.scala:252:32] wire s_uop_4_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_ldq = stq_uop_1_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_uses_stq; // @[lsu.scala:252:32] wire s_uop_4_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_2_uses_stq = stq_uop_1_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_is_unique; // @[lsu.scala:252:32] wire s_uop_4_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_2_is_unique = stq_uop_1_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_4_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_2_flush_on_commit = stq_uop_1_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_4_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_csr_cmd = stq_uop_1_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_4_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_2_ldst_is_rs1 = stq_uop_1_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_4_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_ldst = stq_uop_1_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs1 = stq_uop_1_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs2 = stq_uop_1_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_1_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_4_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_2_lrs3 = stq_uop_1_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_dst_rtype = stq_uop_1_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs1_rtype = stq_uop_1_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_4_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_lrs2_rtype = stq_uop_1_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_frs3_en; // @[lsu.scala:252:32] wire s_uop_4_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_2_frs3_en = stq_uop_1_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fcn_dw; // @[lsu.scala:252:32] wire s_uop_4_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_2_fcn_dw = stq_uop_1_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_1_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_4_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_2_fcn_op = stq_uop_1_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_fp_val; // @[lsu.scala:252:32] wire s_uop_4_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_2_fp_val = stq_uop_1_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_4_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_fp_rm = stq_uop_1_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_1_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_4_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_2_fp_typ = stq_uop_1_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_pf_if = stq_uop_1_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ae_if = stq_uop_1_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_4_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_xcpt_ma_if = stq_uop_1_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_4_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_debug_if = stq_uop_1_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_4_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_2_bp_xcpt_if = stq_uop_1_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_fsrc = stq_uop_1_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_1_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_4_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_2_debug_tsrc = stq_uop_1_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_inst = stq_uop_2_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_2_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_5_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_3_debug_inst = stq_uop_2_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rvc; // @[lsu.scala:252:32] wire s_uop_5_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rvc = stq_uop_2_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_2_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_5_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_3_debug_pc = stq_uop_2_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_0; // @[lsu.scala:252:32] wire s_uop_5_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_0 = stq_uop_2_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_1; // @[lsu.scala:252:32] wire s_uop_5_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_1 = stq_uop_2_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_2; // @[lsu.scala:252:32] wire s_uop_5_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_2 = stq_uop_2_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iq_type_3; // @[lsu.scala:252:32] wire s_uop_5_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_iq_type_3 = stq_uop_2_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_0; // @[lsu.scala:252:32] wire s_uop_5_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_0 = stq_uop_2_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_1; // @[lsu.scala:252:32] wire s_uop_5_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_1 = stq_uop_2_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_2; // @[lsu.scala:252:32] wire s_uop_5_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_2 = stq_uop_2_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_3; // @[lsu.scala:252:32] wire s_uop_5_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_3 = stq_uop_2_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_4; // @[lsu.scala:252:32] wire s_uop_5_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_4 = stq_uop_2_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_5; // @[lsu.scala:252:32] wire s_uop_5_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_5 = stq_uop_2_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_6; // @[lsu.scala:252:32] wire s_uop_5_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_6 = stq_uop_2_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_7; // @[lsu.scala:252:32] wire s_uop_5_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_7 = stq_uop_2_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_8; // @[lsu.scala:252:32] wire s_uop_5_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_8 = stq_uop_2_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fu_code_9; // @[lsu.scala:252:32] wire s_uop_5_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_3_fu_code_9 = stq_uop_2_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued; // @[lsu.scala:252:32] wire s_uop_5_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued = stq_uop_2_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_agen = stq_uop_2_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_5_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_issued_partial_dgen = stq_uop_2_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_5_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_iw_p1_speculative_child = stq_uop_2_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_5_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_iw_p2_speculative_child = stq_uop_2_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p1_bypass_hint = stq_uop_2_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p2_bypass_hint = stq_uop_2_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_5_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_3_iw_p3_bypass_hint = stq_uop_2_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_dis_col_sel = stq_uop_2_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_2_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_5_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_3_br_mask = stq_uop_2_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_tag = stq_uop_2_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_2_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_5_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_3_br_type = stq_uop_2_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfb; // @[lsu.scala:252:32] wire s_uop_5_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfb = stq_uop_2_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fence; // @[lsu.scala:252:32] wire s_uop_5_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fence = stq_uop_2_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_fencei; // @[lsu.scala:252:32] wire s_uop_5_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_fencei = stq_uop_2_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sfence; // @[lsu.scala:252:32] wire s_uop_5_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sfence = stq_uop_2_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_amo; // @[lsu.scala:252:32] wire s_uop_5_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_amo = stq_uop_2_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_eret; // @[lsu.scala:252:32] wire s_uop_5_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_eret = stq_uop_2_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_5_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_sys_pc2epc = stq_uop_2_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_rocc; // @[lsu.scala:252:32] wire s_uop_5_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_rocc = stq_uop_2_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_mov; // @[lsu.scala:252:32] wire s_uop_5_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_mov = stq_uop_2_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ftq_idx = stq_uop_2_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_edge_inst; // @[lsu.scala:252:32] wire s_uop_5_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_3_edge_inst = stq_uop_2_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_5_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_pc_lob = stq_uop_2_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_taken; // @[lsu.scala:252:32] wire s_uop_5_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1324:37] wire uop_3_taken = stq_uop_2_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_imm_rename; // @[lsu.scala:252:32] wire s_uop_5_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_3_imm_rename = stq_uop_2_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_imm_sel = stq_uop_2_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_5_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_pimm = stq_uop_2_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_2_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_5_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_3_imm_packed = stq_uop_2_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_5_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_op1_sel = stq_uop_2_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_5_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_op2_sel = stq_uop_2_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ldst = stq_uop_2_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wen = stq_uop_2_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren1 = stq_uop_2_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren2 = stq_uop_2_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_ren3 = stq_uop_2_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap12 = stq_uop_2_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_swap23 = stq_uop_2_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagIn = stq_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_ctrl_typeTagOut = stq_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fromint = stq_uop_2_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_toint = stq_uop_2_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fastpipe = stq_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_fma = stq_uop_2_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_div = stq_uop_2_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_sqrt = stq_uop_2_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_wflags = stq_uop_2_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_5_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_ctrl_vec = stq_uop_2_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_5_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_rob_idx = stq_uop_2_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ldq_idx = stq_uop_2_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_5_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_stq_idx = stq_uop_2_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_5_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_rxq_idx = stq_uop_2_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_pdst = stq_uop_2_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs1 = stq_uop_2_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs2 = stq_uop_2_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_5_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_prs3 = stq_uop_2_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_5_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_ppred = stq_uop_2_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs1_busy; // @[lsu.scala:252:32] wire s_uop_5_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs1_busy = stq_uop_2_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs2_busy; // @[lsu.scala:252:32] wire s_uop_5_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs2_busy = stq_uop_2_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_prs3_busy; // @[lsu.scala:252:32] wire s_uop_5_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_prs3_busy = stq_uop_2_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ppred_busy; // @[lsu.scala:252:32] wire s_uop_5_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_3_ppred_busy = stq_uop_2_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_2_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_5_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_3_stale_pdst = stq_uop_2_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_exception; // @[lsu.scala:252:32] wire s_uop_5_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1324:37] wire uop_3_exception = stq_uop_2_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_2_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_5_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_3_exc_cause = stq_uop_2_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_5_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_mem_cmd = stq_uop_2_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_5_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_mem_size = stq_uop_2_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_mem_signed; // @[lsu.scala:252:32] wire s_uop_5_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_3_mem_signed = stq_uop_2_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_ldq; // @[lsu.scala:252:32] wire s_uop_5_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_ldq = stq_uop_2_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_uses_stq; // @[lsu.scala:252:32] wire s_uop_5_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_3_uses_stq = stq_uop_2_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_is_unique; // @[lsu.scala:252:32] wire s_uop_5_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_3_is_unique = stq_uop_2_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_5_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_3_flush_on_commit = stq_uop_2_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_5_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_csr_cmd = stq_uop_2_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_5_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_3_ldst_is_rs1 = stq_uop_2_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_5_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_ldst = stq_uop_2_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs1 = stq_uop_2_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs2 = stq_uop_2_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_2_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_5_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_3_lrs3 = stq_uop_2_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_dst_rtype = stq_uop_2_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs1_rtype = stq_uop_2_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_5_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_lrs2_rtype = stq_uop_2_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_frs3_en; // @[lsu.scala:252:32] wire s_uop_5_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_3_frs3_en = stq_uop_2_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fcn_dw; // @[lsu.scala:252:32] wire s_uop_5_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_3_fcn_dw = stq_uop_2_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_2_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_5_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_3_fcn_op = stq_uop_2_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_fp_val; // @[lsu.scala:252:32] wire s_uop_5_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_3_fp_val = stq_uop_2_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_5_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_fp_rm = stq_uop_2_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_2_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_5_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_3_fp_typ = stq_uop_2_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_pf_if = stq_uop_2_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ae_if = stq_uop_2_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_5_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_xcpt_ma_if = stq_uop_2_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_5_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_debug_if = stq_uop_2_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_5_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_3_bp_xcpt_if = stq_uop_2_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_fsrc = stq_uop_2_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_2_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_5_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_3_debug_tsrc = stq_uop_2_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_inst = stq_uop_3_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_3_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_6_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_4_debug_inst = stq_uop_3_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rvc; // @[lsu.scala:252:32] wire s_uop_6_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rvc = stq_uop_3_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_3_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_6_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_4_debug_pc = stq_uop_3_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_0; // @[lsu.scala:252:32] wire s_uop_6_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_0 = stq_uop_3_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_1; // @[lsu.scala:252:32] wire s_uop_6_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_1 = stq_uop_3_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_2; // @[lsu.scala:252:32] wire s_uop_6_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_2 = stq_uop_3_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iq_type_3; // @[lsu.scala:252:32] wire s_uop_6_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_iq_type_3 = stq_uop_3_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_0; // @[lsu.scala:252:32] wire s_uop_6_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_0 = stq_uop_3_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_1; // @[lsu.scala:252:32] wire s_uop_6_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_1 = stq_uop_3_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_2; // @[lsu.scala:252:32] wire s_uop_6_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_2 = stq_uop_3_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_3; // @[lsu.scala:252:32] wire s_uop_6_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_3 = stq_uop_3_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_4; // @[lsu.scala:252:32] wire s_uop_6_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_4 = stq_uop_3_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_5; // @[lsu.scala:252:32] wire s_uop_6_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_5 = stq_uop_3_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_6; // @[lsu.scala:252:32] wire s_uop_6_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_6 = stq_uop_3_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_7; // @[lsu.scala:252:32] wire s_uop_6_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_7 = stq_uop_3_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_8; // @[lsu.scala:252:32] wire s_uop_6_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_8 = stq_uop_3_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fu_code_9; // @[lsu.scala:252:32] wire s_uop_6_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_4_fu_code_9 = stq_uop_3_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued; // @[lsu.scala:252:32] wire s_uop_6_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued = stq_uop_3_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_agen = stq_uop_3_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_6_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_issued_partial_dgen = stq_uop_3_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_6_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_iw_p1_speculative_child = stq_uop_3_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_6_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_iw_p2_speculative_child = stq_uop_3_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p1_bypass_hint = stq_uop_3_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p2_bypass_hint = stq_uop_3_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_6_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_4_iw_p3_bypass_hint = stq_uop_3_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_dis_col_sel = stq_uop_3_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_3_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_6_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_4_br_mask = stq_uop_3_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_tag = stq_uop_3_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_3_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_6_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_4_br_type = stq_uop_3_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfb; // @[lsu.scala:252:32] wire s_uop_6_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfb = stq_uop_3_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fence; // @[lsu.scala:252:32] wire s_uop_6_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fence = stq_uop_3_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_fencei; // @[lsu.scala:252:32] wire s_uop_6_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_fencei = stq_uop_3_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sfence; // @[lsu.scala:252:32] wire s_uop_6_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sfence = stq_uop_3_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_amo; // @[lsu.scala:252:32] wire s_uop_6_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_amo = stq_uop_3_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_eret; // @[lsu.scala:252:32] wire s_uop_6_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_eret = stq_uop_3_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_6_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_sys_pc2epc = stq_uop_3_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_rocc; // @[lsu.scala:252:32] wire s_uop_6_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_rocc = stq_uop_3_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_mov; // @[lsu.scala:252:32] wire s_uop_6_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_mov = stq_uop_3_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ftq_idx = stq_uop_3_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_edge_inst; // @[lsu.scala:252:32] wire s_uop_6_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_4_edge_inst = stq_uop_3_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_6_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_pc_lob = stq_uop_3_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_taken; // @[lsu.scala:252:32] wire s_uop_6_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1324:37] wire uop_4_taken = stq_uop_3_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_imm_rename; // @[lsu.scala:252:32] wire s_uop_6_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_4_imm_rename = stq_uop_3_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_imm_sel = stq_uop_3_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_6_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_pimm = stq_uop_3_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_3_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_6_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_4_imm_packed = stq_uop_3_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_6_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_op1_sel = stq_uop_3_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_6_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_op2_sel = stq_uop_3_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ldst = stq_uop_3_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wen = stq_uop_3_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren1 = stq_uop_3_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren2 = stq_uop_3_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_ren3 = stq_uop_3_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap12 = stq_uop_3_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_swap23 = stq_uop_3_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagIn = stq_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_ctrl_typeTagOut = stq_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fromint = stq_uop_3_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_toint = stq_uop_3_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fastpipe = stq_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_fma = stq_uop_3_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_div = stq_uop_3_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_sqrt = stq_uop_3_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_wflags = stq_uop_3_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_6_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_ctrl_vec = stq_uop_3_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_6_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_rob_idx = stq_uop_3_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ldq_idx = stq_uop_3_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_6_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_stq_idx = stq_uop_3_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_6_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_rxq_idx = stq_uop_3_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_pdst = stq_uop_3_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs1 = stq_uop_3_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs2 = stq_uop_3_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_6_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_prs3 = stq_uop_3_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_6_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_ppred = stq_uop_3_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs1_busy; // @[lsu.scala:252:32] wire s_uop_6_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs1_busy = stq_uop_3_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs2_busy; // @[lsu.scala:252:32] wire s_uop_6_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs2_busy = stq_uop_3_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_prs3_busy; // @[lsu.scala:252:32] wire s_uop_6_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_prs3_busy = stq_uop_3_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ppred_busy; // @[lsu.scala:252:32] wire s_uop_6_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_4_ppred_busy = stq_uop_3_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_3_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_6_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_4_stale_pdst = stq_uop_3_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_exception; // @[lsu.scala:252:32] wire s_uop_6_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1324:37] wire uop_4_exception = stq_uop_3_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_3_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_6_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_4_exc_cause = stq_uop_3_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_6_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_mem_cmd = stq_uop_3_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_6_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_mem_size = stq_uop_3_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_mem_signed; // @[lsu.scala:252:32] wire s_uop_6_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_4_mem_signed = stq_uop_3_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_ldq; // @[lsu.scala:252:32] wire s_uop_6_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_ldq = stq_uop_3_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_uses_stq; // @[lsu.scala:252:32] wire s_uop_6_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_4_uses_stq = stq_uop_3_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_is_unique; // @[lsu.scala:252:32] wire s_uop_6_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_4_is_unique = stq_uop_3_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_6_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_4_flush_on_commit = stq_uop_3_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_6_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_csr_cmd = stq_uop_3_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_6_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_4_ldst_is_rs1 = stq_uop_3_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_6_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_ldst = stq_uop_3_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs1 = stq_uop_3_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs2 = stq_uop_3_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_3_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_6_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_4_lrs3 = stq_uop_3_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_dst_rtype = stq_uop_3_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs1_rtype = stq_uop_3_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_6_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_lrs2_rtype = stq_uop_3_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_frs3_en; // @[lsu.scala:252:32] wire s_uop_6_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_4_frs3_en = stq_uop_3_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fcn_dw; // @[lsu.scala:252:32] wire s_uop_6_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_4_fcn_dw = stq_uop_3_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_3_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_6_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_4_fcn_op = stq_uop_3_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_fp_val; // @[lsu.scala:252:32] wire s_uop_6_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_4_fp_val = stq_uop_3_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_6_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_fp_rm = stq_uop_3_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_3_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_6_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_4_fp_typ = stq_uop_3_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_pf_if = stq_uop_3_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ae_if = stq_uop_3_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_6_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_xcpt_ma_if = stq_uop_3_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_6_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_debug_if = stq_uop_3_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_6_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_4_bp_xcpt_if = stq_uop_3_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_fsrc = stq_uop_3_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_3_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_6_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_4_debug_tsrc = stq_uop_3_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_inst = stq_uop_4_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_4_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_7_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_5_debug_inst = stq_uop_4_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rvc; // @[lsu.scala:252:32] wire s_uop_7_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rvc = stq_uop_4_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_4_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_7_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_5_debug_pc = stq_uop_4_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_0; // @[lsu.scala:252:32] wire s_uop_7_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_0 = stq_uop_4_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_1; // @[lsu.scala:252:32] wire s_uop_7_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_1 = stq_uop_4_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_2; // @[lsu.scala:252:32] wire s_uop_7_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_2 = stq_uop_4_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iq_type_3; // @[lsu.scala:252:32] wire s_uop_7_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_iq_type_3 = stq_uop_4_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_0; // @[lsu.scala:252:32] wire s_uop_7_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_0 = stq_uop_4_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_1; // @[lsu.scala:252:32] wire s_uop_7_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_1 = stq_uop_4_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_2; // @[lsu.scala:252:32] wire s_uop_7_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_2 = stq_uop_4_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_3; // @[lsu.scala:252:32] wire s_uop_7_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_3 = stq_uop_4_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_4; // @[lsu.scala:252:32] wire s_uop_7_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_4 = stq_uop_4_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_5; // @[lsu.scala:252:32] wire s_uop_7_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_5 = stq_uop_4_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_6; // @[lsu.scala:252:32] wire s_uop_7_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_6 = stq_uop_4_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_7; // @[lsu.scala:252:32] wire s_uop_7_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_7 = stq_uop_4_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_8; // @[lsu.scala:252:32] wire s_uop_7_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_8 = stq_uop_4_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fu_code_9; // @[lsu.scala:252:32] wire s_uop_7_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_5_fu_code_9 = stq_uop_4_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued; // @[lsu.scala:252:32] wire s_uop_7_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued = stq_uop_4_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_agen = stq_uop_4_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_7_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_issued_partial_dgen = stq_uop_4_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_7_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_iw_p1_speculative_child = stq_uop_4_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_7_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_iw_p2_speculative_child = stq_uop_4_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p1_bypass_hint = stq_uop_4_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p2_bypass_hint = stq_uop_4_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_7_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_5_iw_p3_bypass_hint = stq_uop_4_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_dis_col_sel = stq_uop_4_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_4_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_7_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_5_br_mask = stq_uop_4_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_tag = stq_uop_4_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_4_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_7_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_5_br_type = stq_uop_4_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfb; // @[lsu.scala:252:32] wire s_uop_7_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfb = stq_uop_4_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fence; // @[lsu.scala:252:32] wire s_uop_7_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fence = stq_uop_4_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_fencei; // @[lsu.scala:252:32] wire s_uop_7_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_fencei = stq_uop_4_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sfence; // @[lsu.scala:252:32] wire s_uop_7_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sfence = stq_uop_4_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_amo; // @[lsu.scala:252:32] wire s_uop_7_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_amo = stq_uop_4_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_eret; // @[lsu.scala:252:32] wire s_uop_7_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_eret = stq_uop_4_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_7_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_sys_pc2epc = stq_uop_4_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_rocc; // @[lsu.scala:252:32] wire s_uop_7_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_rocc = stq_uop_4_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_mov; // @[lsu.scala:252:32] wire s_uop_7_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_mov = stq_uop_4_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ftq_idx = stq_uop_4_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_edge_inst; // @[lsu.scala:252:32] wire s_uop_7_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_5_edge_inst = stq_uop_4_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_7_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_pc_lob = stq_uop_4_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_taken; // @[lsu.scala:252:32] wire s_uop_7_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1324:37] wire uop_5_taken = stq_uop_4_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_imm_rename; // @[lsu.scala:252:32] wire s_uop_7_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_5_imm_rename = stq_uop_4_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_imm_sel = stq_uop_4_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_7_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_pimm = stq_uop_4_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_4_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_7_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_5_imm_packed = stq_uop_4_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_7_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_op1_sel = stq_uop_4_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_7_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_op2_sel = stq_uop_4_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ldst = stq_uop_4_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wen = stq_uop_4_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren1 = stq_uop_4_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren2 = stq_uop_4_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_ren3 = stq_uop_4_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap12 = stq_uop_4_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_swap23 = stq_uop_4_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagIn = stq_uop_4_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_ctrl_typeTagOut = stq_uop_4_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fromint = stq_uop_4_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_toint = stq_uop_4_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fastpipe = stq_uop_4_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_fma = stq_uop_4_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_div = stq_uop_4_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_sqrt = stq_uop_4_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_wflags = stq_uop_4_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_7_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_ctrl_vec = stq_uop_4_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_7_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_rob_idx = stq_uop_4_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ldq_idx = stq_uop_4_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_7_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_stq_idx = stq_uop_4_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_7_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_rxq_idx = stq_uop_4_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_pdst = stq_uop_4_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs1 = stq_uop_4_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs2 = stq_uop_4_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_7_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_prs3 = stq_uop_4_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_7_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_ppred = stq_uop_4_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs1_busy; // @[lsu.scala:252:32] wire s_uop_7_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs1_busy = stq_uop_4_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs2_busy; // @[lsu.scala:252:32] wire s_uop_7_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs2_busy = stq_uop_4_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_prs3_busy; // @[lsu.scala:252:32] wire s_uop_7_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_prs3_busy = stq_uop_4_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ppred_busy; // @[lsu.scala:252:32] wire s_uop_7_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_5_ppred_busy = stq_uop_4_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_4_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_7_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_5_stale_pdst = stq_uop_4_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_exception; // @[lsu.scala:252:32] wire s_uop_7_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1324:37] wire uop_5_exception = stq_uop_4_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_4_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_7_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_5_exc_cause = stq_uop_4_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_7_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_mem_cmd = stq_uop_4_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_7_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_mem_size = stq_uop_4_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_mem_signed; // @[lsu.scala:252:32] wire s_uop_7_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_5_mem_signed = stq_uop_4_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_ldq; // @[lsu.scala:252:32] wire s_uop_7_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_ldq = stq_uop_4_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_uses_stq; // @[lsu.scala:252:32] wire s_uop_7_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_5_uses_stq = stq_uop_4_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_is_unique; // @[lsu.scala:252:32] wire s_uop_7_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_5_is_unique = stq_uop_4_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_7_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_5_flush_on_commit = stq_uop_4_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_7_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_csr_cmd = stq_uop_4_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_7_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_5_ldst_is_rs1 = stq_uop_4_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_7_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_ldst = stq_uop_4_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs1 = stq_uop_4_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs2 = stq_uop_4_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_4_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_7_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_5_lrs3 = stq_uop_4_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_dst_rtype = stq_uop_4_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs1_rtype = stq_uop_4_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_7_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_lrs2_rtype = stq_uop_4_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_frs3_en; // @[lsu.scala:252:32] wire s_uop_7_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_5_frs3_en = stq_uop_4_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fcn_dw; // @[lsu.scala:252:32] wire s_uop_7_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_5_fcn_dw = stq_uop_4_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_4_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_7_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_5_fcn_op = stq_uop_4_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_fp_val; // @[lsu.scala:252:32] wire s_uop_7_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_5_fp_val = stq_uop_4_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_7_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_fp_rm = stq_uop_4_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_4_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_7_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_5_fp_typ = stq_uop_4_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_pf_if = stq_uop_4_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ae_if = stq_uop_4_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_7_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_xcpt_ma_if = stq_uop_4_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_7_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_debug_if = stq_uop_4_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_7_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_5_bp_xcpt_if = stq_uop_4_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_fsrc = stq_uop_4_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_4_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_7_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_5_debug_tsrc = stq_uop_4_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_inst = stq_uop_5_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_5_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_8_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_6_debug_inst = stq_uop_5_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rvc; // @[lsu.scala:252:32] wire s_uop_8_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rvc = stq_uop_5_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_5_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_8_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_6_debug_pc = stq_uop_5_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_0; // @[lsu.scala:252:32] wire s_uop_8_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_0 = stq_uop_5_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_1; // @[lsu.scala:252:32] wire s_uop_8_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_1 = stq_uop_5_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_2; // @[lsu.scala:252:32] wire s_uop_8_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_2 = stq_uop_5_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iq_type_3; // @[lsu.scala:252:32] wire s_uop_8_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_iq_type_3 = stq_uop_5_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_0; // @[lsu.scala:252:32] wire s_uop_8_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_0 = stq_uop_5_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_1; // @[lsu.scala:252:32] wire s_uop_8_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_1 = stq_uop_5_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_2; // @[lsu.scala:252:32] wire s_uop_8_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_2 = stq_uop_5_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_3; // @[lsu.scala:252:32] wire s_uop_8_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_3 = stq_uop_5_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_4; // @[lsu.scala:252:32] wire s_uop_8_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_4 = stq_uop_5_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_5; // @[lsu.scala:252:32] wire s_uop_8_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_5 = stq_uop_5_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_6; // @[lsu.scala:252:32] wire s_uop_8_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_6 = stq_uop_5_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_7; // @[lsu.scala:252:32] wire s_uop_8_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_7 = stq_uop_5_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_8; // @[lsu.scala:252:32] wire s_uop_8_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_8 = stq_uop_5_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fu_code_9; // @[lsu.scala:252:32] wire s_uop_8_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_6_fu_code_9 = stq_uop_5_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued; // @[lsu.scala:252:32] wire s_uop_8_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued = stq_uop_5_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_agen = stq_uop_5_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_8_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_issued_partial_dgen = stq_uop_5_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_8_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_iw_p1_speculative_child = stq_uop_5_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_8_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_iw_p2_speculative_child = stq_uop_5_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p1_bypass_hint = stq_uop_5_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p2_bypass_hint = stq_uop_5_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_8_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_6_iw_p3_bypass_hint = stq_uop_5_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_dis_col_sel = stq_uop_5_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_5_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_8_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_6_br_mask = stq_uop_5_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_tag = stq_uop_5_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_5_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_8_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_6_br_type = stq_uop_5_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfb; // @[lsu.scala:252:32] wire s_uop_8_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfb = stq_uop_5_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fence; // @[lsu.scala:252:32] wire s_uop_8_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fence = stq_uop_5_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_fencei; // @[lsu.scala:252:32] wire s_uop_8_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_fencei = stq_uop_5_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sfence; // @[lsu.scala:252:32] wire s_uop_8_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sfence = stq_uop_5_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_amo; // @[lsu.scala:252:32] wire s_uop_8_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_amo = stq_uop_5_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_eret; // @[lsu.scala:252:32] wire s_uop_8_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_eret = stq_uop_5_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_8_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_sys_pc2epc = stq_uop_5_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_rocc; // @[lsu.scala:252:32] wire s_uop_8_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_rocc = stq_uop_5_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_mov; // @[lsu.scala:252:32] wire s_uop_8_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_mov = stq_uop_5_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ftq_idx = stq_uop_5_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_edge_inst; // @[lsu.scala:252:32] wire s_uop_8_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_6_edge_inst = stq_uop_5_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_8_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_pc_lob = stq_uop_5_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_taken; // @[lsu.scala:252:32] wire s_uop_8_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1324:37] wire uop_6_taken = stq_uop_5_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_imm_rename; // @[lsu.scala:252:32] wire s_uop_8_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_6_imm_rename = stq_uop_5_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_imm_sel = stq_uop_5_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_8_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_pimm = stq_uop_5_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_5_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_8_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_6_imm_packed = stq_uop_5_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_8_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_op1_sel = stq_uop_5_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_8_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_op2_sel = stq_uop_5_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ldst = stq_uop_5_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wen = stq_uop_5_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren1 = stq_uop_5_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren2 = stq_uop_5_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_ren3 = stq_uop_5_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap12 = stq_uop_5_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_swap23 = stq_uop_5_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagIn = stq_uop_5_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_ctrl_typeTagOut = stq_uop_5_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fromint = stq_uop_5_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_toint = stq_uop_5_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fastpipe = stq_uop_5_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_fma = stq_uop_5_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_div = stq_uop_5_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_sqrt = stq_uop_5_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_wflags = stq_uop_5_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_8_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_ctrl_vec = stq_uop_5_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_8_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_rob_idx = stq_uop_5_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ldq_idx = stq_uop_5_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_8_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_stq_idx = stq_uop_5_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_8_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_rxq_idx = stq_uop_5_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_pdst = stq_uop_5_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs1 = stq_uop_5_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs2 = stq_uop_5_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_8_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_prs3 = stq_uop_5_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_8_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_ppred = stq_uop_5_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs1_busy; // @[lsu.scala:252:32] wire s_uop_8_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs1_busy = stq_uop_5_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs2_busy; // @[lsu.scala:252:32] wire s_uop_8_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs2_busy = stq_uop_5_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_prs3_busy; // @[lsu.scala:252:32] wire s_uop_8_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_prs3_busy = stq_uop_5_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ppred_busy; // @[lsu.scala:252:32] wire s_uop_8_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_6_ppred_busy = stq_uop_5_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_5_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_8_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_6_stale_pdst = stq_uop_5_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_exception; // @[lsu.scala:252:32] wire s_uop_8_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1324:37] wire uop_6_exception = stq_uop_5_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_5_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_8_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_6_exc_cause = stq_uop_5_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_8_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_mem_cmd = stq_uop_5_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_8_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_mem_size = stq_uop_5_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_mem_signed; // @[lsu.scala:252:32] wire s_uop_8_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_6_mem_signed = stq_uop_5_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_ldq; // @[lsu.scala:252:32] wire s_uop_8_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_ldq = stq_uop_5_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_uses_stq; // @[lsu.scala:252:32] wire s_uop_8_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_6_uses_stq = stq_uop_5_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_is_unique; // @[lsu.scala:252:32] wire s_uop_8_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_6_is_unique = stq_uop_5_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_8_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_6_flush_on_commit = stq_uop_5_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_8_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_csr_cmd = stq_uop_5_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_8_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_6_ldst_is_rs1 = stq_uop_5_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_8_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_ldst = stq_uop_5_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs1 = stq_uop_5_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs2 = stq_uop_5_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_5_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_8_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_6_lrs3 = stq_uop_5_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_dst_rtype = stq_uop_5_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs1_rtype = stq_uop_5_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_8_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_lrs2_rtype = stq_uop_5_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_frs3_en; // @[lsu.scala:252:32] wire s_uop_8_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_6_frs3_en = stq_uop_5_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fcn_dw; // @[lsu.scala:252:32] wire s_uop_8_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_6_fcn_dw = stq_uop_5_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_5_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_8_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_6_fcn_op = stq_uop_5_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_fp_val; // @[lsu.scala:252:32] wire s_uop_8_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_6_fp_val = stq_uop_5_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_8_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_fp_rm = stq_uop_5_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_5_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_8_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_6_fp_typ = stq_uop_5_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_pf_if = stq_uop_5_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ae_if = stq_uop_5_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_8_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_xcpt_ma_if = stq_uop_5_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_8_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_debug_if = stq_uop_5_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_8_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_6_bp_xcpt_if = stq_uop_5_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_fsrc = stq_uop_5_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_5_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_8_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_6_debug_tsrc = stq_uop_5_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_inst = stq_uop_6_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_6_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_9_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_7_debug_inst = stq_uop_6_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rvc; // @[lsu.scala:252:32] wire s_uop_9_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rvc = stq_uop_6_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_6_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_9_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_7_debug_pc = stq_uop_6_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_0; // @[lsu.scala:252:32] wire s_uop_9_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_0 = stq_uop_6_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_1; // @[lsu.scala:252:32] wire s_uop_9_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_1 = stq_uop_6_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_2; // @[lsu.scala:252:32] wire s_uop_9_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_2 = stq_uop_6_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iq_type_3; // @[lsu.scala:252:32] wire s_uop_9_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_iq_type_3 = stq_uop_6_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_0; // @[lsu.scala:252:32] wire s_uop_9_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_0 = stq_uop_6_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_1; // @[lsu.scala:252:32] wire s_uop_9_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_1 = stq_uop_6_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_2; // @[lsu.scala:252:32] wire s_uop_9_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_2 = stq_uop_6_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_3; // @[lsu.scala:252:32] wire s_uop_9_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_3 = stq_uop_6_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_4; // @[lsu.scala:252:32] wire s_uop_9_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_4 = stq_uop_6_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_5; // @[lsu.scala:252:32] wire s_uop_9_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_5 = stq_uop_6_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_6; // @[lsu.scala:252:32] wire s_uop_9_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_6 = stq_uop_6_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_7; // @[lsu.scala:252:32] wire s_uop_9_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_7 = stq_uop_6_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_8; // @[lsu.scala:252:32] wire s_uop_9_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_8 = stq_uop_6_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fu_code_9; // @[lsu.scala:252:32] wire s_uop_9_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_7_fu_code_9 = stq_uop_6_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued; // @[lsu.scala:252:32] wire s_uop_9_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued = stq_uop_6_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_agen = stq_uop_6_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_9_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_issued_partial_dgen = stq_uop_6_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_9_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_iw_p1_speculative_child = stq_uop_6_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_9_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_iw_p2_speculative_child = stq_uop_6_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p1_bypass_hint = stq_uop_6_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p2_bypass_hint = stq_uop_6_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_9_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_7_iw_p3_bypass_hint = stq_uop_6_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_dis_col_sel = stq_uop_6_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_6_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_9_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_7_br_mask = stq_uop_6_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_tag = stq_uop_6_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_6_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_9_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_7_br_type = stq_uop_6_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfb; // @[lsu.scala:252:32] wire s_uop_9_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfb = stq_uop_6_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fence; // @[lsu.scala:252:32] wire s_uop_9_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fence = stq_uop_6_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_fencei; // @[lsu.scala:252:32] wire s_uop_9_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_fencei = stq_uop_6_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sfence; // @[lsu.scala:252:32] wire s_uop_9_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sfence = stq_uop_6_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_amo; // @[lsu.scala:252:32] wire s_uop_9_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_amo = stq_uop_6_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_eret; // @[lsu.scala:252:32] wire s_uop_9_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_eret = stq_uop_6_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_9_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_sys_pc2epc = stq_uop_6_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_rocc; // @[lsu.scala:252:32] wire s_uop_9_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_rocc = stq_uop_6_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_mov; // @[lsu.scala:252:32] wire s_uop_9_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_mov = stq_uop_6_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ftq_idx = stq_uop_6_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_edge_inst; // @[lsu.scala:252:32] wire s_uop_9_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_7_edge_inst = stq_uop_6_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_9_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_pc_lob = stq_uop_6_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_taken; // @[lsu.scala:252:32] wire s_uop_9_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1324:37] wire uop_7_taken = stq_uop_6_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_imm_rename; // @[lsu.scala:252:32] wire s_uop_9_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_7_imm_rename = stq_uop_6_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_imm_sel = stq_uop_6_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_9_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_pimm = stq_uop_6_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_6_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_9_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_7_imm_packed = stq_uop_6_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_9_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_op1_sel = stq_uop_6_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_9_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_op2_sel = stq_uop_6_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ldst = stq_uop_6_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wen = stq_uop_6_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren1 = stq_uop_6_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren2 = stq_uop_6_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_ren3 = stq_uop_6_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap12 = stq_uop_6_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_swap23 = stq_uop_6_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagIn = stq_uop_6_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_ctrl_typeTagOut = stq_uop_6_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fromint = stq_uop_6_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_toint = stq_uop_6_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fastpipe = stq_uop_6_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_fma = stq_uop_6_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_div = stq_uop_6_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_sqrt = stq_uop_6_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_wflags = stq_uop_6_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_9_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_ctrl_vec = stq_uop_6_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_9_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_rob_idx = stq_uop_6_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ldq_idx = stq_uop_6_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_9_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_stq_idx = stq_uop_6_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_9_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_rxq_idx = stq_uop_6_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_pdst = stq_uop_6_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs1 = stq_uop_6_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs2 = stq_uop_6_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_9_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_prs3 = stq_uop_6_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_9_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_ppred = stq_uop_6_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs1_busy; // @[lsu.scala:252:32] wire s_uop_9_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs1_busy = stq_uop_6_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs2_busy; // @[lsu.scala:252:32] wire s_uop_9_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs2_busy = stq_uop_6_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_prs3_busy; // @[lsu.scala:252:32] wire s_uop_9_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_prs3_busy = stq_uop_6_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ppred_busy; // @[lsu.scala:252:32] wire s_uop_9_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_7_ppred_busy = stq_uop_6_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_6_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_9_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_7_stale_pdst = stq_uop_6_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_exception; // @[lsu.scala:252:32] wire s_uop_9_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1324:37] wire uop_7_exception = stq_uop_6_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_6_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_9_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_7_exc_cause = stq_uop_6_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_9_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_mem_cmd = stq_uop_6_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_9_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_mem_size = stq_uop_6_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_mem_signed; // @[lsu.scala:252:32] wire s_uop_9_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_7_mem_signed = stq_uop_6_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_ldq; // @[lsu.scala:252:32] wire s_uop_9_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_ldq = stq_uop_6_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_uses_stq; // @[lsu.scala:252:32] wire s_uop_9_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_7_uses_stq = stq_uop_6_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_is_unique; // @[lsu.scala:252:32] wire s_uop_9_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_7_is_unique = stq_uop_6_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_9_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_7_flush_on_commit = stq_uop_6_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_9_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_csr_cmd = stq_uop_6_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_9_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_7_ldst_is_rs1 = stq_uop_6_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_9_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_ldst = stq_uop_6_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs1 = stq_uop_6_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs2 = stq_uop_6_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_6_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_9_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_7_lrs3 = stq_uop_6_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_dst_rtype = stq_uop_6_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs1_rtype = stq_uop_6_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_9_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_lrs2_rtype = stq_uop_6_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_frs3_en; // @[lsu.scala:252:32] wire s_uop_9_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_7_frs3_en = stq_uop_6_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fcn_dw; // @[lsu.scala:252:32] wire s_uop_9_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_7_fcn_dw = stq_uop_6_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_6_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_9_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_7_fcn_op = stq_uop_6_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_fp_val; // @[lsu.scala:252:32] wire s_uop_9_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_7_fp_val = stq_uop_6_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_9_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_fp_rm = stq_uop_6_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_6_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_9_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_7_fp_typ = stq_uop_6_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_pf_if = stq_uop_6_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ae_if = stq_uop_6_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_9_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_xcpt_ma_if = stq_uop_6_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_9_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_debug_if = stq_uop_6_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_9_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_7_bp_xcpt_if = stq_uop_6_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_fsrc = stq_uop_6_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_6_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_9_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_7_debug_tsrc = stq_uop_6_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_inst = stq_uop_7_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_7_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_10_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_8_debug_inst = stq_uop_7_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rvc; // @[lsu.scala:252:32] wire s_uop_10_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rvc = stq_uop_7_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_7_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_10_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_8_debug_pc = stq_uop_7_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_0; // @[lsu.scala:252:32] wire s_uop_10_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_0 = stq_uop_7_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_1; // @[lsu.scala:252:32] wire s_uop_10_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_1 = stq_uop_7_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_2; // @[lsu.scala:252:32] wire s_uop_10_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_2 = stq_uop_7_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iq_type_3; // @[lsu.scala:252:32] wire s_uop_10_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_iq_type_3 = stq_uop_7_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_0; // @[lsu.scala:252:32] wire s_uop_10_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_0 = stq_uop_7_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_1; // @[lsu.scala:252:32] wire s_uop_10_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_1 = stq_uop_7_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_2; // @[lsu.scala:252:32] wire s_uop_10_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_2 = stq_uop_7_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_3; // @[lsu.scala:252:32] wire s_uop_10_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_3 = stq_uop_7_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_4; // @[lsu.scala:252:32] wire s_uop_10_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_4 = stq_uop_7_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_5; // @[lsu.scala:252:32] wire s_uop_10_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_5 = stq_uop_7_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_6; // @[lsu.scala:252:32] wire s_uop_10_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_6 = stq_uop_7_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_7; // @[lsu.scala:252:32] wire s_uop_10_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_7 = stq_uop_7_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_8; // @[lsu.scala:252:32] wire s_uop_10_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_8 = stq_uop_7_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fu_code_9; // @[lsu.scala:252:32] wire s_uop_10_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_8_fu_code_9 = stq_uop_7_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued; // @[lsu.scala:252:32] wire s_uop_10_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued = stq_uop_7_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_agen = stq_uop_7_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_10_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_issued_partial_dgen = stq_uop_7_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_10_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_iw_p1_speculative_child = stq_uop_7_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_10_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_iw_p2_speculative_child = stq_uop_7_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p1_bypass_hint = stq_uop_7_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p2_bypass_hint = stq_uop_7_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_10_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_8_iw_p3_bypass_hint = stq_uop_7_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_dis_col_sel = stq_uop_7_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_7_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_10_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_8_br_mask = stq_uop_7_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_tag = stq_uop_7_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_7_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_10_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_8_br_type = stq_uop_7_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfb; // @[lsu.scala:252:32] wire s_uop_10_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfb = stq_uop_7_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fence; // @[lsu.scala:252:32] wire s_uop_10_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fence = stq_uop_7_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_fencei; // @[lsu.scala:252:32] wire s_uop_10_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_fencei = stq_uop_7_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sfence; // @[lsu.scala:252:32] wire s_uop_10_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sfence = stq_uop_7_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_amo; // @[lsu.scala:252:32] wire s_uop_10_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_amo = stq_uop_7_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_eret; // @[lsu.scala:252:32] wire s_uop_10_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_eret = stq_uop_7_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_10_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_sys_pc2epc = stq_uop_7_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_rocc; // @[lsu.scala:252:32] wire s_uop_10_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_rocc = stq_uop_7_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_mov; // @[lsu.scala:252:32] wire s_uop_10_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_mov = stq_uop_7_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ftq_idx = stq_uop_7_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_edge_inst; // @[lsu.scala:252:32] wire s_uop_10_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_8_edge_inst = stq_uop_7_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_10_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_pc_lob = stq_uop_7_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_taken; // @[lsu.scala:252:32] wire s_uop_10_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1324:37] wire uop_8_taken = stq_uop_7_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_imm_rename; // @[lsu.scala:252:32] wire s_uop_10_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_8_imm_rename = stq_uop_7_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_imm_sel = stq_uop_7_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_10_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_pimm = stq_uop_7_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_7_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_10_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_8_imm_packed = stq_uop_7_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_10_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_op1_sel = stq_uop_7_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_10_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_op2_sel = stq_uop_7_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ldst = stq_uop_7_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wen = stq_uop_7_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren1 = stq_uop_7_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren2 = stq_uop_7_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_ren3 = stq_uop_7_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap12 = stq_uop_7_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_swap23 = stq_uop_7_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagIn = stq_uop_7_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_ctrl_typeTagOut = stq_uop_7_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fromint = stq_uop_7_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_toint = stq_uop_7_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fastpipe = stq_uop_7_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_fma = stq_uop_7_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_div = stq_uop_7_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_sqrt = stq_uop_7_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_wflags = stq_uop_7_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_10_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_ctrl_vec = stq_uop_7_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_10_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_rob_idx = stq_uop_7_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ldq_idx = stq_uop_7_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_10_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_stq_idx = stq_uop_7_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_10_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_rxq_idx = stq_uop_7_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_pdst = stq_uop_7_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs1 = stq_uop_7_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs2 = stq_uop_7_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_10_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_prs3 = stq_uop_7_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_10_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_ppred = stq_uop_7_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs1_busy; // @[lsu.scala:252:32] wire s_uop_10_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs1_busy = stq_uop_7_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs2_busy; // @[lsu.scala:252:32] wire s_uop_10_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs2_busy = stq_uop_7_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_prs3_busy; // @[lsu.scala:252:32] wire s_uop_10_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_prs3_busy = stq_uop_7_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ppred_busy; // @[lsu.scala:252:32] wire s_uop_10_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_8_ppred_busy = stq_uop_7_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_7_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_10_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_8_stale_pdst = stq_uop_7_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_exception; // @[lsu.scala:252:32] wire s_uop_10_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1324:37] wire uop_8_exception = stq_uop_7_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_7_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_10_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_8_exc_cause = stq_uop_7_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_10_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_mem_cmd = stq_uop_7_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_10_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_mem_size = stq_uop_7_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_mem_signed; // @[lsu.scala:252:32] wire s_uop_10_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_8_mem_signed = stq_uop_7_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_ldq; // @[lsu.scala:252:32] wire s_uop_10_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_ldq = stq_uop_7_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_uses_stq; // @[lsu.scala:252:32] wire s_uop_10_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_8_uses_stq = stq_uop_7_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_is_unique; // @[lsu.scala:252:32] wire s_uop_10_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_8_is_unique = stq_uop_7_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_10_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_8_flush_on_commit = stq_uop_7_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_10_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_csr_cmd = stq_uop_7_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_10_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_8_ldst_is_rs1 = stq_uop_7_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_10_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_ldst = stq_uop_7_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs1 = stq_uop_7_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs2 = stq_uop_7_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_7_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_10_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_8_lrs3 = stq_uop_7_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_dst_rtype = stq_uop_7_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs1_rtype = stq_uop_7_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_10_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_lrs2_rtype = stq_uop_7_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_frs3_en; // @[lsu.scala:252:32] wire s_uop_10_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_8_frs3_en = stq_uop_7_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fcn_dw; // @[lsu.scala:252:32] wire s_uop_10_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_8_fcn_dw = stq_uop_7_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_7_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_10_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_8_fcn_op = stq_uop_7_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_fp_val; // @[lsu.scala:252:32] wire s_uop_10_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_8_fp_val = stq_uop_7_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_10_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_fp_rm = stq_uop_7_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_7_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_10_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_8_fp_typ = stq_uop_7_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_pf_if = stq_uop_7_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ae_if = stq_uop_7_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_10_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_xcpt_ma_if = stq_uop_7_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_10_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_debug_if = stq_uop_7_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_10_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_8_bp_xcpt_if = stq_uop_7_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_fsrc = stq_uop_7_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_7_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_10_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_8_debug_tsrc = stq_uop_7_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_inst = stq_uop_8_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_8_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_11_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_9_debug_inst = stq_uop_8_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rvc; // @[lsu.scala:252:32] wire s_uop_11_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rvc = stq_uop_8_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_8_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_11_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_9_debug_pc = stq_uop_8_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_0; // @[lsu.scala:252:32] wire s_uop_11_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_0 = stq_uop_8_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_1; // @[lsu.scala:252:32] wire s_uop_11_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_1 = stq_uop_8_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_2; // @[lsu.scala:252:32] wire s_uop_11_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_2 = stq_uop_8_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iq_type_3; // @[lsu.scala:252:32] wire s_uop_11_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_iq_type_3 = stq_uop_8_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_0; // @[lsu.scala:252:32] wire s_uop_11_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_0 = stq_uop_8_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_1; // @[lsu.scala:252:32] wire s_uop_11_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_1 = stq_uop_8_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_2; // @[lsu.scala:252:32] wire s_uop_11_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_2 = stq_uop_8_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_3; // @[lsu.scala:252:32] wire s_uop_11_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_3 = stq_uop_8_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_4; // @[lsu.scala:252:32] wire s_uop_11_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_4 = stq_uop_8_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_5; // @[lsu.scala:252:32] wire s_uop_11_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_5 = stq_uop_8_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_6; // @[lsu.scala:252:32] wire s_uop_11_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_6 = stq_uop_8_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_7; // @[lsu.scala:252:32] wire s_uop_11_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_7 = stq_uop_8_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_8; // @[lsu.scala:252:32] wire s_uop_11_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_8 = stq_uop_8_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fu_code_9; // @[lsu.scala:252:32] wire s_uop_11_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_9_fu_code_9 = stq_uop_8_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued; // @[lsu.scala:252:32] wire s_uop_11_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued = stq_uop_8_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_agen = stq_uop_8_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_11_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_issued_partial_dgen = stq_uop_8_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_11_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_iw_p1_speculative_child = stq_uop_8_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_11_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_iw_p2_speculative_child = stq_uop_8_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p1_bypass_hint = stq_uop_8_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p2_bypass_hint = stq_uop_8_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_11_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_9_iw_p3_bypass_hint = stq_uop_8_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_dis_col_sel = stq_uop_8_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_8_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_11_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_9_br_mask = stq_uop_8_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_tag = stq_uop_8_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_8_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_11_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_9_br_type = stq_uop_8_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfb; // @[lsu.scala:252:32] wire s_uop_11_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfb = stq_uop_8_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fence; // @[lsu.scala:252:32] wire s_uop_11_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fence = stq_uop_8_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_fencei; // @[lsu.scala:252:32] wire s_uop_11_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_fencei = stq_uop_8_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sfence; // @[lsu.scala:252:32] wire s_uop_11_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sfence = stq_uop_8_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_amo; // @[lsu.scala:252:32] wire s_uop_11_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_amo = stq_uop_8_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_eret; // @[lsu.scala:252:32] wire s_uop_11_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_eret = stq_uop_8_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_11_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_sys_pc2epc = stq_uop_8_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_rocc; // @[lsu.scala:252:32] wire s_uop_11_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_rocc = stq_uop_8_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_mov; // @[lsu.scala:252:32] wire s_uop_11_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_mov = stq_uop_8_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ftq_idx = stq_uop_8_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_edge_inst; // @[lsu.scala:252:32] wire s_uop_11_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_9_edge_inst = stq_uop_8_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_11_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_pc_lob = stq_uop_8_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_taken; // @[lsu.scala:252:32] wire s_uop_11_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1324:37] wire uop_9_taken = stq_uop_8_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_imm_rename; // @[lsu.scala:252:32] wire s_uop_11_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_9_imm_rename = stq_uop_8_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_imm_sel = stq_uop_8_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_11_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_pimm = stq_uop_8_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_8_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_11_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_9_imm_packed = stq_uop_8_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_11_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_op1_sel = stq_uop_8_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_11_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_op2_sel = stq_uop_8_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ldst = stq_uop_8_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wen = stq_uop_8_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren1 = stq_uop_8_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren2 = stq_uop_8_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_ren3 = stq_uop_8_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap12 = stq_uop_8_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_swap23 = stq_uop_8_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagIn = stq_uop_8_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_ctrl_typeTagOut = stq_uop_8_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fromint = stq_uop_8_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_toint = stq_uop_8_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fastpipe = stq_uop_8_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_fma = stq_uop_8_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_div = stq_uop_8_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_sqrt = stq_uop_8_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_wflags = stq_uop_8_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_11_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_ctrl_vec = stq_uop_8_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_11_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_rob_idx = stq_uop_8_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ldq_idx = stq_uop_8_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_11_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_stq_idx = stq_uop_8_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_11_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_rxq_idx = stq_uop_8_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_pdst = stq_uop_8_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs1 = stq_uop_8_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs2 = stq_uop_8_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_11_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_prs3 = stq_uop_8_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_11_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_ppred = stq_uop_8_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs1_busy; // @[lsu.scala:252:32] wire s_uop_11_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs1_busy = stq_uop_8_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs2_busy; // @[lsu.scala:252:32] wire s_uop_11_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs2_busy = stq_uop_8_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_prs3_busy; // @[lsu.scala:252:32] wire s_uop_11_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_prs3_busy = stq_uop_8_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ppred_busy; // @[lsu.scala:252:32] wire s_uop_11_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_9_ppred_busy = stq_uop_8_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_8_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_11_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_9_stale_pdst = stq_uop_8_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_exception; // @[lsu.scala:252:32] wire s_uop_11_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1324:37] wire uop_9_exception = stq_uop_8_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_8_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_11_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_9_exc_cause = stq_uop_8_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_11_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_mem_cmd = stq_uop_8_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_11_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_mem_size = stq_uop_8_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_mem_signed; // @[lsu.scala:252:32] wire s_uop_11_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_9_mem_signed = stq_uop_8_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_ldq; // @[lsu.scala:252:32] wire s_uop_11_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_ldq = stq_uop_8_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_uses_stq; // @[lsu.scala:252:32] wire s_uop_11_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_9_uses_stq = stq_uop_8_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_is_unique; // @[lsu.scala:252:32] wire s_uop_11_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_9_is_unique = stq_uop_8_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_11_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_9_flush_on_commit = stq_uop_8_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_11_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_csr_cmd = stq_uop_8_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_11_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_9_ldst_is_rs1 = stq_uop_8_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_11_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_ldst = stq_uop_8_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs1 = stq_uop_8_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs2 = stq_uop_8_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_8_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_11_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_9_lrs3 = stq_uop_8_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_dst_rtype = stq_uop_8_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs1_rtype = stq_uop_8_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_11_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_lrs2_rtype = stq_uop_8_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_frs3_en; // @[lsu.scala:252:32] wire s_uop_11_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_9_frs3_en = stq_uop_8_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fcn_dw; // @[lsu.scala:252:32] wire s_uop_11_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_9_fcn_dw = stq_uop_8_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_8_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_11_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_9_fcn_op = stq_uop_8_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_fp_val; // @[lsu.scala:252:32] wire s_uop_11_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_9_fp_val = stq_uop_8_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_11_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_fp_rm = stq_uop_8_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_8_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_11_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_9_fp_typ = stq_uop_8_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_pf_if = stq_uop_8_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ae_if = stq_uop_8_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_11_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_xcpt_ma_if = stq_uop_8_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_11_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_debug_if = stq_uop_8_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_11_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_9_bp_xcpt_if = stq_uop_8_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_fsrc = stq_uop_8_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_8_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_11_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_9_debug_tsrc = stq_uop_8_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_inst = stq_uop_9_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_9_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_12_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_10_debug_inst = stq_uop_9_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rvc; // @[lsu.scala:252:32] wire s_uop_12_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rvc = stq_uop_9_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_9_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_12_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_10_debug_pc = stq_uop_9_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_0; // @[lsu.scala:252:32] wire s_uop_12_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_0 = stq_uop_9_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_1; // @[lsu.scala:252:32] wire s_uop_12_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_1 = stq_uop_9_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_2; // @[lsu.scala:252:32] wire s_uop_12_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_2 = stq_uop_9_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iq_type_3; // @[lsu.scala:252:32] wire s_uop_12_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_iq_type_3 = stq_uop_9_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_0; // @[lsu.scala:252:32] wire s_uop_12_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_0 = stq_uop_9_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_1; // @[lsu.scala:252:32] wire s_uop_12_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_1 = stq_uop_9_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_2; // @[lsu.scala:252:32] wire s_uop_12_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_2 = stq_uop_9_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_3; // @[lsu.scala:252:32] wire s_uop_12_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_3 = stq_uop_9_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_4; // @[lsu.scala:252:32] wire s_uop_12_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_4 = stq_uop_9_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_5; // @[lsu.scala:252:32] wire s_uop_12_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_5 = stq_uop_9_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_6; // @[lsu.scala:252:32] wire s_uop_12_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_6 = stq_uop_9_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_7; // @[lsu.scala:252:32] wire s_uop_12_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_7 = stq_uop_9_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_8; // @[lsu.scala:252:32] wire s_uop_12_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_8 = stq_uop_9_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fu_code_9; // @[lsu.scala:252:32] wire s_uop_12_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_10_fu_code_9 = stq_uop_9_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued; // @[lsu.scala:252:32] wire s_uop_12_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued = stq_uop_9_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_agen = stq_uop_9_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_12_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_issued_partial_dgen = stq_uop_9_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_12_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_iw_p1_speculative_child = stq_uop_9_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_12_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_iw_p2_speculative_child = stq_uop_9_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p1_bypass_hint = stq_uop_9_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p2_bypass_hint = stq_uop_9_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_12_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_10_iw_p3_bypass_hint = stq_uop_9_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_dis_col_sel = stq_uop_9_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_9_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_12_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_10_br_mask = stq_uop_9_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_tag = stq_uop_9_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_9_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_12_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_10_br_type = stq_uop_9_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfb; // @[lsu.scala:252:32] wire s_uop_12_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfb = stq_uop_9_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fence; // @[lsu.scala:252:32] wire s_uop_12_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fence = stq_uop_9_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_fencei; // @[lsu.scala:252:32] wire s_uop_12_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_fencei = stq_uop_9_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sfence; // @[lsu.scala:252:32] wire s_uop_12_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sfence = stq_uop_9_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_amo; // @[lsu.scala:252:32] wire s_uop_12_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_amo = stq_uop_9_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_eret; // @[lsu.scala:252:32] wire s_uop_12_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_eret = stq_uop_9_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_12_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_sys_pc2epc = stq_uop_9_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_rocc; // @[lsu.scala:252:32] wire s_uop_12_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_rocc = stq_uop_9_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_mov; // @[lsu.scala:252:32] wire s_uop_12_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_mov = stq_uop_9_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ftq_idx = stq_uop_9_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_edge_inst; // @[lsu.scala:252:32] wire s_uop_12_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_10_edge_inst = stq_uop_9_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_12_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_pc_lob = stq_uop_9_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_taken; // @[lsu.scala:252:32] wire s_uop_12_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1324:37] wire uop_10_taken = stq_uop_9_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_imm_rename; // @[lsu.scala:252:32] wire s_uop_12_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_10_imm_rename = stq_uop_9_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_imm_sel = stq_uop_9_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_12_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_pimm = stq_uop_9_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_9_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_12_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_10_imm_packed = stq_uop_9_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_12_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_op1_sel = stq_uop_9_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_12_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_op2_sel = stq_uop_9_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ldst = stq_uop_9_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wen = stq_uop_9_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren1 = stq_uop_9_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren2 = stq_uop_9_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_ren3 = stq_uop_9_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap12 = stq_uop_9_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_swap23 = stq_uop_9_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagIn = stq_uop_9_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_ctrl_typeTagOut = stq_uop_9_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fromint = stq_uop_9_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_toint = stq_uop_9_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fastpipe = stq_uop_9_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_fma = stq_uop_9_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_div = stq_uop_9_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_sqrt = stq_uop_9_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_wflags = stq_uop_9_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_12_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_ctrl_vec = stq_uop_9_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_12_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_rob_idx = stq_uop_9_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ldq_idx = stq_uop_9_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_12_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_stq_idx = stq_uop_9_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_12_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_rxq_idx = stq_uop_9_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_pdst = stq_uop_9_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs1 = stq_uop_9_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs2 = stq_uop_9_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_12_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_prs3 = stq_uop_9_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_12_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_ppred = stq_uop_9_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs1_busy; // @[lsu.scala:252:32] wire s_uop_12_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs1_busy = stq_uop_9_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs2_busy; // @[lsu.scala:252:32] wire s_uop_12_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs2_busy = stq_uop_9_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_prs3_busy; // @[lsu.scala:252:32] wire s_uop_12_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_prs3_busy = stq_uop_9_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ppred_busy; // @[lsu.scala:252:32] wire s_uop_12_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_10_ppred_busy = stq_uop_9_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_9_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_12_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_10_stale_pdst = stq_uop_9_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_exception; // @[lsu.scala:252:32] wire s_uop_12_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1324:37] wire uop_10_exception = stq_uop_9_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_9_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_12_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_10_exc_cause = stq_uop_9_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_12_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_mem_cmd = stq_uop_9_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_12_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_mem_size = stq_uop_9_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_mem_signed; // @[lsu.scala:252:32] wire s_uop_12_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_10_mem_signed = stq_uop_9_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_ldq; // @[lsu.scala:252:32] wire s_uop_12_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_ldq = stq_uop_9_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_uses_stq; // @[lsu.scala:252:32] wire s_uop_12_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_10_uses_stq = stq_uop_9_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_is_unique; // @[lsu.scala:252:32] wire s_uop_12_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_10_is_unique = stq_uop_9_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_12_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_10_flush_on_commit = stq_uop_9_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_12_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_csr_cmd = stq_uop_9_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_12_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_10_ldst_is_rs1 = stq_uop_9_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_12_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_ldst = stq_uop_9_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs1 = stq_uop_9_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs2 = stq_uop_9_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_9_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_12_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_10_lrs3 = stq_uop_9_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_dst_rtype = stq_uop_9_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs1_rtype = stq_uop_9_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_12_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_lrs2_rtype = stq_uop_9_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_frs3_en; // @[lsu.scala:252:32] wire s_uop_12_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_10_frs3_en = stq_uop_9_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fcn_dw; // @[lsu.scala:252:32] wire s_uop_12_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_10_fcn_dw = stq_uop_9_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_9_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_12_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_10_fcn_op = stq_uop_9_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_fp_val; // @[lsu.scala:252:32] wire s_uop_12_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_10_fp_val = stq_uop_9_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_12_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_fp_rm = stq_uop_9_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_9_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_12_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_10_fp_typ = stq_uop_9_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_pf_if = stq_uop_9_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ae_if = stq_uop_9_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_12_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_xcpt_ma_if = stq_uop_9_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_12_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_debug_if = stq_uop_9_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_12_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_10_bp_xcpt_if = stq_uop_9_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_fsrc = stq_uop_9_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_9_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_12_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_10_debug_tsrc = stq_uop_9_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_inst = stq_uop_10_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_10_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_13_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_11_debug_inst = stq_uop_10_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rvc; // @[lsu.scala:252:32] wire s_uop_13_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rvc = stq_uop_10_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_10_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_13_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_11_debug_pc = stq_uop_10_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_0; // @[lsu.scala:252:32] wire s_uop_13_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_0 = stq_uop_10_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_1; // @[lsu.scala:252:32] wire s_uop_13_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_1 = stq_uop_10_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_2; // @[lsu.scala:252:32] wire s_uop_13_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_2 = stq_uop_10_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iq_type_3; // @[lsu.scala:252:32] wire s_uop_13_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_iq_type_3 = stq_uop_10_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_0; // @[lsu.scala:252:32] wire s_uop_13_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_0 = stq_uop_10_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_1; // @[lsu.scala:252:32] wire s_uop_13_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_1 = stq_uop_10_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_2; // @[lsu.scala:252:32] wire s_uop_13_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_2 = stq_uop_10_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_3; // @[lsu.scala:252:32] wire s_uop_13_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_3 = stq_uop_10_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_4; // @[lsu.scala:252:32] wire s_uop_13_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_4 = stq_uop_10_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_5; // @[lsu.scala:252:32] wire s_uop_13_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_5 = stq_uop_10_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_6; // @[lsu.scala:252:32] wire s_uop_13_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_6 = stq_uop_10_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_7; // @[lsu.scala:252:32] wire s_uop_13_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_7 = stq_uop_10_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_8; // @[lsu.scala:252:32] wire s_uop_13_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_8 = stq_uop_10_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fu_code_9; // @[lsu.scala:252:32] wire s_uop_13_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_11_fu_code_9 = stq_uop_10_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued; // @[lsu.scala:252:32] wire s_uop_13_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued = stq_uop_10_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_agen = stq_uop_10_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_13_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_issued_partial_dgen = stq_uop_10_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_13_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_iw_p1_speculative_child = stq_uop_10_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_13_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_iw_p2_speculative_child = stq_uop_10_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p1_bypass_hint = stq_uop_10_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p2_bypass_hint = stq_uop_10_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_13_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_11_iw_p3_bypass_hint = stq_uop_10_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_dis_col_sel = stq_uop_10_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_10_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_13_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_11_br_mask = stq_uop_10_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_tag = stq_uop_10_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_10_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_13_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_11_br_type = stq_uop_10_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfb; // @[lsu.scala:252:32] wire s_uop_13_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfb = stq_uop_10_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fence; // @[lsu.scala:252:32] wire s_uop_13_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fence = stq_uop_10_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_fencei; // @[lsu.scala:252:32] wire s_uop_13_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_fencei = stq_uop_10_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sfence; // @[lsu.scala:252:32] wire s_uop_13_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sfence = stq_uop_10_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_amo; // @[lsu.scala:252:32] wire s_uop_13_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_amo = stq_uop_10_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_eret; // @[lsu.scala:252:32] wire s_uop_13_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_eret = stq_uop_10_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_13_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_sys_pc2epc = stq_uop_10_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_rocc; // @[lsu.scala:252:32] wire s_uop_13_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_rocc = stq_uop_10_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_mov; // @[lsu.scala:252:32] wire s_uop_13_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_mov = stq_uop_10_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ftq_idx = stq_uop_10_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_edge_inst; // @[lsu.scala:252:32] wire s_uop_13_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_11_edge_inst = stq_uop_10_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_13_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_pc_lob = stq_uop_10_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_taken; // @[lsu.scala:252:32] wire s_uop_13_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1324:37] wire uop_11_taken = stq_uop_10_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_imm_rename; // @[lsu.scala:252:32] wire s_uop_13_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_11_imm_rename = stq_uop_10_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_imm_sel = stq_uop_10_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_13_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_pimm = stq_uop_10_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_10_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_13_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_11_imm_packed = stq_uop_10_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_13_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_op1_sel = stq_uop_10_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_13_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_op2_sel = stq_uop_10_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ldst = stq_uop_10_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wen = stq_uop_10_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren1 = stq_uop_10_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren2 = stq_uop_10_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_ren3 = stq_uop_10_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap12 = stq_uop_10_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_swap23 = stq_uop_10_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagIn = stq_uop_10_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_ctrl_typeTagOut = stq_uop_10_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fromint = stq_uop_10_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_toint = stq_uop_10_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fastpipe = stq_uop_10_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_fma = stq_uop_10_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_div = stq_uop_10_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_sqrt = stq_uop_10_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_wflags = stq_uop_10_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_13_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_ctrl_vec = stq_uop_10_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_13_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_rob_idx = stq_uop_10_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ldq_idx = stq_uop_10_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_13_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_stq_idx = stq_uop_10_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_13_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_rxq_idx = stq_uop_10_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_pdst = stq_uop_10_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs1 = stq_uop_10_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs2 = stq_uop_10_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_13_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_prs3 = stq_uop_10_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_13_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_ppred = stq_uop_10_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs1_busy; // @[lsu.scala:252:32] wire s_uop_13_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs1_busy = stq_uop_10_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs2_busy; // @[lsu.scala:252:32] wire s_uop_13_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs2_busy = stq_uop_10_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_prs3_busy; // @[lsu.scala:252:32] wire s_uop_13_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_prs3_busy = stq_uop_10_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ppred_busy; // @[lsu.scala:252:32] wire s_uop_13_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_11_ppred_busy = stq_uop_10_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_10_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_13_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_11_stale_pdst = stq_uop_10_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_exception; // @[lsu.scala:252:32] wire s_uop_13_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1324:37] wire uop_11_exception = stq_uop_10_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_10_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_13_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_11_exc_cause = stq_uop_10_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_13_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_mem_cmd = stq_uop_10_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_13_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_mem_size = stq_uop_10_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_mem_signed; // @[lsu.scala:252:32] wire s_uop_13_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_11_mem_signed = stq_uop_10_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_ldq; // @[lsu.scala:252:32] wire s_uop_13_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_ldq = stq_uop_10_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_uses_stq; // @[lsu.scala:252:32] wire s_uop_13_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_11_uses_stq = stq_uop_10_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_is_unique; // @[lsu.scala:252:32] wire s_uop_13_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_11_is_unique = stq_uop_10_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_13_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_11_flush_on_commit = stq_uop_10_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_13_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_csr_cmd = stq_uop_10_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_13_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_11_ldst_is_rs1 = stq_uop_10_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_13_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_ldst = stq_uop_10_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs1 = stq_uop_10_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs2 = stq_uop_10_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_10_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_13_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_11_lrs3 = stq_uop_10_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_dst_rtype = stq_uop_10_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs1_rtype = stq_uop_10_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_13_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_lrs2_rtype = stq_uop_10_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_frs3_en; // @[lsu.scala:252:32] wire s_uop_13_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_11_frs3_en = stq_uop_10_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fcn_dw; // @[lsu.scala:252:32] wire s_uop_13_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_11_fcn_dw = stq_uop_10_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_10_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_13_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_11_fcn_op = stq_uop_10_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_fp_val; // @[lsu.scala:252:32] wire s_uop_13_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_11_fp_val = stq_uop_10_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_13_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_fp_rm = stq_uop_10_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_10_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_13_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_11_fp_typ = stq_uop_10_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_pf_if = stq_uop_10_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ae_if = stq_uop_10_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_13_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_xcpt_ma_if = stq_uop_10_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_13_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_debug_if = stq_uop_10_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_13_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_11_bp_xcpt_if = stq_uop_10_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_fsrc = stq_uop_10_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_10_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_13_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_11_debug_tsrc = stq_uop_10_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_inst = stq_uop_11_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_11_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_14_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_12_debug_inst = stq_uop_11_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rvc; // @[lsu.scala:252:32] wire s_uop_14_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rvc = stq_uop_11_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_11_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_14_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_12_debug_pc = stq_uop_11_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_0; // @[lsu.scala:252:32] wire s_uop_14_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_0 = stq_uop_11_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_1; // @[lsu.scala:252:32] wire s_uop_14_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_1 = stq_uop_11_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_2; // @[lsu.scala:252:32] wire s_uop_14_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_2 = stq_uop_11_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iq_type_3; // @[lsu.scala:252:32] wire s_uop_14_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_iq_type_3 = stq_uop_11_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_0; // @[lsu.scala:252:32] wire s_uop_14_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_0 = stq_uop_11_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_1; // @[lsu.scala:252:32] wire s_uop_14_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_1 = stq_uop_11_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_2; // @[lsu.scala:252:32] wire s_uop_14_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_2 = stq_uop_11_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_3; // @[lsu.scala:252:32] wire s_uop_14_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_3 = stq_uop_11_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_4; // @[lsu.scala:252:32] wire s_uop_14_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_4 = stq_uop_11_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_5; // @[lsu.scala:252:32] wire s_uop_14_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_5 = stq_uop_11_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_6; // @[lsu.scala:252:32] wire s_uop_14_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_6 = stq_uop_11_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_7; // @[lsu.scala:252:32] wire s_uop_14_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_7 = stq_uop_11_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_8; // @[lsu.scala:252:32] wire s_uop_14_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_8 = stq_uop_11_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fu_code_9; // @[lsu.scala:252:32] wire s_uop_14_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_12_fu_code_9 = stq_uop_11_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued; // @[lsu.scala:252:32] wire s_uop_14_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued = stq_uop_11_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_agen = stq_uop_11_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_14_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_issued_partial_dgen = stq_uop_11_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_14_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_iw_p1_speculative_child = stq_uop_11_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_14_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_iw_p2_speculative_child = stq_uop_11_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p1_bypass_hint = stq_uop_11_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p2_bypass_hint = stq_uop_11_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_14_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_12_iw_p3_bypass_hint = stq_uop_11_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_dis_col_sel = stq_uop_11_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_11_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_14_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_12_br_mask = stq_uop_11_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_tag = stq_uop_11_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_11_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_14_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_12_br_type = stq_uop_11_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfb; // @[lsu.scala:252:32] wire s_uop_14_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfb = stq_uop_11_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fence; // @[lsu.scala:252:32] wire s_uop_14_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fence = stq_uop_11_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_fencei; // @[lsu.scala:252:32] wire s_uop_14_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_fencei = stq_uop_11_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sfence; // @[lsu.scala:252:32] wire s_uop_14_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sfence = stq_uop_11_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_amo; // @[lsu.scala:252:32] wire s_uop_14_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_amo = stq_uop_11_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_eret; // @[lsu.scala:252:32] wire s_uop_14_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_eret = stq_uop_11_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_14_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_sys_pc2epc = stq_uop_11_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_rocc; // @[lsu.scala:252:32] wire s_uop_14_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_rocc = stq_uop_11_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_mov; // @[lsu.scala:252:32] wire s_uop_14_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_mov = stq_uop_11_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ftq_idx = stq_uop_11_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_edge_inst; // @[lsu.scala:252:32] wire s_uop_14_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_12_edge_inst = stq_uop_11_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_14_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_pc_lob = stq_uop_11_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_taken; // @[lsu.scala:252:32] wire s_uop_14_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1324:37] wire uop_12_taken = stq_uop_11_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_imm_rename; // @[lsu.scala:252:32] wire s_uop_14_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_12_imm_rename = stq_uop_11_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_imm_sel = stq_uop_11_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_14_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_pimm = stq_uop_11_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_11_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_14_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_12_imm_packed = stq_uop_11_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_14_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_op1_sel = stq_uop_11_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_14_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_op2_sel = stq_uop_11_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ldst = stq_uop_11_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wen = stq_uop_11_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren1 = stq_uop_11_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren2 = stq_uop_11_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_ren3 = stq_uop_11_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap12 = stq_uop_11_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_swap23 = stq_uop_11_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagIn = stq_uop_11_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_ctrl_typeTagOut = stq_uop_11_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fromint = stq_uop_11_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_toint = stq_uop_11_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fastpipe = stq_uop_11_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_fma = stq_uop_11_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_div = stq_uop_11_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_sqrt = stq_uop_11_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_wflags = stq_uop_11_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_14_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_ctrl_vec = stq_uop_11_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_14_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_rob_idx = stq_uop_11_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ldq_idx = stq_uop_11_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_14_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_stq_idx = stq_uop_11_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_14_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_rxq_idx = stq_uop_11_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_pdst = stq_uop_11_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs1 = stq_uop_11_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs2 = stq_uop_11_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_14_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_prs3 = stq_uop_11_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_14_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_ppred = stq_uop_11_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs1_busy; // @[lsu.scala:252:32] wire s_uop_14_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs1_busy = stq_uop_11_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs2_busy; // @[lsu.scala:252:32] wire s_uop_14_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs2_busy = stq_uop_11_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_prs3_busy; // @[lsu.scala:252:32] wire s_uop_14_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_prs3_busy = stq_uop_11_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ppred_busy; // @[lsu.scala:252:32] wire s_uop_14_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_12_ppred_busy = stq_uop_11_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_11_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_14_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_12_stale_pdst = stq_uop_11_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_exception; // @[lsu.scala:252:32] wire s_uop_14_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1324:37] wire uop_12_exception = stq_uop_11_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_11_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_14_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_12_exc_cause = stq_uop_11_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_14_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_mem_cmd = stq_uop_11_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_14_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_mem_size = stq_uop_11_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_mem_signed; // @[lsu.scala:252:32] wire s_uop_14_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_12_mem_signed = stq_uop_11_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_ldq; // @[lsu.scala:252:32] wire s_uop_14_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_ldq = stq_uop_11_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_uses_stq; // @[lsu.scala:252:32] wire s_uop_14_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_12_uses_stq = stq_uop_11_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_is_unique; // @[lsu.scala:252:32] wire s_uop_14_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_12_is_unique = stq_uop_11_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_14_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_12_flush_on_commit = stq_uop_11_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_14_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_csr_cmd = stq_uop_11_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_14_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_12_ldst_is_rs1 = stq_uop_11_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_14_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_ldst = stq_uop_11_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs1 = stq_uop_11_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs2 = stq_uop_11_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_11_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_14_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_12_lrs3 = stq_uop_11_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_dst_rtype = stq_uop_11_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs1_rtype = stq_uop_11_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_14_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_lrs2_rtype = stq_uop_11_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_frs3_en; // @[lsu.scala:252:32] wire s_uop_14_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_12_frs3_en = stq_uop_11_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fcn_dw; // @[lsu.scala:252:32] wire s_uop_14_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_12_fcn_dw = stq_uop_11_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_11_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_14_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_12_fcn_op = stq_uop_11_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_fp_val; // @[lsu.scala:252:32] wire s_uop_14_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_12_fp_val = stq_uop_11_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_14_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_fp_rm = stq_uop_11_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_11_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_14_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_12_fp_typ = stq_uop_11_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_pf_if = stq_uop_11_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ae_if = stq_uop_11_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_14_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_xcpt_ma_if = stq_uop_11_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_14_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_debug_if = stq_uop_11_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_14_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_12_bp_xcpt_if = stq_uop_11_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_fsrc = stq_uop_11_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_11_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_14_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_12_debug_tsrc = stq_uop_11_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_inst = stq_uop_12_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_12_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_15_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_13_debug_inst = stq_uop_12_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rvc; // @[lsu.scala:252:32] wire s_uop_15_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rvc = stq_uop_12_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_12_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_15_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_13_debug_pc = stq_uop_12_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_0; // @[lsu.scala:252:32] wire s_uop_15_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_0 = stq_uop_12_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_1; // @[lsu.scala:252:32] wire s_uop_15_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_1 = stq_uop_12_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_2; // @[lsu.scala:252:32] wire s_uop_15_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_2 = stq_uop_12_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iq_type_3; // @[lsu.scala:252:32] wire s_uop_15_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_iq_type_3 = stq_uop_12_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_0; // @[lsu.scala:252:32] wire s_uop_15_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_0 = stq_uop_12_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_1; // @[lsu.scala:252:32] wire s_uop_15_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_1 = stq_uop_12_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_2; // @[lsu.scala:252:32] wire s_uop_15_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_2 = stq_uop_12_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_3; // @[lsu.scala:252:32] wire s_uop_15_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_3 = stq_uop_12_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_4; // @[lsu.scala:252:32] wire s_uop_15_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_4 = stq_uop_12_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_5; // @[lsu.scala:252:32] wire s_uop_15_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_5 = stq_uop_12_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_6; // @[lsu.scala:252:32] wire s_uop_15_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_6 = stq_uop_12_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_7; // @[lsu.scala:252:32] wire s_uop_15_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_7 = stq_uop_12_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_8; // @[lsu.scala:252:32] wire s_uop_15_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_8 = stq_uop_12_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fu_code_9; // @[lsu.scala:252:32] wire s_uop_15_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_13_fu_code_9 = stq_uop_12_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued; // @[lsu.scala:252:32] wire s_uop_15_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued = stq_uop_12_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_agen = stq_uop_12_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_15_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_issued_partial_dgen = stq_uop_12_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_15_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_iw_p1_speculative_child = stq_uop_12_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_15_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_iw_p2_speculative_child = stq_uop_12_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p1_bypass_hint = stq_uop_12_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p2_bypass_hint = stq_uop_12_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_15_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_13_iw_p3_bypass_hint = stq_uop_12_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_dis_col_sel = stq_uop_12_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_12_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_15_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_13_br_mask = stq_uop_12_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_tag = stq_uop_12_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_12_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_15_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_13_br_type = stq_uop_12_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfb; // @[lsu.scala:252:32] wire s_uop_15_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfb = stq_uop_12_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fence; // @[lsu.scala:252:32] wire s_uop_15_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fence = stq_uop_12_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_fencei; // @[lsu.scala:252:32] wire s_uop_15_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_fencei = stq_uop_12_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sfence; // @[lsu.scala:252:32] wire s_uop_15_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sfence = stq_uop_12_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_amo; // @[lsu.scala:252:32] wire s_uop_15_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_amo = stq_uop_12_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_eret; // @[lsu.scala:252:32] wire s_uop_15_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_eret = stq_uop_12_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_15_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_sys_pc2epc = stq_uop_12_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_rocc; // @[lsu.scala:252:32] wire s_uop_15_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_rocc = stq_uop_12_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_mov; // @[lsu.scala:252:32] wire s_uop_15_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_mov = stq_uop_12_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ftq_idx = stq_uop_12_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_edge_inst; // @[lsu.scala:252:32] wire s_uop_15_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_13_edge_inst = stq_uop_12_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_15_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_pc_lob = stq_uop_12_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_taken; // @[lsu.scala:252:32] wire s_uop_15_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1324:37] wire uop_13_taken = stq_uop_12_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_imm_rename; // @[lsu.scala:252:32] wire s_uop_15_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_13_imm_rename = stq_uop_12_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_imm_sel = stq_uop_12_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_15_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_pimm = stq_uop_12_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_12_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_15_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_13_imm_packed = stq_uop_12_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_15_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_op1_sel = stq_uop_12_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_15_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_op2_sel = stq_uop_12_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ldst = stq_uop_12_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wen = stq_uop_12_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren1 = stq_uop_12_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren2 = stq_uop_12_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_ren3 = stq_uop_12_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap12 = stq_uop_12_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_swap23 = stq_uop_12_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagIn = stq_uop_12_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_ctrl_typeTagOut = stq_uop_12_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fromint = stq_uop_12_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_toint = stq_uop_12_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fastpipe = stq_uop_12_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_fma = stq_uop_12_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_div = stq_uop_12_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_sqrt = stq_uop_12_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_wflags = stq_uop_12_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_15_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_ctrl_vec = stq_uop_12_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_15_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_rob_idx = stq_uop_12_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ldq_idx = stq_uop_12_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_15_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_stq_idx = stq_uop_12_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_15_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_rxq_idx = stq_uop_12_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_pdst = stq_uop_12_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs1 = stq_uop_12_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs2 = stq_uop_12_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_15_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_prs3 = stq_uop_12_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_15_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_ppred = stq_uop_12_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs1_busy; // @[lsu.scala:252:32] wire s_uop_15_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs1_busy = stq_uop_12_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs2_busy; // @[lsu.scala:252:32] wire s_uop_15_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs2_busy = stq_uop_12_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_prs3_busy; // @[lsu.scala:252:32] wire s_uop_15_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_prs3_busy = stq_uop_12_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ppred_busy; // @[lsu.scala:252:32] wire s_uop_15_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_13_ppred_busy = stq_uop_12_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_12_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_15_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_13_stale_pdst = stq_uop_12_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_exception; // @[lsu.scala:252:32] wire s_uop_15_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1324:37] wire uop_13_exception = stq_uop_12_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_12_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_15_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_13_exc_cause = stq_uop_12_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_15_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_mem_cmd = stq_uop_12_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_15_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_mem_size = stq_uop_12_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_mem_signed; // @[lsu.scala:252:32] wire s_uop_15_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_13_mem_signed = stq_uop_12_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_ldq; // @[lsu.scala:252:32] wire s_uop_15_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_ldq = stq_uop_12_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_uses_stq; // @[lsu.scala:252:32] wire s_uop_15_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_13_uses_stq = stq_uop_12_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_is_unique; // @[lsu.scala:252:32] wire s_uop_15_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_13_is_unique = stq_uop_12_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_15_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_13_flush_on_commit = stq_uop_12_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_15_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_csr_cmd = stq_uop_12_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_15_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_13_ldst_is_rs1 = stq_uop_12_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_15_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_ldst = stq_uop_12_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs1 = stq_uop_12_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs2 = stq_uop_12_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_12_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_15_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_13_lrs3 = stq_uop_12_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_dst_rtype = stq_uop_12_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs1_rtype = stq_uop_12_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_15_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_lrs2_rtype = stq_uop_12_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_frs3_en; // @[lsu.scala:252:32] wire s_uop_15_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_13_frs3_en = stq_uop_12_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fcn_dw; // @[lsu.scala:252:32] wire s_uop_15_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_13_fcn_dw = stq_uop_12_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_12_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_15_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_13_fcn_op = stq_uop_12_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_fp_val; // @[lsu.scala:252:32] wire s_uop_15_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_13_fp_val = stq_uop_12_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_15_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_fp_rm = stq_uop_12_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_12_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_15_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_13_fp_typ = stq_uop_12_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_pf_if = stq_uop_12_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ae_if = stq_uop_12_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_15_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_xcpt_ma_if = stq_uop_12_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_15_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_debug_if = stq_uop_12_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_15_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_13_bp_xcpt_if = stq_uop_12_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_fsrc = stq_uop_12_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_12_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_15_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_13_debug_tsrc = stq_uop_12_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_inst = stq_uop_13_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_13_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_16_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_14_debug_inst = stq_uop_13_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rvc; // @[lsu.scala:252:32] wire s_uop_16_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rvc = stq_uop_13_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_13_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_16_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_14_debug_pc = stq_uop_13_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_0; // @[lsu.scala:252:32] wire s_uop_16_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_0 = stq_uop_13_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_1; // @[lsu.scala:252:32] wire s_uop_16_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_1 = stq_uop_13_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_2; // @[lsu.scala:252:32] wire s_uop_16_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_2 = stq_uop_13_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iq_type_3; // @[lsu.scala:252:32] wire s_uop_16_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_iq_type_3 = stq_uop_13_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_0; // @[lsu.scala:252:32] wire s_uop_16_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_0 = stq_uop_13_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_1; // @[lsu.scala:252:32] wire s_uop_16_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_1 = stq_uop_13_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_2; // @[lsu.scala:252:32] wire s_uop_16_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_2 = stq_uop_13_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_3; // @[lsu.scala:252:32] wire s_uop_16_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_3 = stq_uop_13_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_4; // @[lsu.scala:252:32] wire s_uop_16_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_4 = stq_uop_13_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_5; // @[lsu.scala:252:32] wire s_uop_16_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_5 = stq_uop_13_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_6; // @[lsu.scala:252:32] wire s_uop_16_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_6 = stq_uop_13_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_7; // @[lsu.scala:252:32] wire s_uop_16_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_7 = stq_uop_13_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_8; // @[lsu.scala:252:32] wire s_uop_16_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_8 = stq_uop_13_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fu_code_9; // @[lsu.scala:252:32] wire s_uop_16_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_14_fu_code_9 = stq_uop_13_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued; // @[lsu.scala:252:32] wire s_uop_16_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued = stq_uop_13_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_agen = stq_uop_13_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_16_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_issued_partial_dgen = stq_uop_13_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_16_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_iw_p1_speculative_child = stq_uop_13_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_16_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_iw_p2_speculative_child = stq_uop_13_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p1_bypass_hint = stq_uop_13_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p2_bypass_hint = stq_uop_13_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_16_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_14_iw_p3_bypass_hint = stq_uop_13_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_dis_col_sel = stq_uop_13_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_13_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_16_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_14_br_mask = stq_uop_13_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_tag = stq_uop_13_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_13_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_16_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_14_br_type = stq_uop_13_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfb; // @[lsu.scala:252:32] wire s_uop_16_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfb = stq_uop_13_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fence; // @[lsu.scala:252:32] wire s_uop_16_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fence = stq_uop_13_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_fencei; // @[lsu.scala:252:32] wire s_uop_16_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_fencei = stq_uop_13_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sfence; // @[lsu.scala:252:32] wire s_uop_16_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sfence = stq_uop_13_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_amo; // @[lsu.scala:252:32] wire s_uop_16_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_amo = stq_uop_13_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_eret; // @[lsu.scala:252:32] wire s_uop_16_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_eret = stq_uop_13_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_16_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_sys_pc2epc = stq_uop_13_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_rocc; // @[lsu.scala:252:32] wire s_uop_16_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_rocc = stq_uop_13_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_mov; // @[lsu.scala:252:32] wire s_uop_16_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_mov = stq_uop_13_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ftq_idx = stq_uop_13_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_edge_inst; // @[lsu.scala:252:32] wire s_uop_16_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_14_edge_inst = stq_uop_13_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_16_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_pc_lob = stq_uop_13_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_taken; // @[lsu.scala:252:32] wire s_uop_16_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1324:37] wire uop_14_taken = stq_uop_13_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_imm_rename; // @[lsu.scala:252:32] wire s_uop_16_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_14_imm_rename = stq_uop_13_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_imm_sel = stq_uop_13_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_16_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_pimm = stq_uop_13_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_13_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_16_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_14_imm_packed = stq_uop_13_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_16_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_op1_sel = stq_uop_13_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_16_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_op2_sel = stq_uop_13_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ldst = stq_uop_13_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wen = stq_uop_13_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren1 = stq_uop_13_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren2 = stq_uop_13_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_ren3 = stq_uop_13_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap12 = stq_uop_13_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_swap23 = stq_uop_13_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagIn = stq_uop_13_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_ctrl_typeTagOut = stq_uop_13_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fromint = stq_uop_13_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_toint = stq_uop_13_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fastpipe = stq_uop_13_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_fma = stq_uop_13_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_div = stq_uop_13_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_sqrt = stq_uop_13_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_wflags = stq_uop_13_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_16_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_ctrl_vec = stq_uop_13_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_16_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_rob_idx = stq_uop_13_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ldq_idx = stq_uop_13_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_16_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_stq_idx = stq_uop_13_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_16_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_rxq_idx = stq_uop_13_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_pdst = stq_uop_13_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs1 = stq_uop_13_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs2 = stq_uop_13_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_16_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_prs3 = stq_uop_13_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_16_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_ppred = stq_uop_13_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs1_busy; // @[lsu.scala:252:32] wire s_uop_16_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs1_busy = stq_uop_13_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs2_busy; // @[lsu.scala:252:32] wire s_uop_16_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs2_busy = stq_uop_13_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_prs3_busy; // @[lsu.scala:252:32] wire s_uop_16_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_prs3_busy = stq_uop_13_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ppred_busy; // @[lsu.scala:252:32] wire s_uop_16_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_14_ppred_busy = stq_uop_13_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_13_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_16_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_14_stale_pdst = stq_uop_13_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_exception; // @[lsu.scala:252:32] wire s_uop_16_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1324:37] wire uop_14_exception = stq_uop_13_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_13_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_16_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_14_exc_cause = stq_uop_13_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_16_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_mem_cmd = stq_uop_13_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_16_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_mem_size = stq_uop_13_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_mem_signed; // @[lsu.scala:252:32] wire s_uop_16_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_14_mem_signed = stq_uop_13_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_ldq; // @[lsu.scala:252:32] wire s_uop_16_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_ldq = stq_uop_13_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_uses_stq; // @[lsu.scala:252:32] wire s_uop_16_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_14_uses_stq = stq_uop_13_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_is_unique; // @[lsu.scala:252:32] wire s_uop_16_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_14_is_unique = stq_uop_13_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_16_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_14_flush_on_commit = stq_uop_13_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_16_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_csr_cmd = stq_uop_13_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_16_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_14_ldst_is_rs1 = stq_uop_13_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_16_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_ldst = stq_uop_13_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs1 = stq_uop_13_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs2 = stq_uop_13_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_13_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_16_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_14_lrs3 = stq_uop_13_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_dst_rtype = stq_uop_13_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs1_rtype = stq_uop_13_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_16_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_lrs2_rtype = stq_uop_13_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_frs3_en; // @[lsu.scala:252:32] wire s_uop_16_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_14_frs3_en = stq_uop_13_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fcn_dw; // @[lsu.scala:252:32] wire s_uop_16_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_14_fcn_dw = stq_uop_13_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_13_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_16_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_14_fcn_op = stq_uop_13_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_fp_val; // @[lsu.scala:252:32] wire s_uop_16_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_14_fp_val = stq_uop_13_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_16_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_fp_rm = stq_uop_13_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_13_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_16_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_14_fp_typ = stq_uop_13_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_pf_if = stq_uop_13_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ae_if = stq_uop_13_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_16_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_xcpt_ma_if = stq_uop_13_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_16_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_debug_if = stq_uop_13_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_16_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_14_bp_xcpt_if = stq_uop_13_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_fsrc = stq_uop_13_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_13_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_16_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_14_debug_tsrc = stq_uop_13_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_inst = stq_uop_14_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_14_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_17_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_15_debug_inst = stq_uop_14_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rvc; // @[lsu.scala:252:32] wire s_uop_17_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rvc = stq_uop_14_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_14_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_17_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_15_debug_pc = stq_uop_14_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_0; // @[lsu.scala:252:32] wire s_uop_17_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_0 = stq_uop_14_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_1; // @[lsu.scala:252:32] wire s_uop_17_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_1 = stq_uop_14_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_2; // @[lsu.scala:252:32] wire s_uop_17_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_2 = stq_uop_14_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iq_type_3; // @[lsu.scala:252:32] wire s_uop_17_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_iq_type_3 = stq_uop_14_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_0; // @[lsu.scala:252:32] wire s_uop_17_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_0 = stq_uop_14_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_1; // @[lsu.scala:252:32] wire s_uop_17_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_1 = stq_uop_14_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_2; // @[lsu.scala:252:32] wire s_uop_17_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_2 = stq_uop_14_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_3; // @[lsu.scala:252:32] wire s_uop_17_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_3 = stq_uop_14_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_4; // @[lsu.scala:252:32] wire s_uop_17_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_4 = stq_uop_14_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_5; // @[lsu.scala:252:32] wire s_uop_17_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_5 = stq_uop_14_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_6; // @[lsu.scala:252:32] wire s_uop_17_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_6 = stq_uop_14_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_7; // @[lsu.scala:252:32] wire s_uop_17_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_7 = stq_uop_14_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_8; // @[lsu.scala:252:32] wire s_uop_17_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_8 = stq_uop_14_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fu_code_9; // @[lsu.scala:252:32] wire s_uop_17_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_15_fu_code_9 = stq_uop_14_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued; // @[lsu.scala:252:32] wire s_uop_17_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued = stq_uop_14_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_agen = stq_uop_14_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_17_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_issued_partial_dgen = stq_uop_14_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_17_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_iw_p1_speculative_child = stq_uop_14_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_17_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_iw_p2_speculative_child = stq_uop_14_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p1_bypass_hint = stq_uop_14_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p2_bypass_hint = stq_uop_14_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_17_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_15_iw_p3_bypass_hint = stq_uop_14_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_dis_col_sel = stq_uop_14_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_14_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_17_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_15_br_mask = stq_uop_14_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_tag = stq_uop_14_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_14_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_17_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_15_br_type = stq_uop_14_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfb; // @[lsu.scala:252:32] wire s_uop_17_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfb = stq_uop_14_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fence; // @[lsu.scala:252:32] wire s_uop_17_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fence = stq_uop_14_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_fencei; // @[lsu.scala:252:32] wire s_uop_17_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_fencei = stq_uop_14_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sfence; // @[lsu.scala:252:32] wire s_uop_17_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sfence = stq_uop_14_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_amo; // @[lsu.scala:252:32] wire s_uop_17_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_amo = stq_uop_14_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_eret; // @[lsu.scala:252:32] wire s_uop_17_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_eret = stq_uop_14_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_17_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_sys_pc2epc = stq_uop_14_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_rocc; // @[lsu.scala:252:32] wire s_uop_17_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_rocc = stq_uop_14_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_mov; // @[lsu.scala:252:32] wire s_uop_17_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_mov = stq_uop_14_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ftq_idx = stq_uop_14_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_edge_inst; // @[lsu.scala:252:32] wire s_uop_17_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_15_edge_inst = stq_uop_14_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_17_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_pc_lob = stq_uop_14_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_taken; // @[lsu.scala:252:32] wire s_uop_17_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1324:37] wire uop_15_taken = stq_uop_14_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_imm_rename; // @[lsu.scala:252:32] wire s_uop_17_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_15_imm_rename = stq_uop_14_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_imm_sel = stq_uop_14_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_17_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_pimm = stq_uop_14_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_14_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_17_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_15_imm_packed = stq_uop_14_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_17_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_op1_sel = stq_uop_14_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_17_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_op2_sel = stq_uop_14_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ldst = stq_uop_14_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wen = stq_uop_14_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren1 = stq_uop_14_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren2 = stq_uop_14_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_ren3 = stq_uop_14_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap12 = stq_uop_14_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_swap23 = stq_uop_14_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagIn = stq_uop_14_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_ctrl_typeTagOut = stq_uop_14_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fromint = stq_uop_14_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_toint = stq_uop_14_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fastpipe = stq_uop_14_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_fma = stq_uop_14_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_div = stq_uop_14_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_sqrt = stq_uop_14_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_wflags = stq_uop_14_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_17_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_ctrl_vec = stq_uop_14_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_17_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_rob_idx = stq_uop_14_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ldq_idx = stq_uop_14_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_17_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_stq_idx = stq_uop_14_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_17_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_rxq_idx = stq_uop_14_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_pdst = stq_uop_14_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs1 = stq_uop_14_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs2 = stq_uop_14_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_17_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_prs3 = stq_uop_14_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_17_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_ppred = stq_uop_14_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs1_busy; // @[lsu.scala:252:32] wire s_uop_17_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs1_busy = stq_uop_14_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs2_busy; // @[lsu.scala:252:32] wire s_uop_17_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs2_busy = stq_uop_14_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_prs3_busy; // @[lsu.scala:252:32] wire s_uop_17_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_prs3_busy = stq_uop_14_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ppred_busy; // @[lsu.scala:252:32] wire s_uop_17_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_15_ppred_busy = stq_uop_14_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_14_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_17_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_15_stale_pdst = stq_uop_14_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_exception; // @[lsu.scala:252:32] wire s_uop_17_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1324:37] wire uop_15_exception = stq_uop_14_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_14_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_17_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_15_exc_cause = stq_uop_14_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_17_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_mem_cmd = stq_uop_14_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_17_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_mem_size = stq_uop_14_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_mem_signed; // @[lsu.scala:252:32] wire s_uop_17_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_15_mem_signed = stq_uop_14_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_ldq; // @[lsu.scala:252:32] wire s_uop_17_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_ldq = stq_uop_14_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_uses_stq; // @[lsu.scala:252:32] wire s_uop_17_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_15_uses_stq = stq_uop_14_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_is_unique; // @[lsu.scala:252:32] wire s_uop_17_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_15_is_unique = stq_uop_14_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_17_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_15_flush_on_commit = stq_uop_14_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_17_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_csr_cmd = stq_uop_14_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_17_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_15_ldst_is_rs1 = stq_uop_14_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_17_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_ldst = stq_uop_14_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs1 = stq_uop_14_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs2 = stq_uop_14_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_14_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_17_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_15_lrs3 = stq_uop_14_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_dst_rtype = stq_uop_14_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs1_rtype = stq_uop_14_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_17_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_lrs2_rtype = stq_uop_14_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_frs3_en; // @[lsu.scala:252:32] wire s_uop_17_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_15_frs3_en = stq_uop_14_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fcn_dw; // @[lsu.scala:252:32] wire s_uop_17_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_15_fcn_dw = stq_uop_14_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_14_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_17_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_15_fcn_op = stq_uop_14_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_fp_val; // @[lsu.scala:252:32] wire s_uop_17_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_15_fp_val = stq_uop_14_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_17_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_fp_rm = stq_uop_14_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_14_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_17_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_15_fp_typ = stq_uop_14_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_pf_if = stq_uop_14_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ae_if = stq_uop_14_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_17_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_xcpt_ma_if = stq_uop_14_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_17_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_debug_if = stq_uop_14_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_17_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_15_bp_xcpt_if = stq_uop_14_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_fsrc = stq_uop_14_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_14_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_17_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_15_debug_tsrc = stq_uop_14_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_18_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_inst = stq_uop_15_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_15_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_18_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_16_debug_inst = stq_uop_15_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rvc; // @[lsu.scala:252:32] wire s_uop_18_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rvc = stq_uop_15_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_15_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_18_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_16_debug_pc = stq_uop_15_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_0; // @[lsu.scala:252:32] wire s_uop_18_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_0 = stq_uop_15_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_1; // @[lsu.scala:252:32] wire s_uop_18_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_1 = stq_uop_15_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_2; // @[lsu.scala:252:32] wire s_uop_18_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_2 = stq_uop_15_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iq_type_3; // @[lsu.scala:252:32] wire s_uop_18_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_iq_type_3 = stq_uop_15_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_0; // @[lsu.scala:252:32] wire s_uop_18_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_0 = stq_uop_15_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_1; // @[lsu.scala:252:32] wire s_uop_18_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_1 = stq_uop_15_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_2; // @[lsu.scala:252:32] wire s_uop_18_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_2 = stq_uop_15_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_3; // @[lsu.scala:252:32] wire s_uop_18_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_3 = stq_uop_15_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_4; // @[lsu.scala:252:32] wire s_uop_18_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_4 = stq_uop_15_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_5; // @[lsu.scala:252:32] wire s_uop_18_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_5 = stq_uop_15_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_6; // @[lsu.scala:252:32] wire s_uop_18_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_6 = stq_uop_15_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_7; // @[lsu.scala:252:32] wire s_uop_18_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_7 = stq_uop_15_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_8; // @[lsu.scala:252:32] wire s_uop_18_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_8 = stq_uop_15_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fu_code_9; // @[lsu.scala:252:32] wire s_uop_18_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_16_fu_code_9 = stq_uop_15_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued; // @[lsu.scala:252:32] wire s_uop_18_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued = stq_uop_15_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_18_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_agen = stq_uop_15_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_18_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_issued_partial_dgen = stq_uop_15_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_18_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_iw_p1_speculative_child = stq_uop_15_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_18_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_iw_p2_speculative_child = stq_uop_15_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p1_bypass_hint = stq_uop_15_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p2_bypass_hint = stq_uop_15_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_18_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_16_iw_p3_bypass_hint = stq_uop_15_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_dis_col_sel = stq_uop_15_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_15_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_18_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_16_br_mask = stq_uop_15_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_18_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_tag = stq_uop_15_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_15_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_18_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_16_br_type = stq_uop_15_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfb; // @[lsu.scala:252:32] wire s_uop_18_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfb = stq_uop_15_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fence; // @[lsu.scala:252:32] wire s_uop_18_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fence = stq_uop_15_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_fencei; // @[lsu.scala:252:32] wire s_uop_18_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_fencei = stq_uop_15_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sfence; // @[lsu.scala:252:32] wire s_uop_18_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sfence = stq_uop_15_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_amo; // @[lsu.scala:252:32] wire s_uop_18_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_amo = stq_uop_15_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_eret; // @[lsu.scala:252:32] wire s_uop_18_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_eret = stq_uop_15_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_18_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_sys_pc2epc = stq_uop_15_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_rocc; // @[lsu.scala:252:32] wire s_uop_18_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_rocc = stq_uop_15_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_mov; // @[lsu.scala:252:32] wire s_uop_18_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_mov = stq_uop_15_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ftq_idx = stq_uop_15_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_edge_inst; // @[lsu.scala:252:32] wire s_uop_18_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_16_edge_inst = stq_uop_15_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_18_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_pc_lob = stq_uop_15_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_taken; // @[lsu.scala:252:32] wire s_uop_18_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1324:37] wire uop_16_taken = stq_uop_15_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_imm_rename; // @[lsu.scala:252:32] wire s_uop_18_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_16_imm_rename = stq_uop_15_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_imm_sel = stq_uop_15_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_18_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_pimm = stq_uop_15_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_15_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_18_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_16_imm_packed = stq_uop_15_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_18_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_op1_sel = stq_uop_15_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_18_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_op2_sel = stq_uop_15_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ldst = stq_uop_15_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wen = stq_uop_15_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren1 = stq_uop_15_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren2 = stq_uop_15_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_ren3 = stq_uop_15_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap12 = stq_uop_15_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_swap23 = stq_uop_15_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagIn = stq_uop_15_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_ctrl_typeTagOut = stq_uop_15_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fromint = stq_uop_15_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_toint = stq_uop_15_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fastpipe = stq_uop_15_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_fma = stq_uop_15_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_div = stq_uop_15_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_sqrt = stq_uop_15_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_wflags = stq_uop_15_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_18_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_ctrl_vec = stq_uop_15_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_18_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_rob_idx = stq_uop_15_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ldq_idx = stq_uop_15_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_18_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_stq_idx = stq_uop_15_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_18_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_rxq_idx = stq_uop_15_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_18_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_pdst = stq_uop_15_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs1 = stq_uop_15_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs2 = stq_uop_15_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_18_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_prs3 = stq_uop_15_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_18_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_ppred = stq_uop_15_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs1_busy; // @[lsu.scala:252:32] wire s_uop_18_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs1_busy = stq_uop_15_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs2_busy; // @[lsu.scala:252:32] wire s_uop_18_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs2_busy = stq_uop_15_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_prs3_busy; // @[lsu.scala:252:32] wire s_uop_18_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_prs3_busy = stq_uop_15_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ppred_busy; // @[lsu.scala:252:32] wire s_uop_18_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_16_ppred_busy = stq_uop_15_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_15_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_18_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_16_stale_pdst = stq_uop_15_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_exception; // @[lsu.scala:252:32] wire s_uop_18_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1324:37] wire uop_16_exception = stq_uop_15_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_15_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_18_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_16_exc_cause = stq_uop_15_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_18_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_mem_cmd = stq_uop_15_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_18_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_mem_size = stq_uop_15_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_mem_signed; // @[lsu.scala:252:32] wire s_uop_18_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_16_mem_signed = stq_uop_15_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_ldq; // @[lsu.scala:252:32] wire s_uop_18_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_ldq = stq_uop_15_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_uses_stq; // @[lsu.scala:252:32] wire s_uop_18_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_16_uses_stq = stq_uop_15_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_is_unique; // @[lsu.scala:252:32] wire s_uop_18_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_16_is_unique = stq_uop_15_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_18_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_16_flush_on_commit = stq_uop_15_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_18_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_csr_cmd = stq_uop_15_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_18_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_16_ldst_is_rs1 = stq_uop_15_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_18_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_ldst = stq_uop_15_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs1 = stq_uop_15_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs2 = stq_uop_15_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_15_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_18_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_16_lrs3 = stq_uop_15_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_dst_rtype = stq_uop_15_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs1_rtype = stq_uop_15_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_18_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_lrs2_rtype = stq_uop_15_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_frs3_en; // @[lsu.scala:252:32] wire s_uop_18_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_16_frs3_en = stq_uop_15_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fcn_dw; // @[lsu.scala:252:32] wire s_uop_18_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_16_fcn_dw = stq_uop_15_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_15_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_18_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_16_fcn_op = stq_uop_15_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_fp_val; // @[lsu.scala:252:32] wire s_uop_18_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_16_fp_val = stq_uop_15_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_18_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_fp_rm = stq_uop_15_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_15_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_18_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_16_fp_typ = stq_uop_15_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_pf_if = stq_uop_15_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ae_if = stq_uop_15_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_18_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_xcpt_ma_if = stq_uop_15_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_18_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_debug_if = stq_uop_15_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_18_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_16_bp_xcpt_if = stq_uop_15_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_18_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_fsrc = stq_uop_15_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_15_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_18_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_16_debug_tsrc = stq_uop_15_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_16_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_19_inst = stq_uop_16_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_17_inst = stq_uop_16_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_16_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_19_debug_inst = stq_uop_16_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_17_debug_inst = stq_uop_16_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_rvc; // @[lsu.scala:252:32] wire s_uop_19_is_rvc = stq_uop_16_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_rvc = stq_uop_16_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_16_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_19_debug_pc = stq_uop_16_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_17_debug_pc = stq_uop_16_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_0; // @[lsu.scala:252:32] wire s_uop_19_iq_type_0 = stq_uop_16_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_0 = stq_uop_16_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_1; // @[lsu.scala:252:32] wire s_uop_19_iq_type_1 = stq_uop_16_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_1 = stq_uop_16_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_2; // @[lsu.scala:252:32] wire s_uop_19_iq_type_2 = stq_uop_16_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_2 = stq_uop_16_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iq_type_3; // @[lsu.scala:252:32] wire s_uop_19_iq_type_3 = stq_uop_16_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_17_iq_type_3 = stq_uop_16_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_0; // @[lsu.scala:252:32] wire s_uop_19_fu_code_0 = stq_uop_16_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_0 = stq_uop_16_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_1; // @[lsu.scala:252:32] wire s_uop_19_fu_code_1 = stq_uop_16_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_1 = stq_uop_16_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_2; // @[lsu.scala:252:32] wire s_uop_19_fu_code_2 = stq_uop_16_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_2 = stq_uop_16_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_3; // @[lsu.scala:252:32] wire s_uop_19_fu_code_3 = stq_uop_16_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_3 = stq_uop_16_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_4; // @[lsu.scala:252:32] wire s_uop_19_fu_code_4 = stq_uop_16_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_4 = stq_uop_16_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_5; // @[lsu.scala:252:32] wire s_uop_19_fu_code_5 = stq_uop_16_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_5 = stq_uop_16_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_6; // @[lsu.scala:252:32] wire s_uop_19_fu_code_6 = stq_uop_16_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_6 = stq_uop_16_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_7; // @[lsu.scala:252:32] wire s_uop_19_fu_code_7 = stq_uop_16_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_7 = stq_uop_16_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_8; // @[lsu.scala:252:32] wire s_uop_19_fu_code_8 = stq_uop_16_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_8 = stq_uop_16_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fu_code_9; // @[lsu.scala:252:32] wire s_uop_19_fu_code_9 = stq_uop_16_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_17_fu_code_9 = stq_uop_16_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued; // @[lsu.scala:252:32] wire s_uop_19_iw_issued = stq_uop_16_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued = stq_uop_16_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_19_iw_issued_partial_agen = stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued_partial_agen = stq_uop_16_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_19_iw_issued_partial_dgen = stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_issued_partial_dgen = stq_uop_16_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_19_iw_p1_speculative_child = stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_iw_p1_speculative_child = stq_uop_16_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_19_iw_p2_speculative_child = stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_iw_p2_speculative_child = stq_uop_16_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p1_bypass_hint = stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p1_bypass_hint = stq_uop_16_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p2_bypass_hint = stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p2_bypass_hint = stq_uop_16_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_19_iw_p3_bypass_hint = stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_17_iw_p3_bypass_hint = stq_uop_16_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_dis_col_sel = stq_uop_16_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_dis_col_sel = stq_uop_16_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_16_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_19_br_mask = stq_uop_16_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_17_br_mask = stq_uop_16_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_16_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_19_br_tag = stq_uop_16_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_17_br_tag = stq_uop_16_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_16_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_19_br_type = stq_uop_16_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_17_br_type = stq_uop_16_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sfb; // @[lsu.scala:252:32] wire s_uop_19_is_sfb = stq_uop_16_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sfb = stq_uop_16_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_fence; // @[lsu.scala:252:32] wire s_uop_19_is_fence = stq_uop_16_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_fence = stq_uop_16_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_fencei; // @[lsu.scala:252:32] wire s_uop_19_is_fencei = stq_uop_16_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_fencei = stq_uop_16_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sfence; // @[lsu.scala:252:32] wire s_uop_19_is_sfence = stq_uop_16_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sfence = stq_uop_16_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_amo; // @[lsu.scala:252:32] wire s_uop_19_is_amo = stq_uop_16_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_amo = stq_uop_16_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_eret; // @[lsu.scala:252:32] wire s_uop_19_is_eret = stq_uop_16_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_eret = stq_uop_16_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_19_is_sys_pc2epc = stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_sys_pc2epc = stq_uop_16_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_rocc; // @[lsu.scala:252:32] wire s_uop_19_is_rocc = stq_uop_16_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_rocc = stq_uop_16_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_mov; // @[lsu.scala:252:32] wire s_uop_19_is_mov = stq_uop_16_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_mov = stq_uop_16_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ftq_idx = stq_uop_16_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ftq_idx = stq_uop_16_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_edge_inst; // @[lsu.scala:252:32] wire s_uop_19_edge_inst = stq_uop_16_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_17_edge_inst = stq_uop_16_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_19_pc_lob = stq_uop_16_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_pc_lob = stq_uop_16_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_taken; // @[lsu.scala:252:32] wire s_uop_19_taken = stq_uop_16_taken; // @[lsu.scala:252:32, :1324:37] wire uop_17_taken = stq_uop_16_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_imm_rename; // @[lsu.scala:252:32] wire s_uop_19_imm_rename = stq_uop_16_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_17_imm_rename = stq_uop_16_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_imm_sel = stq_uop_16_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_imm_sel = stq_uop_16_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_19_pimm = stq_uop_16_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_pimm = stq_uop_16_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_16_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_19_imm_packed = stq_uop_16_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_17_imm_packed = stq_uop_16_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_19_op1_sel = stq_uop_16_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_op1_sel = stq_uop_16_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_19_op2_sel = stq_uop_16_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_op2_sel = stq_uop_16_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ldst = stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ldst = stq_uop_16_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_wen = stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_wen = stq_uop_16_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren1 = stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren1 = stq_uop_16_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren2 = stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren2 = stq_uop_16_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_ren3 = stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_ren3 = stq_uop_16_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_swap12 = stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_swap12 = stq_uop_16_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_swap23 = stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_swap23 = stq_uop_16_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_ctrl_typeTagIn = stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_ctrl_typeTagIn = stq_uop_16_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_ctrl_typeTagOut = stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_ctrl_typeTagOut = stq_uop_16_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fromint = stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fromint = stq_uop_16_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_toint = stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_toint = stq_uop_16_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fastpipe = stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fastpipe = stq_uop_16_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_fma = stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_fma = stq_uop_16_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_div = stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_div = stq_uop_16_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_sqrt = stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_sqrt = stq_uop_16_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_wflags = stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_wflags = stq_uop_16_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_19_fp_ctrl_vec = stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_ctrl_vec = stq_uop_16_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_19_rob_idx = stq_uop_16_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_rob_idx = stq_uop_16_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ldq_idx = stq_uop_16_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ldq_idx = stq_uop_16_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_19_stq_idx = stq_uop_16_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_stq_idx = stq_uop_16_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_19_rxq_idx = stq_uop_16_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_rxq_idx = stq_uop_16_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_19_pdst = stq_uop_16_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_pdst = stq_uop_16_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs1 = stq_uop_16_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs1 = stq_uop_16_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs2 = stq_uop_16_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs2 = stq_uop_16_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_19_prs3 = stq_uop_16_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_prs3 = stq_uop_16_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_19_ppred = stq_uop_16_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_ppred = stq_uop_16_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs1_busy; // @[lsu.scala:252:32] wire s_uop_19_prs1_busy = stq_uop_16_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs1_busy = stq_uop_16_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs2_busy; // @[lsu.scala:252:32] wire s_uop_19_prs2_busy = stq_uop_16_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs2_busy = stq_uop_16_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_prs3_busy; // @[lsu.scala:252:32] wire s_uop_19_prs3_busy = stq_uop_16_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_prs3_busy = stq_uop_16_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_ppred_busy; // @[lsu.scala:252:32] wire s_uop_19_ppred_busy = stq_uop_16_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_17_ppred_busy = stq_uop_16_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_16_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_19_stale_pdst = stq_uop_16_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_17_stale_pdst = stq_uop_16_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_exception; // @[lsu.scala:252:32] wire s_uop_19_exception = stq_uop_16_exception; // @[lsu.scala:252:32, :1324:37] wire uop_17_exception = stq_uop_16_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_16_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_19_exc_cause = stq_uop_16_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_17_exc_cause = stq_uop_16_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_19_mem_cmd = stq_uop_16_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_mem_cmd = stq_uop_16_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_19_mem_size = stq_uop_16_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_mem_size = stq_uop_16_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_mem_signed; // @[lsu.scala:252:32] wire s_uop_19_mem_signed = stq_uop_16_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_17_mem_signed = stq_uop_16_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_uses_ldq; // @[lsu.scala:252:32] wire s_uop_19_uses_ldq = stq_uop_16_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_17_uses_ldq = stq_uop_16_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_uses_stq; // @[lsu.scala:252:32] wire s_uop_19_uses_stq = stq_uop_16_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_17_uses_stq = stq_uop_16_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_is_unique; // @[lsu.scala:252:32] wire s_uop_19_is_unique = stq_uop_16_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_17_is_unique = stq_uop_16_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_19_flush_on_commit = stq_uop_16_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_17_flush_on_commit = stq_uop_16_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_19_csr_cmd = stq_uop_16_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_csr_cmd = stq_uop_16_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_19_ldst_is_rs1 = stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_17_ldst_is_rs1 = stq_uop_16_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_19_ldst = stq_uop_16_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_ldst = stq_uop_16_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs1 = stq_uop_16_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs1 = stq_uop_16_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs2 = stq_uop_16_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs2 = stq_uop_16_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_16_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_19_lrs3 = stq_uop_16_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_17_lrs3 = stq_uop_16_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_dst_rtype = stq_uop_16_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_dst_rtype = stq_uop_16_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_lrs1_rtype = stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_lrs1_rtype = stq_uop_16_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_19_lrs2_rtype = stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_lrs2_rtype = stq_uop_16_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_frs3_en; // @[lsu.scala:252:32] wire s_uop_19_frs3_en = stq_uop_16_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_17_frs3_en = stq_uop_16_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fcn_dw; // @[lsu.scala:252:32] wire s_uop_19_fcn_dw = stq_uop_16_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_17_fcn_dw = stq_uop_16_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_16_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_19_fcn_op = stq_uop_16_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_17_fcn_op = stq_uop_16_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_fp_val; // @[lsu.scala:252:32] wire s_uop_19_fp_val = stq_uop_16_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_17_fp_val = stq_uop_16_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_19_fp_rm = stq_uop_16_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_fp_rm = stq_uop_16_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_16_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_19_fp_typ = stq_uop_16_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_17_fp_typ = stq_uop_16_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_pf_if = stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_pf_if = stq_uop_16_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_ae_if = stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_ae_if = stq_uop_16_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_19_xcpt_ma_if = stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_xcpt_ma_if = stq_uop_16_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_19_bp_debug_if = stq_uop_16_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_bp_debug_if = stq_uop_16_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_19_bp_xcpt_if = stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_17_bp_xcpt_if = stq_uop_16_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_19_debug_fsrc = stq_uop_16_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_debug_fsrc = stq_uop_16_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_16_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_19_debug_tsrc = stq_uop_16_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_17_debug_tsrc = stq_uop_16_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_17_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_20_inst = stq_uop_17_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_18_inst = stq_uop_17_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_17_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_20_debug_inst = stq_uop_17_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_18_debug_inst = stq_uop_17_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_rvc; // @[lsu.scala:252:32] wire s_uop_20_is_rvc = stq_uop_17_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_rvc = stq_uop_17_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_17_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_20_debug_pc = stq_uop_17_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_18_debug_pc = stq_uop_17_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_0; // @[lsu.scala:252:32] wire s_uop_20_iq_type_0 = stq_uop_17_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_0 = stq_uop_17_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_1; // @[lsu.scala:252:32] wire s_uop_20_iq_type_1 = stq_uop_17_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_1 = stq_uop_17_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_2; // @[lsu.scala:252:32] wire s_uop_20_iq_type_2 = stq_uop_17_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_2 = stq_uop_17_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iq_type_3; // @[lsu.scala:252:32] wire s_uop_20_iq_type_3 = stq_uop_17_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_18_iq_type_3 = stq_uop_17_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_0; // @[lsu.scala:252:32] wire s_uop_20_fu_code_0 = stq_uop_17_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_0 = stq_uop_17_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_1; // @[lsu.scala:252:32] wire s_uop_20_fu_code_1 = stq_uop_17_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_1 = stq_uop_17_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_2; // @[lsu.scala:252:32] wire s_uop_20_fu_code_2 = stq_uop_17_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_2 = stq_uop_17_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_3; // @[lsu.scala:252:32] wire s_uop_20_fu_code_3 = stq_uop_17_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_3 = stq_uop_17_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_4; // @[lsu.scala:252:32] wire s_uop_20_fu_code_4 = stq_uop_17_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_4 = stq_uop_17_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_5; // @[lsu.scala:252:32] wire s_uop_20_fu_code_5 = stq_uop_17_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_5 = stq_uop_17_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_6; // @[lsu.scala:252:32] wire s_uop_20_fu_code_6 = stq_uop_17_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_6 = stq_uop_17_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_7; // @[lsu.scala:252:32] wire s_uop_20_fu_code_7 = stq_uop_17_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_7 = stq_uop_17_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_8; // @[lsu.scala:252:32] wire s_uop_20_fu_code_8 = stq_uop_17_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_8 = stq_uop_17_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fu_code_9; // @[lsu.scala:252:32] wire s_uop_20_fu_code_9 = stq_uop_17_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_18_fu_code_9 = stq_uop_17_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued; // @[lsu.scala:252:32] wire s_uop_20_iw_issued = stq_uop_17_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued = stq_uop_17_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_20_iw_issued_partial_agen = stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued_partial_agen = stq_uop_17_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_20_iw_issued_partial_dgen = stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_issued_partial_dgen = stq_uop_17_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_20_iw_p1_speculative_child = stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_iw_p1_speculative_child = stq_uop_17_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_20_iw_p2_speculative_child = stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_iw_p2_speculative_child = stq_uop_17_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p1_bypass_hint = stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p1_bypass_hint = stq_uop_17_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p2_bypass_hint = stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p2_bypass_hint = stq_uop_17_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_20_iw_p3_bypass_hint = stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_18_iw_p3_bypass_hint = stq_uop_17_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_dis_col_sel = stq_uop_17_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_dis_col_sel = stq_uop_17_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_17_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_20_br_mask = stq_uop_17_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_18_br_mask = stq_uop_17_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_17_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_20_br_tag = stq_uop_17_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_18_br_tag = stq_uop_17_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_17_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_20_br_type = stq_uop_17_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_18_br_type = stq_uop_17_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sfb; // @[lsu.scala:252:32] wire s_uop_20_is_sfb = stq_uop_17_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sfb = stq_uop_17_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_fence; // @[lsu.scala:252:32] wire s_uop_20_is_fence = stq_uop_17_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_fence = stq_uop_17_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_fencei; // @[lsu.scala:252:32] wire s_uop_20_is_fencei = stq_uop_17_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_fencei = stq_uop_17_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sfence; // @[lsu.scala:252:32] wire s_uop_20_is_sfence = stq_uop_17_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sfence = stq_uop_17_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_amo; // @[lsu.scala:252:32] wire s_uop_20_is_amo = stq_uop_17_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_amo = stq_uop_17_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_eret; // @[lsu.scala:252:32] wire s_uop_20_is_eret = stq_uop_17_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_eret = stq_uop_17_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_20_is_sys_pc2epc = stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_sys_pc2epc = stq_uop_17_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_rocc; // @[lsu.scala:252:32] wire s_uop_20_is_rocc = stq_uop_17_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_rocc = stq_uop_17_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_mov; // @[lsu.scala:252:32] wire s_uop_20_is_mov = stq_uop_17_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_mov = stq_uop_17_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ftq_idx = stq_uop_17_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ftq_idx = stq_uop_17_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_edge_inst; // @[lsu.scala:252:32] wire s_uop_20_edge_inst = stq_uop_17_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_18_edge_inst = stq_uop_17_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_20_pc_lob = stq_uop_17_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_pc_lob = stq_uop_17_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_taken; // @[lsu.scala:252:32] wire s_uop_20_taken = stq_uop_17_taken; // @[lsu.scala:252:32, :1324:37] wire uop_18_taken = stq_uop_17_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_imm_rename; // @[lsu.scala:252:32] wire s_uop_20_imm_rename = stq_uop_17_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_18_imm_rename = stq_uop_17_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_imm_sel = stq_uop_17_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_imm_sel = stq_uop_17_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_20_pimm = stq_uop_17_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_pimm = stq_uop_17_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_17_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_20_imm_packed = stq_uop_17_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_18_imm_packed = stq_uop_17_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_20_op1_sel = stq_uop_17_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_op1_sel = stq_uop_17_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_20_op2_sel = stq_uop_17_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_op2_sel = stq_uop_17_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ldst = stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ldst = stq_uop_17_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_wen = stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_wen = stq_uop_17_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren1 = stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren1 = stq_uop_17_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren2 = stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren2 = stq_uop_17_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_ren3 = stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_ren3 = stq_uop_17_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_swap12 = stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_swap12 = stq_uop_17_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_swap23 = stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_swap23 = stq_uop_17_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_ctrl_typeTagIn = stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_ctrl_typeTagIn = stq_uop_17_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_ctrl_typeTagOut = stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_ctrl_typeTagOut = stq_uop_17_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fromint = stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fromint = stq_uop_17_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_toint = stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_toint = stq_uop_17_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fastpipe = stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fastpipe = stq_uop_17_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_fma = stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_fma = stq_uop_17_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_div = stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_div = stq_uop_17_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_sqrt = stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_sqrt = stq_uop_17_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_wflags = stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_wflags = stq_uop_17_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_20_fp_ctrl_vec = stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_ctrl_vec = stq_uop_17_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_20_rob_idx = stq_uop_17_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_rob_idx = stq_uop_17_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ldq_idx = stq_uop_17_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ldq_idx = stq_uop_17_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_20_stq_idx = stq_uop_17_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_stq_idx = stq_uop_17_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_20_rxq_idx = stq_uop_17_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_rxq_idx = stq_uop_17_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_20_pdst = stq_uop_17_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_pdst = stq_uop_17_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs1 = stq_uop_17_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs1 = stq_uop_17_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs2 = stq_uop_17_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs2 = stq_uop_17_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_20_prs3 = stq_uop_17_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_prs3 = stq_uop_17_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_20_ppred = stq_uop_17_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_ppred = stq_uop_17_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs1_busy; // @[lsu.scala:252:32] wire s_uop_20_prs1_busy = stq_uop_17_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs1_busy = stq_uop_17_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs2_busy; // @[lsu.scala:252:32] wire s_uop_20_prs2_busy = stq_uop_17_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs2_busy = stq_uop_17_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_prs3_busy; // @[lsu.scala:252:32] wire s_uop_20_prs3_busy = stq_uop_17_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_prs3_busy = stq_uop_17_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_ppred_busy; // @[lsu.scala:252:32] wire s_uop_20_ppred_busy = stq_uop_17_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_18_ppred_busy = stq_uop_17_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_17_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_20_stale_pdst = stq_uop_17_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_18_stale_pdst = stq_uop_17_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_exception; // @[lsu.scala:252:32] wire s_uop_20_exception = stq_uop_17_exception; // @[lsu.scala:252:32, :1324:37] wire uop_18_exception = stq_uop_17_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_17_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_20_exc_cause = stq_uop_17_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_18_exc_cause = stq_uop_17_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_20_mem_cmd = stq_uop_17_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_mem_cmd = stq_uop_17_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_20_mem_size = stq_uop_17_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_mem_size = stq_uop_17_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_mem_signed; // @[lsu.scala:252:32] wire s_uop_20_mem_signed = stq_uop_17_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_18_mem_signed = stq_uop_17_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_uses_ldq; // @[lsu.scala:252:32] wire s_uop_20_uses_ldq = stq_uop_17_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_18_uses_ldq = stq_uop_17_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_uses_stq; // @[lsu.scala:252:32] wire s_uop_20_uses_stq = stq_uop_17_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_18_uses_stq = stq_uop_17_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_is_unique; // @[lsu.scala:252:32] wire s_uop_20_is_unique = stq_uop_17_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_18_is_unique = stq_uop_17_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_20_flush_on_commit = stq_uop_17_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_18_flush_on_commit = stq_uop_17_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_20_csr_cmd = stq_uop_17_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_csr_cmd = stq_uop_17_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_20_ldst_is_rs1 = stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_18_ldst_is_rs1 = stq_uop_17_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_20_ldst = stq_uop_17_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_ldst = stq_uop_17_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs1 = stq_uop_17_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs1 = stq_uop_17_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs2 = stq_uop_17_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs2 = stq_uop_17_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_17_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_20_lrs3 = stq_uop_17_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_18_lrs3 = stq_uop_17_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_dst_rtype = stq_uop_17_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_dst_rtype = stq_uop_17_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_lrs1_rtype = stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_lrs1_rtype = stq_uop_17_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_20_lrs2_rtype = stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_lrs2_rtype = stq_uop_17_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_frs3_en; // @[lsu.scala:252:32] wire s_uop_20_frs3_en = stq_uop_17_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_18_frs3_en = stq_uop_17_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fcn_dw; // @[lsu.scala:252:32] wire s_uop_20_fcn_dw = stq_uop_17_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_18_fcn_dw = stq_uop_17_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_17_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_20_fcn_op = stq_uop_17_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_18_fcn_op = stq_uop_17_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_fp_val; // @[lsu.scala:252:32] wire s_uop_20_fp_val = stq_uop_17_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_18_fp_val = stq_uop_17_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_20_fp_rm = stq_uop_17_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_fp_rm = stq_uop_17_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_17_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_20_fp_typ = stq_uop_17_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_18_fp_typ = stq_uop_17_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_pf_if = stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_pf_if = stq_uop_17_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_ae_if = stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_ae_if = stq_uop_17_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_20_xcpt_ma_if = stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_xcpt_ma_if = stq_uop_17_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_20_bp_debug_if = stq_uop_17_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_bp_debug_if = stq_uop_17_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_20_bp_xcpt_if = stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_18_bp_xcpt_if = stq_uop_17_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_20_debug_fsrc = stq_uop_17_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_debug_fsrc = stq_uop_17_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_17_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_20_debug_tsrc = stq_uop_17_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_18_debug_tsrc = stq_uop_17_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_18_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_21_inst = stq_uop_18_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_19_inst = stq_uop_18_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_18_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_21_debug_inst = stq_uop_18_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_19_debug_inst = stq_uop_18_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_rvc; // @[lsu.scala:252:32] wire s_uop_21_is_rvc = stq_uop_18_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_rvc = stq_uop_18_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_18_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_21_debug_pc = stq_uop_18_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_19_debug_pc = stq_uop_18_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_0; // @[lsu.scala:252:32] wire s_uop_21_iq_type_0 = stq_uop_18_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_0 = stq_uop_18_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_1; // @[lsu.scala:252:32] wire s_uop_21_iq_type_1 = stq_uop_18_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_1 = stq_uop_18_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_2; // @[lsu.scala:252:32] wire s_uop_21_iq_type_2 = stq_uop_18_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_2 = stq_uop_18_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iq_type_3; // @[lsu.scala:252:32] wire s_uop_21_iq_type_3 = stq_uop_18_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_19_iq_type_3 = stq_uop_18_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_0; // @[lsu.scala:252:32] wire s_uop_21_fu_code_0 = stq_uop_18_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_0 = stq_uop_18_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_1; // @[lsu.scala:252:32] wire s_uop_21_fu_code_1 = stq_uop_18_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_1 = stq_uop_18_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_2; // @[lsu.scala:252:32] wire s_uop_21_fu_code_2 = stq_uop_18_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_2 = stq_uop_18_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_3; // @[lsu.scala:252:32] wire s_uop_21_fu_code_3 = stq_uop_18_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_3 = stq_uop_18_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_4; // @[lsu.scala:252:32] wire s_uop_21_fu_code_4 = stq_uop_18_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_4 = stq_uop_18_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_5; // @[lsu.scala:252:32] wire s_uop_21_fu_code_5 = stq_uop_18_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_5 = stq_uop_18_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_6; // @[lsu.scala:252:32] wire s_uop_21_fu_code_6 = stq_uop_18_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_6 = stq_uop_18_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_7; // @[lsu.scala:252:32] wire s_uop_21_fu_code_7 = stq_uop_18_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_7 = stq_uop_18_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_8; // @[lsu.scala:252:32] wire s_uop_21_fu_code_8 = stq_uop_18_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_8 = stq_uop_18_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fu_code_9; // @[lsu.scala:252:32] wire s_uop_21_fu_code_9 = stq_uop_18_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_19_fu_code_9 = stq_uop_18_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued; // @[lsu.scala:252:32] wire s_uop_21_iw_issued = stq_uop_18_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued = stq_uop_18_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_21_iw_issued_partial_agen = stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued_partial_agen = stq_uop_18_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_21_iw_issued_partial_dgen = stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_issued_partial_dgen = stq_uop_18_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_21_iw_p1_speculative_child = stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_iw_p1_speculative_child = stq_uop_18_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_21_iw_p2_speculative_child = stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_iw_p2_speculative_child = stq_uop_18_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p1_bypass_hint = stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p1_bypass_hint = stq_uop_18_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p2_bypass_hint = stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p2_bypass_hint = stq_uop_18_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_21_iw_p3_bypass_hint = stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_19_iw_p3_bypass_hint = stq_uop_18_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_dis_col_sel = stq_uop_18_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_dis_col_sel = stq_uop_18_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_18_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_21_br_mask = stq_uop_18_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_19_br_mask = stq_uop_18_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_18_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_21_br_tag = stq_uop_18_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_19_br_tag = stq_uop_18_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_18_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_21_br_type = stq_uop_18_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_19_br_type = stq_uop_18_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sfb; // @[lsu.scala:252:32] wire s_uop_21_is_sfb = stq_uop_18_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sfb = stq_uop_18_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_fence; // @[lsu.scala:252:32] wire s_uop_21_is_fence = stq_uop_18_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_fence = stq_uop_18_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_fencei; // @[lsu.scala:252:32] wire s_uop_21_is_fencei = stq_uop_18_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_fencei = stq_uop_18_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sfence; // @[lsu.scala:252:32] wire s_uop_21_is_sfence = stq_uop_18_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sfence = stq_uop_18_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_amo; // @[lsu.scala:252:32] wire s_uop_21_is_amo = stq_uop_18_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_amo = stq_uop_18_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_eret; // @[lsu.scala:252:32] wire s_uop_21_is_eret = stq_uop_18_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_eret = stq_uop_18_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_21_is_sys_pc2epc = stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_sys_pc2epc = stq_uop_18_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_rocc; // @[lsu.scala:252:32] wire s_uop_21_is_rocc = stq_uop_18_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_rocc = stq_uop_18_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_mov; // @[lsu.scala:252:32] wire s_uop_21_is_mov = stq_uop_18_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_mov = stq_uop_18_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ftq_idx = stq_uop_18_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ftq_idx = stq_uop_18_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_edge_inst; // @[lsu.scala:252:32] wire s_uop_21_edge_inst = stq_uop_18_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_19_edge_inst = stq_uop_18_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_21_pc_lob = stq_uop_18_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_pc_lob = stq_uop_18_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_taken; // @[lsu.scala:252:32] wire s_uop_21_taken = stq_uop_18_taken; // @[lsu.scala:252:32, :1324:37] wire uop_19_taken = stq_uop_18_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_imm_rename; // @[lsu.scala:252:32] wire s_uop_21_imm_rename = stq_uop_18_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_19_imm_rename = stq_uop_18_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_imm_sel = stq_uop_18_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_imm_sel = stq_uop_18_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_21_pimm = stq_uop_18_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_pimm = stq_uop_18_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_18_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_21_imm_packed = stq_uop_18_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_19_imm_packed = stq_uop_18_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_21_op1_sel = stq_uop_18_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_op1_sel = stq_uop_18_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_21_op2_sel = stq_uop_18_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_op2_sel = stq_uop_18_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ldst = stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ldst = stq_uop_18_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_wen = stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_wen = stq_uop_18_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren1 = stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren1 = stq_uop_18_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren2 = stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren2 = stq_uop_18_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_ren3 = stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_ren3 = stq_uop_18_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_swap12 = stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_swap12 = stq_uop_18_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_swap23 = stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_swap23 = stq_uop_18_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_ctrl_typeTagIn = stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_ctrl_typeTagIn = stq_uop_18_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_ctrl_typeTagOut = stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_ctrl_typeTagOut = stq_uop_18_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fromint = stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fromint = stq_uop_18_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_toint = stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_toint = stq_uop_18_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fastpipe = stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fastpipe = stq_uop_18_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_fma = stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_fma = stq_uop_18_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_div = stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_div = stq_uop_18_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_sqrt = stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_sqrt = stq_uop_18_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_wflags = stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_wflags = stq_uop_18_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_21_fp_ctrl_vec = stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_ctrl_vec = stq_uop_18_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_21_rob_idx = stq_uop_18_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_rob_idx = stq_uop_18_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ldq_idx = stq_uop_18_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ldq_idx = stq_uop_18_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_21_stq_idx = stq_uop_18_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_stq_idx = stq_uop_18_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_21_rxq_idx = stq_uop_18_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_rxq_idx = stq_uop_18_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_21_pdst = stq_uop_18_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_pdst = stq_uop_18_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs1 = stq_uop_18_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs1 = stq_uop_18_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs2 = stq_uop_18_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs2 = stq_uop_18_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_21_prs3 = stq_uop_18_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_prs3 = stq_uop_18_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_21_ppred = stq_uop_18_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_ppred = stq_uop_18_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs1_busy; // @[lsu.scala:252:32] wire s_uop_21_prs1_busy = stq_uop_18_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs1_busy = stq_uop_18_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs2_busy; // @[lsu.scala:252:32] wire s_uop_21_prs2_busy = stq_uop_18_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs2_busy = stq_uop_18_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_prs3_busy; // @[lsu.scala:252:32] wire s_uop_21_prs3_busy = stq_uop_18_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_prs3_busy = stq_uop_18_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_ppred_busy; // @[lsu.scala:252:32] wire s_uop_21_ppred_busy = stq_uop_18_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_19_ppred_busy = stq_uop_18_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_18_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_21_stale_pdst = stq_uop_18_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_19_stale_pdst = stq_uop_18_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_exception; // @[lsu.scala:252:32] wire s_uop_21_exception = stq_uop_18_exception; // @[lsu.scala:252:32, :1324:37] wire uop_19_exception = stq_uop_18_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_18_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_21_exc_cause = stq_uop_18_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_19_exc_cause = stq_uop_18_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_21_mem_cmd = stq_uop_18_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_mem_cmd = stq_uop_18_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_21_mem_size = stq_uop_18_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_mem_size = stq_uop_18_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_mem_signed; // @[lsu.scala:252:32] wire s_uop_21_mem_signed = stq_uop_18_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_19_mem_signed = stq_uop_18_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_uses_ldq; // @[lsu.scala:252:32] wire s_uop_21_uses_ldq = stq_uop_18_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_19_uses_ldq = stq_uop_18_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_uses_stq; // @[lsu.scala:252:32] wire s_uop_21_uses_stq = stq_uop_18_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_19_uses_stq = stq_uop_18_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_is_unique; // @[lsu.scala:252:32] wire s_uop_21_is_unique = stq_uop_18_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_19_is_unique = stq_uop_18_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_21_flush_on_commit = stq_uop_18_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_19_flush_on_commit = stq_uop_18_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_21_csr_cmd = stq_uop_18_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_csr_cmd = stq_uop_18_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_21_ldst_is_rs1 = stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_19_ldst_is_rs1 = stq_uop_18_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_21_ldst = stq_uop_18_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_ldst = stq_uop_18_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs1 = stq_uop_18_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs1 = stq_uop_18_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs2 = stq_uop_18_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs2 = stq_uop_18_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_18_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_21_lrs3 = stq_uop_18_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_19_lrs3 = stq_uop_18_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_dst_rtype = stq_uop_18_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_dst_rtype = stq_uop_18_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_lrs1_rtype = stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_lrs1_rtype = stq_uop_18_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_21_lrs2_rtype = stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_lrs2_rtype = stq_uop_18_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_frs3_en; // @[lsu.scala:252:32] wire s_uop_21_frs3_en = stq_uop_18_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_19_frs3_en = stq_uop_18_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fcn_dw; // @[lsu.scala:252:32] wire s_uop_21_fcn_dw = stq_uop_18_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_19_fcn_dw = stq_uop_18_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_18_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_21_fcn_op = stq_uop_18_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_19_fcn_op = stq_uop_18_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_fp_val; // @[lsu.scala:252:32] wire s_uop_21_fp_val = stq_uop_18_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_19_fp_val = stq_uop_18_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_21_fp_rm = stq_uop_18_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_fp_rm = stq_uop_18_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_18_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_21_fp_typ = stq_uop_18_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_19_fp_typ = stq_uop_18_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_pf_if = stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_pf_if = stq_uop_18_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_ae_if = stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_ae_if = stq_uop_18_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_21_xcpt_ma_if = stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_xcpt_ma_if = stq_uop_18_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_21_bp_debug_if = stq_uop_18_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_bp_debug_if = stq_uop_18_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_21_bp_xcpt_if = stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_19_bp_xcpt_if = stq_uop_18_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_21_debug_fsrc = stq_uop_18_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_debug_fsrc = stq_uop_18_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_18_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_21_debug_tsrc = stq_uop_18_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_19_debug_tsrc = stq_uop_18_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_19_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_22_inst = stq_uop_19_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_20_inst = stq_uop_19_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_19_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_22_debug_inst = stq_uop_19_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_20_debug_inst = stq_uop_19_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_rvc; // @[lsu.scala:252:32] wire s_uop_22_is_rvc = stq_uop_19_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_rvc = stq_uop_19_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_19_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_22_debug_pc = stq_uop_19_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_20_debug_pc = stq_uop_19_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_0; // @[lsu.scala:252:32] wire s_uop_22_iq_type_0 = stq_uop_19_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_0 = stq_uop_19_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_1; // @[lsu.scala:252:32] wire s_uop_22_iq_type_1 = stq_uop_19_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_1 = stq_uop_19_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_2; // @[lsu.scala:252:32] wire s_uop_22_iq_type_2 = stq_uop_19_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_2 = stq_uop_19_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iq_type_3; // @[lsu.scala:252:32] wire s_uop_22_iq_type_3 = stq_uop_19_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_20_iq_type_3 = stq_uop_19_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_0; // @[lsu.scala:252:32] wire s_uop_22_fu_code_0 = stq_uop_19_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_0 = stq_uop_19_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_1; // @[lsu.scala:252:32] wire s_uop_22_fu_code_1 = stq_uop_19_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_1 = stq_uop_19_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_2; // @[lsu.scala:252:32] wire s_uop_22_fu_code_2 = stq_uop_19_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_2 = stq_uop_19_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_3; // @[lsu.scala:252:32] wire s_uop_22_fu_code_3 = stq_uop_19_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_3 = stq_uop_19_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_4; // @[lsu.scala:252:32] wire s_uop_22_fu_code_4 = stq_uop_19_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_4 = stq_uop_19_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_5; // @[lsu.scala:252:32] wire s_uop_22_fu_code_5 = stq_uop_19_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_5 = stq_uop_19_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_6; // @[lsu.scala:252:32] wire s_uop_22_fu_code_6 = stq_uop_19_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_6 = stq_uop_19_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_7; // @[lsu.scala:252:32] wire s_uop_22_fu_code_7 = stq_uop_19_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_7 = stq_uop_19_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_8; // @[lsu.scala:252:32] wire s_uop_22_fu_code_8 = stq_uop_19_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_8 = stq_uop_19_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fu_code_9; // @[lsu.scala:252:32] wire s_uop_22_fu_code_9 = stq_uop_19_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_20_fu_code_9 = stq_uop_19_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued; // @[lsu.scala:252:32] wire s_uop_22_iw_issued = stq_uop_19_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued = stq_uop_19_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_22_iw_issued_partial_agen = stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued_partial_agen = stq_uop_19_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_22_iw_issued_partial_dgen = stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_issued_partial_dgen = stq_uop_19_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_22_iw_p1_speculative_child = stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_iw_p1_speculative_child = stq_uop_19_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_22_iw_p2_speculative_child = stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_iw_p2_speculative_child = stq_uop_19_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p1_bypass_hint = stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p1_bypass_hint = stq_uop_19_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p2_bypass_hint = stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p2_bypass_hint = stq_uop_19_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_22_iw_p3_bypass_hint = stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_20_iw_p3_bypass_hint = stq_uop_19_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_dis_col_sel = stq_uop_19_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_dis_col_sel = stq_uop_19_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_19_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_22_br_mask = stq_uop_19_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_20_br_mask = stq_uop_19_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_19_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_22_br_tag = stq_uop_19_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_20_br_tag = stq_uop_19_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_19_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_22_br_type = stq_uop_19_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_20_br_type = stq_uop_19_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sfb; // @[lsu.scala:252:32] wire s_uop_22_is_sfb = stq_uop_19_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sfb = stq_uop_19_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_fence; // @[lsu.scala:252:32] wire s_uop_22_is_fence = stq_uop_19_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_fence = stq_uop_19_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_fencei; // @[lsu.scala:252:32] wire s_uop_22_is_fencei = stq_uop_19_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_fencei = stq_uop_19_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sfence; // @[lsu.scala:252:32] wire s_uop_22_is_sfence = stq_uop_19_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sfence = stq_uop_19_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_amo; // @[lsu.scala:252:32] wire s_uop_22_is_amo = stq_uop_19_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_amo = stq_uop_19_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_eret; // @[lsu.scala:252:32] wire s_uop_22_is_eret = stq_uop_19_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_eret = stq_uop_19_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_22_is_sys_pc2epc = stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_sys_pc2epc = stq_uop_19_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_rocc; // @[lsu.scala:252:32] wire s_uop_22_is_rocc = stq_uop_19_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_rocc = stq_uop_19_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_mov; // @[lsu.scala:252:32] wire s_uop_22_is_mov = stq_uop_19_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_mov = stq_uop_19_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ftq_idx = stq_uop_19_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ftq_idx = stq_uop_19_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_edge_inst; // @[lsu.scala:252:32] wire s_uop_22_edge_inst = stq_uop_19_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_20_edge_inst = stq_uop_19_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_22_pc_lob = stq_uop_19_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_pc_lob = stq_uop_19_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_taken; // @[lsu.scala:252:32] wire s_uop_22_taken = stq_uop_19_taken; // @[lsu.scala:252:32, :1324:37] wire uop_20_taken = stq_uop_19_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_imm_rename; // @[lsu.scala:252:32] wire s_uop_22_imm_rename = stq_uop_19_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_20_imm_rename = stq_uop_19_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_imm_sel = stq_uop_19_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_imm_sel = stq_uop_19_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_22_pimm = stq_uop_19_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_pimm = stq_uop_19_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_19_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_22_imm_packed = stq_uop_19_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_20_imm_packed = stq_uop_19_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_22_op1_sel = stq_uop_19_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_op1_sel = stq_uop_19_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_22_op2_sel = stq_uop_19_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_op2_sel = stq_uop_19_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ldst = stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ldst = stq_uop_19_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_wen = stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_wen = stq_uop_19_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren1 = stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren1 = stq_uop_19_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren2 = stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren2 = stq_uop_19_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_ren3 = stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_ren3 = stq_uop_19_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_swap12 = stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_swap12 = stq_uop_19_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_swap23 = stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_swap23 = stq_uop_19_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_ctrl_typeTagIn = stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_ctrl_typeTagIn = stq_uop_19_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_ctrl_typeTagOut = stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_ctrl_typeTagOut = stq_uop_19_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fromint = stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fromint = stq_uop_19_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_toint = stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_toint = stq_uop_19_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fastpipe = stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fastpipe = stq_uop_19_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_fma = stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_fma = stq_uop_19_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_div = stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_div = stq_uop_19_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_sqrt = stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_sqrt = stq_uop_19_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_wflags = stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_wflags = stq_uop_19_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_22_fp_ctrl_vec = stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_ctrl_vec = stq_uop_19_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_22_rob_idx = stq_uop_19_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_rob_idx = stq_uop_19_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ldq_idx = stq_uop_19_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ldq_idx = stq_uop_19_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_22_stq_idx = stq_uop_19_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_stq_idx = stq_uop_19_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_22_rxq_idx = stq_uop_19_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_rxq_idx = stq_uop_19_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_22_pdst = stq_uop_19_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_pdst = stq_uop_19_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs1 = stq_uop_19_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs1 = stq_uop_19_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs2 = stq_uop_19_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs2 = stq_uop_19_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_22_prs3 = stq_uop_19_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_prs3 = stq_uop_19_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_22_ppred = stq_uop_19_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_ppred = stq_uop_19_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs1_busy; // @[lsu.scala:252:32] wire s_uop_22_prs1_busy = stq_uop_19_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs1_busy = stq_uop_19_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs2_busy; // @[lsu.scala:252:32] wire s_uop_22_prs2_busy = stq_uop_19_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs2_busy = stq_uop_19_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_prs3_busy; // @[lsu.scala:252:32] wire s_uop_22_prs3_busy = stq_uop_19_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_prs3_busy = stq_uop_19_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_ppred_busy; // @[lsu.scala:252:32] wire s_uop_22_ppred_busy = stq_uop_19_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_20_ppred_busy = stq_uop_19_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_19_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_22_stale_pdst = stq_uop_19_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_20_stale_pdst = stq_uop_19_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_exception; // @[lsu.scala:252:32] wire s_uop_22_exception = stq_uop_19_exception; // @[lsu.scala:252:32, :1324:37] wire uop_20_exception = stq_uop_19_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_19_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_22_exc_cause = stq_uop_19_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_20_exc_cause = stq_uop_19_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_22_mem_cmd = stq_uop_19_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_mem_cmd = stq_uop_19_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_22_mem_size = stq_uop_19_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_mem_size = stq_uop_19_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_mem_signed; // @[lsu.scala:252:32] wire s_uop_22_mem_signed = stq_uop_19_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_20_mem_signed = stq_uop_19_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_uses_ldq; // @[lsu.scala:252:32] wire s_uop_22_uses_ldq = stq_uop_19_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_20_uses_ldq = stq_uop_19_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_uses_stq; // @[lsu.scala:252:32] wire s_uop_22_uses_stq = stq_uop_19_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_20_uses_stq = stq_uop_19_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_is_unique; // @[lsu.scala:252:32] wire s_uop_22_is_unique = stq_uop_19_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_20_is_unique = stq_uop_19_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_22_flush_on_commit = stq_uop_19_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_20_flush_on_commit = stq_uop_19_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_22_csr_cmd = stq_uop_19_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_csr_cmd = stq_uop_19_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_22_ldst_is_rs1 = stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_20_ldst_is_rs1 = stq_uop_19_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_22_ldst = stq_uop_19_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_ldst = stq_uop_19_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs1 = stq_uop_19_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs1 = stq_uop_19_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs2 = stq_uop_19_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs2 = stq_uop_19_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_19_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_22_lrs3 = stq_uop_19_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_20_lrs3 = stq_uop_19_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_dst_rtype = stq_uop_19_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_dst_rtype = stq_uop_19_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_lrs1_rtype = stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_lrs1_rtype = stq_uop_19_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_22_lrs2_rtype = stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_lrs2_rtype = stq_uop_19_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_frs3_en; // @[lsu.scala:252:32] wire s_uop_22_frs3_en = stq_uop_19_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_20_frs3_en = stq_uop_19_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fcn_dw; // @[lsu.scala:252:32] wire s_uop_22_fcn_dw = stq_uop_19_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_20_fcn_dw = stq_uop_19_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_19_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_22_fcn_op = stq_uop_19_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_20_fcn_op = stq_uop_19_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_fp_val; // @[lsu.scala:252:32] wire s_uop_22_fp_val = stq_uop_19_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_20_fp_val = stq_uop_19_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_22_fp_rm = stq_uop_19_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_fp_rm = stq_uop_19_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_19_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_22_fp_typ = stq_uop_19_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_20_fp_typ = stq_uop_19_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_pf_if = stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_pf_if = stq_uop_19_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_ae_if = stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_ae_if = stq_uop_19_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_22_xcpt_ma_if = stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_xcpt_ma_if = stq_uop_19_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_22_bp_debug_if = stq_uop_19_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_bp_debug_if = stq_uop_19_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_22_bp_xcpt_if = stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_20_bp_xcpt_if = stq_uop_19_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_22_debug_fsrc = stq_uop_19_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_debug_fsrc = stq_uop_19_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_19_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_22_debug_tsrc = stq_uop_19_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_20_debug_tsrc = stq_uop_19_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_20_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_23_inst = stq_uop_20_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_21_inst = stq_uop_20_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_20_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_23_debug_inst = stq_uop_20_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_21_debug_inst = stq_uop_20_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_rvc; // @[lsu.scala:252:32] wire s_uop_23_is_rvc = stq_uop_20_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_rvc = stq_uop_20_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_20_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_23_debug_pc = stq_uop_20_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_21_debug_pc = stq_uop_20_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_0; // @[lsu.scala:252:32] wire s_uop_23_iq_type_0 = stq_uop_20_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_0 = stq_uop_20_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_1; // @[lsu.scala:252:32] wire s_uop_23_iq_type_1 = stq_uop_20_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_1 = stq_uop_20_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_2; // @[lsu.scala:252:32] wire s_uop_23_iq_type_2 = stq_uop_20_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_2 = stq_uop_20_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iq_type_3; // @[lsu.scala:252:32] wire s_uop_23_iq_type_3 = stq_uop_20_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_21_iq_type_3 = stq_uop_20_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_0; // @[lsu.scala:252:32] wire s_uop_23_fu_code_0 = stq_uop_20_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_0 = stq_uop_20_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_1; // @[lsu.scala:252:32] wire s_uop_23_fu_code_1 = stq_uop_20_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_1 = stq_uop_20_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_2; // @[lsu.scala:252:32] wire s_uop_23_fu_code_2 = stq_uop_20_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_2 = stq_uop_20_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_3; // @[lsu.scala:252:32] wire s_uop_23_fu_code_3 = stq_uop_20_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_3 = stq_uop_20_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_4; // @[lsu.scala:252:32] wire s_uop_23_fu_code_4 = stq_uop_20_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_4 = stq_uop_20_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_5; // @[lsu.scala:252:32] wire s_uop_23_fu_code_5 = stq_uop_20_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_5 = stq_uop_20_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_6; // @[lsu.scala:252:32] wire s_uop_23_fu_code_6 = stq_uop_20_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_6 = stq_uop_20_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_7; // @[lsu.scala:252:32] wire s_uop_23_fu_code_7 = stq_uop_20_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_7 = stq_uop_20_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_8; // @[lsu.scala:252:32] wire s_uop_23_fu_code_8 = stq_uop_20_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_8 = stq_uop_20_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fu_code_9; // @[lsu.scala:252:32] wire s_uop_23_fu_code_9 = stq_uop_20_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_21_fu_code_9 = stq_uop_20_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued; // @[lsu.scala:252:32] wire s_uop_23_iw_issued = stq_uop_20_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued = stq_uop_20_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_23_iw_issued_partial_agen = stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued_partial_agen = stq_uop_20_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_23_iw_issued_partial_dgen = stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_issued_partial_dgen = stq_uop_20_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_23_iw_p1_speculative_child = stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_iw_p1_speculative_child = stq_uop_20_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_23_iw_p2_speculative_child = stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_iw_p2_speculative_child = stq_uop_20_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p1_bypass_hint = stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p1_bypass_hint = stq_uop_20_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p2_bypass_hint = stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p2_bypass_hint = stq_uop_20_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_23_iw_p3_bypass_hint = stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_21_iw_p3_bypass_hint = stq_uop_20_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_dis_col_sel = stq_uop_20_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_dis_col_sel = stq_uop_20_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_20_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_23_br_mask = stq_uop_20_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_21_br_mask = stq_uop_20_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_20_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_23_br_tag = stq_uop_20_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_21_br_tag = stq_uop_20_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_20_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_23_br_type = stq_uop_20_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_21_br_type = stq_uop_20_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sfb; // @[lsu.scala:252:32] wire s_uop_23_is_sfb = stq_uop_20_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sfb = stq_uop_20_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_fence; // @[lsu.scala:252:32] wire s_uop_23_is_fence = stq_uop_20_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_fence = stq_uop_20_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_fencei; // @[lsu.scala:252:32] wire s_uop_23_is_fencei = stq_uop_20_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_fencei = stq_uop_20_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sfence; // @[lsu.scala:252:32] wire s_uop_23_is_sfence = stq_uop_20_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sfence = stq_uop_20_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_amo; // @[lsu.scala:252:32] wire s_uop_23_is_amo = stq_uop_20_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_amo = stq_uop_20_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_eret; // @[lsu.scala:252:32] wire s_uop_23_is_eret = stq_uop_20_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_eret = stq_uop_20_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_23_is_sys_pc2epc = stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_sys_pc2epc = stq_uop_20_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_rocc; // @[lsu.scala:252:32] wire s_uop_23_is_rocc = stq_uop_20_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_rocc = stq_uop_20_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_mov; // @[lsu.scala:252:32] wire s_uop_23_is_mov = stq_uop_20_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_mov = stq_uop_20_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ftq_idx = stq_uop_20_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ftq_idx = stq_uop_20_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_edge_inst; // @[lsu.scala:252:32] wire s_uop_23_edge_inst = stq_uop_20_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_21_edge_inst = stq_uop_20_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_23_pc_lob = stq_uop_20_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_pc_lob = stq_uop_20_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_taken; // @[lsu.scala:252:32] wire s_uop_23_taken = stq_uop_20_taken; // @[lsu.scala:252:32, :1324:37] wire uop_21_taken = stq_uop_20_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_imm_rename; // @[lsu.scala:252:32] wire s_uop_23_imm_rename = stq_uop_20_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_21_imm_rename = stq_uop_20_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_imm_sel = stq_uop_20_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_imm_sel = stq_uop_20_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_23_pimm = stq_uop_20_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_pimm = stq_uop_20_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_20_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_23_imm_packed = stq_uop_20_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_21_imm_packed = stq_uop_20_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_23_op1_sel = stq_uop_20_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_op1_sel = stq_uop_20_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_23_op2_sel = stq_uop_20_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_op2_sel = stq_uop_20_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ldst = stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ldst = stq_uop_20_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_wen = stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_wen = stq_uop_20_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren1 = stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren1 = stq_uop_20_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren2 = stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren2 = stq_uop_20_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_ren3 = stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_ren3 = stq_uop_20_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_swap12 = stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_swap12 = stq_uop_20_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_swap23 = stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_swap23 = stq_uop_20_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_ctrl_typeTagIn = stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_ctrl_typeTagIn = stq_uop_20_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_ctrl_typeTagOut = stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_ctrl_typeTagOut = stq_uop_20_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fromint = stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fromint = stq_uop_20_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_toint = stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_toint = stq_uop_20_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fastpipe = stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fastpipe = stq_uop_20_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_fma = stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_fma = stq_uop_20_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_div = stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_div = stq_uop_20_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_sqrt = stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_sqrt = stq_uop_20_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_wflags = stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_wflags = stq_uop_20_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_23_fp_ctrl_vec = stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_ctrl_vec = stq_uop_20_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_23_rob_idx = stq_uop_20_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_rob_idx = stq_uop_20_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ldq_idx = stq_uop_20_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ldq_idx = stq_uop_20_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_23_stq_idx = stq_uop_20_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_stq_idx = stq_uop_20_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_23_rxq_idx = stq_uop_20_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_rxq_idx = stq_uop_20_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_23_pdst = stq_uop_20_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_pdst = stq_uop_20_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs1 = stq_uop_20_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs1 = stq_uop_20_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs2 = stq_uop_20_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs2 = stq_uop_20_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_23_prs3 = stq_uop_20_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_prs3 = stq_uop_20_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_23_ppred = stq_uop_20_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_ppred = stq_uop_20_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs1_busy; // @[lsu.scala:252:32] wire s_uop_23_prs1_busy = stq_uop_20_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs1_busy = stq_uop_20_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs2_busy; // @[lsu.scala:252:32] wire s_uop_23_prs2_busy = stq_uop_20_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs2_busy = stq_uop_20_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_prs3_busy; // @[lsu.scala:252:32] wire s_uop_23_prs3_busy = stq_uop_20_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_prs3_busy = stq_uop_20_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_ppred_busy; // @[lsu.scala:252:32] wire s_uop_23_ppred_busy = stq_uop_20_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_21_ppred_busy = stq_uop_20_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_20_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_23_stale_pdst = stq_uop_20_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_21_stale_pdst = stq_uop_20_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_exception; // @[lsu.scala:252:32] wire s_uop_23_exception = stq_uop_20_exception; // @[lsu.scala:252:32, :1324:37] wire uop_21_exception = stq_uop_20_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_20_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_23_exc_cause = stq_uop_20_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_21_exc_cause = stq_uop_20_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_23_mem_cmd = stq_uop_20_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_mem_cmd = stq_uop_20_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_23_mem_size = stq_uop_20_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_mem_size = stq_uop_20_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_mem_signed; // @[lsu.scala:252:32] wire s_uop_23_mem_signed = stq_uop_20_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_21_mem_signed = stq_uop_20_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_uses_ldq; // @[lsu.scala:252:32] wire s_uop_23_uses_ldq = stq_uop_20_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_21_uses_ldq = stq_uop_20_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_uses_stq; // @[lsu.scala:252:32] wire s_uop_23_uses_stq = stq_uop_20_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_21_uses_stq = stq_uop_20_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_is_unique; // @[lsu.scala:252:32] wire s_uop_23_is_unique = stq_uop_20_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_21_is_unique = stq_uop_20_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_23_flush_on_commit = stq_uop_20_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_21_flush_on_commit = stq_uop_20_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_23_csr_cmd = stq_uop_20_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_csr_cmd = stq_uop_20_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_23_ldst_is_rs1 = stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_21_ldst_is_rs1 = stq_uop_20_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_23_ldst = stq_uop_20_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_ldst = stq_uop_20_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs1 = stq_uop_20_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs1 = stq_uop_20_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs2 = stq_uop_20_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs2 = stq_uop_20_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_20_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_23_lrs3 = stq_uop_20_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_21_lrs3 = stq_uop_20_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_dst_rtype = stq_uop_20_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_dst_rtype = stq_uop_20_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_lrs1_rtype = stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_lrs1_rtype = stq_uop_20_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_23_lrs2_rtype = stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_lrs2_rtype = stq_uop_20_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_frs3_en; // @[lsu.scala:252:32] wire s_uop_23_frs3_en = stq_uop_20_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_21_frs3_en = stq_uop_20_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fcn_dw; // @[lsu.scala:252:32] wire s_uop_23_fcn_dw = stq_uop_20_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_21_fcn_dw = stq_uop_20_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_20_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_23_fcn_op = stq_uop_20_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_21_fcn_op = stq_uop_20_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_fp_val; // @[lsu.scala:252:32] wire s_uop_23_fp_val = stq_uop_20_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_21_fp_val = stq_uop_20_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_23_fp_rm = stq_uop_20_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_fp_rm = stq_uop_20_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_20_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_23_fp_typ = stq_uop_20_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_21_fp_typ = stq_uop_20_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_pf_if = stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_pf_if = stq_uop_20_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_ae_if = stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_ae_if = stq_uop_20_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_23_xcpt_ma_if = stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_xcpt_ma_if = stq_uop_20_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_23_bp_debug_if = stq_uop_20_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_bp_debug_if = stq_uop_20_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_23_bp_xcpt_if = stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_21_bp_xcpt_if = stq_uop_20_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_23_debug_fsrc = stq_uop_20_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_debug_fsrc = stq_uop_20_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_20_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_23_debug_tsrc = stq_uop_20_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_21_debug_tsrc = stq_uop_20_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_21_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_24_inst = stq_uop_21_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_22_inst = stq_uop_21_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_21_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_24_debug_inst = stq_uop_21_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_22_debug_inst = stq_uop_21_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_rvc; // @[lsu.scala:252:32] wire s_uop_24_is_rvc = stq_uop_21_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_rvc = stq_uop_21_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_21_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_24_debug_pc = stq_uop_21_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_22_debug_pc = stq_uop_21_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_0; // @[lsu.scala:252:32] wire s_uop_24_iq_type_0 = stq_uop_21_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_0 = stq_uop_21_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_1; // @[lsu.scala:252:32] wire s_uop_24_iq_type_1 = stq_uop_21_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_1 = stq_uop_21_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_2; // @[lsu.scala:252:32] wire s_uop_24_iq_type_2 = stq_uop_21_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_2 = stq_uop_21_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iq_type_3; // @[lsu.scala:252:32] wire s_uop_24_iq_type_3 = stq_uop_21_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_22_iq_type_3 = stq_uop_21_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_0; // @[lsu.scala:252:32] wire s_uop_24_fu_code_0 = stq_uop_21_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_0 = stq_uop_21_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_1; // @[lsu.scala:252:32] wire s_uop_24_fu_code_1 = stq_uop_21_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_1 = stq_uop_21_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_2; // @[lsu.scala:252:32] wire s_uop_24_fu_code_2 = stq_uop_21_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_2 = stq_uop_21_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_3; // @[lsu.scala:252:32] wire s_uop_24_fu_code_3 = stq_uop_21_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_3 = stq_uop_21_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_4; // @[lsu.scala:252:32] wire s_uop_24_fu_code_4 = stq_uop_21_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_4 = stq_uop_21_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_5; // @[lsu.scala:252:32] wire s_uop_24_fu_code_5 = stq_uop_21_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_5 = stq_uop_21_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_6; // @[lsu.scala:252:32] wire s_uop_24_fu_code_6 = stq_uop_21_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_6 = stq_uop_21_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_7; // @[lsu.scala:252:32] wire s_uop_24_fu_code_7 = stq_uop_21_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_7 = stq_uop_21_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_8; // @[lsu.scala:252:32] wire s_uop_24_fu_code_8 = stq_uop_21_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_8 = stq_uop_21_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fu_code_9; // @[lsu.scala:252:32] wire s_uop_24_fu_code_9 = stq_uop_21_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_22_fu_code_9 = stq_uop_21_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued; // @[lsu.scala:252:32] wire s_uop_24_iw_issued = stq_uop_21_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued = stq_uop_21_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_24_iw_issued_partial_agen = stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued_partial_agen = stq_uop_21_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_24_iw_issued_partial_dgen = stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_issued_partial_dgen = stq_uop_21_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_24_iw_p1_speculative_child = stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_iw_p1_speculative_child = stq_uop_21_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_24_iw_p2_speculative_child = stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_iw_p2_speculative_child = stq_uop_21_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p1_bypass_hint = stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p1_bypass_hint = stq_uop_21_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p2_bypass_hint = stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p2_bypass_hint = stq_uop_21_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_24_iw_p3_bypass_hint = stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_22_iw_p3_bypass_hint = stq_uop_21_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_dis_col_sel = stq_uop_21_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_dis_col_sel = stq_uop_21_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_21_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_24_br_mask = stq_uop_21_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_22_br_mask = stq_uop_21_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_21_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_24_br_tag = stq_uop_21_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_22_br_tag = stq_uop_21_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_21_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_24_br_type = stq_uop_21_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_22_br_type = stq_uop_21_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sfb; // @[lsu.scala:252:32] wire s_uop_24_is_sfb = stq_uop_21_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sfb = stq_uop_21_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_fence; // @[lsu.scala:252:32] wire s_uop_24_is_fence = stq_uop_21_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_fence = stq_uop_21_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_fencei; // @[lsu.scala:252:32] wire s_uop_24_is_fencei = stq_uop_21_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_fencei = stq_uop_21_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sfence; // @[lsu.scala:252:32] wire s_uop_24_is_sfence = stq_uop_21_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sfence = stq_uop_21_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_amo; // @[lsu.scala:252:32] wire s_uop_24_is_amo = stq_uop_21_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_amo = stq_uop_21_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_eret; // @[lsu.scala:252:32] wire s_uop_24_is_eret = stq_uop_21_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_eret = stq_uop_21_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_24_is_sys_pc2epc = stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_sys_pc2epc = stq_uop_21_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_rocc; // @[lsu.scala:252:32] wire s_uop_24_is_rocc = stq_uop_21_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_rocc = stq_uop_21_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_mov; // @[lsu.scala:252:32] wire s_uop_24_is_mov = stq_uop_21_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_mov = stq_uop_21_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ftq_idx = stq_uop_21_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ftq_idx = stq_uop_21_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_edge_inst; // @[lsu.scala:252:32] wire s_uop_24_edge_inst = stq_uop_21_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_22_edge_inst = stq_uop_21_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_24_pc_lob = stq_uop_21_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_pc_lob = stq_uop_21_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_taken; // @[lsu.scala:252:32] wire s_uop_24_taken = stq_uop_21_taken; // @[lsu.scala:252:32, :1324:37] wire uop_22_taken = stq_uop_21_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_imm_rename; // @[lsu.scala:252:32] wire s_uop_24_imm_rename = stq_uop_21_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_22_imm_rename = stq_uop_21_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_imm_sel = stq_uop_21_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_imm_sel = stq_uop_21_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_24_pimm = stq_uop_21_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_pimm = stq_uop_21_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_21_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_24_imm_packed = stq_uop_21_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_22_imm_packed = stq_uop_21_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_24_op1_sel = stq_uop_21_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_op1_sel = stq_uop_21_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_24_op2_sel = stq_uop_21_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_op2_sel = stq_uop_21_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ldst = stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ldst = stq_uop_21_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_wen = stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_wen = stq_uop_21_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren1 = stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren1 = stq_uop_21_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren2 = stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren2 = stq_uop_21_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_ren3 = stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_ren3 = stq_uop_21_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_swap12 = stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_swap12 = stq_uop_21_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_swap23 = stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_swap23 = stq_uop_21_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_ctrl_typeTagIn = stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_ctrl_typeTagIn = stq_uop_21_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_ctrl_typeTagOut = stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_ctrl_typeTagOut = stq_uop_21_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fromint = stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fromint = stq_uop_21_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_toint = stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_toint = stq_uop_21_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fastpipe = stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fastpipe = stq_uop_21_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_fma = stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_fma = stq_uop_21_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_div = stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_div = stq_uop_21_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_sqrt = stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_sqrt = stq_uop_21_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_wflags = stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_wflags = stq_uop_21_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_24_fp_ctrl_vec = stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_ctrl_vec = stq_uop_21_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_24_rob_idx = stq_uop_21_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_rob_idx = stq_uop_21_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ldq_idx = stq_uop_21_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ldq_idx = stq_uop_21_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_24_stq_idx = stq_uop_21_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_stq_idx = stq_uop_21_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_24_rxq_idx = stq_uop_21_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_rxq_idx = stq_uop_21_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_24_pdst = stq_uop_21_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_pdst = stq_uop_21_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs1 = stq_uop_21_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs1 = stq_uop_21_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs2 = stq_uop_21_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs2 = stq_uop_21_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_24_prs3 = stq_uop_21_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_prs3 = stq_uop_21_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_24_ppred = stq_uop_21_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_ppred = stq_uop_21_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs1_busy; // @[lsu.scala:252:32] wire s_uop_24_prs1_busy = stq_uop_21_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs1_busy = stq_uop_21_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs2_busy; // @[lsu.scala:252:32] wire s_uop_24_prs2_busy = stq_uop_21_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs2_busy = stq_uop_21_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_prs3_busy; // @[lsu.scala:252:32] wire s_uop_24_prs3_busy = stq_uop_21_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_prs3_busy = stq_uop_21_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_ppred_busy; // @[lsu.scala:252:32] wire s_uop_24_ppred_busy = stq_uop_21_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_22_ppred_busy = stq_uop_21_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_21_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_24_stale_pdst = stq_uop_21_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_22_stale_pdst = stq_uop_21_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_exception; // @[lsu.scala:252:32] wire s_uop_24_exception = stq_uop_21_exception; // @[lsu.scala:252:32, :1324:37] wire uop_22_exception = stq_uop_21_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_21_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_24_exc_cause = stq_uop_21_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_22_exc_cause = stq_uop_21_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_24_mem_cmd = stq_uop_21_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_mem_cmd = stq_uop_21_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_24_mem_size = stq_uop_21_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_mem_size = stq_uop_21_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_mem_signed; // @[lsu.scala:252:32] wire s_uop_24_mem_signed = stq_uop_21_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_22_mem_signed = stq_uop_21_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_uses_ldq; // @[lsu.scala:252:32] wire s_uop_24_uses_ldq = stq_uop_21_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_22_uses_ldq = stq_uop_21_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_uses_stq; // @[lsu.scala:252:32] wire s_uop_24_uses_stq = stq_uop_21_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_22_uses_stq = stq_uop_21_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_is_unique; // @[lsu.scala:252:32] wire s_uop_24_is_unique = stq_uop_21_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_22_is_unique = stq_uop_21_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_24_flush_on_commit = stq_uop_21_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_22_flush_on_commit = stq_uop_21_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_24_csr_cmd = stq_uop_21_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_csr_cmd = stq_uop_21_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_24_ldst_is_rs1 = stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_22_ldst_is_rs1 = stq_uop_21_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_24_ldst = stq_uop_21_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_ldst = stq_uop_21_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs1 = stq_uop_21_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs1 = stq_uop_21_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs2 = stq_uop_21_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs2 = stq_uop_21_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_21_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_24_lrs3 = stq_uop_21_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_22_lrs3 = stq_uop_21_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_dst_rtype = stq_uop_21_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_dst_rtype = stq_uop_21_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_lrs1_rtype = stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_lrs1_rtype = stq_uop_21_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_24_lrs2_rtype = stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_lrs2_rtype = stq_uop_21_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_frs3_en; // @[lsu.scala:252:32] wire s_uop_24_frs3_en = stq_uop_21_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_22_frs3_en = stq_uop_21_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fcn_dw; // @[lsu.scala:252:32] wire s_uop_24_fcn_dw = stq_uop_21_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_22_fcn_dw = stq_uop_21_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_21_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_24_fcn_op = stq_uop_21_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_22_fcn_op = stq_uop_21_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_fp_val; // @[lsu.scala:252:32] wire s_uop_24_fp_val = stq_uop_21_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_22_fp_val = stq_uop_21_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_24_fp_rm = stq_uop_21_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_fp_rm = stq_uop_21_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_21_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_24_fp_typ = stq_uop_21_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_22_fp_typ = stq_uop_21_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_pf_if = stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_pf_if = stq_uop_21_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_ae_if = stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_ae_if = stq_uop_21_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_24_xcpt_ma_if = stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_xcpt_ma_if = stq_uop_21_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_24_bp_debug_if = stq_uop_21_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_bp_debug_if = stq_uop_21_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_24_bp_xcpt_if = stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_22_bp_xcpt_if = stq_uop_21_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_24_debug_fsrc = stq_uop_21_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_debug_fsrc = stq_uop_21_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_21_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_24_debug_tsrc = stq_uop_21_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_22_debug_tsrc = stq_uop_21_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_22_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_25_inst = stq_uop_22_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_23_inst = stq_uop_22_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_22_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_25_debug_inst = stq_uop_22_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_23_debug_inst = stq_uop_22_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_rvc; // @[lsu.scala:252:32] wire s_uop_25_is_rvc = stq_uop_22_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_rvc = stq_uop_22_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_22_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_25_debug_pc = stq_uop_22_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_23_debug_pc = stq_uop_22_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_0; // @[lsu.scala:252:32] wire s_uop_25_iq_type_0 = stq_uop_22_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_0 = stq_uop_22_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_1; // @[lsu.scala:252:32] wire s_uop_25_iq_type_1 = stq_uop_22_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_1 = stq_uop_22_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_2; // @[lsu.scala:252:32] wire s_uop_25_iq_type_2 = stq_uop_22_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_2 = stq_uop_22_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iq_type_3; // @[lsu.scala:252:32] wire s_uop_25_iq_type_3 = stq_uop_22_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_23_iq_type_3 = stq_uop_22_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_0; // @[lsu.scala:252:32] wire s_uop_25_fu_code_0 = stq_uop_22_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_0 = stq_uop_22_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_1; // @[lsu.scala:252:32] wire s_uop_25_fu_code_1 = stq_uop_22_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_1 = stq_uop_22_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_2; // @[lsu.scala:252:32] wire s_uop_25_fu_code_2 = stq_uop_22_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_2 = stq_uop_22_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_3; // @[lsu.scala:252:32] wire s_uop_25_fu_code_3 = stq_uop_22_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_3 = stq_uop_22_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_4; // @[lsu.scala:252:32] wire s_uop_25_fu_code_4 = stq_uop_22_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_4 = stq_uop_22_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_5; // @[lsu.scala:252:32] wire s_uop_25_fu_code_5 = stq_uop_22_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_5 = stq_uop_22_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_6; // @[lsu.scala:252:32] wire s_uop_25_fu_code_6 = stq_uop_22_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_6 = stq_uop_22_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_7; // @[lsu.scala:252:32] wire s_uop_25_fu_code_7 = stq_uop_22_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_7 = stq_uop_22_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_8; // @[lsu.scala:252:32] wire s_uop_25_fu_code_8 = stq_uop_22_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_8 = stq_uop_22_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fu_code_9; // @[lsu.scala:252:32] wire s_uop_25_fu_code_9 = stq_uop_22_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_23_fu_code_9 = stq_uop_22_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued; // @[lsu.scala:252:32] wire s_uop_25_iw_issued = stq_uop_22_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued = stq_uop_22_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_25_iw_issued_partial_agen = stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued_partial_agen = stq_uop_22_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_25_iw_issued_partial_dgen = stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_issued_partial_dgen = stq_uop_22_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_25_iw_p1_speculative_child = stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_iw_p1_speculative_child = stq_uop_22_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_25_iw_p2_speculative_child = stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_iw_p2_speculative_child = stq_uop_22_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p1_bypass_hint = stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p1_bypass_hint = stq_uop_22_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p2_bypass_hint = stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p2_bypass_hint = stq_uop_22_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_25_iw_p3_bypass_hint = stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_23_iw_p3_bypass_hint = stq_uop_22_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_dis_col_sel = stq_uop_22_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_dis_col_sel = stq_uop_22_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_22_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_25_br_mask = stq_uop_22_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_23_br_mask = stq_uop_22_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_22_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_25_br_tag = stq_uop_22_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_23_br_tag = stq_uop_22_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_22_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_25_br_type = stq_uop_22_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_23_br_type = stq_uop_22_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sfb; // @[lsu.scala:252:32] wire s_uop_25_is_sfb = stq_uop_22_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sfb = stq_uop_22_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_fence; // @[lsu.scala:252:32] wire s_uop_25_is_fence = stq_uop_22_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_fence = stq_uop_22_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_fencei; // @[lsu.scala:252:32] wire s_uop_25_is_fencei = stq_uop_22_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_fencei = stq_uop_22_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sfence; // @[lsu.scala:252:32] wire s_uop_25_is_sfence = stq_uop_22_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sfence = stq_uop_22_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_amo; // @[lsu.scala:252:32] wire s_uop_25_is_amo = stq_uop_22_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_amo = stq_uop_22_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_eret; // @[lsu.scala:252:32] wire s_uop_25_is_eret = stq_uop_22_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_eret = stq_uop_22_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_25_is_sys_pc2epc = stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_sys_pc2epc = stq_uop_22_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_rocc; // @[lsu.scala:252:32] wire s_uop_25_is_rocc = stq_uop_22_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_rocc = stq_uop_22_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_mov; // @[lsu.scala:252:32] wire s_uop_25_is_mov = stq_uop_22_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_mov = stq_uop_22_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ftq_idx = stq_uop_22_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ftq_idx = stq_uop_22_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_edge_inst; // @[lsu.scala:252:32] wire s_uop_25_edge_inst = stq_uop_22_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_23_edge_inst = stq_uop_22_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_25_pc_lob = stq_uop_22_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_pc_lob = stq_uop_22_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_taken; // @[lsu.scala:252:32] wire s_uop_25_taken = stq_uop_22_taken; // @[lsu.scala:252:32, :1324:37] wire uop_23_taken = stq_uop_22_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_imm_rename; // @[lsu.scala:252:32] wire s_uop_25_imm_rename = stq_uop_22_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_23_imm_rename = stq_uop_22_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_imm_sel = stq_uop_22_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_imm_sel = stq_uop_22_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_25_pimm = stq_uop_22_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_pimm = stq_uop_22_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_22_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_25_imm_packed = stq_uop_22_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_23_imm_packed = stq_uop_22_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_25_op1_sel = stq_uop_22_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_op1_sel = stq_uop_22_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_25_op2_sel = stq_uop_22_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_op2_sel = stq_uop_22_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ldst = stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ldst = stq_uop_22_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_wen = stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_wen = stq_uop_22_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren1 = stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren1 = stq_uop_22_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren2 = stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren2 = stq_uop_22_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_ren3 = stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_ren3 = stq_uop_22_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_swap12 = stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_swap12 = stq_uop_22_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_swap23 = stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_swap23 = stq_uop_22_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_ctrl_typeTagIn = stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_ctrl_typeTagIn = stq_uop_22_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_ctrl_typeTagOut = stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_ctrl_typeTagOut = stq_uop_22_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fromint = stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fromint = stq_uop_22_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_toint = stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_toint = stq_uop_22_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fastpipe = stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fastpipe = stq_uop_22_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_fma = stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_fma = stq_uop_22_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_div = stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_div = stq_uop_22_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_sqrt = stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_sqrt = stq_uop_22_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_wflags = stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_wflags = stq_uop_22_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_25_fp_ctrl_vec = stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_ctrl_vec = stq_uop_22_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_25_rob_idx = stq_uop_22_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_rob_idx = stq_uop_22_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ldq_idx = stq_uop_22_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ldq_idx = stq_uop_22_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_25_stq_idx = stq_uop_22_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_stq_idx = stq_uop_22_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_25_rxq_idx = stq_uop_22_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_rxq_idx = stq_uop_22_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_25_pdst = stq_uop_22_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_pdst = stq_uop_22_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs1 = stq_uop_22_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs1 = stq_uop_22_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs2 = stq_uop_22_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs2 = stq_uop_22_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_25_prs3 = stq_uop_22_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_prs3 = stq_uop_22_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_25_ppred = stq_uop_22_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_ppred = stq_uop_22_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs1_busy; // @[lsu.scala:252:32] wire s_uop_25_prs1_busy = stq_uop_22_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs1_busy = stq_uop_22_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs2_busy; // @[lsu.scala:252:32] wire s_uop_25_prs2_busy = stq_uop_22_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs2_busy = stq_uop_22_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_prs3_busy; // @[lsu.scala:252:32] wire s_uop_25_prs3_busy = stq_uop_22_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_prs3_busy = stq_uop_22_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_ppred_busy; // @[lsu.scala:252:32] wire s_uop_25_ppred_busy = stq_uop_22_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_23_ppred_busy = stq_uop_22_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_22_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_25_stale_pdst = stq_uop_22_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_23_stale_pdst = stq_uop_22_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_exception; // @[lsu.scala:252:32] wire s_uop_25_exception = stq_uop_22_exception; // @[lsu.scala:252:32, :1324:37] wire uop_23_exception = stq_uop_22_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_22_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_25_exc_cause = stq_uop_22_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_23_exc_cause = stq_uop_22_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_25_mem_cmd = stq_uop_22_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_mem_cmd = stq_uop_22_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_25_mem_size = stq_uop_22_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_mem_size = stq_uop_22_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_mem_signed; // @[lsu.scala:252:32] wire s_uop_25_mem_signed = stq_uop_22_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_23_mem_signed = stq_uop_22_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_uses_ldq; // @[lsu.scala:252:32] wire s_uop_25_uses_ldq = stq_uop_22_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_23_uses_ldq = stq_uop_22_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_uses_stq; // @[lsu.scala:252:32] wire s_uop_25_uses_stq = stq_uop_22_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_23_uses_stq = stq_uop_22_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_is_unique; // @[lsu.scala:252:32] wire s_uop_25_is_unique = stq_uop_22_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_23_is_unique = stq_uop_22_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_25_flush_on_commit = stq_uop_22_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_23_flush_on_commit = stq_uop_22_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_25_csr_cmd = stq_uop_22_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_csr_cmd = stq_uop_22_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_25_ldst_is_rs1 = stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_23_ldst_is_rs1 = stq_uop_22_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_25_ldst = stq_uop_22_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_ldst = stq_uop_22_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs1 = stq_uop_22_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs1 = stq_uop_22_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs2 = stq_uop_22_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs2 = stq_uop_22_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_22_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_25_lrs3 = stq_uop_22_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_23_lrs3 = stq_uop_22_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_dst_rtype = stq_uop_22_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_dst_rtype = stq_uop_22_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_lrs1_rtype = stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_lrs1_rtype = stq_uop_22_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_25_lrs2_rtype = stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_lrs2_rtype = stq_uop_22_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_frs3_en; // @[lsu.scala:252:32] wire s_uop_25_frs3_en = stq_uop_22_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_23_frs3_en = stq_uop_22_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fcn_dw; // @[lsu.scala:252:32] wire s_uop_25_fcn_dw = stq_uop_22_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_23_fcn_dw = stq_uop_22_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_22_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_25_fcn_op = stq_uop_22_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_23_fcn_op = stq_uop_22_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_fp_val; // @[lsu.scala:252:32] wire s_uop_25_fp_val = stq_uop_22_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_23_fp_val = stq_uop_22_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_25_fp_rm = stq_uop_22_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_fp_rm = stq_uop_22_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_22_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_25_fp_typ = stq_uop_22_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_23_fp_typ = stq_uop_22_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_pf_if = stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_pf_if = stq_uop_22_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_ae_if = stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_ae_if = stq_uop_22_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_25_xcpt_ma_if = stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_xcpt_ma_if = stq_uop_22_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_25_bp_debug_if = stq_uop_22_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_bp_debug_if = stq_uop_22_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_25_bp_xcpt_if = stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_23_bp_xcpt_if = stq_uop_22_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_25_debug_fsrc = stq_uop_22_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_debug_fsrc = stq_uop_22_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_22_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_25_debug_tsrc = stq_uop_22_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_23_debug_tsrc = stq_uop_22_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_23_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_26_inst = stq_uop_23_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_24_inst = stq_uop_23_inst; // @[lsu.scala:252:32, :1678:25] reg [31:0] stq_uop_23_debug_inst; // @[lsu.scala:252:32] wire [31:0] s_uop_26_debug_inst = stq_uop_23_debug_inst; // @[lsu.scala:252:32, :1324:37] wire [31:0] uop_24_debug_inst = stq_uop_23_debug_inst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_rvc; // @[lsu.scala:252:32] wire s_uop_26_is_rvc = stq_uop_23_is_rvc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_rvc = stq_uop_23_is_rvc; // @[lsu.scala:252:32, :1678:25] reg [39:0] stq_uop_23_debug_pc; // @[lsu.scala:252:32] wire [39:0] s_uop_26_debug_pc = stq_uop_23_debug_pc; // @[lsu.scala:252:32, :1324:37] wire [39:0] uop_24_debug_pc = stq_uop_23_debug_pc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_0; // @[lsu.scala:252:32] wire s_uop_26_iq_type_0 = stq_uop_23_iq_type_0; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_0 = stq_uop_23_iq_type_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_1; // @[lsu.scala:252:32] wire s_uop_26_iq_type_1 = stq_uop_23_iq_type_1; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_1 = stq_uop_23_iq_type_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_2; // @[lsu.scala:252:32] wire s_uop_26_iq_type_2 = stq_uop_23_iq_type_2; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_2 = stq_uop_23_iq_type_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iq_type_3; // @[lsu.scala:252:32] wire s_uop_26_iq_type_3 = stq_uop_23_iq_type_3; // @[lsu.scala:252:32, :1324:37] wire uop_24_iq_type_3 = stq_uop_23_iq_type_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_0; // @[lsu.scala:252:32] wire s_uop_26_fu_code_0 = stq_uop_23_fu_code_0; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_0 = stq_uop_23_fu_code_0; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_1; // @[lsu.scala:252:32] wire s_uop_26_fu_code_1 = stq_uop_23_fu_code_1; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_1 = stq_uop_23_fu_code_1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_2; // @[lsu.scala:252:32] wire s_uop_26_fu_code_2 = stq_uop_23_fu_code_2; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_2 = stq_uop_23_fu_code_2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_3; // @[lsu.scala:252:32] wire s_uop_26_fu_code_3 = stq_uop_23_fu_code_3; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_3 = stq_uop_23_fu_code_3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_4; // @[lsu.scala:252:32] wire s_uop_26_fu_code_4 = stq_uop_23_fu_code_4; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_4 = stq_uop_23_fu_code_4; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_5; // @[lsu.scala:252:32] wire s_uop_26_fu_code_5 = stq_uop_23_fu_code_5; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_5 = stq_uop_23_fu_code_5; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_6; // @[lsu.scala:252:32] wire s_uop_26_fu_code_6 = stq_uop_23_fu_code_6; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_6 = stq_uop_23_fu_code_6; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_7; // @[lsu.scala:252:32] wire s_uop_26_fu_code_7 = stq_uop_23_fu_code_7; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_7 = stq_uop_23_fu_code_7; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_8; // @[lsu.scala:252:32] wire s_uop_26_fu_code_8 = stq_uop_23_fu_code_8; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_8 = stq_uop_23_fu_code_8; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fu_code_9; // @[lsu.scala:252:32] wire s_uop_26_fu_code_9 = stq_uop_23_fu_code_9; // @[lsu.scala:252:32, :1324:37] wire uop_24_fu_code_9 = stq_uop_23_fu_code_9; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued; // @[lsu.scala:252:32] wire s_uop_26_iw_issued = stq_uop_23_iw_issued; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued = stq_uop_23_iw_issued; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32] wire s_uop_26_iw_issued_partial_agen = stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued_partial_agen = stq_uop_23_iw_issued_partial_agen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32] wire s_uop_26_iw_issued_partial_dgen = stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_issued_partial_dgen = stq_uop_23_iw_issued_partial_dgen; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_26_iw_p1_speculative_child = stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_iw_p1_speculative_child = stq_uop_23_iw_p1_speculative_child; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32] wire [2:0] s_uop_26_iw_p2_speculative_child = stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_iw_p2_speculative_child = stq_uop_23_iw_p2_speculative_child; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p1_bypass_hint = stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p1_bypass_hint = stq_uop_23_iw_p1_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p2_bypass_hint = stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p2_bypass_hint = stq_uop_23_iw_p2_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32] wire s_uop_26_iw_p3_bypass_hint = stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1324:37] wire uop_24_iw_p3_bypass_hint = stq_uop_23_iw_p3_bypass_hint; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_dis_col_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_dis_col_sel = stq_uop_23_dis_col_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_dis_col_sel = stq_uop_23_dis_col_sel; // @[lsu.scala:252:32, :1678:25] reg [15:0] stq_uop_23_br_mask; // @[lsu.scala:252:32] wire [15:0] s_uop_26_br_mask = stq_uop_23_br_mask; // @[lsu.scala:252:32, :1324:37] wire [15:0] uop_24_br_mask = stq_uop_23_br_mask; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_23_br_tag; // @[lsu.scala:252:32] wire [3:0] s_uop_26_br_tag = stq_uop_23_br_tag; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_24_br_tag = stq_uop_23_br_tag; // @[lsu.scala:252:32, :1678:25] reg [3:0] stq_uop_23_br_type; // @[lsu.scala:252:32] wire [3:0] s_uop_26_br_type = stq_uop_23_br_type; // @[lsu.scala:252:32, :1324:37] wire [3:0] uop_24_br_type = stq_uop_23_br_type; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sfb; // @[lsu.scala:252:32] wire s_uop_26_is_sfb = stq_uop_23_is_sfb; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sfb = stq_uop_23_is_sfb; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_fence; // @[lsu.scala:252:32] wire s_uop_26_is_fence = stq_uop_23_is_fence; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_fence = stq_uop_23_is_fence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_fencei; // @[lsu.scala:252:32] wire s_uop_26_is_fencei = stq_uop_23_is_fencei; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_fencei = stq_uop_23_is_fencei; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sfence; // @[lsu.scala:252:32] wire s_uop_26_is_sfence = stq_uop_23_is_sfence; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sfence = stq_uop_23_is_sfence; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_amo; // @[lsu.scala:252:32] wire s_uop_26_is_amo = stq_uop_23_is_amo; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_amo = stq_uop_23_is_amo; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_eret; // @[lsu.scala:252:32] wire s_uop_26_is_eret = stq_uop_23_is_eret; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_eret = stq_uop_23_is_eret; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32] wire s_uop_26_is_sys_pc2epc = stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_sys_pc2epc = stq_uop_23_is_sys_pc2epc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_rocc; // @[lsu.scala:252:32] wire s_uop_26_is_rocc = stq_uop_23_is_rocc; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_rocc = stq_uop_23_is_rocc; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_mov; // @[lsu.scala:252:32] wire s_uop_26_is_mov = stq_uop_23_is_mov; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_mov = stq_uop_23_is_mov; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ftq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ftq_idx = stq_uop_23_ftq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ftq_idx = stq_uop_23_ftq_idx; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_edge_inst; // @[lsu.scala:252:32] wire s_uop_26_edge_inst = stq_uop_23_edge_inst; // @[lsu.scala:252:32, :1324:37] wire uop_24_edge_inst = stq_uop_23_edge_inst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_pc_lob; // @[lsu.scala:252:32] wire [5:0] s_uop_26_pc_lob = stq_uop_23_pc_lob; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_pc_lob = stq_uop_23_pc_lob; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_taken; // @[lsu.scala:252:32] wire s_uop_26_taken = stq_uop_23_taken; // @[lsu.scala:252:32, :1324:37] wire uop_24_taken = stq_uop_23_taken; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_imm_rename; // @[lsu.scala:252:32] wire s_uop_26_imm_rename = stq_uop_23_imm_rename; // @[lsu.scala:252:32, :1324:37] wire uop_24_imm_rename = stq_uop_23_imm_rename; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_imm_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_imm_sel = stq_uop_23_imm_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_imm_sel = stq_uop_23_imm_sel; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_pimm; // @[lsu.scala:252:32] wire [4:0] s_uop_26_pimm = stq_uop_23_pimm; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_pimm = stq_uop_23_pimm; // @[lsu.scala:252:32, :1678:25] reg [19:0] stq_uop_23_imm_packed; // @[lsu.scala:252:32] wire [19:0] s_uop_26_imm_packed = stq_uop_23_imm_packed; // @[lsu.scala:252:32, :1324:37] wire [19:0] uop_24_imm_packed = stq_uop_23_imm_packed; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_op1_sel; // @[lsu.scala:252:32] wire [1:0] s_uop_26_op1_sel = stq_uop_23_op1_sel; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_op1_sel = stq_uop_23_op1_sel; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_op2_sel; // @[lsu.scala:252:32] wire [2:0] s_uop_26_op2_sel = stq_uop_23_op2_sel; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_op2_sel = stq_uop_23_op2_sel; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ldst = stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ldst = stq_uop_23_fp_ctrl_ldst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_wen = stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_wen = stq_uop_23_fp_ctrl_wen; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren1 = stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren1 = stq_uop_23_fp_ctrl_ren1; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren2 = stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren2 = stq_uop_23_fp_ctrl_ren2; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_ren3 = stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_ren3 = stq_uop_23_fp_ctrl_ren3; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_swap12 = stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_swap12 = stq_uop_23_fp_ctrl_swap12; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_swap23 = stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_swap23 = stq_uop_23_fp_ctrl_swap23; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_ctrl_typeTagIn = stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_ctrl_typeTagIn = stq_uop_23_fp_ctrl_typeTagIn; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_ctrl_typeTagOut = stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_ctrl_typeTagOut = stq_uop_23_fp_ctrl_typeTagOut; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fromint = stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fromint = stq_uop_23_fp_ctrl_fromint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_toint = stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_toint = stq_uop_23_fp_ctrl_toint; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fastpipe = stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fastpipe = stq_uop_23_fp_ctrl_fastpipe; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_fma = stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_fma = stq_uop_23_fp_ctrl_fma; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_div = stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_div = stq_uop_23_fp_ctrl_div; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_sqrt = stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_sqrt = stq_uop_23_fp_ctrl_sqrt; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_wflags = stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_wflags = stq_uop_23_fp_ctrl_wflags; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32] wire s_uop_26_fp_ctrl_vec = stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_ctrl_vec = stq_uop_23_fp_ctrl_vec; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_rob_idx; // @[lsu.scala:252:32] wire [6:0] s_uop_26_rob_idx = stq_uop_23_rob_idx; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_rob_idx = stq_uop_23_rob_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ldq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ldq_idx = stq_uop_23_ldq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ldq_idx = stq_uop_23_ldq_idx; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_stq_idx; // @[lsu.scala:252:32] wire [4:0] s_uop_26_stq_idx = stq_uop_23_stq_idx; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_stq_idx = stq_uop_23_stq_idx; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_rxq_idx; // @[lsu.scala:252:32] wire [1:0] s_uop_26_rxq_idx = stq_uop_23_rxq_idx; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_rxq_idx = stq_uop_23_rxq_idx; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_26_pdst = stq_uop_23_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_pdst = stq_uop_23_pdst; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs1; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs1 = stq_uop_23_prs1; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs1 = stq_uop_23_prs1; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs2; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs2 = stq_uop_23_prs2; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs2 = stq_uop_23_prs2; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_prs3; // @[lsu.scala:252:32] wire [6:0] s_uop_26_prs3 = stq_uop_23_prs3; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_prs3 = stq_uop_23_prs3; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_ppred; // @[lsu.scala:252:32] wire [4:0] s_uop_26_ppred = stq_uop_23_ppred; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_ppred = stq_uop_23_ppred; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs1_busy; // @[lsu.scala:252:32] wire s_uop_26_prs1_busy = stq_uop_23_prs1_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs1_busy = stq_uop_23_prs1_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs2_busy; // @[lsu.scala:252:32] wire s_uop_26_prs2_busy = stq_uop_23_prs2_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs2_busy = stq_uop_23_prs2_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_prs3_busy; // @[lsu.scala:252:32] wire s_uop_26_prs3_busy = stq_uop_23_prs3_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_prs3_busy = stq_uop_23_prs3_busy; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_ppred_busy; // @[lsu.scala:252:32] wire s_uop_26_ppred_busy = stq_uop_23_ppred_busy; // @[lsu.scala:252:32, :1324:37] wire uop_24_ppred_busy = stq_uop_23_ppred_busy; // @[lsu.scala:252:32, :1678:25] reg [6:0] stq_uop_23_stale_pdst; // @[lsu.scala:252:32] wire [6:0] s_uop_26_stale_pdst = stq_uop_23_stale_pdst; // @[lsu.scala:252:32, :1324:37] wire [6:0] uop_24_stale_pdst = stq_uop_23_stale_pdst; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_exception; // @[lsu.scala:252:32] wire s_uop_26_exception = stq_uop_23_exception; // @[lsu.scala:252:32, :1324:37] wire uop_24_exception = stq_uop_23_exception; // @[lsu.scala:252:32, :1678:25] reg [63:0] stq_uop_23_exc_cause; // @[lsu.scala:252:32] wire [63:0] s_uop_26_exc_cause = stq_uop_23_exc_cause; // @[lsu.scala:252:32, :1324:37] wire [63:0] uop_24_exc_cause = stq_uop_23_exc_cause; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_mem_cmd; // @[lsu.scala:252:32] wire [4:0] s_uop_26_mem_cmd = stq_uop_23_mem_cmd; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_mem_cmd = stq_uop_23_mem_cmd; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_mem_size; // @[lsu.scala:252:32] wire [1:0] s_uop_26_mem_size = stq_uop_23_mem_size; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_mem_size = stq_uop_23_mem_size; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_mem_signed; // @[lsu.scala:252:32] wire s_uop_26_mem_signed = stq_uop_23_mem_signed; // @[lsu.scala:252:32, :1324:37] wire uop_24_mem_signed = stq_uop_23_mem_signed; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_uses_ldq; // @[lsu.scala:252:32] wire s_uop_26_uses_ldq = stq_uop_23_uses_ldq; // @[lsu.scala:252:32, :1324:37] wire uop_24_uses_ldq = stq_uop_23_uses_ldq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_uses_stq; // @[lsu.scala:252:32] wire s_uop_26_uses_stq = stq_uop_23_uses_stq; // @[lsu.scala:252:32, :1324:37] wire uop_24_uses_stq = stq_uop_23_uses_stq; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_is_unique; // @[lsu.scala:252:32] wire s_uop_26_is_unique = stq_uop_23_is_unique; // @[lsu.scala:252:32, :1324:37] wire uop_24_is_unique = stq_uop_23_is_unique; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_flush_on_commit; // @[lsu.scala:252:32] wire s_uop_26_flush_on_commit = stq_uop_23_flush_on_commit; // @[lsu.scala:252:32, :1324:37] wire uop_24_flush_on_commit = stq_uop_23_flush_on_commit; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_csr_cmd; // @[lsu.scala:252:32] wire [2:0] s_uop_26_csr_cmd = stq_uop_23_csr_cmd; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_csr_cmd = stq_uop_23_csr_cmd; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32] wire s_uop_26_ldst_is_rs1 = stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32, :1324:37] wire uop_24_ldst_is_rs1 = stq_uop_23_ldst_is_rs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_ldst; // @[lsu.scala:252:32] wire [5:0] s_uop_26_ldst = stq_uop_23_ldst; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_ldst = stq_uop_23_ldst; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs1; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs1 = stq_uop_23_lrs1; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs1 = stq_uop_23_lrs1; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs2; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs2 = stq_uop_23_lrs2; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs2 = stq_uop_23_lrs2; // @[lsu.scala:252:32, :1678:25] reg [5:0] stq_uop_23_lrs3; // @[lsu.scala:252:32] wire [5:0] s_uop_26_lrs3 = stq_uop_23_lrs3; // @[lsu.scala:252:32, :1324:37] wire [5:0] uop_24_lrs3 = stq_uop_23_lrs3; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_dst_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_dst_rtype = stq_uop_23_dst_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_dst_rtype = stq_uop_23_dst_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_lrs1_rtype = stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_lrs1_rtype = stq_uop_23_lrs1_rtype; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32] wire [1:0] s_uop_26_lrs2_rtype = stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_lrs2_rtype = stq_uop_23_lrs2_rtype; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_frs3_en; // @[lsu.scala:252:32] wire s_uop_26_frs3_en = stq_uop_23_frs3_en; // @[lsu.scala:252:32, :1324:37] wire uop_24_frs3_en = stq_uop_23_frs3_en; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fcn_dw; // @[lsu.scala:252:32] wire s_uop_26_fcn_dw = stq_uop_23_fcn_dw; // @[lsu.scala:252:32, :1324:37] wire uop_24_fcn_dw = stq_uop_23_fcn_dw; // @[lsu.scala:252:32, :1678:25] reg [4:0] stq_uop_23_fcn_op; // @[lsu.scala:252:32] wire [4:0] s_uop_26_fcn_op = stq_uop_23_fcn_op; // @[lsu.scala:252:32, :1324:37] wire [4:0] uop_24_fcn_op = stq_uop_23_fcn_op; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_fp_val; // @[lsu.scala:252:32] wire s_uop_26_fp_val = stq_uop_23_fp_val; // @[lsu.scala:252:32, :1324:37] wire uop_24_fp_val = stq_uop_23_fp_val; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_fp_rm; // @[lsu.scala:252:32] wire [2:0] s_uop_26_fp_rm = stq_uop_23_fp_rm; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_fp_rm = stq_uop_23_fp_rm; // @[lsu.scala:252:32, :1678:25] reg [1:0] stq_uop_23_fp_typ; // @[lsu.scala:252:32] wire [1:0] s_uop_26_fp_typ = stq_uop_23_fp_typ; // @[lsu.scala:252:32, :1324:37] wire [1:0] uop_24_fp_typ = stq_uop_23_fp_typ; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_pf_if = stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_pf_if = stq_uop_23_xcpt_pf_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_ae_if = stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_ae_if = stq_uop_23_xcpt_ae_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32] wire s_uop_26_xcpt_ma_if = stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_xcpt_ma_if = stq_uop_23_xcpt_ma_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_bp_debug_if; // @[lsu.scala:252:32] wire s_uop_26_bp_debug_if = stq_uop_23_bp_debug_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_bp_debug_if = stq_uop_23_bp_debug_if; // @[lsu.scala:252:32, :1678:25] reg stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32] wire s_uop_26_bp_xcpt_if = stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32, :1324:37] wire uop_24_bp_xcpt_if = stq_uop_23_bp_xcpt_if; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_debug_fsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_26_debug_fsrc = stq_uop_23_debug_fsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_debug_fsrc = stq_uop_23_debug_fsrc; // @[lsu.scala:252:32, :1678:25] reg [2:0] stq_uop_23_debug_tsrc; // @[lsu.scala:252:32] wire [2:0] s_uop_26_debug_tsrc = stq_uop_23_debug_tsrc; // @[lsu.scala:252:32, :1324:37] wire [2:0] uop_24_debug_tsrc = stq_uop_23_debug_tsrc; // @[lsu.scala:252:32, :1678:25] reg stq_addr_0_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_0_bits; // @[lsu.scala:253:32] reg stq_addr_1_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_1_bits; // @[lsu.scala:253:32] reg stq_addr_2_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_2_bits; // @[lsu.scala:253:32] reg stq_addr_3_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_3_bits; // @[lsu.scala:253:32] reg stq_addr_4_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_4_bits; // @[lsu.scala:253:32] reg stq_addr_5_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_5_bits; // @[lsu.scala:253:32] reg stq_addr_6_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_6_bits; // @[lsu.scala:253:32] reg stq_addr_7_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_7_bits; // @[lsu.scala:253:32] reg stq_addr_8_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_8_bits; // @[lsu.scala:253:32] reg stq_addr_9_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_9_bits; // @[lsu.scala:253:32] reg stq_addr_10_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_10_bits; // @[lsu.scala:253:32] reg stq_addr_11_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_11_bits; // @[lsu.scala:253:32] reg stq_addr_12_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_12_bits; // @[lsu.scala:253:32] reg stq_addr_13_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_13_bits; // @[lsu.scala:253:32] reg stq_addr_14_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_14_bits; // @[lsu.scala:253:32] reg stq_addr_15_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_15_bits; // @[lsu.scala:253:32] reg stq_addr_16_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_16_bits; // @[lsu.scala:253:32] reg stq_addr_17_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_17_bits; // @[lsu.scala:253:32] reg stq_addr_18_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_18_bits; // @[lsu.scala:253:32] reg stq_addr_19_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_19_bits; // @[lsu.scala:253:32] reg stq_addr_20_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_20_bits; // @[lsu.scala:253:32] reg stq_addr_21_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_21_bits; // @[lsu.scala:253:32] reg stq_addr_22_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_22_bits; // @[lsu.scala:253:32] reg stq_addr_23_valid; // @[lsu.scala:253:32] reg [39:0] stq_addr_23_bits; // @[lsu.scala:253:32] reg stq_addr_is_virtual_0; // @[lsu.scala:254:32] reg stq_addr_is_virtual_1; // @[lsu.scala:254:32] reg stq_addr_is_virtual_2; // @[lsu.scala:254:32] reg stq_addr_is_virtual_3; // @[lsu.scala:254:32] reg stq_addr_is_virtual_4; // @[lsu.scala:254:32] reg stq_addr_is_virtual_5; // @[lsu.scala:254:32] reg stq_addr_is_virtual_6; // @[lsu.scala:254:32] reg stq_addr_is_virtual_7; // @[lsu.scala:254:32] reg stq_addr_is_virtual_8; // @[lsu.scala:254:32] reg stq_addr_is_virtual_9; // @[lsu.scala:254:32] reg stq_addr_is_virtual_10; // @[lsu.scala:254:32] reg stq_addr_is_virtual_11; // @[lsu.scala:254:32] reg stq_addr_is_virtual_12; // @[lsu.scala:254:32] reg stq_addr_is_virtual_13; // @[lsu.scala:254:32] reg stq_addr_is_virtual_14; // @[lsu.scala:254:32] reg stq_addr_is_virtual_15; // @[lsu.scala:254:32] reg stq_addr_is_virtual_16; // @[lsu.scala:254:32] reg stq_addr_is_virtual_17; // @[lsu.scala:254:32] reg stq_addr_is_virtual_18; // @[lsu.scala:254:32] reg stq_addr_is_virtual_19; // @[lsu.scala:254:32] reg stq_addr_is_virtual_20; // @[lsu.scala:254:32] reg stq_addr_is_virtual_21; // @[lsu.scala:254:32] reg stq_addr_is_virtual_22; // @[lsu.scala:254:32] reg stq_addr_is_virtual_23; // @[lsu.scala:254:32] reg stq_data_0_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_0_bits; // @[lsu.scala:255:32] reg stq_data_1_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_1_bits; // @[lsu.scala:255:32] reg stq_data_2_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_2_bits; // @[lsu.scala:255:32] reg stq_data_3_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_3_bits; // @[lsu.scala:255:32] reg stq_data_4_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_4_bits; // @[lsu.scala:255:32] reg stq_data_5_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_5_bits; // @[lsu.scala:255:32] reg stq_data_6_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_6_bits; // @[lsu.scala:255:32] reg stq_data_7_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_7_bits; // @[lsu.scala:255:32] reg stq_data_8_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_8_bits; // @[lsu.scala:255:32] reg stq_data_9_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_9_bits; // @[lsu.scala:255:32] reg stq_data_10_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_10_bits; // @[lsu.scala:255:32] reg stq_data_11_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_11_bits; // @[lsu.scala:255:32] reg stq_data_12_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_12_bits; // @[lsu.scala:255:32] reg stq_data_13_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_13_bits; // @[lsu.scala:255:32] reg stq_data_14_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_14_bits; // @[lsu.scala:255:32] reg stq_data_15_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_15_bits; // @[lsu.scala:255:32] reg stq_data_16_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_16_bits; // @[lsu.scala:255:32] reg stq_data_17_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_17_bits; // @[lsu.scala:255:32] reg stq_data_18_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_18_bits; // @[lsu.scala:255:32] reg stq_data_19_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_19_bits; // @[lsu.scala:255:32] reg stq_data_20_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_20_bits; // @[lsu.scala:255:32] reg stq_data_21_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_21_bits; // @[lsu.scala:255:32] reg stq_data_22_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_22_bits; // @[lsu.scala:255:32] reg stq_data_23_valid; // @[lsu.scala:255:32] reg [63:0] stq_data_23_bits; // @[lsu.scala:255:32] reg stq_committed_0; // @[lsu.scala:256:32] reg stq_committed_1; // @[lsu.scala:256:32] reg stq_committed_2; // @[lsu.scala:256:32] reg stq_committed_3; // @[lsu.scala:256:32] reg stq_committed_4; // @[lsu.scala:256:32] reg stq_committed_5; // @[lsu.scala:256:32] reg stq_committed_6; // @[lsu.scala:256:32] reg stq_committed_7; // @[lsu.scala:256:32] reg stq_committed_8; // @[lsu.scala:256:32] reg stq_committed_9; // @[lsu.scala:256:32] reg stq_committed_10; // @[lsu.scala:256:32] reg stq_committed_11; // @[lsu.scala:256:32] reg stq_committed_12; // @[lsu.scala:256:32] reg stq_committed_13; // @[lsu.scala:256:32] reg stq_committed_14; // @[lsu.scala:256:32] reg stq_committed_15; // @[lsu.scala:256:32] reg stq_committed_16; // @[lsu.scala:256:32] reg stq_committed_17; // @[lsu.scala:256:32] reg stq_committed_18; // @[lsu.scala:256:32] reg stq_committed_19; // @[lsu.scala:256:32] reg stq_committed_20; // @[lsu.scala:256:32] reg stq_committed_21; // @[lsu.scala:256:32] reg stq_committed_22; // @[lsu.scala:256:32] reg stq_committed_23; // @[lsu.scala:256:32] reg stq_succeeded_0; // @[lsu.scala:257:32] reg stq_succeeded_1; // @[lsu.scala:257:32] reg stq_succeeded_2; // @[lsu.scala:257:32] reg stq_succeeded_3; // @[lsu.scala:257:32] reg stq_succeeded_4; // @[lsu.scala:257:32] reg stq_succeeded_5; // @[lsu.scala:257:32] reg stq_succeeded_6; // @[lsu.scala:257:32] reg stq_succeeded_7; // @[lsu.scala:257:32] reg stq_succeeded_8; // @[lsu.scala:257:32] reg stq_succeeded_9; // @[lsu.scala:257:32] reg stq_succeeded_10; // @[lsu.scala:257:32] reg stq_succeeded_11; // @[lsu.scala:257:32] reg stq_succeeded_12; // @[lsu.scala:257:32] reg stq_succeeded_13; // @[lsu.scala:257:32] reg stq_succeeded_14; // @[lsu.scala:257:32] reg stq_succeeded_15; // @[lsu.scala:257:32] reg stq_succeeded_16; // @[lsu.scala:257:32] reg stq_succeeded_17; // @[lsu.scala:257:32] reg stq_succeeded_18; // @[lsu.scala:257:32] reg stq_succeeded_19; // @[lsu.scala:257:32] reg stq_succeeded_20; // @[lsu.scala:257:32] reg stq_succeeded_21; // @[lsu.scala:257:32] reg stq_succeeded_22; // @[lsu.scala:257:32] reg stq_succeeded_23; // @[lsu.scala:257:32] reg stq_can_execute_0; // @[lsu.scala:258:32] reg stq_can_execute_1; // @[lsu.scala:258:32] reg stq_can_execute_2; // @[lsu.scala:258:32] reg stq_can_execute_3; // @[lsu.scala:258:32] reg stq_can_execute_4; // @[lsu.scala:258:32] reg stq_can_execute_5; // @[lsu.scala:258:32] reg stq_can_execute_6; // @[lsu.scala:258:32] reg stq_can_execute_7; // @[lsu.scala:258:32] reg stq_can_execute_8; // @[lsu.scala:258:32] reg stq_can_execute_9; // @[lsu.scala:258:32] reg stq_can_execute_10; // @[lsu.scala:258:32] reg stq_can_execute_11; // @[lsu.scala:258:32] reg stq_can_execute_12; // @[lsu.scala:258:32] reg stq_can_execute_13; // @[lsu.scala:258:32] reg stq_can_execute_14; // @[lsu.scala:258:32] reg stq_can_execute_15; // @[lsu.scala:258:32] reg stq_can_execute_16; // @[lsu.scala:258:32] reg stq_can_execute_17; // @[lsu.scala:258:32] reg stq_can_execute_18; // @[lsu.scala:258:32] reg stq_can_execute_19; // @[lsu.scala:258:32] reg stq_can_execute_20; // @[lsu.scala:258:32] reg stq_can_execute_21; // @[lsu.scala:258:32] reg stq_can_execute_22; // @[lsu.scala:258:32] reg stq_can_execute_23; // @[lsu.scala:258:32] reg stq_cleared_0; // @[lsu.scala:259:32] reg stq_cleared_1; // @[lsu.scala:259:32] reg stq_cleared_2; // @[lsu.scala:259:32] reg stq_cleared_3; // @[lsu.scala:259:32] reg stq_cleared_4; // @[lsu.scala:259:32] reg stq_cleared_5; // @[lsu.scala:259:32] reg stq_cleared_6; // @[lsu.scala:259:32] reg stq_cleared_7; // @[lsu.scala:259:32] reg stq_cleared_8; // @[lsu.scala:259:32] reg stq_cleared_9; // @[lsu.scala:259:32] reg stq_cleared_10; // @[lsu.scala:259:32] reg stq_cleared_11; // @[lsu.scala:259:32] reg stq_cleared_12; // @[lsu.scala:259:32] reg stq_cleared_13; // @[lsu.scala:259:32] reg stq_cleared_14; // @[lsu.scala:259:32] reg stq_cleared_15; // @[lsu.scala:259:32] reg stq_cleared_16; // @[lsu.scala:259:32] reg stq_cleared_17; // @[lsu.scala:259:32] reg stq_cleared_18; // @[lsu.scala:259:32] reg stq_cleared_19; // @[lsu.scala:259:32] reg stq_cleared_20; // @[lsu.scala:259:32] reg stq_cleared_21; // @[lsu.scala:259:32] reg stq_cleared_22; // @[lsu.scala:259:32] reg stq_cleared_23; // @[lsu.scala:259:32] reg [63:0] stq_debug_wb_data_0; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_1; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_2; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_3; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_4; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_5; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_6; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_7; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_8; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_9; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_10; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_11; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_12; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_13; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_14; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_15; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_16; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_17; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_18; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_19; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_20; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_21; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_22; // @[lsu.scala:260:32] reg [63:0] stq_debug_wb_data_23; // @[lsu.scala:260:32] reg [4:0] ldq_head; // @[lsu.scala:278:29] reg [4:0] ldq_tail; // @[lsu.scala:279:29] assign io_core_dis_ldq_idx_0_0 = ldq_tail; // @[lsu.scala:211:7, :279:29] reg [4:0] stq_head; // @[lsu.scala:280:29] reg [4:0] stq_tail; // @[lsu.scala:281:29] assign io_core_dis_stq_idx_0_0 = stq_tail; // @[lsu.scala:211:7, :281:29] reg [4:0] stq_commit_head; // @[lsu.scala:282:29] reg [4:0] stq_execute_head; // @[lsu.scala:283:29] reg [2:0] hella_state; // @[lsu.scala:301:38] reg [39:0] hella_req_addr; // @[lsu.scala:302:34] assign io_hellacache_resp_bits_addr_0 = hella_req_addr; // @[lsu.scala:211:7, :302:34] reg hella_req_dv; // @[lsu.scala:302:34] reg [63:0] hella_data_data; // @[lsu.scala:303:34] wire [63:0] _dmem_req_0_bits_data_T_42 = hella_data_data; // @[AMOALU.scala:29:13] reg [7:0] hella_data_mask; // @[lsu.scala:303:34] reg [31:0] hella_paddr; // @[lsu.scala:304:34] reg hella_xcpt_ma_ld; // @[lsu.scala:305:34] reg hella_xcpt_ma_st; // @[lsu.scala:305:34] reg hella_xcpt_pf_ld; // @[lsu.scala:305:34] reg hella_xcpt_pf_st; // @[lsu.scala:305:34] reg hella_xcpt_gf_ld; // @[lsu.scala:305:34] reg hella_xcpt_gf_st; // @[lsu.scala:305:34] reg hella_xcpt_ae_ld; // @[lsu.scala:305:34] reg hella_xcpt_ae_st; // @[lsu.scala:305:34] assign _io_core_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] assign io_core_perf_tlbMiss_0 = _io_core_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire clear_store; // @[lsu.scala:318:33] wire ldq_will_succeed_0; // @[lsu.scala:325:44] wire ldq_will_succeed_1; // @[lsu.scala:325:44] wire ldq_will_succeed_2; // @[lsu.scala:325:44] wire ldq_will_succeed_3; // @[lsu.scala:325:44] wire ldq_will_succeed_4; // @[lsu.scala:325:44] wire ldq_will_succeed_5; // @[lsu.scala:325:44] wire ldq_will_succeed_6; // @[lsu.scala:325:44] wire ldq_will_succeed_7; // @[lsu.scala:325:44] wire ldq_will_succeed_8; // @[lsu.scala:325:44] wire ldq_will_succeed_9; // @[lsu.scala:325:44] wire ldq_will_succeed_10; // @[lsu.scala:325:44] wire ldq_will_succeed_11; // @[lsu.scala:325:44] wire ldq_will_succeed_12; // @[lsu.scala:325:44] wire ldq_will_succeed_13; // @[lsu.scala:325:44] wire ldq_will_succeed_14; // @[lsu.scala:325:44] wire ldq_will_succeed_15; // @[lsu.scala:325:44] wire ldq_will_succeed_16; // @[lsu.scala:325:44] wire ldq_will_succeed_17; // @[lsu.scala:325:44] wire ldq_will_succeed_18; // @[lsu.scala:325:44] wire ldq_will_succeed_19; // @[lsu.scala:325:44] wire ldq_will_succeed_20; // @[lsu.scala:325:44] wire ldq_will_succeed_21; // @[lsu.scala:325:44] wire ldq_will_succeed_22; // @[lsu.scala:325:44] wire ldq_will_succeed_23; // @[lsu.scala:325:44] wire [31:0] _GEN = 32'h1 << stq_head; // @[lsu.scala:280:29, :340:56] wire [31:0] _ldq_st_dep_mask_0_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_0_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_1_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_1_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_2_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_2_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_3_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_3_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_4_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_4_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_5_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_5_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_6_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_6_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_7_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_7_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_8_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_8_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_9_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_9_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_10_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_10_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_11_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_11_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_12_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_12_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_13_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_13_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_14_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_14_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_15_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_15_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_16_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_16_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_17_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_17_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_18_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_18_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_19_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_19_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_20_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_20_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_21_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_21_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_22_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_22_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _ldq_st_dep_mask_23_T; // @[lsu.scala:340:56] assign _ldq_st_dep_mask_23_T = _GEN; // @[lsu.scala:340:56] wire [31:0] _next_live_store_mask_T; // @[lsu.scala:355:71] assign _next_live_store_mask_T = _GEN; // @[lsu.scala:340:56, :355:71] wire [31:0] _ldq_st_dep_mask_0_T_1 = ~_ldq_st_dep_mask_0_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_0_T_2 = {8'h0, _ldq_st_dep_mask_0_T_1[23:0] & ldq_st_dep_mask_0}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_1_T_1 = ~_ldq_st_dep_mask_1_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_1_T_2 = {8'h0, _ldq_st_dep_mask_1_T_1[23:0] & ldq_st_dep_mask_1}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_2_T_1 = ~_ldq_st_dep_mask_2_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_2_T_2 = {8'h0, _ldq_st_dep_mask_2_T_1[23:0] & ldq_st_dep_mask_2}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_3_T_1 = ~_ldq_st_dep_mask_3_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_3_T_2 = {8'h0, _ldq_st_dep_mask_3_T_1[23:0] & ldq_st_dep_mask_3}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_4_T_1 = ~_ldq_st_dep_mask_4_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_4_T_2 = {8'h0, _ldq_st_dep_mask_4_T_1[23:0] & ldq_st_dep_mask_4}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_5_T_1 = ~_ldq_st_dep_mask_5_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_5_T_2 = {8'h0, _ldq_st_dep_mask_5_T_1[23:0] & ldq_st_dep_mask_5}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_6_T_1 = ~_ldq_st_dep_mask_6_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_6_T_2 = {8'h0, _ldq_st_dep_mask_6_T_1[23:0] & ldq_st_dep_mask_6}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_7_T_1 = ~_ldq_st_dep_mask_7_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_7_T_2 = {8'h0, _ldq_st_dep_mask_7_T_1[23:0] & ldq_st_dep_mask_7}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_8_T_1 = ~_ldq_st_dep_mask_8_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_8_T_2 = {8'h0, _ldq_st_dep_mask_8_T_1[23:0] & ldq_st_dep_mask_8}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_9_T_1 = ~_ldq_st_dep_mask_9_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_9_T_2 = {8'h0, _ldq_st_dep_mask_9_T_1[23:0] & ldq_st_dep_mask_9}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_10_T_1 = ~_ldq_st_dep_mask_10_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_10_T_2 = {8'h0, _ldq_st_dep_mask_10_T_1[23:0] & ldq_st_dep_mask_10}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_11_T_1 = ~_ldq_st_dep_mask_11_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_11_T_2 = {8'h0, _ldq_st_dep_mask_11_T_1[23:0] & ldq_st_dep_mask_11}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_12_T_1 = ~_ldq_st_dep_mask_12_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_12_T_2 = {8'h0, _ldq_st_dep_mask_12_T_1[23:0] & ldq_st_dep_mask_12}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_13_T_1 = ~_ldq_st_dep_mask_13_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_13_T_2 = {8'h0, _ldq_st_dep_mask_13_T_1[23:0] & ldq_st_dep_mask_13}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_14_T_1 = ~_ldq_st_dep_mask_14_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_14_T_2 = {8'h0, _ldq_st_dep_mask_14_T_1[23:0] & ldq_st_dep_mask_14}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_15_T_1 = ~_ldq_st_dep_mask_15_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_15_T_2 = {8'h0, _ldq_st_dep_mask_15_T_1[23:0] & ldq_st_dep_mask_15}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_16_T_1 = ~_ldq_st_dep_mask_16_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_16_T_2 = {8'h0, _ldq_st_dep_mask_16_T_1[23:0] & ldq_st_dep_mask_16}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_17_T_1 = ~_ldq_st_dep_mask_17_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_17_T_2 = {8'h0, _ldq_st_dep_mask_17_T_1[23:0] & ldq_st_dep_mask_17}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_18_T_1 = ~_ldq_st_dep_mask_18_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_18_T_2 = {8'h0, _ldq_st_dep_mask_18_T_1[23:0] & ldq_st_dep_mask_18}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_19_T_1 = ~_ldq_st_dep_mask_19_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_19_T_2 = {8'h0, _ldq_st_dep_mask_19_T_1[23:0] & ldq_st_dep_mask_19}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_20_T_1 = ~_ldq_st_dep_mask_20_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_20_T_2 = {8'h0, _ldq_st_dep_mask_20_T_1[23:0] & ldq_st_dep_mask_20}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_21_T_1 = ~_ldq_st_dep_mask_21_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_21_T_2 = {8'h0, _ldq_st_dep_mask_21_T_1[23:0] & ldq_st_dep_mask_21}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_22_T_1 = ~_ldq_st_dep_mask_22_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_22_T_2 = {8'h0, _ldq_st_dep_mask_22_T_1[23:0] & ldq_st_dep_mask_22}; // @[lsu.scala:227:36, :340:{48,50}] wire [31:0] _ldq_st_dep_mask_23_T_1 = ~_ldq_st_dep_mask_23_T; // @[lsu.scala:340:{50,56}] wire [31:0] _ldq_st_dep_mask_23_T_2 = {8'h0, _ldq_st_dep_mask_23_T_1[23:0] & ldq_st_dep_mask_23}; // @[lsu.scala:227:36, :340:{48,50}] reg dis_ldq_oh_0; // @[lsu.scala:348:23] reg dis_ldq_oh_1; // @[lsu.scala:348:23] reg dis_ldq_oh_2; // @[lsu.scala:348:23] reg dis_ldq_oh_3; // @[lsu.scala:348:23] reg dis_ldq_oh_4; // @[lsu.scala:348:23] reg dis_ldq_oh_5; // @[lsu.scala:348:23] reg dis_ldq_oh_6; // @[lsu.scala:348:23] reg dis_ldq_oh_7; // @[lsu.scala:348:23] reg dis_ldq_oh_8; // @[lsu.scala:348:23] reg dis_ldq_oh_9; // @[lsu.scala:348:23] reg dis_ldq_oh_10; // @[lsu.scala:348:23] reg dis_ldq_oh_11; // @[lsu.scala:348:23] reg dis_ldq_oh_12; // @[lsu.scala:348:23] reg dis_ldq_oh_13; // @[lsu.scala:348:23] reg dis_ldq_oh_14; // @[lsu.scala:348:23] reg dis_ldq_oh_15; // @[lsu.scala:348:23] reg dis_ldq_oh_16; // @[lsu.scala:348:23] reg dis_ldq_oh_17; // @[lsu.scala:348:23] reg dis_ldq_oh_18; // @[lsu.scala:348:23] reg dis_ldq_oh_19; // @[lsu.scala:348:23] reg dis_ldq_oh_20; // @[lsu.scala:348:23] reg dis_ldq_oh_21; // @[lsu.scala:348:23] reg dis_ldq_oh_22; // @[lsu.scala:348:23] reg dis_ldq_oh_23; // @[lsu.scala:348:23] reg dis_stq_oh_0; // @[lsu.scala:349:23] reg dis_stq_oh_1; // @[lsu.scala:349:23] reg dis_stq_oh_2; // @[lsu.scala:349:23] reg dis_stq_oh_3; // @[lsu.scala:349:23] reg dis_stq_oh_4; // @[lsu.scala:349:23] reg dis_stq_oh_5; // @[lsu.scala:349:23] reg dis_stq_oh_6; // @[lsu.scala:349:23] reg dis_stq_oh_7; // @[lsu.scala:349:23] reg dis_stq_oh_8; // @[lsu.scala:349:23] reg dis_stq_oh_9; // @[lsu.scala:349:23] reg dis_stq_oh_10; // @[lsu.scala:349:23] reg dis_stq_oh_11; // @[lsu.scala:349:23] reg dis_stq_oh_12; // @[lsu.scala:349:23] reg dis_stq_oh_13; // @[lsu.scala:349:23] reg dis_stq_oh_14; // @[lsu.scala:349:23] reg dis_stq_oh_15; // @[lsu.scala:349:23] reg dis_stq_oh_16; // @[lsu.scala:349:23] reg dis_stq_oh_17; // @[lsu.scala:349:23] reg dis_stq_oh_18; // @[lsu.scala:349:23] reg dis_stq_oh_19; // @[lsu.scala:349:23] reg dis_stq_oh_20; // @[lsu.scala:349:23] reg dis_stq_oh_21; // @[lsu.scala:349:23] reg dis_stq_oh_22; // @[lsu.scala:349:23] reg dis_stq_oh_23; // @[lsu.scala:349:23] reg dis_uops_0_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_0_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_inst = dis_uops_0_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_0_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_debug_inst = dis_uops_0_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_0_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_is_rvc = dis_uops_0_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_0_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_debug_pc = dis_uops_0_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_iq_type_0 = dis_uops_0_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_iq_type_1 = dis_uops_0_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_iq_type_2 = dis_uops_0_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_0_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_iq_type_3 = dis_uops_0_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_fu_code_0 = dis_uops_0_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_fu_code_1 = dis_uops_0_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_fu_code_2 = dis_uops_0_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_fu_code_3 = dis_uops_0_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_fu_code_4 = dis_uops_0_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_fu_code_5 = dis_uops_0_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_fu_code_6 = dis_uops_0_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_fu_code_7 = dis_uops_0_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_fu_code_8 = dis_uops_0_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_0_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_fu_code_9 = dis_uops_0_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_iw_issued = dis_uops_0_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_agen = dis_uops_0_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_0_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_iw_issued_partial_dgen = dis_uops_0_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_iw_p1_speculative_child = dis_uops_0_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_iw_p2_speculative_child = dis_uops_0_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p1_bypass_hint = dis_uops_0_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p2_bypass_hint = dis_uops_0_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_0_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_iw_p3_bypass_hint = dis_uops_0_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_dis_col_sel = dis_uops_0_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_0_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_0_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_tag = dis_uops_0_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_0_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_br_type = dis_uops_0_bits_br_type; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_is_sfb = dis_uops_0_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_0_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_is_fence = dis_uops_0_bits_is_fence; // @[util.scala:104:23] reg dis_uops_0_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_is_fencei = dis_uops_0_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_0_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_is_sfence = dis_uops_0_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_0_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_is_amo = dis_uops_0_bits_is_amo; // @[util.scala:104:23] reg dis_uops_0_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_is_eret = dis_uops_0_bits_is_eret; // @[util.scala:104:23] reg dis_uops_0_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_is_sys_pc2epc = dis_uops_0_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_0_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_is_rocc = dis_uops_0_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_0_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_is_mov = dis_uops_0_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ftq_idx = dis_uops_0_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_0_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_edge_inst = dis_uops_0_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_pc_lob = dis_uops_0_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_0_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] wire stq_uop_out_taken = dis_uops_0_bits_taken; // @[util.scala:104:23] reg dis_uops_0_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_imm_rename = dis_uops_0_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_imm_sel = dis_uops_0_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_pimm = dis_uops_0_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_0_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_imm_packed = dis_uops_0_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_op1_sel = dis_uops_0_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_op2_sel = dis_uops_0_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ldst = dis_uops_0_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wen = dis_uops_0_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren1 = dis_uops_0_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren2 = dis_uops_0_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_ren3 = dis_uops_0_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap12 = dis_uops_0_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_swap23 = dis_uops_0_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagIn = dis_uops_0_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_ctrl_typeTagOut = dis_uops_0_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fromint = dis_uops_0_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_toint = dis_uops_0_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fastpipe = dis_uops_0_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_fma = dis_uops_0_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_div = dis_uops_0_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_sqrt = dis_uops_0_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_wflags = dis_uops_0_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_0_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_fp_ctrl_vec = dis_uops_0_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_rob_idx = dis_uops_0_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_ldq_idx = dis_uops_0_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_stq_idx = dis_uops_0_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_rxq_idx = dis_uops_0_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_pdst = dis_uops_0_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs1 = dis_uops_0_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs2 = dis_uops_0_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_prs3 = dis_uops_0_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_ppred = dis_uops_0_bits_ppred; // @[util.scala:104:23] reg dis_uops_0_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_prs1_busy = dis_uops_0_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_prs2_busy = dis_uops_0_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_0_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_prs3_busy = dis_uops_0_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_0_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_ppred_busy = dis_uops_0_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_0_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_stale_pdst = dis_uops_0_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_0_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] wire stq_uop_out_exception = dis_uops_0_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_0_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_exc_cause = dis_uops_0_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_mem_cmd = dis_uops_0_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_mem_size = dis_uops_0_bits_mem_size; // @[util.scala:104:23] reg dis_uops_0_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_mem_signed = dis_uops_0_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_uses_ldq = dis_uops_0_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_0_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_uses_stq = dis_uops_0_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_0_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_is_unique = dis_uops_0_bits_is_unique; // @[util.scala:104:23] reg dis_uops_0_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_flush_on_commit = dis_uops_0_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_csr_cmd = dis_uops_0_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_0_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_ldst_is_rs1 = dis_uops_0_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_ldst = dis_uops_0_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs1 = dis_uops_0_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs2 = dis_uops_0_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_0_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_lrs3 = dis_uops_0_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_dst_rtype = dis_uops_0_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs1_rtype = dis_uops_0_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_lrs2_rtype = dis_uops_0_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_0_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_frs3_en = dis_uops_0_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_0_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_fcn_dw = dis_uops_0_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_0_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_fcn_op = dis_uops_0_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_0_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_fp_val = dis_uops_0_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_fp_rm = dis_uops_0_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_0_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_fp_typ = dis_uops_0_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_pf_if = dis_uops_0_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ae_if = dis_uops_0_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_0_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_xcpt_ma_if = dis_uops_0_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_bp_debug_if = dis_uops_0_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_0_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_bp_xcpt_if = dis_uops_0_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_fsrc = dis_uops_0_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_0_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_debug_tsrc = dis_uops_0_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_1_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_1_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_inst = dis_uops_1_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_1_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_1_debug_inst = dis_uops_1_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_1_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_1_is_rvc = dis_uops_1_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_1_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_1_debug_pc = dis_uops_1_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_0 = dis_uops_1_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_1 = dis_uops_1_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_2 = dis_uops_1_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_1_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_1_iq_type_3 = dis_uops_1_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_0 = dis_uops_1_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_1 = dis_uops_1_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_2 = dis_uops_1_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_3 = dis_uops_1_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_4 = dis_uops_1_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_5 = dis_uops_1_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_6 = dis_uops_1_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_7 = dis_uops_1_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_8 = dis_uops_1_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_1_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_1_fu_code_9 = dis_uops_1_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued = dis_uops_1_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_agen = dis_uops_1_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_1_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_1_iw_issued_partial_dgen = dis_uops_1_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_iw_p1_speculative_child = dis_uops_1_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_iw_p2_speculative_child = dis_uops_1_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p1_bypass_hint = dis_uops_1_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p2_bypass_hint = dis_uops_1_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_1_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_1_iw_p3_bypass_hint = dis_uops_1_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_dis_col_sel = dis_uops_1_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_1_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_1_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_tag = dis_uops_1_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_1_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_1_br_type = dis_uops_1_bits_br_type; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_1_is_sfb = dis_uops_1_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_1_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_1_is_fence = dis_uops_1_bits_is_fence; // @[util.scala:104:23] reg dis_uops_1_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_1_is_fencei = dis_uops_1_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_1_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_1_is_sfence = dis_uops_1_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_1_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_1_is_amo = dis_uops_1_bits_is_amo; // @[util.scala:104:23] reg dis_uops_1_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_1_is_eret = dis_uops_1_bits_is_eret; // @[util.scala:104:23] reg dis_uops_1_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_1_is_sys_pc2epc = dis_uops_1_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_1_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_1_is_rocc = dis_uops_1_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_1_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_1_is_mov = dis_uops_1_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ftq_idx = dis_uops_1_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_1_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_1_edge_inst = dis_uops_1_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_pc_lob = dis_uops_1_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_1_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] wire stq_uop_out_1_taken = dis_uops_1_bits_taken; // @[util.scala:104:23] reg dis_uops_1_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_1_imm_rename = dis_uops_1_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_imm_sel = dis_uops_1_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_pimm = dis_uops_1_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_1_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_1_imm_packed = dis_uops_1_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_op1_sel = dis_uops_1_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_op2_sel = dis_uops_1_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ldst = dis_uops_1_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wen = dis_uops_1_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren1 = dis_uops_1_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren2 = dis_uops_1_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_ren3 = dis_uops_1_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap12 = dis_uops_1_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_swap23 = dis_uops_1_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagIn = dis_uops_1_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_ctrl_typeTagOut = dis_uops_1_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fromint = dis_uops_1_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_toint = dis_uops_1_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fastpipe = dis_uops_1_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_fma = dis_uops_1_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_div = dis_uops_1_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_sqrt = dis_uops_1_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_wflags = dis_uops_1_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_1_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_1_fp_ctrl_vec = dis_uops_1_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_rob_idx = dis_uops_1_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ldq_idx = dis_uops_1_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_stq_idx = dis_uops_1_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_rxq_idx = dis_uops_1_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_pdst = dis_uops_1_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs1 = dis_uops_1_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs2 = dis_uops_1_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_prs3 = dis_uops_1_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_ppred = dis_uops_1_bits_ppred; // @[util.scala:104:23] reg dis_uops_1_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs1_busy = dis_uops_1_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs2_busy = dis_uops_1_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_1_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_1_prs3_busy = dis_uops_1_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_1_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_1_ppred_busy = dis_uops_1_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_1_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_1_stale_pdst = dis_uops_1_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_1_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] wire stq_uop_out_1_exception = dis_uops_1_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_1_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_1_exc_cause = dis_uops_1_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_mem_cmd = dis_uops_1_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_mem_size = dis_uops_1_bits_mem_size; // @[util.scala:104:23] reg dis_uops_1_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_1_mem_signed = dis_uops_1_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_1_uses_ldq = dis_uops_1_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_1_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_1_uses_stq = dis_uops_1_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_1_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_1_is_unique = dis_uops_1_bits_is_unique; // @[util.scala:104:23] reg dis_uops_1_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_1_flush_on_commit = dis_uops_1_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_csr_cmd = dis_uops_1_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_1_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_1_ldst_is_rs1 = dis_uops_1_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_ldst = dis_uops_1_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs1 = dis_uops_1_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs2 = dis_uops_1_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_1_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_1_lrs3 = dis_uops_1_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_dst_rtype = dis_uops_1_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs1_rtype = dis_uops_1_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_lrs2_rtype = dis_uops_1_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_1_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_1_frs3_en = dis_uops_1_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_1_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_1_fcn_dw = dis_uops_1_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_1_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_1_fcn_op = dis_uops_1_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_1_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_1_fp_val = dis_uops_1_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_fp_rm = dis_uops_1_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_1_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_1_fp_typ = dis_uops_1_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_pf_if = dis_uops_1_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ae_if = dis_uops_1_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_1_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_1_xcpt_ma_if = dis_uops_1_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_debug_if = dis_uops_1_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_1_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_1_bp_xcpt_if = dis_uops_1_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_fsrc = dis_uops_1_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_1_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_1_debug_tsrc = dis_uops_1_bits_debug_tsrc; // @[util.scala:104:23] reg dis_uops_2_valid; // @[lsu.scala:352:23] reg [31:0] dis_uops_2_bits_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_2_inst = dis_uops_2_bits_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_2_inst = dis_uops_2_bits_inst; // @[util.scala:104:23] reg [31:0] dis_uops_2_bits_debug_inst; // @[lsu.scala:352:23] wire [31:0] ldq_uop_out_2_debug_inst = dis_uops_2_bits_debug_inst; // @[util.scala:104:23] wire [31:0] stq_uop_out_2_debug_inst = dis_uops_2_bits_debug_inst; // @[util.scala:104:23] reg dis_uops_2_bits_is_rvc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_rvc = dis_uops_2_bits_is_rvc; // @[util.scala:104:23] wire stq_uop_out_2_is_rvc = dis_uops_2_bits_is_rvc; // @[util.scala:104:23] reg [39:0] dis_uops_2_bits_debug_pc; // @[lsu.scala:352:23] wire [39:0] ldq_uop_out_2_debug_pc = dis_uops_2_bits_debug_pc; // @[util.scala:104:23] wire [39:0] stq_uop_out_2_debug_pc = dis_uops_2_bits_debug_pc; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_0; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_0 = dis_uops_2_bits_iq_type_0; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_0 = dis_uops_2_bits_iq_type_0; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_1; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_1 = dis_uops_2_bits_iq_type_1; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_1 = dis_uops_2_bits_iq_type_1; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_2; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_2 = dis_uops_2_bits_iq_type_2; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_2 = dis_uops_2_bits_iq_type_2; // @[util.scala:104:23] reg dis_uops_2_bits_iq_type_3; // @[lsu.scala:352:23] wire ldq_uop_out_2_iq_type_3 = dis_uops_2_bits_iq_type_3; // @[util.scala:104:23] wire stq_uop_out_2_iq_type_3 = dis_uops_2_bits_iq_type_3; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_0; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_0 = dis_uops_2_bits_fu_code_0; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_0 = dis_uops_2_bits_fu_code_0; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_1; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_1 = dis_uops_2_bits_fu_code_1; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_1 = dis_uops_2_bits_fu_code_1; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_2; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_2 = dis_uops_2_bits_fu_code_2; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_2 = dis_uops_2_bits_fu_code_2; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_3; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_3 = dis_uops_2_bits_fu_code_3; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_3 = dis_uops_2_bits_fu_code_3; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_4; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_4 = dis_uops_2_bits_fu_code_4; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_4 = dis_uops_2_bits_fu_code_4; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_5; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_5 = dis_uops_2_bits_fu_code_5; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_5 = dis_uops_2_bits_fu_code_5; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_6; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_6 = dis_uops_2_bits_fu_code_6; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_6 = dis_uops_2_bits_fu_code_6; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_7; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_7 = dis_uops_2_bits_fu_code_7; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_7 = dis_uops_2_bits_fu_code_7; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_8; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_8 = dis_uops_2_bits_fu_code_8; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_8 = dis_uops_2_bits_fu_code_8; // @[util.scala:104:23] reg dis_uops_2_bits_fu_code_9; // @[lsu.scala:352:23] wire ldq_uop_out_2_fu_code_9 = dis_uops_2_bits_fu_code_9; // @[util.scala:104:23] wire stq_uop_out_2_fu_code_9 = dis_uops_2_bits_fu_code_9; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued = dis_uops_2_bits_iw_issued; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued = dis_uops_2_bits_iw_issued; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued_partial_agen; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued_partial_agen = dis_uops_2_bits_iw_issued_partial_agen; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued_partial_agen = dis_uops_2_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg dis_uops_2_bits_iw_issued_partial_dgen; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_issued_partial_dgen = dis_uops_2_bits_iw_issued_partial_dgen; // @[util.scala:104:23] wire stq_uop_out_2_iw_issued_partial_dgen = dis_uops_2_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_iw_p1_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_iw_p1_speculative_child = dis_uops_2_bits_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_iw_p1_speculative_child = dis_uops_2_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_iw_p2_speculative_child; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_iw_p2_speculative_child = dis_uops_2_bits_iw_p2_speculative_child; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_iw_p2_speculative_child = dis_uops_2_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p1_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p1_bypass_hint = dis_uops_2_bits_iw_p1_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p1_bypass_hint = dis_uops_2_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p2_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p2_bypass_hint = dis_uops_2_bits_iw_p2_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p2_bypass_hint = dis_uops_2_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg dis_uops_2_bits_iw_p3_bypass_hint; // @[lsu.scala:352:23] wire ldq_uop_out_2_iw_p3_bypass_hint = dis_uops_2_bits_iw_p3_bypass_hint; // @[util.scala:104:23] wire stq_uop_out_2_iw_p3_bypass_hint = dis_uops_2_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_dis_col_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_dis_col_sel = dis_uops_2_bits_dis_col_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_dis_col_sel = dis_uops_2_bits_dis_col_sel; // @[util.scala:104:23] reg [15:0] dis_uops_2_bits_br_mask; // @[lsu.scala:352:23] reg [3:0] dis_uops_2_bits_br_tag; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_2_br_tag = dis_uops_2_bits_br_tag; // @[util.scala:104:23] wire [3:0] stq_uop_out_2_br_tag = dis_uops_2_bits_br_tag; // @[util.scala:104:23] reg [3:0] dis_uops_2_bits_br_type; // @[lsu.scala:352:23] wire [3:0] ldq_uop_out_2_br_type = dis_uops_2_bits_br_type; // @[util.scala:104:23] wire [3:0] stq_uop_out_2_br_type = dis_uops_2_bits_br_type; // @[util.scala:104:23] reg dis_uops_2_bits_is_sfb; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sfb = dis_uops_2_bits_is_sfb; // @[util.scala:104:23] wire stq_uop_out_2_is_sfb = dis_uops_2_bits_is_sfb; // @[util.scala:104:23] reg dis_uops_2_bits_is_fence; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_fence = dis_uops_2_bits_is_fence; // @[util.scala:104:23] wire stq_uop_out_2_is_fence = dis_uops_2_bits_is_fence; // @[util.scala:104:23] reg dis_uops_2_bits_is_fencei; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_fencei = dis_uops_2_bits_is_fencei; // @[util.scala:104:23] wire stq_uop_out_2_is_fencei = dis_uops_2_bits_is_fencei; // @[util.scala:104:23] reg dis_uops_2_bits_is_sfence; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sfence = dis_uops_2_bits_is_sfence; // @[util.scala:104:23] wire stq_uop_out_2_is_sfence = dis_uops_2_bits_is_sfence; // @[util.scala:104:23] reg dis_uops_2_bits_is_amo; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_amo = dis_uops_2_bits_is_amo; // @[util.scala:104:23] wire stq_uop_out_2_is_amo = dis_uops_2_bits_is_amo; // @[util.scala:104:23] reg dis_uops_2_bits_is_eret; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_eret = dis_uops_2_bits_is_eret; // @[util.scala:104:23] wire stq_uop_out_2_is_eret = dis_uops_2_bits_is_eret; // @[util.scala:104:23] reg dis_uops_2_bits_is_sys_pc2epc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_sys_pc2epc = dis_uops_2_bits_is_sys_pc2epc; // @[util.scala:104:23] wire stq_uop_out_2_is_sys_pc2epc = dis_uops_2_bits_is_sys_pc2epc; // @[util.scala:104:23] reg dis_uops_2_bits_is_rocc; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_rocc = dis_uops_2_bits_is_rocc; // @[util.scala:104:23] wire stq_uop_out_2_is_rocc = dis_uops_2_bits_is_rocc; // @[util.scala:104:23] reg dis_uops_2_bits_is_mov; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_mov = dis_uops_2_bits_is_mov; // @[util.scala:104:23] wire stq_uop_out_2_is_mov = dis_uops_2_bits_is_mov; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ftq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ftq_idx = dis_uops_2_bits_ftq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ftq_idx = dis_uops_2_bits_ftq_idx; // @[util.scala:104:23] reg dis_uops_2_bits_edge_inst; // @[lsu.scala:352:23] wire ldq_uop_out_2_edge_inst = dis_uops_2_bits_edge_inst; // @[util.scala:104:23] wire stq_uop_out_2_edge_inst = dis_uops_2_bits_edge_inst; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_pc_lob; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_pc_lob = dis_uops_2_bits_pc_lob; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_pc_lob = dis_uops_2_bits_pc_lob; // @[util.scala:104:23] reg dis_uops_2_bits_taken; // @[lsu.scala:352:23] wire ldq_uop_out_2_taken = dis_uops_2_bits_taken; // @[util.scala:104:23] wire stq_uop_out_2_taken = dis_uops_2_bits_taken; // @[util.scala:104:23] reg dis_uops_2_bits_imm_rename; // @[lsu.scala:352:23] wire ldq_uop_out_2_imm_rename = dis_uops_2_bits_imm_rename; // @[util.scala:104:23] wire stq_uop_out_2_imm_rename = dis_uops_2_bits_imm_rename; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_imm_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_imm_sel = dis_uops_2_bits_imm_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_imm_sel = dis_uops_2_bits_imm_sel; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_pimm; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_pimm = dis_uops_2_bits_pimm; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_pimm = dis_uops_2_bits_pimm; // @[util.scala:104:23] reg [19:0] dis_uops_2_bits_imm_packed; // @[lsu.scala:352:23] wire [19:0] ldq_uop_out_2_imm_packed = dis_uops_2_bits_imm_packed; // @[util.scala:104:23] wire [19:0] stq_uop_out_2_imm_packed = dis_uops_2_bits_imm_packed; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_op1_sel; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_op1_sel = dis_uops_2_bits_op1_sel; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_op1_sel = dis_uops_2_bits_op1_sel; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_op2_sel; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_op2_sel = dis_uops_2_bits_op2_sel; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_op2_sel = dis_uops_2_bits_op2_sel; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ldst; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ldst = dis_uops_2_bits_fp_ctrl_ldst; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ldst = dis_uops_2_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_wen; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_wen = dis_uops_2_bits_fp_ctrl_wen; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_wen = dis_uops_2_bits_fp_ctrl_wen; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren1; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren1 = dis_uops_2_bits_fp_ctrl_ren1; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren1 = dis_uops_2_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren2; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren2 = dis_uops_2_bits_fp_ctrl_ren2; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren2 = dis_uops_2_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_ren3; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_ren3 = dis_uops_2_bits_fp_ctrl_ren3; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_ren3 = dis_uops_2_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_swap12; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_swap12 = dis_uops_2_bits_fp_ctrl_swap12; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_swap12 = dis_uops_2_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_swap23; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_swap23 = dis_uops_2_bits_fp_ctrl_swap23; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_swap23 = dis_uops_2_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_ctrl_typeTagIn; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_ctrl_typeTagIn = dis_uops_2_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_ctrl_typeTagIn = dis_uops_2_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_ctrl_typeTagOut; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_ctrl_typeTagOut = dis_uops_2_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_ctrl_typeTagOut = dis_uops_2_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fromint; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fromint = dis_uops_2_bits_fp_ctrl_fromint; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fromint = dis_uops_2_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_toint; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_toint = dis_uops_2_bits_fp_ctrl_toint; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_toint = dis_uops_2_bits_fp_ctrl_toint; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fastpipe; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fastpipe = dis_uops_2_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fastpipe = dis_uops_2_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_fma; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_fma = dis_uops_2_bits_fp_ctrl_fma; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_fma = dis_uops_2_bits_fp_ctrl_fma; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_div; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_div = dis_uops_2_bits_fp_ctrl_div; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_div = dis_uops_2_bits_fp_ctrl_div; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_sqrt; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_sqrt = dis_uops_2_bits_fp_ctrl_sqrt; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_sqrt = dis_uops_2_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_wflags; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_wflags = dis_uops_2_bits_fp_ctrl_wflags; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_wflags = dis_uops_2_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg dis_uops_2_bits_fp_ctrl_vec; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_ctrl_vec = dis_uops_2_bits_fp_ctrl_vec; // @[util.scala:104:23] wire stq_uop_out_2_fp_ctrl_vec = dis_uops_2_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_rob_idx; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_rob_idx = dis_uops_2_bits_rob_idx; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_rob_idx = dis_uops_2_bits_rob_idx; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ldq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ldq_idx = dis_uops_2_bits_ldq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ldq_idx = dis_uops_2_bits_ldq_idx; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_stq_idx; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_stq_idx = dis_uops_2_bits_stq_idx; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_stq_idx = dis_uops_2_bits_stq_idx; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_rxq_idx; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_rxq_idx = dis_uops_2_bits_rxq_idx; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_rxq_idx = dis_uops_2_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_pdst = dis_uops_2_bits_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_pdst = dis_uops_2_bits_pdst; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs1; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs1 = dis_uops_2_bits_prs1; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs1 = dis_uops_2_bits_prs1; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs2; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs2 = dis_uops_2_bits_prs2; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs2 = dis_uops_2_bits_prs2; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_prs3; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_prs3 = dis_uops_2_bits_prs3; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_prs3 = dis_uops_2_bits_prs3; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_ppred; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_ppred = dis_uops_2_bits_ppred; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_ppred = dis_uops_2_bits_ppred; // @[util.scala:104:23] reg dis_uops_2_bits_prs1_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs1_busy = dis_uops_2_bits_prs1_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs1_busy = dis_uops_2_bits_prs1_busy; // @[util.scala:104:23] reg dis_uops_2_bits_prs2_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs2_busy = dis_uops_2_bits_prs2_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs2_busy = dis_uops_2_bits_prs2_busy; // @[util.scala:104:23] reg dis_uops_2_bits_prs3_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_prs3_busy = dis_uops_2_bits_prs3_busy; // @[util.scala:104:23] wire stq_uop_out_2_prs3_busy = dis_uops_2_bits_prs3_busy; // @[util.scala:104:23] reg dis_uops_2_bits_ppred_busy; // @[lsu.scala:352:23] wire ldq_uop_out_2_ppred_busy = dis_uops_2_bits_ppred_busy; // @[util.scala:104:23] wire stq_uop_out_2_ppred_busy = dis_uops_2_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] dis_uops_2_bits_stale_pdst; // @[lsu.scala:352:23] wire [6:0] ldq_uop_out_2_stale_pdst = dis_uops_2_bits_stale_pdst; // @[util.scala:104:23] wire [6:0] stq_uop_out_2_stale_pdst = dis_uops_2_bits_stale_pdst; // @[util.scala:104:23] reg dis_uops_2_bits_exception; // @[lsu.scala:352:23] wire ldq_uop_out_2_exception = dis_uops_2_bits_exception; // @[util.scala:104:23] wire stq_uop_out_2_exception = dis_uops_2_bits_exception; // @[util.scala:104:23] reg [63:0] dis_uops_2_bits_exc_cause; // @[lsu.scala:352:23] wire [63:0] ldq_uop_out_2_exc_cause = dis_uops_2_bits_exc_cause; // @[util.scala:104:23] wire [63:0] stq_uop_out_2_exc_cause = dis_uops_2_bits_exc_cause; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_mem_cmd; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_mem_cmd = dis_uops_2_bits_mem_cmd; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_mem_cmd = dis_uops_2_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_mem_size; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_mem_size = dis_uops_2_bits_mem_size; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_mem_size = dis_uops_2_bits_mem_size; // @[util.scala:104:23] reg dis_uops_2_bits_mem_signed; // @[lsu.scala:352:23] wire ldq_uop_out_2_mem_signed = dis_uops_2_bits_mem_signed; // @[util.scala:104:23] wire stq_uop_out_2_mem_signed = dis_uops_2_bits_mem_signed; // @[util.scala:104:23] reg dis_uops_2_bits_uses_ldq; // @[lsu.scala:352:23] wire ldq_uop_out_2_uses_ldq = dis_uops_2_bits_uses_ldq; // @[util.scala:104:23] wire stq_uop_out_2_uses_ldq = dis_uops_2_bits_uses_ldq; // @[util.scala:104:23] reg dis_uops_2_bits_uses_stq; // @[lsu.scala:352:23] wire ldq_uop_out_2_uses_stq = dis_uops_2_bits_uses_stq; // @[util.scala:104:23] wire stq_uop_out_2_uses_stq = dis_uops_2_bits_uses_stq; // @[util.scala:104:23] reg dis_uops_2_bits_is_unique; // @[lsu.scala:352:23] wire ldq_uop_out_2_is_unique = dis_uops_2_bits_is_unique; // @[util.scala:104:23] wire stq_uop_out_2_is_unique = dis_uops_2_bits_is_unique; // @[util.scala:104:23] reg dis_uops_2_bits_flush_on_commit; // @[lsu.scala:352:23] wire ldq_uop_out_2_flush_on_commit = dis_uops_2_bits_flush_on_commit; // @[util.scala:104:23] wire stq_uop_out_2_flush_on_commit = dis_uops_2_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_csr_cmd; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_csr_cmd = dis_uops_2_bits_csr_cmd; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_csr_cmd = dis_uops_2_bits_csr_cmd; // @[util.scala:104:23] reg dis_uops_2_bits_ldst_is_rs1; // @[lsu.scala:352:23] wire ldq_uop_out_2_ldst_is_rs1 = dis_uops_2_bits_ldst_is_rs1; // @[util.scala:104:23] wire stq_uop_out_2_ldst_is_rs1 = dis_uops_2_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_ldst; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_ldst = dis_uops_2_bits_ldst; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_ldst = dis_uops_2_bits_ldst; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs1; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs1 = dis_uops_2_bits_lrs1; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs1 = dis_uops_2_bits_lrs1; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs2; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs2 = dis_uops_2_bits_lrs2; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs2 = dis_uops_2_bits_lrs2; // @[util.scala:104:23] reg [5:0] dis_uops_2_bits_lrs3; // @[lsu.scala:352:23] wire [5:0] ldq_uop_out_2_lrs3 = dis_uops_2_bits_lrs3; // @[util.scala:104:23] wire [5:0] stq_uop_out_2_lrs3 = dis_uops_2_bits_lrs3; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_dst_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_dst_rtype = dis_uops_2_bits_dst_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_dst_rtype = dis_uops_2_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_lrs1_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_lrs1_rtype = dis_uops_2_bits_lrs1_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_lrs1_rtype = dis_uops_2_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_lrs2_rtype; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_lrs2_rtype = dis_uops_2_bits_lrs2_rtype; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_lrs2_rtype = dis_uops_2_bits_lrs2_rtype; // @[util.scala:104:23] reg dis_uops_2_bits_frs3_en; // @[lsu.scala:352:23] wire ldq_uop_out_2_frs3_en = dis_uops_2_bits_frs3_en; // @[util.scala:104:23] wire stq_uop_out_2_frs3_en = dis_uops_2_bits_frs3_en; // @[util.scala:104:23] reg dis_uops_2_bits_fcn_dw; // @[lsu.scala:352:23] wire ldq_uop_out_2_fcn_dw = dis_uops_2_bits_fcn_dw; // @[util.scala:104:23] wire stq_uop_out_2_fcn_dw = dis_uops_2_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] dis_uops_2_bits_fcn_op; // @[lsu.scala:352:23] wire [4:0] ldq_uop_out_2_fcn_op = dis_uops_2_bits_fcn_op; // @[util.scala:104:23] wire [4:0] stq_uop_out_2_fcn_op = dis_uops_2_bits_fcn_op; // @[util.scala:104:23] reg dis_uops_2_bits_fp_val; // @[lsu.scala:352:23] wire ldq_uop_out_2_fp_val = dis_uops_2_bits_fp_val; // @[util.scala:104:23] wire stq_uop_out_2_fp_val = dis_uops_2_bits_fp_val; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_fp_rm; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_fp_rm = dis_uops_2_bits_fp_rm; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_fp_rm = dis_uops_2_bits_fp_rm; // @[util.scala:104:23] reg [1:0] dis_uops_2_bits_fp_typ; // @[lsu.scala:352:23] wire [1:0] ldq_uop_out_2_fp_typ = dis_uops_2_bits_fp_typ; // @[util.scala:104:23] wire [1:0] stq_uop_out_2_fp_typ = dis_uops_2_bits_fp_typ; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_pf_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_pf_if = dis_uops_2_bits_xcpt_pf_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_pf_if = dis_uops_2_bits_xcpt_pf_if; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_ae_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_ae_if = dis_uops_2_bits_xcpt_ae_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_ae_if = dis_uops_2_bits_xcpt_ae_if; // @[util.scala:104:23] reg dis_uops_2_bits_xcpt_ma_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_xcpt_ma_if = dis_uops_2_bits_xcpt_ma_if; // @[util.scala:104:23] wire stq_uop_out_2_xcpt_ma_if = dis_uops_2_bits_xcpt_ma_if; // @[util.scala:104:23] reg dis_uops_2_bits_bp_debug_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_bp_debug_if = dis_uops_2_bits_bp_debug_if; // @[util.scala:104:23] wire stq_uop_out_2_bp_debug_if = dis_uops_2_bits_bp_debug_if; // @[util.scala:104:23] reg dis_uops_2_bits_bp_xcpt_if; // @[lsu.scala:352:23] wire ldq_uop_out_2_bp_xcpt_if = dis_uops_2_bits_bp_xcpt_if; // @[util.scala:104:23] wire stq_uop_out_2_bp_xcpt_if = dis_uops_2_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_debug_fsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_debug_fsrc = dis_uops_2_bits_debug_fsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_debug_fsrc = dis_uops_2_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] dis_uops_2_bits_debug_tsrc; // @[lsu.scala:352:23] wire [2:0] ldq_uop_out_2_debug_tsrc = dis_uops_2_bits_debug_tsrc; // @[util.scala:104:23] wire [2:0] stq_uop_out_2_debug_tsrc = dis_uops_2_bits_debug_tsrc; // @[util.scala:104:23] wire [1:0] _GEN_0 = {stq_valid_2, stq_valid_1}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_lo_hi = _GEN_0; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_lo_lo = {live_store_mask_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_1 = {stq_valid_5, stq_valid_4}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_lo_hi_hi = _GEN_1; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_lo_hi = {live_store_mask_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_lo_lo = {live_store_mask_lo_lo_hi, live_store_mask_lo_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_2 = {stq_valid_8, stq_valid_7}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_lo_hi = _GEN_2; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_hi_lo = {live_store_mask_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_3 = {stq_valid_11, stq_valid_10}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_lo_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35] wire [1:0] stq_valids_lo_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_lo_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_lo_hi_hi_hi = _GEN_3; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_lo_hi_hi = {live_store_mask_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_lo_hi = {live_store_mask_lo_hi_hi, live_store_mask_lo_hi_lo}; // @[lsu.scala:354:35] wire [11:0] live_store_mask_lo = {live_store_mask_lo_hi, live_store_mask_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_4 = {stq_valid_14, stq_valid_13}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_lo_hi = _GEN_4; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_lo_lo = {live_store_mask_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_5 = {stq_valid_17, stq_valid_16}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_lo_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_lo_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_lo_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_lo_hi_hi = _GEN_5; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_lo_hi = {live_store_mask_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_hi_lo = {live_store_mask_hi_lo_hi, live_store_mask_hi_lo_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_6 = {stq_valid_20, stq_valid_19}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_lo_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_lo_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_lo_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_lo_hi = _GEN_6; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_hi_lo = {live_store_mask_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :354:35] wire [1:0] _GEN_7 = {stq_valid_23, stq_valid_22}; // @[lsu.scala:251:32, :354:35] wire [1:0] live_store_mask_hi_hi_hi_hi; // @[lsu.scala:354:35] assign live_store_mask_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35] wire [1:0] stq_valids_hi_hi_hi_hi; // @[lsu.scala:362:31] assign stq_valids_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :362:31] wire [1:0] fast_stq_valids_hi_hi_hi_hi; // @[lsu.scala:1342:35] assign fast_stq_valids_hi_hi_hi_hi = _GEN_7; // @[lsu.scala:354:35, :1342:35] wire [2:0] live_store_mask_hi_hi_hi = {live_store_mask_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :354:35] wire [5:0] live_store_mask_hi_hi = {live_store_mask_hi_hi_hi, live_store_mask_hi_hi_lo}; // @[lsu.scala:354:35] wire [11:0] live_store_mask_hi = {live_store_mask_hi_hi, live_store_mask_hi_lo}; // @[lsu.scala:354:35] wire [23:0] _live_store_mask_T = {live_store_mask_hi, live_store_mask_lo}; // @[lsu.scala:354:35] wire [1:0] _GEN_8 = {dis_stq_oh_2, dis_stq_oh_1}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_lo_hi_1 = _GEN_8; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_lo_hi_1 = _GEN_8; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_lo_lo_1 = {live_store_mask_lo_lo_lo_hi_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_9 = {dis_stq_oh_5, dis_stq_oh_4}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_lo_hi_hi_1 = _GEN_9; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_lo_hi_hi_1 = _GEN_9; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_lo_hi_1 = {live_store_mask_lo_lo_hi_hi_1, dis_stq_oh_3}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_lo_lo_1 = {live_store_mask_lo_lo_hi_1, live_store_mask_lo_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_10 = {dis_stq_oh_8, dis_stq_oh_7}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_lo_hi_1 = _GEN_10; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_lo_hi_1 = _GEN_10; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_hi_lo_1 = {live_store_mask_lo_hi_lo_hi_1, dis_stq_oh_6}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_11 = {dis_stq_oh_11, dis_stq_oh_10}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_lo_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_lo_hi_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55] wire [1:0] stq_valids_lo_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_lo_hi_hi_hi_1 = _GEN_11; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_lo_hi_hi_1 = {live_store_mask_lo_hi_hi_hi_1, dis_stq_oh_9}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_lo_hi_1 = {live_store_mask_lo_hi_hi_1, live_store_mask_lo_hi_lo_1}; // @[lsu.scala:354:55] wire [11:0] live_store_mask_lo_1 = {live_store_mask_lo_hi_1, live_store_mask_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_12 = {dis_stq_oh_14, dis_stq_oh_13}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_lo_hi_1 = _GEN_12; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_lo_hi_1 = _GEN_12; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_lo_lo_1 = {live_store_mask_hi_lo_lo_hi_1, dis_stq_oh_12}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_13 = {dis_stq_oh_17, dis_stq_oh_16}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_lo_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_lo_hi_hi_1 = _GEN_13; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_lo_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_lo_hi_hi_1 = _GEN_13; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_lo_hi_1 = {live_store_mask_hi_lo_hi_hi_1, dis_stq_oh_15}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_hi_lo_1 = {live_store_mask_hi_lo_hi_1, live_store_mask_hi_lo_lo_1}; // @[lsu.scala:354:55] wire [1:0] _GEN_14 = {dis_stq_oh_20, dis_stq_oh_19}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_lo_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_lo_hi_1 = _GEN_14; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_lo_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_lo_hi_1 = _GEN_14; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_hi_lo_1 = {live_store_mask_hi_hi_lo_hi_1, dis_stq_oh_18}; // @[lsu.scala:349:23, :354:55] wire [1:0] _GEN_15 = {dis_stq_oh_23, dis_stq_oh_22}; // @[lsu.scala:349:23, :354:55] wire [1:0] live_store_mask_hi_hi_hi_hi_1; // @[lsu.scala:354:55] assign live_store_mask_hi_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55] wire [1:0] stq_valids_hi_hi_hi_hi_1; // @[lsu.scala:362:51] assign stq_valids_hi_hi_hi_hi_1 = _GEN_15; // @[lsu.scala:354:55, :362:51] wire [2:0] live_store_mask_hi_hi_hi_1 = {live_store_mask_hi_hi_hi_hi_1, dis_stq_oh_21}; // @[lsu.scala:349:23, :354:55] wire [5:0] live_store_mask_hi_hi_1 = {live_store_mask_hi_hi_hi_1, live_store_mask_hi_hi_lo_1}; // @[lsu.scala:354:55] wire [11:0] live_store_mask_hi_1 = {live_store_mask_hi_hi_1, live_store_mask_hi_lo_1}; // @[lsu.scala:354:55] wire [23:0] _live_store_mask_T_1 = {live_store_mask_hi_1, live_store_mask_lo_1}; // @[lsu.scala:354:55] wire [23:0] live_store_mask = _live_store_mask_T | _live_store_mask_T_1; // @[lsu.scala:354:{35,42,55}] wire [31:0] _next_live_store_mask_T_1 = ~_next_live_store_mask_T; // @[lsu.scala:355:{65,71}] wire [31:0] _next_live_store_mask_T_2 = {8'h0, _next_live_store_mask_T_1[23:0] & live_store_mask}; // @[lsu.scala:354:42, :355:{63,65}] wire [31:0] next_live_store_mask = clear_store ? _next_live_store_mask_T_2 : {8'h0, live_store_mask}; // @[lsu.scala:318:33, :354:42, :355:{33,63}] wire [31:0] _ldq_tail_oh_T = 32'h1 << ldq_tail; // @[OneHot.scala:58:35] wire [23:0] ldq_tail_oh = _ldq_tail_oh_T[23:0]; // @[OneHot.scala:58:35] wire [1:0] _GEN_16 = {ldq_valid_2, ldq_valid_1}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_lo_hi = _GEN_16; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_lo_hi_1 = _GEN_16; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_lo_lo = {ldq_valids_lo_lo_lo_hi, ldq_valid_0}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_17 = {ldq_valid_5, ldq_valid_4}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_lo_hi_hi = _GEN_17; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_lo_hi_hi_1 = _GEN_17; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_lo_hi = {ldq_valids_lo_lo_hi_hi, ldq_valid_3}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_lo_lo = {ldq_valids_lo_lo_hi, ldq_valids_lo_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_18 = {ldq_valid_8, ldq_valid_7}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_lo_hi = _GEN_18; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_lo_hi_1 = _GEN_18; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_hi_lo = {ldq_valids_lo_hi_lo_hi, ldq_valid_6}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_19 = {ldq_valid_11, ldq_valid_10}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_lo_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_lo_hi_hi_hi = _GEN_19; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_lo_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_lo_hi_hi_hi_1 = _GEN_19; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_lo_hi_hi = {ldq_valids_lo_hi_hi_hi, ldq_valid_9}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_lo_hi = {ldq_valids_lo_hi_hi, ldq_valids_lo_hi_lo}; // @[lsu.scala:360:31] wire [11:0] ldq_valids_lo = {ldq_valids_lo_hi, ldq_valids_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_20 = {ldq_valid_14, ldq_valid_13}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_lo_hi = _GEN_20; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_lo_hi_1 = _GEN_20; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_lo_lo = {ldq_valids_hi_lo_lo_hi, ldq_valid_12}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_21 = {ldq_valid_17, ldq_valid_16}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_lo_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_lo_hi_hi = _GEN_21; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_lo_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_lo_hi_hi_1 = _GEN_21; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_lo_hi = {ldq_valids_hi_lo_hi_hi, ldq_valid_15}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_hi_lo = {ldq_valids_hi_lo_hi, ldq_valids_hi_lo_lo}; // @[lsu.scala:360:31] wire [1:0] _GEN_22 = {ldq_valid_20, ldq_valid_19}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_lo_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_lo_hi = _GEN_22; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_lo_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_lo_hi_1 = _GEN_22; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_hi_lo = {ldq_valids_hi_hi_lo_hi, ldq_valid_18}; // @[lsu.scala:218:36, :360:31] wire [1:0] _GEN_23 = {ldq_valid_23, ldq_valid_22}; // @[lsu.scala:218:36, :360:31] wire [1:0] ldq_valids_hi_hi_hi_hi; // @[lsu.scala:360:31] assign ldq_valids_hi_hi_hi_hi = _GEN_23; // @[lsu.scala:360:31] wire [1:0] ld_xcpt_valid_hi_hi_hi_hi_1; // @[lsu.scala:1437:58] assign ld_xcpt_valid_hi_hi_hi_hi_1 = _GEN_23; // @[lsu.scala:360:31, :1437:58] wire [2:0] ldq_valids_hi_hi_hi = {ldq_valids_hi_hi_hi_hi, ldq_valid_21}; // @[lsu.scala:218:36, :360:31] wire [5:0] ldq_valids_hi_hi = {ldq_valids_hi_hi_hi, ldq_valids_hi_hi_lo}; // @[lsu.scala:360:31] wire [11:0] ldq_valids_hi = {ldq_valids_hi_hi, ldq_valids_hi_lo}; // @[lsu.scala:360:31] wire [23:0] _ldq_valids_T = {ldq_valids_hi, ldq_valids_lo}; // @[lsu.scala:360:31] wire [1:0] ldq_valids_lo_lo_lo_hi_1 = {dis_ldq_oh_2, dis_ldq_oh_1}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_lo_lo_1 = {ldq_valids_lo_lo_lo_hi_1, dis_ldq_oh_0}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_lo_hi_hi_1 = {dis_ldq_oh_5, dis_ldq_oh_4}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_lo_hi_1 = {ldq_valids_lo_lo_hi_hi_1, dis_ldq_oh_3}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_lo_lo_1 = {ldq_valids_lo_lo_hi_1, ldq_valids_lo_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_lo_hi_lo_hi_1 = {dis_ldq_oh_8, dis_ldq_oh_7}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_hi_lo_1 = {ldq_valids_lo_hi_lo_hi_1, dis_ldq_oh_6}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_lo_hi_hi_hi_1 = {dis_ldq_oh_11, dis_ldq_oh_10}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_lo_hi_hi_1 = {ldq_valids_lo_hi_hi_hi_1, dis_ldq_oh_9}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_lo_hi_1 = {ldq_valids_lo_hi_hi_1, ldq_valids_lo_hi_lo_1}; // @[lsu.scala:360:51] wire [11:0] ldq_valids_lo_1 = {ldq_valids_lo_hi_1, ldq_valids_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_lo_lo_hi_1 = {dis_ldq_oh_14, dis_ldq_oh_13}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_lo_lo_1 = {ldq_valids_hi_lo_lo_hi_1, dis_ldq_oh_12}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_lo_hi_hi_1 = {dis_ldq_oh_17, dis_ldq_oh_16}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_lo_hi_1 = {ldq_valids_hi_lo_hi_hi_1, dis_ldq_oh_15}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_hi_lo_1 = {ldq_valids_hi_lo_hi_1, ldq_valids_hi_lo_lo_1}; // @[lsu.scala:360:51] wire [1:0] ldq_valids_hi_hi_lo_hi_1 = {dis_ldq_oh_20, dis_ldq_oh_19}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_hi_lo_1 = {ldq_valids_hi_hi_lo_hi_1, dis_ldq_oh_18}; // @[lsu.scala:348:23, :360:51] wire [1:0] ldq_valids_hi_hi_hi_hi_1 = {dis_ldq_oh_23, dis_ldq_oh_22}; // @[lsu.scala:348:23, :360:51] wire [2:0] ldq_valids_hi_hi_hi_1 = {ldq_valids_hi_hi_hi_hi_1, dis_ldq_oh_21}; // @[lsu.scala:348:23, :360:51] wire [5:0] ldq_valids_hi_hi_1 = {ldq_valids_hi_hi_hi_1, ldq_valids_hi_hi_lo_1}; // @[lsu.scala:360:51] wire [11:0] ldq_valids_hi_1 = {ldq_valids_hi_hi_1, ldq_valids_hi_lo_1}; // @[lsu.scala:360:51] wire [23:0] _ldq_valids_T_1 = {ldq_valids_hi_1, ldq_valids_lo_1}; // @[lsu.scala:360:51] wire [23:0] ldq_valids = _ldq_valids_T | _ldq_valids_T_1; // @[lsu.scala:360:{31,38,51}] wire [31:0] _stq_tail_oh_T = 32'h1 << stq_tail; // @[OneHot.scala:58:35] wire [23:0] stq_tail_oh = _stq_tail_oh_T[23:0]; // @[OneHot.scala:58:35] wire [2:0] stq_valids_lo_lo_lo = {stq_valids_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_lo_lo_hi = {stq_valids_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_lo_lo = {stq_valids_lo_lo_hi, stq_valids_lo_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_lo_hi_lo = {stq_valids_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_lo_hi_hi = {stq_valids_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_lo_hi = {stq_valids_lo_hi_hi, stq_valids_lo_hi_lo}; // @[lsu.scala:362:31] wire [11:0] stq_valids_lo = {stq_valids_lo_hi, stq_valids_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_hi_lo_lo = {stq_valids_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_hi_lo_hi = {stq_valids_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_hi_lo = {stq_valids_hi_lo_hi, stq_valids_hi_lo_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_hi_hi_lo = {stq_valids_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :362:31] wire [2:0] stq_valids_hi_hi_hi = {stq_valids_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :362:31] wire [5:0] stq_valids_hi_hi = {stq_valids_hi_hi_hi, stq_valids_hi_hi_lo}; // @[lsu.scala:362:31] wire [11:0] stq_valids_hi = {stq_valids_hi_hi, stq_valids_hi_lo}; // @[lsu.scala:362:31] wire [23:0] _stq_valids_T = {stq_valids_hi, stq_valids_lo}; // @[lsu.scala:362:31] wire [2:0] stq_valids_lo_lo_lo_1 = {stq_valids_lo_lo_lo_hi_1, dis_stq_oh_0}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_lo_lo_hi_1 = {stq_valids_lo_lo_hi_hi_1, dis_stq_oh_3}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_lo_lo_1 = {stq_valids_lo_lo_hi_1, stq_valids_lo_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_lo_hi_lo_1 = {stq_valids_lo_hi_lo_hi_1, dis_stq_oh_6}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_lo_hi_hi_1 = {stq_valids_lo_hi_hi_hi_1, dis_stq_oh_9}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_lo_hi_1 = {stq_valids_lo_hi_hi_1, stq_valids_lo_hi_lo_1}; // @[lsu.scala:362:51] wire [11:0] stq_valids_lo_1 = {stq_valids_lo_hi_1, stq_valids_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_hi_lo_lo_1 = {stq_valids_hi_lo_lo_hi_1, dis_stq_oh_12}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_hi_lo_hi_1 = {stq_valids_hi_lo_hi_hi_1, dis_stq_oh_15}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_hi_lo_1 = {stq_valids_hi_lo_hi_1, stq_valids_hi_lo_lo_1}; // @[lsu.scala:362:51] wire [2:0] stq_valids_hi_hi_lo_1 = {stq_valids_hi_hi_lo_hi_1, dis_stq_oh_18}; // @[lsu.scala:349:23, :362:51] wire [2:0] stq_valids_hi_hi_hi_1 = {stq_valids_hi_hi_hi_hi_1, dis_stq_oh_21}; // @[lsu.scala:349:23, :362:51] wire [5:0] stq_valids_hi_hi_1 = {stq_valids_hi_hi_hi_1, stq_valids_hi_hi_lo_1}; // @[lsu.scala:362:51] wire [11:0] stq_valids_hi_1 = {stq_valids_hi_hi_1, stq_valids_hi_lo_1}; // @[lsu.scala:362:51] wire [23:0] _stq_valids_T_1 = {stq_valids_hi_1, stq_valids_lo_1}; // @[lsu.scala:362:51] wire [23:0] stq_valids = _stq_valids_T | _stq_valids_T_1; // @[lsu.scala:362:{31,38,51}] wire _GEN_24 = stq_valid_0 | stq_valid_1; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T; // @[lsu.scala:364:40] assign _stq_nonempty_T = _GEN_24; // @[lsu.scala:364:40] wire _io_hellacache_store_pending_T; // @[lsu.scala:1804:52] assign _io_hellacache_store_pending_T = _GEN_24; // @[lsu.scala:364:40, :1804:52] wire _stq_nonempty_T_1 = _stq_nonempty_T | stq_valid_2; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_2 = _stq_nonempty_T_1 | stq_valid_3; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_3 = _stq_nonempty_T_2 | stq_valid_4; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_4 = _stq_nonempty_T_3 | stq_valid_5; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_5 = _stq_nonempty_T_4 | stq_valid_6; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_6 = _stq_nonempty_T_5 | stq_valid_7; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_7 = _stq_nonempty_T_6 | stq_valid_8; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_8 = _stq_nonempty_T_7 | stq_valid_9; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_9 = _stq_nonempty_T_8 | stq_valid_10; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_10 = _stq_nonempty_T_9 | stq_valid_11; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_11 = _stq_nonempty_T_10 | stq_valid_12; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_12 = _stq_nonempty_T_11 | stq_valid_13; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_13 = _stq_nonempty_T_12 | stq_valid_14; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_14 = _stq_nonempty_T_13 | stq_valid_15; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_15 = _stq_nonempty_T_14 | stq_valid_16; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_16 = _stq_nonempty_T_15 | stq_valid_17; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_17 = _stq_nonempty_T_16 | stq_valid_18; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_18 = _stq_nonempty_T_17 | stq_valid_19; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_19 = _stq_nonempty_T_18 | stq_valid_20; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_20 = _stq_nonempty_T_19 | stq_valid_21; // @[lsu.scala:251:32, :364:40] wire _stq_nonempty_T_21 = _stq_nonempty_T_20 | stq_valid_22; // @[lsu.scala:251:32, :364:40] wire stq_nonempty = _stq_nonempty_T_21 | stq_valid_23; // @[lsu.scala:251:32, :364:40] wire [23:0] _ldq_full_T = ldq_tail_oh & ldq_valids; // @[lsu.scala:359:39, :360:38, :369:33] assign ldq_full = |_ldq_full_T; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_0_0 = ldq_full; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T = stq_tail_oh & stq_valids; // @[lsu.scala:361:39, :362:38, :373:33] assign stq_full = |_stq_full_T; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_0_0 = stq_full; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val = _dis_ld_val_T & _dis_ld_val_T_1; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T = io_core_dis_uops_0_valid_0 & io_core_dis_uops_0_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_1 = ~io_core_dis_uops_0_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val = _dis_st_val_T & _dis_st_val_T_1; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_0_valid_T = dis_ld_val | dis_st_val; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap = ldq_tail == 5'h17; // @[util.scala:213:25] wire [31:0] _GEN_25 = {{ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_0}, {ldq_valid_23}, {ldq_valid_22}, {ldq_valid_21}, {ldq_valid_20}, {ldq_valid_19}, {ldq_valid_18}, {ldq_valid_17}, {ldq_valid_16}, {ldq_valid_15}, {ldq_valid_14}, {ldq_valid_13}, {ldq_valid_12}, {ldq_valid_11}, {ldq_valid_10}, {ldq_valid_9}, {ldq_valid_8}, {ldq_valid_7}, {ldq_valid_6}, {ldq_valid_5}, {ldq_valid_4}, {ldq_valid_3}, {ldq_valid_2}, {ldq_valid_1}, {ldq_valid_0}}; // @[lsu.scala:218:36, :387:15] wire wrap_1 = stq_tail == 5'h17; // @[util.scala:213:25] wire [31:0] _GEN_26 = {{stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_0}, {stq_valid_23}, {stq_valid_22}, {stq_valid_21}, {stq_valid_20}, {stq_valid_19}, {stq_valid_18}, {stq_valid_17}, {stq_valid_16}, {stq_valid_15}, {stq_valid_14}, {stq_valid_13}, {stq_valid_12}, {stq_valid_11}, {stq_valid_10}, {stq_valid_9}, {stq_valid_8}, {stq_valid_7}, {stq_valid_6}, {stq_valid_5}, {stq_valid_4}, {stq_valid_3}, {stq_valid_2}, {stq_valid_1}, {stq_valid_0}}; // @[lsu.scala:251:32, :392:15] wire _T_16 = dis_uops_0_valid & dis_uops_0_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_27 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_0_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T; // @[util.scala:126:51] assign _ldq_valid_T = _GEN_27; // @[util.scala:126:51] wire [15:0] _stq_valid_T; // @[util.scala:126:51] assign _stq_valid_T = _GEN_27; // @[util.scala:126:51] wire _ldq_valid_T_1 = |_ldq_valid_T; // @[util.scala:126:{51,59}] wire _ldq_valid_T_2 = _ldq_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_3 = ~_ldq_valid_T_2; // @[util.scala:61:61] wire _GEN_28 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h0; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_29 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h1; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_30 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h2; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_31 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h3; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_32 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h4; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_33 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h5; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_34 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h6; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_35 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h7; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_36 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h8; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_37 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h9; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_38 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hA; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_39 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hB; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_40 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hC; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_41 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hD; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_42 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hE; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_43 = _T_16 & dis_uops_0_bits_ldq_idx == 5'hF; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_44 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h10; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_45 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h11; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_46 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h12; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_47 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h13; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_48 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h14; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_49 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h15; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_50 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h16; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire _GEN_51 = _T_16 & dis_uops_0_bits_ldq_idx == 5'h17; // @[lsu.scala:218:36, :352:23, :394:{29,59}, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] ldq_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _ldq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign ldq_uop_out_br_mask = _ldq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire _stq_valid_T_1 = |_stq_valid_T; // @[util.scala:126:{51,59}] wire _stq_valid_T_2 = _stq_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_3 = ~_stq_valid_T_2; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] stq_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_1 = dis_uops_0_bits_br_mask & _stq_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign stq_uop_out_br_mask = _stq_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [4:0] _T_20 = wrap ? 5'h0 : ldq_tail + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_ldq_idx_1_0 = dis_ld_val ? _T_20 : ldq_tail; // @[util.scala:214:10] wire [5:0] _stq_tail_plus_sum_T = {1'h0, stq_tail}; // @[util.scala:174:20, :214:28] wire [4:0] _T_27 = wrap_1 ? 5'h0 : stq_tail + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_stq_idx_1_0 = dis_st_val ? _T_27 : stq_tail; // @[util.scala:214:10] wire [22:0] _out_T = ldq_tail_oh[22:0]; // @[util.scala:256:25] wire _out_T_1 = ldq_tail_oh[23]; // @[util.scala:256:40] wire [23:0] out = {_out_T, _out_T_1}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_38 = io_core_dis_uops_0_bits_uses_ldq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out : ldq_tail_oh; // @[util.scala:256:18] wire [22:0] _out_T_2 = stq_tail_oh[22:0]; // @[util.scala:256:25] wire _out_T_3 = stq_tail_oh[23]; // @[util.scala:256:40] wire [23:0] out_1 = {_out_T_2, _out_T_3}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_43 = io_core_dis_uops_0_bits_uses_stq_0 & ~io_core_dis_uops_0_bits_exception_0 ? out_1 : stq_tail_oh; // @[util.scala:256:18] wire [23:0] _ldq_full_T_1 = _T_38 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_1 = |_ldq_full_T_1; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_1_0 = ldq_full_1; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T_1 = _T_43 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_1 = |_stq_full_T_1; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_1_0 = stq_full_1; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_1 = _dis_ld_val_T_2 & _dis_ld_val_T_3; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_2 = io_core_dis_uops_1_valid_0 & io_core_dis_uops_1_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_3 = ~io_core_dis_uops_1_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_1 = _dis_st_val_T_2 & _dis_st_val_T_3; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_1_valid_T = dis_ld_val_1 | dis_st_val_1; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap_2 = io_core_dis_ldq_idx_1_0 == 5'h17; // @[util.scala:213:25] wire wrap_3 = io_core_dis_stq_idx_1_0 == 5'h17; // @[util.scala:213:25] wire _T_60 = dis_uops_1_valid & dis_uops_1_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_52 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_1_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T_4; // @[util.scala:126:51] assign _ldq_valid_T_4 = _GEN_52; // @[util.scala:126:51] wire [15:0] _stq_valid_T_4; // @[util.scala:126:51] assign _stq_valid_T_4 = _GEN_52; // @[util.scala:126:51] wire _ldq_valid_T_5 = |_ldq_valid_T_4; // @[util.scala:126:{51,59}] wire _ldq_valid_T_6 = _ldq_valid_T_5 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_7 = ~_ldq_valid_T_6; // @[util.scala:61:61] wire _GEN_53 = dis_uops_1_bits_ldq_idx == 5'h0; // @[lsu.scala:352:23, :396:42] wire _GEN_54 = dis_uops_1_bits_ldq_idx == 5'h1; // @[lsu.scala:352:23, :396:42] wire _GEN_55 = dis_uops_1_bits_ldq_idx == 5'h2; // @[lsu.scala:352:23, :396:42] wire _GEN_56 = dis_uops_1_bits_ldq_idx == 5'h3; // @[lsu.scala:352:23, :396:42] wire _GEN_57 = dis_uops_1_bits_ldq_idx == 5'h4; // @[lsu.scala:352:23, :396:42] wire _GEN_58 = dis_uops_1_bits_ldq_idx == 5'h5; // @[lsu.scala:352:23, :396:42] wire _GEN_59 = dis_uops_1_bits_ldq_idx == 5'h6; // @[lsu.scala:352:23, :396:42] wire _GEN_60 = dis_uops_1_bits_ldq_idx == 5'h7; // @[lsu.scala:352:23, :396:42] wire _GEN_61 = dis_uops_1_bits_ldq_idx == 5'h8; // @[lsu.scala:352:23, :396:42] wire _GEN_62 = dis_uops_1_bits_ldq_idx == 5'h9; // @[lsu.scala:352:23, :396:42] wire _GEN_63 = dis_uops_1_bits_ldq_idx == 5'hA; // @[lsu.scala:352:23, :396:42] wire _GEN_64 = dis_uops_1_bits_ldq_idx == 5'hB; // @[lsu.scala:352:23, :396:42] wire _GEN_65 = dis_uops_1_bits_ldq_idx == 5'hC; // @[lsu.scala:352:23, :396:42] wire _GEN_66 = dis_uops_1_bits_ldq_idx == 5'hD; // @[lsu.scala:352:23, :396:42] wire _GEN_67 = dis_uops_1_bits_ldq_idx == 5'hE; // @[lsu.scala:352:23, :396:42] wire _GEN_68 = dis_uops_1_bits_ldq_idx == 5'hF; // @[lsu.scala:352:23, :396:42] wire _GEN_69 = dis_uops_1_bits_ldq_idx == 5'h10; // @[lsu.scala:352:23, :396:42] wire _GEN_70 = dis_uops_1_bits_ldq_idx == 5'h11; // @[lsu.scala:352:23, :396:42] wire _GEN_71 = dis_uops_1_bits_ldq_idx == 5'h12; // @[lsu.scala:352:23, :396:42] wire _GEN_72 = dis_uops_1_bits_ldq_idx == 5'h13; // @[lsu.scala:352:23, :396:42] wire _GEN_73 = dis_uops_1_bits_ldq_idx == 5'h14; // @[lsu.scala:352:23, :396:42] wire _GEN_74 = dis_uops_1_bits_ldq_idx == 5'h15; // @[lsu.scala:352:23, :396:42] wire _GEN_75 = dis_uops_1_bits_ldq_idx == 5'h16; // @[lsu.scala:352:23, :396:42] wire _GEN_76 = dis_uops_1_bits_ldq_idx == 5'h17; // @[lsu.scala:352:23, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] ldq_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _ldq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign ldq_uop_out_1_br_mask = _ldq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _GEN_77 = _GEN_53 | _GEN_28; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_78 = _GEN_54 | _GEN_29; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_79 = _GEN_55 | _GEN_30; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_80 = _GEN_56 | _GEN_31; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_81 = _GEN_57 | _GEN_32; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_82 = _GEN_58 | _GEN_33; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_83 = _GEN_59 | _GEN_34; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_84 = _GEN_60 | _GEN_35; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_85 = _GEN_61 | _GEN_36; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_86 = _GEN_62 | _GEN_37; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_87 = _GEN_63 | _GEN_38; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_88 = _GEN_64 | _GEN_39; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_89 = _GEN_65 | _GEN_40; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_90 = _GEN_66 | _GEN_41; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_91 = _GEN_67 | _GEN_42; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_92 = _GEN_68 | _GEN_43; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_93 = _GEN_69 | _GEN_44; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_94 = _GEN_70 | _GEN_45; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_95 = _GEN_71 | _GEN_46; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_96 = _GEN_72 | _GEN_47; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_97 = _GEN_73 | _GEN_48; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_98 = _GEN_74 | _GEN_49; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_99 = _GEN_75 | _GEN_50; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _GEN_100 = _GEN_76 | _GEN_51; // @[lsu.scala:218:36, :220:36, :394:59, :396:42, :399:42] wire _stq_valid_T_5 = |_stq_valid_T_4; // @[util.scala:126:{51,59}] wire _stq_valid_T_6 = _stq_valid_T_5 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_7 = ~_stq_valid_T_6; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] stq_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_3 = dis_uops_1_bits_br_mask & _stq_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign stq_uop_out_1_br_mask = _stq_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire [4:0] _T_64 = wrap_2 ? 5'h0 : io_core_dis_ldq_idx_1_0 + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_ldq_idx_2_0 = dis_ld_val_1 ? _T_64 : io_core_dis_ldq_idx_1_0; // @[util.scala:214:10] wire [4:0] _T_71 = wrap_3 ? 5'h0 : io_core_dis_stq_idx_1_0 + 5'h1; // @[util.scala:213:25, :214:{10,28}] assign io_core_dis_stq_idx_2_0 = dis_st_val_1 ? _T_71 : io_core_dis_stq_idx_1_0; // @[util.scala:214:10] wire [22:0] _out_T_4 = _T_38[22:0]; // @[util.scala:256:25] wire _out_T_5 = _T_38[23]; // @[util.scala:256:40] wire [23:0] out_2 = {_out_T_4, _out_T_5}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_82 = io_core_dis_uops_1_bits_uses_ldq_0 & ~io_core_dis_uops_1_bits_exception_0 ? out_2 : _T_38; // @[util.scala:256:18] wire [22:0] _out_T_6 = _T_43[22:0]; // @[util.scala:256:25] wire _out_T_7 = _T_43[23]; // @[util.scala:256:40] wire [23:0] out_3 = {_out_T_6, _out_T_7}; // @[util.scala:256:{18,25,40}] wire [23:0] _T_87 = io_core_dis_uops_1_bits_uses_stq_0 & ~io_core_dis_uops_1_bits_exception_0 ? out_3 : _T_43; // @[util.scala:256:18] wire [23:0] _ldq_full_T_2 = _T_82 & ldq_valids; // @[lsu.scala:360:38, :369:33, :428:22] assign ldq_full_2 = |_ldq_full_T_2; // @[lsu.scala:369:{33,47}] assign io_core_ldq_full_2_0 = ldq_full_2; // @[lsu.scala:211:7, :369:47] wire [23:0] _stq_full_T_2 = _T_87 & stq_valids; // @[lsu.scala:362:38, :373:33, :430:22] assign stq_full_2 = |_stq_full_T_2; // @[lsu.scala:373:{33,47}] assign io_core_stq_full_2_0 = stq_full_2; // @[lsu.scala:211:7, :373:47] wire _dis_ld_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_ldq_0; // @[lsu.scala:211:7, :377:48] wire _dis_ld_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:211:7, :377:88] wire dis_ld_val_2 = _dis_ld_val_T_4 & _dis_ld_val_T_5; // @[lsu.scala:377:{48,85,88}] wire _dis_st_val_T_4 = io_core_dis_uops_2_valid_0 & io_core_dis_uops_2_bits_uses_stq_0; // @[lsu.scala:211:7, :378:48] wire _dis_st_val_T_5 = ~io_core_dis_uops_2_bits_exception_0; // @[lsu.scala:211:7, :377:88, :378:88] wire dis_st_val_2 = _dis_st_val_T_4 & _dis_st_val_T_5; // @[lsu.scala:378:{48,85,88}] wire _dis_uops_2_valid_T = dis_ld_val_2 | dis_st_val_2; // @[lsu.scala:377:85, :378:85, :380:37] wire wrap_4 = io_core_dis_ldq_idx_2_0 == 5'h17; // @[util.scala:213:25] wire wrap_5 = io_core_dis_stq_idx_2_0 == 5'h17; // @[util.scala:213:25] wire _T_104 = dis_uops_2_valid & dis_uops_2_bits_uses_ldq; // @[lsu.scala:352:23, :394:29] wire [15:0] _GEN_101 = io_core_brupdate_b1_mispredict_mask_0 & dis_uops_2_bits_br_mask; // @[util.scala:126:51] wire [15:0] _ldq_valid_T_8; // @[util.scala:126:51] assign _ldq_valid_T_8 = _GEN_101; // @[util.scala:126:51] wire [15:0] _stq_valid_T_8; // @[util.scala:126:51] assign _stq_valid_T_8 = _GEN_101; // @[util.scala:126:51] wire _ldq_valid_T_9 = |_ldq_valid_T_8; // @[util.scala:126:{51,59}] wire _ldq_valid_T_10 = _ldq_valid_T_9 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _ldq_valid_T_11 = ~_ldq_valid_T_10; // @[util.scala:61:61] wire _GEN_102 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h0; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_103 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h1; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_104 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h2; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_105 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h3; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_106 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h4; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_107 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h5; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_108 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h6; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_109 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h7; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_110 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h8; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_111 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h9; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_112 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hA; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_113 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hB; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_114 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hC; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_115 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hD; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_116 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hE; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_117 = _T_104 & dis_uops_2_bits_ldq_idx == 5'hF; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_118 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h10; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_119 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h11; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_120 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h12; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_121 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h13; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_122 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h14; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_123 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h15; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_124 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h16; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire _GEN_125 = _T_104 & dis_uops_2_bits_ldq_idx == 5'h17; // @[lsu.scala:352:23, :394:{29,59}, :396:42] wire [15:0] _ldq_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] ldq_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _ldq_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _ldq_uop_out_br_mask_T_5 = dis_uops_2_bits_br_mask & _ldq_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign ldq_uop_out_2_br_mask = _ldq_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire _stq_valid_T_9 = |_stq_valid_T_8; // @[util.scala:126:{51,59}] wire _stq_valid_T_10 = _stq_valid_T_9 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _stq_valid_T_11 = ~_stq_valid_T_10; // @[util.scala:61:61] wire [15:0] _stq_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] stq_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _stq_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _stq_uop_out_br_mask_T_5 = dis_uops_2_bits_br_mask & _stq_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign stq_uop_out_2_br_mask = _stq_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire [22:0] _out_T_8 = _T_82[22:0]; // @[util.scala:256:25] wire _out_T_9 = _T_82[23]; // @[util.scala:256:40] wire [23:0] out_4 = {_out_T_8, _out_T_9}; // @[util.scala:256:{18,25,40}] wire [22:0] _out_T_10 = _T_87[22:0]; // @[util.scala:256:25] wire _out_T_11 = _T_87[23]; // @[util.scala:256:40] wire [23:0] out_5 = {_out_T_10, _out_T_11}; // @[util.scala:256:{18,25,40}] wire stq_enq_e_e_valid = _GEN_26[stq_execute_head]; // @[lsu.scala:262:17, :283:29, :392:15, :438:42] wire _io_core_fencei_rdy_T = ~stq_nonempty; // @[lsu.scala:364:40, :446:28] assign _io_core_fencei_rdy_T_1 = _io_core_fencei_rdy_T & io_dmem_ordered_0; // @[lsu.scala:211:7, :446:{28,42}] assign io_core_fencei_rdy_0 = _io_core_fencei_rdy_T_1; // @[lsu.scala:211:7, :446:42] wire mem_xcpt_valid; // @[lsu.scala:457:29] wire [3:0] mem_xcpt_cause; // @[lsu.scala:458:29] wire mem_xcpt_uop_iq_type_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_iq_type_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_0; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_4; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_5; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_6; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_7; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_8; // @[lsu.scala:459:29] wire mem_xcpt_uop_fu_code_9; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_inst; // @[lsu.scala:459:29] wire [31:0] mem_xcpt_uop_debug_inst; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rvc; // @[lsu.scala:459:29] wire [39:0] mem_xcpt_uop_debug_pc; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29] wire mem_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29] wire [15:0] mem_xcpt_uop_br_mask; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_tag; // @[lsu.scala:459:29] wire [3:0] mem_xcpt_uop_br_type; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfb; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_fencei; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sfence; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_amo; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_eret; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_rocc; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_mov; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ftq_idx; // @[lsu.scala:459:29] wire mem_xcpt_uop_edge_inst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_pc_lob; // @[lsu.scala:459:29] wire mem_xcpt_uop_taken; // @[lsu.scala:459:29] wire mem_xcpt_uop_imm_rename; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_imm_sel; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_pimm; // @[lsu.scala:459:29] wire [19:0] mem_xcpt_uop_imm_packed; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_op1_sel; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_op2_sel; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_rob_idx; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ldq_idx; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_stq_idx; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_rxq_idx; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_pdst; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs1; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs2; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_prs3; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_ppred; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs1_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs2_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_prs3_busy; // @[lsu.scala:459:29] wire mem_xcpt_uop_ppred_busy; // @[lsu.scala:459:29] wire [6:0] mem_xcpt_uop_stale_pdst; // @[lsu.scala:459:29] wire mem_xcpt_uop_exception; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_uop_exc_cause; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_mem_cmd; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_mem_size; // @[lsu.scala:459:29] wire mem_xcpt_uop_mem_signed; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_ldq; // @[lsu.scala:459:29] wire mem_xcpt_uop_uses_stq; // @[lsu.scala:459:29] wire mem_xcpt_uop_is_unique; // @[lsu.scala:459:29] wire mem_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_csr_cmd; // @[lsu.scala:459:29] wire mem_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_ldst; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs1; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs2; // @[lsu.scala:459:29] wire [5:0] mem_xcpt_uop_lrs3; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_dst_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29] wire mem_xcpt_uop_frs3_en; // @[lsu.scala:459:29] wire mem_xcpt_uop_fcn_dw; // @[lsu.scala:459:29] wire [4:0] mem_xcpt_uop_fcn_op; // @[lsu.scala:459:29] wire mem_xcpt_uop_fp_val; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_fp_rm; // @[lsu.scala:459:29] wire [1:0] mem_xcpt_uop_fp_typ; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29] wire mem_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29] wire [2:0] mem_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29] wire [63:0] mem_xcpt_vaddr; // @[lsu.scala:460:29] wire will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_exec_0; // @[lsu.scala:469:39] wire will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_agen_0; // @[lsu.scala:470:41] wire will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_agen_0; // @[lsu.scala:471:41] wire will_fire_sfence_0_will_fire; // @[lsu.scala:657:65] wire will_fire_sfence_0; // @[lsu.scala:472:41] wire will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_incoming_0; // @[lsu.scala:473:41] wire _exe_passthr_T = will_fire_hella_incoming_0; // @[lsu.scala:473:41, :756:23] wire will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_hella_wakeup_0; // @[lsu.scala:474:41] wire will_fire_release_0_will_fire; // @[lsu.scala:657:65] assign io_dmem_release_ready_0 = will_fire_release_0; // @[lsu.scala:211:7, :475:41] wire will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_retry_0; // @[lsu.scala:476:41] wire will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_retry_0; // @[lsu.scala:477:41] wire will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_fast_0; // @[lsu.scala:478:41] wire will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65] wire will_fire_store_commit_slow_0; // @[lsu.scala:479:41] wire will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65] wire will_fire_load_wakeup_0; // @[lsu.scala:480:41] wire block_load_mask_0; // @[lsu.scala:488:36] wire block_load_mask_1; // @[lsu.scala:488:36] wire block_load_mask_2; // @[lsu.scala:488:36] wire block_load_mask_3; // @[lsu.scala:488:36] wire block_load_mask_4; // @[lsu.scala:488:36] wire block_load_mask_5; // @[lsu.scala:488:36] wire block_load_mask_6; // @[lsu.scala:488:36] wire block_load_mask_7; // @[lsu.scala:488:36] wire block_load_mask_8; // @[lsu.scala:488:36] wire block_load_mask_9; // @[lsu.scala:488:36] wire block_load_mask_10; // @[lsu.scala:488:36] wire block_load_mask_11; // @[lsu.scala:488:36] wire block_load_mask_12; // @[lsu.scala:488:36] wire block_load_mask_13; // @[lsu.scala:488:36] wire block_load_mask_14; // @[lsu.scala:488:36] wire block_load_mask_15; // @[lsu.scala:488:36] wire block_load_mask_16; // @[lsu.scala:488:36] wire block_load_mask_17; // @[lsu.scala:488:36] wire block_load_mask_18; // @[lsu.scala:488:36] wire block_load_mask_19; // @[lsu.scala:488:36] wire block_load_mask_20; // @[lsu.scala:488:36] wire block_load_mask_21; // @[lsu.scala:488:36] wire block_load_mask_22; // @[lsu.scala:488:36] wire block_load_mask_23; // @[lsu.scala:488:36] reg p1_block_load_mask_0; // @[lsu.scala:489:35] reg p1_block_load_mask_1; // @[lsu.scala:489:35] reg p1_block_load_mask_2; // @[lsu.scala:489:35] reg p1_block_load_mask_3; // @[lsu.scala:489:35] reg p1_block_load_mask_4; // @[lsu.scala:489:35] reg p1_block_load_mask_5; // @[lsu.scala:489:35] reg p1_block_load_mask_6; // @[lsu.scala:489:35] reg p1_block_load_mask_7; // @[lsu.scala:489:35] reg p1_block_load_mask_8; // @[lsu.scala:489:35] reg p1_block_load_mask_9; // @[lsu.scala:489:35] reg p1_block_load_mask_10; // @[lsu.scala:489:35] reg p1_block_load_mask_11; // @[lsu.scala:489:35] reg p1_block_load_mask_12; // @[lsu.scala:489:35] reg p1_block_load_mask_13; // @[lsu.scala:489:35] reg p1_block_load_mask_14; // @[lsu.scala:489:35] reg p1_block_load_mask_15; // @[lsu.scala:489:35] reg p1_block_load_mask_16; // @[lsu.scala:489:35] reg p1_block_load_mask_17; // @[lsu.scala:489:35] reg p1_block_load_mask_18; // @[lsu.scala:489:35] reg p1_block_load_mask_19; // @[lsu.scala:489:35] reg p1_block_load_mask_20; // @[lsu.scala:489:35] reg p1_block_load_mask_21; // @[lsu.scala:489:35] reg p1_block_load_mask_22; // @[lsu.scala:489:35] reg p1_block_load_mask_23; // @[lsu.scala:489:35] reg p2_block_load_mask_0; // @[lsu.scala:490:35] reg p2_block_load_mask_1; // @[lsu.scala:490:35] reg p2_block_load_mask_2; // @[lsu.scala:490:35] reg p2_block_load_mask_3; // @[lsu.scala:490:35] reg p2_block_load_mask_4; // @[lsu.scala:490:35] reg p2_block_load_mask_5; // @[lsu.scala:490:35] reg p2_block_load_mask_6; // @[lsu.scala:490:35] reg p2_block_load_mask_7; // @[lsu.scala:490:35] reg p2_block_load_mask_8; // @[lsu.scala:490:35] reg p2_block_load_mask_9; // @[lsu.scala:490:35] reg p2_block_load_mask_10; // @[lsu.scala:490:35] reg p2_block_load_mask_11; // @[lsu.scala:490:35] reg p2_block_load_mask_12; // @[lsu.scala:490:35] reg p2_block_load_mask_13; // @[lsu.scala:490:35] reg p2_block_load_mask_14; // @[lsu.scala:490:35] reg p2_block_load_mask_15; // @[lsu.scala:490:35] reg p2_block_load_mask_16; // @[lsu.scala:490:35] reg p2_block_load_mask_17; // @[lsu.scala:490:35] reg p2_block_load_mask_18; // @[lsu.scala:490:35] reg p2_block_load_mask_19; // @[lsu.scala:490:35] reg p2_block_load_mask_20; // @[lsu.scala:490:35] reg p2_block_load_mask_21; // @[lsu.scala:490:35] reg p2_block_load_mask_22; // @[lsu.scala:490:35] reg p2_block_load_mask_23; // @[lsu.scala:490:35] wire [6:0] _stq_tail_plus_sum_T_2 = {1'h0, _stq_tail_plus_sum_T} + 7'h6; // @[util.scala:174:{20,38}] wire [5:0] stq_tail_plus_sum = _stq_tail_plus_sum_T_2[5:0]; // @[util.scala:174:38] wire _stq_tail_plus_T = stq_tail_plus_sum > 6'h17; // @[util.scala:174:38, :175:15] wire [6:0] _stq_tail_plus_T_1 = {1'h0, stq_tail_plus_sum} - 7'h18; // @[util.scala:174:38, :176:15] wire [5:0] _stq_tail_plus_T_2 = _stq_tail_plus_T_1[5:0]; // @[util.scala:176:15] wire [5:0] stq_tail_plus = _stq_tail_plus_T ? _stq_tail_plus_T_2 : stq_tail_plus_sum; // @[util.scala:174:38, :175:{10,15}, :176:15] wire [5:0] _GEN_126 = {1'h0, stq_head}; // @[util.scala:364:52] wire _stq_almost_full_T = _GEN_126 < stq_tail_plus; // @[util.scala:175:10, :364:52] wire _stq_almost_full_T_1 = stq_head < stq_tail; // @[util.scala:364:64] wire _stq_almost_full_T_2 = _stq_almost_full_T ^ _stq_almost_full_T_1; // @[util.scala:364:{52,58,64}] wire _stq_almost_full_T_3 = stq_tail_plus < _stq_tail_plus_sum_T; // @[util.scala:174:20, :175:10, :364:78] wire _stq_almost_full_T_4 = _stq_almost_full_T_2 ^ _stq_almost_full_T_3; // @[util.scala:364:{58,72,78}] reg stq_almost_full; // @[lsu.scala:494:32] wire store_needs_order; // @[lsu.scala:498:35] wire _ldq_incoming_e_WIRE_valid = ldq_incoming_e_e_valid; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_inst = ldq_incoming_e_e_bits_uop_inst; // @[lsu.scala:233:17, :501:48] wire [31:0] _ldq_incoming_e_WIRE_bits_uop_debug_inst = ldq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rvc = ldq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_uop_debug_pc = ldq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_0 = ldq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_1 = ldq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_2 = ldq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iq_type_3 = ldq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_0 = ldq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_1 = ldq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_2 = ldq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_3 = ldq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_4 = ldq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_5 = ldq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_6 = ldq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_7 = ldq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_8 = ldq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fu_code_9 = ldq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued = ldq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = ldq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = ldq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = ldq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_dis_col_sel = ldq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :501:48] wire [15:0] _ldq_incoming_e_WIRE_bits_uop_br_mask = ldq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_tag = ldq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :501:48] wire [3:0] _ldq_incoming_e_WIRE_bits_uop_br_type = ldq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfb = ldq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fence = ldq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_fencei = ldq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sfence = ldq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_amo = ldq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_eret = ldq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = ldq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_rocc = ldq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_mov = ldq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ftq_idx = ldq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_edge_inst = ldq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_pc_lob = ldq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_taken = ldq_incoming_e_e_bits_uop_taken; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_imm_rename = ldq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_imm_sel = ldq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_pimm = ldq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :501:48] wire [19:0] _ldq_incoming_e_WIRE_bits_uop_imm_packed = ldq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_op1_sel = ldq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_op2_sel = ldq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = ldq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = ldq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = ldq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = ldq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = ldq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div = ldq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = ldq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = ldq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_rob_idx = ldq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ldq_idx = ldq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_stq_idx = ldq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_rxq_idx = ldq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_pdst = ldq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs1 = ldq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs2 = ldq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_prs3 = ldq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_ppred = ldq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs1_busy = ldq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs2_busy = ldq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_prs3_busy = ldq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ppred_busy = ldq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :501:48] wire [6:0] _ldq_incoming_e_WIRE_bits_uop_stale_pdst = ldq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_exception = ldq_incoming_e_e_bits_uop_exception; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_uop_exc_cause = ldq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_mem_cmd = ldq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_mem_size = ldq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_mem_signed = ldq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_ldq = ldq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_uses_stq = ldq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_is_unique = ldq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_flush_on_commit = ldq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_csr_cmd = ldq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = ldq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_ldst = ldq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs1 = ldq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs2 = ldq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :501:48] wire [5:0] _ldq_incoming_e_WIRE_bits_uop_lrs3 = ldq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_dst_rtype = ldq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype = ldq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype = ldq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_frs3_en = ldq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fcn_dw = ldq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_uop_fcn_op = ldq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_fp_val = ldq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_fp_rm = ldq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :501:48] wire [1:0] _ldq_incoming_e_WIRE_bits_uop_fp_typ = ldq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if = ldq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if = ldq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if = ldq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_debug_if = ldq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if = ldq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_fsrc = ldq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :501:48] wire [2:0] _ldq_incoming_e_WIRE_bits_uop_debug_tsrc = ldq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_valid = ldq_incoming_e_e_bits_addr_valid; // @[lsu.scala:233:17, :501:48] wire [39:0] _ldq_incoming_e_WIRE_bits_addr_bits = ldq_incoming_e_e_bits_addr_bits; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_virtual = ldq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_addr_is_uncacheable = ldq_incoming_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_executed = ldq_incoming_e_e_bits_executed; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_succeeded = ldq_incoming_e_e_bits_succeeded; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_order_fail = ldq_incoming_e_e_bits_order_fail; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_observed = ldq_incoming_e_e_bits_observed; // @[lsu.scala:233:17, :501:48] wire [23:0] _ldq_incoming_e_WIRE_bits_st_dep_mask = ldq_incoming_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :501:48] wire [7:0] _ldq_incoming_e_WIRE_bits_ld_byte_mask = ldq_incoming_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :501:48] wire _ldq_incoming_e_WIRE_bits_forward_std_val = ldq_incoming_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :501:48] wire [4:0] _ldq_incoming_e_WIRE_bits_forward_stq_idx = ldq_incoming_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :501:48] wire [63:0] _ldq_incoming_e_WIRE_bits_debug_wb_data = ldq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :501:48] assign ldq_incoming_e_e_valid = _GEN_25[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :234:32, :321:49, :387:15] wire [31:0][31:0] _GEN_127 = {{ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_0_inst}, {ldq_uop_23_inst}, {ldq_uop_22_inst}, {ldq_uop_21_inst}, {ldq_uop_20_inst}, {ldq_uop_19_inst}, {ldq_uop_18_inst}, {ldq_uop_17_inst}, {ldq_uop_16_inst}, {ldq_uop_15_inst}, {ldq_uop_14_inst}, {ldq_uop_13_inst}, {ldq_uop_12_inst}, {ldq_uop_11_inst}, {ldq_uop_10_inst}, {ldq_uop_9_inst}, {ldq_uop_8_inst}, {ldq_uop_7_inst}, {ldq_uop_6_inst}, {ldq_uop_5_inst}, {ldq_uop_4_inst}, {ldq_uop_3_inst}, {ldq_uop_2_inst}, {ldq_uop_1_inst}, {ldq_uop_0_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_inst = _GEN_127[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][31:0] _GEN_128 = {{ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_0_debug_inst}, {ldq_uop_23_debug_inst}, {ldq_uop_22_debug_inst}, {ldq_uop_21_debug_inst}, {ldq_uop_20_debug_inst}, {ldq_uop_19_debug_inst}, {ldq_uop_18_debug_inst}, {ldq_uop_17_debug_inst}, {ldq_uop_16_debug_inst}, {ldq_uop_15_debug_inst}, {ldq_uop_14_debug_inst}, {ldq_uop_13_debug_inst}, {ldq_uop_12_debug_inst}, {ldq_uop_11_debug_inst}, {ldq_uop_10_debug_inst}, {ldq_uop_9_debug_inst}, {ldq_uop_8_debug_inst}, {ldq_uop_7_debug_inst}, {ldq_uop_6_debug_inst}, {ldq_uop_5_debug_inst}, {ldq_uop_4_debug_inst}, {ldq_uop_3_debug_inst}, {ldq_uop_2_debug_inst}, {ldq_uop_1_debug_inst}, {ldq_uop_0_debug_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_inst = _GEN_128[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_129 = {{ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_0_is_rvc}, {ldq_uop_23_is_rvc}, {ldq_uop_22_is_rvc}, {ldq_uop_21_is_rvc}, {ldq_uop_20_is_rvc}, {ldq_uop_19_is_rvc}, {ldq_uop_18_is_rvc}, {ldq_uop_17_is_rvc}, {ldq_uop_16_is_rvc}, {ldq_uop_15_is_rvc}, {ldq_uop_14_is_rvc}, {ldq_uop_13_is_rvc}, {ldq_uop_12_is_rvc}, {ldq_uop_11_is_rvc}, {ldq_uop_10_is_rvc}, {ldq_uop_9_is_rvc}, {ldq_uop_8_is_rvc}, {ldq_uop_7_is_rvc}, {ldq_uop_6_is_rvc}, {ldq_uop_5_is_rvc}, {ldq_uop_4_is_rvc}, {ldq_uop_3_is_rvc}, {ldq_uop_2_is_rvc}, {ldq_uop_1_is_rvc}, {ldq_uop_0_is_rvc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rvc = _GEN_129[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][39:0] _GEN_130 = {{ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_0_debug_pc}, {ldq_uop_23_debug_pc}, {ldq_uop_22_debug_pc}, {ldq_uop_21_debug_pc}, {ldq_uop_20_debug_pc}, {ldq_uop_19_debug_pc}, {ldq_uop_18_debug_pc}, {ldq_uop_17_debug_pc}, {ldq_uop_16_debug_pc}, {ldq_uop_15_debug_pc}, {ldq_uop_14_debug_pc}, {ldq_uop_13_debug_pc}, {ldq_uop_12_debug_pc}, {ldq_uop_11_debug_pc}, {ldq_uop_10_debug_pc}, {ldq_uop_9_debug_pc}, {ldq_uop_8_debug_pc}, {ldq_uop_7_debug_pc}, {ldq_uop_6_debug_pc}, {ldq_uop_5_debug_pc}, {ldq_uop_4_debug_pc}, {ldq_uop_3_debug_pc}, {ldq_uop_2_debug_pc}, {ldq_uop_1_debug_pc}, {ldq_uop_0_debug_pc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_pc = _GEN_130[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_131 = {{ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_0_iq_type_0}, {ldq_uop_23_iq_type_0}, {ldq_uop_22_iq_type_0}, {ldq_uop_21_iq_type_0}, {ldq_uop_20_iq_type_0}, {ldq_uop_19_iq_type_0}, {ldq_uop_18_iq_type_0}, {ldq_uop_17_iq_type_0}, {ldq_uop_16_iq_type_0}, {ldq_uop_15_iq_type_0}, {ldq_uop_14_iq_type_0}, {ldq_uop_13_iq_type_0}, {ldq_uop_12_iq_type_0}, {ldq_uop_11_iq_type_0}, {ldq_uop_10_iq_type_0}, {ldq_uop_9_iq_type_0}, {ldq_uop_8_iq_type_0}, {ldq_uop_7_iq_type_0}, {ldq_uop_6_iq_type_0}, {ldq_uop_5_iq_type_0}, {ldq_uop_4_iq_type_0}, {ldq_uop_3_iq_type_0}, {ldq_uop_2_iq_type_0}, {ldq_uop_1_iq_type_0}, {ldq_uop_0_iq_type_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_0 = _GEN_131[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_132 = {{ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_0_iq_type_1}, {ldq_uop_23_iq_type_1}, {ldq_uop_22_iq_type_1}, {ldq_uop_21_iq_type_1}, {ldq_uop_20_iq_type_1}, {ldq_uop_19_iq_type_1}, {ldq_uop_18_iq_type_1}, {ldq_uop_17_iq_type_1}, {ldq_uop_16_iq_type_1}, {ldq_uop_15_iq_type_1}, {ldq_uop_14_iq_type_1}, {ldq_uop_13_iq_type_1}, {ldq_uop_12_iq_type_1}, {ldq_uop_11_iq_type_1}, {ldq_uop_10_iq_type_1}, {ldq_uop_9_iq_type_1}, {ldq_uop_8_iq_type_1}, {ldq_uop_7_iq_type_1}, {ldq_uop_6_iq_type_1}, {ldq_uop_5_iq_type_1}, {ldq_uop_4_iq_type_1}, {ldq_uop_3_iq_type_1}, {ldq_uop_2_iq_type_1}, {ldq_uop_1_iq_type_1}, {ldq_uop_0_iq_type_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_1 = _GEN_132[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_133 = {{ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_0_iq_type_2}, {ldq_uop_23_iq_type_2}, {ldq_uop_22_iq_type_2}, {ldq_uop_21_iq_type_2}, {ldq_uop_20_iq_type_2}, {ldq_uop_19_iq_type_2}, {ldq_uop_18_iq_type_2}, {ldq_uop_17_iq_type_2}, {ldq_uop_16_iq_type_2}, {ldq_uop_15_iq_type_2}, {ldq_uop_14_iq_type_2}, {ldq_uop_13_iq_type_2}, {ldq_uop_12_iq_type_2}, {ldq_uop_11_iq_type_2}, {ldq_uop_10_iq_type_2}, {ldq_uop_9_iq_type_2}, {ldq_uop_8_iq_type_2}, {ldq_uop_7_iq_type_2}, {ldq_uop_6_iq_type_2}, {ldq_uop_5_iq_type_2}, {ldq_uop_4_iq_type_2}, {ldq_uop_3_iq_type_2}, {ldq_uop_2_iq_type_2}, {ldq_uop_1_iq_type_2}, {ldq_uop_0_iq_type_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_2 = _GEN_133[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_134 = {{ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_0_iq_type_3}, {ldq_uop_23_iq_type_3}, {ldq_uop_22_iq_type_3}, {ldq_uop_21_iq_type_3}, {ldq_uop_20_iq_type_3}, {ldq_uop_19_iq_type_3}, {ldq_uop_18_iq_type_3}, {ldq_uop_17_iq_type_3}, {ldq_uop_16_iq_type_3}, {ldq_uop_15_iq_type_3}, {ldq_uop_14_iq_type_3}, {ldq_uop_13_iq_type_3}, {ldq_uop_12_iq_type_3}, {ldq_uop_11_iq_type_3}, {ldq_uop_10_iq_type_3}, {ldq_uop_9_iq_type_3}, {ldq_uop_8_iq_type_3}, {ldq_uop_7_iq_type_3}, {ldq_uop_6_iq_type_3}, {ldq_uop_5_iq_type_3}, {ldq_uop_4_iq_type_3}, {ldq_uop_3_iq_type_3}, {ldq_uop_2_iq_type_3}, {ldq_uop_1_iq_type_3}, {ldq_uop_0_iq_type_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iq_type_3 = _GEN_134[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_135 = {{ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_0_fu_code_0}, {ldq_uop_23_fu_code_0}, {ldq_uop_22_fu_code_0}, {ldq_uop_21_fu_code_0}, {ldq_uop_20_fu_code_0}, {ldq_uop_19_fu_code_0}, {ldq_uop_18_fu_code_0}, {ldq_uop_17_fu_code_0}, {ldq_uop_16_fu_code_0}, {ldq_uop_15_fu_code_0}, {ldq_uop_14_fu_code_0}, {ldq_uop_13_fu_code_0}, {ldq_uop_12_fu_code_0}, {ldq_uop_11_fu_code_0}, {ldq_uop_10_fu_code_0}, {ldq_uop_9_fu_code_0}, {ldq_uop_8_fu_code_0}, {ldq_uop_7_fu_code_0}, {ldq_uop_6_fu_code_0}, {ldq_uop_5_fu_code_0}, {ldq_uop_4_fu_code_0}, {ldq_uop_3_fu_code_0}, {ldq_uop_2_fu_code_0}, {ldq_uop_1_fu_code_0}, {ldq_uop_0_fu_code_0}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_0 = _GEN_135[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_136 = {{ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_0_fu_code_1}, {ldq_uop_23_fu_code_1}, {ldq_uop_22_fu_code_1}, {ldq_uop_21_fu_code_1}, {ldq_uop_20_fu_code_1}, {ldq_uop_19_fu_code_1}, {ldq_uop_18_fu_code_1}, {ldq_uop_17_fu_code_1}, {ldq_uop_16_fu_code_1}, {ldq_uop_15_fu_code_1}, {ldq_uop_14_fu_code_1}, {ldq_uop_13_fu_code_1}, {ldq_uop_12_fu_code_1}, {ldq_uop_11_fu_code_1}, {ldq_uop_10_fu_code_1}, {ldq_uop_9_fu_code_1}, {ldq_uop_8_fu_code_1}, {ldq_uop_7_fu_code_1}, {ldq_uop_6_fu_code_1}, {ldq_uop_5_fu_code_1}, {ldq_uop_4_fu_code_1}, {ldq_uop_3_fu_code_1}, {ldq_uop_2_fu_code_1}, {ldq_uop_1_fu_code_1}, {ldq_uop_0_fu_code_1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_1 = _GEN_136[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_137 = {{ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_0_fu_code_2}, {ldq_uop_23_fu_code_2}, {ldq_uop_22_fu_code_2}, {ldq_uop_21_fu_code_2}, {ldq_uop_20_fu_code_2}, {ldq_uop_19_fu_code_2}, {ldq_uop_18_fu_code_2}, {ldq_uop_17_fu_code_2}, {ldq_uop_16_fu_code_2}, {ldq_uop_15_fu_code_2}, {ldq_uop_14_fu_code_2}, {ldq_uop_13_fu_code_2}, {ldq_uop_12_fu_code_2}, {ldq_uop_11_fu_code_2}, {ldq_uop_10_fu_code_2}, {ldq_uop_9_fu_code_2}, {ldq_uop_8_fu_code_2}, {ldq_uop_7_fu_code_2}, {ldq_uop_6_fu_code_2}, {ldq_uop_5_fu_code_2}, {ldq_uop_4_fu_code_2}, {ldq_uop_3_fu_code_2}, {ldq_uop_2_fu_code_2}, {ldq_uop_1_fu_code_2}, {ldq_uop_0_fu_code_2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_2 = _GEN_137[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_138 = {{ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_0_fu_code_3}, {ldq_uop_23_fu_code_3}, {ldq_uop_22_fu_code_3}, {ldq_uop_21_fu_code_3}, {ldq_uop_20_fu_code_3}, {ldq_uop_19_fu_code_3}, {ldq_uop_18_fu_code_3}, {ldq_uop_17_fu_code_3}, {ldq_uop_16_fu_code_3}, {ldq_uop_15_fu_code_3}, {ldq_uop_14_fu_code_3}, {ldq_uop_13_fu_code_3}, {ldq_uop_12_fu_code_3}, {ldq_uop_11_fu_code_3}, {ldq_uop_10_fu_code_3}, {ldq_uop_9_fu_code_3}, {ldq_uop_8_fu_code_3}, {ldq_uop_7_fu_code_3}, {ldq_uop_6_fu_code_3}, {ldq_uop_5_fu_code_3}, {ldq_uop_4_fu_code_3}, {ldq_uop_3_fu_code_3}, {ldq_uop_2_fu_code_3}, {ldq_uop_1_fu_code_3}, {ldq_uop_0_fu_code_3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_3 = _GEN_138[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_139 = {{ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_0_fu_code_4}, {ldq_uop_23_fu_code_4}, {ldq_uop_22_fu_code_4}, {ldq_uop_21_fu_code_4}, {ldq_uop_20_fu_code_4}, {ldq_uop_19_fu_code_4}, {ldq_uop_18_fu_code_4}, {ldq_uop_17_fu_code_4}, {ldq_uop_16_fu_code_4}, {ldq_uop_15_fu_code_4}, {ldq_uop_14_fu_code_4}, {ldq_uop_13_fu_code_4}, {ldq_uop_12_fu_code_4}, {ldq_uop_11_fu_code_4}, {ldq_uop_10_fu_code_4}, {ldq_uop_9_fu_code_4}, {ldq_uop_8_fu_code_4}, {ldq_uop_7_fu_code_4}, {ldq_uop_6_fu_code_4}, {ldq_uop_5_fu_code_4}, {ldq_uop_4_fu_code_4}, {ldq_uop_3_fu_code_4}, {ldq_uop_2_fu_code_4}, {ldq_uop_1_fu_code_4}, {ldq_uop_0_fu_code_4}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_4 = _GEN_139[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_140 = {{ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_0_fu_code_5}, {ldq_uop_23_fu_code_5}, {ldq_uop_22_fu_code_5}, {ldq_uop_21_fu_code_5}, {ldq_uop_20_fu_code_5}, {ldq_uop_19_fu_code_5}, {ldq_uop_18_fu_code_5}, {ldq_uop_17_fu_code_5}, {ldq_uop_16_fu_code_5}, {ldq_uop_15_fu_code_5}, {ldq_uop_14_fu_code_5}, {ldq_uop_13_fu_code_5}, {ldq_uop_12_fu_code_5}, {ldq_uop_11_fu_code_5}, {ldq_uop_10_fu_code_5}, {ldq_uop_9_fu_code_5}, {ldq_uop_8_fu_code_5}, {ldq_uop_7_fu_code_5}, {ldq_uop_6_fu_code_5}, {ldq_uop_5_fu_code_5}, {ldq_uop_4_fu_code_5}, {ldq_uop_3_fu_code_5}, {ldq_uop_2_fu_code_5}, {ldq_uop_1_fu_code_5}, {ldq_uop_0_fu_code_5}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_5 = _GEN_140[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_141 = {{ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_0_fu_code_6}, {ldq_uop_23_fu_code_6}, {ldq_uop_22_fu_code_6}, {ldq_uop_21_fu_code_6}, {ldq_uop_20_fu_code_6}, {ldq_uop_19_fu_code_6}, {ldq_uop_18_fu_code_6}, {ldq_uop_17_fu_code_6}, {ldq_uop_16_fu_code_6}, {ldq_uop_15_fu_code_6}, {ldq_uop_14_fu_code_6}, {ldq_uop_13_fu_code_6}, {ldq_uop_12_fu_code_6}, {ldq_uop_11_fu_code_6}, {ldq_uop_10_fu_code_6}, {ldq_uop_9_fu_code_6}, {ldq_uop_8_fu_code_6}, {ldq_uop_7_fu_code_6}, {ldq_uop_6_fu_code_6}, {ldq_uop_5_fu_code_6}, {ldq_uop_4_fu_code_6}, {ldq_uop_3_fu_code_6}, {ldq_uop_2_fu_code_6}, {ldq_uop_1_fu_code_6}, {ldq_uop_0_fu_code_6}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_6 = _GEN_141[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_142 = {{ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_0_fu_code_7}, {ldq_uop_23_fu_code_7}, {ldq_uop_22_fu_code_7}, {ldq_uop_21_fu_code_7}, {ldq_uop_20_fu_code_7}, {ldq_uop_19_fu_code_7}, {ldq_uop_18_fu_code_7}, {ldq_uop_17_fu_code_7}, {ldq_uop_16_fu_code_7}, {ldq_uop_15_fu_code_7}, {ldq_uop_14_fu_code_7}, {ldq_uop_13_fu_code_7}, {ldq_uop_12_fu_code_7}, {ldq_uop_11_fu_code_7}, {ldq_uop_10_fu_code_7}, {ldq_uop_9_fu_code_7}, {ldq_uop_8_fu_code_7}, {ldq_uop_7_fu_code_7}, {ldq_uop_6_fu_code_7}, {ldq_uop_5_fu_code_7}, {ldq_uop_4_fu_code_7}, {ldq_uop_3_fu_code_7}, {ldq_uop_2_fu_code_7}, {ldq_uop_1_fu_code_7}, {ldq_uop_0_fu_code_7}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_7 = _GEN_142[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_143 = {{ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_0_fu_code_8}, {ldq_uop_23_fu_code_8}, {ldq_uop_22_fu_code_8}, {ldq_uop_21_fu_code_8}, {ldq_uop_20_fu_code_8}, {ldq_uop_19_fu_code_8}, {ldq_uop_18_fu_code_8}, {ldq_uop_17_fu_code_8}, {ldq_uop_16_fu_code_8}, {ldq_uop_15_fu_code_8}, {ldq_uop_14_fu_code_8}, {ldq_uop_13_fu_code_8}, {ldq_uop_12_fu_code_8}, {ldq_uop_11_fu_code_8}, {ldq_uop_10_fu_code_8}, {ldq_uop_9_fu_code_8}, {ldq_uop_8_fu_code_8}, {ldq_uop_7_fu_code_8}, {ldq_uop_6_fu_code_8}, {ldq_uop_5_fu_code_8}, {ldq_uop_4_fu_code_8}, {ldq_uop_3_fu_code_8}, {ldq_uop_2_fu_code_8}, {ldq_uop_1_fu_code_8}, {ldq_uop_0_fu_code_8}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_8 = _GEN_143[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_144 = {{ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_0_fu_code_9}, {ldq_uop_23_fu_code_9}, {ldq_uop_22_fu_code_9}, {ldq_uop_21_fu_code_9}, {ldq_uop_20_fu_code_9}, {ldq_uop_19_fu_code_9}, {ldq_uop_18_fu_code_9}, {ldq_uop_17_fu_code_9}, {ldq_uop_16_fu_code_9}, {ldq_uop_15_fu_code_9}, {ldq_uop_14_fu_code_9}, {ldq_uop_13_fu_code_9}, {ldq_uop_12_fu_code_9}, {ldq_uop_11_fu_code_9}, {ldq_uop_10_fu_code_9}, {ldq_uop_9_fu_code_9}, {ldq_uop_8_fu_code_9}, {ldq_uop_7_fu_code_9}, {ldq_uop_6_fu_code_9}, {ldq_uop_5_fu_code_9}, {ldq_uop_4_fu_code_9}, {ldq_uop_3_fu_code_9}, {ldq_uop_2_fu_code_9}, {ldq_uop_1_fu_code_9}, {ldq_uop_0_fu_code_9}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fu_code_9 = _GEN_144[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_145 = {{ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_0_iw_issued}, {ldq_uop_23_iw_issued}, {ldq_uop_22_iw_issued}, {ldq_uop_21_iw_issued}, {ldq_uop_20_iw_issued}, {ldq_uop_19_iw_issued}, {ldq_uop_18_iw_issued}, {ldq_uop_17_iw_issued}, {ldq_uop_16_iw_issued}, {ldq_uop_15_iw_issued}, {ldq_uop_14_iw_issued}, {ldq_uop_13_iw_issued}, {ldq_uop_12_iw_issued}, {ldq_uop_11_iw_issued}, {ldq_uop_10_iw_issued}, {ldq_uop_9_iw_issued}, {ldq_uop_8_iw_issued}, {ldq_uop_7_iw_issued}, {ldq_uop_6_iw_issued}, {ldq_uop_5_iw_issued}, {ldq_uop_4_iw_issued}, {ldq_uop_3_iw_issued}, {ldq_uop_2_iw_issued}, {ldq_uop_1_iw_issued}, {ldq_uop_0_iw_issued}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued = _GEN_145[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_146 = {{ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}, {ldq_uop_23_iw_issued_partial_agen}, {ldq_uop_22_iw_issued_partial_agen}, {ldq_uop_21_iw_issued_partial_agen}, {ldq_uop_20_iw_issued_partial_agen}, {ldq_uop_19_iw_issued_partial_agen}, {ldq_uop_18_iw_issued_partial_agen}, {ldq_uop_17_iw_issued_partial_agen}, {ldq_uop_16_iw_issued_partial_agen}, {ldq_uop_15_iw_issued_partial_agen}, {ldq_uop_14_iw_issued_partial_agen}, {ldq_uop_13_iw_issued_partial_agen}, {ldq_uop_12_iw_issued_partial_agen}, {ldq_uop_11_iw_issued_partial_agen}, {ldq_uop_10_iw_issued_partial_agen}, {ldq_uop_9_iw_issued_partial_agen}, {ldq_uop_8_iw_issued_partial_agen}, {ldq_uop_7_iw_issued_partial_agen}, {ldq_uop_6_iw_issued_partial_agen}, {ldq_uop_5_iw_issued_partial_agen}, {ldq_uop_4_iw_issued_partial_agen}, {ldq_uop_3_iw_issued_partial_agen}, {ldq_uop_2_iw_issued_partial_agen}, {ldq_uop_1_iw_issued_partial_agen}, {ldq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_147 = {{ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}, {ldq_uop_23_iw_issued_partial_dgen}, {ldq_uop_22_iw_issued_partial_dgen}, {ldq_uop_21_iw_issued_partial_dgen}, {ldq_uop_20_iw_issued_partial_dgen}, {ldq_uop_19_iw_issued_partial_dgen}, {ldq_uop_18_iw_issued_partial_dgen}, {ldq_uop_17_iw_issued_partial_dgen}, {ldq_uop_16_iw_issued_partial_dgen}, {ldq_uop_15_iw_issued_partial_dgen}, {ldq_uop_14_iw_issued_partial_dgen}, {ldq_uop_13_iw_issued_partial_dgen}, {ldq_uop_12_iw_issued_partial_dgen}, {ldq_uop_11_iw_issued_partial_dgen}, {ldq_uop_10_iw_issued_partial_dgen}, {ldq_uop_9_iw_issued_partial_dgen}, {ldq_uop_8_iw_issued_partial_dgen}, {ldq_uop_7_iw_issued_partial_dgen}, {ldq_uop_6_iw_issued_partial_dgen}, {ldq_uop_5_iw_issued_partial_dgen}, {ldq_uop_4_iw_issued_partial_dgen}, {ldq_uop_3_iw_issued_partial_dgen}, {ldq_uop_2_iw_issued_partial_dgen}, {ldq_uop_1_iw_issued_partial_dgen}, {ldq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_148 = {{ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}, {ldq_uop_23_iw_p1_speculative_child}, {ldq_uop_22_iw_p1_speculative_child}, {ldq_uop_21_iw_p1_speculative_child}, {ldq_uop_20_iw_p1_speculative_child}, {ldq_uop_19_iw_p1_speculative_child}, {ldq_uop_18_iw_p1_speculative_child}, {ldq_uop_17_iw_p1_speculative_child}, {ldq_uop_16_iw_p1_speculative_child}, {ldq_uop_15_iw_p1_speculative_child}, {ldq_uop_14_iw_p1_speculative_child}, {ldq_uop_13_iw_p1_speculative_child}, {ldq_uop_12_iw_p1_speculative_child}, {ldq_uop_11_iw_p1_speculative_child}, {ldq_uop_10_iw_p1_speculative_child}, {ldq_uop_9_iw_p1_speculative_child}, {ldq_uop_8_iw_p1_speculative_child}, {ldq_uop_7_iw_p1_speculative_child}, {ldq_uop_6_iw_p1_speculative_child}, {ldq_uop_5_iw_p1_speculative_child}, {ldq_uop_4_iw_p1_speculative_child}, {ldq_uop_3_iw_p1_speculative_child}, {ldq_uop_2_iw_p1_speculative_child}, {ldq_uop_1_iw_p1_speculative_child}, {ldq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_149 = {{ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}, {ldq_uop_23_iw_p2_speculative_child}, {ldq_uop_22_iw_p2_speculative_child}, {ldq_uop_21_iw_p2_speculative_child}, {ldq_uop_20_iw_p2_speculative_child}, {ldq_uop_19_iw_p2_speculative_child}, {ldq_uop_18_iw_p2_speculative_child}, {ldq_uop_17_iw_p2_speculative_child}, {ldq_uop_16_iw_p2_speculative_child}, {ldq_uop_15_iw_p2_speculative_child}, {ldq_uop_14_iw_p2_speculative_child}, {ldq_uop_13_iw_p2_speculative_child}, {ldq_uop_12_iw_p2_speculative_child}, {ldq_uop_11_iw_p2_speculative_child}, {ldq_uop_10_iw_p2_speculative_child}, {ldq_uop_9_iw_p2_speculative_child}, {ldq_uop_8_iw_p2_speculative_child}, {ldq_uop_7_iw_p2_speculative_child}, {ldq_uop_6_iw_p2_speculative_child}, {ldq_uop_5_iw_p2_speculative_child}, {ldq_uop_4_iw_p2_speculative_child}, {ldq_uop_3_iw_p2_speculative_child}, {ldq_uop_2_iw_p2_speculative_child}, {ldq_uop_1_iw_p2_speculative_child}, {ldq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_150 = {{ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}, {ldq_uop_23_iw_p1_bypass_hint}, {ldq_uop_22_iw_p1_bypass_hint}, {ldq_uop_21_iw_p1_bypass_hint}, {ldq_uop_20_iw_p1_bypass_hint}, {ldq_uop_19_iw_p1_bypass_hint}, {ldq_uop_18_iw_p1_bypass_hint}, {ldq_uop_17_iw_p1_bypass_hint}, {ldq_uop_16_iw_p1_bypass_hint}, {ldq_uop_15_iw_p1_bypass_hint}, {ldq_uop_14_iw_p1_bypass_hint}, {ldq_uop_13_iw_p1_bypass_hint}, {ldq_uop_12_iw_p1_bypass_hint}, {ldq_uop_11_iw_p1_bypass_hint}, {ldq_uop_10_iw_p1_bypass_hint}, {ldq_uop_9_iw_p1_bypass_hint}, {ldq_uop_8_iw_p1_bypass_hint}, {ldq_uop_7_iw_p1_bypass_hint}, {ldq_uop_6_iw_p1_bypass_hint}, {ldq_uop_5_iw_p1_bypass_hint}, {ldq_uop_4_iw_p1_bypass_hint}, {ldq_uop_3_iw_p1_bypass_hint}, {ldq_uop_2_iw_p1_bypass_hint}, {ldq_uop_1_iw_p1_bypass_hint}, {ldq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_151 = {{ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}, {ldq_uop_23_iw_p2_bypass_hint}, {ldq_uop_22_iw_p2_bypass_hint}, {ldq_uop_21_iw_p2_bypass_hint}, {ldq_uop_20_iw_p2_bypass_hint}, {ldq_uop_19_iw_p2_bypass_hint}, {ldq_uop_18_iw_p2_bypass_hint}, {ldq_uop_17_iw_p2_bypass_hint}, {ldq_uop_16_iw_p2_bypass_hint}, {ldq_uop_15_iw_p2_bypass_hint}, {ldq_uop_14_iw_p2_bypass_hint}, {ldq_uop_13_iw_p2_bypass_hint}, {ldq_uop_12_iw_p2_bypass_hint}, {ldq_uop_11_iw_p2_bypass_hint}, {ldq_uop_10_iw_p2_bypass_hint}, {ldq_uop_9_iw_p2_bypass_hint}, {ldq_uop_8_iw_p2_bypass_hint}, {ldq_uop_7_iw_p2_bypass_hint}, {ldq_uop_6_iw_p2_bypass_hint}, {ldq_uop_5_iw_p2_bypass_hint}, {ldq_uop_4_iw_p2_bypass_hint}, {ldq_uop_3_iw_p2_bypass_hint}, {ldq_uop_2_iw_p2_bypass_hint}, {ldq_uop_1_iw_p2_bypass_hint}, {ldq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_152 = {{ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}, {ldq_uop_23_iw_p3_bypass_hint}, {ldq_uop_22_iw_p3_bypass_hint}, {ldq_uop_21_iw_p3_bypass_hint}, {ldq_uop_20_iw_p3_bypass_hint}, {ldq_uop_19_iw_p3_bypass_hint}, {ldq_uop_18_iw_p3_bypass_hint}, {ldq_uop_17_iw_p3_bypass_hint}, {ldq_uop_16_iw_p3_bypass_hint}, {ldq_uop_15_iw_p3_bypass_hint}, {ldq_uop_14_iw_p3_bypass_hint}, {ldq_uop_13_iw_p3_bypass_hint}, {ldq_uop_12_iw_p3_bypass_hint}, {ldq_uop_11_iw_p3_bypass_hint}, {ldq_uop_10_iw_p3_bypass_hint}, {ldq_uop_9_iw_p3_bypass_hint}, {ldq_uop_8_iw_p3_bypass_hint}, {ldq_uop_7_iw_p3_bypass_hint}, {ldq_uop_6_iw_p3_bypass_hint}, {ldq_uop_5_iw_p3_bypass_hint}, {ldq_uop_4_iw_p3_bypass_hint}, {ldq_uop_3_iw_p3_bypass_hint}, {ldq_uop_2_iw_p3_bypass_hint}, {ldq_uop_1_iw_p3_bypass_hint}, {ldq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_153 = {{ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_0_dis_col_sel}, {ldq_uop_23_dis_col_sel}, {ldq_uop_22_dis_col_sel}, {ldq_uop_21_dis_col_sel}, {ldq_uop_20_dis_col_sel}, {ldq_uop_19_dis_col_sel}, {ldq_uop_18_dis_col_sel}, {ldq_uop_17_dis_col_sel}, {ldq_uop_16_dis_col_sel}, {ldq_uop_15_dis_col_sel}, {ldq_uop_14_dis_col_sel}, {ldq_uop_13_dis_col_sel}, {ldq_uop_12_dis_col_sel}, {ldq_uop_11_dis_col_sel}, {ldq_uop_10_dis_col_sel}, {ldq_uop_9_dis_col_sel}, {ldq_uop_8_dis_col_sel}, {ldq_uop_7_dis_col_sel}, {ldq_uop_6_dis_col_sel}, {ldq_uop_5_dis_col_sel}, {ldq_uop_4_dis_col_sel}, {ldq_uop_3_dis_col_sel}, {ldq_uop_2_dis_col_sel}, {ldq_uop_1_dis_col_sel}, {ldq_uop_0_dis_col_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dis_col_sel = _GEN_153[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][15:0] _GEN_154 = {{ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_0_br_mask}, {ldq_uop_23_br_mask}, {ldq_uop_22_br_mask}, {ldq_uop_21_br_mask}, {ldq_uop_20_br_mask}, {ldq_uop_19_br_mask}, {ldq_uop_18_br_mask}, {ldq_uop_17_br_mask}, {ldq_uop_16_br_mask}, {ldq_uop_15_br_mask}, {ldq_uop_14_br_mask}, {ldq_uop_13_br_mask}, {ldq_uop_12_br_mask}, {ldq_uop_11_br_mask}, {ldq_uop_10_br_mask}, {ldq_uop_9_br_mask}, {ldq_uop_8_br_mask}, {ldq_uop_7_br_mask}, {ldq_uop_6_br_mask}, {ldq_uop_5_br_mask}, {ldq_uop_4_br_mask}, {ldq_uop_3_br_mask}, {ldq_uop_2_br_mask}, {ldq_uop_1_br_mask}, {ldq_uop_0_br_mask}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_mask = _GEN_154[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][3:0] _GEN_155 = {{ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_0_br_tag}, {ldq_uop_23_br_tag}, {ldq_uop_22_br_tag}, {ldq_uop_21_br_tag}, {ldq_uop_20_br_tag}, {ldq_uop_19_br_tag}, {ldq_uop_18_br_tag}, {ldq_uop_17_br_tag}, {ldq_uop_16_br_tag}, {ldq_uop_15_br_tag}, {ldq_uop_14_br_tag}, {ldq_uop_13_br_tag}, {ldq_uop_12_br_tag}, {ldq_uop_11_br_tag}, {ldq_uop_10_br_tag}, {ldq_uop_9_br_tag}, {ldq_uop_8_br_tag}, {ldq_uop_7_br_tag}, {ldq_uop_6_br_tag}, {ldq_uop_5_br_tag}, {ldq_uop_4_br_tag}, {ldq_uop_3_br_tag}, {ldq_uop_2_br_tag}, {ldq_uop_1_br_tag}, {ldq_uop_0_br_tag}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_tag = _GEN_155[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][3:0] _GEN_156 = {{ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_0_br_type}, {ldq_uop_23_br_type}, {ldq_uop_22_br_type}, {ldq_uop_21_br_type}, {ldq_uop_20_br_type}, {ldq_uop_19_br_type}, {ldq_uop_18_br_type}, {ldq_uop_17_br_type}, {ldq_uop_16_br_type}, {ldq_uop_15_br_type}, {ldq_uop_14_br_type}, {ldq_uop_13_br_type}, {ldq_uop_12_br_type}, {ldq_uop_11_br_type}, {ldq_uop_10_br_type}, {ldq_uop_9_br_type}, {ldq_uop_8_br_type}, {ldq_uop_7_br_type}, {ldq_uop_6_br_type}, {ldq_uop_5_br_type}, {ldq_uop_4_br_type}, {ldq_uop_3_br_type}, {ldq_uop_2_br_type}, {ldq_uop_1_br_type}, {ldq_uop_0_br_type}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_br_type = _GEN_156[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_157 = {{ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_0_is_sfb}, {ldq_uop_23_is_sfb}, {ldq_uop_22_is_sfb}, {ldq_uop_21_is_sfb}, {ldq_uop_20_is_sfb}, {ldq_uop_19_is_sfb}, {ldq_uop_18_is_sfb}, {ldq_uop_17_is_sfb}, {ldq_uop_16_is_sfb}, {ldq_uop_15_is_sfb}, {ldq_uop_14_is_sfb}, {ldq_uop_13_is_sfb}, {ldq_uop_12_is_sfb}, {ldq_uop_11_is_sfb}, {ldq_uop_10_is_sfb}, {ldq_uop_9_is_sfb}, {ldq_uop_8_is_sfb}, {ldq_uop_7_is_sfb}, {ldq_uop_6_is_sfb}, {ldq_uop_5_is_sfb}, {ldq_uop_4_is_sfb}, {ldq_uop_3_is_sfb}, {ldq_uop_2_is_sfb}, {ldq_uop_1_is_sfb}, {ldq_uop_0_is_sfb}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfb = _GEN_157[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_158 = {{ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_0_is_fence}, {ldq_uop_23_is_fence}, {ldq_uop_22_is_fence}, {ldq_uop_21_is_fence}, {ldq_uop_20_is_fence}, {ldq_uop_19_is_fence}, {ldq_uop_18_is_fence}, {ldq_uop_17_is_fence}, {ldq_uop_16_is_fence}, {ldq_uop_15_is_fence}, {ldq_uop_14_is_fence}, {ldq_uop_13_is_fence}, {ldq_uop_12_is_fence}, {ldq_uop_11_is_fence}, {ldq_uop_10_is_fence}, {ldq_uop_9_is_fence}, {ldq_uop_8_is_fence}, {ldq_uop_7_is_fence}, {ldq_uop_6_is_fence}, {ldq_uop_5_is_fence}, {ldq_uop_4_is_fence}, {ldq_uop_3_is_fence}, {ldq_uop_2_is_fence}, {ldq_uop_1_is_fence}, {ldq_uop_0_is_fence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fence = _GEN_158[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_159 = {{ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_0_is_fencei}, {ldq_uop_23_is_fencei}, {ldq_uop_22_is_fencei}, {ldq_uop_21_is_fencei}, {ldq_uop_20_is_fencei}, {ldq_uop_19_is_fencei}, {ldq_uop_18_is_fencei}, {ldq_uop_17_is_fencei}, {ldq_uop_16_is_fencei}, {ldq_uop_15_is_fencei}, {ldq_uop_14_is_fencei}, {ldq_uop_13_is_fencei}, {ldq_uop_12_is_fencei}, {ldq_uop_11_is_fencei}, {ldq_uop_10_is_fencei}, {ldq_uop_9_is_fencei}, {ldq_uop_8_is_fencei}, {ldq_uop_7_is_fencei}, {ldq_uop_6_is_fencei}, {ldq_uop_5_is_fencei}, {ldq_uop_4_is_fencei}, {ldq_uop_3_is_fencei}, {ldq_uop_2_is_fencei}, {ldq_uop_1_is_fencei}, {ldq_uop_0_is_fencei}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_fencei = _GEN_159[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_160 = {{ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_0_is_sfence}, {ldq_uop_23_is_sfence}, {ldq_uop_22_is_sfence}, {ldq_uop_21_is_sfence}, {ldq_uop_20_is_sfence}, {ldq_uop_19_is_sfence}, {ldq_uop_18_is_sfence}, {ldq_uop_17_is_sfence}, {ldq_uop_16_is_sfence}, {ldq_uop_15_is_sfence}, {ldq_uop_14_is_sfence}, {ldq_uop_13_is_sfence}, {ldq_uop_12_is_sfence}, {ldq_uop_11_is_sfence}, {ldq_uop_10_is_sfence}, {ldq_uop_9_is_sfence}, {ldq_uop_8_is_sfence}, {ldq_uop_7_is_sfence}, {ldq_uop_6_is_sfence}, {ldq_uop_5_is_sfence}, {ldq_uop_4_is_sfence}, {ldq_uop_3_is_sfence}, {ldq_uop_2_is_sfence}, {ldq_uop_1_is_sfence}, {ldq_uop_0_is_sfence}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sfence = _GEN_160[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_161 = {{ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_0_is_amo}, {ldq_uop_23_is_amo}, {ldq_uop_22_is_amo}, {ldq_uop_21_is_amo}, {ldq_uop_20_is_amo}, {ldq_uop_19_is_amo}, {ldq_uop_18_is_amo}, {ldq_uop_17_is_amo}, {ldq_uop_16_is_amo}, {ldq_uop_15_is_amo}, {ldq_uop_14_is_amo}, {ldq_uop_13_is_amo}, {ldq_uop_12_is_amo}, {ldq_uop_11_is_amo}, {ldq_uop_10_is_amo}, {ldq_uop_9_is_amo}, {ldq_uop_8_is_amo}, {ldq_uop_7_is_amo}, {ldq_uop_6_is_amo}, {ldq_uop_5_is_amo}, {ldq_uop_4_is_amo}, {ldq_uop_3_is_amo}, {ldq_uop_2_is_amo}, {ldq_uop_1_is_amo}, {ldq_uop_0_is_amo}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_amo = _GEN_161[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_162 = {{ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_0_is_eret}, {ldq_uop_23_is_eret}, {ldq_uop_22_is_eret}, {ldq_uop_21_is_eret}, {ldq_uop_20_is_eret}, {ldq_uop_19_is_eret}, {ldq_uop_18_is_eret}, {ldq_uop_17_is_eret}, {ldq_uop_16_is_eret}, {ldq_uop_15_is_eret}, {ldq_uop_14_is_eret}, {ldq_uop_13_is_eret}, {ldq_uop_12_is_eret}, {ldq_uop_11_is_eret}, {ldq_uop_10_is_eret}, {ldq_uop_9_is_eret}, {ldq_uop_8_is_eret}, {ldq_uop_7_is_eret}, {ldq_uop_6_is_eret}, {ldq_uop_5_is_eret}, {ldq_uop_4_is_eret}, {ldq_uop_3_is_eret}, {ldq_uop_2_is_eret}, {ldq_uop_1_is_eret}, {ldq_uop_0_is_eret}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_eret = _GEN_162[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_163 = {{ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}, {ldq_uop_23_is_sys_pc2epc}, {ldq_uop_22_is_sys_pc2epc}, {ldq_uop_21_is_sys_pc2epc}, {ldq_uop_20_is_sys_pc2epc}, {ldq_uop_19_is_sys_pc2epc}, {ldq_uop_18_is_sys_pc2epc}, {ldq_uop_17_is_sys_pc2epc}, {ldq_uop_16_is_sys_pc2epc}, {ldq_uop_15_is_sys_pc2epc}, {ldq_uop_14_is_sys_pc2epc}, {ldq_uop_13_is_sys_pc2epc}, {ldq_uop_12_is_sys_pc2epc}, {ldq_uop_11_is_sys_pc2epc}, {ldq_uop_10_is_sys_pc2epc}, {ldq_uop_9_is_sys_pc2epc}, {ldq_uop_8_is_sys_pc2epc}, {ldq_uop_7_is_sys_pc2epc}, {ldq_uop_6_is_sys_pc2epc}, {ldq_uop_5_is_sys_pc2epc}, {ldq_uop_4_is_sys_pc2epc}, {ldq_uop_3_is_sys_pc2epc}, {ldq_uop_2_is_sys_pc2epc}, {ldq_uop_1_is_sys_pc2epc}, {ldq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_163[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_164 = {{ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_0_is_rocc}, {ldq_uop_23_is_rocc}, {ldq_uop_22_is_rocc}, {ldq_uop_21_is_rocc}, {ldq_uop_20_is_rocc}, {ldq_uop_19_is_rocc}, {ldq_uop_18_is_rocc}, {ldq_uop_17_is_rocc}, {ldq_uop_16_is_rocc}, {ldq_uop_15_is_rocc}, {ldq_uop_14_is_rocc}, {ldq_uop_13_is_rocc}, {ldq_uop_12_is_rocc}, {ldq_uop_11_is_rocc}, {ldq_uop_10_is_rocc}, {ldq_uop_9_is_rocc}, {ldq_uop_8_is_rocc}, {ldq_uop_7_is_rocc}, {ldq_uop_6_is_rocc}, {ldq_uop_5_is_rocc}, {ldq_uop_4_is_rocc}, {ldq_uop_3_is_rocc}, {ldq_uop_2_is_rocc}, {ldq_uop_1_is_rocc}, {ldq_uop_0_is_rocc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_rocc = _GEN_164[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_165 = {{ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_0_is_mov}, {ldq_uop_23_is_mov}, {ldq_uop_22_is_mov}, {ldq_uop_21_is_mov}, {ldq_uop_20_is_mov}, {ldq_uop_19_is_mov}, {ldq_uop_18_is_mov}, {ldq_uop_17_is_mov}, {ldq_uop_16_is_mov}, {ldq_uop_15_is_mov}, {ldq_uop_14_is_mov}, {ldq_uop_13_is_mov}, {ldq_uop_12_is_mov}, {ldq_uop_11_is_mov}, {ldq_uop_10_is_mov}, {ldq_uop_9_is_mov}, {ldq_uop_8_is_mov}, {ldq_uop_7_is_mov}, {ldq_uop_6_is_mov}, {ldq_uop_5_is_mov}, {ldq_uop_4_is_mov}, {ldq_uop_3_is_mov}, {ldq_uop_2_is_mov}, {ldq_uop_1_is_mov}, {ldq_uop_0_is_mov}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_mov = _GEN_165[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_166 = {{ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_0_ftq_idx}, {ldq_uop_23_ftq_idx}, {ldq_uop_22_ftq_idx}, {ldq_uop_21_ftq_idx}, {ldq_uop_20_ftq_idx}, {ldq_uop_19_ftq_idx}, {ldq_uop_18_ftq_idx}, {ldq_uop_17_ftq_idx}, {ldq_uop_16_ftq_idx}, {ldq_uop_15_ftq_idx}, {ldq_uop_14_ftq_idx}, {ldq_uop_13_ftq_idx}, {ldq_uop_12_ftq_idx}, {ldq_uop_11_ftq_idx}, {ldq_uop_10_ftq_idx}, {ldq_uop_9_ftq_idx}, {ldq_uop_8_ftq_idx}, {ldq_uop_7_ftq_idx}, {ldq_uop_6_ftq_idx}, {ldq_uop_5_ftq_idx}, {ldq_uop_4_ftq_idx}, {ldq_uop_3_ftq_idx}, {ldq_uop_2_ftq_idx}, {ldq_uop_1_ftq_idx}, {ldq_uop_0_ftq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ftq_idx = _GEN_166[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_167 = {{ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_0_edge_inst}, {ldq_uop_23_edge_inst}, {ldq_uop_22_edge_inst}, {ldq_uop_21_edge_inst}, {ldq_uop_20_edge_inst}, {ldq_uop_19_edge_inst}, {ldq_uop_18_edge_inst}, {ldq_uop_17_edge_inst}, {ldq_uop_16_edge_inst}, {ldq_uop_15_edge_inst}, {ldq_uop_14_edge_inst}, {ldq_uop_13_edge_inst}, {ldq_uop_12_edge_inst}, {ldq_uop_11_edge_inst}, {ldq_uop_10_edge_inst}, {ldq_uop_9_edge_inst}, {ldq_uop_8_edge_inst}, {ldq_uop_7_edge_inst}, {ldq_uop_6_edge_inst}, {ldq_uop_5_edge_inst}, {ldq_uop_4_edge_inst}, {ldq_uop_3_edge_inst}, {ldq_uop_2_edge_inst}, {ldq_uop_1_edge_inst}, {ldq_uop_0_edge_inst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_edge_inst = _GEN_167[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_168 = {{ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_0_pc_lob}, {ldq_uop_23_pc_lob}, {ldq_uop_22_pc_lob}, {ldq_uop_21_pc_lob}, {ldq_uop_20_pc_lob}, {ldq_uop_19_pc_lob}, {ldq_uop_18_pc_lob}, {ldq_uop_17_pc_lob}, {ldq_uop_16_pc_lob}, {ldq_uop_15_pc_lob}, {ldq_uop_14_pc_lob}, {ldq_uop_13_pc_lob}, {ldq_uop_12_pc_lob}, {ldq_uop_11_pc_lob}, {ldq_uop_10_pc_lob}, {ldq_uop_9_pc_lob}, {ldq_uop_8_pc_lob}, {ldq_uop_7_pc_lob}, {ldq_uop_6_pc_lob}, {ldq_uop_5_pc_lob}, {ldq_uop_4_pc_lob}, {ldq_uop_3_pc_lob}, {ldq_uop_2_pc_lob}, {ldq_uop_1_pc_lob}, {ldq_uop_0_pc_lob}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pc_lob = _GEN_168[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_169 = {{ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_0_taken}, {ldq_uop_23_taken}, {ldq_uop_22_taken}, {ldq_uop_21_taken}, {ldq_uop_20_taken}, {ldq_uop_19_taken}, {ldq_uop_18_taken}, {ldq_uop_17_taken}, {ldq_uop_16_taken}, {ldq_uop_15_taken}, {ldq_uop_14_taken}, {ldq_uop_13_taken}, {ldq_uop_12_taken}, {ldq_uop_11_taken}, {ldq_uop_10_taken}, {ldq_uop_9_taken}, {ldq_uop_8_taken}, {ldq_uop_7_taken}, {ldq_uop_6_taken}, {ldq_uop_5_taken}, {ldq_uop_4_taken}, {ldq_uop_3_taken}, {ldq_uop_2_taken}, {ldq_uop_1_taken}, {ldq_uop_0_taken}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_taken = _GEN_169[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_170 = {{ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_0_imm_rename}, {ldq_uop_23_imm_rename}, {ldq_uop_22_imm_rename}, {ldq_uop_21_imm_rename}, {ldq_uop_20_imm_rename}, {ldq_uop_19_imm_rename}, {ldq_uop_18_imm_rename}, {ldq_uop_17_imm_rename}, {ldq_uop_16_imm_rename}, {ldq_uop_15_imm_rename}, {ldq_uop_14_imm_rename}, {ldq_uop_13_imm_rename}, {ldq_uop_12_imm_rename}, {ldq_uop_11_imm_rename}, {ldq_uop_10_imm_rename}, {ldq_uop_9_imm_rename}, {ldq_uop_8_imm_rename}, {ldq_uop_7_imm_rename}, {ldq_uop_6_imm_rename}, {ldq_uop_5_imm_rename}, {ldq_uop_4_imm_rename}, {ldq_uop_3_imm_rename}, {ldq_uop_2_imm_rename}, {ldq_uop_1_imm_rename}, {ldq_uop_0_imm_rename}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_rename = _GEN_170[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_171 = {{ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_0_imm_sel}, {ldq_uop_23_imm_sel}, {ldq_uop_22_imm_sel}, {ldq_uop_21_imm_sel}, {ldq_uop_20_imm_sel}, {ldq_uop_19_imm_sel}, {ldq_uop_18_imm_sel}, {ldq_uop_17_imm_sel}, {ldq_uop_16_imm_sel}, {ldq_uop_15_imm_sel}, {ldq_uop_14_imm_sel}, {ldq_uop_13_imm_sel}, {ldq_uop_12_imm_sel}, {ldq_uop_11_imm_sel}, {ldq_uop_10_imm_sel}, {ldq_uop_9_imm_sel}, {ldq_uop_8_imm_sel}, {ldq_uop_7_imm_sel}, {ldq_uop_6_imm_sel}, {ldq_uop_5_imm_sel}, {ldq_uop_4_imm_sel}, {ldq_uop_3_imm_sel}, {ldq_uop_2_imm_sel}, {ldq_uop_1_imm_sel}, {ldq_uop_0_imm_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_sel = _GEN_171[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_172 = {{ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_0_pimm}, {ldq_uop_23_pimm}, {ldq_uop_22_pimm}, {ldq_uop_21_pimm}, {ldq_uop_20_pimm}, {ldq_uop_19_pimm}, {ldq_uop_18_pimm}, {ldq_uop_17_pimm}, {ldq_uop_16_pimm}, {ldq_uop_15_pimm}, {ldq_uop_14_pimm}, {ldq_uop_13_pimm}, {ldq_uop_12_pimm}, {ldq_uop_11_pimm}, {ldq_uop_10_pimm}, {ldq_uop_9_pimm}, {ldq_uop_8_pimm}, {ldq_uop_7_pimm}, {ldq_uop_6_pimm}, {ldq_uop_5_pimm}, {ldq_uop_4_pimm}, {ldq_uop_3_pimm}, {ldq_uop_2_pimm}, {ldq_uop_1_pimm}, {ldq_uop_0_pimm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pimm = _GEN_172[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][19:0] _GEN_173 = {{ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_0_imm_packed}, {ldq_uop_23_imm_packed}, {ldq_uop_22_imm_packed}, {ldq_uop_21_imm_packed}, {ldq_uop_20_imm_packed}, {ldq_uop_19_imm_packed}, {ldq_uop_18_imm_packed}, {ldq_uop_17_imm_packed}, {ldq_uop_16_imm_packed}, {ldq_uop_15_imm_packed}, {ldq_uop_14_imm_packed}, {ldq_uop_13_imm_packed}, {ldq_uop_12_imm_packed}, {ldq_uop_11_imm_packed}, {ldq_uop_10_imm_packed}, {ldq_uop_9_imm_packed}, {ldq_uop_8_imm_packed}, {ldq_uop_7_imm_packed}, {ldq_uop_6_imm_packed}, {ldq_uop_5_imm_packed}, {ldq_uop_4_imm_packed}, {ldq_uop_3_imm_packed}, {ldq_uop_2_imm_packed}, {ldq_uop_1_imm_packed}, {ldq_uop_0_imm_packed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_imm_packed = _GEN_173[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_174 = {{ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_0_op1_sel}, {ldq_uop_23_op1_sel}, {ldq_uop_22_op1_sel}, {ldq_uop_21_op1_sel}, {ldq_uop_20_op1_sel}, {ldq_uop_19_op1_sel}, {ldq_uop_18_op1_sel}, {ldq_uop_17_op1_sel}, {ldq_uop_16_op1_sel}, {ldq_uop_15_op1_sel}, {ldq_uop_14_op1_sel}, {ldq_uop_13_op1_sel}, {ldq_uop_12_op1_sel}, {ldq_uop_11_op1_sel}, {ldq_uop_10_op1_sel}, {ldq_uop_9_op1_sel}, {ldq_uop_8_op1_sel}, {ldq_uop_7_op1_sel}, {ldq_uop_6_op1_sel}, {ldq_uop_5_op1_sel}, {ldq_uop_4_op1_sel}, {ldq_uop_3_op1_sel}, {ldq_uop_2_op1_sel}, {ldq_uop_1_op1_sel}, {ldq_uop_0_op1_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op1_sel = _GEN_174[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_175 = {{ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_0_op2_sel}, {ldq_uop_23_op2_sel}, {ldq_uop_22_op2_sel}, {ldq_uop_21_op2_sel}, {ldq_uop_20_op2_sel}, {ldq_uop_19_op2_sel}, {ldq_uop_18_op2_sel}, {ldq_uop_17_op2_sel}, {ldq_uop_16_op2_sel}, {ldq_uop_15_op2_sel}, {ldq_uop_14_op2_sel}, {ldq_uop_13_op2_sel}, {ldq_uop_12_op2_sel}, {ldq_uop_11_op2_sel}, {ldq_uop_10_op2_sel}, {ldq_uop_9_op2_sel}, {ldq_uop_8_op2_sel}, {ldq_uop_7_op2_sel}, {ldq_uop_6_op2_sel}, {ldq_uop_5_op2_sel}, {ldq_uop_4_op2_sel}, {ldq_uop_3_op2_sel}, {ldq_uop_2_op2_sel}, {ldq_uop_1_op2_sel}, {ldq_uop_0_op2_sel}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_op2_sel = _GEN_175[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_176 = {{ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}, {ldq_uop_23_fp_ctrl_ldst}, {ldq_uop_22_fp_ctrl_ldst}, {ldq_uop_21_fp_ctrl_ldst}, {ldq_uop_20_fp_ctrl_ldst}, {ldq_uop_19_fp_ctrl_ldst}, {ldq_uop_18_fp_ctrl_ldst}, {ldq_uop_17_fp_ctrl_ldst}, {ldq_uop_16_fp_ctrl_ldst}, {ldq_uop_15_fp_ctrl_ldst}, {ldq_uop_14_fp_ctrl_ldst}, {ldq_uop_13_fp_ctrl_ldst}, {ldq_uop_12_fp_ctrl_ldst}, {ldq_uop_11_fp_ctrl_ldst}, {ldq_uop_10_fp_ctrl_ldst}, {ldq_uop_9_fp_ctrl_ldst}, {ldq_uop_8_fp_ctrl_ldst}, {ldq_uop_7_fp_ctrl_ldst}, {ldq_uop_6_fp_ctrl_ldst}, {ldq_uop_5_fp_ctrl_ldst}, {ldq_uop_4_fp_ctrl_ldst}, {ldq_uop_3_fp_ctrl_ldst}, {ldq_uop_2_fp_ctrl_ldst}, {ldq_uop_1_fp_ctrl_ldst}, {ldq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_177 = {{ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}, {ldq_uop_23_fp_ctrl_wen}, {ldq_uop_22_fp_ctrl_wen}, {ldq_uop_21_fp_ctrl_wen}, {ldq_uop_20_fp_ctrl_wen}, {ldq_uop_19_fp_ctrl_wen}, {ldq_uop_18_fp_ctrl_wen}, {ldq_uop_17_fp_ctrl_wen}, {ldq_uop_16_fp_ctrl_wen}, {ldq_uop_15_fp_ctrl_wen}, {ldq_uop_14_fp_ctrl_wen}, {ldq_uop_13_fp_ctrl_wen}, {ldq_uop_12_fp_ctrl_wen}, {ldq_uop_11_fp_ctrl_wen}, {ldq_uop_10_fp_ctrl_wen}, {ldq_uop_9_fp_ctrl_wen}, {ldq_uop_8_fp_ctrl_wen}, {ldq_uop_7_fp_ctrl_wen}, {ldq_uop_6_fp_ctrl_wen}, {ldq_uop_5_fp_ctrl_wen}, {ldq_uop_4_fp_ctrl_wen}, {ldq_uop_3_fp_ctrl_wen}, {ldq_uop_2_fp_ctrl_wen}, {ldq_uop_1_fp_ctrl_wen}, {ldq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_177[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_178 = {{ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}, {ldq_uop_23_fp_ctrl_ren1}, {ldq_uop_22_fp_ctrl_ren1}, {ldq_uop_21_fp_ctrl_ren1}, {ldq_uop_20_fp_ctrl_ren1}, {ldq_uop_19_fp_ctrl_ren1}, {ldq_uop_18_fp_ctrl_ren1}, {ldq_uop_17_fp_ctrl_ren1}, {ldq_uop_16_fp_ctrl_ren1}, {ldq_uop_15_fp_ctrl_ren1}, {ldq_uop_14_fp_ctrl_ren1}, {ldq_uop_13_fp_ctrl_ren1}, {ldq_uop_12_fp_ctrl_ren1}, {ldq_uop_11_fp_ctrl_ren1}, {ldq_uop_10_fp_ctrl_ren1}, {ldq_uop_9_fp_ctrl_ren1}, {ldq_uop_8_fp_ctrl_ren1}, {ldq_uop_7_fp_ctrl_ren1}, {ldq_uop_6_fp_ctrl_ren1}, {ldq_uop_5_fp_ctrl_ren1}, {ldq_uop_4_fp_ctrl_ren1}, {ldq_uop_3_fp_ctrl_ren1}, {ldq_uop_2_fp_ctrl_ren1}, {ldq_uop_1_fp_ctrl_ren1}, {ldq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_179 = {{ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}, {ldq_uop_23_fp_ctrl_ren2}, {ldq_uop_22_fp_ctrl_ren2}, {ldq_uop_21_fp_ctrl_ren2}, {ldq_uop_20_fp_ctrl_ren2}, {ldq_uop_19_fp_ctrl_ren2}, {ldq_uop_18_fp_ctrl_ren2}, {ldq_uop_17_fp_ctrl_ren2}, {ldq_uop_16_fp_ctrl_ren2}, {ldq_uop_15_fp_ctrl_ren2}, {ldq_uop_14_fp_ctrl_ren2}, {ldq_uop_13_fp_ctrl_ren2}, {ldq_uop_12_fp_ctrl_ren2}, {ldq_uop_11_fp_ctrl_ren2}, {ldq_uop_10_fp_ctrl_ren2}, {ldq_uop_9_fp_ctrl_ren2}, {ldq_uop_8_fp_ctrl_ren2}, {ldq_uop_7_fp_ctrl_ren2}, {ldq_uop_6_fp_ctrl_ren2}, {ldq_uop_5_fp_ctrl_ren2}, {ldq_uop_4_fp_ctrl_ren2}, {ldq_uop_3_fp_ctrl_ren2}, {ldq_uop_2_fp_ctrl_ren2}, {ldq_uop_1_fp_ctrl_ren2}, {ldq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_180 = {{ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}, {ldq_uop_23_fp_ctrl_ren3}, {ldq_uop_22_fp_ctrl_ren3}, {ldq_uop_21_fp_ctrl_ren3}, {ldq_uop_20_fp_ctrl_ren3}, {ldq_uop_19_fp_ctrl_ren3}, {ldq_uop_18_fp_ctrl_ren3}, {ldq_uop_17_fp_ctrl_ren3}, {ldq_uop_16_fp_ctrl_ren3}, {ldq_uop_15_fp_ctrl_ren3}, {ldq_uop_14_fp_ctrl_ren3}, {ldq_uop_13_fp_ctrl_ren3}, {ldq_uop_12_fp_ctrl_ren3}, {ldq_uop_11_fp_ctrl_ren3}, {ldq_uop_10_fp_ctrl_ren3}, {ldq_uop_9_fp_ctrl_ren3}, {ldq_uop_8_fp_ctrl_ren3}, {ldq_uop_7_fp_ctrl_ren3}, {ldq_uop_6_fp_ctrl_ren3}, {ldq_uop_5_fp_ctrl_ren3}, {ldq_uop_4_fp_ctrl_ren3}, {ldq_uop_3_fp_ctrl_ren3}, {ldq_uop_2_fp_ctrl_ren3}, {ldq_uop_1_fp_ctrl_ren3}, {ldq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_181 = {{ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}, {ldq_uop_23_fp_ctrl_swap12}, {ldq_uop_22_fp_ctrl_swap12}, {ldq_uop_21_fp_ctrl_swap12}, {ldq_uop_20_fp_ctrl_swap12}, {ldq_uop_19_fp_ctrl_swap12}, {ldq_uop_18_fp_ctrl_swap12}, {ldq_uop_17_fp_ctrl_swap12}, {ldq_uop_16_fp_ctrl_swap12}, {ldq_uop_15_fp_ctrl_swap12}, {ldq_uop_14_fp_ctrl_swap12}, {ldq_uop_13_fp_ctrl_swap12}, {ldq_uop_12_fp_ctrl_swap12}, {ldq_uop_11_fp_ctrl_swap12}, {ldq_uop_10_fp_ctrl_swap12}, {ldq_uop_9_fp_ctrl_swap12}, {ldq_uop_8_fp_ctrl_swap12}, {ldq_uop_7_fp_ctrl_swap12}, {ldq_uop_6_fp_ctrl_swap12}, {ldq_uop_5_fp_ctrl_swap12}, {ldq_uop_4_fp_ctrl_swap12}, {ldq_uop_3_fp_ctrl_swap12}, {ldq_uop_2_fp_ctrl_swap12}, {ldq_uop_1_fp_ctrl_swap12}, {ldq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_182 = {{ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}, {ldq_uop_23_fp_ctrl_swap23}, {ldq_uop_22_fp_ctrl_swap23}, {ldq_uop_21_fp_ctrl_swap23}, {ldq_uop_20_fp_ctrl_swap23}, {ldq_uop_19_fp_ctrl_swap23}, {ldq_uop_18_fp_ctrl_swap23}, {ldq_uop_17_fp_ctrl_swap23}, {ldq_uop_16_fp_ctrl_swap23}, {ldq_uop_15_fp_ctrl_swap23}, {ldq_uop_14_fp_ctrl_swap23}, {ldq_uop_13_fp_ctrl_swap23}, {ldq_uop_12_fp_ctrl_swap23}, {ldq_uop_11_fp_ctrl_swap23}, {ldq_uop_10_fp_ctrl_swap23}, {ldq_uop_9_fp_ctrl_swap23}, {ldq_uop_8_fp_ctrl_swap23}, {ldq_uop_7_fp_ctrl_swap23}, {ldq_uop_6_fp_ctrl_swap23}, {ldq_uop_5_fp_ctrl_swap23}, {ldq_uop_4_fp_ctrl_swap23}, {ldq_uop_3_fp_ctrl_swap23}, {ldq_uop_2_fp_ctrl_swap23}, {ldq_uop_1_fp_ctrl_swap23}, {ldq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_183 = {{ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}, {ldq_uop_23_fp_ctrl_typeTagIn}, {ldq_uop_22_fp_ctrl_typeTagIn}, {ldq_uop_21_fp_ctrl_typeTagIn}, {ldq_uop_20_fp_ctrl_typeTagIn}, {ldq_uop_19_fp_ctrl_typeTagIn}, {ldq_uop_18_fp_ctrl_typeTagIn}, {ldq_uop_17_fp_ctrl_typeTagIn}, {ldq_uop_16_fp_ctrl_typeTagIn}, {ldq_uop_15_fp_ctrl_typeTagIn}, {ldq_uop_14_fp_ctrl_typeTagIn}, {ldq_uop_13_fp_ctrl_typeTagIn}, {ldq_uop_12_fp_ctrl_typeTagIn}, {ldq_uop_11_fp_ctrl_typeTagIn}, {ldq_uop_10_fp_ctrl_typeTagIn}, {ldq_uop_9_fp_ctrl_typeTagIn}, {ldq_uop_8_fp_ctrl_typeTagIn}, {ldq_uop_7_fp_ctrl_typeTagIn}, {ldq_uop_6_fp_ctrl_typeTagIn}, {ldq_uop_5_fp_ctrl_typeTagIn}, {ldq_uop_4_fp_ctrl_typeTagIn}, {ldq_uop_3_fp_ctrl_typeTagIn}, {ldq_uop_2_fp_ctrl_typeTagIn}, {ldq_uop_1_fp_ctrl_typeTagIn}, {ldq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_184 = {{ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}, {ldq_uop_23_fp_ctrl_typeTagOut}, {ldq_uop_22_fp_ctrl_typeTagOut}, {ldq_uop_21_fp_ctrl_typeTagOut}, {ldq_uop_20_fp_ctrl_typeTagOut}, {ldq_uop_19_fp_ctrl_typeTagOut}, {ldq_uop_18_fp_ctrl_typeTagOut}, {ldq_uop_17_fp_ctrl_typeTagOut}, {ldq_uop_16_fp_ctrl_typeTagOut}, {ldq_uop_15_fp_ctrl_typeTagOut}, {ldq_uop_14_fp_ctrl_typeTagOut}, {ldq_uop_13_fp_ctrl_typeTagOut}, {ldq_uop_12_fp_ctrl_typeTagOut}, {ldq_uop_11_fp_ctrl_typeTagOut}, {ldq_uop_10_fp_ctrl_typeTagOut}, {ldq_uop_9_fp_ctrl_typeTagOut}, {ldq_uop_8_fp_ctrl_typeTagOut}, {ldq_uop_7_fp_ctrl_typeTagOut}, {ldq_uop_6_fp_ctrl_typeTagOut}, {ldq_uop_5_fp_ctrl_typeTagOut}, {ldq_uop_4_fp_ctrl_typeTagOut}, {ldq_uop_3_fp_ctrl_typeTagOut}, {ldq_uop_2_fp_ctrl_typeTagOut}, {ldq_uop_1_fp_ctrl_typeTagOut}, {ldq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_185 = {{ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}, {ldq_uop_23_fp_ctrl_fromint}, {ldq_uop_22_fp_ctrl_fromint}, {ldq_uop_21_fp_ctrl_fromint}, {ldq_uop_20_fp_ctrl_fromint}, {ldq_uop_19_fp_ctrl_fromint}, {ldq_uop_18_fp_ctrl_fromint}, {ldq_uop_17_fp_ctrl_fromint}, {ldq_uop_16_fp_ctrl_fromint}, {ldq_uop_15_fp_ctrl_fromint}, {ldq_uop_14_fp_ctrl_fromint}, {ldq_uop_13_fp_ctrl_fromint}, {ldq_uop_12_fp_ctrl_fromint}, {ldq_uop_11_fp_ctrl_fromint}, {ldq_uop_10_fp_ctrl_fromint}, {ldq_uop_9_fp_ctrl_fromint}, {ldq_uop_8_fp_ctrl_fromint}, {ldq_uop_7_fp_ctrl_fromint}, {ldq_uop_6_fp_ctrl_fromint}, {ldq_uop_5_fp_ctrl_fromint}, {ldq_uop_4_fp_ctrl_fromint}, {ldq_uop_3_fp_ctrl_fromint}, {ldq_uop_2_fp_ctrl_fromint}, {ldq_uop_1_fp_ctrl_fromint}, {ldq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_186 = {{ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}, {ldq_uop_23_fp_ctrl_toint}, {ldq_uop_22_fp_ctrl_toint}, {ldq_uop_21_fp_ctrl_toint}, {ldq_uop_20_fp_ctrl_toint}, {ldq_uop_19_fp_ctrl_toint}, {ldq_uop_18_fp_ctrl_toint}, {ldq_uop_17_fp_ctrl_toint}, {ldq_uop_16_fp_ctrl_toint}, {ldq_uop_15_fp_ctrl_toint}, {ldq_uop_14_fp_ctrl_toint}, {ldq_uop_13_fp_ctrl_toint}, {ldq_uop_12_fp_ctrl_toint}, {ldq_uop_11_fp_ctrl_toint}, {ldq_uop_10_fp_ctrl_toint}, {ldq_uop_9_fp_ctrl_toint}, {ldq_uop_8_fp_ctrl_toint}, {ldq_uop_7_fp_ctrl_toint}, {ldq_uop_6_fp_ctrl_toint}, {ldq_uop_5_fp_ctrl_toint}, {ldq_uop_4_fp_ctrl_toint}, {ldq_uop_3_fp_ctrl_toint}, {ldq_uop_2_fp_ctrl_toint}, {ldq_uop_1_fp_ctrl_toint}, {ldq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_186[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_187 = {{ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}, {ldq_uop_23_fp_ctrl_fastpipe}, {ldq_uop_22_fp_ctrl_fastpipe}, {ldq_uop_21_fp_ctrl_fastpipe}, {ldq_uop_20_fp_ctrl_fastpipe}, {ldq_uop_19_fp_ctrl_fastpipe}, {ldq_uop_18_fp_ctrl_fastpipe}, {ldq_uop_17_fp_ctrl_fastpipe}, {ldq_uop_16_fp_ctrl_fastpipe}, {ldq_uop_15_fp_ctrl_fastpipe}, {ldq_uop_14_fp_ctrl_fastpipe}, {ldq_uop_13_fp_ctrl_fastpipe}, {ldq_uop_12_fp_ctrl_fastpipe}, {ldq_uop_11_fp_ctrl_fastpipe}, {ldq_uop_10_fp_ctrl_fastpipe}, {ldq_uop_9_fp_ctrl_fastpipe}, {ldq_uop_8_fp_ctrl_fastpipe}, {ldq_uop_7_fp_ctrl_fastpipe}, {ldq_uop_6_fp_ctrl_fastpipe}, {ldq_uop_5_fp_ctrl_fastpipe}, {ldq_uop_4_fp_ctrl_fastpipe}, {ldq_uop_3_fp_ctrl_fastpipe}, {ldq_uop_2_fp_ctrl_fastpipe}, {ldq_uop_1_fp_ctrl_fastpipe}, {ldq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_188 = {{ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}, {ldq_uop_23_fp_ctrl_fma}, {ldq_uop_22_fp_ctrl_fma}, {ldq_uop_21_fp_ctrl_fma}, {ldq_uop_20_fp_ctrl_fma}, {ldq_uop_19_fp_ctrl_fma}, {ldq_uop_18_fp_ctrl_fma}, {ldq_uop_17_fp_ctrl_fma}, {ldq_uop_16_fp_ctrl_fma}, {ldq_uop_15_fp_ctrl_fma}, {ldq_uop_14_fp_ctrl_fma}, {ldq_uop_13_fp_ctrl_fma}, {ldq_uop_12_fp_ctrl_fma}, {ldq_uop_11_fp_ctrl_fma}, {ldq_uop_10_fp_ctrl_fma}, {ldq_uop_9_fp_ctrl_fma}, {ldq_uop_8_fp_ctrl_fma}, {ldq_uop_7_fp_ctrl_fma}, {ldq_uop_6_fp_ctrl_fma}, {ldq_uop_5_fp_ctrl_fma}, {ldq_uop_4_fp_ctrl_fma}, {ldq_uop_3_fp_ctrl_fma}, {ldq_uop_2_fp_ctrl_fma}, {ldq_uop_1_fp_ctrl_fma}, {ldq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_188[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_189 = {{ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}, {ldq_uop_23_fp_ctrl_div}, {ldq_uop_22_fp_ctrl_div}, {ldq_uop_21_fp_ctrl_div}, {ldq_uop_20_fp_ctrl_div}, {ldq_uop_19_fp_ctrl_div}, {ldq_uop_18_fp_ctrl_div}, {ldq_uop_17_fp_ctrl_div}, {ldq_uop_16_fp_ctrl_div}, {ldq_uop_15_fp_ctrl_div}, {ldq_uop_14_fp_ctrl_div}, {ldq_uop_13_fp_ctrl_div}, {ldq_uop_12_fp_ctrl_div}, {ldq_uop_11_fp_ctrl_div}, {ldq_uop_10_fp_ctrl_div}, {ldq_uop_9_fp_ctrl_div}, {ldq_uop_8_fp_ctrl_div}, {ldq_uop_7_fp_ctrl_div}, {ldq_uop_6_fp_ctrl_div}, {ldq_uop_5_fp_ctrl_div}, {ldq_uop_4_fp_ctrl_div}, {ldq_uop_3_fp_ctrl_div}, {ldq_uop_2_fp_ctrl_div}, {ldq_uop_1_fp_ctrl_div}, {ldq_uop_0_fp_ctrl_div}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_189[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_190 = {{ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}, {ldq_uop_23_fp_ctrl_sqrt}, {ldq_uop_22_fp_ctrl_sqrt}, {ldq_uop_21_fp_ctrl_sqrt}, {ldq_uop_20_fp_ctrl_sqrt}, {ldq_uop_19_fp_ctrl_sqrt}, {ldq_uop_18_fp_ctrl_sqrt}, {ldq_uop_17_fp_ctrl_sqrt}, {ldq_uop_16_fp_ctrl_sqrt}, {ldq_uop_15_fp_ctrl_sqrt}, {ldq_uop_14_fp_ctrl_sqrt}, {ldq_uop_13_fp_ctrl_sqrt}, {ldq_uop_12_fp_ctrl_sqrt}, {ldq_uop_11_fp_ctrl_sqrt}, {ldq_uop_10_fp_ctrl_sqrt}, {ldq_uop_9_fp_ctrl_sqrt}, {ldq_uop_8_fp_ctrl_sqrt}, {ldq_uop_7_fp_ctrl_sqrt}, {ldq_uop_6_fp_ctrl_sqrt}, {ldq_uop_5_fp_ctrl_sqrt}, {ldq_uop_4_fp_ctrl_sqrt}, {ldq_uop_3_fp_ctrl_sqrt}, {ldq_uop_2_fp_ctrl_sqrt}, {ldq_uop_1_fp_ctrl_sqrt}, {ldq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_191 = {{ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}, {ldq_uop_23_fp_ctrl_wflags}, {ldq_uop_22_fp_ctrl_wflags}, {ldq_uop_21_fp_ctrl_wflags}, {ldq_uop_20_fp_ctrl_wflags}, {ldq_uop_19_fp_ctrl_wflags}, {ldq_uop_18_fp_ctrl_wflags}, {ldq_uop_17_fp_ctrl_wflags}, {ldq_uop_16_fp_ctrl_wflags}, {ldq_uop_15_fp_ctrl_wflags}, {ldq_uop_14_fp_ctrl_wflags}, {ldq_uop_13_fp_ctrl_wflags}, {ldq_uop_12_fp_ctrl_wflags}, {ldq_uop_11_fp_ctrl_wflags}, {ldq_uop_10_fp_ctrl_wflags}, {ldq_uop_9_fp_ctrl_wflags}, {ldq_uop_8_fp_ctrl_wflags}, {ldq_uop_7_fp_ctrl_wflags}, {ldq_uop_6_fp_ctrl_wflags}, {ldq_uop_5_fp_ctrl_wflags}, {ldq_uop_4_fp_ctrl_wflags}, {ldq_uop_3_fp_ctrl_wflags}, {ldq_uop_2_fp_ctrl_wflags}, {ldq_uop_1_fp_ctrl_wflags}, {ldq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_192 = {{ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}, {ldq_uop_23_fp_ctrl_vec}, {ldq_uop_22_fp_ctrl_vec}, {ldq_uop_21_fp_ctrl_vec}, {ldq_uop_20_fp_ctrl_vec}, {ldq_uop_19_fp_ctrl_vec}, {ldq_uop_18_fp_ctrl_vec}, {ldq_uop_17_fp_ctrl_vec}, {ldq_uop_16_fp_ctrl_vec}, {ldq_uop_15_fp_ctrl_vec}, {ldq_uop_14_fp_ctrl_vec}, {ldq_uop_13_fp_ctrl_vec}, {ldq_uop_12_fp_ctrl_vec}, {ldq_uop_11_fp_ctrl_vec}, {ldq_uop_10_fp_ctrl_vec}, {ldq_uop_9_fp_ctrl_vec}, {ldq_uop_8_fp_ctrl_vec}, {ldq_uop_7_fp_ctrl_vec}, {ldq_uop_6_fp_ctrl_vec}, {ldq_uop_5_fp_ctrl_vec}, {ldq_uop_4_fp_ctrl_vec}, {ldq_uop_3_fp_ctrl_vec}, {ldq_uop_2_fp_ctrl_vec}, {ldq_uop_1_fp_ctrl_vec}, {ldq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_192[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_193 = {{ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_0_rob_idx}, {ldq_uop_23_rob_idx}, {ldq_uop_22_rob_idx}, {ldq_uop_21_rob_idx}, {ldq_uop_20_rob_idx}, {ldq_uop_19_rob_idx}, {ldq_uop_18_rob_idx}, {ldq_uop_17_rob_idx}, {ldq_uop_16_rob_idx}, {ldq_uop_15_rob_idx}, {ldq_uop_14_rob_idx}, {ldq_uop_13_rob_idx}, {ldq_uop_12_rob_idx}, {ldq_uop_11_rob_idx}, {ldq_uop_10_rob_idx}, {ldq_uop_9_rob_idx}, {ldq_uop_8_rob_idx}, {ldq_uop_7_rob_idx}, {ldq_uop_6_rob_idx}, {ldq_uop_5_rob_idx}, {ldq_uop_4_rob_idx}, {ldq_uop_3_rob_idx}, {ldq_uop_2_rob_idx}, {ldq_uop_1_rob_idx}, {ldq_uop_0_rob_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rob_idx = _GEN_193[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_194 = {{ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_0_ldq_idx}, {ldq_uop_23_ldq_idx}, {ldq_uop_22_ldq_idx}, {ldq_uop_21_ldq_idx}, {ldq_uop_20_ldq_idx}, {ldq_uop_19_ldq_idx}, {ldq_uop_18_ldq_idx}, {ldq_uop_17_ldq_idx}, {ldq_uop_16_ldq_idx}, {ldq_uop_15_ldq_idx}, {ldq_uop_14_ldq_idx}, {ldq_uop_13_ldq_idx}, {ldq_uop_12_ldq_idx}, {ldq_uop_11_ldq_idx}, {ldq_uop_10_ldq_idx}, {ldq_uop_9_ldq_idx}, {ldq_uop_8_ldq_idx}, {ldq_uop_7_ldq_idx}, {ldq_uop_6_ldq_idx}, {ldq_uop_5_ldq_idx}, {ldq_uop_4_ldq_idx}, {ldq_uop_3_ldq_idx}, {ldq_uop_2_ldq_idx}, {ldq_uop_1_ldq_idx}, {ldq_uop_0_ldq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldq_idx = _GEN_194[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_195 = {{ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_0_stq_idx}, {ldq_uop_23_stq_idx}, {ldq_uop_22_stq_idx}, {ldq_uop_21_stq_idx}, {ldq_uop_20_stq_idx}, {ldq_uop_19_stq_idx}, {ldq_uop_18_stq_idx}, {ldq_uop_17_stq_idx}, {ldq_uop_16_stq_idx}, {ldq_uop_15_stq_idx}, {ldq_uop_14_stq_idx}, {ldq_uop_13_stq_idx}, {ldq_uop_12_stq_idx}, {ldq_uop_11_stq_idx}, {ldq_uop_10_stq_idx}, {ldq_uop_9_stq_idx}, {ldq_uop_8_stq_idx}, {ldq_uop_7_stq_idx}, {ldq_uop_6_stq_idx}, {ldq_uop_5_stq_idx}, {ldq_uop_4_stq_idx}, {ldq_uop_3_stq_idx}, {ldq_uop_2_stq_idx}, {ldq_uop_1_stq_idx}, {ldq_uop_0_stq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stq_idx = _GEN_195[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_196 = {{ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_0_rxq_idx}, {ldq_uop_23_rxq_idx}, {ldq_uop_22_rxq_idx}, {ldq_uop_21_rxq_idx}, {ldq_uop_20_rxq_idx}, {ldq_uop_19_rxq_idx}, {ldq_uop_18_rxq_idx}, {ldq_uop_17_rxq_idx}, {ldq_uop_16_rxq_idx}, {ldq_uop_15_rxq_idx}, {ldq_uop_14_rxq_idx}, {ldq_uop_13_rxq_idx}, {ldq_uop_12_rxq_idx}, {ldq_uop_11_rxq_idx}, {ldq_uop_10_rxq_idx}, {ldq_uop_9_rxq_idx}, {ldq_uop_8_rxq_idx}, {ldq_uop_7_rxq_idx}, {ldq_uop_6_rxq_idx}, {ldq_uop_5_rxq_idx}, {ldq_uop_4_rxq_idx}, {ldq_uop_3_rxq_idx}, {ldq_uop_2_rxq_idx}, {ldq_uop_1_rxq_idx}, {ldq_uop_0_rxq_idx}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_rxq_idx = _GEN_196[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_197 = {{ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_0_pdst}, {ldq_uop_23_pdst}, {ldq_uop_22_pdst}, {ldq_uop_21_pdst}, {ldq_uop_20_pdst}, {ldq_uop_19_pdst}, {ldq_uop_18_pdst}, {ldq_uop_17_pdst}, {ldq_uop_16_pdst}, {ldq_uop_15_pdst}, {ldq_uop_14_pdst}, {ldq_uop_13_pdst}, {ldq_uop_12_pdst}, {ldq_uop_11_pdst}, {ldq_uop_10_pdst}, {ldq_uop_9_pdst}, {ldq_uop_8_pdst}, {ldq_uop_7_pdst}, {ldq_uop_6_pdst}, {ldq_uop_5_pdst}, {ldq_uop_4_pdst}, {ldq_uop_3_pdst}, {ldq_uop_2_pdst}, {ldq_uop_1_pdst}, {ldq_uop_0_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_pdst = _GEN_197[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_198 = {{ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_0_prs1}, {ldq_uop_23_prs1}, {ldq_uop_22_prs1}, {ldq_uop_21_prs1}, {ldq_uop_20_prs1}, {ldq_uop_19_prs1}, {ldq_uop_18_prs1}, {ldq_uop_17_prs1}, {ldq_uop_16_prs1}, {ldq_uop_15_prs1}, {ldq_uop_14_prs1}, {ldq_uop_13_prs1}, {ldq_uop_12_prs1}, {ldq_uop_11_prs1}, {ldq_uop_10_prs1}, {ldq_uop_9_prs1}, {ldq_uop_8_prs1}, {ldq_uop_7_prs1}, {ldq_uop_6_prs1}, {ldq_uop_5_prs1}, {ldq_uop_4_prs1}, {ldq_uop_3_prs1}, {ldq_uop_2_prs1}, {ldq_uop_1_prs1}, {ldq_uop_0_prs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1 = _GEN_198[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_199 = {{ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_0_prs2}, {ldq_uop_23_prs2}, {ldq_uop_22_prs2}, {ldq_uop_21_prs2}, {ldq_uop_20_prs2}, {ldq_uop_19_prs2}, {ldq_uop_18_prs2}, {ldq_uop_17_prs2}, {ldq_uop_16_prs2}, {ldq_uop_15_prs2}, {ldq_uop_14_prs2}, {ldq_uop_13_prs2}, {ldq_uop_12_prs2}, {ldq_uop_11_prs2}, {ldq_uop_10_prs2}, {ldq_uop_9_prs2}, {ldq_uop_8_prs2}, {ldq_uop_7_prs2}, {ldq_uop_6_prs2}, {ldq_uop_5_prs2}, {ldq_uop_4_prs2}, {ldq_uop_3_prs2}, {ldq_uop_2_prs2}, {ldq_uop_1_prs2}, {ldq_uop_0_prs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2 = _GEN_199[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_200 = {{ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_0_prs3}, {ldq_uop_23_prs3}, {ldq_uop_22_prs3}, {ldq_uop_21_prs3}, {ldq_uop_20_prs3}, {ldq_uop_19_prs3}, {ldq_uop_18_prs3}, {ldq_uop_17_prs3}, {ldq_uop_16_prs3}, {ldq_uop_15_prs3}, {ldq_uop_14_prs3}, {ldq_uop_13_prs3}, {ldq_uop_12_prs3}, {ldq_uop_11_prs3}, {ldq_uop_10_prs3}, {ldq_uop_9_prs3}, {ldq_uop_8_prs3}, {ldq_uop_7_prs3}, {ldq_uop_6_prs3}, {ldq_uop_5_prs3}, {ldq_uop_4_prs3}, {ldq_uop_3_prs3}, {ldq_uop_2_prs3}, {ldq_uop_1_prs3}, {ldq_uop_0_prs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3 = _GEN_200[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_201 = {{ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_0_ppred}, {ldq_uop_23_ppred}, {ldq_uop_22_ppred}, {ldq_uop_21_ppred}, {ldq_uop_20_ppred}, {ldq_uop_19_ppred}, {ldq_uop_18_ppred}, {ldq_uop_17_ppred}, {ldq_uop_16_ppred}, {ldq_uop_15_ppred}, {ldq_uop_14_ppred}, {ldq_uop_13_ppred}, {ldq_uop_12_ppred}, {ldq_uop_11_ppred}, {ldq_uop_10_ppred}, {ldq_uop_9_ppred}, {ldq_uop_8_ppred}, {ldq_uop_7_ppred}, {ldq_uop_6_ppred}, {ldq_uop_5_ppred}, {ldq_uop_4_ppred}, {ldq_uop_3_ppred}, {ldq_uop_2_ppred}, {ldq_uop_1_ppred}, {ldq_uop_0_ppred}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred = _GEN_201[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_202 = {{ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_0_prs1_busy}, {ldq_uop_23_prs1_busy}, {ldq_uop_22_prs1_busy}, {ldq_uop_21_prs1_busy}, {ldq_uop_20_prs1_busy}, {ldq_uop_19_prs1_busy}, {ldq_uop_18_prs1_busy}, {ldq_uop_17_prs1_busy}, {ldq_uop_16_prs1_busy}, {ldq_uop_15_prs1_busy}, {ldq_uop_14_prs1_busy}, {ldq_uop_13_prs1_busy}, {ldq_uop_12_prs1_busy}, {ldq_uop_11_prs1_busy}, {ldq_uop_10_prs1_busy}, {ldq_uop_9_prs1_busy}, {ldq_uop_8_prs1_busy}, {ldq_uop_7_prs1_busy}, {ldq_uop_6_prs1_busy}, {ldq_uop_5_prs1_busy}, {ldq_uop_4_prs1_busy}, {ldq_uop_3_prs1_busy}, {ldq_uop_2_prs1_busy}, {ldq_uop_1_prs1_busy}, {ldq_uop_0_prs1_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs1_busy = _GEN_202[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_203 = {{ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_0_prs2_busy}, {ldq_uop_23_prs2_busy}, {ldq_uop_22_prs2_busy}, {ldq_uop_21_prs2_busy}, {ldq_uop_20_prs2_busy}, {ldq_uop_19_prs2_busy}, {ldq_uop_18_prs2_busy}, {ldq_uop_17_prs2_busy}, {ldq_uop_16_prs2_busy}, {ldq_uop_15_prs2_busy}, {ldq_uop_14_prs2_busy}, {ldq_uop_13_prs2_busy}, {ldq_uop_12_prs2_busy}, {ldq_uop_11_prs2_busy}, {ldq_uop_10_prs2_busy}, {ldq_uop_9_prs2_busy}, {ldq_uop_8_prs2_busy}, {ldq_uop_7_prs2_busy}, {ldq_uop_6_prs2_busy}, {ldq_uop_5_prs2_busy}, {ldq_uop_4_prs2_busy}, {ldq_uop_3_prs2_busy}, {ldq_uop_2_prs2_busy}, {ldq_uop_1_prs2_busy}, {ldq_uop_0_prs2_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs2_busy = _GEN_203[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_204 = {{ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_0_prs3_busy}, {ldq_uop_23_prs3_busy}, {ldq_uop_22_prs3_busy}, {ldq_uop_21_prs3_busy}, {ldq_uop_20_prs3_busy}, {ldq_uop_19_prs3_busy}, {ldq_uop_18_prs3_busy}, {ldq_uop_17_prs3_busy}, {ldq_uop_16_prs3_busy}, {ldq_uop_15_prs3_busy}, {ldq_uop_14_prs3_busy}, {ldq_uop_13_prs3_busy}, {ldq_uop_12_prs3_busy}, {ldq_uop_11_prs3_busy}, {ldq_uop_10_prs3_busy}, {ldq_uop_9_prs3_busy}, {ldq_uop_8_prs3_busy}, {ldq_uop_7_prs3_busy}, {ldq_uop_6_prs3_busy}, {ldq_uop_5_prs3_busy}, {ldq_uop_4_prs3_busy}, {ldq_uop_3_prs3_busy}, {ldq_uop_2_prs3_busy}, {ldq_uop_1_prs3_busy}, {ldq_uop_0_prs3_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_prs3_busy = _GEN_204[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_205 = {{ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_0_ppred_busy}, {ldq_uop_23_ppred_busy}, {ldq_uop_22_ppred_busy}, {ldq_uop_21_ppred_busy}, {ldq_uop_20_ppred_busy}, {ldq_uop_19_ppred_busy}, {ldq_uop_18_ppred_busy}, {ldq_uop_17_ppred_busy}, {ldq_uop_16_ppred_busy}, {ldq_uop_15_ppred_busy}, {ldq_uop_14_ppred_busy}, {ldq_uop_13_ppred_busy}, {ldq_uop_12_ppred_busy}, {ldq_uop_11_ppred_busy}, {ldq_uop_10_ppred_busy}, {ldq_uop_9_ppred_busy}, {ldq_uop_8_ppred_busy}, {ldq_uop_7_ppred_busy}, {ldq_uop_6_ppred_busy}, {ldq_uop_5_ppred_busy}, {ldq_uop_4_ppred_busy}, {ldq_uop_3_ppred_busy}, {ldq_uop_2_ppred_busy}, {ldq_uop_1_ppred_busy}, {ldq_uop_0_ppred_busy}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ppred_busy = _GEN_205[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][6:0] _GEN_206 = {{ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_0_stale_pdst}, {ldq_uop_23_stale_pdst}, {ldq_uop_22_stale_pdst}, {ldq_uop_21_stale_pdst}, {ldq_uop_20_stale_pdst}, {ldq_uop_19_stale_pdst}, {ldq_uop_18_stale_pdst}, {ldq_uop_17_stale_pdst}, {ldq_uop_16_stale_pdst}, {ldq_uop_15_stale_pdst}, {ldq_uop_14_stale_pdst}, {ldq_uop_13_stale_pdst}, {ldq_uop_12_stale_pdst}, {ldq_uop_11_stale_pdst}, {ldq_uop_10_stale_pdst}, {ldq_uop_9_stale_pdst}, {ldq_uop_8_stale_pdst}, {ldq_uop_7_stale_pdst}, {ldq_uop_6_stale_pdst}, {ldq_uop_5_stale_pdst}, {ldq_uop_4_stale_pdst}, {ldq_uop_3_stale_pdst}, {ldq_uop_2_stale_pdst}, {ldq_uop_1_stale_pdst}, {ldq_uop_0_stale_pdst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_stale_pdst = _GEN_206[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_207 = {{ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_0_exception}, {ldq_uop_23_exception}, {ldq_uop_22_exception}, {ldq_uop_21_exception}, {ldq_uop_20_exception}, {ldq_uop_19_exception}, {ldq_uop_18_exception}, {ldq_uop_17_exception}, {ldq_uop_16_exception}, {ldq_uop_15_exception}, {ldq_uop_14_exception}, {ldq_uop_13_exception}, {ldq_uop_12_exception}, {ldq_uop_11_exception}, {ldq_uop_10_exception}, {ldq_uop_9_exception}, {ldq_uop_8_exception}, {ldq_uop_7_exception}, {ldq_uop_6_exception}, {ldq_uop_5_exception}, {ldq_uop_4_exception}, {ldq_uop_3_exception}, {ldq_uop_2_exception}, {ldq_uop_1_exception}, {ldq_uop_0_exception}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exception = _GEN_207[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][63:0] _GEN_208 = {{ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_0_exc_cause}, {ldq_uop_23_exc_cause}, {ldq_uop_22_exc_cause}, {ldq_uop_21_exc_cause}, {ldq_uop_20_exc_cause}, {ldq_uop_19_exc_cause}, {ldq_uop_18_exc_cause}, {ldq_uop_17_exc_cause}, {ldq_uop_16_exc_cause}, {ldq_uop_15_exc_cause}, {ldq_uop_14_exc_cause}, {ldq_uop_13_exc_cause}, {ldq_uop_12_exc_cause}, {ldq_uop_11_exc_cause}, {ldq_uop_10_exc_cause}, {ldq_uop_9_exc_cause}, {ldq_uop_8_exc_cause}, {ldq_uop_7_exc_cause}, {ldq_uop_6_exc_cause}, {ldq_uop_5_exc_cause}, {ldq_uop_4_exc_cause}, {ldq_uop_3_exc_cause}, {ldq_uop_2_exc_cause}, {ldq_uop_1_exc_cause}, {ldq_uop_0_exc_cause}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_exc_cause = _GEN_208[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_209 = {{ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_0_mem_cmd}, {ldq_uop_23_mem_cmd}, {ldq_uop_22_mem_cmd}, {ldq_uop_21_mem_cmd}, {ldq_uop_20_mem_cmd}, {ldq_uop_19_mem_cmd}, {ldq_uop_18_mem_cmd}, {ldq_uop_17_mem_cmd}, {ldq_uop_16_mem_cmd}, {ldq_uop_15_mem_cmd}, {ldq_uop_14_mem_cmd}, {ldq_uop_13_mem_cmd}, {ldq_uop_12_mem_cmd}, {ldq_uop_11_mem_cmd}, {ldq_uop_10_mem_cmd}, {ldq_uop_9_mem_cmd}, {ldq_uop_8_mem_cmd}, {ldq_uop_7_mem_cmd}, {ldq_uop_6_mem_cmd}, {ldq_uop_5_mem_cmd}, {ldq_uop_4_mem_cmd}, {ldq_uop_3_mem_cmd}, {ldq_uop_2_mem_cmd}, {ldq_uop_1_mem_cmd}, {ldq_uop_0_mem_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_cmd = _GEN_209[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_210 = {{ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_0_mem_size}, {ldq_uop_23_mem_size}, {ldq_uop_22_mem_size}, {ldq_uop_21_mem_size}, {ldq_uop_20_mem_size}, {ldq_uop_19_mem_size}, {ldq_uop_18_mem_size}, {ldq_uop_17_mem_size}, {ldq_uop_16_mem_size}, {ldq_uop_15_mem_size}, {ldq_uop_14_mem_size}, {ldq_uop_13_mem_size}, {ldq_uop_12_mem_size}, {ldq_uop_11_mem_size}, {ldq_uop_10_mem_size}, {ldq_uop_9_mem_size}, {ldq_uop_8_mem_size}, {ldq_uop_7_mem_size}, {ldq_uop_6_mem_size}, {ldq_uop_5_mem_size}, {ldq_uop_4_mem_size}, {ldq_uop_3_mem_size}, {ldq_uop_2_mem_size}, {ldq_uop_1_mem_size}, {ldq_uop_0_mem_size}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_size = _GEN_210[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_211 = {{ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_0_mem_signed}, {ldq_uop_23_mem_signed}, {ldq_uop_22_mem_signed}, {ldq_uop_21_mem_signed}, {ldq_uop_20_mem_signed}, {ldq_uop_19_mem_signed}, {ldq_uop_18_mem_signed}, {ldq_uop_17_mem_signed}, {ldq_uop_16_mem_signed}, {ldq_uop_15_mem_signed}, {ldq_uop_14_mem_signed}, {ldq_uop_13_mem_signed}, {ldq_uop_12_mem_signed}, {ldq_uop_11_mem_signed}, {ldq_uop_10_mem_signed}, {ldq_uop_9_mem_signed}, {ldq_uop_8_mem_signed}, {ldq_uop_7_mem_signed}, {ldq_uop_6_mem_signed}, {ldq_uop_5_mem_signed}, {ldq_uop_4_mem_signed}, {ldq_uop_3_mem_signed}, {ldq_uop_2_mem_signed}, {ldq_uop_1_mem_signed}, {ldq_uop_0_mem_signed}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_mem_signed = _GEN_211[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_212 = {{ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_0_uses_ldq}, {ldq_uop_23_uses_ldq}, {ldq_uop_22_uses_ldq}, {ldq_uop_21_uses_ldq}, {ldq_uop_20_uses_ldq}, {ldq_uop_19_uses_ldq}, {ldq_uop_18_uses_ldq}, {ldq_uop_17_uses_ldq}, {ldq_uop_16_uses_ldq}, {ldq_uop_15_uses_ldq}, {ldq_uop_14_uses_ldq}, {ldq_uop_13_uses_ldq}, {ldq_uop_12_uses_ldq}, {ldq_uop_11_uses_ldq}, {ldq_uop_10_uses_ldq}, {ldq_uop_9_uses_ldq}, {ldq_uop_8_uses_ldq}, {ldq_uop_7_uses_ldq}, {ldq_uop_6_uses_ldq}, {ldq_uop_5_uses_ldq}, {ldq_uop_4_uses_ldq}, {ldq_uop_3_uses_ldq}, {ldq_uop_2_uses_ldq}, {ldq_uop_1_uses_ldq}, {ldq_uop_0_uses_ldq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_ldq = _GEN_212[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_213 = {{ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_0_uses_stq}, {ldq_uop_23_uses_stq}, {ldq_uop_22_uses_stq}, {ldq_uop_21_uses_stq}, {ldq_uop_20_uses_stq}, {ldq_uop_19_uses_stq}, {ldq_uop_18_uses_stq}, {ldq_uop_17_uses_stq}, {ldq_uop_16_uses_stq}, {ldq_uop_15_uses_stq}, {ldq_uop_14_uses_stq}, {ldq_uop_13_uses_stq}, {ldq_uop_12_uses_stq}, {ldq_uop_11_uses_stq}, {ldq_uop_10_uses_stq}, {ldq_uop_9_uses_stq}, {ldq_uop_8_uses_stq}, {ldq_uop_7_uses_stq}, {ldq_uop_6_uses_stq}, {ldq_uop_5_uses_stq}, {ldq_uop_4_uses_stq}, {ldq_uop_3_uses_stq}, {ldq_uop_2_uses_stq}, {ldq_uop_1_uses_stq}, {ldq_uop_0_uses_stq}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_uses_stq = _GEN_213[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_214 = {{ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_0_is_unique}, {ldq_uop_23_is_unique}, {ldq_uop_22_is_unique}, {ldq_uop_21_is_unique}, {ldq_uop_20_is_unique}, {ldq_uop_19_is_unique}, {ldq_uop_18_is_unique}, {ldq_uop_17_is_unique}, {ldq_uop_16_is_unique}, {ldq_uop_15_is_unique}, {ldq_uop_14_is_unique}, {ldq_uop_13_is_unique}, {ldq_uop_12_is_unique}, {ldq_uop_11_is_unique}, {ldq_uop_10_is_unique}, {ldq_uop_9_is_unique}, {ldq_uop_8_is_unique}, {ldq_uop_7_is_unique}, {ldq_uop_6_is_unique}, {ldq_uop_5_is_unique}, {ldq_uop_4_is_unique}, {ldq_uop_3_is_unique}, {ldq_uop_2_is_unique}, {ldq_uop_1_is_unique}, {ldq_uop_0_is_unique}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_is_unique = _GEN_214[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_215 = {{ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_0_flush_on_commit}, {ldq_uop_23_flush_on_commit}, {ldq_uop_22_flush_on_commit}, {ldq_uop_21_flush_on_commit}, {ldq_uop_20_flush_on_commit}, {ldq_uop_19_flush_on_commit}, {ldq_uop_18_flush_on_commit}, {ldq_uop_17_flush_on_commit}, {ldq_uop_16_flush_on_commit}, {ldq_uop_15_flush_on_commit}, {ldq_uop_14_flush_on_commit}, {ldq_uop_13_flush_on_commit}, {ldq_uop_12_flush_on_commit}, {ldq_uop_11_flush_on_commit}, {ldq_uop_10_flush_on_commit}, {ldq_uop_9_flush_on_commit}, {ldq_uop_8_flush_on_commit}, {ldq_uop_7_flush_on_commit}, {ldq_uop_6_flush_on_commit}, {ldq_uop_5_flush_on_commit}, {ldq_uop_4_flush_on_commit}, {ldq_uop_3_flush_on_commit}, {ldq_uop_2_flush_on_commit}, {ldq_uop_1_flush_on_commit}, {ldq_uop_0_flush_on_commit}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_flush_on_commit = _GEN_215[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_216 = {{ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_0_csr_cmd}, {ldq_uop_23_csr_cmd}, {ldq_uop_22_csr_cmd}, {ldq_uop_21_csr_cmd}, {ldq_uop_20_csr_cmd}, {ldq_uop_19_csr_cmd}, {ldq_uop_18_csr_cmd}, {ldq_uop_17_csr_cmd}, {ldq_uop_16_csr_cmd}, {ldq_uop_15_csr_cmd}, {ldq_uop_14_csr_cmd}, {ldq_uop_13_csr_cmd}, {ldq_uop_12_csr_cmd}, {ldq_uop_11_csr_cmd}, {ldq_uop_10_csr_cmd}, {ldq_uop_9_csr_cmd}, {ldq_uop_8_csr_cmd}, {ldq_uop_7_csr_cmd}, {ldq_uop_6_csr_cmd}, {ldq_uop_5_csr_cmd}, {ldq_uop_4_csr_cmd}, {ldq_uop_3_csr_cmd}, {ldq_uop_2_csr_cmd}, {ldq_uop_1_csr_cmd}, {ldq_uop_0_csr_cmd}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_csr_cmd = _GEN_216[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_217 = {{ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}, {ldq_uop_23_ldst_is_rs1}, {ldq_uop_22_ldst_is_rs1}, {ldq_uop_21_ldst_is_rs1}, {ldq_uop_20_ldst_is_rs1}, {ldq_uop_19_ldst_is_rs1}, {ldq_uop_18_ldst_is_rs1}, {ldq_uop_17_ldst_is_rs1}, {ldq_uop_16_ldst_is_rs1}, {ldq_uop_15_ldst_is_rs1}, {ldq_uop_14_ldst_is_rs1}, {ldq_uop_13_ldst_is_rs1}, {ldq_uop_12_ldst_is_rs1}, {ldq_uop_11_ldst_is_rs1}, {ldq_uop_10_ldst_is_rs1}, {ldq_uop_9_ldst_is_rs1}, {ldq_uop_8_ldst_is_rs1}, {ldq_uop_7_ldst_is_rs1}, {ldq_uop_6_ldst_is_rs1}, {ldq_uop_5_ldst_is_rs1}, {ldq_uop_4_ldst_is_rs1}, {ldq_uop_3_ldst_is_rs1}, {ldq_uop_2_ldst_is_rs1}, {ldq_uop_1_ldst_is_rs1}, {ldq_uop_0_ldst_is_rs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_217[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_218 = {{ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_0_ldst}, {ldq_uop_23_ldst}, {ldq_uop_22_ldst}, {ldq_uop_21_ldst}, {ldq_uop_20_ldst}, {ldq_uop_19_ldst}, {ldq_uop_18_ldst}, {ldq_uop_17_ldst}, {ldq_uop_16_ldst}, {ldq_uop_15_ldst}, {ldq_uop_14_ldst}, {ldq_uop_13_ldst}, {ldq_uop_12_ldst}, {ldq_uop_11_ldst}, {ldq_uop_10_ldst}, {ldq_uop_9_ldst}, {ldq_uop_8_ldst}, {ldq_uop_7_ldst}, {ldq_uop_6_ldst}, {ldq_uop_5_ldst}, {ldq_uop_4_ldst}, {ldq_uop_3_ldst}, {ldq_uop_2_ldst}, {ldq_uop_1_ldst}, {ldq_uop_0_ldst}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_ldst = _GEN_218[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_219 = {{ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_0_lrs1}, {ldq_uop_23_lrs1}, {ldq_uop_22_lrs1}, {ldq_uop_21_lrs1}, {ldq_uop_20_lrs1}, {ldq_uop_19_lrs1}, {ldq_uop_18_lrs1}, {ldq_uop_17_lrs1}, {ldq_uop_16_lrs1}, {ldq_uop_15_lrs1}, {ldq_uop_14_lrs1}, {ldq_uop_13_lrs1}, {ldq_uop_12_lrs1}, {ldq_uop_11_lrs1}, {ldq_uop_10_lrs1}, {ldq_uop_9_lrs1}, {ldq_uop_8_lrs1}, {ldq_uop_7_lrs1}, {ldq_uop_6_lrs1}, {ldq_uop_5_lrs1}, {ldq_uop_4_lrs1}, {ldq_uop_3_lrs1}, {ldq_uop_2_lrs1}, {ldq_uop_1_lrs1}, {ldq_uop_0_lrs1}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1 = _GEN_219[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_220 = {{ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_0_lrs2}, {ldq_uop_23_lrs2}, {ldq_uop_22_lrs2}, {ldq_uop_21_lrs2}, {ldq_uop_20_lrs2}, {ldq_uop_19_lrs2}, {ldq_uop_18_lrs2}, {ldq_uop_17_lrs2}, {ldq_uop_16_lrs2}, {ldq_uop_15_lrs2}, {ldq_uop_14_lrs2}, {ldq_uop_13_lrs2}, {ldq_uop_12_lrs2}, {ldq_uop_11_lrs2}, {ldq_uop_10_lrs2}, {ldq_uop_9_lrs2}, {ldq_uop_8_lrs2}, {ldq_uop_7_lrs2}, {ldq_uop_6_lrs2}, {ldq_uop_5_lrs2}, {ldq_uop_4_lrs2}, {ldq_uop_3_lrs2}, {ldq_uop_2_lrs2}, {ldq_uop_1_lrs2}, {ldq_uop_0_lrs2}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2 = _GEN_220[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][5:0] _GEN_221 = {{ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_0_lrs3}, {ldq_uop_23_lrs3}, {ldq_uop_22_lrs3}, {ldq_uop_21_lrs3}, {ldq_uop_20_lrs3}, {ldq_uop_19_lrs3}, {ldq_uop_18_lrs3}, {ldq_uop_17_lrs3}, {ldq_uop_16_lrs3}, {ldq_uop_15_lrs3}, {ldq_uop_14_lrs3}, {ldq_uop_13_lrs3}, {ldq_uop_12_lrs3}, {ldq_uop_11_lrs3}, {ldq_uop_10_lrs3}, {ldq_uop_9_lrs3}, {ldq_uop_8_lrs3}, {ldq_uop_7_lrs3}, {ldq_uop_6_lrs3}, {ldq_uop_5_lrs3}, {ldq_uop_4_lrs3}, {ldq_uop_3_lrs3}, {ldq_uop_2_lrs3}, {ldq_uop_1_lrs3}, {ldq_uop_0_lrs3}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs3 = _GEN_221[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_222 = {{ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_0_dst_rtype}, {ldq_uop_23_dst_rtype}, {ldq_uop_22_dst_rtype}, {ldq_uop_21_dst_rtype}, {ldq_uop_20_dst_rtype}, {ldq_uop_19_dst_rtype}, {ldq_uop_18_dst_rtype}, {ldq_uop_17_dst_rtype}, {ldq_uop_16_dst_rtype}, {ldq_uop_15_dst_rtype}, {ldq_uop_14_dst_rtype}, {ldq_uop_13_dst_rtype}, {ldq_uop_12_dst_rtype}, {ldq_uop_11_dst_rtype}, {ldq_uop_10_dst_rtype}, {ldq_uop_9_dst_rtype}, {ldq_uop_8_dst_rtype}, {ldq_uop_7_dst_rtype}, {ldq_uop_6_dst_rtype}, {ldq_uop_5_dst_rtype}, {ldq_uop_4_dst_rtype}, {ldq_uop_3_dst_rtype}, {ldq_uop_2_dst_rtype}, {ldq_uop_1_dst_rtype}, {ldq_uop_0_dst_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_dst_rtype = _GEN_222[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_223 = {{ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}, {ldq_uop_23_lrs1_rtype}, {ldq_uop_22_lrs1_rtype}, {ldq_uop_21_lrs1_rtype}, {ldq_uop_20_lrs1_rtype}, {ldq_uop_19_lrs1_rtype}, {ldq_uop_18_lrs1_rtype}, {ldq_uop_17_lrs1_rtype}, {ldq_uop_16_lrs1_rtype}, {ldq_uop_15_lrs1_rtype}, {ldq_uop_14_lrs1_rtype}, {ldq_uop_13_lrs1_rtype}, {ldq_uop_12_lrs1_rtype}, {ldq_uop_11_lrs1_rtype}, {ldq_uop_10_lrs1_rtype}, {ldq_uop_9_lrs1_rtype}, {ldq_uop_8_lrs1_rtype}, {ldq_uop_7_lrs1_rtype}, {ldq_uop_6_lrs1_rtype}, {ldq_uop_5_lrs1_rtype}, {ldq_uop_4_lrs1_rtype}, {ldq_uop_3_lrs1_rtype}, {ldq_uop_2_lrs1_rtype}, {ldq_uop_1_lrs1_rtype}, {ldq_uop_0_lrs1_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_223[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_224 = {{ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}, {ldq_uop_23_lrs2_rtype}, {ldq_uop_22_lrs2_rtype}, {ldq_uop_21_lrs2_rtype}, {ldq_uop_20_lrs2_rtype}, {ldq_uop_19_lrs2_rtype}, {ldq_uop_18_lrs2_rtype}, {ldq_uop_17_lrs2_rtype}, {ldq_uop_16_lrs2_rtype}, {ldq_uop_15_lrs2_rtype}, {ldq_uop_14_lrs2_rtype}, {ldq_uop_13_lrs2_rtype}, {ldq_uop_12_lrs2_rtype}, {ldq_uop_11_lrs2_rtype}, {ldq_uop_10_lrs2_rtype}, {ldq_uop_9_lrs2_rtype}, {ldq_uop_8_lrs2_rtype}, {ldq_uop_7_lrs2_rtype}, {ldq_uop_6_lrs2_rtype}, {ldq_uop_5_lrs2_rtype}, {ldq_uop_4_lrs2_rtype}, {ldq_uop_3_lrs2_rtype}, {ldq_uop_2_lrs2_rtype}, {ldq_uop_1_lrs2_rtype}, {ldq_uop_0_lrs2_rtype}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_224[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_225 = {{ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_0_frs3_en}, {ldq_uop_23_frs3_en}, {ldq_uop_22_frs3_en}, {ldq_uop_21_frs3_en}, {ldq_uop_20_frs3_en}, {ldq_uop_19_frs3_en}, {ldq_uop_18_frs3_en}, {ldq_uop_17_frs3_en}, {ldq_uop_16_frs3_en}, {ldq_uop_15_frs3_en}, {ldq_uop_14_frs3_en}, {ldq_uop_13_frs3_en}, {ldq_uop_12_frs3_en}, {ldq_uop_11_frs3_en}, {ldq_uop_10_frs3_en}, {ldq_uop_9_frs3_en}, {ldq_uop_8_frs3_en}, {ldq_uop_7_frs3_en}, {ldq_uop_6_frs3_en}, {ldq_uop_5_frs3_en}, {ldq_uop_4_frs3_en}, {ldq_uop_3_frs3_en}, {ldq_uop_2_frs3_en}, {ldq_uop_1_frs3_en}, {ldq_uop_0_frs3_en}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_frs3_en = _GEN_225[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_226 = {{ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_0_fcn_dw}, {ldq_uop_23_fcn_dw}, {ldq_uop_22_fcn_dw}, {ldq_uop_21_fcn_dw}, {ldq_uop_20_fcn_dw}, {ldq_uop_19_fcn_dw}, {ldq_uop_18_fcn_dw}, {ldq_uop_17_fcn_dw}, {ldq_uop_16_fcn_dw}, {ldq_uop_15_fcn_dw}, {ldq_uop_14_fcn_dw}, {ldq_uop_13_fcn_dw}, {ldq_uop_12_fcn_dw}, {ldq_uop_11_fcn_dw}, {ldq_uop_10_fcn_dw}, {ldq_uop_9_fcn_dw}, {ldq_uop_8_fcn_dw}, {ldq_uop_7_fcn_dw}, {ldq_uop_6_fcn_dw}, {ldq_uop_5_fcn_dw}, {ldq_uop_4_fcn_dw}, {ldq_uop_3_fcn_dw}, {ldq_uop_2_fcn_dw}, {ldq_uop_1_fcn_dw}, {ldq_uop_0_fcn_dw}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_dw = _GEN_226[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][4:0] _GEN_227 = {{ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_0_fcn_op}, {ldq_uop_23_fcn_op}, {ldq_uop_22_fcn_op}, {ldq_uop_21_fcn_op}, {ldq_uop_20_fcn_op}, {ldq_uop_19_fcn_op}, {ldq_uop_18_fcn_op}, {ldq_uop_17_fcn_op}, {ldq_uop_16_fcn_op}, {ldq_uop_15_fcn_op}, {ldq_uop_14_fcn_op}, {ldq_uop_13_fcn_op}, {ldq_uop_12_fcn_op}, {ldq_uop_11_fcn_op}, {ldq_uop_10_fcn_op}, {ldq_uop_9_fcn_op}, {ldq_uop_8_fcn_op}, {ldq_uop_7_fcn_op}, {ldq_uop_6_fcn_op}, {ldq_uop_5_fcn_op}, {ldq_uop_4_fcn_op}, {ldq_uop_3_fcn_op}, {ldq_uop_2_fcn_op}, {ldq_uop_1_fcn_op}, {ldq_uop_0_fcn_op}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fcn_op = _GEN_227[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_228 = {{ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_0_fp_val}, {ldq_uop_23_fp_val}, {ldq_uop_22_fp_val}, {ldq_uop_21_fp_val}, {ldq_uop_20_fp_val}, {ldq_uop_19_fp_val}, {ldq_uop_18_fp_val}, {ldq_uop_17_fp_val}, {ldq_uop_16_fp_val}, {ldq_uop_15_fp_val}, {ldq_uop_14_fp_val}, {ldq_uop_13_fp_val}, {ldq_uop_12_fp_val}, {ldq_uop_11_fp_val}, {ldq_uop_10_fp_val}, {ldq_uop_9_fp_val}, {ldq_uop_8_fp_val}, {ldq_uop_7_fp_val}, {ldq_uop_6_fp_val}, {ldq_uop_5_fp_val}, {ldq_uop_4_fp_val}, {ldq_uop_3_fp_val}, {ldq_uop_2_fp_val}, {ldq_uop_1_fp_val}, {ldq_uop_0_fp_val}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_val = _GEN_228[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_229 = {{ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_0_fp_rm}, {ldq_uop_23_fp_rm}, {ldq_uop_22_fp_rm}, {ldq_uop_21_fp_rm}, {ldq_uop_20_fp_rm}, {ldq_uop_19_fp_rm}, {ldq_uop_18_fp_rm}, {ldq_uop_17_fp_rm}, {ldq_uop_16_fp_rm}, {ldq_uop_15_fp_rm}, {ldq_uop_14_fp_rm}, {ldq_uop_13_fp_rm}, {ldq_uop_12_fp_rm}, {ldq_uop_11_fp_rm}, {ldq_uop_10_fp_rm}, {ldq_uop_9_fp_rm}, {ldq_uop_8_fp_rm}, {ldq_uop_7_fp_rm}, {ldq_uop_6_fp_rm}, {ldq_uop_5_fp_rm}, {ldq_uop_4_fp_rm}, {ldq_uop_3_fp_rm}, {ldq_uop_2_fp_rm}, {ldq_uop_1_fp_rm}, {ldq_uop_0_fp_rm}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_rm = _GEN_229[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][1:0] _GEN_230 = {{ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_0_fp_typ}, {ldq_uop_23_fp_typ}, {ldq_uop_22_fp_typ}, {ldq_uop_21_fp_typ}, {ldq_uop_20_fp_typ}, {ldq_uop_19_fp_typ}, {ldq_uop_18_fp_typ}, {ldq_uop_17_fp_typ}, {ldq_uop_16_fp_typ}, {ldq_uop_15_fp_typ}, {ldq_uop_14_fp_typ}, {ldq_uop_13_fp_typ}, {ldq_uop_12_fp_typ}, {ldq_uop_11_fp_typ}, {ldq_uop_10_fp_typ}, {ldq_uop_9_fp_typ}, {ldq_uop_8_fp_typ}, {ldq_uop_7_fp_typ}, {ldq_uop_6_fp_typ}, {ldq_uop_5_fp_typ}, {ldq_uop_4_fp_typ}, {ldq_uop_3_fp_typ}, {ldq_uop_2_fp_typ}, {ldq_uop_1_fp_typ}, {ldq_uop_0_fp_typ}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_fp_typ = _GEN_230[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_231 = {{ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}, {ldq_uop_23_xcpt_pf_if}, {ldq_uop_22_xcpt_pf_if}, {ldq_uop_21_xcpt_pf_if}, {ldq_uop_20_xcpt_pf_if}, {ldq_uop_19_xcpt_pf_if}, {ldq_uop_18_xcpt_pf_if}, {ldq_uop_17_xcpt_pf_if}, {ldq_uop_16_xcpt_pf_if}, {ldq_uop_15_xcpt_pf_if}, {ldq_uop_14_xcpt_pf_if}, {ldq_uop_13_xcpt_pf_if}, {ldq_uop_12_xcpt_pf_if}, {ldq_uop_11_xcpt_pf_if}, {ldq_uop_10_xcpt_pf_if}, {ldq_uop_9_xcpt_pf_if}, {ldq_uop_8_xcpt_pf_if}, {ldq_uop_7_xcpt_pf_if}, {ldq_uop_6_xcpt_pf_if}, {ldq_uop_5_xcpt_pf_if}, {ldq_uop_4_xcpt_pf_if}, {ldq_uop_3_xcpt_pf_if}, {ldq_uop_2_xcpt_pf_if}, {ldq_uop_1_xcpt_pf_if}, {ldq_uop_0_xcpt_pf_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_231[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_232 = {{ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}, {ldq_uop_23_xcpt_ae_if}, {ldq_uop_22_xcpt_ae_if}, {ldq_uop_21_xcpt_ae_if}, {ldq_uop_20_xcpt_ae_if}, {ldq_uop_19_xcpt_ae_if}, {ldq_uop_18_xcpt_ae_if}, {ldq_uop_17_xcpt_ae_if}, {ldq_uop_16_xcpt_ae_if}, {ldq_uop_15_xcpt_ae_if}, {ldq_uop_14_xcpt_ae_if}, {ldq_uop_13_xcpt_ae_if}, {ldq_uop_12_xcpt_ae_if}, {ldq_uop_11_xcpt_ae_if}, {ldq_uop_10_xcpt_ae_if}, {ldq_uop_9_xcpt_ae_if}, {ldq_uop_8_xcpt_ae_if}, {ldq_uop_7_xcpt_ae_if}, {ldq_uop_6_xcpt_ae_if}, {ldq_uop_5_xcpt_ae_if}, {ldq_uop_4_xcpt_ae_if}, {ldq_uop_3_xcpt_ae_if}, {ldq_uop_2_xcpt_ae_if}, {ldq_uop_1_xcpt_ae_if}, {ldq_uop_0_xcpt_ae_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_232[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_233 = {{ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}, {ldq_uop_23_xcpt_ma_if}, {ldq_uop_22_xcpt_ma_if}, {ldq_uop_21_xcpt_ma_if}, {ldq_uop_20_xcpt_ma_if}, {ldq_uop_19_xcpt_ma_if}, {ldq_uop_18_xcpt_ma_if}, {ldq_uop_17_xcpt_ma_if}, {ldq_uop_16_xcpt_ma_if}, {ldq_uop_15_xcpt_ma_if}, {ldq_uop_14_xcpt_ma_if}, {ldq_uop_13_xcpt_ma_if}, {ldq_uop_12_xcpt_ma_if}, {ldq_uop_11_xcpt_ma_if}, {ldq_uop_10_xcpt_ma_if}, {ldq_uop_9_xcpt_ma_if}, {ldq_uop_8_xcpt_ma_if}, {ldq_uop_7_xcpt_ma_if}, {ldq_uop_6_xcpt_ma_if}, {ldq_uop_5_xcpt_ma_if}, {ldq_uop_4_xcpt_ma_if}, {ldq_uop_3_xcpt_ma_if}, {ldq_uop_2_xcpt_ma_if}, {ldq_uop_1_xcpt_ma_if}, {ldq_uop_0_xcpt_ma_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_233[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_234 = {{ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_0_bp_debug_if}, {ldq_uop_23_bp_debug_if}, {ldq_uop_22_bp_debug_if}, {ldq_uop_21_bp_debug_if}, {ldq_uop_20_bp_debug_if}, {ldq_uop_19_bp_debug_if}, {ldq_uop_18_bp_debug_if}, {ldq_uop_17_bp_debug_if}, {ldq_uop_16_bp_debug_if}, {ldq_uop_15_bp_debug_if}, {ldq_uop_14_bp_debug_if}, {ldq_uop_13_bp_debug_if}, {ldq_uop_12_bp_debug_if}, {ldq_uop_11_bp_debug_if}, {ldq_uop_10_bp_debug_if}, {ldq_uop_9_bp_debug_if}, {ldq_uop_8_bp_debug_if}, {ldq_uop_7_bp_debug_if}, {ldq_uop_6_bp_debug_if}, {ldq_uop_5_bp_debug_if}, {ldq_uop_4_bp_debug_if}, {ldq_uop_3_bp_debug_if}, {ldq_uop_2_bp_debug_if}, {ldq_uop_1_bp_debug_if}, {ldq_uop_0_bp_debug_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_debug_if = _GEN_234[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_235 = {{ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}, {ldq_uop_23_bp_xcpt_if}, {ldq_uop_22_bp_xcpt_if}, {ldq_uop_21_bp_xcpt_if}, {ldq_uop_20_bp_xcpt_if}, {ldq_uop_19_bp_xcpt_if}, {ldq_uop_18_bp_xcpt_if}, {ldq_uop_17_bp_xcpt_if}, {ldq_uop_16_bp_xcpt_if}, {ldq_uop_15_bp_xcpt_if}, {ldq_uop_14_bp_xcpt_if}, {ldq_uop_13_bp_xcpt_if}, {ldq_uop_12_bp_xcpt_if}, {ldq_uop_11_bp_xcpt_if}, {ldq_uop_10_bp_xcpt_if}, {ldq_uop_9_bp_xcpt_if}, {ldq_uop_8_bp_xcpt_if}, {ldq_uop_7_bp_xcpt_if}, {ldq_uop_6_bp_xcpt_if}, {ldq_uop_5_bp_xcpt_if}, {ldq_uop_4_bp_xcpt_if}, {ldq_uop_3_bp_xcpt_if}, {ldq_uop_2_bp_xcpt_if}, {ldq_uop_1_bp_xcpt_if}, {ldq_uop_0_bp_xcpt_if}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_235[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_236 = {{ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_0_debug_fsrc}, {ldq_uop_23_debug_fsrc}, {ldq_uop_22_debug_fsrc}, {ldq_uop_21_debug_fsrc}, {ldq_uop_20_debug_fsrc}, {ldq_uop_19_debug_fsrc}, {ldq_uop_18_debug_fsrc}, {ldq_uop_17_debug_fsrc}, {ldq_uop_16_debug_fsrc}, {ldq_uop_15_debug_fsrc}, {ldq_uop_14_debug_fsrc}, {ldq_uop_13_debug_fsrc}, {ldq_uop_12_debug_fsrc}, {ldq_uop_11_debug_fsrc}, {ldq_uop_10_debug_fsrc}, {ldq_uop_9_debug_fsrc}, {ldq_uop_8_debug_fsrc}, {ldq_uop_7_debug_fsrc}, {ldq_uop_6_debug_fsrc}, {ldq_uop_5_debug_fsrc}, {ldq_uop_4_debug_fsrc}, {ldq_uop_3_debug_fsrc}, {ldq_uop_2_debug_fsrc}, {ldq_uop_1_debug_fsrc}, {ldq_uop_0_debug_fsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_fsrc = _GEN_236[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0][2:0] _GEN_237 = {{ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_0_debug_tsrc}, {ldq_uop_23_debug_tsrc}, {ldq_uop_22_debug_tsrc}, {ldq_uop_21_debug_tsrc}, {ldq_uop_20_debug_tsrc}, {ldq_uop_19_debug_tsrc}, {ldq_uop_18_debug_tsrc}, {ldq_uop_17_debug_tsrc}, {ldq_uop_16_debug_tsrc}, {ldq_uop_15_debug_tsrc}, {ldq_uop_14_debug_tsrc}, {ldq_uop_13_debug_tsrc}, {ldq_uop_12_debug_tsrc}, {ldq_uop_11_debug_tsrc}, {ldq_uop_10_debug_tsrc}, {ldq_uop_9_debug_tsrc}, {ldq_uop_8_debug_tsrc}, {ldq_uop_7_debug_tsrc}, {ldq_uop_6_debug_tsrc}, {ldq_uop_5_debug_tsrc}, {ldq_uop_4_debug_tsrc}, {ldq_uop_3_debug_tsrc}, {ldq_uop_2_debug_tsrc}, {ldq_uop_1_debug_tsrc}, {ldq_uop_0_debug_tsrc}}; // @[lsu.scala:219:36, :235:32] assign ldq_incoming_e_e_bits_uop_debug_tsrc = _GEN_237[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :235:32, :321:49] wire [31:0] _GEN_238 = {{ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_0_valid}, {ldq_addr_23_valid}, {ldq_addr_22_valid}, {ldq_addr_21_valid}, {ldq_addr_20_valid}, {ldq_addr_19_valid}, {ldq_addr_18_valid}, {ldq_addr_17_valid}, {ldq_addr_16_valid}, {ldq_addr_15_valid}, {ldq_addr_14_valid}, {ldq_addr_13_valid}, {ldq_addr_12_valid}, {ldq_addr_11_valid}, {ldq_addr_10_valid}, {ldq_addr_9_valid}, {ldq_addr_8_valid}, {ldq_addr_7_valid}, {ldq_addr_6_valid}, {ldq_addr_5_valid}, {ldq_addr_4_valid}, {ldq_addr_3_valid}, {ldq_addr_2_valid}, {ldq_addr_1_valid}, {ldq_addr_0_valid}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_valid = _GEN_238[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [31:0][39:0] _GEN_239 = {{ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_0_bits}, {ldq_addr_23_bits}, {ldq_addr_22_bits}, {ldq_addr_21_bits}, {ldq_addr_20_bits}, {ldq_addr_19_bits}, {ldq_addr_18_bits}, {ldq_addr_17_bits}, {ldq_addr_16_bits}, {ldq_addr_15_bits}, {ldq_addr_14_bits}, {ldq_addr_13_bits}, {ldq_addr_12_bits}, {ldq_addr_11_bits}, {ldq_addr_10_bits}, {ldq_addr_9_bits}, {ldq_addr_8_bits}, {ldq_addr_7_bits}, {ldq_addr_6_bits}, {ldq_addr_5_bits}, {ldq_addr_4_bits}, {ldq_addr_3_bits}, {ldq_addr_2_bits}, {ldq_addr_1_bits}, {ldq_addr_0_bits}}; // @[lsu.scala:220:36, :236:32] assign ldq_incoming_e_e_bits_addr_bits = _GEN_239[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :236:32, :321:49] wire [31:0] _GEN_240 = {{ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_0}, {ldq_addr_is_virtual_23}, {ldq_addr_is_virtual_22}, {ldq_addr_is_virtual_21}, {ldq_addr_is_virtual_20}, {ldq_addr_is_virtual_19}, {ldq_addr_is_virtual_18}, {ldq_addr_is_virtual_17}, {ldq_addr_is_virtual_16}, {ldq_addr_is_virtual_15}, {ldq_addr_is_virtual_14}, {ldq_addr_is_virtual_13}, {ldq_addr_is_virtual_12}, {ldq_addr_is_virtual_11}, {ldq_addr_is_virtual_10}, {ldq_addr_is_virtual_9}, {ldq_addr_is_virtual_8}, {ldq_addr_is_virtual_7}, {ldq_addr_is_virtual_6}, {ldq_addr_is_virtual_5}, {ldq_addr_is_virtual_4}, {ldq_addr_is_virtual_3}, {ldq_addr_is_virtual_2}, {ldq_addr_is_virtual_1}, {ldq_addr_is_virtual_0}}; // @[lsu.scala:221:36, :237:32] assign ldq_incoming_e_e_bits_addr_is_virtual = _GEN_240[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :237:32, :321:49] wire [31:0] _GEN_241 = {{ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_0}, {ldq_addr_is_uncacheable_23}, {ldq_addr_is_uncacheable_22}, {ldq_addr_is_uncacheable_21}, {ldq_addr_is_uncacheable_20}, {ldq_addr_is_uncacheable_19}, {ldq_addr_is_uncacheable_18}, {ldq_addr_is_uncacheable_17}, {ldq_addr_is_uncacheable_16}, {ldq_addr_is_uncacheable_15}, {ldq_addr_is_uncacheable_14}, {ldq_addr_is_uncacheable_13}, {ldq_addr_is_uncacheable_12}, {ldq_addr_is_uncacheable_11}, {ldq_addr_is_uncacheable_10}, {ldq_addr_is_uncacheable_9}, {ldq_addr_is_uncacheable_8}, {ldq_addr_is_uncacheable_7}, {ldq_addr_is_uncacheable_6}, {ldq_addr_is_uncacheable_5}, {ldq_addr_is_uncacheable_4}, {ldq_addr_is_uncacheable_3}, {ldq_addr_is_uncacheable_2}, {ldq_addr_is_uncacheable_1}, {ldq_addr_is_uncacheable_0}}; // @[lsu.scala:222:36, :238:32] assign ldq_incoming_e_e_bits_addr_is_uncacheable = _GEN_241[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :238:32, :321:49] wire [31:0] _GEN_242 = {{ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_0}, {ldq_executed_23}, {ldq_executed_22}, {ldq_executed_21}, {ldq_executed_20}, {ldq_executed_19}, {ldq_executed_18}, {ldq_executed_17}, {ldq_executed_16}, {ldq_executed_15}, {ldq_executed_14}, {ldq_executed_13}, {ldq_executed_12}, {ldq_executed_11}, {ldq_executed_10}, {ldq_executed_9}, {ldq_executed_8}, {ldq_executed_7}, {ldq_executed_6}, {ldq_executed_5}, {ldq_executed_4}, {ldq_executed_3}, {ldq_executed_2}, {ldq_executed_1}, {ldq_executed_0}}; // @[lsu.scala:223:36, :239:32] assign ldq_incoming_e_e_bits_executed = _GEN_242[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :239:32, :321:49] wire [31:0] _GEN_243 = {{ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_0}, {ldq_succeeded_23}, {ldq_succeeded_22}, {ldq_succeeded_21}, {ldq_succeeded_20}, {ldq_succeeded_19}, {ldq_succeeded_18}, {ldq_succeeded_17}, {ldq_succeeded_16}, {ldq_succeeded_15}, {ldq_succeeded_14}, {ldq_succeeded_13}, {ldq_succeeded_12}, {ldq_succeeded_11}, {ldq_succeeded_10}, {ldq_succeeded_9}, {ldq_succeeded_8}, {ldq_succeeded_7}, {ldq_succeeded_6}, {ldq_succeeded_5}, {ldq_succeeded_4}, {ldq_succeeded_3}, {ldq_succeeded_2}, {ldq_succeeded_1}, {ldq_succeeded_0}}; // @[lsu.scala:224:36, :240:32] assign ldq_incoming_e_e_bits_succeeded = _GEN_243[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :240:32, :321:49] wire [31:0] _GEN_244 = {{ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_0}, {ldq_order_fail_23}, {ldq_order_fail_22}, {ldq_order_fail_21}, {ldq_order_fail_20}, {ldq_order_fail_19}, {ldq_order_fail_18}, {ldq_order_fail_17}, {ldq_order_fail_16}, {ldq_order_fail_15}, {ldq_order_fail_14}, {ldq_order_fail_13}, {ldq_order_fail_12}, {ldq_order_fail_11}, {ldq_order_fail_10}, {ldq_order_fail_9}, {ldq_order_fail_8}, {ldq_order_fail_7}, {ldq_order_fail_6}, {ldq_order_fail_5}, {ldq_order_fail_4}, {ldq_order_fail_3}, {ldq_order_fail_2}, {ldq_order_fail_1}, {ldq_order_fail_0}}; // @[lsu.scala:225:36, :241:32] assign ldq_incoming_e_e_bits_order_fail = _GEN_244[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :241:32, :321:49] wire [31:0] _GEN_245 = {{ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_0}, {ldq_observed_23}, {ldq_observed_22}, {ldq_observed_21}, {ldq_observed_20}, {ldq_observed_19}, {ldq_observed_18}, {ldq_observed_17}, {ldq_observed_16}, {ldq_observed_15}, {ldq_observed_14}, {ldq_observed_13}, {ldq_observed_12}, {ldq_observed_11}, {ldq_observed_10}, {ldq_observed_9}, {ldq_observed_8}, {ldq_observed_7}, {ldq_observed_6}, {ldq_observed_5}, {ldq_observed_4}, {ldq_observed_3}, {ldq_observed_2}, {ldq_observed_1}, {ldq_observed_0}}; // @[lsu.scala:226:36, :242:32] assign ldq_incoming_e_e_bits_observed = _GEN_245[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :242:32, :321:49] wire [31:0][23:0] _GEN_246 = {{ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_0}, {ldq_st_dep_mask_23}, {ldq_st_dep_mask_22}, {ldq_st_dep_mask_21}, {ldq_st_dep_mask_20}, {ldq_st_dep_mask_19}, {ldq_st_dep_mask_18}, {ldq_st_dep_mask_17}, {ldq_st_dep_mask_16}, {ldq_st_dep_mask_15}, {ldq_st_dep_mask_14}, {ldq_st_dep_mask_13}, {ldq_st_dep_mask_12}, {ldq_st_dep_mask_11}, {ldq_st_dep_mask_10}, {ldq_st_dep_mask_9}, {ldq_st_dep_mask_8}, {ldq_st_dep_mask_7}, {ldq_st_dep_mask_6}, {ldq_st_dep_mask_5}, {ldq_st_dep_mask_4}, {ldq_st_dep_mask_3}, {ldq_st_dep_mask_2}, {ldq_st_dep_mask_1}, {ldq_st_dep_mask_0}}; // @[lsu.scala:227:36, :243:32] assign ldq_incoming_e_e_bits_st_dep_mask = _GEN_246[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :243:32, :321:49] wire [31:0][7:0] _GEN_247 = {{ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_0}, {ldq_ld_byte_mask_23}, {ldq_ld_byte_mask_22}, {ldq_ld_byte_mask_21}, {ldq_ld_byte_mask_20}, {ldq_ld_byte_mask_19}, {ldq_ld_byte_mask_18}, {ldq_ld_byte_mask_17}, {ldq_ld_byte_mask_16}, {ldq_ld_byte_mask_15}, {ldq_ld_byte_mask_14}, {ldq_ld_byte_mask_13}, {ldq_ld_byte_mask_12}, {ldq_ld_byte_mask_11}, {ldq_ld_byte_mask_10}, {ldq_ld_byte_mask_9}, {ldq_ld_byte_mask_8}, {ldq_ld_byte_mask_7}, {ldq_ld_byte_mask_6}, {ldq_ld_byte_mask_5}, {ldq_ld_byte_mask_4}, {ldq_ld_byte_mask_3}, {ldq_ld_byte_mask_2}, {ldq_ld_byte_mask_1}, {ldq_ld_byte_mask_0}}; // @[lsu.scala:228:36, :244:32] assign ldq_incoming_e_e_bits_ld_byte_mask = _GEN_247[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :244:32, :321:49] wire [31:0] _GEN_248 = {{ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_0}, {ldq_forward_std_val_23}, {ldq_forward_std_val_22}, {ldq_forward_std_val_21}, {ldq_forward_std_val_20}, {ldq_forward_std_val_19}, {ldq_forward_std_val_18}, {ldq_forward_std_val_17}, {ldq_forward_std_val_16}, {ldq_forward_std_val_15}, {ldq_forward_std_val_14}, {ldq_forward_std_val_13}, {ldq_forward_std_val_12}, {ldq_forward_std_val_11}, {ldq_forward_std_val_10}, {ldq_forward_std_val_9}, {ldq_forward_std_val_8}, {ldq_forward_std_val_7}, {ldq_forward_std_val_6}, {ldq_forward_std_val_5}, {ldq_forward_std_val_4}, {ldq_forward_std_val_3}, {ldq_forward_std_val_2}, {ldq_forward_std_val_1}, {ldq_forward_std_val_0}}; // @[lsu.scala:229:36, :245:32] assign ldq_incoming_e_e_bits_forward_std_val = _GEN_248[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :245:32, :321:49] wire [31:0][4:0] _GEN_249 = {{ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_0}, {ldq_forward_stq_idx_23}, {ldq_forward_stq_idx_22}, {ldq_forward_stq_idx_21}, {ldq_forward_stq_idx_20}, {ldq_forward_stq_idx_19}, {ldq_forward_stq_idx_18}, {ldq_forward_stq_idx_17}, {ldq_forward_stq_idx_16}, {ldq_forward_stq_idx_15}, {ldq_forward_stq_idx_14}, {ldq_forward_stq_idx_13}, {ldq_forward_stq_idx_12}, {ldq_forward_stq_idx_11}, {ldq_forward_stq_idx_10}, {ldq_forward_stq_idx_9}, {ldq_forward_stq_idx_8}, {ldq_forward_stq_idx_7}, {ldq_forward_stq_idx_6}, {ldq_forward_stq_idx_5}, {ldq_forward_stq_idx_4}, {ldq_forward_stq_idx_3}, {ldq_forward_stq_idx_2}, {ldq_forward_stq_idx_1}, {ldq_forward_stq_idx_0}}; // @[lsu.scala:230:36, :246:32] assign ldq_incoming_e_e_bits_forward_stq_idx = _GEN_249[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :246:32, :321:49] wire [31:0][63:0] _GEN_250 = {{ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_0}, {ldq_debug_wb_data_23}, {ldq_debug_wb_data_22}, {ldq_debug_wb_data_21}, {ldq_debug_wb_data_20}, {ldq_debug_wb_data_19}, {ldq_debug_wb_data_18}, {ldq_debug_wb_data_17}, {ldq_debug_wb_data_16}, {ldq_debug_wb_data_15}, {ldq_debug_wb_data_14}, {ldq_debug_wb_data_13}, {ldq_debug_wb_data_12}, {ldq_debug_wb_data_11}, {ldq_debug_wb_data_10}, {ldq_debug_wb_data_9}, {ldq_debug_wb_data_8}, {ldq_debug_wb_data_7}, {ldq_debug_wb_data_6}, {ldq_debug_wb_data_5}, {ldq_debug_wb_data_4}, {ldq_debug_wb_data_3}, {ldq_debug_wb_data_2}, {ldq_debug_wb_data_1}, {ldq_debug_wb_data_0}}; // @[lsu.scala:231:36, :247:32] assign ldq_incoming_e_e_bits_debug_wb_data = _GEN_250[ldq_incoming_idx_0]; // @[lsu.scala:233:17, :247:32, :321:49] wire ldq_incoming_e_0_valid = _ldq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_inst = _ldq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :501:48] wire [31:0] ldq_incoming_e_0_bits_uop_debug_inst = _ldq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rvc = _ldq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_uop_debug_pc = _ldq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_0 = _ldq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_1 = _ldq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_2 = _ldq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iq_type_3 = _ldq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_0 = _ldq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_1 = _ldq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_2 = _ldq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_3 = _ldq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_4 = _ldq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_5 = _ldq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_6 = _ldq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_7 = _ldq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_8 = _ldq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fu_code_9 = _ldq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued = _ldq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_agen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _ldq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_iw_p1_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_iw_p2_speculative_child = _ldq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _ldq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_dis_col_sel = _ldq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :501:48] wire [15:0] ldq_incoming_e_0_bits_uop_br_mask = _ldq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_tag = _ldq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :501:48] wire [3:0] ldq_incoming_e_0_bits_uop_br_type = _ldq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfb = _ldq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fence = _ldq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_fencei = _ldq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sfence = _ldq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_amo = _ldq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_eret = _ldq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_sys_pc2epc = _ldq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_rocc = _ldq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_mov = _ldq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ftq_idx = _ldq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_edge_inst = _ldq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_pc_lob = _ldq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_taken = _ldq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_imm_rename = _ldq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_imm_sel = _ldq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_pimm = _ldq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :501:48] wire [19:0] ldq_incoming_e_0_bits_uop_imm_packed = _ldq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_op1_sel = _ldq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_op2_sel = _ldq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ldst = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wen = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fromint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_toint = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_fma = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_div = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_wflags = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_ctrl_vec = _ldq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_rob_idx = _ldq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ldq_idx = _ldq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_stq_idx = _ldq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_rxq_idx = _ldq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_pdst = _ldq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs1 = _ldq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs2 = _ldq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_prs3 = _ldq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_ppred = _ldq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs1_busy = _ldq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs2_busy = _ldq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_prs3_busy = _ldq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ppred_busy = _ldq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :501:48] wire [6:0] ldq_incoming_e_0_bits_uop_stale_pdst = _ldq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_exception = _ldq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_uop_exc_cause = _ldq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_mem_cmd = _ldq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_mem_size = _ldq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_mem_signed = _ldq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_ldq = _ldq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_uses_stq = _ldq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_is_unique = _ldq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_flush_on_commit = _ldq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_csr_cmd = _ldq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_ldst_is_rs1 = _ldq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_ldst = _ldq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs1 = _ldq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs2 = _ldq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :501:48] wire [5:0] ldq_incoming_e_0_bits_uop_lrs3 = _ldq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_dst_rtype = _ldq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs1_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_lrs2_rtype = _ldq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_frs3_en = _ldq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fcn_dw = _ldq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_uop_fcn_op = _ldq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_fp_val = _ldq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_fp_rm = _ldq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :501:48] wire [1:0] ldq_incoming_e_0_bits_uop_fp_typ = _ldq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_pf_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ae_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_xcpt_ma_if = _ldq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_debug_if = _ldq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_uop_bp_xcpt_if = _ldq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_fsrc = _ldq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :501:48] wire [2:0] ldq_incoming_e_0_bits_uop_debug_tsrc = _ldq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_valid = _ldq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :501:48] wire [39:0] ldq_incoming_e_0_bits_addr_bits = _ldq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_virtual = _ldq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_addr_is_uncacheable = _ldq_incoming_e_WIRE_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_executed = _ldq_incoming_e_WIRE_bits_executed; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_succeeded = _ldq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_order_fail = _ldq_incoming_e_WIRE_bits_order_fail; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_observed = _ldq_incoming_e_WIRE_bits_observed; // @[lsu.scala:321:49, :501:48] wire [23:0] ldq_incoming_e_0_bits_st_dep_mask = _ldq_incoming_e_WIRE_bits_st_dep_mask; // @[lsu.scala:321:49, :501:48] wire [7:0] ldq_incoming_e_0_bits_ld_byte_mask = _ldq_incoming_e_WIRE_bits_ld_byte_mask; // @[lsu.scala:321:49, :501:48] wire ldq_incoming_e_0_bits_forward_std_val = _ldq_incoming_e_WIRE_bits_forward_std_val; // @[lsu.scala:321:49, :501:48] wire [4:0] ldq_incoming_e_0_bits_forward_stq_idx = _ldq_incoming_e_WIRE_bits_forward_stq_idx; // @[lsu.scala:321:49, :501:48] wire [63:0] ldq_incoming_e_0_bits_debug_wb_data = _ldq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :501:48] wire [31:0] mem_ldq_incoming_e_out_bits_uop_inst = ldq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_incoming_e_out_bits_uop_debug_inst = ldq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rvc = ldq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_uop_debug_pc = ldq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_0 = ldq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_1 = ldq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_2 = ldq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iq_type_3 = ldq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_0 = ldq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_1 = ldq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_2 = ldq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_3 = ldq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_4 = ldq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_5 = ldq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_6 = ldq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_7 = ldq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_8 = ldq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fu_code_9 = ldq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued = ldq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen = ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen = ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child = ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child = ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint = ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_dis_col_sel = ldq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_tag = ldq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_incoming_e_out_bits_uop_br_type = ldq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfb = ldq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fence = ldq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_fencei = ldq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sfence = ldq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_amo = ldq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_eret = ldq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc = ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_rocc = ldq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_mov = ldq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ftq_idx = ldq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_edge_inst = ldq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_pc_lob = ldq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_taken = ldq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_imm_rename = ldq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_imm_sel = ldq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_pimm = ldq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_incoming_e_out_bits_uop_imm_packed = ldq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_op1_sel = ldq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_op2_sel = ldq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst = ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen = ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3 = ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23 = ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint = ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint = ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma = ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div = ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt = ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags = ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec = ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_rob_idx = ldq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ldq_idx = ldq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_stq_idx = ldq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_rxq_idx = ldq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_pdst = ldq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs1 = ldq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs2 = ldq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_prs3 = ldq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_ppred = ldq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs1_busy = ldq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs2_busy = ldq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_prs3_busy = ldq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ppred_busy = ldq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_incoming_e_out_bits_uop_stale_pdst = ldq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_exception = ldq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_uop_exc_cause = ldq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_mem_cmd = ldq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_mem_size = ldq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_mem_signed = ldq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_ldq = ldq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_uses_stq = ldq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_is_unique = ldq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_flush_on_commit = ldq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_csr_cmd = ldq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1 = ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_ldst = ldq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs1 = ldq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs2 = ldq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_incoming_e_out_bits_uop_lrs3 = ldq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_dst_rtype = ldq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs1_rtype = ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_lrs2_rtype = ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_frs3_en = ldq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fcn_dw = ldq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_uop_fcn_op = ldq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_fp_val = ldq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_fp_rm = ldq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_incoming_e_out_bits_uop_fp_typ = ldq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if = ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if = ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if = ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_debug_if = ldq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if = ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_fsrc = ldq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_incoming_e_out_bits_uop_debug_tsrc = ldq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_valid = ldq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_incoming_e_out_bits_addr_bits = ldq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_virtual = ldq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_addr_is_uncacheable = ldq_incoming_e_0_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_executed = ldq_incoming_e_0_bits_executed; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_succeeded = ldq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_order_fail = ldq_incoming_e_0_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_observed = ldq_incoming_e_0_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_incoming_e_out_bits_st_dep_mask = ldq_incoming_e_0_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_incoming_e_out_bits_ld_byte_mask = ldq_incoming_e_0_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_incoming_e_out_bits_forward_std_val = ldq_incoming_e_0_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_incoming_e_out_bits_forward_stq_idx = ldq_incoming_e_0_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_incoming_e_out_bits_debug_wb_data = ldq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire _stq_incoming_e_WIRE_valid = stq_incoming_e_e_valid; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_inst = stq_incoming_e_e_bits_uop_inst; // @[lsu.scala:262:17, :504:48] wire [31:0] _stq_incoming_e_WIRE_bits_uop_debug_inst = stq_incoming_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rvc = stq_incoming_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_uop_debug_pc = stq_incoming_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_0 = stq_incoming_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_1 = stq_incoming_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_2 = stq_incoming_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iq_type_3 = stq_incoming_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_0 = stq_incoming_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_1 = stq_incoming_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_2 = stq_incoming_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_3 = stq_incoming_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_4 = stq_incoming_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_5 = stq_incoming_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_6 = stq_incoming_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_7 = stq_incoming_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_8 = stq_incoming_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fu_code_9 = stq_incoming_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued = stq_incoming_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen = stq_incoming_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen = stq_incoming_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child = stq_incoming_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child = stq_incoming_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint = stq_incoming_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint = stq_incoming_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint = stq_incoming_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_dis_col_sel = stq_incoming_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :504:48] wire [15:0] _stq_incoming_e_WIRE_bits_uop_br_mask = stq_incoming_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_tag = stq_incoming_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :504:48] wire [3:0] _stq_incoming_e_WIRE_bits_uop_br_type = stq_incoming_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfb = stq_incoming_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fence = stq_incoming_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_fencei = stq_incoming_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sfence = stq_incoming_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_amo = stq_incoming_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_eret = stq_incoming_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc = stq_incoming_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_rocc = stq_incoming_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_mov = stq_incoming_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ftq_idx = stq_incoming_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_edge_inst = stq_incoming_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_pc_lob = stq_incoming_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_taken = stq_incoming_e_e_bits_uop_taken; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_imm_rename = stq_incoming_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_imm_sel = stq_incoming_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_pimm = stq_incoming_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :504:48] wire [19:0] _stq_incoming_e_WIRE_bits_uop_imm_packed = stq_incoming_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_op1_sel = stq_incoming_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_op2_sel = stq_incoming_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst = stq_incoming_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen = stq_incoming_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1 = stq_incoming_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2 = stq_incoming_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3 = stq_incoming_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12 = stq_incoming_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23 = stq_incoming_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint = stq_incoming_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint = stq_incoming_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma = stq_incoming_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div = stq_incoming_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt = stq_incoming_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags = stq_incoming_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec = stq_incoming_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_rob_idx = stq_incoming_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ldq_idx = stq_incoming_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_stq_idx = stq_incoming_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_rxq_idx = stq_incoming_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_pdst = stq_incoming_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs1 = stq_incoming_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs2 = stq_incoming_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_prs3 = stq_incoming_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_ppred = stq_incoming_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs1_busy = stq_incoming_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs2_busy = stq_incoming_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_prs3_busy = stq_incoming_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ppred_busy = stq_incoming_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :504:48] wire [6:0] _stq_incoming_e_WIRE_bits_uop_stale_pdst = stq_incoming_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_exception = stq_incoming_e_e_bits_uop_exception; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_uop_exc_cause = stq_incoming_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_mem_cmd = stq_incoming_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_mem_size = stq_incoming_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_mem_signed = stq_incoming_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_ldq = stq_incoming_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_uses_stq = stq_incoming_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_is_unique = stq_incoming_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_flush_on_commit = stq_incoming_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_csr_cmd = stq_incoming_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1 = stq_incoming_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_ldst = stq_incoming_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs1 = stq_incoming_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs2 = stq_incoming_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :504:48] wire [5:0] _stq_incoming_e_WIRE_bits_uop_lrs3 = stq_incoming_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_dst_rtype = stq_incoming_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs1_rtype = stq_incoming_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_lrs2_rtype = stq_incoming_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_frs3_en = stq_incoming_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fcn_dw = stq_incoming_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :504:48] wire [4:0] _stq_incoming_e_WIRE_bits_uop_fcn_op = stq_incoming_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_fp_val = stq_incoming_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_fp_rm = stq_incoming_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :504:48] wire [1:0] _stq_incoming_e_WIRE_bits_uop_fp_typ = stq_incoming_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if = stq_incoming_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if = stq_incoming_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if = stq_incoming_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_debug_if = stq_incoming_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if = stq_incoming_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_fsrc = stq_incoming_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :504:48] wire [2:0] _stq_incoming_e_WIRE_bits_uop_debug_tsrc = stq_incoming_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_valid = stq_incoming_e_e_bits_addr_valid; // @[lsu.scala:262:17, :504:48] wire [39:0] _stq_incoming_e_WIRE_bits_addr_bits = stq_incoming_e_e_bits_addr_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_addr_is_virtual = stq_incoming_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_data_valid = stq_incoming_e_e_bits_data_valid; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_data_bits = stq_incoming_e_e_bits_data_bits; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_committed = stq_incoming_e_e_bits_committed; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_succeeded = stq_incoming_e_e_bits_succeeded; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_can_execute = stq_incoming_e_e_bits_can_execute; // @[lsu.scala:262:17, :504:48] wire _stq_incoming_e_WIRE_bits_cleared = stq_incoming_e_e_bits_cleared; // @[lsu.scala:262:17, :504:48] wire [63:0] _stq_incoming_e_WIRE_bits_debug_wb_data = stq_incoming_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :504:48] assign stq_incoming_e_e_valid = _GEN_26[stq_incoming_idx_0]; // @[lsu.scala:262:17, :263:32, :321:49, :392:15] wire [31:0][31:0] _GEN_251 = {{stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_0_inst}, {stq_uop_23_inst}, {stq_uop_22_inst}, {stq_uop_21_inst}, {stq_uop_20_inst}, {stq_uop_19_inst}, {stq_uop_18_inst}, {stq_uop_17_inst}, {stq_uop_16_inst}, {stq_uop_15_inst}, {stq_uop_14_inst}, {stq_uop_13_inst}, {stq_uop_12_inst}, {stq_uop_11_inst}, {stq_uop_10_inst}, {stq_uop_9_inst}, {stq_uop_8_inst}, {stq_uop_7_inst}, {stq_uop_6_inst}, {stq_uop_5_inst}, {stq_uop_4_inst}, {stq_uop_3_inst}, {stq_uop_2_inst}, {stq_uop_1_inst}, {stq_uop_0_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_inst = _GEN_251[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][31:0] _GEN_252 = {{stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_0_debug_inst}, {stq_uop_23_debug_inst}, {stq_uop_22_debug_inst}, {stq_uop_21_debug_inst}, {stq_uop_20_debug_inst}, {stq_uop_19_debug_inst}, {stq_uop_18_debug_inst}, {stq_uop_17_debug_inst}, {stq_uop_16_debug_inst}, {stq_uop_15_debug_inst}, {stq_uop_14_debug_inst}, {stq_uop_13_debug_inst}, {stq_uop_12_debug_inst}, {stq_uop_11_debug_inst}, {stq_uop_10_debug_inst}, {stq_uop_9_debug_inst}, {stq_uop_8_debug_inst}, {stq_uop_7_debug_inst}, {stq_uop_6_debug_inst}, {stq_uop_5_debug_inst}, {stq_uop_4_debug_inst}, {stq_uop_3_debug_inst}, {stq_uop_2_debug_inst}, {stq_uop_1_debug_inst}, {stq_uop_0_debug_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_inst = _GEN_252[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_253 = {{stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_0_is_rvc}, {stq_uop_23_is_rvc}, {stq_uop_22_is_rvc}, {stq_uop_21_is_rvc}, {stq_uop_20_is_rvc}, {stq_uop_19_is_rvc}, {stq_uop_18_is_rvc}, {stq_uop_17_is_rvc}, {stq_uop_16_is_rvc}, {stq_uop_15_is_rvc}, {stq_uop_14_is_rvc}, {stq_uop_13_is_rvc}, {stq_uop_12_is_rvc}, {stq_uop_11_is_rvc}, {stq_uop_10_is_rvc}, {stq_uop_9_is_rvc}, {stq_uop_8_is_rvc}, {stq_uop_7_is_rvc}, {stq_uop_6_is_rvc}, {stq_uop_5_is_rvc}, {stq_uop_4_is_rvc}, {stq_uop_3_is_rvc}, {stq_uop_2_is_rvc}, {stq_uop_1_is_rvc}, {stq_uop_0_is_rvc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rvc = _GEN_253[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][39:0] _GEN_254 = {{stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_0_debug_pc}, {stq_uop_23_debug_pc}, {stq_uop_22_debug_pc}, {stq_uop_21_debug_pc}, {stq_uop_20_debug_pc}, {stq_uop_19_debug_pc}, {stq_uop_18_debug_pc}, {stq_uop_17_debug_pc}, {stq_uop_16_debug_pc}, {stq_uop_15_debug_pc}, {stq_uop_14_debug_pc}, {stq_uop_13_debug_pc}, {stq_uop_12_debug_pc}, {stq_uop_11_debug_pc}, {stq_uop_10_debug_pc}, {stq_uop_9_debug_pc}, {stq_uop_8_debug_pc}, {stq_uop_7_debug_pc}, {stq_uop_6_debug_pc}, {stq_uop_5_debug_pc}, {stq_uop_4_debug_pc}, {stq_uop_3_debug_pc}, {stq_uop_2_debug_pc}, {stq_uop_1_debug_pc}, {stq_uop_0_debug_pc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_pc = _GEN_254[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_255 = {{stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_0_iq_type_0}, {stq_uop_23_iq_type_0}, {stq_uop_22_iq_type_0}, {stq_uop_21_iq_type_0}, {stq_uop_20_iq_type_0}, {stq_uop_19_iq_type_0}, {stq_uop_18_iq_type_0}, {stq_uop_17_iq_type_0}, {stq_uop_16_iq_type_0}, {stq_uop_15_iq_type_0}, {stq_uop_14_iq_type_0}, {stq_uop_13_iq_type_0}, {stq_uop_12_iq_type_0}, {stq_uop_11_iq_type_0}, {stq_uop_10_iq_type_0}, {stq_uop_9_iq_type_0}, {stq_uop_8_iq_type_0}, {stq_uop_7_iq_type_0}, {stq_uop_6_iq_type_0}, {stq_uop_5_iq_type_0}, {stq_uop_4_iq_type_0}, {stq_uop_3_iq_type_0}, {stq_uop_2_iq_type_0}, {stq_uop_1_iq_type_0}, {stq_uop_0_iq_type_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_0 = _GEN_255[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_256 = {{stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_0_iq_type_1}, {stq_uop_23_iq_type_1}, {stq_uop_22_iq_type_1}, {stq_uop_21_iq_type_1}, {stq_uop_20_iq_type_1}, {stq_uop_19_iq_type_1}, {stq_uop_18_iq_type_1}, {stq_uop_17_iq_type_1}, {stq_uop_16_iq_type_1}, {stq_uop_15_iq_type_1}, {stq_uop_14_iq_type_1}, {stq_uop_13_iq_type_1}, {stq_uop_12_iq_type_1}, {stq_uop_11_iq_type_1}, {stq_uop_10_iq_type_1}, {stq_uop_9_iq_type_1}, {stq_uop_8_iq_type_1}, {stq_uop_7_iq_type_1}, {stq_uop_6_iq_type_1}, {stq_uop_5_iq_type_1}, {stq_uop_4_iq_type_1}, {stq_uop_3_iq_type_1}, {stq_uop_2_iq_type_1}, {stq_uop_1_iq_type_1}, {stq_uop_0_iq_type_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_1 = _GEN_256[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_257 = {{stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_0_iq_type_2}, {stq_uop_23_iq_type_2}, {stq_uop_22_iq_type_2}, {stq_uop_21_iq_type_2}, {stq_uop_20_iq_type_2}, {stq_uop_19_iq_type_2}, {stq_uop_18_iq_type_2}, {stq_uop_17_iq_type_2}, {stq_uop_16_iq_type_2}, {stq_uop_15_iq_type_2}, {stq_uop_14_iq_type_2}, {stq_uop_13_iq_type_2}, {stq_uop_12_iq_type_2}, {stq_uop_11_iq_type_2}, {stq_uop_10_iq_type_2}, {stq_uop_9_iq_type_2}, {stq_uop_8_iq_type_2}, {stq_uop_7_iq_type_2}, {stq_uop_6_iq_type_2}, {stq_uop_5_iq_type_2}, {stq_uop_4_iq_type_2}, {stq_uop_3_iq_type_2}, {stq_uop_2_iq_type_2}, {stq_uop_1_iq_type_2}, {stq_uop_0_iq_type_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_2 = _GEN_257[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_258 = {{stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_0_iq_type_3}, {stq_uop_23_iq_type_3}, {stq_uop_22_iq_type_3}, {stq_uop_21_iq_type_3}, {stq_uop_20_iq_type_3}, {stq_uop_19_iq_type_3}, {stq_uop_18_iq_type_3}, {stq_uop_17_iq_type_3}, {stq_uop_16_iq_type_3}, {stq_uop_15_iq_type_3}, {stq_uop_14_iq_type_3}, {stq_uop_13_iq_type_3}, {stq_uop_12_iq_type_3}, {stq_uop_11_iq_type_3}, {stq_uop_10_iq_type_3}, {stq_uop_9_iq_type_3}, {stq_uop_8_iq_type_3}, {stq_uop_7_iq_type_3}, {stq_uop_6_iq_type_3}, {stq_uop_5_iq_type_3}, {stq_uop_4_iq_type_3}, {stq_uop_3_iq_type_3}, {stq_uop_2_iq_type_3}, {stq_uop_1_iq_type_3}, {stq_uop_0_iq_type_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iq_type_3 = _GEN_258[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_259 = {{stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_0_fu_code_0}, {stq_uop_23_fu_code_0}, {stq_uop_22_fu_code_0}, {stq_uop_21_fu_code_0}, {stq_uop_20_fu_code_0}, {stq_uop_19_fu_code_0}, {stq_uop_18_fu_code_0}, {stq_uop_17_fu_code_0}, {stq_uop_16_fu_code_0}, {stq_uop_15_fu_code_0}, {stq_uop_14_fu_code_0}, {stq_uop_13_fu_code_0}, {stq_uop_12_fu_code_0}, {stq_uop_11_fu_code_0}, {stq_uop_10_fu_code_0}, {stq_uop_9_fu_code_0}, {stq_uop_8_fu_code_0}, {stq_uop_7_fu_code_0}, {stq_uop_6_fu_code_0}, {stq_uop_5_fu_code_0}, {stq_uop_4_fu_code_0}, {stq_uop_3_fu_code_0}, {stq_uop_2_fu_code_0}, {stq_uop_1_fu_code_0}, {stq_uop_0_fu_code_0}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_0 = _GEN_259[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_260 = {{stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_0_fu_code_1}, {stq_uop_23_fu_code_1}, {stq_uop_22_fu_code_1}, {stq_uop_21_fu_code_1}, {stq_uop_20_fu_code_1}, {stq_uop_19_fu_code_1}, {stq_uop_18_fu_code_1}, {stq_uop_17_fu_code_1}, {stq_uop_16_fu_code_1}, {stq_uop_15_fu_code_1}, {stq_uop_14_fu_code_1}, {stq_uop_13_fu_code_1}, {stq_uop_12_fu_code_1}, {stq_uop_11_fu_code_1}, {stq_uop_10_fu_code_1}, {stq_uop_9_fu_code_1}, {stq_uop_8_fu_code_1}, {stq_uop_7_fu_code_1}, {stq_uop_6_fu_code_1}, {stq_uop_5_fu_code_1}, {stq_uop_4_fu_code_1}, {stq_uop_3_fu_code_1}, {stq_uop_2_fu_code_1}, {stq_uop_1_fu_code_1}, {stq_uop_0_fu_code_1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_1 = _GEN_260[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_261 = {{stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_0_fu_code_2}, {stq_uop_23_fu_code_2}, {stq_uop_22_fu_code_2}, {stq_uop_21_fu_code_2}, {stq_uop_20_fu_code_2}, {stq_uop_19_fu_code_2}, {stq_uop_18_fu_code_2}, {stq_uop_17_fu_code_2}, {stq_uop_16_fu_code_2}, {stq_uop_15_fu_code_2}, {stq_uop_14_fu_code_2}, {stq_uop_13_fu_code_2}, {stq_uop_12_fu_code_2}, {stq_uop_11_fu_code_2}, {stq_uop_10_fu_code_2}, {stq_uop_9_fu_code_2}, {stq_uop_8_fu_code_2}, {stq_uop_7_fu_code_2}, {stq_uop_6_fu_code_2}, {stq_uop_5_fu_code_2}, {stq_uop_4_fu_code_2}, {stq_uop_3_fu_code_2}, {stq_uop_2_fu_code_2}, {stq_uop_1_fu_code_2}, {stq_uop_0_fu_code_2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_2 = _GEN_261[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_262 = {{stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_0_fu_code_3}, {stq_uop_23_fu_code_3}, {stq_uop_22_fu_code_3}, {stq_uop_21_fu_code_3}, {stq_uop_20_fu_code_3}, {stq_uop_19_fu_code_3}, {stq_uop_18_fu_code_3}, {stq_uop_17_fu_code_3}, {stq_uop_16_fu_code_3}, {stq_uop_15_fu_code_3}, {stq_uop_14_fu_code_3}, {stq_uop_13_fu_code_3}, {stq_uop_12_fu_code_3}, {stq_uop_11_fu_code_3}, {stq_uop_10_fu_code_3}, {stq_uop_9_fu_code_3}, {stq_uop_8_fu_code_3}, {stq_uop_7_fu_code_3}, {stq_uop_6_fu_code_3}, {stq_uop_5_fu_code_3}, {stq_uop_4_fu_code_3}, {stq_uop_3_fu_code_3}, {stq_uop_2_fu_code_3}, {stq_uop_1_fu_code_3}, {stq_uop_0_fu_code_3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_3 = _GEN_262[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_263 = {{stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_0_fu_code_4}, {stq_uop_23_fu_code_4}, {stq_uop_22_fu_code_4}, {stq_uop_21_fu_code_4}, {stq_uop_20_fu_code_4}, {stq_uop_19_fu_code_4}, {stq_uop_18_fu_code_4}, {stq_uop_17_fu_code_4}, {stq_uop_16_fu_code_4}, {stq_uop_15_fu_code_4}, {stq_uop_14_fu_code_4}, {stq_uop_13_fu_code_4}, {stq_uop_12_fu_code_4}, {stq_uop_11_fu_code_4}, {stq_uop_10_fu_code_4}, {stq_uop_9_fu_code_4}, {stq_uop_8_fu_code_4}, {stq_uop_7_fu_code_4}, {stq_uop_6_fu_code_4}, {stq_uop_5_fu_code_4}, {stq_uop_4_fu_code_4}, {stq_uop_3_fu_code_4}, {stq_uop_2_fu_code_4}, {stq_uop_1_fu_code_4}, {stq_uop_0_fu_code_4}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_4 = _GEN_263[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_264 = {{stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_0_fu_code_5}, {stq_uop_23_fu_code_5}, {stq_uop_22_fu_code_5}, {stq_uop_21_fu_code_5}, {stq_uop_20_fu_code_5}, {stq_uop_19_fu_code_5}, {stq_uop_18_fu_code_5}, {stq_uop_17_fu_code_5}, {stq_uop_16_fu_code_5}, {stq_uop_15_fu_code_5}, {stq_uop_14_fu_code_5}, {stq_uop_13_fu_code_5}, {stq_uop_12_fu_code_5}, {stq_uop_11_fu_code_5}, {stq_uop_10_fu_code_5}, {stq_uop_9_fu_code_5}, {stq_uop_8_fu_code_5}, {stq_uop_7_fu_code_5}, {stq_uop_6_fu_code_5}, {stq_uop_5_fu_code_5}, {stq_uop_4_fu_code_5}, {stq_uop_3_fu_code_5}, {stq_uop_2_fu_code_5}, {stq_uop_1_fu_code_5}, {stq_uop_0_fu_code_5}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_5 = _GEN_264[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_265 = {{stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_0_fu_code_6}, {stq_uop_23_fu_code_6}, {stq_uop_22_fu_code_6}, {stq_uop_21_fu_code_6}, {stq_uop_20_fu_code_6}, {stq_uop_19_fu_code_6}, {stq_uop_18_fu_code_6}, {stq_uop_17_fu_code_6}, {stq_uop_16_fu_code_6}, {stq_uop_15_fu_code_6}, {stq_uop_14_fu_code_6}, {stq_uop_13_fu_code_6}, {stq_uop_12_fu_code_6}, {stq_uop_11_fu_code_6}, {stq_uop_10_fu_code_6}, {stq_uop_9_fu_code_6}, {stq_uop_8_fu_code_6}, {stq_uop_7_fu_code_6}, {stq_uop_6_fu_code_6}, {stq_uop_5_fu_code_6}, {stq_uop_4_fu_code_6}, {stq_uop_3_fu_code_6}, {stq_uop_2_fu_code_6}, {stq_uop_1_fu_code_6}, {stq_uop_0_fu_code_6}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_6 = _GEN_265[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_266 = {{stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_0_fu_code_7}, {stq_uop_23_fu_code_7}, {stq_uop_22_fu_code_7}, {stq_uop_21_fu_code_7}, {stq_uop_20_fu_code_7}, {stq_uop_19_fu_code_7}, {stq_uop_18_fu_code_7}, {stq_uop_17_fu_code_7}, {stq_uop_16_fu_code_7}, {stq_uop_15_fu_code_7}, {stq_uop_14_fu_code_7}, {stq_uop_13_fu_code_7}, {stq_uop_12_fu_code_7}, {stq_uop_11_fu_code_7}, {stq_uop_10_fu_code_7}, {stq_uop_9_fu_code_7}, {stq_uop_8_fu_code_7}, {stq_uop_7_fu_code_7}, {stq_uop_6_fu_code_7}, {stq_uop_5_fu_code_7}, {stq_uop_4_fu_code_7}, {stq_uop_3_fu_code_7}, {stq_uop_2_fu_code_7}, {stq_uop_1_fu_code_7}, {stq_uop_0_fu_code_7}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_7 = _GEN_266[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_267 = {{stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_0_fu_code_8}, {stq_uop_23_fu_code_8}, {stq_uop_22_fu_code_8}, {stq_uop_21_fu_code_8}, {stq_uop_20_fu_code_8}, {stq_uop_19_fu_code_8}, {stq_uop_18_fu_code_8}, {stq_uop_17_fu_code_8}, {stq_uop_16_fu_code_8}, {stq_uop_15_fu_code_8}, {stq_uop_14_fu_code_8}, {stq_uop_13_fu_code_8}, {stq_uop_12_fu_code_8}, {stq_uop_11_fu_code_8}, {stq_uop_10_fu_code_8}, {stq_uop_9_fu_code_8}, {stq_uop_8_fu_code_8}, {stq_uop_7_fu_code_8}, {stq_uop_6_fu_code_8}, {stq_uop_5_fu_code_8}, {stq_uop_4_fu_code_8}, {stq_uop_3_fu_code_8}, {stq_uop_2_fu_code_8}, {stq_uop_1_fu_code_8}, {stq_uop_0_fu_code_8}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_8 = _GEN_267[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_268 = {{stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_0_fu_code_9}, {stq_uop_23_fu_code_9}, {stq_uop_22_fu_code_9}, {stq_uop_21_fu_code_9}, {stq_uop_20_fu_code_9}, {stq_uop_19_fu_code_9}, {stq_uop_18_fu_code_9}, {stq_uop_17_fu_code_9}, {stq_uop_16_fu_code_9}, {stq_uop_15_fu_code_9}, {stq_uop_14_fu_code_9}, {stq_uop_13_fu_code_9}, {stq_uop_12_fu_code_9}, {stq_uop_11_fu_code_9}, {stq_uop_10_fu_code_9}, {stq_uop_9_fu_code_9}, {stq_uop_8_fu_code_9}, {stq_uop_7_fu_code_9}, {stq_uop_6_fu_code_9}, {stq_uop_5_fu_code_9}, {stq_uop_4_fu_code_9}, {stq_uop_3_fu_code_9}, {stq_uop_2_fu_code_9}, {stq_uop_1_fu_code_9}, {stq_uop_0_fu_code_9}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fu_code_9 = _GEN_268[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_269 = {{stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_0_iw_issued}, {stq_uop_23_iw_issued}, {stq_uop_22_iw_issued}, {stq_uop_21_iw_issued}, {stq_uop_20_iw_issued}, {stq_uop_19_iw_issued}, {stq_uop_18_iw_issued}, {stq_uop_17_iw_issued}, {stq_uop_16_iw_issued}, {stq_uop_15_iw_issued}, {stq_uop_14_iw_issued}, {stq_uop_13_iw_issued}, {stq_uop_12_iw_issued}, {stq_uop_11_iw_issued}, {stq_uop_10_iw_issued}, {stq_uop_9_iw_issued}, {stq_uop_8_iw_issued}, {stq_uop_7_iw_issued}, {stq_uop_6_iw_issued}, {stq_uop_5_iw_issued}, {stq_uop_4_iw_issued}, {stq_uop_3_iw_issued}, {stq_uop_2_iw_issued}, {stq_uop_1_iw_issued}, {stq_uop_0_iw_issued}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued = _GEN_269[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_270 = {{stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}, {stq_uop_23_iw_issued_partial_agen}, {stq_uop_22_iw_issued_partial_agen}, {stq_uop_21_iw_issued_partial_agen}, {stq_uop_20_iw_issued_partial_agen}, {stq_uop_19_iw_issued_partial_agen}, {stq_uop_18_iw_issued_partial_agen}, {stq_uop_17_iw_issued_partial_agen}, {stq_uop_16_iw_issued_partial_agen}, {stq_uop_15_iw_issued_partial_agen}, {stq_uop_14_iw_issued_partial_agen}, {stq_uop_13_iw_issued_partial_agen}, {stq_uop_12_iw_issued_partial_agen}, {stq_uop_11_iw_issued_partial_agen}, {stq_uop_10_iw_issued_partial_agen}, {stq_uop_9_iw_issued_partial_agen}, {stq_uop_8_iw_issued_partial_agen}, {stq_uop_7_iw_issued_partial_agen}, {stq_uop_6_iw_issued_partial_agen}, {stq_uop_5_iw_issued_partial_agen}, {stq_uop_4_iw_issued_partial_agen}, {stq_uop_3_iw_issued_partial_agen}, {stq_uop_2_iw_issued_partial_agen}, {stq_uop_1_iw_issued_partial_agen}, {stq_uop_0_iw_issued_partial_agen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_271 = {{stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}, {stq_uop_23_iw_issued_partial_dgen}, {stq_uop_22_iw_issued_partial_dgen}, {stq_uop_21_iw_issued_partial_dgen}, {stq_uop_20_iw_issued_partial_dgen}, {stq_uop_19_iw_issued_partial_dgen}, {stq_uop_18_iw_issued_partial_dgen}, {stq_uop_17_iw_issued_partial_dgen}, {stq_uop_16_iw_issued_partial_dgen}, {stq_uop_15_iw_issued_partial_dgen}, {stq_uop_14_iw_issued_partial_dgen}, {stq_uop_13_iw_issued_partial_dgen}, {stq_uop_12_iw_issued_partial_dgen}, {stq_uop_11_iw_issued_partial_dgen}, {stq_uop_10_iw_issued_partial_dgen}, {stq_uop_9_iw_issued_partial_dgen}, {stq_uop_8_iw_issued_partial_dgen}, {stq_uop_7_iw_issued_partial_dgen}, {stq_uop_6_iw_issued_partial_dgen}, {stq_uop_5_iw_issued_partial_dgen}, {stq_uop_4_iw_issued_partial_dgen}, {stq_uop_3_iw_issued_partial_dgen}, {stq_uop_2_iw_issued_partial_dgen}, {stq_uop_1_iw_issued_partial_dgen}, {stq_uop_0_iw_issued_partial_dgen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_272 = {{stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}, {stq_uop_23_iw_p1_speculative_child}, {stq_uop_22_iw_p1_speculative_child}, {stq_uop_21_iw_p1_speculative_child}, {stq_uop_20_iw_p1_speculative_child}, {stq_uop_19_iw_p1_speculative_child}, {stq_uop_18_iw_p1_speculative_child}, {stq_uop_17_iw_p1_speculative_child}, {stq_uop_16_iw_p1_speculative_child}, {stq_uop_15_iw_p1_speculative_child}, {stq_uop_14_iw_p1_speculative_child}, {stq_uop_13_iw_p1_speculative_child}, {stq_uop_12_iw_p1_speculative_child}, {stq_uop_11_iw_p1_speculative_child}, {stq_uop_10_iw_p1_speculative_child}, {stq_uop_9_iw_p1_speculative_child}, {stq_uop_8_iw_p1_speculative_child}, {stq_uop_7_iw_p1_speculative_child}, {stq_uop_6_iw_p1_speculative_child}, {stq_uop_5_iw_p1_speculative_child}, {stq_uop_4_iw_p1_speculative_child}, {stq_uop_3_iw_p1_speculative_child}, {stq_uop_2_iw_p1_speculative_child}, {stq_uop_1_iw_p1_speculative_child}, {stq_uop_0_iw_p1_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_273 = {{stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}, {stq_uop_23_iw_p2_speculative_child}, {stq_uop_22_iw_p2_speculative_child}, {stq_uop_21_iw_p2_speculative_child}, {stq_uop_20_iw_p2_speculative_child}, {stq_uop_19_iw_p2_speculative_child}, {stq_uop_18_iw_p2_speculative_child}, {stq_uop_17_iw_p2_speculative_child}, {stq_uop_16_iw_p2_speculative_child}, {stq_uop_15_iw_p2_speculative_child}, {stq_uop_14_iw_p2_speculative_child}, {stq_uop_13_iw_p2_speculative_child}, {stq_uop_12_iw_p2_speculative_child}, {stq_uop_11_iw_p2_speculative_child}, {stq_uop_10_iw_p2_speculative_child}, {stq_uop_9_iw_p2_speculative_child}, {stq_uop_8_iw_p2_speculative_child}, {stq_uop_7_iw_p2_speculative_child}, {stq_uop_6_iw_p2_speculative_child}, {stq_uop_5_iw_p2_speculative_child}, {stq_uop_4_iw_p2_speculative_child}, {stq_uop_3_iw_p2_speculative_child}, {stq_uop_2_iw_p2_speculative_child}, {stq_uop_1_iw_p2_speculative_child}, {stq_uop_0_iw_p2_speculative_child}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_274 = {{stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}, {stq_uop_23_iw_p1_bypass_hint}, {stq_uop_22_iw_p1_bypass_hint}, {stq_uop_21_iw_p1_bypass_hint}, {stq_uop_20_iw_p1_bypass_hint}, {stq_uop_19_iw_p1_bypass_hint}, {stq_uop_18_iw_p1_bypass_hint}, {stq_uop_17_iw_p1_bypass_hint}, {stq_uop_16_iw_p1_bypass_hint}, {stq_uop_15_iw_p1_bypass_hint}, {stq_uop_14_iw_p1_bypass_hint}, {stq_uop_13_iw_p1_bypass_hint}, {stq_uop_12_iw_p1_bypass_hint}, {stq_uop_11_iw_p1_bypass_hint}, {stq_uop_10_iw_p1_bypass_hint}, {stq_uop_9_iw_p1_bypass_hint}, {stq_uop_8_iw_p1_bypass_hint}, {stq_uop_7_iw_p1_bypass_hint}, {stq_uop_6_iw_p1_bypass_hint}, {stq_uop_5_iw_p1_bypass_hint}, {stq_uop_4_iw_p1_bypass_hint}, {stq_uop_3_iw_p1_bypass_hint}, {stq_uop_2_iw_p1_bypass_hint}, {stq_uop_1_iw_p1_bypass_hint}, {stq_uop_0_iw_p1_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_275 = {{stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}, {stq_uop_23_iw_p2_bypass_hint}, {stq_uop_22_iw_p2_bypass_hint}, {stq_uop_21_iw_p2_bypass_hint}, {stq_uop_20_iw_p2_bypass_hint}, {stq_uop_19_iw_p2_bypass_hint}, {stq_uop_18_iw_p2_bypass_hint}, {stq_uop_17_iw_p2_bypass_hint}, {stq_uop_16_iw_p2_bypass_hint}, {stq_uop_15_iw_p2_bypass_hint}, {stq_uop_14_iw_p2_bypass_hint}, {stq_uop_13_iw_p2_bypass_hint}, {stq_uop_12_iw_p2_bypass_hint}, {stq_uop_11_iw_p2_bypass_hint}, {stq_uop_10_iw_p2_bypass_hint}, {stq_uop_9_iw_p2_bypass_hint}, {stq_uop_8_iw_p2_bypass_hint}, {stq_uop_7_iw_p2_bypass_hint}, {stq_uop_6_iw_p2_bypass_hint}, {stq_uop_5_iw_p2_bypass_hint}, {stq_uop_4_iw_p2_bypass_hint}, {stq_uop_3_iw_p2_bypass_hint}, {stq_uop_2_iw_p2_bypass_hint}, {stq_uop_1_iw_p2_bypass_hint}, {stq_uop_0_iw_p2_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_276 = {{stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}, {stq_uop_23_iw_p3_bypass_hint}, {stq_uop_22_iw_p3_bypass_hint}, {stq_uop_21_iw_p3_bypass_hint}, {stq_uop_20_iw_p3_bypass_hint}, {stq_uop_19_iw_p3_bypass_hint}, {stq_uop_18_iw_p3_bypass_hint}, {stq_uop_17_iw_p3_bypass_hint}, {stq_uop_16_iw_p3_bypass_hint}, {stq_uop_15_iw_p3_bypass_hint}, {stq_uop_14_iw_p3_bypass_hint}, {stq_uop_13_iw_p3_bypass_hint}, {stq_uop_12_iw_p3_bypass_hint}, {stq_uop_11_iw_p3_bypass_hint}, {stq_uop_10_iw_p3_bypass_hint}, {stq_uop_9_iw_p3_bypass_hint}, {stq_uop_8_iw_p3_bypass_hint}, {stq_uop_7_iw_p3_bypass_hint}, {stq_uop_6_iw_p3_bypass_hint}, {stq_uop_5_iw_p3_bypass_hint}, {stq_uop_4_iw_p3_bypass_hint}, {stq_uop_3_iw_p3_bypass_hint}, {stq_uop_2_iw_p3_bypass_hint}, {stq_uop_1_iw_p3_bypass_hint}, {stq_uop_0_iw_p3_bypass_hint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_277 = {{stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_0_dis_col_sel}, {stq_uop_23_dis_col_sel}, {stq_uop_22_dis_col_sel}, {stq_uop_21_dis_col_sel}, {stq_uop_20_dis_col_sel}, {stq_uop_19_dis_col_sel}, {stq_uop_18_dis_col_sel}, {stq_uop_17_dis_col_sel}, {stq_uop_16_dis_col_sel}, {stq_uop_15_dis_col_sel}, {stq_uop_14_dis_col_sel}, {stq_uop_13_dis_col_sel}, {stq_uop_12_dis_col_sel}, {stq_uop_11_dis_col_sel}, {stq_uop_10_dis_col_sel}, {stq_uop_9_dis_col_sel}, {stq_uop_8_dis_col_sel}, {stq_uop_7_dis_col_sel}, {stq_uop_6_dis_col_sel}, {stq_uop_5_dis_col_sel}, {stq_uop_4_dis_col_sel}, {stq_uop_3_dis_col_sel}, {stq_uop_2_dis_col_sel}, {stq_uop_1_dis_col_sel}, {stq_uop_0_dis_col_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dis_col_sel = _GEN_277[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][15:0] _GEN_278 = {{stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_0_br_mask}, {stq_uop_23_br_mask}, {stq_uop_22_br_mask}, {stq_uop_21_br_mask}, {stq_uop_20_br_mask}, {stq_uop_19_br_mask}, {stq_uop_18_br_mask}, {stq_uop_17_br_mask}, {stq_uop_16_br_mask}, {stq_uop_15_br_mask}, {stq_uop_14_br_mask}, {stq_uop_13_br_mask}, {stq_uop_12_br_mask}, {stq_uop_11_br_mask}, {stq_uop_10_br_mask}, {stq_uop_9_br_mask}, {stq_uop_8_br_mask}, {stq_uop_7_br_mask}, {stq_uop_6_br_mask}, {stq_uop_5_br_mask}, {stq_uop_4_br_mask}, {stq_uop_3_br_mask}, {stq_uop_2_br_mask}, {stq_uop_1_br_mask}, {stq_uop_0_br_mask}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_mask = _GEN_278[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][3:0] _GEN_279 = {{stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_0_br_tag}, {stq_uop_23_br_tag}, {stq_uop_22_br_tag}, {stq_uop_21_br_tag}, {stq_uop_20_br_tag}, {stq_uop_19_br_tag}, {stq_uop_18_br_tag}, {stq_uop_17_br_tag}, {stq_uop_16_br_tag}, {stq_uop_15_br_tag}, {stq_uop_14_br_tag}, {stq_uop_13_br_tag}, {stq_uop_12_br_tag}, {stq_uop_11_br_tag}, {stq_uop_10_br_tag}, {stq_uop_9_br_tag}, {stq_uop_8_br_tag}, {stq_uop_7_br_tag}, {stq_uop_6_br_tag}, {stq_uop_5_br_tag}, {stq_uop_4_br_tag}, {stq_uop_3_br_tag}, {stq_uop_2_br_tag}, {stq_uop_1_br_tag}, {stq_uop_0_br_tag}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_tag = _GEN_279[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][3:0] _GEN_280 = {{stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_0_br_type}, {stq_uop_23_br_type}, {stq_uop_22_br_type}, {stq_uop_21_br_type}, {stq_uop_20_br_type}, {stq_uop_19_br_type}, {stq_uop_18_br_type}, {stq_uop_17_br_type}, {stq_uop_16_br_type}, {stq_uop_15_br_type}, {stq_uop_14_br_type}, {stq_uop_13_br_type}, {stq_uop_12_br_type}, {stq_uop_11_br_type}, {stq_uop_10_br_type}, {stq_uop_9_br_type}, {stq_uop_8_br_type}, {stq_uop_7_br_type}, {stq_uop_6_br_type}, {stq_uop_5_br_type}, {stq_uop_4_br_type}, {stq_uop_3_br_type}, {stq_uop_2_br_type}, {stq_uop_1_br_type}, {stq_uop_0_br_type}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_br_type = _GEN_280[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_281 = {{stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_0_is_sfb}, {stq_uop_23_is_sfb}, {stq_uop_22_is_sfb}, {stq_uop_21_is_sfb}, {stq_uop_20_is_sfb}, {stq_uop_19_is_sfb}, {stq_uop_18_is_sfb}, {stq_uop_17_is_sfb}, {stq_uop_16_is_sfb}, {stq_uop_15_is_sfb}, {stq_uop_14_is_sfb}, {stq_uop_13_is_sfb}, {stq_uop_12_is_sfb}, {stq_uop_11_is_sfb}, {stq_uop_10_is_sfb}, {stq_uop_9_is_sfb}, {stq_uop_8_is_sfb}, {stq_uop_7_is_sfb}, {stq_uop_6_is_sfb}, {stq_uop_5_is_sfb}, {stq_uop_4_is_sfb}, {stq_uop_3_is_sfb}, {stq_uop_2_is_sfb}, {stq_uop_1_is_sfb}, {stq_uop_0_is_sfb}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfb = _GEN_281[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_282 = {{stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_0_is_fence}, {stq_uop_23_is_fence}, {stq_uop_22_is_fence}, {stq_uop_21_is_fence}, {stq_uop_20_is_fence}, {stq_uop_19_is_fence}, {stq_uop_18_is_fence}, {stq_uop_17_is_fence}, {stq_uop_16_is_fence}, {stq_uop_15_is_fence}, {stq_uop_14_is_fence}, {stq_uop_13_is_fence}, {stq_uop_12_is_fence}, {stq_uop_11_is_fence}, {stq_uop_10_is_fence}, {stq_uop_9_is_fence}, {stq_uop_8_is_fence}, {stq_uop_7_is_fence}, {stq_uop_6_is_fence}, {stq_uop_5_is_fence}, {stq_uop_4_is_fence}, {stq_uop_3_is_fence}, {stq_uop_2_is_fence}, {stq_uop_1_is_fence}, {stq_uop_0_is_fence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fence = _GEN_282[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_283 = {{stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_0_is_fencei}, {stq_uop_23_is_fencei}, {stq_uop_22_is_fencei}, {stq_uop_21_is_fencei}, {stq_uop_20_is_fencei}, {stq_uop_19_is_fencei}, {stq_uop_18_is_fencei}, {stq_uop_17_is_fencei}, {stq_uop_16_is_fencei}, {stq_uop_15_is_fencei}, {stq_uop_14_is_fencei}, {stq_uop_13_is_fencei}, {stq_uop_12_is_fencei}, {stq_uop_11_is_fencei}, {stq_uop_10_is_fencei}, {stq_uop_9_is_fencei}, {stq_uop_8_is_fencei}, {stq_uop_7_is_fencei}, {stq_uop_6_is_fencei}, {stq_uop_5_is_fencei}, {stq_uop_4_is_fencei}, {stq_uop_3_is_fencei}, {stq_uop_2_is_fencei}, {stq_uop_1_is_fencei}, {stq_uop_0_is_fencei}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_fencei = _GEN_283[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_284 = {{stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_0_is_sfence}, {stq_uop_23_is_sfence}, {stq_uop_22_is_sfence}, {stq_uop_21_is_sfence}, {stq_uop_20_is_sfence}, {stq_uop_19_is_sfence}, {stq_uop_18_is_sfence}, {stq_uop_17_is_sfence}, {stq_uop_16_is_sfence}, {stq_uop_15_is_sfence}, {stq_uop_14_is_sfence}, {stq_uop_13_is_sfence}, {stq_uop_12_is_sfence}, {stq_uop_11_is_sfence}, {stq_uop_10_is_sfence}, {stq_uop_9_is_sfence}, {stq_uop_8_is_sfence}, {stq_uop_7_is_sfence}, {stq_uop_6_is_sfence}, {stq_uop_5_is_sfence}, {stq_uop_4_is_sfence}, {stq_uop_3_is_sfence}, {stq_uop_2_is_sfence}, {stq_uop_1_is_sfence}, {stq_uop_0_is_sfence}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sfence = _GEN_284[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_285 = {{stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_0_is_amo}, {stq_uop_23_is_amo}, {stq_uop_22_is_amo}, {stq_uop_21_is_amo}, {stq_uop_20_is_amo}, {stq_uop_19_is_amo}, {stq_uop_18_is_amo}, {stq_uop_17_is_amo}, {stq_uop_16_is_amo}, {stq_uop_15_is_amo}, {stq_uop_14_is_amo}, {stq_uop_13_is_amo}, {stq_uop_12_is_amo}, {stq_uop_11_is_amo}, {stq_uop_10_is_amo}, {stq_uop_9_is_amo}, {stq_uop_8_is_amo}, {stq_uop_7_is_amo}, {stq_uop_6_is_amo}, {stq_uop_5_is_amo}, {stq_uop_4_is_amo}, {stq_uop_3_is_amo}, {stq_uop_2_is_amo}, {stq_uop_1_is_amo}, {stq_uop_0_is_amo}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_amo = _GEN_285[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_286 = {{stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_0_is_eret}, {stq_uop_23_is_eret}, {stq_uop_22_is_eret}, {stq_uop_21_is_eret}, {stq_uop_20_is_eret}, {stq_uop_19_is_eret}, {stq_uop_18_is_eret}, {stq_uop_17_is_eret}, {stq_uop_16_is_eret}, {stq_uop_15_is_eret}, {stq_uop_14_is_eret}, {stq_uop_13_is_eret}, {stq_uop_12_is_eret}, {stq_uop_11_is_eret}, {stq_uop_10_is_eret}, {stq_uop_9_is_eret}, {stq_uop_8_is_eret}, {stq_uop_7_is_eret}, {stq_uop_6_is_eret}, {stq_uop_5_is_eret}, {stq_uop_4_is_eret}, {stq_uop_3_is_eret}, {stq_uop_2_is_eret}, {stq_uop_1_is_eret}, {stq_uop_0_is_eret}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_eret = _GEN_286[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_287 = {{stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}, {stq_uop_23_is_sys_pc2epc}, {stq_uop_22_is_sys_pc2epc}, {stq_uop_21_is_sys_pc2epc}, {stq_uop_20_is_sys_pc2epc}, {stq_uop_19_is_sys_pc2epc}, {stq_uop_18_is_sys_pc2epc}, {stq_uop_17_is_sys_pc2epc}, {stq_uop_16_is_sys_pc2epc}, {stq_uop_15_is_sys_pc2epc}, {stq_uop_14_is_sys_pc2epc}, {stq_uop_13_is_sys_pc2epc}, {stq_uop_12_is_sys_pc2epc}, {stq_uop_11_is_sys_pc2epc}, {stq_uop_10_is_sys_pc2epc}, {stq_uop_9_is_sys_pc2epc}, {stq_uop_8_is_sys_pc2epc}, {stq_uop_7_is_sys_pc2epc}, {stq_uop_6_is_sys_pc2epc}, {stq_uop_5_is_sys_pc2epc}, {stq_uop_4_is_sys_pc2epc}, {stq_uop_3_is_sys_pc2epc}, {stq_uop_2_is_sys_pc2epc}, {stq_uop_1_is_sys_pc2epc}, {stq_uop_0_is_sys_pc2epc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_288 = {{stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_0_is_rocc}, {stq_uop_23_is_rocc}, {stq_uop_22_is_rocc}, {stq_uop_21_is_rocc}, {stq_uop_20_is_rocc}, {stq_uop_19_is_rocc}, {stq_uop_18_is_rocc}, {stq_uop_17_is_rocc}, {stq_uop_16_is_rocc}, {stq_uop_15_is_rocc}, {stq_uop_14_is_rocc}, {stq_uop_13_is_rocc}, {stq_uop_12_is_rocc}, {stq_uop_11_is_rocc}, {stq_uop_10_is_rocc}, {stq_uop_9_is_rocc}, {stq_uop_8_is_rocc}, {stq_uop_7_is_rocc}, {stq_uop_6_is_rocc}, {stq_uop_5_is_rocc}, {stq_uop_4_is_rocc}, {stq_uop_3_is_rocc}, {stq_uop_2_is_rocc}, {stq_uop_1_is_rocc}, {stq_uop_0_is_rocc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_rocc = _GEN_288[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_289 = {{stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_0_is_mov}, {stq_uop_23_is_mov}, {stq_uop_22_is_mov}, {stq_uop_21_is_mov}, {stq_uop_20_is_mov}, {stq_uop_19_is_mov}, {stq_uop_18_is_mov}, {stq_uop_17_is_mov}, {stq_uop_16_is_mov}, {stq_uop_15_is_mov}, {stq_uop_14_is_mov}, {stq_uop_13_is_mov}, {stq_uop_12_is_mov}, {stq_uop_11_is_mov}, {stq_uop_10_is_mov}, {stq_uop_9_is_mov}, {stq_uop_8_is_mov}, {stq_uop_7_is_mov}, {stq_uop_6_is_mov}, {stq_uop_5_is_mov}, {stq_uop_4_is_mov}, {stq_uop_3_is_mov}, {stq_uop_2_is_mov}, {stq_uop_1_is_mov}, {stq_uop_0_is_mov}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_mov = _GEN_289[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_290 = {{stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_0_ftq_idx}, {stq_uop_23_ftq_idx}, {stq_uop_22_ftq_idx}, {stq_uop_21_ftq_idx}, {stq_uop_20_ftq_idx}, {stq_uop_19_ftq_idx}, {stq_uop_18_ftq_idx}, {stq_uop_17_ftq_idx}, {stq_uop_16_ftq_idx}, {stq_uop_15_ftq_idx}, {stq_uop_14_ftq_idx}, {stq_uop_13_ftq_idx}, {stq_uop_12_ftq_idx}, {stq_uop_11_ftq_idx}, {stq_uop_10_ftq_idx}, {stq_uop_9_ftq_idx}, {stq_uop_8_ftq_idx}, {stq_uop_7_ftq_idx}, {stq_uop_6_ftq_idx}, {stq_uop_5_ftq_idx}, {stq_uop_4_ftq_idx}, {stq_uop_3_ftq_idx}, {stq_uop_2_ftq_idx}, {stq_uop_1_ftq_idx}, {stq_uop_0_ftq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ftq_idx = _GEN_290[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_291 = {{stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_0_edge_inst}, {stq_uop_23_edge_inst}, {stq_uop_22_edge_inst}, {stq_uop_21_edge_inst}, {stq_uop_20_edge_inst}, {stq_uop_19_edge_inst}, {stq_uop_18_edge_inst}, {stq_uop_17_edge_inst}, {stq_uop_16_edge_inst}, {stq_uop_15_edge_inst}, {stq_uop_14_edge_inst}, {stq_uop_13_edge_inst}, {stq_uop_12_edge_inst}, {stq_uop_11_edge_inst}, {stq_uop_10_edge_inst}, {stq_uop_9_edge_inst}, {stq_uop_8_edge_inst}, {stq_uop_7_edge_inst}, {stq_uop_6_edge_inst}, {stq_uop_5_edge_inst}, {stq_uop_4_edge_inst}, {stq_uop_3_edge_inst}, {stq_uop_2_edge_inst}, {stq_uop_1_edge_inst}, {stq_uop_0_edge_inst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_edge_inst = _GEN_291[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_292 = {{stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_0_pc_lob}, {stq_uop_23_pc_lob}, {stq_uop_22_pc_lob}, {stq_uop_21_pc_lob}, {stq_uop_20_pc_lob}, {stq_uop_19_pc_lob}, {stq_uop_18_pc_lob}, {stq_uop_17_pc_lob}, {stq_uop_16_pc_lob}, {stq_uop_15_pc_lob}, {stq_uop_14_pc_lob}, {stq_uop_13_pc_lob}, {stq_uop_12_pc_lob}, {stq_uop_11_pc_lob}, {stq_uop_10_pc_lob}, {stq_uop_9_pc_lob}, {stq_uop_8_pc_lob}, {stq_uop_7_pc_lob}, {stq_uop_6_pc_lob}, {stq_uop_5_pc_lob}, {stq_uop_4_pc_lob}, {stq_uop_3_pc_lob}, {stq_uop_2_pc_lob}, {stq_uop_1_pc_lob}, {stq_uop_0_pc_lob}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pc_lob = _GEN_292[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_293 = {{stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_0_taken}, {stq_uop_23_taken}, {stq_uop_22_taken}, {stq_uop_21_taken}, {stq_uop_20_taken}, {stq_uop_19_taken}, {stq_uop_18_taken}, {stq_uop_17_taken}, {stq_uop_16_taken}, {stq_uop_15_taken}, {stq_uop_14_taken}, {stq_uop_13_taken}, {stq_uop_12_taken}, {stq_uop_11_taken}, {stq_uop_10_taken}, {stq_uop_9_taken}, {stq_uop_8_taken}, {stq_uop_7_taken}, {stq_uop_6_taken}, {stq_uop_5_taken}, {stq_uop_4_taken}, {stq_uop_3_taken}, {stq_uop_2_taken}, {stq_uop_1_taken}, {stq_uop_0_taken}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_taken = _GEN_293[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_294 = {{stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_0_imm_rename}, {stq_uop_23_imm_rename}, {stq_uop_22_imm_rename}, {stq_uop_21_imm_rename}, {stq_uop_20_imm_rename}, {stq_uop_19_imm_rename}, {stq_uop_18_imm_rename}, {stq_uop_17_imm_rename}, {stq_uop_16_imm_rename}, {stq_uop_15_imm_rename}, {stq_uop_14_imm_rename}, {stq_uop_13_imm_rename}, {stq_uop_12_imm_rename}, {stq_uop_11_imm_rename}, {stq_uop_10_imm_rename}, {stq_uop_9_imm_rename}, {stq_uop_8_imm_rename}, {stq_uop_7_imm_rename}, {stq_uop_6_imm_rename}, {stq_uop_5_imm_rename}, {stq_uop_4_imm_rename}, {stq_uop_3_imm_rename}, {stq_uop_2_imm_rename}, {stq_uop_1_imm_rename}, {stq_uop_0_imm_rename}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_rename = _GEN_294[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_295 = {{stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_0_imm_sel}, {stq_uop_23_imm_sel}, {stq_uop_22_imm_sel}, {stq_uop_21_imm_sel}, {stq_uop_20_imm_sel}, {stq_uop_19_imm_sel}, {stq_uop_18_imm_sel}, {stq_uop_17_imm_sel}, {stq_uop_16_imm_sel}, {stq_uop_15_imm_sel}, {stq_uop_14_imm_sel}, {stq_uop_13_imm_sel}, {stq_uop_12_imm_sel}, {stq_uop_11_imm_sel}, {stq_uop_10_imm_sel}, {stq_uop_9_imm_sel}, {stq_uop_8_imm_sel}, {stq_uop_7_imm_sel}, {stq_uop_6_imm_sel}, {stq_uop_5_imm_sel}, {stq_uop_4_imm_sel}, {stq_uop_3_imm_sel}, {stq_uop_2_imm_sel}, {stq_uop_1_imm_sel}, {stq_uop_0_imm_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_sel = _GEN_295[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_296 = {{stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_0_pimm}, {stq_uop_23_pimm}, {stq_uop_22_pimm}, {stq_uop_21_pimm}, {stq_uop_20_pimm}, {stq_uop_19_pimm}, {stq_uop_18_pimm}, {stq_uop_17_pimm}, {stq_uop_16_pimm}, {stq_uop_15_pimm}, {stq_uop_14_pimm}, {stq_uop_13_pimm}, {stq_uop_12_pimm}, {stq_uop_11_pimm}, {stq_uop_10_pimm}, {stq_uop_9_pimm}, {stq_uop_8_pimm}, {stq_uop_7_pimm}, {stq_uop_6_pimm}, {stq_uop_5_pimm}, {stq_uop_4_pimm}, {stq_uop_3_pimm}, {stq_uop_2_pimm}, {stq_uop_1_pimm}, {stq_uop_0_pimm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pimm = _GEN_296[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][19:0] _GEN_297 = {{stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_0_imm_packed}, {stq_uop_23_imm_packed}, {stq_uop_22_imm_packed}, {stq_uop_21_imm_packed}, {stq_uop_20_imm_packed}, {stq_uop_19_imm_packed}, {stq_uop_18_imm_packed}, {stq_uop_17_imm_packed}, {stq_uop_16_imm_packed}, {stq_uop_15_imm_packed}, {stq_uop_14_imm_packed}, {stq_uop_13_imm_packed}, {stq_uop_12_imm_packed}, {stq_uop_11_imm_packed}, {stq_uop_10_imm_packed}, {stq_uop_9_imm_packed}, {stq_uop_8_imm_packed}, {stq_uop_7_imm_packed}, {stq_uop_6_imm_packed}, {stq_uop_5_imm_packed}, {stq_uop_4_imm_packed}, {stq_uop_3_imm_packed}, {stq_uop_2_imm_packed}, {stq_uop_1_imm_packed}, {stq_uop_0_imm_packed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_imm_packed = _GEN_297[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_298 = {{stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_0_op1_sel}, {stq_uop_23_op1_sel}, {stq_uop_22_op1_sel}, {stq_uop_21_op1_sel}, {stq_uop_20_op1_sel}, {stq_uop_19_op1_sel}, {stq_uop_18_op1_sel}, {stq_uop_17_op1_sel}, {stq_uop_16_op1_sel}, {stq_uop_15_op1_sel}, {stq_uop_14_op1_sel}, {stq_uop_13_op1_sel}, {stq_uop_12_op1_sel}, {stq_uop_11_op1_sel}, {stq_uop_10_op1_sel}, {stq_uop_9_op1_sel}, {stq_uop_8_op1_sel}, {stq_uop_7_op1_sel}, {stq_uop_6_op1_sel}, {stq_uop_5_op1_sel}, {stq_uop_4_op1_sel}, {stq_uop_3_op1_sel}, {stq_uop_2_op1_sel}, {stq_uop_1_op1_sel}, {stq_uop_0_op1_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op1_sel = _GEN_298[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_299 = {{stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_0_op2_sel}, {stq_uop_23_op2_sel}, {stq_uop_22_op2_sel}, {stq_uop_21_op2_sel}, {stq_uop_20_op2_sel}, {stq_uop_19_op2_sel}, {stq_uop_18_op2_sel}, {stq_uop_17_op2_sel}, {stq_uop_16_op2_sel}, {stq_uop_15_op2_sel}, {stq_uop_14_op2_sel}, {stq_uop_13_op2_sel}, {stq_uop_12_op2_sel}, {stq_uop_11_op2_sel}, {stq_uop_10_op2_sel}, {stq_uop_9_op2_sel}, {stq_uop_8_op2_sel}, {stq_uop_7_op2_sel}, {stq_uop_6_op2_sel}, {stq_uop_5_op2_sel}, {stq_uop_4_op2_sel}, {stq_uop_3_op2_sel}, {stq_uop_2_op2_sel}, {stq_uop_1_op2_sel}, {stq_uop_0_op2_sel}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_op2_sel = _GEN_299[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_300 = {{stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}, {stq_uop_23_fp_ctrl_ldst}, {stq_uop_22_fp_ctrl_ldst}, {stq_uop_21_fp_ctrl_ldst}, {stq_uop_20_fp_ctrl_ldst}, {stq_uop_19_fp_ctrl_ldst}, {stq_uop_18_fp_ctrl_ldst}, {stq_uop_17_fp_ctrl_ldst}, {stq_uop_16_fp_ctrl_ldst}, {stq_uop_15_fp_ctrl_ldst}, {stq_uop_14_fp_ctrl_ldst}, {stq_uop_13_fp_ctrl_ldst}, {stq_uop_12_fp_ctrl_ldst}, {stq_uop_11_fp_ctrl_ldst}, {stq_uop_10_fp_ctrl_ldst}, {stq_uop_9_fp_ctrl_ldst}, {stq_uop_8_fp_ctrl_ldst}, {stq_uop_7_fp_ctrl_ldst}, {stq_uop_6_fp_ctrl_ldst}, {stq_uop_5_fp_ctrl_ldst}, {stq_uop_4_fp_ctrl_ldst}, {stq_uop_3_fp_ctrl_ldst}, {stq_uop_2_fp_ctrl_ldst}, {stq_uop_1_fp_ctrl_ldst}, {stq_uop_0_fp_ctrl_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_301 = {{stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}, {stq_uop_23_fp_ctrl_wen}, {stq_uop_22_fp_ctrl_wen}, {stq_uop_21_fp_ctrl_wen}, {stq_uop_20_fp_ctrl_wen}, {stq_uop_19_fp_ctrl_wen}, {stq_uop_18_fp_ctrl_wen}, {stq_uop_17_fp_ctrl_wen}, {stq_uop_16_fp_ctrl_wen}, {stq_uop_15_fp_ctrl_wen}, {stq_uop_14_fp_ctrl_wen}, {stq_uop_13_fp_ctrl_wen}, {stq_uop_12_fp_ctrl_wen}, {stq_uop_11_fp_ctrl_wen}, {stq_uop_10_fp_ctrl_wen}, {stq_uop_9_fp_ctrl_wen}, {stq_uop_8_fp_ctrl_wen}, {stq_uop_7_fp_ctrl_wen}, {stq_uop_6_fp_ctrl_wen}, {stq_uop_5_fp_ctrl_wen}, {stq_uop_4_fp_ctrl_wen}, {stq_uop_3_fp_ctrl_wen}, {stq_uop_2_fp_ctrl_wen}, {stq_uop_1_fp_ctrl_wen}, {stq_uop_0_fp_ctrl_wen}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_302 = {{stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}, {stq_uop_23_fp_ctrl_ren1}, {stq_uop_22_fp_ctrl_ren1}, {stq_uop_21_fp_ctrl_ren1}, {stq_uop_20_fp_ctrl_ren1}, {stq_uop_19_fp_ctrl_ren1}, {stq_uop_18_fp_ctrl_ren1}, {stq_uop_17_fp_ctrl_ren1}, {stq_uop_16_fp_ctrl_ren1}, {stq_uop_15_fp_ctrl_ren1}, {stq_uop_14_fp_ctrl_ren1}, {stq_uop_13_fp_ctrl_ren1}, {stq_uop_12_fp_ctrl_ren1}, {stq_uop_11_fp_ctrl_ren1}, {stq_uop_10_fp_ctrl_ren1}, {stq_uop_9_fp_ctrl_ren1}, {stq_uop_8_fp_ctrl_ren1}, {stq_uop_7_fp_ctrl_ren1}, {stq_uop_6_fp_ctrl_ren1}, {stq_uop_5_fp_ctrl_ren1}, {stq_uop_4_fp_ctrl_ren1}, {stq_uop_3_fp_ctrl_ren1}, {stq_uop_2_fp_ctrl_ren1}, {stq_uop_1_fp_ctrl_ren1}, {stq_uop_0_fp_ctrl_ren1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_303 = {{stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}, {stq_uop_23_fp_ctrl_ren2}, {stq_uop_22_fp_ctrl_ren2}, {stq_uop_21_fp_ctrl_ren2}, {stq_uop_20_fp_ctrl_ren2}, {stq_uop_19_fp_ctrl_ren2}, {stq_uop_18_fp_ctrl_ren2}, {stq_uop_17_fp_ctrl_ren2}, {stq_uop_16_fp_ctrl_ren2}, {stq_uop_15_fp_ctrl_ren2}, {stq_uop_14_fp_ctrl_ren2}, {stq_uop_13_fp_ctrl_ren2}, {stq_uop_12_fp_ctrl_ren2}, {stq_uop_11_fp_ctrl_ren2}, {stq_uop_10_fp_ctrl_ren2}, {stq_uop_9_fp_ctrl_ren2}, {stq_uop_8_fp_ctrl_ren2}, {stq_uop_7_fp_ctrl_ren2}, {stq_uop_6_fp_ctrl_ren2}, {stq_uop_5_fp_ctrl_ren2}, {stq_uop_4_fp_ctrl_ren2}, {stq_uop_3_fp_ctrl_ren2}, {stq_uop_2_fp_ctrl_ren2}, {stq_uop_1_fp_ctrl_ren2}, {stq_uop_0_fp_ctrl_ren2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_304 = {{stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}, {stq_uop_23_fp_ctrl_ren3}, {stq_uop_22_fp_ctrl_ren3}, {stq_uop_21_fp_ctrl_ren3}, {stq_uop_20_fp_ctrl_ren3}, {stq_uop_19_fp_ctrl_ren3}, {stq_uop_18_fp_ctrl_ren3}, {stq_uop_17_fp_ctrl_ren3}, {stq_uop_16_fp_ctrl_ren3}, {stq_uop_15_fp_ctrl_ren3}, {stq_uop_14_fp_ctrl_ren3}, {stq_uop_13_fp_ctrl_ren3}, {stq_uop_12_fp_ctrl_ren3}, {stq_uop_11_fp_ctrl_ren3}, {stq_uop_10_fp_ctrl_ren3}, {stq_uop_9_fp_ctrl_ren3}, {stq_uop_8_fp_ctrl_ren3}, {stq_uop_7_fp_ctrl_ren3}, {stq_uop_6_fp_ctrl_ren3}, {stq_uop_5_fp_ctrl_ren3}, {stq_uop_4_fp_ctrl_ren3}, {stq_uop_3_fp_ctrl_ren3}, {stq_uop_2_fp_ctrl_ren3}, {stq_uop_1_fp_ctrl_ren3}, {stq_uop_0_fp_ctrl_ren3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_305 = {{stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}, {stq_uop_23_fp_ctrl_swap12}, {stq_uop_22_fp_ctrl_swap12}, {stq_uop_21_fp_ctrl_swap12}, {stq_uop_20_fp_ctrl_swap12}, {stq_uop_19_fp_ctrl_swap12}, {stq_uop_18_fp_ctrl_swap12}, {stq_uop_17_fp_ctrl_swap12}, {stq_uop_16_fp_ctrl_swap12}, {stq_uop_15_fp_ctrl_swap12}, {stq_uop_14_fp_ctrl_swap12}, {stq_uop_13_fp_ctrl_swap12}, {stq_uop_12_fp_ctrl_swap12}, {stq_uop_11_fp_ctrl_swap12}, {stq_uop_10_fp_ctrl_swap12}, {stq_uop_9_fp_ctrl_swap12}, {stq_uop_8_fp_ctrl_swap12}, {stq_uop_7_fp_ctrl_swap12}, {stq_uop_6_fp_ctrl_swap12}, {stq_uop_5_fp_ctrl_swap12}, {stq_uop_4_fp_ctrl_swap12}, {stq_uop_3_fp_ctrl_swap12}, {stq_uop_2_fp_ctrl_swap12}, {stq_uop_1_fp_ctrl_swap12}, {stq_uop_0_fp_ctrl_swap12}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_306 = {{stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}, {stq_uop_23_fp_ctrl_swap23}, {stq_uop_22_fp_ctrl_swap23}, {stq_uop_21_fp_ctrl_swap23}, {stq_uop_20_fp_ctrl_swap23}, {stq_uop_19_fp_ctrl_swap23}, {stq_uop_18_fp_ctrl_swap23}, {stq_uop_17_fp_ctrl_swap23}, {stq_uop_16_fp_ctrl_swap23}, {stq_uop_15_fp_ctrl_swap23}, {stq_uop_14_fp_ctrl_swap23}, {stq_uop_13_fp_ctrl_swap23}, {stq_uop_12_fp_ctrl_swap23}, {stq_uop_11_fp_ctrl_swap23}, {stq_uop_10_fp_ctrl_swap23}, {stq_uop_9_fp_ctrl_swap23}, {stq_uop_8_fp_ctrl_swap23}, {stq_uop_7_fp_ctrl_swap23}, {stq_uop_6_fp_ctrl_swap23}, {stq_uop_5_fp_ctrl_swap23}, {stq_uop_4_fp_ctrl_swap23}, {stq_uop_3_fp_ctrl_swap23}, {stq_uop_2_fp_ctrl_swap23}, {stq_uop_1_fp_ctrl_swap23}, {stq_uop_0_fp_ctrl_swap23}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_307 = {{stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}, {stq_uop_23_fp_ctrl_typeTagIn}, {stq_uop_22_fp_ctrl_typeTagIn}, {stq_uop_21_fp_ctrl_typeTagIn}, {stq_uop_20_fp_ctrl_typeTagIn}, {stq_uop_19_fp_ctrl_typeTagIn}, {stq_uop_18_fp_ctrl_typeTagIn}, {stq_uop_17_fp_ctrl_typeTagIn}, {stq_uop_16_fp_ctrl_typeTagIn}, {stq_uop_15_fp_ctrl_typeTagIn}, {stq_uop_14_fp_ctrl_typeTagIn}, {stq_uop_13_fp_ctrl_typeTagIn}, {stq_uop_12_fp_ctrl_typeTagIn}, {stq_uop_11_fp_ctrl_typeTagIn}, {stq_uop_10_fp_ctrl_typeTagIn}, {stq_uop_9_fp_ctrl_typeTagIn}, {stq_uop_8_fp_ctrl_typeTagIn}, {stq_uop_7_fp_ctrl_typeTagIn}, {stq_uop_6_fp_ctrl_typeTagIn}, {stq_uop_5_fp_ctrl_typeTagIn}, {stq_uop_4_fp_ctrl_typeTagIn}, {stq_uop_3_fp_ctrl_typeTagIn}, {stq_uop_2_fp_ctrl_typeTagIn}, {stq_uop_1_fp_ctrl_typeTagIn}, {stq_uop_0_fp_ctrl_typeTagIn}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_308 = {{stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}, {stq_uop_23_fp_ctrl_typeTagOut}, {stq_uop_22_fp_ctrl_typeTagOut}, {stq_uop_21_fp_ctrl_typeTagOut}, {stq_uop_20_fp_ctrl_typeTagOut}, {stq_uop_19_fp_ctrl_typeTagOut}, {stq_uop_18_fp_ctrl_typeTagOut}, {stq_uop_17_fp_ctrl_typeTagOut}, {stq_uop_16_fp_ctrl_typeTagOut}, {stq_uop_15_fp_ctrl_typeTagOut}, {stq_uop_14_fp_ctrl_typeTagOut}, {stq_uop_13_fp_ctrl_typeTagOut}, {stq_uop_12_fp_ctrl_typeTagOut}, {stq_uop_11_fp_ctrl_typeTagOut}, {stq_uop_10_fp_ctrl_typeTagOut}, {stq_uop_9_fp_ctrl_typeTagOut}, {stq_uop_8_fp_ctrl_typeTagOut}, {stq_uop_7_fp_ctrl_typeTagOut}, {stq_uop_6_fp_ctrl_typeTagOut}, {stq_uop_5_fp_ctrl_typeTagOut}, {stq_uop_4_fp_ctrl_typeTagOut}, {stq_uop_3_fp_ctrl_typeTagOut}, {stq_uop_2_fp_ctrl_typeTagOut}, {stq_uop_1_fp_ctrl_typeTagOut}, {stq_uop_0_fp_ctrl_typeTagOut}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_309 = {{stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}, {stq_uop_23_fp_ctrl_fromint}, {stq_uop_22_fp_ctrl_fromint}, {stq_uop_21_fp_ctrl_fromint}, {stq_uop_20_fp_ctrl_fromint}, {stq_uop_19_fp_ctrl_fromint}, {stq_uop_18_fp_ctrl_fromint}, {stq_uop_17_fp_ctrl_fromint}, {stq_uop_16_fp_ctrl_fromint}, {stq_uop_15_fp_ctrl_fromint}, {stq_uop_14_fp_ctrl_fromint}, {stq_uop_13_fp_ctrl_fromint}, {stq_uop_12_fp_ctrl_fromint}, {stq_uop_11_fp_ctrl_fromint}, {stq_uop_10_fp_ctrl_fromint}, {stq_uop_9_fp_ctrl_fromint}, {stq_uop_8_fp_ctrl_fromint}, {stq_uop_7_fp_ctrl_fromint}, {stq_uop_6_fp_ctrl_fromint}, {stq_uop_5_fp_ctrl_fromint}, {stq_uop_4_fp_ctrl_fromint}, {stq_uop_3_fp_ctrl_fromint}, {stq_uop_2_fp_ctrl_fromint}, {stq_uop_1_fp_ctrl_fromint}, {stq_uop_0_fp_ctrl_fromint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_310 = {{stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}, {stq_uop_23_fp_ctrl_toint}, {stq_uop_22_fp_ctrl_toint}, {stq_uop_21_fp_ctrl_toint}, {stq_uop_20_fp_ctrl_toint}, {stq_uop_19_fp_ctrl_toint}, {stq_uop_18_fp_ctrl_toint}, {stq_uop_17_fp_ctrl_toint}, {stq_uop_16_fp_ctrl_toint}, {stq_uop_15_fp_ctrl_toint}, {stq_uop_14_fp_ctrl_toint}, {stq_uop_13_fp_ctrl_toint}, {stq_uop_12_fp_ctrl_toint}, {stq_uop_11_fp_ctrl_toint}, {stq_uop_10_fp_ctrl_toint}, {stq_uop_9_fp_ctrl_toint}, {stq_uop_8_fp_ctrl_toint}, {stq_uop_7_fp_ctrl_toint}, {stq_uop_6_fp_ctrl_toint}, {stq_uop_5_fp_ctrl_toint}, {stq_uop_4_fp_ctrl_toint}, {stq_uop_3_fp_ctrl_toint}, {stq_uop_2_fp_ctrl_toint}, {stq_uop_1_fp_ctrl_toint}, {stq_uop_0_fp_ctrl_toint}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_311 = {{stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}, {stq_uop_23_fp_ctrl_fastpipe}, {stq_uop_22_fp_ctrl_fastpipe}, {stq_uop_21_fp_ctrl_fastpipe}, {stq_uop_20_fp_ctrl_fastpipe}, {stq_uop_19_fp_ctrl_fastpipe}, {stq_uop_18_fp_ctrl_fastpipe}, {stq_uop_17_fp_ctrl_fastpipe}, {stq_uop_16_fp_ctrl_fastpipe}, {stq_uop_15_fp_ctrl_fastpipe}, {stq_uop_14_fp_ctrl_fastpipe}, {stq_uop_13_fp_ctrl_fastpipe}, {stq_uop_12_fp_ctrl_fastpipe}, {stq_uop_11_fp_ctrl_fastpipe}, {stq_uop_10_fp_ctrl_fastpipe}, {stq_uop_9_fp_ctrl_fastpipe}, {stq_uop_8_fp_ctrl_fastpipe}, {stq_uop_7_fp_ctrl_fastpipe}, {stq_uop_6_fp_ctrl_fastpipe}, {stq_uop_5_fp_ctrl_fastpipe}, {stq_uop_4_fp_ctrl_fastpipe}, {stq_uop_3_fp_ctrl_fastpipe}, {stq_uop_2_fp_ctrl_fastpipe}, {stq_uop_1_fp_ctrl_fastpipe}, {stq_uop_0_fp_ctrl_fastpipe}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_312 = {{stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}, {stq_uop_23_fp_ctrl_fma}, {stq_uop_22_fp_ctrl_fma}, {stq_uop_21_fp_ctrl_fma}, {stq_uop_20_fp_ctrl_fma}, {stq_uop_19_fp_ctrl_fma}, {stq_uop_18_fp_ctrl_fma}, {stq_uop_17_fp_ctrl_fma}, {stq_uop_16_fp_ctrl_fma}, {stq_uop_15_fp_ctrl_fma}, {stq_uop_14_fp_ctrl_fma}, {stq_uop_13_fp_ctrl_fma}, {stq_uop_12_fp_ctrl_fma}, {stq_uop_11_fp_ctrl_fma}, {stq_uop_10_fp_ctrl_fma}, {stq_uop_9_fp_ctrl_fma}, {stq_uop_8_fp_ctrl_fma}, {stq_uop_7_fp_ctrl_fma}, {stq_uop_6_fp_ctrl_fma}, {stq_uop_5_fp_ctrl_fma}, {stq_uop_4_fp_ctrl_fma}, {stq_uop_3_fp_ctrl_fma}, {stq_uop_2_fp_ctrl_fma}, {stq_uop_1_fp_ctrl_fma}, {stq_uop_0_fp_ctrl_fma}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_313 = {{stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}, {stq_uop_23_fp_ctrl_div}, {stq_uop_22_fp_ctrl_div}, {stq_uop_21_fp_ctrl_div}, {stq_uop_20_fp_ctrl_div}, {stq_uop_19_fp_ctrl_div}, {stq_uop_18_fp_ctrl_div}, {stq_uop_17_fp_ctrl_div}, {stq_uop_16_fp_ctrl_div}, {stq_uop_15_fp_ctrl_div}, {stq_uop_14_fp_ctrl_div}, {stq_uop_13_fp_ctrl_div}, {stq_uop_12_fp_ctrl_div}, {stq_uop_11_fp_ctrl_div}, {stq_uop_10_fp_ctrl_div}, {stq_uop_9_fp_ctrl_div}, {stq_uop_8_fp_ctrl_div}, {stq_uop_7_fp_ctrl_div}, {stq_uop_6_fp_ctrl_div}, {stq_uop_5_fp_ctrl_div}, {stq_uop_4_fp_ctrl_div}, {stq_uop_3_fp_ctrl_div}, {stq_uop_2_fp_ctrl_div}, {stq_uop_1_fp_ctrl_div}, {stq_uop_0_fp_ctrl_div}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_314 = {{stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}, {stq_uop_23_fp_ctrl_sqrt}, {stq_uop_22_fp_ctrl_sqrt}, {stq_uop_21_fp_ctrl_sqrt}, {stq_uop_20_fp_ctrl_sqrt}, {stq_uop_19_fp_ctrl_sqrt}, {stq_uop_18_fp_ctrl_sqrt}, {stq_uop_17_fp_ctrl_sqrt}, {stq_uop_16_fp_ctrl_sqrt}, {stq_uop_15_fp_ctrl_sqrt}, {stq_uop_14_fp_ctrl_sqrt}, {stq_uop_13_fp_ctrl_sqrt}, {stq_uop_12_fp_ctrl_sqrt}, {stq_uop_11_fp_ctrl_sqrt}, {stq_uop_10_fp_ctrl_sqrt}, {stq_uop_9_fp_ctrl_sqrt}, {stq_uop_8_fp_ctrl_sqrt}, {stq_uop_7_fp_ctrl_sqrt}, {stq_uop_6_fp_ctrl_sqrt}, {stq_uop_5_fp_ctrl_sqrt}, {stq_uop_4_fp_ctrl_sqrt}, {stq_uop_3_fp_ctrl_sqrt}, {stq_uop_2_fp_ctrl_sqrt}, {stq_uop_1_fp_ctrl_sqrt}, {stq_uop_0_fp_ctrl_sqrt}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_315 = {{stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}, {stq_uop_23_fp_ctrl_wflags}, {stq_uop_22_fp_ctrl_wflags}, {stq_uop_21_fp_ctrl_wflags}, {stq_uop_20_fp_ctrl_wflags}, {stq_uop_19_fp_ctrl_wflags}, {stq_uop_18_fp_ctrl_wflags}, {stq_uop_17_fp_ctrl_wflags}, {stq_uop_16_fp_ctrl_wflags}, {stq_uop_15_fp_ctrl_wflags}, {stq_uop_14_fp_ctrl_wflags}, {stq_uop_13_fp_ctrl_wflags}, {stq_uop_12_fp_ctrl_wflags}, {stq_uop_11_fp_ctrl_wflags}, {stq_uop_10_fp_ctrl_wflags}, {stq_uop_9_fp_ctrl_wflags}, {stq_uop_8_fp_ctrl_wflags}, {stq_uop_7_fp_ctrl_wflags}, {stq_uop_6_fp_ctrl_wflags}, {stq_uop_5_fp_ctrl_wflags}, {stq_uop_4_fp_ctrl_wflags}, {stq_uop_3_fp_ctrl_wflags}, {stq_uop_2_fp_ctrl_wflags}, {stq_uop_1_fp_ctrl_wflags}, {stq_uop_0_fp_ctrl_wflags}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_316 = {{stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}, {stq_uop_23_fp_ctrl_vec}, {stq_uop_22_fp_ctrl_vec}, {stq_uop_21_fp_ctrl_vec}, {stq_uop_20_fp_ctrl_vec}, {stq_uop_19_fp_ctrl_vec}, {stq_uop_18_fp_ctrl_vec}, {stq_uop_17_fp_ctrl_vec}, {stq_uop_16_fp_ctrl_vec}, {stq_uop_15_fp_ctrl_vec}, {stq_uop_14_fp_ctrl_vec}, {stq_uop_13_fp_ctrl_vec}, {stq_uop_12_fp_ctrl_vec}, {stq_uop_11_fp_ctrl_vec}, {stq_uop_10_fp_ctrl_vec}, {stq_uop_9_fp_ctrl_vec}, {stq_uop_8_fp_ctrl_vec}, {stq_uop_7_fp_ctrl_vec}, {stq_uop_6_fp_ctrl_vec}, {stq_uop_5_fp_ctrl_vec}, {stq_uop_4_fp_ctrl_vec}, {stq_uop_3_fp_ctrl_vec}, {stq_uop_2_fp_ctrl_vec}, {stq_uop_1_fp_ctrl_vec}, {stq_uop_0_fp_ctrl_vec}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_317 = {{stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_0_rob_idx}, {stq_uop_23_rob_idx}, {stq_uop_22_rob_idx}, {stq_uop_21_rob_idx}, {stq_uop_20_rob_idx}, {stq_uop_19_rob_idx}, {stq_uop_18_rob_idx}, {stq_uop_17_rob_idx}, {stq_uop_16_rob_idx}, {stq_uop_15_rob_idx}, {stq_uop_14_rob_idx}, {stq_uop_13_rob_idx}, {stq_uop_12_rob_idx}, {stq_uop_11_rob_idx}, {stq_uop_10_rob_idx}, {stq_uop_9_rob_idx}, {stq_uop_8_rob_idx}, {stq_uop_7_rob_idx}, {stq_uop_6_rob_idx}, {stq_uop_5_rob_idx}, {stq_uop_4_rob_idx}, {stq_uop_3_rob_idx}, {stq_uop_2_rob_idx}, {stq_uop_1_rob_idx}, {stq_uop_0_rob_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rob_idx = _GEN_317[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_318 = {{stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_0_ldq_idx}, {stq_uop_23_ldq_idx}, {stq_uop_22_ldq_idx}, {stq_uop_21_ldq_idx}, {stq_uop_20_ldq_idx}, {stq_uop_19_ldq_idx}, {stq_uop_18_ldq_idx}, {stq_uop_17_ldq_idx}, {stq_uop_16_ldq_idx}, {stq_uop_15_ldq_idx}, {stq_uop_14_ldq_idx}, {stq_uop_13_ldq_idx}, {stq_uop_12_ldq_idx}, {stq_uop_11_ldq_idx}, {stq_uop_10_ldq_idx}, {stq_uop_9_ldq_idx}, {stq_uop_8_ldq_idx}, {stq_uop_7_ldq_idx}, {stq_uop_6_ldq_idx}, {stq_uop_5_ldq_idx}, {stq_uop_4_ldq_idx}, {stq_uop_3_ldq_idx}, {stq_uop_2_ldq_idx}, {stq_uop_1_ldq_idx}, {stq_uop_0_ldq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldq_idx = _GEN_318[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_319 = {{stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_0_stq_idx}, {stq_uop_23_stq_idx}, {stq_uop_22_stq_idx}, {stq_uop_21_stq_idx}, {stq_uop_20_stq_idx}, {stq_uop_19_stq_idx}, {stq_uop_18_stq_idx}, {stq_uop_17_stq_idx}, {stq_uop_16_stq_idx}, {stq_uop_15_stq_idx}, {stq_uop_14_stq_idx}, {stq_uop_13_stq_idx}, {stq_uop_12_stq_idx}, {stq_uop_11_stq_idx}, {stq_uop_10_stq_idx}, {stq_uop_9_stq_idx}, {stq_uop_8_stq_idx}, {stq_uop_7_stq_idx}, {stq_uop_6_stq_idx}, {stq_uop_5_stq_idx}, {stq_uop_4_stq_idx}, {stq_uop_3_stq_idx}, {stq_uop_2_stq_idx}, {stq_uop_1_stq_idx}, {stq_uop_0_stq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stq_idx = _GEN_319[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_320 = {{stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_0_rxq_idx}, {stq_uop_23_rxq_idx}, {stq_uop_22_rxq_idx}, {stq_uop_21_rxq_idx}, {stq_uop_20_rxq_idx}, {stq_uop_19_rxq_idx}, {stq_uop_18_rxq_idx}, {stq_uop_17_rxq_idx}, {stq_uop_16_rxq_idx}, {stq_uop_15_rxq_idx}, {stq_uop_14_rxq_idx}, {stq_uop_13_rxq_idx}, {stq_uop_12_rxq_idx}, {stq_uop_11_rxq_idx}, {stq_uop_10_rxq_idx}, {stq_uop_9_rxq_idx}, {stq_uop_8_rxq_idx}, {stq_uop_7_rxq_idx}, {stq_uop_6_rxq_idx}, {stq_uop_5_rxq_idx}, {stq_uop_4_rxq_idx}, {stq_uop_3_rxq_idx}, {stq_uop_2_rxq_idx}, {stq_uop_1_rxq_idx}, {stq_uop_0_rxq_idx}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_rxq_idx = _GEN_320[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_321 = {{stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_0_pdst}, {stq_uop_23_pdst}, {stq_uop_22_pdst}, {stq_uop_21_pdst}, {stq_uop_20_pdst}, {stq_uop_19_pdst}, {stq_uop_18_pdst}, {stq_uop_17_pdst}, {stq_uop_16_pdst}, {stq_uop_15_pdst}, {stq_uop_14_pdst}, {stq_uop_13_pdst}, {stq_uop_12_pdst}, {stq_uop_11_pdst}, {stq_uop_10_pdst}, {stq_uop_9_pdst}, {stq_uop_8_pdst}, {stq_uop_7_pdst}, {stq_uop_6_pdst}, {stq_uop_5_pdst}, {stq_uop_4_pdst}, {stq_uop_3_pdst}, {stq_uop_2_pdst}, {stq_uop_1_pdst}, {stq_uop_0_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_pdst = _GEN_321[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_322 = {{stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_0_prs1}, {stq_uop_23_prs1}, {stq_uop_22_prs1}, {stq_uop_21_prs1}, {stq_uop_20_prs1}, {stq_uop_19_prs1}, {stq_uop_18_prs1}, {stq_uop_17_prs1}, {stq_uop_16_prs1}, {stq_uop_15_prs1}, {stq_uop_14_prs1}, {stq_uop_13_prs1}, {stq_uop_12_prs1}, {stq_uop_11_prs1}, {stq_uop_10_prs1}, {stq_uop_9_prs1}, {stq_uop_8_prs1}, {stq_uop_7_prs1}, {stq_uop_6_prs1}, {stq_uop_5_prs1}, {stq_uop_4_prs1}, {stq_uop_3_prs1}, {stq_uop_2_prs1}, {stq_uop_1_prs1}, {stq_uop_0_prs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1 = _GEN_322[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_323 = {{stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_0_prs2}, {stq_uop_23_prs2}, {stq_uop_22_prs2}, {stq_uop_21_prs2}, {stq_uop_20_prs2}, {stq_uop_19_prs2}, {stq_uop_18_prs2}, {stq_uop_17_prs2}, {stq_uop_16_prs2}, {stq_uop_15_prs2}, {stq_uop_14_prs2}, {stq_uop_13_prs2}, {stq_uop_12_prs2}, {stq_uop_11_prs2}, {stq_uop_10_prs2}, {stq_uop_9_prs2}, {stq_uop_8_prs2}, {stq_uop_7_prs2}, {stq_uop_6_prs2}, {stq_uop_5_prs2}, {stq_uop_4_prs2}, {stq_uop_3_prs2}, {stq_uop_2_prs2}, {stq_uop_1_prs2}, {stq_uop_0_prs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2 = _GEN_323[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_324 = {{stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_0_prs3}, {stq_uop_23_prs3}, {stq_uop_22_prs3}, {stq_uop_21_prs3}, {stq_uop_20_prs3}, {stq_uop_19_prs3}, {stq_uop_18_prs3}, {stq_uop_17_prs3}, {stq_uop_16_prs3}, {stq_uop_15_prs3}, {stq_uop_14_prs3}, {stq_uop_13_prs3}, {stq_uop_12_prs3}, {stq_uop_11_prs3}, {stq_uop_10_prs3}, {stq_uop_9_prs3}, {stq_uop_8_prs3}, {stq_uop_7_prs3}, {stq_uop_6_prs3}, {stq_uop_5_prs3}, {stq_uop_4_prs3}, {stq_uop_3_prs3}, {stq_uop_2_prs3}, {stq_uop_1_prs3}, {stq_uop_0_prs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3 = _GEN_324[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_325 = {{stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_0_ppred}, {stq_uop_23_ppred}, {stq_uop_22_ppred}, {stq_uop_21_ppred}, {stq_uop_20_ppred}, {stq_uop_19_ppred}, {stq_uop_18_ppred}, {stq_uop_17_ppred}, {stq_uop_16_ppred}, {stq_uop_15_ppred}, {stq_uop_14_ppred}, {stq_uop_13_ppred}, {stq_uop_12_ppred}, {stq_uop_11_ppred}, {stq_uop_10_ppred}, {stq_uop_9_ppred}, {stq_uop_8_ppred}, {stq_uop_7_ppred}, {stq_uop_6_ppred}, {stq_uop_5_ppred}, {stq_uop_4_ppred}, {stq_uop_3_ppred}, {stq_uop_2_ppred}, {stq_uop_1_ppred}, {stq_uop_0_ppred}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred = _GEN_325[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_326 = {{stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_0_prs1_busy}, {stq_uop_23_prs1_busy}, {stq_uop_22_prs1_busy}, {stq_uop_21_prs1_busy}, {stq_uop_20_prs1_busy}, {stq_uop_19_prs1_busy}, {stq_uop_18_prs1_busy}, {stq_uop_17_prs1_busy}, {stq_uop_16_prs1_busy}, {stq_uop_15_prs1_busy}, {stq_uop_14_prs1_busy}, {stq_uop_13_prs1_busy}, {stq_uop_12_prs1_busy}, {stq_uop_11_prs1_busy}, {stq_uop_10_prs1_busy}, {stq_uop_9_prs1_busy}, {stq_uop_8_prs1_busy}, {stq_uop_7_prs1_busy}, {stq_uop_6_prs1_busy}, {stq_uop_5_prs1_busy}, {stq_uop_4_prs1_busy}, {stq_uop_3_prs1_busy}, {stq_uop_2_prs1_busy}, {stq_uop_1_prs1_busy}, {stq_uop_0_prs1_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs1_busy = _GEN_326[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_327 = {{stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_0_prs2_busy}, {stq_uop_23_prs2_busy}, {stq_uop_22_prs2_busy}, {stq_uop_21_prs2_busy}, {stq_uop_20_prs2_busy}, {stq_uop_19_prs2_busy}, {stq_uop_18_prs2_busy}, {stq_uop_17_prs2_busy}, {stq_uop_16_prs2_busy}, {stq_uop_15_prs2_busy}, {stq_uop_14_prs2_busy}, {stq_uop_13_prs2_busy}, {stq_uop_12_prs2_busy}, {stq_uop_11_prs2_busy}, {stq_uop_10_prs2_busy}, {stq_uop_9_prs2_busy}, {stq_uop_8_prs2_busy}, {stq_uop_7_prs2_busy}, {stq_uop_6_prs2_busy}, {stq_uop_5_prs2_busy}, {stq_uop_4_prs2_busy}, {stq_uop_3_prs2_busy}, {stq_uop_2_prs2_busy}, {stq_uop_1_prs2_busy}, {stq_uop_0_prs2_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs2_busy = _GEN_327[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_328 = {{stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_0_prs3_busy}, {stq_uop_23_prs3_busy}, {stq_uop_22_prs3_busy}, {stq_uop_21_prs3_busy}, {stq_uop_20_prs3_busy}, {stq_uop_19_prs3_busy}, {stq_uop_18_prs3_busy}, {stq_uop_17_prs3_busy}, {stq_uop_16_prs3_busy}, {stq_uop_15_prs3_busy}, {stq_uop_14_prs3_busy}, {stq_uop_13_prs3_busy}, {stq_uop_12_prs3_busy}, {stq_uop_11_prs3_busy}, {stq_uop_10_prs3_busy}, {stq_uop_9_prs3_busy}, {stq_uop_8_prs3_busy}, {stq_uop_7_prs3_busy}, {stq_uop_6_prs3_busy}, {stq_uop_5_prs3_busy}, {stq_uop_4_prs3_busy}, {stq_uop_3_prs3_busy}, {stq_uop_2_prs3_busy}, {stq_uop_1_prs3_busy}, {stq_uop_0_prs3_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_prs3_busy = _GEN_328[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_329 = {{stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_0_ppred_busy}, {stq_uop_23_ppred_busy}, {stq_uop_22_ppred_busy}, {stq_uop_21_ppred_busy}, {stq_uop_20_ppred_busy}, {stq_uop_19_ppred_busy}, {stq_uop_18_ppred_busy}, {stq_uop_17_ppred_busy}, {stq_uop_16_ppred_busy}, {stq_uop_15_ppred_busy}, {stq_uop_14_ppred_busy}, {stq_uop_13_ppred_busy}, {stq_uop_12_ppred_busy}, {stq_uop_11_ppred_busy}, {stq_uop_10_ppred_busy}, {stq_uop_9_ppred_busy}, {stq_uop_8_ppred_busy}, {stq_uop_7_ppred_busy}, {stq_uop_6_ppred_busy}, {stq_uop_5_ppred_busy}, {stq_uop_4_ppred_busy}, {stq_uop_3_ppred_busy}, {stq_uop_2_ppred_busy}, {stq_uop_1_ppred_busy}, {stq_uop_0_ppred_busy}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ppred_busy = _GEN_329[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][6:0] _GEN_330 = {{stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_0_stale_pdst}, {stq_uop_23_stale_pdst}, {stq_uop_22_stale_pdst}, {stq_uop_21_stale_pdst}, {stq_uop_20_stale_pdst}, {stq_uop_19_stale_pdst}, {stq_uop_18_stale_pdst}, {stq_uop_17_stale_pdst}, {stq_uop_16_stale_pdst}, {stq_uop_15_stale_pdst}, {stq_uop_14_stale_pdst}, {stq_uop_13_stale_pdst}, {stq_uop_12_stale_pdst}, {stq_uop_11_stale_pdst}, {stq_uop_10_stale_pdst}, {stq_uop_9_stale_pdst}, {stq_uop_8_stale_pdst}, {stq_uop_7_stale_pdst}, {stq_uop_6_stale_pdst}, {stq_uop_5_stale_pdst}, {stq_uop_4_stale_pdst}, {stq_uop_3_stale_pdst}, {stq_uop_2_stale_pdst}, {stq_uop_1_stale_pdst}, {stq_uop_0_stale_pdst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_stale_pdst = _GEN_330[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_331 = {{stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_0_exception}, {stq_uop_23_exception}, {stq_uop_22_exception}, {stq_uop_21_exception}, {stq_uop_20_exception}, {stq_uop_19_exception}, {stq_uop_18_exception}, {stq_uop_17_exception}, {stq_uop_16_exception}, {stq_uop_15_exception}, {stq_uop_14_exception}, {stq_uop_13_exception}, {stq_uop_12_exception}, {stq_uop_11_exception}, {stq_uop_10_exception}, {stq_uop_9_exception}, {stq_uop_8_exception}, {stq_uop_7_exception}, {stq_uop_6_exception}, {stq_uop_5_exception}, {stq_uop_4_exception}, {stq_uop_3_exception}, {stq_uop_2_exception}, {stq_uop_1_exception}, {stq_uop_0_exception}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exception = _GEN_331[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][63:0] _GEN_332 = {{stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_0_exc_cause}, {stq_uop_23_exc_cause}, {stq_uop_22_exc_cause}, {stq_uop_21_exc_cause}, {stq_uop_20_exc_cause}, {stq_uop_19_exc_cause}, {stq_uop_18_exc_cause}, {stq_uop_17_exc_cause}, {stq_uop_16_exc_cause}, {stq_uop_15_exc_cause}, {stq_uop_14_exc_cause}, {stq_uop_13_exc_cause}, {stq_uop_12_exc_cause}, {stq_uop_11_exc_cause}, {stq_uop_10_exc_cause}, {stq_uop_9_exc_cause}, {stq_uop_8_exc_cause}, {stq_uop_7_exc_cause}, {stq_uop_6_exc_cause}, {stq_uop_5_exc_cause}, {stq_uop_4_exc_cause}, {stq_uop_3_exc_cause}, {stq_uop_2_exc_cause}, {stq_uop_1_exc_cause}, {stq_uop_0_exc_cause}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_exc_cause = _GEN_332[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_333 = {{stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_0_mem_cmd}, {stq_uop_23_mem_cmd}, {stq_uop_22_mem_cmd}, {stq_uop_21_mem_cmd}, {stq_uop_20_mem_cmd}, {stq_uop_19_mem_cmd}, {stq_uop_18_mem_cmd}, {stq_uop_17_mem_cmd}, {stq_uop_16_mem_cmd}, {stq_uop_15_mem_cmd}, {stq_uop_14_mem_cmd}, {stq_uop_13_mem_cmd}, {stq_uop_12_mem_cmd}, {stq_uop_11_mem_cmd}, {stq_uop_10_mem_cmd}, {stq_uop_9_mem_cmd}, {stq_uop_8_mem_cmd}, {stq_uop_7_mem_cmd}, {stq_uop_6_mem_cmd}, {stq_uop_5_mem_cmd}, {stq_uop_4_mem_cmd}, {stq_uop_3_mem_cmd}, {stq_uop_2_mem_cmd}, {stq_uop_1_mem_cmd}, {stq_uop_0_mem_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_cmd = _GEN_333[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_334 = {{stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_0_mem_size}, {stq_uop_23_mem_size}, {stq_uop_22_mem_size}, {stq_uop_21_mem_size}, {stq_uop_20_mem_size}, {stq_uop_19_mem_size}, {stq_uop_18_mem_size}, {stq_uop_17_mem_size}, {stq_uop_16_mem_size}, {stq_uop_15_mem_size}, {stq_uop_14_mem_size}, {stq_uop_13_mem_size}, {stq_uop_12_mem_size}, {stq_uop_11_mem_size}, {stq_uop_10_mem_size}, {stq_uop_9_mem_size}, {stq_uop_8_mem_size}, {stq_uop_7_mem_size}, {stq_uop_6_mem_size}, {stq_uop_5_mem_size}, {stq_uop_4_mem_size}, {stq_uop_3_mem_size}, {stq_uop_2_mem_size}, {stq_uop_1_mem_size}, {stq_uop_0_mem_size}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_size = _GEN_334[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_335 = {{stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_0_mem_signed}, {stq_uop_23_mem_signed}, {stq_uop_22_mem_signed}, {stq_uop_21_mem_signed}, {stq_uop_20_mem_signed}, {stq_uop_19_mem_signed}, {stq_uop_18_mem_signed}, {stq_uop_17_mem_signed}, {stq_uop_16_mem_signed}, {stq_uop_15_mem_signed}, {stq_uop_14_mem_signed}, {stq_uop_13_mem_signed}, {stq_uop_12_mem_signed}, {stq_uop_11_mem_signed}, {stq_uop_10_mem_signed}, {stq_uop_9_mem_signed}, {stq_uop_8_mem_signed}, {stq_uop_7_mem_signed}, {stq_uop_6_mem_signed}, {stq_uop_5_mem_signed}, {stq_uop_4_mem_signed}, {stq_uop_3_mem_signed}, {stq_uop_2_mem_signed}, {stq_uop_1_mem_signed}, {stq_uop_0_mem_signed}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_mem_signed = _GEN_335[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_336 = {{stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_0_uses_ldq}, {stq_uop_23_uses_ldq}, {stq_uop_22_uses_ldq}, {stq_uop_21_uses_ldq}, {stq_uop_20_uses_ldq}, {stq_uop_19_uses_ldq}, {stq_uop_18_uses_ldq}, {stq_uop_17_uses_ldq}, {stq_uop_16_uses_ldq}, {stq_uop_15_uses_ldq}, {stq_uop_14_uses_ldq}, {stq_uop_13_uses_ldq}, {stq_uop_12_uses_ldq}, {stq_uop_11_uses_ldq}, {stq_uop_10_uses_ldq}, {stq_uop_9_uses_ldq}, {stq_uop_8_uses_ldq}, {stq_uop_7_uses_ldq}, {stq_uop_6_uses_ldq}, {stq_uop_5_uses_ldq}, {stq_uop_4_uses_ldq}, {stq_uop_3_uses_ldq}, {stq_uop_2_uses_ldq}, {stq_uop_1_uses_ldq}, {stq_uop_0_uses_ldq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_ldq = _GEN_336[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_337 = {{stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_0_uses_stq}, {stq_uop_23_uses_stq}, {stq_uop_22_uses_stq}, {stq_uop_21_uses_stq}, {stq_uop_20_uses_stq}, {stq_uop_19_uses_stq}, {stq_uop_18_uses_stq}, {stq_uop_17_uses_stq}, {stq_uop_16_uses_stq}, {stq_uop_15_uses_stq}, {stq_uop_14_uses_stq}, {stq_uop_13_uses_stq}, {stq_uop_12_uses_stq}, {stq_uop_11_uses_stq}, {stq_uop_10_uses_stq}, {stq_uop_9_uses_stq}, {stq_uop_8_uses_stq}, {stq_uop_7_uses_stq}, {stq_uop_6_uses_stq}, {stq_uop_5_uses_stq}, {stq_uop_4_uses_stq}, {stq_uop_3_uses_stq}, {stq_uop_2_uses_stq}, {stq_uop_1_uses_stq}, {stq_uop_0_uses_stq}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_uses_stq = _GEN_337[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_338 = {{stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_0_is_unique}, {stq_uop_23_is_unique}, {stq_uop_22_is_unique}, {stq_uop_21_is_unique}, {stq_uop_20_is_unique}, {stq_uop_19_is_unique}, {stq_uop_18_is_unique}, {stq_uop_17_is_unique}, {stq_uop_16_is_unique}, {stq_uop_15_is_unique}, {stq_uop_14_is_unique}, {stq_uop_13_is_unique}, {stq_uop_12_is_unique}, {stq_uop_11_is_unique}, {stq_uop_10_is_unique}, {stq_uop_9_is_unique}, {stq_uop_8_is_unique}, {stq_uop_7_is_unique}, {stq_uop_6_is_unique}, {stq_uop_5_is_unique}, {stq_uop_4_is_unique}, {stq_uop_3_is_unique}, {stq_uop_2_is_unique}, {stq_uop_1_is_unique}, {stq_uop_0_is_unique}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_is_unique = _GEN_338[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_339 = {{stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_0_flush_on_commit}, {stq_uop_23_flush_on_commit}, {stq_uop_22_flush_on_commit}, {stq_uop_21_flush_on_commit}, {stq_uop_20_flush_on_commit}, {stq_uop_19_flush_on_commit}, {stq_uop_18_flush_on_commit}, {stq_uop_17_flush_on_commit}, {stq_uop_16_flush_on_commit}, {stq_uop_15_flush_on_commit}, {stq_uop_14_flush_on_commit}, {stq_uop_13_flush_on_commit}, {stq_uop_12_flush_on_commit}, {stq_uop_11_flush_on_commit}, {stq_uop_10_flush_on_commit}, {stq_uop_9_flush_on_commit}, {stq_uop_8_flush_on_commit}, {stq_uop_7_flush_on_commit}, {stq_uop_6_flush_on_commit}, {stq_uop_5_flush_on_commit}, {stq_uop_4_flush_on_commit}, {stq_uop_3_flush_on_commit}, {stq_uop_2_flush_on_commit}, {stq_uop_1_flush_on_commit}, {stq_uop_0_flush_on_commit}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_flush_on_commit = _GEN_339[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_340 = {{stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_0_csr_cmd}, {stq_uop_23_csr_cmd}, {stq_uop_22_csr_cmd}, {stq_uop_21_csr_cmd}, {stq_uop_20_csr_cmd}, {stq_uop_19_csr_cmd}, {stq_uop_18_csr_cmd}, {stq_uop_17_csr_cmd}, {stq_uop_16_csr_cmd}, {stq_uop_15_csr_cmd}, {stq_uop_14_csr_cmd}, {stq_uop_13_csr_cmd}, {stq_uop_12_csr_cmd}, {stq_uop_11_csr_cmd}, {stq_uop_10_csr_cmd}, {stq_uop_9_csr_cmd}, {stq_uop_8_csr_cmd}, {stq_uop_7_csr_cmd}, {stq_uop_6_csr_cmd}, {stq_uop_5_csr_cmd}, {stq_uop_4_csr_cmd}, {stq_uop_3_csr_cmd}, {stq_uop_2_csr_cmd}, {stq_uop_1_csr_cmd}, {stq_uop_0_csr_cmd}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_csr_cmd = _GEN_340[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_341 = {{stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}, {stq_uop_23_ldst_is_rs1}, {stq_uop_22_ldst_is_rs1}, {stq_uop_21_ldst_is_rs1}, {stq_uop_20_ldst_is_rs1}, {stq_uop_19_ldst_is_rs1}, {stq_uop_18_ldst_is_rs1}, {stq_uop_17_ldst_is_rs1}, {stq_uop_16_ldst_is_rs1}, {stq_uop_15_ldst_is_rs1}, {stq_uop_14_ldst_is_rs1}, {stq_uop_13_ldst_is_rs1}, {stq_uop_12_ldst_is_rs1}, {stq_uop_11_ldst_is_rs1}, {stq_uop_10_ldst_is_rs1}, {stq_uop_9_ldst_is_rs1}, {stq_uop_8_ldst_is_rs1}, {stq_uop_7_ldst_is_rs1}, {stq_uop_6_ldst_is_rs1}, {stq_uop_5_ldst_is_rs1}, {stq_uop_4_ldst_is_rs1}, {stq_uop_3_ldst_is_rs1}, {stq_uop_2_ldst_is_rs1}, {stq_uop_1_ldst_is_rs1}, {stq_uop_0_ldst_is_rs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_342 = {{stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_0_ldst}, {stq_uop_23_ldst}, {stq_uop_22_ldst}, {stq_uop_21_ldst}, {stq_uop_20_ldst}, {stq_uop_19_ldst}, {stq_uop_18_ldst}, {stq_uop_17_ldst}, {stq_uop_16_ldst}, {stq_uop_15_ldst}, {stq_uop_14_ldst}, {stq_uop_13_ldst}, {stq_uop_12_ldst}, {stq_uop_11_ldst}, {stq_uop_10_ldst}, {stq_uop_9_ldst}, {stq_uop_8_ldst}, {stq_uop_7_ldst}, {stq_uop_6_ldst}, {stq_uop_5_ldst}, {stq_uop_4_ldst}, {stq_uop_3_ldst}, {stq_uop_2_ldst}, {stq_uop_1_ldst}, {stq_uop_0_ldst}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_ldst = _GEN_342[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_343 = {{stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_0_lrs1}, {stq_uop_23_lrs1}, {stq_uop_22_lrs1}, {stq_uop_21_lrs1}, {stq_uop_20_lrs1}, {stq_uop_19_lrs1}, {stq_uop_18_lrs1}, {stq_uop_17_lrs1}, {stq_uop_16_lrs1}, {stq_uop_15_lrs1}, {stq_uop_14_lrs1}, {stq_uop_13_lrs1}, {stq_uop_12_lrs1}, {stq_uop_11_lrs1}, {stq_uop_10_lrs1}, {stq_uop_9_lrs1}, {stq_uop_8_lrs1}, {stq_uop_7_lrs1}, {stq_uop_6_lrs1}, {stq_uop_5_lrs1}, {stq_uop_4_lrs1}, {stq_uop_3_lrs1}, {stq_uop_2_lrs1}, {stq_uop_1_lrs1}, {stq_uop_0_lrs1}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1 = _GEN_343[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_344 = {{stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_0_lrs2}, {stq_uop_23_lrs2}, {stq_uop_22_lrs2}, {stq_uop_21_lrs2}, {stq_uop_20_lrs2}, {stq_uop_19_lrs2}, {stq_uop_18_lrs2}, {stq_uop_17_lrs2}, {stq_uop_16_lrs2}, {stq_uop_15_lrs2}, {stq_uop_14_lrs2}, {stq_uop_13_lrs2}, {stq_uop_12_lrs2}, {stq_uop_11_lrs2}, {stq_uop_10_lrs2}, {stq_uop_9_lrs2}, {stq_uop_8_lrs2}, {stq_uop_7_lrs2}, {stq_uop_6_lrs2}, {stq_uop_5_lrs2}, {stq_uop_4_lrs2}, {stq_uop_3_lrs2}, {stq_uop_2_lrs2}, {stq_uop_1_lrs2}, {stq_uop_0_lrs2}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2 = _GEN_344[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][5:0] _GEN_345 = {{stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_0_lrs3}, {stq_uop_23_lrs3}, {stq_uop_22_lrs3}, {stq_uop_21_lrs3}, {stq_uop_20_lrs3}, {stq_uop_19_lrs3}, {stq_uop_18_lrs3}, {stq_uop_17_lrs3}, {stq_uop_16_lrs3}, {stq_uop_15_lrs3}, {stq_uop_14_lrs3}, {stq_uop_13_lrs3}, {stq_uop_12_lrs3}, {stq_uop_11_lrs3}, {stq_uop_10_lrs3}, {stq_uop_9_lrs3}, {stq_uop_8_lrs3}, {stq_uop_7_lrs3}, {stq_uop_6_lrs3}, {stq_uop_5_lrs3}, {stq_uop_4_lrs3}, {stq_uop_3_lrs3}, {stq_uop_2_lrs3}, {stq_uop_1_lrs3}, {stq_uop_0_lrs3}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs3 = _GEN_345[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_346 = {{stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_0_dst_rtype}, {stq_uop_23_dst_rtype}, {stq_uop_22_dst_rtype}, {stq_uop_21_dst_rtype}, {stq_uop_20_dst_rtype}, {stq_uop_19_dst_rtype}, {stq_uop_18_dst_rtype}, {stq_uop_17_dst_rtype}, {stq_uop_16_dst_rtype}, {stq_uop_15_dst_rtype}, {stq_uop_14_dst_rtype}, {stq_uop_13_dst_rtype}, {stq_uop_12_dst_rtype}, {stq_uop_11_dst_rtype}, {stq_uop_10_dst_rtype}, {stq_uop_9_dst_rtype}, {stq_uop_8_dst_rtype}, {stq_uop_7_dst_rtype}, {stq_uop_6_dst_rtype}, {stq_uop_5_dst_rtype}, {stq_uop_4_dst_rtype}, {stq_uop_3_dst_rtype}, {stq_uop_2_dst_rtype}, {stq_uop_1_dst_rtype}, {stq_uop_0_dst_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_dst_rtype = _GEN_346[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_347 = {{stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_0_lrs1_rtype}, {stq_uop_23_lrs1_rtype}, {stq_uop_22_lrs1_rtype}, {stq_uop_21_lrs1_rtype}, {stq_uop_20_lrs1_rtype}, {stq_uop_19_lrs1_rtype}, {stq_uop_18_lrs1_rtype}, {stq_uop_17_lrs1_rtype}, {stq_uop_16_lrs1_rtype}, {stq_uop_15_lrs1_rtype}, {stq_uop_14_lrs1_rtype}, {stq_uop_13_lrs1_rtype}, {stq_uop_12_lrs1_rtype}, {stq_uop_11_lrs1_rtype}, {stq_uop_10_lrs1_rtype}, {stq_uop_9_lrs1_rtype}, {stq_uop_8_lrs1_rtype}, {stq_uop_7_lrs1_rtype}, {stq_uop_6_lrs1_rtype}, {stq_uop_5_lrs1_rtype}, {stq_uop_4_lrs1_rtype}, {stq_uop_3_lrs1_rtype}, {stq_uop_2_lrs1_rtype}, {stq_uop_1_lrs1_rtype}, {stq_uop_0_lrs1_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_348 = {{stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_0_lrs2_rtype}, {stq_uop_23_lrs2_rtype}, {stq_uop_22_lrs2_rtype}, {stq_uop_21_lrs2_rtype}, {stq_uop_20_lrs2_rtype}, {stq_uop_19_lrs2_rtype}, {stq_uop_18_lrs2_rtype}, {stq_uop_17_lrs2_rtype}, {stq_uop_16_lrs2_rtype}, {stq_uop_15_lrs2_rtype}, {stq_uop_14_lrs2_rtype}, {stq_uop_13_lrs2_rtype}, {stq_uop_12_lrs2_rtype}, {stq_uop_11_lrs2_rtype}, {stq_uop_10_lrs2_rtype}, {stq_uop_9_lrs2_rtype}, {stq_uop_8_lrs2_rtype}, {stq_uop_7_lrs2_rtype}, {stq_uop_6_lrs2_rtype}, {stq_uop_5_lrs2_rtype}, {stq_uop_4_lrs2_rtype}, {stq_uop_3_lrs2_rtype}, {stq_uop_2_lrs2_rtype}, {stq_uop_1_lrs2_rtype}, {stq_uop_0_lrs2_rtype}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_349 = {{stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_0_frs3_en}, {stq_uop_23_frs3_en}, {stq_uop_22_frs3_en}, {stq_uop_21_frs3_en}, {stq_uop_20_frs3_en}, {stq_uop_19_frs3_en}, {stq_uop_18_frs3_en}, {stq_uop_17_frs3_en}, {stq_uop_16_frs3_en}, {stq_uop_15_frs3_en}, {stq_uop_14_frs3_en}, {stq_uop_13_frs3_en}, {stq_uop_12_frs3_en}, {stq_uop_11_frs3_en}, {stq_uop_10_frs3_en}, {stq_uop_9_frs3_en}, {stq_uop_8_frs3_en}, {stq_uop_7_frs3_en}, {stq_uop_6_frs3_en}, {stq_uop_5_frs3_en}, {stq_uop_4_frs3_en}, {stq_uop_3_frs3_en}, {stq_uop_2_frs3_en}, {stq_uop_1_frs3_en}, {stq_uop_0_frs3_en}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_frs3_en = _GEN_349[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_350 = {{stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_0_fcn_dw}, {stq_uop_23_fcn_dw}, {stq_uop_22_fcn_dw}, {stq_uop_21_fcn_dw}, {stq_uop_20_fcn_dw}, {stq_uop_19_fcn_dw}, {stq_uop_18_fcn_dw}, {stq_uop_17_fcn_dw}, {stq_uop_16_fcn_dw}, {stq_uop_15_fcn_dw}, {stq_uop_14_fcn_dw}, {stq_uop_13_fcn_dw}, {stq_uop_12_fcn_dw}, {stq_uop_11_fcn_dw}, {stq_uop_10_fcn_dw}, {stq_uop_9_fcn_dw}, {stq_uop_8_fcn_dw}, {stq_uop_7_fcn_dw}, {stq_uop_6_fcn_dw}, {stq_uop_5_fcn_dw}, {stq_uop_4_fcn_dw}, {stq_uop_3_fcn_dw}, {stq_uop_2_fcn_dw}, {stq_uop_1_fcn_dw}, {stq_uop_0_fcn_dw}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_dw = _GEN_350[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][4:0] _GEN_351 = {{stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_0_fcn_op}, {stq_uop_23_fcn_op}, {stq_uop_22_fcn_op}, {stq_uop_21_fcn_op}, {stq_uop_20_fcn_op}, {stq_uop_19_fcn_op}, {stq_uop_18_fcn_op}, {stq_uop_17_fcn_op}, {stq_uop_16_fcn_op}, {stq_uop_15_fcn_op}, {stq_uop_14_fcn_op}, {stq_uop_13_fcn_op}, {stq_uop_12_fcn_op}, {stq_uop_11_fcn_op}, {stq_uop_10_fcn_op}, {stq_uop_9_fcn_op}, {stq_uop_8_fcn_op}, {stq_uop_7_fcn_op}, {stq_uop_6_fcn_op}, {stq_uop_5_fcn_op}, {stq_uop_4_fcn_op}, {stq_uop_3_fcn_op}, {stq_uop_2_fcn_op}, {stq_uop_1_fcn_op}, {stq_uop_0_fcn_op}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fcn_op = _GEN_351[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_352 = {{stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_0_fp_val}, {stq_uop_23_fp_val}, {stq_uop_22_fp_val}, {stq_uop_21_fp_val}, {stq_uop_20_fp_val}, {stq_uop_19_fp_val}, {stq_uop_18_fp_val}, {stq_uop_17_fp_val}, {stq_uop_16_fp_val}, {stq_uop_15_fp_val}, {stq_uop_14_fp_val}, {stq_uop_13_fp_val}, {stq_uop_12_fp_val}, {stq_uop_11_fp_val}, {stq_uop_10_fp_val}, {stq_uop_9_fp_val}, {stq_uop_8_fp_val}, {stq_uop_7_fp_val}, {stq_uop_6_fp_val}, {stq_uop_5_fp_val}, {stq_uop_4_fp_val}, {stq_uop_3_fp_val}, {stq_uop_2_fp_val}, {stq_uop_1_fp_val}, {stq_uop_0_fp_val}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_val = _GEN_352[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_353 = {{stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_0_fp_rm}, {stq_uop_23_fp_rm}, {stq_uop_22_fp_rm}, {stq_uop_21_fp_rm}, {stq_uop_20_fp_rm}, {stq_uop_19_fp_rm}, {stq_uop_18_fp_rm}, {stq_uop_17_fp_rm}, {stq_uop_16_fp_rm}, {stq_uop_15_fp_rm}, {stq_uop_14_fp_rm}, {stq_uop_13_fp_rm}, {stq_uop_12_fp_rm}, {stq_uop_11_fp_rm}, {stq_uop_10_fp_rm}, {stq_uop_9_fp_rm}, {stq_uop_8_fp_rm}, {stq_uop_7_fp_rm}, {stq_uop_6_fp_rm}, {stq_uop_5_fp_rm}, {stq_uop_4_fp_rm}, {stq_uop_3_fp_rm}, {stq_uop_2_fp_rm}, {stq_uop_1_fp_rm}, {stq_uop_0_fp_rm}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_rm = _GEN_353[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][1:0] _GEN_354 = {{stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_0_fp_typ}, {stq_uop_23_fp_typ}, {stq_uop_22_fp_typ}, {stq_uop_21_fp_typ}, {stq_uop_20_fp_typ}, {stq_uop_19_fp_typ}, {stq_uop_18_fp_typ}, {stq_uop_17_fp_typ}, {stq_uop_16_fp_typ}, {stq_uop_15_fp_typ}, {stq_uop_14_fp_typ}, {stq_uop_13_fp_typ}, {stq_uop_12_fp_typ}, {stq_uop_11_fp_typ}, {stq_uop_10_fp_typ}, {stq_uop_9_fp_typ}, {stq_uop_8_fp_typ}, {stq_uop_7_fp_typ}, {stq_uop_6_fp_typ}, {stq_uop_5_fp_typ}, {stq_uop_4_fp_typ}, {stq_uop_3_fp_typ}, {stq_uop_2_fp_typ}, {stq_uop_1_fp_typ}, {stq_uop_0_fp_typ}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_fp_typ = _GEN_354[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_355 = {{stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}, {stq_uop_23_xcpt_pf_if}, {stq_uop_22_xcpt_pf_if}, {stq_uop_21_xcpt_pf_if}, {stq_uop_20_xcpt_pf_if}, {stq_uop_19_xcpt_pf_if}, {stq_uop_18_xcpt_pf_if}, {stq_uop_17_xcpt_pf_if}, {stq_uop_16_xcpt_pf_if}, {stq_uop_15_xcpt_pf_if}, {stq_uop_14_xcpt_pf_if}, {stq_uop_13_xcpt_pf_if}, {stq_uop_12_xcpt_pf_if}, {stq_uop_11_xcpt_pf_if}, {stq_uop_10_xcpt_pf_if}, {stq_uop_9_xcpt_pf_if}, {stq_uop_8_xcpt_pf_if}, {stq_uop_7_xcpt_pf_if}, {stq_uop_6_xcpt_pf_if}, {stq_uop_5_xcpt_pf_if}, {stq_uop_4_xcpt_pf_if}, {stq_uop_3_xcpt_pf_if}, {stq_uop_2_xcpt_pf_if}, {stq_uop_1_xcpt_pf_if}, {stq_uop_0_xcpt_pf_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_356 = {{stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}, {stq_uop_23_xcpt_ae_if}, {stq_uop_22_xcpt_ae_if}, {stq_uop_21_xcpt_ae_if}, {stq_uop_20_xcpt_ae_if}, {stq_uop_19_xcpt_ae_if}, {stq_uop_18_xcpt_ae_if}, {stq_uop_17_xcpt_ae_if}, {stq_uop_16_xcpt_ae_if}, {stq_uop_15_xcpt_ae_if}, {stq_uop_14_xcpt_ae_if}, {stq_uop_13_xcpt_ae_if}, {stq_uop_12_xcpt_ae_if}, {stq_uop_11_xcpt_ae_if}, {stq_uop_10_xcpt_ae_if}, {stq_uop_9_xcpt_ae_if}, {stq_uop_8_xcpt_ae_if}, {stq_uop_7_xcpt_ae_if}, {stq_uop_6_xcpt_ae_if}, {stq_uop_5_xcpt_ae_if}, {stq_uop_4_xcpt_ae_if}, {stq_uop_3_xcpt_ae_if}, {stq_uop_2_xcpt_ae_if}, {stq_uop_1_xcpt_ae_if}, {stq_uop_0_xcpt_ae_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_357 = {{stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}, {stq_uop_23_xcpt_ma_if}, {stq_uop_22_xcpt_ma_if}, {stq_uop_21_xcpt_ma_if}, {stq_uop_20_xcpt_ma_if}, {stq_uop_19_xcpt_ma_if}, {stq_uop_18_xcpt_ma_if}, {stq_uop_17_xcpt_ma_if}, {stq_uop_16_xcpt_ma_if}, {stq_uop_15_xcpt_ma_if}, {stq_uop_14_xcpt_ma_if}, {stq_uop_13_xcpt_ma_if}, {stq_uop_12_xcpt_ma_if}, {stq_uop_11_xcpt_ma_if}, {stq_uop_10_xcpt_ma_if}, {stq_uop_9_xcpt_ma_if}, {stq_uop_8_xcpt_ma_if}, {stq_uop_7_xcpt_ma_if}, {stq_uop_6_xcpt_ma_if}, {stq_uop_5_xcpt_ma_if}, {stq_uop_4_xcpt_ma_if}, {stq_uop_3_xcpt_ma_if}, {stq_uop_2_xcpt_ma_if}, {stq_uop_1_xcpt_ma_if}, {stq_uop_0_xcpt_ma_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_358 = {{stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_0_bp_debug_if}, {stq_uop_23_bp_debug_if}, {stq_uop_22_bp_debug_if}, {stq_uop_21_bp_debug_if}, {stq_uop_20_bp_debug_if}, {stq_uop_19_bp_debug_if}, {stq_uop_18_bp_debug_if}, {stq_uop_17_bp_debug_if}, {stq_uop_16_bp_debug_if}, {stq_uop_15_bp_debug_if}, {stq_uop_14_bp_debug_if}, {stq_uop_13_bp_debug_if}, {stq_uop_12_bp_debug_if}, {stq_uop_11_bp_debug_if}, {stq_uop_10_bp_debug_if}, {stq_uop_9_bp_debug_if}, {stq_uop_8_bp_debug_if}, {stq_uop_7_bp_debug_if}, {stq_uop_6_bp_debug_if}, {stq_uop_5_bp_debug_if}, {stq_uop_4_bp_debug_if}, {stq_uop_3_bp_debug_if}, {stq_uop_2_bp_debug_if}, {stq_uop_1_bp_debug_if}, {stq_uop_0_bp_debug_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_debug_if = _GEN_358[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_359 = {{stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}, {stq_uop_23_bp_xcpt_if}, {stq_uop_22_bp_xcpt_if}, {stq_uop_21_bp_xcpt_if}, {stq_uop_20_bp_xcpt_if}, {stq_uop_19_bp_xcpt_if}, {stq_uop_18_bp_xcpt_if}, {stq_uop_17_bp_xcpt_if}, {stq_uop_16_bp_xcpt_if}, {stq_uop_15_bp_xcpt_if}, {stq_uop_14_bp_xcpt_if}, {stq_uop_13_bp_xcpt_if}, {stq_uop_12_bp_xcpt_if}, {stq_uop_11_bp_xcpt_if}, {stq_uop_10_bp_xcpt_if}, {stq_uop_9_bp_xcpt_if}, {stq_uop_8_bp_xcpt_if}, {stq_uop_7_bp_xcpt_if}, {stq_uop_6_bp_xcpt_if}, {stq_uop_5_bp_xcpt_if}, {stq_uop_4_bp_xcpt_if}, {stq_uop_3_bp_xcpt_if}, {stq_uop_2_bp_xcpt_if}, {stq_uop_1_bp_xcpt_if}, {stq_uop_0_bp_xcpt_if}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_360 = {{stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_0_debug_fsrc}, {stq_uop_23_debug_fsrc}, {stq_uop_22_debug_fsrc}, {stq_uop_21_debug_fsrc}, {stq_uop_20_debug_fsrc}, {stq_uop_19_debug_fsrc}, {stq_uop_18_debug_fsrc}, {stq_uop_17_debug_fsrc}, {stq_uop_16_debug_fsrc}, {stq_uop_15_debug_fsrc}, {stq_uop_14_debug_fsrc}, {stq_uop_13_debug_fsrc}, {stq_uop_12_debug_fsrc}, {stq_uop_11_debug_fsrc}, {stq_uop_10_debug_fsrc}, {stq_uop_9_debug_fsrc}, {stq_uop_8_debug_fsrc}, {stq_uop_7_debug_fsrc}, {stq_uop_6_debug_fsrc}, {stq_uop_5_debug_fsrc}, {stq_uop_4_debug_fsrc}, {stq_uop_3_debug_fsrc}, {stq_uop_2_debug_fsrc}, {stq_uop_1_debug_fsrc}, {stq_uop_0_debug_fsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_fsrc = _GEN_360[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0][2:0] _GEN_361 = {{stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_0_debug_tsrc}, {stq_uop_23_debug_tsrc}, {stq_uop_22_debug_tsrc}, {stq_uop_21_debug_tsrc}, {stq_uop_20_debug_tsrc}, {stq_uop_19_debug_tsrc}, {stq_uop_18_debug_tsrc}, {stq_uop_17_debug_tsrc}, {stq_uop_16_debug_tsrc}, {stq_uop_15_debug_tsrc}, {stq_uop_14_debug_tsrc}, {stq_uop_13_debug_tsrc}, {stq_uop_12_debug_tsrc}, {stq_uop_11_debug_tsrc}, {stq_uop_10_debug_tsrc}, {stq_uop_9_debug_tsrc}, {stq_uop_8_debug_tsrc}, {stq_uop_7_debug_tsrc}, {stq_uop_6_debug_tsrc}, {stq_uop_5_debug_tsrc}, {stq_uop_4_debug_tsrc}, {stq_uop_3_debug_tsrc}, {stq_uop_2_debug_tsrc}, {stq_uop_1_debug_tsrc}, {stq_uop_0_debug_tsrc}}; // @[lsu.scala:252:32, :264:32] assign stq_incoming_e_e_bits_uop_debug_tsrc = _GEN_361[stq_incoming_idx_0]; // @[lsu.scala:262:17, :264:32, :321:49] wire [31:0] _GEN_362 = {{stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_0_valid}, {stq_addr_23_valid}, {stq_addr_22_valid}, {stq_addr_21_valid}, {stq_addr_20_valid}, {stq_addr_19_valid}, {stq_addr_18_valid}, {stq_addr_17_valid}, {stq_addr_16_valid}, {stq_addr_15_valid}, {stq_addr_14_valid}, {stq_addr_13_valid}, {stq_addr_12_valid}, {stq_addr_11_valid}, {stq_addr_10_valid}, {stq_addr_9_valid}, {stq_addr_8_valid}, {stq_addr_7_valid}, {stq_addr_6_valid}, {stq_addr_5_valid}, {stq_addr_4_valid}, {stq_addr_3_valid}, {stq_addr_2_valid}, {stq_addr_1_valid}, {stq_addr_0_valid}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_valid = _GEN_362[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [31:0][39:0] _GEN_363 = {{stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_0_bits}, {stq_addr_23_bits}, {stq_addr_22_bits}, {stq_addr_21_bits}, {stq_addr_20_bits}, {stq_addr_19_bits}, {stq_addr_18_bits}, {stq_addr_17_bits}, {stq_addr_16_bits}, {stq_addr_15_bits}, {stq_addr_14_bits}, {stq_addr_13_bits}, {stq_addr_12_bits}, {stq_addr_11_bits}, {stq_addr_10_bits}, {stq_addr_9_bits}, {stq_addr_8_bits}, {stq_addr_7_bits}, {stq_addr_6_bits}, {stq_addr_5_bits}, {stq_addr_4_bits}, {stq_addr_3_bits}, {stq_addr_2_bits}, {stq_addr_1_bits}, {stq_addr_0_bits}}; // @[lsu.scala:253:32, :265:32] assign stq_incoming_e_e_bits_addr_bits = _GEN_363[stq_incoming_idx_0]; // @[lsu.scala:262:17, :265:32, :321:49] wire [31:0] _GEN_364 = {{stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_0}, {stq_addr_is_virtual_23}, {stq_addr_is_virtual_22}, {stq_addr_is_virtual_21}, {stq_addr_is_virtual_20}, {stq_addr_is_virtual_19}, {stq_addr_is_virtual_18}, {stq_addr_is_virtual_17}, {stq_addr_is_virtual_16}, {stq_addr_is_virtual_15}, {stq_addr_is_virtual_14}, {stq_addr_is_virtual_13}, {stq_addr_is_virtual_12}, {stq_addr_is_virtual_11}, {stq_addr_is_virtual_10}, {stq_addr_is_virtual_9}, {stq_addr_is_virtual_8}, {stq_addr_is_virtual_7}, {stq_addr_is_virtual_6}, {stq_addr_is_virtual_5}, {stq_addr_is_virtual_4}, {stq_addr_is_virtual_3}, {stq_addr_is_virtual_2}, {stq_addr_is_virtual_1}, {stq_addr_is_virtual_0}}; // @[lsu.scala:254:32, :266:32] assign stq_incoming_e_e_bits_addr_is_virtual = _GEN_364[stq_incoming_idx_0]; // @[lsu.scala:262:17, :266:32, :321:49] wire [31:0] _GEN_365 = {{stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_0_valid}, {stq_data_23_valid}, {stq_data_22_valid}, {stq_data_21_valid}, {stq_data_20_valid}, {stq_data_19_valid}, {stq_data_18_valid}, {stq_data_17_valid}, {stq_data_16_valid}, {stq_data_15_valid}, {stq_data_14_valid}, {stq_data_13_valid}, {stq_data_12_valid}, {stq_data_11_valid}, {stq_data_10_valid}, {stq_data_9_valid}, {stq_data_8_valid}, {stq_data_7_valid}, {stq_data_6_valid}, {stq_data_5_valid}, {stq_data_4_valid}, {stq_data_3_valid}, {stq_data_2_valid}, {stq_data_1_valid}, {stq_data_0_valid}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_valid = _GEN_365[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [31:0][63:0] _GEN_366 = {{stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_0_bits}, {stq_data_23_bits}, {stq_data_22_bits}, {stq_data_21_bits}, {stq_data_20_bits}, {stq_data_19_bits}, {stq_data_18_bits}, {stq_data_17_bits}, {stq_data_16_bits}, {stq_data_15_bits}, {stq_data_14_bits}, {stq_data_13_bits}, {stq_data_12_bits}, {stq_data_11_bits}, {stq_data_10_bits}, {stq_data_9_bits}, {stq_data_8_bits}, {stq_data_7_bits}, {stq_data_6_bits}, {stq_data_5_bits}, {stq_data_4_bits}, {stq_data_3_bits}, {stq_data_2_bits}, {stq_data_1_bits}, {stq_data_0_bits}}; // @[lsu.scala:255:32, :267:32] assign stq_incoming_e_e_bits_data_bits = _GEN_366[stq_incoming_idx_0]; // @[lsu.scala:262:17, :267:32, :321:49] wire [31:0] _GEN_367 = {{stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_0}, {stq_committed_23}, {stq_committed_22}, {stq_committed_21}, {stq_committed_20}, {stq_committed_19}, {stq_committed_18}, {stq_committed_17}, {stq_committed_16}, {stq_committed_15}, {stq_committed_14}, {stq_committed_13}, {stq_committed_12}, {stq_committed_11}, {stq_committed_10}, {stq_committed_9}, {stq_committed_8}, {stq_committed_7}, {stq_committed_6}, {stq_committed_5}, {stq_committed_4}, {stq_committed_3}, {stq_committed_2}, {stq_committed_1}, {stq_committed_0}}; // @[lsu.scala:256:32, :268:32] assign stq_incoming_e_e_bits_committed = _GEN_367[stq_incoming_idx_0]; // @[lsu.scala:262:17, :268:32, :321:49] wire [31:0] _GEN_368 = {{stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_0}, {stq_succeeded_23}, {stq_succeeded_22}, {stq_succeeded_21}, {stq_succeeded_20}, {stq_succeeded_19}, {stq_succeeded_18}, {stq_succeeded_17}, {stq_succeeded_16}, {stq_succeeded_15}, {stq_succeeded_14}, {stq_succeeded_13}, {stq_succeeded_12}, {stq_succeeded_11}, {stq_succeeded_10}, {stq_succeeded_9}, {stq_succeeded_8}, {stq_succeeded_7}, {stq_succeeded_6}, {stq_succeeded_5}, {stq_succeeded_4}, {stq_succeeded_3}, {stq_succeeded_2}, {stq_succeeded_1}, {stq_succeeded_0}}; // @[lsu.scala:257:32, :269:32] assign stq_incoming_e_e_bits_succeeded = _GEN_368[stq_incoming_idx_0]; // @[lsu.scala:262:17, :269:32, :321:49] wire [31:0] _GEN_369 = {{stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_0}, {stq_can_execute_23}, {stq_can_execute_22}, {stq_can_execute_21}, {stq_can_execute_20}, {stq_can_execute_19}, {stq_can_execute_18}, {stq_can_execute_17}, {stq_can_execute_16}, {stq_can_execute_15}, {stq_can_execute_14}, {stq_can_execute_13}, {stq_can_execute_12}, {stq_can_execute_11}, {stq_can_execute_10}, {stq_can_execute_9}, {stq_can_execute_8}, {stq_can_execute_7}, {stq_can_execute_6}, {stq_can_execute_5}, {stq_can_execute_4}, {stq_can_execute_3}, {stq_can_execute_2}, {stq_can_execute_1}, {stq_can_execute_0}}; // @[lsu.scala:258:32, :270:32] assign stq_incoming_e_e_bits_can_execute = _GEN_369[stq_incoming_idx_0]; // @[lsu.scala:262:17, :270:32, :321:49] wire [31:0] _GEN_370 = {{stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_0}, {stq_cleared_23}, {stq_cleared_22}, {stq_cleared_21}, {stq_cleared_20}, {stq_cleared_19}, {stq_cleared_18}, {stq_cleared_17}, {stq_cleared_16}, {stq_cleared_15}, {stq_cleared_14}, {stq_cleared_13}, {stq_cleared_12}, {stq_cleared_11}, {stq_cleared_10}, {stq_cleared_9}, {stq_cleared_8}, {stq_cleared_7}, {stq_cleared_6}, {stq_cleared_5}, {stq_cleared_4}, {stq_cleared_3}, {stq_cleared_2}, {stq_cleared_1}, {stq_cleared_0}}; // @[lsu.scala:259:32, :271:32] assign stq_incoming_e_e_bits_cleared = _GEN_370[stq_incoming_idx_0]; // @[lsu.scala:262:17, :271:32, :321:49] wire [31:0][63:0] _GEN_371 = {{stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_0}, {stq_debug_wb_data_23}, {stq_debug_wb_data_22}, {stq_debug_wb_data_21}, {stq_debug_wb_data_20}, {stq_debug_wb_data_19}, {stq_debug_wb_data_18}, {stq_debug_wb_data_17}, {stq_debug_wb_data_16}, {stq_debug_wb_data_15}, {stq_debug_wb_data_14}, {stq_debug_wb_data_13}, {stq_debug_wb_data_12}, {stq_debug_wb_data_11}, {stq_debug_wb_data_10}, {stq_debug_wb_data_9}, {stq_debug_wb_data_8}, {stq_debug_wb_data_7}, {stq_debug_wb_data_6}, {stq_debug_wb_data_5}, {stq_debug_wb_data_4}, {stq_debug_wb_data_3}, {stq_debug_wb_data_2}, {stq_debug_wb_data_1}, {stq_debug_wb_data_0}}; // @[lsu.scala:260:32, :272:32] assign stq_incoming_e_e_bits_debug_wb_data = _GEN_371[stq_incoming_idx_0]; // @[lsu.scala:262:17, :272:32, :321:49] wire stq_incoming_e_0_valid = _stq_incoming_e_WIRE_valid; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_inst = _stq_incoming_e_WIRE_bits_uop_inst; // @[lsu.scala:321:49, :504:48] wire [31:0] stq_incoming_e_0_bits_uop_debug_inst = _stq_incoming_e_WIRE_bits_uop_debug_inst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rvc = _stq_incoming_e_WIRE_bits_uop_is_rvc; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_uop_debug_pc = _stq_incoming_e_WIRE_bits_uop_debug_pc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_0 = _stq_incoming_e_WIRE_bits_uop_iq_type_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_1 = _stq_incoming_e_WIRE_bits_uop_iq_type_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_2 = _stq_incoming_e_WIRE_bits_uop_iq_type_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iq_type_3 = _stq_incoming_e_WIRE_bits_uop_iq_type_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_0 = _stq_incoming_e_WIRE_bits_uop_fu_code_0; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_1 = _stq_incoming_e_WIRE_bits_uop_fu_code_1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_2 = _stq_incoming_e_WIRE_bits_uop_fu_code_2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_3 = _stq_incoming_e_WIRE_bits_uop_fu_code_3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_4 = _stq_incoming_e_WIRE_bits_uop_fu_code_4; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_5 = _stq_incoming_e_WIRE_bits_uop_fu_code_5; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_6 = _stq_incoming_e_WIRE_bits_uop_fu_code_6; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_7 = _stq_incoming_e_WIRE_bits_uop_fu_code_7; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_8 = _stq_incoming_e_WIRE_bits_uop_fu_code_8; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fu_code_9 = _stq_incoming_e_WIRE_bits_uop_fu_code_9; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued = _stq_incoming_e_WIRE_bits_uop_iw_issued; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_agen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_issued_partial_dgen = _stq_incoming_e_WIRE_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_iw_p1_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_iw_p2_speculative_child = _stq_incoming_e_WIRE_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p1_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p2_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_iw_p3_bypass_hint = _stq_incoming_e_WIRE_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_dis_col_sel = _stq_incoming_e_WIRE_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :504:48] wire [15:0] stq_incoming_e_0_bits_uop_br_mask = _stq_incoming_e_WIRE_bits_uop_br_mask; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_tag = _stq_incoming_e_WIRE_bits_uop_br_tag; // @[lsu.scala:321:49, :504:48] wire [3:0] stq_incoming_e_0_bits_uop_br_type = _stq_incoming_e_WIRE_bits_uop_br_type; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfb = _stq_incoming_e_WIRE_bits_uop_is_sfb; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fence = _stq_incoming_e_WIRE_bits_uop_is_fence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_fencei = _stq_incoming_e_WIRE_bits_uop_is_fencei; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sfence = _stq_incoming_e_WIRE_bits_uop_is_sfence; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_amo = _stq_incoming_e_WIRE_bits_uop_is_amo; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_eret = _stq_incoming_e_WIRE_bits_uop_is_eret; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_sys_pc2epc = _stq_incoming_e_WIRE_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_rocc = _stq_incoming_e_WIRE_bits_uop_is_rocc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_mov = _stq_incoming_e_WIRE_bits_uop_is_mov; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ftq_idx = _stq_incoming_e_WIRE_bits_uop_ftq_idx; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_edge_inst = _stq_incoming_e_WIRE_bits_uop_edge_inst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_pc_lob = _stq_incoming_e_WIRE_bits_uop_pc_lob; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_taken = _stq_incoming_e_WIRE_bits_uop_taken; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_imm_rename = _stq_incoming_e_WIRE_bits_uop_imm_rename; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_imm_sel = _stq_incoming_e_WIRE_bits_uop_imm_sel; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_pimm = _stq_incoming_e_WIRE_bits_uop_pimm; // @[lsu.scala:321:49, :504:48] wire [19:0] stq_incoming_e_0_bits_uop_imm_packed = _stq_incoming_e_WIRE_bits_uop_imm_packed; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_op1_sel = _stq_incoming_e_WIRE_bits_uop_op1_sel; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_op2_sel = _stq_incoming_e_WIRE_bits_uop_op2_sel; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ldst = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wen = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren1 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren2 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_ren3 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap12 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_swap23 = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fromint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_toint = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_fma = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_div = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_sqrt = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_wflags = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_ctrl_vec = _stq_incoming_e_WIRE_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_rob_idx = _stq_incoming_e_WIRE_bits_uop_rob_idx; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ldq_idx = _stq_incoming_e_WIRE_bits_uop_ldq_idx; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_stq_idx = _stq_incoming_e_WIRE_bits_uop_stq_idx; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_rxq_idx = _stq_incoming_e_WIRE_bits_uop_rxq_idx; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_pdst = _stq_incoming_e_WIRE_bits_uop_pdst; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs1 = _stq_incoming_e_WIRE_bits_uop_prs1; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs2 = _stq_incoming_e_WIRE_bits_uop_prs2; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_prs3 = _stq_incoming_e_WIRE_bits_uop_prs3; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_ppred = _stq_incoming_e_WIRE_bits_uop_ppred; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs1_busy = _stq_incoming_e_WIRE_bits_uop_prs1_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs2_busy = _stq_incoming_e_WIRE_bits_uop_prs2_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_prs3_busy = _stq_incoming_e_WIRE_bits_uop_prs3_busy; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ppred_busy = _stq_incoming_e_WIRE_bits_uop_ppred_busy; // @[lsu.scala:321:49, :504:48] wire [6:0] stq_incoming_e_0_bits_uop_stale_pdst = _stq_incoming_e_WIRE_bits_uop_stale_pdst; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_exception = _stq_incoming_e_WIRE_bits_uop_exception; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_uop_exc_cause = _stq_incoming_e_WIRE_bits_uop_exc_cause; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_mem_cmd = _stq_incoming_e_WIRE_bits_uop_mem_cmd; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_mem_size = _stq_incoming_e_WIRE_bits_uop_mem_size; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_mem_signed = _stq_incoming_e_WIRE_bits_uop_mem_signed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_ldq = _stq_incoming_e_WIRE_bits_uop_uses_ldq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_uses_stq = _stq_incoming_e_WIRE_bits_uop_uses_stq; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_is_unique = _stq_incoming_e_WIRE_bits_uop_is_unique; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_flush_on_commit = _stq_incoming_e_WIRE_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_csr_cmd = _stq_incoming_e_WIRE_bits_uop_csr_cmd; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_ldst_is_rs1 = _stq_incoming_e_WIRE_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_ldst = _stq_incoming_e_WIRE_bits_uop_ldst; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs1 = _stq_incoming_e_WIRE_bits_uop_lrs1; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs2 = _stq_incoming_e_WIRE_bits_uop_lrs2; // @[lsu.scala:321:49, :504:48] wire [5:0] stq_incoming_e_0_bits_uop_lrs3 = _stq_incoming_e_WIRE_bits_uop_lrs3; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_dst_rtype = _stq_incoming_e_WIRE_bits_uop_dst_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs1_rtype = _stq_incoming_e_WIRE_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_lrs2_rtype = _stq_incoming_e_WIRE_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_frs3_en = _stq_incoming_e_WIRE_bits_uop_frs3_en; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fcn_dw = _stq_incoming_e_WIRE_bits_uop_fcn_dw; // @[lsu.scala:321:49, :504:48] wire [4:0] stq_incoming_e_0_bits_uop_fcn_op = _stq_incoming_e_WIRE_bits_uop_fcn_op; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_fp_val = _stq_incoming_e_WIRE_bits_uop_fp_val; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_fp_rm = _stq_incoming_e_WIRE_bits_uop_fp_rm; // @[lsu.scala:321:49, :504:48] wire [1:0] stq_incoming_e_0_bits_uop_fp_typ = _stq_incoming_e_WIRE_bits_uop_fp_typ; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_pf_if = _stq_incoming_e_WIRE_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ae_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_xcpt_ma_if = _stq_incoming_e_WIRE_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_debug_if = _stq_incoming_e_WIRE_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_uop_bp_xcpt_if = _stq_incoming_e_WIRE_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_fsrc = _stq_incoming_e_WIRE_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :504:48] wire [2:0] stq_incoming_e_0_bits_uop_debug_tsrc = _stq_incoming_e_WIRE_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_valid = _stq_incoming_e_WIRE_bits_addr_valid; // @[lsu.scala:321:49, :504:48] wire [39:0] stq_incoming_e_0_bits_addr_bits = _stq_incoming_e_WIRE_bits_addr_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_addr_is_virtual = _stq_incoming_e_WIRE_bits_addr_is_virtual; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_data_valid = _stq_incoming_e_WIRE_bits_data_valid; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_data_bits = _stq_incoming_e_WIRE_bits_data_bits; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_committed = _stq_incoming_e_WIRE_bits_committed; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_succeeded = _stq_incoming_e_WIRE_bits_succeeded; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_can_execute = _stq_incoming_e_WIRE_bits_can_execute; // @[lsu.scala:321:49, :504:48] wire stq_incoming_e_0_bits_cleared = _stq_incoming_e_WIRE_bits_cleared; // @[lsu.scala:321:49, :504:48] wire [63:0] stq_incoming_e_0_bits_debug_wb_data = _stq_incoming_e_WIRE_bits_debug_wb_data; // @[lsu.scala:321:49, :504:48] wire [31:0] mem_stq_incoming_e_out_bits_uop_inst = stq_incoming_e_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_incoming_e_out_bits_uop_debug_inst = stq_incoming_e_0_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rvc = stq_incoming_e_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_uop_debug_pc = stq_incoming_e_0_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_0 = stq_incoming_e_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_1 = stq_incoming_e_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_2 = stq_incoming_e_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iq_type_3 = stq_incoming_e_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_0 = stq_incoming_e_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_1 = stq_incoming_e_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_2 = stq_incoming_e_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_3 = stq_incoming_e_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_4 = stq_incoming_e_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_5 = stq_incoming_e_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_6 = stq_incoming_e_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_7 = stq_incoming_e_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_8 = stq_incoming_e_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fu_code_9 = stq_incoming_e_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued = stq_incoming_e_0_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen = stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen = stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child = stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child = stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint = stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint = stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint = stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_dis_col_sel = stq_incoming_e_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_tag = stq_incoming_e_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_incoming_e_out_bits_uop_br_type = stq_incoming_e_0_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfb = stq_incoming_e_0_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fence = stq_incoming_e_0_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_fencei = stq_incoming_e_0_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sfence = stq_incoming_e_0_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_amo = stq_incoming_e_0_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_eret = stq_incoming_e_0_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc = stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_rocc = stq_incoming_e_0_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_mov = stq_incoming_e_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ftq_idx = stq_incoming_e_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_edge_inst = stq_incoming_e_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_pc_lob = stq_incoming_e_0_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_taken = stq_incoming_e_0_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_imm_rename = stq_incoming_e_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_imm_sel = stq_incoming_e_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_pimm = stq_incoming_e_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_incoming_e_out_bits_uop_imm_packed = stq_incoming_e_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_op1_sel = stq_incoming_e_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_op2_sel = stq_incoming_e_0_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst = stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen = stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1 = stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2 = stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3 = stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12 = stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23 = stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut = stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint = stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint = stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe = stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma = stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_div = stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt = stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags = stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec = stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_rob_idx = stq_incoming_e_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ldq_idx = stq_incoming_e_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_stq_idx = stq_incoming_e_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_rxq_idx = stq_incoming_e_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_pdst = stq_incoming_e_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs1 = stq_incoming_e_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs2 = stq_incoming_e_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_prs3 = stq_incoming_e_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_ppred = stq_incoming_e_0_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs1_busy = stq_incoming_e_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs2_busy = stq_incoming_e_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_prs3_busy = stq_incoming_e_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ppred_busy = stq_incoming_e_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_incoming_e_out_bits_uop_stale_pdst = stq_incoming_e_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_exception = stq_incoming_e_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_uop_exc_cause = stq_incoming_e_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_mem_cmd = stq_incoming_e_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_mem_size = stq_incoming_e_0_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_mem_signed = stq_incoming_e_0_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_ldq = stq_incoming_e_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_uses_stq = stq_incoming_e_0_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_is_unique = stq_incoming_e_0_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_flush_on_commit = stq_incoming_e_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_csr_cmd = stq_incoming_e_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_ldst_is_rs1 = stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_ldst = stq_incoming_e_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs1 = stq_incoming_e_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs2 = stq_incoming_e_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_incoming_e_out_bits_uop_lrs3 = stq_incoming_e_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_dst_rtype = stq_incoming_e_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs1_rtype = stq_incoming_e_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_lrs2_rtype = stq_incoming_e_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_frs3_en = stq_incoming_e_0_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fcn_dw = stq_incoming_e_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_incoming_e_out_bits_uop_fcn_op = stq_incoming_e_0_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_fp_val = stq_incoming_e_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_fp_rm = stq_incoming_e_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_incoming_e_out_bits_uop_fp_typ = stq_incoming_e_0_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_pf_if = stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ae_if = stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_xcpt_ma_if = stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_debug_if = stq_incoming_e_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_uop_bp_xcpt_if = stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_fsrc = stq_incoming_e_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_incoming_e_out_bits_uop_debug_tsrc = stq_incoming_e_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_valid = stq_incoming_e_0_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_incoming_e_out_bits_addr_bits = stq_incoming_e_0_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_addr_is_virtual = stq_incoming_e_0_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_data_valid = stq_incoming_e_0_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_data_bits = stq_incoming_e_0_bits_data_bits; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_committed = stq_incoming_e_0_bits_committed; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_succeeded = stq_incoming_e_0_bits_succeeded; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_can_execute = stq_incoming_e_0_bits_can_execute; // @[util.scala:114:23] wire mem_stq_incoming_e_out_bits_cleared = stq_incoming_e_0_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_incoming_e_out_bits_debug_wb_data = stq_incoming_e_0_bits_debug_wb_data; // @[util.scala:114:23] wire ldq_wakeup_idx_block = block_load_mask_0 | p1_block_load_mask_0; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T = ~ldq_executed_0; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_1 = ldq_addr_0_valid & _ldq_wakeup_idx_T; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_2 = ~ldq_succeeded_0; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_3 = _ldq_wakeup_idx_T_1 & _ldq_wakeup_idx_T_2; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_4 = ~ldq_addr_is_virtual_0; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_5 = _ldq_wakeup_idx_T_3 & _ldq_wakeup_idx_T_4; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_6 = ~ldq_wakeup_idx_block; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_7 = _ldq_wakeup_idx_T_5 & _ldq_wakeup_idx_T_6; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_1 = block_load_mask_1 | p1_block_load_mask_1; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_8 = ~ldq_executed_1; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_9 = ldq_addr_1_valid & _ldq_wakeup_idx_T_8; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_10 = ~ldq_succeeded_1; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_11 = _ldq_wakeup_idx_T_9 & _ldq_wakeup_idx_T_10; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_12 = ~ldq_addr_is_virtual_1; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_13 = _ldq_wakeup_idx_T_11 & _ldq_wakeup_idx_T_12; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_14 = ~ldq_wakeup_idx_block_1; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_15 = _ldq_wakeup_idx_T_13 & _ldq_wakeup_idx_T_14; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_2 = block_load_mask_2 | p1_block_load_mask_2; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_16 = ~ldq_executed_2; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_17 = ldq_addr_2_valid & _ldq_wakeup_idx_T_16; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_18 = ~ldq_succeeded_2; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_19 = _ldq_wakeup_idx_T_17 & _ldq_wakeup_idx_T_18; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_20 = ~ldq_addr_is_virtual_2; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_21 = _ldq_wakeup_idx_T_19 & _ldq_wakeup_idx_T_20; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_22 = ~ldq_wakeup_idx_block_2; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_23 = _ldq_wakeup_idx_T_21 & _ldq_wakeup_idx_T_22; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_3 = block_load_mask_3 | p1_block_load_mask_3; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_24 = ~ldq_executed_3; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_25 = ldq_addr_3_valid & _ldq_wakeup_idx_T_24; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_26 = ~ldq_succeeded_3; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_27 = _ldq_wakeup_idx_T_25 & _ldq_wakeup_idx_T_26; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_28 = ~ldq_addr_is_virtual_3; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_29 = _ldq_wakeup_idx_T_27 & _ldq_wakeup_idx_T_28; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_30 = ~ldq_wakeup_idx_block_3; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_31 = _ldq_wakeup_idx_T_29 & _ldq_wakeup_idx_T_30; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_4 = block_load_mask_4 | p1_block_load_mask_4; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_32 = ~ldq_executed_4; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_33 = ldq_addr_4_valid & _ldq_wakeup_idx_T_32; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_34 = ~ldq_succeeded_4; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_35 = _ldq_wakeup_idx_T_33 & _ldq_wakeup_idx_T_34; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_36 = ~ldq_addr_is_virtual_4; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_37 = _ldq_wakeup_idx_T_35 & _ldq_wakeup_idx_T_36; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_38 = ~ldq_wakeup_idx_block_4; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_39 = _ldq_wakeup_idx_T_37 & _ldq_wakeup_idx_T_38; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_5 = block_load_mask_5 | p1_block_load_mask_5; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_40 = ~ldq_executed_5; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_41 = ldq_addr_5_valid & _ldq_wakeup_idx_T_40; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_42 = ~ldq_succeeded_5; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_43 = _ldq_wakeup_idx_T_41 & _ldq_wakeup_idx_T_42; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_44 = ~ldq_addr_is_virtual_5; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_45 = _ldq_wakeup_idx_T_43 & _ldq_wakeup_idx_T_44; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_46 = ~ldq_wakeup_idx_block_5; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_47 = _ldq_wakeup_idx_T_45 & _ldq_wakeup_idx_T_46; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_6 = block_load_mask_6 | p1_block_load_mask_6; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_48 = ~ldq_executed_6; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_49 = ldq_addr_6_valid & _ldq_wakeup_idx_T_48; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_50 = ~ldq_succeeded_6; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_51 = _ldq_wakeup_idx_T_49 & _ldq_wakeup_idx_T_50; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_52 = ~ldq_addr_is_virtual_6; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_53 = _ldq_wakeup_idx_T_51 & _ldq_wakeup_idx_T_52; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_54 = ~ldq_wakeup_idx_block_6; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_55 = _ldq_wakeup_idx_T_53 & _ldq_wakeup_idx_T_54; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_7 = block_load_mask_7 | p1_block_load_mask_7; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_56 = ~ldq_executed_7; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_57 = ldq_addr_7_valid & _ldq_wakeup_idx_T_56; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_58 = ~ldq_succeeded_7; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_59 = _ldq_wakeup_idx_T_57 & _ldq_wakeup_idx_T_58; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_60 = ~ldq_addr_is_virtual_7; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_61 = _ldq_wakeup_idx_T_59 & _ldq_wakeup_idx_T_60; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_62 = ~ldq_wakeup_idx_block_7; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_63 = _ldq_wakeup_idx_T_61 & _ldq_wakeup_idx_T_62; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_8 = block_load_mask_8 | p1_block_load_mask_8; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_64 = ~ldq_executed_8; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_65 = ldq_addr_8_valid & _ldq_wakeup_idx_T_64; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_66 = ~ldq_succeeded_8; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_67 = _ldq_wakeup_idx_T_65 & _ldq_wakeup_idx_T_66; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_68 = ~ldq_addr_is_virtual_8; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_69 = _ldq_wakeup_idx_T_67 & _ldq_wakeup_idx_T_68; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_70 = ~ldq_wakeup_idx_block_8; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_71 = _ldq_wakeup_idx_T_69 & _ldq_wakeup_idx_T_70; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_9 = block_load_mask_9 | p1_block_load_mask_9; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_72 = ~ldq_executed_9; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_73 = ldq_addr_9_valid & _ldq_wakeup_idx_T_72; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_74 = ~ldq_succeeded_9; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_75 = _ldq_wakeup_idx_T_73 & _ldq_wakeup_idx_T_74; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_76 = ~ldq_addr_is_virtual_9; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_77 = _ldq_wakeup_idx_T_75 & _ldq_wakeup_idx_T_76; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_78 = ~ldq_wakeup_idx_block_9; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_79 = _ldq_wakeup_idx_T_77 & _ldq_wakeup_idx_T_78; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_10 = block_load_mask_10 | p1_block_load_mask_10; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_80 = ~ldq_executed_10; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_81 = ldq_addr_10_valid & _ldq_wakeup_idx_T_80; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_82 = ~ldq_succeeded_10; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_83 = _ldq_wakeup_idx_T_81 & _ldq_wakeup_idx_T_82; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_84 = ~ldq_addr_is_virtual_10; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_85 = _ldq_wakeup_idx_T_83 & _ldq_wakeup_idx_T_84; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_86 = ~ldq_wakeup_idx_block_10; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_87 = _ldq_wakeup_idx_T_85 & _ldq_wakeup_idx_T_86; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_11 = block_load_mask_11 | p1_block_load_mask_11; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_88 = ~ldq_executed_11; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_89 = ldq_addr_11_valid & _ldq_wakeup_idx_T_88; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_90 = ~ldq_succeeded_11; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_91 = _ldq_wakeup_idx_T_89 & _ldq_wakeup_idx_T_90; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_92 = ~ldq_addr_is_virtual_11; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_93 = _ldq_wakeup_idx_T_91 & _ldq_wakeup_idx_T_92; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_94 = ~ldq_wakeup_idx_block_11; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_95 = _ldq_wakeup_idx_T_93 & _ldq_wakeup_idx_T_94; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_12 = block_load_mask_12 | p1_block_load_mask_12; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_96 = ~ldq_executed_12; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_97 = ldq_addr_12_valid & _ldq_wakeup_idx_T_96; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_98 = ~ldq_succeeded_12; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_99 = _ldq_wakeup_idx_T_97 & _ldq_wakeup_idx_T_98; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_100 = ~ldq_addr_is_virtual_12; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_101 = _ldq_wakeup_idx_T_99 & _ldq_wakeup_idx_T_100; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_102 = ~ldq_wakeup_idx_block_12; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_103 = _ldq_wakeup_idx_T_101 & _ldq_wakeup_idx_T_102; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_13 = block_load_mask_13 | p1_block_load_mask_13; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_104 = ~ldq_executed_13; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_105 = ldq_addr_13_valid & _ldq_wakeup_idx_T_104; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_106 = ~ldq_succeeded_13; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_107 = _ldq_wakeup_idx_T_105 & _ldq_wakeup_idx_T_106; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_108 = ~ldq_addr_is_virtual_13; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_109 = _ldq_wakeup_idx_T_107 & _ldq_wakeup_idx_T_108; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_110 = ~ldq_wakeup_idx_block_13; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_111 = _ldq_wakeup_idx_T_109 & _ldq_wakeup_idx_T_110; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_14 = block_load_mask_14 | p1_block_load_mask_14; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_112 = ~ldq_executed_14; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_113 = ldq_addr_14_valid & _ldq_wakeup_idx_T_112; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_114 = ~ldq_succeeded_14; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_115 = _ldq_wakeup_idx_T_113 & _ldq_wakeup_idx_T_114; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_116 = ~ldq_addr_is_virtual_14; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_117 = _ldq_wakeup_idx_T_115 & _ldq_wakeup_idx_T_116; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_118 = ~ldq_wakeup_idx_block_14; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_119 = _ldq_wakeup_idx_T_117 & _ldq_wakeup_idx_T_118; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_15 = block_load_mask_15 | p1_block_load_mask_15; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_120 = ~ldq_executed_15; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_121 = ldq_addr_15_valid & _ldq_wakeup_idx_T_120; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_122 = ~ldq_succeeded_15; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_123 = _ldq_wakeup_idx_T_121 & _ldq_wakeup_idx_T_122; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_124 = ~ldq_addr_is_virtual_15; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_125 = _ldq_wakeup_idx_T_123 & _ldq_wakeup_idx_T_124; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_126 = ~ldq_wakeup_idx_block_15; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_127 = _ldq_wakeup_idx_T_125 & _ldq_wakeup_idx_T_126; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_16 = block_load_mask_16 | p1_block_load_mask_16; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_128 = ~ldq_executed_16; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_129 = ldq_addr_16_valid & _ldq_wakeup_idx_T_128; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_130 = ~ldq_succeeded_16; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_131 = _ldq_wakeup_idx_T_129 & _ldq_wakeup_idx_T_130; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_132 = ~ldq_addr_is_virtual_16; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_133 = _ldq_wakeup_idx_T_131 & _ldq_wakeup_idx_T_132; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_134 = ~ldq_wakeup_idx_block_16; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_135 = _ldq_wakeup_idx_T_133 & _ldq_wakeup_idx_T_134; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_17 = block_load_mask_17 | p1_block_load_mask_17; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_136 = ~ldq_executed_17; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_137 = ldq_addr_17_valid & _ldq_wakeup_idx_T_136; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_138 = ~ldq_succeeded_17; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_139 = _ldq_wakeup_idx_T_137 & _ldq_wakeup_idx_T_138; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_140 = ~ldq_addr_is_virtual_17; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_141 = _ldq_wakeup_idx_T_139 & _ldq_wakeup_idx_T_140; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_142 = ~ldq_wakeup_idx_block_17; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_143 = _ldq_wakeup_idx_T_141 & _ldq_wakeup_idx_T_142; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_18 = block_load_mask_18 | p1_block_load_mask_18; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_144 = ~ldq_executed_18; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_145 = ldq_addr_18_valid & _ldq_wakeup_idx_T_144; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_146 = ~ldq_succeeded_18; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_147 = _ldq_wakeup_idx_T_145 & _ldq_wakeup_idx_T_146; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_148 = ~ldq_addr_is_virtual_18; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_149 = _ldq_wakeup_idx_T_147 & _ldq_wakeup_idx_T_148; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_150 = ~ldq_wakeup_idx_block_18; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_151 = _ldq_wakeup_idx_T_149 & _ldq_wakeup_idx_T_150; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_19 = block_load_mask_19 | p1_block_load_mask_19; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_152 = ~ldq_executed_19; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_153 = ldq_addr_19_valid & _ldq_wakeup_idx_T_152; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_154 = ~ldq_succeeded_19; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_155 = _ldq_wakeup_idx_T_153 & _ldq_wakeup_idx_T_154; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_156 = ~ldq_addr_is_virtual_19; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_157 = _ldq_wakeup_idx_T_155 & _ldq_wakeup_idx_T_156; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_158 = ~ldq_wakeup_idx_block_19; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_159 = _ldq_wakeup_idx_T_157 & _ldq_wakeup_idx_T_158; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_20 = block_load_mask_20 | p1_block_load_mask_20; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_160 = ~ldq_executed_20; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_161 = ldq_addr_20_valid & _ldq_wakeup_idx_T_160; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_162 = ~ldq_succeeded_20; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_163 = _ldq_wakeup_idx_T_161 & _ldq_wakeup_idx_T_162; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_164 = ~ldq_addr_is_virtual_20; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_165 = _ldq_wakeup_idx_T_163 & _ldq_wakeup_idx_T_164; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_166 = ~ldq_wakeup_idx_block_20; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_167 = _ldq_wakeup_idx_T_165 & _ldq_wakeup_idx_T_166; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_21 = block_load_mask_21 | p1_block_load_mask_21; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_168 = ~ldq_executed_21; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_169 = ldq_addr_21_valid & _ldq_wakeup_idx_T_168; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_170 = ~ldq_succeeded_21; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_171 = _ldq_wakeup_idx_T_169 & _ldq_wakeup_idx_T_170; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_172 = ~ldq_addr_is_virtual_21; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_173 = _ldq_wakeup_idx_T_171 & _ldq_wakeup_idx_T_172; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_174 = ~ldq_wakeup_idx_block_21; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_175 = _ldq_wakeup_idx_T_173 & _ldq_wakeup_idx_T_174; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_22 = block_load_mask_22 | p1_block_load_mask_22; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_176 = ~ldq_executed_22; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_177 = ldq_addr_22_valid & _ldq_wakeup_idx_T_176; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_178 = ~ldq_succeeded_22; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_179 = _ldq_wakeup_idx_T_177 & _ldq_wakeup_idx_T_178; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_180 = ~ldq_addr_is_virtual_22; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_181 = _ldq_wakeup_idx_T_179 & _ldq_wakeup_idx_T_180; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_182 = ~ldq_wakeup_idx_block_22; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_183 = _ldq_wakeup_idx_T_181 & _ldq_wakeup_idx_T_182; // @[lsu.scala:508:{64,91,94}] wire ldq_wakeup_idx_block_23 = block_load_mask_23 | p1_block_load_mask_23; // @[lsu.scala:488:36, :489:35, :507:36] wire _ldq_wakeup_idx_T_184 = ~ldq_executed_23; // @[lsu.scala:223:36, :508:26] wire _ldq_wakeup_idx_T_185 = ldq_addr_23_valid & _ldq_wakeup_idx_T_184; // @[lsu.scala:220:36, :508:{23,26}] wire _ldq_wakeup_idx_T_186 = ~ldq_succeeded_23; // @[lsu.scala:224:36, :508:46] wire _ldq_wakeup_idx_T_187 = _ldq_wakeup_idx_T_185 & _ldq_wakeup_idx_T_186; // @[lsu.scala:508:{23,43,46}] wire _ldq_wakeup_idx_T_188 = ~ldq_addr_is_virtual_23; // @[lsu.scala:221:36, :508:67] wire _ldq_wakeup_idx_T_189 = _ldq_wakeup_idx_T_187 & _ldq_wakeup_idx_T_188; // @[lsu.scala:508:{43,64,67}] wire _ldq_wakeup_idx_T_190 = ~ldq_wakeup_idx_block_23; // @[lsu.scala:507:36, :508:94] wire _ldq_wakeup_idx_T_191 = _ldq_wakeup_idx_T_189 & _ldq_wakeup_idx_T_190; // @[lsu.scala:508:{64,91,94}] wire _GEN_372 = ldq_head == 5'h0; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire _l_idx_temp_vec_T; // @[util.scala:352:72] assign _l_idx_temp_vec_T = _GEN_372; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_0 = _ldq_wakeup_idx_T_7 & _ldq_wakeup_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_373 = ldq_head < 5'h2; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire _l_idx_temp_vec_T_1; // @[util.scala:352:72] assign _l_idx_temp_vec_T_1 = _GEN_373; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_1 = _ldq_wakeup_idx_T_15 & _ldq_wakeup_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_374 = ldq_head < 5'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire _l_idx_temp_vec_T_2; // @[util.scala:352:72] assign _l_idx_temp_vec_T_2 = _GEN_374; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_2 = _ldq_wakeup_idx_T_23 & _ldq_wakeup_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_375 = ldq_head < 5'h4; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire _l_idx_temp_vec_T_3; // @[util.scala:352:72] assign _l_idx_temp_vec_T_3 = _GEN_375; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_3 = _ldq_wakeup_idx_T_31 & _ldq_wakeup_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_376 = ldq_head < 5'h5; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire _l_idx_temp_vec_T_4; // @[util.scala:352:72] assign _l_idx_temp_vec_T_4 = _GEN_376; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_4 = _ldq_wakeup_idx_T_39 & _ldq_wakeup_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_377 = ldq_head < 5'h6; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire _l_idx_temp_vec_T_5; // @[util.scala:352:72] assign _l_idx_temp_vec_T_5 = _GEN_377; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_5 = _ldq_wakeup_idx_T_47 & _ldq_wakeup_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_378 = ldq_head < 5'h7; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire _l_idx_temp_vec_T_6; // @[util.scala:352:72] assign _l_idx_temp_vec_T_6 = _GEN_378; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_6 = _ldq_wakeup_idx_T_55 & _ldq_wakeup_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _GEN_379 = ldq_head < 5'h8; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire _l_idx_temp_vec_T_7; // @[util.scala:352:72] assign _l_idx_temp_vec_T_7 = _GEN_379; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_7 = _ldq_wakeup_idx_T_63 & _ldq_wakeup_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_380 = ldq_head < 5'h9; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire _l_idx_temp_vec_T_8; // @[util.scala:352:72] assign _l_idx_temp_vec_T_8 = _GEN_380; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_8 = _ldq_wakeup_idx_T_71 & _ldq_wakeup_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_381 = ldq_head < 5'hA; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire _l_idx_temp_vec_T_9; // @[util.scala:352:72] assign _l_idx_temp_vec_T_9 = _GEN_381; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_9 = _ldq_wakeup_idx_T_79 & _ldq_wakeup_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_382 = ldq_head < 5'hB; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire _l_idx_temp_vec_T_10; // @[util.scala:352:72] assign _l_idx_temp_vec_T_10 = _GEN_382; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_10 = _ldq_wakeup_idx_T_87 & _ldq_wakeup_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_383 = ldq_head < 5'hC; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire _l_idx_temp_vec_T_11; // @[util.scala:352:72] assign _l_idx_temp_vec_T_11 = _GEN_383; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_11 = _ldq_wakeup_idx_T_95 & _ldq_wakeup_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_384 = ldq_head < 5'hD; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire _l_idx_temp_vec_T_12; // @[util.scala:352:72] assign _l_idx_temp_vec_T_12 = _GEN_384; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_12 = _ldq_wakeup_idx_T_103 & _ldq_wakeup_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_385 = ldq_head < 5'hE; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire _l_idx_temp_vec_T_13; // @[util.scala:352:72] assign _l_idx_temp_vec_T_13 = _GEN_385; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_13 = _ldq_wakeup_idx_T_111 & _ldq_wakeup_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_386 = ldq_head < 5'hF; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire _l_idx_temp_vec_T_14; // @[util.scala:352:72] assign _l_idx_temp_vec_T_14 = _GEN_386; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_14 = _ldq_wakeup_idx_T_119 & _ldq_wakeup_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _ldq_wakeup_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_15 = _ldq_wakeup_idx_T_127 & _ldq_wakeup_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _GEN_387 = ldq_head < 5'h11; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire _l_idx_temp_vec_T_16; // @[util.scala:352:72] assign _l_idx_temp_vec_T_16 = _GEN_387; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_16 = _ldq_wakeup_idx_T_135 & _ldq_wakeup_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _GEN_388 = ldq_head < 5'h12; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire _l_idx_temp_vec_T_17; // @[util.scala:352:72] assign _l_idx_temp_vec_T_17 = _GEN_388; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_17 = _ldq_wakeup_idx_T_143 & _ldq_wakeup_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _GEN_389 = ldq_head < 5'h13; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire _l_idx_temp_vec_T_18; // @[util.scala:352:72] assign _l_idx_temp_vec_T_18 = _GEN_389; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_18 = _ldq_wakeup_idx_T_151 & _ldq_wakeup_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _GEN_390 = ldq_head < 5'h14; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire _l_idx_temp_vec_T_19; // @[util.scala:352:72] assign _l_idx_temp_vec_T_19 = _GEN_390; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_19 = _ldq_wakeup_idx_T_159 & _ldq_wakeup_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _GEN_391 = ldq_head < 5'h15; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire _l_idx_temp_vec_T_20; // @[util.scala:352:72] assign _l_idx_temp_vec_T_20 = _GEN_391; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_20 = _ldq_wakeup_idx_T_167 & _ldq_wakeup_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _GEN_392 = ldq_head < 5'h16; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire _l_idx_temp_vec_T_21; // @[util.scala:352:72] assign _l_idx_temp_vec_T_21 = _GEN_392; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_21 = _ldq_wakeup_idx_T_175 & _ldq_wakeup_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _GEN_393 = ldq_head < 5'h17; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire _l_idx_temp_vec_T_22; // @[util.scala:352:72] assign _l_idx_temp_vec_T_22 = _GEN_393; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_22 = _ldq_wakeup_idx_T_183 & _ldq_wakeup_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _GEN_394 = ldq_head[4:3] != 2'h3; // @[util.scala:352:72] wire _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:352:72] assign _ldq_wakeup_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire _ldq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:72] assign _ldq_enq_retry_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire _l_idx_temp_vec_T_23; // @[util.scala:352:72] assign _l_idx_temp_vec_T_23 = _GEN_394; // @[util.scala:352:72] wire ldq_wakeup_idx_temp_vec_23 = _ldq_wakeup_idx_T_191 & _ldq_wakeup_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _ldq_wakeup_idx_idx_T = {5'h1B, ~_ldq_wakeup_idx_T_183}; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_1 = _ldq_wakeup_idx_T_175 ? 6'h35 : _ldq_wakeup_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_2 = _ldq_wakeup_idx_T_167 ? 6'h34 : _ldq_wakeup_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_3 = _ldq_wakeup_idx_T_159 ? 6'h33 : _ldq_wakeup_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_4 = _ldq_wakeup_idx_T_151 ? 6'h32 : _ldq_wakeup_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_5 = _ldq_wakeup_idx_T_143 ? 6'h31 : _ldq_wakeup_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_6 = _ldq_wakeup_idx_T_135 ? 6'h30 : _ldq_wakeup_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_7 = _ldq_wakeup_idx_T_127 ? 6'h2F : _ldq_wakeup_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_8 = _ldq_wakeup_idx_T_119 ? 6'h2E : _ldq_wakeup_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_9 = _ldq_wakeup_idx_T_111 ? 6'h2D : _ldq_wakeup_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_10 = _ldq_wakeup_idx_T_103 ? 6'h2C : _ldq_wakeup_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_11 = _ldq_wakeup_idx_T_95 ? 6'h2B : _ldq_wakeup_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_12 = _ldq_wakeup_idx_T_87 ? 6'h2A : _ldq_wakeup_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_13 = _ldq_wakeup_idx_T_79 ? 6'h29 : _ldq_wakeup_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_14 = _ldq_wakeup_idx_T_71 ? 6'h28 : _ldq_wakeup_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_15 = _ldq_wakeup_idx_T_63 ? 6'h27 : _ldq_wakeup_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_16 = _ldq_wakeup_idx_T_55 ? 6'h26 : _ldq_wakeup_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_17 = _ldq_wakeup_idx_T_47 ? 6'h25 : _ldq_wakeup_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_18 = _ldq_wakeup_idx_T_39 ? 6'h24 : _ldq_wakeup_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_19 = _ldq_wakeup_idx_T_31 ? 6'h23 : _ldq_wakeup_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_20 = _ldq_wakeup_idx_T_23 ? 6'h22 : _ldq_wakeup_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_21 = _ldq_wakeup_idx_T_15 ? 6'h21 : _ldq_wakeup_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_22 = _ldq_wakeup_idx_T_7 ? 6'h20 : _ldq_wakeup_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_23 = _ldq_wakeup_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_24 = _ldq_wakeup_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_25 = _ldq_wakeup_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_26 = _ldq_wakeup_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_27 = _ldq_wakeup_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_28 = _ldq_wakeup_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_29 = _ldq_wakeup_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_30 = _ldq_wakeup_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_31 = ldq_wakeup_idx_temp_vec_23 ? 6'h17 : _ldq_wakeup_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_32 = ldq_wakeup_idx_temp_vec_22 ? 6'h16 : _ldq_wakeup_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_33 = ldq_wakeup_idx_temp_vec_21 ? 6'h15 : _ldq_wakeup_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_34 = ldq_wakeup_idx_temp_vec_20 ? 6'h14 : _ldq_wakeup_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_35 = ldq_wakeup_idx_temp_vec_19 ? 6'h13 : _ldq_wakeup_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_36 = ldq_wakeup_idx_temp_vec_18 ? 6'h12 : _ldq_wakeup_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_37 = ldq_wakeup_idx_temp_vec_17 ? 6'h11 : _ldq_wakeup_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_38 = ldq_wakeup_idx_temp_vec_16 ? 6'h10 : _ldq_wakeup_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_39 = ldq_wakeup_idx_temp_vec_15 ? 6'hF : _ldq_wakeup_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_40 = ldq_wakeup_idx_temp_vec_14 ? 6'hE : _ldq_wakeup_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_41 = ldq_wakeup_idx_temp_vec_13 ? 6'hD : _ldq_wakeup_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_42 = ldq_wakeup_idx_temp_vec_12 ? 6'hC : _ldq_wakeup_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_43 = ldq_wakeup_idx_temp_vec_11 ? 6'hB : _ldq_wakeup_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_44 = ldq_wakeup_idx_temp_vec_10 ? 6'hA : _ldq_wakeup_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_45 = ldq_wakeup_idx_temp_vec_9 ? 6'h9 : _ldq_wakeup_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_46 = ldq_wakeup_idx_temp_vec_8 ? 6'h8 : _ldq_wakeup_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_47 = ldq_wakeup_idx_temp_vec_7 ? 6'h7 : _ldq_wakeup_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_48 = ldq_wakeup_idx_temp_vec_6 ? 6'h6 : _ldq_wakeup_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_49 = ldq_wakeup_idx_temp_vec_5 ? 6'h5 : _ldq_wakeup_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_50 = ldq_wakeup_idx_temp_vec_4 ? 6'h4 : _ldq_wakeup_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_51 = ldq_wakeup_idx_temp_vec_3 ? 6'h3 : _ldq_wakeup_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_52 = ldq_wakeup_idx_temp_vec_2 ? 6'h2 : _ldq_wakeup_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_wakeup_idx_idx_T_53 = ldq_wakeup_idx_temp_vec_1 ? 6'h1 : _ldq_wakeup_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_wakeup_idx_idx = ldq_wakeup_idx_temp_vec_0 ? 6'h0 : _ldq_wakeup_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_wakeup_idx_T_192 = ldq_wakeup_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_valid_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_uop_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_executed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_succeeded_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_order_fail_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_observed_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_st_dep_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_forward_std_val_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _ldq_wakeup_e_e_bits_debug_wb_data_T = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _can_fire_load_wakeup_T_9 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire [4:0] _can_fire_load_wakeup_T_13 = ldq_wakeup_idx; // @[lsu.scala:506:31] wire ldq_wakeup_e_valid = ldq_wakeup_e_e_valid; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_inst = ldq_wakeup_e_e_bits_uop_inst; // @[lsu.scala:233:17, :510:32] wire [31:0] ldq_wakeup_e_bits_uop_debug_inst = ldq_wakeup_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rvc = ldq_wakeup_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_uop_debug_pc = ldq_wakeup_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_0 = ldq_wakeup_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_1 = ldq_wakeup_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_2 = ldq_wakeup_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iq_type_3 = ldq_wakeup_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_0 = ldq_wakeup_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_1 = ldq_wakeup_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_2 = ldq_wakeup_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_3 = ldq_wakeup_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_4 = ldq_wakeup_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_5 = ldq_wakeup_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_6 = ldq_wakeup_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_7 = ldq_wakeup_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_8 = ldq_wakeup_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fu_code_9 = ldq_wakeup_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued = ldq_wakeup_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_dis_col_sel = ldq_wakeup_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :510:32] wire [15:0] ldq_wakeup_e_bits_uop_br_mask = ldq_wakeup_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_tag = ldq_wakeup_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :510:32] wire [3:0] ldq_wakeup_e_bits_uop_br_type = ldq_wakeup_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfb = ldq_wakeup_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fence = ldq_wakeup_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_fencei = ldq_wakeup_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sfence = ldq_wakeup_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_amo = ldq_wakeup_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_eret = ldq_wakeup_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_sys_pc2epc = ldq_wakeup_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_rocc = ldq_wakeup_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_mov = ldq_wakeup_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ftq_idx = ldq_wakeup_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_edge_inst = ldq_wakeup_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_pc_lob = ldq_wakeup_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_taken = ldq_wakeup_e_e_bits_uop_taken; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_imm_rename = ldq_wakeup_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_imm_sel = ldq_wakeup_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_pimm = ldq_wakeup_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :510:32] wire [19:0] ldq_wakeup_e_bits_uop_imm_packed = ldq_wakeup_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_op1_sel = ldq_wakeup_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_op2_sel = ldq_wakeup_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wen = ldq_wakeup_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_toint = ldq_wakeup_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_fma = ldq_wakeup_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_div = ldq_wakeup_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_ctrl_vec = ldq_wakeup_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_rob_idx = ldq_wakeup_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ldq_idx = ldq_wakeup_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_stq_idx = ldq_wakeup_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_rxq_idx = ldq_wakeup_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_pdst = ldq_wakeup_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs1 = ldq_wakeup_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs2 = ldq_wakeup_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_prs3 = ldq_wakeup_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_ppred = ldq_wakeup_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs1_busy = ldq_wakeup_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs2_busy = ldq_wakeup_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_prs3_busy = ldq_wakeup_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ppred_busy = ldq_wakeup_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :510:32] wire [6:0] ldq_wakeup_e_bits_uop_stale_pdst = ldq_wakeup_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_exception = ldq_wakeup_e_e_bits_uop_exception; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_uop_exc_cause = ldq_wakeup_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_mem_cmd = ldq_wakeup_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_mem_size = ldq_wakeup_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_mem_signed = ldq_wakeup_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_ldq = ldq_wakeup_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_uses_stq = ldq_wakeup_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_is_unique = ldq_wakeup_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_flush_on_commit = ldq_wakeup_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_csr_cmd = ldq_wakeup_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_ldst_is_rs1 = ldq_wakeup_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_ldst = ldq_wakeup_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs1 = ldq_wakeup_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs2 = ldq_wakeup_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :510:32] wire [5:0] ldq_wakeup_e_bits_uop_lrs3 = ldq_wakeup_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_dst_rtype = ldq_wakeup_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs1_rtype = ldq_wakeup_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_lrs2_rtype = ldq_wakeup_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_frs3_en = ldq_wakeup_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fcn_dw = ldq_wakeup_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_uop_fcn_op = ldq_wakeup_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_fp_val = ldq_wakeup_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_fp_rm = ldq_wakeup_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :510:32] wire [1:0] ldq_wakeup_e_bits_uop_fp_typ = ldq_wakeup_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_pf_if = ldq_wakeup_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ae_if = ldq_wakeup_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_xcpt_ma_if = ldq_wakeup_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_debug_if = ldq_wakeup_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_uop_bp_xcpt_if = ldq_wakeup_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_fsrc = ldq_wakeup_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :510:32] wire [2:0] ldq_wakeup_e_bits_uop_debug_tsrc = ldq_wakeup_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_valid = ldq_wakeup_e_e_bits_addr_valid; // @[lsu.scala:233:17, :510:32] wire [39:0] ldq_wakeup_e_bits_addr_bits = ldq_wakeup_e_e_bits_addr_bits; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_virtual = ldq_wakeup_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_addr_is_uncacheable = ldq_wakeup_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_executed = ldq_wakeup_e_e_bits_executed; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_succeeded = ldq_wakeup_e_e_bits_succeeded; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_order_fail = ldq_wakeup_e_e_bits_order_fail; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_observed = ldq_wakeup_e_e_bits_observed; // @[lsu.scala:233:17, :510:32] wire [23:0] ldq_wakeup_e_bits_st_dep_mask = ldq_wakeup_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :510:32] wire [7:0] ldq_wakeup_e_bits_ld_byte_mask = ldq_wakeup_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :510:32] wire ldq_wakeup_e_bits_forward_std_val = ldq_wakeup_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :510:32] wire [4:0] ldq_wakeup_e_bits_forward_stq_idx = ldq_wakeup_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :510:32] wire [63:0] ldq_wakeup_e_bits_debug_wb_data = ldq_wakeup_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :510:32] wire [4:0] _ldq_wakeup_e_e_valid_T_1 = _ldq_wakeup_e_e_valid_T; assign ldq_wakeup_e_e_valid = _GEN_25[_ldq_wakeup_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [4:0] _ldq_wakeup_e_e_bits_uop_T_1 = _ldq_wakeup_e_e_bits_uop_T; assign ldq_wakeup_e_e_bits_uop_inst = _GEN_127[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_inst = _GEN_128[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rvc = _GEN_129[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_pc = _GEN_130[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_0 = _GEN_131[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_1 = _GEN_132[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_2 = _GEN_133[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iq_type_3 = _GEN_134[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_0 = _GEN_135[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_1 = _GEN_136[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_2 = _GEN_137[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_3 = _GEN_138[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_4 = _GEN_139[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_5 = _GEN_140[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_6 = _GEN_141[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_7 = _GEN_142[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_8 = _GEN_143[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fu_code_9 = _GEN_144[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued = _GEN_145[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dis_col_sel = _GEN_153[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_mask = _GEN_154[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_tag = _GEN_155[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_br_type = _GEN_156[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfb = _GEN_157[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fence = _GEN_158[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_fencei = _GEN_159[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sfence = _GEN_160[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_amo = _GEN_161[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_eret = _GEN_162[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_rocc = _GEN_164[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_mov = _GEN_165[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ftq_idx = _GEN_166[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_edge_inst = _GEN_167[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pc_lob = _GEN_168[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_taken = _GEN_169[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_rename = _GEN_170[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_sel = _GEN_171[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pimm = _GEN_172[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_imm_packed = _GEN_173[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op1_sel = _GEN_174[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_op2_sel = _GEN_175[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_div = _GEN_189[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rob_idx = _GEN_193[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldq_idx = _GEN_194[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stq_idx = _GEN_195[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_rxq_idx = _GEN_196[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_pdst = _GEN_197[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1 = _GEN_198[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2 = _GEN_199[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3 = _GEN_200[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred = _GEN_201[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs1_busy = _GEN_202[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs2_busy = _GEN_203[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_prs3_busy = _GEN_204[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ppred_busy = _GEN_205[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_stale_pdst = _GEN_206[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exception = _GEN_207[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_exc_cause = _GEN_208[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_cmd = _GEN_209[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_size = _GEN_210[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_mem_signed = _GEN_211[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_ldq = _GEN_212[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_uses_stq = _GEN_213[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_is_unique = _GEN_214[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_flush_on_commit = _GEN_215[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_csr_cmd = _GEN_216[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_ldst = _GEN_218[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1 = _GEN_219[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2 = _GEN_220[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs3 = _GEN_221[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_dst_rtype = _GEN_222[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs1_rtype = _GEN_223[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_lrs2_rtype = _GEN_224[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_frs3_en = _GEN_225[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_dw = _GEN_226[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fcn_op = _GEN_227[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_val = _GEN_228[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_rm = _GEN_229[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_fp_typ = _GEN_230[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_pf_if = _GEN_231[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ae_if = _GEN_232[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_xcpt_ma_if = _GEN_233[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_debug_if = _GEN_234[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_bp_xcpt_if = _GEN_235[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_fsrc = _GEN_236[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign ldq_wakeup_e_e_bits_uop_debug_tsrc = _GEN_237[_ldq_wakeup_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_T_1 = _ldq_wakeup_e_e_bits_addr_T; assign ldq_wakeup_e_e_bits_addr_valid = _GEN_238[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign ldq_wakeup_e_e_bits_addr_bits = _GEN_239[_ldq_wakeup_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_virtual_T_1 = _ldq_wakeup_e_e_bits_addr_is_virtual_T; assign ldq_wakeup_e_e_bits_addr_is_virtual = _GEN_240[_ldq_wakeup_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [4:0] _ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1 = _ldq_wakeup_e_e_bits_addr_is_uncacheable_T; assign ldq_wakeup_e_e_bits_addr_is_uncacheable = _GEN_241[_ldq_wakeup_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [4:0] _ldq_wakeup_e_e_bits_executed_T_1 = _ldq_wakeup_e_e_bits_executed_T; assign ldq_wakeup_e_e_bits_executed = _GEN_242[_ldq_wakeup_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [4:0] _ldq_wakeup_e_e_bits_succeeded_T_1 = _ldq_wakeup_e_e_bits_succeeded_T; assign ldq_wakeup_e_e_bits_succeeded = _GEN_243[_ldq_wakeup_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [4:0] _ldq_wakeup_e_e_bits_order_fail_T_1 = _ldq_wakeup_e_e_bits_order_fail_T; assign ldq_wakeup_e_e_bits_order_fail = _GEN_244[_ldq_wakeup_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [4:0] _ldq_wakeup_e_e_bits_observed_T_1 = _ldq_wakeup_e_e_bits_observed_T; assign ldq_wakeup_e_e_bits_observed = _GEN_245[_ldq_wakeup_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [4:0] _ldq_wakeup_e_e_bits_st_dep_mask_T_1 = _ldq_wakeup_e_e_bits_st_dep_mask_T; assign ldq_wakeup_e_e_bits_st_dep_mask = _GEN_246[_ldq_wakeup_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [4:0] _ldq_wakeup_e_e_bits_ld_byte_mask_T_1 = _ldq_wakeup_e_e_bits_ld_byte_mask_T; assign ldq_wakeup_e_e_bits_ld_byte_mask = _GEN_247[_ldq_wakeup_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [4:0] _ldq_wakeup_e_e_bits_forward_std_val_T_1 = _ldq_wakeup_e_e_bits_forward_std_val_T; assign ldq_wakeup_e_e_bits_forward_std_val = _GEN_248[_ldq_wakeup_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [4:0] _ldq_wakeup_e_e_bits_forward_stq_idx_T_1 = _ldq_wakeup_e_e_bits_forward_stq_idx_T; assign ldq_wakeup_e_e_bits_forward_stq_idx = _GEN_249[_ldq_wakeup_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [4:0] _ldq_wakeup_e_e_bits_debug_wb_data_T_1 = _ldq_wakeup_e_e_bits_debug_wb_data_T; assign ldq_wakeup_e_e_bits_debug_wb_data = _GEN_250[_ldq_wakeup_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_inst = ldq_wakeup_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_wakeup_e_out_bits_uop_debug_inst = ldq_wakeup_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rvc = ldq_wakeup_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_uop_debug_pc = ldq_wakeup_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_0 = ldq_wakeup_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_1 = ldq_wakeup_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_2 = ldq_wakeup_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iq_type_3 = ldq_wakeup_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_0 = ldq_wakeup_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_1 = ldq_wakeup_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_2 = ldq_wakeup_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_3 = ldq_wakeup_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_4 = ldq_wakeup_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_5 = ldq_wakeup_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_6 = ldq_wakeup_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_7 = ldq_wakeup_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_8 = ldq_wakeup_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fu_code_9 = ldq_wakeup_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued = ldq_wakeup_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_agen = ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_issued_partial_dgen = ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iw_p1_speculative_child = ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_iw_p2_speculative_child = ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p1_bypass_hint = ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p2_bypass_hint = ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_iw_p3_bypass_hint = ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_dis_col_sel = ldq_wakeup_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_tag = ldq_wakeup_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_wakeup_e_out_bits_uop_br_type = ldq_wakeup_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfb = ldq_wakeup_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fence = ldq_wakeup_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_fencei = ldq_wakeup_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sfence = ldq_wakeup_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_amo = ldq_wakeup_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_eret = ldq_wakeup_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_sys_pc2epc = ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_rocc = ldq_wakeup_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_mov = ldq_wakeup_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ftq_idx = ldq_wakeup_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_edge_inst = ldq_wakeup_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_pc_lob = ldq_wakeup_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_taken = ldq_wakeup_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_imm_rename = ldq_wakeup_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_imm_sel = ldq_wakeup_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_pimm = ldq_wakeup_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_wakeup_e_out_bits_uop_imm_packed = ldq_wakeup_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_op1_sel = ldq_wakeup_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_op2_sel = ldq_wakeup_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ldst = ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wen = ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren1 = ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren2 = ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_ren3 = ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap12 = ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_swap23 = ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagIn = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_typeTagOut = ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fromint = ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_toint = ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fastpipe = ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_fma = ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_div = ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_sqrt = ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_wflags = ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_ctrl_vec = ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_rob_idx = ldq_wakeup_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ldq_idx = ldq_wakeup_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = ldq_wakeup_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_rxq_idx = ldq_wakeup_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_pdst = ldq_wakeup_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs1 = ldq_wakeup_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs2 = ldq_wakeup_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_prs3 = ldq_wakeup_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_ppred = ldq_wakeup_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs1_busy = ldq_wakeup_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs2_busy = ldq_wakeup_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_prs3_busy = ldq_wakeup_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ppred_busy = ldq_wakeup_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_wakeup_e_out_bits_uop_stale_pdst = ldq_wakeup_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_exception = ldq_wakeup_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_uop_exc_cause = ldq_wakeup_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_mem_cmd = ldq_wakeup_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = ldq_wakeup_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_mem_signed = ldq_wakeup_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_ldq = ldq_wakeup_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_uses_stq = ldq_wakeup_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_is_unique = ldq_wakeup_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_flush_on_commit = ldq_wakeup_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_csr_cmd = ldq_wakeup_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_ldst_is_rs1 = ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_ldst = ldq_wakeup_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs1 = ldq_wakeup_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs2 = ldq_wakeup_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_wakeup_e_out_bits_uop_lrs3 = ldq_wakeup_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_dst_rtype = ldq_wakeup_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs1_rtype = ldq_wakeup_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_lrs2_rtype = ldq_wakeup_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_frs3_en = ldq_wakeup_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fcn_dw = ldq_wakeup_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_uop_fcn_op = ldq_wakeup_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_fp_val = ldq_wakeup_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_fp_rm = ldq_wakeup_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_wakeup_e_out_bits_uop_fp_typ = ldq_wakeup_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_pf_if = ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ae_if = ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_xcpt_ma_if = ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_debug_if = ldq_wakeup_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_uop_bp_xcpt_if = ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_fsrc = ldq_wakeup_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_wakeup_e_out_bits_uop_debug_tsrc = ldq_wakeup_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_valid = ldq_wakeup_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_wakeup_e_out_bits_addr_bits = ldq_wakeup_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_virtual = ldq_wakeup_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_addr_is_uncacheable = ldq_wakeup_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_executed = ldq_wakeup_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_succeeded = ldq_wakeup_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_order_fail = ldq_wakeup_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_observed = ldq_wakeup_e_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = ldq_wakeup_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_wakeup_e_out_bits_ld_byte_mask = ldq_wakeup_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_bits_forward_std_val = ldq_wakeup_e_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_wakeup_e_out_bits_forward_stq_idx = ldq_wakeup_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_wakeup_e_out_bits_debug_wb_data = ldq_wakeup_e_bits_debug_wb_data; // @[util.scala:114:23] reg [4:0] ldq_enq_retry_idx; // @[lsu.scala:514:30] wire _ldq_enq_retry_idx_T = ldq_addr_0_valid & ldq_addr_is_virtual_0; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_1 = |ldq_enq_retry_idx; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_2 = _ldq_enq_retry_idx_T & _ldq_enq_retry_idx_T_1; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_3 = ldq_addr_1_valid & ldq_addr_is_virtual_1; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_4 = ldq_enq_retry_idx != 5'h1; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_5 = _ldq_enq_retry_idx_T_3 & _ldq_enq_retry_idx_T_4; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_6 = ldq_addr_2_valid & ldq_addr_is_virtual_2; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_7 = ldq_enq_retry_idx != 5'h2; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_8 = _ldq_enq_retry_idx_T_6 & _ldq_enq_retry_idx_T_7; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_9 = ldq_addr_3_valid & ldq_addr_is_virtual_3; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_10 = ldq_enq_retry_idx != 5'h3; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_11 = _ldq_enq_retry_idx_T_9 & _ldq_enq_retry_idx_T_10; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_12 = ldq_addr_4_valid & ldq_addr_is_virtual_4; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_13 = ldq_enq_retry_idx != 5'h4; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_14 = _ldq_enq_retry_idx_T_12 & _ldq_enq_retry_idx_T_13; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_15 = ldq_addr_5_valid & ldq_addr_is_virtual_5; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_16 = ldq_enq_retry_idx != 5'h5; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_17 = _ldq_enq_retry_idx_T_15 & _ldq_enq_retry_idx_T_16; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_18 = ldq_addr_6_valid & ldq_addr_is_virtual_6; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_19 = ldq_enq_retry_idx != 5'h6; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_20 = _ldq_enq_retry_idx_T_18 & _ldq_enq_retry_idx_T_19; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_21 = ldq_addr_7_valid & ldq_addr_is_virtual_7; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_22 = ldq_enq_retry_idx != 5'h7; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_23 = _ldq_enq_retry_idx_T_21 & _ldq_enq_retry_idx_T_22; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_24 = ldq_addr_8_valid & ldq_addr_is_virtual_8; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_25 = ldq_enq_retry_idx != 5'h8; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_26 = _ldq_enq_retry_idx_T_24 & _ldq_enq_retry_idx_T_25; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_27 = ldq_addr_9_valid & ldq_addr_is_virtual_9; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_28 = ldq_enq_retry_idx != 5'h9; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_29 = _ldq_enq_retry_idx_T_27 & _ldq_enq_retry_idx_T_28; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_30 = ldq_addr_10_valid & ldq_addr_is_virtual_10; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_31 = ldq_enq_retry_idx != 5'hA; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_32 = _ldq_enq_retry_idx_T_30 & _ldq_enq_retry_idx_T_31; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_33 = ldq_addr_11_valid & ldq_addr_is_virtual_11; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_34 = ldq_enq_retry_idx != 5'hB; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_35 = _ldq_enq_retry_idx_T_33 & _ldq_enq_retry_idx_T_34; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_36 = ldq_addr_12_valid & ldq_addr_is_virtual_12; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_37 = ldq_enq_retry_idx != 5'hC; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_38 = _ldq_enq_retry_idx_T_36 & _ldq_enq_retry_idx_T_37; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_39 = ldq_addr_13_valid & ldq_addr_is_virtual_13; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_40 = ldq_enq_retry_idx != 5'hD; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_41 = _ldq_enq_retry_idx_T_39 & _ldq_enq_retry_idx_T_40; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_42 = ldq_addr_14_valid & ldq_addr_is_virtual_14; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_43 = ldq_enq_retry_idx != 5'hE; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_44 = _ldq_enq_retry_idx_T_42 & _ldq_enq_retry_idx_T_43; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_45 = ldq_addr_15_valid & ldq_addr_is_virtual_15; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_46 = ldq_enq_retry_idx != 5'hF; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_47 = _ldq_enq_retry_idx_T_45 & _ldq_enq_retry_idx_T_46; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_48 = ldq_addr_16_valid & ldq_addr_is_virtual_16; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_49 = ldq_enq_retry_idx != 5'h10; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_50 = _ldq_enq_retry_idx_T_48 & _ldq_enq_retry_idx_T_49; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_51 = ldq_addr_17_valid & ldq_addr_is_virtual_17; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_52 = ldq_enq_retry_idx != 5'h11; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_53 = _ldq_enq_retry_idx_T_51 & _ldq_enq_retry_idx_T_52; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_54 = ldq_addr_18_valid & ldq_addr_is_virtual_18; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_55 = ldq_enq_retry_idx != 5'h12; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_56 = _ldq_enq_retry_idx_T_54 & _ldq_enq_retry_idx_T_55; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_57 = ldq_addr_19_valid & ldq_addr_is_virtual_19; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_58 = ldq_enq_retry_idx != 5'h13; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_59 = _ldq_enq_retry_idx_T_57 & _ldq_enq_retry_idx_T_58; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_60 = ldq_addr_20_valid & ldq_addr_is_virtual_20; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_61 = ldq_enq_retry_idx != 5'h14; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_62 = _ldq_enq_retry_idx_T_60 & _ldq_enq_retry_idx_T_61; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_63 = ldq_addr_21_valid & ldq_addr_is_virtual_21; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_64 = ldq_enq_retry_idx != 5'h15; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_65 = _ldq_enq_retry_idx_T_63 & _ldq_enq_retry_idx_T_64; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_66 = ldq_addr_22_valid & ldq_addr_is_virtual_22; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_67 = ldq_enq_retry_idx != 5'h16; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_68 = _ldq_enq_retry_idx_T_66 & _ldq_enq_retry_idx_T_67; // @[lsu.scala:516:{23,49,57}] wire _ldq_enq_retry_idx_T_69 = ldq_addr_23_valid & ldq_addr_is_virtual_23; // @[lsu.scala:220:36, :221:36, :516:23] wire _ldq_enq_retry_idx_T_70 = ldq_enq_retry_idx != 5'h17; // @[lsu.scala:514:30, :516:57] wire _ldq_enq_retry_idx_T_71 = _ldq_enq_retry_idx_T_69 & _ldq_enq_retry_idx_T_70; // @[lsu.scala:516:{23,49,57}] wire ldq_enq_retry_idx_temp_vec_0 = _ldq_enq_retry_idx_T_2 & _ldq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_1 = _ldq_enq_retry_idx_T_5 & _ldq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_2 = _ldq_enq_retry_idx_T_8 & _ldq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_3 = _ldq_enq_retry_idx_T_11 & _ldq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_4 = _ldq_enq_retry_idx_T_14 & _ldq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_5 = _ldq_enq_retry_idx_T_17 & _ldq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_6 = _ldq_enq_retry_idx_T_20 & _ldq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_7 = _ldq_enq_retry_idx_T_23 & _ldq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_8 = _ldq_enq_retry_idx_T_26 & _ldq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_9 = _ldq_enq_retry_idx_T_29 & _ldq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_10 = _ldq_enq_retry_idx_T_32 & _ldq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_11 = _ldq_enq_retry_idx_T_35 & _ldq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_12 = _ldq_enq_retry_idx_T_38 & _ldq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_13 = _ldq_enq_retry_idx_T_41 & _ldq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_14 = _ldq_enq_retry_idx_T_44 & _ldq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _ldq_enq_retry_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire ldq_enq_retry_idx_temp_vec_15 = _ldq_enq_retry_idx_T_47 & _ldq_enq_retry_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_16 = _ldq_enq_retry_idx_T_50 & _ldq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_17 = _ldq_enq_retry_idx_T_53 & _ldq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_18 = _ldq_enq_retry_idx_T_56 & _ldq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_19 = _ldq_enq_retry_idx_T_59 & _ldq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_20 = _ldq_enq_retry_idx_T_62 & _ldq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_21 = _ldq_enq_retry_idx_T_65 & _ldq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_22 = _ldq_enq_retry_idx_T_68 & _ldq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire ldq_enq_retry_idx_temp_vec_23 = _ldq_enq_retry_idx_T_71 & _ldq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _ldq_enq_retry_idx_idx_T = {5'h1B, ~_ldq_enq_retry_idx_T_68}; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_1 = _ldq_enq_retry_idx_T_65 ? 6'h35 : _ldq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_2 = _ldq_enq_retry_idx_T_62 ? 6'h34 : _ldq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_3 = _ldq_enq_retry_idx_T_59 ? 6'h33 : _ldq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_4 = _ldq_enq_retry_idx_T_56 ? 6'h32 : _ldq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_5 = _ldq_enq_retry_idx_T_53 ? 6'h31 : _ldq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_6 = _ldq_enq_retry_idx_T_50 ? 6'h30 : _ldq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_7 = _ldq_enq_retry_idx_T_47 ? 6'h2F : _ldq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_8 = _ldq_enq_retry_idx_T_44 ? 6'h2E : _ldq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_9 = _ldq_enq_retry_idx_T_41 ? 6'h2D : _ldq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_10 = _ldq_enq_retry_idx_T_38 ? 6'h2C : _ldq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_11 = _ldq_enq_retry_idx_T_35 ? 6'h2B : _ldq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_12 = _ldq_enq_retry_idx_T_32 ? 6'h2A : _ldq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_13 = _ldq_enq_retry_idx_T_29 ? 6'h29 : _ldq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_14 = _ldq_enq_retry_idx_T_26 ? 6'h28 : _ldq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_15 = _ldq_enq_retry_idx_T_23 ? 6'h27 : _ldq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_16 = _ldq_enq_retry_idx_T_20 ? 6'h26 : _ldq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_17 = _ldq_enq_retry_idx_T_17 ? 6'h25 : _ldq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_18 = _ldq_enq_retry_idx_T_14 ? 6'h24 : _ldq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_19 = _ldq_enq_retry_idx_T_11 ? 6'h23 : _ldq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_20 = _ldq_enq_retry_idx_T_8 ? 6'h22 : _ldq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_21 = _ldq_enq_retry_idx_T_5 ? 6'h21 : _ldq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_22 = _ldq_enq_retry_idx_T_2 ? 6'h20 : _ldq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_23 = _ldq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_24 = _ldq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_25 = _ldq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_26 = _ldq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_27 = _ldq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_28 = _ldq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_29 = _ldq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_30 = _ldq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_31 = ldq_enq_retry_idx_temp_vec_23 ? 6'h17 : _ldq_enq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_32 = ldq_enq_retry_idx_temp_vec_22 ? 6'h16 : _ldq_enq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_33 = ldq_enq_retry_idx_temp_vec_21 ? 6'h15 : _ldq_enq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_34 = ldq_enq_retry_idx_temp_vec_20 ? 6'h14 : _ldq_enq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_35 = ldq_enq_retry_idx_temp_vec_19 ? 6'h13 : _ldq_enq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_36 = ldq_enq_retry_idx_temp_vec_18 ? 6'h12 : _ldq_enq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_37 = ldq_enq_retry_idx_temp_vec_17 ? 6'h11 : _ldq_enq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_38 = ldq_enq_retry_idx_temp_vec_16 ? 6'h10 : _ldq_enq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_39 = ldq_enq_retry_idx_temp_vec_15 ? 6'hF : _ldq_enq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_40 = ldq_enq_retry_idx_temp_vec_14 ? 6'hE : _ldq_enq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_41 = ldq_enq_retry_idx_temp_vec_13 ? 6'hD : _ldq_enq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_42 = ldq_enq_retry_idx_temp_vec_12 ? 6'hC : _ldq_enq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_43 = ldq_enq_retry_idx_temp_vec_11 ? 6'hB : _ldq_enq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_44 = ldq_enq_retry_idx_temp_vec_10 ? 6'hA : _ldq_enq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_45 = ldq_enq_retry_idx_temp_vec_9 ? 6'h9 : _ldq_enq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_46 = ldq_enq_retry_idx_temp_vec_8 ? 6'h8 : _ldq_enq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_47 = ldq_enq_retry_idx_temp_vec_7 ? 6'h7 : _ldq_enq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_48 = ldq_enq_retry_idx_temp_vec_6 ? 6'h6 : _ldq_enq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_49 = ldq_enq_retry_idx_temp_vec_5 ? 6'h5 : _ldq_enq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_50 = ldq_enq_retry_idx_temp_vec_4 ? 6'h4 : _ldq_enq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_51 = ldq_enq_retry_idx_temp_vec_3 ? 6'h3 : _ldq_enq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_52 = ldq_enq_retry_idx_temp_vec_2 ? 6'h2 : _ldq_enq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _ldq_enq_retry_idx_idx_T_53 = ldq_enq_retry_idx_temp_vec_1 ? 6'h1 : _ldq_enq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] ldq_enq_retry_idx_idx = ldq_enq_retry_idx_temp_vec_0 ? 6'h0 : _ldq_enq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _ldq_enq_retry_idx_T_72 = ldq_enq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] wire ldq_enq_retry_e_valid = ldq_enq_retry_e_e_valid; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_inst = ldq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:233:17, :518:33] wire [31:0] ldq_enq_retry_e_bits_uop_debug_inst = ldq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rvc = ldq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_uop_debug_pc = ldq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_0 = ldq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_1 = ldq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_2 = ldq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iq_type_3 = ldq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_0 = ldq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_1 = ldq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_2 = ldq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_3 = ldq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_4 = ldq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_5 = ldq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_6 = ldq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_7 = ldq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_8 = ldq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fu_code_9 = ldq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued = ldq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_agen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen = ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_iw_p1_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_iw_p2_speculative_child = ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint = ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_dis_col_sel = ldq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:233:17, :518:33] wire [15:0] ldq_enq_retry_e_bits_uop_br_mask = ldq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_tag = ldq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:233:17, :518:33] wire [3:0] ldq_enq_retry_e_bits_uop_br_type = ldq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfb = ldq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fence = ldq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_fencei = ldq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sfence = ldq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_amo = ldq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_eret = ldq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_sys_pc2epc = ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_rocc = ldq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_mov = ldq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ftq_idx = ldq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_edge_inst = ldq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_pc_lob = ldq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_taken = ldq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_imm_rename = ldq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_imm_sel = ldq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_pimm = ldq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:233:17, :518:33] wire [19:0] ldq_enq_retry_e_bits_uop_imm_packed = ldq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_op1_sel = ldq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_op2_sel = ldq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ldst = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wen = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren1 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren2 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_ren3 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap12 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_swap23 = ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fromint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_toint = ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_fma = ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_div = ldq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt = ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_wflags = ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_ctrl_vec = ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_rob_idx = ldq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ldq_idx = ldq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_stq_idx = ldq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_rxq_idx = ldq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_pdst = ldq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs1 = ldq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs2 = ldq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_prs3 = ldq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_ppred = ldq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs1_busy = ldq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs2_busy = ldq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_prs3_busy = ldq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ppred_busy = ldq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:233:17, :518:33] wire [6:0] ldq_enq_retry_e_bits_uop_stale_pdst = ldq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_exception = ldq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_uop_exc_cause = ldq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_mem_cmd = ldq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_mem_size = ldq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_mem_signed = ldq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_ldq = ldq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_uses_stq = ldq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_is_unique = ldq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_flush_on_commit = ldq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_csr_cmd = ldq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_ldst_is_rs1 = ldq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_ldst = ldq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs1 = ldq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs2 = ldq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:233:17, :518:33] wire [5:0] ldq_enq_retry_e_bits_uop_lrs3 = ldq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_dst_rtype = ldq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs1_rtype = ldq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_lrs2_rtype = ldq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_frs3_en = ldq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fcn_dw = ldq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_uop_fcn_op = ldq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_fp_val = ldq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_fp_rm = ldq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:233:17, :518:33] wire [1:0] ldq_enq_retry_e_bits_uop_fp_typ = ldq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_pf_if = ldq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ae_if = ldq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_xcpt_ma_if = ldq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_debug_if = ldq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_uop_bp_xcpt_if = ldq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_fsrc = ldq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:233:17, :518:33] wire [2:0] ldq_enq_retry_e_bits_uop_debug_tsrc = ldq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_valid = ldq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:233:17, :518:33] wire [39:0] ldq_enq_retry_e_bits_addr_bits = ldq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_virtual = ldq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_addr_is_uncacheable = ldq_enq_retry_e_e_bits_addr_is_uncacheable; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_executed = ldq_enq_retry_e_e_bits_executed; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_succeeded = ldq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_order_fail = ldq_enq_retry_e_e_bits_order_fail; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_observed = ldq_enq_retry_e_e_bits_observed; // @[lsu.scala:233:17, :518:33] wire [23:0] ldq_enq_retry_e_bits_st_dep_mask = ldq_enq_retry_e_e_bits_st_dep_mask; // @[lsu.scala:233:17, :518:33] wire [7:0] ldq_enq_retry_e_bits_ld_byte_mask = ldq_enq_retry_e_e_bits_ld_byte_mask; // @[lsu.scala:233:17, :518:33] wire ldq_enq_retry_e_bits_forward_std_val = ldq_enq_retry_e_e_bits_forward_std_val; // @[lsu.scala:233:17, :518:33] wire [4:0] ldq_enq_retry_e_bits_forward_stq_idx = ldq_enq_retry_e_e_bits_forward_stq_idx; // @[lsu.scala:233:17, :518:33] wire [63:0] ldq_enq_retry_e_bits_debug_wb_data = ldq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:233:17, :518:33] assign ldq_enq_retry_e_e_valid = _GEN_25[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :514:30] assign ldq_enq_retry_e_e_bits_uop_inst = _GEN_127[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_inst = _GEN_128[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rvc = _GEN_129[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_pc = _GEN_130[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_131[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_132[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_133[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_134[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_135[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_136[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_137[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_138[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_139[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_140[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_141[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_142[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_143[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_144[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued = _GEN_145[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_153[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_mask = _GEN_154[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_tag = _GEN_155[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_br_type = _GEN_156[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfb = _GEN_157[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fence = _GEN_158[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_fencei = _GEN_159[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sfence = _GEN_160[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_amo = _GEN_161[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_eret = _GEN_162[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_163[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_rocc = _GEN_164[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_mov = _GEN_165[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_166[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_edge_inst = _GEN_167[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pc_lob = _GEN_168[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_taken = _GEN_169[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_rename = _GEN_170[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_sel = _GEN_171[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pimm = _GEN_172[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_imm_packed = _GEN_173[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op1_sel = _GEN_174[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_op2_sel = _GEN_175[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_177[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_186[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_188[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_189[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_192[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rob_idx = _GEN_193[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_194[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stq_idx = _GEN_195[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_196[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_pdst = _GEN_197[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1 = _GEN_198[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2 = _GEN_199[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3 = _GEN_200[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred = _GEN_201[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_202[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_203[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_204[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_205[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_206[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exception = _GEN_207[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_exc_cause = _GEN_208[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_209[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_size = _GEN_210[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_mem_signed = _GEN_211[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_212[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_uses_stq = _GEN_213[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_is_unique = _GEN_214[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_215[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_216[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_217[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_ldst = _GEN_218[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1 = _GEN_219[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2 = _GEN_220[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs3 = _GEN_221[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_222[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_223[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_224[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_frs3_en = _GEN_225[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_226[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fcn_op = _GEN_227[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_val = _GEN_228[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_rm = _GEN_229[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_fp_typ = _GEN_230[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_231[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_232[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_233[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_234[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_235[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_236[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_237[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :235:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_valid = _GEN_238[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_bits = _GEN_239[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :236:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_virtual = _GEN_240[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :237:32, :514:30] assign ldq_enq_retry_e_e_bits_addr_is_uncacheable = _GEN_241[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :238:32, :514:30] assign ldq_enq_retry_e_e_bits_executed = _GEN_242[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :239:32, :514:30] assign ldq_enq_retry_e_e_bits_succeeded = _GEN_243[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :240:32, :514:30] assign ldq_enq_retry_e_e_bits_order_fail = _GEN_244[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :241:32, :514:30] assign ldq_enq_retry_e_e_bits_observed = _GEN_245[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :242:32, :514:30] assign ldq_enq_retry_e_e_bits_st_dep_mask = _GEN_246[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :243:32, :514:30] assign ldq_enq_retry_e_e_bits_ld_byte_mask = _GEN_247[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :244:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_std_val = _GEN_248[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :245:32, :514:30] assign ldq_enq_retry_e_e_bits_forward_stq_idx = _GEN_249[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :246:32, :514:30] assign ldq_enq_retry_e_e_bits_debug_wb_data = _GEN_250[ldq_enq_retry_idx]; // @[lsu.scala:233:17, :247:32, :514:30] reg [4:0] stq_enq_retry_idx; // @[lsu.scala:520:30] wire _stq_enq_retry_idx_T = stq_addr_0_valid & stq_addr_is_virtual_0; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_1 = |stq_enq_retry_idx; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_2 = _stq_enq_retry_idx_T & _stq_enq_retry_idx_T_1; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_3 = stq_addr_1_valid & stq_addr_is_virtual_1; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_4 = stq_enq_retry_idx != 5'h1; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_5 = _stq_enq_retry_idx_T_3 & _stq_enq_retry_idx_T_4; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_6 = stq_addr_2_valid & stq_addr_is_virtual_2; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_7 = stq_enq_retry_idx != 5'h2; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_8 = _stq_enq_retry_idx_T_6 & _stq_enq_retry_idx_T_7; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_9 = stq_addr_3_valid & stq_addr_is_virtual_3; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_10 = stq_enq_retry_idx != 5'h3; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_11 = _stq_enq_retry_idx_T_9 & _stq_enq_retry_idx_T_10; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_12 = stq_addr_4_valid & stq_addr_is_virtual_4; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_13 = stq_enq_retry_idx != 5'h4; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_14 = _stq_enq_retry_idx_T_12 & _stq_enq_retry_idx_T_13; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_15 = stq_addr_5_valid & stq_addr_is_virtual_5; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_16 = stq_enq_retry_idx != 5'h5; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_17 = _stq_enq_retry_idx_T_15 & _stq_enq_retry_idx_T_16; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_18 = stq_addr_6_valid & stq_addr_is_virtual_6; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_19 = stq_enq_retry_idx != 5'h6; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_20 = _stq_enq_retry_idx_T_18 & _stq_enq_retry_idx_T_19; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_21 = stq_addr_7_valid & stq_addr_is_virtual_7; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_22 = stq_enq_retry_idx != 5'h7; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_23 = _stq_enq_retry_idx_T_21 & _stq_enq_retry_idx_T_22; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_24 = stq_addr_8_valid & stq_addr_is_virtual_8; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_25 = stq_enq_retry_idx != 5'h8; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_26 = _stq_enq_retry_idx_T_24 & _stq_enq_retry_idx_T_25; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_27 = stq_addr_9_valid & stq_addr_is_virtual_9; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_28 = stq_enq_retry_idx != 5'h9; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_29 = _stq_enq_retry_idx_T_27 & _stq_enq_retry_idx_T_28; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_30 = stq_addr_10_valid & stq_addr_is_virtual_10; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_31 = stq_enq_retry_idx != 5'hA; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_32 = _stq_enq_retry_idx_T_30 & _stq_enq_retry_idx_T_31; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_33 = stq_addr_11_valid & stq_addr_is_virtual_11; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_34 = stq_enq_retry_idx != 5'hB; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_35 = _stq_enq_retry_idx_T_33 & _stq_enq_retry_idx_T_34; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_36 = stq_addr_12_valid & stq_addr_is_virtual_12; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_37 = stq_enq_retry_idx != 5'hC; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_38 = _stq_enq_retry_idx_T_36 & _stq_enq_retry_idx_T_37; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_39 = stq_addr_13_valid & stq_addr_is_virtual_13; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_40 = stq_enq_retry_idx != 5'hD; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_41 = _stq_enq_retry_idx_T_39 & _stq_enq_retry_idx_T_40; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_42 = stq_addr_14_valid & stq_addr_is_virtual_14; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_43 = stq_enq_retry_idx != 5'hE; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_44 = _stq_enq_retry_idx_T_42 & _stq_enq_retry_idx_T_43; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_45 = stq_addr_15_valid & stq_addr_is_virtual_15; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_46 = stq_enq_retry_idx != 5'hF; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_47 = _stq_enq_retry_idx_T_45 & _stq_enq_retry_idx_T_46; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_48 = stq_addr_16_valid & stq_addr_is_virtual_16; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_49 = stq_enq_retry_idx != 5'h10; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_50 = _stq_enq_retry_idx_T_48 & _stq_enq_retry_idx_T_49; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_51 = stq_addr_17_valid & stq_addr_is_virtual_17; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_52 = stq_enq_retry_idx != 5'h11; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_53 = _stq_enq_retry_idx_T_51 & _stq_enq_retry_idx_T_52; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_54 = stq_addr_18_valid & stq_addr_is_virtual_18; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_55 = stq_enq_retry_idx != 5'h12; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_56 = _stq_enq_retry_idx_T_54 & _stq_enq_retry_idx_T_55; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_57 = stq_addr_19_valid & stq_addr_is_virtual_19; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_58 = stq_enq_retry_idx != 5'h13; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_59 = _stq_enq_retry_idx_T_57 & _stq_enq_retry_idx_T_58; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_60 = stq_addr_20_valid & stq_addr_is_virtual_20; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_61 = stq_enq_retry_idx != 5'h14; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_62 = _stq_enq_retry_idx_T_60 & _stq_enq_retry_idx_T_61; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_63 = stq_addr_21_valid & stq_addr_is_virtual_21; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_64 = stq_enq_retry_idx != 5'h15; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_65 = _stq_enq_retry_idx_T_63 & _stq_enq_retry_idx_T_64; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_66 = stq_addr_22_valid & stq_addr_is_virtual_22; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_67 = stq_enq_retry_idx != 5'h16; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_68 = _stq_enq_retry_idx_T_66 & _stq_enq_retry_idx_T_67; // @[lsu.scala:522:{23,49,57}] wire _stq_enq_retry_idx_T_69 = stq_addr_23_valid & stq_addr_is_virtual_23; // @[lsu.scala:253:32, :254:32, :522:23] wire _stq_enq_retry_idx_T_70 = stq_enq_retry_idx != 5'h17; // @[lsu.scala:520:30, :522:57] wire _stq_enq_retry_idx_T_71 = _stq_enq_retry_idx_T_69 & _stq_enq_retry_idx_T_70; // @[lsu.scala:522:{23,49,57}] wire _GEN_395 = stq_commit_head == 5'h0; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T = _GEN_395; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T = _GEN_395; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_0 = _stq_enq_retry_idx_T_2 & _stq_enq_retry_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _GEN_396 = stq_commit_head < 5'h2; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_1 = _GEN_396; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_1 = _GEN_396; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_1 = _stq_enq_retry_idx_T_5 & _stq_enq_retry_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _GEN_397 = stq_commit_head < 5'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_2 = _GEN_397; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_2 = _GEN_397; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_2 = _stq_enq_retry_idx_T_8 & _stq_enq_retry_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _GEN_398 = stq_commit_head < 5'h4; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_3 = _GEN_398; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_3 = _GEN_398; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_3 = _stq_enq_retry_idx_T_11 & _stq_enq_retry_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _GEN_399 = stq_commit_head < 5'h5; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_4 = _GEN_399; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_4 = _GEN_399; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_4 = _stq_enq_retry_idx_T_14 & _stq_enq_retry_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _GEN_400 = stq_commit_head < 5'h6; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_5 = _GEN_400; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_5 = _GEN_400; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_5 = _stq_enq_retry_idx_T_17 & _stq_enq_retry_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _GEN_401 = stq_commit_head < 5'h7; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_6 = _GEN_401; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_6 = _GEN_401; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_6 = _stq_enq_retry_idx_T_20 & _stq_enq_retry_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _GEN_402 = stq_commit_head < 5'h8; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_7 = _GEN_402; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_7 = _GEN_402; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_7 = _stq_enq_retry_idx_T_23 & _stq_enq_retry_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _GEN_403 = stq_commit_head < 5'h9; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_8 = _GEN_403; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_8 = _GEN_403; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_8 = _stq_enq_retry_idx_T_26 & _stq_enq_retry_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _GEN_404 = stq_commit_head < 5'hA; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_9 = _GEN_404; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_9 = _GEN_404; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_9 = _stq_enq_retry_idx_T_29 & _stq_enq_retry_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _GEN_405 = stq_commit_head < 5'hB; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_10 = _GEN_405; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_10 = _GEN_405; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_10 = _stq_enq_retry_idx_T_32 & _stq_enq_retry_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _GEN_406 = stq_commit_head < 5'hC; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_11 = _GEN_406; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_11 = _GEN_406; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_11 = _stq_enq_retry_idx_T_35 & _stq_enq_retry_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _GEN_407 = stq_commit_head < 5'hD; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_12 = _GEN_407; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_12 = _GEN_407; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_12 = _stq_enq_retry_idx_T_38 & _stq_enq_retry_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _GEN_408 = stq_commit_head < 5'hE; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_13 = _GEN_408; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_13 = _GEN_408; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_13 = _stq_enq_retry_idx_T_41 & _stq_enq_retry_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _GEN_409 = stq_commit_head < 5'hF; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_14 = _GEN_409; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_14 = _GEN_409; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_14 = _stq_enq_retry_idx_T_44 & _stq_enq_retry_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _stq_enq_retry_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_15 = _stq_enq_retry_idx_T_47 & _stq_enq_retry_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _GEN_410 = stq_commit_head < 5'h11; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_16 = _GEN_410; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_16; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_16 = _GEN_410; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_16 = _stq_enq_retry_idx_T_50 & _stq_enq_retry_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _GEN_411 = stq_commit_head < 5'h12; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_17 = _GEN_411; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_17; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_17 = _GEN_411; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_17 = _stq_enq_retry_idx_T_53 & _stq_enq_retry_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _GEN_412 = stq_commit_head < 5'h13; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_18 = _GEN_412; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_18; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_18 = _GEN_412; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_18 = _stq_enq_retry_idx_T_56 & _stq_enq_retry_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _GEN_413 = stq_commit_head < 5'h14; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_19 = _GEN_413; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_19; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_19 = _GEN_413; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_19 = _stq_enq_retry_idx_T_59 & _stq_enq_retry_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _GEN_414 = stq_commit_head < 5'h15; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_20 = _GEN_414; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_20; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_20 = _GEN_414; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_20 = _stq_enq_retry_idx_T_62 & _stq_enq_retry_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _GEN_415 = stq_commit_head < 5'h16; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_21 = _GEN_415; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_21; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_21 = _GEN_415; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_21 = _stq_enq_retry_idx_T_65 & _stq_enq_retry_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _GEN_416 = stq_commit_head < 5'h17; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_22 = _GEN_416; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_22; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_22 = _GEN_416; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_22 = _stq_enq_retry_idx_T_68 & _stq_enq_retry_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _GEN_417 = stq_commit_head[4:3] != 2'h3; // @[util.scala:352:72] wire _stq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:72] assign _stq_enq_retry_idx_temp_vec_T_23 = _GEN_417; // @[util.scala:352:72] wire _stq_clr_head_idx_temp_vec_T_23; // @[util.scala:352:72] assign _stq_clr_head_idx_temp_vec_T_23 = _GEN_417; // @[util.scala:352:72] wire stq_enq_retry_idx_temp_vec_23 = _stq_enq_retry_idx_T_71 & _stq_enq_retry_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _stq_enq_retry_idx_idx_T = {5'h1B, ~_stq_enq_retry_idx_T_68}; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_1 = _stq_enq_retry_idx_T_65 ? 6'h35 : _stq_enq_retry_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_2 = _stq_enq_retry_idx_T_62 ? 6'h34 : _stq_enq_retry_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_3 = _stq_enq_retry_idx_T_59 ? 6'h33 : _stq_enq_retry_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_4 = _stq_enq_retry_idx_T_56 ? 6'h32 : _stq_enq_retry_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_5 = _stq_enq_retry_idx_T_53 ? 6'h31 : _stq_enq_retry_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_6 = _stq_enq_retry_idx_T_50 ? 6'h30 : _stq_enq_retry_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_7 = _stq_enq_retry_idx_T_47 ? 6'h2F : _stq_enq_retry_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_8 = _stq_enq_retry_idx_T_44 ? 6'h2E : _stq_enq_retry_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_9 = _stq_enq_retry_idx_T_41 ? 6'h2D : _stq_enq_retry_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_10 = _stq_enq_retry_idx_T_38 ? 6'h2C : _stq_enq_retry_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_11 = _stq_enq_retry_idx_T_35 ? 6'h2B : _stq_enq_retry_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_12 = _stq_enq_retry_idx_T_32 ? 6'h2A : _stq_enq_retry_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_13 = _stq_enq_retry_idx_T_29 ? 6'h29 : _stq_enq_retry_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_14 = _stq_enq_retry_idx_T_26 ? 6'h28 : _stq_enq_retry_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_15 = _stq_enq_retry_idx_T_23 ? 6'h27 : _stq_enq_retry_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_16 = _stq_enq_retry_idx_T_20 ? 6'h26 : _stq_enq_retry_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_17 = _stq_enq_retry_idx_T_17 ? 6'h25 : _stq_enq_retry_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_18 = _stq_enq_retry_idx_T_14 ? 6'h24 : _stq_enq_retry_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_19 = _stq_enq_retry_idx_T_11 ? 6'h23 : _stq_enq_retry_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_20 = _stq_enq_retry_idx_T_8 ? 6'h22 : _stq_enq_retry_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_21 = _stq_enq_retry_idx_T_5 ? 6'h21 : _stq_enq_retry_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_22 = _stq_enq_retry_idx_T_2 ? 6'h20 : _stq_enq_retry_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_23 = _stq_enq_retry_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_24 = _stq_enq_retry_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_25 = _stq_enq_retry_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_26 = _stq_enq_retry_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_27 = _stq_enq_retry_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_28 = _stq_enq_retry_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_29 = _stq_enq_retry_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_30 = _stq_enq_retry_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_31 = stq_enq_retry_idx_temp_vec_23 ? 6'h17 : _stq_enq_retry_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_32 = stq_enq_retry_idx_temp_vec_22 ? 6'h16 : _stq_enq_retry_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_33 = stq_enq_retry_idx_temp_vec_21 ? 6'h15 : _stq_enq_retry_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_34 = stq_enq_retry_idx_temp_vec_20 ? 6'h14 : _stq_enq_retry_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_35 = stq_enq_retry_idx_temp_vec_19 ? 6'h13 : _stq_enq_retry_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_36 = stq_enq_retry_idx_temp_vec_18 ? 6'h12 : _stq_enq_retry_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_37 = stq_enq_retry_idx_temp_vec_17 ? 6'h11 : _stq_enq_retry_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_38 = stq_enq_retry_idx_temp_vec_16 ? 6'h10 : _stq_enq_retry_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_39 = stq_enq_retry_idx_temp_vec_15 ? 6'hF : _stq_enq_retry_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_40 = stq_enq_retry_idx_temp_vec_14 ? 6'hE : _stq_enq_retry_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_41 = stq_enq_retry_idx_temp_vec_13 ? 6'hD : _stq_enq_retry_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_42 = stq_enq_retry_idx_temp_vec_12 ? 6'hC : _stq_enq_retry_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_43 = stq_enq_retry_idx_temp_vec_11 ? 6'hB : _stq_enq_retry_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_44 = stq_enq_retry_idx_temp_vec_10 ? 6'hA : _stq_enq_retry_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_45 = stq_enq_retry_idx_temp_vec_9 ? 6'h9 : _stq_enq_retry_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_46 = stq_enq_retry_idx_temp_vec_8 ? 6'h8 : _stq_enq_retry_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_47 = stq_enq_retry_idx_temp_vec_7 ? 6'h7 : _stq_enq_retry_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_48 = stq_enq_retry_idx_temp_vec_6 ? 6'h6 : _stq_enq_retry_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_49 = stq_enq_retry_idx_temp_vec_5 ? 6'h5 : _stq_enq_retry_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_50 = stq_enq_retry_idx_temp_vec_4 ? 6'h4 : _stq_enq_retry_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_51 = stq_enq_retry_idx_temp_vec_3 ? 6'h3 : _stq_enq_retry_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_52 = stq_enq_retry_idx_temp_vec_2 ? 6'h2 : _stq_enq_retry_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _stq_enq_retry_idx_idx_T_53 = stq_enq_retry_idx_temp_vec_1 ? 6'h1 : _stq_enq_retry_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] stq_enq_retry_idx_idx = stq_enq_retry_idx_temp_vec_0 ? 6'h0 : _stq_enq_retry_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _stq_enq_retry_idx_T_72 = stq_enq_retry_idx_idx[4:0]; // @[Mux.scala:50:70] wire stq_enq_retry_e_valid = stq_enq_retry_e_e_valid; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_inst = stq_enq_retry_e_e_bits_uop_inst; // @[lsu.scala:262:17, :524:35] wire [31:0] stq_enq_retry_e_bits_uop_debug_inst = stq_enq_retry_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rvc = stq_enq_retry_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_uop_debug_pc = stq_enq_retry_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_0 = stq_enq_retry_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_1 = stq_enq_retry_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_2 = stq_enq_retry_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iq_type_3 = stq_enq_retry_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_0 = stq_enq_retry_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_1 = stq_enq_retry_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_2 = stq_enq_retry_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_3 = stq_enq_retry_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_4 = stq_enq_retry_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_5 = stq_enq_retry_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_6 = stq_enq_retry_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_7 = stq_enq_retry_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_8 = stq_enq_retry_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fu_code_9 = stq_enq_retry_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued = stq_enq_retry_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_agen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_issued_partial_dgen = stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_iw_p1_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_iw_p2_speculative_child = stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p1_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p2_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_iw_p3_bypass_hint = stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_dis_col_sel = stq_enq_retry_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :524:35] wire [15:0] stq_enq_retry_e_bits_uop_br_mask = stq_enq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_tag = stq_enq_retry_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :524:35] wire [3:0] stq_enq_retry_e_bits_uop_br_type = stq_enq_retry_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfb = stq_enq_retry_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fence = stq_enq_retry_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_fencei = stq_enq_retry_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sfence = stq_enq_retry_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_amo = stq_enq_retry_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_eret = stq_enq_retry_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_sys_pc2epc = stq_enq_retry_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_rocc = stq_enq_retry_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_mov = stq_enq_retry_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ftq_idx = stq_enq_retry_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_edge_inst = stq_enq_retry_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_pc_lob = stq_enq_retry_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_taken = stq_enq_retry_e_e_bits_uop_taken; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_imm_rename = stq_enq_retry_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_imm_sel = stq_enq_retry_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_pimm = stq_enq_retry_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :524:35] wire [19:0] stq_enq_retry_e_bits_uop_imm_packed = stq_enq_retry_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_op1_sel = stq_enq_retry_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_op2_sel = stq_enq_retry_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ldst = stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wen = stq_enq_retry_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren1 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren2 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_ren3 = stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap12 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_swap23 = stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fromint = stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_toint = stq_enq_retry_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe = stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_fma = stq_enq_retry_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_div = stq_enq_retry_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_sqrt = stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_wflags = stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_ctrl_vec = stq_enq_retry_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_rob_idx = stq_enq_retry_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ldq_idx = stq_enq_retry_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_stq_idx = stq_enq_retry_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_rxq_idx = stq_enq_retry_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_pdst = stq_enq_retry_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs1 = stq_enq_retry_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs2 = stq_enq_retry_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_prs3 = stq_enq_retry_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_ppred = stq_enq_retry_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs1_busy = stq_enq_retry_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs2_busy = stq_enq_retry_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_prs3_busy = stq_enq_retry_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ppred_busy = stq_enq_retry_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :524:35] wire [6:0] stq_enq_retry_e_bits_uop_stale_pdst = stq_enq_retry_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_exception = stq_enq_retry_e_e_bits_uop_exception; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_uop_exc_cause = stq_enq_retry_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_mem_cmd = stq_enq_retry_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_mem_size = stq_enq_retry_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_mem_signed = stq_enq_retry_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_ldq = stq_enq_retry_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_uses_stq = stq_enq_retry_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_is_unique = stq_enq_retry_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_flush_on_commit = stq_enq_retry_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_csr_cmd = stq_enq_retry_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_ldst_is_rs1 = stq_enq_retry_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_ldst = stq_enq_retry_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs1 = stq_enq_retry_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs2 = stq_enq_retry_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :524:35] wire [5:0] stq_enq_retry_e_bits_uop_lrs3 = stq_enq_retry_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_dst_rtype = stq_enq_retry_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs1_rtype = stq_enq_retry_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_lrs2_rtype = stq_enq_retry_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_frs3_en = stq_enq_retry_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fcn_dw = stq_enq_retry_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :524:35] wire [4:0] stq_enq_retry_e_bits_uop_fcn_op = stq_enq_retry_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_fp_val = stq_enq_retry_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_fp_rm = stq_enq_retry_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :524:35] wire [1:0] stq_enq_retry_e_bits_uop_fp_typ = stq_enq_retry_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_pf_if = stq_enq_retry_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ae_if = stq_enq_retry_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_xcpt_ma_if = stq_enq_retry_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_debug_if = stq_enq_retry_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_uop_bp_xcpt_if = stq_enq_retry_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_fsrc = stq_enq_retry_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :524:35] wire [2:0] stq_enq_retry_e_bits_uop_debug_tsrc = stq_enq_retry_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_valid = stq_enq_retry_e_e_bits_addr_valid; // @[lsu.scala:262:17, :524:35] wire [39:0] stq_enq_retry_e_bits_addr_bits = stq_enq_retry_e_e_bits_addr_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_addr_is_virtual = stq_enq_retry_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_data_valid = stq_enq_retry_e_e_bits_data_valid; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_data_bits = stq_enq_retry_e_e_bits_data_bits; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_committed = stq_enq_retry_e_e_bits_committed; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_succeeded = stq_enq_retry_e_e_bits_succeeded; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_can_execute = stq_enq_retry_e_e_bits_can_execute; // @[lsu.scala:262:17, :524:35] wire stq_enq_retry_e_bits_cleared = stq_enq_retry_e_e_bits_cleared; // @[lsu.scala:262:17, :524:35] wire [63:0] stq_enq_retry_e_bits_debug_wb_data = stq_enq_retry_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :524:35] assign stq_enq_retry_e_e_valid = _GEN_26[stq_enq_retry_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :520:30] assign stq_enq_retry_e_e_bits_uop_inst = _GEN_251[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_inst = _GEN_252[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rvc = _GEN_253[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_pc = _GEN_254[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_0 = _GEN_255[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_1 = _GEN_256[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_2 = _GEN_257[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iq_type_3 = _GEN_258[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_0 = _GEN_259[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_1 = _GEN_260[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_2 = _GEN_261[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_3 = _GEN_262[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_4 = _GEN_263[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_5 = _GEN_264[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_6 = _GEN_265[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_7 = _GEN_266[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_8 = _GEN_267[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fu_code_9 = _GEN_268[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued = _GEN_269[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dis_col_sel = _GEN_277[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_mask = _GEN_278[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_tag = _GEN_279[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_br_type = _GEN_280[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfb = _GEN_281[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fence = _GEN_282[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_fencei = _GEN_283[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sfence = _GEN_284[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_amo = _GEN_285[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_eret = _GEN_286[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_rocc = _GEN_288[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_mov = _GEN_289[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ftq_idx = _GEN_290[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_edge_inst = _GEN_291[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pc_lob = _GEN_292[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_taken = _GEN_293[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_rename = _GEN_294[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_sel = _GEN_295[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pimm = _GEN_296[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_imm_packed = _GEN_297[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op1_sel = _GEN_298[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_op2_sel = _GEN_299[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rob_idx = _GEN_317[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldq_idx = _GEN_318[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stq_idx = _GEN_319[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_rxq_idx = _GEN_320[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_pdst = _GEN_321[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1 = _GEN_322[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2 = _GEN_323[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3 = _GEN_324[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred = _GEN_325[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs1_busy = _GEN_326[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs2_busy = _GEN_327[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_prs3_busy = _GEN_328[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ppred_busy = _GEN_329[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_stale_pdst = _GEN_330[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exception = _GEN_331[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_exc_cause = _GEN_332[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_cmd = _GEN_333[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_size = _GEN_334[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_mem_signed = _GEN_335[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_ldq = _GEN_336[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_uses_stq = _GEN_337[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_is_unique = _GEN_338[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_flush_on_commit = _GEN_339[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_csr_cmd = _GEN_340[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_ldst = _GEN_342[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1 = _GEN_343[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2 = _GEN_344[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs3 = _GEN_345[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_dst_rtype = _GEN_346[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_frs3_en = _GEN_349[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_dw = _GEN_350[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fcn_op = _GEN_351[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_val = _GEN_352[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_rm = _GEN_353[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_fp_typ = _GEN_354[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_debug_if = _GEN_358[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_fsrc = _GEN_360[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_uop_debug_tsrc = _GEN_361[stq_enq_retry_idx]; // @[lsu.scala:262:17, :264:32, :520:30] assign stq_enq_retry_e_e_bits_addr_valid = _GEN_362[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_bits = _GEN_363[stq_enq_retry_idx]; // @[lsu.scala:262:17, :265:32, :520:30] assign stq_enq_retry_e_e_bits_addr_is_virtual = _GEN_364[stq_enq_retry_idx]; // @[lsu.scala:262:17, :266:32, :520:30] assign stq_enq_retry_e_e_bits_data_valid = _GEN_365[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_data_bits = _GEN_366[stq_enq_retry_idx]; // @[lsu.scala:262:17, :267:32, :520:30] assign stq_enq_retry_e_e_bits_committed = _GEN_367[stq_enq_retry_idx]; // @[lsu.scala:262:17, :268:32, :520:30] assign stq_enq_retry_e_e_bits_succeeded = _GEN_368[stq_enq_retry_idx]; // @[lsu.scala:262:17, :269:32, :520:30] assign stq_enq_retry_e_e_bits_can_execute = _GEN_369[stq_enq_retry_idx]; // @[lsu.scala:262:17, :270:32, :520:30] assign stq_enq_retry_e_e_bits_cleared = _GEN_370[stq_enq_retry_idx]; // @[lsu.scala:262:17, :271:32, :520:30] assign stq_enq_retry_e_e_bits_debug_wb_data = _GEN_371[stq_enq_retry_idx]; // @[lsu.scala:262:17, :272:32, :520:30] wire _can_enq_load_retry_T = ldq_enq_retry_e_valid & ldq_enq_retry_e_bits_addr_valid; // @[lsu.scala:518:33, :526:81] wire can_enq_load_retry = _can_enq_load_retry_T & ldq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:518:33, :526:81, :527:81] wire _can_enq_store_retry_T = stq_enq_retry_e_valid & stq_enq_retry_e_bits_addr_valid; // @[lsu.scala:524:35, :529:81] wire can_enq_store_retry = _can_enq_store_retry_T & stq_enq_retry_e_bits_addr_is_virtual; // @[lsu.scala:524:35, :529:81, :530:81] wire _retry_queue_io_enq_valid_T = can_enq_store_retry | can_enq_load_retry; // @[lsu.scala:527:81, :530:81, :537:55] wire [39:0] _retry_queue_io_enq_bits_data_T = can_enq_store_retry ? stq_enq_retry_e_bits_addr_bits : ldq_enq_retry_e_bits_addr_bits; // @[lsu.scala:518:33, :524:35, :530:81, :539:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_inst : ldq_enq_retry_e_bits_uop_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [31:0] _retry_queue_io_enq_bits_uop_T_debug_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_inst : ldq_enq_retry_e_bits_uop_debug_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rvc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rvc : ldq_enq_retry_e_bits_uop_is_rvc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [39:0] _retry_queue_io_enq_bits_uop_T_debug_pc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_pc : ldq_enq_retry_e_bits_uop_debug_pc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_0 : ldq_enq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_1 : ldq_enq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_2 : ldq_enq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iq_type_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iq_type_3 : ldq_enq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_0 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_0 : ldq_enq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_1 : ldq_enq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_2 : ldq_enq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_3 : ldq_enq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_4 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_4 : ldq_enq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_5 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_5 : ldq_enq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_6 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_6 : ldq_enq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_7 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_7 : ldq_enq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_8 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_8 : ldq_enq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fu_code_9 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fu_code_9 : ldq_enq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued : ldq_enq_retry_e_bits_uop_iw_issued; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_agen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_agen : ldq_enq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_issued_partial_dgen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_issued_partial_dgen : ldq_enq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_iw_p1_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_speculative_child : ldq_enq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_iw_p2_speculative_child = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_speculative_child : ldq_enq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p1_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p1_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p2_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p2_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_iw_p3_bypass_hint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_iw_p3_bypass_hint : ldq_enq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_dis_col_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dis_col_sel : ldq_enq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [15:0] _retry_queue_io_enq_bits_uop_T_br_mask = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_mask : ldq_enq_retry_e_bits_uop_br_mask; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_tag = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_tag : ldq_enq_retry_e_bits_uop_br_tag; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [3:0] _retry_queue_io_enq_bits_uop_T_br_type = can_enq_store_retry ? stq_enq_retry_e_bits_uop_br_type : ldq_enq_retry_e_bits_uop_br_type; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfb = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfb : ldq_enq_retry_e_bits_uop_is_sfb; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fence : ldq_enq_retry_e_bits_uop_is_fence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_fencei = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_fencei : ldq_enq_retry_e_bits_uop_is_fencei; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sfence = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sfence : ldq_enq_retry_e_bits_uop_is_sfence; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_amo = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_amo : ldq_enq_retry_e_bits_uop_is_amo; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_eret = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_eret : ldq_enq_retry_e_bits_uop_is_eret; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_sys_pc2epc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_sys_pc2epc : ldq_enq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_rocc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_rocc : ldq_enq_retry_e_bits_uop_is_rocc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_mov = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_mov : ldq_enq_retry_e_bits_uop_is_mov; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ftq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ftq_idx : ldq_enq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_edge_inst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_edge_inst : ldq_enq_retry_e_bits_uop_edge_inst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_pc_lob = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pc_lob : ldq_enq_retry_e_bits_uop_pc_lob; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_taken = can_enq_store_retry ? stq_enq_retry_e_bits_uop_taken : ldq_enq_retry_e_bits_uop_taken; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_imm_rename = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_rename : ldq_enq_retry_e_bits_uop_imm_rename; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_imm_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_sel : ldq_enq_retry_e_bits_uop_imm_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_pimm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pimm : ldq_enq_retry_e_bits_uop_pimm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [19:0] _retry_queue_io_enq_bits_uop_T_imm_packed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_imm_packed : ldq_enq_retry_e_bits_uop_imm_packed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_op1_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op1_sel : ldq_enq_retry_e_bits_uop_op1_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_op2_sel = can_enq_store_retry ? stq_enq_retry_e_bits_uop_op2_sel : ldq_enq_retry_e_bits_uop_op2_sel; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ldst : ldq_enq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wen = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wen : ldq_enq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren1 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren2 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_ren3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_ren3 : ldq_enq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap12 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap12 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_swap23 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_swap23 : ldq_enq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagIn = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_ctrl_typeTagOut = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut : ldq_enq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fromint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fromint : ldq_enq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_toint = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_toint : ldq_enq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fastpipe = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fastpipe : ldq_enq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_fma = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_fma : ldq_enq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_div = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_div : ldq_enq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_sqrt = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_sqrt : ldq_enq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_wflags = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_wflags : ldq_enq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_ctrl_vec = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_ctrl_vec : ldq_enq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_rob_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rob_idx : ldq_enq_retry_e_bits_uop_rob_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ldq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldq_idx : ldq_enq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_stq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stq_idx : ldq_enq_retry_e_bits_uop_stq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_rxq_idx = can_enq_store_retry ? stq_enq_retry_e_bits_uop_rxq_idx : ldq_enq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_pdst : ldq_enq_retry_e_bits_uop_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1 : ldq_enq_retry_e_bits_uop_prs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2 : ldq_enq_retry_e_bits_uop_prs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_prs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3 : ldq_enq_retry_e_bits_uop_prs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_ppred = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred : ldq_enq_retry_e_bits_uop_ppred; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs1_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs1_busy : ldq_enq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs2_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs2_busy : ldq_enq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_prs3_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_prs3_busy : ldq_enq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ppred_busy = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ppred_busy : ldq_enq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [6:0] _retry_queue_io_enq_bits_uop_T_stale_pdst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_stale_pdst : ldq_enq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_exception = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exception : ldq_enq_retry_e_bits_uop_exception; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [63:0] _retry_queue_io_enq_bits_uop_T_exc_cause = can_enq_store_retry ? stq_enq_retry_e_bits_uop_exc_cause : ldq_enq_retry_e_bits_uop_exc_cause; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_mem_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_cmd : ldq_enq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_mem_size = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_size : ldq_enq_retry_e_bits_uop_mem_size; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_mem_signed = can_enq_store_retry ? stq_enq_retry_e_bits_uop_mem_signed : ldq_enq_retry_e_bits_uop_mem_signed; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_ldq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_ldq : ldq_enq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_uses_stq = can_enq_store_retry ? stq_enq_retry_e_bits_uop_uses_stq : ldq_enq_retry_e_bits_uop_uses_stq; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_is_unique = can_enq_store_retry ? stq_enq_retry_e_bits_uop_is_unique : ldq_enq_retry_e_bits_uop_is_unique; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_flush_on_commit = can_enq_store_retry ? stq_enq_retry_e_bits_uop_flush_on_commit : ldq_enq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_csr_cmd = can_enq_store_retry ? stq_enq_retry_e_bits_uop_csr_cmd : ldq_enq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_ldst_is_rs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst_is_rs1 : ldq_enq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_ldst = can_enq_store_retry ? stq_enq_retry_e_bits_uop_ldst : ldq_enq_retry_e_bits_uop_ldst; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs1 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1 : ldq_enq_retry_e_bits_uop_lrs1; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs2 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2 : ldq_enq_retry_e_bits_uop_lrs2; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [5:0] _retry_queue_io_enq_bits_uop_T_lrs3 = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs3 : ldq_enq_retry_e_bits_uop_lrs3; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_dst_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_dst_rtype : ldq_enq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs1_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs1_rtype : ldq_enq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_lrs2_rtype = can_enq_store_retry ? stq_enq_retry_e_bits_uop_lrs2_rtype : ldq_enq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_frs3_en = can_enq_store_retry ? stq_enq_retry_e_bits_uop_frs3_en : ldq_enq_retry_e_bits_uop_frs3_en; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fcn_dw = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_dw : ldq_enq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [4:0] _retry_queue_io_enq_bits_uop_T_fcn_op = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fcn_op : ldq_enq_retry_e_bits_uop_fcn_op; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_fp_val = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_val : ldq_enq_retry_e_bits_uop_fp_val; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_fp_rm = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_rm : ldq_enq_retry_e_bits_uop_fp_rm; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [1:0] _retry_queue_io_enq_bits_uop_T_fp_typ = can_enq_store_retry ? stq_enq_retry_e_bits_uop_fp_typ : ldq_enq_retry_e_bits_uop_fp_typ; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_pf_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_pf_if : ldq_enq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ae_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ae_if : ldq_enq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_xcpt_ma_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_xcpt_ma_if : ldq_enq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_debug_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_debug_if : ldq_enq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_T_bp_xcpt_if = can_enq_store_retry ? stq_enq_retry_e_bits_uop_bp_xcpt_if : ldq_enq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_fsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_fsrc : ldq_enq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire [2:0] _retry_queue_io_enq_bits_uop_T_debug_tsrc = can_enq_store_retry ? stq_enq_retry_e_bits_uop_debug_tsrc : ldq_enq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:518:33, :524:35, :530:81, :540:38] wire _retry_queue_io_enq_bits_uop_uses_ldq_T = ~can_enq_store_retry; // @[lsu.scala:530:81, :541:65] wire _retry_queue_io_enq_bits_uop_uses_ldq_T_1 = can_enq_load_retry & _retry_queue_io_enq_bits_uop_uses_ldq_T; // @[lsu.scala:527:81, :541:{62,65}] wire _GEN_418 = will_fire_load_retry_0 | will_fire_store_retry_0; // @[lsu.scala:476:41, :477:41, :554:65] wire _retry_queue_io_deq_ready_T; // @[lsu.scala:554:65] assign _retry_queue_io_deq_ready_T = _GEN_418; // @[lsu.scala:554:65] wire _exe_tlb_uop_T_1; // @[lsu.scala:720:53] assign _exe_tlb_uop_T_1 = _GEN_418; // @[lsu.scala:554:65, :720:53] wire _exe_tlb_vaddr_T_2; // @[lsu.scala:730:53] assign _exe_tlb_vaddr_T_2 = _GEN_418; // @[lsu.scala:554:65, :730:53] wire stq_execute_queue_flush; // @[lsu.scala:556:41] wire stq_enq_e_valid = stq_enq_e_e_valid; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_inst = stq_enq_e_e_bits_uop_inst; // @[lsu.scala:262:17, :561:27] wire [31:0] stq_enq_e_bits_uop_debug_inst = stq_enq_e_e_bits_uop_debug_inst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rvc = stq_enq_e_e_bits_uop_is_rvc; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_uop_debug_pc = stq_enq_e_e_bits_uop_debug_pc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_0 = stq_enq_e_e_bits_uop_iq_type_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_1 = stq_enq_e_e_bits_uop_iq_type_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_2 = stq_enq_e_e_bits_uop_iq_type_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iq_type_3 = stq_enq_e_e_bits_uop_iq_type_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_0 = stq_enq_e_e_bits_uop_fu_code_0; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_1 = stq_enq_e_e_bits_uop_fu_code_1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_2 = stq_enq_e_e_bits_uop_fu_code_2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_3 = stq_enq_e_e_bits_uop_fu_code_3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_4 = stq_enq_e_e_bits_uop_fu_code_4; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_5 = stq_enq_e_e_bits_uop_fu_code_5; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_6 = stq_enq_e_e_bits_uop_fu_code_6; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_7 = stq_enq_e_e_bits_uop_fu_code_7; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_8 = stq_enq_e_e_bits_uop_fu_code_8; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fu_code_9 = stq_enq_e_e_bits_uop_fu_code_9; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued = stq_enq_e_e_bits_uop_iw_issued; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_agen = stq_enq_e_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_issued_partial_dgen = stq_enq_e_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_iw_p1_speculative_child = stq_enq_e_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_iw_p2_speculative_child = stq_enq_e_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p1_bypass_hint = stq_enq_e_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p2_bypass_hint = stq_enq_e_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_iw_p3_bypass_hint = stq_enq_e_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_dis_col_sel = stq_enq_e_e_bits_uop_dis_col_sel; // @[lsu.scala:262:17, :561:27] wire [15:0] stq_enq_e_bits_uop_br_mask = stq_enq_e_e_bits_uop_br_mask; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_tag = stq_enq_e_e_bits_uop_br_tag; // @[lsu.scala:262:17, :561:27] wire [3:0] stq_enq_e_bits_uop_br_type = stq_enq_e_e_bits_uop_br_type; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfb = stq_enq_e_e_bits_uop_is_sfb; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fence = stq_enq_e_e_bits_uop_is_fence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_fencei = stq_enq_e_e_bits_uop_is_fencei; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sfence = stq_enq_e_e_bits_uop_is_sfence; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_amo = stq_enq_e_e_bits_uop_is_amo; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_eret = stq_enq_e_e_bits_uop_is_eret; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_sys_pc2epc = stq_enq_e_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_rocc = stq_enq_e_e_bits_uop_is_rocc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_mov = stq_enq_e_e_bits_uop_is_mov; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ftq_idx = stq_enq_e_e_bits_uop_ftq_idx; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_edge_inst = stq_enq_e_e_bits_uop_edge_inst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_pc_lob = stq_enq_e_e_bits_uop_pc_lob; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_taken = stq_enq_e_e_bits_uop_taken; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_imm_rename = stq_enq_e_e_bits_uop_imm_rename; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_imm_sel = stq_enq_e_e_bits_uop_imm_sel; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_pimm = stq_enq_e_e_bits_uop_pimm; // @[lsu.scala:262:17, :561:27] wire [19:0] stq_enq_e_bits_uop_imm_packed = stq_enq_e_e_bits_uop_imm_packed; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_op1_sel = stq_enq_e_e_bits_uop_op1_sel; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_op2_sel = stq_enq_e_e_bits_uop_op2_sel; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ldst = stq_enq_e_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wen = stq_enq_e_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren1 = stq_enq_e_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren2 = stq_enq_e_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_ren3 = stq_enq_e_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap12 = stq_enq_e_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_swap23 = stq_enq_e_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagIn = stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_ctrl_typeTagOut = stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fromint = stq_enq_e_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_toint = stq_enq_e_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fastpipe = stq_enq_e_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_fma = stq_enq_e_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_div = stq_enq_e_e_bits_uop_fp_ctrl_div; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_sqrt = stq_enq_e_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_wflags = stq_enq_e_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_ctrl_vec = stq_enq_e_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_rob_idx = stq_enq_e_e_bits_uop_rob_idx; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ldq_idx = stq_enq_e_e_bits_uop_ldq_idx; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_stq_idx = stq_enq_e_e_bits_uop_stq_idx; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_rxq_idx = stq_enq_e_e_bits_uop_rxq_idx; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_pdst = stq_enq_e_e_bits_uop_pdst; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs1 = stq_enq_e_e_bits_uop_prs1; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs2 = stq_enq_e_e_bits_uop_prs2; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_prs3 = stq_enq_e_e_bits_uop_prs3; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_ppred = stq_enq_e_e_bits_uop_ppred; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs1_busy = stq_enq_e_e_bits_uop_prs1_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs2_busy = stq_enq_e_e_bits_uop_prs2_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_prs3_busy = stq_enq_e_e_bits_uop_prs3_busy; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ppred_busy = stq_enq_e_e_bits_uop_ppred_busy; // @[lsu.scala:262:17, :561:27] wire [6:0] stq_enq_e_bits_uop_stale_pdst = stq_enq_e_e_bits_uop_stale_pdst; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_exception = stq_enq_e_e_bits_uop_exception; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_uop_exc_cause = stq_enq_e_e_bits_uop_exc_cause; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_mem_cmd = stq_enq_e_e_bits_uop_mem_cmd; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_mem_size = stq_enq_e_e_bits_uop_mem_size; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_mem_signed = stq_enq_e_e_bits_uop_mem_signed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_ldq = stq_enq_e_e_bits_uop_uses_ldq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_uses_stq = stq_enq_e_e_bits_uop_uses_stq; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_is_unique = stq_enq_e_e_bits_uop_is_unique; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_flush_on_commit = stq_enq_e_e_bits_uop_flush_on_commit; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_csr_cmd = stq_enq_e_e_bits_uop_csr_cmd; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_ldst_is_rs1 = stq_enq_e_e_bits_uop_ldst_is_rs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_ldst = stq_enq_e_e_bits_uop_ldst; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs1 = stq_enq_e_e_bits_uop_lrs1; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs2 = stq_enq_e_e_bits_uop_lrs2; // @[lsu.scala:262:17, :561:27] wire [5:0] stq_enq_e_bits_uop_lrs3 = stq_enq_e_e_bits_uop_lrs3; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_dst_rtype = stq_enq_e_e_bits_uop_dst_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs1_rtype = stq_enq_e_e_bits_uop_lrs1_rtype; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_lrs2_rtype = stq_enq_e_e_bits_uop_lrs2_rtype; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_frs3_en = stq_enq_e_e_bits_uop_frs3_en; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fcn_dw = stq_enq_e_e_bits_uop_fcn_dw; // @[lsu.scala:262:17, :561:27] wire [4:0] stq_enq_e_bits_uop_fcn_op = stq_enq_e_e_bits_uop_fcn_op; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_fp_val = stq_enq_e_e_bits_uop_fp_val; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_fp_rm = stq_enq_e_e_bits_uop_fp_rm; // @[lsu.scala:262:17, :561:27] wire [1:0] stq_enq_e_bits_uop_fp_typ = stq_enq_e_e_bits_uop_fp_typ; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_pf_if = stq_enq_e_e_bits_uop_xcpt_pf_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ae_if = stq_enq_e_e_bits_uop_xcpt_ae_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_xcpt_ma_if = stq_enq_e_e_bits_uop_xcpt_ma_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_debug_if = stq_enq_e_e_bits_uop_bp_debug_if; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_uop_bp_xcpt_if = stq_enq_e_e_bits_uop_bp_xcpt_if; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_fsrc = stq_enq_e_e_bits_uop_debug_fsrc; // @[lsu.scala:262:17, :561:27] wire [2:0] stq_enq_e_bits_uop_debug_tsrc = stq_enq_e_e_bits_uop_debug_tsrc; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_valid = stq_enq_e_e_bits_addr_valid; // @[lsu.scala:262:17, :561:27] wire [39:0] stq_enq_e_bits_addr_bits = stq_enq_e_e_bits_addr_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_addr_is_virtual = stq_enq_e_e_bits_addr_is_virtual; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_data_valid = stq_enq_e_e_bits_data_valid; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_data_bits = stq_enq_e_e_bits_data_bits; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_committed = stq_enq_e_e_bits_committed; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_succeeded = stq_enq_e_e_bits_succeeded; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_can_execute = stq_enq_e_e_bits_can_execute; // @[lsu.scala:262:17, :561:27] wire stq_enq_e_bits_cleared = stq_enq_e_e_bits_cleared; // @[lsu.scala:262:17, :561:27] wire [63:0] stq_enq_e_bits_debug_wb_data = stq_enq_e_e_bits_debug_wb_data; // @[lsu.scala:262:17, :561:27] assign stq_enq_e_e_bits_uop_inst = _GEN_251[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_inst = _GEN_252[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rvc = _GEN_253[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_pc = _GEN_254[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_0 = _GEN_255[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_1 = _GEN_256[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_2 = _GEN_257[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iq_type_3 = _GEN_258[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_0 = _GEN_259[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_1 = _GEN_260[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_2 = _GEN_261[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_3 = _GEN_262[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_4 = _GEN_263[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_5 = _GEN_264[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_6 = _GEN_265[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_7 = _GEN_266[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_8 = _GEN_267[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fu_code_9 = _GEN_268[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued = _GEN_269[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dis_col_sel = _GEN_277[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_mask = _GEN_278[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_tag = _GEN_279[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_br_type = _GEN_280[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfb = _GEN_281[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fence = _GEN_282[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_fencei = _GEN_283[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sfence = _GEN_284[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_amo = _GEN_285[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_eret = _GEN_286[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_sys_pc2epc = _GEN_287[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_rocc = _GEN_288[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_mov = _GEN_289[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ftq_idx = _GEN_290[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_edge_inst = _GEN_291[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pc_lob = _GEN_292[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_taken = _GEN_293[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_rename = _GEN_294[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_sel = _GEN_295[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pimm = _GEN_296[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_imm_packed = _GEN_297[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op1_sel = _GEN_298[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_op2_sel = _GEN_299[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wen = _GEN_301[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_toint = _GEN_310[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_fma = _GEN_312[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_div = _GEN_313[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_ctrl_vec = _GEN_316[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rob_idx = _GEN_317[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldq_idx = _GEN_318[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stq_idx = _GEN_319[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_rxq_idx = _GEN_320[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_pdst = _GEN_321[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1 = _GEN_322[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2 = _GEN_323[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3 = _GEN_324[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred = _GEN_325[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs1_busy = _GEN_326[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs2_busy = _GEN_327[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_prs3_busy = _GEN_328[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ppred_busy = _GEN_329[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_stale_pdst = _GEN_330[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exception = _GEN_331[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_exc_cause = _GEN_332[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_cmd = _GEN_333[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_size = _GEN_334[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_mem_signed = _GEN_335[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_ldq = _GEN_336[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_uses_stq = _GEN_337[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_is_unique = _GEN_338[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_flush_on_commit = _GEN_339[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_csr_cmd = _GEN_340[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst_is_rs1 = _GEN_341[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_ldst = _GEN_342[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1 = _GEN_343[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2 = _GEN_344[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs3 = _GEN_345[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_dst_rtype = _GEN_346[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs1_rtype = _GEN_347[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_lrs2_rtype = _GEN_348[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_frs3_en = _GEN_349[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_dw = _GEN_350[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fcn_op = _GEN_351[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_val = _GEN_352[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_rm = _GEN_353[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_fp_typ = _GEN_354[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_pf_if = _GEN_355[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ae_if = _GEN_356[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_xcpt_ma_if = _GEN_357[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_debug_if = _GEN_358[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_bp_xcpt_if = _GEN_359[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_fsrc = _GEN_360[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_uop_debug_tsrc = _GEN_361[stq_execute_head]; // @[lsu.scala:262:17, :264:32, :283:29] assign stq_enq_e_e_bits_addr_valid = _GEN_362[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_bits = _GEN_363[stq_execute_head]; // @[lsu.scala:262:17, :265:32, :283:29] assign stq_enq_e_e_bits_addr_is_virtual = _GEN_364[stq_execute_head]; // @[lsu.scala:262:17, :266:32, :283:29] assign stq_enq_e_e_bits_data_valid = _GEN_365[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_data_bits = _GEN_366[stq_execute_head]; // @[lsu.scala:262:17, :267:32, :283:29] assign stq_enq_e_e_bits_committed = _GEN_367[stq_execute_head]; // @[lsu.scala:262:17, :268:32, :283:29] assign stq_enq_e_e_bits_succeeded = _GEN_368[stq_execute_head]; // @[lsu.scala:262:17, :269:32, :283:29] assign stq_enq_e_e_bits_can_execute = _GEN_369[stq_execute_head]; // @[lsu.scala:262:17, :270:32, :283:29] assign stq_enq_e_e_bits_cleared = _GEN_370[stq_execute_head]; // @[lsu.scala:262:17, :271:32, :283:29] assign stq_enq_e_e_bits_debug_wb_data = _GEN_371[stq_execute_head]; // @[lsu.scala:262:17, :272:32, :283:29] wire _T_1639 = will_fire_store_commit_fast_0 | will_fire_store_commit_slow_0; // @[lsu.scala:478:41, :479:41, :565:78] wire _stq_execute_queue_io_deq_ready_T; // @[lsu.scala:565:78] assign _stq_execute_queue_io_deq_ready_T = _T_1639; // @[lsu.scala:565:78] wire _fired_store_commit_T; // @[lsu.scala:1048:83] assign _fired_store_commit_T = _T_1639; // @[lsu.scala:565:78, :1048:83] wire _can_enq_store_execute_T = stq_enq_e_valid & stq_enq_e_bits_addr_valid; // @[lsu.scala:561:27, :568:21] wire _can_enq_store_execute_T_1 = _can_enq_store_execute_T & stq_enq_e_bits_data_valid; // @[lsu.scala:561:27, :568:21, :569:31] wire _can_enq_store_execute_T_2 = ~stq_enq_e_bits_addr_is_virtual; // @[lsu.scala:561:27, :571:4] wire _can_enq_store_execute_T_3 = _can_enq_store_execute_T_1 & _can_enq_store_execute_T_2; // @[lsu.scala:569:31, :570:31, :571:4] wire _can_enq_store_execute_T_4 = ~stq_enq_e_bits_uop_exception; // @[lsu.scala:561:27, :572:4] wire _can_enq_store_execute_T_5 = _can_enq_store_execute_T_3 & _can_enq_store_execute_T_4; // @[lsu.scala:570:31, :571:36, :572:4] wire _can_enq_store_execute_T_6 = ~stq_enq_e_bits_uop_is_fence; // @[lsu.scala:561:27, :573:4] wire _can_enq_store_execute_T_7 = _can_enq_store_execute_T_5 & _can_enq_store_execute_T_6; // @[lsu.scala:571:36, :572:34, :573:4] wire _can_enq_store_execute_T_8 = stq_enq_e_bits_committed | stq_enq_e_bits_uop_is_amo; // @[lsu.scala:561:27, :574:30] wire can_enq_store_execute = _can_enq_store_execute_T_7 & _can_enq_store_execute_T_8; // @[lsu.scala:572:34, :573:33, :574:30] wire _GEN_419 = stq_execute_head == 5'h17; // @[util.scala:213:25] wire stq_execute_head_wrap; // @[util.scala:213:25] assign stq_execute_head_wrap = _GEN_419; // @[util.scala:213:25] wire stq_execute_head_wrap_1; // @[util.scala:213:25] assign stq_execute_head_wrap_1 = _GEN_419; // @[util.scala:213:25] wire [5:0] _GEN_420 = {1'h0, stq_execute_head} + 6'h1; // @[util.scala:214:28] wire [5:0] _stq_execute_head_T; // @[util.scala:214:28] assign _stq_execute_head_T = _GEN_420; // @[util.scala:214:28] wire [5:0] _stq_execute_head_T_3; // @[util.scala:214:28] assign _stq_execute_head_T_3 = _GEN_420; // @[util.scala:214:28] wire [4:0] _stq_execute_head_T_1 = _stq_execute_head_T[4:0]; // @[util.scala:214:28] wire [4:0] _stq_execute_head_T_2 = stq_execute_head_wrap ? 5'h0 : _stq_execute_head_T_1; // @[util.scala:213:25, :214:{10,28}] wire _can_fire_load_agen_exec_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :586:61] wire can_fire_load_agen_exec_0 = _can_fire_load_agen_exec_T; // @[lsu.scala:321:49, :586:61] wire _can_fire_store_agen_T = io_core_agen_0_valid_0 & io_core_agen_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :590:61] wire can_fire_store_agen_0 = _can_fire_store_agen_T; // @[lsu.scala:321:49, :590:61] wire _will_fire_sfence_0_will_fire_T_3 = can_fire_sfence_0; // @[lsu.scala:321:49, :656:32] wire can_fire_release_0 = _can_fire_release_T; // @[lsu.scala:321:49, :598:66] wire _will_fire_release_0_will_fire_T_3 = can_fire_release_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_load_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :603:79] reg can_fire_load_retry_REG; // @[lsu.scala:605:41] wire _can_fire_load_retry_T_1 = ~can_fire_load_retry_REG; // @[lsu.scala:605:{33,41}] wire _can_fire_load_retry_T_2 = _can_fire_load_retry_T & _can_fire_load_retry_T_1; // @[lsu.scala:603:79, :604:79, :605:33] wire _can_fire_load_retry_T_3 = _can_fire_load_retry_T_2; // @[lsu.scala:604:79, :605:79] wire can_fire_load_retry_0 = _can_fire_load_retry_T_3; // @[lsu.scala:321:49, :605:79] wire _can_fire_store_retry_T = _retry_queue_io_deq_valid & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :610:79] wire _can_fire_store_retry_T_1 = _can_fire_store_retry_T; // @[lsu.scala:610:79, :611:79] wire can_fire_store_retry_0 = _can_fire_store_retry_T_1; // @[lsu.scala:321:49, :611:79] wire _can_fire_store_commit_slow_T = ~mem_xcpt_valid; // @[lsu.scala:457:29, :617:38] wire _can_fire_store_commit_slow_T_1 = _stq_execute_queue_io_deq_valid & _can_fire_store_commit_slow_T; // @[lsu.scala:558:11, :616:84, :617:38] wire _can_fire_store_commit_slow_T_2 = _can_fire_store_commit_slow_T_1; // @[lsu.scala:616:84, :617:84] wire can_fire_store_commit_slow_0 = _can_fire_store_commit_slow_T_2; // @[lsu.scala:321:49, :617:84] wire _will_fire_store_commit_slow_0_will_fire_T_3 = can_fire_store_commit_slow_0; // @[lsu.scala:321:49, :656:32] wire _can_fire_store_commit_fast_T = can_fire_store_commit_slow_0 & stq_almost_full; // @[lsu.scala:321:49, :494:32, :620:80] wire can_fire_store_commit_fast_0 = _can_fire_store_commit_fast_T; // @[lsu.scala:321:49, :620:80] wire _will_fire_store_commit_fast_0_will_fire_T_3 = can_fire_store_commit_fast_0; // @[lsu.scala:321:49, :656:32] wire block_load_wakeup; // @[lsu.scala:623:35] wire _can_fire_load_wakeup_T = ldq_wakeup_e_valid & ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:510:32, :625:88] wire _can_fire_load_wakeup_T_1 = ~ldq_wakeup_e_bits_succeeded; // @[lsu.scala:510:32, :627:31] wire _can_fire_load_wakeup_T_2 = _can_fire_load_wakeup_T & _can_fire_load_wakeup_T_1; // @[lsu.scala:625:88, :626:88, :627:31] wire _can_fire_load_wakeup_T_3 = ~ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:510:32, :628:31] wire _can_fire_load_wakeup_T_4 = _can_fire_load_wakeup_T_2 & _can_fire_load_wakeup_T_3; // @[lsu.scala:626:88, :627:88, :628:31] wire _can_fire_load_wakeup_T_5 = ~ldq_wakeup_e_bits_executed; // @[lsu.scala:510:32, :629:31] wire _can_fire_load_wakeup_T_6 = _can_fire_load_wakeup_T_4 & _can_fire_load_wakeup_T_5; // @[lsu.scala:627:88, :628:88, :629:31] wire _can_fire_load_wakeup_T_7 = ~ldq_wakeup_e_bits_order_fail; // @[lsu.scala:510:32, :630:31] wire _can_fire_load_wakeup_T_8 = _can_fire_load_wakeup_T_6 & _can_fire_load_wakeup_T_7; // @[lsu.scala:628:88, :629:88, :630:31] wire [4:0] _can_fire_load_wakeup_T_10 = _can_fire_load_wakeup_T_9; wire [31:0] _GEN_421 = {{p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_0}, {p1_block_load_mask_23}, {p1_block_load_mask_22}, {p1_block_load_mask_21}, {p1_block_load_mask_20}, {p1_block_load_mask_19}, {p1_block_load_mask_18}, {p1_block_load_mask_17}, {p1_block_load_mask_16}, {p1_block_load_mask_15}, {p1_block_load_mask_14}, {p1_block_load_mask_13}, {p1_block_load_mask_12}, {p1_block_load_mask_11}, {p1_block_load_mask_10}, {p1_block_load_mask_9}, {p1_block_load_mask_8}, {p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}}; // @[lsu.scala:489:35, :631:31] wire _can_fire_load_wakeup_T_11 = ~_GEN_421[_can_fire_load_wakeup_T_10]; // @[lsu.scala:631:31] wire _can_fire_load_wakeup_T_12 = _can_fire_load_wakeup_T_8 & _can_fire_load_wakeup_T_11; // @[lsu.scala:629:88, :630:88, :631:31] wire [4:0] _can_fire_load_wakeup_T_14 = _can_fire_load_wakeup_T_13; wire [31:0] _GEN_422 = {{p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_0}, {p2_block_load_mask_23}, {p2_block_load_mask_22}, {p2_block_load_mask_21}, {p2_block_load_mask_20}, {p2_block_load_mask_19}, {p2_block_load_mask_18}, {p2_block_load_mask_17}, {p2_block_load_mask_16}, {p2_block_load_mask_15}, {p2_block_load_mask_14}, {p2_block_load_mask_13}, {p2_block_load_mask_12}, {p2_block_load_mask_11}, {p2_block_load_mask_10}, {p2_block_load_mask_9}, {p2_block_load_mask_8}, {p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}}; // @[lsu.scala:490:35, :632:31] wire _can_fire_load_wakeup_T_15 = ~_GEN_422[_can_fire_load_wakeup_T_14]; // @[lsu.scala:632:31] wire _can_fire_load_wakeup_T_16 = _can_fire_load_wakeup_T_12 & _can_fire_load_wakeup_T_15; // @[lsu.scala:630:88, :631:88, :632:31] reg can_fire_load_wakeup_REG; // @[lsu.scala:633:39] wire _can_fire_load_wakeup_T_17 = ~can_fire_load_wakeup_REG; // @[lsu.scala:633:{31,39}] wire _can_fire_load_wakeup_T_18 = _can_fire_load_wakeup_T_16 & _can_fire_load_wakeup_T_17; // @[lsu.scala:631:88, :632:88, :633:31] wire _can_fire_load_wakeup_T_19 = ~block_load_wakeup; // @[lsu.scala:623:35, :634:31] wire _can_fire_load_wakeup_T_20 = _can_fire_load_wakeup_T_18 & _can_fire_load_wakeup_T_19; // @[lsu.scala:632:88, :633:88, :634:31] wire _can_fire_load_wakeup_T_21 = _can_fire_load_wakeup_T_20; // @[lsu.scala:633:88, :634:88] wire _can_fire_load_wakeup_T_22 = ~ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:510:32, :636:32] wire _can_fire_load_wakeup_T_23 = ldq_head == ldq_wakeup_idx; // @[lsu.scala:278:29, :506:31, :637:84] wire _can_fire_load_wakeup_T_24 = io_core_commit_load_at_rob_head_0 & _can_fire_load_wakeup_T_23; // @[lsu.scala:211:7, :636:107, :637:84] wire _can_fire_load_wakeup_T_25 = ldq_wakeup_e_bits_st_dep_mask == 24'h0; // @[lsu.scala:510:32, :638:112] wire _can_fire_load_wakeup_T_26 = _can_fire_load_wakeup_T_24 & _can_fire_load_wakeup_T_25; // @[lsu.scala:636:107, :637:103, :638:112] wire _can_fire_load_wakeup_T_27 = _can_fire_load_wakeup_T_22 | _can_fire_load_wakeup_T_26; // @[lsu.scala:636:{32,71}, :637:103] wire _can_fire_load_wakeup_T_28 = _can_fire_load_wakeup_T_21 & _can_fire_load_wakeup_T_27; // @[lsu.scala:634:88, :635:88, :636:71] wire can_fire_load_wakeup_0 = _can_fire_load_wakeup_T_28; // @[lsu.scala:321:49, :635:88] wire _will_fire_load_wakeup_0_will_fire_T_3 = can_fire_load_wakeup_0; // @[lsu.scala:321:49, :656:32] wire can_fire_hella_incoming_0; // @[lsu.scala:641:42] wire can_fire_hella_wakeup_0; // @[lsu.scala:644:42] wire _will_fire_hella_wakeup_0_will_fire_T_3 = can_fire_hella_wakeup_0; // @[lsu.scala:644:42, :656:32] wire _exe_tlb_valid_0_T; // @[lsu.scala:696:25] wire exe_tlb_valid_0; // @[lsu.scala:649:27] wire _will_fire_sfence_0_will_fire_T_7 = _will_fire_sfence_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_sfence_0_will_fire = _will_fire_sfence_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_sfence_0 = will_fire_sfence_0_will_fire; // @[lsu.scala:472:41, :657:65] wire _will_fire_sfence_0_T = will_fire_sfence_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_sfence_0_T_1 = ~_will_fire_sfence_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_sfence_0_T_2 = _will_fire_sfence_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_commit_fast_0_T_2 = _will_fire_sfence_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_commit_fast_0_will_fire_T = ~_will_fire_sfence_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_fast_0_will_fire_T_7 = _will_fire_store_commit_fast_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] assign will_fire_store_commit_fast_0_will_fire = _will_fire_store_commit_fast_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] assign will_fire_store_commit_fast_0 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:478:41, :657:65] wire _will_fire_store_commit_fast_0_T_6 = will_fire_store_commit_fast_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_fast_0_T_7 = ~_will_fire_store_commit_fast_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_fast_0_T_8 = _will_fire_store_commit_fast_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_exec_0_will_fire_T = ~_will_fire_store_commit_fast_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_exec_0_will_fire_T_1 = _will_fire_load_agen_exec_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_exec_0_will_fire_T_2 = ~_will_fire_load_agen_exec_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_exec_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_exec_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_exec_0_will_fire_T_7 = _will_fire_load_agen_exec_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_load_agen_exec_0_will_fire_T_8 = ~_will_fire_store_commit_fast_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_agen_exec_0_will_fire_T_9 = _will_fire_load_agen_exec_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_agen_exec_0_will_fire_T_10 = ~_will_fire_load_agen_exec_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_agen_exec_0_will_fire = _will_fire_load_agen_exec_0_will_fire_T_7 & _will_fire_load_agen_exec_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_agen_exec_0 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:469:39, :657:65] wire _will_fire_load_agen_exec_0_T = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_exec_0_T_3 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_exec_0_T_6 = will_fire_load_agen_exec_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_agen_exec_0_T_1 = ~_will_fire_load_agen_exec_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_exec_0_T_2 = _will_fire_store_commit_fast_0_T_2 & _will_fire_load_agen_exec_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_exec_0_T_4 = ~_will_fire_load_agen_exec_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_exec_0_T_5 = _will_fire_load_agen_exec_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_agen_exec_0_T_7 = ~_will_fire_load_agen_exec_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_agen_exec_0_T_8 = _will_fire_store_commit_fast_0_T_8 & _will_fire_load_agen_exec_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_agen_0_T_8 = _will_fire_load_agen_exec_0_T_8; // @[lsu.scala:661:31] wire _will_fire_load_agen_0_will_fire_T = ~_will_fire_load_agen_exec_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_agen_0_will_fire_T_1 = _will_fire_load_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_agen_0_will_fire_T_2 = ~_will_fire_load_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_agen_0_will_fire_T_3 = can_fire_load_agen_exec_0 & _will_fire_load_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_agen_0_will_fire_T_4 = ~_will_fire_load_agen_exec_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_agen_0_will_fire_T_5 = _will_fire_load_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_agen_0_will_fire_T_6 = ~_will_fire_load_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_agen_0_will_fire_T_7 = _will_fire_load_agen_0_will_fire_T_3 & _will_fire_load_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_load_agen_0_will_fire = _will_fire_load_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_load_agen_0_will_fire_T_8 = ~_will_fire_load_agen_exec_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_load_agen_0 = will_fire_load_agen_0_will_fire; // @[lsu.scala:470:41, :657:65] wire _will_fire_load_agen_0_T = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_agen_0_T_3 = will_fire_load_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_agen_0_T_1 = ~_will_fire_load_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_agen_0_T_2 = _will_fire_load_agen_exec_0_T_2 & _will_fire_load_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_agen_0_T_4 = ~_will_fire_load_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_agen_0_T_5 = _will_fire_load_agen_exec_0_T_5 & _will_fire_load_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_agen_0_T_8 = _will_fire_load_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_agen_0_will_fire_T = ~_will_fire_load_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_agen_0_will_fire_T_1 = _will_fire_store_agen_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_agen_0_will_fire_T_2 = ~_will_fire_store_agen_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_agen_0_will_fire_T_3 = can_fire_store_agen_0 & _will_fire_store_agen_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_agen_0_will_fire_T_4 = ~_will_fire_load_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_agen_0_will_fire_T_5 = _will_fire_store_agen_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_agen_0_will_fire_T_6 = ~_will_fire_store_agen_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_agen_0_will_fire_T_7 = _will_fire_store_agen_0_will_fire_T_3 & _will_fire_store_agen_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_agen_0_will_fire = _will_fire_store_agen_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_agen_0_will_fire_T_8 = ~_will_fire_load_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_agen_0 = will_fire_store_agen_0_will_fire; // @[lsu.scala:471:41, :657:65] wire _will_fire_store_agen_0_T = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_agen_0_T_3 = will_fire_store_agen_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_agen_0_T_1 = ~_will_fire_store_agen_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_agen_0_T_2 = _will_fire_load_agen_0_T_2 & _will_fire_store_agen_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_release_0_T_2 = _will_fire_store_agen_0_T_2; // @[lsu.scala:659:31] wire _will_fire_store_agen_0_T_4 = ~_will_fire_store_agen_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_agen_0_T_5 = _will_fire_load_agen_0_T_5 & _will_fire_store_agen_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_release_0_T_8 = _will_fire_store_agen_0_T_8; // @[lsu.scala:661:31] wire _will_fire_release_0_will_fire_T = ~_will_fire_store_agen_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_release_0_will_fire_T_4 = ~_will_fire_store_agen_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_release_0_will_fire_T_5 = _will_fire_release_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_release_0_will_fire_T_6 = ~_will_fire_release_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_release_0_will_fire_T_7 = _will_fire_release_0_will_fire_T_3 & _will_fire_release_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_release_0_will_fire = _will_fire_release_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_release_0_will_fire_T_8 = ~_will_fire_store_agen_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_release_0 = will_fire_release_0_will_fire; // @[lsu.scala:475:41, :657:65] wire _will_fire_release_0_T_3 = will_fire_release_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_release_0_T_4 = ~_will_fire_release_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_release_0_T_5 = _will_fire_store_agen_0_T_5 & _will_fire_release_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_hella_incoming_0_T_5 = _will_fire_release_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_will_fire_T = ~_will_fire_release_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_incoming_0_will_fire_T_1 = _will_fire_hella_incoming_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_hella_incoming_0_will_fire_T_2 = ~_will_fire_hella_incoming_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_hella_incoming_0_will_fire_T_3 = can_fire_hella_incoming_0 & _will_fire_hella_incoming_0_will_fire_T_2; // @[lsu.scala:641:42, :656:{32,35}] wire _will_fire_hella_incoming_0_will_fire_T_7 = _will_fire_hella_incoming_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_incoming_0_will_fire_T_4 = ~_will_fire_release_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_incoming_0_will_fire_T_8 = ~_will_fire_release_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_incoming_0_will_fire_T_9 = _will_fire_hella_incoming_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_incoming_0_will_fire_T_10 = ~_will_fire_hella_incoming_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_incoming_0_will_fire = _will_fire_hella_incoming_0_will_fire_T_7 & _will_fire_hella_incoming_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_incoming_0 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:473:41, :657:65] wire _will_fire_hella_incoming_0_T = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_hella_incoming_0_T_6 = will_fire_hella_incoming_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_incoming_0_T_1 = ~_will_fire_hella_incoming_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_hella_incoming_0_T_2 = _will_fire_release_0_T_2 & _will_fire_hella_incoming_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_hella_wakeup_0_T_2 = _will_fire_hella_incoming_0_T_2; // @[lsu.scala:659:31] wire _will_fire_hella_wakeup_0_T_5 = _will_fire_hella_incoming_0_T_5; // @[lsu.scala:660:31] wire _will_fire_hella_incoming_0_T_7 = ~_will_fire_hella_incoming_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_incoming_0_T_8 = _will_fire_release_0_T_8 & _will_fire_hella_incoming_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_hella_wakeup_0_will_fire_T = ~_will_fire_hella_incoming_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_hella_wakeup_0_will_fire_T_7 = _will_fire_hella_wakeup_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_hella_wakeup_0_will_fire_T_4 = ~_will_fire_hella_incoming_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_hella_wakeup_0_will_fire_T_8 = ~_will_fire_hella_incoming_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_hella_wakeup_0_will_fire_T_9 = _will_fire_hella_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~_will_fire_hella_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_hella_wakeup_0_will_fire = _will_fire_hella_wakeup_0_will_fire_T_7 & _will_fire_hella_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_hella_wakeup_0 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:474:41, :657:65] wire _will_fire_hella_wakeup_0_T_6 = will_fire_hella_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_hella_wakeup_0_T_7 = ~_will_fire_hella_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_hella_wakeup_0_T_8 = _will_fire_hella_incoming_0_T_8 & _will_fire_hella_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_retry_0_T_8 = _will_fire_hella_wakeup_0_T_8; // @[lsu.scala:661:31] wire _will_fire_store_retry_0_will_fire_T = ~_will_fire_hella_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_retry_0_will_fire_T_1 = _will_fire_store_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_store_retry_0_will_fire_T_2 = ~_will_fire_store_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_store_retry_0_will_fire_T_3 = can_fire_store_retry_0 & _will_fire_store_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_store_retry_0_will_fire_T_4 = ~_will_fire_hella_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_retry_0_will_fire_T_5 = _will_fire_store_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_store_retry_0_will_fire_T_6 = ~_will_fire_store_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_store_retry_0_will_fire_T_7 = _will_fire_store_retry_0_will_fire_T_3 & _will_fire_store_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] assign will_fire_store_retry_0_will_fire = _will_fire_store_retry_0_will_fire_T_7; // @[lsu.scala:656:63, :657:65] wire _will_fire_store_retry_0_will_fire_T_8 = ~_will_fire_hella_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] assign will_fire_store_retry_0 = will_fire_store_retry_0_will_fire; // @[lsu.scala:477:41, :657:65] wire _will_fire_store_retry_0_T = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_store_retry_0_T_3 = will_fire_store_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_store_retry_0_T_1 = ~_will_fire_store_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_store_retry_0_T_2 = _will_fire_hella_wakeup_0_T_2 & _will_fire_store_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_store_retry_0_T_4 = ~_will_fire_store_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_store_retry_0_T_5 = _will_fire_hella_wakeup_0_T_5 & _will_fire_store_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_will_fire_T = ~_will_fire_store_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_retry_0_will_fire_T_1 = _will_fire_load_retry_0_will_fire_T; // @[lsu.scala:656:{48,51}] wire _will_fire_load_retry_0_will_fire_T_2 = ~_will_fire_load_retry_0_will_fire_T_1; // @[lsu.scala:656:{35,48}] wire _will_fire_load_retry_0_will_fire_T_3 = can_fire_load_retry_0 & _will_fire_load_retry_0_will_fire_T_2; // @[lsu.scala:321:49, :656:{32,35}] wire _will_fire_load_retry_0_will_fire_T_4 = ~_will_fire_store_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_retry_0_will_fire_T_5 = _will_fire_load_retry_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_retry_0_will_fire_T_6 = ~_will_fire_load_retry_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_retry_0_will_fire_T_7 = _will_fire_load_retry_0_will_fire_T_3 & _will_fire_load_retry_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_retry_0_will_fire_T_8 = ~_will_fire_store_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_retry_0_will_fire_T_9 = _will_fire_load_retry_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_retry_0_will_fire_T_10 = ~_will_fire_load_retry_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_retry_0_will_fire = _will_fire_load_retry_0_will_fire_T_7 & _will_fire_load_retry_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_retry_0 = will_fire_load_retry_0_will_fire; // @[lsu.scala:476:41, :657:65] wire _will_fire_load_retry_0_T = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :659:46] wire _will_fire_load_retry_0_T_3 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_retry_0_T_6 = will_fire_load_retry_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_load_retry_0_T_1 = ~_will_fire_load_retry_0_T; // @[lsu.scala:659:{34,46}] wire _will_fire_load_retry_0_T_2 = _will_fire_store_retry_0_T_2 & _will_fire_load_retry_0_T_1; // @[lsu.scala:659:{31,34}] wire _will_fire_load_wakeup_0_T_2 = _will_fire_load_retry_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_retry_0_T_4 = ~_will_fire_load_retry_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_retry_0_T_5 = _will_fire_store_retry_0_T_5 & _will_fire_load_retry_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_load_retry_0_T_7 = ~_will_fire_load_retry_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_retry_0_T_8 = _will_fire_store_retry_0_T_8 & _will_fire_load_retry_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_load_wakeup_0_will_fire_T = ~_will_fire_load_retry_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_load_wakeup_0_will_fire_T_4 = ~_will_fire_load_retry_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_load_wakeup_0_will_fire_T_5 = _will_fire_load_wakeup_0_will_fire_T_4; // @[lsu.scala:657:{49,52}] wire _will_fire_load_wakeup_0_will_fire_T_6 = ~_will_fire_load_wakeup_0_will_fire_T_5; // @[lsu.scala:657:{35,49}] wire _will_fire_load_wakeup_0_will_fire_T_7 = _will_fire_load_wakeup_0_will_fire_T_3 & _will_fire_load_wakeup_0_will_fire_T_6; // @[lsu.scala:656:{32,63}, :657:35] wire _will_fire_load_wakeup_0_will_fire_T_8 = ~_will_fire_load_retry_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_load_wakeup_0_will_fire_T_9 = _will_fire_load_wakeup_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_load_wakeup_0_will_fire_T_10 = ~_will_fire_load_wakeup_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_load_wakeup_0_will_fire = _will_fire_load_wakeup_0_will_fire_T_7 & _will_fire_load_wakeup_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_load_wakeup_0 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:480:41, :657:65] wire _will_fire_load_wakeup_0_T_3 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :660:46] wire _will_fire_load_wakeup_0_T_6 = will_fire_load_wakeup_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_2 = _will_fire_load_wakeup_0_T_2; // @[lsu.scala:659:31] wire _will_fire_load_wakeup_0_T_4 = ~_will_fire_load_wakeup_0_T_3; // @[lsu.scala:660:{34,46}] wire _will_fire_load_wakeup_0_T_5 = _will_fire_load_retry_0_T_5 & _will_fire_load_wakeup_0_T_4; // @[lsu.scala:660:{31,34}] wire _will_fire_store_commit_slow_0_T_5 = _will_fire_load_wakeup_0_T_5; // @[lsu.scala:660:31] wire _will_fire_load_wakeup_0_T_7 = ~_will_fire_load_wakeup_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_load_wakeup_0_T_8 = _will_fire_load_retry_0_T_8 & _will_fire_load_wakeup_0_T_7; // @[lsu.scala:661:{31,34}] wire _will_fire_store_commit_slow_0_will_fire_T = ~_will_fire_load_wakeup_0_T_2; // @[lsu.scala:656:51, :659:31] wire _will_fire_store_commit_slow_0_will_fire_T_7 = _will_fire_store_commit_slow_0_will_fire_T_3; // @[lsu.scala:656:{32,63}] wire _will_fire_store_commit_slow_0_will_fire_T_4 = ~_will_fire_load_wakeup_0_T_5; // @[lsu.scala:657:52, :660:31] wire _will_fire_store_commit_slow_0_will_fire_T_8 = ~_will_fire_load_wakeup_0_T_8; // @[lsu.scala:658:50, :661:31] wire _will_fire_store_commit_slow_0_will_fire_T_9 = _will_fire_store_commit_slow_0_will_fire_T_8; // @[lsu.scala:658:{47,50}] wire _will_fire_store_commit_slow_0_will_fire_T_10 = ~_will_fire_store_commit_slow_0_will_fire_T_9; // @[lsu.scala:658:{35,47}] assign will_fire_store_commit_slow_0_will_fire = _will_fire_store_commit_slow_0_will_fire_T_7 & _will_fire_store_commit_slow_0_will_fire_T_10; // @[lsu.scala:656:63, :657:65, :658:35] assign will_fire_store_commit_slow_0 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:479:41, :657:65] wire _will_fire_store_commit_slow_0_T_6 = will_fire_store_commit_slow_0_will_fire; // @[lsu.scala:657:65, :661:46] wire _will_fire_store_commit_slow_0_T_7 = ~_will_fire_store_commit_slow_0_T_6; // @[lsu.scala:661:{34,46}] wire _will_fire_store_commit_slow_0_T_8 = _will_fire_load_wakeup_0_T_8 & _will_fire_store_commit_slow_0_T_7; // @[lsu.scala:661:{31,34}] wire _T_226 = will_fire_load_agen_exec_0 | will_fire_load_agen_0; // @[lsu.scala:469:39, :470:41, :687:61] wire _exe_tlb_uop_T; // @[lsu.scala:717:53] assign _exe_tlb_uop_T = _T_226; // @[lsu.scala:687:61, :717:53] wire _exe_tlb_vaddr_T; // @[lsu.scala:726:53] assign _exe_tlb_vaddr_T = _T_226; // @[lsu.scala:687:61, :726:53] wire _exe_size_T; // @[lsu.scala:738:52] assign _exe_size_T = _T_226; // @[lsu.scala:687:61, :738:52] wire _exe_cmd_T; // @[lsu.scala:746:52] assign _exe_cmd_T = _T_226; // @[lsu.scala:687:61, :746:52] wire _ldq_idx_T; // @[lsu.scala:969:48] assign _ldq_idx_T = _T_226; // @[lsu.scala:687:61, :969:48] wire _GEN_423 = ldq_wakeup_idx == 5'h0; // @[lsu.scala:506:31, :690:49] wire _GEN_424 = ldq_wakeup_idx == 5'h1; // @[lsu.scala:506:31, :690:49] wire _GEN_425 = ldq_wakeup_idx == 5'h2; // @[lsu.scala:506:31, :690:49] wire _GEN_426 = ldq_wakeup_idx == 5'h3; // @[lsu.scala:506:31, :690:49] wire _GEN_427 = ldq_wakeup_idx == 5'h4; // @[lsu.scala:506:31, :690:49] wire _GEN_428 = ldq_wakeup_idx == 5'h5; // @[lsu.scala:506:31, :690:49] wire _GEN_429 = ldq_wakeup_idx == 5'h6; // @[lsu.scala:506:31, :690:49] wire _GEN_430 = ldq_wakeup_idx == 5'h7; // @[lsu.scala:506:31, :690:49] wire _GEN_431 = ldq_wakeup_idx == 5'h8; // @[lsu.scala:506:31, :690:49] wire _GEN_432 = ldq_wakeup_idx == 5'h9; // @[lsu.scala:506:31, :690:49] wire _GEN_433 = ldq_wakeup_idx == 5'hA; // @[lsu.scala:506:31, :690:49] wire _GEN_434 = ldq_wakeup_idx == 5'hB; // @[lsu.scala:506:31, :690:49] wire _GEN_435 = ldq_wakeup_idx == 5'hC; // @[lsu.scala:506:31, :690:49] wire _GEN_436 = ldq_wakeup_idx == 5'hD; // @[lsu.scala:506:31, :690:49] wire _GEN_437 = ldq_wakeup_idx == 5'hE; // @[lsu.scala:506:31, :690:49] wire _GEN_438 = ldq_wakeup_idx == 5'hF; // @[lsu.scala:506:31, :690:49] wire _GEN_439 = ldq_wakeup_idx == 5'h10; // @[lsu.scala:506:31, :690:49] wire _GEN_440 = ldq_wakeup_idx == 5'h11; // @[lsu.scala:506:31, :690:49] wire _GEN_441 = ldq_wakeup_idx == 5'h12; // @[lsu.scala:506:31, :690:49] wire _GEN_442 = ldq_wakeup_idx == 5'h13; // @[lsu.scala:506:31, :690:49] wire _GEN_443 = ldq_wakeup_idx == 5'h14; // @[lsu.scala:506:31, :690:49] wire _GEN_444 = ldq_wakeup_idx == 5'h15; // @[lsu.scala:506:31, :690:49] wire _GEN_445 = ldq_wakeup_idx == 5'h16; // @[lsu.scala:506:31, :690:49] wire _GEN_446 = ldq_wakeup_idx == 5'h17; // @[lsu.scala:506:31, :690:49] wire _GEN_447 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h0; // @[lsu.scala:533:27, :694:49] assign block_load_mask_0 = will_fire_load_wakeup_0 ? _GEN_423 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h0 : will_fire_load_retry_0 & _GEN_447; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_448 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h1; // @[lsu.scala:533:27, :694:49] assign block_load_mask_1 = will_fire_load_wakeup_0 ? _GEN_424 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h1 : will_fire_load_retry_0 & _GEN_448; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_449 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h2; // @[lsu.scala:533:27, :694:49] assign block_load_mask_2 = will_fire_load_wakeup_0 ? _GEN_425 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h2 : will_fire_load_retry_0 & _GEN_449; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_450 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h3; // @[lsu.scala:533:27, :694:49] assign block_load_mask_3 = will_fire_load_wakeup_0 ? _GEN_426 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h3 : will_fire_load_retry_0 & _GEN_450; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_451 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h4; // @[lsu.scala:533:27, :694:49] assign block_load_mask_4 = will_fire_load_wakeup_0 ? _GEN_427 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h4 : will_fire_load_retry_0 & _GEN_451; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_452 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h5; // @[lsu.scala:533:27, :694:49] assign block_load_mask_5 = will_fire_load_wakeup_0 ? _GEN_428 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h5 : will_fire_load_retry_0 & _GEN_452; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_453 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h6; // @[lsu.scala:533:27, :694:49] assign block_load_mask_6 = will_fire_load_wakeup_0 ? _GEN_429 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h6 : will_fire_load_retry_0 & _GEN_453; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_454 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h7; // @[lsu.scala:533:27, :694:49] assign block_load_mask_7 = will_fire_load_wakeup_0 ? _GEN_430 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h7 : will_fire_load_retry_0 & _GEN_454; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_455 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h8; // @[lsu.scala:533:27, :694:49] assign block_load_mask_8 = will_fire_load_wakeup_0 ? _GEN_431 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h8 : will_fire_load_retry_0 & _GEN_455; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_456 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h9; // @[lsu.scala:533:27, :694:49] assign block_load_mask_9 = will_fire_load_wakeup_0 ? _GEN_432 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h9 : will_fire_load_retry_0 & _GEN_456; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_457 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hA; // @[lsu.scala:533:27, :694:49] assign block_load_mask_10 = will_fire_load_wakeup_0 ? _GEN_433 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hA : will_fire_load_retry_0 & _GEN_457; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_458 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hB; // @[lsu.scala:533:27, :694:49] assign block_load_mask_11 = will_fire_load_wakeup_0 ? _GEN_434 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hB : will_fire_load_retry_0 & _GEN_458; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_459 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hC; // @[lsu.scala:533:27, :694:49] assign block_load_mask_12 = will_fire_load_wakeup_0 ? _GEN_435 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hC : will_fire_load_retry_0 & _GEN_459; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_460 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hD; // @[lsu.scala:533:27, :694:49] assign block_load_mask_13 = will_fire_load_wakeup_0 ? _GEN_436 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hD : will_fire_load_retry_0 & _GEN_460; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_461 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hE; // @[lsu.scala:533:27, :694:49] assign block_load_mask_14 = will_fire_load_wakeup_0 ? _GEN_437 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hE : will_fire_load_retry_0 & _GEN_461; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_462 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'hF; // @[lsu.scala:533:27, :694:49] assign block_load_mask_15 = will_fire_load_wakeup_0 ? _GEN_438 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'hF : will_fire_load_retry_0 & _GEN_462; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_463 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h10; // @[lsu.scala:533:27, :694:49] assign block_load_mask_16 = will_fire_load_wakeup_0 ? _GEN_439 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h10 : will_fire_load_retry_0 & _GEN_463; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_464 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h11; // @[lsu.scala:533:27, :694:49] assign block_load_mask_17 = will_fire_load_wakeup_0 ? _GEN_440 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h11 : will_fire_load_retry_0 & _GEN_464; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_465 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h12; // @[lsu.scala:533:27, :694:49] assign block_load_mask_18 = will_fire_load_wakeup_0 ? _GEN_441 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h12 : will_fire_load_retry_0 & _GEN_465; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_466 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h13; // @[lsu.scala:533:27, :694:49] assign block_load_mask_19 = will_fire_load_wakeup_0 ? _GEN_442 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h13 : will_fire_load_retry_0 & _GEN_466; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_467 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h14; // @[lsu.scala:533:27, :694:49] assign block_load_mask_20 = will_fire_load_wakeup_0 ? _GEN_443 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h14 : will_fire_load_retry_0 & _GEN_467; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_468 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h15; // @[lsu.scala:533:27, :694:49] assign block_load_mask_21 = will_fire_load_wakeup_0 ? _GEN_444 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h15 : will_fire_load_retry_0 & _GEN_468; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_469 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h16; // @[lsu.scala:533:27, :694:49] assign block_load_mask_22 = will_fire_load_wakeup_0 ? _GEN_445 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h16 : will_fire_load_retry_0 & _GEN_469; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] wire _GEN_470 = _retry_queue_io_deq_bits_uop_ldq_idx == 5'h17; // @[lsu.scala:533:27, :694:49] assign block_load_mask_23 = will_fire_load_wakeup_0 ? _GEN_446 : _T_226 ? io_core_agen_0_bits_uop_ldq_idx_0 == 5'h17 : will_fire_load_retry_0 & _GEN_470; // @[lsu.scala:211:7, :476:41, :480:41, :488:36, :687:61, :689:37, :690:49, :691:73, :692:49, :693:43, :694:49] assign _exe_tlb_valid_0_T = ~_will_fire_store_commit_slow_0_T_2; // @[lsu.scala:659:31, :696:25] assign exe_tlb_valid_0 = _exe_tlb_valid_0_T; // @[lsu.scala:649:27, :696:25] wire [31:0] _exe_tlb_uop_T_3_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_3_debug_inst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_inst : 32'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rvc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rvc; // @[lsu.scala:533:27, :720:{24,53}] wire [39:0] _exe_tlb_uop_T_3_debug_pc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_pc : 40'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iq_type_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iq_type_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_0 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_4 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_4; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_5 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_5; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_6 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_6; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_7 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_7; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_8 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_8; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fu_code_9 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fu_code_9; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_agen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_agen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_issued_partial_dgen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_iw_p1_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_iw_p2_speculative_child = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p1_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p2_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_iw_p3_bypass_hint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_dis_col_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [15:0] _exe_tlb_uop_T_3_br_mask = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_mask : 16'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_tag = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_tag : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [3:0] _exe_tlb_uop_T_3_br_type = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_br_type : 4'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfb = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfb; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_fencei = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_fencei; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sfence = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sfence; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_amo = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_amo; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_eret = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_eret; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_sys_pc2epc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_sys_pc2epc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_rocc = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_rocc; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_mov = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_mov; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ftq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_edge_inst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_edge_inst; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_pc_lob = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pc_lob : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_taken = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_taken; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_imm_rename = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_imm_rename; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_imm_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_pimm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pimm : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [19:0] _exe_tlb_uop_T_3_imm_packed = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_imm_packed : 20'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_op1_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op1_sel : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_op2_sel = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_op2_sel : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ldst = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ldst; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wen = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wen; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren1; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren2 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren2; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_ren3 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_ren3; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap12 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap12; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_swap23 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_swap23; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagIn = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_ctrl_typeTagOut = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fromint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fromint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_toint = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_toint; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fastpipe = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_fma = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_fma; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_div = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_div; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_sqrt = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_wflags = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_wflags; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_ctrl_vec = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_ctrl_vec; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_rob_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rob_idx : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ldq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_stq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stq_idx : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_rxq_idx = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs1 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs2 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_prs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_prs3 : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_ppred = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ppred : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs1_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs1_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs2_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs2_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_prs3_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_prs3_busy; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ppred_busy = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ppred_busy; // @[lsu.scala:533:27, :720:{24,53}] wire [6:0] _exe_tlb_uop_T_3_stale_pdst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_exception = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_exception; // @[lsu.scala:533:27, :720:{24,53}] wire [63:0] _exe_tlb_uop_T_3_exc_cause = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_exc_cause : 64'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_mem_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_mem_size = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_mem_size : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_mem_signed = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_mem_signed; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_ldq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_ldq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_uses_stq = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_uses_stq; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_is_unique = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_is_unique; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_flush_on_commit = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_flush_on_commit; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_csr_cmd = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_ldst_is_rs1 = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_ldst_is_rs1; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_ldst = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_ldst : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs1 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs2 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [5:0] _exe_tlb_uop_T_3_lrs3 = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs3 : 6'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_dst_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs1_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_lrs2_rtype = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_frs3_en = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_frs3_en; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fcn_dw = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fcn_dw; // @[lsu.scala:533:27, :720:{24,53}] wire [4:0] _exe_tlb_uop_T_3_fcn_op = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fcn_op : 5'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_fp_val = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_fp_val; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_fp_rm = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_rm : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [1:0] _exe_tlb_uop_T_3_fp_typ = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_fp_typ : 2'h0; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_pf_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_pf_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ae_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ae_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_xcpt_ma_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_xcpt_ma_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_debug_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_debug_if; // @[lsu.scala:533:27, :720:{24,53}] wire _exe_tlb_uop_T_3_bp_xcpt_if = _exe_tlb_uop_T_1 & _retry_queue_io_deq_bits_uop_bp_xcpt_if; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_fsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [2:0] _exe_tlb_uop_T_3_debug_tsrc = _exe_tlb_uop_T_1 ? _retry_queue_io_deq_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:533:27, :720:{24,53}] wire [31:0] _exe_tlb_uop_T_4_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_3_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_4_debug_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_3_debug_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rvc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_3_is_rvc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [39:0] _exe_tlb_uop_T_4_debug_pc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_3_debug_pc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_3_iq_type_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_3_iq_type_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_3_iq_type_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iq_type_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_3_iq_type_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_0 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_3_fu_code_0; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_3_fu_code_1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_3_fu_code_2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_3_fu_code_3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_4 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_3_fu_code_4; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_5 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_3_fu_code_5; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_6 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_3_fu_code_6; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_7 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_3_fu_code_7; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_8 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_3_fu_code_8; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fu_code_9 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_3_fu_code_9; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_3_iw_issued; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_agen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_3_iw_issued_partial_agen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_issued_partial_dgen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_3_iw_issued_partial_dgen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_iw_p1_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_3_iw_p1_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_iw_p2_speculative_child = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_3_iw_p2_speculative_child; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p1_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_3_iw_p1_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p2_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_3_iw_p2_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_iw_p3_bypass_hint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_3_iw_p3_bypass_hint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_dis_col_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_3_dis_col_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [15:0] _exe_tlb_uop_T_4_br_mask = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_3_br_mask; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_tag = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_3_br_tag; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [3:0] _exe_tlb_uop_T_4_br_type = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_3_br_type; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfb = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_3_is_sfb; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_3_is_fence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_fencei = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_3_is_fencei; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sfence = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_3_is_sfence; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_amo = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_3_is_amo; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_eret = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_3_is_eret; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_sys_pc2epc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_3_is_sys_pc2epc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_rocc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_3_is_rocc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_mov = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_3_is_mov; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ftq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_3_ftq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_edge_inst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_3_edge_inst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_pc_lob = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_3_pc_lob; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_taken = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_3_taken; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_imm_rename = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_3_imm_rename; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_imm_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_3_imm_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_pimm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_3_pimm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [19:0] _exe_tlb_uop_T_4_imm_packed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_3_imm_packed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_op1_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_3_op1_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_op2_sel = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_3_op2_sel; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_3_fp_ctrl_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wen = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_3_fp_ctrl_wen; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_3_fp_ctrl_ren1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_3_fp_ctrl_ren2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_ren3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_3_fp_ctrl_ren3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap12 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_3_fp_ctrl_swap12; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_swap23 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_3_fp_ctrl_swap23; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagIn = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_3_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_ctrl_typeTagOut = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_3_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fromint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_3_fp_ctrl_fromint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_toint = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_3_fp_ctrl_toint; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fastpipe = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_3_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_fma = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_3_fp_ctrl_fma; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_div = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_3_fp_ctrl_div; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_sqrt = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_3_fp_ctrl_sqrt; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_wflags = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_3_fp_ctrl_wflags; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_ctrl_vec = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_3_fp_ctrl_vec; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_rob_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_3_rob_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ldq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_3_ldq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_stq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_3_stq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_rxq_idx = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_3_rxq_idx; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_3_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_3_prs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_3_prs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_prs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_3_prs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_ppred = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_3_ppred; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs1_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_3_prs1_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs2_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_3_prs2_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_prs3_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_3_prs3_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ppred_busy = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_3_ppred_busy; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [6:0] _exe_tlb_uop_T_4_stale_pdst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_3_stale_pdst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_exception = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_3_exception; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [63:0] _exe_tlb_uop_T_4_exc_cause = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_3_exc_cause; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_mem_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_3_mem_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_mem_size = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_3_mem_size; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_mem_signed = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_3_mem_signed; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_ldq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_3_uses_ldq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_uses_stq = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_3_uses_stq; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_is_unique = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_3_is_unique; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_flush_on_commit = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_3_flush_on_commit; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_csr_cmd = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_3_csr_cmd; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_ldst_is_rs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_3_ldst_is_rs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_ldst = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_3_ldst; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs1 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_3_lrs1; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs2 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_3_lrs2; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [5:0] _exe_tlb_uop_T_4_lrs3 = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_3_lrs3; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_dst_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_3_dst_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs1_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_3_lrs1_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_lrs2_rtype = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_3_lrs2_rtype; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_frs3_en = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_3_frs3_en; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fcn_dw = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_3_fcn_dw; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [4:0] _exe_tlb_uop_T_4_fcn_op = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_3_fcn_op; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_fp_val = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_3_fp_val; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_fp_rm = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_3_fp_rm; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [1:0] _exe_tlb_uop_T_4_fp_typ = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_3_fp_typ; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_pf_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_3_xcpt_pf_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ae_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_3_xcpt_ae_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_xcpt_ma_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_3_xcpt_ma_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_debug_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_3_bp_debug_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire _exe_tlb_uop_T_4_bp_xcpt_if = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_3_bp_xcpt_if; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_fsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_3_debug_fsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [2:0] _exe_tlb_uop_T_4_debug_tsrc = will_fire_store_agen_0 ? stq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_3_debug_tsrc; // @[lsu.scala:321:49, :471:41, :719:24, :720:24] wire [31:0] _exe_tlb_uop_T_5_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_inst : _exe_tlb_uop_T_4_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] _exe_tlb_uop_T_5_debug_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_inst : _exe_tlb_uop_T_4_debug_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rvc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rvc : _exe_tlb_uop_T_4_is_rvc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [39:0] _exe_tlb_uop_T_5_debug_pc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_pc : _exe_tlb_uop_T_4_debug_pc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_0 : _exe_tlb_uop_T_4_iq_type_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_1 : _exe_tlb_uop_T_4_iq_type_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_2 : _exe_tlb_uop_T_4_iq_type_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iq_type_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iq_type_3 : _exe_tlb_uop_T_4_iq_type_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_0 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_0 : _exe_tlb_uop_T_4_fu_code_0; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_1 : _exe_tlb_uop_T_4_fu_code_1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_2 : _exe_tlb_uop_T_4_fu_code_2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_3 : _exe_tlb_uop_T_4_fu_code_3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_4 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_4 : _exe_tlb_uop_T_4_fu_code_4; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_5 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_5 : _exe_tlb_uop_T_4_fu_code_5; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_6 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_6 : _exe_tlb_uop_T_4_fu_code_6; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_7 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_7 : _exe_tlb_uop_T_4_fu_code_7; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_8 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_8 : _exe_tlb_uop_T_4_fu_code_8; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fu_code_9 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fu_code_9 : _exe_tlb_uop_T_4_fu_code_9; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued : _exe_tlb_uop_T_4_iw_issued; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_agen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _exe_tlb_uop_T_4_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_issued_partial_dgen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _exe_tlb_uop_T_4_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_iw_p1_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _exe_tlb_uop_T_4_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_iw_p2_speculative_child = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _exe_tlb_uop_T_4_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p1_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _exe_tlb_uop_T_4_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p2_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _exe_tlb_uop_T_4_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_iw_p3_bypass_hint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _exe_tlb_uop_T_4_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_dis_col_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dis_col_sel : _exe_tlb_uop_T_4_dis_col_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [15:0] _exe_tlb_uop_T_5_br_mask = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_mask : _exe_tlb_uop_T_4_br_mask; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_tag = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_tag : _exe_tlb_uop_T_4_br_tag; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [3:0] _exe_tlb_uop_T_5_br_type = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_br_type : _exe_tlb_uop_T_4_br_type; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfb = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfb : _exe_tlb_uop_T_4_is_sfb; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fence : _exe_tlb_uop_T_4_is_fence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_fencei = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_fencei : _exe_tlb_uop_T_4_is_fencei; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sfence = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sfence : _exe_tlb_uop_T_4_is_sfence; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_amo = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_amo : _exe_tlb_uop_T_4_is_amo; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_eret = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_eret : _exe_tlb_uop_T_4_is_eret; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_sys_pc2epc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _exe_tlb_uop_T_4_is_sys_pc2epc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_rocc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_rocc : _exe_tlb_uop_T_4_is_rocc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_mov = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_mov : _exe_tlb_uop_T_4_is_mov; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ftq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ftq_idx : _exe_tlb_uop_T_4_ftq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_edge_inst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_edge_inst : _exe_tlb_uop_T_4_edge_inst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_pc_lob = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pc_lob : _exe_tlb_uop_T_4_pc_lob; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_taken = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_taken : _exe_tlb_uop_T_4_taken; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_imm_rename = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_rename : _exe_tlb_uop_T_4_imm_rename; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_imm_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_sel : _exe_tlb_uop_T_4_imm_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_pimm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pimm : _exe_tlb_uop_T_4_pimm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [19:0] _exe_tlb_uop_T_5_imm_packed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_imm_packed : _exe_tlb_uop_T_4_imm_packed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_op1_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op1_sel : _exe_tlb_uop_T_4_op1_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_op2_sel = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_op2_sel : _exe_tlb_uop_T_4_op2_sel; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _exe_tlb_uop_T_4_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wen = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _exe_tlb_uop_T_4_fp_ctrl_wen; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _exe_tlb_uop_T_4_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _exe_tlb_uop_T_4_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_ren3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _exe_tlb_uop_T_4_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap12 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _exe_tlb_uop_T_4_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_swap23 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _exe_tlb_uop_T_4_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagIn = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _exe_tlb_uop_T_4_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_ctrl_typeTagOut = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _exe_tlb_uop_T_4_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fromint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _exe_tlb_uop_T_4_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_toint = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _exe_tlb_uop_T_4_fp_ctrl_toint; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fastpipe = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _exe_tlb_uop_T_4_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_fma = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _exe_tlb_uop_T_4_fp_ctrl_fma; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_div = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_div : _exe_tlb_uop_T_4_fp_ctrl_div; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_sqrt = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _exe_tlb_uop_T_4_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_wflags = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _exe_tlb_uop_T_4_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_ctrl_vec = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _exe_tlb_uop_T_4_fp_ctrl_vec; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_rob_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rob_idx : _exe_tlb_uop_T_4_rob_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ldq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldq_idx : _exe_tlb_uop_T_4_ldq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_stq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stq_idx : _exe_tlb_uop_T_4_stq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_rxq_idx = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_rxq_idx : _exe_tlb_uop_T_4_rxq_idx; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_pdst : _exe_tlb_uop_T_4_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1 : _exe_tlb_uop_T_4_prs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2 : _exe_tlb_uop_T_4_prs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_prs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3 : _exe_tlb_uop_T_4_prs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_ppred = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred : _exe_tlb_uop_T_4_ppred; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs1_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs1_busy : _exe_tlb_uop_T_4_prs1_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs2_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs2_busy : _exe_tlb_uop_T_4_prs2_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_prs3_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_prs3_busy : _exe_tlb_uop_T_4_prs3_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ppred_busy = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ppred_busy : _exe_tlb_uop_T_4_ppred_busy; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [6:0] _exe_tlb_uop_T_5_stale_pdst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_stale_pdst : _exe_tlb_uop_T_4_stale_pdst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_exception = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exception : _exe_tlb_uop_T_4_exception; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [63:0] _exe_tlb_uop_T_5_exc_cause = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_exc_cause : _exe_tlb_uop_T_4_exc_cause; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_mem_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_cmd : _exe_tlb_uop_T_4_mem_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_mem_size = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_size : _exe_tlb_uop_T_4_mem_size; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_mem_signed = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_mem_signed : _exe_tlb_uop_T_4_mem_signed; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_ldq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_ldq : _exe_tlb_uop_T_4_uses_ldq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_uses_stq = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_uses_stq : _exe_tlb_uop_T_4_uses_stq; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_is_unique = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_is_unique : _exe_tlb_uop_T_4_is_unique; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_flush_on_commit = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_flush_on_commit : _exe_tlb_uop_T_4_flush_on_commit; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_csr_cmd = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_csr_cmd : _exe_tlb_uop_T_4_csr_cmd; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_ldst_is_rs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _exe_tlb_uop_T_4_ldst_is_rs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_ldst = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_ldst : _exe_tlb_uop_T_4_ldst; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs1 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1 : _exe_tlb_uop_T_4_lrs1; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs2 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2 : _exe_tlb_uop_T_4_lrs2; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [5:0] _exe_tlb_uop_T_5_lrs3 = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs3 : _exe_tlb_uop_T_4_lrs3; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_dst_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_dst_rtype : _exe_tlb_uop_T_4_dst_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs1_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs1_rtype : _exe_tlb_uop_T_4_lrs1_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_lrs2_rtype = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_lrs2_rtype : _exe_tlb_uop_T_4_lrs2_rtype; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_frs3_en = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_frs3_en : _exe_tlb_uop_T_4_frs3_en; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fcn_dw = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_dw : _exe_tlb_uop_T_4_fcn_dw; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [4:0] _exe_tlb_uop_T_5_fcn_op = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fcn_op : _exe_tlb_uop_T_4_fcn_op; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_fp_val = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_val : _exe_tlb_uop_T_4_fp_val; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_fp_rm = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_rm : _exe_tlb_uop_T_4_fp_rm; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [1:0] _exe_tlb_uop_T_5_fp_typ = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_fp_typ : _exe_tlb_uop_T_4_fp_typ; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_pf_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_pf_if : _exe_tlb_uop_T_4_xcpt_pf_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ae_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ae_if : _exe_tlb_uop_T_4_xcpt_ae_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_xcpt_ma_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_xcpt_ma_if : _exe_tlb_uop_T_4_xcpt_ma_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_debug_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_debug_if : _exe_tlb_uop_T_4_bp_debug_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire _exe_tlb_uop_T_5_bp_xcpt_if = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_bp_xcpt_if : _exe_tlb_uop_T_4_bp_xcpt_if; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_fsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_fsrc : _exe_tlb_uop_T_4_debug_fsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [2:0] _exe_tlb_uop_T_5_debug_tsrc = _exe_tlb_uop_T ? ldq_incoming_e_0_bits_uop_debug_tsrc : _exe_tlb_uop_T_4_debug_tsrc; // @[lsu.scala:321:49, :717:{24,53}, :719:24] wire [31:0] exe_tlb_uop_0_inst = _exe_tlb_uop_T_5_inst; // @[lsu.scala:321:49, :717:24] wire [31:0] exe_tlb_uop_0_debug_inst = _exe_tlb_uop_T_5_debug_inst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rvc = _exe_tlb_uop_T_5_is_rvc; // @[lsu.scala:321:49, :717:24] wire [39:0] exe_tlb_uop_0_debug_pc = _exe_tlb_uop_T_5_debug_pc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_0 = _exe_tlb_uop_T_5_iq_type_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_1 = _exe_tlb_uop_T_5_iq_type_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_2 = _exe_tlb_uop_T_5_iq_type_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iq_type_3 = _exe_tlb_uop_T_5_iq_type_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_0 = _exe_tlb_uop_T_5_fu_code_0; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_1 = _exe_tlb_uop_T_5_fu_code_1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_2 = _exe_tlb_uop_T_5_fu_code_2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_3 = _exe_tlb_uop_T_5_fu_code_3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_4 = _exe_tlb_uop_T_5_fu_code_4; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_5 = _exe_tlb_uop_T_5_fu_code_5; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_6 = _exe_tlb_uop_T_5_fu_code_6; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_7 = _exe_tlb_uop_T_5_fu_code_7; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_8 = _exe_tlb_uop_T_5_fu_code_8; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fu_code_9 = _exe_tlb_uop_T_5_fu_code_9; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued = _exe_tlb_uop_T_5_iw_issued; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_agen = _exe_tlb_uop_T_5_iw_issued_partial_agen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_issued_partial_dgen = _exe_tlb_uop_T_5_iw_issued_partial_dgen; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_iw_p1_speculative_child = _exe_tlb_uop_T_5_iw_p1_speculative_child; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_iw_p2_speculative_child = _exe_tlb_uop_T_5_iw_p2_speculative_child; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p1_bypass_hint = _exe_tlb_uop_T_5_iw_p1_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p2_bypass_hint = _exe_tlb_uop_T_5_iw_p2_bypass_hint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_iw_p3_bypass_hint = _exe_tlb_uop_T_5_iw_p3_bypass_hint; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_dis_col_sel = _exe_tlb_uop_T_5_dis_col_sel; // @[lsu.scala:321:49, :717:24] wire [15:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_5_br_mask; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_tag = _exe_tlb_uop_T_5_br_tag; // @[lsu.scala:321:49, :717:24] wire [3:0] exe_tlb_uop_0_br_type = _exe_tlb_uop_T_5_br_type; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfb = _exe_tlb_uop_T_5_is_sfb; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_5_is_fence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_fencei = _exe_tlb_uop_T_5_is_fencei; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sfence = _exe_tlb_uop_T_5_is_sfence; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_amo = _exe_tlb_uop_T_5_is_amo; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_eret = _exe_tlb_uop_T_5_is_eret; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_sys_pc2epc = _exe_tlb_uop_T_5_is_sys_pc2epc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_rocc = _exe_tlb_uop_T_5_is_rocc; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_mov = _exe_tlb_uop_T_5_is_mov; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ftq_idx = _exe_tlb_uop_T_5_ftq_idx; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_edge_inst = _exe_tlb_uop_T_5_edge_inst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_pc_lob = _exe_tlb_uop_T_5_pc_lob; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_taken = _exe_tlb_uop_T_5_taken; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_imm_rename = _exe_tlb_uop_T_5_imm_rename; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_imm_sel = _exe_tlb_uop_T_5_imm_sel; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_pimm = _exe_tlb_uop_T_5_pimm; // @[lsu.scala:321:49, :717:24] wire [19:0] exe_tlb_uop_0_imm_packed = _exe_tlb_uop_T_5_imm_packed; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_op1_sel = _exe_tlb_uop_T_5_op1_sel; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_op2_sel = _exe_tlb_uop_T_5_op2_sel; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ldst = _exe_tlb_uop_T_5_fp_ctrl_ldst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wen = _exe_tlb_uop_T_5_fp_ctrl_wen; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren1 = _exe_tlb_uop_T_5_fp_ctrl_ren1; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren2 = _exe_tlb_uop_T_5_fp_ctrl_ren2; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_ren3 = _exe_tlb_uop_T_5_fp_ctrl_ren3; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap12 = _exe_tlb_uop_T_5_fp_ctrl_swap12; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_swap23 = _exe_tlb_uop_T_5_fp_ctrl_swap23; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagIn = _exe_tlb_uop_T_5_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_ctrl_typeTagOut = _exe_tlb_uop_T_5_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fromint = _exe_tlb_uop_T_5_fp_ctrl_fromint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_toint = _exe_tlb_uop_T_5_fp_ctrl_toint; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fastpipe = _exe_tlb_uop_T_5_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_fma = _exe_tlb_uop_T_5_fp_ctrl_fma; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_div = _exe_tlb_uop_T_5_fp_ctrl_div; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_sqrt = _exe_tlb_uop_T_5_fp_ctrl_sqrt; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_wflags = _exe_tlb_uop_T_5_fp_ctrl_wflags; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_ctrl_vec = _exe_tlb_uop_T_5_fp_ctrl_vec; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_5_rob_idx; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_5_ldq_idx; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_5_stq_idx; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_rxq_idx = _exe_tlb_uop_T_5_rxq_idx; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_pdst = _exe_tlb_uop_T_5_pdst; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs1 = _exe_tlb_uop_T_5_prs1; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs2 = _exe_tlb_uop_T_5_prs2; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_prs3 = _exe_tlb_uop_T_5_prs3; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_ppred = _exe_tlb_uop_T_5_ppred; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs1_busy = _exe_tlb_uop_T_5_prs1_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs2_busy = _exe_tlb_uop_T_5_prs2_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_prs3_busy = _exe_tlb_uop_T_5_prs3_busy; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ppred_busy = _exe_tlb_uop_T_5_ppred_busy; // @[lsu.scala:321:49, :717:24] wire [6:0] exe_tlb_uop_0_stale_pdst = _exe_tlb_uop_T_5_stale_pdst; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_exception = _exe_tlb_uop_T_5_exception; // @[lsu.scala:321:49, :717:24] wire [63:0] exe_tlb_uop_0_exc_cause = _exe_tlb_uop_T_5_exc_cause; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_5_mem_cmd; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_5_mem_size; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_mem_signed = _exe_tlb_uop_T_5_mem_signed; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_5_uses_ldq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_5_uses_stq; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_is_unique = _exe_tlb_uop_T_5_is_unique; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_flush_on_commit = _exe_tlb_uop_T_5_flush_on_commit; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_csr_cmd = _exe_tlb_uop_T_5_csr_cmd; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_ldst_is_rs1 = _exe_tlb_uop_T_5_ldst_is_rs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_ldst = _exe_tlb_uop_T_5_ldst; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs1 = _exe_tlb_uop_T_5_lrs1; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs2 = _exe_tlb_uop_T_5_lrs2; // @[lsu.scala:321:49, :717:24] wire [5:0] exe_tlb_uop_0_lrs3 = _exe_tlb_uop_T_5_lrs3; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_dst_rtype = _exe_tlb_uop_T_5_dst_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs1_rtype = _exe_tlb_uop_T_5_lrs1_rtype; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_lrs2_rtype = _exe_tlb_uop_T_5_lrs2_rtype; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_frs3_en = _exe_tlb_uop_T_5_frs3_en; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fcn_dw = _exe_tlb_uop_T_5_fcn_dw; // @[lsu.scala:321:49, :717:24] wire [4:0] exe_tlb_uop_0_fcn_op = _exe_tlb_uop_T_5_fcn_op; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_fp_val = _exe_tlb_uop_T_5_fp_val; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_fp_rm = _exe_tlb_uop_T_5_fp_rm; // @[lsu.scala:321:49, :717:24] wire [1:0] exe_tlb_uop_0_fp_typ = _exe_tlb_uop_T_5_fp_typ; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_pf_if = _exe_tlb_uop_T_5_xcpt_pf_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ae_if = _exe_tlb_uop_T_5_xcpt_ae_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_xcpt_ma_if = _exe_tlb_uop_T_5_xcpt_ma_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_debug_if = _exe_tlb_uop_T_5_bp_debug_if; // @[lsu.scala:321:49, :717:24] wire exe_tlb_uop_0_bp_xcpt_if = _exe_tlb_uop_T_5_bp_xcpt_if; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_fsrc = _exe_tlb_uop_T_5_debug_fsrc; // @[lsu.scala:321:49, :717:24] wire [2:0] exe_tlb_uop_0_debug_tsrc = _exe_tlb_uop_T_5_debug_tsrc; // @[lsu.scala:321:49, :717:24] wire [31:0] mem_xcpt_uops_out_inst = exe_tlb_uop_0_inst; // @[util.scala:104:23] wire [31:0] mem_xcpt_uops_out_debug_inst = exe_tlb_uop_0_debug_inst; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rvc = exe_tlb_uop_0_is_rvc; // @[util.scala:104:23] wire [39:0] mem_xcpt_uops_out_debug_pc = exe_tlb_uop_0_debug_pc; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_0 = exe_tlb_uop_0_iq_type_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_1 = exe_tlb_uop_0_iq_type_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_2 = exe_tlb_uop_0_iq_type_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_iq_type_3 = exe_tlb_uop_0_iq_type_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_0 = exe_tlb_uop_0_fu_code_0; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_1 = exe_tlb_uop_0_fu_code_1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_2 = exe_tlb_uop_0_fu_code_2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_3 = exe_tlb_uop_0_fu_code_3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_4 = exe_tlb_uop_0_fu_code_4; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_5 = exe_tlb_uop_0_fu_code_5; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_6 = exe_tlb_uop_0_fu_code_6; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_7 = exe_tlb_uop_0_fu_code_7; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_8 = exe_tlb_uop_0_fu_code_8; // @[util.scala:104:23] wire mem_xcpt_uops_out_fu_code_9 = exe_tlb_uop_0_fu_code_9; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued = exe_tlb_uop_0_iw_issued; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_agen = exe_tlb_uop_0_iw_issued_partial_agen; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_issued_partial_dgen = exe_tlb_uop_0_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_iw_p1_speculative_child = exe_tlb_uop_0_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_iw_p2_speculative_child = exe_tlb_uop_0_iw_p2_speculative_child; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p1_bypass_hint = exe_tlb_uop_0_iw_p1_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p2_bypass_hint = exe_tlb_uop_0_iw_p2_bypass_hint; // @[util.scala:104:23] wire mem_xcpt_uops_out_iw_p3_bypass_hint = exe_tlb_uop_0_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_dis_col_sel = exe_tlb_uop_0_dis_col_sel; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_tag = exe_tlb_uop_0_br_tag; // @[util.scala:104:23] wire [3:0] mem_xcpt_uops_out_br_type = exe_tlb_uop_0_br_type; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfb = exe_tlb_uop_0_is_sfb; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fence = exe_tlb_uop_0_is_fence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_fencei = exe_tlb_uop_0_is_fencei; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sfence = exe_tlb_uop_0_is_sfence; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_amo = exe_tlb_uop_0_is_amo; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_eret = exe_tlb_uop_0_is_eret; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_sys_pc2epc = exe_tlb_uop_0_is_sys_pc2epc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_rocc = exe_tlb_uop_0_is_rocc; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_mov = exe_tlb_uop_0_is_mov; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ftq_idx = exe_tlb_uop_0_ftq_idx; // @[util.scala:104:23] wire mem_xcpt_uops_out_edge_inst = exe_tlb_uop_0_edge_inst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_pc_lob = exe_tlb_uop_0_pc_lob; // @[util.scala:104:23] wire mem_xcpt_uops_out_taken = exe_tlb_uop_0_taken; // @[util.scala:104:23] wire mem_xcpt_uops_out_imm_rename = exe_tlb_uop_0_imm_rename; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_imm_sel = exe_tlb_uop_0_imm_sel; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_pimm = exe_tlb_uop_0_pimm; // @[util.scala:104:23] wire [19:0] mem_xcpt_uops_out_imm_packed = exe_tlb_uop_0_imm_packed; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_op1_sel = exe_tlb_uop_0_op1_sel; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_op2_sel = exe_tlb_uop_0_op2_sel; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ldst = exe_tlb_uop_0_fp_ctrl_ldst; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wen = exe_tlb_uop_0_fp_ctrl_wen; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren1 = exe_tlb_uop_0_fp_ctrl_ren1; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren2 = exe_tlb_uop_0_fp_ctrl_ren2; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_ren3 = exe_tlb_uop_0_fp_ctrl_ren3; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap12 = exe_tlb_uop_0_fp_ctrl_swap12; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_swap23 = exe_tlb_uop_0_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagIn = exe_tlb_uop_0_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_ctrl_typeTagOut = exe_tlb_uop_0_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fromint = exe_tlb_uop_0_fp_ctrl_fromint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_toint = exe_tlb_uop_0_fp_ctrl_toint; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fastpipe = exe_tlb_uop_0_fp_ctrl_fastpipe; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_fma = exe_tlb_uop_0_fp_ctrl_fma; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_div = exe_tlb_uop_0_fp_ctrl_div; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_sqrt = exe_tlb_uop_0_fp_ctrl_sqrt; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_wflags = exe_tlb_uop_0_fp_ctrl_wflags; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_ctrl_vec = exe_tlb_uop_0_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_rob_idx = exe_tlb_uop_0_rob_idx; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ldq_idx = exe_tlb_uop_0_ldq_idx; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_stq_idx = exe_tlb_uop_0_stq_idx; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_rxq_idx = exe_tlb_uop_0_rxq_idx; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_pdst = exe_tlb_uop_0_pdst; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs1 = exe_tlb_uop_0_prs1; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs2 = exe_tlb_uop_0_prs2; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_prs3 = exe_tlb_uop_0_prs3; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_ppred = exe_tlb_uop_0_ppred; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs1_busy = exe_tlb_uop_0_prs1_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs2_busy = exe_tlb_uop_0_prs2_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_prs3_busy = exe_tlb_uop_0_prs3_busy; // @[util.scala:104:23] wire mem_xcpt_uops_out_ppred_busy = exe_tlb_uop_0_ppred_busy; // @[util.scala:104:23] wire [6:0] mem_xcpt_uops_out_stale_pdst = exe_tlb_uop_0_stale_pdst; // @[util.scala:104:23] wire mem_xcpt_uops_out_exception = exe_tlb_uop_0_exception; // @[util.scala:104:23] wire [63:0] mem_xcpt_uops_out_exc_cause = exe_tlb_uop_0_exc_cause; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_mem_cmd = exe_tlb_uop_0_mem_cmd; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_mem_size = exe_tlb_uop_0_mem_size; // @[util.scala:104:23] wire mem_xcpt_uops_out_mem_signed = exe_tlb_uop_0_mem_signed; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_ldq = exe_tlb_uop_0_uses_ldq; // @[util.scala:104:23] wire mem_xcpt_uops_out_uses_stq = exe_tlb_uop_0_uses_stq; // @[util.scala:104:23] wire mem_xcpt_uops_out_is_unique = exe_tlb_uop_0_is_unique; // @[util.scala:104:23] wire mem_xcpt_uops_out_flush_on_commit = exe_tlb_uop_0_flush_on_commit; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_csr_cmd = exe_tlb_uop_0_csr_cmd; // @[util.scala:104:23] wire mem_xcpt_uops_out_ldst_is_rs1 = exe_tlb_uop_0_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_ldst = exe_tlb_uop_0_ldst; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs1 = exe_tlb_uop_0_lrs1; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs2 = exe_tlb_uop_0_lrs2; // @[util.scala:104:23] wire [5:0] mem_xcpt_uops_out_lrs3 = exe_tlb_uop_0_lrs3; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_dst_rtype = exe_tlb_uop_0_dst_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs1_rtype = exe_tlb_uop_0_lrs1_rtype; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_lrs2_rtype = exe_tlb_uop_0_lrs2_rtype; // @[util.scala:104:23] wire mem_xcpt_uops_out_frs3_en = exe_tlb_uop_0_frs3_en; // @[util.scala:104:23] wire mem_xcpt_uops_out_fcn_dw = exe_tlb_uop_0_fcn_dw; // @[util.scala:104:23] wire [4:0] mem_xcpt_uops_out_fcn_op = exe_tlb_uop_0_fcn_op; // @[util.scala:104:23] wire mem_xcpt_uops_out_fp_val = exe_tlb_uop_0_fp_val; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_fp_rm = exe_tlb_uop_0_fp_rm; // @[util.scala:104:23] wire [1:0] mem_xcpt_uops_out_fp_typ = exe_tlb_uop_0_fp_typ; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_pf_if = exe_tlb_uop_0_xcpt_pf_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ae_if = exe_tlb_uop_0_xcpt_ae_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_xcpt_ma_if = exe_tlb_uop_0_xcpt_ma_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_debug_if = exe_tlb_uop_0_bp_debug_if; // @[util.scala:104:23] wire mem_xcpt_uops_out_bp_xcpt_if = exe_tlb_uop_0_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_fsrc = exe_tlb_uop_0_debug_fsrc; // @[util.scala:104:23] wire [2:0] mem_xcpt_uops_out_debug_tsrc = exe_tlb_uop_0_debug_tsrc; // @[util.scala:104:23] wire _exe_tlb_vaddr_T_1 = _exe_tlb_vaddr_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :726:53, :727:53] wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_hella_incoming_0 ? hella_req_addr : 40'h0; // @[lsu.scala:302:34, :473:41, :732:24] wire [63:0] _exe_tlb_vaddr_T_4 = _exe_tlb_vaddr_T_2 ? _retry_queue_io_deq_bits_data : {24'h0, _exe_tlb_vaddr_T_3}; // @[lsu.scala:533:27, :730:{24,53}, :732:24] wire [63:0] _exe_tlb_vaddr_T_5 = will_fire_sfence_0 ? {25'h0, io_core_sfence_bits_addr_0} : _exe_tlb_vaddr_T_4; // @[lsu.scala:211:7, :472:41, :729:24, :730:24] wire [63:0] _exe_tlb_vaddr_T_6 = _exe_tlb_vaddr_T_1 ? io_core_agen_0_bits_data_0 : _exe_tlb_vaddr_T_5; // @[lsu.scala:211:7, :726:24, :727:53, :729:24] wire [63:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_6; // @[lsu.scala:321:49, :726:24] wire _exe_size_T_1 = _exe_size_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :738:52, :739:52] wire _exe_size_T_2 = _exe_size_T_1 | will_fire_load_retry_0; // @[lsu.scala:476:41, :739:52, :740:52] wire _exe_size_T_3 = _exe_size_T_2 | will_fire_store_retry_0; // @[lsu.scala:477:41, :740:52, :741:52] wire [1:0] _exe_size_T_4 = {2{will_fire_hella_incoming_0}}; // @[lsu.scala:473:41, :743:23] wire [1:0] _exe_size_T_5 = _exe_size_T_3 ? exe_tlb_uop_0_mem_size : _exe_size_T_4; // @[lsu.scala:321:49, :738:23, :741:52, :743:23] wire [1:0] exe_size_0 = _exe_size_T_5; // @[lsu.scala:321:49, :738:23] wire _exe_cmd_T_1 = _exe_cmd_T | will_fire_store_agen_0; // @[lsu.scala:471:41, :746:52, :747:52] wire _exe_cmd_T_2 = _exe_cmd_T_1 | will_fire_load_retry_0; // @[lsu.scala:476:41, :747:52, :748:52] wire _exe_cmd_T_3 = _exe_cmd_T_2 | will_fire_store_retry_0; // @[lsu.scala:477:41, :748:52, :749:52] wire [4:0] _exe_cmd_T_4 = will_fire_sfence_0 ? 5'h14 : 5'h0; // @[lsu.scala:472:41, :752:23] wire [4:0] _exe_cmd_T_5 = will_fire_hella_incoming_0 ? 5'h0 : _exe_cmd_T_4; // @[lsu.scala:473:41, :751:23, :752:23] wire [4:0] _exe_cmd_T_6 = _exe_cmd_T_3 ? exe_tlb_uop_0_mem_cmd : _exe_cmd_T_5; // @[lsu.scala:321:49, :746:23, :749:52, :751:23] wire [4:0] exe_cmd_0 = _exe_cmd_T_6; // @[lsu.scala:321:49, :746:23] wire exe_passthr_0 = _exe_passthr_T; // @[lsu.scala:321:49, :756:23] wire _exe_kill_T = will_fire_hella_incoming_0 & io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :473:41, :759:23] wire exe_kill_0 = _exe_kill_T; // @[lsu.scala:321:49, :759:23] wire _ma_ld_T = _dtlb_io_resp_0_ma_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :782:52] wire ma_ld_0 = _ma_ld_T; // @[lsu.scala:321:49, :782:52] wire _ma_st_T = _dtlb_io_resp_0_ma_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :783:52] wire _ma_st_T_1 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82] wire _ma_st_T_2 = _ma_st_T & _ma_st_T_1; // @[lsu.scala:783:{52,79,82}] wire ma_st_0 = _ma_st_T_2; // @[lsu.scala:321:49, :783:79] wire _pf_ld_T = _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :784:52] wire pf_ld_0 = _pf_ld_T; // @[lsu.scala:321:49, :784:52] wire _pf_st_T = _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :785:52] wire pf_st_0 = _pf_st_T; // @[lsu.scala:321:49, :785:52] wire _ae_ld_T = _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq; // @[lsu.scala:308:20, :321:49, :786:52] wire ae_ld_0 = _ae_ld_T; // @[lsu.scala:321:49, :786:52] wire _ae_st_T = _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq; // @[lsu.scala:308:20, :321:49, :787:52] wire ae_st_0 = _ae_st_T; // @[lsu.scala:321:49, :787:52] wire _dbg_bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :789:107] wire _bp_T_2 = ~exe_tlb_uop_0_is_fence; // @[lsu.scala:321:49, :783:82, :791:106] wire _mem_xcpt_valids_T = pf_ld_0 | pf_st_0; // @[lsu.scala:321:49, :797:32] wire _mem_xcpt_valids_T_1 = _mem_xcpt_valids_T | ae_ld_0; // @[lsu.scala:321:49, :797:{32,44}] wire _mem_xcpt_valids_T_2 = _mem_xcpt_valids_T_1 | ae_st_0; // @[lsu.scala:321:49, :797:{44,56}] wire _mem_xcpt_valids_T_3 = _mem_xcpt_valids_T_2 | ma_ld_0; // @[lsu.scala:321:49, :797:{56,68}] wire _mem_xcpt_valids_T_4 = _mem_xcpt_valids_T_3 | ma_st_0; // @[lsu.scala:321:49, :797:{68,80}] wire _mem_xcpt_valids_T_5 = _mem_xcpt_valids_T_4; // @[lsu.scala:797:{80,92}] wire _mem_xcpt_valids_T_6 = _mem_xcpt_valids_T_5; // @[lsu.scala:797:{92,105}] wire _mem_xcpt_valids_T_7 = exe_tlb_valid_0 & _mem_xcpt_valids_T_6; // @[lsu.scala:649:27, :796:39, :797:105] wire [15:0] _mem_xcpt_valids_T_8 = io_core_brupdate_b1_mispredict_mask_0 & exe_tlb_uop_0_br_mask; // @[util.scala:126:51] wire _mem_xcpt_valids_T_9 = |_mem_xcpt_valids_T_8; // @[util.scala:126:{51,59}] wire _mem_xcpt_valids_T_10 = _mem_xcpt_valids_T_9 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_xcpt_valids_T_11 = ~_mem_xcpt_valids_T_10; // @[util.scala:61:61] wire _mem_xcpt_valids_T_12 = _mem_xcpt_valids_T_7 & _mem_xcpt_valids_T_11; // @[lsu.scala:796:39, :797:115, :798:22] wire _mem_xcpt_valids_WIRE_0 = _mem_xcpt_valids_T_12; // @[lsu.scala:321:49, :797:115] reg mem_xcpt_valids_0; // @[lsu.scala:795:32] assign mem_xcpt_valid = mem_xcpt_valids_0; // @[lsu.scala:457:29, :795:32] wire [31:0] _mem_xcpt_uops_WIRE_0_inst = mem_xcpt_uops_out_inst; // @[util.scala:104:23] wire [31:0] _mem_xcpt_uops_WIRE_0_debug_inst = mem_xcpt_uops_out_debug_inst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rvc = mem_xcpt_uops_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_xcpt_uops_WIRE_0_debug_pc = mem_xcpt_uops_out_debug_pc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_0 = mem_xcpt_uops_out_iq_type_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_1 = mem_xcpt_uops_out_iq_type_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_2 = mem_xcpt_uops_out_iq_type_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iq_type_3 = mem_xcpt_uops_out_iq_type_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_0 = mem_xcpt_uops_out_fu_code_0; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_1 = mem_xcpt_uops_out_fu_code_1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_2 = mem_xcpt_uops_out_fu_code_2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_3 = mem_xcpt_uops_out_fu_code_3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_4 = mem_xcpt_uops_out_fu_code_4; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_5 = mem_xcpt_uops_out_fu_code_5; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_6 = mem_xcpt_uops_out_fu_code_6; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_7 = mem_xcpt_uops_out_fu_code_7; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_8 = mem_xcpt_uops_out_fu_code_8; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fu_code_9 = mem_xcpt_uops_out_fu_code_9; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued = mem_xcpt_uops_out_iw_issued; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_agen = mem_xcpt_uops_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_issued_partial_dgen = mem_xcpt_uops_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iw_p1_speculative_child = mem_xcpt_uops_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_iw_p2_speculative_child = mem_xcpt_uops_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p1_bypass_hint = mem_xcpt_uops_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p2_bypass_hint = mem_xcpt_uops_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_iw_p3_bypass_hint = mem_xcpt_uops_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25] wire [2:0] _mem_xcpt_uops_WIRE_0_dis_col_sel = mem_xcpt_uops_out_dis_col_sel; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_WIRE_0_br_mask = mem_xcpt_uops_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_tag = mem_xcpt_uops_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_xcpt_uops_WIRE_0_br_type = mem_xcpt_uops_out_br_type; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfb = mem_xcpt_uops_out_is_sfb; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fence = mem_xcpt_uops_out_is_fence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_fencei = mem_xcpt_uops_out_is_fencei; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sfence = mem_xcpt_uops_out_is_sfence; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_amo = mem_xcpt_uops_out_is_amo; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_eret = mem_xcpt_uops_out_is_eret; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_sys_pc2epc = mem_xcpt_uops_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_rocc = mem_xcpt_uops_out_is_rocc; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_mov = mem_xcpt_uops_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ftq_idx = mem_xcpt_uops_out_ftq_idx; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_edge_inst = mem_xcpt_uops_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_pc_lob = mem_xcpt_uops_out_pc_lob; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_taken = mem_xcpt_uops_out_taken; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_imm_rename = mem_xcpt_uops_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_imm_sel = mem_xcpt_uops_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_pimm = mem_xcpt_uops_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_xcpt_uops_WIRE_0_imm_packed = mem_xcpt_uops_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_op1_sel = mem_xcpt_uops_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_op2_sel = mem_xcpt_uops_out_op2_sel; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ldst = mem_xcpt_uops_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wen = mem_xcpt_uops_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren1 = mem_xcpt_uops_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren2 = mem_xcpt_uops_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_ren3 = mem_xcpt_uops_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap12 = mem_xcpt_uops_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_swap23 = mem_xcpt_uops_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagIn = mem_xcpt_uops_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_ctrl_typeTagOut = mem_xcpt_uops_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fromint = mem_xcpt_uops_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_toint = mem_xcpt_uops_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fastpipe = mem_xcpt_uops_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_fma = mem_xcpt_uops_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_div = mem_xcpt_uops_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_sqrt = mem_xcpt_uops_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_wflags = mem_xcpt_uops_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_ctrl_vec = mem_xcpt_uops_out_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_rob_idx = mem_xcpt_uops_out_rob_idx; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ldq_idx = mem_xcpt_uops_out_ldq_idx; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_stq_idx = mem_xcpt_uops_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_rxq_idx = mem_xcpt_uops_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_pdst = mem_xcpt_uops_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs1 = mem_xcpt_uops_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs2 = mem_xcpt_uops_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_prs3 = mem_xcpt_uops_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_ppred = mem_xcpt_uops_out_ppred; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs1_busy = mem_xcpt_uops_out_prs1_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs2_busy = mem_xcpt_uops_out_prs2_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_prs3_busy = mem_xcpt_uops_out_prs3_busy; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ppred_busy = mem_xcpt_uops_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_xcpt_uops_WIRE_0_stale_pdst = mem_xcpt_uops_out_stale_pdst; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_exception = mem_xcpt_uops_out_exception; // @[util.scala:104:23] wire [63:0] _mem_xcpt_uops_WIRE_0_exc_cause = mem_xcpt_uops_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_mem_cmd = mem_xcpt_uops_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_mem_size = mem_xcpt_uops_out_mem_size; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_mem_signed = mem_xcpt_uops_out_mem_signed; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_ldq = mem_xcpt_uops_out_uses_ldq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_uses_stq = mem_xcpt_uops_out_uses_stq; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_is_unique = mem_xcpt_uops_out_is_unique; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_flush_on_commit = mem_xcpt_uops_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_csr_cmd = mem_xcpt_uops_out_csr_cmd; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_ldst_is_rs1 = mem_xcpt_uops_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_ldst = mem_xcpt_uops_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs1 = mem_xcpt_uops_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs2 = mem_xcpt_uops_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_xcpt_uops_WIRE_0_lrs3 = mem_xcpt_uops_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_dst_rtype = mem_xcpt_uops_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs1_rtype = mem_xcpt_uops_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_lrs2_rtype = mem_xcpt_uops_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_frs3_en = mem_xcpt_uops_out_frs3_en; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fcn_dw = mem_xcpt_uops_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_xcpt_uops_WIRE_0_fcn_op = mem_xcpt_uops_out_fcn_op; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_fp_val = mem_xcpt_uops_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_fp_rm = mem_xcpt_uops_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_xcpt_uops_WIRE_0_fp_typ = mem_xcpt_uops_out_fp_typ; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_pf_if = mem_xcpt_uops_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ae_if = mem_xcpt_uops_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_xcpt_ma_if = mem_xcpt_uops_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_debug_if = mem_xcpt_uops_out_bp_debug_if; // @[util.scala:104:23] wire _mem_xcpt_uops_WIRE_0_bp_xcpt_if = mem_xcpt_uops_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_fsrc = mem_xcpt_uops_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_xcpt_uops_WIRE_0_debug_tsrc = mem_xcpt_uops_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _mem_xcpt_uops_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_xcpt_uops_out_br_mask_T_1 = exe_tlb_uop_0_br_mask & _mem_xcpt_uops_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_xcpt_uops_out_br_mask = _mem_xcpt_uops_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_xcpt_uops_0_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_inst = mem_xcpt_uops_0_inst; // @[lsu.scala:459:29, :799:32] reg [31:0] mem_xcpt_uops_0_debug_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_inst = mem_xcpt_uops_0_debug_inst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rvc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rvc = mem_xcpt_uops_0_is_rvc; // @[lsu.scala:459:29, :799:32] reg [39:0] mem_xcpt_uops_0_debug_pc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_pc = mem_xcpt_uops_0_debug_pc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_0 = mem_xcpt_uops_0_iq_type_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_1 = mem_xcpt_uops_0_iq_type_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_2 = mem_xcpt_uops_0_iq_type_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_iq_type_3 = mem_xcpt_uops_0_iq_type_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_0 = mem_xcpt_uops_0_fu_code_0; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_1 = mem_xcpt_uops_0_fu_code_1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_2 = mem_xcpt_uops_0_fu_code_2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_3 = mem_xcpt_uops_0_fu_code_3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_4 = mem_xcpt_uops_0_fu_code_4; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_5 = mem_xcpt_uops_0_fu_code_5; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_6 = mem_xcpt_uops_0_fu_code_6; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_7 = mem_xcpt_uops_0_fu_code_7; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_8 = mem_xcpt_uops_0_fu_code_8; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:799:32] assign mem_xcpt_uop_fu_code_9 = mem_xcpt_uops_0_fu_code_9; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued = mem_xcpt_uops_0_iw_issued; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_agen = mem_xcpt_uops_0_iw_issued_partial_agen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_issued_partial_dgen = mem_xcpt_uops_0_iw_issued_partial_dgen; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_speculative_child = mem_xcpt_uops_0_iw_p1_speculative_child; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_speculative_child = mem_xcpt_uops_0_iw_p2_speculative_child; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p1_bypass_hint = mem_xcpt_uops_0_iw_p1_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p2_bypass_hint = mem_xcpt_uops_0_iw_p2_bypass_hint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:799:32] assign mem_xcpt_uop_iw_p3_bypass_hint = mem_xcpt_uops_0_iw_p3_bypass_hint; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_dis_col_sel = mem_xcpt_uops_0_dis_col_sel; // @[lsu.scala:459:29, :799:32] reg [15:0] mem_xcpt_uops_0_br_mask; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_mask = mem_xcpt_uops_0_br_mask; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_tag; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_tag = mem_xcpt_uops_0_br_tag; // @[lsu.scala:459:29, :799:32] reg [3:0] mem_xcpt_uops_0_br_type; // @[lsu.scala:799:32] assign mem_xcpt_uop_br_type = mem_xcpt_uops_0_br_type; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfb; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfb = mem_xcpt_uops_0_is_sfb; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fence = mem_xcpt_uops_0_is_fence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_fencei; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_fencei = mem_xcpt_uops_0_is_fencei; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sfence; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sfence = mem_xcpt_uops_0_is_sfence; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_amo; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_amo = mem_xcpt_uops_0_is_amo; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_eret; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_eret = mem_xcpt_uops_0_is_eret; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_sys_pc2epc = mem_xcpt_uops_0_is_sys_pc2epc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_rocc; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_rocc = mem_xcpt_uops_0_is_rocc; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_mov; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_mov = mem_xcpt_uops_0_is_mov; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ftq_idx = mem_xcpt_uops_0_ftq_idx; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_edge_inst; // @[lsu.scala:799:32] assign mem_xcpt_uop_edge_inst = mem_xcpt_uops_0_edge_inst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_pc_lob; // @[lsu.scala:799:32] assign mem_xcpt_uop_pc_lob = mem_xcpt_uops_0_pc_lob; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_taken; // @[lsu.scala:799:32] assign mem_xcpt_uop_taken = mem_xcpt_uops_0_taken; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_imm_rename; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_rename = mem_xcpt_uops_0_imm_rename; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_imm_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_sel = mem_xcpt_uops_0_imm_sel; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_pimm; // @[lsu.scala:799:32] assign mem_xcpt_uop_pimm = mem_xcpt_uops_0_pimm; // @[lsu.scala:459:29, :799:32] reg [19:0] mem_xcpt_uops_0_imm_packed; // @[lsu.scala:799:32] assign mem_xcpt_uop_imm_packed = mem_xcpt_uops_0_imm_packed; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_op1_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op1_sel = mem_xcpt_uops_0_op1_sel; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_op2_sel; // @[lsu.scala:799:32] assign mem_xcpt_uop_op2_sel = mem_xcpt_uops_0_op2_sel; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ldst = mem_xcpt_uops_0_fp_ctrl_ldst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wen = mem_xcpt_uops_0_fp_ctrl_wen; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren1 = mem_xcpt_uops_0_fp_ctrl_ren1; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren2 = mem_xcpt_uops_0_fp_ctrl_ren2; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_ren3 = mem_xcpt_uops_0_fp_ctrl_ren3; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap12 = mem_xcpt_uops_0_fp_ctrl_swap12; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_swap23 = mem_xcpt_uops_0_fp_ctrl_swap23; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagIn = mem_xcpt_uops_0_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_typeTagOut = mem_xcpt_uops_0_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fromint = mem_xcpt_uops_0_fp_ctrl_fromint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_toint = mem_xcpt_uops_0_fp_ctrl_toint; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fastpipe = mem_xcpt_uops_0_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_fma = mem_xcpt_uops_0_fp_ctrl_fma; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_div = mem_xcpt_uops_0_fp_ctrl_div; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_sqrt = mem_xcpt_uops_0_fp_ctrl_sqrt; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_wflags = mem_xcpt_uops_0_fp_ctrl_wflags; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_ctrl_vec = mem_xcpt_uops_0_fp_ctrl_vec; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_rob_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rob_idx = mem_xcpt_uops_0_rob_idx; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldq_idx = mem_xcpt_uops_0_ldq_idx; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_stq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_stq_idx = mem_xcpt_uops_0_stq_idx; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:799:32] assign mem_xcpt_uop_rxq_idx = mem_xcpt_uops_0_rxq_idx; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_pdst = mem_xcpt_uops_0_pdst; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1 = mem_xcpt_uops_0_prs1; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2 = mem_xcpt_uops_0_prs2; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_prs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3 = mem_xcpt_uops_0_prs3; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_ppred; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred = mem_xcpt_uops_0_ppred; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs1_busy = mem_xcpt_uops_0_prs1_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs2_busy = mem_xcpt_uops_0_prs2_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_prs3_busy = mem_xcpt_uops_0_prs3_busy; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:799:32] assign mem_xcpt_uop_ppred_busy = mem_xcpt_uops_0_ppred_busy; // @[lsu.scala:459:29, :799:32] reg [6:0] mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:799:32] assign mem_xcpt_uop_stale_pdst = mem_xcpt_uops_0_stale_pdst; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_exception; // @[lsu.scala:799:32] assign mem_xcpt_uop_exception = mem_xcpt_uops_0_exception; // @[lsu.scala:459:29, :799:32] reg [63:0] mem_xcpt_uops_0_exc_cause; // @[lsu.scala:799:32] assign mem_xcpt_uop_exc_cause = mem_xcpt_uops_0_exc_cause; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_cmd = mem_xcpt_uops_0_mem_cmd; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_mem_size; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_size = mem_xcpt_uops_0_mem_size; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_mem_signed; // @[lsu.scala:799:32] assign mem_xcpt_uop_mem_signed = mem_xcpt_uops_0_mem_signed; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_ldq = mem_xcpt_uops_0_uses_ldq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_uses_stq; // @[lsu.scala:799:32] assign mem_xcpt_uop_uses_stq = mem_xcpt_uops_0_uses_stq; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_is_unique; // @[lsu.scala:799:32] assign mem_xcpt_uop_is_unique = mem_xcpt_uops_0_is_unique; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:799:32] assign mem_xcpt_uop_flush_on_commit = mem_xcpt_uops_0_flush_on_commit; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:799:32] assign mem_xcpt_uop_csr_cmd = mem_xcpt_uops_0_csr_cmd; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst_is_rs1 = mem_xcpt_uops_0_ldst_is_rs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_ldst; // @[lsu.scala:799:32] assign mem_xcpt_uop_ldst = mem_xcpt_uops_0_ldst; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs1; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1 = mem_xcpt_uops_0_lrs1; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs2; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2 = mem_xcpt_uops_0_lrs2; // @[lsu.scala:459:29, :799:32] reg [5:0] mem_xcpt_uops_0_lrs3; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs3 = mem_xcpt_uops_0_lrs3; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_dst_rtype = mem_xcpt_uops_0_dst_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs1_rtype = mem_xcpt_uops_0_lrs1_rtype; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:799:32] assign mem_xcpt_uop_lrs2_rtype = mem_xcpt_uops_0_lrs2_rtype; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_frs3_en; // @[lsu.scala:799:32] assign mem_xcpt_uop_frs3_en = mem_xcpt_uops_0_frs3_en; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_dw = mem_xcpt_uops_0_fcn_dw; // @[lsu.scala:459:29, :799:32] reg [4:0] mem_xcpt_uops_0_fcn_op; // @[lsu.scala:799:32] assign mem_xcpt_uop_fcn_op = mem_xcpt_uops_0_fcn_op; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_fp_val; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_val = mem_xcpt_uops_0_fp_val; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_fp_rm; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_rm = mem_xcpt_uops_0_fp_rm; // @[lsu.scala:459:29, :799:32] reg [1:0] mem_xcpt_uops_0_fp_typ; // @[lsu.scala:799:32] assign mem_xcpt_uop_fp_typ = mem_xcpt_uops_0_fp_typ; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_pf_if = mem_xcpt_uops_0_xcpt_pf_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ae_if = mem_xcpt_uops_0_xcpt_ae_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_xcpt_ma_if = mem_xcpt_uops_0_xcpt_ma_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_debug_if = mem_xcpt_uops_0_bp_debug_if; // @[lsu.scala:459:29, :799:32] reg mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:799:32] assign mem_xcpt_uop_bp_xcpt_if = mem_xcpt_uops_0_bp_xcpt_if; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_fsrc = mem_xcpt_uops_0_debug_fsrc; // @[lsu.scala:459:29, :799:32] reg [2:0] mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:799:32] assign mem_xcpt_uop_debug_tsrc = mem_xcpt_uops_0_debug_tsrc; // @[lsu.scala:459:29, :799:32] wire [2:0] _mem_xcpt_causes_T = ae_ld_0 ? 3'h5 : 3'h0; // @[lsu.scala:321:49, :808:8] wire [2:0] _mem_xcpt_causes_T_1 = ae_st_0 ? 3'h7 : _mem_xcpt_causes_T; // @[lsu.scala:321:49, :807:8, :808:8] wire [3:0] _mem_xcpt_causes_T_2 = pf_ld_0 ? 4'hD : {1'h0, _mem_xcpt_causes_T_1}; // @[lsu.scala:321:49, :806:8, :807:8] wire [3:0] _mem_xcpt_causes_T_3 = pf_st_0 ? 4'hF : _mem_xcpt_causes_T_2; // @[lsu.scala:321:49, :805:8, :806:8] wire [3:0] _mem_xcpt_causes_T_4 = ma_ld_0 ? 4'h4 : _mem_xcpt_causes_T_3; // @[lsu.scala:321:49, :804:8, :805:8] wire [3:0] _mem_xcpt_causes_T_5 = ma_st_0 ? 4'h6 : _mem_xcpt_causes_T_4; // @[lsu.scala:321:49, :803:8, :804:8] wire [3:0] _mem_xcpt_causes_T_6 = _mem_xcpt_causes_T_5; // @[lsu.scala:802:8, :803:8] wire [3:0] _mem_xcpt_causes_T_7 = _mem_xcpt_causes_T_6; // @[lsu.scala:801:8, :802:8] wire [3:0] _mem_xcpt_causes_WIRE_0 = _mem_xcpt_causes_T_7; // @[lsu.scala:321:49, :801:8] reg [3:0] mem_xcpt_causes_0; // @[lsu.scala:800:32] assign mem_xcpt_cause = mem_xcpt_causes_0; // @[lsu.scala:458:29, :800:32] reg [63:0] mem_xcpt_vaddrs_0; // @[lsu.scala:810:32] assign mem_xcpt_vaddr = mem_xcpt_vaddrs_0; // @[lsu.scala:460:29, :810:32] wire _exe_tlb_miss_T_1; // @[lsu.scala:835:83] wire _exe_tlb_miss_T_2 = exe_tlb_valid_0 & _exe_tlb_miss_T_1; // @[lsu.scala:649:27, :835:{58,83}] wire exe_tlb_miss_0 = _exe_tlb_miss_T_2; // @[lsu.scala:321:49, :835:58] wire [19:0] _exe_tlb_paddr_T = _dtlb_io_resp_0_paddr[31:12]; // @[lsu.scala:308:20, :836:62] wire [11:0] _exe_tlb_paddr_T_1 = exe_tlb_vaddr_0[11:0]; // @[lsu.scala:321:49, :837:57] wire [31:0] _exe_tlb_paddr_T_2 = {_exe_tlb_paddr_T, _exe_tlb_paddr_T_1}; // @[lsu.scala:836:{40,62}, :837:57] wire [31:0] exe_tlb_paddr_0 = _exe_tlb_paddr_T_2; // @[lsu.scala:321:49, :836:40] wire _exe_tlb_uncacheable_T = ~_dtlb_io_resp_0_cacheable; // @[lsu.scala:308:20, :838:43] wire exe_tlb_uncacheable_0 = _exe_tlb_uncacheable_T; // @[lsu.scala:321:49, :838:43] reg REG; // @[lsu.scala:845:21] wire [15:0] _exe_agen_killed_T = io_core_brupdate_b1_mispredict_mask_0 & io_core_agen_0_bits_uop_br_mask_0; // @[util.scala:126:51] wire _exe_agen_killed_T_1 = |_exe_agen_killed_T; // @[util.scala:126:{51,59}] wire _exe_agen_killed_T_2 = _exe_agen_killed_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire exe_agen_killed_0 = _exe_agen_killed_T_2; // @[util.scala:61:61] assign io_dmem_req_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_valid_0 = dmem_req_0_valid; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_inst_0 = dmem_req_0_bits_uop_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_inst_0 = dmem_req_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rvc_0 = dmem_req_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_pc_0 = dmem_req_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_0_0 = dmem_req_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_1_0 = dmem_req_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_2_0 = dmem_req_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iq_type_3_0 = dmem_req_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_0_0 = dmem_req_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_1_0 = dmem_req_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_2_0 = dmem_req_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_3_0 = dmem_req_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_4_0 = dmem_req_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_5_0 = dmem_req_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_6_0 = dmem_req_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_7_0 = dmem_req_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_8_0 = dmem_req_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fu_code_9_0 = dmem_req_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_0 = dmem_req_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_agen_0 = dmem_req_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = dmem_req_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_speculative_child_0 = dmem_req_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_speculative_child_0 = dmem_req_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = dmem_req_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = dmem_req_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = dmem_req_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dis_col_sel_0 = dmem_req_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_mask_0 = dmem_req_0_bits_uop_br_mask; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_tag_0 = dmem_req_0_bits_uop_br_tag; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_br_type_0 = dmem_req_0_bits_uop_br_type; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfb_0 = dmem_req_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fence_0 = dmem_req_0_bits_uop_is_fence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_fencei_0 = dmem_req_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sfence_0 = dmem_req_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_amo_0 = dmem_req_0_bits_uop_is_amo; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_eret_0 = dmem_req_0_bits_uop_is_eret; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc_0 = dmem_req_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_rocc_0 = dmem_req_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_mov_0 = dmem_req_0_bits_uop_is_mov; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ftq_idx_0 = dmem_req_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_edge_inst_0 = dmem_req_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pc_lob_0 = dmem_req_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_taken_0 = dmem_req_0_bits_uop_taken; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_rename_0 = dmem_req_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_sel_0 = dmem_req_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pimm_0 = dmem_req_0_bits_uop_pimm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_imm_packed_0 = dmem_req_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op1_sel_0 = dmem_req_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_op2_sel_0 = dmem_req_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ldst_0 = dmem_req_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wen_0 = dmem_req_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren1_0 = dmem_req_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren2_0 = dmem_req_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_ren3_0 = dmem_req_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap12_0 = dmem_req_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_swap23_0 = dmem_req_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = dmem_req_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fromint_0 = dmem_req_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_toint_0 = dmem_req_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = dmem_req_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_fma_0 = dmem_req_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_div_0 = dmem_req_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = dmem_req_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_wflags_0 = dmem_req_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_ctrl_vec_0 = dmem_req_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rob_idx_0 = dmem_req_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldq_idx_0 = dmem_req_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stq_idx_0 = dmem_req_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_rxq_idx_0 = dmem_req_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_pdst_0 = dmem_req_0_bits_uop_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_0 = dmem_req_0_bits_uop_prs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_0 = dmem_req_0_bits_uop_prs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_0 = dmem_req_0_bits_uop_prs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_0 = dmem_req_0_bits_uop_ppred; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs1_busy_0 = dmem_req_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs2_busy_0 = dmem_req_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_prs3_busy_0 = dmem_req_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ppred_busy_0 = dmem_req_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_stale_pdst_0 = dmem_req_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exception_0 = dmem_req_0_bits_uop_exception; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_exc_cause_0 = dmem_req_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_cmd_0 = dmem_req_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_size_0 = dmem_req_0_bits_uop_mem_size; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_mem_signed_0 = dmem_req_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_ldq_0 = dmem_req_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_uses_stq_0 = dmem_req_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_is_unique_0 = dmem_req_0_bits_uop_is_unique; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_flush_on_commit_0 = dmem_req_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_csr_cmd_0 = dmem_req_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1_0 = dmem_req_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_ldst_0 = dmem_req_0_bits_uop_ldst; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_0 = dmem_req_0_bits_uop_lrs1; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_0 = dmem_req_0_bits_uop_lrs2; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs3_0 = dmem_req_0_bits_uop_lrs3; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_dst_rtype_0 = dmem_req_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs1_rtype_0 = dmem_req_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_lrs2_rtype_0 = dmem_req_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_frs3_en_0 = dmem_req_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_dw_0 = dmem_req_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fcn_op_0 = dmem_req_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_val_0 = dmem_req_0_bits_uop_fp_val; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_rm_0 = dmem_req_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_fp_typ_0 = dmem_req_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if_0 = dmem_req_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if_0 = dmem_req_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if_0 = dmem_req_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_debug_if_0 = dmem_req_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if_0 = dmem_req_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_fsrc_0 = dmem_req_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_uop_debug_tsrc_0 = dmem_req_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_addr_0 = dmem_req_0_bits_addr; // @[lsu.scala:211:7, :877:22] wire [39:0] _mem_paddr_WIRE_0 = dmem_req_0_bits_addr; // @[lsu.scala:321:49, :877:22] assign io_dmem_req_bits_0_bits_data_0 = dmem_req_0_bits_data; // @[lsu.scala:211:7, :877:22] assign io_dmem_req_bits_0_bits_is_hella_0 = dmem_req_0_bits_is_hella; // @[lsu.scala:211:7, :877:22] wire _dmem_req_fire_T = io_dmem_req_ready_0 & io_dmem_req_valid_0; // @[Decoupled.scala:51:35] wire _dmem_req_fire_T_1 = dmem_req_0_valid & _dmem_req_fire_T; // @[Decoupled.scala:51:35] wire dmem_req_fire_0 = _dmem_req_fire_T_1; // @[lsu.scala:321:49, :880:55] wire s0_executing_loads_0; // @[lsu.scala:882:36] wire s0_executing_loads_1; // @[lsu.scala:882:36] wire s0_executing_loads_2; // @[lsu.scala:882:36] wire s0_executing_loads_3; // @[lsu.scala:882:36] wire s0_executing_loads_4; // @[lsu.scala:882:36] wire s0_executing_loads_5; // @[lsu.scala:882:36] wire s0_executing_loads_6; // @[lsu.scala:882:36] wire s0_executing_loads_7; // @[lsu.scala:882:36] wire s0_executing_loads_8; // @[lsu.scala:882:36] wire s0_executing_loads_9; // @[lsu.scala:882:36] wire s0_executing_loads_10; // @[lsu.scala:882:36] wire s0_executing_loads_11; // @[lsu.scala:882:36] wire s0_executing_loads_12; // @[lsu.scala:882:36] wire s0_executing_loads_13; // @[lsu.scala:882:36] wire s0_executing_loads_14; // @[lsu.scala:882:36] wire s0_executing_loads_15; // @[lsu.scala:882:36] wire s0_executing_loads_16; // @[lsu.scala:882:36] wire s0_executing_loads_17; // @[lsu.scala:882:36] wire s0_executing_loads_18; // @[lsu.scala:882:36] wire s0_executing_loads_19; // @[lsu.scala:882:36] wire s0_executing_loads_20; // @[lsu.scala:882:36] wire s0_executing_loads_21; // @[lsu.scala:882:36] wire s0_executing_loads_22; // @[lsu.scala:882:36] wire s0_executing_loads_23; // @[lsu.scala:882:36] wire s0_kills_0; // @[lsu.scala:883:22] wire _io_dmem_s1_kill_0_T = s0_kills_0 & dmem_req_fire_0; // @[lsu.scala:321:49, :883:22, :893:47] reg io_dmem_s1_kill_0_REG; // @[lsu.scala:893:34] wire [39:0] _GEN_471 = {8'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :897:30] wire _GEN_472 = exe_tlb_miss_0 | exe_tlb_uncacheable_0; // @[lsu.scala:321:49, :900:49] wire _s0_kills_0_T; // @[lsu.scala:900:49] assign _s0_kills_0_T = _GEN_472; // @[lsu.scala:900:49] wire _s0_kills_0_T_4; // @[lsu.scala:909:38] assign _s0_kills_0_T_4 = _GEN_472; // @[lsu.scala:900:49, :909:38] wire _s0_kills_0_T_1 = _s0_kills_0_T | ma_ld_0; // @[lsu.scala:321:49, :900:{49,75}] wire _s0_kills_0_T_2 = _s0_kills_0_T_1 | ae_ld_0; // @[lsu.scala:321:49, :900:{75,87}] wire _s0_kills_0_T_3 = _s0_kills_0_T_2 | pf_ld_0; // @[lsu.scala:321:49, :900:{87,99}] wire _s0_executing_loads_T = ~s0_kills_0; // @[lsu.scala:883:22, :901:70] wire _s0_executing_loads_T_1 = dmem_req_fire_0 & _s0_executing_loads_T; // @[lsu.scala:321:49, :901:{67,70}] wire _s0_kills_0_T_5 = _s0_kills_0_T_4 | ma_ld_0; // @[lsu.scala:321:49, :909:{38,64}] wire _s0_kills_0_T_6 = _s0_kills_0_T_5 | ae_ld_0; // @[lsu.scala:321:49, :909:{64,76}] wire _s0_kills_0_T_7 = _s0_kills_0_T_6 | pf_ld_0; // @[lsu.scala:321:49, :909:{76,88}] assign s0_kills_0 = will_fire_load_agen_exec_0 ? _s0_kills_0_T_3 : will_fire_load_retry_0 & _s0_kills_0_T_7; // @[lsu.scala:469:39, :476:41, :883:22, :892:17, :895:40, :900:{30,99}, :904:43, :909:{19,88}] wire _s0_executing_loads_T_2 = ~s0_kills_0; // @[lsu.scala:883:22, :901:70, :910:64] wire _s0_executing_loads_T_3 = dmem_req_fire_0 & _s0_executing_loads_T_2; // @[lsu.scala:321:49, :910:{61,64}] wire [1:0] dmem_req_0_bits_data_size; // @[AMOALU.scala:11:18] wire _dmem_req_0_bits_data_T = dmem_req_0_bits_data_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _dmem_req_0_bits_data_T_1 = _stq_execute_queue_io_deq_bits_data_bits[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_2 = {2{_dmem_req_0_bits_data_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_3 = {2{_dmem_req_0_bits_data_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_4 = {2{_dmem_req_0_bits_data_T_3}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_5 = dmem_req_0_bits_data_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _dmem_req_0_bits_data_T_6 = _stq_execute_queue_io_deq_bits_data_bits[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_7 = {2{_dmem_req_0_bits_data_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_8 = {2{_dmem_req_0_bits_data_T_7}}; // @[AMOALU.scala:29:32] wire _dmem_req_0_bits_data_T_9 = dmem_req_0_bits_data_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _dmem_req_0_bits_data_T_10 = _stq_execute_queue_io_deq_bits_data_bits[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_11 = {2{_dmem_req_0_bits_data_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_12 = _dmem_req_0_bits_data_T_9 ? _dmem_req_0_bits_data_T_11 : _stq_execute_queue_io_deq_bits_data_bits; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_13 = _dmem_req_0_bits_data_T_5 ? _dmem_req_0_bits_data_T_8 : _dmem_req_0_bits_data_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _dmem_req_0_bits_data_T_14 = _dmem_req_0_bits_data_T ? _dmem_req_0_bits_data_T_4 : _dmem_req_0_bits_data_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _GEN_473 = will_fire_load_agen_exec_0 | will_fire_load_retry_0; // @[lsu.scala:469:39, :476:41, :556:41, :895:40, :904:43, :911:84] assign dmem_req_0_bits_uop_inst = _GEN_473 ? exe_tlb_uop_0_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_inst = _GEN_473 ? exe_tlb_uop_0_debug_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_inst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rvc = _GEN_473 ? exe_tlb_uop_0_is_rvc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_rvc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_pc = _GEN_473 ? exe_tlb_uop_0_debug_pc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_pc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_0 = _GEN_473 ? exe_tlb_uop_0_iq_type_0 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_1 = _GEN_473 ? exe_tlb_uop_0_iq_type_1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_2 = _GEN_473 ? exe_tlb_uop_0_iq_type_2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iq_type_3 = _GEN_473 ? exe_tlb_uop_0_iq_type_3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iq_type_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_0 = _GEN_473 ? exe_tlb_uop_0_fu_code_0 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_0 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_1 = _GEN_473 ? exe_tlb_uop_0_fu_code_1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_2 = _GEN_473 ? exe_tlb_uop_0_fu_code_2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_3 = _GEN_473 ? exe_tlb_uop_0_fu_code_3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_4 = _GEN_473 ? exe_tlb_uop_0_fu_code_4 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_4 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_5 = _GEN_473 ? exe_tlb_uop_0_fu_code_5 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_5 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_6 = _GEN_473 ? exe_tlb_uop_0_fu_code_6 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_6 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_7 = _GEN_473 ? exe_tlb_uop_0_fu_code_7 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_7 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_8 = _GEN_473 ? exe_tlb_uop_0_fu_code_8 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_8 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fu_code_9 = _GEN_473 ? exe_tlb_uop_0_fu_code_9 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fu_code_9 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued = _GEN_473 ? exe_tlb_uop_0_iw_issued : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_agen = _GEN_473 ? exe_tlb_uop_0_iw_issued_partial_agen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_agen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_issued_partial_dgen = _GEN_473 ? exe_tlb_uop_0_iw_issued_partial_dgen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_issued_partial_dgen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_speculative_child = _GEN_473 ? exe_tlb_uop_0_iw_p1_speculative_child : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_speculative_child = _GEN_473 ? exe_tlb_uop_0_iw_p2_speculative_child : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_speculative_child : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p1_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p1_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p1_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p2_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p2_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p2_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_iw_p3_bypass_hint = _GEN_473 ? exe_tlb_uop_0_iw_p3_bypass_hint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_iw_p3_bypass_hint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dis_col_sel = _GEN_473 ? exe_tlb_uop_0_dis_col_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_dis_col_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_mask = _GEN_473 ? exe_tlb_uop_0_br_mask : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_mask : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_tag = _GEN_473 ? exe_tlb_uop_0_br_tag : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_tag : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_br_type = _GEN_473 ? exe_tlb_uop_0_br_type : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_br_type : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfb = _GEN_473 ? exe_tlb_uop_0_is_sfb : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sfb : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fence = _GEN_473 ? exe_tlb_uop_0_is_fence : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_fence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_fencei = _GEN_473 ? exe_tlb_uop_0_is_fencei : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_fencei : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sfence = _GEN_473 ? exe_tlb_uop_0_is_sfence : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sfence : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_amo = _GEN_473 ? exe_tlb_uop_0_is_amo : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_amo : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_eret = _GEN_473 ? exe_tlb_uop_0_is_eret : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_eret : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_sys_pc2epc = _GEN_473 ? exe_tlb_uop_0_is_sys_pc2epc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_sys_pc2epc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_rocc = _GEN_473 ? exe_tlb_uop_0_is_rocc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_rocc : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_mov = _GEN_473 ? exe_tlb_uop_0_is_mov : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_mov : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ftq_idx = _GEN_473 ? exe_tlb_uop_0_ftq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ftq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_edge_inst = _GEN_473 ? exe_tlb_uop_0_edge_inst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_edge_inst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pc_lob = _GEN_473 ? exe_tlb_uop_0_pc_lob : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pc_lob : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_taken = _GEN_473 ? exe_tlb_uop_0_taken : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_taken : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_rename = _GEN_473 ? exe_tlb_uop_0_imm_rename : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_rename : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_sel = _GEN_473 ? exe_tlb_uop_0_imm_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pimm = _GEN_473 ? exe_tlb_uop_0_pimm : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pimm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_imm_packed = _GEN_473 ? exe_tlb_uop_0_imm_packed : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_imm_packed : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op1_sel = _GEN_473 ? exe_tlb_uop_0_op1_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_op1_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_op2_sel = _GEN_473 ? exe_tlb_uop_0_op2_sel : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_op2_sel : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ldst = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ldst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ldst : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wen = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_wen : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wen : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren1 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren2 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren2 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_ren3 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_ren3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_ren3 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap12 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_swap12 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap12 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_swap23 = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_swap23 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_swap23 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagIn = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_typeTagIn : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagIn : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_typeTagOut = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_typeTagOut : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_typeTagOut : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fromint = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fromint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fromint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_toint = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_toint : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_toint : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fastpipe = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fastpipe : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fastpipe : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_fma = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_fma : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_fma : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_div = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_div : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_div : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_sqrt = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_sqrt : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_sqrt : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_wflags = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_wflags : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_wflags : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_ctrl_vec = _GEN_473 ? exe_tlb_uop_0_fp_ctrl_vec : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_ctrl_vec : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rob_idx = _GEN_473 ? exe_tlb_uop_0_rob_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_rob_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldq_idx = _GEN_473 ? exe_tlb_uop_0_ldq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stq_idx = _GEN_473 ? exe_tlb_uop_0_stq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_stq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_rxq_idx = _GEN_473 ? exe_tlb_uop_0_rxq_idx : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_rxq_idx : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_pdst = _GEN_473 ? exe_tlb_uop_0_pdst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1 = _GEN_473 ? exe_tlb_uop_0_prs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2 = _GEN_473 ? exe_tlb_uop_0_prs2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3 = _GEN_473 ? exe_tlb_uop_0_prs3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred = _GEN_473 ? exe_tlb_uop_0_ppred : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ppred : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs1_busy = _GEN_473 ? exe_tlb_uop_0_prs1_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs1_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs2_busy = _GEN_473 ? exe_tlb_uop_0_prs2_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs2_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_prs3_busy = _GEN_473 ? exe_tlb_uop_0_prs3_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_prs3_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ppred_busy = _GEN_473 ? exe_tlb_uop_0_ppred_busy : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ppred_busy : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_stale_pdst = _GEN_473 ? exe_tlb_uop_0_stale_pdst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_stale_pdst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exception = _GEN_473 ? exe_tlb_uop_0_exception : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_exception : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_exc_cause = _GEN_473 ? exe_tlb_uop_0_exc_cause : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_exc_cause : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_ldq = _GEN_473 ? exe_tlb_uop_0_uses_ldq : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_uses_ldq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_uses_stq = _GEN_473 ? exe_tlb_uop_0_uses_stq : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_uses_stq : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_is_unique = _GEN_473 ? exe_tlb_uop_0_is_unique : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_is_unique : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_flush_on_commit = _GEN_473 ? exe_tlb_uop_0_flush_on_commit : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_flush_on_commit : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_csr_cmd = _GEN_473 ? exe_tlb_uop_0_csr_cmd : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_csr_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst_is_rs1 = _GEN_473 ? exe_tlb_uop_0_ldst_is_rs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldst_is_rs1 : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_ldst = _GEN_473 ? exe_tlb_uop_0_ldst : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_ldst : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1 = _GEN_473 ? exe_tlb_uop_0_lrs1 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs1 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2 = _GEN_473 ? exe_tlb_uop_0_lrs2 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs2 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs3 = _GEN_473 ? exe_tlb_uop_0_lrs3 : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs3 : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_dst_rtype = _GEN_473 ? exe_tlb_uop_0_dst_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_dst_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs1_rtype = _GEN_473 ? exe_tlb_uop_0_lrs1_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs1_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_lrs2_rtype = _GEN_473 ? exe_tlb_uop_0_lrs2_rtype : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_lrs2_rtype : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_frs3_en = _GEN_473 ? exe_tlb_uop_0_frs3_en : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_frs3_en : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_dw = _GEN_473 ? exe_tlb_uop_0_fcn_dw : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fcn_dw : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fcn_op = _GEN_473 ? exe_tlb_uop_0_fcn_op : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fcn_op : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_val = _GEN_473 ? exe_tlb_uop_0_fp_val : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_val : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_rm = _GEN_473 ? exe_tlb_uop_0_fp_rm : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_rm : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_fp_typ = _GEN_473 ? exe_tlb_uop_0_fp_typ : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_fp_typ : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_pf_if = _GEN_473 ? exe_tlb_uop_0_xcpt_pf_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_pf_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ae_if = _GEN_473 ? exe_tlb_uop_0_xcpt_ae_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ae_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_xcpt_ma_if = _GEN_473 ? exe_tlb_uop_0_xcpt_ma_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_xcpt_ma_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_debug_if = _GEN_473 ? exe_tlb_uop_0_bp_debug_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_bp_debug_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_bp_xcpt_if = _GEN_473 ? exe_tlb_uop_0_bp_xcpt_if : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_bp_xcpt_if : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_fsrc = _GEN_473 ? exe_tlb_uop_0_debug_fsrc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_fsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign dmem_req_0_bits_uop_debug_tsrc = _GEN_473 ? exe_tlb_uop_0_debug_tsrc : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_debug_tsrc : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30] assign s0_executing_loads_0 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h0 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_447 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_423 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_1 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h1 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_448 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_424 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_2 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h2 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_449 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_425 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_3 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h3 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_450 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_426 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_4 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h4 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_451 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_427 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_5 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h5 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_452 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_428 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_6 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h6 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_453 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_429 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_7 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h7 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_454 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_430 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_8 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h8 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_455 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_431 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_9 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h9 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_456 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_432 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_10 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hA & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_457 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_433 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_11 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hB & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_458 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_434 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_12 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hC & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_459 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_435 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_13 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hD & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_460 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_436 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_14 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hE & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_461 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_437 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_15 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'hF & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_462 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_438 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_16 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h10 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_463 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_439 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_17 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h11 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_464 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_440 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_18 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h12 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_465 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_441 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_19 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h13 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_466 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_442 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_20 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h14 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_467 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_443 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_21 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h15 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_468 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_444 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_22 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h16 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_469 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_445 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] assign s0_executing_loads_23 = will_fire_load_agen_exec_0 ? ldq_incoming_idx_0 == 5'h17 & _s0_executing_loads_T_1 : will_fire_load_retry_0 ? _GEN_470 & _s0_executing_loads_T_3 : ~_T_1639 & will_fire_load_wakeup_0 & _GEN_446 & dmem_req_fire_0; // @[lsu.scala:321:49, :406:59, :469:39, :476:41, :480:41, :565:78, :690:49, :694:49, :882:36, :895:40, :901:{47,67}, :904:43, :910:{41,61}, :911:84, :926:44, :931:42] wire _dmem_req_0_valid_T = ~io_hellacache_s1_kill_0; // @[lsu.scala:211:7, :937:42] wire _dmem_req_0_valid_T_3 = _dmem_req_0_valid_T; // @[lsu.scala:937:{42,65}] wire _dmem_req_0_valid_T_1 = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69] wire _GEN_474 = will_fire_load_agen_exec_0 | will_fire_load_retry_0 | _T_1639 | will_fire_load_wakeup_0; // @[lsu.scala:304:34, :469:39, :476:41, :480:41, :565:78, :895:40, :904:43, :911:84, :926:44, :934:47] assign dmem_req_0_valid = _GEN_474 | (will_fire_hella_incoming_0 ? _dmem_req_0_valid_T_3 : will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :895:40, :896:30, :904:43, :905:30, :911:84, :912:33, :926:44, :927:30, :934:47, :937:{39,65}, :951:5] assign dmem_req_0_bits_addr = will_fire_load_agen_exec_0 | will_fire_load_retry_0 ? _GEN_471 : _T_1639 ? _stq_execute_queue_io_deq_bits_addr_bits : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_addr_bits : will_fire_hella_incoming_0 ? _GEN_471 : will_fire_hella_wakeup_0 ? {8'h0, hella_paddr} : 40'h0; // @[lsu.scala:304:34, :469:39, :473:41, :474:41, :476:41, :480:41, :510:32, :558:11, :565:78, :877:22, :888:28, :895:40, :897:30, :904:43, :911:84, :913:33, :926:44, :928:30, :934:47, :938:39, :951:5, :954:39] wire [7:0] _dmem_req_0_bits_data_T_31 = hella_data_data[7:0]; // @[AMOALU.scala:29:69] wire [15:0] _dmem_req_0_bits_data_T_32 = {2{_dmem_req_0_bits_data_T_31}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _dmem_req_0_bits_data_T_33 = {2{_dmem_req_0_bits_data_T_32}}; // @[AMOALU.scala:29:32] wire [63:0] _dmem_req_0_bits_data_T_34 = {2{_dmem_req_0_bits_data_T_33}}; // @[AMOALU.scala:29:32] wire [15:0] _dmem_req_0_bits_data_T_36 = hella_data_data[15:0]; // @[AMOALU.scala:29:69] wire [31:0] _dmem_req_0_bits_data_T_37 = {2{_dmem_req_0_bits_data_T_36}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_38 = {2{_dmem_req_0_bits_data_T_37}}; // @[AMOALU.scala:29:32] wire [31:0] _dmem_req_0_bits_data_T_40 = hella_data_data[31:0]; // @[AMOALU.scala:29:69] wire [63:0] _dmem_req_0_bits_data_T_41 = {2{_dmem_req_0_bits_data_T_40}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _dmem_req_0_bits_data_T_43 = _dmem_req_0_bits_data_T_42; // @[AMOALU.scala:29:13] wire [63:0] _dmem_req_0_bits_data_T_44 = _dmem_req_0_bits_data_T_43; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_data = _GEN_473 ? 64'h0 : _T_1639 ? _dmem_req_0_bits_data_T_14 : will_fire_load_wakeup_0 | will_fire_hella_incoming_0 | ~will_fire_hella_wakeup_0 ? 64'h0 : _dmem_req_0_bits_data_T_44; // @[AMOALU.scala:29:13] assign dmem_req_0_bits_uop_mem_cmd = _GEN_473 ? exe_tlb_uop_0_mem_cmd : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_cmd : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_uop_mem_size = _GEN_473 ? exe_tlb_uop_0_mem_size : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_size : will_fire_load_wakeup_0 ? ldq_wakeup_e_bits_uop_mem_size : {2{will_fire_hella_incoming_0 | will_fire_hella_wakeup_0}}; // @[lsu.scala:321:49, :473:41, :474:41, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :887:28, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47, :944:39, :951:5, :960:39] assign dmem_req_0_bits_uop_mem_signed = _GEN_473 ? exe_tlb_uop_0_mem_signed : _T_1639 ? _stq_execute_queue_io_deq_bits_uop_mem_signed : will_fire_load_wakeup_0 & ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :480:41, :510:32, :556:41, :558:11, :565:78, :877:22, :895:40, :898:30, :904:43, :907:30, :911:84, :918:33, :926:44, :929:30, :934:47] assign dmem_req_0_bits_is_hella = ~_GEN_474 & (will_fire_hella_incoming_0 | will_fire_hella_wakeup_0); // @[lsu.scala:304:34, :473:41, :474:41, :877:22, :890:31, :895:40, :904:43, :911:84, :926:44, :934:47, :946:39, :951:5] wire _T_227 = _T_226 | will_fire_load_retry_0; // @[lsu.scala:476:41, :687:61, :967:65] wire [4:0] ldq_idx = _ldq_idx_T ? ldq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_ldq_idx; // @[lsu.scala:321:49, :533:27, :969:{24,48}] wire _ldq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50] wire _ldq_addr_valid_T_1 = _ldq_addr_valid_T | will_fire_load_retry_0; // @[lsu.scala:476:41, :970:{50,70}] wire [63:0] _GEN_475 = exe_tlb_miss_0 ? exe_tlb_vaddr_0 : {32'h0, exe_tlb_paddr_0}; // @[lsu.scala:321:49, :971:53] wire [63:0] _ldq_addr_bits_T; // @[lsu.scala:971:53] assign _ldq_addr_bits_T = _GEN_475; // @[lsu.scala:971:53] wire [63:0] _stq_addr_bits_T; // @[lsu.scala:987:48] assign _stq_addr_bits_T = _GEN_475; // @[lsu.scala:971:53, :987:48] wire [7:0] ldq_ld_byte_mask_mask; // @[lsu.scala:1951:22] wire _ldq_ld_byte_mask_mask_T = exe_tlb_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _ldq_ld_byte_mask_mask_T_1 = exe_tlb_vaddr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _ldq_ld_byte_mask_mask_T_2 = 15'h1 << _ldq_ld_byte_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _ldq_ld_byte_mask_mask_T_3 = exe_tlb_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _ldq_ld_byte_mask_mask_T_4 = exe_tlb_vaddr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _ldq_ld_byte_mask_mask_T_5 = {_ldq_ld_byte_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _ldq_ld_byte_mask_mask_T_6 = 15'h3 << _ldq_ld_byte_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _ldq_ld_byte_mask_mask_T_7 = exe_tlb_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _ldq_ld_byte_mask_mask_T_8 = exe_tlb_vaddr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _ldq_ld_byte_mask_mask_T_9 = _ldq_ld_byte_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _ldq_ld_byte_mask_mask_T_10 = &exe_tlb_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _ldq_ld_byte_mask_mask_T_12 = _ldq_ld_byte_mask_mask_T_7 ? _ldq_ld_byte_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_13 = _ldq_ld_byte_mask_mask_T_3 ? _ldq_ld_byte_mask_mask_T_6 : {7'h0, _ldq_ld_byte_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _ldq_ld_byte_mask_mask_T_14 = _ldq_ld_byte_mask_mask_T ? _ldq_ld_byte_mask_mask_T_2 : _ldq_ld_byte_mask_mask_T_13; // @[Mux.scala:126:16] assign ldq_ld_byte_mask_mask = _ldq_ld_byte_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _ldq_addr_is_uncacheable_T = ~exe_tlb_miss_0; // @[lsu.scala:321:49, :937:69, :975:76] wire _ldq_addr_is_uncacheable_T_1 = exe_tlb_uncacheable_0 & _ldq_addr_is_uncacheable_T; // @[lsu.scala:321:49, :975:{73,76}] wire _T_232 = will_fire_store_agen_0 | will_fire_store_retry_0; // @[lsu.scala:471:41, :477:41, :981:35] wire [4:0] stq_idx = will_fire_store_agen_0 ? stq_incoming_idx_0 : _retry_queue_io_deq_bits_uop_stq_idx; // @[lsu.scala:321:49, :471:41, :533:27, :983:24] wire _stq_addr_valid_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :986:46] wire _stq_addr_valid_T_1 = _stq_addr_valid_T | will_fire_store_retry_0; // @[lsu.scala:477:41, :986:{46,66}] wire _stq_addr_valid_T_2 = ~pf_st_0; // @[lsu.scala:321:49, :986:98] wire _stq_addr_valid_T_3 = _stq_addr_valid_T_1 & _stq_addr_valid_T_2; // @[lsu.scala:986:{66,95,98}] wire slow_wakeups_0_valid; // @[lsu.scala:1495:26] wire _fired_load_agen_exec_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1041:83] wire _fired_load_agen_exec_T_1 = will_fire_load_agen_exec_0 & _fired_load_agen_exec_T; // @[lsu.scala:469:39, :1041:{80,83}] reg fired_load_agen_exec_REG; // @[lsu.scala:1041:51] wire fired_load_agen_exec_0 = fired_load_agen_exec_REG; // @[lsu.scala:321:49, :1041:51] wire _fired_load_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1042:83] wire _fired_load_agen_T_1 = will_fire_load_agen_0 & _fired_load_agen_T; // @[lsu.scala:470:41, :1042:{80,83}] reg fired_load_agen_REG; // @[lsu.scala:1042:51] wire fired_load_agen_0 = fired_load_agen_REG; // @[lsu.scala:321:49, :1042:51] wire _fired_store_agen_T = ~exe_agen_killed_0; // @[lsu.scala:321:49, :970:50, :1043:83] wire _fired_store_agen_T_1 = will_fire_store_agen_0 & _fired_store_agen_T; // @[lsu.scala:471:41, :1043:{80,83}] reg fired_store_agen_REG; // @[lsu.scala:1043:51] wire fired_store_agen_0 = fired_store_agen_REG; // @[lsu.scala:321:49, :1043:51] reg fired_sfence_0; // @[lsu.scala:1044:37] reg fired_release_0; // @[lsu.scala:1045:37] wire do_release_search_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire lcam_is_release_0 = fired_release_0; // @[lsu.scala:321:49, :1045:37] wire [15:0] _GEN_476 = io_core_brupdate_b1_mispredict_mask_0 & _retry_queue_io_deq_bits_uop_br_mask; // @[util.scala:126:51] wire [15:0] _fired_load_retry_T; // @[util.scala:126:51] assign _fired_load_retry_T = _GEN_476; // @[util.scala:126:51] wire [15:0] _fired_store_retry_T; // @[util.scala:126:51] assign _fired_store_retry_T = _GEN_476; // @[util.scala:126:51] wire _fired_load_retry_T_1 = |_fired_load_retry_T; // @[util.scala:126:{51,59}] wire _fired_load_retry_T_2 = _fired_load_retry_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_retry_T_3 = ~_fired_load_retry_T_2; // @[util.scala:61:61] wire _fired_load_retry_T_4 = will_fire_load_retry_0 & _fired_load_retry_T_3; // @[lsu.scala:476:41, :1046:{79,82}] reg fired_load_retry_REG; // @[lsu.scala:1046:51] wire fired_load_retry_0 = fired_load_retry_REG; // @[lsu.scala:321:49, :1046:51] wire _fired_store_retry_T_1 = |_fired_store_retry_T; // @[util.scala:126:{51,59}] wire _fired_store_retry_T_2 = _fired_store_retry_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_store_retry_T_3 = ~_fired_store_retry_T_2; // @[util.scala:61:61] wire _fired_store_retry_T_4 = will_fire_store_retry_0 & _fired_store_retry_T_3; // @[lsu.scala:477:41, :1047:{79,82}] reg fired_store_retry_REG; // @[lsu.scala:1047:51] wire fired_store_retry_0 = fired_store_retry_REG; // @[lsu.scala:321:49, :1047:51] reg fired_store_commit_REG; // @[lsu.scala:1048:51] wire fired_store_commit_0 = fired_store_commit_REG; // @[lsu.scala:321:49, :1048:51] wire [15:0] _GEN_477 = io_core_brupdate_b1_mispredict_mask_0 & ldq_wakeup_e_bits_uop_br_mask; // @[util.scala:126:51] wire [15:0] _fired_load_wakeup_T; // @[util.scala:126:51] assign _fired_load_wakeup_T = _GEN_477; // @[util.scala:126:51] wire [15:0] _mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:51] assign _mem_ldq_wakeup_e_out_valid_T = _GEN_477; // @[util.scala:126:51] wire _fired_load_wakeup_T_1 = |_fired_load_wakeup_T; // @[util.scala:126:{51,59}] wire _fired_load_wakeup_T_2 = _fired_load_wakeup_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _fired_load_wakeup_T_3 = ~_fired_load_wakeup_T_2; // @[util.scala:61:61] wire _fired_load_wakeup_T_4 = will_fire_load_wakeup_0 & _fired_load_wakeup_T_3; // @[lsu.scala:480:41, :1049:{79,82}] reg fired_load_wakeup_REG; // @[lsu.scala:1049:51] wire fired_load_wakeup_0 = fired_load_wakeup_REG; // @[lsu.scala:321:49, :1049:51] reg fired_hella_incoming_0; // @[lsu.scala:1050:37] reg fired_hella_wakeup_0; // @[lsu.scala:1051:37] wire [31:0] _mem_incoming_uop_WIRE_0_inst = mem_incoming_uop_out_inst; // @[util.scala:104:23] wire [31:0] _mem_incoming_uop_WIRE_0_debug_inst = mem_incoming_uop_out_debug_inst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rvc = mem_incoming_uop_out_is_rvc; // @[util.scala:104:23] wire [39:0] _mem_incoming_uop_WIRE_0_debug_pc = mem_incoming_uop_out_debug_pc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_0 = mem_incoming_uop_out_iq_type_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_1 = mem_incoming_uop_out_iq_type_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_2 = mem_incoming_uop_out_iq_type_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iq_type_3 = mem_incoming_uop_out_iq_type_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_0 = mem_incoming_uop_out_fu_code_0; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_1 = mem_incoming_uop_out_fu_code_1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_2 = mem_incoming_uop_out_fu_code_2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_3 = mem_incoming_uop_out_fu_code_3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_4 = mem_incoming_uop_out_fu_code_4; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_5 = mem_incoming_uop_out_fu_code_5; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_6 = mem_incoming_uop_out_fu_code_6; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_7 = mem_incoming_uop_out_fu_code_7; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_8 = mem_incoming_uop_out_fu_code_8; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fu_code_9 = mem_incoming_uop_out_fu_code_9; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued = mem_incoming_uop_out_iw_issued; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_agen = mem_incoming_uop_out_iw_issued_partial_agen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_issued_partial_dgen = mem_incoming_uop_out_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_iw_p1_speculative_child = mem_incoming_uop_out_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_iw_p2_speculative_child = mem_incoming_uop_out_iw_p2_speculative_child; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p1_bypass_hint = mem_incoming_uop_out_iw_p1_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p2_bypass_hint = mem_incoming_uop_out_iw_p2_bypass_hint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_iw_p3_bypass_hint = mem_incoming_uop_out_iw_p3_bypass_hint; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [2:0] _mem_incoming_uop_WIRE_0_dis_col_sel = mem_incoming_uop_out_dis_col_sel; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_WIRE_0_br_mask = mem_incoming_uop_out_br_mask; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_tag = mem_incoming_uop_out_br_tag; // @[util.scala:104:23] wire [3:0] _mem_incoming_uop_WIRE_0_br_type = mem_incoming_uop_out_br_type; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfb = mem_incoming_uop_out_is_sfb; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fence = mem_incoming_uop_out_is_fence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_fencei = mem_incoming_uop_out_is_fencei; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sfence = mem_incoming_uop_out_is_sfence; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_amo = mem_incoming_uop_out_is_amo; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_eret = mem_incoming_uop_out_is_eret; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_sys_pc2epc = mem_incoming_uop_out_is_sys_pc2epc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_rocc = mem_incoming_uop_out_is_rocc; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_mov = mem_incoming_uop_out_is_mov; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ftq_idx = mem_incoming_uop_out_ftq_idx; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_edge_inst = mem_incoming_uop_out_edge_inst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_pc_lob = mem_incoming_uop_out_pc_lob; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_taken = mem_incoming_uop_out_taken; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_imm_rename = mem_incoming_uop_out_imm_rename; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_imm_sel = mem_incoming_uop_out_imm_sel; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_pimm = mem_incoming_uop_out_pimm; // @[util.scala:104:23] wire [19:0] _mem_incoming_uop_WIRE_0_imm_packed = mem_incoming_uop_out_imm_packed; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_op1_sel = mem_incoming_uop_out_op1_sel; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_op2_sel = mem_incoming_uop_out_op2_sel; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ldst = mem_incoming_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wen = mem_incoming_uop_out_fp_ctrl_wen; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren1 = mem_incoming_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren2 = mem_incoming_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_ren3 = mem_incoming_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap12 = mem_incoming_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_swap23 = mem_incoming_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagIn = mem_incoming_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_ctrl_typeTagOut = mem_incoming_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fromint = mem_incoming_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_toint = mem_incoming_uop_out_fp_ctrl_toint; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fastpipe = mem_incoming_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_fma = mem_incoming_uop_out_fp_ctrl_fma; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_div = mem_incoming_uop_out_fp_ctrl_div; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_sqrt = mem_incoming_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_wflags = mem_incoming_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_ctrl_vec = mem_incoming_uop_out_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_rob_idx = mem_incoming_uop_out_rob_idx; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ldq_idx = mem_incoming_uop_out_ldq_idx; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_stq_idx = mem_incoming_uop_out_stq_idx; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_rxq_idx = mem_incoming_uop_out_rxq_idx; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_pdst = mem_incoming_uop_out_pdst; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs1 = mem_incoming_uop_out_prs1; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs2 = mem_incoming_uop_out_prs2; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_prs3 = mem_incoming_uop_out_prs3; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_ppred = mem_incoming_uop_out_ppred; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs1_busy = mem_incoming_uop_out_prs1_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs2_busy = mem_incoming_uop_out_prs2_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_prs3_busy = mem_incoming_uop_out_prs3_busy; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ppred_busy = mem_incoming_uop_out_ppred_busy; // @[util.scala:104:23] wire [6:0] _mem_incoming_uop_WIRE_0_stale_pdst = mem_incoming_uop_out_stale_pdst; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_exception = mem_incoming_uop_out_exception; // @[util.scala:104:23] wire [63:0] _mem_incoming_uop_WIRE_0_exc_cause = mem_incoming_uop_out_exc_cause; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_mem_cmd = mem_incoming_uop_out_mem_cmd; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_mem_size = mem_incoming_uop_out_mem_size; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_mem_signed = mem_incoming_uop_out_mem_signed; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_ldq = mem_incoming_uop_out_uses_ldq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_uses_stq = mem_incoming_uop_out_uses_stq; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_is_unique = mem_incoming_uop_out_is_unique; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_flush_on_commit = mem_incoming_uop_out_flush_on_commit; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_csr_cmd = mem_incoming_uop_out_csr_cmd; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_ldst_is_rs1 = mem_incoming_uop_out_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_ldst = mem_incoming_uop_out_ldst; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs1 = mem_incoming_uop_out_lrs1; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs2 = mem_incoming_uop_out_lrs2; // @[util.scala:104:23] wire [5:0] _mem_incoming_uop_WIRE_0_lrs3 = mem_incoming_uop_out_lrs3; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_dst_rtype = mem_incoming_uop_out_dst_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs1_rtype = mem_incoming_uop_out_lrs1_rtype; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_lrs2_rtype = mem_incoming_uop_out_lrs2_rtype; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_frs3_en = mem_incoming_uop_out_frs3_en; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fcn_dw = mem_incoming_uop_out_fcn_dw; // @[util.scala:104:23] wire [4:0] _mem_incoming_uop_WIRE_0_fcn_op = mem_incoming_uop_out_fcn_op; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_fp_val = mem_incoming_uop_out_fp_val; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_fp_rm = mem_incoming_uop_out_fp_rm; // @[util.scala:104:23] wire [1:0] _mem_incoming_uop_WIRE_0_fp_typ = mem_incoming_uop_out_fp_typ; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_pf_if = mem_incoming_uop_out_xcpt_pf_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ae_if = mem_incoming_uop_out_xcpt_ae_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_xcpt_ma_if = mem_incoming_uop_out_xcpt_ma_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_debug_if = mem_incoming_uop_out_bp_debug_if; // @[util.scala:104:23] wire _mem_incoming_uop_WIRE_0_bp_xcpt_if = mem_incoming_uop_out_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_fsrc = mem_incoming_uop_out_debug_fsrc; // @[util.scala:104:23] wire [2:0] _mem_incoming_uop_WIRE_0_debug_tsrc = mem_incoming_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _mem_incoming_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _mem_incoming_uop_out_br_mask_T_1 = io_core_agen_0_bits_uop_br_mask_0 & _mem_incoming_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign mem_incoming_uop_out_br_mask = _mem_incoming_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] mem_incoming_uop_0_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_inst = mem_incoming_uop_0_inst; // @[util.scala:109:23] reg [31:0] mem_incoming_uop_0_debug_inst; // @[lsu.scala:1053:37] wire [31:0] w1_bits_out_uop_debug_inst = mem_incoming_uop_0_debug_inst; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rvc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rvc = mem_incoming_uop_0_is_rvc; // @[util.scala:109:23] reg [39:0] mem_incoming_uop_0_debug_pc; // @[lsu.scala:1053:37] wire [39:0] w1_bits_out_uop_debug_pc = mem_incoming_uop_0_debug_pc; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_0 = mem_incoming_uop_0_iq_type_0; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_1 = mem_incoming_uop_0_iq_type_1; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_2 = mem_incoming_uop_0_iq_type_2; // @[util.scala:109:23] reg mem_incoming_uop_0_iq_type_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iq_type_3 = mem_incoming_uop_0_iq_type_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_0; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_0 = mem_incoming_uop_0_fu_code_0; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_1 = mem_incoming_uop_0_fu_code_1; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_2 = mem_incoming_uop_0_fu_code_2; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_3 = mem_incoming_uop_0_fu_code_3; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_4; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_4 = mem_incoming_uop_0_fu_code_4; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_5; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_5 = mem_incoming_uop_0_fu_code_5; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_6; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_6 = mem_incoming_uop_0_fu_code_6; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_7; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_7 = mem_incoming_uop_0_fu_code_7; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_8; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_8 = mem_incoming_uop_0_fu_code_8; // @[util.scala:109:23] reg mem_incoming_uop_0_fu_code_9; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fu_code_9 = mem_incoming_uop_0_fu_code_9; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued = mem_incoming_uop_0_iw_issued; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_agen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_agen = mem_incoming_uop_0_iw_issued_partial_agen; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_issued_partial_dgen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_issued_partial_dgen = mem_incoming_uop_0_iw_issued_partial_dgen; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_iw_p1_speculative_child; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_iw_p1_speculative_child = mem_incoming_uop_0_iw_p1_speculative_child; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_iw_p2_speculative_child; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_iw_p2_speculative_child = mem_incoming_uop_0_iw_p2_speculative_child; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p1_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p1_bypass_hint = mem_incoming_uop_0_iw_p1_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p2_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p2_bypass_hint = mem_incoming_uop_0_iw_p2_bypass_hint; // @[util.scala:109:23] reg mem_incoming_uop_0_iw_p3_bypass_hint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_iw_p3_bypass_hint = mem_incoming_uop_0_iw_p3_bypass_hint; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_dis_col_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_dis_col_sel = mem_incoming_uop_0_dis_col_sel; // @[util.scala:109:23] reg [15:0] mem_incoming_uop_0_br_mask; // @[lsu.scala:1053:37] reg [3:0] mem_incoming_uop_0_br_tag; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_tag = mem_incoming_uop_0_br_tag; // @[util.scala:109:23] reg [3:0] mem_incoming_uop_0_br_type; // @[lsu.scala:1053:37] wire [3:0] w1_bits_out_uop_br_type = mem_incoming_uop_0_br_type; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfb; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfb = mem_incoming_uop_0_is_sfb; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fence = mem_incoming_uop_0_is_fence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_fencei; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_fencei = mem_incoming_uop_0_is_fencei; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sfence; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sfence = mem_incoming_uop_0_is_sfence; // @[util.scala:109:23] reg mem_incoming_uop_0_is_amo; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_amo = mem_incoming_uop_0_is_amo; // @[util.scala:109:23] reg mem_incoming_uop_0_is_eret; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_eret = mem_incoming_uop_0_is_eret; // @[util.scala:109:23] reg mem_incoming_uop_0_is_sys_pc2epc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_sys_pc2epc = mem_incoming_uop_0_is_sys_pc2epc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_rocc; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_rocc = mem_incoming_uop_0_is_rocc; // @[util.scala:109:23] reg mem_incoming_uop_0_is_mov; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_mov = mem_incoming_uop_0_is_mov; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ftq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ftq_idx = mem_incoming_uop_0_ftq_idx; // @[util.scala:109:23] reg mem_incoming_uop_0_edge_inst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_edge_inst = mem_incoming_uop_0_edge_inst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_pc_lob; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_pc_lob = mem_incoming_uop_0_pc_lob; // @[util.scala:109:23] reg mem_incoming_uop_0_taken; // @[lsu.scala:1053:37] wire w1_bits_out_uop_taken = mem_incoming_uop_0_taken; // @[util.scala:109:23] reg mem_incoming_uop_0_imm_rename; // @[lsu.scala:1053:37] wire w1_bits_out_uop_imm_rename = mem_incoming_uop_0_imm_rename; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_imm_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_imm_sel = mem_incoming_uop_0_imm_sel; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_pimm; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_pimm = mem_incoming_uop_0_pimm; // @[util.scala:109:23] reg [19:0] mem_incoming_uop_0_imm_packed; // @[lsu.scala:1053:37] wire [19:0] w1_bits_out_uop_imm_packed = mem_incoming_uop_0_imm_packed; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_op1_sel; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_op1_sel = mem_incoming_uop_0_op1_sel; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_op2_sel; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_op2_sel = mem_incoming_uop_0_op2_sel; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ldst; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ldst = mem_incoming_uop_0_fp_ctrl_ldst; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wen; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wen = mem_incoming_uop_0_fp_ctrl_wen; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren1 = mem_incoming_uop_0_fp_ctrl_ren1; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren2; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren2 = mem_incoming_uop_0_fp_ctrl_ren2; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_ren3; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_ren3 = mem_incoming_uop_0_fp_ctrl_ren3; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap12; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap12 = mem_incoming_uop_0_fp_ctrl_swap12; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_swap23; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_swap23 = mem_incoming_uop_0_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagIn = mem_incoming_uop_0_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_ctrl_typeTagOut = mem_incoming_uop_0_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fromint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fromint = mem_incoming_uop_0_fp_ctrl_fromint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_toint; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_toint = mem_incoming_uop_0_fp_ctrl_toint; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fastpipe; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fastpipe = mem_incoming_uop_0_fp_ctrl_fastpipe; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_fma; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_fma = mem_incoming_uop_0_fp_ctrl_fma; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_div; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_div = mem_incoming_uop_0_fp_ctrl_div; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_sqrt; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_sqrt = mem_incoming_uop_0_fp_ctrl_sqrt; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_wflags; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_wflags = mem_incoming_uop_0_fp_ctrl_wflags; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_ctrl_vec; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_ctrl_vec = mem_incoming_uop_0_fp_ctrl_vec; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_rob_idx; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_rob_idx = mem_incoming_uop_0_rob_idx; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ldq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ldq_idx = mem_incoming_uop_0_ldq_idx; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_stq_idx; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_stq_idx = mem_incoming_uop_0_stq_idx; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_rxq_idx; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_rxq_idx = mem_incoming_uop_0_rxq_idx; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_pdst = mem_incoming_uop_0_pdst; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs1; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs1 = mem_incoming_uop_0_prs1; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs2; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs2 = mem_incoming_uop_0_prs2; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_prs3; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_prs3 = mem_incoming_uop_0_prs3; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_ppred; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_ppred = mem_incoming_uop_0_ppred; // @[util.scala:109:23] reg mem_incoming_uop_0_prs1_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs1_busy = mem_incoming_uop_0_prs1_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs2_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs2_busy = mem_incoming_uop_0_prs2_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_prs3_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_prs3_busy = mem_incoming_uop_0_prs3_busy; // @[util.scala:109:23] reg mem_incoming_uop_0_ppred_busy; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ppred_busy = mem_incoming_uop_0_ppred_busy; // @[util.scala:109:23] reg [6:0] mem_incoming_uop_0_stale_pdst; // @[lsu.scala:1053:37] wire [6:0] w1_bits_out_uop_stale_pdst = mem_incoming_uop_0_stale_pdst; // @[util.scala:109:23] reg mem_incoming_uop_0_exception; // @[lsu.scala:1053:37] wire w1_bits_out_uop_exception = mem_incoming_uop_0_exception; // @[util.scala:109:23] reg [63:0] mem_incoming_uop_0_exc_cause; // @[lsu.scala:1053:37] wire [63:0] w1_bits_out_uop_exc_cause = mem_incoming_uop_0_exc_cause; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_mem_cmd; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_mem_cmd = mem_incoming_uop_0_mem_cmd; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_mem_size; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_mem_size = mem_incoming_uop_0_mem_size; // @[util.scala:109:23] reg mem_incoming_uop_0_mem_signed; // @[lsu.scala:1053:37] wire w1_bits_out_uop_mem_signed = mem_incoming_uop_0_mem_signed; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_ldq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_ldq = mem_incoming_uop_0_uses_ldq; // @[util.scala:109:23] reg mem_incoming_uop_0_uses_stq; // @[lsu.scala:1053:37] wire w1_bits_out_uop_uses_stq = mem_incoming_uop_0_uses_stq; // @[util.scala:109:23] reg mem_incoming_uop_0_is_unique; // @[lsu.scala:1053:37] wire w1_bits_out_uop_is_unique = mem_incoming_uop_0_is_unique; // @[util.scala:109:23] reg mem_incoming_uop_0_flush_on_commit; // @[lsu.scala:1053:37] wire w1_bits_out_uop_flush_on_commit = mem_incoming_uop_0_flush_on_commit; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_csr_cmd; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_csr_cmd = mem_incoming_uop_0_csr_cmd; // @[util.scala:109:23] reg mem_incoming_uop_0_ldst_is_rs1; // @[lsu.scala:1053:37] wire w1_bits_out_uop_ldst_is_rs1 = mem_incoming_uop_0_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_ldst; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_ldst = mem_incoming_uop_0_ldst; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs1; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs1 = mem_incoming_uop_0_lrs1; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs2; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs2 = mem_incoming_uop_0_lrs2; // @[util.scala:109:23] reg [5:0] mem_incoming_uop_0_lrs3; // @[lsu.scala:1053:37] wire [5:0] w1_bits_out_uop_lrs3 = mem_incoming_uop_0_lrs3; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_dst_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_dst_rtype = mem_incoming_uop_0_dst_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs1_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs1_rtype = mem_incoming_uop_0_lrs1_rtype; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_lrs2_rtype; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_lrs2_rtype = mem_incoming_uop_0_lrs2_rtype; // @[util.scala:109:23] reg mem_incoming_uop_0_frs3_en; // @[lsu.scala:1053:37] wire w1_bits_out_uop_frs3_en = mem_incoming_uop_0_frs3_en; // @[util.scala:109:23] reg mem_incoming_uop_0_fcn_dw; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fcn_dw = mem_incoming_uop_0_fcn_dw; // @[util.scala:109:23] reg [4:0] mem_incoming_uop_0_fcn_op; // @[lsu.scala:1053:37] wire [4:0] w1_bits_out_uop_fcn_op = mem_incoming_uop_0_fcn_op; // @[util.scala:109:23] reg mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37] wire w1_bits_out_uop_fp_val = mem_incoming_uop_0_fp_val; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_fp_rm; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_fp_rm = mem_incoming_uop_0_fp_rm; // @[util.scala:109:23] reg [1:0] mem_incoming_uop_0_fp_typ; // @[lsu.scala:1053:37] wire [1:0] w1_bits_out_uop_fp_typ = mem_incoming_uop_0_fp_typ; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_pf_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_pf_if = mem_incoming_uop_0_xcpt_pf_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ae_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ae_if = mem_incoming_uop_0_xcpt_ae_if; // @[util.scala:109:23] reg mem_incoming_uop_0_xcpt_ma_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_xcpt_ma_if = mem_incoming_uop_0_xcpt_ma_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_debug_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_debug_if = mem_incoming_uop_0_bp_debug_if; // @[util.scala:109:23] reg mem_incoming_uop_0_bp_xcpt_if; // @[lsu.scala:1053:37] wire w1_bits_out_uop_bp_xcpt_if = mem_incoming_uop_0_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_fsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_fsrc = mem_incoming_uop_0_debug_fsrc; // @[util.scala:109:23] reg [2:0] mem_incoming_uop_0_debug_tsrc; // @[lsu.scala:1053:37] wire [2:0] w1_bits_out_uop_debug_tsrc = mem_incoming_uop_0_debug_tsrc; // @[util.scala:109:23] wire _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_ldq_incoming_e_WIRE_0_valid = mem_ldq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_inst = mem_ldq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_ldq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_ldq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_ldq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_ldq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_ldq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_ldq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_ldq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_ldq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_ldq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_ldq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_ldq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_ldq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_ldq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_ldq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_ldq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_ldq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_ldq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_ldq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_ldq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_ldq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_ldq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_ldq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_mask = mem_ldq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_tag = mem_ldq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_br_type = mem_ldq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_ldq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fence = mem_ldq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_ldq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_ldq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_amo = mem_ldq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_eret = mem_ldq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_ldq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_ldq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_mov = mem_ldq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_ldq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_ldq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_ldq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_taken = mem_ldq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_ldq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_ldq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pimm = mem_ldq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_ldq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_ldq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_ldq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_ldq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_ldq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_ldq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_ldq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_ldq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_pdst = mem_ldq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1 = mem_ldq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2 = mem_ldq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3 = mem_ldq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred = mem_ldq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_ldq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_ldq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_ldq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_ldq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_ldq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_exception = mem_ldq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_ldq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_ldq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_size = mem_ldq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_ldq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_ldq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_ldq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_is_unique = mem_ldq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_ldq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_ldq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_ldq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_ldst = mem_ldq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_ldq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_ldq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_ldq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_ldq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_ldq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_ldq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_ldq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_ldq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_ldq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_val = mem_ldq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_ldq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_ldq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_ldq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_ldq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_ldq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_ldq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_ldq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_ldq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_ldq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_valid = mem_ldq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_ldq_incoming_e_WIRE_0_bits_addr_bits = mem_ldq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_ldq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_addr_is_uncacheable = mem_ldq_incoming_e_out_bits_addr_is_uncacheable; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_executed = mem_ldq_incoming_e_out_bits_executed; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_succeeded = mem_ldq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_order_fail = mem_ldq_incoming_e_out_bits_order_fail; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_observed = mem_ldq_incoming_e_out_bits_observed; // @[util.scala:114:23] wire [23:0] _mem_ldq_incoming_e_WIRE_0_bits_st_dep_mask = mem_ldq_incoming_e_out_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] _mem_ldq_incoming_e_WIRE_0_bits_ld_byte_mask = mem_ldq_incoming_e_out_bits_ld_byte_mask; // @[util.scala:114:23] wire _mem_ldq_incoming_e_WIRE_0_bits_forward_std_val = mem_ldq_incoming_e_out_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] _mem_ldq_incoming_e_WIRE_0_bits_forward_stq_idx = mem_ldq_incoming_e_out_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] _mem_ldq_incoming_e_WIRE_0_bits_debug_wb_data = mem_ldq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] _mem_ldq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1 = ldq_incoming_e_0_bits_uop_br_mask & _mem_ldq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_incoming_e_out_bits_uop_br_mask = _mem_ldq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_ldq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & ldq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_incoming_e_out_valid_T_1 = |_mem_ldq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_incoming_e_out_valid_T_2 = _mem_ldq_incoming_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_incoming_e_out_valid_T_3 = ~_mem_ldq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_incoming_e_out_valid_T_4 = ldq_incoming_e_0_valid & _mem_ldq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_incoming_e_out_valid = _mem_ldq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_incoming_e_0_valid; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1054:37] reg [31:0] mem_ldq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1054:37] reg [15:0] mem_ldq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1054:37] reg [3:0] mem_ldq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1054:37] reg [19:0] mem_ldq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1054:37] reg [6:0] mem_ldq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1054:37] reg [5:0] mem_ldq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1054:37] reg [1:0] mem_ldq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1054:37] reg [2:0] mem_ldq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1054:37] reg [39:0] mem_ldq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_addr_is_uncacheable; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_executed; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_succeeded; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_order_fail; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_observed; // @[lsu.scala:1054:37] reg [23:0] mem_ldq_incoming_e_0_bits_st_dep_mask; // @[lsu.scala:1054:37] reg [7:0] mem_ldq_incoming_e_0_bits_ld_byte_mask; // @[lsu.scala:1054:37] reg mem_ldq_incoming_e_0_bits_forward_std_val; // @[lsu.scala:1054:37] reg [4:0] mem_ldq_incoming_e_0_bits_forward_stq_idx; // @[lsu.scala:1054:37] reg [63:0] mem_ldq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1054:37] wire _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:116:31] wire _mem_stq_incoming_e_WIRE_0_valid = mem_stq_incoming_e_out_valid; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_inst = mem_stq_incoming_e_out_bits_uop_inst; // @[util.scala:114:23] wire [31:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_inst = mem_stq_incoming_e_out_bits_uop_debug_inst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rvc = mem_stq_incoming_e_out_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_pc = mem_stq_incoming_e_out_bits_uop_debug_pc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_0 = mem_stq_incoming_e_out_bits_uop_iq_type_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_1 = mem_stq_incoming_e_out_bits_uop_iq_type_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_2 = mem_stq_incoming_e_out_bits_uop_iq_type_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iq_type_3 = mem_stq_incoming_e_out_bits_uop_iq_type_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_0 = mem_stq_incoming_e_out_bits_uop_fu_code_0; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_1 = mem_stq_incoming_e_out_bits_uop_fu_code_1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_2 = mem_stq_incoming_e_out_bits_uop_fu_code_2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_3 = mem_stq_incoming_e_out_bits_uop_fu_code_3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_4 = mem_stq_incoming_e_out_bits_uop_fu_code_4; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_5 = mem_stq_incoming_e_out_bits_uop_fu_code_5; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_6 = mem_stq_incoming_e_out_bits_uop_fu_code_6; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_7 = mem_stq_incoming_e_out_bits_uop_fu_code_7; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_8 = mem_stq_incoming_e_out_bits_uop_fu_code_8; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fu_code_9 = mem_stq_incoming_e_out_bits_uop_fu_code_9; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued = mem_stq_incoming_e_out_bits_uop_iw_issued; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_agen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_issued_partial_dgen = mem_stq_incoming_e_out_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_speculative_child = mem_stq_incoming_e_out_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p1_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p2_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_iw_p3_bypass_hint = mem_stq_incoming_e_out_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dis_col_sel = mem_stq_incoming_e_out_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_mask = mem_stq_incoming_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_tag = mem_stq_incoming_e_out_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] _mem_stq_incoming_e_WIRE_0_bits_uop_br_type = mem_stq_incoming_e_out_bits_uop_br_type; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfb = mem_stq_incoming_e_out_bits_uop_is_sfb; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fence = mem_stq_incoming_e_out_bits_uop_is_fence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_fencei = mem_stq_incoming_e_out_bits_uop_is_fencei; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sfence = mem_stq_incoming_e_out_bits_uop_is_sfence; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_amo = mem_stq_incoming_e_out_bits_uop_is_amo; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_eret = mem_stq_incoming_e_out_bits_uop_is_eret; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_sys_pc2epc = mem_stq_incoming_e_out_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_rocc = mem_stq_incoming_e_out_bits_uop_is_rocc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_mov = mem_stq_incoming_e_out_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ftq_idx = mem_stq_incoming_e_out_bits_uop_ftq_idx; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_edge_inst = mem_stq_incoming_e_out_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pc_lob = mem_stq_incoming_e_out_bits_uop_pc_lob; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_taken = mem_stq_incoming_e_out_bits_uop_taken; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_imm_rename = mem_stq_incoming_e_out_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_sel = mem_stq_incoming_e_out_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pimm = mem_stq_incoming_e_out_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] _mem_stq_incoming_e_WIRE_0_bits_uop_imm_packed = mem_stq_incoming_e_out_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op1_sel = mem_stq_incoming_e_out_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_op2_sel = mem_stq_incoming_e_out_bits_uop_op2_sel; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ldst = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wen = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren1 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren2 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_ren3 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap12 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_swap23 = mem_stq_incoming_e_out_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagIn = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_typeTagOut = mem_stq_incoming_e_out_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fromint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_toint = mem_stq_incoming_e_out_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fastpipe = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_fma = mem_stq_incoming_e_out_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_div = mem_stq_incoming_e_out_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_sqrt = mem_stq_incoming_e_out_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_wflags = mem_stq_incoming_e_out_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_ctrl_vec = mem_stq_incoming_e_out_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rob_idx = mem_stq_incoming_e_out_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldq_idx = mem_stq_incoming_e_out_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stq_idx = mem_stq_incoming_e_out_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_rxq_idx = mem_stq_incoming_e_out_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_pdst = mem_stq_incoming_e_out_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs1 = mem_stq_incoming_e_out_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs2 = mem_stq_incoming_e_out_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_prs3 = mem_stq_incoming_e_out_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ppred = mem_stq_incoming_e_out_bits_uop_ppred; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs1_busy = mem_stq_incoming_e_out_bits_uop_prs1_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs2_busy = mem_stq_incoming_e_out_bits_uop_prs2_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_prs3_busy = mem_stq_incoming_e_out_bits_uop_prs3_busy; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ppred_busy = mem_stq_incoming_e_out_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] _mem_stq_incoming_e_WIRE_0_bits_uop_stale_pdst = mem_stq_incoming_e_out_bits_uop_stale_pdst; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_exception = mem_stq_incoming_e_out_bits_uop_exception; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_uop_exc_cause = mem_stq_incoming_e_out_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_cmd = mem_stq_incoming_e_out_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_mem_size = mem_stq_incoming_e_out_bits_uop_mem_size; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_mem_signed = mem_stq_incoming_e_out_bits_uop_mem_signed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_ldq = mem_stq_incoming_e_out_bits_uop_uses_ldq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_uses_stq = mem_stq_incoming_e_out_bits_uop_uses_stq; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_is_unique = mem_stq_incoming_e_out_bits_uop_is_unique; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_flush_on_commit = mem_stq_incoming_e_out_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_csr_cmd = mem_stq_incoming_e_out_bits_uop_csr_cmd; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_ldst_is_rs1 = mem_stq_incoming_e_out_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_ldst = mem_stq_incoming_e_out_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1 = mem_stq_incoming_e_out_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2 = mem_stq_incoming_e_out_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs3 = mem_stq_incoming_e_out_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_dst_rtype = mem_stq_incoming_e_out_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs1_rtype = mem_stq_incoming_e_out_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_lrs2_rtype = mem_stq_incoming_e_out_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_frs3_en = mem_stq_incoming_e_out_bits_uop_frs3_en; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_dw = mem_stq_incoming_e_out_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fcn_op = mem_stq_incoming_e_out_bits_uop_fcn_op; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_fp_val = mem_stq_incoming_e_out_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_rm = mem_stq_incoming_e_out_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] _mem_stq_incoming_e_WIRE_0_bits_uop_fp_typ = mem_stq_incoming_e_out_bits_uop_fp_typ; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_pf_if = mem_stq_incoming_e_out_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ae_if = mem_stq_incoming_e_out_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_xcpt_ma_if = mem_stq_incoming_e_out_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_debug_if = mem_stq_incoming_e_out_bits_uop_bp_debug_if; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_uop_bp_xcpt_if = mem_stq_incoming_e_out_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_fsrc = mem_stq_incoming_e_out_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] _mem_stq_incoming_e_WIRE_0_bits_uop_debug_tsrc = mem_stq_incoming_e_out_bits_uop_debug_tsrc; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_valid = mem_stq_incoming_e_out_bits_addr_valid; // @[util.scala:114:23] wire [39:0] _mem_stq_incoming_e_WIRE_0_bits_addr_bits = mem_stq_incoming_e_out_bits_addr_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_addr_is_virtual = mem_stq_incoming_e_out_bits_addr_is_virtual; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_data_valid = mem_stq_incoming_e_out_bits_data_valid; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_data_bits = mem_stq_incoming_e_out_bits_data_bits; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_committed = mem_stq_incoming_e_out_bits_committed; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_succeeded = mem_stq_incoming_e_out_bits_succeeded; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_can_execute = mem_stq_incoming_e_out_bits_can_execute; // @[util.scala:114:23] wire _mem_stq_incoming_e_WIRE_0_bits_cleared = mem_stq_incoming_e_out_bits_cleared; // @[util.scala:114:23] wire [63:0] _mem_stq_incoming_e_WIRE_0_bits_debug_wb_data = mem_stq_incoming_e_out_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] _mem_stq_incoming_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_incoming_e_out_bits_uop_br_mask_T_1 = stq_incoming_e_0_bits_uop_br_mask & _mem_stq_incoming_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_incoming_e_out_bits_uop_br_mask = _mem_stq_incoming_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_stq_incoming_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & stq_incoming_e_0_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_incoming_e_out_valid_T_1 = |_mem_stq_incoming_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_incoming_e_out_valid_T_2 = _mem_stq_incoming_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_incoming_e_out_valid_T_3 = ~_mem_stq_incoming_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_incoming_e_out_valid_T_4 = stq_incoming_e_0_valid & _mem_stq_incoming_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_incoming_e_out_valid = _mem_stq_incoming_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_incoming_e_0_valid; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_inst; // @[lsu.scala:1055:37] reg [31:0] mem_stq_incoming_e_0_bits_uop_debug_inst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rvc; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_uop_debug_pc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iq_type_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_0; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_4; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_5; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_6; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_7; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_8; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fu_code_9; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_dis_col_sel; // @[lsu.scala:1055:37] reg [15:0] mem_stq_incoming_e_0_bits_uop_br_mask; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_tag; // @[lsu.scala:1055:37] reg [3:0] mem_stq_incoming_e_0_bits_uop_br_type; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfb; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_fencei; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sfence; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_amo; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_eret; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_rocc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_mov; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ftq_idx; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_edge_inst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_pc_lob; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_taken; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_imm_rename; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_imm_sel; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_pimm; // @[lsu.scala:1055:37] reg [19:0] mem_stq_incoming_e_0_bits_uop_imm_packed; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_op1_sel; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_op2_sel; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_rob_idx; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ldq_idx; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_stq_idx; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_rxq_idx; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_pdst; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs1; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs2; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_prs3; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_ppred; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs1_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs2_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_prs3_busy; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ppred_busy; // @[lsu.scala:1055:37] reg [6:0] mem_stq_incoming_e_0_bits_uop_stale_pdst; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_exception; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_uop_exc_cause; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_mem_cmd; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_mem_signed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_ldq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_uses_stq; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_is_unique; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_flush_on_commit; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_csr_cmd; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_ldst; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs1; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs2; // @[lsu.scala:1055:37] reg [5:0] mem_stq_incoming_e_0_bits_uop_lrs3; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_dst_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs1_rtype; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_lrs2_rtype; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_frs3_en; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fcn_dw; // @[lsu.scala:1055:37] reg [4:0] mem_stq_incoming_e_0_bits_uop_fcn_op; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_fp_val; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_fp_rm; // @[lsu.scala:1055:37] reg [1:0] mem_stq_incoming_e_0_bits_uop_fp_typ; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_debug_if; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_fsrc; // @[lsu.scala:1055:37] reg [2:0] mem_stq_incoming_e_0_bits_uop_debug_tsrc; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_valid; // @[lsu.scala:1055:37] reg [39:0] mem_stq_incoming_e_0_bits_addr_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_addr_is_virtual; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_data_valid; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_data_bits; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_committed; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_succeeded; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_can_execute; // @[lsu.scala:1055:37] reg mem_stq_incoming_e_0_bits_cleared; // @[lsu.scala:1055:37] reg [63:0] mem_stq_incoming_e_0_bits_debug_wb_data; // @[lsu.scala:1055:37] wire _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_ldq_wakeup_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_wakeup_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_ldq_wakeup_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1 = ldq_wakeup_e_bits_uop_br_mask & _mem_ldq_wakeup_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_wakeup_e_out_bits_uop_br_mask = _mem_ldq_wakeup_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire _mem_ldq_wakeup_e_out_valid_T_1 = |_mem_ldq_wakeup_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_wakeup_e_out_valid_T_2 = _mem_ldq_wakeup_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_wakeup_e_out_valid_T_3 = ~_mem_ldq_wakeup_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_wakeup_e_out_valid_T_4 = ldq_wakeup_e_valid & _mem_ldq_wakeup_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_wakeup_e_out_valid = _mem_ldq_wakeup_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_wakeup_e_valid; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_inst; // @[lsu.scala:1056:37] reg [31:0] mem_ldq_wakeup_e_bits_uop_debug_inst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_uop_debug_pc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_dis_col_sel; // @[lsu.scala:1056:37] reg [15:0] mem_ldq_wakeup_e_bits_uop_br_mask; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_tag; // @[lsu.scala:1056:37] reg [3:0] mem_ldq_wakeup_e_bits_uop_br_type; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ftq_idx; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_pc_lob; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_imm_sel; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_pimm; // @[lsu.scala:1056:37] reg [19:0] mem_ldq_wakeup_e_bits_uop_imm_packed; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_op1_sel; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_op2_sel; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_rob_idx; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ldq_idx; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_stq_idx; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_rxq_idx; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_pdst; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs1; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs2; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_prs3; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_ppred; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:1056:37] reg [6:0] mem_ldq_wakeup_e_bits_uop_stale_pdst; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_uop_exc_cause; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_mem_cmd; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_csr_cmd; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_ldst; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs1; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs2; // @[lsu.scala:1056:37] reg [5:0] mem_ldq_wakeup_e_bits_uop_lrs3; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_dst_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs1_rtype; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_lrs2_rtype; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_uop_fcn_op; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_fp_rm; // @[lsu.scala:1056:37] reg [1:0] mem_ldq_wakeup_e_bits_uop_fp_typ; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_fsrc; // @[lsu.scala:1056:37] reg [2:0] mem_ldq_wakeup_e_bits_uop_debug_tsrc; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:1056:37] reg [39:0] mem_ldq_wakeup_e_bits_addr_bits; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:1056:37] reg [23:0] mem_ldq_wakeup_e_bits_st_dep_mask; // @[lsu.scala:1056:37] reg [7:0] mem_ldq_wakeup_e_bits_ld_byte_mask; // @[lsu.scala:1056:37] reg mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:1056:37] reg [4:0] mem_ldq_wakeup_e_bits_forward_stq_idx; // @[lsu.scala:1056:37] reg [63:0] mem_ldq_wakeup_e_bits_debug_wb_data; // @[lsu.scala:1056:37] wire [31:0] mem_ldq_retry_e_out_bits_uop_inst = mem_ldq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_ldq_retry_e_out_bits_uop_debug_inst = mem_ldq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rvc = mem_ldq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_uop_debug_pc = mem_ldq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_0 = mem_ldq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_1 = mem_ldq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_2 = mem_ldq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iq_type_3 = mem_ldq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_0 = mem_ldq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_1 = mem_ldq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_2 = mem_ldq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_3 = mem_ldq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_4 = mem_ldq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_5 = mem_ldq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_6 = mem_ldq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_7 = mem_ldq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_8 = mem_ldq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fu_code_9 = mem_ldq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued = mem_ldq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_dis_col_sel = mem_ldq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_tag = mem_ldq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_ldq_retry_e_out_bits_uop_br_type = mem_ldq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfb = mem_ldq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fence = mem_ldq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_fencei = mem_ldq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sfence = mem_ldq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_amo = mem_ldq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_eret = mem_ldq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_sys_pc2epc = mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_rocc = mem_ldq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_mov = mem_ldq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ftq_idx = mem_ldq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_edge_inst = mem_ldq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_pc_lob = mem_ldq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_taken = mem_ldq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_imm_rename = mem_ldq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_imm_sel = mem_ldq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_pimm = mem_ldq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_ldq_retry_e_out_bits_uop_imm_packed = mem_ldq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_op1_sel = mem_ldq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_op2_sel = mem_ldq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wen = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_toint = mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_fma = mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_div = mem_ldq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_ctrl_vec = mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_rob_idx = mem_ldq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ldq_idx = mem_ldq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_stq_idx = mem_ldq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_rxq_idx = mem_ldq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_pdst = mem_ldq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs1 = mem_ldq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs2 = mem_ldq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_prs3 = mem_ldq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_ppred = mem_ldq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs1_busy = mem_ldq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs2_busy = mem_ldq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_prs3_busy = mem_ldq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ppred_busy = mem_ldq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_ldq_retry_e_out_bits_uop_stale_pdst = mem_ldq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_exception = mem_ldq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_uop_exc_cause = mem_ldq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_mem_cmd = mem_ldq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = mem_ldq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_mem_signed = mem_ldq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_ldq = mem_ldq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_uses_stq = mem_ldq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_is_unique = mem_ldq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_flush_on_commit = mem_ldq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_csr_cmd = mem_ldq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_ldst_is_rs1 = mem_ldq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_ldst = mem_ldq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs1 = mem_ldq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs2 = mem_ldq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_ldq_retry_e_out_bits_uop_lrs3 = mem_ldq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_dst_rtype = mem_ldq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs1_rtype = mem_ldq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_lrs2_rtype = mem_ldq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_frs3_en = mem_ldq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fcn_dw = mem_ldq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_uop_fcn_op = mem_ldq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_fp_val = mem_ldq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_fp_rm = mem_ldq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_ldq_retry_e_out_bits_uop_fp_typ = mem_ldq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_pf_if = mem_ldq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ae_if = mem_ldq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_xcpt_ma_if = mem_ldq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_debug_if = mem_ldq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_uop_bp_xcpt_if = mem_ldq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_fsrc = mem_ldq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_ldq_retry_e_out_bits_uop_debug_tsrc = mem_ldq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_valid = mem_ldq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_ldq_retry_e_out_bits_addr_bits = mem_ldq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_virtual = mem_ldq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_addr_is_uncacheable = mem_ldq_retry_e_e_bits_addr_is_uncacheable; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_executed = mem_ldq_retry_e_e_bits_executed; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_succeeded = mem_ldq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_order_fail = mem_ldq_retry_e_e_bits_order_fail; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_observed = mem_ldq_retry_e_e_bits_observed; // @[util.scala:114:23] wire [23:0] mem_ldq_retry_e_out_bits_st_dep_mask = mem_ldq_retry_e_e_bits_st_dep_mask; // @[util.scala:114:23] wire [7:0] mem_ldq_retry_e_out_bits_ld_byte_mask = mem_ldq_retry_e_e_bits_ld_byte_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_bits_forward_std_val = mem_ldq_retry_e_e_bits_forward_std_val; // @[util.scala:114:23] wire [4:0] mem_ldq_retry_e_out_bits_forward_stq_idx = mem_ldq_retry_e_e_bits_forward_stq_idx; // @[util.scala:114:23] wire [63:0] mem_ldq_retry_e_out_bits_debug_wb_data = mem_ldq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] mem_ldq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire mem_ldq_retry_e_e_valid; // @[lsu.scala:233:17] assign mem_ldq_retry_e_e_valid = _GEN_25[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :234:32, :387:15, :533:27] assign mem_ldq_retry_e_e_bits_uop_inst = _GEN_127[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_inst = _GEN_128[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rvc = _GEN_129[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_pc = _GEN_130[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_0 = _GEN_131[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_1 = _GEN_132[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_2 = _GEN_133[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iq_type_3 = _GEN_134[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_0 = _GEN_135[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_1 = _GEN_136[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_2 = _GEN_137[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_3 = _GEN_138[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_4 = _GEN_139[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_5 = _GEN_140[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_6 = _GEN_141[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_7 = _GEN_142[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_8 = _GEN_143[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fu_code_9 = _GEN_144[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued = _GEN_145[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dis_col_sel = _GEN_153[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_mask = _GEN_154[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_tag = _GEN_155[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_br_type = _GEN_156[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfb = _GEN_157[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fence = _GEN_158[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_fencei = _GEN_159[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sfence = _GEN_160[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_amo = _GEN_161[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_eret = _GEN_162[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_rocc = _GEN_164[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_mov = _GEN_165[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ftq_idx = _GEN_166[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_edge_inst = _GEN_167[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pc_lob = _GEN_168[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_taken = _GEN_169[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_rename = _GEN_170[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_sel = _GEN_171[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pimm = _GEN_172[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_imm_packed = _GEN_173[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op1_sel = _GEN_174[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_op2_sel = _GEN_175[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_189[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rob_idx = _GEN_193[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldq_idx = _GEN_194[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stq_idx = _GEN_195[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_rxq_idx = _GEN_196[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_pdst = _GEN_197[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1 = _GEN_198[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2 = _GEN_199[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3 = _GEN_200[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred = _GEN_201[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs1_busy = _GEN_202[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs2_busy = _GEN_203[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_prs3_busy = _GEN_204[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ppred_busy = _GEN_205[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_stale_pdst = _GEN_206[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exception = _GEN_207[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_exc_cause = _GEN_208[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_cmd = _GEN_209[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_size = _GEN_210[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_mem_signed = _GEN_211[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_ldq = _GEN_212[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_uses_stq = _GEN_213[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_is_unique = _GEN_214[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_flush_on_commit = _GEN_215[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_csr_cmd = _GEN_216[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_ldst = _GEN_218[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1 = _GEN_219[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2 = _GEN_220[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs3 = _GEN_221[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_dst_rtype = _GEN_222[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs1_rtype = _GEN_223[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_lrs2_rtype = _GEN_224[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_frs3_en = _GEN_225[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_dw = _GEN_226[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fcn_op = _GEN_227[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_val = _GEN_228[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_rm = _GEN_229[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_fp_typ = _GEN_230[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_231[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_232[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_233[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_debug_if = _GEN_234[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_235[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_fsrc = _GEN_236[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_uop_debug_tsrc = _GEN_237[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :235:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_valid = _GEN_238[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_bits = _GEN_239[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :236:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_virtual = _GEN_240[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :237:32, :533:27] assign mem_ldq_retry_e_e_bits_addr_is_uncacheable = _GEN_241[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :238:32, :533:27] assign mem_ldq_retry_e_e_bits_executed = _GEN_242[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :239:32, :533:27] assign mem_ldq_retry_e_e_bits_succeeded = _GEN_243[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :240:32, :533:27] assign mem_ldq_retry_e_e_bits_order_fail = _GEN_244[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :241:32, :533:27] assign mem_ldq_retry_e_e_bits_observed = _GEN_245[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :242:32, :533:27] assign mem_ldq_retry_e_e_bits_st_dep_mask = _GEN_246[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :243:32, :533:27] assign mem_ldq_retry_e_e_bits_ld_byte_mask = _GEN_247[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :244:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_std_val = _GEN_248[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :245:32, :533:27] assign mem_ldq_retry_e_e_bits_forward_stq_idx = _GEN_249[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :246:32, :533:27] assign mem_ldq_retry_e_e_bits_debug_wb_data = _GEN_250[_retry_queue_io_deq_bits_uop_ldq_idx]; // @[lsu.scala:233:17, :247:32, :533:27] wire _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_ldq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_ldq_retry_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_ldq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_ldq_retry_e_out_bits_uop_br_mask_T_1 = mem_ldq_retry_e_e_bits_uop_br_mask & _mem_ldq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_ldq_retry_e_out_bits_uop_br_mask = _mem_ldq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_ldq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_ldq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_ldq_retry_e_out_valid_T_1 = |_mem_ldq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_ldq_retry_e_out_valid_T_2 = _mem_ldq_retry_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_ldq_retry_e_out_valid_T_3 = ~_mem_ldq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_ldq_retry_e_out_valid_T_4 = mem_ldq_retry_e_e_valid & _mem_ldq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_ldq_retry_e_out_valid = _mem_ldq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_ldq_retry_e_valid; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_inst; // @[lsu.scala:1057:37] reg [31:0] mem_ldq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1057:37] reg [15:0] mem_ldq_retry_e_bits_uop_br_mask; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_tag; // @[lsu.scala:1057:37] reg [3:0] mem_ldq_retry_e_bits_uop_br_type; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_amo; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_eret; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_mov; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_taken; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_pimm; // @[lsu.scala:1057:37] reg [19:0] mem_ldq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_pdst; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs1; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs2; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_prs3; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_ppred; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1057:37] reg [6:0] mem_ldq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_exception; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_mem_size; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_is_unique; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_ldst; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs1; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs2; // @[lsu.scala:1057:37] reg [5:0] mem_ldq_retry_e_bits_uop_lrs3; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_fp_val; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1057:37] reg [1:0] mem_ldq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1057:37] reg [2:0] mem_ldq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_valid; // @[lsu.scala:1057:37] reg [39:0] mem_ldq_retry_e_bits_addr_bits; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_addr_is_uncacheable; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_executed; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_succeeded; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_order_fail; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_observed; // @[lsu.scala:1057:37] reg [23:0] mem_ldq_retry_e_bits_st_dep_mask; // @[lsu.scala:1057:37] reg [7:0] mem_ldq_retry_e_bits_ld_byte_mask; // @[lsu.scala:1057:37] reg mem_ldq_retry_e_bits_forward_std_val; // @[lsu.scala:1057:37] reg [4:0] mem_ldq_retry_e_bits_forward_stq_idx; // @[lsu.scala:1057:37] reg [63:0] mem_ldq_retry_e_bits_debug_wb_data; // @[lsu.scala:1057:37] wire [31:0] mem_stq_retry_e_out_bits_uop_inst = mem_stq_retry_e_e_bits_uop_inst; // @[util.scala:114:23] wire [31:0] mem_stq_retry_e_out_bits_uop_debug_inst = mem_stq_retry_e_e_bits_uop_debug_inst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rvc = mem_stq_retry_e_e_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_uop_debug_pc = mem_stq_retry_e_e_bits_uop_debug_pc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_0 = mem_stq_retry_e_e_bits_uop_iq_type_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_1 = mem_stq_retry_e_e_bits_uop_iq_type_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_2 = mem_stq_retry_e_e_bits_uop_iq_type_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iq_type_3 = mem_stq_retry_e_e_bits_uop_iq_type_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_0 = mem_stq_retry_e_e_bits_uop_fu_code_0; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_1 = mem_stq_retry_e_e_bits_uop_fu_code_1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_2 = mem_stq_retry_e_e_bits_uop_fu_code_2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_3 = mem_stq_retry_e_e_bits_uop_fu_code_3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_4 = mem_stq_retry_e_e_bits_uop_fu_code_4; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_5 = mem_stq_retry_e_e_bits_uop_fu_code_5; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_6 = mem_stq_retry_e_e_bits_uop_fu_code_6; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_7 = mem_stq_retry_e_e_bits_uop_fu_code_7; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_8 = mem_stq_retry_e_e_bits_uop_fu_code_8; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fu_code_9 = mem_stq_retry_e_e_bits_uop_fu_code_9; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued = mem_stq_retry_e_e_bits_uop_iw_issued; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_agen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_issued_partial_dgen = mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iw_p1_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_iw_p2_speculative_child = mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p1_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p2_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_iw_p3_bypass_hint = mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_dis_col_sel = mem_stq_retry_e_e_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_tag = mem_stq_retry_e_e_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] mem_stq_retry_e_out_bits_uop_br_type = mem_stq_retry_e_e_bits_uop_br_type; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfb = mem_stq_retry_e_e_bits_uop_is_sfb; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fence = mem_stq_retry_e_e_bits_uop_is_fence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_fencei = mem_stq_retry_e_e_bits_uop_is_fencei; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sfence = mem_stq_retry_e_e_bits_uop_is_sfence; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_amo = mem_stq_retry_e_e_bits_uop_is_amo; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_eret = mem_stq_retry_e_e_bits_uop_is_eret; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_sys_pc2epc = mem_stq_retry_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_rocc = mem_stq_retry_e_e_bits_uop_is_rocc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_mov = mem_stq_retry_e_e_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ftq_idx = mem_stq_retry_e_e_bits_uop_ftq_idx; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_edge_inst = mem_stq_retry_e_e_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_pc_lob = mem_stq_retry_e_e_bits_uop_pc_lob; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_taken = mem_stq_retry_e_e_bits_uop_taken; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_imm_rename = mem_stq_retry_e_e_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_imm_sel = mem_stq_retry_e_e_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_pimm = mem_stq_retry_e_e_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] mem_stq_retry_e_out_bits_uop_imm_packed = mem_stq_retry_e_e_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_op1_sel = mem_stq_retry_e_e_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_op2_sel = mem_stq_retry_e_e_bits_uop_op2_sel; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ldst = mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wen = mem_stq_retry_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren1 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren2 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_ren3 = mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap12 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_swap23 = mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagIn = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_ctrl_typeTagOut = mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fromint = mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_toint = mem_stq_retry_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fastpipe = mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_fma = mem_stq_retry_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_div = mem_stq_retry_e_e_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_sqrt = mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_wflags = mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_ctrl_vec = mem_stq_retry_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_rob_idx = mem_stq_retry_e_e_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ldq_idx = mem_stq_retry_e_e_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_stq_idx = mem_stq_retry_e_e_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_rxq_idx = mem_stq_retry_e_e_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_pdst = mem_stq_retry_e_e_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs1 = mem_stq_retry_e_e_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs2 = mem_stq_retry_e_e_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_prs3 = mem_stq_retry_e_e_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_ppred = mem_stq_retry_e_e_bits_uop_ppred; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs1_busy = mem_stq_retry_e_e_bits_uop_prs1_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs2_busy = mem_stq_retry_e_e_bits_uop_prs2_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_prs3_busy = mem_stq_retry_e_e_bits_uop_prs3_busy; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ppred_busy = mem_stq_retry_e_e_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] mem_stq_retry_e_out_bits_uop_stale_pdst = mem_stq_retry_e_e_bits_uop_stale_pdst; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_exception = mem_stq_retry_e_e_bits_uop_exception; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_uop_exc_cause = mem_stq_retry_e_e_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_mem_cmd = mem_stq_retry_e_e_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = mem_stq_retry_e_e_bits_uop_mem_size; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_mem_signed = mem_stq_retry_e_e_bits_uop_mem_signed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_ldq = mem_stq_retry_e_e_bits_uop_uses_ldq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_uses_stq = mem_stq_retry_e_e_bits_uop_uses_stq; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_is_unique = mem_stq_retry_e_e_bits_uop_is_unique; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_flush_on_commit = mem_stq_retry_e_e_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_csr_cmd = mem_stq_retry_e_e_bits_uop_csr_cmd; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_ldst_is_rs1 = mem_stq_retry_e_e_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_ldst = mem_stq_retry_e_e_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs1 = mem_stq_retry_e_e_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs2 = mem_stq_retry_e_e_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] mem_stq_retry_e_out_bits_uop_lrs3 = mem_stq_retry_e_e_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_dst_rtype = mem_stq_retry_e_e_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs1_rtype = mem_stq_retry_e_e_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_lrs2_rtype = mem_stq_retry_e_e_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_frs3_en = mem_stq_retry_e_e_bits_uop_frs3_en; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fcn_dw = mem_stq_retry_e_e_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] mem_stq_retry_e_out_bits_uop_fcn_op = mem_stq_retry_e_e_bits_uop_fcn_op; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_fp_val = mem_stq_retry_e_e_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_fp_rm = mem_stq_retry_e_e_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] mem_stq_retry_e_out_bits_uop_fp_typ = mem_stq_retry_e_e_bits_uop_fp_typ; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_pf_if = mem_stq_retry_e_e_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ae_if = mem_stq_retry_e_e_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_xcpt_ma_if = mem_stq_retry_e_e_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_debug_if = mem_stq_retry_e_e_bits_uop_bp_debug_if; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_uop_bp_xcpt_if = mem_stq_retry_e_e_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_fsrc = mem_stq_retry_e_e_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] mem_stq_retry_e_out_bits_uop_debug_tsrc = mem_stq_retry_e_e_bits_uop_debug_tsrc; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_valid = mem_stq_retry_e_e_bits_addr_valid; // @[util.scala:114:23] wire [39:0] mem_stq_retry_e_out_bits_addr_bits = mem_stq_retry_e_e_bits_addr_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_addr_is_virtual = mem_stq_retry_e_e_bits_addr_is_virtual; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_data_valid = mem_stq_retry_e_e_bits_data_valid; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_data_bits = mem_stq_retry_e_e_bits_data_bits; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_committed = mem_stq_retry_e_e_bits_committed; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_succeeded = mem_stq_retry_e_e_bits_succeeded; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_can_execute = mem_stq_retry_e_e_bits_can_execute; // @[util.scala:114:23] wire mem_stq_retry_e_out_bits_cleared = mem_stq_retry_e_e_bits_cleared; // @[util.scala:114:23] wire [63:0] mem_stq_retry_e_out_bits_debug_wb_data = mem_stq_retry_e_e_bits_debug_wb_data; // @[util.scala:114:23] wire [15:0] mem_stq_retry_e_e_bits_uop_br_mask; // @[lsu.scala:262:17] wire mem_stq_retry_e_e_valid; // @[lsu.scala:262:17] assign mem_stq_retry_e_e_valid = _GEN_26[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :263:32, :392:15, :533:27] assign mem_stq_retry_e_e_bits_uop_inst = _GEN_251[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_inst = _GEN_252[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rvc = _GEN_253[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_pc = _GEN_254[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_0 = _GEN_255[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_1 = _GEN_256[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_2 = _GEN_257[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iq_type_3 = _GEN_258[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_0 = _GEN_259[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_1 = _GEN_260[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_2 = _GEN_261[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_3 = _GEN_262[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_4 = _GEN_263[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_5 = _GEN_264[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_6 = _GEN_265[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_7 = _GEN_266[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_8 = _GEN_267[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fu_code_9 = _GEN_268[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued = _GEN_269[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_agen = _GEN_270[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_issued_partial_dgen = _GEN_271[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_speculative_child = _GEN_272[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_speculative_child = _GEN_273[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p1_bypass_hint = _GEN_274[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p2_bypass_hint = _GEN_275[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_iw_p3_bypass_hint = _GEN_276[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dis_col_sel = _GEN_277[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_mask = _GEN_278[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_tag = _GEN_279[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_br_type = _GEN_280[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfb = _GEN_281[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fence = _GEN_282[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_fencei = _GEN_283[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sfence = _GEN_284[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_amo = _GEN_285[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_eret = _GEN_286[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_sys_pc2epc = _GEN_287[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_rocc = _GEN_288[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_mov = _GEN_289[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ftq_idx = _GEN_290[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_edge_inst = _GEN_291[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pc_lob = _GEN_292[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_taken = _GEN_293[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_rename = _GEN_294[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_sel = _GEN_295[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pimm = _GEN_296[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_imm_packed = _GEN_297[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op1_sel = _GEN_298[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_op2_sel = _GEN_299[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ldst = _GEN_300[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wen = _GEN_301[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren1 = _GEN_302[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren2 = _GEN_303[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_ren3 = _GEN_304[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap12 = _GEN_305[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_swap23 = _GEN_306[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_307[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_308[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fromint = _GEN_309[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_toint = _GEN_310[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_311[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_fma = _GEN_312[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_div = _GEN_313[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_sqrt = _GEN_314[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_wflags = _GEN_315[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_ctrl_vec = _GEN_316[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rob_idx = _GEN_317[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldq_idx = _GEN_318[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stq_idx = _GEN_319[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_rxq_idx = _GEN_320[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_pdst = _GEN_321[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1 = _GEN_322[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2 = _GEN_323[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3 = _GEN_324[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred = _GEN_325[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs1_busy = _GEN_326[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs2_busy = _GEN_327[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_prs3_busy = _GEN_328[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ppred_busy = _GEN_329[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_stale_pdst = _GEN_330[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exception = _GEN_331[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_exc_cause = _GEN_332[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_cmd = _GEN_333[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_size = _GEN_334[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_mem_signed = _GEN_335[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_ldq = _GEN_336[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_uses_stq = _GEN_337[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_is_unique = _GEN_338[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_flush_on_commit = _GEN_339[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_csr_cmd = _GEN_340[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst_is_rs1 = _GEN_341[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_ldst = _GEN_342[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1 = _GEN_343[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2 = _GEN_344[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs3 = _GEN_345[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_dst_rtype = _GEN_346[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs1_rtype = _GEN_347[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_lrs2_rtype = _GEN_348[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_frs3_en = _GEN_349[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_dw = _GEN_350[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fcn_op = _GEN_351[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_val = _GEN_352[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_rm = _GEN_353[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_fp_typ = _GEN_354[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_pf_if = _GEN_355[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ae_if = _GEN_356[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_xcpt_ma_if = _GEN_357[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_debug_if = _GEN_358[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_bp_xcpt_if = _GEN_359[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_fsrc = _GEN_360[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_uop_debug_tsrc = _GEN_361[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :264:32, :533:27] assign mem_stq_retry_e_e_bits_addr_valid = _GEN_362[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_bits = _GEN_363[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :265:32, :533:27] assign mem_stq_retry_e_e_bits_addr_is_virtual = _GEN_364[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :266:32, :533:27] assign mem_stq_retry_e_e_bits_data_valid = _GEN_365[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_data_bits = _GEN_366[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :267:32, :533:27] assign mem_stq_retry_e_e_bits_committed = _GEN_367[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :268:32, :533:27] assign mem_stq_retry_e_e_bits_succeeded = _GEN_368[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :269:32, :533:27] assign mem_stq_retry_e_e_bits_can_execute = _GEN_369[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :270:32, :533:27] assign mem_stq_retry_e_e_bits_cleared = _GEN_370[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :271:32, :533:27] assign mem_stq_retry_e_e_bits_debug_wb_data = _GEN_371[_retry_queue_io_deq_bits_uop_stq_idx]; // @[lsu.scala:262:17, :272:32, :533:27] wire _mem_stq_retry_e_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] mem_stq_retry_e_out_bits_uop_br_mask; // @[util.scala:114:23] wire mem_stq_retry_e_out_valid; // @[util.scala:114:23] wire [15:0] _mem_stq_retry_e_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _mem_stq_retry_e_out_bits_uop_br_mask_T_1 = mem_stq_retry_e_e_bits_uop_br_mask & _mem_stq_retry_e_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign mem_stq_retry_e_out_bits_uop_br_mask = _mem_stq_retry_e_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & mem_stq_retry_e_e_bits_uop_br_mask; // @[util.scala:126:51] wire _mem_stq_retry_e_out_valid_T_1 = |_mem_stq_retry_e_out_valid_T; // @[util.scala:126:{51,59}] wire _mem_stq_retry_e_out_valid_T_2 = _mem_stq_retry_e_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _mem_stq_retry_e_out_valid_T_3 = ~_mem_stq_retry_e_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _mem_stq_retry_e_out_valid_T_4 = mem_stq_retry_e_e_valid & _mem_stq_retry_e_out_valid_T_3; // @[util.scala:116:{31,34}] assign mem_stq_retry_e_out_valid = _mem_stq_retry_e_out_valid_T_4; // @[util.scala:114:23, :116:31] reg mem_stq_retry_e_valid; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_inst; // @[lsu.scala:1058:37] reg [31:0] mem_stq_retry_e_bits_uop_debug_inst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_uop_debug_pc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_dis_col_sel; // @[lsu.scala:1058:37] reg [15:0] mem_stq_retry_e_bits_uop_br_mask; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_tag; // @[lsu.scala:1058:37] reg [3:0] mem_stq_retry_e_bits_uop_br_type; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ftq_idx; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_pc_lob; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_imm_sel; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_pimm; // @[lsu.scala:1058:37] reg [19:0] mem_stq_retry_e_bits_uop_imm_packed; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_op1_sel; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_op2_sel; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_rob_idx; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ldq_idx; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_stq_idx; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_rxq_idx; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_pdst; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs1; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs2; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_prs3; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_ppred; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:1058:37] reg [6:0] mem_stq_retry_e_bits_uop_stale_pdst; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_uop_exc_cause; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_mem_cmd; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_mem_size; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_csr_cmd; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_ldst; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs1; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs2; // @[lsu.scala:1058:37] reg [5:0] mem_stq_retry_e_bits_uop_lrs3; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_dst_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs1_rtype; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_lrs2_rtype; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:1058:37] reg [4:0] mem_stq_retry_e_bits_uop_fcn_op; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_fp_rm; // @[lsu.scala:1058:37] reg [1:0] mem_stq_retry_e_bits_uop_fp_typ; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_fsrc; // @[lsu.scala:1058:37] reg [2:0] mem_stq_retry_e_bits_uop_debug_tsrc; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:1058:37] reg [39:0] mem_stq_retry_e_bits_addr_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_data_valid; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_data_bits; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_committed; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_succeeded; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_can_execute; // @[lsu.scala:1058:37] reg mem_stq_retry_e_bits_cleared; // @[lsu.scala:1058:37] reg [63:0] mem_stq_retry_e_bits_debug_wb_data; // @[lsu.scala:1058:37] wire _GEN_478 = fired_load_agen_0 | fired_load_agen_exec_0; // @[lsu.scala:321:49, :1060:58] wire _mem_ldq_e_T; // @[lsu.scala:1060:58] assign _mem_ldq_e_T = _GEN_478; // @[lsu.scala:1060:58] wire _do_ld_search_T; // @[lsu.scala:1124:57] assign _do_ld_search_T = _GEN_478; // @[lsu.scala:1060:58, :1124:57] wire _lcam_ldq_idx_T; // @[lsu.scala:1144:51] assign _lcam_ldq_idx_T = _GEN_478; // @[lsu.scala:1060:58, :1144:51] wire _can_forward_T; // @[lsu.scala:1154:58] assign _can_forward_T = _GEN_478; // @[lsu.scala:1060:58, :1154:58] wire _mem_ldq_e_T_1_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [31:0] _mem_ldq_e_T_1_bits_uop_debug_inst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rvc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_uop_debug_pc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iq_type_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_0 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_4 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_5 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_6 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_7 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_8 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fu_code_9 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_dis_col_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [15:0] _mem_ldq_e_T_1_bits_uop_br_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_tag = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [3:0] _mem_ldq_e_T_1_bits_uop_br_type = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfb = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_fencei = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sfence = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_amo = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_eret = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_rocc = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_mov = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ftq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_edge_inst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_pc_lob = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_taken = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_taken; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_imm_rename = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_imm_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_pimm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [19:0] _mem_ldq_e_T_1_bits_uop_imm_packed = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_op1_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_op2_sel = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_div = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_rob_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ldq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_rxq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_prs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_ppred = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs1_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs2_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_prs3_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ppred_busy = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [6:0] _mem_ldq_e_T_1_bits_uop_stale_pdst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_exception = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_exception; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_uop_exc_cause = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_mem_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_mem_size = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_mem_signed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_ldq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_uses_stq = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_is_unique = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_flush_on_commit = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_csr_cmd = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_ldst_is_rs1 = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_ldst = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs1 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs2 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [5:0] _mem_ldq_e_T_1_bits_uop_lrs3 = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_dst_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs1_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_lrs2_rtype = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_frs3_en = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fcn_dw = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_uop_fcn_op = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_fp_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_fp_rm = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [1:0] _mem_ldq_e_T_1_bits_uop_fp_typ = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_pf_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ae_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_xcpt_ma_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_debug_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_uop_bp_xcpt_if = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_fsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [2:0] _mem_ldq_e_T_1_bits_uop_debug_tsrc = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_valid = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_valid; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [39:0] _mem_ldq_e_T_1_bits_addr_bits = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_virtual = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_addr_is_uncacheable = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_executed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_executed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_succeeded = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_succeeded; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_order_fail = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_order_fail; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_observed = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_observed; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [23:0] _mem_ldq_e_T_1_bits_st_dep_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_st_dep_mask : 24'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [7:0] _mem_ldq_e_T_1_bits_ld_byte_mask = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_ld_byte_mask : 8'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_1_bits_forward_std_val = fired_load_wakeup_0 & mem_ldq_wakeup_e_bits_forward_std_val; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [4:0] _mem_ldq_e_T_1_bits_forward_stq_idx = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_forward_stq_idx : 5'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire [63:0] _mem_ldq_e_T_1_bits_debug_wb_data = fired_load_wakeup_0 ? mem_ldq_wakeup_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1056:37, :1063:33] wire _mem_ldq_e_T_2_valid = fired_load_retry_0 ? mem_ldq_retry_e_valid : _mem_ldq_e_T_1_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_inst : _mem_ldq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [31:0] _mem_ldq_e_T_2_bits_uop_debug_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_inst : _mem_ldq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rvc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rvc : _mem_ldq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_uop_debug_pc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_pc : _mem_ldq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_0 : _mem_ldq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_1 : _mem_ldq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_2 : _mem_ldq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iq_type_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iq_type_3 : _mem_ldq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_0 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_0 : _mem_ldq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_1 : _mem_ldq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_2 : _mem_ldq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_3 : _mem_ldq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_4 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_4 : _mem_ldq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_5 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_5 : _mem_ldq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_6 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_6 : _mem_ldq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_7 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_7 : _mem_ldq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_8 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_8 : _mem_ldq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fu_code_9 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fu_code_9 : _mem_ldq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued : _mem_ldq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_dis_col_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dis_col_sel : _mem_ldq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [15:0] _mem_ldq_e_T_2_bits_uop_br_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_mask : _mem_ldq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_tag = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_tag : _mem_ldq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [3:0] _mem_ldq_e_T_2_bits_uop_br_type = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_br_type : _mem_ldq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfb = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfb : _mem_ldq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fence : _mem_ldq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_fencei = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_fencei : _mem_ldq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sfence = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sfence : _mem_ldq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_amo = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_amo : _mem_ldq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_eret = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_eret : _mem_ldq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_rocc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_rocc : _mem_ldq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_mov = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_mov : _mem_ldq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ftq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ftq_idx : _mem_ldq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_edge_inst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_edge_inst : _mem_ldq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_pc_lob = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pc_lob : _mem_ldq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_taken = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_taken : _mem_ldq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_imm_rename = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_rename : _mem_ldq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_imm_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_sel : _mem_ldq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_pimm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pimm : _mem_ldq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [19:0] _mem_ldq_e_T_2_bits_uop_imm_packed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_imm_packed : _mem_ldq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_op1_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op1_sel : _mem_ldq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_op2_sel = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_op2_sel : _mem_ldq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_div = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_div : _mem_ldq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_rob_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rob_idx : _mem_ldq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ldq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldq_idx : _mem_ldq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stq_idx : _mem_ldq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_rxq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_rxq_idx : _mem_ldq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_pdst : _mem_ldq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1 : _mem_ldq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2 : _mem_ldq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_prs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3 : _mem_ldq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_ppred = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred : _mem_ldq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs1_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs1_busy : _mem_ldq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs2_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs2_busy : _mem_ldq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_prs3_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_prs3_busy : _mem_ldq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ppred_busy = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ppred_busy : _mem_ldq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [6:0] _mem_ldq_e_T_2_bits_uop_stale_pdst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_stale_pdst : _mem_ldq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_exception = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exception : _mem_ldq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_uop_exc_cause = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_exc_cause : _mem_ldq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_mem_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_cmd : _mem_ldq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_mem_size = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_size : _mem_ldq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_mem_signed = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_mem_signed : _mem_ldq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_ldq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_ldq : _mem_ldq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_uses_stq = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_uses_stq : _mem_ldq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_is_unique = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_is_unique : _mem_ldq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_flush_on_commit = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_flush_on_commit : _mem_ldq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_csr_cmd = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_csr_cmd : _mem_ldq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_ldst_is_rs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_ldst = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_ldst : _mem_ldq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs1 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1 : _mem_ldq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs2 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2 : _mem_ldq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [5:0] _mem_ldq_e_T_2_bits_uop_lrs3 = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs3 : _mem_ldq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_dst_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_dst_rtype : _mem_ldq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs1_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs1_rtype : _mem_ldq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_lrs2_rtype = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_lrs2_rtype : _mem_ldq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_frs3_en = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_frs3_en : _mem_ldq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fcn_dw = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_dw : _mem_ldq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_uop_fcn_op = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fcn_op : _mem_ldq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_fp_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_val : _mem_ldq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_fp_rm = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_rm : _mem_ldq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [1:0] _mem_ldq_e_T_2_bits_uop_fp_typ = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_fp_typ : _mem_ldq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_pf_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_pf_if : _mem_ldq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ae_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ae_if : _mem_ldq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_xcpt_ma_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_xcpt_ma_if : _mem_ldq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_debug_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_debug_if : _mem_ldq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_uop_bp_xcpt_if = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_bp_xcpt_if : _mem_ldq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_fsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_fsrc : _mem_ldq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [2:0] _mem_ldq_e_T_2_bits_uop_debug_tsrc = fired_load_retry_0 ? mem_ldq_retry_e_bits_uop_debug_tsrc : _mem_ldq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_valid = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_valid : _mem_ldq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [39:0] _mem_ldq_e_T_2_bits_addr_bits = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_bits : _mem_ldq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_virtual = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_virtual : _mem_ldq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_addr_is_uncacheable = fired_load_retry_0 ? mem_ldq_retry_e_bits_addr_is_uncacheable : _mem_ldq_e_T_1_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_executed = fired_load_retry_0 ? mem_ldq_retry_e_bits_executed : _mem_ldq_e_T_1_bits_executed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_succeeded = fired_load_retry_0 ? mem_ldq_retry_e_bits_succeeded : _mem_ldq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_order_fail = fired_load_retry_0 ? mem_ldq_retry_e_bits_order_fail : _mem_ldq_e_T_1_bits_order_fail; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_observed = fired_load_retry_0 ? mem_ldq_retry_e_bits_observed : _mem_ldq_e_T_1_bits_observed; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [23:0] _mem_ldq_e_T_2_bits_st_dep_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_st_dep_mask : _mem_ldq_e_T_1_bits_st_dep_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [7:0] _mem_ldq_e_T_2_bits_ld_byte_mask = fired_load_retry_0 ? mem_ldq_retry_e_bits_ld_byte_mask : _mem_ldq_e_T_1_bits_ld_byte_mask; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_2_bits_forward_std_val = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_std_val : _mem_ldq_e_T_1_bits_forward_std_val; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [4:0] _mem_ldq_e_T_2_bits_forward_stq_idx = fired_load_retry_0 ? mem_ldq_retry_e_bits_forward_stq_idx : _mem_ldq_e_T_1_bits_forward_stq_idx; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire [63:0] _mem_ldq_e_T_2_bits_debug_wb_data = fired_load_retry_0 ? mem_ldq_retry_e_bits_debug_wb_data : _mem_ldq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1057:37, :1062:33, :1063:33] wire _mem_ldq_e_T_3_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_valid : _mem_ldq_e_T_2_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_inst : _mem_ldq_e_T_2_bits_uop_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [31:0] _mem_ldq_e_T_3_bits_uop_debug_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_inst : _mem_ldq_e_T_2_bits_uop_debug_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rvc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rvc : _mem_ldq_e_T_2_bits_uop_is_rvc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_uop_debug_pc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_pc : _mem_ldq_e_T_2_bits_uop_debug_pc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_0 : _mem_ldq_e_T_2_bits_uop_iq_type_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_1 : _mem_ldq_e_T_2_bits_uop_iq_type_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_2 : _mem_ldq_e_T_2_bits_uop_iq_type_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iq_type_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iq_type_3 : _mem_ldq_e_T_2_bits_uop_iq_type_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_0 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_0 : _mem_ldq_e_T_2_bits_uop_fu_code_0; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_1 : _mem_ldq_e_T_2_bits_uop_fu_code_1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_2 : _mem_ldq_e_T_2_bits_uop_fu_code_2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_3 : _mem_ldq_e_T_2_bits_uop_fu_code_3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_4 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_4 : _mem_ldq_e_T_2_bits_uop_fu_code_4; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_5 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_5 : _mem_ldq_e_T_2_bits_uop_fu_code_5; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_6 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_6 : _mem_ldq_e_T_2_bits_uop_fu_code_6; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_7 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_7 : _mem_ldq_e_T_2_bits_uop_fu_code_7; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_8 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_8 : _mem_ldq_e_T_2_bits_uop_fu_code_8; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fu_code_9 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fu_code_9 : _mem_ldq_e_T_2_bits_uop_fu_code_9; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued : _mem_ldq_e_T_2_bits_uop_iw_issued; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_ldq_e_T_2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_ldq_e_T_2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_ldq_e_T_2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_dis_col_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dis_col_sel : _mem_ldq_e_T_2_bits_uop_dis_col_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [15:0] _mem_ldq_e_T_3_bits_uop_br_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_mask : _mem_ldq_e_T_2_bits_uop_br_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_tag = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_tag : _mem_ldq_e_T_2_bits_uop_br_tag; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [3:0] _mem_ldq_e_T_3_bits_uop_br_type = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_br_type : _mem_ldq_e_T_2_bits_uop_br_type; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfb = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfb : _mem_ldq_e_T_2_bits_uop_is_sfb; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fence : _mem_ldq_e_T_2_bits_uop_is_fence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_fencei = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_fencei : _mem_ldq_e_T_2_bits_uop_is_fencei; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sfence = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sfence : _mem_ldq_e_T_2_bits_uop_is_sfence; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_amo = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_amo : _mem_ldq_e_T_2_bits_uop_is_amo; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_eret = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_eret : _mem_ldq_e_T_2_bits_uop_is_eret; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_ldq_e_T_2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_rocc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_rocc : _mem_ldq_e_T_2_bits_uop_is_rocc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_mov = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_mov : _mem_ldq_e_T_2_bits_uop_is_mov; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ftq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ftq_idx : _mem_ldq_e_T_2_bits_uop_ftq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_edge_inst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_edge_inst : _mem_ldq_e_T_2_bits_uop_edge_inst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_pc_lob = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pc_lob : _mem_ldq_e_T_2_bits_uop_pc_lob; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_taken = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_taken : _mem_ldq_e_T_2_bits_uop_taken; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_imm_rename = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_rename : _mem_ldq_e_T_2_bits_uop_imm_rename; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_imm_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_sel : _mem_ldq_e_T_2_bits_uop_imm_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_pimm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pimm : _mem_ldq_e_T_2_bits_uop_pimm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [19:0] _mem_ldq_e_T_3_bits_uop_imm_packed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_imm_packed : _mem_ldq_e_T_2_bits_uop_imm_packed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_op1_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op1_sel : _mem_ldq_e_T_2_bits_uop_op1_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_op2_sel = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_op2_sel : _mem_ldq_e_T_2_bits_uop_op2_sel; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_ldq_e_T_2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_ldq_e_T_2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_ldq_e_T_2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_ldq_e_T_2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_div = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_ldq_e_T_2_bits_uop_fp_ctrl_div; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_ldq_e_T_2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_ldq_e_T_2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_ldq_e_T_2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_rob_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rob_idx : _mem_ldq_e_T_2_bits_uop_rob_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ldq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldq_idx : _mem_ldq_e_T_2_bits_uop_ldq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stq_idx : _mem_ldq_e_T_2_bits_uop_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_rxq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_rxq_idx : _mem_ldq_e_T_2_bits_uop_rxq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_pdst : _mem_ldq_e_T_2_bits_uop_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1 : _mem_ldq_e_T_2_bits_uop_prs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2 : _mem_ldq_e_T_2_bits_uop_prs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_prs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3 : _mem_ldq_e_T_2_bits_uop_prs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_ppred = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred : _mem_ldq_e_T_2_bits_uop_ppred; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs1_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs1_busy : _mem_ldq_e_T_2_bits_uop_prs1_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs2_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs2_busy : _mem_ldq_e_T_2_bits_uop_prs2_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_prs3_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_prs3_busy : _mem_ldq_e_T_2_bits_uop_prs3_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ppred_busy = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ppred_busy : _mem_ldq_e_T_2_bits_uop_ppred_busy; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [6:0] _mem_ldq_e_T_3_bits_uop_stale_pdst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_stale_pdst : _mem_ldq_e_T_2_bits_uop_stale_pdst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_exception = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exception : _mem_ldq_e_T_2_bits_uop_exception; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_uop_exc_cause = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_exc_cause : _mem_ldq_e_T_2_bits_uop_exc_cause; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_mem_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_cmd : _mem_ldq_e_T_2_bits_uop_mem_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_mem_size = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_size : _mem_ldq_e_T_2_bits_uop_mem_size; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_mem_signed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_mem_signed : _mem_ldq_e_T_2_bits_uop_mem_signed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_ldq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_ldq : _mem_ldq_e_T_2_bits_uop_uses_ldq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_uses_stq = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_uses_stq : _mem_ldq_e_T_2_bits_uop_uses_stq; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_is_unique = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_is_unique : _mem_ldq_e_T_2_bits_uop_is_unique; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_flush_on_commit = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_flush_on_commit : _mem_ldq_e_T_2_bits_uop_flush_on_commit; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_csr_cmd = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_csr_cmd : _mem_ldq_e_T_2_bits_uop_csr_cmd; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_ldst_is_rs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_ldq_e_T_2_bits_uop_ldst_is_rs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_ldst = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_ldst : _mem_ldq_e_T_2_bits_uop_ldst; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs1 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1 : _mem_ldq_e_T_2_bits_uop_lrs1; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs2 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2 : _mem_ldq_e_T_2_bits_uop_lrs2; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [5:0] _mem_ldq_e_T_3_bits_uop_lrs3 = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs3 : _mem_ldq_e_T_2_bits_uop_lrs3; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_dst_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_dst_rtype : _mem_ldq_e_T_2_bits_uop_dst_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs1_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs1_rtype : _mem_ldq_e_T_2_bits_uop_lrs1_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_lrs2_rtype = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_lrs2_rtype : _mem_ldq_e_T_2_bits_uop_lrs2_rtype; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_frs3_en = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_frs3_en : _mem_ldq_e_T_2_bits_uop_frs3_en; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fcn_dw = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_dw : _mem_ldq_e_T_2_bits_uop_fcn_dw; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_uop_fcn_op = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fcn_op : _mem_ldq_e_T_2_bits_uop_fcn_op; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_fp_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_val : _mem_ldq_e_T_2_bits_uop_fp_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_fp_rm = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_rm : _mem_ldq_e_T_2_bits_uop_fp_rm; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [1:0] _mem_ldq_e_T_3_bits_uop_fp_typ = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_fp_typ : _mem_ldq_e_T_2_bits_uop_fp_typ; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_pf_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_ldq_e_T_2_bits_uop_xcpt_pf_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ae_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_ldq_e_T_2_bits_uop_xcpt_ae_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_xcpt_ma_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_ldq_e_T_2_bits_uop_xcpt_ma_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_debug_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_debug_if : _mem_ldq_e_T_2_bits_uop_bp_debug_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_uop_bp_xcpt_if = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_ldq_e_T_2_bits_uop_bp_xcpt_if; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_fsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_fsrc : _mem_ldq_e_T_2_bits_uop_debug_fsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [2:0] _mem_ldq_e_T_3_bits_uop_debug_tsrc = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_uop_debug_tsrc : _mem_ldq_e_T_2_bits_uop_debug_tsrc; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_valid = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_valid : _mem_ldq_e_T_2_bits_addr_valid; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [39:0] _mem_ldq_e_T_3_bits_addr_bits = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_bits : _mem_ldq_e_T_2_bits_addr_bits; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_virtual = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_virtual : _mem_ldq_e_T_2_bits_addr_is_virtual; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_addr_is_uncacheable = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_addr_is_uncacheable : _mem_ldq_e_T_2_bits_addr_is_uncacheable; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_executed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_executed : _mem_ldq_e_T_2_bits_executed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_succeeded = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_succeeded : _mem_ldq_e_T_2_bits_succeeded; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_order_fail = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_order_fail : _mem_ldq_e_T_2_bits_order_fail; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_observed = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_observed : _mem_ldq_e_T_2_bits_observed; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [23:0] _mem_ldq_e_T_3_bits_st_dep_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_st_dep_mask : _mem_ldq_e_T_2_bits_st_dep_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [7:0] _mem_ldq_e_T_3_bits_ld_byte_mask = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_ld_byte_mask : _mem_ldq_e_T_2_bits_ld_byte_mask; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire _mem_ldq_e_T_3_bits_forward_std_val = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_std_val : _mem_ldq_e_T_2_bits_forward_std_val; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [4:0] _mem_ldq_e_T_3_bits_forward_stq_idx = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_forward_stq_idx : _mem_ldq_e_T_2_bits_forward_stq_idx; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire [63:0] _mem_ldq_e_T_3_bits_debug_wb_data = _mem_ldq_e_T ? mem_ldq_incoming_e_0_bits_debug_wb_data : _mem_ldq_e_T_2_bits_debug_wb_data; // @[lsu.scala:1054:37, :1060:{33,58}, :1062:33] wire mem_ldq_e_0_valid = _mem_ldq_e_T_3_valid; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_inst = _mem_ldq_e_T_3_bits_uop_inst; // @[lsu.scala:321:49, :1060:33] wire [31:0] mem_ldq_e_0_bits_uop_debug_inst = _mem_ldq_e_T_3_bits_uop_debug_inst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rvc = _mem_ldq_e_T_3_bits_uop_is_rvc; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_uop_debug_pc = _mem_ldq_e_T_3_bits_uop_debug_pc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_0 = _mem_ldq_e_T_3_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_1 = _mem_ldq_e_T_3_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_2 = _mem_ldq_e_T_3_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iq_type_3 = _mem_ldq_e_T_3_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_0 = _mem_ldq_e_T_3_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_1 = _mem_ldq_e_T_3_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_2 = _mem_ldq_e_T_3_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_3 = _mem_ldq_e_T_3_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_4 = _mem_ldq_e_T_3_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_5 = _mem_ldq_e_T_3_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_6 = _mem_ldq_e_T_3_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_7 = _mem_ldq_e_T_3_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_8 = _mem_ldq_e_T_3_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fu_code_9 = _mem_ldq_e_T_3_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued = _mem_ldq_e_T_3_bits_uop_iw_issued; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_agen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_issued_partial_dgen = _mem_ldq_e_T_3_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_iw_p1_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_iw_p2_speculative_child = _mem_ldq_e_T_3_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p1_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p2_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_iw_p3_bypass_hint = _mem_ldq_e_T_3_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_dis_col_sel = _mem_ldq_e_T_3_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1060:33] wire [15:0] mem_ldq_e_0_bits_uop_br_mask = _mem_ldq_e_T_3_bits_uop_br_mask; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_tag = _mem_ldq_e_T_3_bits_uop_br_tag; // @[lsu.scala:321:49, :1060:33] wire [3:0] mem_ldq_e_0_bits_uop_br_type = _mem_ldq_e_T_3_bits_uop_br_type; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfb = _mem_ldq_e_T_3_bits_uop_is_sfb; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fence = _mem_ldq_e_T_3_bits_uop_is_fence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_fencei = _mem_ldq_e_T_3_bits_uop_is_fencei; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sfence = _mem_ldq_e_T_3_bits_uop_is_sfence; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_amo = _mem_ldq_e_T_3_bits_uop_is_amo; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_eret = _mem_ldq_e_T_3_bits_uop_is_eret; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_sys_pc2epc = _mem_ldq_e_T_3_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_rocc = _mem_ldq_e_T_3_bits_uop_is_rocc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_mov = _mem_ldq_e_T_3_bits_uop_is_mov; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ftq_idx = _mem_ldq_e_T_3_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_edge_inst = _mem_ldq_e_T_3_bits_uop_edge_inst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_pc_lob = _mem_ldq_e_T_3_bits_uop_pc_lob; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_taken = _mem_ldq_e_T_3_bits_uop_taken; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_imm_rename = _mem_ldq_e_T_3_bits_uop_imm_rename; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_imm_sel = _mem_ldq_e_T_3_bits_uop_imm_sel; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_pimm = _mem_ldq_e_T_3_bits_uop_pimm; // @[lsu.scala:321:49, :1060:33] wire [19:0] mem_ldq_e_0_bits_uop_imm_packed = _mem_ldq_e_T_3_bits_uop_imm_packed; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_op1_sel = _mem_ldq_e_T_3_bits_uop_op1_sel; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_op2_sel = _mem_ldq_e_T_3_bits_uop_op2_sel; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ldst = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wen = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren1 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren2 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_ren3 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap12 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_swap23 = _mem_ldq_e_T_3_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_ldq_e_T_3_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fromint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_toint = _mem_ldq_e_T_3_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_fma = _mem_ldq_e_T_3_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_div = _mem_ldq_e_T_3_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_sqrt = _mem_ldq_e_T_3_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_wflags = _mem_ldq_e_T_3_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_ctrl_vec = _mem_ldq_e_T_3_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_rob_idx = _mem_ldq_e_T_3_bits_uop_rob_idx; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ldq_idx = _mem_ldq_e_T_3_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_stq_idx = _mem_ldq_e_T_3_bits_uop_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_rxq_idx = _mem_ldq_e_T_3_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_pdst = _mem_ldq_e_T_3_bits_uop_pdst; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs1 = _mem_ldq_e_T_3_bits_uop_prs1; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs2 = _mem_ldq_e_T_3_bits_uop_prs2; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_prs3 = _mem_ldq_e_T_3_bits_uop_prs3; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_ppred = _mem_ldq_e_T_3_bits_uop_ppred; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs1_busy = _mem_ldq_e_T_3_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs2_busy = _mem_ldq_e_T_3_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_prs3_busy = _mem_ldq_e_T_3_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ppred_busy = _mem_ldq_e_T_3_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1060:33] wire [6:0] mem_ldq_e_0_bits_uop_stale_pdst = _mem_ldq_e_T_3_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_exception = _mem_ldq_e_T_3_bits_uop_exception; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_uop_exc_cause = _mem_ldq_e_T_3_bits_uop_exc_cause; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_mem_cmd = _mem_ldq_e_T_3_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_mem_size = _mem_ldq_e_T_3_bits_uop_mem_size; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_mem_signed = _mem_ldq_e_T_3_bits_uop_mem_signed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_ldq = _mem_ldq_e_T_3_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_uses_stq = _mem_ldq_e_T_3_bits_uop_uses_stq; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_is_unique = _mem_ldq_e_T_3_bits_uop_is_unique; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_flush_on_commit = _mem_ldq_e_T_3_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_csr_cmd = _mem_ldq_e_T_3_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_ldst_is_rs1 = _mem_ldq_e_T_3_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_ldst = _mem_ldq_e_T_3_bits_uop_ldst; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs1 = _mem_ldq_e_T_3_bits_uop_lrs1; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs2 = _mem_ldq_e_T_3_bits_uop_lrs2; // @[lsu.scala:321:49, :1060:33] wire [5:0] mem_ldq_e_0_bits_uop_lrs3 = _mem_ldq_e_T_3_bits_uop_lrs3; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_dst_rtype = _mem_ldq_e_T_3_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs1_rtype = _mem_ldq_e_T_3_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_lrs2_rtype = _mem_ldq_e_T_3_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_frs3_en = _mem_ldq_e_T_3_bits_uop_frs3_en; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fcn_dw = _mem_ldq_e_T_3_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_uop_fcn_op = _mem_ldq_e_T_3_bits_uop_fcn_op; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_fp_val = _mem_ldq_e_T_3_bits_uop_fp_val; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_fp_rm = _mem_ldq_e_T_3_bits_uop_fp_rm; // @[lsu.scala:321:49, :1060:33] wire [1:0] mem_ldq_e_0_bits_uop_fp_typ = _mem_ldq_e_T_3_bits_uop_fp_typ; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_pf_if = _mem_ldq_e_T_3_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ae_if = _mem_ldq_e_T_3_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_xcpt_ma_if = _mem_ldq_e_T_3_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_debug_if = _mem_ldq_e_T_3_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_uop_bp_xcpt_if = _mem_ldq_e_T_3_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_fsrc = _mem_ldq_e_T_3_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1060:33] wire [2:0] mem_ldq_e_0_bits_uop_debug_tsrc = _mem_ldq_e_T_3_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_valid = _mem_ldq_e_T_3_bits_addr_valid; // @[lsu.scala:321:49, :1060:33] wire [39:0] mem_ldq_e_0_bits_addr_bits = _mem_ldq_e_T_3_bits_addr_bits; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_virtual = _mem_ldq_e_T_3_bits_addr_is_virtual; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_addr_is_uncacheable = _mem_ldq_e_T_3_bits_addr_is_uncacheable; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_executed = _mem_ldq_e_T_3_bits_executed; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_succeeded = _mem_ldq_e_T_3_bits_succeeded; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_order_fail = _mem_ldq_e_T_3_bits_order_fail; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_observed = _mem_ldq_e_T_3_bits_observed; // @[lsu.scala:321:49, :1060:33] wire [23:0] mem_ldq_e_0_bits_st_dep_mask = _mem_ldq_e_T_3_bits_st_dep_mask; // @[lsu.scala:321:49, :1060:33] wire [7:0] mem_ldq_e_0_bits_ld_byte_mask = _mem_ldq_e_T_3_bits_ld_byte_mask; // @[lsu.scala:321:49, :1060:33] wire mem_ldq_e_0_bits_forward_std_val = _mem_ldq_e_T_3_bits_forward_std_val; // @[lsu.scala:321:49, :1060:33] wire [4:0] mem_ldq_e_0_bits_forward_stq_idx = _mem_ldq_e_T_3_bits_forward_stq_idx; // @[lsu.scala:321:49, :1060:33] wire [63:0] mem_ldq_e_0_bits_debug_wb_data = _mem_ldq_e_T_3_bits_debug_wb_data; // @[lsu.scala:321:49, :1060:33] wire [23:0] lcam_st_dep_mask_0 = mem_ldq_e_0_bits_st_dep_mask; // @[lsu.scala:321:49] wire _mem_stq_e_T_valid = fired_store_retry_0 & mem_stq_retry_e_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [31:0] _mem_stq_e_T_bits_uop_debug_inst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rvc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rvc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_uop_debug_pc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iq_type_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_0 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_4 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_5 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_6 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_7 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_8 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fu_code_9 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_agen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_issued_partial_dgen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_iw_p1_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_iw_p2_speculative_child = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p1_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p2_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_iw_p3_bypass_hint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_dis_col_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [15:0] _mem_stq_e_T_bits_uop_br_mask = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_tag = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [3:0] _mem_stq_e_T_bits_uop_br_type = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfb = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfb; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_fencei = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_fencei; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sfence = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sfence; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_amo = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_amo; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_eret = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_eret; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_sys_pc2epc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_rocc = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_rocc; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_mov = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_mov; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ftq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_edge_inst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_edge_inst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_pc_lob = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_taken = fired_store_retry_0 & mem_stq_retry_e_bits_uop_taken; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_imm_rename = fired_store_retry_0 & mem_stq_retry_e_bits_uop_imm_rename; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_imm_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_pimm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [19:0] _mem_stq_e_T_bits_uop_imm_packed = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_op1_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_op2_sel = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ldst = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wen = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren2 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_ren3 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap12 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_swap23 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fromint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_toint = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_fma = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_div = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_sqrt = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_wflags = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_ctrl_vec = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_rob_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ldq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_stq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_rxq_idx = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_prs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_ppred = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs1_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs2_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_prs3_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ppred_busy = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [6:0] _mem_stq_e_T_bits_uop_stale_pdst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_exception = fired_store_retry_0 & mem_stq_retry_e_bits_uop_exception; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_uop_exc_cause = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_mem_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_mem_size = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_mem_signed = fired_store_retry_0 & mem_stq_retry_e_bits_uop_mem_signed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_ldq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_uses_stq = fired_store_retry_0 & mem_stq_retry_e_bits_uop_uses_stq; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_is_unique = fired_store_retry_0 & mem_stq_retry_e_bits_uop_is_unique; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_flush_on_commit = fired_store_retry_0 & mem_stq_retry_e_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_csr_cmd = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_ldst_is_rs1 = fired_store_retry_0 & mem_stq_retry_e_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_ldst = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs1 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs2 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [5:0] _mem_stq_e_T_bits_uop_lrs3 = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_dst_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs1_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_lrs2_rtype = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_frs3_en = fired_store_retry_0 & mem_stq_retry_e_bits_uop_frs3_en; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fcn_dw = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [4:0] _mem_stq_e_T_bits_uop_fcn_op = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_fp_val = fired_store_retry_0 & mem_stq_retry_e_bits_uop_fp_val; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_fp_rm = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [1:0] _mem_stq_e_T_bits_uop_fp_typ = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_pf_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ae_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_xcpt_ma_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_debug_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_uop_bp_xcpt_if = fired_store_retry_0 & mem_stq_retry_e_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_fsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [2:0] _mem_stq_e_T_bits_uop_debug_tsrc = fired_store_retry_0 ? mem_stq_retry_e_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_valid = fired_store_retry_0 & mem_stq_retry_e_bits_addr_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [39:0] _mem_stq_e_T_bits_addr_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_addr_bits : 40'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_addr_is_virtual = fired_store_retry_0 & mem_stq_retry_e_bits_addr_is_virtual; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_data_valid = fired_store_retry_0 & mem_stq_retry_e_bits_data_valid; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_data_bits = fired_store_retry_0 ? mem_stq_retry_e_bits_data_bits : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_committed = fired_store_retry_0 & mem_stq_retry_e_bits_committed; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_succeeded = fired_store_retry_0 & mem_stq_retry_e_bits_succeeded; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_can_execute = fired_store_retry_0 & mem_stq_retry_e_bits_can_execute; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_bits_cleared = fired_store_retry_0 & mem_stq_retry_e_bits_cleared; // @[lsu.scala:321:49, :1058:37, :1067:33] wire [63:0] _mem_stq_e_T_bits_debug_wb_data = fired_store_retry_0 ? mem_stq_retry_e_bits_debug_wb_data : 64'h0; // @[lsu.scala:321:49, :1058:37, :1067:33] wire _mem_stq_e_T_1_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_valid : _mem_stq_e_T_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_inst : _mem_stq_e_T_bits_uop_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [31:0] _mem_stq_e_T_1_bits_uop_debug_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_inst : _mem_stq_e_T_bits_uop_debug_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rvc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rvc : _mem_stq_e_T_bits_uop_is_rvc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_uop_debug_pc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_pc : _mem_stq_e_T_bits_uop_debug_pc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_0 : _mem_stq_e_T_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_1 : _mem_stq_e_T_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_2 : _mem_stq_e_T_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iq_type_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iq_type_3 : _mem_stq_e_T_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_0 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_0 : _mem_stq_e_T_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_1 : _mem_stq_e_T_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_2 : _mem_stq_e_T_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_3 : _mem_stq_e_T_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_4 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_4 : _mem_stq_e_T_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_5 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_5 : _mem_stq_e_T_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_6 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_6 : _mem_stq_e_T_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_7 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_7 : _mem_stq_e_T_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_8 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_8 : _mem_stq_e_T_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fu_code_9 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fu_code_9 : _mem_stq_e_T_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued : _mem_stq_e_T_bits_uop_iw_issued; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_agen : _mem_stq_e_T_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_issued_partial_dgen : _mem_stq_e_T_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_speculative_child : _mem_stq_e_T_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_speculative_child : _mem_stq_e_T_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p1_bypass_hint : _mem_stq_e_T_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p2_bypass_hint : _mem_stq_e_T_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_iw_p3_bypass_hint : _mem_stq_e_T_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_dis_col_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dis_col_sel : _mem_stq_e_T_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [15:0] _mem_stq_e_T_1_bits_uop_br_mask = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_mask : _mem_stq_e_T_bits_uop_br_mask; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_tag = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_tag : _mem_stq_e_T_bits_uop_br_tag; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [3:0] _mem_stq_e_T_1_bits_uop_br_type = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_br_type : _mem_stq_e_T_bits_uop_br_type; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfb = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfb : _mem_stq_e_T_bits_uop_is_sfb; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fence : _mem_stq_e_T_bits_uop_is_fence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_fencei = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_fencei : _mem_stq_e_T_bits_uop_is_fencei; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sfence = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sfence : _mem_stq_e_T_bits_uop_is_sfence; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_amo = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_amo : _mem_stq_e_T_bits_uop_is_amo; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_eret = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_eret : _mem_stq_e_T_bits_uop_is_eret; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_sys_pc2epc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_sys_pc2epc : _mem_stq_e_T_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_rocc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_rocc : _mem_stq_e_T_bits_uop_is_rocc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_mov = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_mov : _mem_stq_e_T_bits_uop_is_mov; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ftq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ftq_idx : _mem_stq_e_T_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_edge_inst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_edge_inst : _mem_stq_e_T_bits_uop_edge_inst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_pc_lob = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pc_lob : _mem_stq_e_T_bits_uop_pc_lob; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_taken = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_taken : _mem_stq_e_T_bits_uop_taken; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_imm_rename = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_rename : _mem_stq_e_T_bits_uop_imm_rename; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_imm_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_sel : _mem_stq_e_T_bits_uop_imm_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_pimm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pimm : _mem_stq_e_T_bits_uop_pimm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [19:0] _mem_stq_e_T_1_bits_uop_imm_packed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_imm_packed : _mem_stq_e_T_bits_uop_imm_packed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_op1_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op1_sel : _mem_stq_e_T_bits_uop_op1_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_op2_sel = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_op2_sel : _mem_stq_e_T_bits_uop_op2_sel; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ldst : _mem_stq_e_T_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wen = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wen : _mem_stq_e_T_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren1 : _mem_stq_e_T_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren2 : _mem_stq_e_T_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_ren3 : _mem_stq_e_T_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap12 : _mem_stq_e_T_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_swap23 : _mem_stq_e_T_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagIn : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_typeTagOut : _mem_stq_e_T_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fromint : _mem_stq_e_T_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_toint = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_toint : _mem_stq_e_T_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fastpipe : _mem_stq_e_T_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_fma = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_fma : _mem_stq_e_T_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_div = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_div : _mem_stq_e_T_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_sqrt : _mem_stq_e_T_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_wflags : _mem_stq_e_T_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_ctrl_vec = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_ctrl_vec : _mem_stq_e_T_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_rob_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rob_idx : _mem_stq_e_T_bits_uop_rob_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ldq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldq_idx : _mem_stq_e_T_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_stq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stq_idx : _mem_stq_e_T_bits_uop_stq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_rxq_idx = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_rxq_idx : _mem_stq_e_T_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_pdst : _mem_stq_e_T_bits_uop_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1 : _mem_stq_e_T_bits_uop_prs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2 : _mem_stq_e_T_bits_uop_prs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_prs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3 : _mem_stq_e_T_bits_uop_prs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_ppred = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred : _mem_stq_e_T_bits_uop_ppred; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs1_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs1_busy : _mem_stq_e_T_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs2_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs2_busy : _mem_stq_e_T_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_prs3_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_prs3_busy : _mem_stq_e_T_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ppred_busy = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ppred_busy : _mem_stq_e_T_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [6:0] _mem_stq_e_T_1_bits_uop_stale_pdst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_stale_pdst : _mem_stq_e_T_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_exception = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exception : _mem_stq_e_T_bits_uop_exception; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_uop_exc_cause = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_exc_cause : _mem_stq_e_T_bits_uop_exc_cause; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_mem_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_cmd : _mem_stq_e_T_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_mem_size = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_size : _mem_stq_e_T_bits_uop_mem_size; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_mem_signed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_mem_signed : _mem_stq_e_T_bits_uop_mem_signed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_ldq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_ldq : _mem_stq_e_T_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_uses_stq = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_uses_stq : _mem_stq_e_T_bits_uop_uses_stq; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_is_unique = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_is_unique : _mem_stq_e_T_bits_uop_is_unique; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_flush_on_commit = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_flush_on_commit : _mem_stq_e_T_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_csr_cmd = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_csr_cmd : _mem_stq_e_T_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_ldst_is_rs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst_is_rs1 : _mem_stq_e_T_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_ldst = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_ldst : _mem_stq_e_T_bits_uop_ldst; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs1 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1 : _mem_stq_e_T_bits_uop_lrs1; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs2 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2 : _mem_stq_e_T_bits_uop_lrs2; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [5:0] _mem_stq_e_T_1_bits_uop_lrs3 = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs3 : _mem_stq_e_T_bits_uop_lrs3; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_dst_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_dst_rtype : _mem_stq_e_T_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs1_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs1_rtype : _mem_stq_e_T_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_lrs2_rtype = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_lrs2_rtype : _mem_stq_e_T_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_frs3_en = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_frs3_en : _mem_stq_e_T_bits_uop_frs3_en; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fcn_dw = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_dw : _mem_stq_e_T_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [4:0] _mem_stq_e_T_1_bits_uop_fcn_op = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fcn_op : _mem_stq_e_T_bits_uop_fcn_op; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_fp_val = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_val : _mem_stq_e_T_bits_uop_fp_val; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_fp_rm = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_rm : _mem_stq_e_T_bits_uop_fp_rm; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [1:0] _mem_stq_e_T_1_bits_uop_fp_typ = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_fp_typ : _mem_stq_e_T_bits_uop_fp_typ; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_pf_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_pf_if : _mem_stq_e_T_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ae_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ae_if : _mem_stq_e_T_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_xcpt_ma_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_xcpt_ma_if : _mem_stq_e_T_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_debug_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_debug_if : _mem_stq_e_T_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_uop_bp_xcpt_if = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_bp_xcpt_if : _mem_stq_e_T_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_fsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_fsrc : _mem_stq_e_T_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [2:0] _mem_stq_e_T_1_bits_uop_debug_tsrc = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_uop_debug_tsrc : _mem_stq_e_T_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_valid : _mem_stq_e_T_bits_addr_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [39:0] _mem_stq_e_T_1_bits_addr_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_bits : _mem_stq_e_T_bits_addr_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_addr_is_virtual = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_addr_is_virtual : _mem_stq_e_T_bits_addr_is_virtual; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_data_valid = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_valid : _mem_stq_e_T_bits_data_valid; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_data_bits = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_data_bits : _mem_stq_e_T_bits_data_bits; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_committed = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_committed : _mem_stq_e_T_bits_committed; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_succeeded = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_succeeded : _mem_stq_e_T_bits_succeeded; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_can_execute = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_can_execute : _mem_stq_e_T_bits_can_execute; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire _mem_stq_e_T_1_bits_cleared = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_cleared : _mem_stq_e_T_bits_cleared; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire [63:0] _mem_stq_e_T_1_bits_debug_wb_data = fired_store_agen_0 ? mem_stq_incoming_e_0_bits_debug_wb_data : _mem_stq_e_T_bits_debug_wb_data; // @[lsu.scala:321:49, :1055:37, :1066:33, :1067:33] wire mem_stq_e_0_valid = _mem_stq_e_T_1_valid; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_inst = _mem_stq_e_T_1_bits_uop_inst; // @[lsu.scala:321:49, :1066:33] wire [31:0] mem_stq_e_0_bits_uop_debug_inst = _mem_stq_e_T_1_bits_uop_debug_inst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rvc = _mem_stq_e_T_1_bits_uop_is_rvc; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_uop_debug_pc = _mem_stq_e_T_1_bits_uop_debug_pc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_0 = _mem_stq_e_T_1_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_1 = _mem_stq_e_T_1_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_2 = _mem_stq_e_T_1_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iq_type_3 = _mem_stq_e_T_1_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_0 = _mem_stq_e_T_1_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_1 = _mem_stq_e_T_1_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_2 = _mem_stq_e_T_1_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_3 = _mem_stq_e_T_1_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_4 = _mem_stq_e_T_1_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_5 = _mem_stq_e_T_1_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_6 = _mem_stq_e_T_1_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_7 = _mem_stq_e_T_1_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_8 = _mem_stq_e_T_1_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fu_code_9 = _mem_stq_e_T_1_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued = _mem_stq_e_T_1_bits_uop_iw_issued; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_agen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_issued_partial_dgen = _mem_stq_e_T_1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_iw_p1_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_iw_p2_speculative_child = _mem_stq_e_T_1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p1_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p2_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_iw_p3_bypass_hint = _mem_stq_e_T_1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_dis_col_sel = _mem_stq_e_T_1_bits_uop_dis_col_sel; // @[lsu.scala:321:49, :1066:33] wire [15:0] mem_stq_e_0_bits_uop_br_mask = _mem_stq_e_T_1_bits_uop_br_mask; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_tag = _mem_stq_e_T_1_bits_uop_br_tag; // @[lsu.scala:321:49, :1066:33] wire [3:0] mem_stq_e_0_bits_uop_br_type = _mem_stq_e_T_1_bits_uop_br_type; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfb = _mem_stq_e_T_1_bits_uop_is_sfb; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fence = _mem_stq_e_T_1_bits_uop_is_fence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_fencei = _mem_stq_e_T_1_bits_uop_is_fencei; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sfence = _mem_stq_e_T_1_bits_uop_is_sfence; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_amo = _mem_stq_e_T_1_bits_uop_is_amo; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_eret = _mem_stq_e_T_1_bits_uop_is_eret; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_sys_pc2epc = _mem_stq_e_T_1_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_rocc = _mem_stq_e_T_1_bits_uop_is_rocc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_mov = _mem_stq_e_T_1_bits_uop_is_mov; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ftq_idx = _mem_stq_e_T_1_bits_uop_ftq_idx; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_edge_inst = _mem_stq_e_T_1_bits_uop_edge_inst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_pc_lob = _mem_stq_e_T_1_bits_uop_pc_lob; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_taken = _mem_stq_e_T_1_bits_uop_taken; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_imm_rename = _mem_stq_e_T_1_bits_uop_imm_rename; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_imm_sel = _mem_stq_e_T_1_bits_uop_imm_sel; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_pimm = _mem_stq_e_T_1_bits_uop_pimm; // @[lsu.scala:321:49, :1066:33] wire [19:0] mem_stq_e_0_bits_uop_imm_packed = _mem_stq_e_T_1_bits_uop_imm_packed; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_op1_sel = _mem_stq_e_T_1_bits_uop_op1_sel; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_op2_sel = _mem_stq_e_T_1_bits_uop_op2_sel; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ldst = _mem_stq_e_T_1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wen = _mem_stq_e_T_1_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren1 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren2 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_ren3 = _mem_stq_e_T_1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap12 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_swap23 = _mem_stq_e_T_1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut = _mem_stq_e_T_1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fromint = _mem_stq_e_T_1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_toint = _mem_stq_e_T_1_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fastpipe = _mem_stq_e_T_1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_fma = _mem_stq_e_T_1_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_div = _mem_stq_e_T_1_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_sqrt = _mem_stq_e_T_1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_wflags = _mem_stq_e_T_1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_ctrl_vec = _mem_stq_e_T_1_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_rob_idx = _mem_stq_e_T_1_bits_uop_rob_idx; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ldq_idx = _mem_stq_e_T_1_bits_uop_ldq_idx; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_stq_idx = _mem_stq_e_T_1_bits_uop_stq_idx; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_rxq_idx = _mem_stq_e_T_1_bits_uop_rxq_idx; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_pdst = _mem_stq_e_T_1_bits_uop_pdst; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs1 = _mem_stq_e_T_1_bits_uop_prs1; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs2 = _mem_stq_e_T_1_bits_uop_prs2; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_prs3 = _mem_stq_e_T_1_bits_uop_prs3; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_ppred = _mem_stq_e_T_1_bits_uop_ppred; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs1_busy = _mem_stq_e_T_1_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs2_busy = _mem_stq_e_T_1_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_prs3_busy = _mem_stq_e_T_1_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ppred_busy = _mem_stq_e_T_1_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1066:33] wire [6:0] mem_stq_e_0_bits_uop_stale_pdst = _mem_stq_e_T_1_bits_uop_stale_pdst; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_exception = _mem_stq_e_T_1_bits_uop_exception; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_uop_exc_cause = _mem_stq_e_T_1_bits_uop_exc_cause; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_mem_cmd = _mem_stq_e_T_1_bits_uop_mem_cmd; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_mem_size = _mem_stq_e_T_1_bits_uop_mem_size; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_mem_signed = _mem_stq_e_T_1_bits_uop_mem_signed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_ldq = _mem_stq_e_T_1_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_uses_stq = _mem_stq_e_T_1_bits_uop_uses_stq; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_is_unique = _mem_stq_e_T_1_bits_uop_is_unique; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_flush_on_commit = _mem_stq_e_T_1_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_csr_cmd = _mem_stq_e_T_1_bits_uop_csr_cmd; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_ldst_is_rs1 = _mem_stq_e_T_1_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_ldst = _mem_stq_e_T_1_bits_uop_ldst; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs1 = _mem_stq_e_T_1_bits_uop_lrs1; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs2 = _mem_stq_e_T_1_bits_uop_lrs2; // @[lsu.scala:321:49, :1066:33] wire [5:0] mem_stq_e_0_bits_uop_lrs3 = _mem_stq_e_T_1_bits_uop_lrs3; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_dst_rtype = _mem_stq_e_T_1_bits_uop_dst_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs1_rtype = _mem_stq_e_T_1_bits_uop_lrs1_rtype; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_lrs2_rtype = _mem_stq_e_T_1_bits_uop_lrs2_rtype; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_frs3_en = _mem_stq_e_T_1_bits_uop_frs3_en; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fcn_dw = _mem_stq_e_T_1_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1066:33] wire [4:0] mem_stq_e_0_bits_uop_fcn_op = _mem_stq_e_T_1_bits_uop_fcn_op; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_fp_val = _mem_stq_e_T_1_bits_uop_fp_val; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_fp_rm = _mem_stq_e_T_1_bits_uop_fp_rm; // @[lsu.scala:321:49, :1066:33] wire [1:0] mem_stq_e_0_bits_uop_fp_typ = _mem_stq_e_T_1_bits_uop_fp_typ; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_pf_if = _mem_stq_e_T_1_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ae_if = _mem_stq_e_T_1_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_xcpt_ma_if = _mem_stq_e_T_1_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_debug_if = _mem_stq_e_T_1_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_uop_bp_xcpt_if = _mem_stq_e_T_1_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_fsrc = _mem_stq_e_T_1_bits_uop_debug_fsrc; // @[lsu.scala:321:49, :1066:33] wire [2:0] mem_stq_e_0_bits_uop_debug_tsrc = _mem_stq_e_T_1_bits_uop_debug_tsrc; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_valid = _mem_stq_e_T_1_bits_addr_valid; // @[lsu.scala:321:49, :1066:33] wire [39:0] mem_stq_e_0_bits_addr_bits = _mem_stq_e_T_1_bits_addr_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_addr_is_virtual = _mem_stq_e_T_1_bits_addr_is_virtual; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_data_valid = _mem_stq_e_T_1_bits_data_valid; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_data_bits = _mem_stq_e_T_1_bits_data_bits; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_committed = _mem_stq_e_T_1_bits_committed; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_succeeded = _mem_stq_e_T_1_bits_succeeded; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_can_execute = _mem_stq_e_T_1_bits_can_execute; // @[lsu.scala:321:49, :1066:33] wire mem_stq_e_0_bits_cleared = _mem_stq_e_T_1_bits_cleared; // @[lsu.scala:321:49, :1066:33] wire [63:0] mem_stq_e_0_bits_debug_wb_data = _mem_stq_e_T_1_bits_debug_wb_data; // @[lsu.scala:321:49, :1066:33] reg mem_tlb_miss_0; // @[lsu.scala:1070:41] reg mem_tlb_uncacheable_0; // @[lsu.scala:1071:41] reg [39:0] mem_paddr_0; // @[lsu.scala:1072:41] wire _stq_clr_head_idx_T = ~stq_cleared_0; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_1 = stq_valid_0 & _stq_clr_head_idx_T; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_2 = ~stq_cleared_1; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_3 = stq_valid_1 & _stq_clr_head_idx_T_2; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_4 = ~stq_cleared_2; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_5 = stq_valid_2 & _stq_clr_head_idx_T_4; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_6 = ~stq_cleared_3; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_7 = stq_valid_3 & _stq_clr_head_idx_T_6; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_8 = ~stq_cleared_4; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_9 = stq_valid_4 & _stq_clr_head_idx_T_8; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_10 = ~stq_cleared_5; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_11 = stq_valid_5 & _stq_clr_head_idx_T_10; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_12 = ~stq_cleared_6; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_13 = stq_valid_6 & _stq_clr_head_idx_T_12; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_14 = ~stq_cleared_7; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_15 = stq_valid_7 & _stq_clr_head_idx_T_14; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_16 = ~stq_cleared_8; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_17 = stq_valid_8 & _stq_clr_head_idx_T_16; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_18 = ~stq_cleared_9; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_19 = stq_valid_9 & _stq_clr_head_idx_T_18; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_20 = ~stq_cleared_10; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_21 = stq_valid_10 & _stq_clr_head_idx_T_20; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_22 = ~stq_cleared_11; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_23 = stq_valid_11 & _stq_clr_head_idx_T_22; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_24 = ~stq_cleared_12; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_25 = stq_valid_12 & _stq_clr_head_idx_T_24; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_26 = ~stq_cleared_13; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_27 = stq_valid_13 & _stq_clr_head_idx_T_26; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_28 = ~stq_cleared_14; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_29 = stq_valid_14 & _stq_clr_head_idx_T_28; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_30 = ~stq_cleared_15; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_31 = stq_valid_15 & _stq_clr_head_idx_T_30; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_32 = ~stq_cleared_16; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_33 = stq_valid_16 & _stq_clr_head_idx_T_32; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_34 = ~stq_cleared_17; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_35 = stq_valid_17 & _stq_clr_head_idx_T_34; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_36 = ~stq_cleared_18; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_37 = stq_valid_18 & _stq_clr_head_idx_T_36; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_38 = ~stq_cleared_19; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_39 = stq_valid_19 & _stq_clr_head_idx_T_38; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_40 = ~stq_cleared_20; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_41 = stq_valid_20 & _stq_clr_head_idx_T_40; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_42 = ~stq_cleared_21; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_43 = stq_valid_21 & _stq_clr_head_idx_T_42; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_44 = ~stq_cleared_22; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_45 = stq_valid_22 & _stq_clr_head_idx_T_44; // @[lsu.scala:251:32, :1077:{18,21}] wire _stq_clr_head_idx_T_46 = ~stq_cleared_23; // @[lsu.scala:259:32, :1077:21] wire _stq_clr_head_idx_T_47 = stq_valid_23 & _stq_clr_head_idx_T_46; // @[lsu.scala:251:32, :1077:{18,21}] wire stq_clr_head_idx_temp_vec_0 = _stq_clr_head_idx_T_1 & _stq_clr_head_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_1 = _stq_clr_head_idx_T_3 & _stq_clr_head_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_2 = _stq_clr_head_idx_T_5 & _stq_clr_head_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_3 = _stq_clr_head_idx_T_7 & _stq_clr_head_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_4 = _stq_clr_head_idx_T_9 & _stq_clr_head_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_5 = _stq_clr_head_idx_T_11 & _stq_clr_head_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_6 = _stq_clr_head_idx_T_13 & _stq_clr_head_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_7 = _stq_clr_head_idx_T_15 & _stq_clr_head_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_8 = _stq_clr_head_idx_T_17 & _stq_clr_head_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_9 = _stq_clr_head_idx_T_19 & _stq_clr_head_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_10 = _stq_clr_head_idx_T_21 & _stq_clr_head_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_11 = _stq_clr_head_idx_T_23 & _stq_clr_head_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_12 = _stq_clr_head_idx_T_25 & _stq_clr_head_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_13 = _stq_clr_head_idx_T_27 & _stq_clr_head_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_14 = _stq_clr_head_idx_T_29 & _stq_clr_head_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _stq_clr_head_idx_temp_vec_T_15 = ~(stq_commit_head[4]); // @[util.scala:352:72] wire stq_clr_head_idx_temp_vec_15 = _stq_clr_head_idx_T_31 & _stq_clr_head_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_16 = _stq_clr_head_idx_T_33 & _stq_clr_head_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_17 = _stq_clr_head_idx_T_35 & _stq_clr_head_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_18 = _stq_clr_head_idx_T_37 & _stq_clr_head_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_19 = _stq_clr_head_idx_T_39 & _stq_clr_head_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_20 = _stq_clr_head_idx_T_41 & _stq_clr_head_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_21 = _stq_clr_head_idx_T_43 & _stq_clr_head_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_22 = _stq_clr_head_idx_T_45 & _stq_clr_head_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire stq_clr_head_idx_temp_vec_23 = _stq_clr_head_idx_T_47 & _stq_clr_head_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _stq_clr_head_idx_idx_T = {5'h1B, ~_stq_clr_head_idx_T_45}; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_1 = _stq_clr_head_idx_T_43 ? 6'h35 : _stq_clr_head_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_2 = _stq_clr_head_idx_T_41 ? 6'h34 : _stq_clr_head_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_3 = _stq_clr_head_idx_T_39 ? 6'h33 : _stq_clr_head_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_4 = _stq_clr_head_idx_T_37 ? 6'h32 : _stq_clr_head_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_5 = _stq_clr_head_idx_T_35 ? 6'h31 : _stq_clr_head_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_6 = _stq_clr_head_idx_T_33 ? 6'h30 : _stq_clr_head_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_7 = _stq_clr_head_idx_T_31 ? 6'h2F : _stq_clr_head_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_8 = _stq_clr_head_idx_T_29 ? 6'h2E : _stq_clr_head_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_9 = _stq_clr_head_idx_T_27 ? 6'h2D : _stq_clr_head_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_10 = _stq_clr_head_idx_T_25 ? 6'h2C : _stq_clr_head_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_11 = _stq_clr_head_idx_T_23 ? 6'h2B : _stq_clr_head_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_12 = _stq_clr_head_idx_T_21 ? 6'h2A : _stq_clr_head_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_13 = _stq_clr_head_idx_T_19 ? 6'h29 : _stq_clr_head_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_14 = _stq_clr_head_idx_T_17 ? 6'h28 : _stq_clr_head_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_15 = _stq_clr_head_idx_T_15 ? 6'h27 : _stq_clr_head_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_16 = _stq_clr_head_idx_T_13 ? 6'h26 : _stq_clr_head_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_17 = _stq_clr_head_idx_T_11 ? 6'h25 : _stq_clr_head_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_18 = _stq_clr_head_idx_T_9 ? 6'h24 : _stq_clr_head_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_19 = _stq_clr_head_idx_T_7 ? 6'h23 : _stq_clr_head_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_20 = _stq_clr_head_idx_T_5 ? 6'h22 : _stq_clr_head_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_21 = _stq_clr_head_idx_T_3 ? 6'h21 : _stq_clr_head_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_22 = _stq_clr_head_idx_T_1 ? 6'h20 : _stq_clr_head_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_23 = _stq_clr_head_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_24 = _stq_clr_head_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_25 = _stq_clr_head_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_26 = _stq_clr_head_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_27 = _stq_clr_head_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_28 = _stq_clr_head_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_29 = _stq_clr_head_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_30 = _stq_clr_head_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_31 = stq_clr_head_idx_temp_vec_23 ? 6'h17 : _stq_clr_head_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_32 = stq_clr_head_idx_temp_vec_22 ? 6'h16 : _stq_clr_head_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_33 = stq_clr_head_idx_temp_vec_21 ? 6'h15 : _stq_clr_head_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_34 = stq_clr_head_idx_temp_vec_20 ? 6'h14 : _stq_clr_head_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_35 = stq_clr_head_idx_temp_vec_19 ? 6'h13 : _stq_clr_head_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_36 = stq_clr_head_idx_temp_vec_18 ? 6'h12 : _stq_clr_head_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_37 = stq_clr_head_idx_temp_vec_17 ? 6'h11 : _stq_clr_head_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_38 = stq_clr_head_idx_temp_vec_16 ? 6'h10 : _stq_clr_head_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_39 = stq_clr_head_idx_temp_vec_15 ? 6'hF : _stq_clr_head_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_40 = stq_clr_head_idx_temp_vec_14 ? 6'hE : _stq_clr_head_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_41 = stq_clr_head_idx_temp_vec_13 ? 6'hD : _stq_clr_head_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_42 = stq_clr_head_idx_temp_vec_12 ? 6'hC : _stq_clr_head_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_43 = stq_clr_head_idx_temp_vec_11 ? 6'hB : _stq_clr_head_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_44 = stq_clr_head_idx_temp_vec_10 ? 6'hA : _stq_clr_head_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_45 = stq_clr_head_idx_temp_vec_9 ? 6'h9 : _stq_clr_head_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_46 = stq_clr_head_idx_temp_vec_8 ? 6'h8 : _stq_clr_head_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_47 = stq_clr_head_idx_temp_vec_7 ? 6'h7 : _stq_clr_head_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_48 = stq_clr_head_idx_temp_vec_6 ? 6'h6 : _stq_clr_head_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_49 = stq_clr_head_idx_temp_vec_5 ? 6'h5 : _stq_clr_head_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_50 = stq_clr_head_idx_temp_vec_4 ? 6'h4 : _stq_clr_head_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_51 = stq_clr_head_idx_temp_vec_3 ? 6'h3 : _stq_clr_head_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_52 = stq_clr_head_idx_temp_vec_2 ? 6'h2 : _stq_clr_head_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _stq_clr_head_idx_idx_T_53 = stq_clr_head_idx_temp_vec_1 ? 6'h1 : _stq_clr_head_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] stq_clr_head_idx_idx = stq_clr_head_idx_temp_vec_0 ? 6'h0 : _stq_clr_head_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _stq_clr_head_idx_T_48 = stq_clr_head_idx_idx[4:0]; // @[Mux.scala:50:70] reg [4:0] stq_clr_head_idx; // @[lsu.scala:1076:33] wire [4:0] _s_uop_T = stq_clr_head_idx; // @[lsu.scala:1076:33] reg clr_valid; // @[lsu.scala:1084:24] reg [31:0] clr_uop_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_inst = clr_uop_inst; // @[util.scala:104:23] reg [31:0] clr_uop_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_debug_inst = clr_uop_debug_inst; // @[util.scala:104:23] reg clr_uop_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rvc = clr_uop_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_debug_pc = clr_uop_debug_pc; // @[util.scala:104:23] reg clr_uop_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_0 = clr_uop_iq_type_0; // @[util.scala:104:23] reg clr_uop_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_1 = clr_uop_iq_type_1; // @[util.scala:104:23] reg clr_uop_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_2 = clr_uop_iq_type_2; // @[util.scala:104:23] reg clr_uop_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_iq_type_3 = clr_uop_iq_type_3; // @[util.scala:104:23] reg clr_uop_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_0 = clr_uop_fu_code_0; // @[util.scala:104:23] reg clr_uop_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_1 = clr_uop_fu_code_1; // @[util.scala:104:23] reg clr_uop_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_2 = clr_uop_fu_code_2; // @[util.scala:104:23] reg clr_uop_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_3 = clr_uop_fu_code_3; // @[util.scala:104:23] reg clr_uop_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_4 = clr_uop_fu_code_4; // @[util.scala:104:23] reg clr_uop_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_5 = clr_uop_fu_code_5; // @[util.scala:104:23] reg clr_uop_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_6 = clr_uop_fu_code_6; // @[util.scala:104:23] reg clr_uop_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_7 = clr_uop_fu_code_7; // @[util.scala:104:23] reg clr_uop_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_8 = clr_uop_fu_code_8; // @[util.scala:104:23] reg clr_uop_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_fu_code_9 = clr_uop_fu_code_9; // @[util.scala:104:23] reg clr_uop_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued = clr_uop_iw_issued; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_agen = clr_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_issued_partial_dgen = clr_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_iw_p1_speculative_child = clr_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_iw_p2_speculative_child = clr_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p1_bypass_hint = clr_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p2_bypass_hint = clr_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_iw_p3_bypass_hint = clr_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_dis_col_sel = clr_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_tag = clr_uop_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_br_type = clr_uop_br_type; // @[util.scala:104:23] reg clr_uop_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfb = clr_uop_is_sfb; // @[util.scala:104:23] reg clr_uop_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fence = clr_uop_is_fence; // @[util.scala:104:23] reg clr_uop_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_fencei = clr_uop_is_fencei; // @[util.scala:104:23] reg clr_uop_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sfence = clr_uop_is_sfence; // @[util.scala:104:23] reg clr_uop_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_amo = clr_uop_is_amo; // @[util.scala:104:23] reg clr_uop_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_eret = clr_uop_is_eret; // @[util.scala:104:23] reg clr_uop_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_sys_pc2epc = clr_uop_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_rocc = clr_uop_is_rocc; // @[util.scala:104:23] reg clr_uop_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_mov = clr_uop_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ftq_idx = clr_uop_ftq_idx; // @[util.scala:104:23] reg clr_uop_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_edge_inst = clr_uop_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_pc_lob = clr_uop_pc_lob; // @[util.scala:104:23] reg clr_uop_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_taken = clr_uop_taken; // @[util.scala:104:23] reg clr_uop_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_imm_rename = clr_uop_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_imm_sel = clr_uop_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_pimm = clr_uop_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_imm_packed = clr_uop_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_op1_sel = clr_uop_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_op2_sel = clr_uop_op2_sel; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ldst = clr_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wen = clr_uop_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren1 = clr_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren2 = clr_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_ren3 = clr_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap12 = clr_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_swap23 = clr_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagIn = clr_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_ctrl_typeTagOut = clr_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fromint = clr_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_toint = clr_uop_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fastpipe = clr_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_fma = clr_uop_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_div = clr_uop_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_sqrt = clr_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_wflags = clr_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_ctrl_vec = clr_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_rob_idx = clr_uop_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ldq_idx = clr_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_stq_idx = clr_uop_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_rxq_idx = clr_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_pdst = clr_uop_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs1 = clr_uop_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs2 = clr_uop_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_prs3 = clr_uop_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_ppred = clr_uop_ppred; // @[util.scala:104:23] reg clr_uop_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs1_busy = clr_uop_prs1_busy; // @[util.scala:104:23] reg clr_uop_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs2_busy = clr_uop_prs2_busy; // @[util.scala:104:23] reg clr_uop_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_prs3_busy = clr_uop_prs3_busy; // @[util.scala:104:23] reg clr_uop_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_ppred_busy = clr_uop_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_stale_pdst = clr_uop_stale_pdst; // @[util.scala:104:23] reg clr_uop_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_exception = clr_uop_exception; // @[util.scala:104:23] reg [63:0] clr_uop_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_exc_cause = clr_uop_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_mem_cmd = clr_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_mem_size = clr_uop_mem_size; // @[util.scala:104:23] reg clr_uop_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_mem_signed = clr_uop_mem_signed; // @[util.scala:104:23] reg clr_uop_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_ldq = clr_uop_uses_ldq; // @[util.scala:104:23] reg clr_uop_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_uses_stq = clr_uop_uses_stq; // @[util.scala:104:23] reg clr_uop_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_is_unique = clr_uop_is_unique; // @[util.scala:104:23] reg clr_uop_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_flush_on_commit = clr_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_csr_cmd = clr_uop_csr_cmd; // @[util.scala:104:23] reg clr_uop_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_ldst_is_rs1 = clr_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_ldst = clr_uop_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs1 = clr_uop_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs2 = clr_uop_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_lrs3 = clr_uop_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_dst_rtype = clr_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs1_rtype = clr_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_lrs2_rtype = clr_uop_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_frs3_en = clr_uop_frs3_en; // @[util.scala:104:23] reg clr_uop_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_fcn_dw = clr_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_fcn_op = clr_uop_fcn_op; // @[util.scala:104:23] reg clr_uop_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_fp_val = clr_uop_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_fp_rm = clr_uop_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_fp_typ = clr_uop_fp_typ; // @[util.scala:104:23] reg clr_uop_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_pf_if = clr_uop_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ae_if = clr_uop_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_xcpt_ma_if = clr_uop_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_debug_if = clr_uop_bp_debug_if; // @[util.scala:104:23] reg clr_uop_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_bp_xcpt_if = clr_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_fsrc = clr_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_debug_tsrc = clr_uop_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_1 = |_clr_valid_1_T; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_2 = _clr_valid_1_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_3 = ~_clr_valid_1_T_2; // @[util.scala:61:61] wire _clr_valid_1_T_4 = clr_valid & _clr_valid_1_T_3; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_1 = clr_uop_br_mask & _clr_uop_1_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_1_out_br_mask = _clr_uop_1_out_br_mask_T_1; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_0_bits_0 = clr_uop_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_1 = _s_uop_T; wire [31:0] clr_uop_out_inst = s_uop_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_debug_inst = s_uop_debug_inst; // @[util.scala:104:23] wire clr_uop_out_is_rvc = s_uop_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_debug_pc = s_uop_debug_pc; // @[util.scala:104:23] wire clr_uop_out_iq_type_0 = s_uop_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_iq_type_1 = s_uop_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_iq_type_2 = s_uop_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_iq_type_3 = s_uop_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_0 = s_uop_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_fu_code_1 = s_uop_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_fu_code_2 = s_uop_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_fu_code_3 = s_uop_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_fu_code_4 = s_uop_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_fu_code_5 = s_uop_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_fu_code_6 = s_uop_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_fu_code_7 = s_uop_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_fu_code_8 = s_uop_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_fu_code_9 = s_uop_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_iw_issued = s_uop_iw_issued; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_agen = s_uop_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_iw_issued_partial_dgen = s_uop_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_iw_p1_speculative_child = s_uop_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_iw_p2_speculative_child = s_uop_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_iw_p1_bypass_hint = s_uop_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p2_bypass_hint = s_uop_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_iw_p3_bypass_hint = s_uop_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_dis_col_sel = s_uop_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_tag = s_uop_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_br_type = s_uop_br_type; // @[util.scala:104:23] wire clr_uop_out_is_sfb = s_uop_is_sfb; // @[util.scala:104:23] wire clr_uop_out_is_fence = s_uop_is_fence; // @[util.scala:104:23] wire clr_uop_out_is_fencei = s_uop_is_fencei; // @[util.scala:104:23] wire clr_uop_out_is_sfence = s_uop_is_sfence; // @[util.scala:104:23] wire clr_uop_out_is_amo = s_uop_is_amo; // @[util.scala:104:23] wire clr_uop_out_is_eret = s_uop_is_eret; // @[util.scala:104:23] wire clr_uop_out_is_sys_pc2epc = s_uop_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_is_rocc = s_uop_is_rocc; // @[util.scala:104:23] wire clr_uop_out_is_mov = s_uop_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_ftq_idx = s_uop_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_edge_inst = s_uop_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_pc_lob = s_uop_pc_lob; // @[util.scala:104:23] wire clr_uop_out_taken = s_uop_taken; // @[util.scala:104:23] wire clr_uop_out_imm_rename = s_uop_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_imm_sel = s_uop_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_pimm = s_uop_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_imm_packed = s_uop_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_op1_sel = s_uop_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_op2_sel = s_uop_op2_sel; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ldst = s_uop_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wen = s_uop_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren1 = s_uop_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren2 = s_uop_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_ren3 = s_uop_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap12 = s_uop_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_swap23 = s_uop_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagIn = s_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_ctrl_typeTagOut = s_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fromint = s_uop_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_toint = s_uop_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fastpipe = s_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_fma = s_uop_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_div = s_uop_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_sqrt = s_uop_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_wflags = s_uop_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_fp_ctrl_vec = s_uop_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_rob_idx = s_uop_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_ldq_idx = s_uop_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_stq_idx = s_uop_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_rxq_idx = s_uop_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_pdst = s_uop_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs1 = s_uop_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs2 = s_uop_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_prs3 = s_uop_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_ppred = s_uop_ppred; // @[util.scala:104:23] wire clr_uop_out_prs1_busy = s_uop_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_prs2_busy = s_uop_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_prs3_busy = s_uop_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_ppred_busy = s_uop_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_stale_pdst = s_uop_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_exception = s_uop_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_exc_cause = s_uop_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_mem_cmd = s_uop_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_mem_size = s_uop_mem_size; // @[util.scala:104:23] wire clr_uop_out_mem_signed = s_uop_mem_signed; // @[util.scala:104:23] wire clr_uop_out_uses_ldq = s_uop_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_uses_stq = s_uop_uses_stq; // @[util.scala:104:23] wire clr_uop_out_is_unique = s_uop_is_unique; // @[util.scala:104:23] wire clr_uop_out_flush_on_commit = s_uop_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_csr_cmd = s_uop_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_ldst_is_rs1 = s_uop_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_ldst = s_uop_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs1 = s_uop_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs2 = s_uop_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_lrs3 = s_uop_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_dst_rtype = s_uop_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs1_rtype = s_uop_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_lrs2_rtype = s_uop_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_frs3_en = s_uop_frs3_en; // @[util.scala:104:23] wire clr_uop_out_fcn_dw = s_uop_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_fcn_op = s_uop_fcn_op; // @[util.scala:104:23] wire clr_uop_out_fp_val = s_uop_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_fp_rm = s_uop_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_fp_typ = s_uop_fp_typ; // @[util.scala:104:23] wire clr_uop_out_xcpt_pf_if = s_uop_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ae_if = s_uop_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_xcpt_ma_if = s_uop_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_bp_debug_if = s_uop_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_bp_xcpt_if = s_uop_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_fsrc = s_uop_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_debug_tsrc = s_uop_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_br_mask; // @[lsu.scala:1093:25] assign s_uop_inst = _GEN_251[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_inst = _GEN_252[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rvc = _GEN_253[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_pc = _GEN_254[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_0 = _GEN_255[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_1 = _GEN_256[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_2 = _GEN_257[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iq_type_3 = _GEN_258[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_0 = _GEN_259[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_1 = _GEN_260[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_2 = _GEN_261[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_3 = _GEN_262[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_4 = _GEN_263[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_5 = _GEN_264[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_6 = _GEN_265[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_7 = _GEN_266[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_8 = _GEN_267[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fu_code_9 = _GEN_268[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued = _GEN_269[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_agen = _GEN_270[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_issued_partial_dgen = _GEN_271[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_speculative_child = _GEN_272[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_speculative_child = _GEN_273[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p1_bypass_hint = _GEN_274[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p2_bypass_hint = _GEN_275[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_iw_p3_bypass_hint = _GEN_276[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dis_col_sel = _GEN_277[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_mask = _GEN_278[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_tag = _GEN_279[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_br_type = _GEN_280[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfb = _GEN_281[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fence = _GEN_282[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_fencei = _GEN_283[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sfence = _GEN_284[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_amo = _GEN_285[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_eret = _GEN_286[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_sys_pc2epc = _GEN_287[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_rocc = _GEN_288[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_mov = _GEN_289[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ftq_idx = _GEN_290[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_edge_inst = _GEN_291[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pc_lob = _GEN_292[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_taken = _GEN_293[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_rename = _GEN_294[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_sel = _GEN_295[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pimm = _GEN_296[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_imm_packed = _GEN_297[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op1_sel = _GEN_298[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_op2_sel = _GEN_299[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ldst = _GEN_300[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wen = _GEN_301[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren1 = _GEN_302[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren2 = _GEN_303[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_ren3 = _GEN_304[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap12 = _GEN_305[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_swap23 = _GEN_306[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fromint = _GEN_309[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_toint = _GEN_310[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_fma = _GEN_312[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_div = _GEN_313[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_sqrt = _GEN_314[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_wflags = _GEN_315[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_ctrl_vec = _GEN_316[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rob_idx = _GEN_317[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldq_idx = _GEN_318[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stq_idx = _GEN_319[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_rxq_idx = _GEN_320[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_pdst = _GEN_321[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1 = _GEN_322[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2 = _GEN_323[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3 = _GEN_324[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred = _GEN_325[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs1_busy = _GEN_326[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs2_busy = _GEN_327[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_prs3_busy = _GEN_328[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ppred_busy = _GEN_329[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_stale_pdst = _GEN_330[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exception = _GEN_331[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_exc_cause = _GEN_332[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_cmd = _GEN_333[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_size = _GEN_334[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_mem_signed = _GEN_335[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_ldq = _GEN_336[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_uses_stq = _GEN_337[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_is_unique = _GEN_338[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_flush_on_commit = _GEN_339[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_csr_cmd = _GEN_340[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst_is_rs1 = _GEN_341[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_ldst = _GEN_342[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1 = _GEN_343[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2 = _GEN_344[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs3 = _GEN_345[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_dst_rtype = _GEN_346[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs1_rtype = _GEN_347[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_lrs2_rtype = _GEN_348[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_frs3_en = _GEN_349[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_dw = _GEN_350[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fcn_op = _GEN_351[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_val = _GEN_352[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_rm = _GEN_353[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_fp_typ = _GEN_354[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_pf_if = _GEN_355[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ae_if = _GEN_356[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_xcpt_ma_if = _GEN_357[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_debug_if = _GEN_358[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_bp_xcpt_if = _GEN_359[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_fsrc = _GEN_360[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] assign s_uop_debug_tsrc = _GEN_361[_s_uop_T_1]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [15:0] clr_uop_out_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_1 = s_uop_br_mask & _clr_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign clr_uop_out_br_mask = _clr_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire wrap_6 = stq_clr_head_idx == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_0_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_0_valid_T_1 = |_io_core_clr_bsy_0_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_0_valid_T_2 = _io_core_clr_bsy_0_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_0_valid_T_3 = ~_io_core_clr_bsy_0_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_0_valid_T_4 = clr_valid_1 & _io_core_clr_bsy_0_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_0_valid_0 = _io_core_clr_bsy_0_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [4:0] _s_uop_T_2 = wrap_6 ? 5'h0 : stq_clr_head_idx + 5'h1; // @[util.scala:213:25, :214:{10,28}] reg clr_valid_2; // @[lsu.scala:1084:24] reg [31:0] clr_uop_2_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_inst = clr_uop_2_inst; // @[util.scala:104:23] reg [31:0] clr_uop_2_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_1_debug_inst = clr_uop_2_debug_inst; // @[util.scala:104:23] reg clr_uop_2_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rvc = clr_uop_2_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_2_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_1_debug_pc = clr_uop_2_debug_pc; // @[util.scala:104:23] reg clr_uop_2_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_0 = clr_uop_2_iq_type_0; // @[util.scala:104:23] reg clr_uop_2_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_1 = clr_uop_2_iq_type_1; // @[util.scala:104:23] reg clr_uop_2_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_2 = clr_uop_2_iq_type_2; // @[util.scala:104:23] reg clr_uop_2_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iq_type_3 = clr_uop_2_iq_type_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_0 = clr_uop_2_fu_code_0; // @[util.scala:104:23] reg clr_uop_2_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_1 = clr_uop_2_fu_code_1; // @[util.scala:104:23] reg clr_uop_2_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_2 = clr_uop_2_fu_code_2; // @[util.scala:104:23] reg clr_uop_2_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_3 = clr_uop_2_fu_code_3; // @[util.scala:104:23] reg clr_uop_2_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_4 = clr_uop_2_fu_code_4; // @[util.scala:104:23] reg clr_uop_2_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_5 = clr_uop_2_fu_code_5; // @[util.scala:104:23] reg clr_uop_2_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_6 = clr_uop_2_fu_code_6; // @[util.scala:104:23] reg clr_uop_2_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_7 = clr_uop_2_fu_code_7; // @[util.scala:104:23] reg clr_uop_2_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_8 = clr_uop_2_fu_code_8; // @[util.scala:104:23] reg clr_uop_2_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fu_code_9 = clr_uop_2_fu_code_9; // @[util.scala:104:23] reg clr_uop_2_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued = clr_uop_2_iw_issued; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_agen = clr_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_2_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_issued_partial_dgen = clr_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_2_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_iw_p1_speculative_child = clr_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_2_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_iw_p2_speculative_child = clr_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_2_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p1_bypass_hint = clr_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p2_bypass_hint = clr_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_2_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_iw_p3_bypass_hint = clr_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_2_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_dis_col_sel = clr_uop_2_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_2_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_2_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_tag = clr_uop_2_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_2_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_1_br_type = clr_uop_2_br_type; // @[util.scala:104:23] reg clr_uop_2_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfb = clr_uop_2_is_sfb; // @[util.scala:104:23] reg clr_uop_2_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fence = clr_uop_2_is_fence; // @[util.scala:104:23] reg clr_uop_2_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_fencei = clr_uop_2_is_fencei; // @[util.scala:104:23] reg clr_uop_2_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sfence = clr_uop_2_is_sfence; // @[util.scala:104:23] reg clr_uop_2_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_amo = clr_uop_2_is_amo; // @[util.scala:104:23] reg clr_uop_2_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_eret = clr_uop_2_is_eret; // @[util.scala:104:23] reg clr_uop_2_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_sys_pc2epc = clr_uop_2_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_2_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_rocc = clr_uop_2_is_rocc; // @[util.scala:104:23] reg clr_uop_2_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_mov = clr_uop_2_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_2_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ftq_idx = clr_uop_2_ftq_idx; // @[util.scala:104:23] reg clr_uop_2_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_edge_inst = clr_uop_2_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_2_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_pc_lob = clr_uop_2_pc_lob; // @[util.scala:104:23] reg clr_uop_2_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_taken = clr_uop_2_taken; // @[util.scala:104:23] reg clr_uop_2_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_imm_rename = clr_uop_2_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_2_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_imm_sel = clr_uop_2_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_2_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_pimm = clr_uop_2_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_2_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_1_imm_packed = clr_uop_2_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_2_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_op1_sel = clr_uop_2_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_2_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_op2_sel = clr_uop_2_op2_sel; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ldst = clr_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wen = clr_uop_2_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren1 = clr_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren2 = clr_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_ren3 = clr_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap12 = clr_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_swap23 = clr_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagIn = clr_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_ctrl_typeTagOut = clr_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fromint = clr_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_toint = clr_uop_2_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fastpipe = clr_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_fma = clr_uop_2_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_div = clr_uop_2_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_sqrt = clr_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_wflags = clr_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_2_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_ctrl_vec = clr_uop_2_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_2_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_rob_idx = clr_uop_2_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_2_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ldq_idx = clr_uop_2_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_2_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_stq_idx = clr_uop_2_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_2_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_rxq_idx = clr_uop_2_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_2_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_pdst = clr_uop_2_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs1 = clr_uop_2_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs2 = clr_uop_2_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_2_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_prs3 = clr_uop_2_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_2_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_ppred = clr_uop_2_ppred; // @[util.scala:104:23] reg clr_uop_2_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs1_busy = clr_uop_2_prs1_busy; // @[util.scala:104:23] reg clr_uop_2_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs2_busy = clr_uop_2_prs2_busy; // @[util.scala:104:23] reg clr_uop_2_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_prs3_busy = clr_uop_2_prs3_busy; // @[util.scala:104:23] reg clr_uop_2_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ppred_busy = clr_uop_2_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_2_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_1_stale_pdst = clr_uop_2_stale_pdst; // @[util.scala:104:23] reg clr_uop_2_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_exception = clr_uop_2_exception; // @[util.scala:104:23] reg [63:0] clr_uop_2_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_1_exc_cause = clr_uop_2_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_2_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_mem_cmd = clr_uop_2_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_2_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_mem_size = clr_uop_2_mem_size; // @[util.scala:104:23] reg clr_uop_2_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_mem_signed = clr_uop_2_mem_signed; // @[util.scala:104:23] reg clr_uop_2_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_ldq = clr_uop_2_uses_ldq; // @[util.scala:104:23] reg clr_uop_2_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_uses_stq = clr_uop_2_uses_stq; // @[util.scala:104:23] reg clr_uop_2_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_is_unique = clr_uop_2_is_unique; // @[util.scala:104:23] reg clr_uop_2_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_flush_on_commit = clr_uop_2_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_2_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_csr_cmd = clr_uop_2_csr_cmd; // @[util.scala:104:23] reg clr_uop_2_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_ldst_is_rs1 = clr_uop_2_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_ldst = clr_uop_2_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs1 = clr_uop_2_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs2 = clr_uop_2_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_2_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_1_lrs3 = clr_uop_2_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_2_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_dst_rtype = clr_uop_2_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs1_rtype = clr_uop_2_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_2_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_lrs2_rtype = clr_uop_2_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_2_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_frs3_en = clr_uop_2_frs3_en; // @[util.scala:104:23] reg clr_uop_2_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fcn_dw = clr_uop_2_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_2_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_1_fcn_op = clr_uop_2_fcn_op; // @[util.scala:104:23] reg clr_uop_2_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_fp_val = clr_uop_2_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_2_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_fp_rm = clr_uop_2_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_2_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_1_fp_typ = clr_uop_2_fp_typ; // @[util.scala:104:23] reg clr_uop_2_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_pf_if = clr_uop_2_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ae_if = clr_uop_2_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_2_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_xcpt_ma_if = clr_uop_2_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_2_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_debug_if = clr_uop_2_bp_debug_if; // @[util.scala:104:23] reg clr_uop_2_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_1_bp_xcpt_if = clr_uop_2_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_fsrc = clr_uop_2_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_2_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_1_debug_tsrc = clr_uop_2_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T_5 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_2_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_6 = |_clr_valid_1_T_5; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_7 = _clr_valid_1_T_6 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_8 = ~_clr_valid_1_T_7; // @[util.scala:61:61] wire _clr_valid_1_T_9 = clr_valid_2 & _clr_valid_1_T_8; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_1; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_3 = clr_uop_2_br_mask & _clr_uop_1_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_1_out_1_br_mask = _clr_uop_1_out_br_mask_T_3; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_1_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_1_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_1_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_1_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_1_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_1_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_1_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_1_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_1_taken; // @[lsu.scala:1089:30] reg clr_uop_1_1_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_1_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_1_bits_0 = clr_uop_1_1_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_1_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_1_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_1_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_1_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_1_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_1_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_1_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_1_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_1_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_1_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_1_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_1_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_1_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_1_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_1_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_1_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_1_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_1_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_3 = _s_uop_T_2; wire [31:0] clr_uop_out_1_inst = s_uop_1_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_1_debug_inst = s_uop_1_debug_inst; // @[util.scala:104:23] wire clr_uop_out_1_is_rvc = s_uop_1_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_1_debug_pc = s_uop_1_debug_pc; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_0 = s_uop_1_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_1 = s_uop_1_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_2 = s_uop_1_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_1_iq_type_3 = s_uop_1_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_0 = s_uop_1_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_1 = s_uop_1_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_2 = s_uop_1_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_3 = s_uop_1_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_4 = s_uop_1_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_5 = s_uop_1_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_6 = s_uop_1_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_7 = s_uop_1_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_8 = s_uop_1_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_1_fu_code_9 = s_uop_1_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued = s_uop_1_iw_issued; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_agen = s_uop_1_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_1_iw_issued_partial_dgen = s_uop_1_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_iw_p1_speculative_child = s_uop_1_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_iw_p2_speculative_child = s_uop_1_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_1_iw_p1_bypass_hint = s_uop_1_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p2_bypass_hint = s_uop_1_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_1_iw_p3_bypass_hint = s_uop_1_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_dis_col_sel = s_uop_1_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_tag = s_uop_1_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_1_br_type = s_uop_1_br_type; // @[util.scala:104:23] wire clr_uop_out_1_is_sfb = s_uop_1_is_sfb; // @[util.scala:104:23] wire clr_uop_out_1_is_fence = s_uop_1_is_fence; // @[util.scala:104:23] wire clr_uop_out_1_is_fencei = s_uop_1_is_fencei; // @[util.scala:104:23] wire clr_uop_out_1_is_sfence = s_uop_1_is_sfence; // @[util.scala:104:23] wire clr_uop_out_1_is_amo = s_uop_1_is_amo; // @[util.scala:104:23] wire clr_uop_out_1_is_eret = s_uop_1_is_eret; // @[util.scala:104:23] wire clr_uop_out_1_is_sys_pc2epc = s_uop_1_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_1_is_rocc = s_uop_1_is_rocc; // @[util.scala:104:23] wire clr_uop_out_1_is_mov = s_uop_1_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ftq_idx = s_uop_1_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_1_edge_inst = s_uop_1_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_pc_lob = s_uop_1_pc_lob; // @[util.scala:104:23] wire clr_uop_out_1_taken = s_uop_1_taken; // @[util.scala:104:23] wire clr_uop_out_1_imm_rename = s_uop_1_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_imm_sel = s_uop_1_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_pimm = s_uop_1_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_1_imm_packed = s_uop_1_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_op1_sel = s_uop_1_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_op2_sel = s_uop_1_op2_sel; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ldst = s_uop_1_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wen = s_uop_1_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren1 = s_uop_1_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren2 = s_uop_1_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_ren3 = s_uop_1_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap12 = s_uop_1_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_swap23 = s_uop_1_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagIn = s_uop_1_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_ctrl_typeTagOut = s_uop_1_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fromint = s_uop_1_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_toint = s_uop_1_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fastpipe = s_uop_1_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_fma = s_uop_1_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_div = s_uop_1_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_sqrt = s_uop_1_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_wflags = s_uop_1_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_1_fp_ctrl_vec = s_uop_1_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_rob_idx = s_uop_1_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ldq_idx = s_uop_1_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_stq_idx = s_uop_1_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_rxq_idx = s_uop_1_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_pdst = s_uop_1_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs1 = s_uop_1_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs2 = s_uop_1_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_prs3 = s_uop_1_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_ppred = s_uop_1_ppred; // @[util.scala:104:23] wire clr_uop_out_1_prs1_busy = s_uop_1_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs2_busy = s_uop_1_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_1_prs3_busy = s_uop_1_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_1_ppred_busy = s_uop_1_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_1_stale_pdst = s_uop_1_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_1_exception = s_uop_1_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_1_exc_cause = s_uop_1_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_mem_cmd = s_uop_1_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_mem_size = s_uop_1_mem_size; // @[util.scala:104:23] wire clr_uop_out_1_mem_signed = s_uop_1_mem_signed; // @[util.scala:104:23] wire clr_uop_out_1_uses_ldq = s_uop_1_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_1_uses_stq = s_uop_1_uses_stq; // @[util.scala:104:23] wire clr_uop_out_1_is_unique = s_uop_1_is_unique; // @[util.scala:104:23] wire clr_uop_out_1_flush_on_commit = s_uop_1_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_csr_cmd = s_uop_1_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_1_ldst_is_rs1 = s_uop_1_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_ldst = s_uop_1_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs1 = s_uop_1_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs2 = s_uop_1_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_1_lrs3 = s_uop_1_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_dst_rtype = s_uop_1_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs1_rtype = s_uop_1_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_lrs2_rtype = s_uop_1_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_1_frs3_en = s_uop_1_frs3_en; // @[util.scala:104:23] wire clr_uop_out_1_fcn_dw = s_uop_1_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_1_fcn_op = s_uop_1_fcn_op; // @[util.scala:104:23] wire clr_uop_out_1_fp_val = s_uop_1_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_fp_rm = s_uop_1_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_1_fp_typ = s_uop_1_fp_typ; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_pf_if = s_uop_1_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ae_if = s_uop_1_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_1_xcpt_ma_if = s_uop_1_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_debug_if = s_uop_1_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_1_bp_xcpt_if = s_uop_1_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_fsrc = s_uop_1_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_1_debug_tsrc = s_uop_1_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_1_br_mask; // @[lsu.scala:1093:25] assign s_uop_1_inst = _GEN_251[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_inst = _GEN_252[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_rvc = _GEN_253[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_pc = _GEN_254[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_0 = _GEN_255[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_1 = _GEN_256[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_2 = _GEN_257[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iq_type_3 = _GEN_258[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_0 = _GEN_259[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_1 = _GEN_260[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_2 = _GEN_261[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_3 = _GEN_262[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_4 = _GEN_263[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_5 = _GEN_264[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_6 = _GEN_265[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_7 = _GEN_266[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_8 = _GEN_267[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fu_code_9 = _GEN_268[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued = _GEN_269[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued_partial_agen = _GEN_270[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_issued_partial_dgen = _GEN_271[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p1_speculative_child = _GEN_272[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p2_speculative_child = _GEN_273[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p1_bypass_hint = _GEN_274[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p2_bypass_hint = _GEN_275[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_iw_p3_bypass_hint = _GEN_276[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_dis_col_sel = _GEN_277[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_mask = _GEN_278[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_tag = _GEN_279[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_br_type = _GEN_280[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sfb = _GEN_281[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_fence = _GEN_282[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_fencei = _GEN_283[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sfence = _GEN_284[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_amo = _GEN_285[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_eret = _GEN_286[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_sys_pc2epc = _GEN_287[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_rocc = _GEN_288[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_mov = _GEN_289[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ftq_idx = _GEN_290[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_edge_inst = _GEN_291[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pc_lob = _GEN_292[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_taken = _GEN_293[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_rename = _GEN_294[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_sel = _GEN_295[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pimm = _GEN_296[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_imm_packed = _GEN_297[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_op1_sel = _GEN_298[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_op2_sel = _GEN_299[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ldst = _GEN_300[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_wen = _GEN_301[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren1 = _GEN_302[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren2 = _GEN_303[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_ren3 = _GEN_304[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_swap12 = _GEN_305[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_swap23 = _GEN_306[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fromint = _GEN_309[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_toint = _GEN_310[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_fma = _GEN_312[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_div = _GEN_313[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_sqrt = _GEN_314[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_wflags = _GEN_315[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_ctrl_vec = _GEN_316[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_rob_idx = _GEN_317[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldq_idx = _GEN_318[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_stq_idx = _GEN_319[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_rxq_idx = _GEN_320[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_pdst = _GEN_321[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs1 = _GEN_322[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs2 = _GEN_323[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs3 = _GEN_324[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ppred = _GEN_325[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs1_busy = _GEN_326[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs2_busy = _GEN_327[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_prs3_busy = _GEN_328[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ppred_busy = _GEN_329[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_stale_pdst = _GEN_330[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_exception = _GEN_331[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_exc_cause = _GEN_332[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_cmd = _GEN_333[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_size = _GEN_334[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_mem_signed = _GEN_335[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_uses_ldq = _GEN_336[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_uses_stq = _GEN_337[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_is_unique = _GEN_338[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_flush_on_commit = _GEN_339[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_csr_cmd = _GEN_340[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldst_is_rs1 = _GEN_341[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_ldst = _GEN_342[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs1 = _GEN_343[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs2 = _GEN_344[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs3 = _GEN_345[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_dst_rtype = _GEN_346[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs1_rtype = _GEN_347[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_lrs2_rtype = _GEN_348[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_frs3_en = _GEN_349[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fcn_dw = _GEN_350[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fcn_op = _GEN_351[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_val = _GEN_352[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_rm = _GEN_353[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_fp_typ = _GEN_354[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_pf_if = _GEN_355[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_ae_if = _GEN_356[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_xcpt_ma_if = _GEN_357[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_bp_debug_if = _GEN_358[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_bp_xcpt_if = _GEN_359[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_fsrc = _GEN_360[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] assign s_uop_1_debug_tsrc = _GEN_361[_s_uop_T_3]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_3; // @[util.scala:93:25] wire [15:0] clr_uop_out_1_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T_2 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_3 = s_uop_1_br_mask & _clr_uop_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign clr_uop_out_1_br_mask = _clr_uop_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire wrap_7 = _s_uop_T_2 == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_1_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_1_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_1_valid_T_1 = |_io_core_clr_bsy_1_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_1_valid_T_2 = _io_core_clr_bsy_1_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_1_valid_T_3 = ~_io_core_clr_bsy_1_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_1_valid_T_4 = clr_valid_1_1 & _io_core_clr_bsy_1_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_1_valid_0 = _io_core_clr_bsy_1_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire [4:0] _s_uop_T_4 = wrap_7 ? 5'h0 : _s_uop_T_2 + 5'h1; // @[util.scala:213:25, :214:{10,28}] reg clr_valid_3; // @[lsu.scala:1084:24] reg [31:0] clr_uop_3_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_2_inst = clr_uop_3_inst; // @[util.scala:104:23] reg [31:0] clr_uop_3_debug_inst; // @[lsu.scala:1086:24] wire [31:0] clr_uop_1_out_2_debug_inst = clr_uop_3_debug_inst; // @[util.scala:104:23] reg clr_uop_3_is_rvc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_rvc = clr_uop_3_is_rvc; // @[util.scala:104:23] reg [39:0] clr_uop_3_debug_pc; // @[lsu.scala:1086:24] wire [39:0] clr_uop_1_out_2_debug_pc = clr_uop_3_debug_pc; // @[util.scala:104:23] reg clr_uop_3_iq_type_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_0 = clr_uop_3_iq_type_0; // @[util.scala:104:23] reg clr_uop_3_iq_type_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_1 = clr_uop_3_iq_type_1; // @[util.scala:104:23] reg clr_uop_3_iq_type_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_2 = clr_uop_3_iq_type_2; // @[util.scala:104:23] reg clr_uop_3_iq_type_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iq_type_3 = clr_uop_3_iq_type_3; // @[util.scala:104:23] reg clr_uop_3_fu_code_0; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_0 = clr_uop_3_fu_code_0; // @[util.scala:104:23] reg clr_uop_3_fu_code_1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_1 = clr_uop_3_fu_code_1; // @[util.scala:104:23] reg clr_uop_3_fu_code_2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_2 = clr_uop_3_fu_code_2; // @[util.scala:104:23] reg clr_uop_3_fu_code_3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_3 = clr_uop_3_fu_code_3; // @[util.scala:104:23] reg clr_uop_3_fu_code_4; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_4 = clr_uop_3_fu_code_4; // @[util.scala:104:23] reg clr_uop_3_fu_code_5; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_5 = clr_uop_3_fu_code_5; // @[util.scala:104:23] reg clr_uop_3_fu_code_6; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_6 = clr_uop_3_fu_code_6; // @[util.scala:104:23] reg clr_uop_3_fu_code_7; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_7 = clr_uop_3_fu_code_7; // @[util.scala:104:23] reg clr_uop_3_fu_code_8; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_8 = clr_uop_3_fu_code_8; // @[util.scala:104:23] reg clr_uop_3_fu_code_9; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fu_code_9 = clr_uop_3_fu_code_9; // @[util.scala:104:23] reg clr_uop_3_iw_issued; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued = clr_uop_3_iw_issued; // @[util.scala:104:23] reg clr_uop_3_iw_issued_partial_agen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued_partial_agen = clr_uop_3_iw_issued_partial_agen; // @[util.scala:104:23] reg clr_uop_3_iw_issued_partial_dgen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_issued_partial_dgen = clr_uop_3_iw_issued_partial_dgen; // @[util.scala:104:23] reg [2:0] clr_uop_3_iw_p1_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_iw_p1_speculative_child = clr_uop_3_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] clr_uop_3_iw_p2_speculative_child; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_iw_p2_speculative_child = clr_uop_3_iw_p2_speculative_child; // @[util.scala:104:23] reg clr_uop_3_iw_p1_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p1_bypass_hint = clr_uop_3_iw_p1_bypass_hint; // @[util.scala:104:23] reg clr_uop_3_iw_p2_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p2_bypass_hint = clr_uop_3_iw_p2_bypass_hint; // @[util.scala:104:23] reg clr_uop_3_iw_p3_bypass_hint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_iw_p3_bypass_hint = clr_uop_3_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] clr_uop_3_dis_col_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_dis_col_sel = clr_uop_3_dis_col_sel; // @[util.scala:104:23] reg [15:0] clr_uop_3_br_mask; // @[lsu.scala:1086:24] reg [3:0] clr_uop_3_br_tag; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_2_br_tag = clr_uop_3_br_tag; // @[util.scala:104:23] reg [3:0] clr_uop_3_br_type; // @[lsu.scala:1086:24] wire [3:0] clr_uop_1_out_2_br_type = clr_uop_3_br_type; // @[util.scala:104:23] reg clr_uop_3_is_sfb; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sfb = clr_uop_3_is_sfb; // @[util.scala:104:23] reg clr_uop_3_is_fence; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_fence = clr_uop_3_is_fence; // @[util.scala:104:23] reg clr_uop_3_is_fencei; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_fencei = clr_uop_3_is_fencei; // @[util.scala:104:23] reg clr_uop_3_is_sfence; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sfence = clr_uop_3_is_sfence; // @[util.scala:104:23] reg clr_uop_3_is_amo; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_amo = clr_uop_3_is_amo; // @[util.scala:104:23] reg clr_uop_3_is_eret; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_eret = clr_uop_3_is_eret; // @[util.scala:104:23] reg clr_uop_3_is_sys_pc2epc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_sys_pc2epc = clr_uop_3_is_sys_pc2epc; // @[util.scala:104:23] reg clr_uop_3_is_rocc; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_rocc = clr_uop_3_is_rocc; // @[util.scala:104:23] reg clr_uop_3_is_mov; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_mov = clr_uop_3_is_mov; // @[util.scala:104:23] reg [4:0] clr_uop_3_ftq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ftq_idx = clr_uop_3_ftq_idx; // @[util.scala:104:23] reg clr_uop_3_edge_inst; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_edge_inst = clr_uop_3_edge_inst; // @[util.scala:104:23] reg [5:0] clr_uop_3_pc_lob; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_pc_lob = clr_uop_3_pc_lob; // @[util.scala:104:23] reg clr_uop_3_taken; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_taken = clr_uop_3_taken; // @[util.scala:104:23] reg clr_uop_3_imm_rename; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_imm_rename = clr_uop_3_imm_rename; // @[util.scala:104:23] reg [2:0] clr_uop_3_imm_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_imm_sel = clr_uop_3_imm_sel; // @[util.scala:104:23] reg [4:0] clr_uop_3_pimm; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_pimm = clr_uop_3_pimm; // @[util.scala:104:23] reg [19:0] clr_uop_3_imm_packed; // @[lsu.scala:1086:24] wire [19:0] clr_uop_1_out_2_imm_packed = clr_uop_3_imm_packed; // @[util.scala:104:23] reg [1:0] clr_uop_3_op1_sel; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_op1_sel = clr_uop_3_op1_sel; // @[util.scala:104:23] reg [2:0] clr_uop_3_op2_sel; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_op2_sel = clr_uop_3_op2_sel; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ldst; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ldst = clr_uop_3_fp_ctrl_ldst; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_wen; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_wen = clr_uop_3_fp_ctrl_wen; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren1 = clr_uop_3_fp_ctrl_ren1; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren2; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren2 = clr_uop_3_fp_ctrl_ren2; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_ren3; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_ren3 = clr_uop_3_fp_ctrl_ren3; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_swap12; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_swap12 = clr_uop_3_fp_ctrl_swap12; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_swap23; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_swap23 = clr_uop_3_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_ctrl_typeTagIn; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_ctrl_typeTagIn = clr_uop_3_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_ctrl_typeTagOut; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_ctrl_typeTagOut = clr_uop_3_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fromint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fromint = clr_uop_3_fp_ctrl_fromint; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_toint; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_toint = clr_uop_3_fp_ctrl_toint; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fastpipe; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fastpipe = clr_uop_3_fp_ctrl_fastpipe; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_fma; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_fma = clr_uop_3_fp_ctrl_fma; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_div; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_div = clr_uop_3_fp_ctrl_div; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_sqrt; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_sqrt = clr_uop_3_fp_ctrl_sqrt; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_wflags; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_wflags = clr_uop_3_fp_ctrl_wflags; // @[util.scala:104:23] reg clr_uop_3_fp_ctrl_vec; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_ctrl_vec = clr_uop_3_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] clr_uop_3_rob_idx; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_rob_idx = clr_uop_3_rob_idx; // @[util.scala:104:23] reg [4:0] clr_uop_3_ldq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ldq_idx = clr_uop_3_ldq_idx; // @[util.scala:104:23] reg [4:0] clr_uop_3_stq_idx; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_stq_idx = clr_uop_3_stq_idx; // @[util.scala:104:23] reg [1:0] clr_uop_3_rxq_idx; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_rxq_idx = clr_uop_3_rxq_idx; // @[util.scala:104:23] reg [6:0] clr_uop_3_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_pdst = clr_uop_3_pdst; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs1; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs1 = clr_uop_3_prs1; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs2; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs2 = clr_uop_3_prs2; // @[util.scala:104:23] reg [6:0] clr_uop_3_prs3; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_prs3 = clr_uop_3_prs3; // @[util.scala:104:23] reg [4:0] clr_uop_3_ppred; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_ppred = clr_uop_3_ppred; // @[util.scala:104:23] reg clr_uop_3_prs1_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs1_busy = clr_uop_3_prs1_busy; // @[util.scala:104:23] reg clr_uop_3_prs2_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs2_busy = clr_uop_3_prs2_busy; // @[util.scala:104:23] reg clr_uop_3_prs3_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_prs3_busy = clr_uop_3_prs3_busy; // @[util.scala:104:23] reg clr_uop_3_ppred_busy; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_ppred_busy = clr_uop_3_ppred_busy; // @[util.scala:104:23] reg [6:0] clr_uop_3_stale_pdst; // @[lsu.scala:1086:24] wire [6:0] clr_uop_1_out_2_stale_pdst = clr_uop_3_stale_pdst; // @[util.scala:104:23] reg clr_uop_3_exception; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_exception = clr_uop_3_exception; // @[util.scala:104:23] reg [63:0] clr_uop_3_exc_cause; // @[lsu.scala:1086:24] wire [63:0] clr_uop_1_out_2_exc_cause = clr_uop_3_exc_cause; // @[util.scala:104:23] reg [4:0] clr_uop_3_mem_cmd; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_mem_cmd = clr_uop_3_mem_cmd; // @[util.scala:104:23] reg [1:0] clr_uop_3_mem_size; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_mem_size = clr_uop_3_mem_size; // @[util.scala:104:23] reg clr_uop_3_mem_signed; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_mem_signed = clr_uop_3_mem_signed; // @[util.scala:104:23] reg clr_uop_3_uses_ldq; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_uses_ldq = clr_uop_3_uses_ldq; // @[util.scala:104:23] reg clr_uop_3_uses_stq; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_uses_stq = clr_uop_3_uses_stq; // @[util.scala:104:23] reg clr_uop_3_is_unique; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_is_unique = clr_uop_3_is_unique; // @[util.scala:104:23] reg clr_uop_3_flush_on_commit; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_flush_on_commit = clr_uop_3_flush_on_commit; // @[util.scala:104:23] reg [2:0] clr_uop_3_csr_cmd; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_csr_cmd = clr_uop_3_csr_cmd; // @[util.scala:104:23] reg clr_uop_3_ldst_is_rs1; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_ldst_is_rs1 = clr_uop_3_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] clr_uop_3_ldst; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_ldst = clr_uop_3_ldst; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs1; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs1 = clr_uop_3_lrs1; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs2; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs2 = clr_uop_3_lrs2; // @[util.scala:104:23] reg [5:0] clr_uop_3_lrs3; // @[lsu.scala:1086:24] wire [5:0] clr_uop_1_out_2_lrs3 = clr_uop_3_lrs3; // @[util.scala:104:23] reg [1:0] clr_uop_3_dst_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_dst_rtype = clr_uop_3_dst_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_3_lrs1_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_lrs1_rtype = clr_uop_3_lrs1_rtype; // @[util.scala:104:23] reg [1:0] clr_uop_3_lrs2_rtype; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_lrs2_rtype = clr_uop_3_lrs2_rtype; // @[util.scala:104:23] reg clr_uop_3_frs3_en; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_frs3_en = clr_uop_3_frs3_en; // @[util.scala:104:23] reg clr_uop_3_fcn_dw; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fcn_dw = clr_uop_3_fcn_dw; // @[util.scala:104:23] reg [4:0] clr_uop_3_fcn_op; // @[lsu.scala:1086:24] wire [4:0] clr_uop_1_out_2_fcn_op = clr_uop_3_fcn_op; // @[util.scala:104:23] reg clr_uop_3_fp_val; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_fp_val = clr_uop_3_fp_val; // @[util.scala:104:23] reg [2:0] clr_uop_3_fp_rm; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_fp_rm = clr_uop_3_fp_rm; // @[util.scala:104:23] reg [1:0] clr_uop_3_fp_typ; // @[lsu.scala:1086:24] wire [1:0] clr_uop_1_out_2_fp_typ = clr_uop_3_fp_typ; // @[util.scala:104:23] reg clr_uop_3_xcpt_pf_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_pf_if = clr_uop_3_xcpt_pf_if; // @[util.scala:104:23] reg clr_uop_3_xcpt_ae_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_ae_if = clr_uop_3_xcpt_ae_if; // @[util.scala:104:23] reg clr_uop_3_xcpt_ma_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_xcpt_ma_if = clr_uop_3_xcpt_ma_if; // @[util.scala:104:23] reg clr_uop_3_bp_debug_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_bp_debug_if = clr_uop_3_bp_debug_if; // @[util.scala:104:23] reg clr_uop_3_bp_xcpt_if; // @[lsu.scala:1086:24] wire clr_uop_1_out_2_bp_xcpt_if = clr_uop_3_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] clr_uop_3_debug_fsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_debug_fsrc = clr_uop_3_debug_fsrc; // @[util.scala:104:23] reg [2:0] clr_uop_3_debug_tsrc; // @[lsu.scala:1086:24] wire [2:0] clr_uop_1_out_2_debug_tsrc = clr_uop_3_debug_tsrc; // @[util.scala:104:23] wire [15:0] _clr_valid_1_T_10 = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_3_br_mask; // @[util.scala:126:51] wire _clr_valid_1_T_11 = |_clr_valid_1_T_10; // @[util.scala:126:{51,59}] wire _clr_valid_1_T_12 = _clr_valid_1_T_11 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _clr_valid_1_T_13 = ~_clr_valid_1_T_12; // @[util.scala:61:61] wire _clr_valid_1_T_14 = clr_valid_3 & _clr_valid_1_T_13; // @[lsu.scala:1084:24, :1088:{41,44}] reg clr_valid_1_2; // @[lsu.scala:1088:30] wire [15:0] _clr_uop_1_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] clr_uop_1_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_1_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_1_out_br_mask_T_5 = clr_uop_3_br_mask & _clr_uop_1_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign clr_uop_1_out_2_br_mask = _clr_uop_1_out_br_mask_T_5; // @[util.scala:93:25, :104:23] reg [31:0] clr_uop_1_2_inst; // @[lsu.scala:1089:30] reg [31:0] clr_uop_1_2_debug_inst; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_rvc; // @[lsu.scala:1089:30] reg [39:0] clr_uop_1_2_debug_pc; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_0; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_1; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_2; // @[lsu.scala:1089:30] reg clr_uop_1_2_iq_type_3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_0; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_1; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_2; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_4; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_5; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_6; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_7; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_8; // @[lsu.scala:1089:30] reg clr_uop_1_2_fu_code_9; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued_partial_agen; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_issued_partial_dgen; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_iw_p1_speculative_child; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_iw_p2_speculative_child; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p1_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p2_bypass_hint; // @[lsu.scala:1089:30] reg clr_uop_1_2_iw_p3_bypass_hint; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_dis_col_sel; // @[lsu.scala:1089:30] reg [15:0] clr_uop_1_2_br_mask; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_2_br_tag; // @[lsu.scala:1089:30] reg [3:0] clr_uop_1_2_br_type; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sfb; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_fence; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_fencei; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sfence; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_amo; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_eret; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_sys_pc2epc; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_rocc; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_mov; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_ftq_idx; // @[lsu.scala:1089:30] reg clr_uop_1_2_edge_inst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_pc_lob; // @[lsu.scala:1089:30] reg clr_uop_1_2_taken; // @[lsu.scala:1089:30] reg clr_uop_1_2_imm_rename; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_imm_sel; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_pimm; // @[lsu.scala:1089:30] reg [19:0] clr_uop_1_2_imm_packed; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_op1_sel; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_op2_sel; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ldst; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_wen; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren1; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren2; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_ren3; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_swap12; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_swap23; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_ctrl_typeTagIn; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_ctrl_typeTagOut; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fromint; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_toint; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fastpipe; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_fma; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_div; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_sqrt; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_wflags; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_ctrl_vec; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_rob_idx; // @[lsu.scala:1089:30] assign io_core_clr_bsy_2_bits_0 = clr_uop_1_2_rob_idx; // @[lsu.scala:211:7, :1089:30] reg [4:0] clr_uop_1_2_ldq_idx; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_stq_idx; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_rxq_idx; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_pdst; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs1; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs2; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_prs3; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_ppred; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs1_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs2_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_prs3_busy; // @[lsu.scala:1089:30] reg clr_uop_1_2_ppred_busy; // @[lsu.scala:1089:30] reg [6:0] clr_uop_1_2_stale_pdst; // @[lsu.scala:1089:30] reg clr_uop_1_2_exception; // @[lsu.scala:1089:30] reg [63:0] clr_uop_1_2_exc_cause; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_mem_cmd; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_mem_size; // @[lsu.scala:1089:30] reg clr_uop_1_2_mem_signed; // @[lsu.scala:1089:30] reg clr_uop_1_2_uses_ldq; // @[lsu.scala:1089:30] reg clr_uop_1_2_uses_stq; // @[lsu.scala:1089:30] reg clr_uop_1_2_is_unique; // @[lsu.scala:1089:30] reg clr_uop_1_2_flush_on_commit; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_csr_cmd; // @[lsu.scala:1089:30] reg clr_uop_1_2_ldst_is_rs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_ldst; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs1; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs2; // @[lsu.scala:1089:30] reg [5:0] clr_uop_1_2_lrs3; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_dst_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_lrs1_rtype; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_lrs2_rtype; // @[lsu.scala:1089:30] reg clr_uop_1_2_frs3_en; // @[lsu.scala:1089:30] reg clr_uop_1_2_fcn_dw; // @[lsu.scala:1089:30] reg [4:0] clr_uop_1_2_fcn_op; // @[lsu.scala:1089:30] reg clr_uop_1_2_fp_val; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_fp_rm; // @[lsu.scala:1089:30] reg [1:0] clr_uop_1_2_fp_typ; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_pf_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_ae_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_xcpt_ma_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_bp_debug_if; // @[lsu.scala:1089:30] reg clr_uop_1_2_bp_xcpt_if; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_debug_fsrc; // @[lsu.scala:1089:30] reg [2:0] clr_uop_1_2_debug_tsrc; // @[lsu.scala:1089:30] wire [4:0] _s_uop_T_5 = _s_uop_T_4; wire [31:0] clr_uop_out_2_inst = s_uop_2_inst; // @[util.scala:104:23] wire [31:0] clr_uop_out_2_debug_inst = s_uop_2_debug_inst; // @[util.scala:104:23] wire clr_uop_out_2_is_rvc = s_uop_2_is_rvc; // @[util.scala:104:23] wire [39:0] clr_uop_out_2_debug_pc = s_uop_2_debug_pc; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_0 = s_uop_2_iq_type_0; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_1 = s_uop_2_iq_type_1; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_2 = s_uop_2_iq_type_2; // @[util.scala:104:23] wire clr_uop_out_2_iq_type_3 = s_uop_2_iq_type_3; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_0 = s_uop_2_fu_code_0; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_1 = s_uop_2_fu_code_1; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_2 = s_uop_2_fu_code_2; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_3 = s_uop_2_fu_code_3; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_4 = s_uop_2_fu_code_4; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_5 = s_uop_2_fu_code_5; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_6 = s_uop_2_fu_code_6; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_7 = s_uop_2_fu_code_7; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_8 = s_uop_2_fu_code_8; // @[util.scala:104:23] wire clr_uop_out_2_fu_code_9 = s_uop_2_fu_code_9; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued = s_uop_2_iw_issued; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued_partial_agen = s_uop_2_iw_issued_partial_agen; // @[util.scala:104:23] wire clr_uop_out_2_iw_issued_partial_dgen = s_uop_2_iw_issued_partial_dgen; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_iw_p1_speculative_child = s_uop_2_iw_p1_speculative_child; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_iw_p2_speculative_child = s_uop_2_iw_p2_speculative_child; // @[util.scala:104:23] wire clr_uop_out_2_iw_p1_bypass_hint = s_uop_2_iw_p1_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_2_iw_p2_bypass_hint = s_uop_2_iw_p2_bypass_hint; // @[util.scala:104:23] wire clr_uop_out_2_iw_p3_bypass_hint = s_uop_2_iw_p3_bypass_hint; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_dis_col_sel = s_uop_2_dis_col_sel; // @[util.scala:104:23] wire [3:0] clr_uop_out_2_br_tag = s_uop_2_br_tag; // @[util.scala:104:23] wire [3:0] clr_uop_out_2_br_type = s_uop_2_br_type; // @[util.scala:104:23] wire clr_uop_out_2_is_sfb = s_uop_2_is_sfb; // @[util.scala:104:23] wire clr_uop_out_2_is_fence = s_uop_2_is_fence; // @[util.scala:104:23] wire clr_uop_out_2_is_fencei = s_uop_2_is_fencei; // @[util.scala:104:23] wire clr_uop_out_2_is_sfence = s_uop_2_is_sfence; // @[util.scala:104:23] wire clr_uop_out_2_is_amo = s_uop_2_is_amo; // @[util.scala:104:23] wire clr_uop_out_2_is_eret = s_uop_2_is_eret; // @[util.scala:104:23] wire clr_uop_out_2_is_sys_pc2epc = s_uop_2_is_sys_pc2epc; // @[util.scala:104:23] wire clr_uop_out_2_is_rocc = s_uop_2_is_rocc; // @[util.scala:104:23] wire clr_uop_out_2_is_mov = s_uop_2_is_mov; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ftq_idx = s_uop_2_ftq_idx; // @[util.scala:104:23] wire clr_uop_out_2_edge_inst = s_uop_2_edge_inst; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_pc_lob = s_uop_2_pc_lob; // @[util.scala:104:23] wire clr_uop_out_2_taken = s_uop_2_taken; // @[util.scala:104:23] wire clr_uop_out_2_imm_rename = s_uop_2_imm_rename; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_imm_sel = s_uop_2_imm_sel; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_pimm = s_uop_2_pimm; // @[util.scala:104:23] wire [19:0] clr_uop_out_2_imm_packed = s_uop_2_imm_packed; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_op1_sel = s_uop_2_op1_sel; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_op2_sel = s_uop_2_op2_sel; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ldst = s_uop_2_fp_ctrl_ldst; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_wen = s_uop_2_fp_ctrl_wen; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren1 = s_uop_2_fp_ctrl_ren1; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren2 = s_uop_2_fp_ctrl_ren2; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_ren3 = s_uop_2_fp_ctrl_ren3; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_swap12 = s_uop_2_fp_ctrl_swap12; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_swap23 = s_uop_2_fp_ctrl_swap23; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_ctrl_typeTagIn = s_uop_2_fp_ctrl_typeTagIn; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_ctrl_typeTagOut = s_uop_2_fp_ctrl_typeTagOut; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fromint = s_uop_2_fp_ctrl_fromint; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_toint = s_uop_2_fp_ctrl_toint; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fastpipe = s_uop_2_fp_ctrl_fastpipe; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_fma = s_uop_2_fp_ctrl_fma; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_div = s_uop_2_fp_ctrl_div; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_sqrt = s_uop_2_fp_ctrl_sqrt; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_wflags = s_uop_2_fp_ctrl_wflags; // @[util.scala:104:23] wire clr_uop_out_2_fp_ctrl_vec = s_uop_2_fp_ctrl_vec; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_rob_idx = s_uop_2_rob_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ldq_idx = s_uop_2_ldq_idx; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_stq_idx = s_uop_2_stq_idx; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_rxq_idx = s_uop_2_rxq_idx; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_pdst = s_uop_2_pdst; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs1 = s_uop_2_prs1; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs2 = s_uop_2_prs2; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_prs3 = s_uop_2_prs3; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_ppred = s_uop_2_ppred; // @[util.scala:104:23] wire clr_uop_out_2_prs1_busy = s_uop_2_prs1_busy; // @[util.scala:104:23] wire clr_uop_out_2_prs2_busy = s_uop_2_prs2_busy; // @[util.scala:104:23] wire clr_uop_out_2_prs3_busy = s_uop_2_prs3_busy; // @[util.scala:104:23] wire clr_uop_out_2_ppred_busy = s_uop_2_ppred_busy; // @[util.scala:104:23] wire [6:0] clr_uop_out_2_stale_pdst = s_uop_2_stale_pdst; // @[util.scala:104:23] wire clr_uop_out_2_exception = s_uop_2_exception; // @[util.scala:104:23] wire [63:0] clr_uop_out_2_exc_cause = s_uop_2_exc_cause; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_mem_cmd = s_uop_2_mem_cmd; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_mem_size = s_uop_2_mem_size; // @[util.scala:104:23] wire clr_uop_out_2_mem_signed = s_uop_2_mem_signed; // @[util.scala:104:23] wire clr_uop_out_2_uses_ldq = s_uop_2_uses_ldq; // @[util.scala:104:23] wire clr_uop_out_2_uses_stq = s_uop_2_uses_stq; // @[util.scala:104:23] wire clr_uop_out_2_is_unique = s_uop_2_is_unique; // @[util.scala:104:23] wire clr_uop_out_2_flush_on_commit = s_uop_2_flush_on_commit; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_csr_cmd = s_uop_2_csr_cmd; // @[util.scala:104:23] wire clr_uop_out_2_ldst_is_rs1 = s_uop_2_ldst_is_rs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_ldst = s_uop_2_ldst; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs1 = s_uop_2_lrs1; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs2 = s_uop_2_lrs2; // @[util.scala:104:23] wire [5:0] clr_uop_out_2_lrs3 = s_uop_2_lrs3; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_dst_rtype = s_uop_2_dst_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_lrs1_rtype = s_uop_2_lrs1_rtype; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_lrs2_rtype = s_uop_2_lrs2_rtype; // @[util.scala:104:23] wire clr_uop_out_2_frs3_en = s_uop_2_frs3_en; // @[util.scala:104:23] wire clr_uop_out_2_fcn_dw = s_uop_2_fcn_dw; // @[util.scala:104:23] wire [4:0] clr_uop_out_2_fcn_op = s_uop_2_fcn_op; // @[util.scala:104:23] wire clr_uop_out_2_fp_val = s_uop_2_fp_val; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_fp_rm = s_uop_2_fp_rm; // @[util.scala:104:23] wire [1:0] clr_uop_out_2_fp_typ = s_uop_2_fp_typ; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_pf_if = s_uop_2_xcpt_pf_if; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_ae_if = s_uop_2_xcpt_ae_if; // @[util.scala:104:23] wire clr_uop_out_2_xcpt_ma_if = s_uop_2_xcpt_ma_if; // @[util.scala:104:23] wire clr_uop_out_2_bp_debug_if = s_uop_2_bp_debug_if; // @[util.scala:104:23] wire clr_uop_out_2_bp_xcpt_if = s_uop_2_bp_xcpt_if; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_debug_fsrc = s_uop_2_debug_fsrc; // @[util.scala:104:23] wire [2:0] clr_uop_out_2_debug_tsrc = s_uop_2_debug_tsrc; // @[util.scala:104:23] wire [15:0] s_uop_2_br_mask; // @[lsu.scala:1093:25] assign s_uop_2_inst = _GEN_251[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_inst = _GEN_252[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_rvc = _GEN_253[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_pc = _GEN_254[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_0 = _GEN_255[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_1 = _GEN_256[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_2 = _GEN_257[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iq_type_3 = _GEN_258[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_0 = _GEN_259[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_1 = _GEN_260[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_2 = _GEN_261[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_3 = _GEN_262[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_4 = _GEN_263[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_5 = _GEN_264[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_6 = _GEN_265[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_7 = _GEN_266[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_8 = _GEN_267[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fu_code_9 = _GEN_268[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued = _GEN_269[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued_partial_agen = _GEN_270[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_issued_partial_dgen = _GEN_271[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p1_speculative_child = _GEN_272[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p2_speculative_child = _GEN_273[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p1_bypass_hint = _GEN_274[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p2_bypass_hint = _GEN_275[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_iw_p3_bypass_hint = _GEN_276[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_dis_col_sel = _GEN_277[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_mask = _GEN_278[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_tag = _GEN_279[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_br_type = _GEN_280[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sfb = _GEN_281[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_fence = _GEN_282[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_fencei = _GEN_283[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sfence = _GEN_284[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_amo = _GEN_285[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_eret = _GEN_286[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_sys_pc2epc = _GEN_287[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_rocc = _GEN_288[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_mov = _GEN_289[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ftq_idx = _GEN_290[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_edge_inst = _GEN_291[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pc_lob = _GEN_292[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_taken = _GEN_293[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_rename = _GEN_294[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_sel = _GEN_295[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pimm = _GEN_296[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_imm_packed = _GEN_297[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_op1_sel = _GEN_298[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_op2_sel = _GEN_299[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ldst = _GEN_300[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_wen = _GEN_301[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren1 = _GEN_302[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren2 = _GEN_303[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_ren3 = _GEN_304[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_swap12 = _GEN_305[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_swap23 = _GEN_306[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_typeTagIn = _GEN_307[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_typeTagOut = _GEN_308[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fromint = _GEN_309[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_toint = _GEN_310[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fastpipe = _GEN_311[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_fma = _GEN_312[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_div = _GEN_313[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_sqrt = _GEN_314[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_wflags = _GEN_315[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_ctrl_vec = _GEN_316[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_rob_idx = _GEN_317[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldq_idx = _GEN_318[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_stq_idx = _GEN_319[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_rxq_idx = _GEN_320[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_pdst = _GEN_321[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs1 = _GEN_322[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs2 = _GEN_323[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs3 = _GEN_324[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ppred = _GEN_325[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs1_busy = _GEN_326[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs2_busy = _GEN_327[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_prs3_busy = _GEN_328[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ppred_busy = _GEN_329[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_stale_pdst = _GEN_330[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_exception = _GEN_331[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_exc_cause = _GEN_332[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_cmd = _GEN_333[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_size = _GEN_334[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_mem_signed = _GEN_335[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_uses_ldq = _GEN_336[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_uses_stq = _GEN_337[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_is_unique = _GEN_338[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_flush_on_commit = _GEN_339[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_csr_cmd = _GEN_340[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldst_is_rs1 = _GEN_341[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_ldst = _GEN_342[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs1 = _GEN_343[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs2 = _GEN_344[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs3 = _GEN_345[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_dst_rtype = _GEN_346[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs1_rtype = _GEN_347[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_lrs2_rtype = _GEN_348[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_frs3_en = _GEN_349[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fcn_dw = _GEN_350[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fcn_op = _GEN_351[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_val = _GEN_352[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_rm = _GEN_353[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_fp_typ = _GEN_354[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_pf_if = _GEN_355[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_ae_if = _GEN_356[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_xcpt_ma_if = _GEN_357[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_bp_debug_if = _GEN_358[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_bp_xcpt_if = _GEN_359[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_fsrc = _GEN_360[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] assign s_uop_2_debug_tsrc = _GEN_361[_s_uop_T_5]; // @[lsu.scala:264:32, :1093:25] wire [15:0] _clr_uop_out_br_mask_T_5; // @[util.scala:93:25] wire [15:0] clr_uop_out_2_br_mask; // @[util.scala:104:23] wire [15:0] _clr_uop_out_br_mask_T_4 = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _clr_uop_out_br_mask_T_5 = s_uop_2_br_mask & _clr_uop_out_br_mask_T_4; // @[util.scala:93:{25,27}] assign clr_uop_out_2_br_mask = _clr_uop_out_br_mask_T_5; // @[util.scala:93:25, :104:23] wire wrap_8 = _s_uop_T_4 == 5'h17; // @[util.scala:213:25] wire [15:0] _io_core_clr_bsy_2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & clr_uop_1_2_br_mask; // @[util.scala:126:51] wire _io_core_clr_bsy_2_valid_T_1 = |_io_core_clr_bsy_2_valid_T; // @[util.scala:126:{51,59}] wire _io_core_clr_bsy_2_valid_T_2 = _io_core_clr_bsy_2_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_clr_bsy_2_valid_T_3 = ~_io_core_clr_bsy_2_valid_T_2; // @[util.scala:61:61] assign _io_core_clr_bsy_2_valid_T_4 = clr_valid_1_2 & _io_core_clr_bsy_2_valid_T_3; // @[lsu.scala:1088:30, :1107:{45,48}] assign io_core_clr_bsy_2_valid_0 = _io_core_clr_bsy_2_valid_T_4; // @[lsu.scala:211:7, :1107:45] wire _GEN_479 = fired_store_agen_0 | fired_store_retry_0; // @[lsu.scala:321:49, :1122:57] wire _do_st_search_T; // @[lsu.scala:1122:57] assign _do_st_search_T = _GEN_479; // @[lsu.scala:1122:57] wire _lcam_addr_T; // @[lsu.scala:1133:58] assign _lcam_addr_T = _GEN_479; // @[lsu.scala:1122:57, :1133:58] wire _do_st_search_T_1 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85] wire _do_st_search_T_2 = _do_st_search_T & _do_st_search_T_1; // @[lsu.scala:1122:{57,82,85}] wire do_st_search_0 = _do_st_search_T_2; // @[lsu.scala:321:49, :1122:82] wire _do_ld_search_T_1 = _do_ld_search_T | fired_load_retry_0; // @[lsu.scala:321:49, :1124:{57,84}] wire _do_ld_search_T_2 = ~mem_tlb_miss_0; // @[lsu.scala:1070:41, :1122:85, :1124:111] wire _do_ld_search_T_3 = _do_ld_search_T_1 & _do_ld_search_T_2; // @[lsu.scala:1124:{84,108,111}] wire _do_ld_search_T_4 = _do_ld_search_T_3 | fired_load_wakeup_0; // @[lsu.scala:321:49, :1124:{108,129}] wire do_ld_search_0 = _do_ld_search_T_4; // @[lsu.scala:321:49, :1124:129] wire _lcam_addr_T_1 = _lcam_addr_T | fired_load_agen_0; // @[lsu.scala:321:49, :1133:{58,82}] wire _lcam_addr_T_2 = _lcam_addr_T_1 | fired_load_agen_exec_0; // @[lsu.scala:321:49, :1133:{82,104}] reg [31:0] lcam_addr_REG; // @[lsu.scala:1134:45] reg [31:0] lcam_addr_REG_1; // @[lsu.scala:1135:67] wire [39:0] _lcam_addr_T_3 = fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0; // @[lsu.scala:1045:37, :1072:41, :1135:{41,67}] wire [39:0] _lcam_addr_T_4 = _lcam_addr_T_2 ? {8'h0, lcam_addr_REG} : _lcam_addr_T_3; // @[lsu.scala:1133:{37,104}, :1134:45, :1135:41] wire [39:0] lcam_addr_0 = _lcam_addr_T_4; // @[lsu.scala:321:49, :1133:37] wire [31:0] _lcam_uop_T_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_debug_inst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_inst : 32'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rvc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rvc; // @[lsu.scala:321:49, :1138:37] wire [39:0] _lcam_uop_T_debug_pc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_pc : 40'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iq_type_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_iq_type_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_0 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_4 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_4; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_5 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_5; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_6 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_6; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_7 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_7; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_8 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_8; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fu_code_9 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fu_code_9; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_agen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_issued_partial_dgen = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_iw_p1_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p1_speculative_child : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_iw_p2_speculative_child = do_ld_search_0 ? mem_ldq_e_0_bits_uop_iw_p2_speculative_child : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p1_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p2_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_iw_p3_bypass_hint = do_ld_search_0 & mem_ldq_e_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_dis_col_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dis_col_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [15:0] _lcam_uop_T_br_mask = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_mask : 16'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_tag = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_tag : 4'h0; // @[lsu.scala:321:49, :1138:37] wire [3:0] _lcam_uop_T_br_type = do_ld_search_0 ? mem_ldq_e_0_bits_uop_br_type : 4'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfb = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfb; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_fencei = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_fencei; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sfence = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sfence; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_amo = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_amo; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_eret = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_eret; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_sys_pc2epc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_rocc = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_rocc; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_mov = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_mov; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ftq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ftq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_edge_inst = do_ld_search_0 & mem_ldq_e_0_bits_uop_edge_inst; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_pc_lob = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pc_lob : 6'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_taken = do_ld_search_0 & mem_ldq_e_0_bits_uop_taken; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_imm_rename = do_ld_search_0 & mem_ldq_e_0_bits_uop_imm_rename; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_imm_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_pimm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pimm : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [19:0] _lcam_uop_T_imm_packed = do_ld_search_0 ? mem_ldq_e_0_bits_uop_imm_packed : 20'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_op1_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op1_sel : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_op2_sel = do_ld_search_0 ? mem_ldq_e_0_bits_uop_op2_sel : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ldst = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wen = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren2 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_ren3 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap12 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_swap23 = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagIn = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagIn : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_ctrl_typeTagOut = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_ctrl_typeTagOut : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fromint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_toint = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fastpipe = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_fma = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_div = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_sqrt = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_wflags = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_ctrl_vec = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_rob_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rob_idx : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ldq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_stq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stq_idx : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_rxq_idx = do_ld_search_0 ? mem_ldq_e_0_bits_uop_rxq_idx : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs1 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs2 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_prs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_prs3 : 7'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_ppred = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ppred : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs1_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs1_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs2_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs2_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_prs3_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_prs3_busy; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ppred_busy = do_ld_search_0 & mem_ldq_e_0_bits_uop_ppred_busy; // @[lsu.scala:321:49, :1138:37] wire [6:0] _lcam_uop_T_stale_pdst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_stale_pdst : 7'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_exception = do_ld_search_0 & mem_ldq_e_0_bits_uop_exception; // @[lsu.scala:321:49, :1138:37] wire [63:0] _lcam_uop_T_exc_cause = do_ld_search_0 ? mem_ldq_e_0_bits_uop_exc_cause : 64'h0; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_mem_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_cmd : 5'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_mem_size = do_ld_search_0 ? mem_ldq_e_0_bits_uop_mem_size : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_mem_signed = do_ld_search_0 & mem_ldq_e_0_bits_uop_mem_signed; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_ldq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_ldq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_uses_stq = do_ld_search_0 & mem_ldq_e_0_bits_uop_uses_stq; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_is_unique = do_ld_search_0 & mem_ldq_e_0_bits_uop_is_unique; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_flush_on_commit = do_ld_search_0 & mem_ldq_e_0_bits_uop_flush_on_commit; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_csr_cmd = do_ld_search_0 ? mem_ldq_e_0_bits_uop_csr_cmd : 3'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_ldst_is_rs1 = do_ld_search_0 & mem_ldq_e_0_bits_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_ldst = do_ld_search_0 ? mem_ldq_e_0_bits_uop_ldst : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs1 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs2 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [5:0] _lcam_uop_T_lrs3 = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs3 : 6'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_dst_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_dst_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs1_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs1_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_lrs2_rtype = do_ld_search_0 ? mem_ldq_e_0_bits_uop_lrs2_rtype : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_frs3_en = do_ld_search_0 & mem_ldq_e_0_bits_uop_frs3_en; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fcn_dw = do_ld_search_0 & mem_ldq_e_0_bits_uop_fcn_dw; // @[lsu.scala:321:49, :1138:37] wire [4:0] _lcam_uop_T_fcn_op = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fcn_op : 5'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_fp_val = do_ld_search_0 & mem_ldq_e_0_bits_uop_fp_val; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_fp_rm = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_rm : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [1:0] _lcam_uop_T_fp_typ = do_ld_search_0 ? mem_ldq_e_0_bits_uop_fp_typ : 2'h0; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_pf_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ae_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_xcpt_ma_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_debug_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_debug_if; // @[lsu.scala:321:49, :1138:37] wire _lcam_uop_T_bp_xcpt_if = do_ld_search_0 & mem_ldq_e_0_bits_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_fsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_fsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [2:0] _lcam_uop_T_debug_tsrc = do_ld_search_0 ? mem_ldq_e_0_bits_uop_debug_tsrc : 3'h0; // @[lsu.scala:321:49, :1138:37] wire [31:0] _lcam_uop_T_1_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_inst : _lcam_uop_T_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] _lcam_uop_T_1_debug_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_inst : _lcam_uop_T_debug_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rvc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rvc : _lcam_uop_T_is_rvc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [39:0] _lcam_uop_T_1_debug_pc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_pc : _lcam_uop_T_debug_pc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_0 : _lcam_uop_T_iq_type_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_1 : _lcam_uop_T_iq_type_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_2 : _lcam_uop_T_iq_type_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iq_type_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_iq_type_3 : _lcam_uop_T_iq_type_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_0 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_0 : _lcam_uop_T_fu_code_0; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_1 : _lcam_uop_T_fu_code_1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_2 : _lcam_uop_T_fu_code_2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_3 : _lcam_uop_T_fu_code_3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_4 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_4 : _lcam_uop_T_fu_code_4; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_5 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_5 : _lcam_uop_T_fu_code_5; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_6 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_6 : _lcam_uop_T_fu_code_6; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_7 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_7 : _lcam_uop_T_fu_code_7; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_8 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_8 : _lcam_uop_T_fu_code_8; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fu_code_9 = do_st_search_0 ? mem_stq_e_0_bits_uop_fu_code_9 : _lcam_uop_T_fu_code_9; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued : _lcam_uop_T_iw_issued; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_agen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_agen : _lcam_uop_T_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_issued_partial_dgen = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_issued_partial_dgen : _lcam_uop_T_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_iw_p1_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_speculative_child : _lcam_uop_T_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_iw_p2_speculative_child = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_speculative_child : _lcam_uop_T_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p1_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p1_bypass_hint : _lcam_uop_T_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p2_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p2_bypass_hint : _lcam_uop_T_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_iw_p3_bypass_hint = do_st_search_0 ? mem_stq_e_0_bits_uop_iw_p3_bypass_hint : _lcam_uop_T_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_dis_col_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_dis_col_sel : _lcam_uop_T_dis_col_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [15:0] _lcam_uop_T_1_br_mask = do_st_search_0 ? mem_stq_e_0_bits_uop_br_mask : _lcam_uop_T_br_mask; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_tag = do_st_search_0 ? mem_stq_e_0_bits_uop_br_tag : _lcam_uop_T_br_tag; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [3:0] _lcam_uop_T_1_br_type = do_st_search_0 ? mem_stq_e_0_bits_uop_br_type : _lcam_uop_T_br_type; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfb = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfb : _lcam_uop_T_is_sfb; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fence : _lcam_uop_T_is_fence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_fencei = do_st_search_0 ? mem_stq_e_0_bits_uop_is_fencei : _lcam_uop_T_is_fencei; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sfence = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sfence : _lcam_uop_T_is_sfence; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_amo = do_st_search_0 ? mem_stq_e_0_bits_uop_is_amo : _lcam_uop_T_is_amo; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_eret = do_st_search_0 ? mem_stq_e_0_bits_uop_is_eret : _lcam_uop_T_is_eret; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_sys_pc2epc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_sys_pc2epc : _lcam_uop_T_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_rocc = do_st_search_0 ? mem_stq_e_0_bits_uop_is_rocc : _lcam_uop_T_is_rocc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_mov = do_st_search_0 ? mem_stq_e_0_bits_uop_is_mov : _lcam_uop_T_is_mov; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ftq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ftq_idx : _lcam_uop_T_ftq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_edge_inst = do_st_search_0 ? mem_stq_e_0_bits_uop_edge_inst : _lcam_uop_T_edge_inst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_pc_lob = do_st_search_0 ? mem_stq_e_0_bits_uop_pc_lob : _lcam_uop_T_pc_lob; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_taken = do_st_search_0 ? mem_stq_e_0_bits_uop_taken : _lcam_uop_T_taken; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_imm_rename = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_rename : _lcam_uop_T_imm_rename; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_imm_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_sel : _lcam_uop_T_imm_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_pimm = do_st_search_0 ? mem_stq_e_0_bits_uop_pimm : _lcam_uop_T_pimm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [19:0] _lcam_uop_T_1_imm_packed = do_st_search_0 ? mem_stq_e_0_bits_uop_imm_packed : _lcam_uop_T_imm_packed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_op1_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op1_sel : _lcam_uop_T_op1_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_op2_sel = do_st_search_0 ? mem_stq_e_0_bits_uop_op2_sel : _lcam_uop_T_op2_sel; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ldst : _lcam_uop_T_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wen = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wen : _lcam_uop_T_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren1 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren1 : _lcam_uop_T_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren2 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren2 : _lcam_uop_T_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_ren3 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_ren3 : _lcam_uop_T_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap12 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap12 : _lcam_uop_T_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_swap23 = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_swap23 : _lcam_uop_T_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagIn = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagIn : _lcam_uop_T_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_ctrl_typeTagOut = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_typeTagOut : _lcam_uop_T_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fromint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fromint : _lcam_uop_T_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_toint = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_toint : _lcam_uop_T_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fastpipe = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fastpipe : _lcam_uop_T_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_fma = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_fma : _lcam_uop_T_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_div = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_div : _lcam_uop_T_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_sqrt = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_sqrt : _lcam_uop_T_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_wflags = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_wflags : _lcam_uop_T_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_ctrl_vec = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_ctrl_vec : _lcam_uop_T_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_rob_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rob_idx : _lcam_uop_T_rob_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ldq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_ldq_idx : _lcam_uop_T_ldq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_stq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_stq_idx : _lcam_uop_T_stq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_rxq_idx = do_st_search_0 ? mem_stq_e_0_bits_uop_rxq_idx : _lcam_uop_T_rxq_idx; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_pdst : _lcam_uop_T_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1 : _lcam_uop_T_prs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2 : _lcam_uop_T_prs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_prs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3 : _lcam_uop_T_prs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_ppred = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred : _lcam_uop_T_ppred; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs1_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs1_busy : _lcam_uop_T_prs1_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs2_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs2_busy : _lcam_uop_T_prs2_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_prs3_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_prs3_busy : _lcam_uop_T_prs3_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ppred_busy = do_st_search_0 ? mem_stq_e_0_bits_uop_ppred_busy : _lcam_uop_T_ppred_busy; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [6:0] _lcam_uop_T_1_stale_pdst = do_st_search_0 ? mem_stq_e_0_bits_uop_stale_pdst : _lcam_uop_T_stale_pdst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_exception = do_st_search_0 ? mem_stq_e_0_bits_uop_exception : _lcam_uop_T_exception; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [63:0] _lcam_uop_T_1_exc_cause = do_st_search_0 ? mem_stq_e_0_bits_uop_exc_cause : _lcam_uop_T_exc_cause; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_mem_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_cmd : _lcam_uop_T_mem_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_mem_size = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_size : _lcam_uop_T_mem_size; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_mem_signed = do_st_search_0 ? mem_stq_e_0_bits_uop_mem_signed : _lcam_uop_T_mem_signed; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_ldq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_ldq : _lcam_uop_T_uses_ldq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_uses_stq = do_st_search_0 ? mem_stq_e_0_bits_uop_uses_stq : _lcam_uop_T_uses_stq; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_is_unique = do_st_search_0 ? mem_stq_e_0_bits_uop_is_unique : _lcam_uop_T_is_unique; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_flush_on_commit = do_st_search_0 ? mem_stq_e_0_bits_uop_flush_on_commit : _lcam_uop_T_flush_on_commit; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_csr_cmd = do_st_search_0 ? mem_stq_e_0_bits_uop_csr_cmd : _lcam_uop_T_csr_cmd; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_ldst_is_rs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst_is_rs1 : _lcam_uop_T_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_ldst = do_st_search_0 ? mem_stq_e_0_bits_uop_ldst : _lcam_uop_T_ldst; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs1 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1 : _lcam_uop_T_lrs1; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs2 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2 : _lcam_uop_T_lrs2; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [5:0] _lcam_uop_T_1_lrs3 = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs3 : _lcam_uop_T_lrs3; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_dst_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_dst_rtype : _lcam_uop_T_dst_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs1_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs1_rtype : _lcam_uop_T_lrs1_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_lrs2_rtype = do_st_search_0 ? mem_stq_e_0_bits_uop_lrs2_rtype : _lcam_uop_T_lrs2_rtype; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_frs3_en = do_st_search_0 ? mem_stq_e_0_bits_uop_frs3_en : _lcam_uop_T_frs3_en; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fcn_dw = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_dw : _lcam_uop_T_fcn_dw; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [4:0] _lcam_uop_T_1_fcn_op = do_st_search_0 ? mem_stq_e_0_bits_uop_fcn_op : _lcam_uop_T_fcn_op; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_fp_val = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_val : _lcam_uop_T_fp_val; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_fp_rm = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_rm : _lcam_uop_T_fp_rm; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [1:0] _lcam_uop_T_1_fp_typ = do_st_search_0 ? mem_stq_e_0_bits_uop_fp_typ : _lcam_uop_T_fp_typ; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_pf_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_pf_if : _lcam_uop_T_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ae_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ae_if : _lcam_uop_T_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_xcpt_ma_if = do_st_search_0 ? mem_stq_e_0_bits_uop_xcpt_ma_if : _lcam_uop_T_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_debug_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_debug_if : _lcam_uop_T_bp_debug_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire _lcam_uop_T_1_bp_xcpt_if = do_st_search_0 ? mem_stq_e_0_bits_uop_bp_xcpt_if : _lcam_uop_T_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_fsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_fsrc : _lcam_uop_T_debug_fsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [2:0] _lcam_uop_T_1_debug_tsrc = do_st_search_0 ? mem_stq_e_0_bits_uop_debug_tsrc : _lcam_uop_T_debug_tsrc; // @[lsu.scala:321:49, :1137:37, :1138:37] wire [31:0] lcam_uop_0_inst = _lcam_uop_T_1_inst; // @[lsu.scala:321:49, :1137:37] wire [31:0] lcam_uop_0_debug_inst = _lcam_uop_T_1_debug_inst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rvc = _lcam_uop_T_1_is_rvc; // @[lsu.scala:321:49, :1137:37] wire [39:0] lcam_uop_0_debug_pc = _lcam_uop_T_1_debug_pc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_0 = _lcam_uop_T_1_iq_type_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_1 = _lcam_uop_T_1_iq_type_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_2 = _lcam_uop_T_1_iq_type_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iq_type_3 = _lcam_uop_T_1_iq_type_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_0 = _lcam_uop_T_1_fu_code_0; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_1 = _lcam_uop_T_1_fu_code_1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_2 = _lcam_uop_T_1_fu_code_2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_3 = _lcam_uop_T_1_fu_code_3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_4 = _lcam_uop_T_1_fu_code_4; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_5 = _lcam_uop_T_1_fu_code_5; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_6 = _lcam_uop_T_1_fu_code_6; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_7 = _lcam_uop_T_1_fu_code_7; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_8 = _lcam_uop_T_1_fu_code_8; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fu_code_9 = _lcam_uop_T_1_fu_code_9; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued = _lcam_uop_T_1_iw_issued; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_agen = _lcam_uop_T_1_iw_issued_partial_agen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_issued_partial_dgen = _lcam_uop_T_1_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_iw_p1_speculative_child = _lcam_uop_T_1_iw_p1_speculative_child; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_iw_p2_speculative_child = _lcam_uop_T_1_iw_p2_speculative_child; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p1_bypass_hint = _lcam_uop_T_1_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p2_bypass_hint = _lcam_uop_T_1_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_iw_p3_bypass_hint = _lcam_uop_T_1_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_dis_col_sel = _lcam_uop_T_1_dis_col_sel; // @[lsu.scala:321:49, :1137:37] wire [15:0] lcam_uop_0_br_mask = _lcam_uop_T_1_br_mask; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_tag = _lcam_uop_T_1_br_tag; // @[lsu.scala:321:49, :1137:37] wire [3:0] lcam_uop_0_br_type = _lcam_uop_T_1_br_type; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfb = _lcam_uop_T_1_is_sfb; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fence = _lcam_uop_T_1_is_fence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_fencei = _lcam_uop_T_1_is_fencei; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sfence = _lcam_uop_T_1_is_sfence; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_amo = _lcam_uop_T_1_is_amo; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_eret = _lcam_uop_T_1_is_eret; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_sys_pc2epc = _lcam_uop_T_1_is_sys_pc2epc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_rocc = _lcam_uop_T_1_is_rocc; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_mov = _lcam_uop_T_1_is_mov; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ftq_idx = _lcam_uop_T_1_ftq_idx; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_edge_inst = _lcam_uop_T_1_edge_inst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_pc_lob = _lcam_uop_T_1_pc_lob; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_taken = _lcam_uop_T_1_taken; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_imm_rename = _lcam_uop_T_1_imm_rename; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_imm_sel = _lcam_uop_T_1_imm_sel; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_pimm = _lcam_uop_T_1_pimm; // @[lsu.scala:321:49, :1137:37] wire [19:0] lcam_uop_0_imm_packed = _lcam_uop_T_1_imm_packed; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_op1_sel = _lcam_uop_T_1_op1_sel; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_op2_sel = _lcam_uop_T_1_op2_sel; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ldst = _lcam_uop_T_1_fp_ctrl_ldst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wen = _lcam_uop_T_1_fp_ctrl_wen; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren1 = _lcam_uop_T_1_fp_ctrl_ren1; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren2 = _lcam_uop_T_1_fp_ctrl_ren2; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_ren3 = _lcam_uop_T_1_fp_ctrl_ren3; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap12 = _lcam_uop_T_1_fp_ctrl_swap12; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_swap23 = _lcam_uop_T_1_fp_ctrl_swap23; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagIn = _lcam_uop_T_1_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_ctrl_typeTagOut = _lcam_uop_T_1_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fromint = _lcam_uop_T_1_fp_ctrl_fromint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_toint = _lcam_uop_T_1_fp_ctrl_toint; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fastpipe = _lcam_uop_T_1_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_fma = _lcam_uop_T_1_fp_ctrl_fma; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_div = _lcam_uop_T_1_fp_ctrl_div; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_sqrt = _lcam_uop_T_1_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_wflags = _lcam_uop_T_1_fp_ctrl_wflags; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_ctrl_vec = _lcam_uop_T_1_fp_ctrl_vec; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_rob_idx = _lcam_uop_T_1_rob_idx; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ldq_idx = _lcam_uop_T_1_ldq_idx; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_stq_idx = _lcam_uop_T_1_stq_idx; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_rxq_idx = _lcam_uop_T_1_rxq_idx; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_pdst = _lcam_uop_T_1_pdst; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs1 = _lcam_uop_T_1_prs1; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs2 = _lcam_uop_T_1_prs2; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_prs3 = _lcam_uop_T_1_prs3; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_ppred = _lcam_uop_T_1_ppred; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs1_busy = _lcam_uop_T_1_prs1_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs2_busy = _lcam_uop_T_1_prs2_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_prs3_busy = _lcam_uop_T_1_prs3_busy; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ppred_busy = _lcam_uop_T_1_ppred_busy; // @[lsu.scala:321:49, :1137:37] wire [6:0] lcam_uop_0_stale_pdst = _lcam_uop_T_1_stale_pdst; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_exception = _lcam_uop_T_1_exception; // @[lsu.scala:321:49, :1137:37] wire [63:0] lcam_uop_0_exc_cause = _lcam_uop_T_1_exc_cause; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_mem_cmd = _lcam_uop_T_1_mem_cmd; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_mem_size = _lcam_uop_T_1_mem_size; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_mem_signed = _lcam_uop_T_1_mem_signed; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_ldq = _lcam_uop_T_1_uses_ldq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_uses_stq = _lcam_uop_T_1_uses_stq; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_is_unique = _lcam_uop_T_1_is_unique; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_flush_on_commit = _lcam_uop_T_1_flush_on_commit; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_csr_cmd = _lcam_uop_T_1_csr_cmd; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_ldst_is_rs1 = _lcam_uop_T_1_ldst_is_rs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_ldst = _lcam_uop_T_1_ldst; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs1 = _lcam_uop_T_1_lrs1; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs2 = _lcam_uop_T_1_lrs2; // @[lsu.scala:321:49, :1137:37] wire [5:0] lcam_uop_0_lrs3 = _lcam_uop_T_1_lrs3; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_dst_rtype = _lcam_uop_T_1_dst_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs1_rtype = _lcam_uop_T_1_lrs1_rtype; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_lrs2_rtype = _lcam_uop_T_1_lrs2_rtype; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_frs3_en = _lcam_uop_T_1_frs3_en; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fcn_dw = _lcam_uop_T_1_fcn_dw; // @[lsu.scala:321:49, :1137:37] wire [4:0] lcam_uop_0_fcn_op = _lcam_uop_T_1_fcn_op; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_fp_val = _lcam_uop_T_1_fp_val; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_fp_rm = _lcam_uop_T_1_fp_rm; // @[lsu.scala:321:49, :1137:37] wire [1:0] lcam_uop_0_fp_typ = _lcam_uop_T_1_fp_typ; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_pf_if = _lcam_uop_T_1_xcpt_pf_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ae_if = _lcam_uop_T_1_xcpt_ae_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_xcpt_ma_if = _lcam_uop_T_1_xcpt_ma_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_debug_if = _lcam_uop_T_1_bp_debug_if; // @[lsu.scala:321:49, :1137:37] wire lcam_uop_0_bp_xcpt_if = _lcam_uop_T_1_bp_xcpt_if; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_fsrc = _lcam_uop_T_1_debug_fsrc; // @[lsu.scala:321:49, :1137:37] wire [2:0] lcam_uop_0_debug_tsrc = _lcam_uop_T_1_debug_tsrc; // @[lsu.scala:321:49, :1137:37] wire [7:0] lcam_mask_mask; // @[lsu.scala:1951:22] wire [7:0] lcam_mask_0 = lcam_mask_mask; // @[lsu.scala:321:49, :1951:22] wire _lcam_mask_mask_T = lcam_uop_0_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _lcam_mask_mask_T_1 = lcam_addr_0[2:0]; // @[lsu.scala:321:49, :1953:55] wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << _lcam_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _lcam_mask_mask_T_3 = lcam_uop_0_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _lcam_mask_mask_T_4 = lcam_addr_0[2:1]; // @[lsu.scala:321:49, :1954:56] wire [2:0] _lcam_mask_mask_T_5 = {_lcam_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << _lcam_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _lcam_mask_mask_T_7 = lcam_uop_0_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _lcam_mask_mask_T_8 = lcam_addr_0[2]; // @[lsu.scala:321:49, :1955:46] wire [7:0] _lcam_mask_mask_T_9 = _lcam_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _lcam_mask_mask_T_10 = &lcam_uop_0_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _lcam_mask_mask_T_12 = _lcam_mask_mask_T_7 ? _lcam_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_13 = _lcam_mask_mask_T_3 ? _lcam_mask_mask_T_6 : {7'h0, _lcam_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _lcam_mask_mask_T_14 = _lcam_mask_mask_T ? _lcam_mask_mask_T_2 : _lcam_mask_mask_T_13; // @[Mux.scala:126:16] assign lcam_mask_mask = _lcam_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] reg [4:0] lcam_ldq_idx_REG; // @[lsu.scala:1146:58] reg [4:0] lcam_ldq_idx_REG_1; // @[lsu.scala:1147:58] wire [4:0] _lcam_ldq_idx_T_1 = fired_load_retry_0 ? lcam_ldq_idx_REG_1 : 5'h0; // @[lsu.scala:321:49, :1147:{26,58}] wire [4:0] _lcam_ldq_idx_T_2 = fired_load_wakeup_0 ? lcam_ldq_idx_REG : _lcam_ldq_idx_T_1; // @[lsu.scala:321:49, :1146:{26,58}, :1147:26] wire [4:0] _lcam_ldq_idx_T_3 = _lcam_ldq_idx_T ? mem_incoming_uop_0_ldq_idx : _lcam_ldq_idx_T_2; // @[lsu.scala:1053:37, :1144:{26,51}, :1146:26] wire [4:0] lcam_ldq_idx_0 = _lcam_ldq_idx_T_3; // @[lsu.scala:321:49, :1144:26] wire [4:0] _wb_ldst_forward_e_e_valid_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_uop_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_executed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_succeeded_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_order_fail_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_observed_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_forward_std_val_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] wire [4:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T = lcam_ldq_idx_0; // @[lsu.scala:321:49] reg [4:0] lcam_stq_idx_REG; // @[lsu.scala:1150:56] wire [4:0] _lcam_stq_idx_T = fired_store_retry_0 ? lcam_stq_idx_REG : 5'h0; // @[lsu.scala:321:49, :1150:{26,56}] wire [4:0] _lcam_stq_idx_T_1 = fired_store_agen_0 ? mem_incoming_uop_0_stq_idx : _lcam_stq_idx_T; // @[lsu.scala:321:49, :1053:37, :1149:26, :1150:26] wire [4:0] lcam_stq_idx_0 = _lcam_stq_idx_T_1; // @[lsu.scala:321:49, :1149:26] wire [31:0] _lcam_younger_load_mask_hi_mask_T = 32'h1 << lcam_ldq_idx_0; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_hi_mask_T_1 = _lcam_younger_load_mask_hi_mask_T[23:0]; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_hi_mask_T_2 = _lcam_younger_load_mask_hi_mask_T_1; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_3 = {1'h0, _lcam_younger_load_mask_hi_mask_T_1[23:1]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_4 = {2'h0, _lcam_younger_load_mask_hi_mask_T_1[23:2]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_5 = {3'h0, _lcam_younger_load_mask_hi_mask_T_1[23:3]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_6 = {4'h0, _lcam_younger_load_mask_hi_mask_T_1[23:4]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_7 = {5'h0, _lcam_younger_load_mask_hi_mask_T_1[23:5]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_8 = {6'h0, _lcam_younger_load_mask_hi_mask_T_1[23:6]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_9 = {7'h0, _lcam_younger_load_mask_hi_mask_T_1[23:7]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_10 = {8'h0, _lcam_younger_load_mask_hi_mask_T_1[23:8]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_11 = {9'h0, _lcam_younger_load_mask_hi_mask_T_1[23:9]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_12 = {10'h0, _lcam_younger_load_mask_hi_mask_T_1[23:10]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_13 = {11'h0, _lcam_younger_load_mask_hi_mask_T_1[23:11]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_14 = {12'h0, _lcam_younger_load_mask_hi_mask_T_1[23:12]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_15 = {13'h0, _lcam_younger_load_mask_hi_mask_T_1[23:13]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_16 = {14'h0, _lcam_younger_load_mask_hi_mask_T_1[23:14]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_17 = {15'h0, _lcam_younger_load_mask_hi_mask_T_1[23:15]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_18 = {16'h0, _lcam_younger_load_mask_hi_mask_T_1[23:16]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_19 = {17'h0, _lcam_younger_load_mask_hi_mask_T_1[23:17]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_20 = {18'h0, _lcam_younger_load_mask_hi_mask_T_1[23:18]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_21 = {19'h0, _lcam_younger_load_mask_hi_mask_T_1[23:19]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_22 = {20'h0, _lcam_younger_load_mask_hi_mask_T_1[23:20]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_23 = {21'h0, _lcam_younger_load_mask_hi_mask_T_1[23:21]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_24 = {22'h0, _lcam_younger_load_mask_hi_mask_T_1[23:22]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_25 = {23'h0, _lcam_younger_load_mask_hi_mask_T_1[23]}; // @[util.scala:370:41, :383:29] wire [23:0] _lcam_younger_load_mask_hi_mask_T_26 = _lcam_younger_load_mask_hi_mask_T_2 | _lcam_younger_load_mask_hi_mask_T_3; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_27 = _lcam_younger_load_mask_hi_mask_T_26 | _lcam_younger_load_mask_hi_mask_T_4; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_28 = _lcam_younger_load_mask_hi_mask_T_27 | _lcam_younger_load_mask_hi_mask_T_5; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_29 = _lcam_younger_load_mask_hi_mask_T_28 | _lcam_younger_load_mask_hi_mask_T_6; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_30 = _lcam_younger_load_mask_hi_mask_T_29 | _lcam_younger_load_mask_hi_mask_T_7; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_31 = _lcam_younger_load_mask_hi_mask_T_30 | _lcam_younger_load_mask_hi_mask_T_8; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_32 = _lcam_younger_load_mask_hi_mask_T_31 | _lcam_younger_load_mask_hi_mask_T_9; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_33 = _lcam_younger_load_mask_hi_mask_T_32 | _lcam_younger_load_mask_hi_mask_T_10; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_34 = _lcam_younger_load_mask_hi_mask_T_33 | _lcam_younger_load_mask_hi_mask_T_11; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_35 = _lcam_younger_load_mask_hi_mask_T_34 | _lcam_younger_load_mask_hi_mask_T_12; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_36 = _lcam_younger_load_mask_hi_mask_T_35 | _lcam_younger_load_mask_hi_mask_T_13; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_37 = _lcam_younger_load_mask_hi_mask_T_36 | _lcam_younger_load_mask_hi_mask_T_14; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_38 = _lcam_younger_load_mask_hi_mask_T_37 | _lcam_younger_load_mask_hi_mask_T_15; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_39 = _lcam_younger_load_mask_hi_mask_T_38 | _lcam_younger_load_mask_hi_mask_T_16; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_40 = _lcam_younger_load_mask_hi_mask_T_39 | _lcam_younger_load_mask_hi_mask_T_17; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_41 = _lcam_younger_load_mask_hi_mask_T_40 | _lcam_younger_load_mask_hi_mask_T_18; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_42 = _lcam_younger_load_mask_hi_mask_T_41 | _lcam_younger_load_mask_hi_mask_T_19; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_43 = _lcam_younger_load_mask_hi_mask_T_42 | _lcam_younger_load_mask_hi_mask_T_20; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_44 = _lcam_younger_load_mask_hi_mask_T_43 | _lcam_younger_load_mask_hi_mask_T_21; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_45 = _lcam_younger_load_mask_hi_mask_T_44 | _lcam_younger_load_mask_hi_mask_T_22; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_46 = _lcam_younger_load_mask_hi_mask_T_45 | _lcam_younger_load_mask_hi_mask_T_23; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_47 = _lcam_younger_load_mask_hi_mask_T_46 | _lcam_younger_load_mask_hi_mask_T_24; // @[util.scala:383:{29,45}] wire [23:0] _lcam_younger_load_mask_hi_mask_T_48 = _lcam_younger_load_mask_hi_mask_T_47 | _lcam_younger_load_mask_hi_mask_T_25; // @[util.scala:383:{29,45}] wire [23:0] lcam_younger_load_mask_hi_mask = ~_lcam_younger_load_mask_hi_mask_T_48; // @[util.scala:370:19, :383:45] wire [31:0] _lcam_younger_load_mask_lo_mask_T = 32'h1 << ldq_head; // @[OneHot.scala:58:35] wire [23:0] _lcam_younger_load_mask_lo_mask_T_1 = _lcam_younger_load_mask_lo_mask_T[23:0]; // @[OneHot.scala:58:35] wire [24:0] _lcam_younger_load_mask_lo_mask_T_2 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_3 = _lcam_younger_load_mask_lo_mask_T_2[23:0]; // @[util.scala:394:{30,37}] wire [24:0] _lcam_younger_load_mask_lo_mask_T_4 = {_lcam_younger_load_mask_lo_mask_T_1, 1'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_5 = _lcam_younger_load_mask_lo_mask_T_4[23:0]; // @[util.scala:394:{30,37}] wire [26:0] _lcam_younger_load_mask_lo_mask_T_6 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 2'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_7 = _lcam_younger_load_mask_lo_mask_T_6[23:0]; // @[util.scala:394:{30,37}] wire [26:0] _lcam_younger_load_mask_lo_mask_T_8 = {_lcam_younger_load_mask_lo_mask_T_1, 3'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_9 = _lcam_younger_load_mask_lo_mask_T_8[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_10 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 4'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_11 = _lcam_younger_load_mask_lo_mask_T_10[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_12 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 5'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_13 = _lcam_younger_load_mask_lo_mask_T_12[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_14 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 6'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_15 = _lcam_younger_load_mask_lo_mask_T_14[23:0]; // @[util.scala:394:{30,37}] wire [30:0] _lcam_younger_load_mask_lo_mask_T_16 = {_lcam_younger_load_mask_lo_mask_T_1, 7'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_17 = _lcam_younger_load_mask_lo_mask_T_16[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_18 = {7'h0, _lcam_younger_load_mask_lo_mask_T_1, 8'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_19 = _lcam_younger_load_mask_lo_mask_T_18[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_20 = {6'h0, _lcam_younger_load_mask_lo_mask_T_1, 9'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_21 = _lcam_younger_load_mask_lo_mask_T_20[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_22 = {5'h0, _lcam_younger_load_mask_lo_mask_T_1, 10'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_23 = _lcam_younger_load_mask_lo_mask_T_22[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_24 = {4'h0, _lcam_younger_load_mask_lo_mask_T_1, 11'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_25 = _lcam_younger_load_mask_lo_mask_T_24[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_26 = {3'h0, _lcam_younger_load_mask_lo_mask_T_1, 12'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_27 = _lcam_younger_load_mask_lo_mask_T_26[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_28 = {2'h0, _lcam_younger_load_mask_lo_mask_T_1, 13'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_29 = _lcam_younger_load_mask_lo_mask_T_28[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_30 = {1'h0, _lcam_younger_load_mask_lo_mask_T_1, 14'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_31 = _lcam_younger_load_mask_lo_mask_T_30[23:0]; // @[util.scala:394:{30,37}] wire [38:0] _lcam_younger_load_mask_lo_mask_T_32 = {_lcam_younger_load_mask_lo_mask_T_1, 15'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_33 = _lcam_younger_load_mask_lo_mask_T_32[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_34 = {15'h0, _lcam_younger_load_mask_lo_mask_T_1, 16'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_35 = _lcam_younger_load_mask_lo_mask_T_34[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_36 = {14'h0, _lcam_younger_load_mask_lo_mask_T_1, 17'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_37 = _lcam_younger_load_mask_lo_mask_T_36[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_38 = {13'h0, _lcam_younger_load_mask_lo_mask_T_1, 18'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_39 = _lcam_younger_load_mask_lo_mask_T_38[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_40 = {12'h0, _lcam_younger_load_mask_lo_mask_T_1, 19'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_41 = _lcam_younger_load_mask_lo_mask_T_40[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_42 = {11'h0, _lcam_younger_load_mask_lo_mask_T_1, 20'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_43 = _lcam_younger_load_mask_lo_mask_T_42[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_44 = {10'h0, _lcam_younger_load_mask_lo_mask_T_1, 21'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_45 = _lcam_younger_load_mask_lo_mask_T_44[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_46 = {9'h0, _lcam_younger_load_mask_lo_mask_T_1, 22'h0}; // @[util.scala:371:44, :383:29, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_47 = _lcam_younger_load_mask_lo_mask_T_46[23:0]; // @[util.scala:394:{30,37}] wire [54:0] _lcam_younger_load_mask_lo_mask_T_48 = {8'h0, _lcam_younger_load_mask_lo_mask_T_1, 23'h0}; // @[util.scala:371:44, :394:30] wire [23:0] _lcam_younger_load_mask_lo_mask_T_49 = _lcam_younger_load_mask_lo_mask_T_48[23:0]; // @[util.scala:394:{30,37}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_50 = _lcam_younger_load_mask_lo_mask_T_3 | _lcam_younger_load_mask_lo_mask_T_5; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_51 = _lcam_younger_load_mask_lo_mask_T_50 | _lcam_younger_load_mask_lo_mask_T_7; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_52 = _lcam_younger_load_mask_lo_mask_T_51 | _lcam_younger_load_mask_lo_mask_T_9; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_53 = _lcam_younger_load_mask_lo_mask_T_52 | _lcam_younger_load_mask_lo_mask_T_11; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_54 = _lcam_younger_load_mask_lo_mask_T_53 | _lcam_younger_load_mask_lo_mask_T_13; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_55 = _lcam_younger_load_mask_lo_mask_T_54 | _lcam_younger_load_mask_lo_mask_T_15; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_56 = _lcam_younger_load_mask_lo_mask_T_55 | _lcam_younger_load_mask_lo_mask_T_17; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_57 = _lcam_younger_load_mask_lo_mask_T_56 | _lcam_younger_load_mask_lo_mask_T_19; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_58 = _lcam_younger_load_mask_lo_mask_T_57 | _lcam_younger_load_mask_lo_mask_T_21; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_59 = _lcam_younger_load_mask_lo_mask_T_58 | _lcam_younger_load_mask_lo_mask_T_23; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_60 = _lcam_younger_load_mask_lo_mask_T_59 | _lcam_younger_load_mask_lo_mask_T_25; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_61 = _lcam_younger_load_mask_lo_mask_T_60 | _lcam_younger_load_mask_lo_mask_T_27; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_62 = _lcam_younger_load_mask_lo_mask_T_61 | _lcam_younger_load_mask_lo_mask_T_29; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_63 = _lcam_younger_load_mask_lo_mask_T_62 | _lcam_younger_load_mask_lo_mask_T_31; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_64 = _lcam_younger_load_mask_lo_mask_T_63 | _lcam_younger_load_mask_lo_mask_T_33; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_65 = _lcam_younger_load_mask_lo_mask_T_64 | _lcam_younger_load_mask_lo_mask_T_35; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_66 = _lcam_younger_load_mask_lo_mask_T_65 | _lcam_younger_load_mask_lo_mask_T_37; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_67 = _lcam_younger_load_mask_lo_mask_T_66 | _lcam_younger_load_mask_lo_mask_T_39; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_68 = _lcam_younger_load_mask_lo_mask_T_67 | _lcam_younger_load_mask_lo_mask_T_41; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_69 = _lcam_younger_load_mask_lo_mask_T_68 | _lcam_younger_load_mask_lo_mask_T_43; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_70 = _lcam_younger_load_mask_lo_mask_T_69 | _lcam_younger_load_mask_lo_mask_T_45; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_71 = _lcam_younger_load_mask_lo_mask_T_70 | _lcam_younger_load_mask_lo_mask_T_47; // @[util.scala:394:{37,54}] wire [23:0] _lcam_younger_load_mask_lo_mask_T_72 = _lcam_younger_load_mask_lo_mask_T_71 | _lcam_younger_load_mask_lo_mask_T_49; // @[util.scala:394:{37,54}] wire [23:0] lcam_younger_load_mask_lo_mask = ~_lcam_younger_load_mask_lo_mask_T_72; // @[util.scala:371:19, :394:54] wire _lcam_younger_load_mask_T = lcam_ldq_idx_0 < ldq_head; // @[util.scala:372:11] wire [23:0] _lcam_younger_load_mask_T_1 = lcam_younger_load_mask_hi_mask & lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:27] wire [23:0] _lcam_younger_load_mask_T_2 = lcam_younger_load_mask_hi_mask | lcam_younger_load_mask_lo_mask; // @[util.scala:370:19, :371:19, :372:46] wire [23:0] _lcam_younger_load_mask_T_3 = _lcam_younger_load_mask_T ? _lcam_younger_load_mask_T_1 : _lcam_younger_load_mask_T_2; // @[util.scala:372:{8,11,27,46}] wire [23:0] _lcam_younger_load_mask_T_4 = _lcam_younger_load_mask_T_3; // @[util.scala:372:{8,56}] wire [23:0] lcam_younger_load_mask_0 = _lcam_younger_load_mask_T_4; // @[util.scala:372:56] wire _can_forward_T_1 = _can_forward_T | fired_load_retry_0; // @[lsu.scala:321:49, :1154:{58,85}] wire _can_forward_T_2 = ~mem_tlb_uncacheable_0; // @[lsu.scala:1071:41, :1155:5] wire _can_forward_T_3 = ~mem_ldq_wakeup_e_bits_addr_is_uncacheable; // @[lsu.scala:1056:37, :1156:5] wire _can_forward_T_4 = _can_forward_T_1 ? _can_forward_T_2 : _can_forward_T_3; // @[lsu.scala:1154:{38,85}, :1155:5, :1156:5] wire can_forward_0 = _can_forward_T_4; // @[lsu.scala:321:49, :1154:38] wire kill_forward_0; // @[lsu.scala:1159:30] wire [23:0] _ldst_addr_matches_0_T_2; // @[lsu.scala:1344:79] wire [23:0] ldst_addr_matches_0; // @[lsu.scala:1162:34] wire [23:0] _ldst_forward_matches_0_T_2; // @[lsu.scala:1345:82] wire [23:0] ldst_forward_matches_0; // @[lsu.scala:1164:34] wire [23:0] _stld_prs2_matches_0_T_3; // @[lsu.scala:1346:80] wire [23:0] stld_prs2_matches_0; // @[lsu.scala:1166:34] reg s1_executing_loads_0; // @[lsu.scala:1168:35] reg s1_executing_loads_1; // @[lsu.scala:1168:35] reg s1_executing_loads_2; // @[lsu.scala:1168:35] reg s1_executing_loads_3; // @[lsu.scala:1168:35] reg s1_executing_loads_4; // @[lsu.scala:1168:35] reg s1_executing_loads_5; // @[lsu.scala:1168:35] reg s1_executing_loads_6; // @[lsu.scala:1168:35] reg s1_executing_loads_7; // @[lsu.scala:1168:35] reg s1_executing_loads_8; // @[lsu.scala:1168:35] reg s1_executing_loads_9; // @[lsu.scala:1168:35] reg s1_executing_loads_10; // @[lsu.scala:1168:35] reg s1_executing_loads_11; // @[lsu.scala:1168:35] reg s1_executing_loads_12; // @[lsu.scala:1168:35] reg s1_executing_loads_13; // @[lsu.scala:1168:35] reg s1_executing_loads_14; // @[lsu.scala:1168:35] reg s1_executing_loads_15; // @[lsu.scala:1168:35] reg s1_executing_loads_16; // @[lsu.scala:1168:35] reg s1_executing_loads_17; // @[lsu.scala:1168:35] reg s1_executing_loads_18; // @[lsu.scala:1168:35] reg s1_executing_loads_19; // @[lsu.scala:1168:35] reg s1_executing_loads_20; // @[lsu.scala:1168:35] reg s1_executing_loads_21; // @[lsu.scala:1168:35] reg s1_executing_loads_22; // @[lsu.scala:1168:35] reg s1_executing_loads_23; // @[lsu.scala:1168:35] wire s1_set_execute_0; // @[lsu.scala:1169:36] wire s1_set_execute_1; // @[lsu.scala:1169:36] wire s1_set_execute_2; // @[lsu.scala:1169:36] wire s1_set_execute_3; // @[lsu.scala:1169:36] wire s1_set_execute_4; // @[lsu.scala:1169:36] wire s1_set_execute_5; // @[lsu.scala:1169:36] wire s1_set_execute_6; // @[lsu.scala:1169:36] wire s1_set_execute_7; // @[lsu.scala:1169:36] wire s1_set_execute_8; // @[lsu.scala:1169:36] wire s1_set_execute_9; // @[lsu.scala:1169:36] wire s1_set_execute_10; // @[lsu.scala:1169:36] wire s1_set_execute_11; // @[lsu.scala:1169:36] wire s1_set_execute_12; // @[lsu.scala:1169:36] wire s1_set_execute_13; // @[lsu.scala:1169:36] wire s1_set_execute_14; // @[lsu.scala:1169:36] wire s1_set_execute_15; // @[lsu.scala:1169:36] wire s1_set_execute_16; // @[lsu.scala:1169:36] wire s1_set_execute_17; // @[lsu.scala:1169:36] wire s1_set_execute_18; // @[lsu.scala:1169:36] wire s1_set_execute_19; // @[lsu.scala:1169:36] wire s1_set_execute_20; // @[lsu.scala:1169:36] wire s1_set_execute_21; // @[lsu.scala:1169:36] wire s1_set_execute_22; // @[lsu.scala:1169:36] wire s1_set_execute_23; // @[lsu.scala:1169:36] reg [23:0] wb_ldst_forward_matches_0; // @[lsu.scala:1171:41] wire _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1380:100] wire wb_ldst_forward_valid_0; // @[lsu.scala:1172:38] wire [31:0] wb_ldst_forward_e_out_uop_inst = wb_ldst_forward_e_e_bits_uop_inst; // @[util.scala:109:23] wire [31:0] wb_ldst_forward_e_out_uop_debug_inst = wb_ldst_forward_e_e_bits_uop_debug_inst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rvc = wb_ldst_forward_e_e_bits_uop_is_rvc; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_uop_debug_pc = wb_ldst_forward_e_e_bits_uop_debug_pc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_0 = wb_ldst_forward_e_e_bits_uop_iq_type_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_1 = wb_ldst_forward_e_e_bits_uop_iq_type_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_2 = wb_ldst_forward_e_e_bits_uop_iq_type_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iq_type_3 = wb_ldst_forward_e_e_bits_uop_iq_type_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_0 = wb_ldst_forward_e_e_bits_uop_fu_code_0; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_1 = wb_ldst_forward_e_e_bits_uop_fu_code_1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_2 = wb_ldst_forward_e_e_bits_uop_fu_code_2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_3 = wb_ldst_forward_e_e_bits_uop_fu_code_3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_4 = wb_ldst_forward_e_e_bits_uop_fu_code_4; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_5 = wb_ldst_forward_e_e_bits_uop_fu_code_5; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_6 = wb_ldst_forward_e_e_bits_uop_fu_code_6; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_7 = wb_ldst_forward_e_e_bits_uop_fu_code_7; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_8 = wb_ldst_forward_e_e_bits_uop_fu_code_8; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fu_code_9 = wb_ldst_forward_e_e_bits_uop_fu_code_9; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued = wb_ldst_forward_e_e_bits_uop_iw_issued; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_agen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_issued_partial_dgen = wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_iw_p1_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_iw_p2_speculative_child = wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p1_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p2_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_iw_p3_bypass_hint = wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_dis_col_sel = wb_ldst_forward_e_e_bits_uop_dis_col_sel; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_tag = wb_ldst_forward_e_e_bits_uop_br_tag; // @[util.scala:109:23] wire [3:0] wb_ldst_forward_e_out_uop_br_type = wb_ldst_forward_e_e_bits_uop_br_type; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfb = wb_ldst_forward_e_e_bits_uop_is_sfb; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fence = wb_ldst_forward_e_e_bits_uop_is_fence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_fencei = wb_ldst_forward_e_e_bits_uop_is_fencei; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sfence = wb_ldst_forward_e_e_bits_uop_is_sfence; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_amo = wb_ldst_forward_e_e_bits_uop_is_amo; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_eret = wb_ldst_forward_e_e_bits_uop_is_eret; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_sys_pc2epc = wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_rocc = wb_ldst_forward_e_e_bits_uop_is_rocc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_mov = wb_ldst_forward_e_e_bits_uop_is_mov; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ftq_idx = wb_ldst_forward_e_e_bits_uop_ftq_idx; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_edge_inst = wb_ldst_forward_e_e_bits_uop_edge_inst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_pc_lob = wb_ldst_forward_e_e_bits_uop_pc_lob; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_taken = wb_ldst_forward_e_e_bits_uop_taken; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_imm_rename = wb_ldst_forward_e_e_bits_uop_imm_rename; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_imm_sel = wb_ldst_forward_e_e_bits_uop_imm_sel; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_pimm = wb_ldst_forward_e_e_bits_uop_pimm; // @[util.scala:109:23] wire [19:0] wb_ldst_forward_e_out_uop_imm_packed = wb_ldst_forward_e_e_bits_uop_imm_packed; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_op1_sel = wb_ldst_forward_e_e_bits_uop_op1_sel; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_op2_sel = wb_ldst_forward_e_e_bits_uop_op2_sel; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ldst = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wen = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren1 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren2 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_ren3 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap12 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_swap23 = wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fromint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_toint = wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_fma = wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_div = wb_ldst_forward_e_e_bits_uop_fp_ctrl_div; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_sqrt = wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_wflags = wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_ctrl_vec = wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_rob_idx = wb_ldst_forward_e_e_bits_uop_rob_idx; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ldq_idx = wb_ldst_forward_e_e_bits_uop_ldq_idx; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_stq_idx = wb_ldst_forward_e_e_bits_uop_stq_idx; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_rxq_idx = wb_ldst_forward_e_e_bits_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_pdst = wb_ldst_forward_e_e_bits_uop_pdst; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs1 = wb_ldst_forward_e_e_bits_uop_prs1; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs2 = wb_ldst_forward_e_e_bits_uop_prs2; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_prs3 = wb_ldst_forward_e_e_bits_uop_prs3; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_ppred = wb_ldst_forward_e_e_bits_uop_ppred; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs1_busy = wb_ldst_forward_e_e_bits_uop_prs1_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs2_busy = wb_ldst_forward_e_e_bits_uop_prs2_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_prs3_busy = wb_ldst_forward_e_e_bits_uop_prs3_busy; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ppred_busy = wb_ldst_forward_e_e_bits_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] wb_ldst_forward_e_out_uop_stale_pdst = wb_ldst_forward_e_e_bits_uop_stale_pdst; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_exception = wb_ldst_forward_e_e_bits_uop_exception; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_uop_exc_cause = wb_ldst_forward_e_e_bits_uop_exc_cause; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_mem_cmd = wb_ldst_forward_e_e_bits_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_mem_size = wb_ldst_forward_e_e_bits_uop_mem_size; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_mem_signed = wb_ldst_forward_e_e_bits_uop_mem_signed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_ldq = wb_ldst_forward_e_e_bits_uop_uses_ldq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_uses_stq = wb_ldst_forward_e_e_bits_uop_uses_stq; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_is_unique = wb_ldst_forward_e_e_bits_uop_is_unique; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_flush_on_commit = wb_ldst_forward_e_e_bits_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_csr_cmd = wb_ldst_forward_e_e_bits_uop_csr_cmd; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_ldst_is_rs1 = wb_ldst_forward_e_e_bits_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_ldst = wb_ldst_forward_e_e_bits_uop_ldst; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs1 = wb_ldst_forward_e_e_bits_uop_lrs1; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs2 = wb_ldst_forward_e_e_bits_uop_lrs2; // @[util.scala:109:23] wire [5:0] wb_ldst_forward_e_out_uop_lrs3 = wb_ldst_forward_e_e_bits_uop_lrs3; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_dst_rtype = wb_ldst_forward_e_e_bits_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs1_rtype = wb_ldst_forward_e_e_bits_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_lrs2_rtype = wb_ldst_forward_e_e_bits_uop_lrs2_rtype; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_frs3_en = wb_ldst_forward_e_e_bits_uop_frs3_en; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fcn_dw = wb_ldst_forward_e_e_bits_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_uop_fcn_op = wb_ldst_forward_e_e_bits_uop_fcn_op; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_fp_val = wb_ldst_forward_e_e_bits_uop_fp_val; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_fp_rm = wb_ldst_forward_e_e_bits_uop_fp_rm; // @[util.scala:109:23] wire [1:0] wb_ldst_forward_e_out_uop_fp_typ = wb_ldst_forward_e_e_bits_uop_fp_typ; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_pf_if = wb_ldst_forward_e_e_bits_uop_xcpt_pf_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ae_if = wb_ldst_forward_e_e_bits_uop_xcpt_ae_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_xcpt_ma_if = wb_ldst_forward_e_e_bits_uop_xcpt_ma_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_debug_if = wb_ldst_forward_e_e_bits_uop_bp_debug_if; // @[util.scala:109:23] wire wb_ldst_forward_e_out_uop_bp_xcpt_if = wb_ldst_forward_e_e_bits_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_fsrc = wb_ldst_forward_e_e_bits_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] wb_ldst_forward_e_out_uop_debug_tsrc = wb_ldst_forward_e_e_bits_uop_debug_tsrc; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_valid = wb_ldst_forward_e_e_bits_addr_valid; // @[util.scala:109:23] wire [39:0] wb_ldst_forward_e_out_addr_bits = wb_ldst_forward_e_e_bits_addr_bits; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_virtual = wb_ldst_forward_e_e_bits_addr_is_virtual; // @[util.scala:109:23] wire wb_ldst_forward_e_out_addr_is_uncacheable = wb_ldst_forward_e_e_bits_addr_is_uncacheable; // @[util.scala:109:23] wire wb_ldst_forward_e_out_executed = wb_ldst_forward_e_e_bits_executed; // @[util.scala:109:23] wire wb_ldst_forward_e_out_succeeded = wb_ldst_forward_e_e_bits_succeeded; // @[util.scala:109:23] wire wb_ldst_forward_e_out_order_fail = wb_ldst_forward_e_e_bits_order_fail; // @[util.scala:109:23] wire wb_ldst_forward_e_out_observed = wb_ldst_forward_e_e_bits_observed; // @[util.scala:109:23] wire [23:0] wb_ldst_forward_e_out_st_dep_mask = wb_ldst_forward_e_e_bits_st_dep_mask; // @[util.scala:109:23] wire [7:0] wb_ldst_forward_e_out_ld_byte_mask = wb_ldst_forward_e_e_bits_ld_byte_mask; // @[util.scala:109:23] wire wb_ldst_forward_e_out_forward_std_val = wb_ldst_forward_e_e_bits_forward_std_val; // @[util.scala:109:23] wire [4:0] wb_ldst_forward_e_out_forward_stq_idx = wb_ldst_forward_e_e_bits_forward_stq_idx; // @[util.scala:109:23] wire [63:0] wb_ldst_forward_e_out_debug_wb_data = wb_ldst_forward_e_e_bits_debug_wb_data; // @[util.scala:109:23] wire [15:0] wb_ldst_forward_e_e_bits_uop_br_mask; // @[lsu.scala:233:17] wire wb_ldst_forward_e_e_valid; // @[lsu.scala:233:17] wire [4:0] _wb_ldst_forward_e_e_valid_T_1 = _wb_ldst_forward_e_e_valid_T; assign wb_ldst_forward_e_e_valid = _GEN_25[_wb_ldst_forward_e_e_valid_T_1]; // @[lsu.scala:233:17, :234:32, :387:15] wire [4:0] _wb_ldst_forward_e_e_bits_uop_T_1 = _wb_ldst_forward_e_e_bits_uop_T; assign wb_ldst_forward_e_e_bits_uop_inst = _GEN_127[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_inst = _GEN_128[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rvc = _GEN_129[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_pc = _GEN_130[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_0 = _GEN_131[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_1 = _GEN_132[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_2 = _GEN_133[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iq_type_3 = _GEN_134[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_0 = _GEN_135[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_1 = _GEN_136[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_2 = _GEN_137[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_3 = _GEN_138[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_4 = _GEN_139[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_5 = _GEN_140[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_6 = _GEN_141[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_7 = _GEN_142[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_8 = _GEN_143[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fu_code_9 = _GEN_144[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued = _GEN_145[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_agen = _GEN_146[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_issued_partial_dgen = _GEN_147[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_speculative_child = _GEN_148[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_speculative_child = _GEN_149[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p1_bypass_hint = _GEN_150[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p2_bypass_hint = _GEN_151[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_iw_p3_bypass_hint = _GEN_152[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dis_col_sel = _GEN_153[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_mask = _GEN_154[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_tag = _GEN_155[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_br_type = _GEN_156[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfb = _GEN_157[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fence = _GEN_158[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_fencei = _GEN_159[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sfence = _GEN_160[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_amo = _GEN_161[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_eret = _GEN_162[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_sys_pc2epc = _GEN_163[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_rocc = _GEN_164[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_mov = _GEN_165[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ftq_idx = _GEN_166[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_edge_inst = _GEN_167[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pc_lob = _GEN_168[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_taken = _GEN_169[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_rename = _GEN_170[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_sel = _GEN_171[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pimm = _GEN_172[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_imm_packed = _GEN_173[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op1_sel = _GEN_174[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_op2_sel = _GEN_175[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ldst = _GEN_176[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wen = _GEN_177[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren1 = _GEN_178[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren2 = _GEN_179[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_ren3 = _GEN_180[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap12 = _GEN_181[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_swap23 = _GEN_182[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagIn = _GEN_183[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_typeTagOut = _GEN_184[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fromint = _GEN_185[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_toint = _GEN_186[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fastpipe = _GEN_187[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_fma = _GEN_188[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_div = _GEN_189[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_sqrt = _GEN_190[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_wflags = _GEN_191[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_ctrl_vec = _GEN_192[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rob_idx = _GEN_193[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldq_idx = _GEN_194[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stq_idx = _GEN_195[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_rxq_idx = _GEN_196[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_pdst = _GEN_197[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1 = _GEN_198[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2 = _GEN_199[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3 = _GEN_200[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred = _GEN_201[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs1_busy = _GEN_202[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs2_busy = _GEN_203[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_prs3_busy = _GEN_204[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ppred_busy = _GEN_205[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_stale_pdst = _GEN_206[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exception = _GEN_207[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_exc_cause = _GEN_208[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_cmd = _GEN_209[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_size = _GEN_210[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_mem_signed = _GEN_211[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_ldq = _GEN_212[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_uses_stq = _GEN_213[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_is_unique = _GEN_214[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_flush_on_commit = _GEN_215[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_csr_cmd = _GEN_216[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst_is_rs1 = _GEN_217[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_ldst = _GEN_218[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1 = _GEN_219[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2 = _GEN_220[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs3 = _GEN_221[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_dst_rtype = _GEN_222[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs1_rtype = _GEN_223[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_lrs2_rtype = _GEN_224[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_frs3_en = _GEN_225[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_dw = _GEN_226[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fcn_op = _GEN_227[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_val = _GEN_228[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_rm = _GEN_229[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_fp_typ = _GEN_230[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_pf_if = _GEN_231[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ae_if = _GEN_232[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_xcpt_ma_if = _GEN_233[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_debug_if = _GEN_234[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_bp_xcpt_if = _GEN_235[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_fsrc = _GEN_236[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] assign wb_ldst_forward_e_e_bits_uop_debug_tsrc = _GEN_237[_wb_ldst_forward_e_e_bits_uop_T_1]; // @[lsu.scala:233:17, :235:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_T_1 = _wb_ldst_forward_e_e_bits_addr_T; assign wb_ldst_forward_e_e_bits_addr_valid = _GEN_238[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] assign wb_ldst_forward_e_e_bits_addr_bits = _GEN_239[_wb_ldst_forward_e_e_bits_addr_T_1]; // @[lsu.scala:233:17, :236:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_virtual_T_1 = _wb_ldst_forward_e_e_bits_addr_is_virtual_T; assign wb_ldst_forward_e_e_bits_addr_is_virtual = _GEN_240[_wb_ldst_forward_e_e_bits_addr_is_virtual_T_1]; // @[lsu.scala:233:17, :237:32] wire [4:0] _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1 = _wb_ldst_forward_e_e_bits_addr_is_uncacheable_T; assign wb_ldst_forward_e_e_bits_addr_is_uncacheable = _GEN_241[_wb_ldst_forward_e_e_bits_addr_is_uncacheable_T_1]; // @[lsu.scala:233:17, :238:32] wire [4:0] _wb_ldst_forward_e_e_bits_executed_T_1 = _wb_ldst_forward_e_e_bits_executed_T; assign wb_ldst_forward_e_e_bits_executed = _GEN_242[_wb_ldst_forward_e_e_bits_executed_T_1]; // @[lsu.scala:233:17, :239:32] wire [4:0] _wb_ldst_forward_e_e_bits_succeeded_T_1 = _wb_ldst_forward_e_e_bits_succeeded_T; assign wb_ldst_forward_e_e_bits_succeeded = _GEN_243[_wb_ldst_forward_e_e_bits_succeeded_T_1]; // @[lsu.scala:233:17, :240:32] wire [4:0] _wb_ldst_forward_e_e_bits_order_fail_T_1 = _wb_ldst_forward_e_e_bits_order_fail_T; assign wb_ldst_forward_e_e_bits_order_fail = _GEN_244[_wb_ldst_forward_e_e_bits_order_fail_T_1]; // @[lsu.scala:233:17, :241:32] wire [4:0] _wb_ldst_forward_e_e_bits_observed_T_1 = _wb_ldst_forward_e_e_bits_observed_T; assign wb_ldst_forward_e_e_bits_observed = _GEN_245[_wb_ldst_forward_e_e_bits_observed_T_1]; // @[lsu.scala:233:17, :242:32] wire [4:0] _wb_ldst_forward_e_e_bits_st_dep_mask_T_1 = _wb_ldst_forward_e_e_bits_st_dep_mask_T; assign wb_ldst_forward_e_e_bits_st_dep_mask = _GEN_246[_wb_ldst_forward_e_e_bits_st_dep_mask_T_1]; // @[lsu.scala:233:17, :243:32] wire [4:0] _wb_ldst_forward_e_e_bits_ld_byte_mask_T_1 = _wb_ldst_forward_e_e_bits_ld_byte_mask_T; assign wb_ldst_forward_e_e_bits_ld_byte_mask = _GEN_247[_wb_ldst_forward_e_e_bits_ld_byte_mask_T_1]; // @[lsu.scala:233:17, :244:32] wire [4:0] _wb_ldst_forward_e_e_bits_forward_std_val_T_1 = _wb_ldst_forward_e_e_bits_forward_std_val_T; assign wb_ldst_forward_e_e_bits_forward_std_val = _GEN_248[_wb_ldst_forward_e_e_bits_forward_std_val_T_1]; // @[lsu.scala:233:17, :245:32] wire [4:0] _wb_ldst_forward_e_e_bits_forward_stq_idx_T_1 = _wb_ldst_forward_e_e_bits_forward_stq_idx_T; assign wb_ldst_forward_e_e_bits_forward_stq_idx = _GEN_249[_wb_ldst_forward_e_e_bits_forward_stq_idx_T_1]; // @[lsu.scala:233:17, :246:32] wire [4:0] _wb_ldst_forward_e_e_bits_debug_wb_data_T_1 = _wb_ldst_forward_e_e_bits_debug_wb_data_T; assign wb_ldst_forward_e_e_bits_debug_wb_data = _GEN_250[_wb_ldst_forward_e_e_bits_debug_wb_data_T_1]; // @[lsu.scala:233:17, :247:32] wire [15:0] _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] wb_ldst_forward_e_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _wb_ldst_forward_e_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _wb_ldst_forward_e_out_uop_br_mask_T_1 = wb_ldst_forward_e_e_bits_uop_br_mask & _wb_ldst_forward_e_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign wb_ldst_forward_e_out_uop_br_mask = _wb_ldst_forward_e_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg [31:0] wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_inst = wb_ldst_forward_e_REG_uop_inst; // @[lsu.scala:321:49, :1173:55] reg [31:0] wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:1173:55] wire [31:0] wb_ldst_forward_e_0_uop_debug_inst = wb_ldst_forward_e_REG_uop_debug_inst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rvc = wb_ldst_forward_e_REG_uop_is_rvc; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_uop_debug_pc = wb_ldst_forward_e_REG_uop_debug_pc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_0 = wb_ldst_forward_e_REG_uop_iq_type_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_1 = wb_ldst_forward_e_REG_uop_iq_type_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_2 = wb_ldst_forward_e_REG_uop_iq_type_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iq_type_3 = wb_ldst_forward_e_REG_uop_iq_type_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_0 = wb_ldst_forward_e_REG_uop_fu_code_0; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_1 = wb_ldst_forward_e_REG_uop_fu_code_1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_2 = wb_ldst_forward_e_REG_uop_fu_code_2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_3 = wb_ldst_forward_e_REG_uop_fu_code_3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_4 = wb_ldst_forward_e_REG_uop_fu_code_4; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_5 = wb_ldst_forward_e_REG_uop_fu_code_5; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_6 = wb_ldst_forward_e_REG_uop_fu_code_6; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_7 = wb_ldst_forward_e_REG_uop_fu_code_7; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_8 = wb_ldst_forward_e_REG_uop_fu_code_8; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fu_code_9 = wb_ldst_forward_e_REG_uop_fu_code_9; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued = wb_ldst_forward_e_REG_uop_iw_issued; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_agen = wb_ldst_forward_e_REG_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_issued_partial_dgen = wb_ldst_forward_e_REG_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_iw_p1_speculative_child = wb_ldst_forward_e_REG_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_iw_p2_speculative_child = wb_ldst_forward_e_REG_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p1_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p2_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_iw_p3_bypass_hint = wb_ldst_forward_e_REG_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_dis_col_sel = wb_ldst_forward_e_REG_uop_dis_col_sel; // @[lsu.scala:321:49, :1173:55] reg [15:0] wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:1173:55] wire [15:0] wb_ldst_forward_e_0_uop_br_mask = wb_ldst_forward_e_REG_uop_br_mask; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_tag = wb_ldst_forward_e_REG_uop_br_tag; // @[lsu.scala:321:49, :1173:55] reg [3:0] wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:1173:55] wire [3:0] wb_ldst_forward_e_0_uop_br_type = wb_ldst_forward_e_REG_uop_br_type; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfb = wb_ldst_forward_e_REG_uop_is_sfb; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fence = wb_ldst_forward_e_REG_uop_is_fence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_fencei = wb_ldst_forward_e_REG_uop_is_fencei; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sfence = wb_ldst_forward_e_REG_uop_is_sfence; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_amo = wb_ldst_forward_e_REG_uop_is_amo; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_eret = wb_ldst_forward_e_REG_uop_is_eret; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_sys_pc2epc = wb_ldst_forward_e_REG_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_rocc = wb_ldst_forward_e_REG_uop_is_rocc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_mov = wb_ldst_forward_e_REG_uop_is_mov; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ftq_idx = wb_ldst_forward_e_REG_uop_ftq_idx; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_edge_inst = wb_ldst_forward_e_REG_uop_edge_inst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_pc_lob = wb_ldst_forward_e_REG_uop_pc_lob; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_taken = wb_ldst_forward_e_REG_uop_taken; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_imm_rename = wb_ldst_forward_e_REG_uop_imm_rename; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_imm_sel = wb_ldst_forward_e_REG_uop_imm_sel; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_pimm = wb_ldst_forward_e_REG_uop_pimm; // @[lsu.scala:321:49, :1173:55] reg [19:0] wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:1173:55] wire [19:0] wb_ldst_forward_e_0_uop_imm_packed = wb_ldst_forward_e_REG_uop_imm_packed; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_op1_sel = wb_ldst_forward_e_REG_uop_op1_sel; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_op2_sel = wb_ldst_forward_e_REG_uop_op2_sel; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ldst = wb_ldst_forward_e_REG_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wen = wb_ldst_forward_e_REG_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren1 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren2 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_ren3 = wb_ldst_forward_e_REG_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap12 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_swap23 = wb_ldst_forward_e_REG_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut = wb_ldst_forward_e_REG_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fromint = wb_ldst_forward_e_REG_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_toint = wb_ldst_forward_e_REG_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe = wb_ldst_forward_e_REG_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_fma = wb_ldst_forward_e_REG_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_div = wb_ldst_forward_e_REG_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_sqrt = wb_ldst_forward_e_REG_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_wflags = wb_ldst_forward_e_REG_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_ctrl_vec = wb_ldst_forward_e_REG_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_rob_idx = wb_ldst_forward_e_REG_uop_rob_idx; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ldq_idx = wb_ldst_forward_e_REG_uop_ldq_idx; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_stq_idx = wb_ldst_forward_e_REG_uop_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_rxq_idx = wb_ldst_forward_e_REG_uop_rxq_idx; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_pdst = wb_ldst_forward_e_REG_uop_pdst; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs1 = wb_ldst_forward_e_REG_uop_prs1; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs2 = wb_ldst_forward_e_REG_uop_prs2; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_prs3 = wb_ldst_forward_e_REG_uop_prs3; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_ppred = wb_ldst_forward_e_REG_uop_ppred; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs1_busy = wb_ldst_forward_e_REG_uop_prs1_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs2_busy = wb_ldst_forward_e_REG_uop_prs2_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_prs3_busy = wb_ldst_forward_e_REG_uop_prs3_busy; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ppred_busy = wb_ldst_forward_e_REG_uop_ppred_busy; // @[lsu.scala:321:49, :1173:55] reg [6:0] wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:1173:55] wire [6:0] wb_ldst_forward_e_0_uop_stale_pdst = wb_ldst_forward_e_REG_uop_stale_pdst; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_exception = wb_ldst_forward_e_REG_uop_exception; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_uop_exc_cause = wb_ldst_forward_e_REG_uop_exc_cause; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_mem_cmd = wb_ldst_forward_e_REG_uop_mem_cmd; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_mem_size = wb_ldst_forward_e_REG_uop_mem_size; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_mem_signed = wb_ldst_forward_e_REG_uop_mem_signed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_ldq = wb_ldst_forward_e_REG_uop_uses_ldq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_uses_stq = wb_ldst_forward_e_REG_uop_uses_stq; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_is_unique = wb_ldst_forward_e_REG_uop_is_unique; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_flush_on_commit = wb_ldst_forward_e_REG_uop_flush_on_commit; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_csr_cmd = wb_ldst_forward_e_REG_uop_csr_cmd; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_ldst_is_rs1 = wb_ldst_forward_e_REG_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_ldst = wb_ldst_forward_e_REG_uop_ldst; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs1 = wb_ldst_forward_e_REG_uop_lrs1; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs2 = wb_ldst_forward_e_REG_uop_lrs2; // @[lsu.scala:321:49, :1173:55] reg [5:0] wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:1173:55] wire [5:0] wb_ldst_forward_e_0_uop_lrs3 = wb_ldst_forward_e_REG_uop_lrs3; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_dst_rtype = wb_ldst_forward_e_REG_uop_dst_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs1_rtype = wb_ldst_forward_e_REG_uop_lrs1_rtype; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_lrs2_rtype = wb_ldst_forward_e_REG_uop_lrs2_rtype; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_frs3_en = wb_ldst_forward_e_REG_uop_frs3_en; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fcn_dw = wb_ldst_forward_e_REG_uop_fcn_dw; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_uop_fcn_op = wb_ldst_forward_e_REG_uop_fcn_op; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_fp_val = wb_ldst_forward_e_REG_uop_fp_val; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_fp_rm = wb_ldst_forward_e_REG_uop_fp_rm; // @[lsu.scala:321:49, :1173:55] reg [1:0] wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:1173:55] wire [1:0] wb_ldst_forward_e_0_uop_fp_typ = wb_ldst_forward_e_REG_uop_fp_typ; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_pf_if = wb_ldst_forward_e_REG_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ae_if = wb_ldst_forward_e_REG_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_xcpt_ma_if = wb_ldst_forward_e_REG_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_debug_if = wb_ldst_forward_e_REG_uop_bp_debug_if; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_uop_bp_xcpt_if = wb_ldst_forward_e_REG_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_fsrc = wb_ldst_forward_e_REG_uop_debug_fsrc; // @[lsu.scala:321:49, :1173:55] reg [2:0] wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:1173:55] wire [2:0] wb_ldst_forward_e_0_uop_debug_tsrc = wb_ldst_forward_e_REG_uop_debug_tsrc; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_valid = wb_ldst_forward_e_REG_addr_valid; // @[lsu.scala:321:49, :1173:55] reg [39:0] wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:1173:55] wire [39:0] wb_ldst_forward_e_0_addr_bits = wb_ldst_forward_e_REG_addr_bits; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_virtual = wb_ldst_forward_e_REG_addr_is_virtual; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_addr_is_uncacheable = wb_ldst_forward_e_REG_addr_is_uncacheable; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_executed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_executed = wb_ldst_forward_e_REG_executed; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_succeeded = wb_ldst_forward_e_REG_succeeded; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_order_fail = wb_ldst_forward_e_REG_order_fail; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_observed; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_observed = wb_ldst_forward_e_REG_observed; // @[lsu.scala:321:49, :1173:55] reg [23:0] wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:1173:55] wire [23:0] wb_ldst_forward_e_0_st_dep_mask = wb_ldst_forward_e_REG_st_dep_mask; // @[lsu.scala:321:49, :1173:55] reg [7:0] wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:1173:55] wire [7:0] wb_ldst_forward_e_0_ld_byte_mask = wb_ldst_forward_e_REG_ld_byte_mask; // @[lsu.scala:321:49, :1173:55] reg wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:1173:55] wire wb_ldst_forward_e_0_forward_std_val = wb_ldst_forward_e_REG_forward_std_val; // @[lsu.scala:321:49, :1173:55] reg [4:0] wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:1173:55] wire [4:0] wb_ldst_forward_e_0_forward_stq_idx = wb_ldst_forward_e_REG_forward_stq_idx; // @[lsu.scala:321:49, :1173:55] reg [63:0] wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:1173:55] wire [63:0] wb_ldst_forward_e_0_debug_wb_data = wb_ldst_forward_e_REG_debug_wb_data; // @[lsu.scala:321:49, :1173:55] wire [1:0] size_1 = wb_ldst_forward_e_0_uop_mem_size; // @[AMOALU.scala:11:18] reg [4:0] wb_ldst_forward_ldq_idx_0; // @[lsu.scala:1174:41] reg [39:0] wb_ldst_forward_ld_addr_0; // @[lsu.scala:1175:41] wire [4:0] wb_ldst_forward_stq_idx_0; // @[lsu.scala:1176:38] wire failed_load; // @[lsu.scala:1178:29] wire [33:0] _block_addr_matches_T = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_3 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_6 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_9 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_12 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_15 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_18 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_21 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_24 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_27 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_30 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_33 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_36 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_39 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_42 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_45 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_48 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_51 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_54 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_57 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_60 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_63 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_66 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_69 = lcam_addr_0[39:6]; // @[lsu.scala:321:49, :1195:57] wire [33:0] _block_addr_matches_T_1 = ldq_addr_0_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_2 = _block_addr_matches_T == _block_addr_matches_T_1; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_0 = _block_addr_matches_T_2; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_4 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_8 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_12 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_16 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_20 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_24 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_28 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_32 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_36 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_40 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_44 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_48 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_52 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_56 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_60 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_64 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_68 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_72 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_76 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_80 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_84 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_88 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_92 = lcam_addr_0[5:3]; // @[lsu.scala:321:49, :1196:81] wire [2:0] _dword_addr_matches_T_1 = ldq_addr_0_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_2 = _dword_addr_matches_T == _dword_addr_matches_T_1; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_3 = block_addr_matches_0 & _dword_addr_matches_T_2; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_0 = _dword_addr_matches_T_3; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_480 = ldq_ld_byte_mask_0 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T; // @[lsu.scala:1197:46] assign _mask_match_T = _GEN_480; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T; // @[lsu.scala:1198:46] assign _mask_overlap_T = _GEN_480; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_1 = _mask_match_T == ldq_ld_byte_mask_0; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_0 = _mask_match_T_1; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_1 = |_mask_overlap_T; // @[lsu.scala:1198:{46,62}] wire mask_overlap_0 = _mask_overlap_T_1; // @[lsu.scala:321:49, :1198:62] wire _T_374 = ldq_executed_0 | ldq_succeeded_0; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _GEN_481 = {19'h0, lcam_stq_idx_0}; // @[util.scala:383:29] wire [23:0] _T_350 = ldq_st_dep_mask_0 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_354 = do_st_search_0 & ldq_valid_0 & ldq_addr_0_valid & _T_374 & ~ldq_addr_is_virtual_0 & _T_350[0] & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T = ldq_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_1 = ldq_forward_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_2 = _forwarded_is_older_T ^ _forwarded_is_older_T_1; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_3 = lcam_stq_idx_0 < l_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older = _forwarded_is_older_T_2 ^ _forwarded_is_older_T_3; // @[util.scala:364:{58,72,78}] wire _T_358 = ~ldq_forward_std_val_0 | ldq_forward_stq_idx_0 != lcam_stq_idx_0 & forwarded_is_older; // @[util.scala:364:72] wire _GEN_482 = _T_354 & _T_358; // @[lsu.scala:1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76] wire _T_364 = do_ld_search_0 & ldq_valid_0 & ldq_addr_0_valid & ~ldq_addr_is_virtual_0 & dword_addr_matches_0 & mask_overlap_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older = lcam_younger_load_mask_0[0]; // @[lsu.scala:321:49, :1237:58] wire _T_383 = ldq_executed_0 & (ldq_succeeded_0 | ldq_will_succeed_0); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_483 = lcam_ldq_idx_0 == 5'h0; // @[lsu.scala:321:49, :1254:48] wire _GEN_484 = lcam_ldq_idx_0 == 5'h1; // @[lsu.scala:321:49, :1254:48] wire _GEN_485 = lcam_ldq_idx_0 == 5'h2; // @[lsu.scala:321:49, :1254:48] wire _GEN_486 = lcam_ldq_idx_0 == 5'h3; // @[lsu.scala:321:49, :1254:48] wire _GEN_487 = lcam_ldq_idx_0 == 5'h4; // @[lsu.scala:321:49, :1254:48] wire _GEN_488 = lcam_ldq_idx_0 == 5'h5; // @[lsu.scala:321:49, :1254:48] wire _GEN_489 = lcam_ldq_idx_0 == 5'h6; // @[lsu.scala:321:49, :1254:48] wire _GEN_490 = lcam_ldq_idx_0 == 5'h7; // @[lsu.scala:321:49, :1254:48] wire _GEN_491 = lcam_ldq_idx_0 == 5'h8; // @[lsu.scala:321:49, :1254:48] wire _GEN_492 = lcam_ldq_idx_0 == 5'h9; // @[lsu.scala:321:49, :1254:48] wire _GEN_493 = lcam_ldq_idx_0 == 5'hA; // @[lsu.scala:321:49, :1254:48] wire _GEN_494 = lcam_ldq_idx_0 == 5'hB; // @[lsu.scala:321:49, :1254:48] wire _GEN_495 = lcam_ldq_idx_0 == 5'hC; // @[lsu.scala:321:49, :1254:48] wire _GEN_496 = lcam_ldq_idx_0 == 5'hD; // @[lsu.scala:321:49, :1254:48] wire _GEN_497 = lcam_ldq_idx_0 == 5'hE; // @[lsu.scala:321:49, :1254:48] wire _GEN_498 = lcam_ldq_idx_0 == 5'hF; // @[lsu.scala:321:49, :1254:48] wire _GEN_499 = lcam_ldq_idx_0 == 5'h10; // @[lsu.scala:321:49, :1254:48] wire _GEN_500 = lcam_ldq_idx_0 == 5'h11; // @[lsu.scala:321:49, :1254:48] wire _GEN_501 = lcam_ldq_idx_0 == 5'h12; // @[lsu.scala:321:49, :1254:48] wire _GEN_502 = lcam_ldq_idx_0 == 5'h13; // @[lsu.scala:321:49, :1254:48] wire _GEN_503 = lcam_ldq_idx_0 == 5'h14; // @[lsu.scala:321:49, :1254:48] wire _GEN_504 = lcam_ldq_idx_0 == 5'h15; // @[lsu.scala:321:49, :1254:48] wire _GEN_505 = lcam_ldq_idx_0 == 5'h16; // @[lsu.scala:321:49, :1254:48] wire _GEN_506 = lcam_ldq_idx_0 == 5'h17; // @[lsu.scala:321:49, :1254:48] reg REG_1; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_4 = ldq_addr_1_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_5 = _block_addr_matches_T_3 == _block_addr_matches_T_4; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_1_0 = _block_addr_matches_T_5; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_5 = ldq_addr_1_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_6 = _dword_addr_matches_T_4 == _dword_addr_matches_T_5; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_7 = block_addr_matches_1_0 & _dword_addr_matches_T_6; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_1_0 = _dword_addr_matches_T_7; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_507 = ldq_ld_byte_mask_1 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_2; // @[lsu.scala:1197:46] assign _mask_match_T_2 = _GEN_507; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_2; // @[lsu.scala:1198:46] assign _mask_overlap_T_2 = _GEN_507; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_3 = _mask_match_T_2 == ldq_ld_byte_mask_1; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_1_0 = _mask_match_T_3; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_3 = |_mask_overlap_T_2; // @[lsu.scala:1198:{46,62}] wire mask_overlap_1_0 = _mask_overlap_T_3; // @[lsu.scala:321:49, :1198:62] wire _T_426 = ldq_executed_1 | ldq_succeeded_1; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_402 = ldq_st_dep_mask_1 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_4 = ldq_forward_stq_idx_1 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_5 = ldq_forward_stq_idx_1 < l_uop_1_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_6 = _forwarded_is_older_T_4 ^ _forwarded_is_older_T_5; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_7 = lcam_stq_idx_0 < l_uop_1_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_1 = _forwarded_is_older_T_6 ^ _forwarded_is_older_T_7; // @[util.scala:364:{58,72,78}] wire _GEN_508 = do_st_search_0 & ldq_valid_1 & ldq_addr_1_valid & _T_426 & ~ldq_addr_is_virtual_1 & _T_402[0] & dword_addr_matches_1_0 & mask_overlap_1_0 & (~ldq_forward_std_val_1 | ldq_forward_stq_idx_1 != lcam_stq_idx_0 & forwarded_is_older_1); // @[util.scala:364:72] wire _T_416 = do_ld_search_0 & ldq_valid_1 & ldq_addr_1_valid & ~ldq_addr_is_virtual_1 & dword_addr_matches_1_0 & mask_overlap_1_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_1 = lcam_younger_load_mask_0[1]; // @[lsu.scala:321:49, :1237:58] wire _T_435 = ldq_executed_1 & (ldq_succeeded_1 | ldq_will_succeed_1); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_509 = searcher_is_older_1 | _GEN_484; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_2; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_7 = ldq_addr_2_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_8 = _block_addr_matches_T_6 == _block_addr_matches_T_7; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_2_0 = _block_addr_matches_T_8; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_9 = ldq_addr_2_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_10 = _dword_addr_matches_T_8 == _dword_addr_matches_T_9; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_11 = block_addr_matches_2_0 & _dword_addr_matches_T_10; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_2_0 = _dword_addr_matches_T_11; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_510 = ldq_ld_byte_mask_2 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_4; // @[lsu.scala:1197:46] assign _mask_match_T_4 = _GEN_510; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_4; // @[lsu.scala:1198:46] assign _mask_overlap_T_4 = _GEN_510; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_5 = _mask_match_T_4 == ldq_ld_byte_mask_2; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_2_0 = _mask_match_T_5; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_5 = |_mask_overlap_T_4; // @[lsu.scala:1198:{46,62}] wire mask_overlap_2_0 = _mask_overlap_T_5; // @[lsu.scala:321:49, :1198:62] wire _T_478 = ldq_executed_2 | ldq_succeeded_2; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_454 = ldq_st_dep_mask_2 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_458 = do_st_search_0 & ldq_valid_2 & ldq_addr_2_valid & _T_478 & ~ldq_addr_is_virtual_2 & _T_454[0] & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_8 = ldq_forward_stq_idx_2 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_9 = ldq_forward_stq_idx_2 < l_uop_2_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_10 = _forwarded_is_older_T_8 ^ _forwarded_is_older_T_9; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_11 = lcam_stq_idx_0 < l_uop_2_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_2 = _forwarded_is_older_T_10 ^ _forwarded_is_older_T_11; // @[util.scala:364:{58,72,78}] wire _T_462 = ~ldq_forward_std_val_2 | ldq_forward_stq_idx_2 != lcam_stq_idx_0 & forwarded_is_older_2; // @[util.scala:364:72] wire _GEN_511 = _T_458 ? _T_462 | _GEN_508 | _GEN_482 : _GEN_508 | _GEN_482; // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_468 = do_ld_search_0 & ldq_valid_2 & ldq_addr_2_valid & ~ldq_addr_is_virtual_2 & dword_addr_matches_2_0 & mask_overlap_2_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_2 = lcam_younger_load_mask_0[2]; // @[lsu.scala:321:49, :1237:58] wire _T_487 = ldq_executed_2 & (ldq_succeeded_2 | ldq_will_succeed_2); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_512 = searcher_is_older_2 | _GEN_485; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_3; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_10 = ldq_addr_3_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_11 = _block_addr_matches_T_9 == _block_addr_matches_T_10; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_3_0 = _block_addr_matches_T_11; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_13 = ldq_addr_3_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_14 = _dword_addr_matches_T_12 == _dword_addr_matches_T_13; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_15 = block_addr_matches_3_0 & _dword_addr_matches_T_14; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_3_0 = _dword_addr_matches_T_15; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_513 = ldq_ld_byte_mask_3 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_6; // @[lsu.scala:1197:46] assign _mask_match_T_6 = _GEN_513; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_6; // @[lsu.scala:1198:46] assign _mask_overlap_T_6 = _GEN_513; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_7 = _mask_match_T_6 == ldq_ld_byte_mask_3; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_3_0 = _mask_match_T_7; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_7 = |_mask_overlap_T_6; // @[lsu.scala:1198:{46,62}] wire mask_overlap_3_0 = _mask_overlap_T_7; // @[lsu.scala:321:49, :1198:62] wire _T_530 = ldq_executed_3 | ldq_succeeded_3; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_506 = ldq_st_dep_mask_3 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_12 = ldq_forward_stq_idx_3 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_13 = ldq_forward_stq_idx_3 < l_uop_3_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_14 = _forwarded_is_older_T_12 ^ _forwarded_is_older_T_13; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_15 = lcam_stq_idx_0 < l_uop_3_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_3 = _forwarded_is_older_T_14 ^ _forwarded_is_older_T_15; // @[util.scala:364:{58,72,78}] wire _GEN_514 = do_st_search_0 & ldq_valid_3 & ldq_addr_3_valid & _T_530 & ~ldq_addr_is_virtual_3 & _T_506[0] & dword_addr_matches_3_0 & mask_overlap_3_0 & (~ldq_forward_std_val_3 | ldq_forward_stq_idx_3 != lcam_stq_idx_0 & forwarded_is_older_3); // @[util.scala:364:72] wire _T_520 = do_ld_search_0 & ldq_valid_3 & ldq_addr_3_valid & ~ldq_addr_is_virtual_3 & dword_addr_matches_3_0 & mask_overlap_3_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_3 = lcam_younger_load_mask_0[3]; // @[lsu.scala:321:49, :1237:58] wire _T_539 = ldq_executed_3 & (ldq_succeeded_3 | ldq_will_succeed_3); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_515 = searcher_is_older_3 | _GEN_486; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_4; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_13 = ldq_addr_4_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_14 = _block_addr_matches_T_12 == _block_addr_matches_T_13; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_4_0 = _block_addr_matches_T_14; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_17 = ldq_addr_4_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_18 = _dword_addr_matches_T_16 == _dword_addr_matches_T_17; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_19 = block_addr_matches_4_0 & _dword_addr_matches_T_18; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_4_0 = _dword_addr_matches_T_19; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_516 = ldq_ld_byte_mask_4 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_8; // @[lsu.scala:1197:46] assign _mask_match_T_8 = _GEN_516; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_8; // @[lsu.scala:1198:46] assign _mask_overlap_T_8 = _GEN_516; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_9 = _mask_match_T_8 == ldq_ld_byte_mask_4; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_4_0 = _mask_match_T_9; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_9 = |_mask_overlap_T_8; // @[lsu.scala:1198:{46,62}] wire mask_overlap_4_0 = _mask_overlap_T_9; // @[lsu.scala:321:49, :1198:62] wire _T_582 = ldq_executed_4 | ldq_succeeded_4; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_558 = ldq_st_dep_mask_4 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_562 = do_st_search_0 & ldq_valid_4 & ldq_addr_4_valid & _T_582 & ~ldq_addr_is_virtual_4 & _T_558[0] & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_16 = ldq_forward_stq_idx_4 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_17 = ldq_forward_stq_idx_4 < l_uop_4_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_18 = _forwarded_is_older_T_16 ^ _forwarded_is_older_T_17; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_19 = lcam_stq_idx_0 < l_uop_4_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_4 = _forwarded_is_older_T_18 ^ _forwarded_is_older_T_19; // @[util.scala:364:{58,72,78}] wire _T_566 = ~ldq_forward_std_val_4 | ldq_forward_stq_idx_4 != lcam_stq_idx_0 & forwarded_is_older_4; // @[util.scala:364:72] wire _GEN_517 = _T_562 ? _T_566 | _GEN_514 | _GEN_511 : _GEN_514 | _GEN_511; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_572 = do_ld_search_0 & ldq_valid_4 & ldq_addr_4_valid & ~ldq_addr_is_virtual_4 & dword_addr_matches_4_0 & mask_overlap_4_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_4 = lcam_younger_load_mask_0[4]; // @[lsu.scala:321:49, :1237:58] wire _T_591 = ldq_executed_4 & (ldq_succeeded_4 | ldq_will_succeed_4); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_518 = searcher_is_older_4 | _GEN_487; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_5; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_16 = ldq_addr_5_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_17 = _block_addr_matches_T_15 == _block_addr_matches_T_16; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_5_0 = _block_addr_matches_T_17; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_21 = ldq_addr_5_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_22 = _dword_addr_matches_T_20 == _dword_addr_matches_T_21; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_23 = block_addr_matches_5_0 & _dword_addr_matches_T_22; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_5_0 = _dword_addr_matches_T_23; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_519 = ldq_ld_byte_mask_5 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_10; // @[lsu.scala:1197:46] assign _mask_match_T_10 = _GEN_519; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_10; // @[lsu.scala:1198:46] assign _mask_overlap_T_10 = _GEN_519; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_11 = _mask_match_T_10 == ldq_ld_byte_mask_5; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_5_0 = _mask_match_T_11; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_11 = |_mask_overlap_T_10; // @[lsu.scala:1198:{46,62}] wire mask_overlap_5_0 = _mask_overlap_T_11; // @[lsu.scala:321:49, :1198:62] wire _T_634 = ldq_executed_5 | ldq_succeeded_5; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_610 = ldq_st_dep_mask_5 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_20 = ldq_forward_stq_idx_5 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_21 = ldq_forward_stq_idx_5 < l_uop_5_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_22 = _forwarded_is_older_T_20 ^ _forwarded_is_older_T_21; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_23 = lcam_stq_idx_0 < l_uop_5_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_5 = _forwarded_is_older_T_22 ^ _forwarded_is_older_T_23; // @[util.scala:364:{58,72,78}] wire _GEN_520 = do_st_search_0 & ldq_valid_5 & ldq_addr_5_valid & _T_634 & ~ldq_addr_is_virtual_5 & _T_610[0] & dword_addr_matches_5_0 & mask_overlap_5_0 & (~ldq_forward_std_val_5 | ldq_forward_stq_idx_5 != lcam_stq_idx_0 & forwarded_is_older_5); // @[util.scala:364:72] wire _T_624 = do_ld_search_0 & ldq_valid_5 & ldq_addr_5_valid & ~ldq_addr_is_virtual_5 & dword_addr_matches_5_0 & mask_overlap_5_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_5 = lcam_younger_load_mask_0[5]; // @[lsu.scala:321:49, :1237:58] wire _T_643 = ldq_executed_5 & (ldq_succeeded_5 | ldq_will_succeed_5); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_521 = searcher_is_older_5 | _GEN_488; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_6; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_19 = ldq_addr_6_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_20 = _block_addr_matches_T_18 == _block_addr_matches_T_19; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_6_0 = _block_addr_matches_T_20; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_25 = ldq_addr_6_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_26 = _dword_addr_matches_T_24 == _dword_addr_matches_T_25; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_27 = block_addr_matches_6_0 & _dword_addr_matches_T_26; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_6_0 = _dword_addr_matches_T_27; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_522 = ldq_ld_byte_mask_6 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_12; // @[lsu.scala:1197:46] assign _mask_match_T_12 = _GEN_522; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_12; // @[lsu.scala:1198:46] assign _mask_overlap_T_12 = _GEN_522; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_13 = _mask_match_T_12 == ldq_ld_byte_mask_6; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_6_0 = _mask_match_T_13; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_13 = |_mask_overlap_T_12; // @[lsu.scala:1198:{46,62}] wire mask_overlap_6_0 = _mask_overlap_T_13; // @[lsu.scala:321:49, :1198:62] wire _T_686 = ldq_executed_6 | ldq_succeeded_6; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_662 = ldq_st_dep_mask_6 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_666 = do_st_search_0 & ldq_valid_6 & ldq_addr_6_valid & _T_686 & ~ldq_addr_is_virtual_6 & _T_662[0] & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_24 = ldq_forward_stq_idx_6 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_25 = ldq_forward_stq_idx_6 < l_uop_6_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_26 = _forwarded_is_older_T_24 ^ _forwarded_is_older_T_25; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_27 = lcam_stq_idx_0 < l_uop_6_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_6 = _forwarded_is_older_T_26 ^ _forwarded_is_older_T_27; // @[util.scala:364:{58,72,78}] wire _T_670 = ~ldq_forward_std_val_6 | ldq_forward_stq_idx_6 != lcam_stq_idx_0 & forwarded_is_older_6; // @[util.scala:364:72] wire _GEN_523 = _T_666 ? _T_670 | _GEN_520 | _GEN_517 : _GEN_520 | _GEN_517; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_676 = do_ld_search_0 & ldq_valid_6 & ldq_addr_6_valid & ~ldq_addr_is_virtual_6 & dword_addr_matches_6_0 & mask_overlap_6_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_6 = lcam_younger_load_mask_0[6]; // @[lsu.scala:321:49, :1237:58] wire _T_695 = ldq_executed_6 & (ldq_succeeded_6 | ldq_will_succeed_6); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_524 = searcher_is_older_6 | _GEN_489; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_7; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_22 = ldq_addr_7_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_23 = _block_addr_matches_T_21 == _block_addr_matches_T_22; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_7_0 = _block_addr_matches_T_23; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_29 = ldq_addr_7_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_30 = _dword_addr_matches_T_28 == _dword_addr_matches_T_29; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_31 = block_addr_matches_7_0 & _dword_addr_matches_T_30; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_7_0 = _dword_addr_matches_T_31; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_525 = ldq_ld_byte_mask_7 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_14; // @[lsu.scala:1197:46] assign _mask_match_T_14 = _GEN_525; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_14; // @[lsu.scala:1198:46] assign _mask_overlap_T_14 = _GEN_525; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_15 = _mask_match_T_14 == ldq_ld_byte_mask_7; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_7_0 = _mask_match_T_15; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_15 = |_mask_overlap_T_14; // @[lsu.scala:1198:{46,62}] wire mask_overlap_7_0 = _mask_overlap_T_15; // @[lsu.scala:321:49, :1198:62] wire _T_738 = ldq_executed_7 | ldq_succeeded_7; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_714 = ldq_st_dep_mask_7 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_28 = ldq_forward_stq_idx_7 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_29 = ldq_forward_stq_idx_7 < l_uop_7_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_30 = _forwarded_is_older_T_28 ^ _forwarded_is_older_T_29; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_31 = lcam_stq_idx_0 < l_uop_7_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_7 = _forwarded_is_older_T_30 ^ _forwarded_is_older_T_31; // @[util.scala:364:{58,72,78}] wire _GEN_526 = do_st_search_0 & ldq_valid_7 & ldq_addr_7_valid & _T_738 & ~ldq_addr_is_virtual_7 & _T_714[0] & dword_addr_matches_7_0 & mask_overlap_7_0 & (~ldq_forward_std_val_7 | ldq_forward_stq_idx_7 != lcam_stq_idx_0 & forwarded_is_older_7); // @[util.scala:364:72] wire _T_728 = do_ld_search_0 & ldq_valid_7 & ldq_addr_7_valid & ~ldq_addr_is_virtual_7 & dword_addr_matches_7_0 & mask_overlap_7_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_7 = lcam_younger_load_mask_0[7]; // @[lsu.scala:321:49, :1237:58] wire _T_747 = ldq_executed_7 & (ldq_succeeded_7 | ldq_will_succeed_7); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_527 = searcher_is_older_7 | _GEN_490; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_8; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_25 = ldq_addr_8_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_26 = _block_addr_matches_T_24 == _block_addr_matches_T_25; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_8_0 = _block_addr_matches_T_26; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_33 = ldq_addr_8_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_34 = _dword_addr_matches_T_32 == _dword_addr_matches_T_33; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_35 = block_addr_matches_8_0 & _dword_addr_matches_T_34; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_8_0 = _dword_addr_matches_T_35; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_528 = ldq_ld_byte_mask_8 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_16; // @[lsu.scala:1197:46] assign _mask_match_T_16 = _GEN_528; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_16; // @[lsu.scala:1198:46] assign _mask_overlap_T_16 = _GEN_528; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_17 = _mask_match_T_16 == ldq_ld_byte_mask_8; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_8_0 = _mask_match_T_17; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_17 = |_mask_overlap_T_16; // @[lsu.scala:1198:{46,62}] wire mask_overlap_8_0 = _mask_overlap_T_17; // @[lsu.scala:321:49, :1198:62] wire _T_790 = ldq_executed_8 | ldq_succeeded_8; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_766 = ldq_st_dep_mask_8 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_770 = do_st_search_0 & ldq_valid_8 & ldq_addr_8_valid & _T_790 & ~ldq_addr_is_virtual_8 & _T_766[0] & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_32 = ldq_forward_stq_idx_8 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_33 = ldq_forward_stq_idx_8 < l_uop_8_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_34 = _forwarded_is_older_T_32 ^ _forwarded_is_older_T_33; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_35 = lcam_stq_idx_0 < l_uop_8_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_8 = _forwarded_is_older_T_34 ^ _forwarded_is_older_T_35; // @[util.scala:364:{58,72,78}] wire _T_774 = ~ldq_forward_std_val_8 | ldq_forward_stq_idx_8 != lcam_stq_idx_0 & forwarded_is_older_8; // @[util.scala:364:72] wire _GEN_529 = _T_770 ? _T_774 | _GEN_526 | _GEN_523 : _GEN_526 | _GEN_523; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_780 = do_ld_search_0 & ldq_valid_8 & ldq_addr_8_valid & ~ldq_addr_is_virtual_8 & dword_addr_matches_8_0 & mask_overlap_8_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_8 = lcam_younger_load_mask_0[8]; // @[lsu.scala:321:49, :1237:58] wire _T_799 = ldq_executed_8 & (ldq_succeeded_8 | ldq_will_succeed_8); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_530 = searcher_is_older_8 | _GEN_491; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_9; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_28 = ldq_addr_9_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_29 = _block_addr_matches_T_27 == _block_addr_matches_T_28; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_9_0 = _block_addr_matches_T_29; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_37 = ldq_addr_9_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_38 = _dword_addr_matches_T_36 == _dword_addr_matches_T_37; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_39 = block_addr_matches_9_0 & _dword_addr_matches_T_38; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_9_0 = _dword_addr_matches_T_39; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_531 = ldq_ld_byte_mask_9 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_18; // @[lsu.scala:1197:46] assign _mask_match_T_18 = _GEN_531; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_18; // @[lsu.scala:1198:46] assign _mask_overlap_T_18 = _GEN_531; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_19 = _mask_match_T_18 == ldq_ld_byte_mask_9; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_9_0 = _mask_match_T_19; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_19 = |_mask_overlap_T_18; // @[lsu.scala:1198:{46,62}] wire mask_overlap_9_0 = _mask_overlap_T_19; // @[lsu.scala:321:49, :1198:62] wire _T_842 = ldq_executed_9 | ldq_succeeded_9; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_818 = ldq_st_dep_mask_9 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_36 = ldq_forward_stq_idx_9 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_37 = ldq_forward_stq_idx_9 < l_uop_9_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_38 = _forwarded_is_older_T_36 ^ _forwarded_is_older_T_37; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_39 = lcam_stq_idx_0 < l_uop_9_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_9 = _forwarded_is_older_T_38 ^ _forwarded_is_older_T_39; // @[util.scala:364:{58,72,78}] wire _GEN_532 = do_st_search_0 & ldq_valid_9 & ldq_addr_9_valid & _T_842 & ~ldq_addr_is_virtual_9 & _T_818[0] & dword_addr_matches_9_0 & mask_overlap_9_0 & (~ldq_forward_std_val_9 | ldq_forward_stq_idx_9 != lcam_stq_idx_0 & forwarded_is_older_9); // @[util.scala:364:72] wire _T_832 = do_ld_search_0 & ldq_valid_9 & ldq_addr_9_valid & ~ldq_addr_is_virtual_9 & dword_addr_matches_9_0 & mask_overlap_9_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_9 = lcam_younger_load_mask_0[9]; // @[lsu.scala:321:49, :1237:58] wire _T_851 = ldq_executed_9 & (ldq_succeeded_9 | ldq_will_succeed_9); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_533 = searcher_is_older_9 | _GEN_492; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_10; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_31 = ldq_addr_10_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_32 = _block_addr_matches_T_30 == _block_addr_matches_T_31; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_10_0 = _block_addr_matches_T_32; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_41 = ldq_addr_10_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_42 = _dword_addr_matches_T_40 == _dword_addr_matches_T_41; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_43 = block_addr_matches_10_0 & _dword_addr_matches_T_42; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_10_0 = _dword_addr_matches_T_43; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_534 = ldq_ld_byte_mask_10 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_20; // @[lsu.scala:1197:46] assign _mask_match_T_20 = _GEN_534; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_20; // @[lsu.scala:1198:46] assign _mask_overlap_T_20 = _GEN_534; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_21 = _mask_match_T_20 == ldq_ld_byte_mask_10; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_10_0 = _mask_match_T_21; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_21 = |_mask_overlap_T_20; // @[lsu.scala:1198:{46,62}] wire mask_overlap_10_0 = _mask_overlap_T_21; // @[lsu.scala:321:49, :1198:62] wire _T_894 = ldq_executed_10 | ldq_succeeded_10; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_870 = ldq_st_dep_mask_10 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_874 = do_st_search_0 & ldq_valid_10 & ldq_addr_10_valid & _T_894 & ~ldq_addr_is_virtual_10 & _T_870[0] & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_40 = ldq_forward_stq_idx_10 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_41 = ldq_forward_stq_idx_10 < l_uop_10_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_42 = _forwarded_is_older_T_40 ^ _forwarded_is_older_T_41; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_43 = lcam_stq_idx_0 < l_uop_10_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_10 = _forwarded_is_older_T_42 ^ _forwarded_is_older_T_43; // @[util.scala:364:{58,72,78}] wire _T_878 = ~ldq_forward_std_val_10 | ldq_forward_stq_idx_10 != lcam_stq_idx_0 & forwarded_is_older_10; // @[util.scala:364:72] wire _GEN_535 = _T_874 ? _T_878 | _GEN_532 | _GEN_529 : _GEN_532 | _GEN_529; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_884 = do_ld_search_0 & ldq_valid_10 & ldq_addr_10_valid & ~ldq_addr_is_virtual_10 & dword_addr_matches_10_0 & mask_overlap_10_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_10 = lcam_younger_load_mask_0[10]; // @[lsu.scala:321:49, :1237:58] wire _T_903 = ldq_executed_10 & (ldq_succeeded_10 | ldq_will_succeed_10); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_536 = searcher_is_older_10 | _GEN_493; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_11; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_34 = ldq_addr_11_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_35 = _block_addr_matches_T_33 == _block_addr_matches_T_34; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_11_0 = _block_addr_matches_T_35; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_45 = ldq_addr_11_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_46 = _dword_addr_matches_T_44 == _dword_addr_matches_T_45; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_47 = block_addr_matches_11_0 & _dword_addr_matches_T_46; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_11_0 = _dword_addr_matches_T_47; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_537 = ldq_ld_byte_mask_11 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_22; // @[lsu.scala:1197:46] assign _mask_match_T_22 = _GEN_537; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_22; // @[lsu.scala:1198:46] assign _mask_overlap_T_22 = _GEN_537; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_23 = _mask_match_T_22 == ldq_ld_byte_mask_11; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_11_0 = _mask_match_T_23; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_23 = |_mask_overlap_T_22; // @[lsu.scala:1198:{46,62}] wire mask_overlap_11_0 = _mask_overlap_T_23; // @[lsu.scala:321:49, :1198:62] wire _T_946 = ldq_executed_11 | ldq_succeeded_11; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_922 = ldq_st_dep_mask_11 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_44 = ldq_forward_stq_idx_11 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_45 = ldq_forward_stq_idx_11 < l_uop_11_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_46 = _forwarded_is_older_T_44 ^ _forwarded_is_older_T_45; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_47 = lcam_stq_idx_0 < l_uop_11_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_11 = _forwarded_is_older_T_46 ^ _forwarded_is_older_T_47; // @[util.scala:364:{58,72,78}] wire _GEN_538 = do_st_search_0 & ldq_valid_11 & ldq_addr_11_valid & _T_946 & ~ldq_addr_is_virtual_11 & _T_922[0] & dword_addr_matches_11_0 & mask_overlap_11_0 & (~ldq_forward_std_val_11 | ldq_forward_stq_idx_11 != lcam_stq_idx_0 & forwarded_is_older_11); // @[util.scala:364:72] wire _T_936 = do_ld_search_0 & ldq_valid_11 & ldq_addr_11_valid & ~ldq_addr_is_virtual_11 & dword_addr_matches_11_0 & mask_overlap_11_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_11 = lcam_younger_load_mask_0[11]; // @[lsu.scala:321:49, :1237:58] wire _T_955 = ldq_executed_11 & (ldq_succeeded_11 | ldq_will_succeed_11); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_539 = searcher_is_older_11 | _GEN_494; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_12; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_37 = ldq_addr_12_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_38 = _block_addr_matches_T_36 == _block_addr_matches_T_37; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_12_0 = _block_addr_matches_T_38; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_49 = ldq_addr_12_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_50 = _dword_addr_matches_T_48 == _dword_addr_matches_T_49; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_51 = block_addr_matches_12_0 & _dword_addr_matches_T_50; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_12_0 = _dword_addr_matches_T_51; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_540 = ldq_ld_byte_mask_12 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_24; // @[lsu.scala:1197:46] assign _mask_match_T_24 = _GEN_540; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_24; // @[lsu.scala:1198:46] assign _mask_overlap_T_24 = _GEN_540; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_25 = _mask_match_T_24 == ldq_ld_byte_mask_12; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_12_0 = _mask_match_T_25; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_25 = |_mask_overlap_T_24; // @[lsu.scala:1198:{46,62}] wire mask_overlap_12_0 = _mask_overlap_T_25; // @[lsu.scala:321:49, :1198:62] wire _T_998 = ldq_executed_12 | ldq_succeeded_12; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_974 = ldq_st_dep_mask_12 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_978 = do_st_search_0 & ldq_valid_12 & ldq_addr_12_valid & _T_998 & ~ldq_addr_is_virtual_12 & _T_974[0] & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_48 = ldq_forward_stq_idx_12 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_49 = ldq_forward_stq_idx_12 < l_uop_12_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_50 = _forwarded_is_older_T_48 ^ _forwarded_is_older_T_49; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_51 = lcam_stq_idx_0 < l_uop_12_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_12 = _forwarded_is_older_T_50 ^ _forwarded_is_older_T_51; // @[util.scala:364:{58,72,78}] wire _T_982 = ~ldq_forward_std_val_12 | ldq_forward_stq_idx_12 != lcam_stq_idx_0 & forwarded_is_older_12; // @[util.scala:364:72] wire _GEN_541 = _T_978 ? _T_982 | _GEN_538 | _GEN_535 : _GEN_538 | _GEN_535; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_988 = do_ld_search_0 & ldq_valid_12 & ldq_addr_12_valid & ~ldq_addr_is_virtual_12 & dword_addr_matches_12_0 & mask_overlap_12_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_12 = lcam_younger_load_mask_0[12]; // @[lsu.scala:321:49, :1237:58] wire _T_1007 = ldq_executed_12 & (ldq_succeeded_12 | ldq_will_succeed_12); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_542 = searcher_is_older_12 | _GEN_495; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_13; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_40 = ldq_addr_13_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_41 = _block_addr_matches_T_39 == _block_addr_matches_T_40; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_13_0 = _block_addr_matches_T_41; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_53 = ldq_addr_13_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_54 = _dword_addr_matches_T_52 == _dword_addr_matches_T_53; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_55 = block_addr_matches_13_0 & _dword_addr_matches_T_54; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_13_0 = _dword_addr_matches_T_55; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_543 = ldq_ld_byte_mask_13 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_26; // @[lsu.scala:1197:46] assign _mask_match_T_26 = _GEN_543; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_26; // @[lsu.scala:1198:46] assign _mask_overlap_T_26 = _GEN_543; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_27 = _mask_match_T_26 == ldq_ld_byte_mask_13; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_13_0 = _mask_match_T_27; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_27 = |_mask_overlap_T_26; // @[lsu.scala:1198:{46,62}] wire mask_overlap_13_0 = _mask_overlap_T_27; // @[lsu.scala:321:49, :1198:62] wire _T_1050 = ldq_executed_13 | ldq_succeeded_13; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1026 = ldq_st_dep_mask_13 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_52 = ldq_forward_stq_idx_13 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_53 = ldq_forward_stq_idx_13 < l_uop_13_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_54 = _forwarded_is_older_T_52 ^ _forwarded_is_older_T_53; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_55 = lcam_stq_idx_0 < l_uop_13_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_13 = _forwarded_is_older_T_54 ^ _forwarded_is_older_T_55; // @[util.scala:364:{58,72,78}] wire _GEN_544 = do_st_search_0 & ldq_valid_13 & ldq_addr_13_valid & _T_1050 & ~ldq_addr_is_virtual_13 & _T_1026[0] & dword_addr_matches_13_0 & mask_overlap_13_0 & (~ldq_forward_std_val_13 | ldq_forward_stq_idx_13 != lcam_stq_idx_0 & forwarded_is_older_13); // @[util.scala:364:72] wire _T_1040 = do_ld_search_0 & ldq_valid_13 & ldq_addr_13_valid & ~ldq_addr_is_virtual_13 & dword_addr_matches_13_0 & mask_overlap_13_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_13 = lcam_younger_load_mask_0[13]; // @[lsu.scala:321:49, :1237:58] wire _T_1059 = ldq_executed_13 & (ldq_succeeded_13 | ldq_will_succeed_13); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_545 = searcher_is_older_13 | _GEN_496; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_14; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_43 = ldq_addr_14_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_44 = _block_addr_matches_T_42 == _block_addr_matches_T_43; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_14_0 = _block_addr_matches_T_44; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_57 = ldq_addr_14_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_58 = _dword_addr_matches_T_56 == _dword_addr_matches_T_57; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_59 = block_addr_matches_14_0 & _dword_addr_matches_T_58; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_14_0 = _dword_addr_matches_T_59; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_546 = ldq_ld_byte_mask_14 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_28; // @[lsu.scala:1197:46] assign _mask_match_T_28 = _GEN_546; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_28; // @[lsu.scala:1198:46] assign _mask_overlap_T_28 = _GEN_546; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_29 = _mask_match_T_28 == ldq_ld_byte_mask_14; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_14_0 = _mask_match_T_29; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_29 = |_mask_overlap_T_28; // @[lsu.scala:1198:{46,62}] wire mask_overlap_14_0 = _mask_overlap_T_29; // @[lsu.scala:321:49, :1198:62] wire _T_1102 = ldq_executed_14 | ldq_succeeded_14; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1078 = ldq_st_dep_mask_14 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1082 = do_st_search_0 & ldq_valid_14 & ldq_addr_14_valid & _T_1102 & ~ldq_addr_is_virtual_14 & _T_1078[0] & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_56 = ldq_forward_stq_idx_14 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_57 = ldq_forward_stq_idx_14 < l_uop_14_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_58 = _forwarded_is_older_T_56 ^ _forwarded_is_older_T_57; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_59 = lcam_stq_idx_0 < l_uop_14_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_14 = _forwarded_is_older_T_58 ^ _forwarded_is_older_T_59; // @[util.scala:364:{58,72,78}] wire _T_1086 = ~ldq_forward_std_val_14 | ldq_forward_stq_idx_14 != lcam_stq_idx_0 & forwarded_is_older_14; // @[util.scala:364:72] wire _GEN_547 = _T_1082 ? _T_1086 | _GEN_544 | _GEN_541 : _GEN_544 | _GEN_541; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1092 = do_ld_search_0 & ldq_valid_14 & ldq_addr_14_valid & ~ldq_addr_is_virtual_14 & dword_addr_matches_14_0 & mask_overlap_14_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_14 = lcam_younger_load_mask_0[14]; // @[lsu.scala:321:49, :1237:58] wire _T_1111 = ldq_executed_14 & (ldq_succeeded_14 | ldq_will_succeed_14); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_548 = searcher_is_older_14 | _GEN_497; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_15; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_46 = ldq_addr_15_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_47 = _block_addr_matches_T_45 == _block_addr_matches_T_46; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_15_0 = _block_addr_matches_T_47; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_61 = ldq_addr_15_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_62 = _dword_addr_matches_T_60 == _dword_addr_matches_T_61; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_63 = block_addr_matches_15_0 & _dword_addr_matches_T_62; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_15_0 = _dword_addr_matches_T_63; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_549 = ldq_ld_byte_mask_15 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_30; // @[lsu.scala:1197:46] assign _mask_match_T_30 = _GEN_549; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_30; // @[lsu.scala:1198:46] assign _mask_overlap_T_30 = _GEN_549; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_31 = _mask_match_T_30 == ldq_ld_byte_mask_15; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_15_0 = _mask_match_T_31; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_31 = |_mask_overlap_T_30; // @[lsu.scala:1198:{46,62}] wire mask_overlap_15_0 = _mask_overlap_T_31; // @[lsu.scala:321:49, :1198:62] wire _T_1154 = ldq_executed_15 | ldq_succeeded_15; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1130 = ldq_st_dep_mask_15 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_60 = ldq_forward_stq_idx_15 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_61 = ldq_forward_stq_idx_15 < l_uop_15_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_62 = _forwarded_is_older_T_60 ^ _forwarded_is_older_T_61; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_63 = lcam_stq_idx_0 < l_uop_15_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_15 = _forwarded_is_older_T_62 ^ _forwarded_is_older_T_63; // @[util.scala:364:{58,72,78}] wire _GEN_550 = do_st_search_0 & ldq_valid_15 & ldq_addr_15_valid & _T_1154 & ~ldq_addr_is_virtual_15 & _T_1130[0] & dword_addr_matches_15_0 & mask_overlap_15_0 & (~ldq_forward_std_val_15 | ldq_forward_stq_idx_15 != lcam_stq_idx_0 & forwarded_is_older_15); // @[util.scala:364:72] wire _T_1144 = do_ld_search_0 & ldq_valid_15 & ldq_addr_15_valid & ~ldq_addr_is_virtual_15 & dword_addr_matches_15_0 & mask_overlap_15_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_15 = lcam_younger_load_mask_0[15]; // @[lsu.scala:321:49, :1237:58] wire _T_1163 = ldq_executed_15 & (ldq_succeeded_15 | ldq_will_succeed_15); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_551 = searcher_is_older_15 | _GEN_498; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_16; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_49 = ldq_addr_16_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_50 = _block_addr_matches_T_48 == _block_addr_matches_T_49; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_16_0 = _block_addr_matches_T_50; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_65 = ldq_addr_16_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_66 = _dword_addr_matches_T_64 == _dword_addr_matches_T_65; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_67 = block_addr_matches_16_0 & _dword_addr_matches_T_66; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_16_0 = _dword_addr_matches_T_67; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_552 = ldq_ld_byte_mask_16 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_32; // @[lsu.scala:1197:46] assign _mask_match_T_32 = _GEN_552; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_32; // @[lsu.scala:1198:46] assign _mask_overlap_T_32 = _GEN_552; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_33 = _mask_match_T_32 == ldq_ld_byte_mask_16; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_16_0 = _mask_match_T_33; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_33 = |_mask_overlap_T_32; // @[lsu.scala:1198:{46,62}] wire mask_overlap_16_0 = _mask_overlap_T_33; // @[lsu.scala:321:49, :1198:62] wire _T_1206 = ldq_executed_16 | ldq_succeeded_16; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1182 = ldq_st_dep_mask_16 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1186 = do_st_search_0 & ldq_valid_16 & ldq_addr_16_valid & _T_1206 & ~ldq_addr_is_virtual_16 & _T_1182[0] & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_64 = ldq_forward_stq_idx_16 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_65 = ldq_forward_stq_idx_16 < l_uop_16_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_66 = _forwarded_is_older_T_64 ^ _forwarded_is_older_T_65; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_67 = lcam_stq_idx_0 < l_uop_16_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_16 = _forwarded_is_older_T_66 ^ _forwarded_is_older_T_67; // @[util.scala:364:{58,72,78}] wire _T_1190 = ~ldq_forward_std_val_16 | ldq_forward_stq_idx_16 != lcam_stq_idx_0 & forwarded_is_older_16; // @[util.scala:364:72] wire _GEN_553 = _T_1186 ? _T_1190 | _GEN_550 | _GEN_547 : _GEN_550 | _GEN_547; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1196 = do_ld_search_0 & ldq_valid_16 & ldq_addr_16_valid & ~ldq_addr_is_virtual_16 & dword_addr_matches_16_0 & mask_overlap_16_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_16 = lcam_younger_load_mask_0[16]; // @[lsu.scala:321:49, :1237:58] wire _T_1215 = ldq_executed_16 & (ldq_succeeded_16 | ldq_will_succeed_16); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_554 = searcher_is_older_16 | _GEN_499; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_17; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_52 = ldq_addr_17_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_53 = _block_addr_matches_T_51 == _block_addr_matches_T_52; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_17_0 = _block_addr_matches_T_53; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_69 = ldq_addr_17_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_70 = _dword_addr_matches_T_68 == _dword_addr_matches_T_69; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_71 = block_addr_matches_17_0 & _dword_addr_matches_T_70; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_17_0 = _dword_addr_matches_T_71; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_555 = ldq_ld_byte_mask_17 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_34; // @[lsu.scala:1197:46] assign _mask_match_T_34 = _GEN_555; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_34; // @[lsu.scala:1198:46] assign _mask_overlap_T_34 = _GEN_555; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_35 = _mask_match_T_34 == ldq_ld_byte_mask_17; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_17_0 = _mask_match_T_35; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_35 = |_mask_overlap_T_34; // @[lsu.scala:1198:{46,62}] wire mask_overlap_17_0 = _mask_overlap_T_35; // @[lsu.scala:321:49, :1198:62] wire _T_1258 = ldq_executed_17 | ldq_succeeded_17; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1234 = ldq_st_dep_mask_17 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_68 = ldq_forward_stq_idx_17 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_69 = ldq_forward_stq_idx_17 < l_uop_17_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_70 = _forwarded_is_older_T_68 ^ _forwarded_is_older_T_69; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_71 = lcam_stq_idx_0 < l_uop_17_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_17 = _forwarded_is_older_T_70 ^ _forwarded_is_older_T_71; // @[util.scala:364:{58,72,78}] wire _GEN_556 = do_st_search_0 & ldq_valid_17 & ldq_addr_17_valid & _T_1258 & ~ldq_addr_is_virtual_17 & _T_1234[0] & dword_addr_matches_17_0 & mask_overlap_17_0 & (~ldq_forward_std_val_17 | ldq_forward_stq_idx_17 != lcam_stq_idx_0 & forwarded_is_older_17); // @[util.scala:364:72] wire _T_1248 = do_ld_search_0 & ldq_valid_17 & ldq_addr_17_valid & ~ldq_addr_is_virtual_17 & dword_addr_matches_17_0 & mask_overlap_17_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_17 = lcam_younger_load_mask_0[17]; // @[lsu.scala:321:49, :1237:58] wire _T_1267 = ldq_executed_17 & (ldq_succeeded_17 | ldq_will_succeed_17); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_557 = searcher_is_older_17 | _GEN_500; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_18; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_55 = ldq_addr_18_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_56 = _block_addr_matches_T_54 == _block_addr_matches_T_55; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_18_0 = _block_addr_matches_T_56; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_73 = ldq_addr_18_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_74 = _dword_addr_matches_T_72 == _dword_addr_matches_T_73; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_75 = block_addr_matches_18_0 & _dword_addr_matches_T_74; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_18_0 = _dword_addr_matches_T_75; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_558 = ldq_ld_byte_mask_18 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_36; // @[lsu.scala:1197:46] assign _mask_match_T_36 = _GEN_558; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_36; // @[lsu.scala:1198:46] assign _mask_overlap_T_36 = _GEN_558; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_37 = _mask_match_T_36 == ldq_ld_byte_mask_18; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_18_0 = _mask_match_T_37; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_37 = |_mask_overlap_T_36; // @[lsu.scala:1198:{46,62}] wire mask_overlap_18_0 = _mask_overlap_T_37; // @[lsu.scala:321:49, :1198:62] wire _T_1310 = ldq_executed_18 | ldq_succeeded_18; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1286 = ldq_st_dep_mask_18 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1290 = do_st_search_0 & ldq_valid_18 & ldq_addr_18_valid & _T_1310 & ~ldq_addr_is_virtual_18 & _T_1286[0] & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_72 = ldq_forward_stq_idx_18 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_73 = ldq_forward_stq_idx_18 < l_uop_18_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_74 = _forwarded_is_older_T_72 ^ _forwarded_is_older_T_73; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_75 = lcam_stq_idx_0 < l_uop_18_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_18 = _forwarded_is_older_T_74 ^ _forwarded_is_older_T_75; // @[util.scala:364:{58,72,78}] wire _T_1294 = ~ldq_forward_std_val_18 | ldq_forward_stq_idx_18 != lcam_stq_idx_0 & forwarded_is_older_18; // @[util.scala:364:72] wire _GEN_559 = _T_1290 ? _T_1294 | _GEN_556 | _GEN_553 : _GEN_556 | _GEN_553; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1300 = do_ld_search_0 & ldq_valid_18 & ldq_addr_18_valid & ~ldq_addr_is_virtual_18 & dword_addr_matches_18_0 & mask_overlap_18_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_18 = lcam_younger_load_mask_0[18]; // @[lsu.scala:321:49, :1237:58] wire _T_1319 = ldq_executed_18 & (ldq_succeeded_18 | ldq_will_succeed_18); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_560 = searcher_is_older_18 | _GEN_501; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_19; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_58 = ldq_addr_19_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_59 = _block_addr_matches_T_57 == _block_addr_matches_T_58; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_19_0 = _block_addr_matches_T_59; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_77 = ldq_addr_19_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_78 = _dword_addr_matches_T_76 == _dword_addr_matches_T_77; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_79 = block_addr_matches_19_0 & _dword_addr_matches_T_78; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_19_0 = _dword_addr_matches_T_79; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_561 = ldq_ld_byte_mask_19 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_38; // @[lsu.scala:1197:46] assign _mask_match_T_38 = _GEN_561; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_38; // @[lsu.scala:1198:46] assign _mask_overlap_T_38 = _GEN_561; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_39 = _mask_match_T_38 == ldq_ld_byte_mask_19; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_19_0 = _mask_match_T_39; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_39 = |_mask_overlap_T_38; // @[lsu.scala:1198:{46,62}] wire mask_overlap_19_0 = _mask_overlap_T_39; // @[lsu.scala:321:49, :1198:62] wire _T_1362 = ldq_executed_19 | ldq_succeeded_19; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1338 = ldq_st_dep_mask_19 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_76 = ldq_forward_stq_idx_19 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_77 = ldq_forward_stq_idx_19 < l_uop_19_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_78 = _forwarded_is_older_T_76 ^ _forwarded_is_older_T_77; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_79 = lcam_stq_idx_0 < l_uop_19_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_19 = _forwarded_is_older_T_78 ^ _forwarded_is_older_T_79; // @[util.scala:364:{58,72,78}] wire _GEN_562 = do_st_search_0 & ldq_valid_19 & ldq_addr_19_valid & _T_1362 & ~ldq_addr_is_virtual_19 & _T_1338[0] & dword_addr_matches_19_0 & mask_overlap_19_0 & (~ldq_forward_std_val_19 | ldq_forward_stq_idx_19 != lcam_stq_idx_0 & forwarded_is_older_19); // @[util.scala:364:72] wire _T_1352 = do_ld_search_0 & ldq_valid_19 & ldq_addr_19_valid & ~ldq_addr_is_virtual_19 & dword_addr_matches_19_0 & mask_overlap_19_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_19 = lcam_younger_load_mask_0[19]; // @[lsu.scala:321:49, :1237:58] wire _T_1371 = ldq_executed_19 & (ldq_succeeded_19 | ldq_will_succeed_19); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_563 = searcher_is_older_19 | _GEN_502; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_20; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_61 = ldq_addr_20_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_62 = _block_addr_matches_T_60 == _block_addr_matches_T_61; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_20_0 = _block_addr_matches_T_62; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_81 = ldq_addr_20_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_82 = _dword_addr_matches_T_80 == _dword_addr_matches_T_81; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_83 = block_addr_matches_20_0 & _dword_addr_matches_T_82; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_20_0 = _dword_addr_matches_T_83; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_564 = ldq_ld_byte_mask_20 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_40; // @[lsu.scala:1197:46] assign _mask_match_T_40 = _GEN_564; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_40; // @[lsu.scala:1198:46] assign _mask_overlap_T_40 = _GEN_564; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_41 = _mask_match_T_40 == ldq_ld_byte_mask_20; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_20_0 = _mask_match_T_41; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_41 = |_mask_overlap_T_40; // @[lsu.scala:1198:{46,62}] wire mask_overlap_20_0 = _mask_overlap_T_41; // @[lsu.scala:321:49, :1198:62] wire _T_1414 = ldq_executed_20 | ldq_succeeded_20; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1390 = ldq_st_dep_mask_20 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1394 = do_st_search_0 & ldq_valid_20 & ldq_addr_20_valid & _T_1414 & ~ldq_addr_is_virtual_20 & _T_1390[0] & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_80 = ldq_forward_stq_idx_20 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_81 = ldq_forward_stq_idx_20 < l_uop_20_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_82 = _forwarded_is_older_T_80 ^ _forwarded_is_older_T_81; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_83 = lcam_stq_idx_0 < l_uop_20_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_20 = _forwarded_is_older_T_82 ^ _forwarded_is_older_T_83; // @[util.scala:364:{58,72,78}] wire _T_1398 = ~ldq_forward_std_val_20 | ldq_forward_stq_idx_20 != lcam_stq_idx_0 & forwarded_is_older_20; // @[util.scala:364:72] wire _GEN_565 = _T_1394 ? _T_1398 | _GEN_562 | _GEN_559 : _GEN_562 | _GEN_559; // @[lsu.scala:394:59, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23] wire _T_1404 = do_ld_search_0 & ldq_valid_20 & ldq_addr_20_valid & ~ldq_addr_is_virtual_20 & dword_addr_matches_20_0 & mask_overlap_20_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_20 = lcam_younger_load_mask_0[20]; // @[lsu.scala:321:49, :1237:58] wire _T_1423 = ldq_executed_20 & (ldq_succeeded_20 | ldq_will_succeed_20); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_566 = searcher_is_older_20 | _GEN_503; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_21; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_64 = ldq_addr_21_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_65 = _block_addr_matches_T_63 == _block_addr_matches_T_64; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_21_0 = _block_addr_matches_T_65; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_85 = ldq_addr_21_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_86 = _dword_addr_matches_T_84 == _dword_addr_matches_T_85; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_87 = block_addr_matches_21_0 & _dword_addr_matches_T_86; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_21_0 = _dword_addr_matches_T_87; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_567 = ldq_ld_byte_mask_21 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_42; // @[lsu.scala:1197:46] assign _mask_match_T_42 = _GEN_567; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_42; // @[lsu.scala:1198:46] assign _mask_overlap_T_42 = _GEN_567; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_43 = _mask_match_T_42 == ldq_ld_byte_mask_21; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_21_0 = _mask_match_T_43; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_43 = |_mask_overlap_T_42; // @[lsu.scala:1198:{46,62}] wire mask_overlap_21_0 = _mask_overlap_T_43; // @[lsu.scala:321:49, :1198:62] wire _T_1466 = ldq_executed_21 | ldq_succeeded_21; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1442 = ldq_st_dep_mask_21 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_84 = ldq_forward_stq_idx_21 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_85 = ldq_forward_stq_idx_21 < l_uop_21_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_86 = _forwarded_is_older_T_84 ^ _forwarded_is_older_T_85; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_87 = lcam_stq_idx_0 < l_uop_21_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_21 = _forwarded_is_older_T_86 ^ _forwarded_is_older_T_87; // @[util.scala:364:{58,72,78}] wire _GEN_568 = do_st_search_0 & ldq_valid_21 & ldq_addr_21_valid & _T_1466 & ~ldq_addr_is_virtual_21 & _T_1442[0] & dword_addr_matches_21_0 & mask_overlap_21_0 & (~ldq_forward_std_val_21 | ldq_forward_stq_idx_21 != lcam_stq_idx_0 & forwarded_is_older_21); // @[util.scala:364:72] wire _T_1456 = do_ld_search_0 & ldq_valid_21 & ldq_addr_21_valid & ~ldq_addr_is_virtual_21 & dword_addr_matches_21_0 & mask_overlap_21_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_21 = lcam_younger_load_mask_0[21]; // @[lsu.scala:321:49, :1237:58] wire _T_1475 = ldq_executed_21 & (ldq_succeeded_21 | ldq_will_succeed_21); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_569 = searcher_is_older_21 | _GEN_504; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_22; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_67 = ldq_addr_22_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_68 = _block_addr_matches_T_66 == _block_addr_matches_T_67; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_22_0 = _block_addr_matches_T_68; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_89 = ldq_addr_22_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_90 = _dword_addr_matches_T_88 == _dword_addr_matches_T_89; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_91 = block_addr_matches_22_0 & _dword_addr_matches_T_90; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_22_0 = _dword_addr_matches_T_91; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_570 = ldq_ld_byte_mask_22 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_44; // @[lsu.scala:1197:46] assign _mask_match_T_44 = _GEN_570; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_44; // @[lsu.scala:1198:46] assign _mask_overlap_T_44 = _GEN_570; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_45 = _mask_match_T_44 == ldq_ld_byte_mask_22; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_22_0 = _mask_match_T_45; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_45 = |_mask_overlap_T_44; // @[lsu.scala:1198:{46,62}] wire mask_overlap_22_0 = _mask_overlap_T_45; // @[lsu.scala:321:49, :1198:62] wire _T_1518 = ldq_executed_22 | ldq_succeeded_22; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1494 = ldq_st_dep_mask_22 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _T_1498 = do_st_search_0 & ldq_valid_22 & ldq_addr_22_valid & _T_1518 & ~ldq_addr_is_virtual_22 & _T_1494[0] & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1213:57, :1214:57, :1215:57, :1216:{32,57}, :1217:57, :1218:{33,57}, :1219:57] wire _forwarded_is_older_T_88 = ldq_forward_stq_idx_22 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_89 = ldq_forward_stq_idx_22 < l_uop_22_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_90 = _forwarded_is_older_T_88 ^ _forwarded_is_older_T_89; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_91 = lcam_stq_idx_0 < l_uop_22_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_22 = _forwarded_is_older_T_90 ^ _forwarded_is_older_T_91; // @[util.scala:364:{58,72,78}] wire _T_1502 = ~ldq_forward_std_val_22 | ldq_forward_stq_idx_22 != lcam_stq_idx_0 & forwarded_is_older_22; // @[util.scala:364:72] wire _T_1508 = do_ld_search_0 & ldq_valid_22 & ldq_addr_22_valid & ~ldq_addr_is_virtual_22 & dword_addr_matches_22_0 & mask_overlap_22_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_22 = lcam_younger_load_mask_0[22]; // @[lsu.scala:321:49, :1237:58] wire _T_1527 = ldq_executed_22 & (ldq_succeeded_22 | ldq_will_succeed_22); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_571 = searcher_is_older_22 | _GEN_505; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] reg REG_23; // @[lsu.scala:1255:26] wire [33:0] _block_addr_matches_T_70 = ldq_addr_23_bits[39:6]; // @[lsu.scala:220:36, :1195:89] wire _block_addr_matches_T_71 = _block_addr_matches_T_69 == _block_addr_matches_T_70; // @[lsu.scala:1195:{57,73,89}] wire block_addr_matches_23_0 = _block_addr_matches_T_71; // @[lsu.scala:321:49, :1195:73] wire [2:0] _dword_addr_matches_T_93 = ldq_addr_23_bits[5:3]; // @[lsu.scala:220:36, :1196:115] wire _dword_addr_matches_T_94 = _dword_addr_matches_T_92 == _dword_addr_matches_T_93; // @[lsu.scala:1196:{81,100,115}] wire _dword_addr_matches_T_95 = block_addr_matches_23_0 & _dword_addr_matches_T_94; // @[lsu.scala:321:49, :1196:{66,100}] wire dword_addr_matches_23_0 = _dword_addr_matches_T_95; // @[lsu.scala:321:49, :1196:66] wire [7:0] _GEN_572 = ldq_ld_byte_mask_23 & lcam_mask_0; // @[lsu.scala:228:36, :321:49, :1197:46] wire [7:0] _mask_match_T_46; // @[lsu.scala:1197:46] assign _mask_match_T_46 = _GEN_572; // @[lsu.scala:1197:46] wire [7:0] _mask_overlap_T_46; // @[lsu.scala:1198:46] assign _mask_overlap_T_46 = _GEN_572; // @[lsu.scala:1197:46, :1198:46] wire _mask_match_T_47 = _mask_match_T_46 == ldq_ld_byte_mask_23; // @[lsu.scala:228:36, :1197:{46,62}] wire mask_match_23_0 = _mask_match_T_47; // @[lsu.scala:321:49, :1197:62] wire _mask_overlap_T_47 = |_mask_overlap_T_46; // @[lsu.scala:1198:{46,62}] wire mask_overlap_23_0 = _mask_overlap_T_47; // @[lsu.scala:321:49, :1198:62] wire _T_1570 = ldq_executed_23 | ldq_succeeded_23; // @[lsu.scala:223:36, :224:36, :1216:32] wire [23:0] _T_1546 = ldq_st_dep_mask_23 >> _GEN_481; // @[lsu.scala:227:36, :1218:33] wire _forwarded_is_older_T_92 = ldq_forward_stq_idx_23 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_93 = ldq_forward_stq_idx_23 < l_uop_23_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_94 = _forwarded_is_older_T_92 ^ _forwarded_is_older_T_93; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_95 = lcam_stq_idx_0 < l_uop_23_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_23 = _forwarded_is_older_T_94 ^ _forwarded_is_older_T_95; // @[util.scala:364:{58,72,78}] wire _GEN_573 = do_st_search_0 & ldq_valid_23 & ldq_addr_23_valid & _T_1570 & ~ldq_addr_is_virtual_23 & _T_1546[0] & dword_addr_matches_23_0 & mask_overlap_23_0 & (~ldq_forward_std_val_23 | ldq_forward_stq_idx_23 != lcam_stq_idx_0 & forwarded_is_older_23); // @[util.scala:364:72] wire _T_1560 = do_ld_search_0 & ldq_valid_23 & ldq_addr_23_valid & ~ldq_addr_is_virtual_23 & dword_addr_matches_23_0 & mask_overlap_23_0; // @[lsu.scala:218:36, :220:36, :221:36, :321:49, :508:67, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42] wire searcher_is_older_23 = lcam_younger_load_mask_0[23]; // @[lsu.scala:321:49, :1237:58] wire _T_1579 = ldq_executed_23 & (ldq_succeeded_23 | ldq_will_succeed_23); // @[lsu.scala:223:36, :224:36, :325:44, :1253:{30,46}] wire _GEN_574 = searcher_is_older_23 | _GEN_506; // @[lsu.scala:1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:67, :1254:48] wire _GEN_575 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_483)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_483)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_483)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_483)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_483)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_483)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_483)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_483)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_483)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_483)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_483)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_483)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_483)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_483)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_483)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_483)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_483)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_483)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_483)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_483)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_483)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_483)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_483)) & s1_executing_loads_0; // @[lsu.scala:1168:35, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_576 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_484)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_484)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_484)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_484)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_484)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_484)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_484)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_484)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_484)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_484)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_484)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_484)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_484)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_484)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_484)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_484)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_484)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_484)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_484)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_484)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_484)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_484)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_484)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_484)) & s1_executing_loads_1; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_577 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_485)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_485)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_485)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_485)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_485)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_485)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_485)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_485)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_485)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_485)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_485)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_485)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_485)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_485)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_485)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_485)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_485)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_485)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_485)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_485)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_485)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_485)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_485)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_485)) & s1_executing_loads_2; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_578 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_486)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_486)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_486)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_486)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_486)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_486)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_486)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_486)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_486)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_486)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_486)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_486)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_486)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_486)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_486)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_486)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_486)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_486)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_486)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_486)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_486)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_486)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_486)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_486)) & s1_executing_loads_3; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_579 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_487)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_487)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_487)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_487)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_487)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_487)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_487)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_487)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_487)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_487)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_487)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_487)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_487)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_487)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_487)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_487)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_487)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_487)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_487)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_487)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_487)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_487)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_487)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_487)) & s1_executing_loads_4; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_580 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_488)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_488)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_488)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_488)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_488)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_488)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_488)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_488)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_488)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_488)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_488)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_488)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_488)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_488)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_488)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_488)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_488)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_488)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_488)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_488)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_488)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_488)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_488)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_488)) & s1_executing_loads_5; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_581 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_489)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_489)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_489)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_489)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_489)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_489)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_489)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_489)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_489)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_489)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_489)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_489)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_489)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_489)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_489)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_489)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_489)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_489)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_489)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_489)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_489)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_489)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_489)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_489)) & s1_executing_loads_6; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_582 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_490)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_490)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_490)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_490)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_490)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_490)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_490)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_490)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_490)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_490)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_490)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_490)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_490)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_490)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_490)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_490)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_490)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_490)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_490)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_490)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_490)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_490)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_490)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_490)) & s1_executing_loads_7; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_583 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_491)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_491)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_491)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_491)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_491)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_491)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_491)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_491)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_491)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_491)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_491)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_491)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_491)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_491)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_491)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_491)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_491)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_491)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_491)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_491)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_491)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_491)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_491)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_491)) & s1_executing_loads_8; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_584 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_492)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_492)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_492)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_492)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_492)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_492)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_492)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_492)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_492)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_492)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_492)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_492)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_492)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_492)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_492)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_492)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_492)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_492)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_492)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_492)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_492)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_492)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_492)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_492)) & s1_executing_loads_9; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_585 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_493)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_493)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_493)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_493)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_493)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_493)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_493)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_493)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_493)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_493)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_493)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_493)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_493)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_493)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_493)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_493)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_493)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_493)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_493)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_493)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_493)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_493)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_493)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_493)) & s1_executing_loads_10; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_586 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_494)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_494)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_494)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_494)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_494)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_494)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_494)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_494)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_494)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_494)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_494)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_494)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_494)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_494)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_494)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_494)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_494)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_494)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_494)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_494)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_494)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_494)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_494)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_494)) & s1_executing_loads_11; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_587 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_495)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_495)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_495)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_495)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_495)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_495)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_495)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_495)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_495)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_495)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_495)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_495)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_495)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_495)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_495)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_495)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_495)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_495)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_495)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_495)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_495)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_495)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_495)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_495)) & s1_executing_loads_12; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_588 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_496)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_496)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_496)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_496)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_496)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_496)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_496)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_496)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_496)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_496)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_496)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_496)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_496)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_496)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_496)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_496)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_496)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_496)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_496)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_496)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_496)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_496)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_496)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_496)) & s1_executing_loads_13; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_589 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_497)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_497)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_497)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_497)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_497)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_497)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_497)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_497)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_497)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_497)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_497)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_497)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_497)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_497)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_497)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_497)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_497)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_497)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_497)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_497)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_497)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_497)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_497)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_497)) & s1_executing_loads_14; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_590 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_498)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_498)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_498)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_498)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_498)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_498)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_498)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_498)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_498)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_498)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_498)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_498)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_498)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_498)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_498)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_498)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_498)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_498)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_498)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_498)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_498)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_498)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_498)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_498)) & s1_executing_loads_15; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_591 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_499)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_499)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_499)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_499)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_499)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_499)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_499)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_499)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_499)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_499)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_499)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_499)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_499)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_499)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_499)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_499)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_499)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_499)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_499)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_499)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_499)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_499)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_499)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_499)) & s1_executing_loads_16; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_592 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_500)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_500)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_500)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_500)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_500)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_500)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_500)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_500)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_500)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_500)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_500)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_500)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_500)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_500)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_500)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_500)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_500)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_500)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_500)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_500)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_500)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_500)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_500)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_500)) & s1_executing_loads_17; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_593 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_501)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_501)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_501)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_501)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_501)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_501)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_501)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_501)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_501)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_501)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_501)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_501)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_501)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_501)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_501)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_501)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_501)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_501)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_501)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_501)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_501)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_501)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_501)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_501)) & s1_executing_loads_18; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_594 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_502)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_502)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_502)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_502)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_502)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_502)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_502)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_502)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_502)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_502)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_502)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_502)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_502)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_502)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_502)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_502)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_502)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_502)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_502)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_502)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_502)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_502)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_502)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_502)) & s1_executing_loads_19; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_595 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_503)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_503)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_503)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_503)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_503)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_503)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_503)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_503)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_503)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_503)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_503)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_503)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_503)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_503)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_503)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_503)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_503)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_503)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_503)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_503)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_503)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_503)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_503)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_503)) & s1_executing_loads_20; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_596 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_504)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_504)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_504)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_504)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_504)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_504)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_504)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_504)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_504)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_504)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_504)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_504)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_504)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_504)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_504)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_504)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_504)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_504)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_504)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_504)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_504)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_504)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_504)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_504)) & s1_executing_loads_21; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_597 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_505)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_505)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_505)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_505)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_505)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_505)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_505)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_505)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_505)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_505)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_505)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_505)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_505)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_505)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_505)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_505)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_505)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_505)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_505)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_505)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_505)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_505)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_505)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_505)) & s1_executing_loads_22; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] wire _GEN_598 = (~_T_1560 | _GEN_574 | ~(~_T_1579 & _GEN_506)) & (~_T_1508 | _GEN_571 | ~(~_T_1527 & _GEN_506)) & (~_T_1456 | _GEN_569 | ~(~_T_1475 & _GEN_506)) & (~_T_1404 | _GEN_566 | ~(~_T_1423 & _GEN_506)) & (~_T_1352 | _GEN_563 | ~(~_T_1371 & _GEN_506)) & (~_T_1300 | _GEN_560 | ~(~_T_1319 & _GEN_506)) & (~_T_1248 | _GEN_557 | ~(~_T_1267 & _GEN_506)) & (~_T_1196 | _GEN_554 | ~(~_T_1215 & _GEN_506)) & (~_T_1144 | _GEN_551 | ~(~_T_1163 & _GEN_506)) & (~_T_1092 | _GEN_548 | ~(~_T_1111 & _GEN_506)) & (~_T_1040 | _GEN_545 | ~(~_T_1059 & _GEN_506)) & (~_T_988 | _GEN_542 | ~(~_T_1007 & _GEN_506)) & (~_T_936 | _GEN_539 | ~(~_T_955 & _GEN_506)) & (~_T_884 | _GEN_536 | ~(~_T_903 & _GEN_506)) & (~_T_832 | _GEN_533 | ~(~_T_851 & _GEN_506)) & (~_T_780 | _GEN_530 | ~(~_T_799 & _GEN_506)) & (~_T_728 | _GEN_527 | ~(~_T_747 & _GEN_506)) & (~_T_676 | _GEN_524 | ~(~_T_695 & _GEN_506)) & (~_T_624 | _GEN_521 | ~(~_T_643 & _GEN_506)) & (~_T_572 | _GEN_518 | ~(~_T_591 & _GEN_506)) & (~_T_520 | _GEN_515 | ~(~_T_539 & _GEN_506)) & (~_T_468 | _GEN_512 | ~(~_T_487 & _GEN_506)) & (~_T_416 | _GEN_509 | ~(~_T_435 & _GEN_506)) & (~_T_364 | searcher_is_older | ~((|lcam_ldq_idx_0) & ~_T_383 & _GEN_506)) & s1_executing_loads_23; // @[lsu.scala:321:49, :1168:35, :1169:36, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1254:48] reg REG_24; // @[lsu.scala:1255:26] wire _GEN_599 = _T_1560 & ~_GEN_574 & ~_T_1579 & REG_24 & ~fired_load_agen_0 | _T_1508 & ~_GEN_571 & ~_T_1527 & REG_23 & ~fired_load_agen_0 | _T_1456 & ~_GEN_569 & ~_T_1475 & REG_22 & ~fired_load_agen_0 | _T_1404 & ~_GEN_566 & ~_T_1423 & REG_21 & ~fired_load_agen_0 | _T_1352 & ~_GEN_563 & ~_T_1371 & REG_20 & ~fired_load_agen_0 | _T_1300 & ~_GEN_560 & ~_T_1319 & REG_19 & ~fired_load_agen_0 | _T_1248 & ~_GEN_557 & ~_T_1267 & REG_18 & ~fired_load_agen_0 | _T_1196 & ~_GEN_554 & ~_T_1215 & REG_17 & ~fired_load_agen_0 | _T_1144 & ~_GEN_551 & ~_T_1163 & REG_16 & ~fired_load_agen_0 | _T_1092 & ~_GEN_548 & ~_T_1111 & REG_15 & ~fired_load_agen_0 | _T_1040 & ~_GEN_545 & ~_T_1059 & REG_14 & ~fired_load_agen_0 | _T_988 & ~_GEN_542 & ~_T_1007 & REG_13 & ~fired_load_agen_0 | _T_936 & ~_GEN_539 & ~_T_955 & REG_12 & ~fired_load_agen_0 | _T_884 & ~_GEN_536 & ~_T_903 & REG_11 & ~fired_load_agen_0 | _T_832 & ~_GEN_533 & ~_T_851 & REG_10 & ~fired_load_agen_0 | _T_780 & ~_GEN_530 & ~_T_799 & REG_9 & ~fired_load_agen_0 | _T_728 & ~_GEN_527 & ~_T_747 & REG_8 & ~fired_load_agen_0 | _T_676 & ~_GEN_524 & ~_T_695 & REG_7 & ~fired_load_agen_0 | _T_624 & ~_GEN_521 & ~_T_643 & REG_6 & ~fired_load_agen_0 | _T_572 & ~_GEN_518 & ~_T_591 & REG_5 & ~fired_load_agen_0 | _T_520 & ~_GEN_515 & ~_T_539 & REG_4 & ~fired_load_agen_0 | _T_468 & ~_GEN_512 & ~_T_487 & REG_3 & ~fired_load_agen_0 | _T_416 & ~_GEN_509 & ~_T_435 & REG_2 & ~fired_load_agen_0 | _T_364 & ~searcher_is_older & (|lcam_ldq_idx_0) & ~_T_383 & REG_1 & ~fired_load_agen_0 | io_dmem_s1_kill_0_REG; // @[lsu.scala:321:49, :893:{24,34}, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1255:{26,61,64,85}, :1256:48] wire _GEN_600 = _T_1560 & ~_GEN_574 & ~_T_1579 | _T_1508 & ~_GEN_571 & ~_T_1527 | _T_1456 & ~_GEN_569 & ~_T_1475 | _T_1404 & ~_GEN_566 & ~_T_1423 | _T_1352 & ~_GEN_563 & ~_T_1371 | _T_1300 & ~_GEN_560 & ~_T_1319 | _T_1248 & ~_GEN_557 & ~_T_1267 | _T_1196 & ~_GEN_554 & ~_T_1215 | _T_1144 & ~_GEN_551 & ~_T_1163 | _T_1092 & ~_GEN_548 & ~_T_1111 | _T_1040 & ~_GEN_545 & ~_T_1059 | _T_988 & ~_GEN_542 & ~_T_1007 | _T_936 & ~_GEN_539 & ~_T_955 | _T_884 & ~_GEN_536 & ~_T_903 | _T_832 & ~_GEN_533 & ~_T_851 | _T_780 & ~_GEN_530 & ~_T_799 | _T_728 & ~_GEN_527 & ~_T_747 | _T_676 & ~_GEN_524 & ~_T_695 | _T_624 & ~_GEN_521 & ~_T_643 | _T_572 & ~_GEN_518 & ~_T_591 | _T_520 & ~_GEN_515 & ~_T_539 | _T_468 & ~_GEN_512 & ~_T_487 | _T_416 & ~_GEN_509 & ~_T_435 | _T_364 & ~searcher_is_older & (|lcam_ldq_idx_0) & ~_T_383; // @[lsu.scala:321:49, :893:24, :1159:30, :1230:42, :1231:42, :1232:42, :1233:42, :1234:42, :1235:37, :1237:58, :1239:34, :1249:{38,47}, :1253:{17,30,67}, :1258:48] wire [36:0] _nack_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51] wire [36:0] _forward_dword_addr_matches_T = lcam_addr_0[39:3]; // @[lsu.scala:321:49, :1270:51, :1289:54] wire [36:0] _nack_dword_addr_matches_T_1 = io_dmem_nack_0_bits_addr_0[39:3]; // @[lsu.scala:211:7, :1270:89] wire nack_dword_addr_matches = _nack_dword_addr_matches_T == _nack_dword_addr_matches_T_1; // @[lsu.scala:1270:{51,57,89}] wire [7:0] nack_mask; // @[lsu.scala:1951:22] wire _nack_mask_mask_T = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h0; // @[lsu.scala:211:7, :1953:26] wire [2:0] _nack_mask_mask_T_1 = io_dmem_nack_0_bits_addr_0[2:0]; // @[lsu.scala:211:7, :1953:55] wire [14:0] _nack_mask_mask_T_2 = 15'h1 << _nack_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _nack_mask_mask_T_3 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h1; // @[lsu.scala:211:7, :1954:26] wire [1:0] _nack_mask_mask_T_4 = io_dmem_nack_0_bits_addr_0[2:1]; // @[lsu.scala:211:7, :1954:56] wire [2:0] _nack_mask_mask_T_5 = {_nack_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _nack_mask_mask_T_6 = 15'h3 << _nack_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _nack_mask_mask_T_7 = io_dmem_nack_0_bits_uop_mem_size_0 == 2'h2; // @[lsu.scala:211:7, :1955:26] wire _nack_mask_mask_T_8 = io_dmem_nack_0_bits_addr_0[2]; // @[lsu.scala:211:7, :1955:46] wire [7:0] _nack_mask_mask_T_9 = _nack_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _nack_mask_mask_T_10 = &io_dmem_nack_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1956:26] wire [7:0] _nack_mask_mask_T_12 = _nack_mask_mask_T_7 ? _nack_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_13 = _nack_mask_mask_T_3 ? _nack_mask_mask_T_6 : {7'h0, _nack_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _nack_mask_mask_T_14 = _nack_mask_mask_T ? _nack_mask_mask_T_2 : _nack_mask_mask_T_13; // @[Mux.scala:126:16] assign nack_mask = _nack_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _nack_mask_overlap_T = nack_mask & lcam_mask_0; // @[lsu.scala:321:49, :1272:42, :1951:22] wire nack_mask_overlap = |_nack_mask_overlap_T; // @[lsu.scala:1272:{42,58}] wire _T_1596 = do_ld_search_0 & io_dmem_nack_0_valid_0 & io_dmem_nack_0_bits_uop_uses_ldq_0 & nack_dword_addr_matches & nack_mask_overlap & (io_dmem_nack_0_bits_uop_ldq_idx_0 < lcam_ldq_idx_0 ^ io_dmem_nack_0_bits_uop_ldq_idx_0 < ldq_head ^ _lcam_younger_load_mask_T); // @[util.scala:364:{52,58,64,72}, :372:11] wire _GEN_601 = _T_1596 & _GEN_483; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_602 = _T_1596 & _GEN_484; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_603 = _T_1596 & _GEN_485; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_604 = _T_1596 & _GEN_486; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_605 = _T_1596 & _GEN_487; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_606 = _T_1596 & _GEN_488; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_607 = _T_1596 & _GEN_489; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_608 = _T_1596 & _GEN_490; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_609 = _T_1596 & _GEN_491; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_610 = _T_1596 & _GEN_492; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_611 = _T_1596 & _GEN_493; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_612 = _T_1596 & _GEN_494; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_613 = _T_1596 & _GEN_495; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_614 = _T_1596 & _GEN_496; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_615 = _T_1596 & _GEN_497; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_616 = _T_1596 & _GEN_498; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_617 = _T_1596 & _GEN_499; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_618 = _T_1596 & _GEN_500; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_619 = _T_1596 & _GEN_501; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_620 = _T_1596 & _GEN_502; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_621 = _T_1596 & _GEN_503; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_622 = _T_1596 & _GEN_504; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_623 = _T_1596 & _GEN_505; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] wire _GEN_624 = _T_1596 & _GEN_506; // @[lsu.scala:1235:37, :1254:48, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1279:41] reg REG_25; // @[lsu.scala:1280:22] wire _GEN_625 = _T_1596 & REG_25 & ~fired_load_agen_0; // @[lsu.scala:321:49, :1235:37, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1280:{22,57,60,81}, :1281:30] wire [36:0] _forward_dword_addr_matches_T_1 = wb_ldst_forward_ld_addr_0[39:3]; // @[lsu.scala:1175:41, :1289:91] wire forward_dword_addr_matches = _forward_dword_addr_matches_T == _forward_dword_addr_matches_T_1; // @[lsu.scala:1289:{54,59,91}] wire [7:0] forward_mask; // @[lsu.scala:1951:22] wire _forward_mask_mask_T = wb_ldst_forward_e_0_uop_mem_size == 2'h0; // @[lsu.scala:321:49, :1953:26] wire [2:0] _forward_mask_mask_T_1 = wb_ldst_forward_ld_addr_0[2:0]; // @[lsu.scala:1175:41, :1953:55] wire [14:0] _forward_mask_mask_T_2 = 15'h1 << _forward_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _forward_mask_mask_T_3 = wb_ldst_forward_e_0_uop_mem_size == 2'h1; // @[lsu.scala:321:49, :1954:26] wire [1:0] _forward_mask_mask_T_4 = wb_ldst_forward_ld_addr_0[2:1]; // @[lsu.scala:1175:41, :1954:56] wire [2:0] _forward_mask_mask_T_5 = {_forward_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _forward_mask_mask_T_6 = 15'h3 << _forward_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _forward_mask_mask_T_7 = wb_ldst_forward_e_0_uop_mem_size == 2'h2; // @[lsu.scala:321:49, :1955:26] wire _forward_mask_mask_T_8 = wb_ldst_forward_ld_addr_0[2]; // @[lsu.scala:1175:41, :1955:46] wire _iresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T = wb_ldst_forward_ld_addr_0[2]; // @[AMOALU.scala:42:29] wire [7:0] _forward_mask_mask_T_9 = _forward_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _forward_mask_mask_T_10 = &wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1956:26] wire [7:0] _forward_mask_mask_T_12 = _forward_mask_mask_T_7 ? _forward_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_13 = _forward_mask_mask_T_3 ? _forward_mask_mask_T_6 : {7'h0, _forward_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _forward_mask_mask_T_14 = _forward_mask_mask_T ? _forward_mask_mask_T_2 : _forward_mask_mask_T_13; // @[Mux.scala:126:16] assign forward_mask = _forward_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire [7:0] _forward_mask_overlap_T = forward_mask & lcam_mask_0; // @[lsu.scala:321:49, :1291:48, :1951:22] wire forward_mask_overlap = |_forward_mask_overlap_T; // @[lsu.scala:1291:{48,64}] wire _T_1612 = do_ld_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & wb_ldst_forward_e_0_observed & (lcam_ldq_idx_0 < wb_ldst_forward_ldq_idx_0 ^ _lcam_younger_load_mask_T ^ wb_ldst_forward_ldq_idx_0 < ldq_head); // @[util.scala:364:{52,58,72,78}, :372:11] wire _GEN_626 = wb_ldst_forward_ldq_idx_0 == 5'h0; // @[lsu.scala:1174:41, :1298:53] wire _GEN_627 = wb_ldst_forward_ldq_idx_0 == 5'h1; // @[lsu.scala:1174:41, :1298:53] wire _GEN_628 = wb_ldst_forward_ldq_idx_0 == 5'h2; // @[lsu.scala:1174:41, :1298:53] wire _GEN_629 = wb_ldst_forward_ldq_idx_0 == 5'h3; // @[lsu.scala:1174:41, :1298:53] wire _GEN_630 = wb_ldst_forward_ldq_idx_0 == 5'h4; // @[lsu.scala:1174:41, :1298:53] wire _GEN_631 = wb_ldst_forward_ldq_idx_0 == 5'h5; // @[lsu.scala:1174:41, :1298:53] wire _GEN_632 = wb_ldst_forward_ldq_idx_0 == 5'h6; // @[lsu.scala:1174:41, :1298:53] wire _GEN_633 = wb_ldst_forward_ldq_idx_0 == 5'h7; // @[lsu.scala:1174:41, :1298:53] wire _GEN_634 = wb_ldst_forward_ldq_idx_0 == 5'h8; // @[lsu.scala:1174:41, :1298:53] wire _GEN_635 = wb_ldst_forward_ldq_idx_0 == 5'h9; // @[lsu.scala:1174:41, :1298:53] wire _GEN_636 = wb_ldst_forward_ldq_idx_0 == 5'hA; // @[lsu.scala:1174:41, :1298:53] wire _GEN_637 = wb_ldst_forward_ldq_idx_0 == 5'hB; // @[lsu.scala:1174:41, :1298:53] wire _GEN_638 = wb_ldst_forward_ldq_idx_0 == 5'hC; // @[lsu.scala:1174:41, :1298:53] wire _GEN_639 = wb_ldst_forward_ldq_idx_0 == 5'hD; // @[lsu.scala:1174:41, :1298:53] wire _GEN_640 = wb_ldst_forward_ldq_idx_0 == 5'hE; // @[lsu.scala:1174:41, :1298:53] wire _GEN_641 = wb_ldst_forward_ldq_idx_0 == 5'hF; // @[lsu.scala:1174:41, :1298:53] wire _GEN_642 = wb_ldst_forward_ldq_idx_0 == 5'h10; // @[lsu.scala:1174:41, :1298:53] wire _GEN_643 = wb_ldst_forward_ldq_idx_0 == 5'h11; // @[lsu.scala:1174:41, :1298:53] wire _GEN_644 = wb_ldst_forward_ldq_idx_0 == 5'h12; // @[lsu.scala:1174:41, :1298:53] wire _GEN_645 = wb_ldst_forward_ldq_idx_0 == 5'h13; // @[lsu.scala:1174:41, :1298:53] wire _GEN_646 = wb_ldst_forward_ldq_idx_0 == 5'h14; // @[lsu.scala:1174:41, :1298:53] wire _GEN_647 = wb_ldst_forward_ldq_idx_0 == 5'h15; // @[lsu.scala:1174:41, :1298:53] wire _GEN_648 = wb_ldst_forward_ldq_idx_0 == 5'h16; // @[lsu.scala:1174:41, :1298:53] wire _GEN_649 = wb_ldst_forward_ldq_idx_0 == 5'h17; // @[lsu.scala:1174:41, :1298:53] wire _forwarded_is_older_T_96 = wb_ldst_forward_stq_idx_0 < lcam_stq_idx_0; // @[util.scala:364:52] wire _forwarded_is_older_T_97 = wb_ldst_forward_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:64] wire _forwarded_is_older_T_98 = _forwarded_is_older_T_96 ^ _forwarded_is_older_T_97; // @[util.scala:364:{52,58,64}] wire _forwarded_is_older_T_99 = lcam_stq_idx_0 < wb_ldst_forward_e_0_uop_stq_idx; // @[util.scala:364:78] wire forwarded_is_older_24 = _forwarded_is_older_T_98 ^ _forwarded_is_older_T_99; // @[util.scala:364:{58,72,78}] wire [23:0] _T_1618 = wb_ldst_forward_e_0_st_dep_mask >> _GEN_481; // @[lsu.scala:321:49, :1218:33, :1308:46] wire _T_1621 = do_st_search_0 & wb_ldst_forward_valid_0 & forward_dword_addr_matches & forward_mask_overlap & _T_1618[0] & forwarded_is_older_24; // @[util.scala:364:72] assign failed_load = _T_1621 | _T_1612 | _GEN_573 | (_T_1498 ? _T_1502 | _GEN_568 | _GEN_565 : _GEN_568 | _GEN_565); // @[lsu.scala:394:59, :1178:29, :1213:57, :1214:57, :1215:57, :1216:57, :1217:57, :1218:57, :1219:57, :1220:37, :1224:34, :1225:76, :1226:29, :1227:23, :1292:47, :1293:47, :1294:47, :1295:47, :1296:47, :1297:78, :1299:21, :1304:64, :1305:64, :1306:64, :1307:64, :1308:64, :1309:33, :1311:21] wire _addr_matches_0_0_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_1_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_2_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_3_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_4_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_5_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_6_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_7_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_8_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_9_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_10_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_11_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_12_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_13_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_14_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_15_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_16_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_17_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_18_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_19_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_20_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_21_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_22_T_1; // @[lsu.scala:1334:53] wire _addr_matches_0_23_T_1; // @[lsu.scala:1334:53] wire addr_matches_0_0; // @[lsu.scala:1316:29] wire addr_matches_0_1; // @[lsu.scala:1316:29] wire addr_matches_0_2; // @[lsu.scala:1316:29] wire addr_matches_0_3; // @[lsu.scala:1316:29] wire addr_matches_0_4; // @[lsu.scala:1316:29] wire addr_matches_0_5; // @[lsu.scala:1316:29] wire addr_matches_0_6; // @[lsu.scala:1316:29] wire addr_matches_0_7; // @[lsu.scala:1316:29] wire addr_matches_0_8; // @[lsu.scala:1316:29] wire addr_matches_0_9; // @[lsu.scala:1316:29] wire addr_matches_0_10; // @[lsu.scala:1316:29] wire addr_matches_0_11; // @[lsu.scala:1316:29] wire addr_matches_0_12; // @[lsu.scala:1316:29] wire addr_matches_0_13; // @[lsu.scala:1316:29] wire addr_matches_0_14; // @[lsu.scala:1316:29] wire addr_matches_0_15; // @[lsu.scala:1316:29] wire addr_matches_0_16; // @[lsu.scala:1316:29] wire addr_matches_0_17; // @[lsu.scala:1316:29] wire addr_matches_0_18; // @[lsu.scala:1316:29] wire addr_matches_0_19; // @[lsu.scala:1316:29] wire addr_matches_0_20; // @[lsu.scala:1316:29] wire addr_matches_0_21; // @[lsu.scala:1316:29] wire addr_matches_0_22; // @[lsu.scala:1316:29] wire addr_matches_0_23; // @[lsu.scala:1316:29] wire _forward_matches_0_0_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_1_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_2_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_3_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_4_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_5_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_6_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_7_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_8_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_9_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_10_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_11_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_12_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_13_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_14_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_15_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_16_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_17_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_18_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_19_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_20_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_21_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_22_T_2; // @[lsu.scala:1335:67] wire _forward_matches_0_23_T_2; // @[lsu.scala:1335:67] wire forward_matches_0_0; // @[lsu.scala:1317:29] wire forward_matches_0_1; // @[lsu.scala:1317:29] wire forward_matches_0_2; // @[lsu.scala:1317:29] wire forward_matches_0_3; // @[lsu.scala:1317:29] wire forward_matches_0_4; // @[lsu.scala:1317:29] wire forward_matches_0_5; // @[lsu.scala:1317:29] wire forward_matches_0_6; // @[lsu.scala:1317:29] wire forward_matches_0_7; // @[lsu.scala:1317:29] wire forward_matches_0_8; // @[lsu.scala:1317:29] wire forward_matches_0_9; // @[lsu.scala:1317:29] wire forward_matches_0_10; // @[lsu.scala:1317:29] wire forward_matches_0_11; // @[lsu.scala:1317:29] wire forward_matches_0_12; // @[lsu.scala:1317:29] wire forward_matches_0_13; // @[lsu.scala:1317:29] wire forward_matches_0_14; // @[lsu.scala:1317:29] wire forward_matches_0_15; // @[lsu.scala:1317:29] wire forward_matches_0_16; // @[lsu.scala:1317:29] wire forward_matches_0_17; // @[lsu.scala:1317:29] wire forward_matches_0_18; // @[lsu.scala:1317:29] wire forward_matches_0_19; // @[lsu.scala:1317:29] wire forward_matches_0_20; // @[lsu.scala:1317:29] wire forward_matches_0_21; // @[lsu.scala:1317:29] wire forward_matches_0_22; // @[lsu.scala:1317:29] wire forward_matches_0_23; // @[lsu.scala:1317:29] wire _prs2_matches_0_0_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_1_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_2_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_3_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_4_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_5_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_6_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_7_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_8_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_9_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_10_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_11_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_12_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_13_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_14_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_15_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_16_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_17_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_18_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_19_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_20_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_21_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_22_T_3; // @[lsu.scala:1338:58] wire _prs2_matches_0_23_T_3; // @[lsu.scala:1338:58] wire prs2_matches_0_0; // @[lsu.scala:1318:29] wire prs2_matches_0_1; // @[lsu.scala:1318:29] wire prs2_matches_0_2; // @[lsu.scala:1318:29] wire prs2_matches_0_3; // @[lsu.scala:1318:29] wire prs2_matches_0_4; // @[lsu.scala:1318:29] wire prs2_matches_0_5; // @[lsu.scala:1318:29] wire prs2_matches_0_6; // @[lsu.scala:1318:29] wire prs2_matches_0_7; // @[lsu.scala:1318:29] wire prs2_matches_0_8; // @[lsu.scala:1318:29] wire prs2_matches_0_9; // @[lsu.scala:1318:29] wire prs2_matches_0_10; // @[lsu.scala:1318:29] wire prs2_matches_0_11; // @[lsu.scala:1318:29] wire prs2_matches_0_12; // @[lsu.scala:1318:29] wire prs2_matches_0_13; // @[lsu.scala:1318:29] wire prs2_matches_0_14; // @[lsu.scala:1318:29] wire prs2_matches_0_15; // @[lsu.scala:1318:29] wire prs2_matches_0_16; // @[lsu.scala:1318:29] wire prs2_matches_0_17; // @[lsu.scala:1318:29] wire prs2_matches_0_18; // @[lsu.scala:1318:29] wire prs2_matches_0_19; // @[lsu.scala:1318:29] wire prs2_matches_0_20; // @[lsu.scala:1318:29] wire prs2_matches_0_21; // @[lsu.scala:1318:29] wire prs2_matches_0_22; // @[lsu.scala:1318:29] wire prs2_matches_0_23; // @[lsu.scala:1318:29] wire [7:0] write_mask; // @[lsu.scala:1951:22] wire _write_mask_mask_T = s_uop_3_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_1 = stq_addr_0_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_2 = 15'h1 << _write_mask_mask_T_1; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_3 = s_uop_3_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_4 = stq_addr_0_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_5 = {_write_mask_mask_T_4, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_6 = 15'h3 << _write_mask_mask_T_5; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_7 = s_uop_3_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_8 = stq_addr_0_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_9 = _write_mask_mask_T_8 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_10 = &s_uop_3_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_12 = _write_mask_mask_T_7 ? _write_mask_mask_T_9 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_13 = _write_mask_mask_T_3 ? _write_mask_mask_T_6 : {7'h0, _write_mask_mask_T_12}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_14 = _write_mask_mask_T ? _write_mask_mask_T_2 : _write_mask_mask_T_13; // @[Mux.scala:126:16] assign write_mask = _write_mask_mask_T_14[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_96 = ~s_uop_3_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_97 = stq_addr_0_valid & _dword_addr_matches_T_96; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_98 = ~stq_addr_is_virtual_0; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_99 = _dword_addr_matches_T_97 & _dword_addr_matches_T_98; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_100 = stq_addr_0_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire [28:0] _dword_addr_matches_T_101 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_108 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_115 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_122 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_129 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_136 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_143 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_150 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_157 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_164 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_171 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_178 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_185 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_192 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_199 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_206 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_213 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_220 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_227 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_234 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_241 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_248 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_255 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire [28:0] _dword_addr_matches_T_262 = lcam_addr_0[31:3]; // @[lsu.scala:321:49, :1331:81] wire _dword_addr_matches_T_102 = _dword_addr_matches_T_100 == _dword_addr_matches_T_101; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_24 = _dword_addr_matches_T_99 & _dword_addr_matches_T_102; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union = lcam_mask_0 & write_mask; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_0_T = |mask_union; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_0_T_1 = _addr_matches_0_0_T & dword_addr_matches_24; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_0 = _addr_matches_0_0_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_0_T = addr_matches_0_0 & stq_data_0_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_0_T_1 = mask_union == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_0_T_2 = _forward_matches_0_0_T & _forward_matches_0_0_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_0 = _forward_matches_0_0_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_0_T = s_uop_3_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_0_T_1 = s_uop_3_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_0_T_2 = _prs2_matches_0_0_T & _prs2_matches_0_0_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_0_T_3 = _prs2_matches_0_0_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_0 = _prs2_matches_0_0_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_1; // @[lsu.scala:1951:22] wire _write_mask_mask_T_15 = s_uop_4_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_16 = stq_addr_1_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_17 = 15'h1 << _write_mask_mask_T_16; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_18 = s_uop_4_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_19 = stq_addr_1_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_20 = {_write_mask_mask_T_19, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_21 = 15'h3 << _write_mask_mask_T_20; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_22 = s_uop_4_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_23 = stq_addr_1_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_24 = _write_mask_mask_T_23 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_25 = &s_uop_4_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_27 = _write_mask_mask_T_22 ? _write_mask_mask_T_24 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_28 = _write_mask_mask_T_18 ? _write_mask_mask_T_21 : {7'h0, _write_mask_mask_T_27}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_29 = _write_mask_mask_T_15 ? _write_mask_mask_T_17 : _write_mask_mask_T_28; // @[Mux.scala:126:16] assign write_mask_1 = _write_mask_mask_T_29[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_103 = ~s_uop_4_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_104 = stq_addr_1_valid & _dword_addr_matches_T_103; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_105 = ~stq_addr_is_virtual_1; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_106 = _dword_addr_matches_T_104 & _dword_addr_matches_T_105; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_107 = stq_addr_1_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_109 = _dword_addr_matches_T_107 == _dword_addr_matches_T_108; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_25 = _dword_addr_matches_T_106 & _dword_addr_matches_T_109; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_1 = lcam_mask_0 & write_mask_1; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_1_T = |mask_union_1; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_1_T_1 = _addr_matches_0_1_T & dword_addr_matches_25; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_1 = _addr_matches_0_1_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_1_T = addr_matches_0_1 & stq_data_1_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_1_T_1 = mask_union_1 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_1_T_2 = _forward_matches_0_1_T & _forward_matches_0_1_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_1 = _forward_matches_0_1_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_1_T = s_uop_4_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_1_T_1 = s_uop_4_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_1_T_2 = _prs2_matches_0_1_T & _prs2_matches_0_1_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_1_T_3 = _prs2_matches_0_1_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_1 = _prs2_matches_0_1_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_2; // @[lsu.scala:1951:22] wire _write_mask_mask_T_30 = s_uop_5_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_31 = stq_addr_2_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_32 = 15'h1 << _write_mask_mask_T_31; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_33 = s_uop_5_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_34 = stq_addr_2_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_35 = {_write_mask_mask_T_34, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_36 = 15'h3 << _write_mask_mask_T_35; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_37 = s_uop_5_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_38 = stq_addr_2_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_39 = _write_mask_mask_T_38 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_40 = &s_uop_5_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_42 = _write_mask_mask_T_37 ? _write_mask_mask_T_39 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_43 = _write_mask_mask_T_33 ? _write_mask_mask_T_36 : {7'h0, _write_mask_mask_T_42}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_44 = _write_mask_mask_T_30 ? _write_mask_mask_T_32 : _write_mask_mask_T_43; // @[Mux.scala:126:16] assign write_mask_2 = _write_mask_mask_T_44[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_110 = ~s_uop_5_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_111 = stq_addr_2_valid & _dword_addr_matches_T_110; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_112 = ~stq_addr_is_virtual_2; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_113 = _dword_addr_matches_T_111 & _dword_addr_matches_T_112; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_114 = stq_addr_2_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_116 = _dword_addr_matches_T_114 == _dword_addr_matches_T_115; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_26 = _dword_addr_matches_T_113 & _dword_addr_matches_T_116; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_2 = lcam_mask_0 & write_mask_2; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_2_T = |mask_union_2; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_2_T_1 = _addr_matches_0_2_T & dword_addr_matches_26; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_2 = _addr_matches_0_2_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_2_T = addr_matches_0_2 & stq_data_2_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_2_T_1 = mask_union_2 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_2_T_2 = _forward_matches_0_2_T & _forward_matches_0_2_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_2 = _forward_matches_0_2_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_2_T = s_uop_5_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_2_T_1 = s_uop_5_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_2_T_2 = _prs2_matches_0_2_T & _prs2_matches_0_2_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_2_T_3 = _prs2_matches_0_2_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_2 = _prs2_matches_0_2_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_3; // @[lsu.scala:1951:22] wire _write_mask_mask_T_45 = s_uop_6_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_46 = stq_addr_3_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_47 = 15'h1 << _write_mask_mask_T_46; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_48 = s_uop_6_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_49 = stq_addr_3_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_50 = {_write_mask_mask_T_49, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_51 = 15'h3 << _write_mask_mask_T_50; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_52 = s_uop_6_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_53 = stq_addr_3_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_54 = _write_mask_mask_T_53 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_55 = &s_uop_6_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_57 = _write_mask_mask_T_52 ? _write_mask_mask_T_54 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_58 = _write_mask_mask_T_48 ? _write_mask_mask_T_51 : {7'h0, _write_mask_mask_T_57}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_59 = _write_mask_mask_T_45 ? _write_mask_mask_T_47 : _write_mask_mask_T_58; // @[Mux.scala:126:16] assign write_mask_3 = _write_mask_mask_T_59[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_117 = ~s_uop_6_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_118 = stq_addr_3_valid & _dword_addr_matches_T_117; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_119 = ~stq_addr_is_virtual_3; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_120 = _dword_addr_matches_T_118 & _dword_addr_matches_T_119; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_121 = stq_addr_3_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_123 = _dword_addr_matches_T_121 == _dword_addr_matches_T_122; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_27 = _dword_addr_matches_T_120 & _dword_addr_matches_T_123; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_3 = lcam_mask_0 & write_mask_3; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_3_T = |mask_union_3; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_3_T_1 = _addr_matches_0_3_T & dword_addr_matches_27; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_3 = _addr_matches_0_3_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_3_T = addr_matches_0_3 & stq_data_3_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_3_T_1 = mask_union_3 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_3_T_2 = _forward_matches_0_3_T & _forward_matches_0_3_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_3 = _forward_matches_0_3_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_3_T = s_uop_6_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_3_T_1 = s_uop_6_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_3_T_2 = _prs2_matches_0_3_T & _prs2_matches_0_3_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_3_T_3 = _prs2_matches_0_3_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_3 = _prs2_matches_0_3_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_4; // @[lsu.scala:1951:22] wire _write_mask_mask_T_60 = s_uop_7_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_61 = stq_addr_4_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_62 = 15'h1 << _write_mask_mask_T_61; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_63 = s_uop_7_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_64 = stq_addr_4_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_65 = {_write_mask_mask_T_64, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_66 = 15'h3 << _write_mask_mask_T_65; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_67 = s_uop_7_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_68 = stq_addr_4_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_69 = _write_mask_mask_T_68 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_70 = &s_uop_7_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_72 = _write_mask_mask_T_67 ? _write_mask_mask_T_69 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_73 = _write_mask_mask_T_63 ? _write_mask_mask_T_66 : {7'h0, _write_mask_mask_T_72}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_74 = _write_mask_mask_T_60 ? _write_mask_mask_T_62 : _write_mask_mask_T_73; // @[Mux.scala:126:16] assign write_mask_4 = _write_mask_mask_T_74[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_124 = ~s_uop_7_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_125 = stq_addr_4_valid & _dword_addr_matches_T_124; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_126 = ~stq_addr_is_virtual_4; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_127 = _dword_addr_matches_T_125 & _dword_addr_matches_T_126; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_128 = stq_addr_4_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_130 = _dword_addr_matches_T_128 == _dword_addr_matches_T_129; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_28 = _dword_addr_matches_T_127 & _dword_addr_matches_T_130; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_4 = lcam_mask_0 & write_mask_4; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_4_T = |mask_union_4; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_4_T_1 = _addr_matches_0_4_T & dword_addr_matches_28; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_4 = _addr_matches_0_4_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_4_T = addr_matches_0_4 & stq_data_4_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_4_T_1 = mask_union_4 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_4_T_2 = _forward_matches_0_4_T & _forward_matches_0_4_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_4 = _forward_matches_0_4_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_4_T = s_uop_7_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_4_T_1 = s_uop_7_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_4_T_2 = _prs2_matches_0_4_T & _prs2_matches_0_4_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_4_T_3 = _prs2_matches_0_4_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_4 = _prs2_matches_0_4_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_5; // @[lsu.scala:1951:22] wire _write_mask_mask_T_75 = s_uop_8_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_76 = stq_addr_5_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_77 = 15'h1 << _write_mask_mask_T_76; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_78 = s_uop_8_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_79 = stq_addr_5_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_80 = {_write_mask_mask_T_79, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_81 = 15'h3 << _write_mask_mask_T_80; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_82 = s_uop_8_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_83 = stq_addr_5_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_84 = _write_mask_mask_T_83 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_85 = &s_uop_8_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_87 = _write_mask_mask_T_82 ? _write_mask_mask_T_84 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_88 = _write_mask_mask_T_78 ? _write_mask_mask_T_81 : {7'h0, _write_mask_mask_T_87}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_89 = _write_mask_mask_T_75 ? _write_mask_mask_T_77 : _write_mask_mask_T_88; // @[Mux.scala:126:16] assign write_mask_5 = _write_mask_mask_T_89[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_131 = ~s_uop_8_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_132 = stq_addr_5_valid & _dword_addr_matches_T_131; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_133 = ~stq_addr_is_virtual_5; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_134 = _dword_addr_matches_T_132 & _dword_addr_matches_T_133; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_135 = stq_addr_5_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_137 = _dword_addr_matches_T_135 == _dword_addr_matches_T_136; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_29 = _dword_addr_matches_T_134 & _dword_addr_matches_T_137; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_5 = lcam_mask_0 & write_mask_5; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_5_T = |mask_union_5; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_5_T_1 = _addr_matches_0_5_T & dword_addr_matches_29; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_5 = _addr_matches_0_5_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_5_T = addr_matches_0_5 & stq_data_5_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_5_T_1 = mask_union_5 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_5_T_2 = _forward_matches_0_5_T & _forward_matches_0_5_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_5 = _forward_matches_0_5_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_5_T = s_uop_8_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_5_T_1 = s_uop_8_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_5_T_2 = _prs2_matches_0_5_T & _prs2_matches_0_5_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_5_T_3 = _prs2_matches_0_5_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_5 = _prs2_matches_0_5_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_6; // @[lsu.scala:1951:22] wire _write_mask_mask_T_90 = s_uop_9_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_91 = stq_addr_6_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_92 = 15'h1 << _write_mask_mask_T_91; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_93 = s_uop_9_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_94 = stq_addr_6_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_95 = {_write_mask_mask_T_94, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_96 = 15'h3 << _write_mask_mask_T_95; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_97 = s_uop_9_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_98 = stq_addr_6_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_99 = _write_mask_mask_T_98 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_100 = &s_uop_9_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_102 = _write_mask_mask_T_97 ? _write_mask_mask_T_99 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_103 = _write_mask_mask_T_93 ? _write_mask_mask_T_96 : {7'h0, _write_mask_mask_T_102}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_104 = _write_mask_mask_T_90 ? _write_mask_mask_T_92 : _write_mask_mask_T_103; // @[Mux.scala:126:16] assign write_mask_6 = _write_mask_mask_T_104[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_138 = ~s_uop_9_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_139 = stq_addr_6_valid & _dword_addr_matches_T_138; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_140 = ~stq_addr_is_virtual_6; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_141 = _dword_addr_matches_T_139 & _dword_addr_matches_T_140; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_142 = stq_addr_6_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_144 = _dword_addr_matches_T_142 == _dword_addr_matches_T_143; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_30 = _dword_addr_matches_T_141 & _dword_addr_matches_T_144; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_6 = lcam_mask_0 & write_mask_6; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_6_T = |mask_union_6; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_6_T_1 = _addr_matches_0_6_T & dword_addr_matches_30; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_6 = _addr_matches_0_6_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_6_T = addr_matches_0_6 & stq_data_6_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_6_T_1 = mask_union_6 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_6_T_2 = _forward_matches_0_6_T & _forward_matches_0_6_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_6 = _forward_matches_0_6_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_6_T = s_uop_9_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_6_T_1 = s_uop_9_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_6_T_2 = _prs2_matches_0_6_T & _prs2_matches_0_6_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_6_T_3 = _prs2_matches_0_6_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_6 = _prs2_matches_0_6_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_7; // @[lsu.scala:1951:22] wire _write_mask_mask_T_105 = s_uop_10_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_106 = stq_addr_7_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_107 = 15'h1 << _write_mask_mask_T_106; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_108 = s_uop_10_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_109 = stq_addr_7_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_110 = {_write_mask_mask_T_109, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_111 = 15'h3 << _write_mask_mask_T_110; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_112 = s_uop_10_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_113 = stq_addr_7_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_114 = _write_mask_mask_T_113 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_115 = &s_uop_10_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_117 = _write_mask_mask_T_112 ? _write_mask_mask_T_114 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_118 = _write_mask_mask_T_108 ? _write_mask_mask_T_111 : {7'h0, _write_mask_mask_T_117}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_119 = _write_mask_mask_T_105 ? _write_mask_mask_T_107 : _write_mask_mask_T_118; // @[Mux.scala:126:16] assign write_mask_7 = _write_mask_mask_T_119[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_145 = ~s_uop_10_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_146 = stq_addr_7_valid & _dword_addr_matches_T_145; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_147 = ~stq_addr_is_virtual_7; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_148 = _dword_addr_matches_T_146 & _dword_addr_matches_T_147; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_149 = stq_addr_7_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_151 = _dword_addr_matches_T_149 == _dword_addr_matches_T_150; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_31 = _dword_addr_matches_T_148 & _dword_addr_matches_T_151; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_7 = lcam_mask_0 & write_mask_7; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_7_T = |mask_union_7; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_7_T_1 = _addr_matches_0_7_T & dword_addr_matches_31; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_7 = _addr_matches_0_7_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_7_T = addr_matches_0_7 & stq_data_7_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_7_T_1 = mask_union_7 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_7_T_2 = _forward_matches_0_7_T & _forward_matches_0_7_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_7 = _forward_matches_0_7_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_7_T = s_uop_10_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_7_T_1 = s_uop_10_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_7_T_2 = _prs2_matches_0_7_T & _prs2_matches_0_7_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_7_T_3 = _prs2_matches_0_7_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_7 = _prs2_matches_0_7_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_8; // @[lsu.scala:1951:22] wire _write_mask_mask_T_120 = s_uop_11_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_121 = stq_addr_8_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_122 = 15'h1 << _write_mask_mask_T_121; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_123 = s_uop_11_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_124 = stq_addr_8_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_125 = {_write_mask_mask_T_124, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_126 = 15'h3 << _write_mask_mask_T_125; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_127 = s_uop_11_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_128 = stq_addr_8_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_129 = _write_mask_mask_T_128 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_130 = &s_uop_11_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_132 = _write_mask_mask_T_127 ? _write_mask_mask_T_129 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_133 = _write_mask_mask_T_123 ? _write_mask_mask_T_126 : {7'h0, _write_mask_mask_T_132}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_134 = _write_mask_mask_T_120 ? _write_mask_mask_T_122 : _write_mask_mask_T_133; // @[Mux.scala:126:16] assign write_mask_8 = _write_mask_mask_T_134[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_152 = ~s_uop_11_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_153 = stq_addr_8_valid & _dword_addr_matches_T_152; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_154 = ~stq_addr_is_virtual_8; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_155 = _dword_addr_matches_T_153 & _dword_addr_matches_T_154; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_156 = stq_addr_8_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_158 = _dword_addr_matches_T_156 == _dword_addr_matches_T_157; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_32 = _dword_addr_matches_T_155 & _dword_addr_matches_T_158; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_8 = lcam_mask_0 & write_mask_8; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_8_T = |mask_union_8; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_8_T_1 = _addr_matches_0_8_T & dword_addr_matches_32; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_8 = _addr_matches_0_8_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_8_T = addr_matches_0_8 & stq_data_8_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_8_T_1 = mask_union_8 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_8_T_2 = _forward_matches_0_8_T & _forward_matches_0_8_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_8 = _forward_matches_0_8_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_8_T = s_uop_11_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_8_T_1 = s_uop_11_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_8_T_2 = _prs2_matches_0_8_T & _prs2_matches_0_8_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_8_T_3 = _prs2_matches_0_8_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_8 = _prs2_matches_0_8_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_9; // @[lsu.scala:1951:22] wire _write_mask_mask_T_135 = s_uop_12_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_136 = stq_addr_9_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_137 = 15'h1 << _write_mask_mask_T_136; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_138 = s_uop_12_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_139 = stq_addr_9_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_140 = {_write_mask_mask_T_139, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_141 = 15'h3 << _write_mask_mask_T_140; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_142 = s_uop_12_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_143 = stq_addr_9_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_144 = _write_mask_mask_T_143 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_145 = &s_uop_12_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_147 = _write_mask_mask_T_142 ? _write_mask_mask_T_144 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_148 = _write_mask_mask_T_138 ? _write_mask_mask_T_141 : {7'h0, _write_mask_mask_T_147}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_149 = _write_mask_mask_T_135 ? _write_mask_mask_T_137 : _write_mask_mask_T_148; // @[Mux.scala:126:16] assign write_mask_9 = _write_mask_mask_T_149[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_159 = ~s_uop_12_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_160 = stq_addr_9_valid & _dword_addr_matches_T_159; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_161 = ~stq_addr_is_virtual_9; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_162 = _dword_addr_matches_T_160 & _dword_addr_matches_T_161; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_163 = stq_addr_9_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_165 = _dword_addr_matches_T_163 == _dword_addr_matches_T_164; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_33 = _dword_addr_matches_T_162 & _dword_addr_matches_T_165; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_9 = lcam_mask_0 & write_mask_9; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_9_T = |mask_union_9; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_9_T_1 = _addr_matches_0_9_T & dword_addr_matches_33; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_9 = _addr_matches_0_9_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_9_T = addr_matches_0_9 & stq_data_9_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_9_T_1 = mask_union_9 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_9_T_2 = _forward_matches_0_9_T & _forward_matches_0_9_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_9 = _forward_matches_0_9_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_9_T = s_uop_12_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_9_T_1 = s_uop_12_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_9_T_2 = _prs2_matches_0_9_T & _prs2_matches_0_9_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_9_T_3 = _prs2_matches_0_9_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_9 = _prs2_matches_0_9_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_10; // @[lsu.scala:1951:22] wire _write_mask_mask_T_150 = s_uop_13_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_151 = stq_addr_10_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_152 = 15'h1 << _write_mask_mask_T_151; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_153 = s_uop_13_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_154 = stq_addr_10_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_155 = {_write_mask_mask_T_154, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_156 = 15'h3 << _write_mask_mask_T_155; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_157 = s_uop_13_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_158 = stq_addr_10_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_159 = _write_mask_mask_T_158 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_160 = &s_uop_13_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_162 = _write_mask_mask_T_157 ? _write_mask_mask_T_159 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_163 = _write_mask_mask_T_153 ? _write_mask_mask_T_156 : {7'h0, _write_mask_mask_T_162}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_164 = _write_mask_mask_T_150 ? _write_mask_mask_T_152 : _write_mask_mask_T_163; // @[Mux.scala:126:16] assign write_mask_10 = _write_mask_mask_T_164[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_166 = ~s_uop_13_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_167 = stq_addr_10_valid & _dword_addr_matches_T_166; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_168 = ~stq_addr_is_virtual_10; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_169 = _dword_addr_matches_T_167 & _dword_addr_matches_T_168; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_170 = stq_addr_10_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_172 = _dword_addr_matches_T_170 == _dword_addr_matches_T_171; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_34 = _dword_addr_matches_T_169 & _dword_addr_matches_T_172; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_10 = lcam_mask_0 & write_mask_10; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_10_T = |mask_union_10; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_10_T_1 = _addr_matches_0_10_T & dword_addr_matches_34; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_10 = _addr_matches_0_10_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_10_T = addr_matches_0_10 & stq_data_10_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_10_T_1 = mask_union_10 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_10_T_2 = _forward_matches_0_10_T & _forward_matches_0_10_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_10 = _forward_matches_0_10_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_10_T = s_uop_13_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_10_T_1 = s_uop_13_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_10_T_2 = _prs2_matches_0_10_T & _prs2_matches_0_10_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_10_T_3 = _prs2_matches_0_10_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_10 = _prs2_matches_0_10_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_11; // @[lsu.scala:1951:22] wire _write_mask_mask_T_165 = s_uop_14_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_166 = stq_addr_11_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_167 = 15'h1 << _write_mask_mask_T_166; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_168 = s_uop_14_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_169 = stq_addr_11_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_170 = {_write_mask_mask_T_169, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_171 = 15'h3 << _write_mask_mask_T_170; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_172 = s_uop_14_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_173 = stq_addr_11_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_174 = _write_mask_mask_T_173 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_175 = &s_uop_14_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_177 = _write_mask_mask_T_172 ? _write_mask_mask_T_174 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_178 = _write_mask_mask_T_168 ? _write_mask_mask_T_171 : {7'h0, _write_mask_mask_T_177}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_179 = _write_mask_mask_T_165 ? _write_mask_mask_T_167 : _write_mask_mask_T_178; // @[Mux.scala:126:16] assign write_mask_11 = _write_mask_mask_T_179[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_173 = ~s_uop_14_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_174 = stq_addr_11_valid & _dword_addr_matches_T_173; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_175 = ~stq_addr_is_virtual_11; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_176 = _dword_addr_matches_T_174 & _dword_addr_matches_T_175; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_177 = stq_addr_11_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_179 = _dword_addr_matches_T_177 == _dword_addr_matches_T_178; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_35 = _dword_addr_matches_T_176 & _dword_addr_matches_T_179; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_11 = lcam_mask_0 & write_mask_11; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_11_T = |mask_union_11; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_11_T_1 = _addr_matches_0_11_T & dword_addr_matches_35; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_11 = _addr_matches_0_11_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_11_T = addr_matches_0_11 & stq_data_11_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_11_T_1 = mask_union_11 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_11_T_2 = _forward_matches_0_11_T & _forward_matches_0_11_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_11 = _forward_matches_0_11_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_11_T = s_uop_14_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_11_T_1 = s_uop_14_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_11_T_2 = _prs2_matches_0_11_T & _prs2_matches_0_11_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_11_T_3 = _prs2_matches_0_11_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_11 = _prs2_matches_0_11_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_12; // @[lsu.scala:1951:22] wire _write_mask_mask_T_180 = s_uop_15_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_181 = stq_addr_12_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_182 = 15'h1 << _write_mask_mask_T_181; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_183 = s_uop_15_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_184 = stq_addr_12_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_185 = {_write_mask_mask_T_184, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_186 = 15'h3 << _write_mask_mask_T_185; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_187 = s_uop_15_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_188 = stq_addr_12_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_189 = _write_mask_mask_T_188 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_190 = &s_uop_15_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_192 = _write_mask_mask_T_187 ? _write_mask_mask_T_189 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_193 = _write_mask_mask_T_183 ? _write_mask_mask_T_186 : {7'h0, _write_mask_mask_T_192}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_194 = _write_mask_mask_T_180 ? _write_mask_mask_T_182 : _write_mask_mask_T_193; // @[Mux.scala:126:16] assign write_mask_12 = _write_mask_mask_T_194[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_180 = ~s_uop_15_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_181 = stq_addr_12_valid & _dword_addr_matches_T_180; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_182 = ~stq_addr_is_virtual_12; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_183 = _dword_addr_matches_T_181 & _dword_addr_matches_T_182; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_184 = stq_addr_12_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_186 = _dword_addr_matches_T_184 == _dword_addr_matches_T_185; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_36 = _dword_addr_matches_T_183 & _dword_addr_matches_T_186; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_12 = lcam_mask_0 & write_mask_12; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_12_T = |mask_union_12; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_12_T_1 = _addr_matches_0_12_T & dword_addr_matches_36; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_12 = _addr_matches_0_12_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_12_T = addr_matches_0_12 & stq_data_12_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_12_T_1 = mask_union_12 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_12_T_2 = _forward_matches_0_12_T & _forward_matches_0_12_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_12 = _forward_matches_0_12_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_12_T = s_uop_15_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_12_T_1 = s_uop_15_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_12_T_2 = _prs2_matches_0_12_T & _prs2_matches_0_12_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_12_T_3 = _prs2_matches_0_12_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_12 = _prs2_matches_0_12_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_13; // @[lsu.scala:1951:22] wire _write_mask_mask_T_195 = s_uop_16_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_196 = stq_addr_13_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_197 = 15'h1 << _write_mask_mask_T_196; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_198 = s_uop_16_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_199 = stq_addr_13_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_200 = {_write_mask_mask_T_199, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_201 = 15'h3 << _write_mask_mask_T_200; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_202 = s_uop_16_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_203 = stq_addr_13_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_204 = _write_mask_mask_T_203 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_205 = &s_uop_16_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_207 = _write_mask_mask_T_202 ? _write_mask_mask_T_204 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_208 = _write_mask_mask_T_198 ? _write_mask_mask_T_201 : {7'h0, _write_mask_mask_T_207}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_209 = _write_mask_mask_T_195 ? _write_mask_mask_T_197 : _write_mask_mask_T_208; // @[Mux.scala:126:16] assign write_mask_13 = _write_mask_mask_T_209[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_187 = ~s_uop_16_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_188 = stq_addr_13_valid & _dword_addr_matches_T_187; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_189 = ~stq_addr_is_virtual_13; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_190 = _dword_addr_matches_T_188 & _dword_addr_matches_T_189; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_191 = stq_addr_13_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_193 = _dword_addr_matches_T_191 == _dword_addr_matches_T_192; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_37 = _dword_addr_matches_T_190 & _dword_addr_matches_T_193; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_13 = lcam_mask_0 & write_mask_13; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_13_T = |mask_union_13; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_13_T_1 = _addr_matches_0_13_T & dword_addr_matches_37; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_13 = _addr_matches_0_13_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_13_T = addr_matches_0_13 & stq_data_13_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_13_T_1 = mask_union_13 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_13_T_2 = _forward_matches_0_13_T & _forward_matches_0_13_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_13 = _forward_matches_0_13_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_13_T = s_uop_16_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_13_T_1 = s_uop_16_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_13_T_2 = _prs2_matches_0_13_T & _prs2_matches_0_13_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_13_T_3 = _prs2_matches_0_13_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_13 = _prs2_matches_0_13_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_14; // @[lsu.scala:1951:22] wire _write_mask_mask_T_210 = s_uop_17_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_211 = stq_addr_14_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_212 = 15'h1 << _write_mask_mask_T_211; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_213 = s_uop_17_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_214 = stq_addr_14_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_215 = {_write_mask_mask_T_214, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_216 = 15'h3 << _write_mask_mask_T_215; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_217 = s_uop_17_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_218 = stq_addr_14_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_219 = _write_mask_mask_T_218 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_220 = &s_uop_17_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_222 = _write_mask_mask_T_217 ? _write_mask_mask_T_219 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_223 = _write_mask_mask_T_213 ? _write_mask_mask_T_216 : {7'h0, _write_mask_mask_T_222}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_224 = _write_mask_mask_T_210 ? _write_mask_mask_T_212 : _write_mask_mask_T_223; // @[Mux.scala:126:16] assign write_mask_14 = _write_mask_mask_T_224[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_194 = ~s_uop_17_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_195 = stq_addr_14_valid & _dword_addr_matches_T_194; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_196 = ~stq_addr_is_virtual_14; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_197 = _dword_addr_matches_T_195 & _dword_addr_matches_T_196; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_198 = stq_addr_14_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_200 = _dword_addr_matches_T_198 == _dword_addr_matches_T_199; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_38 = _dword_addr_matches_T_197 & _dword_addr_matches_T_200; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_14 = lcam_mask_0 & write_mask_14; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_14_T = |mask_union_14; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_14_T_1 = _addr_matches_0_14_T & dword_addr_matches_38; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_14 = _addr_matches_0_14_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_14_T = addr_matches_0_14 & stq_data_14_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_14_T_1 = mask_union_14 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_14_T_2 = _forward_matches_0_14_T & _forward_matches_0_14_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_14 = _forward_matches_0_14_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_14_T = s_uop_17_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_14_T_1 = s_uop_17_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_14_T_2 = _prs2_matches_0_14_T & _prs2_matches_0_14_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_14_T_3 = _prs2_matches_0_14_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_14 = _prs2_matches_0_14_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_15; // @[lsu.scala:1951:22] wire _write_mask_mask_T_225 = s_uop_18_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_226 = stq_addr_15_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_227 = 15'h1 << _write_mask_mask_T_226; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_228 = s_uop_18_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_229 = stq_addr_15_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_230 = {_write_mask_mask_T_229, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_231 = 15'h3 << _write_mask_mask_T_230; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_232 = s_uop_18_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_233 = stq_addr_15_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_234 = _write_mask_mask_T_233 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_235 = &s_uop_18_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_237 = _write_mask_mask_T_232 ? _write_mask_mask_T_234 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_238 = _write_mask_mask_T_228 ? _write_mask_mask_T_231 : {7'h0, _write_mask_mask_T_237}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_239 = _write_mask_mask_T_225 ? _write_mask_mask_T_227 : _write_mask_mask_T_238; // @[Mux.scala:126:16] assign write_mask_15 = _write_mask_mask_T_239[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_201 = ~s_uop_18_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_202 = stq_addr_15_valid & _dword_addr_matches_T_201; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_203 = ~stq_addr_is_virtual_15; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_204 = _dword_addr_matches_T_202 & _dword_addr_matches_T_203; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_205 = stq_addr_15_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_207 = _dword_addr_matches_T_205 == _dword_addr_matches_T_206; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_39 = _dword_addr_matches_T_204 & _dword_addr_matches_T_207; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_15 = lcam_mask_0 & write_mask_15; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_15_T = |mask_union_15; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_15_T_1 = _addr_matches_0_15_T & dword_addr_matches_39; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_15 = _addr_matches_0_15_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_15_T = addr_matches_0_15 & stq_data_15_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_15_T_1 = mask_union_15 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_15_T_2 = _forward_matches_0_15_T & _forward_matches_0_15_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_15 = _forward_matches_0_15_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_15_T = s_uop_18_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_15_T_1 = s_uop_18_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_15_T_2 = _prs2_matches_0_15_T & _prs2_matches_0_15_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_15_T_3 = _prs2_matches_0_15_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_15 = _prs2_matches_0_15_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_16; // @[lsu.scala:1951:22] wire _write_mask_mask_T_240 = s_uop_19_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_241 = stq_addr_16_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_242 = 15'h1 << _write_mask_mask_T_241; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_243 = s_uop_19_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_244 = stq_addr_16_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_245 = {_write_mask_mask_T_244, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_246 = 15'h3 << _write_mask_mask_T_245; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_247 = s_uop_19_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_248 = stq_addr_16_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_249 = _write_mask_mask_T_248 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_250 = &s_uop_19_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_252 = _write_mask_mask_T_247 ? _write_mask_mask_T_249 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_253 = _write_mask_mask_T_243 ? _write_mask_mask_T_246 : {7'h0, _write_mask_mask_T_252}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_254 = _write_mask_mask_T_240 ? _write_mask_mask_T_242 : _write_mask_mask_T_253; // @[Mux.scala:126:16] assign write_mask_16 = _write_mask_mask_T_254[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_208 = ~s_uop_19_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_209 = stq_addr_16_valid & _dword_addr_matches_T_208; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_210 = ~stq_addr_is_virtual_16; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_211 = _dword_addr_matches_T_209 & _dword_addr_matches_T_210; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_212 = stq_addr_16_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_214 = _dword_addr_matches_T_212 == _dword_addr_matches_T_213; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_40 = _dword_addr_matches_T_211 & _dword_addr_matches_T_214; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_16 = lcam_mask_0 & write_mask_16; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_16_T = |mask_union_16; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_16_T_1 = _addr_matches_0_16_T & dword_addr_matches_40; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_16 = _addr_matches_0_16_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_16_T = addr_matches_0_16 & stq_data_16_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_16_T_1 = mask_union_16 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_16_T_2 = _forward_matches_0_16_T & _forward_matches_0_16_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_16 = _forward_matches_0_16_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_16_T = s_uop_19_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_16_T_1 = s_uop_19_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_16_T_2 = _prs2_matches_0_16_T & _prs2_matches_0_16_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_16_T_3 = _prs2_matches_0_16_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_16 = _prs2_matches_0_16_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_17; // @[lsu.scala:1951:22] wire _write_mask_mask_T_255 = s_uop_20_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_256 = stq_addr_17_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_257 = 15'h1 << _write_mask_mask_T_256; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_258 = s_uop_20_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_259 = stq_addr_17_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_260 = {_write_mask_mask_T_259, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_261 = 15'h3 << _write_mask_mask_T_260; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_262 = s_uop_20_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_263 = stq_addr_17_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_264 = _write_mask_mask_T_263 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_265 = &s_uop_20_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_267 = _write_mask_mask_T_262 ? _write_mask_mask_T_264 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_268 = _write_mask_mask_T_258 ? _write_mask_mask_T_261 : {7'h0, _write_mask_mask_T_267}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_269 = _write_mask_mask_T_255 ? _write_mask_mask_T_257 : _write_mask_mask_T_268; // @[Mux.scala:126:16] assign write_mask_17 = _write_mask_mask_T_269[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_215 = ~s_uop_20_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_216 = stq_addr_17_valid & _dword_addr_matches_T_215; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_217 = ~stq_addr_is_virtual_17; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_218 = _dword_addr_matches_T_216 & _dword_addr_matches_T_217; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_219 = stq_addr_17_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_221 = _dword_addr_matches_T_219 == _dword_addr_matches_T_220; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_41 = _dword_addr_matches_T_218 & _dword_addr_matches_T_221; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_17 = lcam_mask_0 & write_mask_17; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_17_T = |mask_union_17; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_17_T_1 = _addr_matches_0_17_T & dword_addr_matches_41; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_17 = _addr_matches_0_17_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_17_T = addr_matches_0_17 & stq_data_17_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_17_T_1 = mask_union_17 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_17_T_2 = _forward_matches_0_17_T & _forward_matches_0_17_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_17 = _forward_matches_0_17_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_17_T = s_uop_20_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_17_T_1 = s_uop_20_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_17_T_2 = _prs2_matches_0_17_T & _prs2_matches_0_17_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_17_T_3 = _prs2_matches_0_17_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_17 = _prs2_matches_0_17_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_18; // @[lsu.scala:1951:22] wire _write_mask_mask_T_270 = s_uop_21_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_271 = stq_addr_18_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_272 = 15'h1 << _write_mask_mask_T_271; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_273 = s_uop_21_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_274 = stq_addr_18_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_275 = {_write_mask_mask_T_274, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_276 = 15'h3 << _write_mask_mask_T_275; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_277 = s_uop_21_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_278 = stq_addr_18_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_279 = _write_mask_mask_T_278 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_280 = &s_uop_21_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_282 = _write_mask_mask_T_277 ? _write_mask_mask_T_279 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_283 = _write_mask_mask_T_273 ? _write_mask_mask_T_276 : {7'h0, _write_mask_mask_T_282}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_284 = _write_mask_mask_T_270 ? _write_mask_mask_T_272 : _write_mask_mask_T_283; // @[Mux.scala:126:16] assign write_mask_18 = _write_mask_mask_T_284[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_222 = ~s_uop_21_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_223 = stq_addr_18_valid & _dword_addr_matches_T_222; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_224 = ~stq_addr_is_virtual_18; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_225 = _dword_addr_matches_T_223 & _dword_addr_matches_T_224; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_226 = stq_addr_18_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_228 = _dword_addr_matches_T_226 == _dword_addr_matches_T_227; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_42 = _dword_addr_matches_T_225 & _dword_addr_matches_T_228; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_18 = lcam_mask_0 & write_mask_18; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_18_T = |mask_union_18; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_18_T_1 = _addr_matches_0_18_T & dword_addr_matches_42; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_18 = _addr_matches_0_18_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_18_T = addr_matches_0_18 & stq_data_18_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_18_T_1 = mask_union_18 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_18_T_2 = _forward_matches_0_18_T & _forward_matches_0_18_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_18 = _forward_matches_0_18_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_18_T = s_uop_21_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_18_T_1 = s_uop_21_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_18_T_2 = _prs2_matches_0_18_T & _prs2_matches_0_18_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_18_T_3 = _prs2_matches_0_18_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_18 = _prs2_matches_0_18_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_19; // @[lsu.scala:1951:22] wire _write_mask_mask_T_285 = s_uop_22_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_286 = stq_addr_19_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_287 = 15'h1 << _write_mask_mask_T_286; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_288 = s_uop_22_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_289 = stq_addr_19_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_290 = {_write_mask_mask_T_289, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_291 = 15'h3 << _write_mask_mask_T_290; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_292 = s_uop_22_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_293 = stq_addr_19_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_294 = _write_mask_mask_T_293 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_295 = &s_uop_22_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_297 = _write_mask_mask_T_292 ? _write_mask_mask_T_294 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_298 = _write_mask_mask_T_288 ? _write_mask_mask_T_291 : {7'h0, _write_mask_mask_T_297}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_299 = _write_mask_mask_T_285 ? _write_mask_mask_T_287 : _write_mask_mask_T_298; // @[Mux.scala:126:16] assign write_mask_19 = _write_mask_mask_T_299[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_229 = ~s_uop_22_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_230 = stq_addr_19_valid & _dword_addr_matches_T_229; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_231 = ~stq_addr_is_virtual_19; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_232 = _dword_addr_matches_T_230 & _dword_addr_matches_T_231; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_233 = stq_addr_19_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_235 = _dword_addr_matches_T_233 == _dword_addr_matches_T_234; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_43 = _dword_addr_matches_T_232 & _dword_addr_matches_T_235; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_19 = lcam_mask_0 & write_mask_19; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_19_T = |mask_union_19; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_19_T_1 = _addr_matches_0_19_T & dword_addr_matches_43; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_19 = _addr_matches_0_19_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_19_T = addr_matches_0_19 & stq_data_19_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_19_T_1 = mask_union_19 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_19_T_2 = _forward_matches_0_19_T & _forward_matches_0_19_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_19 = _forward_matches_0_19_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_19_T = s_uop_22_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_19_T_1 = s_uop_22_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_19_T_2 = _prs2_matches_0_19_T & _prs2_matches_0_19_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_19_T_3 = _prs2_matches_0_19_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_19 = _prs2_matches_0_19_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_20; // @[lsu.scala:1951:22] wire _write_mask_mask_T_300 = s_uop_23_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_301 = stq_addr_20_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_302 = 15'h1 << _write_mask_mask_T_301; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_303 = s_uop_23_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_304 = stq_addr_20_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_305 = {_write_mask_mask_T_304, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_306 = 15'h3 << _write_mask_mask_T_305; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_307 = s_uop_23_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_308 = stq_addr_20_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_309 = _write_mask_mask_T_308 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_310 = &s_uop_23_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_312 = _write_mask_mask_T_307 ? _write_mask_mask_T_309 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_313 = _write_mask_mask_T_303 ? _write_mask_mask_T_306 : {7'h0, _write_mask_mask_T_312}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_314 = _write_mask_mask_T_300 ? _write_mask_mask_T_302 : _write_mask_mask_T_313; // @[Mux.scala:126:16] assign write_mask_20 = _write_mask_mask_T_314[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_236 = ~s_uop_23_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_237 = stq_addr_20_valid & _dword_addr_matches_T_236; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_238 = ~stq_addr_is_virtual_20; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_239 = _dword_addr_matches_T_237 & _dword_addr_matches_T_238; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_240 = stq_addr_20_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_242 = _dword_addr_matches_T_240 == _dword_addr_matches_T_241; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_44 = _dword_addr_matches_T_239 & _dword_addr_matches_T_242; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_20 = lcam_mask_0 & write_mask_20; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_20_T = |mask_union_20; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_20_T_1 = _addr_matches_0_20_T & dword_addr_matches_44; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_20 = _addr_matches_0_20_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_20_T = addr_matches_0_20 & stq_data_20_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_20_T_1 = mask_union_20 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_20_T_2 = _forward_matches_0_20_T & _forward_matches_0_20_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_20 = _forward_matches_0_20_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_20_T = s_uop_23_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_20_T_1 = s_uop_23_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_20_T_2 = _prs2_matches_0_20_T & _prs2_matches_0_20_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_20_T_3 = _prs2_matches_0_20_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_20 = _prs2_matches_0_20_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_21; // @[lsu.scala:1951:22] wire _write_mask_mask_T_315 = s_uop_24_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_316 = stq_addr_21_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_317 = 15'h1 << _write_mask_mask_T_316; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_318 = s_uop_24_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_319 = stq_addr_21_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_320 = {_write_mask_mask_T_319, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_321 = 15'h3 << _write_mask_mask_T_320; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_322 = s_uop_24_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_323 = stq_addr_21_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_324 = _write_mask_mask_T_323 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_325 = &s_uop_24_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_327 = _write_mask_mask_T_322 ? _write_mask_mask_T_324 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_328 = _write_mask_mask_T_318 ? _write_mask_mask_T_321 : {7'h0, _write_mask_mask_T_327}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_329 = _write_mask_mask_T_315 ? _write_mask_mask_T_317 : _write_mask_mask_T_328; // @[Mux.scala:126:16] assign write_mask_21 = _write_mask_mask_T_329[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_243 = ~s_uop_24_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_244 = stq_addr_21_valid & _dword_addr_matches_T_243; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_245 = ~stq_addr_is_virtual_21; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_246 = _dword_addr_matches_T_244 & _dword_addr_matches_T_245; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_247 = stq_addr_21_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_249 = _dword_addr_matches_T_247 == _dword_addr_matches_T_248; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_45 = _dword_addr_matches_T_246 & _dword_addr_matches_T_249; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_21 = lcam_mask_0 & write_mask_21; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_21_T = |mask_union_21; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_21_T_1 = _addr_matches_0_21_T & dword_addr_matches_45; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_21 = _addr_matches_0_21_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_21_T = addr_matches_0_21 & stq_data_21_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_21_T_1 = mask_union_21 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_21_T_2 = _forward_matches_0_21_T & _forward_matches_0_21_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_21 = _forward_matches_0_21_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_21_T = s_uop_24_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_21_T_1 = s_uop_24_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_21_T_2 = _prs2_matches_0_21_T & _prs2_matches_0_21_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_21_T_3 = _prs2_matches_0_21_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_21 = _prs2_matches_0_21_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_22; // @[lsu.scala:1951:22] wire _write_mask_mask_T_330 = s_uop_25_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_331 = stq_addr_22_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_332 = 15'h1 << _write_mask_mask_T_331; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_333 = s_uop_25_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_334 = stq_addr_22_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_335 = {_write_mask_mask_T_334, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_336 = 15'h3 << _write_mask_mask_T_335; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_337 = s_uop_25_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_338 = stq_addr_22_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_339 = _write_mask_mask_T_338 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_340 = &s_uop_25_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_342 = _write_mask_mask_T_337 ? _write_mask_mask_T_339 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_343 = _write_mask_mask_T_333 ? _write_mask_mask_T_336 : {7'h0, _write_mask_mask_T_342}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_344 = _write_mask_mask_T_330 ? _write_mask_mask_T_332 : _write_mask_mask_T_343; // @[Mux.scala:126:16] assign write_mask_22 = _write_mask_mask_T_344[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_250 = ~s_uop_25_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_251 = stq_addr_22_valid & _dword_addr_matches_T_250; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_252 = ~stq_addr_is_virtual_22; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_253 = _dword_addr_matches_T_251 & _dword_addr_matches_T_252; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_254 = stq_addr_22_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_256 = _dword_addr_matches_T_254 == _dword_addr_matches_T_255; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_46 = _dword_addr_matches_T_253 & _dword_addr_matches_T_256; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_22 = lcam_mask_0 & write_mask_22; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_22_T = |mask_union_22; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_22_T_1 = _addr_matches_0_22_T & dword_addr_matches_46; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_22 = _addr_matches_0_22_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_22_T = addr_matches_0_22 & stq_data_22_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_22_T_1 = mask_union_22 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_22_T_2 = _forward_matches_0_22_T & _forward_matches_0_22_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_22 = _forward_matches_0_22_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_22_T = s_uop_25_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_22_T_1 = s_uop_25_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_22_T_2 = _prs2_matches_0_22_T & _prs2_matches_0_22_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_22_T_3 = _prs2_matches_0_22_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_22 = _prs2_matches_0_22_T_3; // @[lsu.scala:1318:29, :1338:58] wire [7:0] write_mask_23; // @[lsu.scala:1951:22] wire _write_mask_mask_T_345 = s_uop_26_mem_size == 2'h0; // @[lsu.scala:1324:37, :1953:26] wire [2:0] _write_mask_mask_T_346 = stq_addr_23_bits[2:0]; // @[lsu.scala:253:32, :1953:55] wire [14:0] _write_mask_mask_T_347 = 15'h1 << _write_mask_mask_T_346; // @[lsu.scala:1953:{48,55}] wire _write_mask_mask_T_348 = s_uop_26_mem_size == 2'h1; // @[lsu.scala:1324:37, :1954:26] wire [1:0] _write_mask_mask_T_349 = stq_addr_23_bits[2:1]; // @[lsu.scala:253:32, :1954:56] wire [2:0] _write_mask_mask_T_350 = {_write_mask_mask_T_349, 1'h0}; // @[lsu.scala:1954:{56,62}] wire [14:0] _write_mask_mask_T_351 = 15'h3 << _write_mask_mask_T_350; // @[lsu.scala:1954:{48,62}] wire _write_mask_mask_T_352 = s_uop_26_mem_size == 2'h2; // @[lsu.scala:1324:37, :1955:26] wire _write_mask_mask_T_353 = stq_addr_23_bits[2]; // @[lsu.scala:253:32, :1955:46] wire [7:0] _write_mask_mask_T_354 = _write_mask_mask_T_353 ? 8'hF0 : 8'hF; // @[lsu.scala:1955:{41,46}] wire _write_mask_mask_T_355 = &s_uop_26_mem_size; // @[lsu.scala:1324:37, :1956:26] wire [7:0] _write_mask_mask_T_357 = _write_mask_mask_T_352 ? _write_mask_mask_T_354 : 8'hFF; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_358 = _write_mask_mask_T_348 ? _write_mask_mask_T_351 : {7'h0, _write_mask_mask_T_357}; // @[Mux.scala:126:16] wire [14:0] _write_mask_mask_T_359 = _write_mask_mask_T_345 ? _write_mask_mask_T_347 : _write_mask_mask_T_358; // @[Mux.scala:126:16] assign write_mask_23 = _write_mask_mask_T_359[7:0]; // @[Mux.scala:126:16] wire _dword_addr_matches_T_257 = ~s_uop_26_is_amo; // @[lsu.scala:1324:37, :1329:33] wire _dword_addr_matches_T_258 = stq_addr_23_valid & _dword_addr_matches_T_257; // @[lsu.scala:253:32, :1328:52, :1329:33] wire _dword_addr_matches_T_259 = ~stq_addr_is_virtual_23; // @[lsu.scala:254:32, :1330:33] wire _dword_addr_matches_T_260 = _dword_addr_matches_T_258 & _dword_addr_matches_T_259; // @[lsu.scala:1328:52, :1329:52, :1330:33] wire [28:0] _dword_addr_matches_T_261 = stq_addr_23_bits[31:3]; // @[lsu.scala:253:32, :1331:45] wire _dword_addr_matches_T_263 = _dword_addr_matches_T_261 == _dword_addr_matches_T_262; // @[lsu.scala:1331:{45,65,81}] wire dword_addr_matches_47 = _dword_addr_matches_T_260 & _dword_addr_matches_T_263; // @[lsu.scala:1329:52, :1330:52, :1331:65] wire [7:0] mask_union_23 = lcam_mask_0 & write_mask_23; // @[lsu.scala:321:49, :1332:37, :1951:22] wire _addr_matches_0_23_T = |mask_union_23; // @[lsu.scala:1332:37, :1334:44] assign _addr_matches_0_23_T_1 = _addr_matches_0_23_T & dword_addr_matches_47; // @[lsu.scala:1330:52, :1334:{44,53}] assign addr_matches_0_23 = _addr_matches_0_23_T_1; // @[lsu.scala:1316:29, :1334:53] wire _forward_matches_0_23_T = addr_matches_0_23 & stq_data_23_valid; // @[lsu.scala:255:32, :1316:29, :1335:51] wire _forward_matches_0_23_T_1 = mask_union_23 == lcam_mask_0; // @[lsu.scala:321:49, :1332:37, :1335:82] assign _forward_matches_0_23_T_2 = _forward_matches_0_23_T & _forward_matches_0_23_T_1; // @[lsu.scala:1335:{51,67,82}] assign forward_matches_0_23 = _forward_matches_0_23_T_2; // @[lsu.scala:1317:29, :1335:67] wire _prs2_matches_0_23_T = s_uop_26_prs2 == lcam_uop_0_pdst; // @[lsu.scala:321:49, :1324:37, :1337:41] wire _prs2_matches_0_23_T_1 = s_uop_26_lrs2_rtype == 2'h0; // @[lsu.scala:1324:37, :1338:47] wire _prs2_matches_0_23_T_2 = _prs2_matches_0_23_T & _prs2_matches_0_23_T_1; // @[lsu.scala:1337:{41,62}, :1338:47] assign _prs2_matches_0_23_T_3 = _prs2_matches_0_23_T_2; // @[lsu.scala:1337:62, :1338:58] assign prs2_matches_0_23 = _prs2_matches_0_23_T_3; // @[lsu.scala:1318:29, :1338:58] wire [2:0] fast_stq_valids_lo_lo_lo = {fast_stq_valids_lo_lo_lo_hi, stq_valid_0}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_lo_lo_hi = {fast_stq_valids_lo_lo_hi_hi, stq_valid_3}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_lo_lo = {fast_stq_valids_lo_lo_hi, fast_stq_valids_lo_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_lo_hi_lo = {fast_stq_valids_lo_hi_lo_hi, stq_valid_6}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_lo_hi_hi = {fast_stq_valids_lo_hi_hi_hi, stq_valid_9}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_lo_hi = {fast_stq_valids_lo_hi_hi, fast_stq_valids_lo_hi_lo}; // @[lsu.scala:1342:35] wire [11:0] fast_stq_valids_lo = {fast_stq_valids_lo_hi, fast_stq_valids_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_hi_lo_lo = {fast_stq_valids_hi_lo_lo_hi, stq_valid_12}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_hi_lo_hi = {fast_stq_valids_hi_lo_hi_hi, stq_valid_15}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_hi_lo = {fast_stq_valids_hi_lo_hi, fast_stq_valids_hi_lo_lo}; // @[lsu.scala:1342:35] wire [2:0] fast_stq_valids_hi_hi_lo = {fast_stq_valids_hi_hi_lo_hi, stq_valid_18}; // @[lsu.scala:251:32, :1342:35] wire [2:0] fast_stq_valids_hi_hi_hi = {fast_stq_valids_hi_hi_hi_hi, stq_valid_21}; // @[lsu.scala:251:32, :1342:35] wire [5:0] fast_stq_valids_hi_hi = {fast_stq_valids_hi_hi_hi, fast_stq_valids_hi_hi_lo}; // @[lsu.scala:1342:35] wire [11:0] fast_stq_valids_hi = {fast_stq_valids_hi_hi, fast_stq_valids_hi_lo}; // @[lsu.scala:1342:35] wire [23:0] fast_stq_valids = {fast_stq_valids_hi, fast_stq_valids_lo}; // @[lsu.scala:1342:35] wire [1:0] ldst_addr_matches_0_lo_lo_lo_hi = {addr_matches_0_2, addr_matches_0_1}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_lo_lo = {ldst_addr_matches_0_lo_lo_lo_hi, addr_matches_0_0}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_lo_hi_hi = {addr_matches_0_5, addr_matches_0_4}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_lo_hi = {ldst_addr_matches_0_lo_lo_hi_hi, addr_matches_0_3}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_lo_lo = {ldst_addr_matches_0_lo_lo_hi, ldst_addr_matches_0_lo_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_lo_hi = {addr_matches_0_8, addr_matches_0_7}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_hi_lo = {ldst_addr_matches_0_lo_hi_lo_hi, addr_matches_0_6}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_lo_hi_hi_hi = {addr_matches_0_11, addr_matches_0_10}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_lo_hi_hi = {ldst_addr_matches_0_lo_hi_hi_hi, addr_matches_0_9}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_lo_hi = {ldst_addr_matches_0_lo_hi_hi, ldst_addr_matches_0_lo_hi_lo}; // @[lsu.scala:1344:49] wire [11:0] ldst_addr_matches_0_lo = {ldst_addr_matches_0_lo_hi, ldst_addr_matches_0_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_lo_hi = {addr_matches_0_14, addr_matches_0_13}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_lo_lo = {ldst_addr_matches_0_hi_lo_lo_hi, addr_matches_0_12}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_lo_hi_hi = {addr_matches_0_17, addr_matches_0_16}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_lo_hi = {ldst_addr_matches_0_hi_lo_hi_hi, addr_matches_0_15}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_hi_lo = {ldst_addr_matches_0_hi_lo_hi, ldst_addr_matches_0_hi_lo_lo}; // @[lsu.scala:1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_lo_hi = {addr_matches_0_20, addr_matches_0_19}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_hi_lo = {ldst_addr_matches_0_hi_hi_lo_hi, addr_matches_0_18}; // @[lsu.scala:1316:29, :1344:49] wire [1:0] ldst_addr_matches_0_hi_hi_hi_hi = {addr_matches_0_23, addr_matches_0_22}; // @[lsu.scala:1316:29, :1344:49] wire [2:0] ldst_addr_matches_0_hi_hi_hi = {ldst_addr_matches_0_hi_hi_hi_hi, addr_matches_0_21}; // @[lsu.scala:1316:29, :1344:49] wire [5:0] ldst_addr_matches_0_hi_hi = {ldst_addr_matches_0_hi_hi_hi, ldst_addr_matches_0_hi_hi_lo}; // @[lsu.scala:1344:49] wire [11:0] ldst_addr_matches_0_hi = {ldst_addr_matches_0_hi_hi, ldst_addr_matches_0_hi_lo}; // @[lsu.scala:1344:49] wire [23:0] _ldst_addr_matches_0_T = {ldst_addr_matches_0_hi, ldst_addr_matches_0_lo}; // @[lsu.scala:1344:49] wire [23:0] _ldst_addr_matches_0_T_1 = _ldst_addr_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1344:{49,56}] assign _ldst_addr_matches_0_T_2 = _ldst_addr_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1344:{56,79}] assign ldst_addr_matches_0 = _ldst_addr_matches_0_T_2; // @[lsu.scala:1162:34, :1344:79] wire [1:0] ldst_forward_matches_0_lo_lo_lo_hi = {forward_matches_0_2, forward_matches_0_1}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_lo_lo = {ldst_forward_matches_0_lo_lo_lo_hi, forward_matches_0_0}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_lo_hi_hi = {forward_matches_0_5, forward_matches_0_4}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_lo_hi = {ldst_forward_matches_0_lo_lo_hi_hi, forward_matches_0_3}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_lo_lo = {ldst_forward_matches_0_lo_lo_hi, ldst_forward_matches_0_lo_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_lo_hi = {forward_matches_0_8, forward_matches_0_7}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_hi_lo = {ldst_forward_matches_0_lo_hi_lo_hi, forward_matches_0_6}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_lo_hi_hi_hi = {forward_matches_0_11, forward_matches_0_10}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_lo_hi_hi = {ldst_forward_matches_0_lo_hi_hi_hi, forward_matches_0_9}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_lo_hi = {ldst_forward_matches_0_lo_hi_hi, ldst_forward_matches_0_lo_hi_lo}; // @[lsu.scala:1345:52] wire [11:0] ldst_forward_matches_0_lo = {ldst_forward_matches_0_lo_hi, ldst_forward_matches_0_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_lo_hi = {forward_matches_0_14, forward_matches_0_13}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_lo_lo = {ldst_forward_matches_0_hi_lo_lo_hi, forward_matches_0_12}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_lo_hi_hi = {forward_matches_0_17, forward_matches_0_16}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_lo_hi = {ldst_forward_matches_0_hi_lo_hi_hi, forward_matches_0_15}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_hi_lo = {ldst_forward_matches_0_hi_lo_hi, ldst_forward_matches_0_hi_lo_lo}; // @[lsu.scala:1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_lo_hi = {forward_matches_0_20, forward_matches_0_19}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_hi_lo = {ldst_forward_matches_0_hi_hi_lo_hi, forward_matches_0_18}; // @[lsu.scala:1317:29, :1345:52] wire [1:0] ldst_forward_matches_0_hi_hi_hi_hi = {forward_matches_0_23, forward_matches_0_22}; // @[lsu.scala:1317:29, :1345:52] wire [2:0] ldst_forward_matches_0_hi_hi_hi = {ldst_forward_matches_0_hi_hi_hi_hi, forward_matches_0_21}; // @[lsu.scala:1317:29, :1345:52] wire [5:0] ldst_forward_matches_0_hi_hi = {ldst_forward_matches_0_hi_hi_hi, ldst_forward_matches_0_hi_hi_lo}; // @[lsu.scala:1345:52] wire [11:0] ldst_forward_matches_0_hi = {ldst_forward_matches_0_hi_hi, ldst_forward_matches_0_hi_lo}; // @[lsu.scala:1345:52] wire [23:0] _ldst_forward_matches_0_T = {ldst_forward_matches_0_hi, ldst_forward_matches_0_lo}; // @[lsu.scala:1345:52] wire [23:0] _ldst_forward_matches_0_T_1 = _ldst_forward_matches_0_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1345:{52,59}] assign _ldst_forward_matches_0_T_2 = _ldst_forward_matches_0_T_1 & fast_stq_valids; // @[lsu.scala:1342:35, :1345:{59,82}] assign ldst_forward_matches_0 = _ldst_forward_matches_0_T_2; // @[lsu.scala:1164:34, :1345:82] wire [1:0] stld_prs2_matches_0_lo_lo_lo_hi = {prs2_matches_0_2, prs2_matches_0_1}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_lo_lo = {stld_prs2_matches_0_lo_lo_lo_hi, prs2_matches_0_0}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_lo_hi_hi = {prs2_matches_0_5, prs2_matches_0_4}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_lo_hi = {stld_prs2_matches_0_lo_lo_hi_hi, prs2_matches_0_3}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_lo_lo = {stld_prs2_matches_0_lo_lo_hi, stld_prs2_matches_0_lo_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_lo_hi = {prs2_matches_0_8, prs2_matches_0_7}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_hi_lo = {stld_prs2_matches_0_lo_hi_lo_hi, prs2_matches_0_6}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_lo_hi_hi_hi = {prs2_matches_0_11, prs2_matches_0_10}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_lo_hi_hi = {stld_prs2_matches_0_lo_hi_hi_hi, prs2_matches_0_9}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_lo_hi = {stld_prs2_matches_0_lo_hi_hi, stld_prs2_matches_0_lo_hi_lo}; // @[lsu.scala:1346:49] wire [11:0] stld_prs2_matches_0_lo = {stld_prs2_matches_0_lo_hi, stld_prs2_matches_0_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_lo_hi = {prs2_matches_0_14, prs2_matches_0_13}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_lo_lo = {stld_prs2_matches_0_hi_lo_lo_hi, prs2_matches_0_12}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_lo_hi_hi = {prs2_matches_0_17, prs2_matches_0_16}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_lo_hi = {stld_prs2_matches_0_hi_lo_hi_hi, prs2_matches_0_15}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_hi_lo = {stld_prs2_matches_0_hi_lo_hi, stld_prs2_matches_0_hi_lo_lo}; // @[lsu.scala:1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_lo_hi = {prs2_matches_0_20, prs2_matches_0_19}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_hi_lo = {stld_prs2_matches_0_hi_hi_lo_hi, prs2_matches_0_18}; // @[lsu.scala:1318:29, :1346:49] wire [1:0] stld_prs2_matches_0_hi_hi_hi_hi = {prs2_matches_0_23, prs2_matches_0_22}; // @[lsu.scala:1318:29, :1346:49] wire [2:0] stld_prs2_matches_0_hi_hi_hi = {stld_prs2_matches_0_hi_hi_hi_hi, prs2_matches_0_21}; // @[lsu.scala:1318:29, :1346:49] wire [5:0] stld_prs2_matches_0_hi_hi = {stld_prs2_matches_0_hi_hi_hi, stld_prs2_matches_0_hi_hi_lo}; // @[lsu.scala:1346:49] wire [11:0] stld_prs2_matches_0_hi = {stld_prs2_matches_0_hi_hi, stld_prs2_matches_0_hi_lo}; // @[lsu.scala:1346:49] wire [23:0] _stld_prs2_matches_0_T = {stld_prs2_matches_0_hi, stld_prs2_matches_0_lo}; // @[lsu.scala:1346:49] wire [23:0] _stld_prs2_matches_0_T_1 = ~lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1346:58] wire [23:0] _stld_prs2_matches_0_T_2 = _stld_prs2_matches_0_T & _stld_prs2_matches_0_T_1; // @[lsu.scala:1346:{49,56,58}] assign _stld_prs2_matches_0_T_3 = _stld_prs2_matches_0_T_2 & fast_stq_valids; // @[lsu.scala:1342:35, :1346:{56,80}] assign stld_prs2_matches_0 = _stld_prs2_matches_0_T_3; // @[lsu.scala:1166:34, :1346:80] wire _stq_amos_T = stq_uop_0_is_fence | stq_uop_0_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_0 = _stq_amos_T; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_1 = stq_uop_1_is_fence | stq_uop_1_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_1 = _stq_amos_T_1; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_2 = stq_uop_2_is_fence | stq_uop_2_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_2 = _stq_amos_T_2; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_3 = stq_uop_3_is_fence | stq_uop_3_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_3 = _stq_amos_T_3; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_4 = stq_uop_4_is_fence | stq_uop_4_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_4 = _stq_amos_T_4; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_5 = stq_uop_5_is_fence | stq_uop_5_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_5 = _stq_amos_T_5; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_6 = stq_uop_6_is_fence | stq_uop_6_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_6 = _stq_amos_T_6; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_7 = stq_uop_7_is_fence | stq_uop_7_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_7 = _stq_amos_T_7; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_8 = stq_uop_8_is_fence | stq_uop_8_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_8 = _stq_amos_T_8; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_9 = stq_uop_9_is_fence | stq_uop_9_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_9 = _stq_amos_T_9; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_10 = stq_uop_10_is_fence | stq_uop_10_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_10 = _stq_amos_T_10; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_11 = stq_uop_11_is_fence | stq_uop_11_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_11 = _stq_amos_T_11; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_12 = stq_uop_12_is_fence | stq_uop_12_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_12 = _stq_amos_T_12; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_13 = stq_uop_13_is_fence | stq_uop_13_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_13 = _stq_amos_T_13; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_14 = stq_uop_14_is_fence | stq_uop_14_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_14 = _stq_amos_T_14; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_15 = stq_uop_15_is_fence | stq_uop_15_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_15 = _stq_amos_T_15; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_16 = stq_uop_16_is_fence | stq_uop_16_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_16 = _stq_amos_T_16; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_17 = stq_uop_17_is_fence | stq_uop_17_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_17 = _stq_amos_T_17; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_18 = stq_uop_18_is_fence | stq_uop_18_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_18 = _stq_amos_T_18; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_19 = stq_uop_19_is_fence | stq_uop_19_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_19 = _stq_amos_T_19; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_20 = stq_uop_20_is_fence | stq_uop_20_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_20 = _stq_amos_T_20; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_21 = stq_uop_21_is_fence | stq_uop_21_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_21 = _stq_amos_T_21; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_22 = stq_uop_22_is_fence | stq_uop_22_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_22 = _stq_amos_T_22; // @[lsu.scala:1349:{25,54}] wire _stq_amos_T_23 = stq_uop_23_is_fence | stq_uop_23_is_amo; // @[lsu.scala:252:32, :1349:54] wire stq_amos_23 = _stq_amos_T_23; // @[lsu.scala:1349:{25,54}] wire [1:0] has_older_amo_lo_lo_lo_hi = {stq_amos_2, stq_amos_1}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_lo_lo = {has_older_amo_lo_lo_lo_hi, stq_amos_0}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_lo_hi_hi = {stq_amos_5, stq_amos_4}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_lo_hi = {has_older_amo_lo_lo_hi_hi, stq_amos_3}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_lo_lo = {has_older_amo_lo_lo_hi, has_older_amo_lo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_lo_hi_lo_hi = {stq_amos_8, stq_amos_7}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_hi_lo = {has_older_amo_lo_hi_lo_hi, stq_amos_6}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_lo_hi_hi_hi = {stq_amos_11, stq_amos_10}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_lo_hi_hi = {has_older_amo_lo_hi_hi_hi, stq_amos_9}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_lo_hi = {has_older_amo_lo_hi_hi, has_older_amo_lo_hi_lo}; // @[lsu.scala:1351:35] wire [11:0] has_older_amo_lo = {has_older_amo_lo_hi, has_older_amo_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_lo_lo_hi = {stq_amos_14, stq_amos_13}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_lo_lo = {has_older_amo_hi_lo_lo_hi, stq_amos_12}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_lo_hi_hi = {stq_amos_17, stq_amos_16}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_lo_hi = {has_older_amo_hi_lo_hi_hi, stq_amos_15}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_hi_lo = {has_older_amo_hi_lo_hi, has_older_amo_hi_lo_lo}; // @[lsu.scala:1351:35] wire [1:0] has_older_amo_hi_hi_lo_hi = {stq_amos_20, stq_amos_19}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_hi_lo = {has_older_amo_hi_hi_lo_hi, stq_amos_18}; // @[lsu.scala:1349:25, :1351:35] wire [1:0] has_older_amo_hi_hi_hi_hi = {stq_amos_23, stq_amos_22}; // @[lsu.scala:1349:25, :1351:35] wire [2:0] has_older_amo_hi_hi_hi = {has_older_amo_hi_hi_hi_hi, stq_amos_21}; // @[lsu.scala:1349:25, :1351:35] wire [5:0] has_older_amo_hi_hi = {has_older_amo_hi_hi_hi, has_older_amo_hi_hi_lo}; // @[lsu.scala:1351:35] wire [11:0] has_older_amo_hi = {has_older_amo_hi_hi, has_older_amo_hi_lo}; // @[lsu.scala:1351:35] wire [23:0] _has_older_amo_T = {has_older_amo_hi, has_older_amo_lo}; // @[lsu.scala:1351:35] wire [23:0] _has_older_amo_T_1 = _has_older_amo_T & lcam_st_dep_mask_0; // @[lsu.scala:321:49, :1351:{35,42}] wire has_older_amo = |_has_older_amo_T_1; // @[lsu.scala:1351:{42,65}] wire _T_1626 = do_ld_search_0 & (|{has_older_amo, ldst_addr_matches_0}); // @[lsu.scala:321:49, :1162:34, :1351:65, :1352:{27,45,70}] reg REG_26; // @[lsu.scala:1353:20] assign io_dmem_s1_kill_0_0 = _T_1626 ? REG_26 & ~fired_load_agen_0 | _GEN_625 | _GEN_599 : _GEN_625 | _GEN_599; // @[lsu.scala:211:7, :321:49, :893:24, :1235:37, :1239:34, :1278:84, :1280:{57,81}, :1281:30, :1352:{27,81}, :1353:{20,55,58,79}, :1354:42] assign s1_set_execute_0 = _T_1626 ? ~(_GEN_483 | _GEN_601) & _GEN_575 : ~_GEN_601 & _GEN_575; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_1 = _T_1626 ? ~(_GEN_484 | _GEN_602) & _GEN_576 : ~_GEN_602 & _GEN_576; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_2 = _T_1626 ? ~(_GEN_485 | _GEN_603) & _GEN_577 : ~_GEN_603 & _GEN_577; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_3 = _T_1626 ? ~(_GEN_486 | _GEN_604) & _GEN_578 : ~_GEN_604 & _GEN_578; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_4 = _T_1626 ? ~(_GEN_487 | _GEN_605) & _GEN_579 : ~_GEN_605 & _GEN_579; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_5 = _T_1626 ? ~(_GEN_488 | _GEN_606) & _GEN_580 : ~_GEN_606 & _GEN_580; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_6 = _T_1626 ? ~(_GEN_489 | _GEN_607) & _GEN_581 : ~_GEN_607 & _GEN_581; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_7 = _T_1626 ? ~(_GEN_490 | _GEN_608) & _GEN_582 : ~_GEN_608 & _GEN_582; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_8 = _T_1626 ? ~(_GEN_491 | _GEN_609) & _GEN_583 : ~_GEN_609 & _GEN_583; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_9 = _T_1626 ? ~(_GEN_492 | _GEN_610) & _GEN_584 : ~_GEN_610 & _GEN_584; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_10 = _T_1626 ? ~(_GEN_493 | _GEN_611) & _GEN_585 : ~_GEN_611 & _GEN_585; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_11 = _T_1626 ? ~(_GEN_494 | _GEN_612) & _GEN_586 : ~_GEN_612 & _GEN_586; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_12 = _T_1626 ? ~(_GEN_495 | _GEN_613) & _GEN_587 : ~_GEN_613 & _GEN_587; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_13 = _T_1626 ? ~(_GEN_496 | _GEN_614) & _GEN_588 : ~_GEN_614 & _GEN_588; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_14 = _T_1626 ? ~(_GEN_497 | _GEN_615) & _GEN_589 : ~_GEN_615 & _GEN_589; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_15 = _T_1626 ? ~(_GEN_498 | _GEN_616) & _GEN_590 : ~_GEN_616 & _GEN_590; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_16 = _T_1626 ? ~(_GEN_499 | _GEN_617) & _GEN_591 : ~_GEN_617 & _GEN_591; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_17 = _T_1626 ? ~(_GEN_500 | _GEN_618) & _GEN_592 : ~_GEN_618 & _GEN_592; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_18 = _T_1626 ? ~(_GEN_501 | _GEN_619) & _GEN_593 : ~_GEN_619 & _GEN_593; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_19 = _T_1626 ? ~(_GEN_502 | _GEN_620) & _GEN_594 : ~_GEN_620 & _GEN_594; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_20 = _T_1626 ? ~(_GEN_503 | _GEN_621) & _GEN_595 : ~_GEN_621 & _GEN_595; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_21 = _T_1626 ? ~(_GEN_504 | _GEN_622) & _GEN_596 : ~_GEN_622 & _GEN_596; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_22 = _T_1626 ? ~(_GEN_505 | _GEN_623) & _GEN_597 : ~_GEN_623 & _GEN_597; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign s1_set_execute_23 = _T_1626 ? ~(_GEN_506 | _GEN_624) & _GEN_598 : ~_GEN_624 & _GEN_598; // @[lsu.scala:1169:36, :1235:37, :1239:34, :1254:48, :1278:84, :1279:41, :1352:{27,81}, :1356:39] assign kill_forward_0 = _T_1626 ? has_older_amo | _T_1596 | _GEN_600 : _T_1596 | _GEN_600; // @[lsu.scala:1159:30, :1235:37, :1239:34, :1273:48, :1274:48, :1275:48, :1276:48, :1277:48, :1278:84, :1283:25, :1351:65, :1352:{27,81}, :1357:28, :1358:25] wire _wb_ldst_forward_valid_0_T = _logic_io_found_idx == _logic_1_io_found_idx; // @[lsu.scala:1377:55, :1965:23] wire _wb_ldst_forward_valid_0_T_1 = _wb_ldst_forward_valid_0_T & _logic_io_found; // @[lsu.scala:1377:{55,100}, :1965:23] wire _wb_ldst_forward_valid_0_T_2 = _wb_ldst_forward_valid_0_T_1 & _logic_1_io_found; // @[lsu.scala:1377:100, :1378:100, :1965:23] wire _wb_ldst_forward_valid_0_T_3 = ~kill_forward_0; // @[lsu.scala:1159:30, :1380:63] wire _wb_ldst_forward_valid_0_T_4 = can_forward_0 & _wb_ldst_forward_valid_0_T_3; // @[lsu.scala:321:49, :1380:{60,63}] wire _wb_ldst_forward_valid_0_T_5 = _wb_ldst_forward_valid_0_T_4 & do_ld_search_0; // @[lsu.scala:321:49, :1380:{60,80}] reg wb_ldst_forward_valid_0_REG; // @[lsu.scala:1380:44] wire _wb_ldst_forward_valid_0_T_6 = _wb_ldst_forward_valid_0_T_2 & wb_ldst_forward_valid_0_REG; // @[lsu.scala:1378:100, :1379:100, :1380:44] wire [15:0] _wb_ldst_forward_valid_0_T_7 = io_core_brupdate_b1_mispredict_mask_0 & lcam_uop_0_br_mask; // @[util.scala:126:51] wire _wb_ldst_forward_valid_0_T_8 = |_wb_ldst_forward_valid_0_T_7; // @[util.scala:126:{51,59}] wire _wb_ldst_forward_valid_0_T_9 = _wb_ldst_forward_valid_0_T_8 | io_core_exception_0; // @[util.scala:61:61, :126:59] reg wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:45] wire _wb_ldst_forward_valid_0_T_10 = ~wb_ldst_forward_valid_0_REG_1; // @[lsu.scala:1381:{37,45}] assign _wb_ldst_forward_valid_0_T_11 = _wb_ldst_forward_valid_0_T_6 & _wb_ldst_forward_valid_0_T_10; // @[lsu.scala:1379:100, :1380:100, :1381:37] assign wb_ldst_forward_valid_0 = _wb_ldst_forward_valid_0_T_11; // @[lsu.scala:1172:38, :1380:100] reg REG_27; // @[lsu.scala:1394:18] reg [3:0] store_blocked_counter; // @[lsu.scala:1399:36] wire _store_blocked_counter_T = &store_blocked_counter; // @[lsu.scala:1399:36, :1403:58] wire [4:0] _store_blocked_counter_T_1 = {1'h0, store_blocked_counter} + 5'h1; // @[lsu.scala:1399:36, :1403:96] wire [3:0] _store_blocked_counter_T_2 = _store_blocked_counter_T_1[3:0]; // @[lsu.scala:1403:96] wire [3:0] _store_blocked_counter_T_3 = _store_blocked_counter_T ? 4'hF : _store_blocked_counter_T_2; // @[lsu.scala:1403:{35,58,96}] assign block_load_wakeup = (&store_blocked_counter) | REG_27 & ~wb_ldst_forward_valid_0; // @[lsu.scala:623:35, :1172:38, :1394:{18,49,52,79}, :1399:36, :1405:{33,43}, :1406:25] wire _mem_stld_forward_stq_idx_T = stld_prs2_matches_0[0]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_1 = stld_prs2_matches_0[1]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_2 = stld_prs2_matches_0[2]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_3 = stld_prs2_matches_0[3]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_4 = stld_prs2_matches_0[4]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_5 = stld_prs2_matches_0[5]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_6 = stld_prs2_matches_0[6]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_7 = stld_prs2_matches_0[7]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_8 = stld_prs2_matches_0[8]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_9 = stld_prs2_matches_0[9]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_10 = stld_prs2_matches_0[10]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_11 = stld_prs2_matches_0[11]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_12 = stld_prs2_matches_0[12]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_13 = stld_prs2_matches_0[13]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_14 = stld_prs2_matches_0[14]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_15 = stld_prs2_matches_0[15]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_16 = stld_prs2_matches_0[16]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_17 = stld_prs2_matches_0[17]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_18 = stld_prs2_matches_0[18]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_19 = stld_prs2_matches_0[19]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_20 = stld_prs2_matches_0[20]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_21 = stld_prs2_matches_0[21]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_22 = stld_prs2_matches_0[22]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_T_23 = stld_prs2_matches_0[23]; // @[lsu.scala:1166:34, :1412:88] wire _mem_stld_forward_stq_idx_temp_vec_T = lcam_uop_0_stq_idx == 5'h0; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_0 = _mem_stld_forward_stq_idx_T & _mem_stld_forward_stq_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_1 = lcam_uop_0_stq_idx < 5'h2; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_1 = _mem_stld_forward_stq_idx_T_1 & _mem_stld_forward_stq_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_2 = lcam_uop_0_stq_idx < 5'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_2 = _mem_stld_forward_stq_idx_T_2 & _mem_stld_forward_stq_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_3 = lcam_uop_0_stq_idx < 5'h4; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_3 = _mem_stld_forward_stq_idx_T_3 & _mem_stld_forward_stq_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_4 = lcam_uop_0_stq_idx < 5'h5; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_4 = _mem_stld_forward_stq_idx_T_4 & _mem_stld_forward_stq_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_5 = lcam_uop_0_stq_idx < 5'h6; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_5 = _mem_stld_forward_stq_idx_T_5 & _mem_stld_forward_stq_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_6 = lcam_uop_0_stq_idx < 5'h7; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_6 = _mem_stld_forward_stq_idx_T_6 & _mem_stld_forward_stq_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_7 = lcam_uop_0_stq_idx < 5'h8; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_7 = _mem_stld_forward_stq_idx_T_7 & _mem_stld_forward_stq_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_8 = lcam_uop_0_stq_idx < 5'h9; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_8 = _mem_stld_forward_stq_idx_T_8 & _mem_stld_forward_stq_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_9 = lcam_uop_0_stq_idx < 5'hA; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_9 = _mem_stld_forward_stq_idx_T_9 & _mem_stld_forward_stq_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_10 = lcam_uop_0_stq_idx < 5'hB; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_10 = _mem_stld_forward_stq_idx_T_10 & _mem_stld_forward_stq_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_11 = lcam_uop_0_stq_idx < 5'hC; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_11 = _mem_stld_forward_stq_idx_T_11 & _mem_stld_forward_stq_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_12 = lcam_uop_0_stq_idx < 5'hD; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_12 = _mem_stld_forward_stq_idx_T_12 & _mem_stld_forward_stq_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_13 = lcam_uop_0_stq_idx < 5'hE; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_13 = _mem_stld_forward_stq_idx_T_13 & _mem_stld_forward_stq_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_14 = lcam_uop_0_stq_idx < 5'hF; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_14 = _mem_stld_forward_stq_idx_T_14 & _mem_stld_forward_stq_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_15 = ~(lcam_uop_0_stq_idx[4]); // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_15 = _mem_stld_forward_stq_idx_T_15 & _mem_stld_forward_stq_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_16 = lcam_uop_0_stq_idx < 5'h11; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_16 = _mem_stld_forward_stq_idx_T_16 & _mem_stld_forward_stq_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_17 = lcam_uop_0_stq_idx < 5'h12; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_17 = _mem_stld_forward_stq_idx_T_17 & _mem_stld_forward_stq_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_18 = lcam_uop_0_stq_idx < 5'h13; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_18 = _mem_stld_forward_stq_idx_T_18 & _mem_stld_forward_stq_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_19 = lcam_uop_0_stq_idx < 5'h14; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_19 = _mem_stld_forward_stq_idx_T_19 & _mem_stld_forward_stq_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_20 = lcam_uop_0_stq_idx < 5'h15; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_20 = _mem_stld_forward_stq_idx_T_20 & _mem_stld_forward_stq_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_21 = lcam_uop_0_stq_idx < 5'h16; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_21 = _mem_stld_forward_stq_idx_T_21 & _mem_stld_forward_stq_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_22 = lcam_uop_0_stq_idx < 5'h17; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_22 = _mem_stld_forward_stq_idx_T_22 & _mem_stld_forward_stq_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire _mem_stld_forward_stq_idx_temp_vec_T_23 = lcam_uop_0_stq_idx[4:3] != 2'h3; // @[util.scala:352:72] wire mem_stld_forward_stq_idx_temp_vec_23 = _mem_stld_forward_stq_idx_T_23 & _mem_stld_forward_stq_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _mem_stld_forward_stq_idx_idx_T = {5'h1B, ~_mem_stld_forward_stq_idx_T_22}; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_1 = _mem_stld_forward_stq_idx_T_21 ? 6'h35 : _mem_stld_forward_stq_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_2 = _mem_stld_forward_stq_idx_T_20 ? 6'h34 : _mem_stld_forward_stq_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_3 = _mem_stld_forward_stq_idx_T_19 ? 6'h33 : _mem_stld_forward_stq_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_4 = _mem_stld_forward_stq_idx_T_18 ? 6'h32 : _mem_stld_forward_stq_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_5 = _mem_stld_forward_stq_idx_T_17 ? 6'h31 : _mem_stld_forward_stq_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_6 = _mem_stld_forward_stq_idx_T_16 ? 6'h30 : _mem_stld_forward_stq_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_7 = _mem_stld_forward_stq_idx_T_15 ? 6'h2F : _mem_stld_forward_stq_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_8 = _mem_stld_forward_stq_idx_T_14 ? 6'h2E : _mem_stld_forward_stq_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_9 = _mem_stld_forward_stq_idx_T_13 ? 6'h2D : _mem_stld_forward_stq_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_10 = _mem_stld_forward_stq_idx_T_12 ? 6'h2C : _mem_stld_forward_stq_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_11 = _mem_stld_forward_stq_idx_T_11 ? 6'h2B : _mem_stld_forward_stq_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_12 = _mem_stld_forward_stq_idx_T_10 ? 6'h2A : _mem_stld_forward_stq_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_13 = _mem_stld_forward_stq_idx_T_9 ? 6'h29 : _mem_stld_forward_stq_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_14 = _mem_stld_forward_stq_idx_T_8 ? 6'h28 : _mem_stld_forward_stq_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_15 = _mem_stld_forward_stq_idx_T_7 ? 6'h27 : _mem_stld_forward_stq_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_16 = _mem_stld_forward_stq_idx_T_6 ? 6'h26 : _mem_stld_forward_stq_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_17 = _mem_stld_forward_stq_idx_T_5 ? 6'h25 : _mem_stld_forward_stq_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_18 = _mem_stld_forward_stq_idx_T_4 ? 6'h24 : _mem_stld_forward_stq_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_19 = _mem_stld_forward_stq_idx_T_3 ? 6'h23 : _mem_stld_forward_stq_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_20 = _mem_stld_forward_stq_idx_T_2 ? 6'h22 : _mem_stld_forward_stq_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_21 = _mem_stld_forward_stq_idx_T_1 ? 6'h21 : _mem_stld_forward_stq_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_22 = _mem_stld_forward_stq_idx_T ? 6'h20 : _mem_stld_forward_stq_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_23 = _mem_stld_forward_stq_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_24 = _mem_stld_forward_stq_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_25 = _mem_stld_forward_stq_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_26 = _mem_stld_forward_stq_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_27 = _mem_stld_forward_stq_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_28 = _mem_stld_forward_stq_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_29 = _mem_stld_forward_stq_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_30 = _mem_stld_forward_stq_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_31 = mem_stld_forward_stq_idx_temp_vec_23 ? 6'h17 : _mem_stld_forward_stq_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_32 = mem_stld_forward_stq_idx_temp_vec_22 ? 6'h16 : _mem_stld_forward_stq_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_33 = mem_stld_forward_stq_idx_temp_vec_21 ? 6'h15 : _mem_stld_forward_stq_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_34 = mem_stld_forward_stq_idx_temp_vec_20 ? 6'h14 : _mem_stld_forward_stq_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_35 = mem_stld_forward_stq_idx_temp_vec_19 ? 6'h13 : _mem_stld_forward_stq_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_36 = mem_stld_forward_stq_idx_temp_vec_18 ? 6'h12 : _mem_stld_forward_stq_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_37 = mem_stld_forward_stq_idx_temp_vec_17 ? 6'h11 : _mem_stld_forward_stq_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_38 = mem_stld_forward_stq_idx_temp_vec_16 ? 6'h10 : _mem_stld_forward_stq_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_39 = mem_stld_forward_stq_idx_temp_vec_15 ? 6'hF : _mem_stld_forward_stq_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_40 = mem_stld_forward_stq_idx_temp_vec_14 ? 6'hE : _mem_stld_forward_stq_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_41 = mem_stld_forward_stq_idx_temp_vec_13 ? 6'hD : _mem_stld_forward_stq_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_42 = mem_stld_forward_stq_idx_temp_vec_12 ? 6'hC : _mem_stld_forward_stq_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_43 = mem_stld_forward_stq_idx_temp_vec_11 ? 6'hB : _mem_stld_forward_stq_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_44 = mem_stld_forward_stq_idx_temp_vec_10 ? 6'hA : _mem_stld_forward_stq_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_45 = mem_stld_forward_stq_idx_temp_vec_9 ? 6'h9 : _mem_stld_forward_stq_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_46 = mem_stld_forward_stq_idx_temp_vec_8 ? 6'h8 : _mem_stld_forward_stq_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_47 = mem_stld_forward_stq_idx_temp_vec_7 ? 6'h7 : _mem_stld_forward_stq_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_48 = mem_stld_forward_stq_idx_temp_vec_6 ? 6'h6 : _mem_stld_forward_stq_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_49 = mem_stld_forward_stq_idx_temp_vec_5 ? 6'h5 : _mem_stld_forward_stq_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_50 = mem_stld_forward_stq_idx_temp_vec_4 ? 6'h4 : _mem_stld_forward_stq_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_51 = mem_stld_forward_stq_idx_temp_vec_3 ? 6'h3 : _mem_stld_forward_stq_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_52 = mem_stld_forward_stq_idx_temp_vec_2 ? 6'h2 : _mem_stld_forward_stq_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _mem_stld_forward_stq_idx_idx_T_53 = mem_stld_forward_stq_idx_temp_vec_1 ? 6'h1 : _mem_stld_forward_stq_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] mem_stld_forward_stq_idx_idx = mem_stld_forward_stq_idx_temp_vec_0 ? 6'h0 : _mem_stld_forward_stq_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] _mem_stld_forward_stq_idx_T_24 = mem_stld_forward_stq_idx_idx[4:0]; // @[Mux.scala:50:70] wire [4:0] mem_stld_forward_stq_idx_0 = _mem_stld_forward_stq_idx_T_24; // @[util.scala:354:8] wire [23:0] _mem_stld_forward_valid_T = stld_prs2_matches_0 >> mem_stld_forward_stq_idx_0; // @[lsu.scala:321:49, :1166:34, :1413:87] wire _mem_stld_forward_valid_T_1 = _mem_stld_forward_valid_T[0]; // @[lsu.scala:1413:87] wire _mem_stld_forward_valid_T_2 = do_ld_search_0 & _mem_stld_forward_valid_T_1; // @[lsu.scala:321:49, :1413:{64,87}] wire mem_stld_forward_valid_0 = _mem_stld_forward_valid_T_2; // @[lsu.scala:321:49, :1413:64] reg io_core_clr_unsafe_0_valid_REG; // @[lsu.scala:1421:14] wire _io_core_clr_unsafe_0_valid_T = ~io_dmem_nack_0_valid_0; // @[lsu.scala:211:7, :1422:8] wire _io_core_clr_unsafe_0_valid_T_1 = ~fired_load_agen_0; // @[lsu.scala:321:49, :1422:61] wire _io_core_clr_unsafe_0_valid_T_2 = do_ld_search_0 & _io_core_clr_unsafe_0_valid_T_1; // @[lsu.scala:321:49, :1422:{58,61}] wire _io_core_clr_unsafe_0_valid_T_3 = ~io_dmem_s1_kill_0_0; // @[lsu.scala:211:7, :1422:84] wire _io_core_clr_unsafe_0_valid_T_4 = _io_core_clr_unsafe_0_valid_T_2 & _io_core_clr_unsafe_0_valid_T_3; // @[lsu.scala:1422:{58,81,84}] reg io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:114] wire _io_core_clr_unsafe_0_valid_T_5 = _io_core_clr_unsafe_0_valid_T_4 & io_core_clr_unsafe_0_valid_REG_1; // @[lsu.scala:1422:{81,104,114}] reg io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:41] wire _io_core_clr_unsafe_0_valid_T_6 = _io_core_clr_unsafe_0_valid_T & io_core_clr_unsafe_0_valid_REG_2; // @[lsu.scala:1422:{8,31,41}] wire _io_core_clr_unsafe_0_valid_T_7 = io_core_clr_unsafe_0_valid_REG | _io_core_clr_unsafe_0_valid_T_6; // @[lsu.scala:1421:{14,32}, :1422:31] reg io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:18] wire _io_core_clr_unsafe_0_valid_T_8 = ~io_core_clr_unsafe_0_valid_REG_3; // @[lsu.scala:1423:{10,18}] assign _io_core_clr_unsafe_0_valid_T_9 = _io_core_clr_unsafe_0_valid_T_7 & _io_core_clr_unsafe_0_valid_T_8; // @[lsu.scala:1421:32, :1423:{7,10}] assign io_core_clr_unsafe_0_valid_0 = _io_core_clr_unsafe_0_valid_T_9; // @[lsu.scala:211:7, :1423:7] reg [6:0] io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:1424:43] assign io_core_clr_unsafe_0_bits_0 = io_core_clr_unsafe_0_bits_REG; // @[lsu.scala:211:7, :1424:43] wire _l_idx_T = ldq_valid_0 & ldq_order_fail_0; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_1 = ldq_valid_1 & ldq_order_fail_1; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_2 = ldq_valid_2 & ldq_order_fail_2; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_3 = ldq_valid_3 & ldq_order_fail_3; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_4 = ldq_valid_4 & ldq_order_fail_4; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_5 = ldq_valid_5 & ldq_order_fail_5; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_6 = ldq_valid_6 & ldq_order_fail_6; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_7 = ldq_valid_7 & ldq_order_fail_7; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_8 = ldq_valid_8 & ldq_order_fail_8; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_9 = ldq_valid_9 & ldq_order_fail_9; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_10 = ldq_valid_10 & ldq_order_fail_10; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_11 = ldq_valid_11 & ldq_order_fail_11; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_12 = ldq_valid_12 & ldq_order_fail_12; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_13 = ldq_valid_13 & ldq_order_fail_13; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_14 = ldq_valid_14 & ldq_order_fail_14; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_15 = ldq_valid_15 & ldq_order_fail_15; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_16 = ldq_valid_16 & ldq_order_fail_16; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_17 = ldq_valid_17 & ldq_order_fail_17; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_18 = ldq_valid_18 & ldq_order_fail_18; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_19 = ldq_valid_19 & ldq_order_fail_19; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_20 = ldq_valid_20 & ldq_order_fail_20; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_21 = ldq_valid_21 & ldq_order_fail_21; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_22 = ldq_valid_22 & ldq_order_fail_22; // @[lsu.scala:218:36, :225:36, :1429:82] wire _l_idx_T_23 = ldq_valid_23 & ldq_order_fail_23; // @[lsu.scala:218:36, :225:36, :1429:82] wire l_idx_temp_vec_0 = _l_idx_T & _l_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_1 = _l_idx_T_1 & _l_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_2 = _l_idx_T_2 & _l_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_3 = _l_idx_T_3 & _l_idx_temp_vec_T_3; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_4 = _l_idx_T_4 & _l_idx_temp_vec_T_4; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_5 = _l_idx_T_5 & _l_idx_temp_vec_T_5; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_6 = _l_idx_T_6 & _l_idx_temp_vec_T_6; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_7 = _l_idx_T_7 & _l_idx_temp_vec_T_7; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_8 = _l_idx_T_8 & _l_idx_temp_vec_T_8; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_9 = _l_idx_T_9 & _l_idx_temp_vec_T_9; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_10 = _l_idx_T_10 & _l_idx_temp_vec_T_10; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_11 = _l_idx_T_11 & _l_idx_temp_vec_T_11; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_12 = _l_idx_T_12 & _l_idx_temp_vec_T_12; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_13 = _l_idx_T_13 & _l_idx_temp_vec_T_13; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_14 = _l_idx_T_14 & _l_idx_temp_vec_T_14; // @[util.scala:352:{65,72}] wire _l_idx_temp_vec_T_15 = ~(ldq_head[4]); // @[util.scala:352:72] wire l_idx_temp_vec_15 = _l_idx_T_15 & _l_idx_temp_vec_T_15; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_16 = _l_idx_T_16 & _l_idx_temp_vec_T_16; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_17 = _l_idx_T_17 & _l_idx_temp_vec_T_17; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_18 = _l_idx_T_18 & _l_idx_temp_vec_T_18; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_19 = _l_idx_T_19 & _l_idx_temp_vec_T_19; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_20 = _l_idx_T_20 & _l_idx_temp_vec_T_20; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_21 = _l_idx_T_21 & _l_idx_temp_vec_T_21; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_22 = _l_idx_T_22 & _l_idx_temp_vec_T_22; // @[util.scala:352:{65,72}] wire l_idx_temp_vec_23 = _l_idx_T_23 & _l_idx_temp_vec_T_23; // @[util.scala:352:{65,72}] wire [5:0] _l_idx_idx_T = {5'h1B, ~_l_idx_T_22}; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_1 = _l_idx_T_21 ? 6'h35 : _l_idx_idx_T; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_2 = _l_idx_T_20 ? 6'h34 : _l_idx_idx_T_1; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_3 = _l_idx_T_19 ? 6'h33 : _l_idx_idx_T_2; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_4 = _l_idx_T_18 ? 6'h32 : _l_idx_idx_T_3; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_5 = _l_idx_T_17 ? 6'h31 : _l_idx_idx_T_4; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_6 = _l_idx_T_16 ? 6'h30 : _l_idx_idx_T_5; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_7 = _l_idx_T_15 ? 6'h2F : _l_idx_idx_T_6; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_8 = _l_idx_T_14 ? 6'h2E : _l_idx_idx_T_7; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_9 = _l_idx_T_13 ? 6'h2D : _l_idx_idx_T_8; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_10 = _l_idx_T_12 ? 6'h2C : _l_idx_idx_T_9; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_11 = _l_idx_T_11 ? 6'h2B : _l_idx_idx_T_10; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_12 = _l_idx_T_10 ? 6'h2A : _l_idx_idx_T_11; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_13 = _l_idx_T_9 ? 6'h29 : _l_idx_idx_T_12; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_14 = _l_idx_T_8 ? 6'h28 : _l_idx_idx_T_13; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_15 = _l_idx_T_7 ? 6'h27 : _l_idx_idx_T_14; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_16 = _l_idx_T_6 ? 6'h26 : _l_idx_idx_T_15; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_17 = _l_idx_T_5 ? 6'h25 : _l_idx_idx_T_16; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_18 = _l_idx_T_4 ? 6'h24 : _l_idx_idx_T_17; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_19 = _l_idx_T_3 ? 6'h23 : _l_idx_idx_T_18; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_20 = _l_idx_T_2 ? 6'h22 : _l_idx_idx_T_19; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_21 = _l_idx_T_1 ? 6'h21 : _l_idx_idx_T_20; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_22 = _l_idx_T ? 6'h20 : _l_idx_idx_T_21; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_23 = _l_idx_idx_T_22; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_24 = _l_idx_idx_T_23; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_25 = _l_idx_idx_T_24; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_26 = _l_idx_idx_T_25; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_27 = _l_idx_idx_T_26; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_28 = _l_idx_idx_T_27; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_29 = _l_idx_idx_T_28; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_30 = _l_idx_idx_T_29; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_31 = l_idx_temp_vec_23 ? 6'h17 : _l_idx_idx_T_30; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_32 = l_idx_temp_vec_22 ? 6'h16 : _l_idx_idx_T_31; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_33 = l_idx_temp_vec_21 ? 6'h15 : _l_idx_idx_T_32; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_34 = l_idx_temp_vec_20 ? 6'h14 : _l_idx_idx_T_33; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_35 = l_idx_temp_vec_19 ? 6'h13 : _l_idx_idx_T_34; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_36 = l_idx_temp_vec_18 ? 6'h12 : _l_idx_idx_T_35; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_37 = l_idx_temp_vec_17 ? 6'h11 : _l_idx_idx_T_36; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_38 = l_idx_temp_vec_16 ? 6'h10 : _l_idx_idx_T_37; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_39 = l_idx_temp_vec_15 ? 6'hF : _l_idx_idx_T_38; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_40 = l_idx_temp_vec_14 ? 6'hE : _l_idx_idx_T_39; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_41 = l_idx_temp_vec_13 ? 6'hD : _l_idx_idx_T_40; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_42 = l_idx_temp_vec_12 ? 6'hC : _l_idx_idx_T_41; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_43 = l_idx_temp_vec_11 ? 6'hB : _l_idx_idx_T_42; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_44 = l_idx_temp_vec_10 ? 6'hA : _l_idx_idx_T_43; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_45 = l_idx_temp_vec_9 ? 6'h9 : _l_idx_idx_T_44; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_46 = l_idx_temp_vec_8 ? 6'h8 : _l_idx_idx_T_45; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_47 = l_idx_temp_vec_7 ? 6'h7 : _l_idx_idx_T_46; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_48 = l_idx_temp_vec_6 ? 6'h6 : _l_idx_idx_T_47; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_49 = l_idx_temp_vec_5 ? 6'h5 : _l_idx_idx_T_48; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_50 = l_idx_temp_vec_4 ? 6'h4 : _l_idx_idx_T_49; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_51 = l_idx_temp_vec_3 ? 6'h3 : _l_idx_idx_T_50; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_52 = l_idx_temp_vec_2 ? 6'h2 : _l_idx_idx_T_51; // @[Mux.scala:50:70] wire [5:0] _l_idx_idx_T_53 = l_idx_temp_vec_1 ? 6'h1 : _l_idx_idx_T_52; // @[Mux.scala:50:70] wire [5:0] l_idx_idx = l_idx_temp_vec_0 ? 6'h0 : _l_idx_idx_T_53; // @[Mux.scala:50:70] wire [4:0] l_idx = l_idx_idx[4:0]; // @[Mux.scala:50:70] reg r_xcpt_valid; // @[lsu.scala:1434:29] reg [31:0] r_xcpt_uop_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_inst_0 = r_xcpt_uop_inst; // @[lsu.scala:211:7, :1435:25] reg [31:0] r_xcpt_uop_debug_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_inst_0 = r_xcpt_uop_debug_inst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rvc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rvc_0 = r_xcpt_uop_is_rvc; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_uop_debug_pc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_pc_0 = r_xcpt_uop_debug_pc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_0_0 = r_xcpt_uop_iq_type_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_1_0 = r_xcpt_uop_iq_type_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_2_0 = r_xcpt_uop_iq_type_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iq_type_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iq_type_3_0 = r_xcpt_uop_iq_type_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_0; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_0_0 = r_xcpt_uop_fu_code_0; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_1_0 = r_xcpt_uop_fu_code_1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_2_0 = r_xcpt_uop_fu_code_2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_3_0 = r_xcpt_uop_fu_code_3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_4; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_4_0 = r_xcpt_uop_fu_code_4; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_5; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_5_0 = r_xcpt_uop_fu_code_5; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_6; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_6_0 = r_xcpt_uop_fu_code_6; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_7; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_7_0 = r_xcpt_uop_fu_code_7; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_8; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_8_0 = r_xcpt_uop_fu_code_8; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fu_code_9; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fu_code_9_0 = r_xcpt_uop_fu_code_9; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_0 = r_xcpt_uop_iw_issued; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_agen_0 = r_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_issued_partial_dgen_0 = r_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_speculative_child_0 = r_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_speculative_child_0 = r_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p1_bypass_hint_0 = r_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p2_bypass_hint_0 = r_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_iw_p3_bypass_hint_0 = r_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_dis_col_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dis_col_sel_0 = r_xcpt_uop_dis_col_sel; // @[lsu.scala:211:7, :1435:25] reg [15:0] r_xcpt_uop_br_mask; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_mask_0 = r_xcpt_uop_br_mask; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_tag; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_tag_0 = r_xcpt_uop_br_tag; // @[lsu.scala:211:7, :1435:25] reg [3:0] r_xcpt_uop_br_type; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_br_type_0 = r_xcpt_uop_br_type; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfb; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfb_0 = r_xcpt_uop_is_sfb; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fence_0 = r_xcpt_uop_is_fence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_fencei; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_fencei_0 = r_xcpt_uop_is_fencei; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sfence; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sfence_0 = r_xcpt_uop_is_sfence; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_amo; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_amo_0 = r_xcpt_uop_is_amo; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_eret; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_eret_0 = r_xcpt_uop_is_eret; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_sys_pc2epc_0 = r_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_rocc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_rocc_0 = r_xcpt_uop_is_rocc; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_mov; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_mov_0 = r_xcpt_uop_is_mov; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ftq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ftq_idx_0 = r_xcpt_uop_ftq_idx; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_edge_inst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_edge_inst_0 = r_xcpt_uop_edge_inst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_pc_lob; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pc_lob_0 = r_xcpt_uop_pc_lob; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_taken; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_taken_0 = r_xcpt_uop_taken; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_imm_rename; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_rename_0 = r_xcpt_uop_imm_rename; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_imm_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_sel_0 = r_xcpt_uop_imm_sel; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_pimm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pimm_0 = r_xcpt_uop_pimm; // @[lsu.scala:211:7, :1435:25] reg [19:0] r_xcpt_uop_imm_packed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_imm_packed_0 = r_xcpt_uop_imm_packed; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_op1_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op1_sel_0 = r_xcpt_uop_op1_sel; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_op2_sel; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_op2_sel_0 = r_xcpt_uop_op2_sel; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ldst_0 = r_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wen_0 = r_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren1_0 = r_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren2_0 = r_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_ren3_0 = r_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap12_0 = r_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_swap23_0 = r_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = r_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = r_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fromint_0 = r_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_toint_0 = r_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = r_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_fma_0 = r_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_div_0 = r_xcpt_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_sqrt_0 = r_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_wflags_0 = r_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_ctrl_vec_0 = r_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_rob_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rob_idx_0 = r_xcpt_uop_rob_idx; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ldq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldq_idx_0 = r_xcpt_uop_ldq_idx; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_stq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stq_idx_0 = r_xcpt_uop_stq_idx; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_rxq_idx; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_rxq_idx_0 = r_xcpt_uop_rxq_idx; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_pdst_0 = r_xcpt_uop_pdst; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_0 = r_xcpt_uop_prs1; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_0 = r_xcpt_uop_prs2; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_prs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_0 = r_xcpt_uop_prs3; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_ppred; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_0 = r_xcpt_uop_ppred; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs1_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs1_busy_0 = r_xcpt_uop_prs1_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs2_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs2_busy_0 = r_xcpt_uop_prs2_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_prs3_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_prs3_busy_0 = r_xcpt_uop_prs3_busy; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ppred_busy; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ppred_busy_0 = r_xcpt_uop_ppred_busy; // @[lsu.scala:211:7, :1435:25] reg [6:0] r_xcpt_uop_stale_pdst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_stale_pdst_0 = r_xcpt_uop_stale_pdst; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_exception; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exception_0 = r_xcpt_uop_exception; // @[lsu.scala:211:7, :1435:25] reg [63:0] r_xcpt_uop_exc_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_exc_cause_0 = r_xcpt_uop_exc_cause; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_mem_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_cmd_0 = r_xcpt_uop_mem_cmd; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_mem_size; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_size_0 = r_xcpt_uop_mem_size; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_mem_signed; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_mem_signed_0 = r_xcpt_uop_mem_signed; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_ldq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_ldq_0 = r_xcpt_uop_uses_ldq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_uses_stq; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_uses_stq_0 = r_xcpt_uop_uses_stq; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_is_unique; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_is_unique_0 = r_xcpt_uop_is_unique; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_flush_on_commit; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_flush_on_commit_0 = r_xcpt_uop_flush_on_commit; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_csr_cmd; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_csr_cmd_0 = r_xcpt_uop_csr_cmd; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_is_rs1_0 = r_xcpt_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_ldst; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_ldst_0 = r_xcpt_uop_ldst; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs1; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_0 = r_xcpt_uop_lrs1; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs2; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_0 = r_xcpt_uop_lrs2; // @[lsu.scala:211:7, :1435:25] reg [5:0] r_xcpt_uop_lrs3; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs3_0 = r_xcpt_uop_lrs3; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_dst_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_dst_rtype_0 = r_xcpt_uop_dst_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs1_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs1_rtype_0 = r_xcpt_uop_lrs1_rtype; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_lrs2_rtype; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_lrs2_rtype_0 = r_xcpt_uop_lrs2_rtype; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_frs3_en; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_frs3_en_0 = r_xcpt_uop_frs3_en; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fcn_dw; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_dw_0 = r_xcpt_uop_fcn_dw; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_uop_fcn_op; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fcn_op_0 = r_xcpt_uop_fcn_op; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_fp_val; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_val_0 = r_xcpt_uop_fp_val; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_fp_rm; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_rm_0 = r_xcpt_uop_fp_rm; // @[lsu.scala:211:7, :1435:25] reg [1:0] r_xcpt_uop_fp_typ; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_fp_typ_0 = r_xcpt_uop_fp_typ; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_pf_if_0 = r_xcpt_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ae_if_0 = r_xcpt_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_xcpt_ma_if_0 = r_xcpt_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_debug_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_debug_if_0 = r_xcpt_uop_bp_debug_if; // @[lsu.scala:211:7, :1435:25] reg r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_bp_xcpt_if_0 = r_xcpt_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_fsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_fsrc_0 = r_xcpt_uop_debug_fsrc; // @[lsu.scala:211:7, :1435:25] reg [2:0] r_xcpt_uop_debug_tsrc; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_uop_debug_tsrc_0 = r_xcpt_uop_debug_tsrc; // @[lsu.scala:211:7, :1435:25] reg [4:0] r_xcpt_cause; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_cause_0 = r_xcpt_cause; // @[lsu.scala:211:7, :1435:25] reg [39:0] r_xcpt_badvaddr; // @[lsu.scala:1435:25] assign io_core_lxcpt_bits_badvaddr_0 = r_xcpt_badvaddr; // @[lsu.scala:211:7, :1435:25] wire [1:0] ld_xcpt_valid_lo_lo_lo_hi = {ldq_order_fail_2, ldq_order_fail_1}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_lo_lo = {ld_xcpt_valid_lo_lo_lo_hi, ldq_order_fail_0}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_lo_hi_hi = {ldq_order_fail_5, ldq_order_fail_4}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_lo_hi = {ld_xcpt_valid_lo_lo_hi_hi, ldq_order_fail_3}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_lo_lo = {ld_xcpt_valid_lo_lo_hi, ld_xcpt_valid_lo_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_lo_hi_lo_hi = {ldq_order_fail_8, ldq_order_fail_7}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_hi_lo = {ld_xcpt_valid_lo_hi_lo_hi, ldq_order_fail_6}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_lo_hi_hi_hi = {ldq_order_fail_11, ldq_order_fail_10}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_lo_hi_hi = {ld_xcpt_valid_lo_hi_hi_hi, ldq_order_fail_9}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_lo_hi = {ld_xcpt_valid_lo_hi_hi, ld_xcpt_valid_lo_hi_lo}; // @[lsu.scala:1437:39] wire [11:0] ld_xcpt_valid_lo = {ld_xcpt_valid_lo_hi, ld_xcpt_valid_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_lo_lo_hi = {ldq_order_fail_14, ldq_order_fail_13}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_lo_lo = {ld_xcpt_valid_hi_lo_lo_hi, ldq_order_fail_12}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_lo_hi_hi = {ldq_order_fail_17, ldq_order_fail_16}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_lo_hi = {ld_xcpt_valid_hi_lo_hi_hi, ldq_order_fail_15}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_hi_lo = {ld_xcpt_valid_hi_lo_hi, ld_xcpt_valid_hi_lo_lo}; // @[lsu.scala:1437:39] wire [1:0] ld_xcpt_valid_hi_hi_lo_hi = {ldq_order_fail_20, ldq_order_fail_19}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_hi_lo = {ld_xcpt_valid_hi_hi_lo_hi, ldq_order_fail_18}; // @[lsu.scala:225:36, :1437:39] wire [1:0] ld_xcpt_valid_hi_hi_hi_hi = {ldq_order_fail_23, ldq_order_fail_22}; // @[lsu.scala:225:36, :1437:39] wire [2:0] ld_xcpt_valid_hi_hi_hi = {ld_xcpt_valid_hi_hi_hi_hi, ldq_order_fail_21}; // @[lsu.scala:225:36, :1437:39] wire [5:0] ld_xcpt_valid_hi_hi = {ld_xcpt_valid_hi_hi_hi, ld_xcpt_valid_hi_hi_lo}; // @[lsu.scala:1437:39] wire [11:0] ld_xcpt_valid_hi = {ld_xcpt_valid_hi_hi, ld_xcpt_valid_hi_lo}; // @[lsu.scala:1437:39] wire [23:0] _ld_xcpt_valid_T = {ld_xcpt_valid_hi, ld_xcpt_valid_lo}; // @[lsu.scala:1437:39] wire [2:0] ld_xcpt_valid_lo_lo_lo_1 = {ld_xcpt_valid_lo_lo_lo_hi_1, ldq_valid_0}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_lo_lo_hi_1 = {ld_xcpt_valid_lo_lo_hi_hi_1, ldq_valid_3}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_lo_lo_1 = {ld_xcpt_valid_lo_lo_hi_1, ld_xcpt_valid_lo_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_lo_hi_lo_1 = {ld_xcpt_valid_lo_hi_lo_hi_1, ldq_valid_6}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_lo_hi_hi_1 = {ld_xcpt_valid_lo_hi_hi_hi_1, ldq_valid_9}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_lo_hi_1 = {ld_xcpt_valid_lo_hi_hi_1, ld_xcpt_valid_lo_hi_lo_1}; // @[lsu.scala:1437:58] wire [11:0] ld_xcpt_valid_lo_1 = {ld_xcpt_valid_lo_hi_1, ld_xcpt_valid_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_hi_lo_lo_1 = {ld_xcpt_valid_hi_lo_lo_hi_1, ldq_valid_12}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_hi_lo_hi_1 = {ld_xcpt_valid_hi_lo_hi_hi_1, ldq_valid_15}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_hi_lo_1 = {ld_xcpt_valid_hi_lo_hi_1, ld_xcpt_valid_hi_lo_lo_1}; // @[lsu.scala:1437:58] wire [2:0] ld_xcpt_valid_hi_hi_lo_1 = {ld_xcpt_valid_hi_hi_lo_hi_1, ldq_valid_18}; // @[lsu.scala:218:36, :1437:58] wire [2:0] ld_xcpt_valid_hi_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_hi_1, ldq_valid_21}; // @[lsu.scala:218:36, :1437:58] wire [5:0] ld_xcpt_valid_hi_hi_1 = {ld_xcpt_valid_hi_hi_hi_1, ld_xcpt_valid_hi_hi_lo_1}; // @[lsu.scala:1437:58] wire [11:0] ld_xcpt_valid_hi_1 = {ld_xcpt_valid_hi_hi_1, ld_xcpt_valid_hi_lo_1}; // @[lsu.scala:1437:58] wire [23:0] _ld_xcpt_valid_T_1 = {ld_xcpt_valid_hi_1, ld_xcpt_valid_lo_1}; // @[lsu.scala:1437:58] wire [23:0] _ld_xcpt_valid_T_2 = _ld_xcpt_valid_T & _ld_xcpt_valid_T_1; // @[lsu.scala:1437:{39,46,58}] wire ld_xcpt_valid = |_ld_xcpt_valid_T_2; // @[lsu.scala:1437:{46,66}] wire _ld_xcpt_uop_T = l_idx > 5'h17; // @[util.scala:354:8] wire [5:0] _ld_xcpt_uop_T_1 = {1'h0, l_idx} - 6'h18; // @[util.scala:354:8] wire [4:0] _ld_xcpt_uop_T_2 = _ld_xcpt_uop_T_1[4:0]; // @[lsu.scala:1438:76] wire [4:0] _ld_xcpt_uop_T_3 = _ld_xcpt_uop_T ? _ld_xcpt_uop_T_2 : l_idx; // @[util.scala:354:8] wire ld_xcpt_uop_iq_type_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iq_type_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_0; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_4; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_5; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_6; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_7; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_8; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fu_code_9; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_inst; // @[lsu.scala:1438:31] wire [31:0] ld_xcpt_uop_debug_inst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rvc; // @[lsu.scala:1438:31] wire [39:0] ld_xcpt_uop_debug_pc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:1438:31] wire ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_dis_col_sel; // @[lsu.scala:1438:31] wire [15:0] ld_xcpt_uop_br_mask; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_tag; // @[lsu.scala:1438:31] wire [3:0] ld_xcpt_uop_br_type; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfb; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_fencei; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sfence; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_amo; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_eret; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_rocc; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_mov; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ftq_idx; // @[lsu.scala:1438:31] wire ld_xcpt_uop_edge_inst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_pc_lob; // @[lsu.scala:1438:31] wire ld_xcpt_uop_taken; // @[lsu.scala:1438:31] wire ld_xcpt_uop_imm_rename; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_imm_sel; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_pimm; // @[lsu.scala:1438:31] wire [19:0] ld_xcpt_uop_imm_packed; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_op1_sel; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_op2_sel; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_rob_idx; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ldq_idx; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_stq_idx; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_rxq_idx; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_pdst; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs1; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs2; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_prs3; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_ppred; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs1_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs2_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_prs3_busy; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ppred_busy; // @[lsu.scala:1438:31] wire [6:0] ld_xcpt_uop_stale_pdst; // @[lsu.scala:1438:31] wire ld_xcpt_uop_exception; // @[lsu.scala:1438:31] wire [63:0] ld_xcpt_uop_exc_cause; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_mem_cmd; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_mem_size; // @[lsu.scala:1438:31] wire ld_xcpt_uop_mem_signed; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_ldq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_uses_stq; // @[lsu.scala:1438:31] wire ld_xcpt_uop_is_unique; // @[lsu.scala:1438:31] wire ld_xcpt_uop_flush_on_commit; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_csr_cmd; // @[lsu.scala:1438:31] wire ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_ldst; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs1; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs2; // @[lsu.scala:1438:31] wire [5:0] ld_xcpt_uop_lrs3; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_dst_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:1438:31] wire ld_xcpt_uop_frs3_en; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fcn_dw; // @[lsu.scala:1438:31] wire [4:0] ld_xcpt_uop_fcn_op; // @[lsu.scala:1438:31] wire ld_xcpt_uop_fp_val; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_fp_rm; // @[lsu.scala:1438:31] wire [1:0] ld_xcpt_uop_fp_typ; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_debug_if; // @[lsu.scala:1438:31] wire ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_fsrc; // @[lsu.scala:1438:31] wire [2:0] ld_xcpt_uop_debug_tsrc; // @[lsu.scala:1438:31] assign ld_xcpt_uop_inst = _GEN_127[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_inst = _GEN_128[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_rvc = _GEN_129[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_pc = _GEN_130[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_0 = _GEN_131[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_1 = _GEN_132[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_2 = _GEN_133[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iq_type_3 = _GEN_134[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_0 = _GEN_135[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_1 = _GEN_136[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_2 = _GEN_137[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_3 = _GEN_138[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_4 = _GEN_139[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_5 = _GEN_140[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_6 = _GEN_141[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_7 = _GEN_142[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_8 = _GEN_143[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fu_code_9 = _GEN_144[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued = _GEN_145[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued_partial_agen = _GEN_146[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_issued_partial_dgen = _GEN_147[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p1_speculative_child = _GEN_148[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p2_speculative_child = _GEN_149[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p1_bypass_hint = _GEN_150[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p2_bypass_hint = _GEN_151[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_iw_p3_bypass_hint = _GEN_152[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_dis_col_sel = _GEN_153[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_mask = _GEN_154[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_tag = _GEN_155[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_br_type = _GEN_156[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sfb = _GEN_157[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_fence = _GEN_158[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_fencei = _GEN_159[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sfence = _GEN_160[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_amo = _GEN_161[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_eret = _GEN_162[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_sys_pc2epc = _GEN_163[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_rocc = _GEN_164[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_mov = _GEN_165[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ftq_idx = _GEN_166[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_edge_inst = _GEN_167[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pc_lob = _GEN_168[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_taken = _GEN_169[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_rename = _GEN_170[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_sel = _GEN_171[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pimm = _GEN_172[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_imm_packed = _GEN_173[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_op1_sel = _GEN_174[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_op2_sel = _GEN_175[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ldst = _GEN_176[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_wen = _GEN_177[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren1 = _GEN_178[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren2 = _GEN_179[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_ren3 = _GEN_180[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_swap12 = _GEN_181[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_swap23 = _GEN_182[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_typeTagIn = _GEN_183[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_typeTagOut = _GEN_184[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fromint = _GEN_185[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_toint = _GEN_186[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fastpipe = _GEN_187[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_fma = _GEN_188[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_div = _GEN_189[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_sqrt = _GEN_190[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_wflags = _GEN_191[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_ctrl_vec = _GEN_192[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_rob_idx = _GEN_193[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldq_idx = _GEN_194[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_stq_idx = _GEN_195[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_rxq_idx = _GEN_196[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_pdst = _GEN_197[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs1 = _GEN_198[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs2 = _GEN_199[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs3 = _GEN_200[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ppred = _GEN_201[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs1_busy = _GEN_202[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs2_busy = _GEN_203[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_prs3_busy = _GEN_204[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ppred_busy = _GEN_205[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_stale_pdst = _GEN_206[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_exception = _GEN_207[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_exc_cause = _GEN_208[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_cmd = _GEN_209[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_size = _GEN_210[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_mem_signed = _GEN_211[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_uses_ldq = _GEN_212[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_uses_stq = _GEN_213[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_is_unique = _GEN_214[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_flush_on_commit = _GEN_215[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_csr_cmd = _GEN_216[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldst_is_rs1 = _GEN_217[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_ldst = _GEN_218[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs1 = _GEN_219[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs2 = _GEN_220[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs3 = _GEN_221[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_dst_rtype = _GEN_222[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs1_rtype = _GEN_223[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_lrs2_rtype = _GEN_224[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_frs3_en = _GEN_225[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fcn_dw = _GEN_226[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fcn_op = _GEN_227[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_val = _GEN_228[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_rm = _GEN_229[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_fp_typ = _GEN_230[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_pf_if = _GEN_231[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_ae_if = _GEN_232[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_xcpt_ma_if = _GEN_233[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_bp_debug_if = _GEN_234[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_bp_xcpt_if = _GEN_235[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_fsrc = _GEN_236[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] assign ld_xcpt_uop_debug_tsrc = _GEN_237[_ld_xcpt_uop_T_3]; // @[lsu.scala:235:32, :1438:{31,43}] wire _use_mem_xcpt_T = mem_xcpt_uop_rob_idx < ld_xcpt_uop_rob_idx; // @[util.scala:364:52] wire _use_mem_xcpt_T_1 = mem_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:64] wire _use_mem_xcpt_T_2 = _use_mem_xcpt_T ^ _use_mem_xcpt_T_1; // @[util.scala:364:{52,58,64}] wire _use_mem_xcpt_T_3 = ld_xcpt_uop_rob_idx < io_core_rob_head_idx_0; // @[util.scala:364:78] wire _use_mem_xcpt_T_4 = _use_mem_xcpt_T_2 ^ _use_mem_xcpt_T_3; // @[util.scala:364:{58,72,78}] wire _use_mem_xcpt_T_5 = mem_xcpt_valid & _use_mem_xcpt_T_4; // @[util.scala:364:72] wire _use_mem_xcpt_T_6 = ~ld_xcpt_valid; // @[lsu.scala:1437:66, :1440:118] wire use_mem_xcpt = _use_mem_xcpt_T_5 | _use_mem_xcpt_T_6; // @[lsu.scala:1440:{38,115,118}] wire [31:0] xcpt_uop_inst = use_mem_xcpt ? mem_xcpt_uop_inst : ld_xcpt_uop_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [31:0] xcpt_uop_debug_inst = use_mem_xcpt ? mem_xcpt_uop_debug_inst : ld_xcpt_uop_debug_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rvc = use_mem_xcpt ? mem_xcpt_uop_is_rvc : ld_xcpt_uop_is_rvc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [39:0] xcpt_uop_debug_pc = use_mem_xcpt ? mem_xcpt_uop_debug_pc : ld_xcpt_uop_debug_pc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_0 = use_mem_xcpt ? mem_xcpt_uop_iq_type_0 : ld_xcpt_uop_iq_type_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_1 = use_mem_xcpt ? mem_xcpt_uop_iq_type_1 : ld_xcpt_uop_iq_type_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_2 = use_mem_xcpt ? mem_xcpt_uop_iq_type_2 : ld_xcpt_uop_iq_type_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iq_type_3 = use_mem_xcpt ? mem_xcpt_uop_iq_type_3 : ld_xcpt_uop_iq_type_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_0 = use_mem_xcpt ? mem_xcpt_uop_fu_code_0 : ld_xcpt_uop_fu_code_0; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_1 = use_mem_xcpt ? mem_xcpt_uop_fu_code_1 : ld_xcpt_uop_fu_code_1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_2 = use_mem_xcpt ? mem_xcpt_uop_fu_code_2 : ld_xcpt_uop_fu_code_2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_3 = use_mem_xcpt ? mem_xcpt_uop_fu_code_3 : ld_xcpt_uop_fu_code_3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_4 = use_mem_xcpt ? mem_xcpt_uop_fu_code_4 : ld_xcpt_uop_fu_code_4; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_5 = use_mem_xcpt ? mem_xcpt_uop_fu_code_5 : ld_xcpt_uop_fu_code_5; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_6 = use_mem_xcpt ? mem_xcpt_uop_fu_code_6 : ld_xcpt_uop_fu_code_6; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_7 = use_mem_xcpt ? mem_xcpt_uop_fu_code_7 : ld_xcpt_uop_fu_code_7; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_8 = use_mem_xcpt ? mem_xcpt_uop_fu_code_8 : ld_xcpt_uop_fu_code_8; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fu_code_9 = use_mem_xcpt ? mem_xcpt_uop_fu_code_9 : ld_xcpt_uop_fu_code_9; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued = use_mem_xcpt ? mem_xcpt_uop_iw_issued : ld_xcpt_uop_iw_issued; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_agen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_agen : ld_xcpt_uop_iw_issued_partial_agen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_issued_partial_dgen = use_mem_xcpt ? mem_xcpt_uop_iw_issued_partial_dgen : ld_xcpt_uop_iw_issued_partial_dgen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_iw_p1_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p1_speculative_child : ld_xcpt_uop_iw_p1_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_iw_p2_speculative_child = use_mem_xcpt ? mem_xcpt_uop_iw_p2_speculative_child : ld_xcpt_uop_iw_p2_speculative_child; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p1_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p1_bypass_hint : ld_xcpt_uop_iw_p1_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p2_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p2_bypass_hint : ld_xcpt_uop_iw_p2_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_iw_p3_bypass_hint = use_mem_xcpt ? mem_xcpt_uop_iw_p3_bypass_hint : ld_xcpt_uop_iw_p3_bypass_hint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_dis_col_sel = use_mem_xcpt ? mem_xcpt_uop_dis_col_sel : ld_xcpt_uop_dis_col_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [15:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uop_br_mask : ld_xcpt_uop_br_mask; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_tag = use_mem_xcpt ? mem_xcpt_uop_br_tag : ld_xcpt_uop_br_tag; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [3:0] xcpt_uop_br_type = use_mem_xcpt ? mem_xcpt_uop_br_type : ld_xcpt_uop_br_type; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfb = use_mem_xcpt ? mem_xcpt_uop_is_sfb : ld_xcpt_uop_is_sfb; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fence = use_mem_xcpt ? mem_xcpt_uop_is_fence : ld_xcpt_uop_is_fence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_fencei = use_mem_xcpt ? mem_xcpt_uop_is_fencei : ld_xcpt_uop_is_fencei; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sfence = use_mem_xcpt ? mem_xcpt_uop_is_sfence : ld_xcpt_uop_is_sfence; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_amo = use_mem_xcpt ? mem_xcpt_uop_is_amo : ld_xcpt_uop_is_amo; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_eret = use_mem_xcpt ? mem_xcpt_uop_is_eret : ld_xcpt_uop_is_eret; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_sys_pc2epc = use_mem_xcpt ? mem_xcpt_uop_is_sys_pc2epc : ld_xcpt_uop_is_sys_pc2epc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_rocc = use_mem_xcpt ? mem_xcpt_uop_is_rocc : ld_xcpt_uop_is_rocc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_mov = use_mem_xcpt ? mem_xcpt_uop_is_mov : ld_xcpt_uop_is_mov; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ftq_idx = use_mem_xcpt ? mem_xcpt_uop_ftq_idx : ld_xcpt_uop_ftq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_edge_inst = use_mem_xcpt ? mem_xcpt_uop_edge_inst : ld_xcpt_uop_edge_inst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_pc_lob = use_mem_xcpt ? mem_xcpt_uop_pc_lob : ld_xcpt_uop_pc_lob; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_taken = use_mem_xcpt ? mem_xcpt_uop_taken : ld_xcpt_uop_taken; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_imm_rename = use_mem_xcpt ? mem_xcpt_uop_imm_rename : ld_xcpt_uop_imm_rename; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_imm_sel = use_mem_xcpt ? mem_xcpt_uop_imm_sel : ld_xcpt_uop_imm_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_pimm = use_mem_xcpt ? mem_xcpt_uop_pimm : ld_xcpt_uop_pimm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [19:0] xcpt_uop_imm_packed = use_mem_xcpt ? mem_xcpt_uop_imm_packed : ld_xcpt_uop_imm_packed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_op1_sel = use_mem_xcpt ? mem_xcpt_uop_op1_sel : ld_xcpt_uop_op1_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_op2_sel = use_mem_xcpt ? mem_xcpt_uop_op2_sel : ld_xcpt_uop_op2_sel; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ldst = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ldst : ld_xcpt_uop_fp_ctrl_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wen = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wen : ld_xcpt_uop_fp_ctrl_wen; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren1 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren1 : ld_xcpt_uop_fp_ctrl_ren1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren2 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren2 : ld_xcpt_uop_fp_ctrl_ren2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_ren3 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_ren3 : ld_xcpt_uop_fp_ctrl_ren3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap12 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap12 : ld_xcpt_uop_fp_ctrl_swap12; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_swap23 = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_swap23 : ld_xcpt_uop_fp_ctrl_swap23; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagIn = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagIn : ld_xcpt_uop_fp_ctrl_typeTagIn; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_ctrl_typeTagOut = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_typeTagOut : ld_xcpt_uop_fp_ctrl_typeTagOut; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fromint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fromint : ld_xcpt_uop_fp_ctrl_fromint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_toint = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_toint : ld_xcpt_uop_fp_ctrl_toint; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fastpipe = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fastpipe : ld_xcpt_uop_fp_ctrl_fastpipe; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_fma = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_fma : ld_xcpt_uop_fp_ctrl_fma; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_div = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_div : ld_xcpt_uop_fp_ctrl_div; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_sqrt = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_sqrt : ld_xcpt_uop_fp_ctrl_sqrt; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_wflags = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_wflags : ld_xcpt_uop_fp_ctrl_wflags; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_ctrl_vec = use_mem_xcpt ? mem_xcpt_uop_fp_ctrl_vec : ld_xcpt_uop_fp_ctrl_vec; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_rob_idx = use_mem_xcpt ? mem_xcpt_uop_rob_idx : ld_xcpt_uop_rob_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ldq_idx = use_mem_xcpt ? mem_xcpt_uop_ldq_idx : ld_xcpt_uop_ldq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_stq_idx = use_mem_xcpt ? mem_xcpt_uop_stq_idx : ld_xcpt_uop_stq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_rxq_idx = use_mem_xcpt ? mem_xcpt_uop_rxq_idx : ld_xcpt_uop_rxq_idx; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_pdst = use_mem_xcpt ? mem_xcpt_uop_pdst : ld_xcpt_uop_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs1 = use_mem_xcpt ? mem_xcpt_uop_prs1 : ld_xcpt_uop_prs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs2 = use_mem_xcpt ? mem_xcpt_uop_prs2 : ld_xcpt_uop_prs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_prs3 = use_mem_xcpt ? mem_xcpt_uop_prs3 : ld_xcpt_uop_prs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_ppred = use_mem_xcpt ? mem_xcpt_uop_ppred : ld_xcpt_uop_ppred; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs1_busy = use_mem_xcpt ? mem_xcpt_uop_prs1_busy : ld_xcpt_uop_prs1_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs2_busy = use_mem_xcpt ? mem_xcpt_uop_prs2_busy : ld_xcpt_uop_prs2_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_prs3_busy = use_mem_xcpt ? mem_xcpt_uop_prs3_busy : ld_xcpt_uop_prs3_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ppred_busy = use_mem_xcpt ? mem_xcpt_uop_ppred_busy : ld_xcpt_uop_ppred_busy; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [6:0] xcpt_uop_stale_pdst = use_mem_xcpt ? mem_xcpt_uop_stale_pdst : ld_xcpt_uop_stale_pdst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_exception = use_mem_xcpt ? mem_xcpt_uop_exception : ld_xcpt_uop_exception; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [63:0] xcpt_uop_exc_cause = use_mem_xcpt ? mem_xcpt_uop_exc_cause : ld_xcpt_uop_exc_cause; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_mem_cmd = use_mem_xcpt ? mem_xcpt_uop_mem_cmd : ld_xcpt_uop_mem_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_mem_size = use_mem_xcpt ? mem_xcpt_uop_mem_size : ld_xcpt_uop_mem_size; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_mem_signed = use_mem_xcpt ? mem_xcpt_uop_mem_signed : ld_xcpt_uop_mem_signed; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_ldq = use_mem_xcpt ? mem_xcpt_uop_uses_ldq : ld_xcpt_uop_uses_ldq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_uses_stq = use_mem_xcpt ? mem_xcpt_uop_uses_stq : ld_xcpt_uop_uses_stq; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_is_unique = use_mem_xcpt ? mem_xcpt_uop_is_unique : ld_xcpt_uop_is_unique; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_flush_on_commit = use_mem_xcpt ? mem_xcpt_uop_flush_on_commit : ld_xcpt_uop_flush_on_commit; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_csr_cmd = use_mem_xcpt ? mem_xcpt_uop_csr_cmd : ld_xcpt_uop_csr_cmd; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_ldst_is_rs1 = use_mem_xcpt ? mem_xcpt_uop_ldst_is_rs1 : ld_xcpt_uop_ldst_is_rs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_ldst = use_mem_xcpt ? mem_xcpt_uop_ldst : ld_xcpt_uop_ldst; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs1 = use_mem_xcpt ? mem_xcpt_uop_lrs1 : ld_xcpt_uop_lrs1; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs2 = use_mem_xcpt ? mem_xcpt_uop_lrs2 : ld_xcpt_uop_lrs2; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [5:0] xcpt_uop_lrs3 = use_mem_xcpt ? mem_xcpt_uop_lrs3 : ld_xcpt_uop_lrs3; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_dst_rtype = use_mem_xcpt ? mem_xcpt_uop_dst_rtype : ld_xcpt_uop_dst_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs1_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs1_rtype : ld_xcpt_uop_lrs1_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_lrs2_rtype = use_mem_xcpt ? mem_xcpt_uop_lrs2_rtype : ld_xcpt_uop_lrs2_rtype; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_frs3_en = use_mem_xcpt ? mem_xcpt_uop_frs3_en : ld_xcpt_uop_frs3_en; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fcn_dw = use_mem_xcpt ? mem_xcpt_uop_fcn_dw : ld_xcpt_uop_fcn_dw; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [4:0] xcpt_uop_fcn_op = use_mem_xcpt ? mem_xcpt_uop_fcn_op : ld_xcpt_uop_fcn_op; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_fp_val = use_mem_xcpt ? mem_xcpt_uop_fp_val : ld_xcpt_uop_fp_val; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_fp_rm = use_mem_xcpt ? mem_xcpt_uop_fp_rm : ld_xcpt_uop_fp_rm; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [1:0] xcpt_uop_fp_typ = use_mem_xcpt ? mem_xcpt_uop_fp_typ : ld_xcpt_uop_fp_typ; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_pf_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_pf_if : ld_xcpt_uop_xcpt_pf_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ae_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ae_if : ld_xcpt_uop_xcpt_ae_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_xcpt_ma_if = use_mem_xcpt ? mem_xcpt_uop_xcpt_ma_if : ld_xcpt_uop_xcpt_ma_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_debug_if = use_mem_xcpt ? mem_xcpt_uop_bp_debug_if : ld_xcpt_uop_bp_debug_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire xcpt_uop_bp_xcpt_if = use_mem_xcpt ? mem_xcpt_uop_bp_xcpt_if : ld_xcpt_uop_bp_xcpt_if; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_fsrc = use_mem_xcpt ? mem_xcpt_uop_debug_fsrc : ld_xcpt_uop_debug_fsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire [2:0] xcpt_uop_debug_tsrc = use_mem_xcpt ? mem_xcpt_uop_debug_tsrc : ld_xcpt_uop_debug_tsrc; // @[lsu.scala:459:29, :1438:31, :1440:115, :1442:21] wire _r_xcpt_valid_T = ld_xcpt_valid | mem_xcpt_valid; // @[lsu.scala:457:29, :1437:66, :1444:34] wire [15:0] _r_xcpt_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & xcpt_uop_br_mask; // @[util.scala:126:51] wire _r_xcpt_valid_T_2 = |_r_xcpt_valid_T_1; // @[util.scala:126:{51,59}] wire _r_xcpt_valid_T_3 = _r_xcpt_valid_T_2 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _r_xcpt_valid_T_4 = ~_r_xcpt_valid_T_3; // @[util.scala:61:61] wire _r_xcpt_valid_T_5 = _r_xcpt_valid_T & _r_xcpt_valid_T_4; // @[lsu.scala:1444:{34,53,56}] wire [15:0] _r_xcpt_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [15:0] _r_xcpt_uop_br_mask_T_1 = xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:93:{25,27}] wire [4:0] _r_xcpt_cause_T = use_mem_xcpt ? {1'h0, mem_xcpt_cause} : 5'h10; // @[lsu.scala:458:29, :1440:115, :1447:28] wire [15:0] _io_core_lxcpt_valid_T = io_core_brupdate_b1_mispredict_mask_0 & r_xcpt_uop_br_mask; // @[util.scala:126:51] wire _io_core_lxcpt_valid_T_1 = |_io_core_lxcpt_valid_T; // @[util.scala:126:{51,59}] wire _io_core_lxcpt_valid_T_2 = _io_core_lxcpt_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_lxcpt_valid_T_3 = ~_io_core_lxcpt_valid_T_2; // @[util.scala:61:61] assign _io_core_lxcpt_valid_T_4 = r_xcpt_valid & _io_core_lxcpt_valid_T_3; // @[lsu.scala:1434:29, :1450:{39,42}] assign io_core_lxcpt_valid_0 = _io_core_lxcpt_valid_T_4; // @[lsu.scala:211:7, :1450:39] reg wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:1458:47] wire _wakeupArbs_0_io_in_1_valid_T = fired_load_agen_exec_0 & wakeupArbs_0_io_in_1_valid_REG; // @[lsu.scala:321:49, :1457:69, :1458:47] wire _wakeupArbs_0_io_in_1_valid_T_2 = _wakeupArbs_0_io_in_1_valid_T; // @[lsu.scala:1457:69, :1458:69] wire _wakeupArbs_0_io_in_1_valid_T_3 = ~mem_incoming_uop_0_fp_val; // @[lsu.scala:1053:37, :1460:40] wire _wakeupArbs_0_io_in_1_valid_T_4 = _wakeupArbs_0_io_in_1_valid_T_2 & _wakeupArbs_0_io_in_1_valid_T_3; // @[lsu.scala:1458:69, :1459:69, :1460:40] wire [31:0] io_core_iresp_0_out_bits_uop_inst = iresp_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] io_core_iresp_0_out_bits_uop_debug_inst = iresp_0_bits_uop_debug_inst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rvc = iresp_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] io_core_iresp_0_out_bits_uop_debug_pc = iresp_0_bits_uop_debug_pc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_0 = iresp_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_1 = iresp_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_2 = iresp_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iq_type_3 = iresp_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_0 = iresp_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_1 = iresp_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_2 = iresp_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_3 = iresp_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_4 = iresp_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_5 = iresp_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_6 = iresp_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_7 = iresp_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_8 = iresp_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fu_code_9 = iresp_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued = iresp_0_bits_uop_iw_issued; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_agen = iresp_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_issued_partial_dgen = iresp_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_iw_p1_speculative_child = iresp_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_iw_p2_speculative_child = iresp_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p1_bypass_hint = iresp_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p2_bypass_hint = iresp_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_iw_p3_bypass_hint = iresp_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_dis_col_sel = iresp_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_tag = iresp_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] io_core_iresp_0_out_bits_uop_br_type = iresp_0_bits_uop_br_type; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfb = iresp_0_bits_uop_is_sfb; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fence = iresp_0_bits_uop_is_fence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_fencei = iresp_0_bits_uop_is_fencei; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sfence = iresp_0_bits_uop_is_sfence; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_amo = iresp_0_bits_uop_is_amo; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_eret = iresp_0_bits_uop_is_eret; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_sys_pc2epc = iresp_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_rocc = iresp_0_bits_uop_is_rocc; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_mov = iresp_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ftq_idx = iresp_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_edge_inst = iresp_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_pc_lob = iresp_0_bits_uop_pc_lob; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_taken = iresp_0_bits_uop_taken; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_imm_rename = iresp_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_imm_sel = iresp_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_pimm = iresp_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] io_core_iresp_0_out_bits_uop_imm_packed = iresp_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_op1_sel = iresp_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_op2_sel = iresp_0_bits_uop_op2_sel; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ldst = iresp_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wen = iresp_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren1 = iresp_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren2 = iresp_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_ren3 = iresp_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap12 = iresp_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_swap23 = iresp_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagIn = iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_ctrl_typeTagOut = iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fromint = iresp_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_toint = iresp_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fastpipe = iresp_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_fma = iresp_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_div = iresp_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_sqrt = iresp_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_wflags = iresp_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_ctrl_vec = iresp_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_rob_idx = iresp_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ldq_idx = iresp_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_stq_idx = iresp_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_rxq_idx = iresp_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_pdst = iresp_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs1 = iresp_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs2 = iresp_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_prs3 = iresp_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_ppred = iresp_0_bits_uop_ppred; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs1_busy = iresp_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs2_busy = iresp_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_prs3_busy = iresp_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ppred_busy = iresp_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] io_core_iresp_0_out_bits_uop_stale_pdst = iresp_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_exception = iresp_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_uop_exc_cause = iresp_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_mem_cmd = iresp_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_mem_size = iresp_0_bits_uop_mem_size; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_mem_signed = iresp_0_bits_uop_mem_signed; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_ldq = iresp_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_uses_stq = iresp_0_bits_uop_uses_stq; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_is_unique = iresp_0_bits_uop_is_unique; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_flush_on_commit = iresp_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_csr_cmd = iresp_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_ldst_is_rs1 = iresp_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_ldst = iresp_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs1 = iresp_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs2 = iresp_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] io_core_iresp_0_out_bits_uop_lrs3 = iresp_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_dst_rtype = iresp_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs1_rtype = iresp_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_lrs2_rtype = iresp_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_frs3_en = iresp_0_bits_uop_frs3_en; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fcn_dw = iresp_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] io_core_iresp_0_out_bits_uop_fcn_op = iresp_0_bits_uop_fcn_op; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_fp_val = iresp_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_fp_rm = iresp_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] io_core_iresp_0_out_bits_uop_fp_typ = iresp_0_bits_uop_fp_typ; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_pf_if = iresp_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ae_if = iresp_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_xcpt_ma_if = iresp_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_debug_if = iresp_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire io_core_iresp_0_out_bits_uop_bp_xcpt_if = iresp_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_fsrc = iresp_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] io_core_iresp_0_out_bits_uop_debug_tsrc = iresp_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [63:0] io_core_iresp_0_out_bits_data = iresp_0_bits_data; // @[util.scala:114:23] wire [15:0] iresp_0_bits_uop_br_mask; // @[lsu.scala:1477:19] wire iresp_0_valid; // @[lsu.scala:1477:19] assign io_core_fresp_0_valid_0 = fresp_0_valid; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_inst_0 = fresp_0_bits_uop_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_inst_0 = fresp_0_bits_uop_debug_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rvc_0 = fresp_0_bits_uop_is_rvc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_pc_0 = fresp_0_bits_uop_debug_pc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_0_0 = fresp_0_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_1_0 = fresp_0_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_2_0 = fresp_0_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iq_type_3_0 = fresp_0_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_0_0 = fresp_0_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_1_0 = fresp_0_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_2_0 = fresp_0_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_3_0 = fresp_0_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_4_0 = fresp_0_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_5_0 = fresp_0_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_6_0 = fresp_0_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_7_0 = fresp_0_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_8_0 = fresp_0_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fu_code_9_0 = fresp_0_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_0 = fresp_0_bits_uop_iw_issued; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_agen_0 = fresp_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_issued_partial_dgen_0 = fresp_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_speculative_child_0 = fresp_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_speculative_child_0 = fresp_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p1_bypass_hint_0 = fresp_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p2_bypass_hint_0 = fresp_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_iw_p3_bypass_hint_0 = fresp_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dis_col_sel_0 = fresp_0_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_mask_0 = fresp_0_bits_uop_br_mask; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_tag_0 = fresp_0_bits_uop_br_tag; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_br_type_0 = fresp_0_bits_uop_br_type; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfb_0 = fresp_0_bits_uop_is_sfb; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fence_0 = fresp_0_bits_uop_is_fence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_fencei_0 = fresp_0_bits_uop_is_fencei; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sfence_0 = fresp_0_bits_uop_is_sfence; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_amo_0 = fresp_0_bits_uop_is_amo; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_eret_0 = fresp_0_bits_uop_is_eret; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_sys_pc2epc_0 = fresp_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_rocc_0 = fresp_0_bits_uop_is_rocc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_mov_0 = fresp_0_bits_uop_is_mov; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ftq_idx_0 = fresp_0_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_edge_inst_0 = fresp_0_bits_uop_edge_inst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pc_lob_0 = fresp_0_bits_uop_pc_lob; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_taken_0 = fresp_0_bits_uop_taken; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_rename_0 = fresp_0_bits_uop_imm_rename; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_sel_0 = fresp_0_bits_uop_imm_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pimm_0 = fresp_0_bits_uop_pimm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_imm_packed_0 = fresp_0_bits_uop_imm_packed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op1_sel_0 = fresp_0_bits_uop_op1_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_op2_sel_0 = fresp_0_bits_uop_op2_sel; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ldst_0 = fresp_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wen_0 = fresp_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren1_0 = fresp_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren2_0 = fresp_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_ren3_0 = fresp_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap12_0 = fresp_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_swap23_0 = fresp_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fromint_0 = fresp_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_toint_0 = fresp_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = fresp_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_fma_0 = fresp_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_div_0 = fresp_0_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_sqrt_0 = fresp_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_wflags_0 = fresp_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_ctrl_vec_0 = fresp_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rob_idx_0 = fresp_0_bits_uop_rob_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldq_idx_0 = fresp_0_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stq_idx_0 = fresp_0_bits_uop_stq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_rxq_idx_0 = fresp_0_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_pdst_0 = fresp_0_bits_uop_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_0 = fresp_0_bits_uop_prs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_0 = fresp_0_bits_uop_prs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_0 = fresp_0_bits_uop_prs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_0 = fresp_0_bits_uop_ppred; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs1_busy_0 = fresp_0_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs2_busy_0 = fresp_0_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_prs3_busy_0 = fresp_0_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ppred_busy_0 = fresp_0_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_stale_pdst_0 = fresp_0_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exception_0 = fresp_0_bits_uop_exception; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_exc_cause_0 = fresp_0_bits_uop_exc_cause; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_cmd_0 = fresp_0_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_size_0 = fresp_0_bits_uop_mem_size; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_mem_signed_0 = fresp_0_bits_uop_mem_signed; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_ldq_0 = fresp_0_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_uses_stq_0 = fresp_0_bits_uop_uses_stq; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_is_unique_0 = fresp_0_bits_uop_is_unique; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_flush_on_commit_0 = fresp_0_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_csr_cmd_0 = fresp_0_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_is_rs1_0 = fresp_0_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_ldst_0 = fresp_0_bits_uop_ldst; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_0 = fresp_0_bits_uop_lrs1; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_0 = fresp_0_bits_uop_lrs2; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs3_0 = fresp_0_bits_uop_lrs3; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_dst_rtype_0 = fresp_0_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs1_rtype_0 = fresp_0_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_lrs2_rtype_0 = fresp_0_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_frs3_en_0 = fresp_0_bits_uop_frs3_en; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_dw_0 = fresp_0_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fcn_op_0 = fresp_0_bits_uop_fcn_op; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_val_0 = fresp_0_bits_uop_fp_val; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_rm_0 = fresp_0_bits_uop_fp_rm; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_fp_typ_0 = fresp_0_bits_uop_fp_typ; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_pf_if_0 = fresp_0_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ae_if_0 = fresp_0_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_xcpt_ma_if_0 = fresp_0_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_debug_if_0 = fresp_0_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_bp_xcpt_if_0 = fresp_0_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_fsrc_0 = fresp_0_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_uop_debug_tsrc_0 = fresp_0_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1478:19] assign io_core_fresp_0_bits_data_0 = fresp_0_bits_data; // @[lsu.scala:211:7, :1478:19] wire _io_core_iresp_0_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] io_core_iresp_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire io_core_iresp_0_out_valid; // @[util.scala:114:23] wire [15:0] _io_core_iresp_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _io_core_iresp_0_out_bits_uop_br_mask_T_1 = iresp_0_bits_uop_br_mask & _io_core_iresp_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign io_core_iresp_0_out_bits_uop_br_mask = _io_core_iresp_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _io_core_iresp_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & iresp_0_bits_uop_br_mask; // @[util.scala:126:51] wire _io_core_iresp_0_out_valid_T_1 = |_io_core_iresp_0_out_valid_T; // @[util.scala:126:{51,59}] wire _io_core_iresp_0_out_valid_T_2 = _io_core_iresp_0_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _io_core_iresp_0_out_valid_T_3 = ~_io_core_iresp_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _io_core_iresp_0_out_valid_T_4 = iresp_0_valid & _io_core_iresp_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign io_core_iresp_0_out_valid = _io_core_iresp_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg io_core_iresp_0_REG_valid; // @[lsu.scala:1485:70] assign io_core_iresp_0_valid_0 = io_core_iresp_0_REG_valid; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_inst_0 = io_core_iresp_0_REG_bits_uop_inst; // @[lsu.scala:211:7, :1485:70] reg [31:0] io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_inst_0 = io_core_iresp_0_REG_bits_uop_debug_inst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rvc_0 = io_core_iresp_0_REG_bits_uop_is_rvc; // @[lsu.scala:211:7, :1485:70] reg [39:0] io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_pc_0 = io_core_iresp_0_REG_bits_uop_debug_pc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_0_0 = io_core_iresp_0_REG_bits_uop_iq_type_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_1_0 = io_core_iresp_0_REG_bits_uop_iq_type_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_2_0 = io_core_iresp_0_REG_bits_uop_iq_type_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iq_type_3_0 = io_core_iresp_0_REG_bits_uop_iq_type_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_0_0 = io_core_iresp_0_REG_bits_uop_fu_code_0; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_1_0 = io_core_iresp_0_REG_bits_uop_fu_code_1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_2_0 = io_core_iresp_0_REG_bits_uop_fu_code_2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_3_0 = io_core_iresp_0_REG_bits_uop_fu_code_3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_4_0 = io_core_iresp_0_REG_bits_uop_fu_code_4; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_5_0 = io_core_iresp_0_REG_bits_uop_fu_code_5; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_6_0 = io_core_iresp_0_REG_bits_uop_fu_code_6; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_7_0 = io_core_iresp_0_REG_bits_uop_fu_code_7; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_8_0 = io_core_iresp_0_REG_bits_uop_fu_code_8; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fu_code_9_0 = io_core_iresp_0_REG_bits_uop_fu_code_9; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_0 = io_core_iresp_0_REG_bits_uop_iw_issued; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_core_iresp_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_core_iresp_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_core_iresp_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dis_col_sel_0 = io_core_iresp_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:211:7, :1485:70] reg [15:0] io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_mask_0 = io_core_iresp_0_REG_bits_uop_br_mask; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_tag_0 = io_core_iresp_0_REG_bits_uop_br_tag; // @[lsu.scala:211:7, :1485:70] reg [3:0] io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_br_type_0 = io_core_iresp_0_REG_bits_uop_br_type; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfb_0 = io_core_iresp_0_REG_bits_uop_is_sfb; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fence_0 = io_core_iresp_0_REG_bits_uop_is_fence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_fencei_0 = io_core_iresp_0_REG_bits_uop_is_fencei; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sfence_0 = io_core_iresp_0_REG_bits_uop_is_sfence; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_amo_0 = io_core_iresp_0_REG_bits_uop_is_amo; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_eret_0 = io_core_iresp_0_REG_bits_uop_is_eret; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_sys_pc2epc_0 = io_core_iresp_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_rocc_0 = io_core_iresp_0_REG_bits_uop_is_rocc; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_mov_0 = io_core_iresp_0_REG_bits_uop_is_mov; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ftq_idx_0 = io_core_iresp_0_REG_bits_uop_ftq_idx; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_edge_inst_0 = io_core_iresp_0_REG_bits_uop_edge_inst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pc_lob_0 = io_core_iresp_0_REG_bits_uop_pc_lob; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_taken_0 = io_core_iresp_0_REG_bits_uop_taken; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_rename_0 = io_core_iresp_0_REG_bits_uop_imm_rename; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_sel_0 = io_core_iresp_0_REG_bits_uop_imm_sel; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pimm_0 = io_core_iresp_0_REG_bits_uop_pimm; // @[lsu.scala:211:7, :1485:70] reg [19:0] io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_imm_packed_0 = io_core_iresp_0_REG_bits_uop_imm_packed; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op1_sel_0 = io_core_iresp_0_REG_bits_uop_op1_sel; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_op2_sel_0 = io_core_iresp_0_REG_bits_uop_op2_sel; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wen_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_toint_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_fma_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_div_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_ctrl_vec_0 = io_core_iresp_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rob_idx_0 = io_core_iresp_0_REG_bits_uop_rob_idx; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldq_idx_0 = io_core_iresp_0_REG_bits_uop_ldq_idx; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stq_idx_0 = io_core_iresp_0_REG_bits_uop_stq_idx; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_rxq_idx_0 = io_core_iresp_0_REG_bits_uop_rxq_idx; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_pdst_0 = io_core_iresp_0_REG_bits_uop_pdst; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_0 = io_core_iresp_0_REG_bits_uop_prs1; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_0 = io_core_iresp_0_REG_bits_uop_prs2; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_0 = io_core_iresp_0_REG_bits_uop_prs3; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_0 = io_core_iresp_0_REG_bits_uop_ppred; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs1_busy_0 = io_core_iresp_0_REG_bits_uop_prs1_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs2_busy_0 = io_core_iresp_0_REG_bits_uop_prs2_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_prs3_busy_0 = io_core_iresp_0_REG_bits_uop_prs3_busy; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ppred_busy_0 = io_core_iresp_0_REG_bits_uop_ppred_busy; // @[lsu.scala:211:7, :1485:70] reg [6:0] io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_stale_pdst_0 = io_core_iresp_0_REG_bits_uop_stale_pdst; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exception_0 = io_core_iresp_0_REG_bits_uop_exception; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_exc_cause_0 = io_core_iresp_0_REG_bits_uop_exc_cause; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_cmd_0 = io_core_iresp_0_REG_bits_uop_mem_cmd; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_size_0 = io_core_iresp_0_REG_bits_uop_mem_size; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_mem_signed_0 = io_core_iresp_0_REG_bits_uop_mem_signed; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_ldq_0 = io_core_iresp_0_REG_bits_uop_uses_ldq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_uses_stq_0 = io_core_iresp_0_REG_bits_uop_uses_stq; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_is_unique_0 = io_core_iresp_0_REG_bits_uop_is_unique; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_flush_on_commit_0 = io_core_iresp_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_csr_cmd_0 = io_core_iresp_0_REG_bits_uop_csr_cmd; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_is_rs1_0 = io_core_iresp_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_ldst_0 = io_core_iresp_0_REG_bits_uop_ldst; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_0 = io_core_iresp_0_REG_bits_uop_lrs1; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_0 = io_core_iresp_0_REG_bits_uop_lrs2; // @[lsu.scala:211:7, :1485:70] reg [5:0] io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs3_0 = io_core_iresp_0_REG_bits_uop_lrs3; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_dst_rtype_0 = io_core_iresp_0_REG_bits_uop_dst_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs1_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_lrs2_rtype_0 = io_core_iresp_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_frs3_en_0 = io_core_iresp_0_REG_bits_uop_frs3_en; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_dw_0 = io_core_iresp_0_REG_bits_uop_fcn_dw; // @[lsu.scala:211:7, :1485:70] reg [4:0] io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fcn_op_0 = io_core_iresp_0_REG_bits_uop_fcn_op; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_val_0 = io_core_iresp_0_REG_bits_uop_fp_val; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_rm_0 = io_core_iresp_0_REG_bits_uop_fp_rm; // @[lsu.scala:211:7, :1485:70] reg [1:0] io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_fp_typ_0 = io_core_iresp_0_REG_bits_uop_fp_typ; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_pf_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ae_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_xcpt_ma_if_0 = io_core_iresp_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_debug_if_0 = io_core_iresp_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:211:7, :1485:70] reg io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_bp_xcpt_if_0 = io_core_iresp_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_fsrc_0 = io_core_iresp_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:211:7, :1485:70] reg [2:0] io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_uop_debug_tsrc_0 = io_core_iresp_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:211:7, :1485:70] reg [63:0] io_core_iresp_0_REG_bits_data; // @[lsu.scala:1485:70] assign io_core_iresp_0_bits_data_0 = io_core_iresp_0_REG_bits_data; // @[lsu.scala:211:7, :1485:70] wire wb_spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1491:29] wire [31:0] wb_spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1491:29] wire [39:0] wb_spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1491:29] wire [15:0] wb_spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1491:29] wire [3:0] wb_spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1491:29] wire [19:0] wb_spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1491:29] wire [6:0] wb_spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1491:29] wire [63:0] wb_spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1491:29] wire [5:0] wb_spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1491:29] wire [4:0] wb_spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1491:29] wire [1:0] wb_spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1491:29] wire [2:0] wb_spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1491:29] wire wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29] wire spec_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_inst; // @[lsu.scala:1492:26] wire [31:0] spec_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1492:26] wire [39:0] spec_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1492:26] wire [15:0] spec_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1492:26] wire [3:0] spec_wakeups_0_bits_uop_br_type; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_taken; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_pimm; // @[lsu.scala:1492:26] wire [19:0] spec_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_pdst; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs1; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs2; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_prs3; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_ppred; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1492:26] wire [6:0] spec_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_exception; // @[lsu.scala:1492:26] wire [63:0] spec_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_ldst; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1492:26] wire [5:0] spec_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1492:26] wire [4:0] spec_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1492:26] wire [1:0] spec_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_bypassable; // @[lsu.scala:1492:26] wire [2:0] spec_wakeups_0_bits_speculative_mask; // @[lsu.scala:1492:26] wire spec_wakeups_0_bits_rebusy; // @[lsu.scala:1492:26] wire spec_wakeups_0_valid; // @[lsu.scala:1492:26] wire [31:0] slow_wakeups_0_out_bits_uop_inst = wb_slow_wakeups_0_bits_uop_inst; // @[util.scala:114:23] wire [31:0] slow_wakeups_0_out_bits_uop_debug_inst = wb_slow_wakeups_0_bits_uop_debug_inst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rvc = wb_slow_wakeups_0_bits_uop_is_rvc; // @[util.scala:114:23] wire [39:0] slow_wakeups_0_out_bits_uop_debug_pc = wb_slow_wakeups_0_bits_uop_debug_pc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_0 = wb_slow_wakeups_0_bits_uop_iq_type_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_1 = wb_slow_wakeups_0_bits_uop_iq_type_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_2 = wb_slow_wakeups_0_bits_uop_iq_type_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iq_type_3 = wb_slow_wakeups_0_bits_uop_iq_type_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_0 = wb_slow_wakeups_0_bits_uop_fu_code_0; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_1 = wb_slow_wakeups_0_bits_uop_fu_code_1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_2 = wb_slow_wakeups_0_bits_uop_fu_code_2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_3 = wb_slow_wakeups_0_bits_uop_fu_code_3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_4 = wb_slow_wakeups_0_bits_uop_fu_code_4; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_5 = wb_slow_wakeups_0_bits_uop_fu_code_5; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_6 = wb_slow_wakeups_0_bits_uop_fu_code_6; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_7 = wb_slow_wakeups_0_bits_uop_fu_code_7; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_8 = wb_slow_wakeups_0_bits_uop_fu_code_8; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fu_code_9 = wb_slow_wakeups_0_bits_uop_fu_code_9; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued = wb_slow_wakeups_0_bits_uop_iw_issued; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_agen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_issued_partial_dgen = wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_iw_p1_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_iw_p2_speculative_child = wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p1_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p2_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_iw_p3_bypass_hint = wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_dis_col_sel = wb_slow_wakeups_0_bits_uop_dis_col_sel; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_tag = wb_slow_wakeups_0_bits_uop_br_tag; // @[util.scala:114:23] wire [3:0] slow_wakeups_0_out_bits_uop_br_type = wb_slow_wakeups_0_bits_uop_br_type; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfb = wb_slow_wakeups_0_bits_uop_is_sfb; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fence = wb_slow_wakeups_0_bits_uop_is_fence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_fencei = wb_slow_wakeups_0_bits_uop_is_fencei; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sfence = wb_slow_wakeups_0_bits_uop_is_sfence; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_amo = wb_slow_wakeups_0_bits_uop_is_amo; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_eret = wb_slow_wakeups_0_bits_uop_is_eret; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_sys_pc2epc = wb_slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_rocc = wb_slow_wakeups_0_bits_uop_is_rocc; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_mov = wb_slow_wakeups_0_bits_uop_is_mov; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ftq_idx = wb_slow_wakeups_0_bits_uop_ftq_idx; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_edge_inst = wb_slow_wakeups_0_bits_uop_edge_inst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_pc_lob = wb_slow_wakeups_0_bits_uop_pc_lob; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_taken = wb_slow_wakeups_0_bits_uop_taken; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_imm_rename = wb_slow_wakeups_0_bits_uop_imm_rename; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_imm_sel = wb_slow_wakeups_0_bits_uop_imm_sel; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_pimm = wb_slow_wakeups_0_bits_uop_pimm; // @[util.scala:114:23] wire [19:0] slow_wakeups_0_out_bits_uop_imm_packed = wb_slow_wakeups_0_bits_uop_imm_packed; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_op1_sel = wb_slow_wakeups_0_bits_uop_op1_sel; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_op2_sel = wb_slow_wakeups_0_bits_uop_op2_sel; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ldst = wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wen = wb_slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren1 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren2 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_ren3 = wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap12 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_swap23 = wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagIn = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_ctrl_typeTagOut = wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fromint = wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_toint = wb_slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fastpipe = wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_fma = wb_slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_div = wb_slow_wakeups_0_bits_uop_fp_ctrl_div; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_sqrt = wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_wflags = wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_ctrl_vec = wb_slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_rob_idx = wb_slow_wakeups_0_bits_uop_rob_idx; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ldq_idx = wb_slow_wakeups_0_bits_uop_ldq_idx; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_stq_idx = wb_slow_wakeups_0_bits_uop_stq_idx; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_rxq_idx = wb_slow_wakeups_0_bits_uop_rxq_idx; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_pdst = wb_slow_wakeups_0_bits_uop_pdst; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs1 = wb_slow_wakeups_0_bits_uop_prs1; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs2 = wb_slow_wakeups_0_bits_uop_prs2; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_prs3 = wb_slow_wakeups_0_bits_uop_prs3; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_ppred = wb_slow_wakeups_0_bits_uop_ppred; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs1_busy = wb_slow_wakeups_0_bits_uop_prs1_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs2_busy = wb_slow_wakeups_0_bits_uop_prs2_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_prs3_busy = wb_slow_wakeups_0_bits_uop_prs3_busy; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ppred_busy = wb_slow_wakeups_0_bits_uop_ppred_busy; // @[util.scala:114:23] wire [6:0] slow_wakeups_0_out_bits_uop_stale_pdst = wb_slow_wakeups_0_bits_uop_stale_pdst; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_exception = wb_slow_wakeups_0_bits_uop_exception; // @[util.scala:114:23] wire [63:0] slow_wakeups_0_out_bits_uop_exc_cause = wb_slow_wakeups_0_bits_uop_exc_cause; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_mem_cmd = wb_slow_wakeups_0_bits_uop_mem_cmd; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_mem_size = wb_slow_wakeups_0_bits_uop_mem_size; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_mem_signed = wb_slow_wakeups_0_bits_uop_mem_signed; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_ldq = wb_slow_wakeups_0_bits_uop_uses_ldq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_uses_stq = wb_slow_wakeups_0_bits_uop_uses_stq; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_is_unique = wb_slow_wakeups_0_bits_uop_is_unique; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_flush_on_commit = wb_slow_wakeups_0_bits_uop_flush_on_commit; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_csr_cmd = wb_slow_wakeups_0_bits_uop_csr_cmd; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_ldst_is_rs1 = wb_slow_wakeups_0_bits_uop_ldst_is_rs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_ldst = wb_slow_wakeups_0_bits_uop_ldst; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs1 = wb_slow_wakeups_0_bits_uop_lrs1; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs2 = wb_slow_wakeups_0_bits_uop_lrs2; // @[util.scala:114:23] wire [5:0] slow_wakeups_0_out_bits_uop_lrs3 = wb_slow_wakeups_0_bits_uop_lrs3; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_dst_rtype = wb_slow_wakeups_0_bits_uop_dst_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs1_rtype = wb_slow_wakeups_0_bits_uop_lrs1_rtype; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_lrs2_rtype = wb_slow_wakeups_0_bits_uop_lrs2_rtype; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_frs3_en = wb_slow_wakeups_0_bits_uop_frs3_en; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fcn_dw = wb_slow_wakeups_0_bits_uop_fcn_dw; // @[util.scala:114:23] wire [4:0] slow_wakeups_0_out_bits_uop_fcn_op = wb_slow_wakeups_0_bits_uop_fcn_op; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_fp_val = wb_slow_wakeups_0_bits_uop_fp_val; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_fp_rm = wb_slow_wakeups_0_bits_uop_fp_rm; // @[util.scala:114:23] wire [1:0] slow_wakeups_0_out_bits_uop_fp_typ = wb_slow_wakeups_0_bits_uop_fp_typ; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_pf_if = wb_slow_wakeups_0_bits_uop_xcpt_pf_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ae_if = wb_slow_wakeups_0_bits_uop_xcpt_ae_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_xcpt_ma_if = wb_slow_wakeups_0_bits_uop_xcpt_ma_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_debug_if = wb_slow_wakeups_0_bits_uop_bp_debug_if; // @[util.scala:114:23] wire slow_wakeups_0_out_bits_uop_bp_xcpt_if = wb_slow_wakeups_0_bits_uop_bp_xcpt_if; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_fsrc = wb_slow_wakeups_0_bits_uop_debug_fsrc; // @[util.scala:114:23] wire [2:0] slow_wakeups_0_out_bits_uop_debug_tsrc = wb_slow_wakeups_0_bits_uop_debug_tsrc; // @[util.scala:114:23] wire [15:0] wb_slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1494:29] wire wb_slow_wakeups_0_valid; // @[lsu.scala:1494:29] wire slow_wakeups_0_bits_uop_iq_type_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iq_type_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_0; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_4; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_5; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_6; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_7; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_8; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fu_code_9; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_inst; // @[lsu.scala:1495:26] wire [31:0] slow_wakeups_0_bits_uop_debug_inst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rvc; // @[lsu.scala:1495:26] wire [39:0] slow_wakeups_0_bits_uop_debug_pc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_dis_col_sel; // @[lsu.scala:1495:26] wire [15:0] slow_wakeups_0_bits_uop_br_mask; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_tag; // @[lsu.scala:1495:26] wire [3:0] slow_wakeups_0_bits_uop_br_type; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfb; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_fencei; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sfence; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_amo; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_eret; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_rocc; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_mov; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ftq_idx; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_edge_inst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_pc_lob; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_taken; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_imm_rename; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_imm_sel; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_pimm; // @[lsu.scala:1495:26] wire [19:0] slow_wakeups_0_bits_uop_imm_packed; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_op1_sel; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_op2_sel; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_rob_idx; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ldq_idx; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_stq_idx; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_rxq_idx; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_pdst; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs1; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs2; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_prs3; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_ppred; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs1_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs2_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_prs3_busy; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ppred_busy; // @[lsu.scala:1495:26] wire [6:0] slow_wakeups_0_bits_uop_stale_pdst; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_exception; // @[lsu.scala:1495:26] wire [63:0] slow_wakeups_0_bits_uop_exc_cause; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_mem_cmd; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_mem_size; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_mem_signed; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_ldq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_uses_stq; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_is_unique; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_flush_on_commit; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_csr_cmd; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_ldst; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs1; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs2; // @[lsu.scala:1495:26] wire [5:0] slow_wakeups_0_bits_uop_lrs3; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_dst_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_frs3_en; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fcn_dw; // @[lsu.scala:1495:26] wire [4:0] slow_wakeups_0_bits_uop_fcn_op; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_fp_val; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_fp_rm; // @[lsu.scala:1495:26] wire [1:0] slow_wakeups_0_bits_uop_fp_typ; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_debug_if; // @[lsu.scala:1495:26] wire slow_wakeups_0_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_fsrc; // @[lsu.scala:1495:26] wire [2:0] slow_wakeups_0_bits_uop_debug_tsrc; // @[lsu.scala:1495:26] wire dmem_resp_fired_0; // @[lsu.scala:1497:33] reg w1_valid; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_valid = w1_valid; // @[lsu.scala:1491:29, :1499:17] reg [31:0] w1_bits_uop_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_inst = w1_bits_uop_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_inst = w1_bits_uop_inst; // @[util.scala:109:23] reg [31:0] w1_bits_uop_debug_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_inst = w1_bits_uop_debug_inst; // @[lsu.scala:1491:29, :1499:17] wire [31:0] w2_bits_out_uop_debug_inst = w1_bits_uop_debug_inst; // @[util.scala:109:23] reg w1_bits_uop_is_rvc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rvc = w1_bits_uop_is_rvc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rvc = w1_bits_uop_is_rvc; // @[util.scala:109:23] reg [39:0] w1_bits_uop_debug_pc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_pc = w1_bits_uop_debug_pc; // @[lsu.scala:1491:29, :1499:17] wire [39:0] w2_bits_out_uop_debug_pc = w1_bits_uop_debug_pc; // @[util.scala:109:23] reg w1_bits_uop_iq_type_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_0 = w1_bits_uop_iq_type_0; // @[util.scala:109:23] reg w1_bits_uop_iq_type_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_1 = w1_bits_uop_iq_type_1; // @[util.scala:109:23] reg w1_bits_uop_iq_type_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_2 = w1_bits_uop_iq_type_2; // @[util.scala:109:23] reg w1_bits_uop_iq_type_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iq_type_3 = w1_bits_uop_iq_type_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_0; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_0 = w1_bits_uop_fu_code_0; // @[util.scala:109:23] reg w1_bits_uop_fu_code_1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_1 = w1_bits_uop_fu_code_1; // @[util.scala:109:23] reg w1_bits_uop_fu_code_2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_2 = w1_bits_uop_fu_code_2; // @[util.scala:109:23] reg w1_bits_uop_fu_code_3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_3 = w1_bits_uop_fu_code_3; // @[util.scala:109:23] reg w1_bits_uop_fu_code_4; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_4 = w1_bits_uop_fu_code_4; // @[util.scala:109:23] reg w1_bits_uop_fu_code_5; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_5 = w1_bits_uop_fu_code_5; // @[util.scala:109:23] reg w1_bits_uop_fu_code_6; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_6 = w1_bits_uop_fu_code_6; // @[util.scala:109:23] reg w1_bits_uop_fu_code_7; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_7 = w1_bits_uop_fu_code_7; // @[util.scala:109:23] reg w1_bits_uop_fu_code_8; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_8 = w1_bits_uop_fu_code_8; // @[util.scala:109:23] reg w1_bits_uop_fu_code_9; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fu_code_9 = w1_bits_uop_fu_code_9; // @[util.scala:109:23] reg w1_bits_uop_iw_issued; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued = w1_bits_uop_iw_issued; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued = w1_bits_uop_iw_issued; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_agen = w1_bits_uop_iw_issued_partial_agen; // @[util.scala:109:23] reg w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_issued_partial_dgen = w1_bits_uop_iw_issued_partial_dgen; // @[util.scala:109:23] reg [2:0] w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_iw_p1_speculative_child = w1_bits_uop_iw_p1_speculative_child; // @[util.scala:109:23] reg [2:0] w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_iw_p2_speculative_child = w1_bits_uop_iw_p2_speculative_child; // @[util.scala:109:23] reg w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p1_bypass_hint = w1_bits_uop_iw_p1_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p2_bypass_hint = w1_bits_uop_iw_p2_bypass_hint; // @[util.scala:109:23] reg w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_iw_p3_bypass_hint = w1_bits_uop_iw_p3_bypass_hint; // @[util.scala:109:23] reg [2:0] w1_bits_uop_dis_col_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_dis_col_sel = w1_bits_uop_dis_col_sel; // @[util.scala:109:23] reg [15:0] w1_bits_uop_br_mask; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_mask = w1_bits_uop_br_mask; // @[lsu.scala:1491:29, :1499:17] reg [3:0] w1_bits_uop_br_tag; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_tag = w1_bits_uop_br_tag; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_tag = w1_bits_uop_br_tag; // @[util.scala:109:23] reg [3:0] w1_bits_uop_br_type; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_br_type = w1_bits_uop_br_type; // @[lsu.scala:1491:29, :1499:17] wire [3:0] w2_bits_out_uop_br_type = w1_bits_uop_br_type; // @[util.scala:109:23] reg w1_bits_uop_is_sfb; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfb = w1_bits_uop_is_sfb; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfb = w1_bits_uop_is_sfb; // @[util.scala:109:23] reg w1_bits_uop_is_fence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fence = w1_bits_uop_is_fence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fence = w1_bits_uop_is_fence; // @[util.scala:109:23] reg w1_bits_uop_is_fencei; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_fencei = w1_bits_uop_is_fencei; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_fencei = w1_bits_uop_is_fencei; // @[util.scala:109:23] reg w1_bits_uop_is_sfence; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sfence = w1_bits_uop_is_sfence; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sfence = w1_bits_uop_is_sfence; // @[util.scala:109:23] reg w1_bits_uop_is_amo; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_amo = w1_bits_uop_is_amo; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_amo = w1_bits_uop_is_amo; // @[util.scala:109:23] reg w1_bits_uop_is_eret; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_eret = w1_bits_uop_is_eret; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_eret = w1_bits_uop_is_eret; // @[util.scala:109:23] reg w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_sys_pc2epc = w1_bits_uop_is_sys_pc2epc; // @[util.scala:109:23] reg w1_bits_uop_is_rocc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_rocc = w1_bits_uop_is_rocc; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_rocc = w1_bits_uop_is_rocc; // @[util.scala:109:23] reg w1_bits_uop_is_mov; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_mov = w1_bits_uop_is_mov; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_mov = w1_bits_uop_is_mov; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ftq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ftq_idx = w1_bits_uop_ftq_idx; // @[util.scala:109:23] reg w1_bits_uop_edge_inst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_edge_inst = w1_bits_uop_edge_inst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_edge_inst = w1_bits_uop_edge_inst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_pc_lob; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pc_lob = w1_bits_uop_pc_lob; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_pc_lob = w1_bits_uop_pc_lob; // @[util.scala:109:23] reg w1_bits_uop_taken; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_taken = w1_bits_uop_taken; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_taken = w1_bits_uop_taken; // @[util.scala:109:23] reg w1_bits_uop_imm_rename; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_rename = w1_bits_uop_imm_rename; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_imm_rename = w1_bits_uop_imm_rename; // @[util.scala:109:23] reg [2:0] w1_bits_uop_imm_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_sel = w1_bits_uop_imm_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_imm_sel = w1_bits_uop_imm_sel; // @[util.scala:109:23] reg [4:0] w1_bits_uop_pimm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pimm = w1_bits_uop_pimm; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_pimm = w1_bits_uop_pimm; // @[util.scala:109:23] reg [19:0] w1_bits_uop_imm_packed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_imm_packed = w1_bits_uop_imm_packed; // @[lsu.scala:1491:29, :1499:17] wire [19:0] w2_bits_out_uop_imm_packed = w1_bits_uop_imm_packed; // @[util.scala:109:23] reg [1:0] w1_bits_uop_op1_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op1_sel = w1_bits_uop_op1_sel; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_op1_sel = w1_bits_uop_op1_sel; // @[util.scala:109:23] reg [2:0] w1_bits_uop_op2_sel; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_op2_sel = w1_bits_uop_op2_sel; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_op2_sel = w1_bits_uop_op2_sel; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ldst = w1_bits_uop_fp_ctrl_ldst; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wen = w1_bits_uop_fp_ctrl_wen; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren1 = w1_bits_uop_fp_ctrl_ren1; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren2 = w1_bits_uop_fp_ctrl_ren2; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_ren3 = w1_bits_uop_fp_ctrl_ren3; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap12 = w1_bits_uop_fp_ctrl_swap12; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_swap23 = w1_bits_uop_fp_ctrl_swap23; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagIn = w1_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_ctrl_typeTagOut = w1_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fromint = w1_bits_uop_fp_ctrl_fromint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_toint = w1_bits_uop_fp_ctrl_toint; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fastpipe = w1_bits_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_fma = w1_bits_uop_fp_ctrl_fma; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_div = w1_bits_uop_fp_ctrl_div; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_sqrt = w1_bits_uop_fp_ctrl_sqrt; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_wflags = w1_bits_uop_fp_ctrl_wflags; // @[util.scala:109:23] reg w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_ctrl_vec = w1_bits_uop_fp_ctrl_vec; // @[util.scala:109:23] reg [6:0] w1_bits_uop_rob_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rob_idx = w1_bits_uop_rob_idx; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_rob_idx = w1_bits_uop_rob_idx; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ldq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ldq_idx = w1_bits_uop_ldq_idx; // @[util.scala:109:23] reg [4:0] w1_bits_uop_stq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stq_idx = w1_bits_uop_stq_idx; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_stq_idx = w1_bits_uop_stq_idx; // @[util.scala:109:23] reg [1:0] w1_bits_uop_rxq_idx; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_rxq_idx = w1_bits_uop_rxq_idx; // @[util.scala:109:23] reg [6:0] w1_bits_uop_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_pdst = w1_bits_uop_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_pdst = w1_bits_uop_pdst; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1 = w1_bits_uop_prs1; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs1 = w1_bits_uop_prs1; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2 = w1_bits_uop_prs2; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs2 = w1_bits_uop_prs2; // @[util.scala:109:23] reg [6:0] w1_bits_uop_prs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3 = w1_bits_uop_prs3; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_prs3 = w1_bits_uop_prs3; // @[util.scala:109:23] reg [4:0] w1_bits_uop_ppred; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred = w1_bits_uop_ppred; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_ppred = w1_bits_uop_ppred; // @[util.scala:109:23] reg w1_bits_uop_prs1_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs1_busy = w1_bits_uop_prs1_busy; // @[util.scala:109:23] reg w1_bits_uop_prs2_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs2_busy = w1_bits_uop_prs2_busy; // @[util.scala:109:23] reg w1_bits_uop_prs3_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_prs3_busy = w1_bits_uop_prs3_busy; // @[util.scala:109:23] reg w1_bits_uop_ppred_busy; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ppred_busy = w1_bits_uop_ppred_busy; // @[util.scala:109:23] reg [6:0] w1_bits_uop_stale_pdst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[lsu.scala:1491:29, :1499:17] wire [6:0] w2_bits_out_uop_stale_pdst = w1_bits_uop_stale_pdst; // @[util.scala:109:23] reg w1_bits_uop_exception; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exception = w1_bits_uop_exception; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_exception = w1_bits_uop_exception; // @[util.scala:109:23] reg [63:0] w1_bits_uop_exc_cause; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_exc_cause = w1_bits_uop_exc_cause; // @[lsu.scala:1491:29, :1499:17] wire [63:0] w2_bits_out_uop_exc_cause = w1_bits_uop_exc_cause; // @[util.scala:109:23] reg [4:0] w1_bits_uop_mem_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_mem_cmd = w1_bits_uop_mem_cmd; // @[util.scala:109:23] reg [1:0] w1_bits_uop_mem_size; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_size = w1_bits_uop_mem_size; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_mem_size = w1_bits_uop_mem_size; // @[util.scala:109:23] reg w1_bits_uop_mem_signed; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_mem_signed = w1_bits_uop_mem_signed; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_mem_signed = w1_bits_uop_mem_signed; // @[util.scala:109:23] reg w1_bits_uop_uses_ldq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_ldq = w1_bits_uop_uses_ldq; // @[util.scala:109:23] reg w1_bits_uop_uses_stq; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_uses_stq = w1_bits_uop_uses_stq; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_uses_stq = w1_bits_uop_uses_stq; // @[util.scala:109:23] reg w1_bits_uop_is_unique; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_is_unique = w1_bits_uop_is_unique; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_is_unique = w1_bits_uop_is_unique; // @[util.scala:109:23] reg w1_bits_uop_flush_on_commit; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_flush_on_commit = w1_bits_uop_flush_on_commit; // @[util.scala:109:23] reg [2:0] w1_bits_uop_csr_cmd; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_csr_cmd = w1_bits_uop_csr_cmd; // @[util.scala:109:23] reg w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_ldst_is_rs1 = w1_bits_uop_ldst_is_rs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_ldst; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_ldst = w1_bits_uop_ldst; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_ldst = w1_bits_uop_ldst; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs1; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1 = w1_bits_uop_lrs1; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs1 = w1_bits_uop_lrs1; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs2; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2 = w1_bits_uop_lrs2; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs2 = w1_bits_uop_lrs2; // @[util.scala:109:23] reg [5:0] w1_bits_uop_lrs3; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs3 = w1_bits_uop_lrs3; // @[lsu.scala:1491:29, :1499:17] wire [5:0] w2_bits_out_uop_lrs3 = w1_bits_uop_lrs3; // @[util.scala:109:23] reg [1:0] w1_bits_uop_dst_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_dst_rtype = w1_bits_uop_dst_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs1_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs1_rtype = w1_bits_uop_lrs1_rtype; // @[util.scala:109:23] reg [1:0] w1_bits_uop_lrs2_rtype; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_lrs2_rtype = w1_bits_uop_lrs2_rtype; // @[util.scala:109:23] reg w1_bits_uop_frs3_en; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_frs3_en = w1_bits_uop_frs3_en; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_frs3_en = w1_bits_uop_frs3_en; // @[util.scala:109:23] reg w1_bits_uop_fcn_dw; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fcn_dw = w1_bits_uop_fcn_dw; // @[util.scala:109:23] reg [4:0] w1_bits_uop_fcn_op; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fcn_op = w1_bits_uop_fcn_op; // @[lsu.scala:1491:29, :1499:17] wire [4:0] w2_bits_out_uop_fcn_op = w1_bits_uop_fcn_op; // @[util.scala:109:23] reg w1_bits_uop_fp_val; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_val = w1_bits_uop_fp_val; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_fp_val = w1_bits_uop_fp_val; // @[util.scala:109:23] reg [2:0] w1_bits_uop_fp_rm; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_rm = w1_bits_uop_fp_rm; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_fp_rm = w1_bits_uop_fp_rm; // @[util.scala:109:23] reg [1:0] w1_bits_uop_fp_typ; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_fp_typ = w1_bits_uop_fp_typ; // @[lsu.scala:1491:29, :1499:17] wire [1:0] w2_bits_out_uop_fp_typ = w1_bits_uop_fp_typ; // @[util.scala:109:23] reg w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_pf_if = w1_bits_uop_xcpt_pf_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ae_if = w1_bits_uop_xcpt_ae_if; // @[util.scala:109:23] reg w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_xcpt_ma_if = w1_bits_uop_xcpt_ma_if; // @[util.scala:109:23] reg w1_bits_uop_bp_debug_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_debug_if = w1_bits_uop_bp_debug_if; // @[util.scala:109:23] reg w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[lsu.scala:1491:29, :1499:17] wire w2_bits_out_uop_bp_xcpt_if = w1_bits_uop_bp_xcpt_if; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_fsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_fsrc = w1_bits_uop_debug_fsrc; // @[util.scala:109:23] reg [2:0] w1_bits_uop_debug_tsrc; // @[lsu.scala:1499:17] assign wb_spec_wakeups_0_bits_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[lsu.scala:1491:29, :1499:17] wire [2:0] w2_bits_out_uop_debug_tsrc = w1_bits_uop_debug_tsrc; // @[util.scala:109:23] wire _w1_valid_T = _wakeupArbs_0_io_in_1_ready & _wakeupArbs_0_io_in_1_valid_T_4; // @[Decoupled.scala:51:35] wire [15:0] _w1_valid_T_1 = io_core_brupdate_b1_mispredict_mask_0 & mem_incoming_uop_0_br_mask; // @[util.scala:126:51] wire _w1_valid_T_2 = |_w1_valid_T_1; // @[util.scala:126:{51,59}] wire _w1_valid_T_3 = _w1_valid_T_2 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w1_valid_T_4 = ~_w1_valid_T_3; // @[util.scala:61:61] wire _w1_valid_T_5 = _w1_valid_T & _w1_valid_T_4; // @[Decoupled.scala:51:35] wire [15:0] _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] w1_bits_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _w1_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w1_bits_out_uop_br_mask_T_1 = mem_incoming_uop_0_br_mask & _w1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w1_bits_out_uop_br_mask = _w1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] reg w2_valid; // @[lsu.scala:1503:17] assign spec_wakeups_0_valid = w2_valid; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_inst = w2_bits_uop_inst; // @[lsu.scala:1492:26, :1503:17] reg [31:0] w2_bits_uop_debug_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_inst = w2_bits_uop_debug_inst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rvc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rvc = w2_bits_uop_is_rvc; // @[lsu.scala:1492:26, :1503:17] reg [39:0] w2_bits_uop_debug_pc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_pc = w2_bits_uop_debug_pc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_0 = w2_bits_uop_iq_type_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_1 = w2_bits_uop_iq_type_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_2 = w2_bits_uop_iq_type_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iq_type_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iq_type_3 = w2_bits_uop_iq_type_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_0; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_0 = w2_bits_uop_fu_code_0; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_1 = w2_bits_uop_fu_code_1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_2 = w2_bits_uop_fu_code_2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_3 = w2_bits_uop_fu_code_3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_4; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_4 = w2_bits_uop_fu_code_4; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_5; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_5 = w2_bits_uop_fu_code_5; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_6; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_6 = w2_bits_uop_fu_code_6; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_7; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_7 = w2_bits_uop_fu_code_7; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_8; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_8 = w2_bits_uop_fu_code_8; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fu_code_9; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fu_code_9 = w2_bits_uop_fu_code_9; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued = w2_bits_uop_iw_issued; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_agen = w2_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_issued_partial_dgen = w2_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_speculative_child = w2_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_speculative_child = w2_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p1_bypass_hint = w2_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p2_bypass_hint = w2_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_iw_p3_bypass_hint = w2_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_dis_col_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dis_col_sel = w2_bits_uop_dis_col_sel; // @[lsu.scala:1492:26, :1503:17] reg [15:0] w2_bits_uop_br_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_mask = w2_bits_uop_br_mask; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_tag; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_tag = w2_bits_uop_br_tag; // @[lsu.scala:1492:26, :1503:17] reg [3:0] w2_bits_uop_br_type; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_br_type = w2_bits_uop_br_type; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfb; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfb = w2_bits_uop_is_sfb; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fence = w2_bits_uop_is_fence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_fencei; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_fencei = w2_bits_uop_is_fencei; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sfence; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sfence = w2_bits_uop_is_sfence; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_amo; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_amo = w2_bits_uop_is_amo; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_eret; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_eret = w2_bits_uop_is_eret; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_sys_pc2epc = w2_bits_uop_is_sys_pc2epc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_rocc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_rocc = w2_bits_uop_is_rocc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_mov; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_mov = w2_bits_uop_is_mov; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ftq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ftq_idx = w2_bits_uop_ftq_idx; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_edge_inst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_edge_inst = w2_bits_uop_edge_inst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_pc_lob; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pc_lob = w2_bits_uop_pc_lob; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_taken; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_taken = w2_bits_uop_taken; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_imm_rename; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_rename = w2_bits_uop_imm_rename; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_imm_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_sel = w2_bits_uop_imm_sel; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_pimm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pimm = w2_bits_uop_pimm; // @[lsu.scala:1492:26, :1503:17] reg [19:0] w2_bits_uop_imm_packed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_imm_packed = w2_bits_uop_imm_packed; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_op1_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op1_sel = w2_bits_uop_op1_sel; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_op2_sel; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_op2_sel = w2_bits_uop_op2_sel; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ldst = w2_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wen = w2_bits_uop_fp_ctrl_wen; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren1 = w2_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren2 = w2_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_ren3 = w2_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap12 = w2_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_swap23 = w2_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagIn = w2_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_typeTagOut = w2_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fromint = w2_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_toint = w2_bits_uop_fp_ctrl_toint; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fastpipe = w2_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_fma = w2_bits_uop_fp_ctrl_fma; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_div = w2_bits_uop_fp_ctrl_div; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_sqrt = w2_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_wflags = w2_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_ctrl_vec = w2_bits_uop_fp_ctrl_vec; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_rob_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rob_idx = w2_bits_uop_rob_idx; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ldq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldq_idx = w2_bits_uop_ldq_idx; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_stq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stq_idx = w2_bits_uop_stq_idx; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_rxq_idx; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_rxq_idx = w2_bits_uop_rxq_idx; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_pdst = w2_bits_uop_pdst; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1 = w2_bits_uop_prs1; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2 = w2_bits_uop_prs2; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_prs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3 = w2_bits_uop_prs3; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_ppred; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred = w2_bits_uop_ppred; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs1_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs1_busy = w2_bits_uop_prs1_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs2_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs2_busy = w2_bits_uop_prs2_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_prs3_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_prs3_busy = w2_bits_uop_prs3_busy; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ppred_busy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ppred_busy = w2_bits_uop_ppred_busy; // @[lsu.scala:1492:26, :1503:17] reg [6:0] w2_bits_uop_stale_pdst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_stale_pdst = w2_bits_uop_stale_pdst; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_exception; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exception = w2_bits_uop_exception; // @[lsu.scala:1492:26, :1503:17] reg [63:0] w2_bits_uop_exc_cause; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_exc_cause = w2_bits_uop_exc_cause; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_mem_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_cmd = w2_bits_uop_mem_cmd; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_mem_size; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_size = w2_bits_uop_mem_size; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_mem_signed; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_mem_signed = w2_bits_uop_mem_signed; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_ldq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_ldq = w2_bits_uop_uses_ldq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_uses_stq; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_uses_stq = w2_bits_uop_uses_stq; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_is_unique; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_is_unique = w2_bits_uop_is_unique; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_flush_on_commit; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_flush_on_commit = w2_bits_uop_flush_on_commit; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_csr_cmd; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_csr_cmd = w2_bits_uop_csr_cmd; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst_is_rs1 = w2_bits_uop_ldst_is_rs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_ldst; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_ldst = w2_bits_uop_ldst; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs1; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1 = w2_bits_uop_lrs1; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs2; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2 = w2_bits_uop_lrs2; // @[lsu.scala:1492:26, :1503:17] reg [5:0] w2_bits_uop_lrs3; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs3 = w2_bits_uop_lrs3; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_dst_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_dst_rtype = w2_bits_uop_dst_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs1_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs1_rtype = w2_bits_uop_lrs1_rtype; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_lrs2_rtype; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_lrs2_rtype = w2_bits_uop_lrs2_rtype; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_frs3_en; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_frs3_en = w2_bits_uop_frs3_en; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fcn_dw; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_dw = w2_bits_uop_fcn_dw; // @[lsu.scala:1492:26, :1503:17] reg [4:0] w2_bits_uop_fcn_op; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fcn_op = w2_bits_uop_fcn_op; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_fp_val; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_val = w2_bits_uop_fp_val; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_fp_rm; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_rm = w2_bits_uop_fp_rm; // @[lsu.scala:1492:26, :1503:17] reg [1:0] w2_bits_uop_fp_typ; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_fp_typ = w2_bits_uop_fp_typ; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_pf_if = w2_bits_uop_xcpt_pf_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ae_if = w2_bits_uop_xcpt_ae_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_xcpt_ma_if = w2_bits_uop_xcpt_ma_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_debug_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_debug_if = w2_bits_uop_bp_debug_if; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_bp_xcpt_if = w2_bits_uop_bp_xcpt_if; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_fsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_fsrc = w2_bits_uop_debug_fsrc; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_uop_debug_tsrc; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_uop_debug_tsrc = w2_bits_uop_debug_tsrc; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_bypassable; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_bypassable = w2_bits_bypassable; // @[lsu.scala:1492:26, :1503:17] reg [2:0] w2_bits_speculative_mask; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_speculative_mask = w2_bits_speculative_mask; // @[lsu.scala:1492:26, :1503:17] reg w2_bits_rebusy; // @[lsu.scala:1503:17] assign spec_wakeups_0_bits_rebusy = w2_bits_rebusy; // @[lsu.scala:1492:26, :1503:17] wire [15:0] _w2_valid_T = io_core_brupdate_b1_mispredict_mask_0 & w1_bits_uop_br_mask; // @[util.scala:126:51] wire _w2_valid_T_1 = |_w2_valid_T; // @[util.scala:126:{51,59}] wire _w2_valid_T_2 = _w2_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _w2_valid_T_3 = ~_w2_valid_T_2; // @[util.scala:61:61] wire _w2_valid_T_4 = w1_valid & _w2_valid_T_3; // @[lsu.scala:1499:17, :1504:{26,29}] wire [15:0] _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] w2_bits_out_uop_br_mask; // @[util.scala:109:23] wire [15:0] _w2_bits_out_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _w2_bits_out_uop_br_mask_T_1 = w1_bits_uop_br_mask & _w2_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign w2_bits_out_uop_br_mask = _w2_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _GEN_650 = io_dmem_nack_0_valid_0 & ~io_dmem_nack_0_bits_is_hella_0; // @[lsu.scala:211:7, :1520:44] wire _GEN_651 = _GEN_650 & io_dmem_nack_0_bits_uop_uses_ldq_0 & ~reset; // @[lsu.scala:211:7, :1520:44, :1522:55, :1523:15] wire _T_1659 = io_dmem_nack_0_bits_uop_stq_idx_0 < stq_execute_head ^ io_dmem_nack_0_bits_uop_stq_idx_0 < stq_head ^ stq_execute_head < stq_head; // @[util.scala:364:{52,58,64,72,78}] wire _GEN_652 = io_dmem_nack_0_bits_is_hella_0 | io_dmem_nack_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :895:40, :1520:44, :1522:55, :1527:86] assign stq_execute_queue_flush = io_dmem_nack_0_valid_0 & ~_GEN_652 & _T_1659 | ~_GEN_473 & _T_1639 & ~dmem_req_fire_0; // @[util.scala:364:{58,72}] wire _resp_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20] wire _resp_T_1 = _resp_T; // @[lsu.scala:1534:{20,43}] wire [31:0] resp_uop_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_inst_0 : io_dmem_resp_0_bits_uop_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [31:0] resp_uop_debug_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_inst_0 : io_dmem_resp_0_bits_uop_debug_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rvc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rvc_0 : io_dmem_resp_0_bits_uop_is_rvc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [39:0] resp_uop_debug_pc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_pc_0 : io_dmem_resp_0_bits_uop_debug_pc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_0_0 : io_dmem_resp_0_bits_uop_iq_type_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_1_0 : io_dmem_resp_0_bits_uop_iq_type_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_2_0 : io_dmem_resp_0_bits_uop_iq_type_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iq_type_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iq_type_3_0 : io_dmem_resp_0_bits_uop_iq_type_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_0 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_0_0 : io_dmem_resp_0_bits_uop_fu_code_0_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_1_0 : io_dmem_resp_0_bits_uop_fu_code_1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_2_0 : io_dmem_resp_0_bits_uop_fu_code_2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_3_0 : io_dmem_resp_0_bits_uop_fu_code_3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_4 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_4_0 : io_dmem_resp_0_bits_uop_fu_code_4_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_5 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_5_0 : io_dmem_resp_0_bits_uop_fu_code_5_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_6 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_6_0 : io_dmem_resp_0_bits_uop_fu_code_6_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_7 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_7_0 : io_dmem_resp_0_bits_uop_fu_code_7_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_8 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_8_0 : io_dmem_resp_0_bits_uop_fu_code_8_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fu_code_9 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fu_code_9_0 : io_dmem_resp_0_bits_uop_fu_code_9_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_0 : io_dmem_resp_0_bits_uop_iw_issued_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_agen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_agen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_agen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_issued_partial_dgen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_issued_partial_dgen_0 : io_dmem_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_iw_p1_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p1_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_iw_p2_speculative_child = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_speculative_child_0 : io_dmem_resp_0_bits_uop_iw_p2_speculative_child_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p1_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p1_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p2_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p2_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_iw_p3_bypass_hint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_iw_p3_bypass_hint_0 : io_dmem_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_dis_col_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dis_col_sel_0 : io_dmem_resp_0_bits_uop_dis_col_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [15:0] resp_uop_br_mask = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_mask_0 : io_dmem_resp_0_bits_uop_br_mask_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_tag = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_tag_0 : io_dmem_resp_0_bits_uop_br_tag_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [3:0] resp_uop_br_type = _resp_T_1 ? io_dmem_ll_resp_bits_uop_br_type_0 : io_dmem_resp_0_bits_uop_br_type_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfb = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfb_0 : io_dmem_resp_0_bits_uop_is_sfb_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fence_0 : io_dmem_resp_0_bits_uop_is_fence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_fencei = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_fencei_0 : io_dmem_resp_0_bits_uop_is_fencei_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sfence = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sfence_0 : io_dmem_resp_0_bits_uop_is_sfence_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_amo = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_amo_0 : io_dmem_resp_0_bits_uop_is_amo_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_eret = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_eret_0 : io_dmem_resp_0_bits_uop_is_eret_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_sys_pc2epc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_sys_pc2epc_0 : io_dmem_resp_0_bits_uop_is_sys_pc2epc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_rocc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_rocc_0 : io_dmem_resp_0_bits_uop_is_rocc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_mov = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_mov_0 : io_dmem_resp_0_bits_uop_is_mov_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ftq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ftq_idx_0 : io_dmem_resp_0_bits_uop_ftq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_edge_inst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_edge_inst_0 : io_dmem_resp_0_bits_uop_edge_inst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_pc_lob = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pc_lob_0 : io_dmem_resp_0_bits_uop_pc_lob_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_taken = _resp_T_1 ? io_dmem_ll_resp_bits_uop_taken_0 : io_dmem_resp_0_bits_uop_taken_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_imm_rename = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_rename_0 : io_dmem_resp_0_bits_uop_imm_rename_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_imm_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_sel_0 : io_dmem_resp_0_bits_uop_imm_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_pimm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pimm_0 : io_dmem_resp_0_bits_uop_pimm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [19:0] resp_uop_imm_packed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_imm_packed_0 : io_dmem_resp_0_bits_uop_imm_packed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_op1_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op1_sel_0 : io_dmem_resp_0_bits_uop_op1_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_op2_sel = _resp_T_1 ? io_dmem_ll_resp_bits_uop_op2_sel_0 : io_dmem_resp_0_bits_uop_op2_sel_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ldst_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wen = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wen_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wen_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren1_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren2_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_ren3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_ren3_0 : io_dmem_resp_0_bits_uop_fp_ctrl_ren3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap12 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap12_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap12_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_swap23 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_swap23_0 : io_dmem_resp_0_bits_uop_fp_ctrl_swap23_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagIn = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagIn_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_ctrl_typeTagOut = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_typeTagOut_0 : io_dmem_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fromint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fromint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fromint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_toint = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_toint_0 : io_dmem_resp_0_bits_uop_fp_ctrl_toint_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fastpipe = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fastpipe_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_fma = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_fma_0 : io_dmem_resp_0_bits_uop_fp_ctrl_fma_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_div = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_div_0 : io_dmem_resp_0_bits_uop_fp_ctrl_div_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_sqrt = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_sqrt_0 : io_dmem_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_wflags = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_wflags_0 : io_dmem_resp_0_bits_uop_fp_ctrl_wflags_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_ctrl_vec = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_ctrl_vec_0 : io_dmem_resp_0_bits_uop_fp_ctrl_vec_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_rob_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rob_idx_0 : io_dmem_resp_0_bits_uop_rob_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ldq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldq_idx_0 : io_dmem_resp_0_bits_uop_ldq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_stq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stq_idx_0 : io_dmem_resp_0_bits_uop_stq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_rxq_idx = _resp_T_1 ? io_dmem_ll_resp_bits_uop_rxq_idx_0 : io_dmem_resp_0_bits_uop_rxq_idx_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_pdst_0 : io_dmem_resp_0_bits_uop_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_0 : io_dmem_resp_0_bits_uop_prs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_0 : io_dmem_resp_0_bits_uop_prs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_prs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_0 : io_dmem_resp_0_bits_uop_prs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_ppred = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_0 : io_dmem_resp_0_bits_uop_ppred_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs1_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs1_busy_0 : io_dmem_resp_0_bits_uop_prs1_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs2_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs2_busy_0 : io_dmem_resp_0_bits_uop_prs2_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_prs3_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_prs3_busy_0 : io_dmem_resp_0_bits_uop_prs3_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ppred_busy = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ppred_busy_0 : io_dmem_resp_0_bits_uop_ppred_busy_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [6:0] resp_uop_stale_pdst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_stale_pdst_0 : io_dmem_resp_0_bits_uop_stale_pdst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_exception = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exception_0 : io_dmem_resp_0_bits_uop_exception_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_uop_exc_cause = _resp_T_1 ? io_dmem_ll_resp_bits_uop_exc_cause_0 : io_dmem_resp_0_bits_uop_exc_cause_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_mem_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_cmd_0 : io_dmem_resp_0_bits_uop_mem_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_mem_size = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_size_0 : io_dmem_resp_0_bits_uop_mem_size_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_mem_signed = _resp_T_1 ? io_dmem_ll_resp_bits_uop_mem_signed_0 : io_dmem_resp_0_bits_uop_mem_signed_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_ldq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_ldq_0 : io_dmem_resp_0_bits_uop_uses_ldq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_uses_stq = _resp_T_1 ? io_dmem_ll_resp_bits_uop_uses_stq_0 : io_dmem_resp_0_bits_uop_uses_stq_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_is_unique = _resp_T_1 ? io_dmem_ll_resp_bits_uop_is_unique_0 : io_dmem_resp_0_bits_uop_is_unique_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_flush_on_commit = _resp_T_1 ? io_dmem_ll_resp_bits_uop_flush_on_commit_0 : io_dmem_resp_0_bits_uop_flush_on_commit_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_csr_cmd = _resp_T_1 ? io_dmem_ll_resp_bits_uop_csr_cmd_0 : io_dmem_resp_0_bits_uop_csr_cmd_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_ldst_is_rs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_is_rs1_0 : io_dmem_resp_0_bits_uop_ldst_is_rs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_ldst = _resp_T_1 ? io_dmem_ll_resp_bits_uop_ldst_0 : io_dmem_resp_0_bits_uop_ldst_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs1 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_0 : io_dmem_resp_0_bits_uop_lrs1_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs2 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_0 : io_dmem_resp_0_bits_uop_lrs2_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [5:0] resp_uop_lrs3 = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs3_0 : io_dmem_resp_0_bits_uop_lrs3_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_dst_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_dst_rtype_0 : io_dmem_resp_0_bits_uop_dst_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs1_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs1_rtype_0 : io_dmem_resp_0_bits_uop_lrs1_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_lrs2_rtype = _resp_T_1 ? io_dmem_ll_resp_bits_uop_lrs2_rtype_0 : io_dmem_resp_0_bits_uop_lrs2_rtype_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_frs3_en = _resp_T_1 ? io_dmem_ll_resp_bits_uop_frs3_en_0 : io_dmem_resp_0_bits_uop_frs3_en_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fcn_dw = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_dw_0 : io_dmem_resp_0_bits_uop_fcn_dw_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [4:0] resp_uop_fcn_op = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fcn_op_0 : io_dmem_resp_0_bits_uop_fcn_op_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_fp_val = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_val_0 : io_dmem_resp_0_bits_uop_fp_val_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_fp_rm = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_rm_0 : io_dmem_resp_0_bits_uop_fp_rm_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [1:0] resp_uop_fp_typ = _resp_T_1 ? io_dmem_ll_resp_bits_uop_fp_typ_0 : io_dmem_resp_0_bits_uop_fp_typ_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_pf_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_pf_if_0 : io_dmem_resp_0_bits_uop_xcpt_pf_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ae_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ae_if_0 : io_dmem_resp_0_bits_uop_xcpt_ae_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_xcpt_ma_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_xcpt_ma_if_0 : io_dmem_resp_0_bits_uop_xcpt_ma_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_debug_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_debug_if_0 : io_dmem_resp_0_bits_uop_bp_debug_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_uop_bp_xcpt_if = _resp_T_1 ? io_dmem_ll_resp_bits_uop_bp_xcpt_if_0 : io_dmem_resp_0_bits_uop_bp_xcpt_if_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_fsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_fsrc_0 : io_dmem_resp_0_bits_uop_debug_fsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [2:0] resp_uop_debug_tsrc = _resp_T_1 ? io_dmem_ll_resp_bits_uop_debug_tsrc_0 : io_dmem_resp_0_bits_uop_debug_tsrc_0; // @[lsu.scala:211:7, :1534:{19,43}] wire [63:0] resp_data = _resp_T_1 ? io_dmem_ll_resp_bits_data_0 : io_dmem_resp_0_bits_data_0; // @[lsu.scala:211:7, :1534:{19,43}] wire resp_is_hella = _resp_T_1 ? io_dmem_ll_resp_bits_is_hella_0 : io_dmem_resp_0_bits_is_hella_0; // @[lsu.scala:211:7, :1534:{19,43}] wire _io_dmem_ll_resp_ready_T = ~io_dmem_resp_0_valid_0; // @[lsu.scala:211:7, :1534:20, :1537:32] wire _io_dmem_ll_resp_ready_T_1 = ~wb_spec_wakeups_0_valid; // @[lsu.scala:1491:29, :1537:58] assign _io_dmem_ll_resp_ready_T_2 = _io_dmem_ll_resp_ready_T & _io_dmem_ll_resp_ready_T_1; // @[lsu.scala:1537:{32,55,58}] assign io_dmem_ll_resp_ready_0 = _io_dmem_ll_resp_ready_T_2; // @[lsu.scala:211:7, :1537:55] wire _T_2143 = io_dmem_ll_resp_ready_0 & io_dmem_ll_resp_valid_0; // @[Decoupled.scala:51:35] wire _T_1662 = io_dmem_resp_0_valid_0 | _T_2143; // @[Decoupled.scala:51:35] wire _GEN_653 = _T_1662 & resp_uop_uses_ldq; // @[lsu.scala:1534:19, :1539:33, :1540:32] wire uop_iq_type_0; // @[lsu.scala:1543:27] wire uop_iq_type_1; // @[lsu.scala:1543:27] wire uop_iq_type_2; // @[lsu.scala:1543:27] wire uop_iq_type_3; // @[lsu.scala:1543:27] wire uop_fu_code_0; // @[lsu.scala:1543:27] wire uop_fu_code_1; // @[lsu.scala:1543:27] wire uop_fu_code_2; // @[lsu.scala:1543:27] wire uop_fu_code_3; // @[lsu.scala:1543:27] wire uop_fu_code_4; // @[lsu.scala:1543:27] wire uop_fu_code_5; // @[lsu.scala:1543:27] wire uop_fu_code_6; // @[lsu.scala:1543:27] wire uop_fu_code_7; // @[lsu.scala:1543:27] wire uop_fu_code_8; // @[lsu.scala:1543:27] wire uop_fu_code_9; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ldst; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wen; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren1; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren2; // @[lsu.scala:1543:27] wire uop_fp_ctrl_ren3; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap12; // @[lsu.scala:1543:27] wire uop_fp_ctrl_swap23; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagIn; // @[lsu.scala:1543:27] wire [1:0] uop_fp_ctrl_typeTagOut; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fromint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_toint; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fastpipe; // @[lsu.scala:1543:27] wire uop_fp_ctrl_fma; // @[lsu.scala:1543:27] wire uop_fp_ctrl_div; // @[lsu.scala:1543:27] wire uop_fp_ctrl_sqrt; // @[lsu.scala:1543:27] wire uop_fp_ctrl_wflags; // @[lsu.scala:1543:27] wire uop_fp_ctrl_vec; // @[lsu.scala:1543:27] wire [31:0] uop_inst; // @[lsu.scala:1543:27] wire [31:0] uop_debug_inst; // @[lsu.scala:1543:27] wire uop_is_rvc; // @[lsu.scala:1543:27] wire [39:0] uop_debug_pc; // @[lsu.scala:1543:27] wire uop_iw_issued; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_agen; // @[lsu.scala:1543:27] wire uop_iw_issued_partial_dgen; // @[lsu.scala:1543:27] wire [2:0] uop_iw_p1_speculative_child; // @[lsu.scala:1543:27] wire [2:0] uop_iw_p2_speculative_child; // @[lsu.scala:1543:27] wire uop_iw_p1_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p2_bypass_hint; // @[lsu.scala:1543:27] wire uop_iw_p3_bypass_hint; // @[lsu.scala:1543:27] wire [2:0] uop_dis_col_sel; // @[lsu.scala:1543:27] wire [15:0] uop_br_mask; // @[lsu.scala:1543:27] wire [3:0] uop_br_tag; // @[lsu.scala:1543:27] wire [3:0] uop_br_type; // @[lsu.scala:1543:27] wire uop_is_sfb; // @[lsu.scala:1543:27] wire uop_is_fence; // @[lsu.scala:1543:27] wire uop_is_fencei; // @[lsu.scala:1543:27] wire uop_is_sfence; // @[lsu.scala:1543:27] wire uop_is_amo; // @[lsu.scala:1543:27] wire uop_is_eret; // @[lsu.scala:1543:27] wire uop_is_sys_pc2epc; // @[lsu.scala:1543:27] wire uop_is_rocc; // @[lsu.scala:1543:27] wire uop_is_mov; // @[lsu.scala:1543:27] wire [4:0] uop_ftq_idx; // @[lsu.scala:1543:27] wire uop_edge_inst; // @[lsu.scala:1543:27] wire [5:0] uop_pc_lob; // @[lsu.scala:1543:27] wire uop_taken; // @[lsu.scala:1543:27] wire uop_imm_rename; // @[lsu.scala:1543:27] wire [2:0] uop_imm_sel; // @[lsu.scala:1543:27] wire [4:0] uop_pimm; // @[lsu.scala:1543:27] wire [19:0] uop_imm_packed; // @[lsu.scala:1543:27] wire [1:0] uop_op1_sel; // @[lsu.scala:1543:27] wire [2:0] uop_op2_sel; // @[lsu.scala:1543:27] wire [6:0] uop_rob_idx; // @[lsu.scala:1543:27] wire [4:0] uop_ldq_idx; // @[lsu.scala:1543:27] wire [4:0] uop_stq_idx; // @[lsu.scala:1543:27] wire [1:0] uop_rxq_idx; // @[lsu.scala:1543:27] wire [6:0] uop_pdst; // @[lsu.scala:1543:27] wire [6:0] uop_prs1; // @[lsu.scala:1543:27] wire [6:0] uop_prs2; // @[lsu.scala:1543:27] wire [6:0] uop_prs3; // @[lsu.scala:1543:27] wire [4:0] uop_ppred; // @[lsu.scala:1543:27] wire uop_prs1_busy; // @[lsu.scala:1543:27] wire uop_prs2_busy; // @[lsu.scala:1543:27] wire uop_prs3_busy; // @[lsu.scala:1543:27] wire uop_ppred_busy; // @[lsu.scala:1543:27] wire [6:0] uop_stale_pdst; // @[lsu.scala:1543:27] wire uop_exception; // @[lsu.scala:1543:27] wire [63:0] uop_exc_cause; // @[lsu.scala:1543:27] wire [4:0] uop_mem_cmd; // @[lsu.scala:1543:27] wire [1:0] uop_mem_size; // @[lsu.scala:1543:27] wire uop_mem_signed; // @[lsu.scala:1543:27] wire uop_uses_ldq; // @[lsu.scala:1543:27] wire uop_uses_stq; // @[lsu.scala:1543:27] wire uop_is_unique; // @[lsu.scala:1543:27] wire uop_flush_on_commit; // @[lsu.scala:1543:27] wire [2:0] uop_csr_cmd; // @[lsu.scala:1543:27] wire uop_ldst_is_rs1; // @[lsu.scala:1543:27] wire [5:0] uop_ldst; // @[lsu.scala:1543:27] wire [5:0] uop_lrs1; // @[lsu.scala:1543:27] wire [5:0] uop_lrs2; // @[lsu.scala:1543:27] wire [5:0] uop_lrs3; // @[lsu.scala:1543:27] wire [1:0] uop_dst_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs1_rtype; // @[lsu.scala:1543:27] wire [1:0] uop_lrs2_rtype; // @[lsu.scala:1543:27] wire uop_frs3_en; // @[lsu.scala:1543:27] wire uop_fcn_dw; // @[lsu.scala:1543:27] wire [4:0] uop_fcn_op; // @[lsu.scala:1543:27] wire uop_fp_val; // @[lsu.scala:1543:27] wire [2:0] uop_fp_rm; // @[lsu.scala:1543:27] wire [1:0] uop_fp_typ; // @[lsu.scala:1543:27] wire uop_xcpt_pf_if; // @[lsu.scala:1543:27] wire uop_xcpt_ae_if; // @[lsu.scala:1543:27] wire uop_xcpt_ma_if; // @[lsu.scala:1543:27] wire uop_bp_debug_if; // @[lsu.scala:1543:27] wire uop_bp_xcpt_if; // @[lsu.scala:1543:27] wire [2:0] uop_debug_fsrc; // @[lsu.scala:1543:27] wire [2:0] uop_debug_tsrc; // @[lsu.scala:1543:27] assign uop_inst = _GEN_127[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_inst = _GEN_128[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rvc = _GEN_129[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_pc = _GEN_130[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_0 = _GEN_131[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_1 = _GEN_132[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_2 = _GEN_133[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iq_type_3 = _GEN_134[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_0 = _GEN_135[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_1 = _GEN_136[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_2 = _GEN_137[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_3 = _GEN_138[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_4 = _GEN_139[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_5 = _GEN_140[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_6 = _GEN_141[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_7 = _GEN_142[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_8 = _GEN_143[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fu_code_9 = _GEN_144[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued = _GEN_145[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_agen = _GEN_146[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_issued_partial_dgen = _GEN_147[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_speculative_child = _GEN_148[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_speculative_child = _GEN_149[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p1_bypass_hint = _GEN_150[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p2_bypass_hint = _GEN_151[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_iw_p3_bypass_hint = _GEN_152[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dis_col_sel = _GEN_153[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_mask = _GEN_154[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_tag = _GEN_155[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_br_type = _GEN_156[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfb = _GEN_157[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fence = _GEN_158[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_fencei = _GEN_159[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sfence = _GEN_160[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_amo = _GEN_161[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_eret = _GEN_162[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_sys_pc2epc = _GEN_163[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_rocc = _GEN_164[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_mov = _GEN_165[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ftq_idx = _GEN_166[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_edge_inst = _GEN_167[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pc_lob = _GEN_168[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_taken = _GEN_169[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_rename = _GEN_170[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_sel = _GEN_171[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pimm = _GEN_172[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_imm_packed = _GEN_173[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op1_sel = _GEN_174[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_op2_sel = _GEN_175[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ldst = _GEN_176[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wen = _GEN_177[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren1 = _GEN_178[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren2 = _GEN_179[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_ren3 = _GEN_180[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap12 = _GEN_181[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_swap23 = _GEN_182[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagIn = _GEN_183[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_typeTagOut = _GEN_184[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fromint = _GEN_185[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_toint = _GEN_186[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fastpipe = _GEN_187[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_fma = _GEN_188[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_div = _GEN_189[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_sqrt = _GEN_190[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_wflags = _GEN_191[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_ctrl_vec = _GEN_192[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rob_idx = _GEN_193[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldq_idx = _GEN_194[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stq_idx = _GEN_195[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_rxq_idx = _GEN_196[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_pdst = _GEN_197[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1 = _GEN_198[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2 = _GEN_199[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3 = _GEN_200[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred = _GEN_201[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs1_busy = _GEN_202[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs2_busy = _GEN_203[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_prs3_busy = _GEN_204[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ppred_busy = _GEN_205[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_stale_pdst = _GEN_206[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exception = _GEN_207[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_exc_cause = _GEN_208[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_cmd = _GEN_209[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_size = _GEN_210[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_mem_signed = _GEN_211[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_ldq = _GEN_212[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_uses_stq = _GEN_213[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_is_unique = _GEN_214[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_flush_on_commit = _GEN_215[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_csr_cmd = _GEN_216[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst_is_rs1 = _GEN_217[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_ldst = _GEN_218[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1 = _GEN_219[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2 = _GEN_220[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs3 = _GEN_221[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_dst_rtype = _GEN_222[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs1_rtype = _GEN_223[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_lrs2_rtype = _GEN_224[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_frs3_en = _GEN_225[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_dw = _GEN_226[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fcn_op = _GEN_227[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_val = _GEN_228[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_rm = _GEN_229[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_fp_typ = _GEN_230[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_pf_if = _GEN_231[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ae_if = _GEN_232[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_xcpt_ma_if = _GEN_233[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_debug_if = _GEN_234[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_bp_xcpt_if = _GEN_235[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_fsrc = _GEN_236[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] assign uop_debug_tsrc = _GEN_237[resp_uop_ldq_idx]; // @[lsu.scala:235:32, :1534:19, :1543:27] wire send_iresp = uop_dst_rtype == 2'h0; // @[lsu.scala:1543:27, :1544:40] wire send_fresp = uop_dst_rtype == 2'h1; // @[lsu.scala:1543:27, :1545:40] wire _ldq_will_succeed_T = iresp_0_valid | fresp_0_valid; // @[lsu.scala:1477:19, :1478:19, :1560:54] wire _GEN_654 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h0; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_655 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h1; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_656 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h2; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_657 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h3; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_658 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h4; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_659 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h5; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_660 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h6; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_661 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h7; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_662 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h8; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_663 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h9; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_664 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hA; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_665 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hB; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_666 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hC; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_667 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hD; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_668 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hE; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_669 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'hF; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_670 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h10; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_671 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h11; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_672 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h12; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_673 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h13; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_674 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h14; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_675 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h15; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_676 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h16; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] wire _GEN_677 = _T_1662 & resp_uop_uses_ldq & resp_uop_ldq_idx == 5'h17; // @[lsu.scala:394:59, :1534:19, :1539:{33,83}, :1540:32, :1560:36] assign dmem_resp_fired_0 = _T_1662 & (resp_uop_uses_stq | resp_uop_uses_ldq); // @[lsu.scala:1497:33, :1534:19, :1539:{33,83}, :1540:32, :1558:28, :1571:7, :1574:28] wire _GEN_678 = _T_1662 & (resp_uop_uses_stq | resp_uop_uses_ldq & send_iresp); // @[lsu.scala:1481:20, :1534:19, :1539:{33,83}, :1540:32, :1544:40, :1549:28, :1571:7, :1575:28] wire _T_1676 = dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1594:30] wire _T_1678 = ~dmem_resp_fired_0 & wb_ldst_forward_valid_0; // @[lsu.scala:1172:38, :1497:33, :1598:{18,38}] wire [1:0] size; // @[AMOALU.scala:11:18] assign size = _GEN_334[wb_ldst_forward_stq_idx_0]; // @[AMOALU.scala:11:18, :12:8] wire [3:0][63:0] _GEN_679 = {{_GEN_366[wb_ldst_forward_stq_idx_0]}, {{2{_GEN_366[wb_ldst_forward_stq_idx_0][31:0]}}}, {{2{{2{_GEN_366[wb_ldst_forward_stq_idx_0][15:0]}}}}}, {{2{{2{{2{_GEN_366[wb_ldst_forward_stq_idx_0][7:0]}}}}}}}}; // @[AMOALU.scala:29:{13,19,32,69}] wire _GEN_680 = wb_ldst_forward_e_0_uop_dst_rtype == 2'h0; // @[lsu.scala:321:49, :1612:60] wire _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1612:60] assign _wb_slow_wakeups_0_valid_T = _GEN_680; // @[lsu.scala:1612:60] wire _iresp_0_valid_T; // @[lsu.scala:1618:48] assign _iresp_0_valid_T = _GEN_680; // @[lsu.scala:1612:60, :1618:48] wire _GEN_681 = _T_1676 | ~_T_1678; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1598:38, :1599:5] assign wb_slow_wakeups_0_valid = _GEN_681 ? _GEN_678 : _wb_slow_wakeups_0_valid_T; // @[lsu.scala:1481:20, :1494:29, :1539:83, :1571:7, :1595:5, :1599:5, :1612:60] wire [31:0] _GEN_682 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_251[resp_uop_stq_idx] : uop_inst) : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_inst = _GEN_682; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_inst = _GEN_682; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [31:0] _GEN_683 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_252[resp_uop_stq_idx] : uop_debug_inst) : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_inst = _GEN_683; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_inst = _GEN_683; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_684 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_253[resp_uop_stq_idx] : uop_is_rvc) : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rvc = _GEN_684; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rvc = _GEN_684; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [39:0] _GEN_685 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_254[resp_uop_stq_idx] : uop_debug_pc) : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_pc = _GEN_685; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_pc = _GEN_685; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_686 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_255[resp_uop_stq_idx] : uop_iq_type_0) : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_0 = _GEN_686; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_0 = _GEN_686; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_687 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_256[resp_uop_stq_idx] : uop_iq_type_1) : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_1 = _GEN_687; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_1 = _GEN_687; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_688 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_257[resp_uop_stq_idx] : uop_iq_type_2) : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_2 = _GEN_688; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_2 = _GEN_688; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_689 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_258[resp_uop_stq_idx] : uop_iq_type_3) : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iq_type_3 = _GEN_689; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iq_type_3 = _GEN_689; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_690 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_259[resp_uop_stq_idx] : uop_fu_code_0) : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_0 = _GEN_690; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_0 = _GEN_690; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_691 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_260[resp_uop_stq_idx] : uop_fu_code_1) : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_1 = _GEN_691; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_1 = _GEN_691; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_692 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_261[resp_uop_stq_idx] : uop_fu_code_2) : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_2 = _GEN_692; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_2 = _GEN_692; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_693 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_262[resp_uop_stq_idx] : uop_fu_code_3) : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_3 = _GEN_693; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_3 = _GEN_693; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_694 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_263[resp_uop_stq_idx] : uop_fu_code_4) : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_4 = _GEN_694; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_4 = _GEN_694; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_695 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_264[resp_uop_stq_idx] : uop_fu_code_5) : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_5 = _GEN_695; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_5 = _GEN_695; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_696 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_265[resp_uop_stq_idx] : uop_fu_code_6) : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_6 = _GEN_696; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_6 = _GEN_696; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_697 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_266[resp_uop_stq_idx] : uop_fu_code_7) : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_7 = _GEN_697; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_7 = _GEN_697; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_698 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_267[resp_uop_stq_idx] : uop_fu_code_8) : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_8 = _GEN_698; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_8 = _GEN_698; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_699 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_268[resp_uop_stq_idx] : uop_fu_code_9) : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fu_code_9 = _GEN_699; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fu_code_9 = _GEN_699; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_700 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_269[resp_uop_stq_idx] : uop_iw_issued) : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued = _GEN_700; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued = _GEN_700; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_701 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_270[resp_uop_stq_idx] : uop_iw_issued_partial_agen) : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_agen = _GEN_701; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_agen = _GEN_701; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_702 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_271[resp_uop_stq_idx] : uop_iw_issued_partial_dgen) : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_issued_partial_dgen = _GEN_702; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_issued_partial_dgen = _GEN_702; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_703 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_272[resp_uop_stq_idx] : uop_iw_p1_speculative_child) : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_speculative_child = _GEN_703; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_speculative_child = _GEN_703; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_704 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_273[resp_uop_stq_idx] : uop_iw_p2_speculative_child) : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_speculative_child = _GEN_704; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_speculative_child = _GEN_704; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_705 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_274[resp_uop_stq_idx] : uop_iw_p1_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p1_bypass_hint = _GEN_705; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p1_bypass_hint = _GEN_705; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_706 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_275[resp_uop_stq_idx] : uop_iw_p2_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p2_bypass_hint = _GEN_706; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p2_bypass_hint = _GEN_706; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_707 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_276[resp_uop_stq_idx] : uop_iw_p3_bypass_hint) : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_iw_p3_bypass_hint = _GEN_707; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_iw_p3_bypass_hint = _GEN_707; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_708 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_277[resp_uop_stq_idx] : uop_dis_col_sel) : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dis_col_sel = _GEN_708; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dis_col_sel = _GEN_708; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [15:0] _GEN_709 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_278[resp_uop_stq_idx] : uop_br_mask) : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_mask = _GEN_709; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_mask = _GEN_709; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_710 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_279[resp_uop_stq_idx] : uop_br_tag) : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_tag = _GEN_710; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_tag = _GEN_710; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [3:0] _GEN_711 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_280[resp_uop_stq_idx] : uop_br_type) : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_br_type = _GEN_711; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_br_type = _GEN_711; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_712 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_281[resp_uop_stq_idx] : uop_is_sfb) : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfb = _GEN_712; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfb = _GEN_712; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_713 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_282[resp_uop_stq_idx] : uop_is_fence) : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fence = _GEN_713; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fence = _GEN_713; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_714 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_283[resp_uop_stq_idx] : uop_is_fencei) : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_fencei = _GEN_714; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_fencei = _GEN_714; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_715 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_284[resp_uop_stq_idx] : uop_is_sfence) : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sfence = _GEN_715; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sfence = _GEN_715; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_716 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_285[resp_uop_stq_idx] : uop_is_amo) : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_amo = _GEN_716; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_amo = _GEN_716; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_717 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_286[resp_uop_stq_idx] : uop_is_eret) : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_eret = _GEN_717; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_eret = _GEN_717; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_718 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_287[resp_uop_stq_idx] : uop_is_sys_pc2epc) : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_sys_pc2epc = _GEN_718; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_sys_pc2epc = _GEN_718; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_719 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_288[resp_uop_stq_idx] : uop_is_rocc) : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_rocc = _GEN_719; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_rocc = _GEN_719; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_720 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_289[resp_uop_stq_idx] : uop_is_mov) : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_mov = _GEN_720; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_mov = _GEN_720; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_721 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_290[resp_uop_stq_idx] : uop_ftq_idx) : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ftq_idx = _GEN_721; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ftq_idx = _GEN_721; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_722 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_291[resp_uop_stq_idx] : uop_edge_inst) : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_edge_inst = _GEN_722; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_edge_inst = _GEN_722; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_723 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_292[resp_uop_stq_idx] : uop_pc_lob) : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pc_lob = _GEN_723; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pc_lob = _GEN_723; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_724 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_293[resp_uop_stq_idx] : uop_taken) : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_taken = _GEN_724; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_taken = _GEN_724; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_725 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_294[resp_uop_stq_idx] : uop_imm_rename) : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_rename = _GEN_725; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_rename = _GEN_725; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_726 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_295[resp_uop_stq_idx] : uop_imm_sel) : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_sel = _GEN_726; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_sel = _GEN_726; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_727 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_296[resp_uop_stq_idx] : uop_pimm) : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pimm = _GEN_727; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pimm = _GEN_727; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [19:0] _GEN_728 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_297[resp_uop_stq_idx] : uop_imm_packed) : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_imm_packed = _GEN_728; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_imm_packed = _GEN_728; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_729 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_298[resp_uop_stq_idx] : uop_op1_sel) : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op1_sel = _GEN_729; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op1_sel = _GEN_729; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_730 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_299[resp_uop_stq_idx] : uop_op2_sel) : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_op2_sel = _GEN_730; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_op2_sel = _GEN_730; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_731 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_300[resp_uop_stq_idx] : uop_fp_ctrl_ldst) : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ldst = _GEN_731; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ldst = _GEN_731; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_732 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_301[resp_uop_stq_idx] : uop_fp_ctrl_wen) : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wen = _GEN_732; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wen = _GEN_732; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_733 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_302[resp_uop_stq_idx] : uop_fp_ctrl_ren1) : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren1 = _GEN_733; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren1 = _GEN_733; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_734 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_303[resp_uop_stq_idx] : uop_fp_ctrl_ren2) : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren2 = _GEN_734; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren2 = _GEN_734; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_735 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_304[resp_uop_stq_idx] : uop_fp_ctrl_ren3) : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_ren3 = _GEN_735; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_ren3 = _GEN_735; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_736 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_305[resp_uop_stq_idx] : uop_fp_ctrl_swap12) : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap12 = _GEN_736; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap12 = _GEN_736; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_737 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_306[resp_uop_stq_idx] : uop_fp_ctrl_swap23) : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_swap23 = _GEN_737; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_swap23 = _GEN_737; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_738 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_307[resp_uop_stq_idx] : uop_fp_ctrl_typeTagIn) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_738; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = _GEN_738; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_739 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_308[resp_uop_stq_idx] : uop_fp_ctrl_typeTagOut) : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_739; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = _GEN_739; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_740 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_309[resp_uop_stq_idx] : uop_fp_ctrl_fromint) : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fromint = _GEN_740; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fromint = _GEN_740; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_741 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_310[resp_uop_stq_idx] : uop_fp_ctrl_toint) : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_toint = _GEN_741; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_toint = _GEN_741; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_742 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_311[resp_uop_stq_idx] : uop_fp_ctrl_fastpipe) : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_742; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = _GEN_742; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_743 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_312[resp_uop_stq_idx] : uop_fp_ctrl_fma) : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_fma = _GEN_743; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_fma = _GEN_743; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_744 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_313[resp_uop_stq_idx] : uop_fp_ctrl_div) : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_div = _GEN_744; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_div = _GEN_744; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_745 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_314[resp_uop_stq_idx] : uop_fp_ctrl_sqrt) : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_sqrt = _GEN_745; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_sqrt = _GEN_745; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_746 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_315[resp_uop_stq_idx] : uop_fp_ctrl_wflags) : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_wflags = _GEN_746; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_wflags = _GEN_746; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_747 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_316[resp_uop_stq_idx] : uop_fp_ctrl_vec) : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_ctrl_vec = _GEN_747; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_ctrl_vec = _GEN_747; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_748 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_317[resp_uop_stq_idx] : uop_rob_idx) : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rob_idx = _GEN_748; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rob_idx = _GEN_748; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_749 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_318[resp_uop_stq_idx] : uop_ldq_idx) : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldq_idx = _GEN_749; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldq_idx = _GEN_749; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_750 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_319[resp_uop_stq_idx] : uop_stq_idx) : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stq_idx = _GEN_750; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stq_idx = _GEN_750; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_751 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_320[resp_uop_stq_idx] : uop_rxq_idx) : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_rxq_idx = _GEN_751; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_rxq_idx = _GEN_751; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_752 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_321[resp_uop_stq_idx] : uop_pdst) : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_pdst = _GEN_752; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_pdst = _GEN_752; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_753 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_322[resp_uop_stq_idx] : uop_prs1) : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1 = _GEN_753; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1 = _GEN_753; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_754 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_323[resp_uop_stq_idx] : uop_prs2) : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2 = _GEN_754; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2 = _GEN_754; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_755 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_324[resp_uop_stq_idx] : uop_prs3) : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3 = _GEN_755; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3 = _GEN_755; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_756 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_325[resp_uop_stq_idx] : uop_ppred) : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred = _GEN_756; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred = _GEN_756; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_757 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_326[resp_uop_stq_idx] : uop_prs1_busy) : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs1_busy = _GEN_757; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs1_busy = _GEN_757; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_758 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_327[resp_uop_stq_idx] : uop_prs2_busy) : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs2_busy = _GEN_758; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs2_busy = _GEN_758; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_759 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_328[resp_uop_stq_idx] : uop_prs3_busy) : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_prs3_busy = _GEN_759; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_prs3_busy = _GEN_759; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_760 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_329[resp_uop_stq_idx] : uop_ppred_busy) : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ppred_busy = _GEN_760; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ppred_busy = _GEN_760; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [6:0] _GEN_761 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_330[resp_uop_stq_idx] : uop_stale_pdst) : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_stale_pdst = _GEN_761; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_stale_pdst = _GEN_761; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_762 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_331[resp_uop_stq_idx] : uop_exception) : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exception = _GEN_762; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exception = _GEN_762; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [63:0] _GEN_763 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_332[resp_uop_stq_idx] : uop_exc_cause) : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_exc_cause = _GEN_763; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_exc_cause = _GEN_763; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_764 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_333[resp_uop_stq_idx] : uop_mem_cmd) : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_cmd = _GEN_764; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_cmd = _GEN_764; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_765 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_334[resp_uop_stq_idx] : uop_mem_size) : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_size = _GEN_765; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_size = _GEN_765; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_766 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_335[resp_uop_stq_idx] : uop_mem_signed) : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_mem_signed = _GEN_766; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_mem_signed = _GEN_766; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_767 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_336[resp_uop_stq_idx] : uop_uses_ldq) : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_ldq = _GEN_767; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_ldq = _GEN_767; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_768 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_337[resp_uop_stq_idx] : uop_uses_stq) : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_uses_stq = _GEN_768; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_uses_stq = _GEN_768; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_769 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_338[resp_uop_stq_idx] : uop_is_unique) : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_is_unique = _GEN_769; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_is_unique = _GEN_769; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_770 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_339[resp_uop_stq_idx] : uop_flush_on_commit) : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_flush_on_commit = _GEN_770; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_flush_on_commit = _GEN_770; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_771 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_340[resp_uop_stq_idx] : uop_csr_cmd) : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_csr_cmd = _GEN_771; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_csr_cmd = _GEN_771; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_772 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_341[resp_uop_stq_idx] : uop_ldst_is_rs1) : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst_is_rs1 = _GEN_772; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst_is_rs1 = _GEN_772; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_773 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_342[resp_uop_stq_idx] : uop_ldst) : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_ldst = _GEN_773; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_ldst = _GEN_773; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_774 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_343[resp_uop_stq_idx] : uop_lrs1) : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1 = _GEN_774; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1 = _GEN_774; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_775 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_344[resp_uop_stq_idx] : uop_lrs2) : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2 = _GEN_775; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2 = _GEN_775; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [5:0] _GEN_776 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_345[resp_uop_stq_idx] : uop_lrs3) : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs3 = _GEN_776; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs3 = _GEN_776; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_777 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_346[resp_uop_stq_idx] : uop_dst_rtype) : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_dst_rtype = _GEN_777; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_dst_rtype = _GEN_777; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_778 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_347[resp_uop_stq_idx] : uop_lrs1_rtype) : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs1_rtype = _GEN_778; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs1_rtype = _GEN_778; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_779 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_348[resp_uop_stq_idx] : uop_lrs2_rtype) : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_lrs2_rtype = _GEN_779; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_lrs2_rtype = _GEN_779; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_780 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_349[resp_uop_stq_idx] : uop_frs3_en) : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_frs3_en = _GEN_780; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_frs3_en = _GEN_780; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_781 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_350[resp_uop_stq_idx] : uop_fcn_dw) : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_dw = _GEN_781; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_dw = _GEN_781; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [4:0] _GEN_782 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_351[resp_uop_stq_idx] : uop_fcn_op) : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fcn_op = _GEN_782; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fcn_op = _GEN_782; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_783 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_352[resp_uop_stq_idx] : uop_fp_val) : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_val = _GEN_783; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_val = _GEN_783; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_784 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_353[resp_uop_stq_idx] : uop_fp_rm) : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_rm = _GEN_784; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_rm = _GEN_784; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [1:0] _GEN_785 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_354[resp_uop_stq_idx] : uop_fp_typ) : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_fp_typ = _GEN_785; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_fp_typ = _GEN_785; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_786 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_355[resp_uop_stq_idx] : uop_xcpt_pf_if) : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_pf_if = _GEN_786; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_pf_if = _GEN_786; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_787 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_356[resp_uop_stq_idx] : uop_xcpt_ae_if) : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ae_if = _GEN_787; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ae_if = _GEN_787; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_788 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_357[resp_uop_stq_idx] : uop_xcpt_ma_if) : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_xcpt_ma_if = _GEN_788; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_xcpt_ma_if = _GEN_788; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_789 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_358[resp_uop_stq_idx] : uop_bp_debug_if) : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_debug_if = _GEN_789; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_debug_if = _GEN_789; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire _GEN_790 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_359[resp_uop_stq_idx] : uop_bp_xcpt_if) : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_bp_xcpt_if = _GEN_790; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_bp_xcpt_if = _GEN_790; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_791 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_360[resp_uop_stq_idx] : uop_debug_fsrc) : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_fsrc = _GEN_791; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_fsrc = _GEN_791; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] wire [2:0] _GEN_792 = _GEN_681 ? (resp_uop_uses_stq ? _GEN_361[resp_uop_stq_idx] : uop_debug_tsrc) : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:264:32, :321:49, :1534:19, :1539:83, :1540:32, :1543:27, :1571:7, :1576:28, :1595:5, :1599:5] assign iresp_0_bits_uop_debug_tsrc = _GEN_792; // @[lsu.scala:1477:19, :1539:83, :1595:5, :1599:5] assign wb_slow_wakeups_0_bits_uop_debug_tsrc = _GEN_792; // @[lsu.scala:1494:29, :1539:83, :1595:5, :1599:5] assign iresp_0_valid = _GEN_681 ? _GEN_678 : _iresp_0_valid_T; // @[lsu.scala:1477:19, :1481:20, :1539:83, :1571:7, :1595:5, :1599:5, :1618:48] wire _fresp_0_valid_T = wb_ldst_forward_e_0_uop_dst_rtype == 2'h1; // @[lsu.scala:321:49, :1619:48] assign fresp_0_valid = _GEN_681 ? _GEN_653 & send_fresp : _fresp_0_valid_T; // @[lsu.scala:1478:19, :1483:20, :1539:83, :1540:32, :1545:40, :1554:28, :1595:5, :1599:5, :1619:48] assign fresp_0_bits_uop_inst = _GEN_681 ? uop_inst : wb_ldst_forward_e_0_uop_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_inst = _GEN_681 ? uop_debug_inst : wb_ldst_forward_e_0_uop_debug_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rvc = _GEN_681 ? uop_is_rvc : wb_ldst_forward_e_0_uop_is_rvc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_pc = _GEN_681 ? uop_debug_pc : wb_ldst_forward_e_0_uop_debug_pc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_0 = _GEN_681 ? uop_iq_type_0 : wb_ldst_forward_e_0_uop_iq_type_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_1 = _GEN_681 ? uop_iq_type_1 : wb_ldst_forward_e_0_uop_iq_type_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_2 = _GEN_681 ? uop_iq_type_2 : wb_ldst_forward_e_0_uop_iq_type_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iq_type_3 = _GEN_681 ? uop_iq_type_3 : wb_ldst_forward_e_0_uop_iq_type_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_0 = _GEN_681 ? uop_fu_code_0 : wb_ldst_forward_e_0_uop_fu_code_0; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_1 = _GEN_681 ? uop_fu_code_1 : wb_ldst_forward_e_0_uop_fu_code_1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_2 = _GEN_681 ? uop_fu_code_2 : wb_ldst_forward_e_0_uop_fu_code_2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_3 = _GEN_681 ? uop_fu_code_3 : wb_ldst_forward_e_0_uop_fu_code_3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_4 = _GEN_681 ? uop_fu_code_4 : wb_ldst_forward_e_0_uop_fu_code_4; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_5 = _GEN_681 ? uop_fu_code_5 : wb_ldst_forward_e_0_uop_fu_code_5; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_6 = _GEN_681 ? uop_fu_code_6 : wb_ldst_forward_e_0_uop_fu_code_6; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_7 = _GEN_681 ? uop_fu_code_7 : wb_ldst_forward_e_0_uop_fu_code_7; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_8 = _GEN_681 ? uop_fu_code_8 : wb_ldst_forward_e_0_uop_fu_code_8; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fu_code_9 = _GEN_681 ? uop_fu_code_9 : wb_ldst_forward_e_0_uop_fu_code_9; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued = _GEN_681 ? uop_iw_issued : wb_ldst_forward_e_0_uop_iw_issued; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_agen = _GEN_681 ? uop_iw_issued_partial_agen : wb_ldst_forward_e_0_uop_iw_issued_partial_agen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_issued_partial_dgen = _GEN_681 ? uop_iw_issued_partial_dgen : wb_ldst_forward_e_0_uop_iw_issued_partial_dgen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_speculative_child = _GEN_681 ? uop_iw_p1_speculative_child : wb_ldst_forward_e_0_uop_iw_p1_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_speculative_child = _GEN_681 ? uop_iw_p2_speculative_child : wb_ldst_forward_e_0_uop_iw_p2_speculative_child; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p1_bypass_hint = _GEN_681 ? uop_iw_p1_bypass_hint : wb_ldst_forward_e_0_uop_iw_p1_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p2_bypass_hint = _GEN_681 ? uop_iw_p2_bypass_hint : wb_ldst_forward_e_0_uop_iw_p2_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_iw_p3_bypass_hint = _GEN_681 ? uop_iw_p3_bypass_hint : wb_ldst_forward_e_0_uop_iw_p3_bypass_hint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dis_col_sel = _GEN_681 ? uop_dis_col_sel : wb_ldst_forward_e_0_uop_dis_col_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_mask = _GEN_681 ? uop_br_mask : wb_ldst_forward_e_0_uop_br_mask; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_tag = _GEN_681 ? uop_br_tag : wb_ldst_forward_e_0_uop_br_tag; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_br_type = _GEN_681 ? uop_br_type : wb_ldst_forward_e_0_uop_br_type; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfb = _GEN_681 ? uop_is_sfb : wb_ldst_forward_e_0_uop_is_sfb; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fence = _GEN_681 ? uop_is_fence : wb_ldst_forward_e_0_uop_is_fence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_fencei = _GEN_681 ? uop_is_fencei : wb_ldst_forward_e_0_uop_is_fencei; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sfence = _GEN_681 ? uop_is_sfence : wb_ldst_forward_e_0_uop_is_sfence; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_amo = _GEN_681 ? uop_is_amo : wb_ldst_forward_e_0_uop_is_amo; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_eret = _GEN_681 ? uop_is_eret : wb_ldst_forward_e_0_uop_is_eret; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_sys_pc2epc = _GEN_681 ? uop_is_sys_pc2epc : wb_ldst_forward_e_0_uop_is_sys_pc2epc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_rocc = _GEN_681 ? uop_is_rocc : wb_ldst_forward_e_0_uop_is_rocc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_mov = _GEN_681 ? uop_is_mov : wb_ldst_forward_e_0_uop_is_mov; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ftq_idx = _GEN_681 ? uop_ftq_idx : wb_ldst_forward_e_0_uop_ftq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_edge_inst = _GEN_681 ? uop_edge_inst : wb_ldst_forward_e_0_uop_edge_inst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pc_lob = _GEN_681 ? uop_pc_lob : wb_ldst_forward_e_0_uop_pc_lob; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_taken = _GEN_681 ? uop_taken : wb_ldst_forward_e_0_uop_taken; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_rename = _GEN_681 ? uop_imm_rename : wb_ldst_forward_e_0_uop_imm_rename; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_sel = _GEN_681 ? uop_imm_sel : wb_ldst_forward_e_0_uop_imm_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pimm = _GEN_681 ? uop_pimm : wb_ldst_forward_e_0_uop_pimm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_imm_packed = _GEN_681 ? uop_imm_packed : wb_ldst_forward_e_0_uop_imm_packed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op1_sel = _GEN_681 ? uop_op1_sel : wb_ldst_forward_e_0_uop_op1_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_op2_sel = _GEN_681 ? uop_op2_sel : wb_ldst_forward_e_0_uop_op2_sel; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ldst = _GEN_681 ? uop_fp_ctrl_ldst : wb_ldst_forward_e_0_uop_fp_ctrl_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wen = _GEN_681 ? uop_fp_ctrl_wen : wb_ldst_forward_e_0_uop_fp_ctrl_wen; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren1 = _GEN_681 ? uop_fp_ctrl_ren1 : wb_ldst_forward_e_0_uop_fp_ctrl_ren1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren2 = _GEN_681 ? uop_fp_ctrl_ren2 : wb_ldst_forward_e_0_uop_fp_ctrl_ren2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_ren3 = _GEN_681 ? uop_fp_ctrl_ren3 : wb_ldst_forward_e_0_uop_fp_ctrl_ren3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap12 = _GEN_681 ? uop_fp_ctrl_swap12 : wb_ldst_forward_e_0_uop_fp_ctrl_swap12; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_swap23 = _GEN_681 ? uop_fp_ctrl_swap23 : wb_ldst_forward_e_0_uop_fp_ctrl_swap23; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagIn = _GEN_681 ? uop_fp_ctrl_typeTagIn : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagIn; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_typeTagOut = _GEN_681 ? uop_fp_ctrl_typeTagOut : wb_ldst_forward_e_0_uop_fp_ctrl_typeTagOut; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fromint = _GEN_681 ? uop_fp_ctrl_fromint : wb_ldst_forward_e_0_uop_fp_ctrl_fromint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_toint = _GEN_681 ? uop_fp_ctrl_toint : wb_ldst_forward_e_0_uop_fp_ctrl_toint; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fastpipe = _GEN_681 ? uop_fp_ctrl_fastpipe : wb_ldst_forward_e_0_uop_fp_ctrl_fastpipe; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_fma = _GEN_681 ? uop_fp_ctrl_fma : wb_ldst_forward_e_0_uop_fp_ctrl_fma; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_div = _GEN_681 ? uop_fp_ctrl_div : wb_ldst_forward_e_0_uop_fp_ctrl_div; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_sqrt = _GEN_681 ? uop_fp_ctrl_sqrt : wb_ldst_forward_e_0_uop_fp_ctrl_sqrt; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_wflags = _GEN_681 ? uop_fp_ctrl_wflags : wb_ldst_forward_e_0_uop_fp_ctrl_wflags; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_ctrl_vec = _GEN_681 ? uop_fp_ctrl_vec : wb_ldst_forward_e_0_uop_fp_ctrl_vec; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rob_idx = _GEN_681 ? uop_rob_idx : wb_ldst_forward_e_0_uop_rob_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldq_idx = _GEN_681 ? uop_ldq_idx : wb_ldst_forward_e_0_uop_ldq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stq_idx = _GEN_681 ? uop_stq_idx : wb_ldst_forward_e_0_uop_stq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_rxq_idx = _GEN_681 ? uop_rxq_idx : wb_ldst_forward_e_0_uop_rxq_idx; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_pdst = _GEN_681 ? uop_pdst : wb_ldst_forward_e_0_uop_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1 = _GEN_681 ? uop_prs1 : wb_ldst_forward_e_0_uop_prs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2 = _GEN_681 ? uop_prs2 : wb_ldst_forward_e_0_uop_prs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3 = _GEN_681 ? uop_prs3 : wb_ldst_forward_e_0_uop_prs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred = _GEN_681 ? uop_ppred : wb_ldst_forward_e_0_uop_ppred; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs1_busy = _GEN_681 ? uop_prs1_busy : wb_ldst_forward_e_0_uop_prs1_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs2_busy = _GEN_681 ? uop_prs2_busy : wb_ldst_forward_e_0_uop_prs2_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_prs3_busy = _GEN_681 ? uop_prs3_busy : wb_ldst_forward_e_0_uop_prs3_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ppred_busy = _GEN_681 ? uop_ppred_busy : wb_ldst_forward_e_0_uop_ppred_busy; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_stale_pdst = _GEN_681 ? uop_stale_pdst : wb_ldst_forward_e_0_uop_stale_pdst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exception = _GEN_681 ? uop_exception : wb_ldst_forward_e_0_uop_exception; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_exc_cause = _GEN_681 ? uop_exc_cause : wb_ldst_forward_e_0_uop_exc_cause; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_cmd = _GEN_681 ? uop_mem_cmd : wb_ldst_forward_e_0_uop_mem_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_size = _GEN_681 ? uop_mem_size : wb_ldst_forward_e_0_uop_mem_size; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_mem_signed = _GEN_681 ? uop_mem_signed : wb_ldst_forward_e_0_uop_mem_signed; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_ldq = _GEN_681 ? uop_uses_ldq : wb_ldst_forward_e_0_uop_uses_ldq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_uses_stq = _GEN_681 ? uop_uses_stq : wb_ldst_forward_e_0_uop_uses_stq; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_is_unique = _GEN_681 ? uop_is_unique : wb_ldst_forward_e_0_uop_is_unique; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_flush_on_commit = _GEN_681 ? uop_flush_on_commit : wb_ldst_forward_e_0_uop_flush_on_commit; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_csr_cmd = _GEN_681 ? uop_csr_cmd : wb_ldst_forward_e_0_uop_csr_cmd; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst_is_rs1 = _GEN_681 ? uop_ldst_is_rs1 : wb_ldst_forward_e_0_uop_ldst_is_rs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_ldst = _GEN_681 ? uop_ldst : wb_ldst_forward_e_0_uop_ldst; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1 = _GEN_681 ? uop_lrs1 : wb_ldst_forward_e_0_uop_lrs1; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2 = _GEN_681 ? uop_lrs2 : wb_ldst_forward_e_0_uop_lrs2; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs3 = _GEN_681 ? uop_lrs3 : wb_ldst_forward_e_0_uop_lrs3; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_dst_rtype = _GEN_681 ? uop_dst_rtype : wb_ldst_forward_e_0_uop_dst_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs1_rtype = _GEN_681 ? uop_lrs1_rtype : wb_ldst_forward_e_0_uop_lrs1_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_lrs2_rtype = _GEN_681 ? uop_lrs2_rtype : wb_ldst_forward_e_0_uop_lrs2_rtype; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_frs3_en = _GEN_681 ? uop_frs3_en : wb_ldst_forward_e_0_uop_frs3_en; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_dw = _GEN_681 ? uop_fcn_dw : wb_ldst_forward_e_0_uop_fcn_dw; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fcn_op = _GEN_681 ? uop_fcn_op : wb_ldst_forward_e_0_uop_fcn_op; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_val = _GEN_681 ? uop_fp_val : wb_ldst_forward_e_0_uop_fp_val; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_rm = _GEN_681 ? uop_fp_rm : wb_ldst_forward_e_0_uop_fp_rm; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_fp_typ = _GEN_681 ? uop_fp_typ : wb_ldst_forward_e_0_uop_fp_typ; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_pf_if = _GEN_681 ? uop_xcpt_pf_if : wb_ldst_forward_e_0_uop_xcpt_pf_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ae_if = _GEN_681 ? uop_xcpt_ae_if : wb_ldst_forward_e_0_uop_xcpt_ae_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_xcpt_ma_if = _GEN_681 ? uop_xcpt_ma_if : wb_ldst_forward_e_0_uop_xcpt_ma_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_debug_if = _GEN_681 ? uop_bp_debug_if : wb_ldst_forward_e_0_uop_bp_debug_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_bp_xcpt_if = _GEN_681 ? uop_bp_xcpt_if : wb_ldst_forward_e_0_uop_bp_xcpt_if; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_fsrc = _GEN_681 ? uop_debug_fsrc : wb_ldst_forward_e_0_uop_debug_fsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] assign fresp_0_bits_uop_debug_tsrc = _GEN_681 ? uop_debug_tsrc : wb_ldst_forward_e_0_uop_debug_tsrc; // @[lsu.scala:321:49, :1478:19, :1539:83, :1543:27, :1595:5, :1599:5] wire [31:0] _iresp_0_bits_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _iresp_0_bits_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _fresp_0_bits_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _fresp_0_bits_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _ldq_debug_wb_data_shifted_T_1 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37] wire [31:0] _ldq_debug_wb_data_T_5 = _GEN_679[size][63:32]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:37, :45:94] wire [31:0] _iresp_0_bits_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _fresp_0_bits_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] _ldq_debug_wb_data_shifted_T_2 = _GEN_679[size][31:0]; // @[AMOALU.scala:11:18, :29:{13,19}, :42:55] wire [31:0] iresp_0_bits_data_shifted = _iresp_0_bits_data_shifted_T ? _iresp_0_bits_data_shifted_T_1 : _iresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] iresp_0_bits_data_zeroed = iresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _GEN_793 = size_1 == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T = _GEN_793; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_1 = _iresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_2 = iresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _iresp_0_bits_data_T_4 = {32{_iresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _iresp_0_bits_data_T_6 = _iresp_0_bits_data_T_1 ? _iresp_0_bits_data_T_4 : _iresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_7 = {_iresp_0_bits_data_T_6, iresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_3 = wb_ldst_forward_ld_addr_0[1]; // @[AMOALU.scala:42:29] wire [15:0] _iresp_0_bits_data_shifted_T_4 = _iresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _iresp_0_bits_data_shifted_T_5 = _iresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] iresp_0_bits_data_shifted_1 = _iresp_0_bits_data_shifted_T_3 ? _iresp_0_bits_data_shifted_T_4 : _iresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] iresp_0_bits_data_zeroed_1 = iresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _GEN_794 = size_1 == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_8 = _GEN_794; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_9 = _iresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_10 = iresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _iresp_0_bits_data_T_12 = {48{_iresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _iresp_0_bits_data_T_13 = _iresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _iresp_0_bits_data_T_14 = _iresp_0_bits_data_T_9 ? _iresp_0_bits_data_T_12 : _iresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_15 = {_iresp_0_bits_data_T_14, iresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _iresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _fresp_0_bits_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire _ldq_debug_wb_data_shifted_T_6 = wb_ldst_forward_ld_addr_0[0]; // @[AMOALU.scala:42:29] wire [7:0] _iresp_0_bits_data_shifted_T_7 = _iresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _iresp_0_bits_data_shifted_T_8 = _iresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] iresp_0_bits_data_shifted_2 = _iresp_0_bits_data_shifted_T_6 ? _iresp_0_bits_data_shifted_T_7 : _iresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] iresp_0_bits_data_zeroed_2 = iresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _GEN_795 = size_1 == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _iresp_0_bits_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:26] assign _fresp_0_bits_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:26] assign _ldq_debug_wb_data_T_16 = _GEN_795; // @[AMOALU.scala:45:26] wire _iresp_0_bits_data_T_17 = _iresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _iresp_0_bits_data_T_18 = iresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _iresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _iresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _iresp_0_bits_data_T_20 = {56{_iresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _iresp_0_bits_data_T_21 = _iresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _iresp_0_bits_data_T_22 = _iresp_0_bits_data_T_17 ? _iresp_0_bits_data_T_20 : _iresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _iresp_0_bits_data_T_23 = {_iresp_0_bits_data_T_22, iresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign iresp_0_bits_data = _GEN_681 ? resp_data : _iresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire [31:0] fresp_0_bits_data_shifted = _fresp_0_bits_data_shifted_T ? _fresp_0_bits_data_shifted_T_1 : _fresp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] fresp_0_bits_data_zeroed = fresp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_1 = _fresp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_2 = fresp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _fresp_0_bits_data_T_4 = {32{_fresp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _fresp_0_bits_data_T_6 = _fresp_0_bits_data_T_1 ? _fresp_0_bits_data_T_4 : _fresp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_7 = {_fresp_0_bits_data_T_6, fresp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _fresp_0_bits_data_shifted_T_4 = _fresp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _fresp_0_bits_data_shifted_T_5 = _fresp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] fresp_0_bits_data_shifted_1 = _fresp_0_bits_data_shifted_T_3 ? _fresp_0_bits_data_shifted_T_4 : _fresp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] fresp_0_bits_data_zeroed_1 = fresp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_9 = _fresp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_10 = fresp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _fresp_0_bits_data_T_12 = {48{_fresp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _fresp_0_bits_data_T_13 = _fresp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _fresp_0_bits_data_T_14 = _fresp_0_bits_data_T_9 ? _fresp_0_bits_data_T_12 : _fresp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_15 = {_fresp_0_bits_data_T_14, fresp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _fresp_0_bits_data_shifted_T_7 = _fresp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _fresp_0_bits_data_shifted_T_8 = _fresp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] fresp_0_bits_data_shifted_2 = _fresp_0_bits_data_shifted_T_6 ? _fresp_0_bits_data_shifted_T_7 : _fresp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] fresp_0_bits_data_zeroed_2 = fresp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _fresp_0_bits_data_T_17 = _fresp_0_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _fresp_0_bits_data_T_18 = fresp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _fresp_0_bits_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _fresp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _fresp_0_bits_data_T_20 = {56{_fresp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _fresp_0_bits_data_T_21 = _fresp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _fresp_0_bits_data_T_22 = _fresp_0_bits_data_T_17 ? _fresp_0_bits_data_T_20 : _fresp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _fresp_0_bits_data_T_23 = {_fresp_0_bits_data_T_22, fresp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign fresp_0_bits_data = _GEN_681 ? resp_data : _fresp_0_bits_data_T_23; // @[AMOALU.scala:45:16] wire _GEN_796 = _T_1678 & _GEN_626; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_797 = ~_T_1676 & _GEN_796; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_0 = _GEN_797 | (_GEN_654 ? _ldq_will_succeed_T : ~_GEN_102 & (_T_60 ? ~_GEN_77 & ldq_succeeded_0 : ~_GEN_28 & ldq_succeeded_0)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_798 = _T_1678 & _GEN_627; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_799 = ~_T_1676 & _GEN_798; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_1 = _GEN_799 | (_GEN_655 ? _ldq_will_succeed_T : ~_GEN_103 & (_T_60 ? ~_GEN_78 & ldq_succeeded_1 : ~_GEN_29 & ldq_succeeded_1)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_800 = _T_1678 & _GEN_628; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_801 = ~_T_1676 & _GEN_800; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_2 = _GEN_801 | (_GEN_656 ? _ldq_will_succeed_T : ~_GEN_104 & (_T_60 ? ~_GEN_79 & ldq_succeeded_2 : ~_GEN_30 & ldq_succeeded_2)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_802 = _T_1678 & _GEN_629; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_803 = ~_T_1676 & _GEN_802; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_3 = _GEN_803 | (_GEN_657 ? _ldq_will_succeed_T : ~_GEN_105 & (_T_60 ? ~_GEN_80 & ldq_succeeded_3 : ~_GEN_31 & ldq_succeeded_3)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_804 = _T_1678 & _GEN_630; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_805 = ~_T_1676 & _GEN_804; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_4 = _GEN_805 | (_GEN_658 ? _ldq_will_succeed_T : ~_GEN_106 & (_T_60 ? ~_GEN_81 & ldq_succeeded_4 : ~_GEN_32 & ldq_succeeded_4)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_806 = _T_1678 & _GEN_631; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_807 = ~_T_1676 & _GEN_806; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_5 = _GEN_807 | (_GEN_659 ? _ldq_will_succeed_T : ~_GEN_107 & (_T_60 ? ~_GEN_82 & ldq_succeeded_5 : ~_GEN_33 & ldq_succeeded_5)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_808 = _T_1678 & _GEN_632; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_809 = ~_T_1676 & _GEN_808; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_6 = _GEN_809 | (_GEN_660 ? _ldq_will_succeed_T : ~_GEN_108 & (_T_60 ? ~_GEN_83 & ldq_succeeded_6 : ~_GEN_34 & ldq_succeeded_6)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_810 = _T_1678 & _GEN_633; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_811 = ~_T_1676 & _GEN_810; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_7 = _GEN_811 | (_GEN_661 ? _ldq_will_succeed_T : ~_GEN_109 & (_T_60 ? ~_GEN_84 & ldq_succeeded_7 : ~_GEN_35 & ldq_succeeded_7)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_812 = _T_1678 & _GEN_634; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_813 = ~_T_1676 & _GEN_812; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_8 = _GEN_813 | (_GEN_662 ? _ldq_will_succeed_T : ~_GEN_110 & (_T_60 ? ~_GEN_85 & ldq_succeeded_8 : ~_GEN_36 & ldq_succeeded_8)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_814 = _T_1678 & _GEN_635; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_815 = ~_T_1676 & _GEN_814; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_9 = _GEN_815 | (_GEN_663 ? _ldq_will_succeed_T : ~_GEN_111 & (_T_60 ? ~_GEN_86 & ldq_succeeded_9 : ~_GEN_37 & ldq_succeeded_9)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_816 = _T_1678 & _GEN_636; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_817 = ~_T_1676 & _GEN_816; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_10 = _GEN_817 | (_GEN_664 ? _ldq_will_succeed_T : ~_GEN_112 & (_T_60 ? ~_GEN_87 & ldq_succeeded_10 : ~_GEN_38 & ldq_succeeded_10)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_818 = _T_1678 & _GEN_637; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_819 = ~_T_1676 & _GEN_818; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_11 = _GEN_819 | (_GEN_665 ? _ldq_will_succeed_T : ~_GEN_113 & (_T_60 ? ~_GEN_88 & ldq_succeeded_11 : ~_GEN_39 & ldq_succeeded_11)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_820 = _T_1678 & _GEN_638; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_821 = ~_T_1676 & _GEN_820; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_12 = _GEN_821 | (_GEN_666 ? _ldq_will_succeed_T : ~_GEN_114 & (_T_60 ? ~_GEN_89 & ldq_succeeded_12 : ~_GEN_40 & ldq_succeeded_12)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_822 = _T_1678 & _GEN_639; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_823 = ~_T_1676 & _GEN_822; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_13 = _GEN_823 | (_GEN_667 ? _ldq_will_succeed_T : ~_GEN_115 & (_T_60 ? ~_GEN_90 & ldq_succeeded_13 : ~_GEN_41 & ldq_succeeded_13)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_824 = _T_1678 & _GEN_640; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_825 = ~_T_1676 & _GEN_824; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_14 = _GEN_825 | (_GEN_668 ? _ldq_will_succeed_T : ~_GEN_116 & (_T_60 ? ~_GEN_91 & ldq_succeeded_14 : ~_GEN_42 & ldq_succeeded_14)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_826 = _T_1678 & _GEN_641; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_827 = ~_T_1676 & _GEN_826; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_15 = _GEN_827 | (_GEN_669 ? _ldq_will_succeed_T : ~_GEN_117 & (_T_60 ? ~_GEN_92 & ldq_succeeded_15 : ~_GEN_43 & ldq_succeeded_15)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_828 = _T_1678 & _GEN_642; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_829 = ~_T_1676 & _GEN_828; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_16 = _GEN_829 | (_GEN_670 ? _ldq_will_succeed_T : ~_GEN_118 & (_T_60 ? ~_GEN_93 & ldq_succeeded_16 : ~_GEN_44 & ldq_succeeded_16)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_830 = _T_1678 & _GEN_643; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_831 = ~_T_1676 & _GEN_830; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_17 = _GEN_831 | (_GEN_671 ? _ldq_will_succeed_T : ~_GEN_119 & (_T_60 ? ~_GEN_94 & ldq_succeeded_17 : ~_GEN_45 & ldq_succeeded_17)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_832 = _T_1678 & _GEN_644; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_833 = ~_T_1676 & _GEN_832; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_18 = _GEN_833 | (_GEN_672 ? _ldq_will_succeed_T : ~_GEN_120 & (_T_60 ? ~_GEN_95 & ldq_succeeded_18 : ~_GEN_46 & ldq_succeeded_18)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_834 = _T_1678 & _GEN_645; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_835 = ~_T_1676 & _GEN_834; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_19 = _GEN_835 | (_GEN_673 ? _ldq_will_succeed_T : ~_GEN_121 & (_T_60 ? ~_GEN_96 & ldq_succeeded_19 : ~_GEN_47 & ldq_succeeded_19)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_836 = _T_1678 & _GEN_646; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_837 = ~_T_1676 & _GEN_836; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_20 = _GEN_837 | (_GEN_674 ? _ldq_will_succeed_T : ~_GEN_122 & (_T_60 ? ~_GEN_97 & ldq_succeeded_20 : ~_GEN_48 & ldq_succeeded_20)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_838 = _T_1678 & _GEN_647; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_839 = ~_T_1676 & _GEN_838; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_21 = _GEN_839 | (_GEN_675 ? _ldq_will_succeed_T : ~_GEN_123 & (_T_60 ? ~_GEN_98 & ldq_succeeded_21 : ~_GEN_49 & ldq_succeeded_21)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_840 = _T_1678 & _GEN_648; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_841 = ~_T_1676 & _GEN_840; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_22 = _GEN_841 | (_GEN_676 ? _ldq_will_succeed_T : ~_GEN_124 & (_T_60 ? ~_GEN_99 & ldq_succeeded_22 : ~_GEN_50 & ldq_succeeded_22)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire _GEN_842 = _T_1678 & _GEN_649; // @[lsu.scala:1298:53, :1539:83, :1598:38, :1599:5, :1625:34] wire _GEN_843 = ~_T_1676 & _GEN_842; // @[lsu.scala:1539:83, :1594:30, :1595:5, :1599:5, :1625:34] assign ldq_will_succeed_23 = _GEN_843 | (_GEN_677 ? _ldq_will_succeed_T : ~_GEN_125 & (_T_60 ? ~_GEN_100 & ldq_succeeded_23 : ~_GEN_51 & ldq_succeeded_23)); // @[lsu.scala:218:36, :220:36, :224:36, :325:44, :394:{29,59}, :396:42, :399:42, :401:42, :1539:83, :1540:32, :1560:{36,54}, :1595:5, :1599:5] wire [31:0] ldq_debug_wb_data_shifted = _ldq_debug_wb_data_shifted_T ? _ldq_debug_wb_data_shifted_T_1 : _ldq_debug_wb_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] ldq_debug_wb_data_zeroed = ldq_debug_wb_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_1 = _ldq_debug_wb_data_T; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_2 = ldq_debug_wb_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_3 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _ldq_debug_wb_data_T_4 = {32{_ldq_debug_wb_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _ldq_debug_wb_data_T_6 = _ldq_debug_wb_data_T_1 ? _ldq_debug_wb_data_T_4 : _ldq_debug_wb_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_7 = {_ldq_debug_wb_data_T_6, ldq_debug_wb_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [15:0] _ldq_debug_wb_data_shifted_T_4 = _ldq_debug_wb_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _ldq_debug_wb_data_shifted_T_5 = _ldq_debug_wb_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] ldq_debug_wb_data_shifted_1 = _ldq_debug_wb_data_shifted_T_3 ? _ldq_debug_wb_data_shifted_T_4 : _ldq_debug_wb_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] ldq_debug_wb_data_zeroed_1 = ldq_debug_wb_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_9 = _ldq_debug_wb_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_10 = ldq_debug_wb_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_11 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _ldq_debug_wb_data_T_12 = {48{_ldq_debug_wb_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _ldq_debug_wb_data_T_13 = _ldq_debug_wb_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _ldq_debug_wb_data_T_14 = _ldq_debug_wb_data_T_9 ? _ldq_debug_wb_data_T_12 : _ldq_debug_wb_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_15 = {_ldq_debug_wb_data_T_14, ldq_debug_wb_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire [7:0] _ldq_debug_wb_data_shifted_T_7 = _ldq_debug_wb_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _ldq_debug_wb_data_shifted_T_8 = _ldq_debug_wb_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] ldq_debug_wb_data_shifted_2 = _ldq_debug_wb_data_shifted_T_6 ? _ldq_debug_wb_data_shifted_T_7 : _ldq_debug_wb_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] ldq_debug_wb_data_zeroed_2 = ldq_debug_wb_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _ldq_debug_wb_data_T_17 = _ldq_debug_wb_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _ldq_debug_wb_data_T_18 = ldq_debug_wb_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _ldq_debug_wb_data_T_19 = wb_ldst_forward_e_0_uop_mem_signed & _ldq_debug_wb_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _ldq_debug_wb_data_T_20 = {56{_ldq_debug_wb_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _ldq_debug_wb_data_T_21 = _ldq_debug_wb_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _ldq_debug_wb_data_T_22 = _ldq_debug_wb_data_T_17 ? _ldq_debug_wb_data_T_20 : _ldq_debug_wb_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _ldq_debug_wb_data_T_23 = {_ldq_debug_wb_data_T_22, ldq_debug_wb_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _slow_wakeups_0_out_valid_T_4; // @[util.scala:116:31] wire [15:0] _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [15:0] slow_wakeups_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire slow_wakeups_0_out_valid; // @[util.scala:114:23] wire [15:0] _slow_wakeups_0_out_bits_uop_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] assign _slow_wakeups_0_out_bits_uop_br_mask_T_1 = wb_slow_wakeups_0_bits_uop_br_mask & _slow_wakeups_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign slow_wakeups_0_out_bits_uop_br_mask = _slow_wakeups_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [15:0] _slow_wakeups_0_out_valid_T = io_core_brupdate_b1_mispredict_mask_0 & wb_slow_wakeups_0_bits_uop_br_mask; // @[util.scala:126:51] wire _slow_wakeups_0_out_valid_T_1 = |_slow_wakeups_0_out_valid_T; // @[util.scala:126:{51,59}] wire _slow_wakeups_0_out_valid_T_2 = _slow_wakeups_0_out_valid_T_1 | io_core_exception_0; // @[util.scala:61:61, :126:59] wire _slow_wakeups_0_out_valid_T_3 = ~_slow_wakeups_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _slow_wakeups_0_out_valid_T_4 = wb_slow_wakeups_0_valid & _slow_wakeups_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign slow_wakeups_0_out_valid = _slow_wakeups_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg slow_wakeups_0_REG_valid; // @[lsu.scala:1647:79] assign slow_wakeups_0_valid = slow_wakeups_0_REG_valid; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_inst = slow_wakeups_0_REG_bits_uop_inst; // @[lsu.scala:1495:26, :1647:79] reg [31:0] slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_inst = slow_wakeups_0_REG_bits_uop_debug_inst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rvc = slow_wakeups_0_REG_bits_uop_is_rvc; // @[lsu.scala:1495:26, :1647:79] reg [39:0] slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_pc = slow_wakeups_0_REG_bits_uop_debug_pc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_0 = slow_wakeups_0_REG_bits_uop_iq_type_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_1 = slow_wakeups_0_REG_bits_uop_iq_type_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_2 = slow_wakeups_0_REG_bits_uop_iq_type_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iq_type_3 = slow_wakeups_0_REG_bits_uop_iq_type_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_0 = slow_wakeups_0_REG_bits_uop_fu_code_0; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_1 = slow_wakeups_0_REG_bits_uop_fu_code_1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_2 = slow_wakeups_0_REG_bits_uop_fu_code_2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_3 = slow_wakeups_0_REG_bits_uop_fu_code_3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_4 = slow_wakeups_0_REG_bits_uop_fu_code_4; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_5 = slow_wakeups_0_REG_bits_uop_fu_code_5; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_6 = slow_wakeups_0_REG_bits_uop_fu_code_6; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_7 = slow_wakeups_0_REG_bits_uop_fu_code_7; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_8 = slow_wakeups_0_REG_bits_uop_fu_code_8; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fu_code_9 = slow_wakeups_0_REG_bits_uop_fu_code_9; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued = slow_wakeups_0_REG_bits_uop_iw_issued; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_agen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_agen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_issued_partial_dgen = slow_wakeups_0_REG_bits_uop_iw_issued_partial_dgen; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p1_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_speculative_child = slow_wakeups_0_REG_bits_uop_iw_p2_speculative_child; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p1_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p1_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p2_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p2_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_iw_p3_bypass_hint = slow_wakeups_0_REG_bits_uop_iw_p3_bypass_hint; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dis_col_sel = slow_wakeups_0_REG_bits_uop_dis_col_sel; // @[lsu.scala:1495:26, :1647:79] reg [15:0] slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_mask = slow_wakeups_0_REG_bits_uop_br_mask; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_tag = slow_wakeups_0_REG_bits_uop_br_tag; // @[lsu.scala:1495:26, :1647:79] reg [3:0] slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_br_type = slow_wakeups_0_REG_bits_uop_br_type; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfb = slow_wakeups_0_REG_bits_uop_is_sfb; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fence = slow_wakeups_0_REG_bits_uop_is_fence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_fencei = slow_wakeups_0_REG_bits_uop_is_fencei; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sfence = slow_wakeups_0_REG_bits_uop_is_sfence; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_amo = slow_wakeups_0_REG_bits_uop_is_amo; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_eret = slow_wakeups_0_REG_bits_uop_is_eret; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_sys_pc2epc = slow_wakeups_0_REG_bits_uop_is_sys_pc2epc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_rocc = slow_wakeups_0_REG_bits_uop_is_rocc; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_mov = slow_wakeups_0_REG_bits_uop_is_mov; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ftq_idx = slow_wakeups_0_REG_bits_uop_ftq_idx; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_edge_inst = slow_wakeups_0_REG_bits_uop_edge_inst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pc_lob = slow_wakeups_0_REG_bits_uop_pc_lob; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_taken = slow_wakeups_0_REG_bits_uop_taken; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_rename = slow_wakeups_0_REG_bits_uop_imm_rename; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_sel = slow_wakeups_0_REG_bits_uop_imm_sel; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pimm = slow_wakeups_0_REG_bits_uop_pimm; // @[lsu.scala:1495:26, :1647:79] reg [19:0] slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_imm_packed = slow_wakeups_0_REG_bits_uop_imm_packed; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op1_sel = slow_wakeups_0_REG_bits_uop_op1_sel; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_op2_sel = slow_wakeups_0_REG_bits_uop_op2_sel; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ldst = slow_wakeups_0_REG_bits_uop_fp_ctrl_ldst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wen = slow_wakeups_0_REG_bits_uop_fp_ctrl_wen; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren1 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren1; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren2 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren2; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_ren3 = slow_wakeups_0_REG_bits_uop_fp_ctrl_ren3; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap12 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap12; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_swap23 = slow_wakeups_0_REG_bits_uop_fp_ctrl_swap23; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagIn = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagIn; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_typeTagOut = slow_wakeups_0_REG_bits_uop_fp_ctrl_typeTagOut; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fromint = slow_wakeups_0_REG_bits_uop_fp_ctrl_fromint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_toint = slow_wakeups_0_REG_bits_uop_fp_ctrl_toint; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fastpipe = slow_wakeups_0_REG_bits_uop_fp_ctrl_fastpipe; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_fma = slow_wakeups_0_REG_bits_uop_fp_ctrl_fma; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_div = slow_wakeups_0_REG_bits_uop_fp_ctrl_div; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_sqrt = slow_wakeups_0_REG_bits_uop_fp_ctrl_sqrt; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_wflags = slow_wakeups_0_REG_bits_uop_fp_ctrl_wflags; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_ctrl_vec = slow_wakeups_0_REG_bits_uop_fp_ctrl_vec; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rob_idx = slow_wakeups_0_REG_bits_uop_rob_idx; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldq_idx = slow_wakeups_0_REG_bits_uop_ldq_idx; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stq_idx = slow_wakeups_0_REG_bits_uop_stq_idx; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_rxq_idx = slow_wakeups_0_REG_bits_uop_rxq_idx; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_pdst = slow_wakeups_0_REG_bits_uop_pdst; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1 = slow_wakeups_0_REG_bits_uop_prs1; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2 = slow_wakeups_0_REG_bits_uop_prs2; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3 = slow_wakeups_0_REG_bits_uop_prs3; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred = slow_wakeups_0_REG_bits_uop_ppred; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs1_busy = slow_wakeups_0_REG_bits_uop_prs1_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs2_busy = slow_wakeups_0_REG_bits_uop_prs2_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_prs3_busy = slow_wakeups_0_REG_bits_uop_prs3_busy; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ppred_busy = slow_wakeups_0_REG_bits_uop_ppred_busy; // @[lsu.scala:1495:26, :1647:79] reg [6:0] slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_stale_pdst = slow_wakeups_0_REG_bits_uop_stale_pdst; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exception = slow_wakeups_0_REG_bits_uop_exception; // @[lsu.scala:1495:26, :1647:79] reg [63:0] slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_exc_cause = slow_wakeups_0_REG_bits_uop_exc_cause; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_cmd = slow_wakeups_0_REG_bits_uop_mem_cmd; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_size = slow_wakeups_0_REG_bits_uop_mem_size; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_mem_signed = slow_wakeups_0_REG_bits_uop_mem_signed; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_ldq = slow_wakeups_0_REG_bits_uop_uses_ldq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_uses_stq = slow_wakeups_0_REG_bits_uop_uses_stq; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_is_unique = slow_wakeups_0_REG_bits_uop_is_unique; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_flush_on_commit = slow_wakeups_0_REG_bits_uop_flush_on_commit; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_csr_cmd = slow_wakeups_0_REG_bits_uop_csr_cmd; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst_is_rs1 = slow_wakeups_0_REG_bits_uop_ldst_is_rs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_ldst = slow_wakeups_0_REG_bits_uop_ldst; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1 = slow_wakeups_0_REG_bits_uop_lrs1; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2 = slow_wakeups_0_REG_bits_uop_lrs2; // @[lsu.scala:1495:26, :1647:79] reg [5:0] slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs3 = slow_wakeups_0_REG_bits_uop_lrs3; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_dst_rtype = slow_wakeups_0_REG_bits_uop_dst_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs1_rtype = slow_wakeups_0_REG_bits_uop_lrs1_rtype; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_lrs2_rtype = slow_wakeups_0_REG_bits_uop_lrs2_rtype; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_frs3_en = slow_wakeups_0_REG_bits_uop_frs3_en; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_dw = slow_wakeups_0_REG_bits_uop_fcn_dw; // @[lsu.scala:1495:26, :1647:79] reg [4:0] slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fcn_op = slow_wakeups_0_REG_bits_uop_fcn_op; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_val = slow_wakeups_0_REG_bits_uop_fp_val; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_rm = slow_wakeups_0_REG_bits_uop_fp_rm; // @[lsu.scala:1495:26, :1647:79] reg [1:0] slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_fp_typ = slow_wakeups_0_REG_bits_uop_fp_typ; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_pf_if = slow_wakeups_0_REG_bits_uop_xcpt_pf_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ae_if = slow_wakeups_0_REG_bits_uop_xcpt_ae_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_xcpt_ma_if = slow_wakeups_0_REG_bits_uop_xcpt_ma_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_debug_if = slow_wakeups_0_REG_bits_uop_bp_debug_if; // @[lsu.scala:1495:26, :1647:79] reg slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_bp_xcpt_if = slow_wakeups_0_REG_bits_uop_bp_xcpt_if; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_fsrc = slow_wakeups_0_REG_bits_uop_debug_fsrc; // @[lsu.scala:1495:26, :1647:79] reg [2:0] slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1647:79] assign slow_wakeups_0_bits_uop_debug_tsrc = slow_wakeups_0_REG_bits_uop_debug_tsrc; // @[lsu.scala:1495:26, :1647:79] wire [15:0] _stq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_0_br_mask_T_1 = uop_1_br_mask & _stq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_1_br_mask_T_1 = uop_2_br_mask & _stq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_2_br_mask_T_1 = uop_3_br_mask & _stq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_3_br_mask_T_1 = uop_4_br_mask & _stq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_4_br_mask_T_1 = uop_5_br_mask & _stq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_5_br_mask_T_1 = uop_6_br_mask & _stq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_6_br_mask_T_1 = uop_7_br_mask & _stq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_7_br_mask_T_1 = uop_8_br_mask & _stq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_8_br_mask_T_1 = uop_9_br_mask & _stq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_9_br_mask_T_1 = uop_10_br_mask & _stq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_10_br_mask_T_1 = uop_11_br_mask & _stq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_11_br_mask_T_1 = uop_12_br_mask & _stq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_12_br_mask_T_1 = uop_13_br_mask & _stq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_13_br_mask_T_1 = uop_14_br_mask & _stq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_14_br_mask_T_1 = uop_15_br_mask & _stq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_15_br_mask_T_1 = uop_16_br_mask & _stq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_16_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_16_br_mask_T_1 = uop_17_br_mask & _stq_uop_16_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_17_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_17_br_mask_T_1 = uop_18_br_mask & _stq_uop_17_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_18_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_18_br_mask_T_1 = uop_19_br_mask & _stq_uop_18_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_19_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_19_br_mask_T_1 = uop_20_br_mask & _stq_uop_19_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_20_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_20_br_mask_T_1 = uop_21_br_mask & _stq_uop_20_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_21_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_21_br_mask_T_1 = uop_22_br_mask & _stq_uop_21_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_22_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_22_br_mask_T_1 = uop_23_br_mask & _stq_uop_22_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _stq_uop_23_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _stq_uop_23_br_mask_T_1 = uop_24_br_mask & _stq_uop_23_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_0_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_0_br_mask_T_1 = uop_25_br_mask & _ldq_uop_0_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_1_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_1_br_mask_T_1 = uop_26_br_mask & _ldq_uop_1_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_2_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_2_br_mask_T_1 = uop_27_br_mask & _ldq_uop_2_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_3_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_3_br_mask_T_1 = uop_28_br_mask & _ldq_uop_3_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_4_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_4_br_mask_T_1 = uop_29_br_mask & _ldq_uop_4_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_5_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_5_br_mask_T_1 = uop_30_br_mask & _ldq_uop_5_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_6_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_6_br_mask_T_1 = uop_31_br_mask & _ldq_uop_6_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_7_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_7_br_mask_T_1 = uop_32_br_mask & _ldq_uop_7_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_8_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_8_br_mask_T_1 = uop_33_br_mask & _ldq_uop_8_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_9_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_9_br_mask_T_1 = uop_34_br_mask & _ldq_uop_9_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_10_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_10_br_mask_T_1 = uop_35_br_mask & _ldq_uop_10_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_11_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_11_br_mask_T_1 = uop_36_br_mask & _ldq_uop_11_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_12_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_12_br_mask_T_1 = uop_37_br_mask & _ldq_uop_12_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_13_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_13_br_mask_T_1 = uop_38_br_mask & _ldq_uop_13_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_14_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_14_br_mask_T_1 = uop_39_br_mask & _ldq_uop_14_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_15_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_15_br_mask_T_1 = uop_40_br_mask & _ldq_uop_15_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_16_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_16_br_mask_T_1 = uop_41_br_mask & _ldq_uop_16_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_17_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_17_br_mask_T_1 = uop_42_br_mask & _ldq_uop_17_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_18_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_18_br_mask_T_1 = uop_43_br_mask & _ldq_uop_18_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_19_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_19_br_mask_T_1 = uop_44_br_mask & _ldq_uop_19_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_20_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_20_br_mask_T_1 = uop_45_br_mask & _ldq_uop_20_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_21_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_21_br_mask_T_1 = uop_46_br_mask & _ldq_uop_21_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_22_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_22_br_mask_T_1 = uop_47_br_mask & _ldq_uop_22_br_mask_T; // @[util.scala:97:{21,23}] wire [15:0] _ldq_uop_23_br_mask_T = ~io_core_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23] wire [15:0] _ldq_uop_23_br_mask_T_1 = uop_48_br_mask & _ldq_uop_23_br_mask_T; // @[util.scala:97:{21,23}] wire commit_store = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load = io_core_commit_valids_0_0 & io_core_commit_uops_0_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_24_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_24_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_24_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_24_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_24_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_24_debug_inst; // @[lsu.scala:1728:25] wire l_uop_24_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_24_debug_pc; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_24_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_24_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_24_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_24_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_24_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_24_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_24_br_type; // @[lsu.scala:1728:25] wire l_uop_24_is_sfb; // @[lsu.scala:1728:25] wire l_uop_24_is_fence; // @[lsu.scala:1728:25] wire l_uop_24_is_fencei; // @[lsu.scala:1728:25] wire l_uop_24_is_sfence; // @[lsu.scala:1728:25] wire l_uop_24_is_amo; // @[lsu.scala:1728:25] wire l_uop_24_is_eret; // @[lsu.scala:1728:25] wire l_uop_24_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_24_is_rocc; // @[lsu.scala:1728:25] wire l_uop_24_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_24_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_pc_lob; // @[lsu.scala:1728:25] wire l_uop_24_taken; // @[lsu.scala:1728:25] wire l_uop_24_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_24_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_ppred; // @[lsu.scala:1728:25] wire l_uop_24_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_24_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_24_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_24_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_24_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_24_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_24_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_mem_size; // @[lsu.scala:1728:25] wire l_uop_24_mem_signed; // @[lsu.scala:1728:25] wire l_uop_24_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_24_uses_stq; // @[lsu.scala:1728:25] wire l_uop_24_is_unique; // @[lsu.scala:1728:25] wire l_uop_24_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_24_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_24_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_24_frs3_en; // @[lsu.scala:1728:25] wire l_uop_24_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_24_fcn_op; // @[lsu.scala:1728:25] wire l_uop_24_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_24_fp_typ; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_24_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_24_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_24_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_24_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_24_inst = _GEN_127[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_inst = _GEN_128[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_rvc = _GEN_129[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_pc = _GEN_130[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_0 = _GEN_131[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_1 = _GEN_132[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_2 = _GEN_133[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iq_type_3 = _GEN_134[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_0 = _GEN_135[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_1 = _GEN_136[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_2 = _GEN_137[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_3 = _GEN_138[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_4 = _GEN_139[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_5 = _GEN_140[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_6 = _GEN_141[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_7 = _GEN_142[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_8 = _GEN_143[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fu_code_9 = _GEN_144[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued = _GEN_145[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued_partial_agen = _GEN_146[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_issued_partial_dgen = _GEN_147[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p1_speculative_child = _GEN_148[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p2_speculative_child = _GEN_149[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p1_bypass_hint = _GEN_150[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p2_bypass_hint = _GEN_151[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_iw_p3_bypass_hint = _GEN_152[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_dis_col_sel = _GEN_153[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_mask = _GEN_154[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_tag = _GEN_155[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_br_type = _GEN_156[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sfb = _GEN_157[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_fence = _GEN_158[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_fencei = _GEN_159[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sfence = _GEN_160[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_amo = _GEN_161[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_eret = _GEN_162[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_sys_pc2epc = _GEN_163[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_rocc = _GEN_164[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_mov = _GEN_165[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ftq_idx = _GEN_166[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_edge_inst = _GEN_167[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pc_lob = _GEN_168[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_taken = _GEN_169[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_rename = _GEN_170[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_sel = _GEN_171[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pimm = _GEN_172[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_imm_packed = _GEN_173[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_op1_sel = _GEN_174[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_op2_sel = _GEN_175[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ldst = _GEN_176[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_wen = _GEN_177[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren1 = _GEN_178[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren2 = _GEN_179[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_ren3 = _GEN_180[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_swap12 = _GEN_181[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_swap23 = _GEN_182[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_typeTagIn = _GEN_183[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_typeTagOut = _GEN_184[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fromint = _GEN_185[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_toint = _GEN_186[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fastpipe = _GEN_187[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_fma = _GEN_188[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_div = _GEN_189[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_sqrt = _GEN_190[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_wflags = _GEN_191[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_ctrl_vec = _GEN_192[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_rob_idx = _GEN_193[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldq_idx = _GEN_194[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_stq_idx = _GEN_195[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_rxq_idx = _GEN_196[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_pdst = _GEN_197[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs1 = _GEN_198[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs2 = _GEN_199[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs3 = _GEN_200[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ppred = _GEN_201[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs1_busy = _GEN_202[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs2_busy = _GEN_203[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_prs3_busy = _GEN_204[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ppred_busy = _GEN_205[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_stale_pdst = _GEN_206[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_exception = _GEN_207[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_exc_cause = _GEN_208[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_cmd = _GEN_209[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_size = _GEN_210[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_mem_signed = _GEN_211[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_uses_ldq = _GEN_212[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_uses_stq = _GEN_213[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_is_unique = _GEN_214[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_flush_on_commit = _GEN_215[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_csr_cmd = _GEN_216[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldst_is_rs1 = _GEN_217[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_ldst = _GEN_218[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs1 = _GEN_219[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs2 = _GEN_220[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs3 = _GEN_221[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_dst_rtype = _GEN_222[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs1_rtype = _GEN_223[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_lrs2_rtype = _GEN_224[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_frs3_en = _GEN_225[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fcn_dw = _GEN_226[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fcn_op = _GEN_227[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_val = _GEN_228[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_rm = _GEN_229[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_fp_typ = _GEN_230[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_pf_if = _GEN_231[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_ae_if = _GEN_232[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_xcpt_ma_if = _GEN_233[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_bp_debug_if = _GEN_234[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_bp_xcpt_if = _GEN_235[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_fsrc = _GEN_236[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] assign l_uop_24_debug_tsrc = _GEN_237[ldq_head]; // @[lsu.scala:235:32, :278:29, :1728:25] wire s_uop_27_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_27_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_27_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_27_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_27_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_27_debug_inst; // @[lsu.scala:1729:25] wire s_uop_27_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_27_debug_pc; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_27_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_27_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_27_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_27_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_27_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_27_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_27_br_type; // @[lsu.scala:1729:25] wire s_uop_27_is_sfb; // @[lsu.scala:1729:25] wire s_uop_27_is_fence; // @[lsu.scala:1729:25] wire s_uop_27_is_fencei; // @[lsu.scala:1729:25] wire s_uop_27_is_sfence; // @[lsu.scala:1729:25] wire s_uop_27_is_amo; // @[lsu.scala:1729:25] wire s_uop_27_is_eret; // @[lsu.scala:1729:25] wire s_uop_27_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_27_is_rocc; // @[lsu.scala:1729:25] wire s_uop_27_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_27_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_pc_lob; // @[lsu.scala:1729:25] wire s_uop_27_taken; // @[lsu.scala:1729:25] wire s_uop_27_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_27_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_ppred; // @[lsu.scala:1729:25] wire s_uop_27_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_27_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_27_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_27_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_27_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_27_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_27_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_mem_size; // @[lsu.scala:1729:25] wire s_uop_27_mem_signed; // @[lsu.scala:1729:25] wire s_uop_27_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_27_uses_stq; // @[lsu.scala:1729:25] wire s_uop_27_is_unique; // @[lsu.scala:1729:25] wire s_uop_27_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_27_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_27_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_27_frs3_en; // @[lsu.scala:1729:25] wire s_uop_27_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_27_fcn_op; // @[lsu.scala:1729:25] wire s_uop_27_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_27_fp_typ; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_27_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_27_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_27_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_27_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_27_inst = _GEN_251[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_inst = _GEN_252[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_rvc = _GEN_253[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_pc = _GEN_254[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_0 = _GEN_255[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_1 = _GEN_256[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_2 = _GEN_257[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iq_type_3 = _GEN_258[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_0 = _GEN_259[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_1 = _GEN_260[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_2 = _GEN_261[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_3 = _GEN_262[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_4 = _GEN_263[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_5 = _GEN_264[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_6 = _GEN_265[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_7 = _GEN_266[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_8 = _GEN_267[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fu_code_9 = _GEN_268[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued = _GEN_269[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued_partial_agen = _GEN_270[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_issued_partial_dgen = _GEN_271[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p1_speculative_child = _GEN_272[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p2_speculative_child = _GEN_273[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p1_bypass_hint = _GEN_274[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p2_bypass_hint = _GEN_275[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_iw_p3_bypass_hint = _GEN_276[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_dis_col_sel = _GEN_277[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_mask = _GEN_278[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_tag = _GEN_279[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_br_type = _GEN_280[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sfb = _GEN_281[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_fence = _GEN_282[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_fencei = _GEN_283[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sfence = _GEN_284[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_amo = _GEN_285[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_eret = _GEN_286[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_sys_pc2epc = _GEN_287[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_rocc = _GEN_288[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_mov = _GEN_289[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ftq_idx = _GEN_290[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_edge_inst = _GEN_291[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pc_lob = _GEN_292[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_taken = _GEN_293[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_rename = _GEN_294[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_sel = _GEN_295[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pimm = _GEN_296[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_imm_packed = _GEN_297[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_op1_sel = _GEN_298[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_op2_sel = _GEN_299[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ldst = _GEN_300[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_wen = _GEN_301[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren1 = _GEN_302[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren2 = _GEN_303[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_ren3 = _GEN_304[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_swap12 = _GEN_305[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_swap23 = _GEN_306[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_typeTagIn = _GEN_307[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_typeTagOut = _GEN_308[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fromint = _GEN_309[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_toint = _GEN_310[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fastpipe = _GEN_311[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_fma = _GEN_312[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_div = _GEN_313[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_sqrt = _GEN_314[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_wflags = _GEN_315[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_ctrl_vec = _GEN_316[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_rob_idx = _GEN_317[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldq_idx = _GEN_318[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_stq_idx = _GEN_319[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_rxq_idx = _GEN_320[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_pdst = _GEN_321[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs1 = _GEN_322[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs2 = _GEN_323[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs3 = _GEN_324[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ppred = _GEN_325[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs1_busy = _GEN_326[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs2_busy = _GEN_327[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_prs3_busy = _GEN_328[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ppred_busy = _GEN_329[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_stale_pdst = _GEN_330[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_exception = _GEN_331[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_exc_cause = _GEN_332[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_cmd = _GEN_333[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_size = _GEN_334[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_mem_signed = _GEN_335[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_uses_ldq = _GEN_336[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_uses_stq = _GEN_337[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_is_unique = _GEN_338[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_flush_on_commit = _GEN_339[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_csr_cmd = _GEN_340[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldst_is_rs1 = _GEN_341[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_ldst = _GEN_342[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs1 = _GEN_343[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs2 = _GEN_344[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs3 = _GEN_345[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_dst_rtype = _GEN_346[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs1_rtype = _GEN_347[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_lrs2_rtype = _GEN_348[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_frs3_en = _GEN_349[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fcn_dw = _GEN_350[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fcn_op = _GEN_351[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_val = _GEN_352[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_rm = _GEN_353[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_fp_typ = _GEN_354[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_pf_if = _GEN_355[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_ae_if = _GEN_356[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_xcpt_ma_if = _GEN_357[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_bp_debug_if = _GEN_358[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_bp_xcpt_if = _GEN_359[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_fsrc = _GEN_360[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] assign s_uop_27_debug_tsrc = _GEN_361[stq_commit_head]; // @[lsu.scala:264:32, :282:29, :1729:25] wire wrap_9 = stq_commit_head == 5'h17; // @[util.scala:213:25] wire _GEN_844 = ~commit_store & commit_load; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_845 = _GEN_844 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire _GEN_846 = _GEN_25[ldq_head]; // @[lsu.scala:278:29, :387:15, :1736:14] wire wrap_10 = ldq_head == 5'h17; // @[util.scala:213:25] wire [4:0] _T_2078 = wrap_9 ? 5'h0 : stq_commit_head + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2079 = commit_store ? _T_2078 : stq_commit_head; // @[util.scala:214:10] wire [4:0] _T_2082 = wrap_10 ? 5'h0 : ldq_head + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2083 = commit_load ? _T_2082 : ldq_head; // @[util.scala:214:10] wire commit_store_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_1 = io_core_commit_valids_1_0 & io_core_commit_uops_1_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_25_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_25_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_25_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_25_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_25_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_25_debug_inst; // @[lsu.scala:1728:25] wire l_uop_25_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_25_debug_pc; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_25_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_25_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_25_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_25_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_25_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_25_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_25_br_type; // @[lsu.scala:1728:25] wire l_uop_25_is_sfb; // @[lsu.scala:1728:25] wire l_uop_25_is_fence; // @[lsu.scala:1728:25] wire l_uop_25_is_fencei; // @[lsu.scala:1728:25] wire l_uop_25_is_sfence; // @[lsu.scala:1728:25] wire l_uop_25_is_amo; // @[lsu.scala:1728:25] wire l_uop_25_is_eret; // @[lsu.scala:1728:25] wire l_uop_25_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_25_is_rocc; // @[lsu.scala:1728:25] wire l_uop_25_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_25_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_pc_lob; // @[lsu.scala:1728:25] wire l_uop_25_taken; // @[lsu.scala:1728:25] wire l_uop_25_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_25_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_ppred; // @[lsu.scala:1728:25] wire l_uop_25_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_25_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_25_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_25_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_25_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_25_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_25_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_mem_size; // @[lsu.scala:1728:25] wire l_uop_25_mem_signed; // @[lsu.scala:1728:25] wire l_uop_25_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_25_uses_stq; // @[lsu.scala:1728:25] wire l_uop_25_is_unique; // @[lsu.scala:1728:25] wire l_uop_25_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_25_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_25_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_25_frs3_en; // @[lsu.scala:1728:25] wire l_uop_25_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_25_fcn_op; // @[lsu.scala:1728:25] wire l_uop_25_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_25_fp_typ; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_25_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_25_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_25_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_25_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_25_inst = _GEN_127[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_inst = _GEN_128[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_rvc = _GEN_129[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_pc = _GEN_130[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_0 = _GEN_131[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_1 = _GEN_132[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_2 = _GEN_133[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iq_type_3 = _GEN_134[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_0 = _GEN_135[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_1 = _GEN_136[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_2 = _GEN_137[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_3 = _GEN_138[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_4 = _GEN_139[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_5 = _GEN_140[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_6 = _GEN_141[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_7 = _GEN_142[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_8 = _GEN_143[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fu_code_9 = _GEN_144[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued = _GEN_145[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued_partial_agen = _GEN_146[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_issued_partial_dgen = _GEN_147[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p1_speculative_child = _GEN_148[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p2_speculative_child = _GEN_149[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p1_bypass_hint = _GEN_150[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p2_bypass_hint = _GEN_151[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_iw_p3_bypass_hint = _GEN_152[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_dis_col_sel = _GEN_153[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_mask = _GEN_154[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_tag = _GEN_155[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_br_type = _GEN_156[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sfb = _GEN_157[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_fence = _GEN_158[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_fencei = _GEN_159[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sfence = _GEN_160[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_amo = _GEN_161[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_eret = _GEN_162[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_sys_pc2epc = _GEN_163[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_rocc = _GEN_164[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_mov = _GEN_165[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ftq_idx = _GEN_166[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_edge_inst = _GEN_167[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pc_lob = _GEN_168[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_taken = _GEN_169[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_rename = _GEN_170[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_sel = _GEN_171[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pimm = _GEN_172[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_imm_packed = _GEN_173[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_op1_sel = _GEN_174[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_op2_sel = _GEN_175[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ldst = _GEN_176[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_wen = _GEN_177[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren1 = _GEN_178[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren2 = _GEN_179[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_ren3 = _GEN_180[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_swap12 = _GEN_181[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_swap23 = _GEN_182[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_typeTagIn = _GEN_183[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_typeTagOut = _GEN_184[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fromint = _GEN_185[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_toint = _GEN_186[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fastpipe = _GEN_187[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_fma = _GEN_188[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_div = _GEN_189[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_sqrt = _GEN_190[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_wflags = _GEN_191[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_ctrl_vec = _GEN_192[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_rob_idx = _GEN_193[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldq_idx = _GEN_194[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_stq_idx = _GEN_195[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_rxq_idx = _GEN_196[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_pdst = _GEN_197[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs1 = _GEN_198[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs2 = _GEN_199[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs3 = _GEN_200[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ppred = _GEN_201[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs1_busy = _GEN_202[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs2_busy = _GEN_203[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_prs3_busy = _GEN_204[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ppred_busy = _GEN_205[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_stale_pdst = _GEN_206[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_exception = _GEN_207[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_exc_cause = _GEN_208[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_cmd = _GEN_209[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_size = _GEN_210[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_mem_signed = _GEN_211[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_uses_ldq = _GEN_212[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_uses_stq = _GEN_213[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_is_unique = _GEN_214[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_flush_on_commit = _GEN_215[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_csr_cmd = _GEN_216[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldst_is_rs1 = _GEN_217[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_ldst = _GEN_218[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs1 = _GEN_219[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs2 = _GEN_220[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs3 = _GEN_221[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_dst_rtype = _GEN_222[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs1_rtype = _GEN_223[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_lrs2_rtype = _GEN_224[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_frs3_en = _GEN_225[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fcn_dw = _GEN_226[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fcn_op = _GEN_227[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_val = _GEN_228[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_rm = _GEN_229[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_fp_typ = _GEN_230[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_pf_if = _GEN_231[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_ae_if = _GEN_232[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_xcpt_ma_if = _GEN_233[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_bp_debug_if = _GEN_234[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_bp_xcpt_if = _GEN_235[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_fsrc = _GEN_236[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_25_debug_tsrc = _GEN_237[_T_2083]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_28_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_28_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_28_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_28_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_28_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_28_debug_inst; // @[lsu.scala:1729:25] wire s_uop_28_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_28_debug_pc; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_28_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_28_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_28_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_28_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_28_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_28_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_28_br_type; // @[lsu.scala:1729:25] wire s_uop_28_is_sfb; // @[lsu.scala:1729:25] wire s_uop_28_is_fence; // @[lsu.scala:1729:25] wire s_uop_28_is_fencei; // @[lsu.scala:1729:25] wire s_uop_28_is_sfence; // @[lsu.scala:1729:25] wire s_uop_28_is_amo; // @[lsu.scala:1729:25] wire s_uop_28_is_eret; // @[lsu.scala:1729:25] wire s_uop_28_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_28_is_rocc; // @[lsu.scala:1729:25] wire s_uop_28_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_28_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_pc_lob; // @[lsu.scala:1729:25] wire s_uop_28_taken; // @[lsu.scala:1729:25] wire s_uop_28_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_28_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_ppred; // @[lsu.scala:1729:25] wire s_uop_28_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_28_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_28_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_28_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_28_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_28_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_28_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_mem_size; // @[lsu.scala:1729:25] wire s_uop_28_mem_signed; // @[lsu.scala:1729:25] wire s_uop_28_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_28_uses_stq; // @[lsu.scala:1729:25] wire s_uop_28_is_unique; // @[lsu.scala:1729:25] wire s_uop_28_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_28_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_28_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_28_frs3_en; // @[lsu.scala:1729:25] wire s_uop_28_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_28_fcn_op; // @[lsu.scala:1729:25] wire s_uop_28_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_28_fp_typ; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_28_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_28_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_28_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_28_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_28_inst = _GEN_251[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_inst = _GEN_252[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_rvc = _GEN_253[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_pc = _GEN_254[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_0 = _GEN_255[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_1 = _GEN_256[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_2 = _GEN_257[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iq_type_3 = _GEN_258[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_0 = _GEN_259[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_1 = _GEN_260[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_2 = _GEN_261[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_3 = _GEN_262[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_4 = _GEN_263[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_5 = _GEN_264[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_6 = _GEN_265[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_7 = _GEN_266[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_8 = _GEN_267[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fu_code_9 = _GEN_268[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued = _GEN_269[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued_partial_agen = _GEN_270[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_issued_partial_dgen = _GEN_271[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p1_speculative_child = _GEN_272[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p2_speculative_child = _GEN_273[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p1_bypass_hint = _GEN_274[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p2_bypass_hint = _GEN_275[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_iw_p3_bypass_hint = _GEN_276[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_dis_col_sel = _GEN_277[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_mask = _GEN_278[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_tag = _GEN_279[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_br_type = _GEN_280[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sfb = _GEN_281[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_fence = _GEN_282[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_fencei = _GEN_283[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sfence = _GEN_284[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_amo = _GEN_285[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_eret = _GEN_286[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_sys_pc2epc = _GEN_287[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_rocc = _GEN_288[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_mov = _GEN_289[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ftq_idx = _GEN_290[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_edge_inst = _GEN_291[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pc_lob = _GEN_292[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_taken = _GEN_293[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_rename = _GEN_294[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_sel = _GEN_295[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pimm = _GEN_296[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_imm_packed = _GEN_297[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_op1_sel = _GEN_298[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_op2_sel = _GEN_299[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ldst = _GEN_300[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_wen = _GEN_301[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren1 = _GEN_302[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren2 = _GEN_303[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_ren3 = _GEN_304[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_swap12 = _GEN_305[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_swap23 = _GEN_306[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_typeTagIn = _GEN_307[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_typeTagOut = _GEN_308[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fromint = _GEN_309[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_toint = _GEN_310[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fastpipe = _GEN_311[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_fma = _GEN_312[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_div = _GEN_313[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_sqrt = _GEN_314[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_wflags = _GEN_315[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_ctrl_vec = _GEN_316[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_rob_idx = _GEN_317[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldq_idx = _GEN_318[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_stq_idx = _GEN_319[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_rxq_idx = _GEN_320[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_pdst = _GEN_321[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs1 = _GEN_322[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs2 = _GEN_323[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs3 = _GEN_324[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ppred = _GEN_325[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs1_busy = _GEN_326[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs2_busy = _GEN_327[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_prs3_busy = _GEN_328[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ppred_busy = _GEN_329[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_stale_pdst = _GEN_330[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_exception = _GEN_331[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_exc_cause = _GEN_332[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_cmd = _GEN_333[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_size = _GEN_334[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_mem_signed = _GEN_335[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_uses_ldq = _GEN_336[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_uses_stq = _GEN_337[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_is_unique = _GEN_338[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_flush_on_commit = _GEN_339[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_csr_cmd = _GEN_340[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldst_is_rs1 = _GEN_341[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_ldst = _GEN_342[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs1 = _GEN_343[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs2 = _GEN_344[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs3 = _GEN_345[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_dst_rtype = _GEN_346[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs1_rtype = _GEN_347[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_lrs2_rtype = _GEN_348[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_frs3_en = _GEN_349[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fcn_dw = _GEN_350[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fcn_op = _GEN_351[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_val = _GEN_352[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_rm = _GEN_353[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_fp_typ = _GEN_354[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_pf_if = _GEN_355[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_ae_if = _GEN_356[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_xcpt_ma_if = _GEN_357[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_bp_debug_if = _GEN_358[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_bp_xcpt_if = _GEN_359[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_fsrc = _GEN_360[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_28_debug_tsrc = _GEN_361[_T_2079]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire wrap_11 = _T_2079 == 5'h17; // @[util.scala:213:25] wire _GEN_847 = ~commit_store_1 & commit_load_1; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_848 = _GEN_847 & ~reset; // @[lsu.scala:1735:31, :1736:14] wire wrap_12 = _T_2083 == 5'h17; // @[util.scala:213:25] wire [4:0] _T_2094 = wrap_11 ? 5'h0 : _T_2079 + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2095 = commit_store_1 ? _T_2094 : _T_2079; // @[util.scala:214:10] wire [4:0] _T_2098 = wrap_12 ? 5'h0 : _T_2083 + 5'h1; // @[util.scala:213:25, :214:{10,28}] wire [4:0] _T_2099 = commit_load_1 ? _T_2098 : _T_2083; // @[util.scala:214:10] wire commit_store_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_stq_0; // @[lsu.scala:211:7, :1724:49] wire commit_load_2 = io_core_commit_valids_2_0 & io_core_commit_uops_2_uses_ldq_0; // @[lsu.scala:211:7, :1725:49] wire l_uop_26_iq_type_0; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_1; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_2; // @[lsu.scala:1728:25] wire l_uop_26_iq_type_3; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_0; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_1; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_2; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_3; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_4; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_5; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_6; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_7; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_8; // @[lsu.scala:1728:25] wire l_uop_26_fu_code_9; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ldst; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_wen; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren1; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren2; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_ren3; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_swap12; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_swap23; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_ctrl_typeTagIn; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_ctrl_typeTagOut; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fromint; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_toint; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fastpipe; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_fma; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_div; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_sqrt; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_wflags; // @[lsu.scala:1728:25] wire l_uop_26_fp_ctrl_vec; // @[lsu.scala:1728:25] wire [31:0] l_uop_26_inst; // @[lsu.scala:1728:25] wire [31:0] l_uop_26_debug_inst; // @[lsu.scala:1728:25] wire l_uop_26_is_rvc; // @[lsu.scala:1728:25] wire [39:0] l_uop_26_debug_pc; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued_partial_agen; // @[lsu.scala:1728:25] wire l_uop_26_iw_issued_partial_dgen; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_iw_p1_speculative_child; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_iw_p2_speculative_child; // @[lsu.scala:1728:25] wire l_uop_26_iw_p1_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_26_iw_p2_bypass_hint; // @[lsu.scala:1728:25] wire l_uop_26_iw_p3_bypass_hint; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_dis_col_sel; // @[lsu.scala:1728:25] wire [15:0] l_uop_26_br_mask; // @[lsu.scala:1728:25] wire [3:0] l_uop_26_br_tag; // @[lsu.scala:1728:25] wire [3:0] l_uop_26_br_type; // @[lsu.scala:1728:25] wire l_uop_26_is_sfb; // @[lsu.scala:1728:25] wire l_uop_26_is_fence; // @[lsu.scala:1728:25] wire l_uop_26_is_fencei; // @[lsu.scala:1728:25] wire l_uop_26_is_sfence; // @[lsu.scala:1728:25] wire l_uop_26_is_amo; // @[lsu.scala:1728:25] wire l_uop_26_is_eret; // @[lsu.scala:1728:25] wire l_uop_26_is_sys_pc2epc; // @[lsu.scala:1728:25] wire l_uop_26_is_rocc; // @[lsu.scala:1728:25] wire l_uop_26_is_mov; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ftq_idx; // @[lsu.scala:1728:25] wire l_uop_26_edge_inst; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_pc_lob; // @[lsu.scala:1728:25] wire l_uop_26_taken; // @[lsu.scala:1728:25] wire l_uop_26_imm_rename; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_imm_sel; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_pimm; // @[lsu.scala:1728:25] wire [19:0] l_uop_26_imm_packed; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_op1_sel; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_op2_sel; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_rob_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ldq_idx; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_stq_idx; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_rxq_idx; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_pdst; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs1; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs2; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_prs3; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_ppred; // @[lsu.scala:1728:25] wire l_uop_26_prs1_busy; // @[lsu.scala:1728:25] wire l_uop_26_prs2_busy; // @[lsu.scala:1728:25] wire l_uop_26_prs3_busy; // @[lsu.scala:1728:25] wire l_uop_26_ppred_busy; // @[lsu.scala:1728:25] wire [6:0] l_uop_26_stale_pdst; // @[lsu.scala:1728:25] wire l_uop_26_exception; // @[lsu.scala:1728:25] wire [63:0] l_uop_26_exc_cause; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_mem_cmd; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_mem_size; // @[lsu.scala:1728:25] wire l_uop_26_mem_signed; // @[lsu.scala:1728:25] wire l_uop_26_uses_ldq; // @[lsu.scala:1728:25] wire l_uop_26_uses_stq; // @[lsu.scala:1728:25] wire l_uop_26_is_unique; // @[lsu.scala:1728:25] wire l_uop_26_flush_on_commit; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_csr_cmd; // @[lsu.scala:1728:25] wire l_uop_26_ldst_is_rs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_ldst; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs1; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs2; // @[lsu.scala:1728:25] wire [5:0] l_uop_26_lrs3; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_dst_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_lrs1_rtype; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_lrs2_rtype; // @[lsu.scala:1728:25] wire l_uop_26_frs3_en; // @[lsu.scala:1728:25] wire l_uop_26_fcn_dw; // @[lsu.scala:1728:25] wire [4:0] l_uop_26_fcn_op; // @[lsu.scala:1728:25] wire l_uop_26_fp_val; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_fp_rm; // @[lsu.scala:1728:25] wire [1:0] l_uop_26_fp_typ; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_pf_if; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_ae_if; // @[lsu.scala:1728:25] wire l_uop_26_xcpt_ma_if; // @[lsu.scala:1728:25] wire l_uop_26_bp_debug_if; // @[lsu.scala:1728:25] wire l_uop_26_bp_xcpt_if; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_debug_fsrc; // @[lsu.scala:1728:25] wire [2:0] l_uop_26_debug_tsrc; // @[lsu.scala:1728:25] assign l_uop_26_inst = _GEN_127[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_inst = _GEN_128[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_rvc = _GEN_129[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_pc = _GEN_130[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_0 = _GEN_131[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_1 = _GEN_132[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_2 = _GEN_133[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iq_type_3 = _GEN_134[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_0 = _GEN_135[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_1 = _GEN_136[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_2 = _GEN_137[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_3 = _GEN_138[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_4 = _GEN_139[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_5 = _GEN_140[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_6 = _GEN_141[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_7 = _GEN_142[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_8 = _GEN_143[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fu_code_9 = _GEN_144[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued = _GEN_145[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued_partial_agen = _GEN_146[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_issued_partial_dgen = _GEN_147[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p1_speculative_child = _GEN_148[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p2_speculative_child = _GEN_149[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p1_bypass_hint = _GEN_150[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p2_bypass_hint = _GEN_151[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_iw_p3_bypass_hint = _GEN_152[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_dis_col_sel = _GEN_153[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_mask = _GEN_154[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_tag = _GEN_155[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_br_type = _GEN_156[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sfb = _GEN_157[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_fence = _GEN_158[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_fencei = _GEN_159[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sfence = _GEN_160[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_amo = _GEN_161[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_eret = _GEN_162[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_sys_pc2epc = _GEN_163[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_rocc = _GEN_164[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_mov = _GEN_165[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ftq_idx = _GEN_166[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_edge_inst = _GEN_167[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pc_lob = _GEN_168[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_taken = _GEN_169[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_rename = _GEN_170[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_sel = _GEN_171[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pimm = _GEN_172[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_imm_packed = _GEN_173[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_op1_sel = _GEN_174[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_op2_sel = _GEN_175[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ldst = _GEN_176[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_wen = _GEN_177[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren1 = _GEN_178[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren2 = _GEN_179[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_ren3 = _GEN_180[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_swap12 = _GEN_181[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_swap23 = _GEN_182[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_typeTagIn = _GEN_183[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_typeTagOut = _GEN_184[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fromint = _GEN_185[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_toint = _GEN_186[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fastpipe = _GEN_187[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_fma = _GEN_188[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_div = _GEN_189[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_sqrt = _GEN_190[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_wflags = _GEN_191[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_ctrl_vec = _GEN_192[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_rob_idx = _GEN_193[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldq_idx = _GEN_194[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_stq_idx = _GEN_195[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_rxq_idx = _GEN_196[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_pdst = _GEN_197[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs1 = _GEN_198[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs2 = _GEN_199[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs3 = _GEN_200[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ppred = _GEN_201[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs1_busy = _GEN_202[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs2_busy = _GEN_203[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_prs3_busy = _GEN_204[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ppred_busy = _GEN_205[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_stale_pdst = _GEN_206[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_exception = _GEN_207[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_exc_cause = _GEN_208[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_cmd = _GEN_209[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_size = _GEN_210[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_mem_signed = _GEN_211[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_uses_ldq = _GEN_212[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_uses_stq = _GEN_213[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_is_unique = _GEN_214[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_flush_on_commit = _GEN_215[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_csr_cmd = _GEN_216[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldst_is_rs1 = _GEN_217[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_ldst = _GEN_218[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs1 = _GEN_219[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs2 = _GEN_220[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs3 = _GEN_221[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_dst_rtype = _GEN_222[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs1_rtype = _GEN_223[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_lrs2_rtype = _GEN_224[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_frs3_en = _GEN_225[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fcn_dw = _GEN_226[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fcn_op = _GEN_227[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_val = _GEN_228[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_rm = _GEN_229[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_fp_typ = _GEN_230[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_pf_if = _GEN_231[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_ae_if = _GEN_232[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_xcpt_ma_if = _GEN_233[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_bp_debug_if = _GEN_234[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_bp_xcpt_if = _GEN_235[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_fsrc = _GEN_236[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] assign l_uop_26_debug_tsrc = _GEN_237[_T_2099]; // @[lsu.scala:235:32, :1728:25, :1758:31] wire s_uop_29_iq_type_0; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_1; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_2; // @[lsu.scala:1729:25] wire s_uop_29_iq_type_3; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_0; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_1; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_2; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_3; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_4; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_5; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_6; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_7; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_8; // @[lsu.scala:1729:25] wire s_uop_29_fu_code_9; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ldst; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_wen; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren1; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren2; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_ren3; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_swap12; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_swap23; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_ctrl_typeTagIn; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_ctrl_typeTagOut; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fromint; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_toint; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fastpipe; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_fma; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_div; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_sqrt; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_wflags; // @[lsu.scala:1729:25] wire s_uop_29_fp_ctrl_vec; // @[lsu.scala:1729:25] wire [31:0] s_uop_29_inst; // @[lsu.scala:1729:25] wire [31:0] s_uop_29_debug_inst; // @[lsu.scala:1729:25] wire s_uop_29_is_rvc; // @[lsu.scala:1729:25] wire [39:0] s_uop_29_debug_pc; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued_partial_agen; // @[lsu.scala:1729:25] wire s_uop_29_iw_issued_partial_dgen; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_iw_p1_speculative_child; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_iw_p2_speculative_child; // @[lsu.scala:1729:25] wire s_uop_29_iw_p1_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_29_iw_p2_bypass_hint; // @[lsu.scala:1729:25] wire s_uop_29_iw_p3_bypass_hint; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_dis_col_sel; // @[lsu.scala:1729:25] wire [15:0] s_uop_29_br_mask; // @[lsu.scala:1729:25] wire [3:0] s_uop_29_br_tag; // @[lsu.scala:1729:25] wire [3:0] s_uop_29_br_type; // @[lsu.scala:1729:25] wire s_uop_29_is_sfb; // @[lsu.scala:1729:25] wire s_uop_29_is_fence; // @[lsu.scala:1729:25] wire s_uop_29_is_fencei; // @[lsu.scala:1729:25] wire s_uop_29_is_sfence; // @[lsu.scala:1729:25] wire s_uop_29_is_amo; // @[lsu.scala:1729:25] wire s_uop_29_is_eret; // @[lsu.scala:1729:25] wire s_uop_29_is_sys_pc2epc; // @[lsu.scala:1729:25] wire s_uop_29_is_rocc; // @[lsu.scala:1729:25] wire s_uop_29_is_mov; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ftq_idx; // @[lsu.scala:1729:25] wire s_uop_29_edge_inst; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_pc_lob; // @[lsu.scala:1729:25] wire s_uop_29_taken; // @[lsu.scala:1729:25] wire s_uop_29_imm_rename; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_imm_sel; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_pimm; // @[lsu.scala:1729:25] wire [19:0] s_uop_29_imm_packed; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_op1_sel; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_op2_sel; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_rob_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ldq_idx; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_stq_idx; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_rxq_idx; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_pdst; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs1; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs2; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_prs3; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_ppred; // @[lsu.scala:1729:25] wire s_uop_29_prs1_busy; // @[lsu.scala:1729:25] wire s_uop_29_prs2_busy; // @[lsu.scala:1729:25] wire s_uop_29_prs3_busy; // @[lsu.scala:1729:25] wire s_uop_29_ppred_busy; // @[lsu.scala:1729:25] wire [6:0] s_uop_29_stale_pdst; // @[lsu.scala:1729:25] wire s_uop_29_exception; // @[lsu.scala:1729:25] wire [63:0] s_uop_29_exc_cause; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_mem_cmd; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_mem_size; // @[lsu.scala:1729:25] wire s_uop_29_mem_signed; // @[lsu.scala:1729:25] wire s_uop_29_uses_ldq; // @[lsu.scala:1729:25] wire s_uop_29_uses_stq; // @[lsu.scala:1729:25] wire s_uop_29_is_unique; // @[lsu.scala:1729:25] wire s_uop_29_flush_on_commit; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_csr_cmd; // @[lsu.scala:1729:25] wire s_uop_29_ldst_is_rs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_ldst; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs1; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs2; // @[lsu.scala:1729:25] wire [5:0] s_uop_29_lrs3; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_dst_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_lrs1_rtype; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_lrs2_rtype; // @[lsu.scala:1729:25] wire s_uop_29_frs3_en; // @[lsu.scala:1729:25] wire s_uop_29_fcn_dw; // @[lsu.scala:1729:25] wire [4:0] s_uop_29_fcn_op; // @[lsu.scala:1729:25] wire s_uop_29_fp_val; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_fp_rm; // @[lsu.scala:1729:25] wire [1:0] s_uop_29_fp_typ; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_pf_if; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_ae_if; // @[lsu.scala:1729:25] wire s_uop_29_xcpt_ma_if; // @[lsu.scala:1729:25] wire s_uop_29_bp_debug_if; // @[lsu.scala:1729:25] wire s_uop_29_bp_xcpt_if; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_debug_fsrc; // @[lsu.scala:1729:25] wire [2:0] s_uop_29_debug_tsrc; // @[lsu.scala:1729:25] assign s_uop_29_inst = _GEN_251[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_inst = _GEN_252[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_rvc = _GEN_253[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_pc = _GEN_254[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_0 = _GEN_255[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_1 = _GEN_256[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_2 = _GEN_257[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iq_type_3 = _GEN_258[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_0 = _GEN_259[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_1 = _GEN_260[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_2 = _GEN_261[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_3 = _GEN_262[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_4 = _GEN_263[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_5 = _GEN_264[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_6 = _GEN_265[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_7 = _GEN_266[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_8 = _GEN_267[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fu_code_9 = _GEN_268[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued = _GEN_269[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued_partial_agen = _GEN_270[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_issued_partial_dgen = _GEN_271[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p1_speculative_child = _GEN_272[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p2_speculative_child = _GEN_273[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p1_bypass_hint = _GEN_274[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p2_bypass_hint = _GEN_275[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_iw_p3_bypass_hint = _GEN_276[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_dis_col_sel = _GEN_277[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_mask = _GEN_278[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_tag = _GEN_279[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_br_type = _GEN_280[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sfb = _GEN_281[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_fence = _GEN_282[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_fencei = _GEN_283[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sfence = _GEN_284[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_amo = _GEN_285[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_eret = _GEN_286[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_sys_pc2epc = _GEN_287[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_rocc = _GEN_288[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_mov = _GEN_289[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ftq_idx = _GEN_290[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_edge_inst = _GEN_291[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pc_lob = _GEN_292[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_taken = _GEN_293[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_rename = _GEN_294[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_sel = _GEN_295[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pimm = _GEN_296[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_imm_packed = _GEN_297[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_op1_sel = _GEN_298[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_op2_sel = _GEN_299[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ldst = _GEN_300[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_wen = _GEN_301[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren1 = _GEN_302[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren2 = _GEN_303[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_ren3 = _GEN_304[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_swap12 = _GEN_305[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_swap23 = _GEN_306[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_typeTagIn = _GEN_307[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_typeTagOut = _GEN_308[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fromint = _GEN_309[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_toint = _GEN_310[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fastpipe = _GEN_311[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_fma = _GEN_312[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_div = _GEN_313[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_sqrt = _GEN_314[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_wflags = _GEN_315[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_ctrl_vec = _GEN_316[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_rob_idx = _GEN_317[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldq_idx = _GEN_318[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_stq_idx = _GEN_319[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_rxq_idx = _GEN_320[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_pdst = _GEN_321[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs1 = _GEN_322[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs2 = _GEN_323[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs3 = _GEN_324[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ppred = _GEN_325[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs1_busy = _GEN_326[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs2_busy = _GEN_327[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_prs3_busy = _GEN_328[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ppred_busy = _GEN_329[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_stale_pdst = _GEN_330[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_exception = _GEN_331[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_exc_cause = _GEN_332[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_cmd = _GEN_333[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_size = _GEN_334[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_mem_signed = _GEN_335[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_uses_ldq = _GEN_336[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_uses_stq = _GEN_337[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_is_unique = _GEN_338[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_flush_on_commit = _GEN_339[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_csr_cmd = _GEN_340[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldst_is_rs1 = _GEN_341[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_ldst = _GEN_342[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs1 = _GEN_343[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs2 = _GEN_344[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs3 = _GEN_345[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_dst_rtype = _GEN_346[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs1_rtype = _GEN_347[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_lrs2_rtype = _GEN_348[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_frs3_en = _GEN_349[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fcn_dw = _GEN_350[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fcn_op = _GEN_351[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_val = _GEN_352[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_rm = _GEN_353[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_fp_typ = _GEN_354[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_pf_if = _GEN_355[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_ae_if = _GEN_356[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_xcpt_ma_if = _GEN_357[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_bp_debug_if = _GEN_358[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_bp_xcpt_if = _GEN_359[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_fsrc = _GEN_360[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] assign s_uop_29_debug_tsrc = _GEN_361[_T_2095]; // @[lsu.scala:264:32, :1729:25, :1754:31] wire wrap_13 = _T_2095 == 5'h17; // @[util.scala:213:25] wire _GEN_849 = ~commit_store_2 & commit_load_2; // @[lsu.scala:1724:49, :1725:49, :1731:5, :1735:31] wire _GEN_850 = _GEN_849 & ~reset; // @[lsu.scala:1735:31, :1736:14]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_127 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_127( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_162 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_162( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module PE_436 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_180 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c

module PE_436( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_180 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_52 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_65 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_52( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_65 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLAFromNoC_13 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<47>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, const connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T = shr(const, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T connect protocol.bits.user, _protocol_bits_user_WIRE node _T_1 = shr(_T, 0) wire _protocol_bits_address_WIRE : UInt<32> connect _protocol_bits_address_WIRE, _T_1 connect protocol.bits.address, _protocol_bits_address_WIRE node _T_2 = shr(_T_1, 32) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_2 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_3 = shr(_T_2, 6) wire _protocol_bits_size_WIRE : UInt<3> connect _protocol_bits_size_WIRE, _T_3 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_4 = shr(_T_3, 3) wire _protocol_bits_param_WIRE : UInt<3> connect _protocol_bits_param_WIRE, _T_4 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_5 = shr(_T_4, 3) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_5 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_6 = shr(_T_5, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_7 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_7 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_8 = shr(_T_7, 64) wire _protocol_bits_mask_WIRE : UInt<8> connect _protocol_bits_mask_WIRE, _T_8 connect protocol.bits.mask, _protocol_bits_mask_WIRE node _T_9 = shr(_T_8, 8) node _T_10 = and(io.flit.ready, io.flit.valid) node _T_11 = and(_T_10, io.flit.bits.head) when _T_11 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_12 = and(io.flit.ready, io.flit.valid) node _T_13 = and(_T_12, io.flit.bits.tail) when _T_13 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol when io.flit.bits.head : node _io_protocol_bits_mask_T = not(UInt<8>(0h0)) connect io.protocol.bits.mask, _io_protocol_bits_mask_T

module TLAFromNoC_13( // @[TilelinkAdapters.scala:128:7] input clock, // @[TilelinkAdapters.scala:128:7] input reset, // @[TilelinkAdapters.scala:128:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14] output [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [72:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [46:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [46:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[46:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:128:7] if (reset) // @[TilelinkAdapters.scala:128:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :128:7] else // @[TilelinkAdapters.scala:128:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[46:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)

Generate the Verilog code corresponding to this FIRRTL code module BoomDuplicatedDataArray_1 : input clock : Clock input reset : Reset output io : { flip read : { valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>}}[1], flip write : { valid : UInt<1>, bits : { way_en : UInt<4>, addr : UInt<12>, wmask : UInt<1>, data : UInt<64>}}, resp : UInt<64>[4][1], nacks : UInt<1>[1]} node waddr = shr(io.write.bits.addr, 3) node raddr = shr(io.read[0].bits.addr, 3) smem array_0_0 : UInt<64>[1] [512] node _T = bits(io.write.bits.way_en, 0, 0) node _T_1 = and(_T, io.write.valid) when _T_1 : node _data_T = bits(io.write.bits.data, 63, 0) wire data : UInt<64>[1] connect data[0], _data_T node _T_2 = bits(io.write.bits.wmask, 0, 0) write mport MPORT = array_0_0[waddr], clock when _T_2 : connect MPORT[0], data[0] node _io_resp_0_0_T = bits(io.read[0].bits.way_en, 0, 0) node _io_resp_0_0_T_1 = and(_io_resp_0_0_T, io.read[0].valid) wire _io_resp_0_0_WIRE : UInt<9> invalidate _io_resp_0_0_WIRE when _io_resp_0_0_T_1 : connect _io_resp_0_0_WIRE, raddr read mport io_resp_0_0_MPORT = array_0_0[_io_resp_0_0_WIRE], clock reg io_resp_0_0_REG : UInt, clock connect io_resp_0_0_REG, io_resp_0_0_MPORT[0] connect io.resp[0][0], io_resp_0_0_REG smem array_1_0 : UInt<64>[1] [512] node _T_3 = bits(io.write.bits.way_en, 1, 1) node _T_4 = and(_T_3, io.write.valid) when _T_4 : node _data_T_1 = bits(io.write.bits.data, 63, 0) wire data_1 : UInt<64>[1] connect data_1[0], _data_T_1 node _T_5 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_1 = array_1_0[waddr], clock when _T_5 : connect MPORT_1[0], data_1[0] node _io_resp_0_1_T = bits(io.read[0].bits.way_en, 1, 1) node _io_resp_0_1_T_1 = and(_io_resp_0_1_T, io.read[0].valid) wire _io_resp_0_1_WIRE : UInt<9> invalidate _io_resp_0_1_WIRE when _io_resp_0_1_T_1 : connect _io_resp_0_1_WIRE, raddr read mport io_resp_0_1_MPORT = array_1_0[_io_resp_0_1_WIRE], clock reg io_resp_0_1_REG : UInt, clock connect io_resp_0_1_REG, io_resp_0_1_MPORT[0] connect io.resp[0][1], io_resp_0_1_REG smem array_2_0 : UInt<64>[1] [512] node _T_6 = bits(io.write.bits.way_en, 2, 2) node _T_7 = and(_T_6, io.write.valid) when _T_7 : node _data_T_2 = bits(io.write.bits.data, 63, 0) wire data_2 : UInt<64>[1] connect data_2[0], _data_T_2 node _T_8 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_2 = array_2_0[waddr], clock when _T_8 : connect MPORT_2[0], data_2[0] node _io_resp_0_2_T = bits(io.read[0].bits.way_en, 2, 2) node _io_resp_0_2_T_1 = and(_io_resp_0_2_T, io.read[0].valid) wire _io_resp_0_2_WIRE : UInt<9> invalidate _io_resp_0_2_WIRE when _io_resp_0_2_T_1 : connect _io_resp_0_2_WIRE, raddr read mport io_resp_0_2_MPORT = array_2_0[_io_resp_0_2_WIRE], clock reg io_resp_0_2_REG : UInt, clock connect io_resp_0_2_REG, io_resp_0_2_MPORT[0] connect io.resp[0][2], io_resp_0_2_REG smem array_3_0 : UInt<64>[1] [512] node _T_9 = bits(io.write.bits.way_en, 3, 3) node _T_10 = and(_T_9, io.write.valid) when _T_10 : node _data_T_3 = bits(io.write.bits.data, 63, 0) wire data_3 : UInt<64>[1] connect data_3[0], _data_T_3 node _T_11 = bits(io.write.bits.wmask, 0, 0) write mport MPORT_3 = array_3_0[waddr], clock when _T_11 : connect MPORT_3[0], data_3[0] node _io_resp_0_3_T = bits(io.read[0].bits.way_en, 3, 3) node _io_resp_0_3_T_1 = and(_io_resp_0_3_T, io.read[0].valid) wire _io_resp_0_3_WIRE : UInt<9> invalidate _io_resp_0_3_WIRE when _io_resp_0_3_T_1 : connect _io_resp_0_3_WIRE, raddr read mport io_resp_0_3_MPORT = array_3_0[_io_resp_0_3_WIRE], clock reg io_resp_0_3_REG : UInt, clock connect io_resp_0_3_REG, io_resp_0_3_MPORT[0] connect io.resp[0][3], io_resp_0_3_REG connect io.nacks[0], UInt<1>(0h0)

module BoomDuplicatedDataArray_1( // @[dcache.scala:281:7] input clock, // @[dcache.scala:281:7] input reset, // @[dcache.scala:281:7] input io_read_0_valid, // @[dcache.scala:270:14] input [3:0] io_read_0_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_read_0_bits_addr, // @[dcache.scala:270:14] input io_write_valid, // @[dcache.scala:270:14] input [3:0] io_write_bits_way_en, // @[dcache.scala:270:14] input [11:0] io_write_bits_addr, // @[dcache.scala:270:14] input [63:0] io_write_bits_data, // @[dcache.scala:270:14] output [63:0] io_resp_0_0, // @[dcache.scala:270:14] output [63:0] io_resp_0_1, // @[dcache.scala:270:14] output [63:0] io_resp_0_2, // @[dcache.scala:270:14] output [63:0] io_resp_0_3 // @[dcache.scala:270:14] ); wire [63:0] _array_3_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_2_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire [63:0] _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] wire io_read_0_valid_0 = io_read_0_valid; // @[dcache.scala:281:7] wire [3:0] io_read_0_bits_way_en_0 = io_read_0_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_read_0_bits_addr_0 = io_read_0_bits_addr; // @[dcache.scala:281:7] wire io_write_valid_0 = io_write_valid; // @[dcache.scala:281:7] wire [3:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[dcache.scala:281:7] wire [11:0] io_write_bits_addr_0 = io_write_bits_addr; // @[dcache.scala:281:7] wire [63:0] io_write_bits_data_0 = io_write_bits_data; // @[dcache.scala:281:7] wire io_nacks_0 = 1'h0; // @[dcache.scala:281:7] wire io_write_bits_wmask = 1'h1; // @[DescribedSRAM.scala:17:26] wire [63:0] _data_T = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_1 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_2 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] _data_T_3 = io_write_bits_data_0; // @[dcache.scala:281:7, :296:75] wire [63:0] io_resp_0_0_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_1_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_2_0; // @[dcache.scala:281:7] wire [63:0] io_resp_0_3_0; // @[dcache.scala:281:7] wire [8:0] waddr = io_write_bits_addr_0[11:3]; // @[dcache.scala:281:7, :284:34] wire [8:0] raddr = io_read_0_bits_addr_0[11:3]; // @[dcache.scala:281:7, :287:38] wire [8:0] _io_resp_0_0_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_1_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_2_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [8:0] _io_resp_0_3_WIRE = raddr; // @[dcache.scala:287:38, :299:42] wire [63:0] data_0 = _data_T; // @[dcache.scala:296:{27,75}] wire _io_resp_0_0_T = io_read_0_bits_way_en_0[0]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_0_T_1 = _io_resp_0_0_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_0_REG; // @[dcache.scala:299:31] assign io_resp_0_0_0 = io_resp_0_0_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_1_0 = _data_T_1; // @[dcache.scala:296:{27,75}] wire _io_resp_0_1_T = io_read_0_bits_way_en_0[1]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_1_T_1 = _io_resp_0_1_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_1_REG; // @[dcache.scala:299:31] assign io_resp_0_1_0 = io_resp_0_1_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_2_0 = _data_T_2; // @[dcache.scala:296:{27,75}] wire _io_resp_0_2_T = io_read_0_bits_way_en_0[2]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_2_T_1 = _io_resp_0_2_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_2_REG; // @[dcache.scala:299:31] assign io_resp_0_2_0 = io_resp_0_2_REG; // @[dcache.scala:281:7, :299:31] wire [63:0] data_3_0 = _data_T_3; // @[dcache.scala:296:{27,75}] wire _io_resp_0_3_T = io_read_0_bits_way_en_0[3]; // @[dcache.scala:281:7, :299:72] wire _io_resp_0_3_T_1 = _io_resp_0_3_T & io_read_0_valid_0; // @[dcache.scala:281:7, :299:{72,76}] reg [63:0] io_resp_0_3_REG; // @[dcache.scala:299:31] assign io_resp_0_3_0 = io_resp_0_3_REG; // @[dcache.scala:281:7, :299:31] always @(posedge clock) begin // @[dcache.scala:281:7] io_resp_0_0_REG <= _array_0_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_1_REG <= _array_1_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_2_REG <= _array_2_0_0_R0_data; // @[DescribedSRAM.scala:17:26] io_resp_0_3_REG <= _array_3_0_0_R0_data; // @[DescribedSRAM.scala:17:26] always @(posedge) array_0_0_0_0 array_0_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_0_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_0_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_0_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[0] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_1_0_0_0 array_1_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_1_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_1_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_1_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[1] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_1_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_2_0_0_0 array_2_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_2_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_2_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_2_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[2] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_2_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] array_3_0_0_0 array_3_0_0 ( // @[DescribedSRAM.scala:17:26] .R0_addr (_io_resp_0_3_WIRE), // @[dcache.scala:299:42] .R0_en (_io_resp_0_3_T_1), // @[dcache.scala:299:76] .R0_clk (clock), .R0_data (_array_3_0_0_R0_data), .W0_addr (waddr), // @[dcache.scala:284:34] .W0_en (io_write_bits_way_en_0[3] & io_write_valid_0), // @[dcache.scala:281:7, :295:{33,37}] .W0_clk (clock), .W0_data (data_3_0) // @[dcache.scala:296:27] ); // @[DescribedSRAM.scala:17:26] assign io_resp_0_0 = io_resp_0_0_0; // @[dcache.scala:281:7] assign io_resp_0_1 = io_resp_0_1_0; // @[dcache.scala:281:7] assign io_resp_0_2 = io_resp_0_2_0; // @[dcache.scala:281:7] assign io_resp_0_3 = io_resp_0_3_0; // @[dcache.scala:281:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_6ClockSinkDomain : output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, routers_source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_22 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget_8 connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst egress_width_widget of EgressWidthWidget_8 connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 connect routers.auto.dest_nodes_in_3, auto.routers_dest_nodes_in_3 connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit connect routers.auto.source_nodes_out_3.vc_free, auto.routers_source_nodes_out_3.vc_free connect routers.auto.source_nodes_out_3.credit_return, auto.routers_source_nodes_out_3.credit_return connect auto.routers_source_nodes_out_3.flit, routers.auto.source_nodes_out_3.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module TLSplitACDxBENoC_be_router_6ClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [3:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_22 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2), .auto_debug_out_va_stall_3 (auto_routers_debug_out_va_stall_3), .auto_debug_out_va_stall_4 (auto_routers_debug_out_va_stall_4), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2), .auto_debug_out_sa_stall_3 (auto_routers_debug_out_sa_stall_3), .auto_debug_out_sa_stall_4 (auto_routers_debug_out_sa_stall_4), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_3_flit_0_valid (auto_routers_source_nodes_out_3_flit_0_valid), .auto_source_nodes_out_3_flit_0_bits_head (auto_routers_source_nodes_out_3_flit_0_bits_head), .auto_source_nodes_out_3_flit_0_bits_tail (auto_routers_source_nodes_out_3_flit_0_bits_tail), .auto_source_nodes_out_3_flit_0_bits_payload (auto_routers_source_nodes_out_3_flit_0_bits_payload), .auto_source_nodes_out_3_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node), .auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_3_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_3_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_3_flit_0_bits_virt_channel_id), .auto_source_nodes_out_3_credit_return (auto_routers_source_nodes_out_3_credit_return), .auto_source_nodes_out_3_vc_free (auto_routers_source_nodes_out_3_vc_free), .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid), .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head), .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail), .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload), .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node), .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id), .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return), .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free), .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid), .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head), .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail), .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload), .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node), .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id), .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return), .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free), .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid), .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head), .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail), .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload), .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node), .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id), .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return), .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free), .auto_dest_nodes_in_3_flit_0_valid (auto_routers_dest_nodes_in_3_flit_0_valid), .auto_dest_nodes_in_3_flit_0_bits_head (auto_routers_dest_nodes_in_3_flit_0_bits_head), .auto_dest_nodes_in_3_flit_0_bits_tail (auto_routers_dest_nodes_in_3_flit_0_bits_tail), .auto_dest_nodes_in_3_flit_0_bits_payload (auto_routers_dest_nodes_in_3_flit_0_bits_payload), .auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_3_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_3_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_3_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_3_credit_return (auto_routers_dest_nodes_in_3_credit_return), .auto_dest_nodes_in_3_vc_free (auto_routers_dest_nodes_in_3_vc_free), .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid), .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head), .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail), .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload), .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return), .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free), .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid), .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head), .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail), .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload), .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return), .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free), .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid), .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head), .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail), .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload), .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return), .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget_2 ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_tail (auto_ingress_width_widget_in_flit_bits_tail), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (1'h1), // @[LazyModuleImp.scala:107:25] .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_45 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_58 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_45( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_58 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_95 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_96 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_47( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module Router_7 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[4], sa_stall : UInt[4]}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_7 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire ingressNodesIn_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_2.flit.bits.egress_id invalidate ingressNodesIn_2.flit.bits.payload invalidate ingressNodesIn_2.flit.bits.tail invalidate ingressNodesIn_2.flit.bits.head invalidate ingressNodesIn_2.flit.valid invalidate ingressNodesIn_2.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire debugNodeOut : { va_stall : UInt[4], sa_stall : UInt[4]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect ingressNodesIn_2, auto.ingress_nodes_in_2 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.debug_out, debugNodeOut inst input_unit_0_from_23 of InputUnit_7 connect input_unit_0_from_23.clock, clock connect input_unit_0_from_23.reset, reset inst ingress_unit_1_from_12 of IngressUnit_18 connect ingress_unit_1_from_12.clock, clock connect ingress_unit_1_from_12.reset, reset inst ingress_unit_2_from_13 of IngressUnit_19 connect ingress_unit_2_from_13.clock, clock connect ingress_unit_2_from_13.reset, reset inst ingress_unit_3_from_14 of IngressUnit_20 connect ingress_unit_3_from_14.clock, clock connect ingress_unit_3_from_14.reset, reset inst output_unit_0_to_23 of OutputUnit_7 connect output_unit_0_to_23.clock, clock connect output_unit_0_to_23.reset, reset inst egress_unit_1_to_8 of EgressUnit_17 connect egress_unit_1_to_8.clock, clock connect egress_unit_1_to_8.reset, reset inst egress_unit_2_to_9 of EgressUnit_18 connect egress_unit_2_to_9.clock, clock connect egress_unit_2_to_9.reset, reset inst switch of Switch_7 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_7 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_7 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_7 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_5 = bits(_fires_count_T_4, 1, 0) node _fires_count_T_6 = add(_fires_count_T_2, _fires_count_T_3) node _fires_count_T_7 = bits(_fires_count_T_6, 1, 0) node _fires_count_T_8 = add(_fires_count_T_5, _fires_count_T_7) node _fires_count_T_9 = bits(_fires_count_T_8, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_9 connect input_unit_0_from_23.io.in, destNodesIn connect ingress_unit_1_from_12.io.in, ingressNodesIn.flit connect ingress_unit_2_from_13.io.in, ingressNodesIn_1.flit connect ingress_unit_3_from_14.io.in, ingressNodesIn_2.flit connect output_unit_0_to_23.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_23.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_23.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_8.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_8.io.out.valid connect egress_unit_1_to_8.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_9.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_9.io.out.valid connect egress_unit_2_to_9.io.out.ready, egressNodesOut_1.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_23.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_12.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_13.io.router_req connect route_computer.io.req.`3`, ingress_unit_3_from_14.io.router_req connect input_unit_0_from_23.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_12.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_13.io.router_resp, route_computer.io.resp.`2` connect ingress_unit_3_from_14.io.router_resp, route_computer.io.resp.`3` connect vc_allocator.io.req.`0`, input_unit_0_from_23.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_12.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_13.io.vcalloc_req connect vc_allocator.io.req.`3`, ingress_unit_3_from_14.io.vcalloc_req connect input_unit_0_from_23.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_12.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_13.io.vcalloc_resp, vc_allocator.io.resp.`2` connect ingress_unit_3_from_14.io.vcalloc_resp, vc_allocator.io.resp.`3` connect output_unit_0_to_23.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_8.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_9.io.allocs, vc_allocator.io.out_allocs.`2` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_23.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_23.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_23.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_23.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_23.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_23.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_23.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_23.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_23.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_23.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_23.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_23.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_23.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_23.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_23.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_23.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_23.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_23.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_23.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_23.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_23.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_23.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_23.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_23.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_23.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_23.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_23.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_23.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_23.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_23.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_23.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_23.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_23.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_23.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_23.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_23.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_23.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_23.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_23.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_23.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_23.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_8.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_8.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_8.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_9.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_9.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_9.io.channel_status[0].occupied connect input_unit_0_from_23.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect input_unit_0_from_23.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect input_unit_0_from_23.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect input_unit_0_from_23.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect input_unit_0_from_23.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect input_unit_0_from_23.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect input_unit_0_from_23.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect input_unit_0_from_23.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect input_unit_0_from_23.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect input_unit_0_from_23.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_1_from_12.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_1_from_12.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_1_from_12.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_1_from_12.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_1_from_12.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_1_from_12.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_1_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_1_from_12.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_2_from_13.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_2_from_13.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_2_from_13.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_2_from_13.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_2_from_13.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_2_from_13.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_2_from_13.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_2_from_13.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[0], output_unit_0_to_23.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`0`[1], output_unit_0_to_23.io.credit_available[1] connect ingress_unit_3_from_14.io.out_credit_available.`0`[2], output_unit_0_to_23.io.credit_available[2] connect ingress_unit_3_from_14.io.out_credit_available.`0`[3], output_unit_0_to_23.io.credit_available[3] connect ingress_unit_3_from_14.io.out_credit_available.`0`[4], output_unit_0_to_23.io.credit_available[4] connect ingress_unit_3_from_14.io.out_credit_available.`0`[5], output_unit_0_to_23.io.credit_available[5] connect ingress_unit_3_from_14.io.out_credit_available.`0`[6], output_unit_0_to_23.io.credit_available[6] connect ingress_unit_3_from_14.io.out_credit_available.`0`[7], output_unit_0_to_23.io.credit_available[7] connect ingress_unit_3_from_14.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] connect ingress_unit_3_from_14.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_23.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_12.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_13.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], ingress_unit_3_from_14.io.salloc_req[0] connect output_unit_0_to_23.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_23.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_23.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_23.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_23.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_23.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_23.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_23.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_23.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_23.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_23.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_23.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_23.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_23.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_23.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_23.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect egress_unit_1_to_8.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_8.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_23.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_12.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_13.io.out[0] connect switch.io.in.`3`[0], ingress_unit_3_from_14.io.out[0] connect output_unit_0_to_23.io.in, switch.io.out.`0` connect egress_unit_1_to_8.io.in, switch.io.out.`1` connect egress_unit_2_to_9.io.in, switch.io.out.`2` reg REG : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect input_unit_0_from_23.io.block, UInt<1>(0h0) connect ingress_unit_1_from_12.io.block, UInt<1>(0h0) connect ingress_unit_2_from_13.io.block, UInt<1>(0h0) connect ingress_unit_3_from_14.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_23.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_12.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_13.io.debug.va_stall connect debugNodeOut.va_stall[3], ingress_unit_3_from_14.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_23.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_12.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_13.io.debug.sa_stall connect debugNodeOut.sa_stall[3], ingress_unit_3_from_14.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_25 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 23 7 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i12 7 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i13 7 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(ingressNodesIn_2.flit.ready, ingressNodesIn_2.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d i14 7 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e8 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 7 e9 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47

module Router_7( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_2_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_2_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [5:0] auto_ingress_nodes_in_2_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_2_to_9_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_9_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_9_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_8_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_23_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_23_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _ingress_unit_3_from_14_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_3_from_14_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_3_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_3_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_3_from_14_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_13_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_13_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_13_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_13_io_in_ready; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_1_from_12_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_1_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_12_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_23_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_23_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_23_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_23_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_23_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_12_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_13_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _ingress_unit_3_from_14_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_6 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]

Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_NoOutput_8 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset

module BundleBridgeNexus_NoOutput_8(); // @[BundleBridgeNexus.scala:20:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLUARTClockSinkDomain : output auto : { uart_0_int_xing_out : { sync : UInt<1>[1]}, flip uart_0_control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, uart_0_io_out : { txd : UInt<1>, flip rxd : UInt<1>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst uart_0 of TLUART connect uart_0.clock, childClock connect uart_0.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect clockNodeIn, auto.clock_in connect uart_0.auto.io_out.rxd, auto.uart_0_io_out.rxd connect auto.uart_0_io_out.txd, uart_0.auto.io_out.txd connect uart_0.auto.control_xing_in, auto.uart_0_control_xing_in connect auto.uart_0_int_xing_out, uart_0.auto.int_xing_out connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset

module TLUARTClockSinkDomain( // @[ClockDomain.scala:14:9] output auto_uart_0_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_uart_0_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_uart_0_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_uart_0_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_uart_0_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [13:0] auto_uart_0_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_uart_0_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_uart_0_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_uart_0_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_uart_0_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_uart_0_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_uart_0_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_uart_0_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [13:0] auto_uart_0_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_uart_0_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_uart_0_io_out_txd, // @[LazyModuleImp.scala:107:25] input auto_uart_0_io_out_rxd, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); TLUART uart_0 ( // @[UART.scala:271:51] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_int_xing_out_sync_0 (auto_uart_0_int_xing_out_sync_0), .auto_control_xing_in_a_ready (auto_uart_0_control_xing_in_a_ready), .auto_control_xing_in_a_valid (auto_uart_0_control_xing_in_a_valid), .auto_control_xing_in_a_bits_opcode (auto_uart_0_control_xing_in_a_bits_opcode), .auto_control_xing_in_a_bits_param (auto_uart_0_control_xing_in_a_bits_param), .auto_control_xing_in_a_bits_size (auto_uart_0_control_xing_in_a_bits_size), .auto_control_xing_in_a_bits_source (auto_uart_0_control_xing_in_a_bits_source), .auto_control_xing_in_a_bits_address (auto_uart_0_control_xing_in_a_bits_address), .auto_control_xing_in_a_bits_mask (auto_uart_0_control_xing_in_a_bits_mask), .auto_control_xing_in_a_bits_data (auto_uart_0_control_xing_in_a_bits_data), .auto_control_xing_in_a_bits_corrupt (auto_uart_0_control_xing_in_a_bits_corrupt), .auto_control_xing_in_d_ready (auto_uart_0_control_xing_in_d_ready), .auto_control_xing_in_d_valid (auto_uart_0_control_xing_in_d_valid), .auto_control_xing_in_d_bits_opcode (auto_uart_0_control_xing_in_d_bits_opcode), .auto_control_xing_in_d_bits_size (auto_uart_0_control_xing_in_d_bits_size), .auto_control_xing_in_d_bits_source (auto_uart_0_control_xing_in_d_bits_source), .auto_control_xing_in_d_bits_data (auto_uart_0_control_xing_in_d_bits_data), .auto_io_out_txd (auto_uart_0_io_out_txd), .auto_io_out_rxd (auto_uart_0_io_out_rxd) ); // @[UART.scala:271:51] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module TilePRCIDomain_1 : output auto : { intsink_out_2 : UInt<1>[1], intsink_out_1 : UInt<1>[1], intsink_out_0 : UInt<1>[1], flip intsink_in : { sync : UInt<1>[1]}, element_reset_domain_boom_l1_tracegen_status_out : { timeout : { valid : UInt<1>, bits : UInt<4>}, error : { valid : UInt<1>, bits : UInt<4>}}, element_reset_domain_boom_l1_tracegen_trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, element_reset_domain_boom_l1_tracegen_trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip element_reset_domain_boom_l1_tracegen_reset_vector_in : UInt<32>, flip element_reset_domain_boom_l1_tracegen_hartid_in : UInt<1>, flip int_in_clock_xing_in_2 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_1 : { sync : UInt<1>[1]}, flip int_in_clock_xing_in_0 : { sync : UInt<1>[2]}, tl_master_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip tap_clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst element_reset_domain of HierarchicalElementResetDomain_1 inst clockNode of FixedClockBroadcast_1_4 inst buffer of TLBuffer_a32d64s4k3z4c_3 connect buffer.clock, childClock connect buffer.reset, childReset inst buffer_1 of TLBuffer_6 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst intsink of IntSyncAsyncCrossingSink_n1x1_1 connect intsink.clock, childClock connect intsink.reset, childReset inst intsink_1 of IntSyncSyncCrossingSink_n1x2_1 inst intsink_2 of IntSyncSyncCrossingSink_n1x1_5 inst intsink_3 of IntSyncSyncCrossingSink_n1x1_6 inst intsink_4 of IntSyncSyncCrossingSink_n1x1_7 inst intsource of IntSyncCrossingSource_n1x1_3 connect intsource.clock, childClock connect intsource.reset, childReset inst intsink_5 of IntSyncSyncCrossingSink_n1x1_8 inst intsource_1 of IntSyncCrossingSource_n1x1_4 connect intsource_1.clock, childClock connect intsource_1.reset, childReset inst intsink_6 of IntSyncSyncCrossingSink_n1x1_9 inst intsource_2 of IntSyncCrossingSource_n1x1_5 connect intsource_2.clock, childClock connect intsource_2.reset, childReset wire tapClockNodeOut : { clock : Clock, reset : Reset} invalidate tapClockNodeOut.reset invalidate tapClockNodeOut.clock wire tapClockNodeIn : { clock : Clock, reset : Reset} invalidate tapClockNodeIn.reset invalidate tapClockNodeIn.clock connect tapClockNodeOut, tapClockNodeIn wire tlMasterClockXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlMasterClockXingOut.e.bits.sink invalidate tlMasterClockXingOut.e.valid invalidate tlMasterClockXingOut.e.ready invalidate tlMasterClockXingOut.d.bits.corrupt invalidate tlMasterClockXingOut.d.bits.data invalidate tlMasterClockXingOut.d.bits.denied invalidate tlMasterClockXingOut.d.bits.sink invalidate tlMasterClockXingOut.d.bits.source invalidate tlMasterClockXingOut.d.bits.size invalidate tlMasterClockXingOut.d.bits.param invalidate tlMasterClockXingOut.d.bits.opcode invalidate tlMasterClockXingOut.d.valid invalidate tlMasterClockXingOut.d.ready invalidate tlMasterClockXingOut.c.bits.corrupt invalidate tlMasterClockXingOut.c.bits.data invalidate tlMasterClockXingOut.c.bits.address invalidate tlMasterClockXingOut.c.bits.source invalidate tlMasterClockXingOut.c.bits.size invalidate tlMasterClockXingOut.c.bits.param invalidate tlMasterClockXingOut.c.bits.opcode invalidate tlMasterClockXingOut.c.valid invalidate tlMasterClockXingOut.c.ready invalidate tlMasterClockXingOut.b.bits.corrupt invalidate tlMasterClockXingOut.b.bits.data invalidate tlMasterClockXingOut.b.bits.mask invalidate tlMasterClockXingOut.b.bits.address invalidate tlMasterClockXingOut.b.bits.source invalidate tlMasterClockXingOut.b.bits.size invalidate tlMasterClockXingOut.b.bits.param invalidate tlMasterClockXingOut.b.bits.opcode invalidate tlMasterClockXingOut.b.valid invalidate tlMasterClockXingOut.b.ready invalidate tlMasterClockXingOut.a.bits.corrupt invalidate tlMasterClockXingOut.a.bits.data invalidate tlMasterClockXingOut.a.bits.mask invalidate tlMasterClockXingOut.a.bits.address invalidate tlMasterClockXingOut.a.bits.source invalidate tlMasterClockXingOut.a.bits.size invalidate tlMasterClockXingOut.a.bits.param invalidate tlMasterClockXingOut.a.bits.opcode invalidate tlMasterClockXingOut.a.valid invalidate tlMasterClockXingOut.a.ready wire tlMasterClockXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate tlMasterClockXingIn.e.bits.sink invalidate tlMasterClockXingIn.e.valid invalidate tlMasterClockXingIn.e.ready invalidate tlMasterClockXingIn.d.bits.corrupt invalidate tlMasterClockXingIn.d.bits.data invalidate tlMasterClockXingIn.d.bits.denied invalidate tlMasterClockXingIn.d.bits.sink invalidate tlMasterClockXingIn.d.bits.source invalidate tlMasterClockXingIn.d.bits.size invalidate tlMasterClockXingIn.d.bits.param invalidate tlMasterClockXingIn.d.bits.opcode invalidate tlMasterClockXingIn.d.valid invalidate tlMasterClockXingIn.d.ready invalidate tlMasterClockXingIn.c.bits.corrupt invalidate tlMasterClockXingIn.c.bits.data invalidate tlMasterClockXingIn.c.bits.address invalidate tlMasterClockXingIn.c.bits.source invalidate tlMasterClockXingIn.c.bits.size invalidate tlMasterClockXingIn.c.bits.param invalidate tlMasterClockXingIn.c.bits.opcode invalidate tlMasterClockXingIn.c.valid invalidate tlMasterClockXingIn.c.ready invalidate tlMasterClockXingIn.b.bits.corrupt invalidate tlMasterClockXingIn.b.bits.data invalidate tlMasterClockXingIn.b.bits.mask invalidate tlMasterClockXingIn.b.bits.address invalidate tlMasterClockXingIn.b.bits.source invalidate tlMasterClockXingIn.b.bits.size invalidate tlMasterClockXingIn.b.bits.param invalidate tlMasterClockXingIn.b.bits.opcode invalidate tlMasterClockXingIn.b.valid invalidate tlMasterClockXingIn.b.ready invalidate tlMasterClockXingIn.a.bits.corrupt invalidate tlMasterClockXingIn.a.bits.data invalidate tlMasterClockXingIn.a.bits.mask invalidate tlMasterClockXingIn.a.bits.address invalidate tlMasterClockXingIn.a.bits.source invalidate tlMasterClockXingIn.a.bits.size invalidate tlMasterClockXingIn.a.bits.param invalidate tlMasterClockXingIn.a.bits.opcode invalidate tlMasterClockXingIn.a.valid invalidate tlMasterClockXingIn.a.ready connect tlMasterClockXingOut, tlMasterClockXingIn wire intInClockXingOut : { sync : UInt<1>[2]} invalidate intInClockXingOut.sync[0] invalidate intInClockXingOut.sync[1] wire intInClockXingIn : { sync : UInt<1>[2]} invalidate intInClockXingIn.sync[0] invalidate intInClockXingIn.sync[1] connect intInClockXingOut, intInClockXingIn wire intInClockXingOut_1 : { sync : UInt<1>[1]} invalidate intInClockXingOut_1.sync[0] wire intInClockXingIn_1 : { sync : UInt<1>[1]} invalidate intInClockXingIn_1.sync[0] connect intInClockXingOut_1, intInClockXingIn_1 wire intInClockXingOut_2 : { sync : UInt<1>[1]} invalidate intInClockXingOut_2.sync[0] wire intInClockXingIn_2 : { sync : UInt<1>[1]} invalidate intInClockXingIn_2.sync[0] connect intInClockXingOut_2, intInClockXingIn_2 wire intOutClockXingOut : { sync : UInt<1>[1]} invalidate intOutClockXingOut.sync[0] wire intOutClockXingIn : { sync : UInt<1>[1]} invalidate intOutClockXingIn.sync[0] connect intOutClockXingOut, intOutClockXingIn wire intOutClockXingOut_1 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_1.sync[0] wire intOutClockXingIn_1 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_1.sync[0] connect intOutClockXingOut_1, intOutClockXingIn_1 wire intOutClockXingOut_2 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_2.sync[0] wire intOutClockXingIn_2 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_2.sync[0] connect intOutClockXingOut_2, intOutClockXingIn_2 wire intOutClockXingOut_3 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_3.sync[0] wire intOutClockXingIn_3 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_3.sync[0] connect intOutClockXingOut_3, intOutClockXingIn_3 wire intOutClockXingOut_4 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_4.sync[0] wire intOutClockXingIn_4 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_4.sync[0] connect intOutClockXingOut_4, intOutClockXingIn_4 wire intOutClockXingOut_5 : { sync : UInt<1>[1]} invalidate intOutClockXingOut_5.sync[0] wire intOutClockXingIn_5 : { sync : UInt<1>[1]} invalidate intOutClockXingIn_5.sync[0] connect intOutClockXingOut_5, intOutClockXingIn_5 connect clockNode.auto.anon_in, tapClockNodeOut connect element_reset_domain.auto.clock_in, clockNode.auto.anon_out connect intsource.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_halt_out[0] connect intsource_2.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_cease_out[0] connect intsource_1.auto.in[0], element_reset_domain.auto.boom_l1_tracegen_wfi_out[0] connect buffer.auto.in, element_reset_domain.auto.boom_l1_tracegen_buffer_out connect tlMasterClockXingIn.e.bits, buffer.auto.out.e.bits connect tlMasterClockXingIn.e.valid, buffer.auto.out.e.valid connect buffer.auto.out.e.ready, tlMasterClockXingIn.e.ready connect buffer.auto.out.d, tlMasterClockXingIn.d connect tlMasterClockXingIn.c.bits, buffer.auto.out.c.bits connect tlMasterClockXingIn.c.valid, buffer.auto.out.c.valid connect buffer.auto.out.c.ready, tlMasterClockXingIn.c.ready connect buffer.auto.out.b, tlMasterClockXingIn.b connect tlMasterClockXingIn.a.bits, buffer.auto.out.a.bits connect tlMasterClockXingIn.a.valid, buffer.auto.out.a.valid connect buffer.auto.out.a.ready, tlMasterClockXingIn.a.ready connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_0[0], intsink.auto.out[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_1[0], intsink_1.auto.out[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_1[1], intsink_1.auto.out[1] connect intsink_1.auto.in.sync[0], intInClockXingOut.sync[0] connect intsink_1.auto.in.sync[1], intInClockXingOut.sync[1] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_2[0], intsink_2.auto.out[0] connect intsink_2.auto.in.sync[0], intInClockXingOut_1.sync[0] connect element_reset_domain.auto.boom_l1_tracegen_int_local_in_3[0], intsink_3.auto.out[0] connect intsink_3.auto.in.sync[0], intInClockXingOut_2.sync[0] connect intsink_4.auto.in.sync[0], intOutClockXingOut.sync[0] connect intOutClockXingIn, intOutClockXingOut_1 connect intOutClockXingIn_1, intsource.auto.out connect intsink_5.auto.in.sync[0], intOutClockXingOut_2.sync[0] connect intOutClockXingIn_2, intOutClockXingOut_3 connect intOutClockXingIn_3, intsource_1.auto.out connect intsink_6.auto.in.sync[0], intOutClockXingOut_4.sync[0] connect intOutClockXingIn_4, intOutClockXingOut_5 connect intOutClockXingIn_5, intsource_2.auto.out connect tapClockNodeIn, auto.tap_clock_in connect auto.tl_master_clock_xing_out, tlMasterClockXingOut connect intInClockXingIn, auto.int_in_clock_xing_in_0 connect intInClockXingIn_1, auto.int_in_clock_xing_in_1 connect intInClockXingIn_2, auto.int_in_clock_xing_in_2 connect element_reset_domain.auto.boom_l1_tracegen_hartid_in, auto.element_reset_domain_boom_l1_tracegen_hartid_in connect element_reset_domain.auto.boom_l1_tracegen_reset_vector_in, auto.element_reset_domain_boom_l1_tracegen_reset_vector_in connect auto.element_reset_domain_boom_l1_tracegen_trace_source_out.time, element_reset_domain.auto.boom_l1_tracegen_trace_source_out.time connect auto.element_reset_domain_boom_l1_tracegen_trace_source_out.insns, element_reset_domain.auto.boom_l1_tracegen_trace_source_out.insns connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.cause, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.cause connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.tval, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.tval connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.priv, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.priv connect auto.element_reset_domain_boom_l1_tracegen_trace_core_source_out.group, element_reset_domain.auto.boom_l1_tracegen_trace_core_source_out.group connect auto.element_reset_domain_boom_l1_tracegen_status_out, element_reset_domain.auto.boom_l1_tracegen_status_out connect intsink.auto.in.sync[0], auto.intsink_in.sync[0] connect auto.intsink_out_0, intsink_4.auto.out connect auto.intsink_out_1, intsink_5.auto.out connect auto.intsink_out_2, intsink_6.auto.out connect childClock, tapClockNodeIn.clock connect childReset, tapClockNodeIn.reset connect clock, tapClockNodeIn.clock connect reset, tapClockNodeIn.reset

module TilePRCIDomain_1( // @[ClockDomain.scala:14:9] output auto_intsink_out_2_0, // @[LazyModuleImp.scala:107:25] output auto_intsink_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid, // @[LazyModuleImp.scala:107:25] input auto_element_reset_domain_boom_l1_tracegen_hartid_in, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_master_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_master_clock_xing_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_master_clock_xing_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_master_clock_xing_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_master_clock_xing_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_master_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_master_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_master_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_master_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_master_clock_xing_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_master_clock_xing_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_master_clock_xing_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_tap_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_hartid_in_0 = auto_element_reset_domain_boom_l1_tracegen_hartid_in; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_ready_0 = auto_tl_master_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_valid_0 = auto_tl_master_clock_xing_out_b_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_b_bits_param_0 = auto_tl_master_clock_xing_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_b_bits_source_0 = auto_tl_master_clock_xing_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_b_bits_address_0 = auto_tl_master_clock_xing_out_b_bits_address; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_ready_0 = auto_tl_master_clock_xing_out_c_ready; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_valid_0 = auto_tl_master_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_opcode_0 = auto_tl_master_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_tl_master_clock_xing_out_d_bits_param_0 = auto_tl_master_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_size_0 = auto_tl_master_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_d_bits_source_0 = auto_tl_master_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_d_bits_sink_0 = auto_tl_master_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_denied_0 = auto_tl_master_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_d_bits_data_0 = auto_tl_master_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_bits_corrupt_0 = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_ready_0 = auto_tl_master_clock_xing_out_e_ready; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_clock_0 = auto_tap_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_tap_clock_in_reset_0 = auto_tap_clock_in_reset; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_status_out_error_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_status_out_error_bits = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_itype = 4'h0; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_priv = 4'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] auto_element_reset_domain_boom_l1_tracegen_reset_vector_in = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_iaddr = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_tval = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_cause = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_insn = 32'h0; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_reset_vector_in = 32'h0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_iaddr = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_tval = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_iaddr = 40'h0; // @[ClockDomain.scala:14:9] wire [39:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_tval = 40'h0; // @[ClockDomain.scala:14:9] wire [2:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_priv = 3'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_element_reset_domain_boom_l1_tracegen_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_cause = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_trace_source_out_time = 64'h0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [2:0] auto_tl_master_clock_xing_out_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [3:0] auto_tl_master_clock_xing_out_b_bits_size = 4'h6; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_size = 4'h6; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingIn_b_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [7:0] auto_tl_master_clock_xing_out_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire auto_intsink_out_1_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_intsink_in_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_status_out_error_valid = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_2_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_1_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_0 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_int_in_clock_xing_in_0_sync_1 = 1'h0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_status_out_error_valid = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_wfi_out_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_3_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_2_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_1_0 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_1_1 = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_iretire = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_core_source_out_group_0_ilastsize = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_valid = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_exception = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_trace_source_out_insns_0_interrupt = 1'h0; // @[ClockDomain.scala:14:9] wire element_reset_domain__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tlMasterClockXingOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire tlMasterClockXingIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingOut_sync_1 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingIn_sync_1 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_1_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_1_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intInClockXingOut_2_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intInClockXingIn_2_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_2_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_2_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_3_sync_0 = 1'h0; // @[MixedNode.scala:542:17] wire intOutClockXingIn_3_sync_0 = 1'h0; // @[MixedNode.scala:551:17] wire element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_hartid_in = auto_element_reset_domain_boom_l1_tracegen_hartid_in_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_ready = auto_tl_master_clock_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_b_valid = auto_tl_master_clock_xing_out_b_valid_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_b_bits_source = auto_tl_master_clock_xing_out_b_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingOut_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_ready = auto_tl_master_clock_xing_out_c_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17] wire tlMasterClockXingOut_d_valid = auto_tl_master_clock_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] tlMasterClockXingOut_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingOut_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingOut_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingOut_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_ready = auto_tl_master_clock_xing_out_e_ready_0; // @[ClockDomain.scala:14:9] wire tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17] wire tapClockNodeIn_clock = auto_tap_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_2_0_0; // @[ClockDomain.scala:14:9] wire tapClockNodeIn_reset = auto_tap_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_intsink_out_0_0_0; // @[ClockDomain.scala:14:9] wire auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0 = element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire element_reset_domain_clockNodeIn_clock = element_reset_domain_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_clockNodeIn_reset = element_reset_domain_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_cease_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_halt_out_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0; // @[ClockDomain.scala:14:9] wire element_reset_domain_childClock; // @[LazyModuleImp.scala:155:31] wire element_reset_domain_childReset; // @[LazyModuleImp.scala:158:31] assign element_reset_domain_childClock = element_reset_domain_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign element_reset_domain_childReset = element_reset_domain_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire tapClockNodeOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_clock = clockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire tapClockNodeOut_reset; // @[MixedNode.scala:542:17] wire clockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire clockNode_anonIn_reset = clockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] assign element_reset_domain_auto_clock_in_clock = clockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign element_reset_domain_auto_clock_in_reset = clockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_clock = clockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_out_reset = clockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign clockNode_anonOut_clock = clockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNode_anonOut_reset = clockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNode_auto_anon_in_clock = tapClockNodeOut_clock; // @[ClockGroup.scala:104:9] assign clockNode_auto_anon_in_reset = tapClockNodeOut_reset; // @[ClockGroup.scala:104:9] assign childClock = tapClockNodeIn_clock; // @[MixedNode.scala:551:17] assign tapClockNodeOut_clock = tapClockNodeIn_clock; // @[MixedNode.scala:542:17, :551:17] assign childReset = tapClockNodeIn_reset; // @[MixedNode.scala:551:17] assign tapClockNodeOut_reset = tapClockNodeIn_reset; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_ready = tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_a_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_valid_0 = tlMasterClockXingOut_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_opcode_0 = tlMasterClockXingOut_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_param_0 = tlMasterClockXingOut_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_size_0 = tlMasterClockXingOut_a_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_source_0 = tlMasterClockXingOut_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_address_0 = tlMasterClockXingOut_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_mask_0 = tlMasterClockXingOut_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_data_0 = tlMasterClockXingOut_a_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_a_bits_corrupt_0 = tlMasterClockXingOut_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_b_ready_0 = tlMasterClockXingOut_b_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_b_valid = tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_b_bits_param = tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_b_bits_source = tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [31:0] tlMasterClockXingIn_b_bits_address = tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_ready = tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_c_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_valid_0 = tlMasterClockXingOut_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_opcode_0 = tlMasterClockXingOut_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_param_0 = tlMasterClockXingOut_c_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_size_0 = tlMasterClockXingOut_c_bits_size; // @[ClockDomain.scala:14:9] wire [3:0] tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_source_0 = tlMasterClockXingOut_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_address_0 = tlMasterClockXingOut_c_bits_address; // @[ClockDomain.scala:14:9] wire [63:0] tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_data_0 = tlMasterClockXingOut_c_bits_data; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_c_bits_corrupt_0 = tlMasterClockXingOut_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_ready; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_d_ready_0 = tlMasterClockXingOut_d_ready; // @[ClockDomain.scala:14:9] wire tlMasterClockXingIn_d_valid = tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_opcode = tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] wire [1:0] tlMasterClockXingIn_d_bits_param = tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_size = tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] wire [3:0] tlMasterClockXingIn_d_bits_source = tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlMasterClockXingIn_d_bits_sink = tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_denied = tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] wire [63:0] tlMasterClockXingIn_d_bits_data = tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_d_bits_corrupt = tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_ready = tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17] wire tlMasterClockXingIn_e_valid; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_valid_0 = tlMasterClockXingOut_e_valid; // @[ClockDomain.scala:14:9] wire [2:0] tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_master_clock_xing_out_e_bits_sink_0 = tlMasterClockXingOut_e_bits_sink; // @[ClockDomain.scala:14:9] assign tlMasterClockXingOut_a_valid = tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_opcode = tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_param = tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_size = tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_source = tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_address = tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_mask = tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_data = tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_a_bits_corrupt = tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_b_ready = tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_valid = tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_opcode = tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_param = tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_size = tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_source = tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_address = tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_data = tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_c_bits_corrupt = tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_d_ready = tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_valid = tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign tlMasterClockXingOut_e_bits_sink = tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_1_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_sync_0 = intOutClockXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_1_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_sync_0 = intOutClockXingOut_1_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_1_sync_0 = intOutClockXingIn_1_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_4_sync_0; // @[MixedNode.scala:551:17] wire intOutClockXingOut_4_sync_0; // @[MixedNode.scala:542:17] wire intOutClockXingOut_5_sync_0; // @[MixedNode.scala:542:17] assign intOutClockXingOut_4_sync_0 = intOutClockXingIn_4_sync_0; // @[MixedNode.scala:542:17, :551:17] wire intOutClockXingIn_5_sync_0; // @[MixedNode.scala:551:17] assign intOutClockXingIn_4_sync_0 = intOutClockXingOut_5_sync_0; // @[MixedNode.scala:542:17, :551:17] assign intOutClockXingOut_5_sync_0 = intOutClockXingIn_5_sync_0; // @[MixedNode.scala:542:17, :551:17] BoomTraceGenTile_1 element_reset_domain_boom_l1_tracegen ( // @[HasTiles.scala:164:59] .clock (element_reset_domain_childClock), // @[LazyModuleImp.scala:155:31] .reset (element_reset_domain_childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data), .auto_buffer_out_b_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready), .auto_buffer_out_b_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_b_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_c_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid), .auto_buffer_out_c_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode), .auto_buffer_out_c_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param), .auto_buffer_out_c_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size), .auto_buffer_out_c_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source), .auto_buffer_out_c_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address), .auto_buffer_out_c_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data), .auto_buffer_out_d_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready), .auto_buffer_out_d_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_denied (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready), // @[ClockDomain.scala:14:9] .auto_buffer_out_e_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid), .auto_buffer_out_e_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink), .auto_status_out_timeout_valid (element_reset_domain_auto_boom_l1_tracegen_status_out_timeout_valid), .auto_cease_out_0 (element_reset_domain_auto_boom_l1_tracegen_cease_out_0), .auto_halt_out_0 (element_reset_domain_auto_boom_l1_tracegen_halt_out_0), .auto_int_local_in_0_0 (element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0), // @[ClockDomain.scala:14:9] .auto_hartid_in (element_reset_domain_auto_boom_l1_tracegen_hartid_in) // @[ClockDomain.scala:14:9] ); // @[HasTiles.scala:164:59] TLBuffer_a32d64s4k3z4c_3 buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_ready), .auto_in_a_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_valid), // @[ClockDomain.scala:14:9] .auto_in_a_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_a_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_param), // @[ClockDomain.scala:14:9] .auto_in_a_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_size), // @[ClockDomain.scala:14:9] .auto_in_a_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_source), // @[ClockDomain.scala:14:9] .auto_in_a_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_address), // @[ClockDomain.scala:14:9] .auto_in_a_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_mask), // @[ClockDomain.scala:14:9] .auto_in_a_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_a_bits_data), // @[ClockDomain.scala:14:9] .auto_in_b_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_ready), // @[ClockDomain.scala:14:9] .auto_in_b_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_valid), .auto_in_b_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_opcode), .auto_in_b_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_param), .auto_in_b_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_size), .auto_in_b_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_source), .auto_in_b_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_address), .auto_in_b_bits_mask (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_mask), .auto_in_b_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_data), .auto_in_b_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_b_bits_corrupt), .auto_in_c_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_ready), .auto_in_c_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_valid), // @[ClockDomain.scala:14:9] .auto_in_c_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_opcode), // @[ClockDomain.scala:14:9] .auto_in_c_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_param), // @[ClockDomain.scala:14:9] .auto_in_c_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_size), // @[ClockDomain.scala:14:9] .auto_in_c_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_source), // @[ClockDomain.scala:14:9] .auto_in_c_bits_address (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_address), // @[ClockDomain.scala:14:9] .auto_in_c_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_c_bits_data), // @[ClockDomain.scala:14:9] .auto_in_d_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_ready), // @[ClockDomain.scala:14:9] .auto_in_d_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_valid), .auto_in_d_bits_opcode (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_opcode), .auto_in_d_bits_param (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_param), .auto_in_d_bits_size (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_size), .auto_in_d_bits_source (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_source), .auto_in_d_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_sink), .auto_in_d_bits_denied (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_denied), .auto_in_d_bits_data (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_data), .auto_in_d_bits_corrupt (element_reset_domain_auto_boom_l1_tracegen_buffer_out_d_bits_corrupt), .auto_in_e_ready (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_ready), .auto_in_e_valid (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_valid), // @[ClockDomain.scala:14:9] .auto_in_e_bits_sink (element_reset_domain_auto_boom_l1_tracegen_buffer_out_e_bits_sink), // @[ClockDomain.scala:14:9] .auto_out_a_ready (tlMasterClockXingIn_a_ready), // @[MixedNode.scala:551:17] .auto_out_a_valid (tlMasterClockXingIn_a_valid), .auto_out_a_bits_opcode (tlMasterClockXingIn_a_bits_opcode), .auto_out_a_bits_param (tlMasterClockXingIn_a_bits_param), .auto_out_a_bits_size (tlMasterClockXingIn_a_bits_size), .auto_out_a_bits_source (tlMasterClockXingIn_a_bits_source), .auto_out_a_bits_address (tlMasterClockXingIn_a_bits_address), .auto_out_a_bits_mask (tlMasterClockXingIn_a_bits_mask), .auto_out_a_bits_data (tlMasterClockXingIn_a_bits_data), .auto_out_a_bits_corrupt (tlMasterClockXingIn_a_bits_corrupt), .auto_out_b_ready (tlMasterClockXingIn_b_ready), .auto_out_b_valid (tlMasterClockXingIn_b_valid), // @[MixedNode.scala:551:17] .auto_out_b_bits_param (tlMasterClockXingIn_b_bits_param), // @[MixedNode.scala:551:17] .auto_out_b_bits_source (tlMasterClockXingIn_b_bits_source), // @[MixedNode.scala:551:17] .auto_out_b_bits_address (tlMasterClockXingIn_b_bits_address), // @[MixedNode.scala:551:17] .auto_out_c_ready (tlMasterClockXingIn_c_ready), // @[MixedNode.scala:551:17] .auto_out_c_valid (tlMasterClockXingIn_c_valid), .auto_out_c_bits_opcode (tlMasterClockXingIn_c_bits_opcode), .auto_out_c_bits_param (tlMasterClockXingIn_c_bits_param), .auto_out_c_bits_size (tlMasterClockXingIn_c_bits_size), .auto_out_c_bits_source (tlMasterClockXingIn_c_bits_source), .auto_out_c_bits_address (tlMasterClockXingIn_c_bits_address), .auto_out_c_bits_data (tlMasterClockXingIn_c_bits_data), .auto_out_c_bits_corrupt (tlMasterClockXingIn_c_bits_corrupt), .auto_out_d_ready (tlMasterClockXingIn_d_ready), .auto_out_d_valid (tlMasterClockXingIn_d_valid), // @[MixedNode.scala:551:17] .auto_out_d_bits_opcode (tlMasterClockXingIn_d_bits_opcode), // @[MixedNode.scala:551:17] .auto_out_d_bits_param (tlMasterClockXingIn_d_bits_param), // @[MixedNode.scala:551:17] .auto_out_d_bits_size (tlMasterClockXingIn_d_bits_size), // @[MixedNode.scala:551:17] .auto_out_d_bits_source (tlMasterClockXingIn_d_bits_source), // @[MixedNode.scala:551:17] .auto_out_d_bits_sink (tlMasterClockXingIn_d_bits_sink), // @[MixedNode.scala:551:17] .auto_out_d_bits_denied (tlMasterClockXingIn_d_bits_denied), // @[MixedNode.scala:551:17] .auto_out_d_bits_data (tlMasterClockXingIn_d_bits_data), // @[MixedNode.scala:551:17] .auto_out_d_bits_corrupt (tlMasterClockXingIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .auto_out_e_ready (tlMasterClockXingIn_e_ready), // @[MixedNode.scala:551:17] .auto_out_e_valid (tlMasterClockXingIn_e_valid), .auto_out_e_bits_sink (tlMasterClockXingIn_e_bits_sink) ); // @[Buffer.scala:75:28] TLBuffer_6 buffer_1 ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Buffer.scala:75:28] IntSyncAsyncCrossingSink_n1x1_1 intsink ( // @[Crossing.scala:86:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_out_0 (element_reset_domain_auto_boom_l1_tracegen_int_local_in_0_0) ); // @[Crossing.scala:86:29] IntSyncSyncCrossingSink_n1x2_1 intsink_1 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_5 intsink_2 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_6 intsink_3 (); // @[Crossing.scala:109:29] IntSyncSyncCrossingSink_n1x1_7 intsink_4 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_0_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_3 intsource ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_boom_l1_tracegen_halt_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_1_sync_0) ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_8 intsink_5 (); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_4 intsource_1 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset) // @[LazyModuleImp.scala:158:31] ); // @[Crossing.scala:29:31] IntSyncSyncCrossingSink_n1x1_9 intsink_6 ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intOutClockXingOut_4_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (auto_intsink_out_2_0_0) ); // @[Crossing.scala:109:29] IntSyncCrossingSource_n1x1_5 intsource_2 ( // @[Crossing.scala:29:31] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_0 (element_reset_domain_auto_boom_l1_tracegen_cease_out_0), // @[ClockDomain.scala:14:9] .auto_out_sync_0 (intOutClockXingIn_5_sync_0) ); // @[Crossing.scala:29:31] assign auto_intsink_out_2_0 = auto_intsink_out_2_0_0; // @[ClockDomain.scala:14:9] assign auto_intsink_out_0_0 = auto_intsink_out_0_0_0; // @[ClockDomain.scala:14:9] assign auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid = auto_element_reset_domain_boom_l1_tracegen_status_out_timeout_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_valid = auto_tl_master_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_opcode = auto_tl_master_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_param = auto_tl_master_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_size = auto_tl_master_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_source = auto_tl_master_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_address = auto_tl_master_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_mask = auto_tl_master_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_data = auto_tl_master_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_a_bits_corrupt = auto_tl_master_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_b_ready = auto_tl_master_clock_xing_out_b_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_valid = auto_tl_master_clock_xing_out_c_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_opcode = auto_tl_master_clock_xing_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_param = auto_tl_master_clock_xing_out_c_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_size = auto_tl_master_clock_xing_out_c_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_source = auto_tl_master_clock_xing_out_c_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_address = auto_tl_master_clock_xing_out_c_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_data = auto_tl_master_clock_xing_out_c_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_c_bits_corrupt = auto_tl_master_clock_xing_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_d_ready = auto_tl_master_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_valid = auto_tl_master_clock_xing_out_e_valid_0; // @[ClockDomain.scala:14:9] assign auto_tl_master_clock_xing_out_e_bits_sink = auto_tl_master_clock_xing_out_e_bits_sink_0; // @[ClockDomain.scala:14:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_108 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_109 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_53( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_211 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip

module PriorityQueueStage_211( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_167 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_181 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_167( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_181 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module RegisterReadDecode_3 : input clock : Clock input reset : Reset output io : { flip iss_valid : UInt<1>, flip iss_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rrd_valid : UInt<1>, rrd_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}} connect io.rrd_uop, io.iss_uop wire rrd_cs : { br_type : UInt<4>, use_alupipe : UInt<1>, use_muldivpipe : UInt<1>, use_mempipe : UInt<1>, op_fcn : UInt<5>, fcn_dw : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, rf_wen : UInt<1>, csr_cmd : UInt<3>} wire rrd_cs_decoder_decoded_plaInput : UInt<7> node rrd_cs_decoder_decoded_invInputs = not(rrd_cs_decoder_decoded_plaInput) wire rrd_cs_decoder_decoded : UInt<25> node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo) node rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1) node rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2) node rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3) node rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4) node rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5) node rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6) node rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_6) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7) node rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_7) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8) node rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_8) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8) node rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_9) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9) node rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_10) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10) node rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_11) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11) node rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_12) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12) node rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_13) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13) node rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_14) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14) node rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_15) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15) node rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_16) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16) node rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_17) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17) node rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_18) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18) node rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_19) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19) node rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_20) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20) node rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_21) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21) node rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_22) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22) node rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_23) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23) node rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_24) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24) node rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_25) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25) node rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_26) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26) node rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_27) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28) node rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_28) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27) node rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_29) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28) node rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_30) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29) node rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_31) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30) node rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_32) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31) node rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_33) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32) node rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_34) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33) node rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_35) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34) node rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_36) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35) node rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_37) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36) node rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_38) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37) node rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_39) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38) node rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_40) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39) node rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_41) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40) node rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_42) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41) node rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_43) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42) node rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_44) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43) node rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_45) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44) node rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_46) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45) node rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_47) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46) node rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_48) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47) node rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_49) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48) node rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_50) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49) node rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_51) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50) node rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_52) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51) node rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_53) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(rrd_cs_decoder_decoded_invInputs, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52) node rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_54) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53) node rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_55) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54) node rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_56) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55) node rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_57) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_58) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56) node rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_59) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57) node rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_60) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(rrd_cs_decoder_decoded_plaInput, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(rrd_cs_decoder_decoded_invInputs, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58) node rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_61) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59) node rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_62) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(rrd_cs_decoder_decoded_plaInput, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60) node rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_63) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(rrd_cs_decoder_decoded_plaInput, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(rrd_cs_decoder_decoded_plaInput, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(rrd_cs_decoder_decoded_invInputs, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61) node rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_64) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(rrd_cs_decoder_decoded_invInputs, 0, 0) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(rrd_cs_decoder_decoded_invInputs, 1, 1) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(rrd_cs_decoder_decoded_invInputs, 2, 2) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(rrd_cs_decoder_decoded_plaInput, 3, 3) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(rrd_cs_decoder_decoded_invInputs, 4, 4) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(rrd_cs_decoder_decoded_plaInput, 5, 5) node rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(rrd_cs_decoder_decoded_plaInput, 6, 6) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22) node rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8) node _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62) node rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_rrd_cs_decoder_decoded_andMatrixOutputs_T_65) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_10_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_28_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_42_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_3) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_2_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_14_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_0_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = orr(rrd_cs_decoder_decoded_andMatrixOutputs_30_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_8) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_10) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_andMatrixOutputs_1_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_16_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_48_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_12) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_39_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_53_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_14) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_17_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_62_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_16) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_3_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_18) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_20) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_49_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_22) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_59_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_8_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_24) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_51_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_26) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = cat(rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2) node _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = orr(_rrd_cs_decoder_decoded_orMatrixOutputs_T_28) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_6) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_7) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_19, _rrd_cs_decoder_decoded_orMatrixOutputs_T_17) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, UInt<1>(0h0)) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_orMatrixOutputs_T_27, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), _rrd_cs_decoder_decoded_orMatrixOutputs_T_29) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6) node rrd_cs_decoder_decoded_orMatrixOutputs = cat(rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 0, 0) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 1, 1) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 2, 2) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 3, 3) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 4, 4) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 5, 5) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 6, 6) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 7, 7) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 8, 8) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 9, 9) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 10, 10) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 11, 11) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 12, 12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_12) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 13, 13) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 14, 14) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 15, 15) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 16, 16) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 17, 17) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 18, 18) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 19, 19) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 20, 20) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = not(_rrd_cs_decoder_decoded_invMatrixOutputs_T_21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 21, 21) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 22, 22) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 23, 23) node _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = bits(rrd_cs_decoder_decoded_orMatrixOutputs, 24, 24) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9) node rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs_hi = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo) node rrd_cs_decoder_decoded_invMatrixOutputs = cat(rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo) connect rrd_cs_decoder_decoded, rrd_cs_decoder_decoded_invMatrixOutputs connect rrd_cs_decoder_decoded_plaInput, io.rrd_uop.uopc node rrd_cs_decoder_0 = bits(rrd_cs_decoder_decoded, 24, 21) node rrd_cs_decoder_1 = bits(rrd_cs_decoder_decoded, 20, 20) node rrd_cs_decoder_2 = bits(rrd_cs_decoder_decoded, 19, 19) node rrd_cs_decoder_3 = bits(rrd_cs_decoder_decoded, 18, 18) node rrd_cs_decoder_4 = bits(rrd_cs_decoder_decoded, 17, 13) node rrd_cs_decoder_5 = bits(rrd_cs_decoder_decoded, 12, 12) node rrd_cs_decoder_6 = bits(rrd_cs_decoder_decoded, 11, 10) node rrd_cs_decoder_7 = bits(rrd_cs_decoder_decoded, 9, 7) node rrd_cs_decoder_8 = bits(rrd_cs_decoder_decoded, 6, 4) node rrd_cs_decoder_9 = bits(rrd_cs_decoder_decoded, 3, 3) node rrd_cs_decoder_10 = bits(rrd_cs_decoder_decoded, 2, 0) connect rrd_cs.br_type, rrd_cs_decoder_0 connect rrd_cs.use_alupipe, rrd_cs_decoder_1 connect rrd_cs.use_muldivpipe, rrd_cs_decoder_2 connect rrd_cs.use_mempipe, rrd_cs_decoder_3 connect rrd_cs.op_fcn, rrd_cs_decoder_4 connect rrd_cs.fcn_dw, rrd_cs_decoder_5 connect rrd_cs.op1_sel, rrd_cs_decoder_6 connect rrd_cs.op2_sel, rrd_cs_decoder_7 connect rrd_cs.imm_sel, rrd_cs_decoder_8 connect rrd_cs.rf_wen, rrd_cs_decoder_9 connect rrd_cs.csr_cmd, rrd_cs_decoder_10 connect io.rrd_uop.ctrl.br_type, rrd_cs.br_type connect io.rrd_uop.ctrl.op1_sel, rrd_cs.op1_sel connect io.rrd_uop.ctrl.op2_sel, rrd_cs.op2_sel connect io.rrd_uop.ctrl.imm_sel, rrd_cs.imm_sel connect io.rrd_uop.ctrl.op_fcn, rrd_cs.op_fcn connect io.rrd_uop.ctrl.fcn_dw, rrd_cs.fcn_dw node _io_rrd_uop_ctrl_is_load_T = eq(io.rrd_uop.uopc, UInt<7>(0h1)) connect io.rrd_uop.ctrl.is_load, _io_rrd_uop_ctrl_is_load_T node _io_rrd_uop_ctrl_is_sta_T = eq(io.rrd_uop.uopc, UInt<7>(0h2)) node _io_rrd_uop_ctrl_is_sta_T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _io_rrd_uop_ctrl_is_sta_T_2 = or(_io_rrd_uop_ctrl_is_sta_T, _io_rrd_uop_ctrl_is_sta_T_1) connect io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_sta_T_2 node _io_rrd_uop_ctrl_is_std_T = eq(io.rrd_uop.uopc, UInt<7>(0h3)) node _io_rrd_uop_ctrl_is_std_T_1 = eq(io.rrd_uop.lrs2_rtype, UInt<2>(0h0)) node _io_rrd_uop_ctrl_is_std_T_2 = and(io.rrd_uop.ctrl.is_sta, _io_rrd_uop_ctrl_is_std_T_1) node _io_rrd_uop_ctrl_is_std_T_3 = or(_io_rrd_uop_ctrl_is_std_T, _io_rrd_uop_ctrl_is_std_T_2) connect io.rrd_uop.ctrl.is_std, _io_rrd_uop_ctrl_is_std_T_3 node _T = eq(io.rrd_uop.uopc, UInt<7>(0h43)) node _T_1 = eq(io.rrd_uop.uopc, UInt<7>(0h1)) node _T_2 = eq(io.rrd_uop.mem_cmd, UInt<3>(0h6)) node _T_3 = and(_T_1, _T_2) node _T_4 = or(_T, _T_3) when _T_4 : connect io.rrd_uop.imm_packed, UInt<1>(0h0) node _csr_ren_T = eq(rrd_cs.csr_cmd, UInt<3>(0h6)) node _csr_ren_T_1 = eq(rrd_cs.csr_cmd, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(io.rrd_uop.prs1, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node _io_rrd_uop_ctrl_csr_cmd_T = mux(csr_ren, UInt<3>(0h2), rrd_cs.csr_cmd) connect io.rrd_uop.ctrl.csr_cmd, _io_rrd_uop_ctrl_csr_cmd_T connect io.rrd_valid, io.iss_valid

module RegisterReadDecode_3( // @[func-unit-decode.scala:307:7] input clock, // @[func-unit-decode.scala:307:7] input reset, // @[func-unit-decode.scala:307:7] input io_iss_valid, // @[func-unit-decode.scala:310:14] input [6:0] io_iss_uop_uopc, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_inst, // @[func-unit-decode.scala:310:14] input [31:0] io_iss_uop_debug_inst, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_rvc, // @[func-unit-decode.scala:310:14] input [39:0] io_iss_uop_debug_pc, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_iq_type, // @[func-unit-decode.scala:310:14] input [9:0] io_iss_uop_fu_code, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] input io_iss_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_iw_state, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_br, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jalr, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_jal, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sfb, // @[func-unit-decode.scala:310:14] input [7:0] io_iss_uop_br_mask, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_br_tag, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ftq_idx, // @[func-unit-decode.scala:310:14] input io_iss_uop_edge_inst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pc_lob, // @[func-unit-decode.scala:310:14] input io_iss_uop_taken, // @[func-unit-decode.scala:310:14] input [19:0] io_iss_uop_imm_packed, // @[func-unit-decode.scala:310:14] input [11:0] io_iss_uop_csr_addr, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_rob_idx, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_ldq_idx, // @[func-unit-decode.scala:310:14] input [2:0] io_iss_uop_stq_idx, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_rxq_idx, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_pdst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_prs3, // @[func-unit-decode.scala:310:14] input [3:0] io_iss_uop_ppred, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs1_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs2_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_prs3_busy, // @[func-unit-decode.scala:310:14] input io_iss_uop_ppred_busy, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_stale_pdst, // @[func-unit-decode.scala:310:14] input io_iss_uop_exception, // @[func-unit-decode.scala:310:14] input [63:0] io_iss_uop_exc_cause, // @[func-unit-decode.scala:310:14] input io_iss_uop_bypassable, // @[func-unit-decode.scala:310:14] input [4:0] io_iss_uop_mem_cmd, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_mem_size, // @[func-unit-decode.scala:310:14] input io_iss_uop_mem_signed, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fence, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_fencei, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_amo, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_ldq, // @[func-unit-decode.scala:310:14] input io_iss_uop_uses_stq, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] input io_iss_uop_is_unique, // @[func-unit-decode.scala:310:14] input io_iss_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_ldst, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs1, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs2, // @[func-unit-decode.scala:310:14] input [5:0] io_iss_uop_lrs3, // @[func-unit-decode.scala:310:14] input io_iss_uop_ldst_val, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_dst_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] input io_iss_uop_frs3_en, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_val, // @[func-unit-decode.scala:310:14] input io_iss_uop_fp_single, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] input io_iss_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] input [1:0] io_iss_uop_debug_tsrc, // @[func-unit-decode.scala:310:14] output io_rrd_valid, // @[func-unit-decode.scala:310:14] output [6:0] io_rrd_uop_uopc, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_inst, // @[func-unit-decode.scala:310:14] output [31:0] io_rrd_uop_debug_inst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_rvc, // @[func-unit-decode.scala:310:14] output [39:0] io_rrd_uop_debug_pc, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_iq_type, // @[func-unit-decode.scala:310:14] output [9:0] io_rrd_uop_fu_code, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ctrl_br_type, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_ctrl_op1_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_op2_sel, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_imm_sel, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_ctrl_op_fcn, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_fcn_dw, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ctrl_csr_cmd, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_load, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_sta, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ctrl_is_std, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_iw_state, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_br, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jalr, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_jal, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sfb, // @[func-unit-decode.scala:310:14] output [7:0] io_rrd_uop_br_mask, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_br_tag, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ftq_idx, // @[func-unit-decode.scala:310:14] output io_rrd_uop_edge_inst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pc_lob, // @[func-unit-decode.scala:310:14] output io_rrd_uop_taken, // @[func-unit-decode.scala:310:14] output [19:0] io_rrd_uop_imm_packed, // @[func-unit-decode.scala:310:14] output [11:0] io_rrd_uop_csr_addr, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_rob_idx, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_ldq_idx, // @[func-unit-decode.scala:310:14] output [2:0] io_rrd_uop_stq_idx, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_rxq_idx, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_pdst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_prs3, // @[func-unit-decode.scala:310:14] output [3:0] io_rrd_uop_ppred, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs1_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs2_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_prs3_busy, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ppred_busy, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_stale_pdst, // @[func-unit-decode.scala:310:14] output io_rrd_uop_exception, // @[func-unit-decode.scala:310:14] output [63:0] io_rrd_uop_exc_cause, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bypassable, // @[func-unit-decode.scala:310:14] output [4:0] io_rrd_uop_mem_cmd, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_mem_size, // @[func-unit-decode.scala:310:14] output io_rrd_uop_mem_signed, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fence, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_fencei, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_amo, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_ldq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_uses_stq, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_sys_pc2epc, // @[func-unit-decode.scala:310:14] output io_rrd_uop_is_unique, // @[func-unit-decode.scala:310:14] output io_rrd_uop_flush_on_commit, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_is_rs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_ldst, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs1, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs2, // @[func-unit-decode.scala:310:14] output [5:0] io_rrd_uop_lrs3, // @[func-unit-decode.scala:310:14] output io_rrd_uop_ldst_val, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_dst_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs1_rtype, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_lrs2_rtype, // @[func-unit-decode.scala:310:14] output io_rrd_uop_frs3_en, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_val, // @[func-unit-decode.scala:310:14] output io_rrd_uop_fp_single, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_pf_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ae_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_xcpt_ma_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_debug_if, // @[func-unit-decode.scala:310:14] output io_rrd_uop_bp_xcpt_if, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_fsrc, // @[func-unit-decode.scala:310:14] output [1:0] io_rrd_uop_debug_tsrc // @[func-unit-decode.scala:310:14] ); wire io_iss_valid_0 = io_iss_valid; // @[func-unit-decode.scala:307:7] wire [6:0] io_iss_uop_uopc_0 = io_iss_uop_uopc; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_inst_0 = io_iss_uop_inst; // @[func-unit-decode.scala:307:7] wire [31:0] io_iss_uop_debug_inst_0 = io_iss_uop_debug_inst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_rvc_0 = io_iss_uop_is_rvc; // @[func-unit-decode.scala:307:7] wire [39:0] io_iss_uop_debug_pc_0 = io_iss_uop_debug_pc; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_iq_type_0 = io_iss_uop_iq_type; // @[func-unit-decode.scala:307:7] wire [9:0] io_iss_uop_fu_code_0 = io_iss_uop_fu_code; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ctrl_br_type_0 = io_iss_uop_ctrl_br_type; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_ctrl_op1_sel_0 = io_iss_uop_ctrl_op1_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_op2_sel_0 = io_iss_uop_ctrl_op2_sel; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_imm_sel_0 = io_iss_uop_ctrl_imm_sel; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_ctrl_op_fcn_0 = io_iss_uop_ctrl_op_fcn; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_fcn_dw_0 = io_iss_uop_ctrl_fcn_dw; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ctrl_csr_cmd_0 = io_iss_uop_ctrl_csr_cmd; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_load_0 = io_iss_uop_ctrl_is_load; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_sta_0 = io_iss_uop_ctrl_is_sta; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ctrl_is_std_0 = io_iss_uop_ctrl_is_std; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_iw_state_0 = io_iss_uop_iw_state; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_br_0 = io_iss_uop_is_br; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jalr_0 = io_iss_uop_is_jalr; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_jal_0 = io_iss_uop_is_jal; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sfb_0 = io_iss_uop_is_sfb; // @[func-unit-decode.scala:307:7] wire [7:0] io_iss_uop_br_mask_0 = io_iss_uop_br_mask; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_br_tag_0 = io_iss_uop_br_tag; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ftq_idx_0 = io_iss_uop_ftq_idx; // @[func-unit-decode.scala:307:7] wire io_iss_uop_edge_inst_0 = io_iss_uop_edge_inst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pc_lob_0 = io_iss_uop_pc_lob; // @[func-unit-decode.scala:307:7] wire io_iss_uop_taken_0 = io_iss_uop_taken; // @[func-unit-decode.scala:307:7] wire [19:0] io_iss_uop_imm_packed_0 = io_iss_uop_imm_packed; // @[func-unit-decode.scala:307:7] wire [11:0] io_iss_uop_csr_addr_0 = io_iss_uop_csr_addr; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_rob_idx_0 = io_iss_uop_rob_idx; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_ldq_idx_0 = io_iss_uop_ldq_idx; // @[func-unit-decode.scala:307:7] wire [2:0] io_iss_uop_stq_idx_0 = io_iss_uop_stq_idx; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_rxq_idx_0 = io_iss_uop_rxq_idx; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_pdst_0 = io_iss_uop_pdst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs1_0 = io_iss_uop_prs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs2_0 = io_iss_uop_prs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_prs3_0 = io_iss_uop_prs3; // @[func-unit-decode.scala:307:7] wire [3:0] io_iss_uop_ppred_0 = io_iss_uop_ppred; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs1_busy_0 = io_iss_uop_prs1_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs2_busy_0 = io_iss_uop_prs2_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_prs3_busy_0 = io_iss_uop_prs3_busy; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ppred_busy_0 = io_iss_uop_ppred_busy; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_stale_pdst_0 = io_iss_uop_stale_pdst; // @[func-unit-decode.scala:307:7] wire io_iss_uop_exception_0 = io_iss_uop_exception; // @[func-unit-decode.scala:307:7] wire [63:0] io_iss_uop_exc_cause_0 = io_iss_uop_exc_cause; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bypassable_0 = io_iss_uop_bypassable; // @[func-unit-decode.scala:307:7] wire [4:0] io_iss_uop_mem_cmd_0 = io_iss_uop_mem_cmd; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_mem_size_0 = io_iss_uop_mem_size; // @[func-unit-decode.scala:307:7] wire io_iss_uop_mem_signed_0 = io_iss_uop_mem_signed; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fence_0 = io_iss_uop_is_fence; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_fencei_0 = io_iss_uop_is_fencei; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_amo_0 = io_iss_uop_is_amo; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_ldq_0 = io_iss_uop_uses_ldq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_uses_stq_0 = io_iss_uop_uses_stq; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc; // @[func-unit-decode.scala:307:7] wire io_iss_uop_is_unique_0 = io_iss_uop_is_unique; // @[func-unit-decode.scala:307:7] wire io_iss_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_ldst_0 = io_iss_uop_ldst; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs1_0 = io_iss_uop_lrs1; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs2_0 = io_iss_uop_lrs2; // @[func-unit-decode.scala:307:7] wire [5:0] io_iss_uop_lrs3_0 = io_iss_uop_lrs3; // @[func-unit-decode.scala:307:7] wire io_iss_uop_ldst_val_0 = io_iss_uop_ldst_val; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_dst_rtype_0 = io_iss_uop_dst_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype; // @[func-unit-decode.scala:307:7] wire io_iss_uop_frs3_en_0 = io_iss_uop_frs3_en; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_val_0 = io_iss_uop_fp_val; // @[func-unit-decode.scala:307:7] wire io_iss_uop_fp_single_0 = io_iss_uop_fp_single; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if; // @[func-unit-decode.scala:307:7] wire io_iss_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc; // @[func-unit-decode.scala:307:7] wire [1:0] io_iss_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc; // @[func-unit-decode.scala:307:7] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = 2'h0; // @[pla.scala:102:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = 3'h0; // @[pla.scala:102:36] wire io_iss_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_iss_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p1_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_iw_p2_poisoned = 1'h0; // @[func-unit-decode.scala:307:7] wire io_rrd_valid_0 = io_iss_valid_0; // @[func-unit-decode.scala:307:7] wire [6:0] io_rrd_uop_uopc_0 = io_iss_uop_uopc_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_inst_0 = io_iss_uop_inst_0; // @[func-unit-decode.scala:307:7] wire [31:0] io_rrd_uop_debug_inst_0 = io_iss_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_rvc_0 = io_iss_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] wire [39:0] io_rrd_uop_debug_pc_0 = io_iss_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_iq_type_0 = io_iss_uop_iq_type_0; // @[func-unit-decode.scala:307:7] wire [9:0] io_rrd_uop_fu_code_0 = io_iss_uop_fu_code_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_iw_state_0 = io_iss_uop_iw_state_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_br_0 = io_iss_uop_is_br_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jalr_0 = io_iss_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_jal_0 = io_iss_uop_is_jal_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sfb_0 = io_iss_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] wire [7:0] io_rrd_uop_br_mask_0 = io_iss_uop_br_mask_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_br_tag_0 = io_iss_uop_br_tag_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_ftq_idx_0 = io_iss_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_edge_inst_0 = io_iss_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pc_lob_0 = io_iss_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_taken_0 = io_iss_uop_taken_0; // @[func-unit-decode.scala:307:7] wire [11:0] io_rrd_uop_csr_addr_0 = io_iss_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_rob_idx_0 = io_iss_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ldq_idx_0 = io_iss_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_stq_idx_0 = io_iss_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_rxq_idx_0 = io_iss_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_pdst_0 = io_iss_uop_pdst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs1_0 = io_iss_uop_prs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs2_0 = io_iss_uop_prs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_prs3_0 = io_iss_uop_prs3_0; // @[func-unit-decode.scala:307:7] wire [3:0] io_rrd_uop_ppred_0 = io_iss_uop_ppred_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs1_busy_0 = io_iss_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs2_busy_0 = io_iss_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_prs3_busy_0 = io_iss_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ppred_busy_0 = io_iss_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_stale_pdst_0 = io_iss_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_exception_0 = io_iss_uop_exception_0; // @[func-unit-decode.scala:307:7] wire [63:0] io_rrd_uop_exc_cause_0 = io_iss_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bypassable_0 = io_iss_uop_bypassable_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_mem_cmd_0 = io_iss_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_mem_size_0 = io_iss_uop_mem_size_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_mem_signed_0 = io_iss_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fence_0 = io_iss_uop_is_fence_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_fencei_0 = io_iss_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_amo_0 = io_iss_uop_is_amo_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_ldq_0 = io_iss_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_uses_stq_0 = io_iss_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_sys_pc2epc_0 = io_iss_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_is_unique_0 = io_iss_uop_is_unique_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_flush_on_commit_0 = io_iss_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_is_rs1_0 = io_iss_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_ldst_0 = io_iss_uop_ldst_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs1_0 = io_iss_uop_lrs1_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs2_0 = io_iss_uop_lrs2_0; // @[func-unit-decode.scala:307:7] wire [5:0] io_rrd_uop_lrs3_0 = io_iss_uop_lrs3_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ldst_val_0 = io_iss_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_dst_rtype_0 = io_iss_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs1_rtype_0 = io_iss_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_lrs2_rtype_0 = io_iss_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_frs3_en_0 = io_iss_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_val_0 = io_iss_uop_fp_val_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_fp_single_0 = io_iss_uop_fp_single_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_pf_if_0 = io_iss_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ae_if_0 = io_iss_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_xcpt_ma_if_0 = io_iss_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_debug_if_0 = io_iss_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_bp_xcpt_if_0 = io_iss_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_fsrc_0 = io_iss_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_debug_tsrc_0 = io_iss_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] wire [6:0] rrd_cs_decoder_decoded_plaInput = io_rrd_uop_uopc_0; // @[pla.scala:77:22] wire [3:0] rrd_cs_br_type; // @[func-unit-decode.scala:330:20] wire [1:0] rrd_cs_op1_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_op2_sel; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_imm_sel; // @[func-unit-decode.scala:330:20] wire [4:0] rrd_cs_op_fcn; // @[func-unit-decode.scala:330:20] wire rrd_cs_fcn_dw; // @[func-unit-decode.scala:330:20] wire [2:0] _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:349:33] wire _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:339:46] wire _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:340:57] wire _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:341:57] wire [3:0] io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] wire [1:0] io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] wire [4:0] io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] wire [2:0] io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] wire io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] wire [19:0] io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] wire [3:0] rrd_cs_decoder_0; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_br_type_0 = rrd_cs_br_type; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_1; // @[Decode.scala:50:77] wire rrd_cs_decoder_2; // @[Decode.scala:50:77] wire rrd_cs_decoder_3; // @[Decode.scala:50:77] wire [4:0] rrd_cs_decoder_4; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op_fcn_0 = rrd_cs_op_fcn; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_5; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_fcn_dw_0 = rrd_cs_fcn_dw; // @[func-unit-decode.scala:307:7, :330:20] wire [1:0] rrd_cs_decoder_6; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op1_sel_0 = rrd_cs_op1_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_7; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_op2_sel_0 = rrd_cs_op2_sel; // @[func-unit-decode.scala:307:7, :330:20] wire [2:0] rrd_cs_decoder_8; // @[Decode.scala:50:77] assign io_rrd_uop_ctrl_imm_sel_0 = rrd_cs_imm_sel; // @[func-unit-decode.scala:307:7, :330:20] wire rrd_cs_decoder_9; // @[Decode.scala:50:77] wire [2:0] rrd_cs_decoder_10; // @[Decode.scala:50:77] wire rrd_cs_use_alupipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_muldivpipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_use_mempipe; // @[func-unit-decode.scala:330:20] wire rrd_cs_rf_wen; // @[func-unit-decode.scala:330:20] wire [2:0] rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20] wire [6:0] rrd_cs_decoder_decoded_invInputs = ~rrd_cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [24:0] rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [24:0] rrd_cs_decoder_decoded; // @[pla.scala:81:23] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = rrd_cs_decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = rrd_cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = rrd_cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = rrd_cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T = {rrd_cs_decoder_decoded_andMatrixOutputs_hi, rrd_cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_14_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = rrd_cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_56_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = rrd_cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_31_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = rrd_cs_decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_30_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_2 = rrd_cs_decoder_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_7 = rrd_cs_decoder_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = rrd_cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_11_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_7_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_37_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_58_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = rrd_cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_42_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = rrd_cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_45_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_0_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = rrd_cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_54_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_53_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_22_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_64_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_18_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_60_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_24_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_62_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_21_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_48_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_23_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = rrd_cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_52_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_6_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_28_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_26_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_5_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_63_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_25_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_16_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_10_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_29_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_39_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_47_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_65_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_50_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_13_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_9_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_44_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_23, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_32_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_24, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_1_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_25, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_59_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_26, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_43_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_27, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_27_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_28, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_15_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_11, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_29, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_45, rrd_cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_8_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_12, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_30, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_46, rrd_cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_51_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = rrd_cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_45 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_13, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_31, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_47, rrd_cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_33_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_46 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_32, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_48, rrd_cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_12_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_47 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_14, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_33, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_49, rrd_cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_19_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_48 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_15, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_34, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_50, rrd_cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_35_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_49 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_16, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_35, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_51, rrd_cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_55_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_50 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_36, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_52, rrd_cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_61_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_51 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_17, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_37, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_53, rrd_cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_2_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_52 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_18, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_38, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_54, rrd_cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_34_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = rrd_cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_53 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_39, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_55, rrd_cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_17_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_54 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_40, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:90:45, :98:53] wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_56, rrd_cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_46_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_55 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_19, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_41, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_57, rrd_cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_41_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_58, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:90:45, :98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_20_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_56 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_59, rrd_cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_40_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_57 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_60, rrd_cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_38_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_58 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_61, rrd_cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_4_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_59 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:91:29, :98:53] wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_62, rrd_cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_3_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_60 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_20, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_42, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_63 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_63, rrd_cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_36_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_61 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_21, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_43, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_64, rrd_cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_57_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] rrd_cs_decoder_decoded_andMatrixOutputs_lo_62 = {rrd_cs_decoder_decoded_andMatrixOutputs_lo_hi_22, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:90:45, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, rrd_cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:91:29, :98:53] wire [3:0] rrd_cs_decoder_decoded_andMatrixOutputs_hi_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_hi_44, rrd_cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_65 = {rrd_cs_decoder_decoded_andMatrixOutputs_hi_65, rrd_cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire rrd_cs_decoder_decoded_andMatrixOutputs_49_2 = &_rrd_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] _GEN = {rrd_cs_decoder_decoded_andMatrixOutputs_41_2, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = _GEN; // @[pla.scala:114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_26_2, rrd_cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_24_2, rrd_cs_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_andMatrixOutputs_31_2, rrd_cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T = {rrd_cs_decoder_decoded_orMatrixOutputs_hi, rrd_cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_1 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_30_2, rrd_cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_4 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_22_2, rrd_cs_decoder_decoded_andMatrixOutputs_55_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_14_2, rrd_cs_decoder_decoded_andMatrixOutputs_56_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_6 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_5; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_33_2, rrd_cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_8 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_9 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = _GEN_0; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN_0; // @[pla.scala:114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_50_2, rrd_cs_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, rrd_cs_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_60_2, rrd_cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_7_2, rrd_cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [12:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_10 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_11 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_20_2, rrd_cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_34_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_andMatrixOutputs_1_2, rrd_cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_16_2, rrd_cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_48_2, rrd_cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [7:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_3, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [14:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_13 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_38_2, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_13_2, rrd_cs_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [4:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_10_2, rrd_cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_37_2, rrd_cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [10:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_14 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_15 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {rrd_cs_decoder_decoded_andMatrixOutputs_40_2, rrd_cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_19_2, rrd_cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_9_2, rrd_cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_63_2, rrd_cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {rrd_cs_decoder_decoded_andMatrixOutputs_62_2, rrd_cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {rrd_cs_decoder_decoded_andMatrixOutputs_54_2, rrd_cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [7:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [14:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_16 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_17 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_16; // @[pla.scala:114:{19,36}] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_6, rrd_cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = {rrd_cs_decoder_decoded_andMatrixOutputs_17_2, rrd_cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_6, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_18 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_19 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_18; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_1 = {rrd_cs_decoder_decoded_andMatrixOutputs_36_2, rrd_cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_8; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_8 = _GEN_1; // @[pla.scala:114:19] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_9; // @[pla.scala:114:19] assign rrd_cs_decoder_decoded_orMatrixOutputs_hi_9 = _GEN_1; // @[pla.scala:114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_20 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_8, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_21 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_20; // @[pla.scala:114:{19,36}] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_22 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_9, rrd_cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_23 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_22; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_10 = {rrd_cs_decoder_decoded_andMatrixOutputs_59_2, rrd_cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_24 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_10, rrd_cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_25 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_24; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_26 = {rrd_cs_decoder_decoded_andMatrixOutputs_32_2, rrd_cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_27 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_26; // @[pla.scala:114:{19,36}] wire [1:0] _rrd_cs_decoder_decoded_orMatrixOutputs_T_28 = {rrd_cs_decoder_decoded_andMatrixOutputs_27_2, rrd_cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19] wire _rrd_cs_decoder_decoded_orMatrixOutputs_T_29 = |_rrd_cs_decoder_decoded_orMatrixOutputs_T_28; // @[pla.scala:114:{19,36}] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_4, _rrd_cs_decoder_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, 3'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, 1'h0}; // @[pla.scala:102:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:102:36] wire [11:0] rrd_cs_decoder_decoded_orMatrixOutputs_lo_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_lo_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_13, _rrd_cs_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_19, _rrd_cs_decoder_decoded_orMatrixOutputs_T_17}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [5:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_23, _rrd_cs_decoder_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [2:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, 1'h0}; // @[pla.scala:102:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_orMatrixOutputs_T_27, _rrd_cs_decoder_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [1:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {1'h0, _rrd_cs_decoder_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [3:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:102:36] wire [12:0] rrd_cs_decoder_decoded_orMatrixOutputs_hi_11 = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_hi_7, rrd_cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:102:36] wire [24:0] rrd_cs_decoder_decoded_orMatrixOutputs = {rrd_cs_decoder_decoded_orMatrixOutputs_hi_11, rrd_cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:102:36] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T = rrd_cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_1 = rrd_cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_2 = rrd_cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_3 = rrd_cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_4 = rrd_cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_5 = rrd_cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_6 = rrd_cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_7 = rrd_cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_8 = rrd_cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_9 = rrd_cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_10 = rrd_cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_11 = rrd_cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_12 = rrd_cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_13 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_12; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_14 = rrd_cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_15 = rrd_cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_16 = rrd_cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_17 = rrd_cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_18 = rrd_cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_19 = rrd_cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_20 = rrd_cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_21 = rrd_cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :123:56] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_22 = ~_rrd_cs_decoder_decoded_invMatrixOutputs_T_21; // @[pla.scala:123:{40,56}] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_23 = rrd_cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_24 = rrd_cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_25 = rrd_cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _rrd_cs_decoder_decoded_invMatrixOutputs_T_26 = rrd_cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_2, _rrd_cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_5, _rrd_cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_8, _rrd_cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_11, _rrd_cs_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] rrd_cs_decoder_decoded_invMatrixOutputs_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_15, _rrd_cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :123:40] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_18, _rrd_cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [5:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_22, _rrd_cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :123:40, :124:31] wire [2:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, _rrd_cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_24, _rrd_cs_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [1:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {_rrd_cs_decoder_decoded_invMatrixOutputs_T_26, _rrd_cs_decoder_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [3:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] rrd_cs_decoder_decoded_invMatrixOutputs_hi = {rrd_cs_decoder_decoded_invMatrixOutputs_hi_hi, rrd_cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded_invMatrixOutputs = {rrd_cs_decoder_decoded_invMatrixOutputs_hi, rrd_cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign rrd_cs_decoder_decoded = rrd_cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign rrd_cs_decoder_0 = rrd_cs_decoder_decoded[24:21]; // @[pla.scala:81:23] assign rrd_cs_br_type = rrd_cs_decoder_0; // @[Decode.scala:50:77] assign rrd_cs_decoder_1 = rrd_cs_decoder_decoded[20]; // @[pla.scala:81:23] assign rrd_cs_use_alupipe = rrd_cs_decoder_1; // @[Decode.scala:50:77] assign rrd_cs_decoder_2 = rrd_cs_decoder_decoded[19]; // @[pla.scala:81:23] assign rrd_cs_use_muldivpipe = rrd_cs_decoder_2; // @[Decode.scala:50:77] assign rrd_cs_decoder_3 = rrd_cs_decoder_decoded[18]; // @[pla.scala:81:23] assign rrd_cs_use_mempipe = rrd_cs_decoder_3; // @[Decode.scala:50:77] assign rrd_cs_decoder_4 = rrd_cs_decoder_decoded[17:13]; // @[pla.scala:81:23] assign rrd_cs_op_fcn = rrd_cs_decoder_4; // @[Decode.scala:50:77] assign rrd_cs_decoder_5 = rrd_cs_decoder_decoded[12]; // @[pla.scala:81:23] assign rrd_cs_fcn_dw = rrd_cs_decoder_5; // @[Decode.scala:50:77] assign rrd_cs_decoder_6 = rrd_cs_decoder_decoded[11:10]; // @[pla.scala:81:23] assign rrd_cs_op1_sel = rrd_cs_decoder_6; // @[Decode.scala:50:77] assign rrd_cs_decoder_7 = rrd_cs_decoder_decoded[9:7]; // @[pla.scala:81:23] assign rrd_cs_op2_sel = rrd_cs_decoder_7; // @[Decode.scala:50:77] assign rrd_cs_decoder_8 = rrd_cs_decoder_decoded[6:4]; // @[pla.scala:81:23] assign rrd_cs_imm_sel = rrd_cs_decoder_8; // @[Decode.scala:50:77] assign rrd_cs_decoder_9 = rrd_cs_decoder_decoded[3]; // @[pla.scala:81:23] assign rrd_cs_rf_wen = rrd_cs_decoder_9; // @[Decode.scala:50:77] assign rrd_cs_decoder_10 = rrd_cs_decoder_decoded[2:0]; // @[pla.scala:81:23] assign rrd_cs_csr_cmd = rrd_cs_decoder_10; // @[Decode.scala:50:77] assign _io_rrd_uop_ctrl_is_load_T = io_rrd_uop_uopc_0 == 7'h1; // @[func-unit-decode.scala:307:7, :339:46] assign io_rrd_uop_ctrl_is_load_0 = _io_rrd_uop_ctrl_is_load_T; // @[func-unit-decode.scala:307:7, :339:46] wire _io_rrd_uop_ctrl_is_sta_T = io_rrd_uop_uopc_0 == 7'h2; // @[func-unit-decode.scala:307:7, :340:46] wire _io_rrd_uop_ctrl_is_sta_T_1 = io_rrd_uop_uopc_0 == 7'h43; // @[func-unit-decode.scala:307:7, :340:76] assign _io_rrd_uop_ctrl_is_sta_T_2 = _io_rrd_uop_ctrl_is_sta_T | _io_rrd_uop_ctrl_is_sta_T_1; // @[func-unit-decode.scala:340:{46,57,76}] assign io_rrd_uop_ctrl_is_sta_0 = _io_rrd_uop_ctrl_is_sta_T_2; // @[func-unit-decode.scala:307:7, :340:57] wire _io_rrd_uop_ctrl_is_std_T = io_rrd_uop_uopc_0 == 7'h3; // @[func-unit-decode.scala:307:7, :341:46] wire _io_rrd_uop_ctrl_is_std_T_1 = io_rrd_uop_lrs2_rtype_0 == 2'h0; // @[func-unit-decode.scala:307:7, :341:109] wire _io_rrd_uop_ctrl_is_std_T_2 = io_rrd_uop_ctrl_is_sta_0 & _io_rrd_uop_ctrl_is_std_T_1; // @[func-unit-decode.scala:307:7, :341:{84,109}] assign _io_rrd_uop_ctrl_is_std_T_3 = _io_rrd_uop_ctrl_is_std_T | _io_rrd_uop_ctrl_is_std_T_2; // @[func-unit-decode.scala:341:{46,57,84}] assign io_rrd_uop_ctrl_is_std_0 = _io_rrd_uop_ctrl_is_std_T_3; // @[func-unit-decode.scala:307:7, :341:57] assign io_rrd_uop_imm_packed_0 = _io_rrd_uop_ctrl_is_sta_T_1 | _io_rrd_uop_ctrl_is_load_T & io_rrd_uop_mem_cmd_0 == 5'h6 ? 20'h0 : io_iss_uop_imm_packed_0; // @[func-unit-decode.scala:307:7, :320:16, :339:46, :340:76, :343:{39,69,91,103}, :344:27] wire _csr_ren_T = rrd_cs_csr_cmd == 3'h6; // @[func-unit-decode.scala:330:20, :348:33] wire _csr_ren_T_1 = &rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:61] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[func-unit-decode.scala:348:{33,43,61}] wire _csr_ren_T_3 = io_rrd_uop_prs1_0 == 6'h0; // @[pla.scala:114:36] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[func-unit-decode.scala:348:{43,72,82}] assign _io_rrd_uop_ctrl_csr_cmd_T = csr_ren ? 3'h2 : rrd_cs_csr_cmd; // @[func-unit-decode.scala:330:20, :348:72, :349:33] assign io_rrd_uop_ctrl_csr_cmd_0 = _io_rrd_uop_ctrl_csr_cmd_T; // @[func-unit-decode.scala:307:7, :349:33] assign io_rrd_valid = io_rrd_valid_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uopc = io_rrd_uop_uopc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_inst = io_rrd_uop_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_inst = io_rrd_uop_debug_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_rvc = io_rrd_uop_is_rvc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_pc = io_rrd_uop_debug_pc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iq_type = io_rrd_uop_iq_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fu_code = io_rrd_uop_fu_code_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_br_type = io_rrd_uop_ctrl_br_type_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op1_sel = io_rrd_uop_ctrl_op1_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op2_sel = io_rrd_uop_ctrl_op2_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_imm_sel = io_rrd_uop_ctrl_imm_sel_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_op_fcn = io_rrd_uop_ctrl_op_fcn_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_fcn_dw = io_rrd_uop_ctrl_fcn_dw_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_csr_cmd = io_rrd_uop_ctrl_csr_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ctrl_is_std = io_rrd_uop_ctrl_is_std_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_iw_state = io_rrd_uop_iw_state_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_br = io_rrd_uop_is_br_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jalr = io_rrd_uop_is_jalr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_jal = io_rrd_uop_is_jal_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sfb = io_rrd_uop_is_sfb_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_mask = io_rrd_uop_br_mask_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_br_tag = io_rrd_uop_br_tag_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ftq_idx = io_rrd_uop_ftq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_edge_inst = io_rrd_uop_edge_inst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pc_lob = io_rrd_uop_pc_lob_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_taken = io_rrd_uop_taken_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_imm_packed = io_rrd_uop_imm_packed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_csr_addr = io_rrd_uop_csr_addr_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rob_idx = io_rrd_uop_rob_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldq_idx = io_rrd_uop_ldq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stq_idx = io_rrd_uop_stq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_rxq_idx = io_rrd_uop_rxq_idx_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_pdst = io_rrd_uop_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1 = io_rrd_uop_prs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2 = io_rrd_uop_prs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3 = io_rrd_uop_prs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred = io_rrd_uop_ppred_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs1_busy = io_rrd_uop_prs1_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs2_busy = io_rrd_uop_prs2_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_prs3_busy = io_rrd_uop_prs3_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ppred_busy = io_rrd_uop_ppred_busy_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_stale_pdst = io_rrd_uop_stale_pdst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exception = io_rrd_uop_exception_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_exc_cause = io_rrd_uop_exc_cause_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bypassable = io_rrd_uop_bypassable_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_cmd = io_rrd_uop_mem_cmd_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_size = io_rrd_uop_mem_size_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_mem_signed = io_rrd_uop_mem_signed_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fence = io_rrd_uop_is_fence_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_fencei = io_rrd_uop_is_fencei_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_amo = io_rrd_uop_is_amo_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_ldq = io_rrd_uop_uses_ldq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_uses_stq = io_rrd_uop_uses_stq_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_sys_pc2epc = io_rrd_uop_is_sys_pc2epc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_is_unique = io_rrd_uop_is_unique_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_flush_on_commit = io_rrd_uop_flush_on_commit_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_is_rs1 = io_rrd_uop_ldst_is_rs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst = io_rrd_uop_ldst_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1 = io_rrd_uop_lrs1_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2 = io_rrd_uop_lrs2_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs3 = io_rrd_uop_lrs3_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_ldst_val = io_rrd_uop_ldst_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_dst_rtype = io_rrd_uop_dst_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs1_rtype = io_rrd_uop_lrs1_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_lrs2_rtype = io_rrd_uop_lrs2_rtype_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_frs3_en = io_rrd_uop_frs3_en_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_val = io_rrd_uop_fp_val_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_fp_single = io_rrd_uop_fp_single_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_pf_if = io_rrd_uop_xcpt_pf_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ae_if = io_rrd_uop_xcpt_ae_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_xcpt_ma_if = io_rrd_uop_xcpt_ma_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_debug_if = io_rrd_uop_bp_debug_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_bp_xcpt_if = io_rrd_uop_bp_xcpt_if_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_fsrc = io_rrd_uop_debug_fsrc_0; // @[func-unit-decode.scala:307:7] assign io_rrd_uop_debug_tsrc = io_rrd_uop_debug_tsrc_0; // @[func-unit-decode.scala:307:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_32 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x

module OptimizationBarrier_EntryData_32( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_37 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} inst mulFullRaw of MulFullRawFN_37 connect mulFullRaw.io.a.sig, io.a.sig connect mulFullRaw.io.a.sExp, io.a.sExp connect mulFullRaw.io.a.sign, io.a.sign connect mulFullRaw.io.a.isZero, io.a.isZero connect mulFullRaw.io.a.isInf, io.a.isInf connect mulFullRaw.io.a.isNaN, io.a.isNaN connect mulFullRaw.io.b.sig, io.b.sig connect mulFullRaw.io.b.sExp, io.b.sExp connect mulFullRaw.io.b.sign, io.b.sign connect mulFullRaw.io.b.isZero, io.b.isZero connect mulFullRaw.io.b.isInf, io.b.isInf connect mulFullRaw.io.b.isNaN, io.b.isNaN connect io.invalidExc, mulFullRaw.io.invalidExc connect io.rawOut, mulFullRaw.io.rawOut node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) connect io.rawOut.sig, _io_rawOut_sig_T_3

module MulRawFN_37( // @[MulRecFN.scala:75:7] input io_a_isNaN, // @[MulRecFN.scala:77:16] input io_a_isInf, // @[MulRecFN.scala:77:16] input io_a_isZero, // @[MulRecFN.scala:77:16] input io_a_sign, // @[MulRecFN.scala:77:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_a_sig, // @[MulRecFN.scala:77:16] input io_b_isNaN, // @[MulRecFN.scala:77:16] input io_b_isInf, // @[MulRecFN.scala:77:16] input io_b_isZero, // @[MulRecFN.scala:77:16] input io_b_sign, // @[MulRecFN.scala:77:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16] input [24:0] io_b_sig, // @[MulRecFN.scala:77:16] output io_invalidExc, // @[MulRecFN.scala:77:16] output io_rawOut_isNaN, // @[MulRecFN.scala:77:16] output io_rawOut_isInf, // @[MulRecFN.scala:77:16] output io_rawOut_isZero, // @[MulRecFN.scala:77:16] output io_rawOut_sign, // @[MulRecFN.scala:77:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16] output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16] ); wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28] wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7] wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7] wire io_invalidExc_0; // @[MulRecFN.scala:75:7] wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15] wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37] wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}] assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10] MulFullRawFN_37 mulFullRaw ( // @[MulRecFN.scala:84:28] .io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7] .io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7] .io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7] .io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7] .io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7] .io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7] .io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7] .io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7] .io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7] .io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7] .io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7] .io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7] .io_invalidExc (io_invalidExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (_mulFullRaw_io_rawOut_sig) ); // @[MulRecFN.scala:84:28] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<28>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<28>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<28>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<28>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<28>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<28>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<28>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<28>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<28>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:72:89)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<28>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x2_11 : input clock : Clock input reset : Reset output auto : { flip in : UInt<1>[2], out : { sync : UInt<1>[2]}} wire nodeIn : UInt<1>[2] invalidate nodeIn[0] invalidate nodeIn[1] wire nodeOut : { sync : UInt<1>[2]} invalidate nodeOut.sync[0] invalidate nodeOut.sync[1] connect auto.out, nodeOut connect nodeIn, auto.in node _T = cat(nodeIn[1], nodeIn[0]) inst reg of AsyncResetRegVec_w2_i0_11 connect reg.clock, clock connect reg.reset, reset connect reg.io.d, _T connect reg.io.en, UInt<1>(0h1) node _T_1 = bits(reg.io.q, 0, 0) node _T_2 = bits(reg.io.q, 1, 1) connect nodeOut.sync[0], _T_1 connect nodeOut.sync[1], _T_2

module IntSyncCrossingSource_n1x2_11( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset, // @[Crossing.scala:41:9] input auto_in_0, // @[LazyModuleImp.scala:107:25] input auto_in_1, // @[LazyModuleImp.scala:107:25] output auto_out_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_sync_1 // @[LazyModuleImp.scala:107:25] ); wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21] wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9] wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9] wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9] wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_1; // @[MixedNode.scala:542:17] wire auto_out_sync_0_0; // @[Crossing.scala:41:9] wire auto_out_sync_1_0; // @[Crossing.scala:41:9] assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9] assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9] assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21] assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21] AsyncResetRegVec_w2_i0_11 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset), .io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36] .io_q (_reg_io_q) ); // @[AsyncResetReg.scala:86:21] assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9] assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module CSRFile_7 : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<3>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2)) node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv) connect reg_mstatus.prv, _reg_mstatus_prv_T_1 wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h1) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h1) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h1) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<40>, clock reg reg_dscratch0 : UInt<64>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<64>, clock reg reg_mideleg : UInt<64>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<64>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<40>, clock regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) reg reg_mtval : UInt<40>, clock reg reg_mtval2 : UInt<40>, clock reg reg_mscratch : UInt<64>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<64>, clock reg reg_mnepc : UInt<40>, clock regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<64>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<64>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_htval : UInt<40>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<40>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node _T_14 = and(reg_vstvec, _T_13) node _T_15 = bits(_T_14, 39, 39) node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0)) node read_vstvec = cat(_T_16, _T_14) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<64>, clock reg reg_vsepc : UInt<40>, clock reg reg_vscause : UInt<64>, clock reg reg_vstval : UInt<40>, clock reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_sepc : UInt<40>, clock reg reg_scause : UInt<64>, clock reg reg_stval : UInt<40>, clock reg reg_sscratch : UInt<64>, clock reg reg_stvec : UInt<39>, clock reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_17 = eq(x3, UInt<1>(0h0)) when _T_17 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_18 = eq(x11, UInt<1>(0h0)) when _T_18 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip) connect mip.seip, _mip_seip_T connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 62) node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 63, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38) node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38) node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T_2 = not(reg_mepc) node _read_mapping_T_3 = bits(reg_misa, 2, 2) node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) node _read_mapping_T_6 = not(_read_mapping_T_5) node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39) node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) node _read_mapping_T_9 = bits(reg_mtval, 39, 39) node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node _debug_csrs_T_4 = not(_debug_csrs_T_3) node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39) node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0)) node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom) node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie) node lo_4 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze) node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_19 = cat(hi_6, lo_4) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) node read_sie = and(reg_mie, sie_mask) node read_sip = and(read_mip, sie_mask) wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _read_sstatus_WIRE.uie, UInt<1>(0h0) connect _read_sstatus_WIRE.sie, UInt<1>(0h0) connect _read_sstatus_WIRE.hie, UInt<1>(0h0) connect _read_sstatus_WIRE.mie, UInt<1>(0h0) connect _read_sstatus_WIRE.upie, UInt<1>(0h0) connect _read_sstatus_WIRE.spie, UInt<1>(0h0) connect _read_sstatus_WIRE.ube, UInt<1>(0h0) connect _read_sstatus_WIRE.mpie, UInt<1>(0h0) connect _read_sstatus_WIRE.spp, UInt<1>(0h0) connect _read_sstatus_WIRE.vs, UInt<2>(0h0) connect _read_sstatus_WIRE.mpp, UInt<2>(0h0) connect _read_sstatus_WIRE.fs, UInt<2>(0h0) connect _read_sstatus_WIRE.xs, UInt<2>(0h0) connect _read_sstatus_WIRE.mprv, UInt<1>(0h0) connect _read_sstatus_WIRE.sum, UInt<1>(0h0) connect _read_sstatus_WIRE.mxr, UInt<1>(0h0) connect _read_sstatus_WIRE.tvm, UInt<1>(0h0) connect _read_sstatus_WIRE.tw, UInt<1>(0h0) connect _read_sstatus_WIRE.tsr, UInt<1>(0h0) connect _read_sstatus_WIRE.zero1, UInt<8>(0h0) connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _read_sstatus_WIRE.uxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sbe, UInt<1>(0h0) connect _read_sstatus_WIRE.mbe, UInt<1>(0h0) connect _read_sstatus_WIRE.gva, UInt<1>(0h0) connect _read_sstatus_WIRE.mpv, UInt<1>(0h0) connect _read_sstatus_WIRE.zero2, UInt<23>(0h0) connect _read_sstatus_WIRE.sd, UInt<1>(0h0) connect _read_sstatus_WIRE.v, UInt<1>(0h0) connect _read_sstatus_WIRE.prv, UInt<2>(0h0) connect _read_sstatus_WIRE.dv, UInt<1>(0h0) connect _read_sstatus_WIRE.dprv, UInt<2>(0h0) connect _read_sstatus_WIRE.isa, UInt<32>(0h0) connect _read_sstatus_WIRE.wfi, UInt<1>(0h0) connect _read_sstatus_WIRE.cease, UInt<1>(0h0) connect _read_sstatus_WIRE.debug, UInt<1>(0h0) wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect read_sstatus, _read_sstatus_WIRE connect read_sstatus.sd, io.status.sd connect read_sstatus.uxl, io.status.uxl connect read_sstatus.sd_rv32, io.status.sd_rv32 connect read_sstatus.mxr, io.status.mxr connect read_sstatus.sum, io.status.sum connect read_sstatus.xs, io.status.xs connect read_sstatus.fs, io.status.fs connect read_sstatus.vs, io.status.vs connect read_sstatus.spp, io.status.spp connect read_sstatus.spie, io.status.spie connect read_sstatus.sie, io.status.sie node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie) node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie) node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo) node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie) node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie) node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube) node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo) node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4) node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs) node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs) node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo) node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv) node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm) node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr) node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo) node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4) node lo_5 = cat(lo_hi_5, lo_lo_5) node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr) node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32) node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo) node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl) node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva) node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe) node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo) node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4) node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2) node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv) node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v) node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo) node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv) node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease) node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi) node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo) node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_20 = cat(hi_7, lo_5) node _T_21 = bits(_T_20, 63, 0) node _T_22 = bits(reg_stval, 39, 39) node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_24 = cat(_T_23, reg_stval) node hi_8 = cat(reg_satp.mode, reg_satp.asid) node _T_25 = cat(hi_8, reg_satp.ppn) node _T_26 = not(reg_sepc) node _T_27 = bits(reg_misa, 2, 2) node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3)) node _T_29 = or(_T_26, _T_28) node _T_30 = not(_T_29) node _T_31 = bits(_T_30, 39, 39) node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_33 = cat(_T_32, _T_30) node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom) node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie) node lo_6 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze) node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_34 = cat(hi_9, lo_6) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r) node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a) node _T_35 = cat(hi_10, lo_7) node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r) node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a) node _T_36 = cat(hi_11, lo_8) node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r) node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a) node _T_37 = cat(hi_12, lo_9) node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r) node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a) node _T_38 = cat(hi_13, lo_10) node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r) node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a) node _T_39 = cat(hi_14, lo_11) node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r) node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a) node _T_40 = cat(hi_15, lo_12) node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r) node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a) node _T_41 = cat(hi_16, lo_13) node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r) node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a) node _T_42 = cat(hi_17, lo_14) node lo_lo_7 = cat(_T_36, _T_35) node lo_hi_15 = cat(_T_38, _T_37) node lo_15 = cat(lo_hi_15, lo_lo_7) node hi_lo_7 = cat(_T_40, _T_39) node hi_hi_15 = cat(_T_42, _T_41) node hi_18 = cat(hi_hi_15, hi_lo_7) node _T_43 = cat(hi_18, lo_15) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_44 = cat(hi_19, lo_16) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_45 = cat(hi_20, lo_17) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_46 = cat(hi_21, lo_18) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_47 = cat(hi_22, lo_19) node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a) node _T_48 = cat(hi_23, lo_20) node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r) node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a) node _T_49 = cat(hi_24, lo_21) node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r) node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a) node _T_50 = cat(hi_25, lo_22) node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r) node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a) node _T_51 = cat(hi_26, lo_23) node lo_lo_8 = cat(_T_45, _T_44) node lo_hi_24 = cat(_T_47, _T_46) node lo_24 = cat(lo_hi_24, lo_lo_8) node hi_lo_8 = cat(_T_49, _T_48) node hi_hi_24 = cat(_T_51, _T_50) node hi_27 = cat(hi_hi_24, hi_lo_8) node _T_52 = cat(hi_27, lo_24) regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<150> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_53 = bits(decoded, 8, 8) node _T_54 = bits(decoded, 7, 7) node _T_55 = bits(decoded, 6, 6) node _T_56 = bits(decoded, 5, 5) node _T_57 = bits(decoded, 4, 4) node _T_58 = bits(decoded, 3, 3) node _T_59 = bits(decoded, 2, 2) node _T_60 = bits(decoded, 1, 1) node _T_61 = bits(decoded, 0, 0) node _T_62 = bits(_T_53, 0, 0) node insn_call = and(system_insn, _T_62) node _T_63 = bits(_T_54, 0, 0) node insn_break = and(system_insn, _T_63) node _T_64 = bits(_T_55, 0, 0) node insn_ret = and(system_insn, _T_64) node _T_65 = bits(_T_56, 0, 0) node insn_cease = and(system_insn, _T_65) node _T_66 = bits(_T_57, 0, 0) node insn_wfi = and(system_insn, _T_66) node _T_67 = bits(_T_58, 0, 0) node _T_68 = and(system_insn, _T_67) node _T_69 = bits(_T_59, 0, 0) node _T_70 = and(system_insn, _T_69) node _T_71 = bits(_T_60, 0, 0) node _T_72 = and(system_insn, _T_71) node _T_73 = bits(_T_61, 0, 0) node _T_74 = and(system_insn, _T_73) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_75 = bits(decoded_1, 8, 8) node _T_76 = bits(decoded_1, 7, 7) node _T_77 = bits(decoded_1, 6, 6) node _T_78 = bits(decoded_1, 5, 5) node _T_79 = bits(decoded_1, 4, 4) node _T_80 = bits(decoded_1, 3, 3) node _T_81 = bits(decoded_1, 2, 2) node _T_82 = bits(decoded_1, 1, 1) node _T_83 = bits(decoded_1, 0, 0) node _T_84 = bits(_T_75, 0, 0) node is_break = bits(_T_76, 0, 0) node is_ret = bits(_T_77, 0, 0) node _T_85 = bits(_T_78, 0, 0) node is_wfi = bits(_T_79, 0, 0) node is_sfence = bits(_T_80, 0, 0) node is_hfence_vvma = bits(_T_81, 0, 0) node is_hfence_gvma = bits(_T_82, 0, 0) node is_hlsv = bits(_T_83, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11) node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3) node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo) node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h306)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a)) node _csr_exists_T_114 = eq(addr, UInt<9>(0h100)) node _csr_exists_T_115 = eq(addr, UInt<9>(0h144)) node _csr_exists_T_116 = eq(addr, UInt<9>(0h104)) node _csr_exists_T_117 = eq(addr, UInt<9>(0h140)) node _csr_exists_T_118 = eq(addr, UInt<9>(0h142)) node _csr_exists_T_119 = eq(addr, UInt<9>(0h143)) node _csr_exists_T_120 = eq(addr, UInt<9>(0h180)) node _csr_exists_T_121 = eq(addr, UInt<9>(0h141)) node _csr_exists_T_122 = eq(addr, UInt<9>(0h105)) node _csr_exists_T_123 = eq(addr, UInt<9>(0h106)) node _csr_exists_T_124 = eq(addr, UInt<10>(0h303)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h302)) node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a)) node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2) node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3) node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4) node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5) node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6) node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7) node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8) node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9) node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10) node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11) node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12) node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13) node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14) node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15) node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16) node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17) node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18) node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19) node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20) node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21) node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22) node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23) node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24) node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25) node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26) node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27) node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28) node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29) node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30) node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31) node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32) node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33) node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34) node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35) node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36) node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37) node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38) node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39) node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40) node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41) node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42) node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43) node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44) node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45) node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46) node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148) node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 5, 0) node _causeIsDebugInt_T = bits(cause, 63, 63) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 63, 63) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 63, 63) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T) node _delegate_T_2 = bits(cause, 63, 63) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 63, 63) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 63, 63) node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 63, 63) node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<2>(0h2) connect io.status.sxl, UInt<2>(0h2) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<2>(0h2) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<2>(0h2) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_86 = add(insn_ret, insn_call) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(insn_break, io.exception) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_87, _T_89) node _T_91 = bits(_T_90, 2, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_92, UInt<1>(0h1), "") : assert node _T_96 = eq(io.singleStep, UInt<1>(0h0)) node _T_97 = and(insn_wfi, _T_96) node _T_98 = eq(reg_debug, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) when _T_99 : connect reg_wfi, UInt<1>(0h1) node _T_100 = orr(pending_interrupts) node _T_101 = or(_T_100, io.interrupts.debug) node _T_102 = or(_T_101, exception) when _T_102 : connect reg_wfi, UInt<1>(0h0) node _T_103 = bits(io.retire, 0, 0) node _T_104 = or(_T_103, exception) when _T_104 : connect reg_singleStepped, UInt<1>(0h1) node _T_105 = eq(io.singleStep, UInt<1>(0h0)) when _T_105 : connect reg_singleStepped, UInt<1>(0h0) node _T_106 = eq(io.singleStep, UInt<1>(0h0)) node _T_107 = leq(io.retire, UInt<1>(0h1)) node _T_108 = or(_T_106, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_113 = eq(io.retire, UInt<1>(0h0)) node _T_114 = or(_T_112, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 assert(clock, _T_114, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_118 = eq(reg_debug, UInt<1>(0h0)) when _T_118 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, reg_mstatus.prv connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, reg_mstatus.prv connect new_prv, UInt<2>(0h3) else : node _T_119 = and(delegateVS, reg_rnmie) when _T_119 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 63, 63) node _reg_vscause_T_1 = bits(cause, 63, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_120 = and(delegate, reg_rnmie) when _T_120 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, reg_mstatus.prv connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_121 = eq(delegate, UInt<1>(0h0)) node _T_122 = and(en, _T_121) node _T_123 = and(en, delegable) node _T_124 = and(_T_123, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_125 = eq(delegate, UInt<1>(0h0)) node _T_126 = and(en_1, _T_125) node _T_127 = and(en_1, delegable_1) node _T_128 = and(_T_127, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_129 = eq(delegate, UInt<1>(0h0)) node _T_130 = and(en_2, _T_129) node _T_131 = and(en_2, delegable_2) node _T_132 = and(_T_131, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_133 = eq(delegate, UInt<1>(0h0)) node _T_134 = and(en_3, _T_133) node _T_135 = and(en_3, delegable_3) node _T_136 = and(_T_135, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_137 = eq(delegate, UInt<1>(0h0)) node _T_138 = and(en_4, _T_137) node _T_139 = and(en_4, delegable_4) node _T_140 = and(_T_139, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_141 = eq(delegate, UInt<1>(0h0)) node _T_142 = and(en_5, _T_141) node _T_143 = and(en_5, delegable_5) node _T_144 = and(_T_143, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_145 = eq(delegate, UInt<1>(0h0)) node _T_146 = and(en_6, _T_145) node _T_147 = and(en_6, delegable_6) node _T_148 = and(_T_147, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_149 = eq(delegate, UInt<1>(0h0)) node _T_150 = and(en_7, _T_149) node _T_151 = and(en_7, delegable_7) node _T_152 = and(_T_151, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_153 = eq(delegate, UInt<1>(0h0)) node _T_154 = and(en_8, _T_153) node _T_155 = and(en_8, delegable_8) node _T_156 = and(_T_155, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_157 = eq(delegate, UInt<1>(0h0)) node _T_158 = and(en_9, _T_157) node _T_159 = and(en_9, delegable_9) node _T_160 = and(_T_159, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_161 = eq(delegate, UInt<1>(0h0)) node _T_162 = and(en_10, _T_161) node _T_163 = and(en_10, delegable_10) node _T_164 = and(_T_163, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_165 = eq(delegate, UInt<1>(0h0)) node _T_166 = and(en_11, _T_165) node _T_167 = and(en_11, delegable_11) node _T_168 = and(_T_167, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_169 = eq(delegate, UInt<1>(0h0)) node _T_170 = and(en_12, _T_169) node _T_171 = and(en_12, delegable_12) node _T_172 = and(_T_171, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_173 = eq(delegate, UInt<1>(0h0)) node _T_174 = and(en_13, _T_173) node _T_175 = and(en_13, delegable_13) node _T_176 = and(_T_175, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_177 = eq(delegate, UInt<1>(0h0)) node _T_178 = and(en_14, _T_177) node _T_179 = and(en_14, delegable_14) node _T_180 = and(_T_179, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_181 = eq(delegate, UInt<1>(0h0)) node _T_182 = and(en_15, _T_181) node _T_183 = and(en_15, delegable_15) node _T_184 = and(_T_183, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_185 = eq(delegate, UInt<1>(0h0)) node _T_186 = and(en_16, _T_185) node _T_187 = and(en_16, delegable_16) node _T_188 = and(_T_187, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_189 = eq(delegate, UInt<1>(0h0)) node _T_190 = and(en_17, _T_189) node _T_191 = and(en_17, delegable_17) node _T_192 = and(_T_191, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_193 = eq(delegate, UInt<1>(0h0)) node _T_194 = and(en_18, _T_193) node _T_195 = and(en_18, delegable_18) node _T_196 = and(_T_195, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_197 = eq(delegate, UInt<1>(0h0)) node _T_198 = and(en_19, _T_197) node _T_199 = and(en_19, delegable_19) node _T_200 = and(_T_199, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_201 = eq(delegate, UInt<1>(0h0)) node _T_202 = and(en_20, _T_201) node _T_203 = and(en_20, delegable_20) node _T_204 = and(_T_203, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_205 = eq(delegate, UInt<1>(0h0)) node _T_206 = and(en_21, _T_205) node _T_207 = and(en_21, delegable_21) node _T_208 = and(_T_207, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_209 = eq(delegate, UInt<1>(0h0)) node _T_210 = and(en_22, _T_209) node _T_211 = and(en_22, delegable_22) node _T_212 = and(_T_211, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_213 = eq(delegate, UInt<1>(0h0)) node _T_214 = and(en_23, _T_213) node _T_215 = and(en_23, delegable_23) node _T_216 = and(_T_215, delegate) node _en_T_104 = eq(cause, UInt<4>(0h8)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_217 = eq(delegate, UInt<1>(0h0)) node _T_218 = and(en_24, _T_217) node _T_219 = and(en_24, delegable_24) node _T_220 = and(_T_219, delegate) node _en_T_105 = eq(cause, UInt<4>(0h9)) node en_25 = and(exception, _en_T_105) node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200)) node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0)) node _T_221 = eq(delegate, UInt<1>(0h0)) node _T_222 = and(en_25, _T_221) node _T_223 = and(en_25, delegable_25) node _T_224 = and(_T_223, delegate) node _en_T_106 = eq(cause, UInt<4>(0hb)) node en_26 = and(exception, _en_T_106) node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0)) node _T_225 = eq(delegate, UInt<1>(0h0)) node _T_226 = and(en_26, _T_225) node _T_227 = and(en_26, delegable_26) node _T_228 = and(_T_227, delegate) node _en_T_107 = eq(cause, UInt<4>(0hc)) node en_27 = and(exception, _en_T_107) node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000)) node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0)) node _T_229 = eq(delegate, UInt<1>(0h0)) node _T_230 = and(en_27, _T_229) node _T_231 = and(en_27, delegable_27) node _T_232 = and(_T_231, delegate) node _en_T_108 = eq(cause, UInt<4>(0hd)) node en_28 = and(exception, _en_T_108) node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000)) node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0)) node _T_233 = eq(delegate, UInt<1>(0h0)) node _T_234 = and(en_28, _T_233) node _T_235 = and(en_28, delegable_28) node _T_236 = and(_T_235, delegate) node _en_T_109 = eq(cause, UInt<4>(0hf)) node en_29 = and(exception, _en_T_109) node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000)) node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0)) node _T_237 = eq(delegate, UInt<1>(0h0)) node _T_238 = and(en_29, _T_237) node _T_239 = and(en_29, delegable_29) node _T_240 = and(_T_239, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_241 = bits(io.rw.addr, 9, 9) node _T_242 = eq(_T_241, UInt<1>(0h0)) node _T_243 = and(UInt<1>(0h1), _T_242) when _T_243 : node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_244 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_245 = bits(io.rw.addr, 10, 10) node _T_246 = and(UInt<1>(0h1), _T_245) node _T_247 = bits(io.rw.addr, 7, 7) node _T_248 = and(_T_246, _T_247) when _T_248 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_249 = bits(io.rw.addr, 10, 10) node _T_250 = and(UInt<1>(0h0), _T_249) node _T_251 = bits(io.rw.addr, 7, 7) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(_T_250, _T_252) when _T_253 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2)) node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0)) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1 connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_254 = leq(ret_prv, UInt<1>(0h1)) node _T_255 = and(UInt<1>(0h1), _T_254) when _T_255 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2) node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3) node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4) node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5) node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6) node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7) node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8) node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9) node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10) node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11) node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12) node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13) node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14) node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15) node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16) node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17) node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18) node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19) node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20) node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21) node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22) node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23) node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24) node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25) node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26) node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27) node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28) node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29) node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30) node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31) node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32) node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33) node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34) node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35) node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36) node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37) node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38) node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39) node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40) node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41) node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42) node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43) node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44) node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45) node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_256 = andr(UInt<2>(0h1)) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_261 = or(_T_258, _T_259) node _T_262 = or(_T_261, _T_260) node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_264 = and(_T_262, _T_263) else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_267 = and(_T_265, _T_266) node _T_268 = andr(UInt<2>(0h1)) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_273 = or(_T_270, _T_271) node _T_274 = or(_T_273, _T_272) node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_276 = and(_T_274, _T_275) else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_279 = and(_T_277, _T_278) node _T_280 = andr(UInt<2>(0h1)) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_285 = or(_T_282, _T_283) node _T_286 = or(_T_285, _T_284) node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_288 = and(_T_286, _T_287) else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_291 = and(_T_289, _T_290) node _T_292 = andr(UInt<2>(0h1)) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_297 = or(_T_294, _T_295) node _T_298 = or(_T_297, _T_296) node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_300 = and(_T_298, _T_299) else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_303 = and(_T_301, _T_302) node _T_304 = andr(UInt<2>(0h0)) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_309 = or(_T_306, _T_307) node _T_310 = or(_T_309, _T_308) node _T_311 = eq(io.rw.addr, UInt<10>(0h301)) node _T_312 = and(_T_310, _T_311) else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_314 = eq(io.rw.addr, UInt<10>(0h301)) node _T_315 = and(_T_313, _T_314) node _T_316 = andr(UInt<2>(0h0)) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_321 = or(_T_318, _T_319) node _T_322 = or(_T_321, _T_320) node _T_323 = eq(io.rw.addr, UInt<10>(0h300)) node _T_324 = and(_T_322, _T_323) else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_326 = eq(io.rw.addr, UInt<10>(0h300)) node _T_327 = and(_T_325, _T_326) node _T_328 = andr(UInt<2>(0h0)) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_333 = or(_T_330, _T_331) node _T_334 = or(_T_333, _T_332) node _T_335 = eq(io.rw.addr, UInt<10>(0h305)) node _T_336 = and(_T_334, _T_335) else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_338 = eq(io.rw.addr, UInt<10>(0h305)) node _T_339 = and(_T_337, _T_338) node _T_340 = andr(UInt<2>(0h0)) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_345 = or(_T_342, _T_343) node _T_346 = or(_T_345, _T_344) node _T_347 = eq(io.rw.addr, UInt<10>(0h344)) node _T_348 = and(_T_346, _T_347) else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_350 = eq(io.rw.addr, UInt<10>(0h344)) node _T_351 = and(_T_349, _T_350) node _T_352 = andr(UInt<2>(0h0)) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_357 = or(_T_354, _T_355) node _T_358 = or(_T_357, _T_356) node _T_359 = eq(io.rw.addr, UInt<10>(0h304)) node _T_360 = and(_T_358, _T_359) else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_362 = eq(io.rw.addr, UInt<10>(0h304)) node _T_363 = and(_T_361, _T_362) node _T_364 = andr(UInt<2>(0h0)) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_369 = or(_T_366, _T_367) node _T_370 = or(_T_369, _T_368) node _T_371 = eq(io.rw.addr, UInt<10>(0h340)) node _T_372 = and(_T_370, _T_371) else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_374 = eq(io.rw.addr, UInt<10>(0h340)) node _T_375 = and(_T_373, _T_374) node _T_376 = andr(UInt<2>(0h0)) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_381 = or(_T_378, _T_379) node _T_382 = or(_T_381, _T_380) node _T_383 = eq(io.rw.addr, UInt<10>(0h341)) node _T_384 = and(_T_382, _T_383) else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_386 = eq(io.rw.addr, UInt<10>(0h341)) node _T_387 = and(_T_385, _T_386) node _T_388 = andr(UInt<2>(0h0)) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_393 = or(_T_390, _T_391) node _T_394 = or(_T_393, _T_392) node _T_395 = eq(io.rw.addr, UInt<10>(0h343)) node _T_396 = and(_T_394, _T_395) else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_398 = eq(io.rw.addr, UInt<10>(0h343)) node _T_399 = and(_T_397, _T_398) node _T_400 = andr(UInt<2>(0h0)) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_405 = or(_T_402, _T_403) node _T_406 = or(_T_405, _T_404) node _T_407 = eq(io.rw.addr, UInt<10>(0h342)) node _T_408 = and(_T_406, _T_407) else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_410 = eq(io.rw.addr, UInt<10>(0h342)) node _T_411 = and(_T_409, _T_410) node _T_412 = andr(UInt<2>(0h3)) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_417 = or(_T_414, _T_415) node _T_418 = or(_T_417, _T_416) node _T_419 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_420 = and(_T_418, _T_419) else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_422 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_423 = and(_T_421, _T_422) node _T_424 = andr(UInt<2>(0h1)) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_429 = or(_T_426, _T_427) node _T_430 = or(_T_429, _T_428) node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_432 = and(_T_430, _T_431) else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_435 = and(_T_433, _T_434) node _T_436 = andr(UInt<2>(0h1)) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_441 = or(_T_438, _T_439) node _T_442 = or(_T_441, _T_440) node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_444 = and(_T_442, _T_443) else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_447 = and(_T_445, _T_446) node _T_448 = andr(UInt<2>(0h1)) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_453 = or(_T_450, _T_451) node _T_454 = or(_T_453, _T_452) node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_456 = and(_T_454, _T_455) else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_459 = and(_T_457, _T_458) node _T_460 = andr(UInt<2>(0h0)) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_465 = or(_T_462, _T_463) node _T_466 = or(_T_465, _T_464) node _T_467 = eq(io.rw.addr, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_470 = eq(io.rw.addr, UInt<1>(0h1)) node _T_471 = and(_T_469, _T_470) node _T_472 = andr(UInt<2>(0h0)) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_477 = or(_T_474, _T_475) node _T_478 = or(_T_477, _T_476) node _T_479 = eq(io.rw.addr, UInt<2>(0h2)) node _T_480 = and(_T_478, _T_479) else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_482 = eq(io.rw.addr, UInt<2>(0h2)) node _T_483 = and(_T_481, _T_482) node _T_484 = andr(UInt<2>(0h0)) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_489 = or(_T_486, _T_487) node _T_490 = or(_T_489, _T_488) node _T_491 = eq(io.rw.addr, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_494 = eq(io.rw.addr, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = andr(UInt<2>(0h0)) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_501 = or(_T_498, _T_499) node _T_502 = or(_T_501, _T_500) node _T_503 = eq(io.rw.addr, UInt<10>(0h320)) node _T_504 = and(_T_502, _T_503) else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_506 = eq(io.rw.addr, UInt<10>(0h320)) node _T_507 = and(_T_505, _T_506) node _T_508 = andr(UInt<2>(0h2)) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_513 = or(_T_510, _T_511) node _T_514 = or(_T_513, _T_512) node _T_515 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_516 = and(_T_514, _T_515) else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_518 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_519 = and(_T_517, _T_518) node _T_520 = andr(UInt<2>(0h2)) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_525 = or(_T_522, _T_523) node _T_526 = or(_T_525, _T_524) node _T_527 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_528 = and(_T_526, _T_527) else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_530 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_531 = and(_T_529, _T_530) node _T_532 = andr(UInt<2>(0h0)) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_537 = or(_T_534, _T_535) node _T_538 = or(_T_537, _T_536) node _T_539 = eq(io.rw.addr, UInt<10>(0h323)) node _T_540 = and(_T_538, _T_539) else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_542 = eq(io.rw.addr, UInt<10>(0h323)) node _T_543 = and(_T_541, _T_542) node _T_544 = andr(UInt<2>(0h2)) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_549 = or(_T_546, _T_547) node _T_550 = or(_T_549, _T_548) node _T_551 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_552 = and(_T_550, _T_551) else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_554 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_555 = and(_T_553, _T_554) node _T_556 = andr(UInt<2>(0h0)) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_561 = or(_T_558, _T_559) node _T_562 = or(_T_561, _T_560) node _T_563 = eq(io.rw.addr, UInt<10>(0h324)) node _T_564 = and(_T_562, _T_563) else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_566 = eq(io.rw.addr, UInt<10>(0h324)) node _T_567 = and(_T_565, _T_566) node _T_568 = andr(UInt<2>(0h2)) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_573 = or(_T_570, _T_571) node _T_574 = or(_T_573, _T_572) node _T_575 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_576 = and(_T_574, _T_575) else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_578 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_579 = and(_T_577, _T_578) node _T_580 = andr(UInt<2>(0h0)) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_585 = or(_T_582, _T_583) node _T_586 = or(_T_585, _T_584) node _T_587 = eq(io.rw.addr, UInt<10>(0h325)) node _T_588 = and(_T_586, _T_587) else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_590 = eq(io.rw.addr, UInt<10>(0h325)) node _T_591 = and(_T_589, _T_590) node _T_592 = andr(UInt<2>(0h2)) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_597 = or(_T_594, _T_595) node _T_598 = or(_T_597, _T_596) node _T_599 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_600 = and(_T_598, _T_599) else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_602 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_603 = and(_T_601, _T_602) node _T_604 = andr(UInt<2>(0h0)) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_609 = or(_T_606, _T_607) node _T_610 = or(_T_609, _T_608) node _T_611 = eq(io.rw.addr, UInt<10>(0h326)) node _T_612 = and(_T_610, _T_611) else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_614 = eq(io.rw.addr, UInt<10>(0h326)) node _T_615 = and(_T_613, _T_614) node _T_616 = andr(UInt<2>(0h2)) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_621 = or(_T_618, _T_619) node _T_622 = or(_T_621, _T_620) node _T_623 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_624 = and(_T_622, _T_623) else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_626 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_627 = and(_T_625, _T_626) node _T_628 = andr(UInt<2>(0h0)) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_633 = or(_T_630, _T_631) node _T_634 = or(_T_633, _T_632) node _T_635 = eq(io.rw.addr, UInt<10>(0h327)) node _T_636 = and(_T_634, _T_635) else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_638 = eq(io.rw.addr, UInt<10>(0h327)) node _T_639 = and(_T_637, _T_638) node _T_640 = andr(UInt<2>(0h2)) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_645 = or(_T_642, _T_643) node _T_646 = or(_T_645, _T_644) node _T_647 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_648 = and(_T_646, _T_647) else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_650 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_651 = and(_T_649, _T_650) node _T_652 = andr(UInt<2>(0h0)) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_657 = or(_T_654, _T_655) node _T_658 = or(_T_657, _T_656) node _T_659 = eq(io.rw.addr, UInt<10>(0h328)) node _T_660 = and(_T_658, _T_659) else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_662 = eq(io.rw.addr, UInt<10>(0h328)) node _T_663 = and(_T_661, _T_662) node _T_664 = andr(UInt<2>(0h2)) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_669 = or(_T_666, _T_667) node _T_670 = or(_T_669, _T_668) node _T_671 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_672 = and(_T_670, _T_671) else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_674 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_675 = and(_T_673, _T_674) node _T_676 = andr(UInt<2>(0h0)) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_681 = or(_T_678, _T_679) node _T_682 = or(_T_681, _T_680) node _T_683 = eq(io.rw.addr, UInt<10>(0h329)) node _T_684 = and(_T_682, _T_683) else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_686 = eq(io.rw.addr, UInt<10>(0h329)) node _T_687 = and(_T_685, _T_686) node _T_688 = andr(UInt<2>(0h2)) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_693 = or(_T_690, _T_691) node _T_694 = or(_T_693, _T_692) node _T_695 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_696 = and(_T_694, _T_695) else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_698 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_699 = and(_T_697, _T_698) node _T_700 = andr(UInt<2>(0h0)) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_705 = or(_T_702, _T_703) node _T_706 = or(_T_705, _T_704) node _T_707 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_708 = and(_T_706, _T_707) else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_710 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_711 = and(_T_709, _T_710) node _T_712 = andr(UInt<2>(0h2)) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_717 = or(_T_714, _T_715) node _T_718 = or(_T_717, _T_716) node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_720 = and(_T_718, _T_719) else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_723 = and(_T_721, _T_722) node _T_724 = andr(UInt<2>(0h0)) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_729 = or(_T_726, _T_727) node _T_730 = or(_T_729, _T_728) node _T_731 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_732 = and(_T_730, _T_731) else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_734 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_735 = and(_T_733, _T_734) node _T_736 = andr(UInt<2>(0h2)) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_741 = or(_T_738, _T_739) node _T_742 = or(_T_741, _T_740) node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_744 = and(_T_742, _T_743) else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_747 = and(_T_745, _T_746) node _T_748 = andr(UInt<2>(0h0)) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_753 = or(_T_750, _T_751) node _T_754 = or(_T_753, _T_752) node _T_755 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_756 = and(_T_754, _T_755) else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_758 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_759 = and(_T_757, _T_758) node _T_760 = andr(UInt<2>(0h2)) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_765 = or(_T_762, _T_763) node _T_766 = or(_T_765, _T_764) node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_768 = and(_T_766, _T_767) else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_771 = and(_T_769, _T_770) node _T_772 = andr(UInt<2>(0h0)) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_777 = or(_T_774, _T_775) node _T_778 = or(_T_777, _T_776) node _T_779 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_780 = and(_T_778, _T_779) else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_782 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_783 = and(_T_781, _T_782) node _T_784 = andr(UInt<2>(0h2)) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_789 = or(_T_786, _T_787) node _T_790 = or(_T_789, _T_788) node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_792 = and(_T_790, _T_791) else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_795 = and(_T_793, _T_794) node _T_796 = andr(UInt<2>(0h0)) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_801 = or(_T_798, _T_799) node _T_802 = or(_T_801, _T_800) node _T_803 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_804 = and(_T_802, _T_803) else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_806 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_807 = and(_T_805, _T_806) node _T_808 = andr(UInt<2>(0h2)) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_813 = or(_T_810, _T_811) node _T_814 = or(_T_813, _T_812) node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_816 = and(_T_814, _T_815) else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_819 = and(_T_817, _T_818) node _T_820 = andr(UInt<2>(0h0)) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_825 = or(_T_822, _T_823) node _T_826 = or(_T_825, _T_824) node _T_827 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_828 = and(_T_826, _T_827) else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_830 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_831 = and(_T_829, _T_830) node _T_832 = andr(UInt<2>(0h2)) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_837 = or(_T_834, _T_835) node _T_838 = or(_T_837, _T_836) node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_840 = and(_T_838, _T_839) else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_843 = and(_T_841, _T_842) node _T_844 = andr(UInt<2>(0h0)) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_849 = or(_T_846, _T_847) node _T_850 = or(_T_849, _T_848) node _T_851 = eq(io.rw.addr, UInt<10>(0h330)) node _T_852 = and(_T_850, _T_851) else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_854 = eq(io.rw.addr, UInt<10>(0h330)) node _T_855 = and(_T_853, _T_854) node _T_856 = andr(UInt<2>(0h2)) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_864 = and(_T_862, _T_863) else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_866 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_867 = and(_T_865, _T_866) node _T_868 = andr(UInt<2>(0h0)) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_873 = or(_T_870, _T_871) node _T_874 = or(_T_873, _T_872) node _T_875 = eq(io.rw.addr, UInt<10>(0h331)) node _T_876 = and(_T_874, _T_875) else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_878 = eq(io.rw.addr, UInt<10>(0h331)) node _T_879 = and(_T_877, _T_878) node _T_880 = andr(UInt<2>(0h2)) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_885 = or(_T_882, _T_883) node _T_886 = or(_T_885, _T_884) node _T_887 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_888 = and(_T_886, _T_887) else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_890 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_891 = and(_T_889, _T_890) node _T_892 = andr(UInt<2>(0h0)) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_897 = or(_T_894, _T_895) node _T_898 = or(_T_897, _T_896) node _T_899 = eq(io.rw.addr, UInt<10>(0h332)) node _T_900 = and(_T_898, _T_899) else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_902 = eq(io.rw.addr, UInt<10>(0h332)) node _T_903 = and(_T_901, _T_902) node _T_904 = andr(UInt<2>(0h2)) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_909 = or(_T_906, _T_907) node _T_910 = or(_T_909, _T_908) node _T_911 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_912 = and(_T_910, _T_911) else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_914 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_915 = and(_T_913, _T_914) node _T_916 = andr(UInt<2>(0h0)) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_921 = or(_T_918, _T_919) node _T_922 = or(_T_921, _T_920) node _T_923 = eq(io.rw.addr, UInt<10>(0h333)) node _T_924 = and(_T_922, _T_923) else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_926 = eq(io.rw.addr, UInt<10>(0h333)) node _T_927 = and(_T_925, _T_926) node _T_928 = andr(UInt<2>(0h2)) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_933 = or(_T_930, _T_931) node _T_934 = or(_T_933, _T_932) node _T_935 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_936 = and(_T_934, _T_935) else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_938 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_939 = and(_T_937, _T_938) node _T_940 = andr(UInt<2>(0h0)) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_945 = or(_T_942, _T_943) node _T_946 = or(_T_945, _T_944) node _T_947 = eq(io.rw.addr, UInt<10>(0h334)) node _T_948 = and(_T_946, _T_947) else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_950 = eq(io.rw.addr, UInt<10>(0h334)) node _T_951 = and(_T_949, _T_950) node _T_952 = andr(UInt<2>(0h2)) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_957 = or(_T_954, _T_955) node _T_958 = or(_T_957, _T_956) node _T_959 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_960 = and(_T_958, _T_959) else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_962 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_963 = and(_T_961, _T_962) node _T_964 = andr(UInt<2>(0h0)) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_969 = or(_T_966, _T_967) node _T_970 = or(_T_969, _T_968) node _T_971 = eq(io.rw.addr, UInt<10>(0h335)) node _T_972 = and(_T_970, _T_971) else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_974 = eq(io.rw.addr, UInt<10>(0h335)) node _T_975 = and(_T_973, _T_974) node _T_976 = andr(UInt<2>(0h2)) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_981 = or(_T_978, _T_979) node _T_982 = or(_T_981, _T_980) node _T_983 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_984 = and(_T_982, _T_983) else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_986 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_987 = and(_T_985, _T_986) node _T_988 = andr(UInt<2>(0h0)) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_993 = or(_T_990, _T_991) node _T_994 = or(_T_993, _T_992) node _T_995 = eq(io.rw.addr, UInt<10>(0h336)) node _T_996 = and(_T_994, _T_995) else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_998 = eq(io.rw.addr, UInt<10>(0h336)) node _T_999 = and(_T_997, _T_998) node _T_1000 = andr(UInt<2>(0h2)) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1005 = or(_T_1002, _T_1003) node _T_1006 = or(_T_1005, _T_1004) node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1008 = and(_T_1006, _T_1007) else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = andr(UInt<2>(0h0)) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1017 = or(_T_1014, _T_1015) node _T_1018 = or(_T_1017, _T_1016) node _T_1019 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1020 = and(_T_1018, _T_1019) else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1022 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = andr(UInt<2>(0h2)) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1029 = or(_T_1026, _T_1027) node _T_1030 = or(_T_1029, _T_1028) node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1032 = and(_T_1030, _T_1031) else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1035 = and(_T_1033, _T_1034) node _T_1036 = andr(UInt<2>(0h0)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1041 = or(_T_1038, _T_1039) node _T_1042 = or(_T_1041, _T_1040) node _T_1043 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1044 = and(_T_1042, _T_1043) else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1046 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = andr(UInt<2>(0h2)) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1053 = or(_T_1050, _T_1051) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1056 = and(_T_1054, _T_1055) else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = andr(UInt<2>(0h0)) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1065 = or(_T_1062, _T_1063) node _T_1066 = or(_T_1065, _T_1064) node _T_1067 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1068 = and(_T_1066, _T_1067) else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1070 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = andr(UInt<2>(0h2)) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1077 = or(_T_1074, _T_1075) node _T_1078 = or(_T_1077, _T_1076) node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1080 = and(_T_1078, _T_1079) else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = andr(UInt<2>(0h0)) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1089 = or(_T_1086, _T_1087) node _T_1090 = or(_T_1089, _T_1088) node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1092 = and(_T_1090, _T_1091) else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = andr(UInt<2>(0h2)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1101 = or(_T_1098, _T_1099) node _T_1102 = or(_T_1101, _T_1100) node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1104 = and(_T_1102, _T_1103) else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = andr(UInt<2>(0h0)) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1113 = or(_T_1110, _T_1111) node _T_1114 = or(_T_1113, _T_1112) node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1116 = and(_T_1114, _T_1115) else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = andr(UInt<2>(0h2)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1125 = or(_T_1122, _T_1123) node _T_1126 = or(_T_1125, _T_1124) node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1128 = and(_T_1126, _T_1127) else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = andr(UInt<2>(0h0)) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1137 = or(_T_1134, _T_1135) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1140 = and(_T_1138, _T_1139) else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = andr(UInt<2>(0h2)) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1149 = or(_T_1146, _T_1147) node _T_1150 = or(_T_1149, _T_1148) node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1152 = and(_T_1150, _T_1151) else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = andr(UInt<2>(0h0)) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1161 = or(_T_1158, _T_1159) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1164 = and(_T_1162, _T_1163) else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = andr(UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1173 = or(_T_1170, _T_1171) node _T_1174 = or(_T_1173, _T_1172) node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1176 = and(_T_1174, _T_1175) else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = andr(UInt<2>(0h0)) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1185 = or(_T_1182, _T_1183) node _T_1186 = or(_T_1185, _T_1184) node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1188 = and(_T_1186, _T_1187) else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = andr(UInt<2>(0h2)) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1197 = or(_T_1194, _T_1195) node _T_1198 = or(_T_1197, _T_1196) node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1200 = and(_T_1198, _T_1199) else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = andr(UInt<2>(0h0)) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1209 = or(_T_1206, _T_1207) node _T_1210 = or(_T_1209, _T_1208) node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1212 = and(_T_1210, _T_1211) else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = andr(UInt<2>(0h2)) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1221 = or(_T_1218, _T_1219) node _T_1222 = or(_T_1221, _T_1220) node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1224 = and(_T_1222, _T_1223) else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = andr(UInt<2>(0h0)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1233 = or(_T_1230, _T_1231) node _T_1234 = or(_T_1233, _T_1232) node _T_1235 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1236 = and(_T_1234, _T_1235) else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1238 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = andr(UInt<2>(0h3)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1245 = or(_T_1242, _T_1243) node _T_1246 = or(_T_1245, _T_1244) node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1248 = and(_T_1246, _T_1247) else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = andr(UInt<2>(0h3)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1257 = or(_T_1254, _T_1255) node _T_1258 = or(_T_1257, _T_1256) node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1260 = and(_T_1258, _T_1259) else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = andr(UInt<2>(0h0)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1269 = or(_T_1266, _T_1267) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1272 = and(_T_1270, _T_1271) else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = andr(UInt<2>(0h0)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1281 = or(_T_1278, _T_1279) node _T_1282 = or(_T_1281, _T_1280) node _T_1283 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1284 = and(_T_1282, _T_1283) else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1286 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = andr(UInt<2>(0h0)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1293 = or(_T_1290, _T_1291) node _T_1294 = or(_T_1293, _T_1292) node _T_1295 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1296 = and(_T_1294, _T_1295) else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1298 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = andr(UInt<2>(0h0)) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1305 = or(_T_1302, _T_1303) node _T_1306 = or(_T_1305, _T_1304) node _T_1307 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1308 = and(_T_1306, _T_1307) else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1310 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = andr(UInt<2>(0h0)) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1317 = or(_T_1314, _T_1315) node _T_1318 = or(_T_1317, _T_1316) node _T_1319 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1320 = and(_T_1318, _T_1319) else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1322 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = andr(UInt<2>(0h0)) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1329 = or(_T_1326, _T_1327) node _T_1330 = or(_T_1329, _T_1328) node _T_1331 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1332 = and(_T_1330, _T_1331) else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1334 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = andr(UInt<2>(0h0)) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1341 = or(_T_1338, _T_1339) node _T_1342 = or(_T_1341, _T_1340) node _T_1343 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1344 = and(_T_1342, _T_1343) else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1346 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = andr(UInt<2>(0h0)) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1353 = or(_T_1350, _T_1351) node _T_1354 = or(_T_1353, _T_1352) node _T_1355 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1356 = and(_T_1354, _T_1355) else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1358 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = andr(UInt<2>(0h0)) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1365 = or(_T_1362, _T_1363) node _T_1366 = or(_T_1365, _T_1364) node _T_1367 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1368 = and(_T_1366, _T_1367) else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1370 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1371 = and(_T_1369, _T_1370) node _T_1372 = andr(UInt<2>(0h0)) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1377 = or(_T_1374, _T_1375) node _T_1378 = or(_T_1377, _T_1376) node _T_1379 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1380 = and(_T_1378, _T_1379) else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1382 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = andr(UInt<2>(0h0)) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1389 = or(_T_1386, _T_1387) node _T_1390 = or(_T_1389, _T_1388) node _T_1391 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1392 = and(_T_1390, _T_1391) else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1394 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = andr(UInt<2>(0h0)) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1401 = or(_T_1398, _T_1399) node _T_1402 = or(_T_1401, _T_1400) node _T_1403 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1404 = and(_T_1402, _T_1403) else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1406 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = andr(UInt<2>(0h0)) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1413 = or(_T_1410, _T_1411) node _T_1414 = or(_T_1413, _T_1412) node _T_1415 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1416 = and(_T_1414, _T_1415) else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1418 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = andr(UInt<2>(0h0)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1425 = or(_T_1422, _T_1423) node _T_1426 = or(_T_1425, _T_1424) node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1428 = and(_T_1426, _T_1427) else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = andr(UInt<2>(0h0)) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1437 = or(_T_1434, _T_1435) node _T_1438 = or(_T_1437, _T_1436) node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1440 = and(_T_1438, _T_1439) else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = andr(UInt<2>(0h0)) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1449 = or(_T_1446, _T_1447) node _T_1450 = or(_T_1449, _T_1448) node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1452 = and(_T_1450, _T_1451) else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = andr(UInt<2>(0h0)) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1461 = or(_T_1458, _T_1459) node _T_1462 = or(_T_1461, _T_1460) node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1464 = and(_T_1462, _T_1463) else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = andr(UInt<2>(0h0)) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1473 = or(_T_1470, _T_1471) node _T_1474 = or(_T_1473, _T_1472) node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1476 = and(_T_1474, _T_1475) else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = andr(UInt<2>(0h0)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1485 = or(_T_1482, _T_1483) node _T_1486 = or(_T_1485, _T_1484) node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1488 = and(_T_1486, _T_1487) else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = andr(UInt<2>(0h0)) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1497 = or(_T_1494, _T_1495) node _T_1498 = or(_T_1497, _T_1496) node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1500 = and(_T_1498, _T_1499) else : node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = andr(UInt<2>(0h0)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1509 = or(_T_1506, _T_1507) node _T_1510 = or(_T_1509, _T_1508) node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1512 = and(_T_1510, _T_1511) else : node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = andr(UInt<2>(0h0)) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1521 = or(_T_1518, _T_1519) node _T_1522 = or(_T_1521, _T_1520) node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1524 = and(_T_1522, _T_1523) else : node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = andr(UInt<2>(0h0)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1533 = or(_T_1530, _T_1531) node _T_1534 = or(_T_1533, _T_1532) node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1536 = and(_T_1534, _T_1535) else : node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1539 = and(_T_1537, _T_1538) node _T_1540 = andr(UInt<2>(0h0)) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1545 = or(_T_1542, _T_1543) node _T_1546 = or(_T_1545, _T_1544) node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1548 = and(_T_1546, _T_1547) else : node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = andr(UInt<2>(0h0)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1557 = or(_T_1554, _T_1555) node _T_1558 = or(_T_1557, _T_1556) node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1560 = and(_T_1558, _T_1559) else : node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = andr(UInt<2>(0h0)) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1569 = or(_T_1566, _T_1567) node _T_1570 = or(_T_1569, _T_1568) node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1572 = and(_T_1570, _T_1571) else : node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = andr(UInt<2>(0h0)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1581 = or(_T_1578, _T_1579) node _T_1582 = or(_T_1581, _T_1580) node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1584 = and(_T_1582, _T_1583) else : node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1587 = and(_T_1585, _T_1586) node _T_1588 = andr(UInt<2>(0h0)) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1593 = or(_T_1590, _T_1591) node _T_1594 = or(_T_1593, _T_1592) node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1596 = and(_T_1594, _T_1595) else : node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = andr(UInt<2>(0h0)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1605 = or(_T_1602, _T_1603) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1608 = and(_T_1606, _T_1607) else : node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = andr(UInt<2>(0h0)) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1617 = or(_T_1614, _T_1615) node _T_1618 = or(_T_1617, _T_1616) node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1620 = and(_T_1618, _T_1619) else : node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = andr(UInt<2>(0h0)) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1629 = or(_T_1626, _T_1627) node _T_1630 = or(_T_1629, _T_1628) node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1632 = and(_T_1630, _T_1631) else : node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = andr(UInt<2>(0h0)) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1641 = or(_T_1638, _T_1639) node _T_1642 = or(_T_1641, _T_1640) node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1644 = and(_T_1642, _T_1643) else : node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = andr(UInt<2>(0h1)) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1653 = or(_T_1650, _T_1651) node _T_1654 = or(_T_1653, _T_1652) node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1656 = and(_T_1654, _T_1655) else : node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = andr(UInt<2>(0h3)) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1665 = or(_T_1662, _T_1663) node _T_1666 = or(_T_1665, _T_1664) node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1668 = and(_T_1666, _T_1667) else : node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = andr(UInt<2>(0h3)) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1677 = or(_T_1674, _T_1675) node _T_1678 = or(_T_1677, _T_1676) node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1680 = and(_T_1678, _T_1679) else : node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = andr(UInt<2>(0h3)) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1689 = or(_T_1686, _T_1687) node _T_1690 = or(_T_1689, _T_1688) node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1692 = and(_T_1690, _T_1691) else : node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = andr(UInt<2>(0h3)) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1701 = or(_T_1698, _T_1699) node _T_1702 = or(_T_1701, _T_1700) node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1704 = and(_T_1702, _T_1703) else : node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1707 = and(_T_1705, _T_1706) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_100_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.mprv, new_mstatus.mprv node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2)) node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3 connect reg_mstatus.spp, new_mstatus.spp connect reg_mstatus.spie, new_mstatus.spie connect reg_mstatus.sie, new_mstatus.sie connect reg_mstatus.tw, new_mstatus.tw connect reg_mstatus.tsr, new_mstatus.tsr connect reg_mstatus.mxr, new_mstatus.mxr connect reg_mstatus.sum, new_mstatus.sum connect reg_mstatus.tvm, new_mstatus.tvm node _reg_mstatus_fs_T = orr(new_mstatus.fs) node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_1 connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_94_2 : node f = bits(wdata, 5, 5) node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_1709 = bits(io.pc, 1, 1) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1708, _T_1710) node _T_1712 = bits(wdata, 2, 2) node _T_1713 = or(_T_1711, _T_1712) when _T_1713 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) node _reg_misa_T_6 = not(UInt<64>(0h102d)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_108_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 connect reg_mip.ssip, new_mip.ssip connect reg_mip.stip, new_mip.stip connect reg_mip.seip, new_mip.seip when decoded_addr_76_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_132_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_129_2 : connect reg_mscratch, wdata when decoded_addr_72_2 : connect reg_mtvec, wdata when decoded_addr_29_2 : node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_136_2 : connect reg_mtval, wdata when decoded_addr_130_2 : node _reg_mcountinhibit_T = not(UInt<64>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_103_2 : node _T_1714 = bits(wdata, 63, 0) connect small_1, _T_1714 node _large_T_6 = shr(_T_1714, 6) connect large_1, _large_T_6 when decoded_addr_121_2 : node _T_1715 = bits(wdata, 63, 0) connect small, _T_1715 node _large_T_7 = shr(_T_1715, 6) connect large, _large_T_7 when decoded_addr_36_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata when decoded_addr_68_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_frm, wdata when decoded_addr_99_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata node _reg_frm_T = shr(wdata, 5) connect reg_frm, _reg_frm_T when decoded_addr_49_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm connect reg_dcsr.ebreaks, new_dcsr.ebreaks connect reg_dcsr.ebreaku, new_dcsr.ebreaku node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2)) node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv) connect reg_dcsr.prv, _reg_dcsr_prv_T_1 when decoded_addr_89_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_57_2 : connect reg_dscratch0, wdata when decoded_addr_61_2 : wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_sstatus_WIRE : UInt<105> connect _new_sstatus_WIRE, wdata node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0) connect new_sstatus.uie, _new_sstatus_T node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1) connect new_sstatus.sie, _new_sstatus_T_1 node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2) connect new_sstatus.hie, _new_sstatus_T_2 node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3) connect new_sstatus.mie, _new_sstatus_T_3 node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4) connect new_sstatus.upie, _new_sstatus_T_4 node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5) connect new_sstatus.spie, _new_sstatus_T_5 node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6) connect new_sstatus.ube, _new_sstatus_T_6 node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7) connect new_sstatus.mpie, _new_sstatus_T_7 node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8) connect new_sstatus.spp, _new_sstatus_T_8 node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9) connect new_sstatus.vs, _new_sstatus_T_9 node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11) connect new_sstatus.mpp, _new_sstatus_T_10 node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13) connect new_sstatus.fs, _new_sstatus_T_11 node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15) connect new_sstatus.xs, _new_sstatus_T_12 node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17) connect new_sstatus.mprv, _new_sstatus_T_13 node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18) connect new_sstatus.sum, _new_sstatus_T_14 node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19) connect new_sstatus.mxr, _new_sstatus_T_15 node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20) connect new_sstatus.tvm, _new_sstatus_T_16 node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21) connect new_sstatus.tw, _new_sstatus_T_17 node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22) connect new_sstatus.tsr, _new_sstatus_T_18 node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23) connect new_sstatus.zero1, _new_sstatus_T_19 node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31) connect new_sstatus.sd_rv32, _new_sstatus_T_20 node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32) connect new_sstatus.uxl, _new_sstatus_T_21 node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34) connect new_sstatus.sxl, _new_sstatus_T_22 node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36) connect new_sstatus.sbe, _new_sstatus_T_23 node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37) connect new_sstatus.mbe, _new_sstatus_T_24 node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38) connect new_sstatus.gva, _new_sstatus_T_25 node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39) connect new_sstatus.mpv, _new_sstatus_T_26 node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40) connect new_sstatus.zero2, _new_sstatus_T_27 node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63) connect new_sstatus.sd, _new_sstatus_T_28 node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64) connect new_sstatus.v, _new_sstatus_T_29 node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65) connect new_sstatus.prv, _new_sstatus_T_30 node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67) connect new_sstatus.dv, _new_sstatus_T_31 node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68) connect new_sstatus.dprv, _new_sstatus_T_32 node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70) connect new_sstatus.isa, _new_sstatus_T_33 node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102) connect new_sstatus.wfi, _new_sstatus_T_34 node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103) connect new_sstatus.cease, _new_sstatus_T_35 node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104) connect new_sstatus.debug, _new_sstatus_T_36 connect reg_mstatus.sie, new_sstatus.sie connect reg_mstatus.spie, new_sstatus.spie connect reg_mstatus.spp, new_sstatus.spp node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs) node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_3 connect reg_mstatus.vs, UInt<1>(0h0) connect reg_mstatus.mxr, new_sstatus.mxr connect reg_mstatus.sum, new_sstatus.sum when decoded_addr_48_2 : node _new_sip_T = not(read_mideleg) node _new_sip_T_1 = and(read_mip, _new_sip_T) node _new_sip_T_2 = and(wdata, read_mideleg) node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2) wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_sip_WIRE : UInt<16> connect _new_sip_WIRE, _new_sip_T_3 node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0) connect new_sip.usip, _new_sip_T_4 node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1) connect new_sip.ssip, _new_sip_T_5 node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2) connect new_sip.vssip, _new_sip_T_6 node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3) connect new_sip.msip, _new_sip_T_7 node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4) connect new_sip.utip, _new_sip_T_8 node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5) connect new_sip.stip, _new_sip_T_9 node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6) connect new_sip.vstip, _new_sip_T_10 node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7) connect new_sip.mtip, _new_sip_T_11 node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8) connect new_sip.ueip, _new_sip_T_12 node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9) connect new_sip.seip, _new_sip_T_13 node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10) connect new_sip.vseip, _new_sip_T_14 node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11) connect new_sip.meip, _new_sip_T_15 node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12) connect new_sip.sgeip, _new_sip_T_16 node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13) connect new_sip.rocc, _new_sip_T_17 node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14) connect new_sip.debug, _new_sip_T_18 node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15) connect new_sip.zero1, _new_sip_T_19 connect reg_mip.ssip, new_sip.ssip when decoded_addr_6_2 : wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} wire _new_satp_WIRE : UInt<64> connect _new_satp_WIRE, wdata node _new_satp_T = bits(_new_satp_WIRE, 43, 0) connect new_satp.ppn, _new_satp_T node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44) connect new_satp.asid, _new_satp_T_1 node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60) connect new_satp.mode, _new_satp_T_2 node _T_1716 = eq(new_satp.mode, UInt<1>(0h0)) node _T_1717 = eq(new_satp.mode, UInt<4>(0h8)) node _T_1718 = or(_T_1716, _T_1717) when _T_1718 : node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8)) connect reg_satp.mode, _reg_satp_mode_T node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0) connect reg_satp.ppn, _reg_satp_ppn_T when decoded_addr_44_2 : node _reg_mie_T_1 = not(sie_mask) node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1) node _reg_mie_T_3 = and(wdata, sie_mask) node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3) connect reg_mie, _reg_mie_T_4 when decoded_addr_15_2 : connect reg_sscratch, wdata when decoded_addr_28_2 : node _reg_sepc_T = not(wdata) node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1)) node _reg_sepc_T_2 = not(_reg_sepc_T_1) connect reg_sepc, _reg_sepc_T_2 when decoded_addr_25_2 : connect reg_stvec, wdata when decoded_addr_145_2 : node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f)) connect reg_scause, _reg_scause_T when decoded_addr_93_2 : connect reg_stval, wdata when decoded_addr_123_2 : connect reg_mideleg, wdata when decoded_addr_23_2 : connect reg_medeleg, wdata when decoded_addr_137_2 : connect reg_scounteren, wdata when decoded_addr_69_2 : wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE : UInt<64> connect _new_envcfg_WIRE, wdata node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0) connect new_envcfg.fiom, _new_envcfg_T node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1) connect new_envcfg.zero3, _new_envcfg_T_1 node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4) connect new_envcfg.cbie, _new_envcfg_T_2 node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6) connect new_envcfg.cbcfe, _new_envcfg_T_3 node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7) connect new_envcfg.cbze, _new_envcfg_T_4 node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8) connect new_envcfg.zero54, _new_envcfg_T_5 node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62) connect new_envcfg.pbmte, _new_envcfg_T_6 node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63) connect new_envcfg.stce, _new_envcfg_T_7 connect reg_senvcfg.fiom, new_envcfg.fiom when decoded_addr_35_2 : connect reg_mcounteren, wdata when decoded_addr_42_2 : wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE_1 : UInt<64> connect _new_envcfg_WIRE_1, wdata node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0) connect new_envcfg_1.fiom, _new_envcfg_T_8 node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1) connect new_envcfg_1.zero3, _new_envcfg_T_9 node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4) connect new_envcfg_1.cbie, _new_envcfg_T_10 node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6) connect new_envcfg_1.cbcfe, _new_envcfg_T_11 node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7) connect new_envcfg_1.cbze, _new_envcfg_T_12 node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8) connect new_envcfg_1.zero54, _new_envcfg_T_13 node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62) connect new_envcfg_1.pbmte, _new_envcfg_T_14 node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63) connect new_envcfg_1.stce, _new_envcfg_T_15 connect reg_menvcfg.fiom, new_envcfg_1.fiom when decoded_addr_97_2 : connect reg_tselect, wdata node _T_1719 = eq(UInt<1>(0h0), reg_tselect) node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_1721 = or(_T_1720, reg_debug) node _T_1722 = and(_T_1719, _T_1721) when _T_1722 : when decoded_addr_10_2 : connect reg_bp[0].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<64> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<64> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_1723 = gt(newBPC.action, UInt<1>(0h1)) node _T_1724 = or(dMode, _T_1723) when _T_1724 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_1725 = eq(UInt<1>(0h1), reg_tselect) node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_1727 = or(_T_1726, reg_debug) node _T_1728 = and(_T_1725, _T_1727) when _T_1728 : when decoded_addr_10_2 : connect reg_bp[1].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<64> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<64> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_1730 = or(dMode_1, _T_1729) when _T_1730 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_1732 = and(decoded_addr_141_2, _T_1731) when _T_1732 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736) node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737) node _T_1739 = eq(_T_1738, UInt<1>(0h0)) node _T_1740 = and(decoded_addr_104_2, _T_1739) when _T_1740 : connect reg_pmp[0].addr, wdata node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_1742 = and(decoded_addr_141_2, _T_1741) when _T_1742 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746) node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = and(decoded_addr_8_2, _T_1749) when _T_1750 : connect reg_pmp[1].addr, wdata node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_1752 = and(decoded_addr_141_2, _T_1751) when _T_1752 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756) node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = and(decoded_addr_125_2, _T_1759) when _T_1760 : connect reg_pmp[2].addr, wdata node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_1762 = and(decoded_addr_141_2, _T_1761) when _T_1762 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766) node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = and(decoded_addr_85_2, _T_1769) when _T_1770 : connect reg_pmp[3].addr, wdata node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_1772 = and(decoded_addr_141_2, _T_1771) when _T_1772 : node _newCfg_T_28 = shr(wdata, 32) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776) node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) node _T_1780 = and(decoded_addr_54_2, _T_1779) when _T_1780 : connect reg_pmp[4].addr, wdata node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_1782 = and(decoded_addr_141_2, _T_1781) when _T_1782 : node _newCfg_T_35 = shr(wdata, 40) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786) node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = and(decoded_addr_20_2, _T_1789) when _T_1790 : connect reg_pmp[5].addr, wdata node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_1792 = and(decoded_addr_141_2, _T_1791) when _T_1792 : node _newCfg_T_42 = shr(wdata, 48) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1796 = and(_T_1794, _T_1795) node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796) node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = and(decoded_addr_135_2, _T_1799) when _T_1800 : connect reg_pmp[6].addr, wdata node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_1802 = and(decoded_addr_141_2, _T_1801) when _T_1802 : node _newCfg_T_49 = shr(wdata, 56) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806) node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = and(decoded_addr_115_2, _T_1809) when _T_1810 : connect reg_pmp[7].addr, wdata when decoded_addr_18_2 : node _reg_custom_0_T = and(wdata, UInt<64>(0h208)) node _reg_custom_0_T_1 = not(UInt<64>(0h208)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) node _reg_custom_1_T_1 = not(UInt<64>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_38_2 : node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) node _reg_custom_2_T_1 = not(UInt<64>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_127_2 : node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) node _reg_custom_3_T_1 = not(UInt<64>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208)) node _reg_custom_0_T_5 = not(UInt<64>(0h208)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) node _reg_custom_1_T_5 = not(UInt<64>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) node _reg_custom_2_T_5 = not(UInt<64>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) node _reg_custom_3_T_5 = not(UInt<64>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_1811 = asUInt(reset) when _T_1811 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) node _T_1812 = asUInt(reset) when _T_1812 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) node _T_1813 = asUInt(reset) when _T_1813 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<39>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_1814 = asUInt(reset) when _T_1814 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_1815 = asUInt(reset) when _T_1815 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_1816 = asUInt(reset) when _T_1816 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_1817 = asUInt(reset) when _T_1817 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_1818 = asUInt(reset) when _T_1818 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_1819 = asUInt(reset) when _T_1819 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_1820 = asUInt(reset) when _T_1820 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_1821 = asUInt(reset) when _T_1821 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 63, 63) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval

module CSRFile_7( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input [2:0] io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output io_hstatus_spvp, // @[CSR.scala:384:14] output io_hstatus_spv, // @[CSR.scala:384:14] output io_hstatus_gva, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output io_gstatus_sd, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output [1:0] io_gstatus_vs, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input [39:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [63:0] io_trace_0_cause, // @[CSR.scala:384:14] output [39:0] io_trace_0_tval, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire [2:0] io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire delegable_24 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire delegable_29 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire delegable_26 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67] wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48] wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp_0; // @[CSR.scala:377:7] wire io_hstatus_spv_0; // @[CSR.scala:377:7] wire io_hstatus_gva_0; // @[CSR.scala:377:7] wire io_gstatus_sd_0; // @[CSR.scala:377:7] wire io_gstatus_spp_0; // @[CSR.scala:377:7] wire io_gstatus_spie_0; // @[CSR.scala:377:7] wire io_gstatus_sie_0; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_m_0; // @[CSR.scala:377:7] wire io_bp_0_control_s_0; // @[CSR.scala:377:7] wire io_bp_0_control_u_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48] assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67] assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48] assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67] assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67] wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67] wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48] wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38] wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78] assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 | _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}] assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_476 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0

module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_476( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)

Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 : input clock : Clock input reset : Reset output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clientNodeOut.d.bits.corrupt invalidate clientNodeOut.d.bits.data invalidate clientNodeOut.d.bits.denied invalidate clientNodeOut.d.bits.sink invalidate clientNodeOut.d.bits.source invalidate clientNodeOut.d.bits.size invalidate clientNodeOut.d.bits.param invalidate clientNodeOut.d.bits.opcode invalidate clientNodeOut.d.valid invalidate clientNodeOut.d.ready invalidate clientNodeOut.a.bits.corrupt invalidate clientNodeOut.a.bits.data invalidate clientNodeOut.a.bits.mask invalidate clientNodeOut.a.bits.address invalidate clientNodeOut.a.bits.source invalidate clientNodeOut.a.bits.size invalidate clientNodeOut.a.bits.param invalidate clientNodeOut.a.bits.opcode invalidate clientNodeOut.a.valid invalidate clientNodeOut.a.ready connect auto.client_out, clientNodeOut wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect manager_tl.e.bits.sink, UInt<8>(0h0) connect manager_tl.e.valid, UInt<1>(0h0) connect manager_tl.e.ready, UInt<1>(0h0) connect manager_tl.d.bits.corrupt, UInt<1>(0h0) connect manager_tl.d.bits.data, UInt<64>(0h0) connect manager_tl.d.bits.denied, UInt<1>(0h0) connect manager_tl.d.bits.sink, UInt<8>(0h0) connect manager_tl.d.bits.source, UInt<8>(0h0) connect manager_tl.d.bits.size, UInt<8>(0h0) connect manager_tl.d.bits.param, UInt<2>(0h0) connect manager_tl.d.bits.opcode, UInt<3>(0h0) connect manager_tl.d.valid, UInt<1>(0h0) connect manager_tl.d.ready, UInt<1>(0h0) connect manager_tl.c.bits.corrupt, UInt<1>(0h0) connect manager_tl.c.bits.data, UInt<64>(0h0) connect manager_tl.c.bits.address, UInt<64>(0h0) connect manager_tl.c.bits.source, UInt<8>(0h0) connect manager_tl.c.bits.size, UInt<8>(0h0) connect manager_tl.c.bits.param, UInt<3>(0h0) connect manager_tl.c.bits.opcode, UInt<3>(0h0) connect manager_tl.c.valid, UInt<1>(0h0) connect manager_tl.c.ready, UInt<1>(0h0) connect manager_tl.b.bits.corrupt, UInt<1>(0h0) connect manager_tl.b.bits.data, UInt<64>(0h0) connect manager_tl.b.bits.mask, UInt<8>(0h0) connect manager_tl.b.bits.address, UInt<64>(0h0) connect manager_tl.b.bits.source, UInt<8>(0h0) connect manager_tl.b.bits.size, UInt<8>(0h0) connect manager_tl.b.bits.param, UInt<2>(0h0) connect manager_tl.b.bits.opcode, UInt<3>(0h0) connect manager_tl.b.valid, UInt<1>(0h0) connect manager_tl.b.ready, UInt<1>(0h0) connect manager_tl.a.bits.corrupt, UInt<1>(0h0) connect manager_tl.a.bits.data, UInt<64>(0h0) connect manager_tl.a.bits.mask, UInt<8>(0h0) connect manager_tl.a.bits.address, UInt<64>(0h0) connect manager_tl.a.bits.source, UInt<8>(0h0) connect manager_tl.a.bits.size, UInt<8>(0h0) connect manager_tl.a.bits.param, UInt<3>(0h0) connect manager_tl.a.bits.opcode, UInt<3>(0h0) connect manager_tl.a.valid, UInt<1>(0h0) connect manager_tl.a.ready, UInt<1>(0h0) inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_1_2.clock, clock connect out_channels_1_2.reset, reset wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE.bits.data, UInt<64>(0h0) connect _out_channels_WIRE.bits.mask, UInt<8>(0h0) connect _out_channels_WIRE.bits.address, UInt<32>(0h0) connect _out_channels_WIRE.bits.source, UInt<4>(0h0) connect _out_channels_WIRE.bits.size, UInt<4>(0h0) connect _out_channels_WIRE.bits.param, UInt<2>(0h0) connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_3_1.bits, _out_channels_WIRE.bits connect out_channels_3_1.valid, _out_channels_WIRE.valid connect out_channels_3_1.ready, _out_channels_WIRE.ready inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_3_2.clock, clock connect out_channels_3_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_1_2.io.protocol, clientNodeOut.d inst ser_1 of GenericSerializer_TLBeatw67_f32 connect ser_1.clock, clock connect ser_1.reset, reset connect ser_1.io.in, out_channels_1_2.io.beat connect io.ser[1].out.bits, ser_1.io.out.bits connect io.ser[1].out.valid, ser_1.io.out.valid connect ser_1.io.out.ready, io.ser[1].out.ready connect out_channels_3_2.io.protocol, out_channels_3_1 inst ser_3 of GenericSerializer_TLBeatw87_f32 connect ser_3.clock, clock connect ser_3.reset, reset connect ser_3.io.in, out_channels_3_2.io.beat connect io.ser[3].out.bits, ser_3.io.out.bits connect io.ser[3].out.valid, ser_3.io.out.valid connect ser_3.io.out.ready, io.ser[3].out.ready node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _in_channels_WIRE.bits.sink, UInt<3>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect in_channels_0_1.bits, _in_channels_WIRE.bits connect in_channels_0_1.valid, _in_channels_WIRE.valid connect in_channels_0_1.ready, _in_channels_WIRE.ready inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE_1.valid, UInt<1>(0h0) connect _in_channels_WIRE_1.ready, UInt<1>(0h0) wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_2_1.bits, _in_channels_WIRE_1.bits connect in_channels_2_1.valid, _in_channels_WIRE_1.valid connect in_channels_2_1.ready, _in_channels_WIRE_1.ready inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready inst des_0 of GenericDeserializer_TLBeatw10_f32 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready inst des_2 of GenericDeserializer_TLBeatw88_f32 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready inst des_3 of GenericDeserializer_TLBeatw87_f32 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_1 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3

module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_1_out_ready, // @[TLSerdes.scala:40:16] output io_ser_1_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_3_out_ready, // @[TLSerdes.scala:40:16] output io_ser_3_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28] wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23] wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50] wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50] wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50] wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50] TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50] .clock (clock), .reset (reset), .io_protocol_ready (auto_client_out_d_ready), .io_protocol_valid (auto_client_out_d_valid), .io_protocol_bits_opcode (auto_client_out_d_bits_opcode), .io_protocol_bits_param (auto_client_out_d_bits_param), .io_protocol_bits_size ({4'h0, auto_client_out_d_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({4'h0, auto_client_out_d_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_sink ({5'h0, auto_client_out_d_bits_sink}), // @[TLSerdes.scala:68:21] .io_protocol_bits_denied (auto_client_out_d_bits_denied), .io_protocol_bits_data (auto_client_out_d_bits_data), .io_protocol_bits_corrupt (auto_client_out_d_bits_corrupt), .io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_1_2_io_beat_valid), .io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_1_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail) ); // @[TLSerdes.scala:60:50] TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50] .clock (clock), .reset (reset), .io_beat_bits_head (_out_channels_3_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail) ); // @[TLSerdes.scala:62:50] GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_1_io_in_ready), .io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50] .io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50] .io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50] .io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50] .io_out_ready (io_ser_1_out_ready), .io_out_valid (io_ser_1_out_valid), .io_out_bits_flit (io_ser_1_out_bits_flit) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50] .io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50] .io_out_ready (io_ser_3_out_ready), .io_out_valid (io_ser_3_out_valid), .io_out_bits_flit (io_ser_3_out_bits_flit) ); // @[TLSerdes.scala:69:23] TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_ready (auto_client_out_a_ready), .io_protocol_valid (auto_client_out_a_valid), .io_protocol_bits_opcode (auto_client_out_a_bits_opcode), .io_protocol_bits_param (auto_client_out_a_bits_param), .io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address), .io_protocol_bits_mask (auto_client_out_a_bits_mask), .io_protocol_bits_data (auto_client_out_a_bits_data), .io_protocol_bits_corrupt (auto_client_out_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23] .io_in_ready (io_ser_0_in_ready), .io_in_valid (io_ser_0_in_valid), .io_in_bits_flit (io_ser_0_in_bits_flit), .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready), .io_in_valid (io_ser_1_in_valid), .io_in_bits_flit (io_ser_1_in_bits_flit), .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (/* unused */), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready), .io_in_valid (io_ser_2_in_valid), .io_in_bits_flit (io_ser_2_in_bits_flit), .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (/* unused */), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready), .io_in_valid (io_ser_3_in_valid), .io_in_bits_flit (io_ser_3_in_bits_flit), .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready), .io_in_valid (io_ser_4_in_valid), .io_in_bits_flit (io_ser_4_in_bits_flit), .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] assign auto_client_out_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] assign auto_client_out_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] assign auto_client_out_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_UInt_6 : input clock : Clock input reset : Reset output io : { flip x : UInt, y : UInt} connect io.y, io.x

module OptimizationBarrier_UInt_6( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [2:0] io_x, // @[package.scala:268:18] output [2:0] io_y // @[package.scala:268:18] ); wire [2:0] io_x_0 = io_x; // @[package.scala:267:30] wire [2:0] io_y_0 = io_x_0; // @[package.scala:267:30] assign io_y = io_y_0; // @[package.scala:267:30] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_91 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_104 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE

module AsyncValidSync_91( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_104 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_7 : input clock : Clock input reset : Reset output auto : { } skip

module TLFragmenter_7( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset // @[Fragmenter.scala:92:9] ); endmodule

Generate the Verilog code corresponding to this FIRRTL code module DTLB_6 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<2>, clock reg r_sectored_repl_addr : UInt<3>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_126 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_6 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_9 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2]) node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3]) node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn) node _sector_hits_T_4 = shr(_sector_hits_T_3, 2) node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0)) node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v) node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6) node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7) node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2]) node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3]) node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn) node _sector_hits_T_12 = shr(_sector_hits_T_11, 2) node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0)) node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v) node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14) node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15) node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2]) node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3]) node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn) node _sector_hits_T_20 = shr(_sector_hits_T_19, 2) node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0)) node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v) node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22) node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23) node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2]) node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3]) node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn) node _sector_hits_T_28 = shr(_sector_hits_T_27, 2) node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0)) node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v) node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30) node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31) node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2]) node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3]) node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn) node _sector_hits_T_36 = shr(_sector_hits_T_35, 2) node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0)) node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v) node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38) node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39) node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2]) node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3]) node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn) node _sector_hits_T_44 = shr(_sector_hits_T_43, 2) node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0)) node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v) node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46) node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47) node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2]) node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3]) node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn) node _sector_hits_T_52 = shr(_sector_hits_T_51, 2) node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0)) node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v) node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54) node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55) node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2]) node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3]) node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn) node _sector_hits_T_60 = shr(_sector_hits_T_59, 2) node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0)) node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v) node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62) node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1) node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0)) node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18) node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0)) node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16) node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17) node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0)) node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9) node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0)) node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21) node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22) node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1)) node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn) node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0) node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0)) node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26) node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27) node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2) node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0)) node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18) node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0)) node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30) node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31) node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0)) node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9) node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0)) node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35) node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36) node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1)) node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn) node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0) node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0)) node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40) node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41) node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3) node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0)) node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18) node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0)) node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44) node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45) node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0)) node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9) node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0)) node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49) node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50) node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1)) node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn) node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0) node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0)) node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54) node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55) node hitsVec_idx = bits(vpn, 1, 0) node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 2) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node hitsVec_idx_1 = bits(vpn, 1, 0) node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 2) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node hitsVec_idx_2 = bits(vpn, 1, 0) node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 2) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node hitsVec_idx_3 = bits(vpn, 1, 0) node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 2) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node hitsVec_idx_4 = bits(vpn, 1, 0) node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn) node _hitsVec_T_25 = shr(_hitsVec_T_24, 2) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v) node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27) node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28) node hitsVec_4 = and(vm_enabled, _hitsVec_T_29) node hitsVec_idx_5 = bits(vpn, 1, 0) node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn) node _hitsVec_T_31 = shr(_hitsVec_T_30, 2) node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0)) node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v) node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33) node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34) node hitsVec_5 = and(vm_enabled, _hitsVec_T_35) node hitsVec_idx_6 = bits(vpn, 1, 0) node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn) node _hitsVec_T_37 = shr(_hitsVec_T_36, 2) node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0)) node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v) node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39) node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40) node hitsVec_6 = and(vm_enabled, _hitsVec_T_41) node hitsVec_idx_7 = bits(vpn, 1, 0) node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn) node _hitsVec_T_43 = shr(_hitsVec_T_42, 2) node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0)) node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v) node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45) node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46) node hitsVec_7 = and(vm_enabled, _hitsVec_T_47) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18) node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0)) node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50) node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9) node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0)) node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55) node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0) node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0)) node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60) node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61) node hitsVec_8 = and(vm_enabled, _hitsVec_T_62) node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v) node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18) node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0)) node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65) node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66) node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9) node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0)) node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70) node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71) node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1)) node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn) node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0) node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0)) node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75) node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76) node hitsVec_9 = and(vm_enabled, _hitsVec_T_77) node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v) node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2) node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0)) node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18) node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0)) node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80) node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81) node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0)) node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9) node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0)) node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85) node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86) node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1)) node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn) node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0) node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0)) node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90) node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91) node hitsVec_10 = and(vm_enabled, _hitsVec_T_92) node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v) node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3) node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0)) node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18) node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0)) node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95) node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96) node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0)) node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9) node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0)) node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100) node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101) node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1)) node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn) node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0) node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0)) node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105) node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106) node hitsVec_11 = and(vm_enabled, _hitsVec_T_107) node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4) node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0)) node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18) node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0)) node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110) node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111) node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0)) node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9) node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0)) node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115) node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116) node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0)) node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0) node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0)) node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120) node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121) node hitsVec_12 = and(vm_enabled, _hitsVec_T_122) node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0) node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3) node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo) node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7) node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6) node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9) node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11) node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo) node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1)) when _T_4 : connect superpage_entries[1].tag_vpn, r_refill_tag connect superpage_entries[1].tag_v, refill_v node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[1].level, _superpage_entries_1_level_T connect superpage_entries[1].valid[0], UInt<1>(0h1) node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo) node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo) node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo) node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo) node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo) node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo) node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo) connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T when invalidate_refill : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2)) when _T_5 : connect superpage_entries[2].tag_vpn, r_refill_tag connect superpage_entries[2].tag_v, refill_v node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[2].level, _superpage_entries_2_level_T connect superpage_entries[2].valid[0], UInt<1>(0h1) node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo) node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo) node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo) node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo) node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo) node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo) node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo) connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T when invalidate_refill : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3)) when _T_6 : connect superpage_entries[3].tag_vpn, r_refill_tag connect superpage_entries[3].tag_v, refill_v node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[3].level, _superpage_entries_3_level_T connect superpage_entries[3].valid[0], UInt<1>(0h1) node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo) node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo) node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo) node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo) node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo) node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo) node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo) connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T when invalidate_refill : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_7 = eq(waddr_1, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_8 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][0].tag_vpn, r_refill_tag connect sectored_entries[0][0].tag_v, refill_v connect sectored_entries[0][0].level, UInt<2>(0h0) node idx = bits(r_refill_tag, 1, 0) connect sectored_entries[0][0].valid[idx], UInt<1>(0h1) node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo) node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo) node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo) node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo) node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo) node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo) node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo) connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T when invalidate_refill : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_9 = eq(waddr_1, UInt<1>(0h1)) when _T_9 : node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_10 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].tag_vpn, r_refill_tag connect sectored_entries[0][1].tag_v, refill_v connect sectored_entries[0][1].level, UInt<2>(0h0) node idx_1 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1) node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo) node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo) node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo) node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo) node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo) node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo) node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo) connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T when invalidate_refill : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_11 = eq(waddr_1, UInt<2>(0h2)) when _T_11 : node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_12 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].tag_vpn, r_refill_tag connect sectored_entries[0][2].tag_v, refill_v connect sectored_entries[0][2].level, UInt<2>(0h0) node idx_2 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1) node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo) node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo) node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo) node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo) node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo) node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo) node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo) connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T when invalidate_refill : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_13 = eq(waddr_1, UInt<2>(0h3)) when _T_13 : node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_14 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].tag_vpn, r_refill_tag connect sectored_entries[0][3].tag_v, refill_v connect sectored_entries[0][3].level, UInt<2>(0h0) node idx_3 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1) node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo) node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo) node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo) node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo) node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo) node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo) node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo) connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T when invalidate_refill : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_15 = eq(waddr_1, UInt<3>(0h4)) when _T_15 : node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_16 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].tag_vpn, r_refill_tag connect sectored_entries[0][4].tag_v, refill_v connect sectored_entries[0][4].level, UInt<2>(0h0) node idx_4 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1) node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo) node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo) node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo) node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo) node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo) node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo) node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo) connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T when invalidate_refill : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_17 = eq(waddr_1, UInt<3>(0h5)) when _T_17 : node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_18 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].tag_vpn, r_refill_tag connect sectored_entries[0][5].tag_v, refill_v connect sectored_entries[0][5].level, UInt<2>(0h0) node idx_5 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1) node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo) node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo) node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo) node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo) node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo) node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo) node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo) connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T when invalidate_refill : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_19 = eq(waddr_1, UInt<3>(0h6)) when _T_19 : node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_20 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].tag_vpn, r_refill_tag connect sectored_entries[0][6].tag_v, refill_v connect sectored_entries[0][6].level, UInt<2>(0h0) node idx_6 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1) node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo) node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo) node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo) node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo) node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo) node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo) node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo) connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T when invalidate_refill : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_21 = eq(waddr_1, UInt<3>(0h7)) when _T_21 : node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_22 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].tag_vpn, r_refill_tag connect sectored_entries[0][7].tag_v, refill_v connect sectored_entries[0][7].level, UInt<2>(0h0) node idx_7 = bits(r_refill_tag, 1, 0) connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1) node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo) node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo) node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo) node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo) node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo) node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo) node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo) connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T when invalidate_refill : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte node _entries_T = bits(vpn, 1, 0) wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T] node _entries_T_1 = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_22 node _entries_T_23 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_23 inst entries_barrier of OptimizationBarrier_TLBEntryData_127 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn node _entries_T_24 = bits(vpn, 1, 0) wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24] node _entries_T_25 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_45 node _entries_T_46 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_47 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_128 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn node _entries_T_48 = bits(vpn, 1, 0) wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48] node _entries_T_49 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_68 node _entries_T_69 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_71 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_129 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn node _entries_T_72 = bits(vpn, 1, 0) wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72] node _entries_T_73 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_91 node _entries_T_92 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_95 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_130 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn node _entries_T_96 = bits(vpn, 1, 0) wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96] node _entries_T_97 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_114 node _entries_T_115 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_119 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_131 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn node _entries_T_120 = bits(vpn, 1, 0) wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120] node _entries_T_121 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_137 node _entries_T_138 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_138 node _entries_T_139 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_139 node _entries_T_140 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_140 node _entries_T_141 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_141 node _entries_T_142 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_142 node _entries_T_143 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_143 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_132 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _entries_T_144 = bits(vpn, 1, 0) wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_13 : UInt<42> connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144] node _entries_T_145 = bits(_entries_WIRE_13, 0, 0) connect _entries_WIRE_12.fragmented_superpage, _entries_T_145 node _entries_T_146 = bits(_entries_WIRE_13, 1, 1) connect _entries_WIRE_12.c, _entries_T_146 node _entries_T_147 = bits(_entries_WIRE_13, 2, 2) connect _entries_WIRE_12.eff, _entries_T_147 node _entries_T_148 = bits(_entries_WIRE_13, 3, 3) connect _entries_WIRE_12.paa, _entries_T_148 node _entries_T_149 = bits(_entries_WIRE_13, 4, 4) connect _entries_WIRE_12.pal, _entries_T_149 node _entries_T_150 = bits(_entries_WIRE_13, 5, 5) connect _entries_WIRE_12.ppp, _entries_T_150 node _entries_T_151 = bits(_entries_WIRE_13, 6, 6) connect _entries_WIRE_12.pr, _entries_T_151 node _entries_T_152 = bits(_entries_WIRE_13, 7, 7) connect _entries_WIRE_12.px, _entries_T_152 node _entries_T_153 = bits(_entries_WIRE_13, 8, 8) connect _entries_WIRE_12.pw, _entries_T_153 node _entries_T_154 = bits(_entries_WIRE_13, 9, 9) connect _entries_WIRE_12.hr, _entries_T_154 node _entries_T_155 = bits(_entries_WIRE_13, 10, 10) connect _entries_WIRE_12.hx, _entries_T_155 node _entries_T_156 = bits(_entries_WIRE_13, 11, 11) connect _entries_WIRE_12.hw, _entries_T_156 node _entries_T_157 = bits(_entries_WIRE_13, 12, 12) connect _entries_WIRE_12.sr, _entries_T_157 node _entries_T_158 = bits(_entries_WIRE_13, 13, 13) connect _entries_WIRE_12.sx, _entries_T_158 node _entries_T_159 = bits(_entries_WIRE_13, 14, 14) connect _entries_WIRE_12.sw, _entries_T_159 node _entries_T_160 = bits(_entries_WIRE_13, 15, 15) connect _entries_WIRE_12.gf, _entries_T_160 node _entries_T_161 = bits(_entries_WIRE_13, 16, 16) connect _entries_WIRE_12.pf, _entries_T_161 node _entries_T_162 = bits(_entries_WIRE_13, 17, 17) connect _entries_WIRE_12.ae_stage2, _entries_T_162 node _entries_T_163 = bits(_entries_WIRE_13, 18, 18) connect _entries_WIRE_12.ae_final, _entries_T_163 node _entries_T_164 = bits(_entries_WIRE_13, 19, 19) connect _entries_WIRE_12.ae_ptw, _entries_T_164 node _entries_T_165 = bits(_entries_WIRE_13, 20, 20) connect _entries_WIRE_12.g, _entries_T_165 node _entries_T_166 = bits(_entries_WIRE_13, 21, 21) connect _entries_WIRE_12.u, _entries_T_166 node _entries_T_167 = bits(_entries_WIRE_13, 41, 22) connect _entries_WIRE_12.ppn, _entries_T_167 inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_133 connect entries_barrier_6.clock, clock connect entries_barrier_6.reset, reset connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage connect entries_barrier_6.io.x.c, _entries_WIRE_12.c connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr connect entries_barrier_6.io.x.px, _entries_WIRE_12.px connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2 connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw connect entries_barrier_6.io.x.g, _entries_WIRE_12.g connect entries_barrier_6.io.x.u, _entries_WIRE_12.u connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn node _entries_T_168 = bits(vpn, 1, 0) wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_15 : UInt<42> connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168] node _entries_T_169 = bits(_entries_WIRE_15, 0, 0) connect _entries_WIRE_14.fragmented_superpage, _entries_T_169 node _entries_T_170 = bits(_entries_WIRE_15, 1, 1) connect _entries_WIRE_14.c, _entries_T_170 node _entries_T_171 = bits(_entries_WIRE_15, 2, 2) connect _entries_WIRE_14.eff, _entries_T_171 node _entries_T_172 = bits(_entries_WIRE_15, 3, 3) connect _entries_WIRE_14.paa, _entries_T_172 node _entries_T_173 = bits(_entries_WIRE_15, 4, 4) connect _entries_WIRE_14.pal, _entries_T_173 node _entries_T_174 = bits(_entries_WIRE_15, 5, 5) connect _entries_WIRE_14.ppp, _entries_T_174 node _entries_T_175 = bits(_entries_WIRE_15, 6, 6) connect _entries_WIRE_14.pr, _entries_T_175 node _entries_T_176 = bits(_entries_WIRE_15, 7, 7) connect _entries_WIRE_14.px, _entries_T_176 node _entries_T_177 = bits(_entries_WIRE_15, 8, 8) connect _entries_WIRE_14.pw, _entries_T_177 node _entries_T_178 = bits(_entries_WIRE_15, 9, 9) connect _entries_WIRE_14.hr, _entries_T_178 node _entries_T_179 = bits(_entries_WIRE_15, 10, 10) connect _entries_WIRE_14.hx, _entries_T_179 node _entries_T_180 = bits(_entries_WIRE_15, 11, 11) connect _entries_WIRE_14.hw, _entries_T_180 node _entries_T_181 = bits(_entries_WIRE_15, 12, 12) connect _entries_WIRE_14.sr, _entries_T_181 node _entries_T_182 = bits(_entries_WIRE_15, 13, 13) connect _entries_WIRE_14.sx, _entries_T_182 node _entries_T_183 = bits(_entries_WIRE_15, 14, 14) connect _entries_WIRE_14.sw, _entries_T_183 node _entries_T_184 = bits(_entries_WIRE_15, 15, 15) connect _entries_WIRE_14.gf, _entries_T_184 node _entries_T_185 = bits(_entries_WIRE_15, 16, 16) connect _entries_WIRE_14.pf, _entries_T_185 node _entries_T_186 = bits(_entries_WIRE_15, 17, 17) connect _entries_WIRE_14.ae_stage2, _entries_T_186 node _entries_T_187 = bits(_entries_WIRE_15, 18, 18) connect _entries_WIRE_14.ae_final, _entries_T_187 node _entries_T_188 = bits(_entries_WIRE_15, 19, 19) connect _entries_WIRE_14.ae_ptw, _entries_T_188 node _entries_T_189 = bits(_entries_WIRE_15, 20, 20) connect _entries_WIRE_14.g, _entries_T_189 node _entries_T_190 = bits(_entries_WIRE_15, 21, 21) connect _entries_WIRE_14.u, _entries_T_190 node _entries_T_191 = bits(_entries_WIRE_15, 41, 22) connect _entries_WIRE_14.ppn, _entries_T_191 inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_134 connect entries_barrier_7.clock, clock connect entries_barrier_7.reset, reset connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage connect entries_barrier_7.io.x.c, _entries_WIRE_14.c connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr connect entries_barrier_7.io.x.px, _entries_WIRE_14.px connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2 connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw connect entries_barrier_7.io.x.g, _entries_WIRE_14.g connect entries_barrier_7.io.x.u, _entries_WIRE_14.u connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_17 : UInt<42> connect _entries_WIRE_17, superpage_entries[0].data[0] node _entries_T_192 = bits(_entries_WIRE_17, 0, 0) connect _entries_WIRE_16.fragmented_superpage, _entries_T_192 node _entries_T_193 = bits(_entries_WIRE_17, 1, 1) connect _entries_WIRE_16.c, _entries_T_193 node _entries_T_194 = bits(_entries_WIRE_17, 2, 2) connect _entries_WIRE_16.eff, _entries_T_194 node _entries_T_195 = bits(_entries_WIRE_17, 3, 3) connect _entries_WIRE_16.paa, _entries_T_195 node _entries_T_196 = bits(_entries_WIRE_17, 4, 4) connect _entries_WIRE_16.pal, _entries_T_196 node _entries_T_197 = bits(_entries_WIRE_17, 5, 5) connect _entries_WIRE_16.ppp, _entries_T_197 node _entries_T_198 = bits(_entries_WIRE_17, 6, 6) connect _entries_WIRE_16.pr, _entries_T_198 node _entries_T_199 = bits(_entries_WIRE_17, 7, 7) connect _entries_WIRE_16.px, _entries_T_199 node _entries_T_200 = bits(_entries_WIRE_17, 8, 8) connect _entries_WIRE_16.pw, _entries_T_200 node _entries_T_201 = bits(_entries_WIRE_17, 9, 9) connect _entries_WIRE_16.hr, _entries_T_201 node _entries_T_202 = bits(_entries_WIRE_17, 10, 10) connect _entries_WIRE_16.hx, _entries_T_202 node _entries_T_203 = bits(_entries_WIRE_17, 11, 11) connect _entries_WIRE_16.hw, _entries_T_203 node _entries_T_204 = bits(_entries_WIRE_17, 12, 12) connect _entries_WIRE_16.sr, _entries_T_204 node _entries_T_205 = bits(_entries_WIRE_17, 13, 13) connect _entries_WIRE_16.sx, _entries_T_205 node _entries_T_206 = bits(_entries_WIRE_17, 14, 14) connect _entries_WIRE_16.sw, _entries_T_206 node _entries_T_207 = bits(_entries_WIRE_17, 15, 15) connect _entries_WIRE_16.gf, _entries_T_207 node _entries_T_208 = bits(_entries_WIRE_17, 16, 16) connect _entries_WIRE_16.pf, _entries_T_208 node _entries_T_209 = bits(_entries_WIRE_17, 17, 17) connect _entries_WIRE_16.ae_stage2, _entries_T_209 node _entries_T_210 = bits(_entries_WIRE_17, 18, 18) connect _entries_WIRE_16.ae_final, _entries_T_210 node _entries_T_211 = bits(_entries_WIRE_17, 19, 19) connect _entries_WIRE_16.ae_ptw, _entries_T_211 node _entries_T_212 = bits(_entries_WIRE_17, 20, 20) connect _entries_WIRE_16.g, _entries_T_212 node _entries_T_213 = bits(_entries_WIRE_17, 21, 21) connect _entries_WIRE_16.u, _entries_T_213 node _entries_T_214 = bits(_entries_WIRE_17, 41, 22) connect _entries_WIRE_16.ppn, _entries_T_214 inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_135 connect entries_barrier_8.clock, clock connect entries_barrier_8.reset, reset connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage connect entries_barrier_8.io.x.c, _entries_WIRE_16.c connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr connect entries_barrier_8.io.x.px, _entries_WIRE_16.px connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2 connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw connect entries_barrier_8.io.x.g, _entries_WIRE_16.g connect entries_barrier_8.io.x.u, _entries_WIRE_16.u connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_19 : UInt<42> connect _entries_WIRE_19, superpage_entries[1].data[0] node _entries_T_215 = bits(_entries_WIRE_19, 0, 0) connect _entries_WIRE_18.fragmented_superpage, _entries_T_215 node _entries_T_216 = bits(_entries_WIRE_19, 1, 1) connect _entries_WIRE_18.c, _entries_T_216 node _entries_T_217 = bits(_entries_WIRE_19, 2, 2) connect _entries_WIRE_18.eff, _entries_T_217 node _entries_T_218 = bits(_entries_WIRE_19, 3, 3) connect _entries_WIRE_18.paa, _entries_T_218 node _entries_T_219 = bits(_entries_WIRE_19, 4, 4) connect _entries_WIRE_18.pal, _entries_T_219 node _entries_T_220 = bits(_entries_WIRE_19, 5, 5) connect _entries_WIRE_18.ppp, _entries_T_220 node _entries_T_221 = bits(_entries_WIRE_19, 6, 6) connect _entries_WIRE_18.pr, _entries_T_221 node _entries_T_222 = bits(_entries_WIRE_19, 7, 7) connect _entries_WIRE_18.px, _entries_T_222 node _entries_T_223 = bits(_entries_WIRE_19, 8, 8) connect _entries_WIRE_18.pw, _entries_T_223 node _entries_T_224 = bits(_entries_WIRE_19, 9, 9) connect _entries_WIRE_18.hr, _entries_T_224 node _entries_T_225 = bits(_entries_WIRE_19, 10, 10) connect _entries_WIRE_18.hx, _entries_T_225 node _entries_T_226 = bits(_entries_WIRE_19, 11, 11) connect _entries_WIRE_18.hw, _entries_T_226 node _entries_T_227 = bits(_entries_WIRE_19, 12, 12) connect _entries_WIRE_18.sr, _entries_T_227 node _entries_T_228 = bits(_entries_WIRE_19, 13, 13) connect _entries_WIRE_18.sx, _entries_T_228 node _entries_T_229 = bits(_entries_WIRE_19, 14, 14) connect _entries_WIRE_18.sw, _entries_T_229 node _entries_T_230 = bits(_entries_WIRE_19, 15, 15) connect _entries_WIRE_18.gf, _entries_T_230 node _entries_T_231 = bits(_entries_WIRE_19, 16, 16) connect _entries_WIRE_18.pf, _entries_T_231 node _entries_T_232 = bits(_entries_WIRE_19, 17, 17) connect _entries_WIRE_18.ae_stage2, _entries_T_232 node _entries_T_233 = bits(_entries_WIRE_19, 18, 18) connect _entries_WIRE_18.ae_final, _entries_T_233 node _entries_T_234 = bits(_entries_WIRE_19, 19, 19) connect _entries_WIRE_18.ae_ptw, _entries_T_234 node _entries_T_235 = bits(_entries_WIRE_19, 20, 20) connect _entries_WIRE_18.g, _entries_T_235 node _entries_T_236 = bits(_entries_WIRE_19, 21, 21) connect _entries_WIRE_18.u, _entries_T_236 node _entries_T_237 = bits(_entries_WIRE_19, 41, 22) connect _entries_WIRE_18.ppn, _entries_T_237 inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_136 connect entries_barrier_9.clock, clock connect entries_barrier_9.reset, reset connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage connect entries_barrier_9.io.x.c, _entries_WIRE_18.c connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr connect entries_barrier_9.io.x.px, _entries_WIRE_18.px connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2 connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw connect entries_barrier_9.io.x.g, _entries_WIRE_18.g connect entries_barrier_9.io.x.u, _entries_WIRE_18.u connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_21 : UInt<42> connect _entries_WIRE_21, superpage_entries[2].data[0] node _entries_T_238 = bits(_entries_WIRE_21, 0, 0) connect _entries_WIRE_20.fragmented_superpage, _entries_T_238 node _entries_T_239 = bits(_entries_WIRE_21, 1, 1) connect _entries_WIRE_20.c, _entries_T_239 node _entries_T_240 = bits(_entries_WIRE_21, 2, 2) connect _entries_WIRE_20.eff, _entries_T_240 node _entries_T_241 = bits(_entries_WIRE_21, 3, 3) connect _entries_WIRE_20.paa, _entries_T_241 node _entries_T_242 = bits(_entries_WIRE_21, 4, 4) connect _entries_WIRE_20.pal, _entries_T_242 node _entries_T_243 = bits(_entries_WIRE_21, 5, 5) connect _entries_WIRE_20.ppp, _entries_T_243 node _entries_T_244 = bits(_entries_WIRE_21, 6, 6) connect _entries_WIRE_20.pr, _entries_T_244 node _entries_T_245 = bits(_entries_WIRE_21, 7, 7) connect _entries_WIRE_20.px, _entries_T_245 node _entries_T_246 = bits(_entries_WIRE_21, 8, 8) connect _entries_WIRE_20.pw, _entries_T_246 node _entries_T_247 = bits(_entries_WIRE_21, 9, 9) connect _entries_WIRE_20.hr, _entries_T_247 node _entries_T_248 = bits(_entries_WIRE_21, 10, 10) connect _entries_WIRE_20.hx, _entries_T_248 node _entries_T_249 = bits(_entries_WIRE_21, 11, 11) connect _entries_WIRE_20.hw, _entries_T_249 node _entries_T_250 = bits(_entries_WIRE_21, 12, 12) connect _entries_WIRE_20.sr, _entries_T_250 node _entries_T_251 = bits(_entries_WIRE_21, 13, 13) connect _entries_WIRE_20.sx, _entries_T_251 node _entries_T_252 = bits(_entries_WIRE_21, 14, 14) connect _entries_WIRE_20.sw, _entries_T_252 node _entries_T_253 = bits(_entries_WIRE_21, 15, 15) connect _entries_WIRE_20.gf, _entries_T_253 node _entries_T_254 = bits(_entries_WIRE_21, 16, 16) connect _entries_WIRE_20.pf, _entries_T_254 node _entries_T_255 = bits(_entries_WIRE_21, 17, 17) connect _entries_WIRE_20.ae_stage2, _entries_T_255 node _entries_T_256 = bits(_entries_WIRE_21, 18, 18) connect _entries_WIRE_20.ae_final, _entries_T_256 node _entries_T_257 = bits(_entries_WIRE_21, 19, 19) connect _entries_WIRE_20.ae_ptw, _entries_T_257 node _entries_T_258 = bits(_entries_WIRE_21, 20, 20) connect _entries_WIRE_20.g, _entries_T_258 node _entries_T_259 = bits(_entries_WIRE_21, 21, 21) connect _entries_WIRE_20.u, _entries_T_259 node _entries_T_260 = bits(_entries_WIRE_21, 41, 22) connect _entries_WIRE_20.ppn, _entries_T_260 inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_137 connect entries_barrier_10.clock, clock connect entries_barrier_10.reset, reset connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage connect entries_barrier_10.io.x.c, _entries_WIRE_20.c connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr connect entries_barrier_10.io.x.px, _entries_WIRE_20.px connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2 connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw connect entries_barrier_10.io.x.g, _entries_WIRE_20.g connect entries_barrier_10.io.x.u, _entries_WIRE_20.u connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_23 : UInt<42> connect _entries_WIRE_23, superpage_entries[3].data[0] node _entries_T_261 = bits(_entries_WIRE_23, 0, 0) connect _entries_WIRE_22.fragmented_superpage, _entries_T_261 node _entries_T_262 = bits(_entries_WIRE_23, 1, 1) connect _entries_WIRE_22.c, _entries_T_262 node _entries_T_263 = bits(_entries_WIRE_23, 2, 2) connect _entries_WIRE_22.eff, _entries_T_263 node _entries_T_264 = bits(_entries_WIRE_23, 3, 3) connect _entries_WIRE_22.paa, _entries_T_264 node _entries_T_265 = bits(_entries_WIRE_23, 4, 4) connect _entries_WIRE_22.pal, _entries_T_265 node _entries_T_266 = bits(_entries_WIRE_23, 5, 5) connect _entries_WIRE_22.ppp, _entries_T_266 node _entries_T_267 = bits(_entries_WIRE_23, 6, 6) connect _entries_WIRE_22.pr, _entries_T_267 node _entries_T_268 = bits(_entries_WIRE_23, 7, 7) connect _entries_WIRE_22.px, _entries_T_268 node _entries_T_269 = bits(_entries_WIRE_23, 8, 8) connect _entries_WIRE_22.pw, _entries_T_269 node _entries_T_270 = bits(_entries_WIRE_23, 9, 9) connect _entries_WIRE_22.hr, _entries_T_270 node _entries_T_271 = bits(_entries_WIRE_23, 10, 10) connect _entries_WIRE_22.hx, _entries_T_271 node _entries_T_272 = bits(_entries_WIRE_23, 11, 11) connect _entries_WIRE_22.hw, _entries_T_272 node _entries_T_273 = bits(_entries_WIRE_23, 12, 12) connect _entries_WIRE_22.sr, _entries_T_273 node _entries_T_274 = bits(_entries_WIRE_23, 13, 13) connect _entries_WIRE_22.sx, _entries_T_274 node _entries_T_275 = bits(_entries_WIRE_23, 14, 14) connect _entries_WIRE_22.sw, _entries_T_275 node _entries_T_276 = bits(_entries_WIRE_23, 15, 15) connect _entries_WIRE_22.gf, _entries_T_276 node _entries_T_277 = bits(_entries_WIRE_23, 16, 16) connect _entries_WIRE_22.pf, _entries_T_277 node _entries_T_278 = bits(_entries_WIRE_23, 17, 17) connect _entries_WIRE_22.ae_stage2, _entries_T_278 node _entries_T_279 = bits(_entries_WIRE_23, 18, 18) connect _entries_WIRE_22.ae_final, _entries_T_279 node _entries_T_280 = bits(_entries_WIRE_23, 19, 19) connect _entries_WIRE_22.ae_ptw, _entries_T_280 node _entries_T_281 = bits(_entries_WIRE_23, 20, 20) connect _entries_WIRE_22.g, _entries_T_281 node _entries_T_282 = bits(_entries_WIRE_23, 21, 21) connect _entries_WIRE_22.u, _entries_T_282 node _entries_T_283 = bits(_entries_WIRE_23, 41, 22) connect _entries_WIRE_22.ppn, _entries_T_283 inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_138 connect entries_barrier_11.clock, clock connect entries_barrier_11.reset, reset connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage connect entries_barrier_11.io.x.c, _entries_WIRE_22.c connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr connect entries_barrier_11.io.x.px, _entries_WIRE_22.px connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2 connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw connect entries_barrier_11.io.x.g, _entries_WIRE_22.g connect entries_barrier_11.io.x.u, _entries_WIRE_22.u connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_25 : UInt<42> connect _entries_WIRE_25, special_entry.data[0] node _entries_T_284 = bits(_entries_WIRE_25, 0, 0) connect _entries_WIRE_24.fragmented_superpage, _entries_T_284 node _entries_T_285 = bits(_entries_WIRE_25, 1, 1) connect _entries_WIRE_24.c, _entries_T_285 node _entries_T_286 = bits(_entries_WIRE_25, 2, 2) connect _entries_WIRE_24.eff, _entries_T_286 node _entries_T_287 = bits(_entries_WIRE_25, 3, 3) connect _entries_WIRE_24.paa, _entries_T_287 node _entries_T_288 = bits(_entries_WIRE_25, 4, 4) connect _entries_WIRE_24.pal, _entries_T_288 node _entries_T_289 = bits(_entries_WIRE_25, 5, 5) connect _entries_WIRE_24.ppp, _entries_T_289 node _entries_T_290 = bits(_entries_WIRE_25, 6, 6) connect _entries_WIRE_24.pr, _entries_T_290 node _entries_T_291 = bits(_entries_WIRE_25, 7, 7) connect _entries_WIRE_24.px, _entries_T_291 node _entries_T_292 = bits(_entries_WIRE_25, 8, 8) connect _entries_WIRE_24.pw, _entries_T_292 node _entries_T_293 = bits(_entries_WIRE_25, 9, 9) connect _entries_WIRE_24.hr, _entries_T_293 node _entries_T_294 = bits(_entries_WIRE_25, 10, 10) connect _entries_WIRE_24.hx, _entries_T_294 node _entries_T_295 = bits(_entries_WIRE_25, 11, 11) connect _entries_WIRE_24.hw, _entries_T_295 node _entries_T_296 = bits(_entries_WIRE_25, 12, 12) connect _entries_WIRE_24.sr, _entries_T_296 node _entries_T_297 = bits(_entries_WIRE_25, 13, 13) connect _entries_WIRE_24.sx, _entries_T_297 node _entries_T_298 = bits(_entries_WIRE_25, 14, 14) connect _entries_WIRE_24.sw, _entries_T_298 node _entries_T_299 = bits(_entries_WIRE_25, 15, 15) connect _entries_WIRE_24.gf, _entries_T_299 node _entries_T_300 = bits(_entries_WIRE_25, 16, 16) connect _entries_WIRE_24.pf, _entries_T_300 node _entries_T_301 = bits(_entries_WIRE_25, 17, 17) connect _entries_WIRE_24.ae_stage2, _entries_T_301 node _entries_T_302 = bits(_entries_WIRE_25, 18, 18) connect _entries_WIRE_24.ae_final, _entries_T_302 node _entries_T_303 = bits(_entries_WIRE_25, 19, 19) connect _entries_WIRE_24.ae_ptw, _entries_T_303 node _entries_T_304 = bits(_entries_WIRE_25, 20, 20) connect _entries_WIRE_24.g, _entries_T_304 node _entries_T_305 = bits(_entries_WIRE_25, 21, 21) connect _entries_WIRE_24.u, _entries_T_305 node _entries_T_306 = bits(_entries_WIRE_25, 41, 22) connect _entries_WIRE_24.ppn, _entries_T_306 inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_139 connect entries_barrier_12.clock, clock connect entries_barrier_12.reset, reset connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage connect entries_barrier_12.io.x.c, _entries_WIRE_24.c connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr connect entries_barrier_12.io.x.px, _entries_WIRE_24.px connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2 connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw connect entries_barrier_12.io.x.g, _entries_WIRE_24.g connect entries_barrier_12.io.x.u, _entries_WIRE_24.u connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_8.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18) node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0)) node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0)) node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn) node _ppn_T_19 = bits(_ppn_T_18, 17, 9) node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19) node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1)) node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0)) node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn) node _ppn_T_23 = bits(_ppn_T_22, 8, 0) node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23) node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18) node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0)) node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0)) node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn) node _ppn_T_27 = bits(_ppn_T_26, 17, 9) node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27) node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1)) node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0)) node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn) node _ppn_T_31 = bits(_ppn_T_30, 8, 0) node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31) node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18) node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0)) node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0)) node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn) node _ppn_T_35 = bits(_ppn_T_34, 17, 9) node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35) node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0)) node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0)) node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn) node _ppn_T_39 = bits(_ppn_T_38, 8, 0) node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39) node _ppn_T_41 = bits(vpn, 19, 0) node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0)) node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0)) node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0)) node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0)) node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0)) node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0)) node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0)) node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0)) node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43) node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44) node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45) node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46) node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47) node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48) node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49) node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50) node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51) node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52) node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53) node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54) node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55) wire ppn : UInt<20> connect ppn, _ppn_T_68 node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo) node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw) node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw) node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw) node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo) node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final) node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final) node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final) node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final) node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo) node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo) node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf) node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf) node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf) node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf) node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo) node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf) node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf) node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf) node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf) node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo) node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1) node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo) node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1) node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u) node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u) node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u) node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u) node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0)) node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo) node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2) node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2) node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2) node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr) node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr) node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo) node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr) node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr) node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr) node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr) node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo) node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx) node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1) node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx) node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1) node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw) node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw) node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo) node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw) node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw) node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw) node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw) node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo) node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx) node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx) node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo) node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx) node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx) node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx) node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx) node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo) node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0)) node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr) node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo) node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr) node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr) node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr) node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr) node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo) node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx) node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1) node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx) node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1) node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw) node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo) node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw) node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw) node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw) node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw) node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo) node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx) node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo) node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx) node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx) node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx) node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx) node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo) node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr) node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr) node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr) node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr) node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo) node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr) node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr) node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr) node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw) node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw) node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw) node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw) node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo) node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw) node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw) node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw) node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px) node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px) node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px) node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px) node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo) node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px) node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px) node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px) node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px) node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff) node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff) node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff) node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff) node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo) node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff) node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff) node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff) node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c) node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c) node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo) node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c) node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c) node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp) node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp) node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp) node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp) node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo) node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp) node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp) node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp) node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa) node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa) node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa) node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa) node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo) node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa) node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa) node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa) node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal) node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal) node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal) node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal) node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo) node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal) node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal) node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal) node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c) node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c) node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c) node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c) node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo) node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c) node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c) node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c) node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<14>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 12, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) wire _state_vec_WIRE : UInt<7>[1] connect _state_vec_WIRE[0], UInt<7>(0h0) regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _T_23 = and(io.req.valid, vm_enabled) when _T_23 : node _T_24 = or(sector_hits_0, sector_hits_1) node _T_25 = or(_T_24, sector_hits_2) node _T_26 = or(_T_25, sector_hits_3) node _T_27 = or(_T_26, sector_hits_4) node _T_28 = or(_T_27, sector_hits_5) node _T_29 = or(_T_28, sector_hits_6) node _T_30 = or(_T_29, sector_hits_7) when _T_30 : node lo_lo = cat(sector_hits_1, sector_hits_0) node lo_hi = cat(sector_hits_3, sector_hits_2) node lo = cat(lo_hi, lo_lo) node hi_lo = cat(sector_hits_5, sector_hits_4) node hi_hi = cat(sector_hits_7, sector_hits_6) node hi = cat(hi_hi, hi_lo) node _T_31 = cat(hi, lo) node hi_1 = bits(_T_31, 7, 4) node lo_1 = bits(_T_31, 3, 0) node _T_32 = orr(hi_1) node _T_33 = or(hi_1, lo_1) node hi_2 = bits(_T_33, 3, 2) node lo_2 = bits(_T_33, 1, 0) node _T_34 = orr(hi_2) node _T_35 = or(hi_2, lo_2) node _T_36 = bits(_T_35, 1, 1) node _T_37 = cat(_T_34, _T_36) node _T_38 = cat(_T_32, _T_37) node state_vec_0_touch_way_sized = bits(_T_38, 2, 0) node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2) node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0)) node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3) node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0) node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1) node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0)) node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1) node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0) node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0) node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0)) node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3) node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0) node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0) node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0)) node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1) node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4) node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8) node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9) node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0) node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1) node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0)) node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1) node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0) node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0) node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0)) node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14) node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0) node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0) node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0)) node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2) node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15) node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19) node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state) node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10) node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21) connect state_vec[0], _state_vec_0_T_22 node _T_39 = or(superpage_hits_0, superpage_hits_1) node _T_40 = or(_T_39, superpage_hits_2) node _T_41 = or(_T_40, superpage_hits_3) when _T_41 : node lo_3 = cat(superpage_hits_1, superpage_hits_0) node hi_3 = cat(superpage_hits_3, superpage_hits_2) node _T_42 = cat(hi_3, lo_3) node hi_4 = bits(_T_42, 3, 2) node lo_4 = bits(_T_42, 1, 0) node _T_43 = orr(hi_4) node _T_44 = or(hi_4, lo_4) node _T_45 = bits(_T_44, 1, 1) node _T_46 = cat(_T_43, _T_45) node state_reg_touch_way_sized = bits(_T_46, 1, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg_1, 1, 1) node state_reg_right_subtree_state = bits(state_reg_1, 0, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0)) node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2) node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0) node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0) node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0)) node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state) node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3) node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7) connect state_reg_1, _state_reg_T_8 node _multipleHits_T = bits(real_hits, 5, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0) node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0) node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1) node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0) node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9) node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3) node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0) node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1) node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0) node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18) node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20) node _multipleHits_T_21 = bits(real_hits, 12, 6) node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0) node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0) node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0) node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1) node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0) node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0) node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1) node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0) node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5) node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5) node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28) node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6) node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3) node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6) node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30) node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3) node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0) node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0) node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0) node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1) node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0) node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7) node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7) node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36) node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2) node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0) node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0) node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1) node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0) node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8) node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8) node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41) node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9) node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4) node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9) node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43) node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10) node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5) node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10) node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45) node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11) node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6) node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11) node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_48 = and(_T_47, io.ptw.req.bits.valid) when _T_48 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_49 = and(io.req.ready, io.req.valid) node _T_50 = and(_T_49, tlb_miss) when _T_50 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2) node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1) node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0) node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0) node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0) node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1) node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2) node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0]) node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0]) node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo) node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids) node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0) node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1) node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2) node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3) node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10) node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11) node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0) node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2) node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1) node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0) node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5) node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6) node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7) node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8) node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1]) node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2]) node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3]) node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1]) node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2]) node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3]) node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1]) node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2]) node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3]) node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1]) node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2]) node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3]) node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1]) node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2]) node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3]) node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1]) node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2]) node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3]) node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1]) node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2]) node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3]) node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1]) node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2]) node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3]) node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2) node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8) node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo) node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14) node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20) node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0) node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1) node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2) node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3) node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4) node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5) node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6) node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7) node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20) node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21) node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22) node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23) node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24) node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25) node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4) node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5) node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6) node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6 node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2) node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo) node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4) node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6) node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2) node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0) node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2) node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2) node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1) node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5) node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7 node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1) node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2) node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3) connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2 node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0) node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2) node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo) node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2) node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0) node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1) node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1) node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1) node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3) connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4 node _T_51 = eq(state, UInt<2>(0h1)) when _T_51 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_52 = eq(state, UInt<2>(0h2)) node _T_53 = and(_T_52, io.sfence.valid) when _T_53 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_55 = shr(io.sfence.bits.addr, 12) node _T_56 = eq(_T_55, vpn) node _T_57 = or(_T_54, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_57, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_61 = eq(hg, UInt<1>(0h0)) node _T_62 = and(_T_61, io.sfence.bits.rs1) when _T_62 : node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_64 = shr(_T_63, 2) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = eq(sectored_entries[0][0].tag_v, hv) node _T_67 = and(_T_65, _T_66) when _T_67 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_68 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_68 node _T_69 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_69 node _T_70 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_70 node _T_71 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_71 node _T_72 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_72 node _T_73 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_73 node _T_74 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_74 node _T_75 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_75 node _T_76 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_76 node _T_77 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_77 node _T_78 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_78 node _T_79 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_79 node _T_80 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_80 node _T_81 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_81 node _T_82 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_82 node _T_83 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_83 node _T_84 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_84 node _T_85 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_85 node _T_86 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_86 node _T_87 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_87 node _T_88 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_88 node _T_89 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_89 node _T_90 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_90 wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[1] node _T_91 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_91 node _T_92 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_92 node _T_93 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_93 node _T_94 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_94 node _T_95 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_95 node _T_96 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_96 node _T_97 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_97 node _T_98 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_98 node _T_99 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_99 node _T_100 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_100 node _T_101 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_101 node _T_102 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_102 node _T_103 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_103 node _T_104 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_104 node _T_105 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_105 node _T_106 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_106 node _T_107 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_107 node _T_108 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_108 node _T_109 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_109 node _T_110 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_110 node _T_111 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_111 node _T_112 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_112 node _T_113 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_113 wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[2] node _T_114 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_114 node _T_115 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_115 node _T_116 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_116 node _T_117 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_117 node _T_118 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_118 node _T_119 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_119 node _T_120 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_120 node _T_121 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_121 node _T_122 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_122 node _T_123 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_123 node _T_124 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_124 node _T_125 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_125 node _T_126 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_126 node _T_127 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_127 node _T_128 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_128 node _T_129 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_129 node _T_130 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_130 node _T_131 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_131 node _T_132 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_132 node _T_133 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_133 node _T_134 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_134 node _T_135 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_135 node _T_136 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_136 wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[3] node _T_137 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_137 node _T_138 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_138 node _T_139 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_139 node _T_140 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_140 node _T_141 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_141 node _T_142 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_142 node _T_143 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_143 node _T_144 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_144 node _T_145 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_145 node _T_146 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_146 node _T_147 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_147 node _T_148 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_148 node _T_149 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_149 node _T_150 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_150 node _T_151 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_151 node _T_152 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_152 node _T_153 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_153 node _T_154 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_154 node _T_155 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_155 node _T_156 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_156 node _T_157 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_157 node _T_158 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_158 node _T_159 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_159 node _T_160 = eq(sectored_entries[0][0].tag_v, hv) node _T_161 = bits(vpn, 1, 0) node _T_162 = eq(UInt<1>(0h0), _T_161) node _T_163 = and(_T_160, _T_162) when _T_163 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_164 = eq(sectored_entries[0][0].tag_v, hv) node _T_165 = bits(vpn, 1, 0) node _T_166 = eq(UInt<1>(0h1), _T_165) node _T_167 = and(_T_164, _T_166) when _T_167 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_168 = eq(sectored_entries[0][0].tag_v, hv) node _T_169 = bits(vpn, 1, 0) node _T_170 = eq(UInt<2>(0h2), _T_169) node _T_171 = and(_T_168, _T_170) when _T_171 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_172 = eq(sectored_entries[0][0].tag_v, hv) node _T_173 = bits(vpn, 1, 0) node _T_174 = eq(UInt<2>(0h3), _T_173) node _T_175 = and(_T_172, _T_174) when _T_175 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_177 = shr(_T_176, 18) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][0].data[0] node _T_179 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_179 node _T_180 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_180 node _T_181 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_181 node _T_182 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_182 node _T_183 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_183 node _T_184 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_184 node _T_185 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_185 node _T_186 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_186 node _T_187 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_187 node _T_188 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_188 node _T_189 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_189 node _T_190 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_190 node _T_191 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_191 node _T_192 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_192 node _T_193 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_193 node _T_194 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_194 node _T_195 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_195 node _T_196 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_196 node _T_197 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_197 node _T_198 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_198 node _T_199 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_199 node _T_200 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_200 node _T_201 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_201 wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][0].data[1] node _T_202 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_202 node _T_203 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_203 node _T_204 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_204 node _T_205 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_205 node _T_206 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_206 node _T_207 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_207 node _T_208 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_208 node _T_209 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_209 node _T_210 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_210 node _T_211 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_211 node _T_212 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_212 node _T_213 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_213 node _T_214 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_214 node _T_215 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_215 node _T_216 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_216 node _T_217 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_217 node _T_218 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_218 node _T_219 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_219 node _T_220 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_220 node _T_221 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_221 node _T_222 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_222 node _T_223 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_223 node _T_224 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_224 wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][0].data[2] node _T_225 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_225 node _T_226 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_226 node _T_227 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_227 node _T_228 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_228 node _T_229 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_229 node _T_230 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_230 node _T_231 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_231 node _T_232 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_232 node _T_233 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_233 node _T_234 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_234 node _T_235 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_235 node _T_236 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_236 node _T_237 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_237 node _T_238 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_238 node _T_239 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_239 node _T_240 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_240 node _T_241 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_241 node _T_242 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_242 node _T_243 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_243 node _T_244 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_244 node _T_245 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_245 node _T_246 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_246 node _T_247 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_247 wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][0].data[3] node _T_248 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_248 node _T_249 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_249 node _T_250 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_250 node _T_251 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_251 node _T_252 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_252 node _T_253 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_253 node _T_254 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_254 node _T_255 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_255 node _T_256 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_256 node _T_257 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_257 node _T_258 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_258 node _T_259 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_259 node _T_260 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_260 node _T_261 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_261 node _T_262 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_262 node _T_263 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_263 node _T_264 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_264 node _T_265 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_265 node _T_266 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_266 node _T_267 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_267 node _T_268 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_268 node _T_269 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_269 node _T_270 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_270 node _T_271 = eq(sectored_entries[0][0].tag_v, hv) node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage) when _T_272 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_273 = eq(sectored_entries[0][0].tag_v, hv) node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage) when _T_274 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_275 = eq(sectored_entries[0][0].tag_v, hv) node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage) when _T_276 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_277 = eq(sectored_entries[0][0].tag_v, hv) node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage) when _T_278 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_279 = eq(hg, UInt<1>(0h0)) node _T_280 = and(_T_279, io.sfence.bits.rs2) when _T_280 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][0].data[0] node _T_281 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_281 node _T_282 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_282 node _T_283 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_283 node _T_284 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_284 node _T_285 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_285 node _T_286 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_286 node _T_287 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_287 node _T_288 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_288 node _T_289 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_289 node _T_290 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_290 node _T_291 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_291 node _T_292 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_292 node _T_293 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_293 node _T_294 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_294 node _T_295 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_295 node _T_296 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_296 node _T_297 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_297 node _T_298 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_298 node _T_299 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_299 node _T_300 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_300 node _T_301 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_301 node _T_302 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_302 node _T_303 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_303 wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][0].data[1] node _T_304 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_304 node _T_305 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_305 node _T_306 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_306 node _T_307 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_307 node _T_308 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_308 node _T_309 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_309 node _T_310 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_310 node _T_311 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_311 node _T_312 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_312 node _T_313 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_313 node _T_314 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_314 node _T_315 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_315 node _T_316 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_316 node _T_317 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_317 node _T_318 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_318 node _T_319 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_319 node _T_320 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_320 node _T_321 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_321 node _T_322 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_322 node _T_323 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_323 node _T_324 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_324 node _T_325 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_325 node _T_326 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_326 wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][0].data[2] node _T_327 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_327 node _T_328 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_328 node _T_329 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_329 node _T_330 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_330 node _T_331 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_331 node _T_332 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_332 node _T_333 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_333 node _T_334 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_334 node _T_335 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_335 node _T_336 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_336 node _T_337 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_337 node _T_338 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_338 node _T_339 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_339 node _T_340 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_340 node _T_341 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_341 node _T_342 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_342 node _T_343 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_343 node _T_344 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_344 node _T_345 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_345 node _T_346 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_346 node _T_347 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_347 node _T_348 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_348 node _T_349 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_349 wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][0].data[3] node _T_350 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_350 node _T_351 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_351 node _T_352 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_352 node _T_353 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_353 node _T_354 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_354 node _T_355 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_355 node _T_356 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_356 node _T_357 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_357 node _T_358 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_358 node _T_359 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_359 node _T_360 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_360 node _T_361 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_361 node _T_362 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_362 node _T_363 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_363 node _T_364 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_364 node _T_365 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_365 node _T_366 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_366 node _T_367 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_367 node _T_368 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_368 node _T_369 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_369 node _T_370 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_370 node _T_371 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_371 node _T_372 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_372 node _T_373 = eq(sectored_entries[0][0].tag_v, hv) node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0)) node _T_375 = and(_T_373, _T_374) when _T_375 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_376 = eq(sectored_entries[0][0].tag_v, hv) node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) when _T_378 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_379 = eq(sectored_entries[0][0].tag_v, hv) node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_381 = and(_T_379, _T_380) when _T_381 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_382 = eq(sectored_entries[0][0].tag_v, hv) node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0)) node _T_384 = and(_T_382, _T_383) when _T_384 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) else : node _T_385 = or(hv, hg) wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][0].data[0] node _T_386 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_386 node _T_387 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_387 node _T_388 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_388 node _T_389 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_389 node _T_390 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_390 node _T_391 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_391 node _T_392 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_392 node _T_393 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_393 node _T_394 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_394 node _T_395 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_395 node _T_396 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_396 node _T_397 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_397 node _T_398 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_398 node _T_399 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_399 node _T_400 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_400 node _T_401 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_401 node _T_402 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_402 node _T_403 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_403 node _T_404 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_404 node _T_405 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_405 node _T_406 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_406 node _T_407 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_407 node _T_408 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_408 wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][0].data[1] node _T_409 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_409 node _T_410 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_410 node _T_411 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_411 node _T_412 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_412 node _T_413 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_413 node _T_414 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_414 node _T_415 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_415 node _T_416 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_416 node _T_417 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_417 node _T_418 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_418 node _T_419 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_419 node _T_420 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_420 node _T_421 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_421 node _T_422 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_422 node _T_423 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_423 node _T_424 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_424 node _T_425 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_425 node _T_426 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_426 node _T_427 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_427 node _T_428 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_428 node _T_429 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_429 node _T_430 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_430 node _T_431 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_431 wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][0].data[2] node _T_432 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_432 node _T_433 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_433 node _T_434 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_434 node _T_435 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_435 node _T_436 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_436 node _T_437 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_437 node _T_438 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_438 node _T_439 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_439 node _T_440 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_440 node _T_441 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_441 node _T_442 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_442 node _T_443 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_443 node _T_444 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_444 node _T_445 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_445 node _T_446 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_446 node _T_447 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_447 node _T_448 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_448 node _T_449 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_449 node _T_450 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_450 node _T_451 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_451 node _T_452 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_452 node _T_453 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_453 node _T_454 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_454 wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][0].data[3] node _T_455 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_455 node _T_456 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_456 node _T_457 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_457 node _T_458 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_458 node _T_459 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_459 node _T_460 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_460 node _T_461 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_461 node _T_462 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_462 node _T_463 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_463 node _T_464 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_464 node _T_465 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_465 node _T_466 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_466 node _T_467 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_467 node _T_468 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_468 node _T_469 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_469 node _T_470 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_470 node _T_471 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_471 node _T_472 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_472 node _T_473 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_473 node _T_474 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_474 node _T_475 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_475 node _T_476 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_476 node _T_477 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_477 node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_478 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_479 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_480 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385) when _T_481 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_482 = eq(hg_1, UInt<1>(0h0)) node _T_483 = and(_T_482, io.sfence.bits.rs1) when _T_483 : node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_485 = shr(_T_484, 2) node _T_486 = eq(_T_485, UInt<1>(0h0)) node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_488 = and(_T_486, _T_487) when _T_488 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[0][1].data[0] node _T_489 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_489 node _T_490 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_490 node _T_491 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_491 node _T_492 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_492 node _T_493 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_493 node _T_494 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_494 node _T_495 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_495 node _T_496 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_496 node _T_497 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_497 node _T_498 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_498 node _T_499 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_499 node _T_500 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_500 node _T_501 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_501 node _T_502 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_502 node _T_503 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_503 node _T_504 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_504 node _T_505 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_505 node _T_506 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_506 node _T_507 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_507 node _T_508 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_508 node _T_509 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_509 node _T_510 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_510 node _T_511 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_511 wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[0][1].data[1] node _T_512 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_512 node _T_513 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_513 node _T_514 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_514 node _T_515 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_515 node _T_516 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_516 node _T_517 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_517 node _T_518 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_518 node _T_519 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_519 node _T_520 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_520 node _T_521 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_521 node _T_522 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_522 node _T_523 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_523 node _T_524 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_524 node _T_525 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_525 node _T_526 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_526 node _T_527 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_527 node _T_528 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_528 node _T_529 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_529 node _T_530 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_530 node _T_531 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_531 node _T_532 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_532 node _T_533 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_533 node _T_534 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_534 wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[0][1].data[2] node _T_535 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_535 node _T_536 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_536 node _T_537 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_537 node _T_538 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_538 node _T_539 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_539 node _T_540 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_540 node _T_541 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_541 node _T_542 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_542 node _T_543 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_543 node _T_544 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_544 node _T_545 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_545 node _T_546 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_546 node _T_547 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_547 node _T_548 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_548 node _T_549 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_549 node _T_550 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_550 node _T_551 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_551 node _T_552 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_552 node _T_553 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_553 node _T_554 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_554 node _T_555 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_555 node _T_556 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_556 node _T_557 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_557 wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[0][1].data[3] node _T_558 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_558 node _T_559 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_559 node _T_560 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_560 node _T_561 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_561 node _T_562 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_562 node _T_563 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_563 node _T_564 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_564 node _T_565 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_565 node _T_566 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_566 node _T_567 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_567 node _T_568 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_568 node _T_569 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_569 node _T_570 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_570 node _T_571 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_571 node _T_572 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_572 node _T_573 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_573 node _T_574 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_574 node _T_575 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_575 node _T_576 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_576 node _T_577 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_577 node _T_578 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_578 node _T_579 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_579 node _T_580 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_580 node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_582 = bits(vpn, 1, 0) node _T_583 = eq(UInt<1>(0h0), _T_582) node _T_584 = and(_T_581, _T_583) when _T_584 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_586 = bits(vpn, 1, 0) node _T_587 = eq(UInt<1>(0h1), _T_586) node _T_588 = and(_T_585, _T_587) when _T_588 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_590 = bits(vpn, 1, 0) node _T_591 = eq(UInt<2>(0h2), _T_590) node _T_592 = and(_T_589, _T_591) when _T_592 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_594 = bits(vpn, 1, 0) node _T_595 = eq(UInt<2>(0h3), _T_594) node _T_596 = and(_T_593, _T_595) when _T_596 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_598 = shr(_T_597, 18) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[0][1].data[0] node _T_600 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_600 node _T_601 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_601 node _T_602 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_602 node _T_603 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_603 node _T_604 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_604 node _T_605 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_605 node _T_606 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_606 node _T_607 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_607 node _T_608 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_608 node _T_609 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_609 node _T_610 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_610 node _T_611 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_611 node _T_612 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_612 node _T_613 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_613 node _T_614 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_614 node _T_615 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_615 node _T_616 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_616 node _T_617 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_617 node _T_618 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_618 node _T_619 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_619 node _T_620 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_620 node _T_621 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_621 node _T_622 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_622 wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[0][1].data[1] node _T_623 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_623 node _T_624 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_624 node _T_625 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_625 node _T_626 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_626 node _T_627 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_627 node _T_628 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_628 node _T_629 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_629 node _T_630 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_630 node _T_631 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_631 node _T_632 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_632 node _T_633 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_633 node _T_634 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_634 node _T_635 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_635 node _T_636 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_636 node _T_637 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_637 node _T_638 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_638 node _T_639 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_639 node _T_640 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_640 node _T_641 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_641 node _T_642 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_642 node _T_643 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_643 node _T_644 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_644 node _T_645 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_645 wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[0][1].data[2] node _T_646 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_646 node _T_647 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_647 node _T_648 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_648 node _T_649 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_649 node _T_650 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_650 node _T_651 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_651 node _T_652 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_652 node _T_653 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_653 node _T_654 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_654 node _T_655 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_655 node _T_656 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_656 node _T_657 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_657 node _T_658 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_658 node _T_659 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_659 node _T_660 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_660 node _T_661 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_661 node _T_662 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_662 node _T_663 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_663 node _T_664 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_664 node _T_665 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_665 node _T_666 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_666 node _T_667 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_667 node _T_668 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_668 wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[0][1].data[3] node _T_669 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_669 node _T_670 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_670 node _T_671 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_671 node _T_672 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_672 node _T_673 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_673 node _T_674 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_674 node _T_675 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_675 node _T_676 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_676 node _T_677 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_677 node _T_678 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_678 node _T_679 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_679 node _T_680 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_680 node _T_681 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_681 node _T_682 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_682 node _T_683 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_683 node _T_684 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_684 node _T_685 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_685 node _T_686 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_686 node _T_687 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_687 node _T_688 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_688 node _T_689 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_689 node _T_690 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_690 node _T_691 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_691 node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage) when _T_693 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage) when _T_695 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage) when _T_697 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage) when _T_699 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_700 = eq(hg_1, UInt<1>(0h0)) node _T_701 = and(_T_700, io.sfence.bits.rs2) when _T_701 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[0][1].data[0] node _T_702 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_702 node _T_703 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_703 node _T_704 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_704 node _T_705 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_705 node _T_706 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_706 node _T_707 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_707 node _T_708 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_708 node _T_709 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_709 node _T_710 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_710 node _T_711 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_711 node _T_712 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_712 node _T_713 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_713 node _T_714 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_714 node _T_715 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_715 node _T_716 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_716 node _T_717 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_717 node _T_718 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_718 node _T_719 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_719 node _T_720 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_720 node _T_721 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_721 node _T_722 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_722 node _T_723 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_723 node _T_724 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_724 wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[0][1].data[1] node _T_725 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_725 node _T_726 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_726 node _T_727 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_727 node _T_728 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_728 node _T_729 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_729 node _T_730 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_730 node _T_731 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_731 node _T_732 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_732 node _T_733 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_733 node _T_734 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_734 node _T_735 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_735 node _T_736 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_736 node _T_737 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_737 node _T_738 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_738 node _T_739 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_739 node _T_740 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_740 node _T_741 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_741 node _T_742 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_742 node _T_743 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_743 node _T_744 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_744 node _T_745 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_745 node _T_746 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_746 node _T_747 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_747 wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[0][1].data[2] node _T_748 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_748 node _T_749 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_749 node _T_750 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_750 node _T_751 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_751 node _T_752 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_752 node _T_753 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_753 node _T_754 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_754 node _T_755 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_755 node _T_756 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_756 node _T_757 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_757 node _T_758 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_758 node _T_759 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_759 node _T_760 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_760 node _T_761 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_761 node _T_762 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_762 node _T_763 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_763 node _T_764 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_764 node _T_765 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_765 node _T_766 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_766 node _T_767 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_767 node _T_768 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_768 node _T_769 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_769 node _T_770 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_770 wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[0][1].data[3] node _T_771 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_771 node _T_772 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_772 node _T_773 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_773 node _T_774 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_774 node _T_775 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_775 node _T_776 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_776 node _T_777 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_777 node _T_778 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_778 node _T_779 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_779 node _T_780 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_780 node _T_781 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_781 node _T_782 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_782 node _T_783 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_783 node _T_784 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_784 node _T_785 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_785 node _T_786 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_786 node _T_787 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_787 node _T_788 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_788 node _T_789 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_789 node _T_790 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_790 node _T_791 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_791 node _T_792 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_792 node _T_793 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_793 node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0)) node _T_796 = and(_T_794, _T_795) when _T_796 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0)) node _T_799 = and(_T_797, _T_798) when _T_799 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_802 = and(_T_800, _T_801) when _T_802 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0)) node _T_805 = and(_T_803, _T_804) when _T_805 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) else : node _T_806 = or(hv_1, hg_1) wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[0][1].data[0] node _T_807 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_807 node _T_808 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_808 node _T_809 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_809 node _T_810 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_810 node _T_811 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_811 node _T_812 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_812 node _T_813 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_813 node _T_814 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_814 node _T_815 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_815 node _T_816 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_816 node _T_817 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_817 node _T_818 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_818 node _T_819 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_819 node _T_820 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_820 node _T_821 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_821 node _T_822 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_822 node _T_823 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_823 node _T_824 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_824 node _T_825 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_825 node _T_826 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_826 node _T_827 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_827 node _T_828 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_828 node _T_829 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_829 wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[0][1].data[1] node _T_830 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_830 node _T_831 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_831 node _T_832 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_832 node _T_833 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_833 node _T_834 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_834 node _T_835 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_835 node _T_836 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_836 node _T_837 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_837 node _T_838 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_838 node _T_839 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_839 node _T_840 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_840 node _T_841 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_841 node _T_842 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_842 node _T_843 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_843 node _T_844 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_844 node _T_845 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_845 node _T_846 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_846 node _T_847 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_847 node _T_848 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_848 node _T_849 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_849 node _T_850 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_850 node _T_851 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_851 node _T_852 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_852 wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[0][1].data[2] node _T_853 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_853 node _T_854 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_854 node _T_855 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_855 node _T_856 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_856 node _T_857 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_857 node _T_858 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_858 node _T_859 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_859 node _T_860 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_860 node _T_861 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_861 node _T_862 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_862 node _T_863 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_863 node _T_864 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_864 node _T_865 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_865 node _T_866 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_866 node _T_867 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_867 node _T_868 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_868 node _T_869 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_869 node _T_870 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_870 node _T_871 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_871 node _T_872 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_872 node _T_873 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_873 node _T_874 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_874 node _T_875 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_875 wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[0][1].data[3] node _T_876 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_876 node _T_877 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_877 node _T_878 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_878 node _T_879 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_879 node _T_880 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_880 node _T_881 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_881 node _T_882 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_882 node _T_883 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_883 node _T_884 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_884 node _T_885 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_885 node _T_886 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_886 node _T_887 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_887 node _T_888 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_888 node _T_889 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_889 node _T_890 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_890 node _T_891 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_891 node _T_892 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_892 node _T_893 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_893 node _T_894 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_894 node _T_895 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_895 node _T_896 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_896 node _T_897 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_897 node _T_898 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_898 node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_899 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_900 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_901 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806) when _T_902 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_903 = eq(hg_2, UInt<1>(0h0)) node _T_904 = and(_T_903, io.sfence.bits.rs1) when _T_904 : node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_906 = shr(_T_905, 2) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_909 = and(_T_907, _T_908) when _T_909 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[0][2].data[0] node _T_910 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_910 node _T_911 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_911 node _T_912 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_912 node _T_913 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_913 node _T_914 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_914 node _T_915 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_915 node _T_916 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_916 node _T_917 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_917 node _T_918 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_918 node _T_919 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_919 node _T_920 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_920 node _T_921 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_921 node _T_922 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_922 node _T_923 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_923 node _T_924 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_924 node _T_925 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_925 node _T_926 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_926 node _T_927 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_927 node _T_928 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_928 node _T_929 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_929 node _T_930 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_930 node _T_931 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_931 node _T_932 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_932 wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[0][2].data[1] node _T_933 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_933 node _T_934 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_934 node _T_935 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_935 node _T_936 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_936 node _T_937 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_937 node _T_938 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_938 node _T_939 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_939 node _T_940 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_940 node _T_941 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_941 node _T_942 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_942 node _T_943 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_943 node _T_944 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_944 node _T_945 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_945 node _T_946 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_946 node _T_947 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_947 node _T_948 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_948 node _T_949 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_949 node _T_950 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_950 node _T_951 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_951 node _T_952 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_952 node _T_953 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_953 node _T_954 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_954 node _T_955 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_955 wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[0][2].data[2] node _T_956 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_956 node _T_957 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_957 node _T_958 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_958 node _T_959 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_959 node _T_960 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_960 node _T_961 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_961 node _T_962 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_962 node _T_963 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_963 node _T_964 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_964 node _T_965 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_965 node _T_966 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_966 node _T_967 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_967 node _T_968 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_968 node _T_969 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_969 node _T_970 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_970 node _T_971 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_971 node _T_972 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_972 node _T_973 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_973 node _T_974 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_974 node _T_975 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_975 node _T_976 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_976 node _T_977 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_977 node _T_978 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_978 wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[0][2].data[3] node _T_979 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_979 node _T_980 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_980 node _T_981 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_981 node _T_982 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_982 node _T_983 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_983 node _T_984 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_984 node _T_985 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_985 node _T_986 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_986 node _T_987 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_987 node _T_988 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_988 node _T_989 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_989 node _T_990 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_990 node _T_991 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_991 node _T_992 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_992 node _T_993 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_993 node _T_994 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_994 node _T_995 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_995 node _T_996 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_996 node _T_997 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_997 node _T_998 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_998 node _T_999 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_999 node _T_1000 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1000 node _T_1001 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1001 node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1003 = bits(vpn, 1, 0) node _T_1004 = eq(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_1002, _T_1004) when _T_1005 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1007 = bits(vpn, 1, 0) node _T_1008 = eq(UInt<1>(0h1), _T_1007) node _T_1009 = and(_T_1006, _T_1008) when _T_1009 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1011 = bits(vpn, 1, 0) node _T_1012 = eq(UInt<2>(0h2), _T_1011) node _T_1013 = and(_T_1010, _T_1012) when _T_1013 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1015 = bits(vpn, 1, 0) node _T_1016 = eq(UInt<2>(0h3), _T_1015) node _T_1017 = and(_T_1014, _T_1016) when _T_1017 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_1019 = shr(_T_1018, 18) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[0][2].data[0] node _T_1021 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1021 node _T_1022 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1022 node _T_1023 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1023 node _T_1024 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1024 node _T_1025 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1025 node _T_1026 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1026 node _T_1027 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1027 node _T_1028 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1028 node _T_1029 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1029 node _T_1030 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1030 node _T_1031 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1031 node _T_1032 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1032 node _T_1033 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1033 node _T_1034 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1034 node _T_1035 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1035 node _T_1036 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1036 node _T_1037 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1037 node _T_1038 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1038 node _T_1039 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1039 node _T_1040 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1040 node _T_1041 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1041 node _T_1042 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1042 node _T_1043 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1043 wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[0][2].data[1] node _T_1044 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1044 node _T_1045 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1045 node _T_1046 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1046 node _T_1047 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1047 node _T_1048 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1048 node _T_1049 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1049 node _T_1050 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1050 node _T_1051 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1051 node _T_1052 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1052 node _T_1053 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1053 node _T_1054 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1054 node _T_1055 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1055 node _T_1056 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1056 node _T_1057 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1057 node _T_1058 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1058 node _T_1059 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1059 node _T_1060 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1060 node _T_1061 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1061 node _T_1062 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1062 node _T_1063 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1063 node _T_1064 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1064 node _T_1065 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1065 node _T_1066 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1066 wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[0][2].data[2] node _T_1067 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1067 node _T_1068 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1068 node _T_1069 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1069 node _T_1070 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1070 node _T_1071 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1071 node _T_1072 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1072 node _T_1073 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1073 node _T_1074 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1074 node _T_1075 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1075 node _T_1076 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1076 node _T_1077 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1077 node _T_1078 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1078 node _T_1079 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1079 node _T_1080 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1080 node _T_1081 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1081 node _T_1082 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1082 node _T_1083 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1083 node _T_1084 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1084 node _T_1085 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1085 node _T_1086 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1086 node _T_1087 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1087 node _T_1088 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1088 node _T_1089 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1089 wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[0][2].data[3] node _T_1090 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1090 node _T_1091 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1091 node _T_1092 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1092 node _T_1093 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1093 node _T_1094 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1094 node _T_1095 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1095 node _T_1096 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1096 node _T_1097 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1097 node _T_1098 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1098 node _T_1099 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1099 node _T_1100 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1100 node _T_1101 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1101 node _T_1102 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1102 node _T_1103 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1103 node _T_1104 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1104 node _T_1105 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1105 node _T_1106 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1106 node _T_1107 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1107 node _T_1108 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1108 node _T_1109 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1109 node _T_1110 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1110 node _T_1111 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1111 node _T_1112 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1112 node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage) when _T_1114 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage) when _T_1116 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage) when _T_1118 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage) when _T_1120 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1121 = eq(hg_2, UInt<1>(0h0)) node _T_1122 = and(_T_1121, io.sfence.bits.rs2) when _T_1122 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[0][2].data[0] node _T_1123 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1123 node _T_1124 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1124 node _T_1125 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1125 node _T_1126 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1126 node _T_1127 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1127 node _T_1128 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1128 node _T_1129 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1129 node _T_1130 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1130 node _T_1131 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1131 node _T_1132 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1132 node _T_1133 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1133 node _T_1134 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1134 node _T_1135 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1135 node _T_1136 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1136 node _T_1137 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1137 node _T_1138 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1138 node _T_1139 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1139 node _T_1140 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1140 node _T_1141 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1141 node _T_1142 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1142 node _T_1143 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1143 node _T_1144 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1144 node _T_1145 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1145 wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[0][2].data[1] node _T_1146 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1146 node _T_1147 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1147 node _T_1148 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1148 node _T_1149 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1149 node _T_1150 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1150 node _T_1151 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1151 node _T_1152 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1152 node _T_1153 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1153 node _T_1154 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1154 node _T_1155 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1155 node _T_1156 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1156 node _T_1157 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1157 node _T_1158 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1158 node _T_1159 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1159 node _T_1160 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1160 node _T_1161 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1161 node _T_1162 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1162 node _T_1163 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1163 node _T_1164 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1164 node _T_1165 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1165 node _T_1166 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1166 node _T_1167 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1167 node _T_1168 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1168 wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[0][2].data[2] node _T_1169 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1169 node _T_1170 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1170 node _T_1171 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1171 node _T_1172 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1172 node _T_1173 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1173 node _T_1174 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1174 node _T_1175 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1175 node _T_1176 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1176 node _T_1177 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1177 node _T_1178 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1178 node _T_1179 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1179 node _T_1180 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1180 node _T_1181 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1181 node _T_1182 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1182 node _T_1183 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1183 node _T_1184 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1184 node _T_1185 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1185 node _T_1186 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1186 node _T_1187 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1187 node _T_1188 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1188 node _T_1189 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1189 node _T_1190 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1190 node _T_1191 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1191 wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[0][2].data[3] node _T_1192 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1192 node _T_1193 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1193 node _T_1194 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1194 node _T_1195 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1195 node _T_1196 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1196 node _T_1197 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1197 node _T_1198 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1198 node _T_1199 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1199 node _T_1200 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1200 node _T_1201 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1201 node _T_1202 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1202 node _T_1203 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1203 node _T_1204 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1204 node _T_1205 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1205 node _T_1206 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1206 node _T_1207 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1207 node _T_1208 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1208 node _T_1209 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1209 node _T_1210 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1210 node _T_1211 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1211 node _T_1212 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1212 node _T_1213 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1213 node _T_1214 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1214 node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0)) node _T_1217 = and(_T_1215, _T_1216) when _T_1217 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0)) node _T_1220 = and(_T_1218, _T_1219) when _T_1220 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1223 = and(_T_1221, _T_1222) when _T_1223 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0)) node _T_1226 = and(_T_1224, _T_1225) when _T_1226 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) else : node _T_1227 = or(hv_2, hg_2) wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[0][2].data[0] node _T_1228 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1228 node _T_1229 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1229 node _T_1230 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1230 node _T_1231 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1231 node _T_1232 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1232 node _T_1233 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1233 node _T_1234 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1234 node _T_1235 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1235 node _T_1236 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1236 node _T_1237 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1237 node _T_1238 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1238 node _T_1239 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1239 node _T_1240 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1240 node _T_1241 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1241 node _T_1242 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1242 node _T_1243 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1243 node _T_1244 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1244 node _T_1245 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1245 node _T_1246 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1246 node _T_1247 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1247 node _T_1248 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1248 node _T_1249 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1249 node _T_1250 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1250 wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[0][2].data[1] node _T_1251 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1251 node _T_1252 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1252 node _T_1253 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1253 node _T_1254 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1254 node _T_1255 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1255 node _T_1256 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1256 node _T_1257 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1257 node _T_1258 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1258 node _T_1259 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1259 node _T_1260 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1260 node _T_1261 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1261 node _T_1262 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1262 node _T_1263 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1263 node _T_1264 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1264 node _T_1265 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1265 node _T_1266 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1266 node _T_1267 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1267 node _T_1268 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1268 node _T_1269 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1269 node _T_1270 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1270 node _T_1271 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1271 node _T_1272 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1272 node _T_1273 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1273 wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[0][2].data[2] node _T_1274 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1274 node _T_1275 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1275 node _T_1276 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1276 node _T_1277 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1277 node _T_1278 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1278 node _T_1279 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1279 node _T_1280 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1280 node _T_1281 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1281 node _T_1282 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1282 node _T_1283 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1283 node _T_1284 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1284 node _T_1285 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1285 node _T_1286 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1286 node _T_1287 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1287 node _T_1288 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1288 node _T_1289 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1289 node _T_1290 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1290 node _T_1291 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1291 node _T_1292 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1292 node _T_1293 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1293 node _T_1294 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1294 node _T_1295 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1295 node _T_1296 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1296 wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[0][2].data[3] node _T_1297 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1297 node _T_1298 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1298 node _T_1299 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1299 node _T_1300 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1300 node _T_1301 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1301 node _T_1302 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1302 node _T_1303 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1303 node _T_1304 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1304 node _T_1305 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1305 node _T_1306 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1306 node _T_1307 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1307 node _T_1308 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1308 node _T_1309 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1309 node _T_1310 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1310 node _T_1311 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1311 node _T_1312 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1312 node _T_1313 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1313 node _T_1314 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1314 node _T_1315 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1315 node _T_1316 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1316 node _T_1317 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1317 node _T_1318 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1318 node _T_1319 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1319 node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1320 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1321 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1322 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227) when _T_1323 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1324 = eq(hg_3, UInt<1>(0h0)) node _T_1325 = and(_T_1324, io.sfence.bits.rs1) when _T_1325 : node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1327 = shr(_T_1326, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1330 = and(_T_1328, _T_1329) when _T_1330 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[0][3].data[0] node _T_1331 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1331 node _T_1332 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1332 node _T_1333 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1333 node _T_1334 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1334 node _T_1335 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1335 node _T_1336 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1336 node _T_1337 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1337 node _T_1338 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1338 node _T_1339 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1339 node _T_1340 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1340 node _T_1341 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1341 node _T_1342 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1342 node _T_1343 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1343 node _T_1344 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1344 node _T_1345 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1345 node _T_1346 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1346 node _T_1347 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1347 node _T_1348 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1348 node _T_1349 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1349 node _T_1350 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1350 node _T_1351 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1351 node _T_1352 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1352 node _T_1353 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1353 wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[0][3].data[1] node _T_1354 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1354 node _T_1355 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1355 node _T_1356 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1356 node _T_1357 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1357 node _T_1358 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1358 node _T_1359 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1359 node _T_1360 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1360 node _T_1361 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1361 node _T_1362 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1362 node _T_1363 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1363 node _T_1364 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1364 node _T_1365 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1365 node _T_1366 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1366 node _T_1367 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1367 node _T_1368 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1368 node _T_1369 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1369 node _T_1370 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1370 node _T_1371 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1371 node _T_1372 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1372 node _T_1373 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1373 node _T_1374 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1374 node _T_1375 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1375 node _T_1376 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1376 wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[0][3].data[2] node _T_1377 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1377 node _T_1378 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1378 node _T_1379 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1379 node _T_1380 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1380 node _T_1381 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1381 node _T_1382 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1382 node _T_1383 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1383 node _T_1384 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1384 node _T_1385 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1385 node _T_1386 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1386 node _T_1387 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1387 node _T_1388 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1388 node _T_1389 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1389 node _T_1390 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1390 node _T_1391 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1391 node _T_1392 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1392 node _T_1393 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1393 node _T_1394 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1394 node _T_1395 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1395 node _T_1396 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1396 node _T_1397 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1397 node _T_1398 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1398 node _T_1399 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1399 wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[0][3].data[3] node _T_1400 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1400 node _T_1401 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1401 node _T_1402 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1402 node _T_1403 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1403 node _T_1404 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1404 node _T_1405 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1405 node _T_1406 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1406 node _T_1407 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1407 node _T_1408 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1408 node _T_1409 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1409 node _T_1410 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1410 node _T_1411 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1411 node _T_1412 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1412 node _T_1413 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1413 node _T_1414 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1414 node _T_1415 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1415 node _T_1416 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1416 node _T_1417 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1417 node _T_1418 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1418 node _T_1419 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1419 node _T_1420 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1420 node _T_1421 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1421 node _T_1422 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1422 node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1424 = bits(vpn, 1, 0) node _T_1425 = eq(UInt<1>(0h0), _T_1424) node _T_1426 = and(_T_1423, _T_1425) when _T_1426 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1428 = bits(vpn, 1, 0) node _T_1429 = eq(UInt<1>(0h1), _T_1428) node _T_1430 = and(_T_1427, _T_1429) when _T_1430 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1432 = bits(vpn, 1, 0) node _T_1433 = eq(UInt<2>(0h2), _T_1432) node _T_1434 = and(_T_1431, _T_1433) when _T_1434 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1436 = bits(vpn, 1, 0) node _T_1437 = eq(UInt<2>(0h3), _T_1436) node _T_1438 = and(_T_1435, _T_1437) when _T_1438 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_1440 = shr(_T_1439, 18) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[0][3].data[0] node _T_1442 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1442 node _T_1443 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1443 node _T_1444 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1444 node _T_1445 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1445 node _T_1446 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1446 node _T_1447 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1447 node _T_1448 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1448 node _T_1449 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1449 node _T_1450 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1450 node _T_1451 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1451 node _T_1452 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1452 node _T_1453 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1453 node _T_1454 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1454 node _T_1455 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1455 node _T_1456 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1456 node _T_1457 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1457 node _T_1458 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1458 node _T_1459 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1459 node _T_1460 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1460 node _T_1461 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1461 node _T_1462 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1462 node _T_1463 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1463 node _T_1464 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1464 wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[0][3].data[1] node _T_1465 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1465 node _T_1466 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1466 node _T_1467 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1467 node _T_1468 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1468 node _T_1469 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1469 node _T_1470 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1470 node _T_1471 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1471 node _T_1472 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1472 node _T_1473 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1473 node _T_1474 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1474 node _T_1475 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1475 node _T_1476 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1476 node _T_1477 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1477 node _T_1478 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1478 node _T_1479 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1479 node _T_1480 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1480 node _T_1481 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1481 node _T_1482 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1482 node _T_1483 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1483 node _T_1484 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1484 node _T_1485 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1485 node _T_1486 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1486 node _T_1487 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1487 wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[0][3].data[2] node _T_1488 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1488 node _T_1489 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1489 node _T_1490 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1490 node _T_1491 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1491 node _T_1492 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1492 node _T_1493 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1493 node _T_1494 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1494 node _T_1495 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1495 node _T_1496 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1496 node _T_1497 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1497 node _T_1498 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1498 node _T_1499 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1499 node _T_1500 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1500 node _T_1501 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1501 node _T_1502 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1502 node _T_1503 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1503 node _T_1504 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1504 node _T_1505 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1505 node _T_1506 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1506 node _T_1507 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1507 node _T_1508 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1508 node _T_1509 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1509 node _T_1510 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1510 wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[0][3].data[3] node _T_1511 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1511 node _T_1512 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1512 node _T_1513 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1513 node _T_1514 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1514 node _T_1515 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1515 node _T_1516 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1516 node _T_1517 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1517 node _T_1518 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1518 node _T_1519 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1519 node _T_1520 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1520 node _T_1521 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1521 node _T_1522 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1522 node _T_1523 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1523 node _T_1524 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1524 node _T_1525 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1525 node _T_1526 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1526 node _T_1527 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1527 node _T_1528 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1528 node _T_1529 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1529 node _T_1530 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1530 node _T_1531 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1531 node _T_1532 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1532 node _T_1533 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1533 node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage) when _T_1535 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage) when _T_1537 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage) when _T_1539 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage) when _T_1541 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1542 = eq(hg_3, UInt<1>(0h0)) node _T_1543 = and(_T_1542, io.sfence.bits.rs2) when _T_1543 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[0][3].data[0] node _T_1544 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1544 node _T_1545 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1545 node _T_1546 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1546 node _T_1547 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1547 node _T_1548 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1548 node _T_1549 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1549 node _T_1550 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1550 node _T_1551 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1551 node _T_1552 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1552 node _T_1553 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1553 node _T_1554 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1554 node _T_1555 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1555 node _T_1556 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1556 node _T_1557 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1557 node _T_1558 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1558 node _T_1559 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1559 node _T_1560 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1560 node _T_1561 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1561 node _T_1562 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1562 node _T_1563 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1563 node _T_1564 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1564 node _T_1565 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1565 node _T_1566 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1566 wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[0][3].data[1] node _T_1567 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1567 node _T_1568 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1568 node _T_1569 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1569 node _T_1570 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1570 node _T_1571 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1571 node _T_1572 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1572 node _T_1573 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1573 node _T_1574 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1574 node _T_1575 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1575 node _T_1576 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1576 node _T_1577 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1577 node _T_1578 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1578 node _T_1579 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1579 node _T_1580 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1580 node _T_1581 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1581 node _T_1582 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1582 node _T_1583 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1583 node _T_1584 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1584 node _T_1585 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1585 node _T_1586 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1586 node _T_1587 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1587 node _T_1588 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1588 node _T_1589 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1589 wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[0][3].data[2] node _T_1590 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1590 node _T_1591 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1591 node _T_1592 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1592 node _T_1593 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1593 node _T_1594 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1594 node _T_1595 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1595 node _T_1596 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1596 node _T_1597 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1597 node _T_1598 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1598 node _T_1599 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1599 node _T_1600 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1600 node _T_1601 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1601 node _T_1602 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1602 node _T_1603 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1603 node _T_1604 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1604 node _T_1605 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1605 node _T_1606 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1606 node _T_1607 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1607 node _T_1608 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1608 node _T_1609 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1609 node _T_1610 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1610 node _T_1611 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1611 node _T_1612 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1612 wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[0][3].data[3] node _T_1613 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1613 node _T_1614 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1614 node _T_1615 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1615 node _T_1616 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1616 node _T_1617 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1617 node _T_1618 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1618 node _T_1619 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1619 node _T_1620 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1620 node _T_1621 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1621 node _T_1622 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1622 node _T_1623 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1623 node _T_1624 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1624 node _T_1625 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1625 node _T_1626 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1626 node _T_1627 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1627 node _T_1628 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1628 node _T_1629 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1629 node _T_1630 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1630 node _T_1631 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1631 node _T_1632 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1632 node _T_1633 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1633 node _T_1634 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1634 node _T_1635 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1635 node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0)) node _T_1638 = and(_T_1636, _T_1637) when _T_1638 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0)) node _T_1641 = and(_T_1639, _T_1640) when _T_1641 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1644 = and(_T_1642, _T_1643) when _T_1644 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0)) node _T_1647 = and(_T_1645, _T_1646) when _T_1647 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) else : node _T_1648 = or(hv_3, hg_3) wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[0][3].data[0] node _T_1649 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1649 node _T_1650 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1650 node _T_1651 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1651 node _T_1652 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1652 node _T_1653 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1653 node _T_1654 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1654 node _T_1655 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1655 node _T_1656 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1656 node _T_1657 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1657 node _T_1658 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1658 node _T_1659 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1659 node _T_1660 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1660 node _T_1661 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1661 node _T_1662 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1662 node _T_1663 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1663 node _T_1664 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1664 node _T_1665 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1665 node _T_1666 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1666 node _T_1667 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1667 node _T_1668 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1668 node _T_1669 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1669 node _T_1670 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1670 node _T_1671 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1671 wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[0][3].data[1] node _T_1672 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1672 node _T_1673 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1673 node _T_1674 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1674 node _T_1675 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1675 node _T_1676 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1676 node _T_1677 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1677 node _T_1678 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1678 node _T_1679 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1679 node _T_1680 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1680 node _T_1681 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1681 node _T_1682 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1682 node _T_1683 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1683 node _T_1684 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1684 node _T_1685 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1685 node _T_1686 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1686 node _T_1687 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1687 node _T_1688 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1688 node _T_1689 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1689 node _T_1690 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1690 node _T_1691 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1691 node _T_1692 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1692 node _T_1693 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1693 node _T_1694 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1694 wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[0][3].data[2] node _T_1695 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1695 node _T_1696 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1696 node _T_1697 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1697 node _T_1698 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1698 node _T_1699 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1699 node _T_1700 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1700 node _T_1701 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1701 node _T_1702 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1702 node _T_1703 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1703 node _T_1704 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1704 node _T_1705 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1705 node _T_1706 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1706 node _T_1707 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1707 node _T_1708 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1708 node _T_1709 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1709 node _T_1710 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1710 node _T_1711 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1711 node _T_1712 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1712 node _T_1713 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1713 node _T_1714 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1714 node _T_1715 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1715 node _T_1716 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1716 node _T_1717 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1717 wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[0][3].data[3] node _T_1718 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1718 node _T_1719 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1719 node _T_1720 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1720 node _T_1721 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1721 node _T_1722 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1722 node _T_1723 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1723 node _T_1724 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1724 node _T_1725 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1725 node _T_1726 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1726 node _T_1727 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1727 node _T_1728 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1728 node _T_1729 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1729 node _T_1730 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1730 node _T_1731 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1731 node _T_1732 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1732 node _T_1733 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1733 node _T_1734 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1734 node _T_1735 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1735 node _T_1736 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1736 node _T_1737 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1737 node _T_1738 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1738 node _T_1739 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1739 node _T_1740 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1740 node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1741 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1742 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1743 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648) when _T_1744 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_4, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 2) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, sectored_entries[0][4].data[0] node _T_1752 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1753 node _T_1754 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1754 node _T_1755 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1755 node _T_1756 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1756 node _T_1757 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1757 node _T_1758 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1758 node _T_1759 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1759 node _T_1760 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1760 node _T_1761 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1761 node _T_1762 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1762 node _T_1763 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1763 node _T_1764 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1764 node _T_1765 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1765 node _T_1766 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1766 node _T_1767 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1767 node _T_1768 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1768 node _T_1769 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1770 node _T_1771 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1772 node _T_1773 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1773 node _T_1774 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1774 wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, sectored_entries[0][4].data[1] node _T_1775 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1775 node _T_1776 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1776 node _T_1777 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1777 node _T_1778 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1778 node _T_1779 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1779 node _T_1780 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1780 node _T_1781 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1781 node _T_1782 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1782 node _T_1783 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1783 node _T_1784 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1784 node _T_1785 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1785 node _T_1786 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1786 node _T_1787 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1787 node _T_1788 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1788 node _T_1789 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1789 node _T_1790 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1790 node _T_1791 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1791 node _T_1792 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1792 node _T_1793 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1793 node _T_1794 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1794 node _T_1795 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1795 node _T_1796 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1796 node _T_1797 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1797 wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, sectored_entries[0][4].data[2] node _T_1798 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1798 node _T_1799 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1799 node _T_1800 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1800 node _T_1801 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1801 node _T_1802 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1802 node _T_1803 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1803 node _T_1804 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1804 node _T_1805 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1805 node _T_1806 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1806 node _T_1807 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1807 node _T_1808 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1808 node _T_1809 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1809 node _T_1810 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1810 node _T_1811 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1811 node _T_1812 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1812 node _T_1813 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1813 node _T_1814 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1814 node _T_1815 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1815 node _T_1816 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1816 node _T_1817 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1817 node _T_1818 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1818 node _T_1819 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1819 node _T_1820 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1820 wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, sectored_entries[0][4].data[3] node _T_1821 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1821 node _T_1822 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1822 node _T_1823 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1823 node _T_1824 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1824 node _T_1825 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1825 node _T_1826 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1826 node _T_1827 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1827 node _T_1828 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1828 node _T_1829 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1829 node _T_1830 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1830 node _T_1831 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1831 node _T_1832 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1832 node _T_1833 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1833 node _T_1834 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1834 node _T_1835 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1835 node _T_1836 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1836 node _T_1837 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1837 node _T_1838 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1838 node _T_1839 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1839 node _T_1840 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1840 node _T_1841 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1841 node _T_1842 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1842 node _T_1843 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1843 node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1845 = bits(vpn, 1, 0) node _T_1846 = eq(UInt<1>(0h0), _T_1845) node _T_1847 = and(_T_1844, _T_1846) when _T_1847 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1849 = bits(vpn, 1, 0) node _T_1850 = eq(UInt<1>(0h1), _T_1849) node _T_1851 = and(_T_1848, _T_1850) when _T_1851 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1853 = bits(vpn, 1, 0) node _T_1854 = eq(UInt<2>(0h2), _T_1853) node _T_1855 = and(_T_1852, _T_1854) when _T_1855 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1857 = bits(vpn, 1, 0) node _T_1858 = eq(UInt<2>(0h3), _T_1857) node _T_1859 = and(_T_1856, _T_1858) when _T_1859 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn) node _T_1861 = shr(_T_1860, 18) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, sectored_entries[0][4].data[0] node _T_1863 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_1863 node _T_1864 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_1864 node _T_1865 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_1865 node _T_1866 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_1866 node _T_1867 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_1867 node _T_1868 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_1868 node _T_1869 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_1869 node _T_1870 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_1870 node _T_1871 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_1871 node _T_1872 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_1872 node _T_1873 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_1873 node _T_1874 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_1874 node _T_1875 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_1875 node _T_1876 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_1876 node _T_1877 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_1877 node _T_1878 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_1878 node _T_1879 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_1879 node _T_1880 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_1880 node _T_1881 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_1881 node _T_1882 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_1882 node _T_1883 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_1883 node _T_1884 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_1884 node _T_1885 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_1885 wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, sectored_entries[0][4].data[1] node _T_1886 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_1886 node _T_1887 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_1887 node _T_1888 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_1888 node _T_1889 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_1889 node _T_1890 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_1890 node _T_1891 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_1891 node _T_1892 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_1892 node _T_1893 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_1893 node _T_1894 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_1894 node _T_1895 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_1895 node _T_1896 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_1896 node _T_1897 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_1897 node _T_1898 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_1898 node _T_1899 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_1899 node _T_1900 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_1900 node _T_1901 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_1901 node _T_1902 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_1902 node _T_1903 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_1903 node _T_1904 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_1904 node _T_1905 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_1905 node _T_1906 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_1906 node _T_1907 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_1907 node _T_1908 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_1908 wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][4].data[2] node _T_1909 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_1909 node _T_1910 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_1910 node _T_1911 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_1911 node _T_1912 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_1912 node _T_1913 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_1913 node _T_1914 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_1914 node _T_1915 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_1915 node _T_1916 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_1916 node _T_1917 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_1917 node _T_1918 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_1918 node _T_1919 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_1919 node _T_1920 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_1920 node _T_1921 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_1921 node _T_1922 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_1922 node _T_1923 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_1923 node _T_1924 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_1924 node _T_1925 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_1925 node _T_1926 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_1926 node _T_1927 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_1927 node _T_1928 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_1928 node _T_1929 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_1929 node _T_1930 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_1930 node _T_1931 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_1931 wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][4].data[3] node _T_1932 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_1932 node _T_1933 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_1933 node _T_1934 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_1934 node _T_1935 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_1935 node _T_1936 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_1936 node _T_1937 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_1937 node _T_1938 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_1938 node _T_1939 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_1939 node _T_1940 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_1940 node _T_1941 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_1941 node _T_1942 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_1942 node _T_1943 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_1943 node _T_1944 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_1944 node _T_1945 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_1945 node _T_1946 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_1946 node _T_1947 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_1947 node _T_1948 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_1948 node _T_1949 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_1949 node _T_1950 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_1950 node _T_1951 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_1951 node _T_1952 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_1952 node _T_1953 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_1953 node _T_1954 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_1954 node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage) when _T_1956 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage) when _T_1958 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage) when _T_1960 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage) when _T_1962 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_1963 = eq(hg_4, UInt<1>(0h0)) node _T_1964 = and(_T_1963, io.sfence.bits.rs2) when _T_1964 : wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][4].data[0] node _T_1965 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_1965 node _T_1966 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_1966 node _T_1967 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_1967 node _T_1968 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_1968 node _T_1969 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_1969 node _T_1970 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_1970 node _T_1971 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_1971 node _T_1972 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_1972 node _T_1973 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_1973 node _T_1974 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_1974 node _T_1975 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_1975 node _T_1976 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_1976 node _T_1977 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_1977 node _T_1978 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_1978 node _T_1979 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_1979 node _T_1980 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_1980 node _T_1981 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_1981 node _T_1982 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_1982 node _T_1983 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_1983 node _T_1984 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_1984 node _T_1985 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_1985 node _T_1986 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_1986 node _T_1987 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_1987 wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][4].data[1] node _T_1988 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_1988 node _T_1989 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_1989 node _T_1990 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_1990 node _T_1991 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_1991 node _T_1992 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_1992 node _T_1993 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_1993 node _T_1994 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_1994 node _T_1995 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_1995 node _T_1996 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_1996 node _T_1997 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_1997 node _T_1998 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_1998 node _T_1999 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_1999 node _T_2000 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2000 node _T_2001 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2001 node _T_2002 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2002 node _T_2003 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2003 node _T_2004 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2004 node _T_2005 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2005 node _T_2006 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2006 node _T_2007 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2007 node _T_2008 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2008 node _T_2009 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2009 node _T_2010 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2010 wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[0][4].data[2] node _T_2011 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2011 node _T_2012 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2012 node _T_2013 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2013 node _T_2014 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2014 node _T_2015 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2015 node _T_2016 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2016 node _T_2017 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2017 node _T_2018 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2018 node _T_2019 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2019 node _T_2020 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2020 node _T_2021 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2021 node _T_2022 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2022 node _T_2023 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2023 node _T_2024 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2024 node _T_2025 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2025 node _T_2026 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2026 node _T_2027 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2027 node _T_2028 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2028 node _T_2029 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2029 node _T_2030 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2030 node _T_2031 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2031 node _T_2032 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2032 node _T_2033 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2033 wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[0][4].data[3] node _T_2034 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2034 node _T_2035 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2035 node _T_2036 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2036 node _T_2037 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2037 node _T_2038 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2038 node _T_2039 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2039 node _T_2040 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2040 node _T_2041 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2041 node _T_2042 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2042 node _T_2043 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2043 node _T_2044 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2044 node _T_2045 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2045 node _T_2046 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2046 node _T_2047 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2047 node _T_2048 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2048 node _T_2049 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2049 node _T_2050 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2050 node _T_2051 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2051 node _T_2052 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2052 node _T_2053 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2053 node _T_2054 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2054 node _T_2055 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2055 node _T_2056 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2056 node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0)) node _T_2059 = and(_T_2057, _T_2058) when _T_2059 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0)) node _T_2062 = and(_T_2060, _T_2061) when _T_2062 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0)) node _T_2065 = and(_T_2063, _T_2064) when _T_2065 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4) node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0)) node _T_2068 = and(_T_2066, _T_2067) when _T_2068 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) else : node _T_2069 = or(hv_4, hg_4) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[0][4].data[0] node _T_2070 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2070 node _T_2071 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2071 node _T_2072 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2072 node _T_2073 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2073 node _T_2074 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2074 node _T_2075 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2075 node _T_2076 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2076 node _T_2077 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2077 node _T_2078 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2078 node _T_2079 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2079 node _T_2080 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2080 node _T_2081 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2081 node _T_2082 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2082 node _T_2083 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2083 node _T_2084 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2084 node _T_2085 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2085 node _T_2086 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2086 node _T_2087 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2087 node _T_2088 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2088 node _T_2089 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2089 node _T_2090 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2090 node _T_2091 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2091 node _T_2092 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2092 wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[0][4].data[1] node _T_2093 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2093 node _T_2094 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2094 node _T_2095 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2095 node _T_2096 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2096 node _T_2097 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2097 node _T_2098 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2098 node _T_2099 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2099 node _T_2100 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2100 node _T_2101 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2101 node _T_2102 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2102 node _T_2103 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2103 node _T_2104 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2104 node _T_2105 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2105 node _T_2106 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2106 node _T_2107 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2107 node _T_2108 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2108 node _T_2109 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2109 node _T_2110 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2110 node _T_2111 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2111 node _T_2112 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2112 node _T_2113 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2113 node _T_2114 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2114 node _T_2115 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2115 wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[0][4].data[2] node _T_2116 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2116 node _T_2117 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2117 node _T_2118 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2118 node _T_2119 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2119 node _T_2120 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2120 node _T_2121 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2121 node _T_2122 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2122 node _T_2123 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2123 node _T_2124 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2124 node _T_2125 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2125 node _T_2126 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2126 node _T_2127 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2127 node _T_2128 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2128 node _T_2129 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2129 node _T_2130 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2130 node _T_2131 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2131 node _T_2132 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2132 node _T_2133 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2133 node _T_2134 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2134 node _T_2135 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2135 node _T_2136 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2136 node _T_2137 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2137 node _T_2138 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2138 wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[0][4].data[3] node _T_2139 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2139 node _T_2140 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2140 node _T_2141 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2141 node _T_2142 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2142 node _T_2143 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2143 node _T_2144 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2144 node _T_2145 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2145 node _T_2146 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2146 node _T_2147 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2147 node _T_2148 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2148 node _T_2149 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2149 node _T_2150 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2150 node _T_2151 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2151 node _T_2152 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2152 node _T_2153 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2153 node _T_2154 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2154 node _T_2155 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2155 node _T_2156 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2156 node _T_2157 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2157 node _T_2158 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2158 node _T_2159 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2159 node _T_2160 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2160 node _T_2161 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2161 node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2162 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2163 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2164 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069) when _T_2165 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2166 = eq(hg_5, UInt<1>(0h0)) node _T_2167 = and(_T_2166, io.sfence.bits.rs1) when _T_2167 : node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2169 = shr(_T_2168, 2) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2172 = and(_T_2170, _T_2171) when _T_2172 : wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[0][5].data[0] node _T_2173 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2173 node _T_2174 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2174 node _T_2175 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2175 node _T_2176 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2176 node _T_2177 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2177 node _T_2178 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2178 node _T_2179 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2179 node _T_2180 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2180 node _T_2181 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2181 node _T_2182 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2182 node _T_2183 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2183 node _T_2184 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2184 node _T_2185 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2185 node _T_2186 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2186 node _T_2187 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2187 node _T_2188 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2188 node _T_2189 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2189 node _T_2190 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2190 node _T_2191 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2191 node _T_2192 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2192 node _T_2193 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2193 node _T_2194 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2194 node _T_2195 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2195 wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[0][5].data[1] node _T_2196 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2196 node _T_2197 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2197 node _T_2198 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2198 node _T_2199 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2199 node _T_2200 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2200 node _T_2201 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2201 node _T_2202 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2202 node _T_2203 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2203 node _T_2204 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2204 node _T_2205 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2205 node _T_2206 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2206 node _T_2207 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2207 node _T_2208 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2208 node _T_2209 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2209 node _T_2210 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2210 node _T_2211 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2211 node _T_2212 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2212 node _T_2213 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2213 node _T_2214 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2214 node _T_2215 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2215 node _T_2216 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2216 node _T_2217 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2217 node _T_2218 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2218 wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[0][5].data[2] node _T_2219 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2219 node _T_2220 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2220 node _T_2221 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2221 node _T_2222 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2222 node _T_2223 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2223 node _T_2224 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2224 node _T_2225 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2225 node _T_2226 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2226 node _T_2227 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2227 node _T_2228 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2228 node _T_2229 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2229 node _T_2230 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2230 node _T_2231 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2231 node _T_2232 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2232 node _T_2233 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2233 node _T_2234 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2234 node _T_2235 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2235 node _T_2236 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2236 node _T_2237 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2237 node _T_2238 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2238 node _T_2239 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2239 node _T_2240 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2240 node _T_2241 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2241 wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[0][5].data[3] node _T_2242 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2242 node _T_2243 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2243 node _T_2244 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2244 node _T_2245 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2245 node _T_2246 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2246 node _T_2247 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2247 node _T_2248 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2248 node _T_2249 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2249 node _T_2250 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2250 node _T_2251 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2251 node _T_2252 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2252 node _T_2253 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2253 node _T_2254 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2254 node _T_2255 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2255 node _T_2256 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2256 node _T_2257 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2257 node _T_2258 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2258 node _T_2259 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2259 node _T_2260 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2260 node _T_2261 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2261 node _T_2262 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2262 node _T_2263 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2263 node _T_2264 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2264 node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2266 = bits(vpn, 1, 0) node _T_2267 = eq(UInt<1>(0h0), _T_2266) node _T_2268 = and(_T_2265, _T_2267) when _T_2268 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2270 = bits(vpn, 1, 0) node _T_2271 = eq(UInt<1>(0h1), _T_2270) node _T_2272 = and(_T_2269, _T_2271) when _T_2272 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2274 = bits(vpn, 1, 0) node _T_2275 = eq(UInt<2>(0h2), _T_2274) node _T_2276 = and(_T_2273, _T_2275) when _T_2276 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2278 = bits(vpn, 1, 0) node _T_2279 = eq(UInt<2>(0h3), _T_2278) node _T_2280 = and(_T_2277, _T_2279) when _T_2280 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn) node _T_2282 = shr(_T_2281, 18) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[0][5].data[0] node _T_2284 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2284 node _T_2285 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2285 node _T_2286 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2286 node _T_2287 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2287 node _T_2288 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2288 node _T_2289 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2289 node _T_2290 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2290 node _T_2291 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2291 node _T_2292 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2292 node _T_2293 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2293 node _T_2294 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2294 node _T_2295 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2295 node _T_2296 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2296 node _T_2297 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2297 node _T_2298 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2298 node _T_2299 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2299 node _T_2300 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2300 node _T_2301 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2301 node _T_2302 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2302 node _T_2303 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2303 node _T_2304 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2304 node _T_2305 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2305 node _T_2306 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2306 wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[0][5].data[1] node _T_2307 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2307 node _T_2308 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2308 node _T_2309 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2309 node _T_2310 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2310 node _T_2311 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2311 node _T_2312 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2312 node _T_2313 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2313 node _T_2314 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2314 node _T_2315 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2315 node _T_2316 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2316 node _T_2317 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2317 node _T_2318 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2318 node _T_2319 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2319 node _T_2320 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2320 node _T_2321 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2321 node _T_2322 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2322 node _T_2323 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2323 node _T_2324 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2324 node _T_2325 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2325 node _T_2326 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2326 node _T_2327 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2327 node _T_2328 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2328 node _T_2329 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2329 wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, sectored_entries[0][5].data[2] node _T_2330 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2330 node _T_2331 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2331 node _T_2332 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2332 node _T_2333 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2333 node _T_2334 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2334 node _T_2335 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2335 node _T_2336 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2336 node _T_2337 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2337 node _T_2338 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2338 node _T_2339 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2339 node _T_2340 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2340 node _T_2341 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2341 node _T_2342 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2342 node _T_2343 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2343 node _T_2344 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2344 node _T_2345 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2345 node _T_2346 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2346 node _T_2347 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2347 node _T_2348 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2348 node _T_2349 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2349 node _T_2350 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2350 node _T_2351 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2351 node _T_2352 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2352 wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, sectored_entries[0][5].data[3] node _T_2353 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2353 node _T_2354 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2354 node _T_2355 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2355 node _T_2356 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2356 node _T_2357 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2357 node _T_2358 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2358 node _T_2359 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2359 node _T_2360 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2360 node _T_2361 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2361 node _T_2362 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2362 node _T_2363 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2363 node _T_2364 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2364 node _T_2365 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2365 node _T_2366 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2366 node _T_2367 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2367 node _T_2368 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2368 node _T_2369 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2369 node _T_2370 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2370 node _T_2371 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2371 node _T_2372 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2372 node _T_2373 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2373 node _T_2374 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2374 node _T_2375 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2375 node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage) when _T_2377 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage) when _T_2379 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage) when _T_2381 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage) when _T_2383 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2384 = eq(hg_5, UInt<1>(0h0)) node _T_2385 = and(_T_2384, io.sfence.bits.rs2) when _T_2385 : wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_177 : UInt<42> connect _WIRE_177, sectored_entries[0][5].data[0] node _T_2386 = bits(_WIRE_177, 0, 0) connect _WIRE_176.fragmented_superpage, _T_2386 node _T_2387 = bits(_WIRE_177, 1, 1) connect _WIRE_176.c, _T_2387 node _T_2388 = bits(_WIRE_177, 2, 2) connect _WIRE_176.eff, _T_2388 node _T_2389 = bits(_WIRE_177, 3, 3) connect _WIRE_176.paa, _T_2389 node _T_2390 = bits(_WIRE_177, 4, 4) connect _WIRE_176.pal, _T_2390 node _T_2391 = bits(_WIRE_177, 5, 5) connect _WIRE_176.ppp, _T_2391 node _T_2392 = bits(_WIRE_177, 6, 6) connect _WIRE_176.pr, _T_2392 node _T_2393 = bits(_WIRE_177, 7, 7) connect _WIRE_176.px, _T_2393 node _T_2394 = bits(_WIRE_177, 8, 8) connect _WIRE_176.pw, _T_2394 node _T_2395 = bits(_WIRE_177, 9, 9) connect _WIRE_176.hr, _T_2395 node _T_2396 = bits(_WIRE_177, 10, 10) connect _WIRE_176.hx, _T_2396 node _T_2397 = bits(_WIRE_177, 11, 11) connect _WIRE_176.hw, _T_2397 node _T_2398 = bits(_WIRE_177, 12, 12) connect _WIRE_176.sr, _T_2398 node _T_2399 = bits(_WIRE_177, 13, 13) connect _WIRE_176.sx, _T_2399 node _T_2400 = bits(_WIRE_177, 14, 14) connect _WIRE_176.sw, _T_2400 node _T_2401 = bits(_WIRE_177, 15, 15) connect _WIRE_176.gf, _T_2401 node _T_2402 = bits(_WIRE_177, 16, 16) connect _WIRE_176.pf, _T_2402 node _T_2403 = bits(_WIRE_177, 17, 17) connect _WIRE_176.ae_stage2, _T_2403 node _T_2404 = bits(_WIRE_177, 18, 18) connect _WIRE_176.ae_final, _T_2404 node _T_2405 = bits(_WIRE_177, 19, 19) connect _WIRE_176.ae_ptw, _T_2405 node _T_2406 = bits(_WIRE_177, 20, 20) connect _WIRE_176.g, _T_2406 node _T_2407 = bits(_WIRE_177, 21, 21) connect _WIRE_176.u, _T_2407 node _T_2408 = bits(_WIRE_177, 41, 22) connect _WIRE_176.ppn, _T_2408 wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_179 : UInt<42> connect _WIRE_179, sectored_entries[0][5].data[1] node _T_2409 = bits(_WIRE_179, 0, 0) connect _WIRE_178.fragmented_superpage, _T_2409 node _T_2410 = bits(_WIRE_179, 1, 1) connect _WIRE_178.c, _T_2410 node _T_2411 = bits(_WIRE_179, 2, 2) connect _WIRE_178.eff, _T_2411 node _T_2412 = bits(_WIRE_179, 3, 3) connect _WIRE_178.paa, _T_2412 node _T_2413 = bits(_WIRE_179, 4, 4) connect _WIRE_178.pal, _T_2413 node _T_2414 = bits(_WIRE_179, 5, 5) connect _WIRE_178.ppp, _T_2414 node _T_2415 = bits(_WIRE_179, 6, 6) connect _WIRE_178.pr, _T_2415 node _T_2416 = bits(_WIRE_179, 7, 7) connect _WIRE_178.px, _T_2416 node _T_2417 = bits(_WIRE_179, 8, 8) connect _WIRE_178.pw, _T_2417 node _T_2418 = bits(_WIRE_179, 9, 9) connect _WIRE_178.hr, _T_2418 node _T_2419 = bits(_WIRE_179, 10, 10) connect _WIRE_178.hx, _T_2419 node _T_2420 = bits(_WIRE_179, 11, 11) connect _WIRE_178.hw, _T_2420 node _T_2421 = bits(_WIRE_179, 12, 12) connect _WIRE_178.sr, _T_2421 node _T_2422 = bits(_WIRE_179, 13, 13) connect _WIRE_178.sx, _T_2422 node _T_2423 = bits(_WIRE_179, 14, 14) connect _WIRE_178.sw, _T_2423 node _T_2424 = bits(_WIRE_179, 15, 15) connect _WIRE_178.gf, _T_2424 node _T_2425 = bits(_WIRE_179, 16, 16) connect _WIRE_178.pf, _T_2425 node _T_2426 = bits(_WIRE_179, 17, 17) connect _WIRE_178.ae_stage2, _T_2426 node _T_2427 = bits(_WIRE_179, 18, 18) connect _WIRE_178.ae_final, _T_2427 node _T_2428 = bits(_WIRE_179, 19, 19) connect _WIRE_178.ae_ptw, _T_2428 node _T_2429 = bits(_WIRE_179, 20, 20) connect _WIRE_178.g, _T_2429 node _T_2430 = bits(_WIRE_179, 21, 21) connect _WIRE_178.u, _T_2430 node _T_2431 = bits(_WIRE_179, 41, 22) connect _WIRE_178.ppn, _T_2431 wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_181 : UInt<42> connect _WIRE_181, sectored_entries[0][5].data[2] node _T_2432 = bits(_WIRE_181, 0, 0) connect _WIRE_180.fragmented_superpage, _T_2432 node _T_2433 = bits(_WIRE_181, 1, 1) connect _WIRE_180.c, _T_2433 node _T_2434 = bits(_WIRE_181, 2, 2) connect _WIRE_180.eff, _T_2434 node _T_2435 = bits(_WIRE_181, 3, 3) connect _WIRE_180.paa, _T_2435 node _T_2436 = bits(_WIRE_181, 4, 4) connect _WIRE_180.pal, _T_2436 node _T_2437 = bits(_WIRE_181, 5, 5) connect _WIRE_180.ppp, _T_2437 node _T_2438 = bits(_WIRE_181, 6, 6) connect _WIRE_180.pr, _T_2438 node _T_2439 = bits(_WIRE_181, 7, 7) connect _WIRE_180.px, _T_2439 node _T_2440 = bits(_WIRE_181, 8, 8) connect _WIRE_180.pw, _T_2440 node _T_2441 = bits(_WIRE_181, 9, 9) connect _WIRE_180.hr, _T_2441 node _T_2442 = bits(_WIRE_181, 10, 10) connect _WIRE_180.hx, _T_2442 node _T_2443 = bits(_WIRE_181, 11, 11) connect _WIRE_180.hw, _T_2443 node _T_2444 = bits(_WIRE_181, 12, 12) connect _WIRE_180.sr, _T_2444 node _T_2445 = bits(_WIRE_181, 13, 13) connect _WIRE_180.sx, _T_2445 node _T_2446 = bits(_WIRE_181, 14, 14) connect _WIRE_180.sw, _T_2446 node _T_2447 = bits(_WIRE_181, 15, 15) connect _WIRE_180.gf, _T_2447 node _T_2448 = bits(_WIRE_181, 16, 16) connect _WIRE_180.pf, _T_2448 node _T_2449 = bits(_WIRE_181, 17, 17) connect _WIRE_180.ae_stage2, _T_2449 node _T_2450 = bits(_WIRE_181, 18, 18) connect _WIRE_180.ae_final, _T_2450 node _T_2451 = bits(_WIRE_181, 19, 19) connect _WIRE_180.ae_ptw, _T_2451 node _T_2452 = bits(_WIRE_181, 20, 20) connect _WIRE_180.g, _T_2452 node _T_2453 = bits(_WIRE_181, 21, 21) connect _WIRE_180.u, _T_2453 node _T_2454 = bits(_WIRE_181, 41, 22) connect _WIRE_180.ppn, _T_2454 wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_183 : UInt<42> connect _WIRE_183, sectored_entries[0][5].data[3] node _T_2455 = bits(_WIRE_183, 0, 0) connect _WIRE_182.fragmented_superpage, _T_2455 node _T_2456 = bits(_WIRE_183, 1, 1) connect _WIRE_182.c, _T_2456 node _T_2457 = bits(_WIRE_183, 2, 2) connect _WIRE_182.eff, _T_2457 node _T_2458 = bits(_WIRE_183, 3, 3) connect _WIRE_182.paa, _T_2458 node _T_2459 = bits(_WIRE_183, 4, 4) connect _WIRE_182.pal, _T_2459 node _T_2460 = bits(_WIRE_183, 5, 5) connect _WIRE_182.ppp, _T_2460 node _T_2461 = bits(_WIRE_183, 6, 6) connect _WIRE_182.pr, _T_2461 node _T_2462 = bits(_WIRE_183, 7, 7) connect _WIRE_182.px, _T_2462 node _T_2463 = bits(_WIRE_183, 8, 8) connect _WIRE_182.pw, _T_2463 node _T_2464 = bits(_WIRE_183, 9, 9) connect _WIRE_182.hr, _T_2464 node _T_2465 = bits(_WIRE_183, 10, 10) connect _WIRE_182.hx, _T_2465 node _T_2466 = bits(_WIRE_183, 11, 11) connect _WIRE_182.hw, _T_2466 node _T_2467 = bits(_WIRE_183, 12, 12) connect _WIRE_182.sr, _T_2467 node _T_2468 = bits(_WIRE_183, 13, 13) connect _WIRE_182.sx, _T_2468 node _T_2469 = bits(_WIRE_183, 14, 14) connect _WIRE_182.sw, _T_2469 node _T_2470 = bits(_WIRE_183, 15, 15) connect _WIRE_182.gf, _T_2470 node _T_2471 = bits(_WIRE_183, 16, 16) connect _WIRE_182.pf, _T_2471 node _T_2472 = bits(_WIRE_183, 17, 17) connect _WIRE_182.ae_stage2, _T_2472 node _T_2473 = bits(_WIRE_183, 18, 18) connect _WIRE_182.ae_final, _T_2473 node _T_2474 = bits(_WIRE_183, 19, 19) connect _WIRE_182.ae_ptw, _T_2474 node _T_2475 = bits(_WIRE_183, 20, 20) connect _WIRE_182.g, _T_2475 node _T_2476 = bits(_WIRE_183, 21, 21) connect _WIRE_182.u, _T_2476 node _T_2477 = bits(_WIRE_183, 41, 22) connect _WIRE_182.ppn, _T_2477 node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0)) node _T_2480 = and(_T_2478, _T_2479) when _T_2480 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0)) node _T_2483 = and(_T_2481, _T_2482) when _T_2483 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5) node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0)) node _T_2489 = and(_T_2487, _T_2488) when _T_2489 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) else : node _T_2490 = or(hv_5, hg_5) wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_185 : UInt<42> connect _WIRE_185, sectored_entries[0][5].data[0] node _T_2491 = bits(_WIRE_185, 0, 0) connect _WIRE_184.fragmented_superpage, _T_2491 node _T_2492 = bits(_WIRE_185, 1, 1) connect _WIRE_184.c, _T_2492 node _T_2493 = bits(_WIRE_185, 2, 2) connect _WIRE_184.eff, _T_2493 node _T_2494 = bits(_WIRE_185, 3, 3) connect _WIRE_184.paa, _T_2494 node _T_2495 = bits(_WIRE_185, 4, 4) connect _WIRE_184.pal, _T_2495 node _T_2496 = bits(_WIRE_185, 5, 5) connect _WIRE_184.ppp, _T_2496 node _T_2497 = bits(_WIRE_185, 6, 6) connect _WIRE_184.pr, _T_2497 node _T_2498 = bits(_WIRE_185, 7, 7) connect _WIRE_184.px, _T_2498 node _T_2499 = bits(_WIRE_185, 8, 8) connect _WIRE_184.pw, _T_2499 node _T_2500 = bits(_WIRE_185, 9, 9) connect _WIRE_184.hr, _T_2500 node _T_2501 = bits(_WIRE_185, 10, 10) connect _WIRE_184.hx, _T_2501 node _T_2502 = bits(_WIRE_185, 11, 11) connect _WIRE_184.hw, _T_2502 node _T_2503 = bits(_WIRE_185, 12, 12) connect _WIRE_184.sr, _T_2503 node _T_2504 = bits(_WIRE_185, 13, 13) connect _WIRE_184.sx, _T_2504 node _T_2505 = bits(_WIRE_185, 14, 14) connect _WIRE_184.sw, _T_2505 node _T_2506 = bits(_WIRE_185, 15, 15) connect _WIRE_184.gf, _T_2506 node _T_2507 = bits(_WIRE_185, 16, 16) connect _WIRE_184.pf, _T_2507 node _T_2508 = bits(_WIRE_185, 17, 17) connect _WIRE_184.ae_stage2, _T_2508 node _T_2509 = bits(_WIRE_185, 18, 18) connect _WIRE_184.ae_final, _T_2509 node _T_2510 = bits(_WIRE_185, 19, 19) connect _WIRE_184.ae_ptw, _T_2510 node _T_2511 = bits(_WIRE_185, 20, 20) connect _WIRE_184.g, _T_2511 node _T_2512 = bits(_WIRE_185, 21, 21) connect _WIRE_184.u, _T_2512 node _T_2513 = bits(_WIRE_185, 41, 22) connect _WIRE_184.ppn, _T_2513 wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_187 : UInt<42> connect _WIRE_187, sectored_entries[0][5].data[1] node _T_2514 = bits(_WIRE_187, 0, 0) connect _WIRE_186.fragmented_superpage, _T_2514 node _T_2515 = bits(_WIRE_187, 1, 1) connect _WIRE_186.c, _T_2515 node _T_2516 = bits(_WIRE_187, 2, 2) connect _WIRE_186.eff, _T_2516 node _T_2517 = bits(_WIRE_187, 3, 3) connect _WIRE_186.paa, _T_2517 node _T_2518 = bits(_WIRE_187, 4, 4) connect _WIRE_186.pal, _T_2518 node _T_2519 = bits(_WIRE_187, 5, 5) connect _WIRE_186.ppp, _T_2519 node _T_2520 = bits(_WIRE_187, 6, 6) connect _WIRE_186.pr, _T_2520 node _T_2521 = bits(_WIRE_187, 7, 7) connect _WIRE_186.px, _T_2521 node _T_2522 = bits(_WIRE_187, 8, 8) connect _WIRE_186.pw, _T_2522 node _T_2523 = bits(_WIRE_187, 9, 9) connect _WIRE_186.hr, _T_2523 node _T_2524 = bits(_WIRE_187, 10, 10) connect _WIRE_186.hx, _T_2524 node _T_2525 = bits(_WIRE_187, 11, 11) connect _WIRE_186.hw, _T_2525 node _T_2526 = bits(_WIRE_187, 12, 12) connect _WIRE_186.sr, _T_2526 node _T_2527 = bits(_WIRE_187, 13, 13) connect _WIRE_186.sx, _T_2527 node _T_2528 = bits(_WIRE_187, 14, 14) connect _WIRE_186.sw, _T_2528 node _T_2529 = bits(_WIRE_187, 15, 15) connect _WIRE_186.gf, _T_2529 node _T_2530 = bits(_WIRE_187, 16, 16) connect _WIRE_186.pf, _T_2530 node _T_2531 = bits(_WIRE_187, 17, 17) connect _WIRE_186.ae_stage2, _T_2531 node _T_2532 = bits(_WIRE_187, 18, 18) connect _WIRE_186.ae_final, _T_2532 node _T_2533 = bits(_WIRE_187, 19, 19) connect _WIRE_186.ae_ptw, _T_2533 node _T_2534 = bits(_WIRE_187, 20, 20) connect _WIRE_186.g, _T_2534 node _T_2535 = bits(_WIRE_187, 21, 21) connect _WIRE_186.u, _T_2535 node _T_2536 = bits(_WIRE_187, 41, 22) connect _WIRE_186.ppn, _T_2536 wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_189 : UInt<42> connect _WIRE_189, sectored_entries[0][5].data[2] node _T_2537 = bits(_WIRE_189, 0, 0) connect _WIRE_188.fragmented_superpage, _T_2537 node _T_2538 = bits(_WIRE_189, 1, 1) connect _WIRE_188.c, _T_2538 node _T_2539 = bits(_WIRE_189, 2, 2) connect _WIRE_188.eff, _T_2539 node _T_2540 = bits(_WIRE_189, 3, 3) connect _WIRE_188.paa, _T_2540 node _T_2541 = bits(_WIRE_189, 4, 4) connect _WIRE_188.pal, _T_2541 node _T_2542 = bits(_WIRE_189, 5, 5) connect _WIRE_188.ppp, _T_2542 node _T_2543 = bits(_WIRE_189, 6, 6) connect _WIRE_188.pr, _T_2543 node _T_2544 = bits(_WIRE_189, 7, 7) connect _WIRE_188.px, _T_2544 node _T_2545 = bits(_WIRE_189, 8, 8) connect _WIRE_188.pw, _T_2545 node _T_2546 = bits(_WIRE_189, 9, 9) connect _WIRE_188.hr, _T_2546 node _T_2547 = bits(_WIRE_189, 10, 10) connect _WIRE_188.hx, _T_2547 node _T_2548 = bits(_WIRE_189, 11, 11) connect _WIRE_188.hw, _T_2548 node _T_2549 = bits(_WIRE_189, 12, 12) connect _WIRE_188.sr, _T_2549 node _T_2550 = bits(_WIRE_189, 13, 13) connect _WIRE_188.sx, _T_2550 node _T_2551 = bits(_WIRE_189, 14, 14) connect _WIRE_188.sw, _T_2551 node _T_2552 = bits(_WIRE_189, 15, 15) connect _WIRE_188.gf, _T_2552 node _T_2553 = bits(_WIRE_189, 16, 16) connect _WIRE_188.pf, _T_2553 node _T_2554 = bits(_WIRE_189, 17, 17) connect _WIRE_188.ae_stage2, _T_2554 node _T_2555 = bits(_WIRE_189, 18, 18) connect _WIRE_188.ae_final, _T_2555 node _T_2556 = bits(_WIRE_189, 19, 19) connect _WIRE_188.ae_ptw, _T_2556 node _T_2557 = bits(_WIRE_189, 20, 20) connect _WIRE_188.g, _T_2557 node _T_2558 = bits(_WIRE_189, 21, 21) connect _WIRE_188.u, _T_2558 node _T_2559 = bits(_WIRE_189, 41, 22) connect _WIRE_188.ppn, _T_2559 wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_191 : UInt<42> connect _WIRE_191, sectored_entries[0][5].data[3] node _T_2560 = bits(_WIRE_191, 0, 0) connect _WIRE_190.fragmented_superpage, _T_2560 node _T_2561 = bits(_WIRE_191, 1, 1) connect _WIRE_190.c, _T_2561 node _T_2562 = bits(_WIRE_191, 2, 2) connect _WIRE_190.eff, _T_2562 node _T_2563 = bits(_WIRE_191, 3, 3) connect _WIRE_190.paa, _T_2563 node _T_2564 = bits(_WIRE_191, 4, 4) connect _WIRE_190.pal, _T_2564 node _T_2565 = bits(_WIRE_191, 5, 5) connect _WIRE_190.ppp, _T_2565 node _T_2566 = bits(_WIRE_191, 6, 6) connect _WIRE_190.pr, _T_2566 node _T_2567 = bits(_WIRE_191, 7, 7) connect _WIRE_190.px, _T_2567 node _T_2568 = bits(_WIRE_191, 8, 8) connect _WIRE_190.pw, _T_2568 node _T_2569 = bits(_WIRE_191, 9, 9) connect _WIRE_190.hr, _T_2569 node _T_2570 = bits(_WIRE_191, 10, 10) connect _WIRE_190.hx, _T_2570 node _T_2571 = bits(_WIRE_191, 11, 11) connect _WIRE_190.hw, _T_2571 node _T_2572 = bits(_WIRE_191, 12, 12) connect _WIRE_190.sr, _T_2572 node _T_2573 = bits(_WIRE_191, 13, 13) connect _WIRE_190.sx, _T_2573 node _T_2574 = bits(_WIRE_191, 14, 14) connect _WIRE_190.sw, _T_2574 node _T_2575 = bits(_WIRE_191, 15, 15) connect _WIRE_190.gf, _T_2575 node _T_2576 = bits(_WIRE_191, 16, 16) connect _WIRE_190.pf, _T_2576 node _T_2577 = bits(_WIRE_191, 17, 17) connect _WIRE_190.ae_stage2, _T_2577 node _T_2578 = bits(_WIRE_191, 18, 18) connect _WIRE_190.ae_final, _T_2578 node _T_2579 = bits(_WIRE_191, 19, 19) connect _WIRE_190.ae_ptw, _T_2579 node _T_2580 = bits(_WIRE_191, 20, 20) connect _WIRE_190.g, _T_2580 node _T_2581 = bits(_WIRE_191, 21, 21) connect _WIRE_190.u, _T_2581 node _T_2582 = bits(_WIRE_191, 41, 22) connect _WIRE_190.ppn, _T_2582 node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2583 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2584 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2585 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490) when _T_2586 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_2587 = eq(hg_6, UInt<1>(0h0)) node _T_2588 = and(_T_2587, io.sfence.bits.rs1) when _T_2588 : node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2590 = shr(_T_2589, 2) node _T_2591 = eq(_T_2590, UInt<1>(0h0)) node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2593 = and(_T_2591, _T_2592) when _T_2593 : wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_193 : UInt<42> connect _WIRE_193, sectored_entries[0][6].data[0] node _T_2594 = bits(_WIRE_193, 0, 0) connect _WIRE_192.fragmented_superpage, _T_2594 node _T_2595 = bits(_WIRE_193, 1, 1) connect _WIRE_192.c, _T_2595 node _T_2596 = bits(_WIRE_193, 2, 2) connect _WIRE_192.eff, _T_2596 node _T_2597 = bits(_WIRE_193, 3, 3) connect _WIRE_192.paa, _T_2597 node _T_2598 = bits(_WIRE_193, 4, 4) connect _WIRE_192.pal, _T_2598 node _T_2599 = bits(_WIRE_193, 5, 5) connect _WIRE_192.ppp, _T_2599 node _T_2600 = bits(_WIRE_193, 6, 6) connect _WIRE_192.pr, _T_2600 node _T_2601 = bits(_WIRE_193, 7, 7) connect _WIRE_192.px, _T_2601 node _T_2602 = bits(_WIRE_193, 8, 8) connect _WIRE_192.pw, _T_2602 node _T_2603 = bits(_WIRE_193, 9, 9) connect _WIRE_192.hr, _T_2603 node _T_2604 = bits(_WIRE_193, 10, 10) connect _WIRE_192.hx, _T_2604 node _T_2605 = bits(_WIRE_193, 11, 11) connect _WIRE_192.hw, _T_2605 node _T_2606 = bits(_WIRE_193, 12, 12) connect _WIRE_192.sr, _T_2606 node _T_2607 = bits(_WIRE_193, 13, 13) connect _WIRE_192.sx, _T_2607 node _T_2608 = bits(_WIRE_193, 14, 14) connect _WIRE_192.sw, _T_2608 node _T_2609 = bits(_WIRE_193, 15, 15) connect _WIRE_192.gf, _T_2609 node _T_2610 = bits(_WIRE_193, 16, 16) connect _WIRE_192.pf, _T_2610 node _T_2611 = bits(_WIRE_193, 17, 17) connect _WIRE_192.ae_stage2, _T_2611 node _T_2612 = bits(_WIRE_193, 18, 18) connect _WIRE_192.ae_final, _T_2612 node _T_2613 = bits(_WIRE_193, 19, 19) connect _WIRE_192.ae_ptw, _T_2613 node _T_2614 = bits(_WIRE_193, 20, 20) connect _WIRE_192.g, _T_2614 node _T_2615 = bits(_WIRE_193, 21, 21) connect _WIRE_192.u, _T_2615 node _T_2616 = bits(_WIRE_193, 41, 22) connect _WIRE_192.ppn, _T_2616 wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_195 : UInt<42> connect _WIRE_195, sectored_entries[0][6].data[1] node _T_2617 = bits(_WIRE_195, 0, 0) connect _WIRE_194.fragmented_superpage, _T_2617 node _T_2618 = bits(_WIRE_195, 1, 1) connect _WIRE_194.c, _T_2618 node _T_2619 = bits(_WIRE_195, 2, 2) connect _WIRE_194.eff, _T_2619 node _T_2620 = bits(_WIRE_195, 3, 3) connect _WIRE_194.paa, _T_2620 node _T_2621 = bits(_WIRE_195, 4, 4) connect _WIRE_194.pal, _T_2621 node _T_2622 = bits(_WIRE_195, 5, 5) connect _WIRE_194.ppp, _T_2622 node _T_2623 = bits(_WIRE_195, 6, 6) connect _WIRE_194.pr, _T_2623 node _T_2624 = bits(_WIRE_195, 7, 7) connect _WIRE_194.px, _T_2624 node _T_2625 = bits(_WIRE_195, 8, 8) connect _WIRE_194.pw, _T_2625 node _T_2626 = bits(_WIRE_195, 9, 9) connect _WIRE_194.hr, _T_2626 node _T_2627 = bits(_WIRE_195, 10, 10) connect _WIRE_194.hx, _T_2627 node _T_2628 = bits(_WIRE_195, 11, 11) connect _WIRE_194.hw, _T_2628 node _T_2629 = bits(_WIRE_195, 12, 12) connect _WIRE_194.sr, _T_2629 node _T_2630 = bits(_WIRE_195, 13, 13) connect _WIRE_194.sx, _T_2630 node _T_2631 = bits(_WIRE_195, 14, 14) connect _WIRE_194.sw, _T_2631 node _T_2632 = bits(_WIRE_195, 15, 15) connect _WIRE_194.gf, _T_2632 node _T_2633 = bits(_WIRE_195, 16, 16) connect _WIRE_194.pf, _T_2633 node _T_2634 = bits(_WIRE_195, 17, 17) connect _WIRE_194.ae_stage2, _T_2634 node _T_2635 = bits(_WIRE_195, 18, 18) connect _WIRE_194.ae_final, _T_2635 node _T_2636 = bits(_WIRE_195, 19, 19) connect _WIRE_194.ae_ptw, _T_2636 node _T_2637 = bits(_WIRE_195, 20, 20) connect _WIRE_194.g, _T_2637 node _T_2638 = bits(_WIRE_195, 21, 21) connect _WIRE_194.u, _T_2638 node _T_2639 = bits(_WIRE_195, 41, 22) connect _WIRE_194.ppn, _T_2639 wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_197 : UInt<42> connect _WIRE_197, sectored_entries[0][6].data[2] node _T_2640 = bits(_WIRE_197, 0, 0) connect _WIRE_196.fragmented_superpage, _T_2640 node _T_2641 = bits(_WIRE_197, 1, 1) connect _WIRE_196.c, _T_2641 node _T_2642 = bits(_WIRE_197, 2, 2) connect _WIRE_196.eff, _T_2642 node _T_2643 = bits(_WIRE_197, 3, 3) connect _WIRE_196.paa, _T_2643 node _T_2644 = bits(_WIRE_197, 4, 4) connect _WIRE_196.pal, _T_2644 node _T_2645 = bits(_WIRE_197, 5, 5) connect _WIRE_196.ppp, _T_2645 node _T_2646 = bits(_WIRE_197, 6, 6) connect _WIRE_196.pr, _T_2646 node _T_2647 = bits(_WIRE_197, 7, 7) connect _WIRE_196.px, _T_2647 node _T_2648 = bits(_WIRE_197, 8, 8) connect _WIRE_196.pw, _T_2648 node _T_2649 = bits(_WIRE_197, 9, 9) connect _WIRE_196.hr, _T_2649 node _T_2650 = bits(_WIRE_197, 10, 10) connect _WIRE_196.hx, _T_2650 node _T_2651 = bits(_WIRE_197, 11, 11) connect _WIRE_196.hw, _T_2651 node _T_2652 = bits(_WIRE_197, 12, 12) connect _WIRE_196.sr, _T_2652 node _T_2653 = bits(_WIRE_197, 13, 13) connect _WIRE_196.sx, _T_2653 node _T_2654 = bits(_WIRE_197, 14, 14) connect _WIRE_196.sw, _T_2654 node _T_2655 = bits(_WIRE_197, 15, 15) connect _WIRE_196.gf, _T_2655 node _T_2656 = bits(_WIRE_197, 16, 16) connect _WIRE_196.pf, _T_2656 node _T_2657 = bits(_WIRE_197, 17, 17) connect _WIRE_196.ae_stage2, _T_2657 node _T_2658 = bits(_WIRE_197, 18, 18) connect _WIRE_196.ae_final, _T_2658 node _T_2659 = bits(_WIRE_197, 19, 19) connect _WIRE_196.ae_ptw, _T_2659 node _T_2660 = bits(_WIRE_197, 20, 20) connect _WIRE_196.g, _T_2660 node _T_2661 = bits(_WIRE_197, 21, 21) connect _WIRE_196.u, _T_2661 node _T_2662 = bits(_WIRE_197, 41, 22) connect _WIRE_196.ppn, _T_2662 wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_199 : UInt<42> connect _WIRE_199, sectored_entries[0][6].data[3] node _T_2663 = bits(_WIRE_199, 0, 0) connect _WIRE_198.fragmented_superpage, _T_2663 node _T_2664 = bits(_WIRE_199, 1, 1) connect _WIRE_198.c, _T_2664 node _T_2665 = bits(_WIRE_199, 2, 2) connect _WIRE_198.eff, _T_2665 node _T_2666 = bits(_WIRE_199, 3, 3) connect _WIRE_198.paa, _T_2666 node _T_2667 = bits(_WIRE_199, 4, 4) connect _WIRE_198.pal, _T_2667 node _T_2668 = bits(_WIRE_199, 5, 5) connect _WIRE_198.ppp, _T_2668 node _T_2669 = bits(_WIRE_199, 6, 6) connect _WIRE_198.pr, _T_2669 node _T_2670 = bits(_WIRE_199, 7, 7) connect _WIRE_198.px, _T_2670 node _T_2671 = bits(_WIRE_199, 8, 8) connect _WIRE_198.pw, _T_2671 node _T_2672 = bits(_WIRE_199, 9, 9) connect _WIRE_198.hr, _T_2672 node _T_2673 = bits(_WIRE_199, 10, 10) connect _WIRE_198.hx, _T_2673 node _T_2674 = bits(_WIRE_199, 11, 11) connect _WIRE_198.hw, _T_2674 node _T_2675 = bits(_WIRE_199, 12, 12) connect _WIRE_198.sr, _T_2675 node _T_2676 = bits(_WIRE_199, 13, 13) connect _WIRE_198.sx, _T_2676 node _T_2677 = bits(_WIRE_199, 14, 14) connect _WIRE_198.sw, _T_2677 node _T_2678 = bits(_WIRE_199, 15, 15) connect _WIRE_198.gf, _T_2678 node _T_2679 = bits(_WIRE_199, 16, 16) connect _WIRE_198.pf, _T_2679 node _T_2680 = bits(_WIRE_199, 17, 17) connect _WIRE_198.ae_stage2, _T_2680 node _T_2681 = bits(_WIRE_199, 18, 18) connect _WIRE_198.ae_final, _T_2681 node _T_2682 = bits(_WIRE_199, 19, 19) connect _WIRE_198.ae_ptw, _T_2682 node _T_2683 = bits(_WIRE_199, 20, 20) connect _WIRE_198.g, _T_2683 node _T_2684 = bits(_WIRE_199, 21, 21) connect _WIRE_198.u, _T_2684 node _T_2685 = bits(_WIRE_199, 41, 22) connect _WIRE_198.ppn, _T_2685 node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2687 = bits(vpn, 1, 0) node _T_2688 = eq(UInt<1>(0h0), _T_2687) node _T_2689 = and(_T_2686, _T_2688) when _T_2689 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2691 = bits(vpn, 1, 0) node _T_2692 = eq(UInt<1>(0h1), _T_2691) node _T_2693 = and(_T_2690, _T_2692) when _T_2693 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2695 = bits(vpn, 1, 0) node _T_2696 = eq(UInt<2>(0h2), _T_2695) node _T_2697 = and(_T_2694, _T_2696) when _T_2697 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2699 = bits(vpn, 1, 0) node _T_2700 = eq(UInt<2>(0h3), _T_2699) node _T_2701 = and(_T_2698, _T_2700) when _T_2701 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn) node _T_2703 = shr(_T_2702, 18) node _T_2704 = eq(_T_2703, UInt<1>(0h0)) when _T_2704 : wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_201 : UInt<42> connect _WIRE_201, sectored_entries[0][6].data[0] node _T_2705 = bits(_WIRE_201, 0, 0) connect _WIRE_200.fragmented_superpage, _T_2705 node _T_2706 = bits(_WIRE_201, 1, 1) connect _WIRE_200.c, _T_2706 node _T_2707 = bits(_WIRE_201, 2, 2) connect _WIRE_200.eff, _T_2707 node _T_2708 = bits(_WIRE_201, 3, 3) connect _WIRE_200.paa, _T_2708 node _T_2709 = bits(_WIRE_201, 4, 4) connect _WIRE_200.pal, _T_2709 node _T_2710 = bits(_WIRE_201, 5, 5) connect _WIRE_200.ppp, _T_2710 node _T_2711 = bits(_WIRE_201, 6, 6) connect _WIRE_200.pr, _T_2711 node _T_2712 = bits(_WIRE_201, 7, 7) connect _WIRE_200.px, _T_2712 node _T_2713 = bits(_WIRE_201, 8, 8) connect _WIRE_200.pw, _T_2713 node _T_2714 = bits(_WIRE_201, 9, 9) connect _WIRE_200.hr, _T_2714 node _T_2715 = bits(_WIRE_201, 10, 10) connect _WIRE_200.hx, _T_2715 node _T_2716 = bits(_WIRE_201, 11, 11) connect _WIRE_200.hw, _T_2716 node _T_2717 = bits(_WIRE_201, 12, 12) connect _WIRE_200.sr, _T_2717 node _T_2718 = bits(_WIRE_201, 13, 13) connect _WIRE_200.sx, _T_2718 node _T_2719 = bits(_WIRE_201, 14, 14) connect _WIRE_200.sw, _T_2719 node _T_2720 = bits(_WIRE_201, 15, 15) connect _WIRE_200.gf, _T_2720 node _T_2721 = bits(_WIRE_201, 16, 16) connect _WIRE_200.pf, _T_2721 node _T_2722 = bits(_WIRE_201, 17, 17) connect _WIRE_200.ae_stage2, _T_2722 node _T_2723 = bits(_WIRE_201, 18, 18) connect _WIRE_200.ae_final, _T_2723 node _T_2724 = bits(_WIRE_201, 19, 19) connect _WIRE_200.ae_ptw, _T_2724 node _T_2725 = bits(_WIRE_201, 20, 20) connect _WIRE_200.g, _T_2725 node _T_2726 = bits(_WIRE_201, 21, 21) connect _WIRE_200.u, _T_2726 node _T_2727 = bits(_WIRE_201, 41, 22) connect _WIRE_200.ppn, _T_2727 wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_203 : UInt<42> connect _WIRE_203, sectored_entries[0][6].data[1] node _T_2728 = bits(_WIRE_203, 0, 0) connect _WIRE_202.fragmented_superpage, _T_2728 node _T_2729 = bits(_WIRE_203, 1, 1) connect _WIRE_202.c, _T_2729 node _T_2730 = bits(_WIRE_203, 2, 2) connect _WIRE_202.eff, _T_2730 node _T_2731 = bits(_WIRE_203, 3, 3) connect _WIRE_202.paa, _T_2731 node _T_2732 = bits(_WIRE_203, 4, 4) connect _WIRE_202.pal, _T_2732 node _T_2733 = bits(_WIRE_203, 5, 5) connect _WIRE_202.ppp, _T_2733 node _T_2734 = bits(_WIRE_203, 6, 6) connect _WIRE_202.pr, _T_2734 node _T_2735 = bits(_WIRE_203, 7, 7) connect _WIRE_202.px, _T_2735 node _T_2736 = bits(_WIRE_203, 8, 8) connect _WIRE_202.pw, _T_2736 node _T_2737 = bits(_WIRE_203, 9, 9) connect _WIRE_202.hr, _T_2737 node _T_2738 = bits(_WIRE_203, 10, 10) connect _WIRE_202.hx, _T_2738 node _T_2739 = bits(_WIRE_203, 11, 11) connect _WIRE_202.hw, _T_2739 node _T_2740 = bits(_WIRE_203, 12, 12) connect _WIRE_202.sr, _T_2740 node _T_2741 = bits(_WIRE_203, 13, 13) connect _WIRE_202.sx, _T_2741 node _T_2742 = bits(_WIRE_203, 14, 14) connect _WIRE_202.sw, _T_2742 node _T_2743 = bits(_WIRE_203, 15, 15) connect _WIRE_202.gf, _T_2743 node _T_2744 = bits(_WIRE_203, 16, 16) connect _WIRE_202.pf, _T_2744 node _T_2745 = bits(_WIRE_203, 17, 17) connect _WIRE_202.ae_stage2, _T_2745 node _T_2746 = bits(_WIRE_203, 18, 18) connect _WIRE_202.ae_final, _T_2746 node _T_2747 = bits(_WIRE_203, 19, 19) connect _WIRE_202.ae_ptw, _T_2747 node _T_2748 = bits(_WIRE_203, 20, 20) connect _WIRE_202.g, _T_2748 node _T_2749 = bits(_WIRE_203, 21, 21) connect _WIRE_202.u, _T_2749 node _T_2750 = bits(_WIRE_203, 41, 22) connect _WIRE_202.ppn, _T_2750 wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_205 : UInt<42> connect _WIRE_205, sectored_entries[0][6].data[2] node _T_2751 = bits(_WIRE_205, 0, 0) connect _WIRE_204.fragmented_superpage, _T_2751 node _T_2752 = bits(_WIRE_205, 1, 1) connect _WIRE_204.c, _T_2752 node _T_2753 = bits(_WIRE_205, 2, 2) connect _WIRE_204.eff, _T_2753 node _T_2754 = bits(_WIRE_205, 3, 3) connect _WIRE_204.paa, _T_2754 node _T_2755 = bits(_WIRE_205, 4, 4) connect _WIRE_204.pal, _T_2755 node _T_2756 = bits(_WIRE_205, 5, 5) connect _WIRE_204.ppp, _T_2756 node _T_2757 = bits(_WIRE_205, 6, 6) connect _WIRE_204.pr, _T_2757 node _T_2758 = bits(_WIRE_205, 7, 7) connect _WIRE_204.px, _T_2758 node _T_2759 = bits(_WIRE_205, 8, 8) connect _WIRE_204.pw, _T_2759 node _T_2760 = bits(_WIRE_205, 9, 9) connect _WIRE_204.hr, _T_2760 node _T_2761 = bits(_WIRE_205, 10, 10) connect _WIRE_204.hx, _T_2761 node _T_2762 = bits(_WIRE_205, 11, 11) connect _WIRE_204.hw, _T_2762 node _T_2763 = bits(_WIRE_205, 12, 12) connect _WIRE_204.sr, _T_2763 node _T_2764 = bits(_WIRE_205, 13, 13) connect _WIRE_204.sx, _T_2764 node _T_2765 = bits(_WIRE_205, 14, 14) connect _WIRE_204.sw, _T_2765 node _T_2766 = bits(_WIRE_205, 15, 15) connect _WIRE_204.gf, _T_2766 node _T_2767 = bits(_WIRE_205, 16, 16) connect _WIRE_204.pf, _T_2767 node _T_2768 = bits(_WIRE_205, 17, 17) connect _WIRE_204.ae_stage2, _T_2768 node _T_2769 = bits(_WIRE_205, 18, 18) connect _WIRE_204.ae_final, _T_2769 node _T_2770 = bits(_WIRE_205, 19, 19) connect _WIRE_204.ae_ptw, _T_2770 node _T_2771 = bits(_WIRE_205, 20, 20) connect _WIRE_204.g, _T_2771 node _T_2772 = bits(_WIRE_205, 21, 21) connect _WIRE_204.u, _T_2772 node _T_2773 = bits(_WIRE_205, 41, 22) connect _WIRE_204.ppn, _T_2773 wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_207 : UInt<42> connect _WIRE_207, sectored_entries[0][6].data[3] node _T_2774 = bits(_WIRE_207, 0, 0) connect _WIRE_206.fragmented_superpage, _T_2774 node _T_2775 = bits(_WIRE_207, 1, 1) connect _WIRE_206.c, _T_2775 node _T_2776 = bits(_WIRE_207, 2, 2) connect _WIRE_206.eff, _T_2776 node _T_2777 = bits(_WIRE_207, 3, 3) connect _WIRE_206.paa, _T_2777 node _T_2778 = bits(_WIRE_207, 4, 4) connect _WIRE_206.pal, _T_2778 node _T_2779 = bits(_WIRE_207, 5, 5) connect _WIRE_206.ppp, _T_2779 node _T_2780 = bits(_WIRE_207, 6, 6) connect _WIRE_206.pr, _T_2780 node _T_2781 = bits(_WIRE_207, 7, 7) connect _WIRE_206.px, _T_2781 node _T_2782 = bits(_WIRE_207, 8, 8) connect _WIRE_206.pw, _T_2782 node _T_2783 = bits(_WIRE_207, 9, 9) connect _WIRE_206.hr, _T_2783 node _T_2784 = bits(_WIRE_207, 10, 10) connect _WIRE_206.hx, _T_2784 node _T_2785 = bits(_WIRE_207, 11, 11) connect _WIRE_206.hw, _T_2785 node _T_2786 = bits(_WIRE_207, 12, 12) connect _WIRE_206.sr, _T_2786 node _T_2787 = bits(_WIRE_207, 13, 13) connect _WIRE_206.sx, _T_2787 node _T_2788 = bits(_WIRE_207, 14, 14) connect _WIRE_206.sw, _T_2788 node _T_2789 = bits(_WIRE_207, 15, 15) connect _WIRE_206.gf, _T_2789 node _T_2790 = bits(_WIRE_207, 16, 16) connect _WIRE_206.pf, _T_2790 node _T_2791 = bits(_WIRE_207, 17, 17) connect _WIRE_206.ae_stage2, _T_2791 node _T_2792 = bits(_WIRE_207, 18, 18) connect _WIRE_206.ae_final, _T_2792 node _T_2793 = bits(_WIRE_207, 19, 19) connect _WIRE_206.ae_ptw, _T_2793 node _T_2794 = bits(_WIRE_207, 20, 20) connect _WIRE_206.g, _T_2794 node _T_2795 = bits(_WIRE_207, 21, 21) connect _WIRE_206.u, _T_2795 node _T_2796 = bits(_WIRE_207, 41, 22) connect _WIRE_206.ppn, _T_2796 node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage) when _T_2798 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage) when _T_2800 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage) when _T_2802 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage) when _T_2804 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2805 = eq(hg_6, UInt<1>(0h0)) node _T_2806 = and(_T_2805, io.sfence.bits.rs2) when _T_2806 : wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_209 : UInt<42> connect _WIRE_209, sectored_entries[0][6].data[0] node _T_2807 = bits(_WIRE_209, 0, 0) connect _WIRE_208.fragmented_superpage, _T_2807 node _T_2808 = bits(_WIRE_209, 1, 1) connect _WIRE_208.c, _T_2808 node _T_2809 = bits(_WIRE_209, 2, 2) connect _WIRE_208.eff, _T_2809 node _T_2810 = bits(_WIRE_209, 3, 3) connect _WIRE_208.paa, _T_2810 node _T_2811 = bits(_WIRE_209, 4, 4) connect _WIRE_208.pal, _T_2811 node _T_2812 = bits(_WIRE_209, 5, 5) connect _WIRE_208.ppp, _T_2812 node _T_2813 = bits(_WIRE_209, 6, 6) connect _WIRE_208.pr, _T_2813 node _T_2814 = bits(_WIRE_209, 7, 7) connect _WIRE_208.px, _T_2814 node _T_2815 = bits(_WIRE_209, 8, 8) connect _WIRE_208.pw, _T_2815 node _T_2816 = bits(_WIRE_209, 9, 9) connect _WIRE_208.hr, _T_2816 node _T_2817 = bits(_WIRE_209, 10, 10) connect _WIRE_208.hx, _T_2817 node _T_2818 = bits(_WIRE_209, 11, 11) connect _WIRE_208.hw, _T_2818 node _T_2819 = bits(_WIRE_209, 12, 12) connect _WIRE_208.sr, _T_2819 node _T_2820 = bits(_WIRE_209, 13, 13) connect _WIRE_208.sx, _T_2820 node _T_2821 = bits(_WIRE_209, 14, 14) connect _WIRE_208.sw, _T_2821 node _T_2822 = bits(_WIRE_209, 15, 15) connect _WIRE_208.gf, _T_2822 node _T_2823 = bits(_WIRE_209, 16, 16) connect _WIRE_208.pf, _T_2823 node _T_2824 = bits(_WIRE_209, 17, 17) connect _WIRE_208.ae_stage2, _T_2824 node _T_2825 = bits(_WIRE_209, 18, 18) connect _WIRE_208.ae_final, _T_2825 node _T_2826 = bits(_WIRE_209, 19, 19) connect _WIRE_208.ae_ptw, _T_2826 node _T_2827 = bits(_WIRE_209, 20, 20) connect _WIRE_208.g, _T_2827 node _T_2828 = bits(_WIRE_209, 21, 21) connect _WIRE_208.u, _T_2828 node _T_2829 = bits(_WIRE_209, 41, 22) connect _WIRE_208.ppn, _T_2829 wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_211 : UInt<42> connect _WIRE_211, sectored_entries[0][6].data[1] node _T_2830 = bits(_WIRE_211, 0, 0) connect _WIRE_210.fragmented_superpage, _T_2830 node _T_2831 = bits(_WIRE_211, 1, 1) connect _WIRE_210.c, _T_2831 node _T_2832 = bits(_WIRE_211, 2, 2) connect _WIRE_210.eff, _T_2832 node _T_2833 = bits(_WIRE_211, 3, 3) connect _WIRE_210.paa, _T_2833 node _T_2834 = bits(_WIRE_211, 4, 4) connect _WIRE_210.pal, _T_2834 node _T_2835 = bits(_WIRE_211, 5, 5) connect _WIRE_210.ppp, _T_2835 node _T_2836 = bits(_WIRE_211, 6, 6) connect _WIRE_210.pr, _T_2836 node _T_2837 = bits(_WIRE_211, 7, 7) connect _WIRE_210.px, _T_2837 node _T_2838 = bits(_WIRE_211, 8, 8) connect _WIRE_210.pw, _T_2838 node _T_2839 = bits(_WIRE_211, 9, 9) connect _WIRE_210.hr, _T_2839 node _T_2840 = bits(_WIRE_211, 10, 10) connect _WIRE_210.hx, _T_2840 node _T_2841 = bits(_WIRE_211, 11, 11) connect _WIRE_210.hw, _T_2841 node _T_2842 = bits(_WIRE_211, 12, 12) connect _WIRE_210.sr, _T_2842 node _T_2843 = bits(_WIRE_211, 13, 13) connect _WIRE_210.sx, _T_2843 node _T_2844 = bits(_WIRE_211, 14, 14) connect _WIRE_210.sw, _T_2844 node _T_2845 = bits(_WIRE_211, 15, 15) connect _WIRE_210.gf, _T_2845 node _T_2846 = bits(_WIRE_211, 16, 16) connect _WIRE_210.pf, _T_2846 node _T_2847 = bits(_WIRE_211, 17, 17) connect _WIRE_210.ae_stage2, _T_2847 node _T_2848 = bits(_WIRE_211, 18, 18) connect _WIRE_210.ae_final, _T_2848 node _T_2849 = bits(_WIRE_211, 19, 19) connect _WIRE_210.ae_ptw, _T_2849 node _T_2850 = bits(_WIRE_211, 20, 20) connect _WIRE_210.g, _T_2850 node _T_2851 = bits(_WIRE_211, 21, 21) connect _WIRE_210.u, _T_2851 node _T_2852 = bits(_WIRE_211, 41, 22) connect _WIRE_210.ppn, _T_2852 wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_213 : UInt<42> connect _WIRE_213, sectored_entries[0][6].data[2] node _T_2853 = bits(_WIRE_213, 0, 0) connect _WIRE_212.fragmented_superpage, _T_2853 node _T_2854 = bits(_WIRE_213, 1, 1) connect _WIRE_212.c, _T_2854 node _T_2855 = bits(_WIRE_213, 2, 2) connect _WIRE_212.eff, _T_2855 node _T_2856 = bits(_WIRE_213, 3, 3) connect _WIRE_212.paa, _T_2856 node _T_2857 = bits(_WIRE_213, 4, 4) connect _WIRE_212.pal, _T_2857 node _T_2858 = bits(_WIRE_213, 5, 5) connect _WIRE_212.ppp, _T_2858 node _T_2859 = bits(_WIRE_213, 6, 6) connect _WIRE_212.pr, _T_2859 node _T_2860 = bits(_WIRE_213, 7, 7) connect _WIRE_212.px, _T_2860 node _T_2861 = bits(_WIRE_213, 8, 8) connect _WIRE_212.pw, _T_2861 node _T_2862 = bits(_WIRE_213, 9, 9) connect _WIRE_212.hr, _T_2862 node _T_2863 = bits(_WIRE_213, 10, 10) connect _WIRE_212.hx, _T_2863 node _T_2864 = bits(_WIRE_213, 11, 11) connect _WIRE_212.hw, _T_2864 node _T_2865 = bits(_WIRE_213, 12, 12) connect _WIRE_212.sr, _T_2865 node _T_2866 = bits(_WIRE_213, 13, 13) connect _WIRE_212.sx, _T_2866 node _T_2867 = bits(_WIRE_213, 14, 14) connect _WIRE_212.sw, _T_2867 node _T_2868 = bits(_WIRE_213, 15, 15) connect _WIRE_212.gf, _T_2868 node _T_2869 = bits(_WIRE_213, 16, 16) connect _WIRE_212.pf, _T_2869 node _T_2870 = bits(_WIRE_213, 17, 17) connect _WIRE_212.ae_stage2, _T_2870 node _T_2871 = bits(_WIRE_213, 18, 18) connect _WIRE_212.ae_final, _T_2871 node _T_2872 = bits(_WIRE_213, 19, 19) connect _WIRE_212.ae_ptw, _T_2872 node _T_2873 = bits(_WIRE_213, 20, 20) connect _WIRE_212.g, _T_2873 node _T_2874 = bits(_WIRE_213, 21, 21) connect _WIRE_212.u, _T_2874 node _T_2875 = bits(_WIRE_213, 41, 22) connect _WIRE_212.ppn, _T_2875 wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_215 : UInt<42> connect _WIRE_215, sectored_entries[0][6].data[3] node _T_2876 = bits(_WIRE_215, 0, 0) connect _WIRE_214.fragmented_superpage, _T_2876 node _T_2877 = bits(_WIRE_215, 1, 1) connect _WIRE_214.c, _T_2877 node _T_2878 = bits(_WIRE_215, 2, 2) connect _WIRE_214.eff, _T_2878 node _T_2879 = bits(_WIRE_215, 3, 3) connect _WIRE_214.paa, _T_2879 node _T_2880 = bits(_WIRE_215, 4, 4) connect _WIRE_214.pal, _T_2880 node _T_2881 = bits(_WIRE_215, 5, 5) connect _WIRE_214.ppp, _T_2881 node _T_2882 = bits(_WIRE_215, 6, 6) connect _WIRE_214.pr, _T_2882 node _T_2883 = bits(_WIRE_215, 7, 7) connect _WIRE_214.px, _T_2883 node _T_2884 = bits(_WIRE_215, 8, 8) connect _WIRE_214.pw, _T_2884 node _T_2885 = bits(_WIRE_215, 9, 9) connect _WIRE_214.hr, _T_2885 node _T_2886 = bits(_WIRE_215, 10, 10) connect _WIRE_214.hx, _T_2886 node _T_2887 = bits(_WIRE_215, 11, 11) connect _WIRE_214.hw, _T_2887 node _T_2888 = bits(_WIRE_215, 12, 12) connect _WIRE_214.sr, _T_2888 node _T_2889 = bits(_WIRE_215, 13, 13) connect _WIRE_214.sx, _T_2889 node _T_2890 = bits(_WIRE_215, 14, 14) connect _WIRE_214.sw, _T_2890 node _T_2891 = bits(_WIRE_215, 15, 15) connect _WIRE_214.gf, _T_2891 node _T_2892 = bits(_WIRE_215, 16, 16) connect _WIRE_214.pf, _T_2892 node _T_2893 = bits(_WIRE_215, 17, 17) connect _WIRE_214.ae_stage2, _T_2893 node _T_2894 = bits(_WIRE_215, 18, 18) connect _WIRE_214.ae_final, _T_2894 node _T_2895 = bits(_WIRE_215, 19, 19) connect _WIRE_214.ae_ptw, _T_2895 node _T_2896 = bits(_WIRE_215, 20, 20) connect _WIRE_214.g, _T_2896 node _T_2897 = bits(_WIRE_215, 21, 21) connect _WIRE_214.u, _T_2897 node _T_2898 = bits(_WIRE_215, 41, 22) connect _WIRE_214.ppn, _T_2898 node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0)) node _T_2901 = and(_T_2899, _T_2900) when _T_2901 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0)) node _T_2904 = and(_T_2902, _T_2903) when _T_2904 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0)) node _T_2907 = and(_T_2905, _T_2906) when _T_2907 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6) node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0)) node _T_2910 = and(_T_2908, _T_2909) when _T_2910 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) else : node _T_2911 = or(hv_6, hg_6) wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_217 : UInt<42> connect _WIRE_217, sectored_entries[0][6].data[0] node _T_2912 = bits(_WIRE_217, 0, 0) connect _WIRE_216.fragmented_superpage, _T_2912 node _T_2913 = bits(_WIRE_217, 1, 1) connect _WIRE_216.c, _T_2913 node _T_2914 = bits(_WIRE_217, 2, 2) connect _WIRE_216.eff, _T_2914 node _T_2915 = bits(_WIRE_217, 3, 3) connect _WIRE_216.paa, _T_2915 node _T_2916 = bits(_WIRE_217, 4, 4) connect _WIRE_216.pal, _T_2916 node _T_2917 = bits(_WIRE_217, 5, 5) connect _WIRE_216.ppp, _T_2917 node _T_2918 = bits(_WIRE_217, 6, 6) connect _WIRE_216.pr, _T_2918 node _T_2919 = bits(_WIRE_217, 7, 7) connect _WIRE_216.px, _T_2919 node _T_2920 = bits(_WIRE_217, 8, 8) connect _WIRE_216.pw, _T_2920 node _T_2921 = bits(_WIRE_217, 9, 9) connect _WIRE_216.hr, _T_2921 node _T_2922 = bits(_WIRE_217, 10, 10) connect _WIRE_216.hx, _T_2922 node _T_2923 = bits(_WIRE_217, 11, 11) connect _WIRE_216.hw, _T_2923 node _T_2924 = bits(_WIRE_217, 12, 12) connect _WIRE_216.sr, _T_2924 node _T_2925 = bits(_WIRE_217, 13, 13) connect _WIRE_216.sx, _T_2925 node _T_2926 = bits(_WIRE_217, 14, 14) connect _WIRE_216.sw, _T_2926 node _T_2927 = bits(_WIRE_217, 15, 15) connect _WIRE_216.gf, _T_2927 node _T_2928 = bits(_WIRE_217, 16, 16) connect _WIRE_216.pf, _T_2928 node _T_2929 = bits(_WIRE_217, 17, 17) connect _WIRE_216.ae_stage2, _T_2929 node _T_2930 = bits(_WIRE_217, 18, 18) connect _WIRE_216.ae_final, _T_2930 node _T_2931 = bits(_WIRE_217, 19, 19) connect _WIRE_216.ae_ptw, _T_2931 node _T_2932 = bits(_WIRE_217, 20, 20) connect _WIRE_216.g, _T_2932 node _T_2933 = bits(_WIRE_217, 21, 21) connect _WIRE_216.u, _T_2933 node _T_2934 = bits(_WIRE_217, 41, 22) connect _WIRE_216.ppn, _T_2934 wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_219 : UInt<42> connect _WIRE_219, sectored_entries[0][6].data[1] node _T_2935 = bits(_WIRE_219, 0, 0) connect _WIRE_218.fragmented_superpage, _T_2935 node _T_2936 = bits(_WIRE_219, 1, 1) connect _WIRE_218.c, _T_2936 node _T_2937 = bits(_WIRE_219, 2, 2) connect _WIRE_218.eff, _T_2937 node _T_2938 = bits(_WIRE_219, 3, 3) connect _WIRE_218.paa, _T_2938 node _T_2939 = bits(_WIRE_219, 4, 4) connect _WIRE_218.pal, _T_2939 node _T_2940 = bits(_WIRE_219, 5, 5) connect _WIRE_218.ppp, _T_2940 node _T_2941 = bits(_WIRE_219, 6, 6) connect _WIRE_218.pr, _T_2941 node _T_2942 = bits(_WIRE_219, 7, 7) connect _WIRE_218.px, _T_2942 node _T_2943 = bits(_WIRE_219, 8, 8) connect _WIRE_218.pw, _T_2943 node _T_2944 = bits(_WIRE_219, 9, 9) connect _WIRE_218.hr, _T_2944 node _T_2945 = bits(_WIRE_219, 10, 10) connect _WIRE_218.hx, _T_2945 node _T_2946 = bits(_WIRE_219, 11, 11) connect _WIRE_218.hw, _T_2946 node _T_2947 = bits(_WIRE_219, 12, 12) connect _WIRE_218.sr, _T_2947 node _T_2948 = bits(_WIRE_219, 13, 13) connect _WIRE_218.sx, _T_2948 node _T_2949 = bits(_WIRE_219, 14, 14) connect _WIRE_218.sw, _T_2949 node _T_2950 = bits(_WIRE_219, 15, 15) connect _WIRE_218.gf, _T_2950 node _T_2951 = bits(_WIRE_219, 16, 16) connect _WIRE_218.pf, _T_2951 node _T_2952 = bits(_WIRE_219, 17, 17) connect _WIRE_218.ae_stage2, _T_2952 node _T_2953 = bits(_WIRE_219, 18, 18) connect _WIRE_218.ae_final, _T_2953 node _T_2954 = bits(_WIRE_219, 19, 19) connect _WIRE_218.ae_ptw, _T_2954 node _T_2955 = bits(_WIRE_219, 20, 20) connect _WIRE_218.g, _T_2955 node _T_2956 = bits(_WIRE_219, 21, 21) connect _WIRE_218.u, _T_2956 node _T_2957 = bits(_WIRE_219, 41, 22) connect _WIRE_218.ppn, _T_2957 wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_221 : UInt<42> connect _WIRE_221, sectored_entries[0][6].data[2] node _T_2958 = bits(_WIRE_221, 0, 0) connect _WIRE_220.fragmented_superpage, _T_2958 node _T_2959 = bits(_WIRE_221, 1, 1) connect _WIRE_220.c, _T_2959 node _T_2960 = bits(_WIRE_221, 2, 2) connect _WIRE_220.eff, _T_2960 node _T_2961 = bits(_WIRE_221, 3, 3) connect _WIRE_220.paa, _T_2961 node _T_2962 = bits(_WIRE_221, 4, 4) connect _WIRE_220.pal, _T_2962 node _T_2963 = bits(_WIRE_221, 5, 5) connect _WIRE_220.ppp, _T_2963 node _T_2964 = bits(_WIRE_221, 6, 6) connect _WIRE_220.pr, _T_2964 node _T_2965 = bits(_WIRE_221, 7, 7) connect _WIRE_220.px, _T_2965 node _T_2966 = bits(_WIRE_221, 8, 8) connect _WIRE_220.pw, _T_2966 node _T_2967 = bits(_WIRE_221, 9, 9) connect _WIRE_220.hr, _T_2967 node _T_2968 = bits(_WIRE_221, 10, 10) connect _WIRE_220.hx, _T_2968 node _T_2969 = bits(_WIRE_221, 11, 11) connect _WIRE_220.hw, _T_2969 node _T_2970 = bits(_WIRE_221, 12, 12) connect _WIRE_220.sr, _T_2970 node _T_2971 = bits(_WIRE_221, 13, 13) connect _WIRE_220.sx, _T_2971 node _T_2972 = bits(_WIRE_221, 14, 14) connect _WIRE_220.sw, _T_2972 node _T_2973 = bits(_WIRE_221, 15, 15) connect _WIRE_220.gf, _T_2973 node _T_2974 = bits(_WIRE_221, 16, 16) connect _WIRE_220.pf, _T_2974 node _T_2975 = bits(_WIRE_221, 17, 17) connect _WIRE_220.ae_stage2, _T_2975 node _T_2976 = bits(_WIRE_221, 18, 18) connect _WIRE_220.ae_final, _T_2976 node _T_2977 = bits(_WIRE_221, 19, 19) connect _WIRE_220.ae_ptw, _T_2977 node _T_2978 = bits(_WIRE_221, 20, 20) connect _WIRE_220.g, _T_2978 node _T_2979 = bits(_WIRE_221, 21, 21) connect _WIRE_220.u, _T_2979 node _T_2980 = bits(_WIRE_221, 41, 22) connect _WIRE_220.ppn, _T_2980 wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_223 : UInt<42> connect _WIRE_223, sectored_entries[0][6].data[3] node _T_2981 = bits(_WIRE_223, 0, 0) connect _WIRE_222.fragmented_superpage, _T_2981 node _T_2982 = bits(_WIRE_223, 1, 1) connect _WIRE_222.c, _T_2982 node _T_2983 = bits(_WIRE_223, 2, 2) connect _WIRE_222.eff, _T_2983 node _T_2984 = bits(_WIRE_223, 3, 3) connect _WIRE_222.paa, _T_2984 node _T_2985 = bits(_WIRE_223, 4, 4) connect _WIRE_222.pal, _T_2985 node _T_2986 = bits(_WIRE_223, 5, 5) connect _WIRE_222.ppp, _T_2986 node _T_2987 = bits(_WIRE_223, 6, 6) connect _WIRE_222.pr, _T_2987 node _T_2988 = bits(_WIRE_223, 7, 7) connect _WIRE_222.px, _T_2988 node _T_2989 = bits(_WIRE_223, 8, 8) connect _WIRE_222.pw, _T_2989 node _T_2990 = bits(_WIRE_223, 9, 9) connect _WIRE_222.hr, _T_2990 node _T_2991 = bits(_WIRE_223, 10, 10) connect _WIRE_222.hx, _T_2991 node _T_2992 = bits(_WIRE_223, 11, 11) connect _WIRE_222.hw, _T_2992 node _T_2993 = bits(_WIRE_223, 12, 12) connect _WIRE_222.sr, _T_2993 node _T_2994 = bits(_WIRE_223, 13, 13) connect _WIRE_222.sx, _T_2994 node _T_2995 = bits(_WIRE_223, 14, 14) connect _WIRE_222.sw, _T_2995 node _T_2996 = bits(_WIRE_223, 15, 15) connect _WIRE_222.gf, _T_2996 node _T_2997 = bits(_WIRE_223, 16, 16) connect _WIRE_222.pf, _T_2997 node _T_2998 = bits(_WIRE_223, 17, 17) connect _WIRE_222.ae_stage2, _T_2998 node _T_2999 = bits(_WIRE_223, 18, 18) connect _WIRE_222.ae_final, _T_2999 node _T_3000 = bits(_WIRE_223, 19, 19) connect _WIRE_222.ae_ptw, _T_3000 node _T_3001 = bits(_WIRE_223, 20, 20) connect _WIRE_222.g, _T_3001 node _T_3002 = bits(_WIRE_223, 21, 21) connect _WIRE_222.u, _T_3002 node _T_3003 = bits(_WIRE_223, 41, 22) connect _WIRE_222.ppn, _T_3003 node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3004 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3005 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3006 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911) when _T_3007 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3008 = eq(hg_7, UInt<1>(0h0)) node _T_3009 = and(_T_3008, io.sfence.bits.rs1) when _T_3009 : node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3011 = shr(_T_3010, 2) node _T_3012 = eq(_T_3011, UInt<1>(0h0)) node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3014 = and(_T_3012, _T_3013) when _T_3014 : wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_225 : UInt<42> connect _WIRE_225, sectored_entries[0][7].data[0] node _T_3015 = bits(_WIRE_225, 0, 0) connect _WIRE_224.fragmented_superpage, _T_3015 node _T_3016 = bits(_WIRE_225, 1, 1) connect _WIRE_224.c, _T_3016 node _T_3017 = bits(_WIRE_225, 2, 2) connect _WIRE_224.eff, _T_3017 node _T_3018 = bits(_WIRE_225, 3, 3) connect _WIRE_224.paa, _T_3018 node _T_3019 = bits(_WIRE_225, 4, 4) connect _WIRE_224.pal, _T_3019 node _T_3020 = bits(_WIRE_225, 5, 5) connect _WIRE_224.ppp, _T_3020 node _T_3021 = bits(_WIRE_225, 6, 6) connect _WIRE_224.pr, _T_3021 node _T_3022 = bits(_WIRE_225, 7, 7) connect _WIRE_224.px, _T_3022 node _T_3023 = bits(_WIRE_225, 8, 8) connect _WIRE_224.pw, _T_3023 node _T_3024 = bits(_WIRE_225, 9, 9) connect _WIRE_224.hr, _T_3024 node _T_3025 = bits(_WIRE_225, 10, 10) connect _WIRE_224.hx, _T_3025 node _T_3026 = bits(_WIRE_225, 11, 11) connect _WIRE_224.hw, _T_3026 node _T_3027 = bits(_WIRE_225, 12, 12) connect _WIRE_224.sr, _T_3027 node _T_3028 = bits(_WIRE_225, 13, 13) connect _WIRE_224.sx, _T_3028 node _T_3029 = bits(_WIRE_225, 14, 14) connect _WIRE_224.sw, _T_3029 node _T_3030 = bits(_WIRE_225, 15, 15) connect _WIRE_224.gf, _T_3030 node _T_3031 = bits(_WIRE_225, 16, 16) connect _WIRE_224.pf, _T_3031 node _T_3032 = bits(_WIRE_225, 17, 17) connect _WIRE_224.ae_stage2, _T_3032 node _T_3033 = bits(_WIRE_225, 18, 18) connect _WIRE_224.ae_final, _T_3033 node _T_3034 = bits(_WIRE_225, 19, 19) connect _WIRE_224.ae_ptw, _T_3034 node _T_3035 = bits(_WIRE_225, 20, 20) connect _WIRE_224.g, _T_3035 node _T_3036 = bits(_WIRE_225, 21, 21) connect _WIRE_224.u, _T_3036 node _T_3037 = bits(_WIRE_225, 41, 22) connect _WIRE_224.ppn, _T_3037 wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_227 : UInt<42> connect _WIRE_227, sectored_entries[0][7].data[1] node _T_3038 = bits(_WIRE_227, 0, 0) connect _WIRE_226.fragmented_superpage, _T_3038 node _T_3039 = bits(_WIRE_227, 1, 1) connect _WIRE_226.c, _T_3039 node _T_3040 = bits(_WIRE_227, 2, 2) connect _WIRE_226.eff, _T_3040 node _T_3041 = bits(_WIRE_227, 3, 3) connect _WIRE_226.paa, _T_3041 node _T_3042 = bits(_WIRE_227, 4, 4) connect _WIRE_226.pal, _T_3042 node _T_3043 = bits(_WIRE_227, 5, 5) connect _WIRE_226.ppp, _T_3043 node _T_3044 = bits(_WIRE_227, 6, 6) connect _WIRE_226.pr, _T_3044 node _T_3045 = bits(_WIRE_227, 7, 7) connect _WIRE_226.px, _T_3045 node _T_3046 = bits(_WIRE_227, 8, 8) connect _WIRE_226.pw, _T_3046 node _T_3047 = bits(_WIRE_227, 9, 9) connect _WIRE_226.hr, _T_3047 node _T_3048 = bits(_WIRE_227, 10, 10) connect _WIRE_226.hx, _T_3048 node _T_3049 = bits(_WIRE_227, 11, 11) connect _WIRE_226.hw, _T_3049 node _T_3050 = bits(_WIRE_227, 12, 12) connect _WIRE_226.sr, _T_3050 node _T_3051 = bits(_WIRE_227, 13, 13) connect _WIRE_226.sx, _T_3051 node _T_3052 = bits(_WIRE_227, 14, 14) connect _WIRE_226.sw, _T_3052 node _T_3053 = bits(_WIRE_227, 15, 15) connect _WIRE_226.gf, _T_3053 node _T_3054 = bits(_WIRE_227, 16, 16) connect _WIRE_226.pf, _T_3054 node _T_3055 = bits(_WIRE_227, 17, 17) connect _WIRE_226.ae_stage2, _T_3055 node _T_3056 = bits(_WIRE_227, 18, 18) connect _WIRE_226.ae_final, _T_3056 node _T_3057 = bits(_WIRE_227, 19, 19) connect _WIRE_226.ae_ptw, _T_3057 node _T_3058 = bits(_WIRE_227, 20, 20) connect _WIRE_226.g, _T_3058 node _T_3059 = bits(_WIRE_227, 21, 21) connect _WIRE_226.u, _T_3059 node _T_3060 = bits(_WIRE_227, 41, 22) connect _WIRE_226.ppn, _T_3060 wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_229 : UInt<42> connect _WIRE_229, sectored_entries[0][7].data[2] node _T_3061 = bits(_WIRE_229, 0, 0) connect _WIRE_228.fragmented_superpage, _T_3061 node _T_3062 = bits(_WIRE_229, 1, 1) connect _WIRE_228.c, _T_3062 node _T_3063 = bits(_WIRE_229, 2, 2) connect _WIRE_228.eff, _T_3063 node _T_3064 = bits(_WIRE_229, 3, 3) connect _WIRE_228.paa, _T_3064 node _T_3065 = bits(_WIRE_229, 4, 4) connect _WIRE_228.pal, _T_3065 node _T_3066 = bits(_WIRE_229, 5, 5) connect _WIRE_228.ppp, _T_3066 node _T_3067 = bits(_WIRE_229, 6, 6) connect _WIRE_228.pr, _T_3067 node _T_3068 = bits(_WIRE_229, 7, 7) connect _WIRE_228.px, _T_3068 node _T_3069 = bits(_WIRE_229, 8, 8) connect _WIRE_228.pw, _T_3069 node _T_3070 = bits(_WIRE_229, 9, 9) connect _WIRE_228.hr, _T_3070 node _T_3071 = bits(_WIRE_229, 10, 10) connect _WIRE_228.hx, _T_3071 node _T_3072 = bits(_WIRE_229, 11, 11) connect _WIRE_228.hw, _T_3072 node _T_3073 = bits(_WIRE_229, 12, 12) connect _WIRE_228.sr, _T_3073 node _T_3074 = bits(_WIRE_229, 13, 13) connect _WIRE_228.sx, _T_3074 node _T_3075 = bits(_WIRE_229, 14, 14) connect _WIRE_228.sw, _T_3075 node _T_3076 = bits(_WIRE_229, 15, 15) connect _WIRE_228.gf, _T_3076 node _T_3077 = bits(_WIRE_229, 16, 16) connect _WIRE_228.pf, _T_3077 node _T_3078 = bits(_WIRE_229, 17, 17) connect _WIRE_228.ae_stage2, _T_3078 node _T_3079 = bits(_WIRE_229, 18, 18) connect _WIRE_228.ae_final, _T_3079 node _T_3080 = bits(_WIRE_229, 19, 19) connect _WIRE_228.ae_ptw, _T_3080 node _T_3081 = bits(_WIRE_229, 20, 20) connect _WIRE_228.g, _T_3081 node _T_3082 = bits(_WIRE_229, 21, 21) connect _WIRE_228.u, _T_3082 node _T_3083 = bits(_WIRE_229, 41, 22) connect _WIRE_228.ppn, _T_3083 wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_231 : UInt<42> connect _WIRE_231, sectored_entries[0][7].data[3] node _T_3084 = bits(_WIRE_231, 0, 0) connect _WIRE_230.fragmented_superpage, _T_3084 node _T_3085 = bits(_WIRE_231, 1, 1) connect _WIRE_230.c, _T_3085 node _T_3086 = bits(_WIRE_231, 2, 2) connect _WIRE_230.eff, _T_3086 node _T_3087 = bits(_WIRE_231, 3, 3) connect _WIRE_230.paa, _T_3087 node _T_3088 = bits(_WIRE_231, 4, 4) connect _WIRE_230.pal, _T_3088 node _T_3089 = bits(_WIRE_231, 5, 5) connect _WIRE_230.ppp, _T_3089 node _T_3090 = bits(_WIRE_231, 6, 6) connect _WIRE_230.pr, _T_3090 node _T_3091 = bits(_WIRE_231, 7, 7) connect _WIRE_230.px, _T_3091 node _T_3092 = bits(_WIRE_231, 8, 8) connect _WIRE_230.pw, _T_3092 node _T_3093 = bits(_WIRE_231, 9, 9) connect _WIRE_230.hr, _T_3093 node _T_3094 = bits(_WIRE_231, 10, 10) connect _WIRE_230.hx, _T_3094 node _T_3095 = bits(_WIRE_231, 11, 11) connect _WIRE_230.hw, _T_3095 node _T_3096 = bits(_WIRE_231, 12, 12) connect _WIRE_230.sr, _T_3096 node _T_3097 = bits(_WIRE_231, 13, 13) connect _WIRE_230.sx, _T_3097 node _T_3098 = bits(_WIRE_231, 14, 14) connect _WIRE_230.sw, _T_3098 node _T_3099 = bits(_WIRE_231, 15, 15) connect _WIRE_230.gf, _T_3099 node _T_3100 = bits(_WIRE_231, 16, 16) connect _WIRE_230.pf, _T_3100 node _T_3101 = bits(_WIRE_231, 17, 17) connect _WIRE_230.ae_stage2, _T_3101 node _T_3102 = bits(_WIRE_231, 18, 18) connect _WIRE_230.ae_final, _T_3102 node _T_3103 = bits(_WIRE_231, 19, 19) connect _WIRE_230.ae_ptw, _T_3103 node _T_3104 = bits(_WIRE_231, 20, 20) connect _WIRE_230.g, _T_3104 node _T_3105 = bits(_WIRE_231, 21, 21) connect _WIRE_230.u, _T_3105 node _T_3106 = bits(_WIRE_231, 41, 22) connect _WIRE_230.ppn, _T_3106 node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3108 = bits(vpn, 1, 0) node _T_3109 = eq(UInt<1>(0h0), _T_3108) node _T_3110 = and(_T_3107, _T_3109) when _T_3110 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3112 = bits(vpn, 1, 0) node _T_3113 = eq(UInt<1>(0h1), _T_3112) node _T_3114 = and(_T_3111, _T_3113) when _T_3114 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3116 = bits(vpn, 1, 0) node _T_3117 = eq(UInt<2>(0h2), _T_3116) node _T_3118 = and(_T_3115, _T_3117) when _T_3118 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3120 = bits(vpn, 1, 0) node _T_3121 = eq(UInt<2>(0h3), _T_3120) node _T_3122 = and(_T_3119, _T_3121) when _T_3122 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn) node _T_3124 = shr(_T_3123, 18) node _T_3125 = eq(_T_3124, UInt<1>(0h0)) when _T_3125 : wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_233 : UInt<42> connect _WIRE_233, sectored_entries[0][7].data[0] node _T_3126 = bits(_WIRE_233, 0, 0) connect _WIRE_232.fragmented_superpage, _T_3126 node _T_3127 = bits(_WIRE_233, 1, 1) connect _WIRE_232.c, _T_3127 node _T_3128 = bits(_WIRE_233, 2, 2) connect _WIRE_232.eff, _T_3128 node _T_3129 = bits(_WIRE_233, 3, 3) connect _WIRE_232.paa, _T_3129 node _T_3130 = bits(_WIRE_233, 4, 4) connect _WIRE_232.pal, _T_3130 node _T_3131 = bits(_WIRE_233, 5, 5) connect _WIRE_232.ppp, _T_3131 node _T_3132 = bits(_WIRE_233, 6, 6) connect _WIRE_232.pr, _T_3132 node _T_3133 = bits(_WIRE_233, 7, 7) connect _WIRE_232.px, _T_3133 node _T_3134 = bits(_WIRE_233, 8, 8) connect _WIRE_232.pw, _T_3134 node _T_3135 = bits(_WIRE_233, 9, 9) connect _WIRE_232.hr, _T_3135 node _T_3136 = bits(_WIRE_233, 10, 10) connect _WIRE_232.hx, _T_3136 node _T_3137 = bits(_WIRE_233, 11, 11) connect _WIRE_232.hw, _T_3137 node _T_3138 = bits(_WIRE_233, 12, 12) connect _WIRE_232.sr, _T_3138 node _T_3139 = bits(_WIRE_233, 13, 13) connect _WIRE_232.sx, _T_3139 node _T_3140 = bits(_WIRE_233, 14, 14) connect _WIRE_232.sw, _T_3140 node _T_3141 = bits(_WIRE_233, 15, 15) connect _WIRE_232.gf, _T_3141 node _T_3142 = bits(_WIRE_233, 16, 16) connect _WIRE_232.pf, _T_3142 node _T_3143 = bits(_WIRE_233, 17, 17) connect _WIRE_232.ae_stage2, _T_3143 node _T_3144 = bits(_WIRE_233, 18, 18) connect _WIRE_232.ae_final, _T_3144 node _T_3145 = bits(_WIRE_233, 19, 19) connect _WIRE_232.ae_ptw, _T_3145 node _T_3146 = bits(_WIRE_233, 20, 20) connect _WIRE_232.g, _T_3146 node _T_3147 = bits(_WIRE_233, 21, 21) connect _WIRE_232.u, _T_3147 node _T_3148 = bits(_WIRE_233, 41, 22) connect _WIRE_232.ppn, _T_3148 wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_235 : UInt<42> connect _WIRE_235, sectored_entries[0][7].data[1] node _T_3149 = bits(_WIRE_235, 0, 0) connect _WIRE_234.fragmented_superpage, _T_3149 node _T_3150 = bits(_WIRE_235, 1, 1) connect _WIRE_234.c, _T_3150 node _T_3151 = bits(_WIRE_235, 2, 2) connect _WIRE_234.eff, _T_3151 node _T_3152 = bits(_WIRE_235, 3, 3) connect _WIRE_234.paa, _T_3152 node _T_3153 = bits(_WIRE_235, 4, 4) connect _WIRE_234.pal, _T_3153 node _T_3154 = bits(_WIRE_235, 5, 5) connect _WIRE_234.ppp, _T_3154 node _T_3155 = bits(_WIRE_235, 6, 6) connect _WIRE_234.pr, _T_3155 node _T_3156 = bits(_WIRE_235, 7, 7) connect _WIRE_234.px, _T_3156 node _T_3157 = bits(_WIRE_235, 8, 8) connect _WIRE_234.pw, _T_3157 node _T_3158 = bits(_WIRE_235, 9, 9) connect _WIRE_234.hr, _T_3158 node _T_3159 = bits(_WIRE_235, 10, 10) connect _WIRE_234.hx, _T_3159 node _T_3160 = bits(_WIRE_235, 11, 11) connect _WIRE_234.hw, _T_3160 node _T_3161 = bits(_WIRE_235, 12, 12) connect _WIRE_234.sr, _T_3161 node _T_3162 = bits(_WIRE_235, 13, 13) connect _WIRE_234.sx, _T_3162 node _T_3163 = bits(_WIRE_235, 14, 14) connect _WIRE_234.sw, _T_3163 node _T_3164 = bits(_WIRE_235, 15, 15) connect _WIRE_234.gf, _T_3164 node _T_3165 = bits(_WIRE_235, 16, 16) connect _WIRE_234.pf, _T_3165 node _T_3166 = bits(_WIRE_235, 17, 17) connect _WIRE_234.ae_stage2, _T_3166 node _T_3167 = bits(_WIRE_235, 18, 18) connect _WIRE_234.ae_final, _T_3167 node _T_3168 = bits(_WIRE_235, 19, 19) connect _WIRE_234.ae_ptw, _T_3168 node _T_3169 = bits(_WIRE_235, 20, 20) connect _WIRE_234.g, _T_3169 node _T_3170 = bits(_WIRE_235, 21, 21) connect _WIRE_234.u, _T_3170 node _T_3171 = bits(_WIRE_235, 41, 22) connect _WIRE_234.ppn, _T_3171 wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_237 : UInt<42> connect _WIRE_237, sectored_entries[0][7].data[2] node _T_3172 = bits(_WIRE_237, 0, 0) connect _WIRE_236.fragmented_superpage, _T_3172 node _T_3173 = bits(_WIRE_237, 1, 1) connect _WIRE_236.c, _T_3173 node _T_3174 = bits(_WIRE_237, 2, 2) connect _WIRE_236.eff, _T_3174 node _T_3175 = bits(_WIRE_237, 3, 3) connect _WIRE_236.paa, _T_3175 node _T_3176 = bits(_WIRE_237, 4, 4) connect _WIRE_236.pal, _T_3176 node _T_3177 = bits(_WIRE_237, 5, 5) connect _WIRE_236.ppp, _T_3177 node _T_3178 = bits(_WIRE_237, 6, 6) connect _WIRE_236.pr, _T_3178 node _T_3179 = bits(_WIRE_237, 7, 7) connect _WIRE_236.px, _T_3179 node _T_3180 = bits(_WIRE_237, 8, 8) connect _WIRE_236.pw, _T_3180 node _T_3181 = bits(_WIRE_237, 9, 9) connect _WIRE_236.hr, _T_3181 node _T_3182 = bits(_WIRE_237, 10, 10) connect _WIRE_236.hx, _T_3182 node _T_3183 = bits(_WIRE_237, 11, 11) connect _WIRE_236.hw, _T_3183 node _T_3184 = bits(_WIRE_237, 12, 12) connect _WIRE_236.sr, _T_3184 node _T_3185 = bits(_WIRE_237, 13, 13) connect _WIRE_236.sx, _T_3185 node _T_3186 = bits(_WIRE_237, 14, 14) connect _WIRE_236.sw, _T_3186 node _T_3187 = bits(_WIRE_237, 15, 15) connect _WIRE_236.gf, _T_3187 node _T_3188 = bits(_WIRE_237, 16, 16) connect _WIRE_236.pf, _T_3188 node _T_3189 = bits(_WIRE_237, 17, 17) connect _WIRE_236.ae_stage2, _T_3189 node _T_3190 = bits(_WIRE_237, 18, 18) connect _WIRE_236.ae_final, _T_3190 node _T_3191 = bits(_WIRE_237, 19, 19) connect _WIRE_236.ae_ptw, _T_3191 node _T_3192 = bits(_WIRE_237, 20, 20) connect _WIRE_236.g, _T_3192 node _T_3193 = bits(_WIRE_237, 21, 21) connect _WIRE_236.u, _T_3193 node _T_3194 = bits(_WIRE_237, 41, 22) connect _WIRE_236.ppn, _T_3194 wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_239 : UInt<42> connect _WIRE_239, sectored_entries[0][7].data[3] node _T_3195 = bits(_WIRE_239, 0, 0) connect _WIRE_238.fragmented_superpage, _T_3195 node _T_3196 = bits(_WIRE_239, 1, 1) connect _WIRE_238.c, _T_3196 node _T_3197 = bits(_WIRE_239, 2, 2) connect _WIRE_238.eff, _T_3197 node _T_3198 = bits(_WIRE_239, 3, 3) connect _WIRE_238.paa, _T_3198 node _T_3199 = bits(_WIRE_239, 4, 4) connect _WIRE_238.pal, _T_3199 node _T_3200 = bits(_WIRE_239, 5, 5) connect _WIRE_238.ppp, _T_3200 node _T_3201 = bits(_WIRE_239, 6, 6) connect _WIRE_238.pr, _T_3201 node _T_3202 = bits(_WIRE_239, 7, 7) connect _WIRE_238.px, _T_3202 node _T_3203 = bits(_WIRE_239, 8, 8) connect _WIRE_238.pw, _T_3203 node _T_3204 = bits(_WIRE_239, 9, 9) connect _WIRE_238.hr, _T_3204 node _T_3205 = bits(_WIRE_239, 10, 10) connect _WIRE_238.hx, _T_3205 node _T_3206 = bits(_WIRE_239, 11, 11) connect _WIRE_238.hw, _T_3206 node _T_3207 = bits(_WIRE_239, 12, 12) connect _WIRE_238.sr, _T_3207 node _T_3208 = bits(_WIRE_239, 13, 13) connect _WIRE_238.sx, _T_3208 node _T_3209 = bits(_WIRE_239, 14, 14) connect _WIRE_238.sw, _T_3209 node _T_3210 = bits(_WIRE_239, 15, 15) connect _WIRE_238.gf, _T_3210 node _T_3211 = bits(_WIRE_239, 16, 16) connect _WIRE_238.pf, _T_3211 node _T_3212 = bits(_WIRE_239, 17, 17) connect _WIRE_238.ae_stage2, _T_3212 node _T_3213 = bits(_WIRE_239, 18, 18) connect _WIRE_238.ae_final, _T_3213 node _T_3214 = bits(_WIRE_239, 19, 19) connect _WIRE_238.ae_ptw, _T_3214 node _T_3215 = bits(_WIRE_239, 20, 20) connect _WIRE_238.g, _T_3215 node _T_3216 = bits(_WIRE_239, 21, 21) connect _WIRE_238.u, _T_3216 node _T_3217 = bits(_WIRE_239, 41, 22) connect _WIRE_238.ppn, _T_3217 node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage) when _T_3219 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage) when _T_3221 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage) when _T_3223 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage) when _T_3225 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3226 = eq(hg_7, UInt<1>(0h0)) node _T_3227 = and(_T_3226, io.sfence.bits.rs2) when _T_3227 : wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_241 : UInt<42> connect _WIRE_241, sectored_entries[0][7].data[0] node _T_3228 = bits(_WIRE_241, 0, 0) connect _WIRE_240.fragmented_superpage, _T_3228 node _T_3229 = bits(_WIRE_241, 1, 1) connect _WIRE_240.c, _T_3229 node _T_3230 = bits(_WIRE_241, 2, 2) connect _WIRE_240.eff, _T_3230 node _T_3231 = bits(_WIRE_241, 3, 3) connect _WIRE_240.paa, _T_3231 node _T_3232 = bits(_WIRE_241, 4, 4) connect _WIRE_240.pal, _T_3232 node _T_3233 = bits(_WIRE_241, 5, 5) connect _WIRE_240.ppp, _T_3233 node _T_3234 = bits(_WIRE_241, 6, 6) connect _WIRE_240.pr, _T_3234 node _T_3235 = bits(_WIRE_241, 7, 7) connect _WIRE_240.px, _T_3235 node _T_3236 = bits(_WIRE_241, 8, 8) connect _WIRE_240.pw, _T_3236 node _T_3237 = bits(_WIRE_241, 9, 9) connect _WIRE_240.hr, _T_3237 node _T_3238 = bits(_WIRE_241, 10, 10) connect _WIRE_240.hx, _T_3238 node _T_3239 = bits(_WIRE_241, 11, 11) connect _WIRE_240.hw, _T_3239 node _T_3240 = bits(_WIRE_241, 12, 12) connect _WIRE_240.sr, _T_3240 node _T_3241 = bits(_WIRE_241, 13, 13) connect _WIRE_240.sx, _T_3241 node _T_3242 = bits(_WIRE_241, 14, 14) connect _WIRE_240.sw, _T_3242 node _T_3243 = bits(_WIRE_241, 15, 15) connect _WIRE_240.gf, _T_3243 node _T_3244 = bits(_WIRE_241, 16, 16) connect _WIRE_240.pf, _T_3244 node _T_3245 = bits(_WIRE_241, 17, 17) connect _WIRE_240.ae_stage2, _T_3245 node _T_3246 = bits(_WIRE_241, 18, 18) connect _WIRE_240.ae_final, _T_3246 node _T_3247 = bits(_WIRE_241, 19, 19) connect _WIRE_240.ae_ptw, _T_3247 node _T_3248 = bits(_WIRE_241, 20, 20) connect _WIRE_240.g, _T_3248 node _T_3249 = bits(_WIRE_241, 21, 21) connect _WIRE_240.u, _T_3249 node _T_3250 = bits(_WIRE_241, 41, 22) connect _WIRE_240.ppn, _T_3250 wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_243 : UInt<42> connect _WIRE_243, sectored_entries[0][7].data[1] node _T_3251 = bits(_WIRE_243, 0, 0) connect _WIRE_242.fragmented_superpage, _T_3251 node _T_3252 = bits(_WIRE_243, 1, 1) connect _WIRE_242.c, _T_3252 node _T_3253 = bits(_WIRE_243, 2, 2) connect _WIRE_242.eff, _T_3253 node _T_3254 = bits(_WIRE_243, 3, 3) connect _WIRE_242.paa, _T_3254 node _T_3255 = bits(_WIRE_243, 4, 4) connect _WIRE_242.pal, _T_3255 node _T_3256 = bits(_WIRE_243, 5, 5) connect _WIRE_242.ppp, _T_3256 node _T_3257 = bits(_WIRE_243, 6, 6) connect _WIRE_242.pr, _T_3257 node _T_3258 = bits(_WIRE_243, 7, 7) connect _WIRE_242.px, _T_3258 node _T_3259 = bits(_WIRE_243, 8, 8) connect _WIRE_242.pw, _T_3259 node _T_3260 = bits(_WIRE_243, 9, 9) connect _WIRE_242.hr, _T_3260 node _T_3261 = bits(_WIRE_243, 10, 10) connect _WIRE_242.hx, _T_3261 node _T_3262 = bits(_WIRE_243, 11, 11) connect _WIRE_242.hw, _T_3262 node _T_3263 = bits(_WIRE_243, 12, 12) connect _WIRE_242.sr, _T_3263 node _T_3264 = bits(_WIRE_243, 13, 13) connect _WIRE_242.sx, _T_3264 node _T_3265 = bits(_WIRE_243, 14, 14) connect _WIRE_242.sw, _T_3265 node _T_3266 = bits(_WIRE_243, 15, 15) connect _WIRE_242.gf, _T_3266 node _T_3267 = bits(_WIRE_243, 16, 16) connect _WIRE_242.pf, _T_3267 node _T_3268 = bits(_WIRE_243, 17, 17) connect _WIRE_242.ae_stage2, _T_3268 node _T_3269 = bits(_WIRE_243, 18, 18) connect _WIRE_242.ae_final, _T_3269 node _T_3270 = bits(_WIRE_243, 19, 19) connect _WIRE_242.ae_ptw, _T_3270 node _T_3271 = bits(_WIRE_243, 20, 20) connect _WIRE_242.g, _T_3271 node _T_3272 = bits(_WIRE_243, 21, 21) connect _WIRE_242.u, _T_3272 node _T_3273 = bits(_WIRE_243, 41, 22) connect _WIRE_242.ppn, _T_3273 wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_245 : UInt<42> connect _WIRE_245, sectored_entries[0][7].data[2] node _T_3274 = bits(_WIRE_245, 0, 0) connect _WIRE_244.fragmented_superpage, _T_3274 node _T_3275 = bits(_WIRE_245, 1, 1) connect _WIRE_244.c, _T_3275 node _T_3276 = bits(_WIRE_245, 2, 2) connect _WIRE_244.eff, _T_3276 node _T_3277 = bits(_WIRE_245, 3, 3) connect _WIRE_244.paa, _T_3277 node _T_3278 = bits(_WIRE_245, 4, 4) connect _WIRE_244.pal, _T_3278 node _T_3279 = bits(_WIRE_245, 5, 5) connect _WIRE_244.ppp, _T_3279 node _T_3280 = bits(_WIRE_245, 6, 6) connect _WIRE_244.pr, _T_3280 node _T_3281 = bits(_WIRE_245, 7, 7) connect _WIRE_244.px, _T_3281 node _T_3282 = bits(_WIRE_245, 8, 8) connect _WIRE_244.pw, _T_3282 node _T_3283 = bits(_WIRE_245, 9, 9) connect _WIRE_244.hr, _T_3283 node _T_3284 = bits(_WIRE_245, 10, 10) connect _WIRE_244.hx, _T_3284 node _T_3285 = bits(_WIRE_245, 11, 11) connect _WIRE_244.hw, _T_3285 node _T_3286 = bits(_WIRE_245, 12, 12) connect _WIRE_244.sr, _T_3286 node _T_3287 = bits(_WIRE_245, 13, 13) connect _WIRE_244.sx, _T_3287 node _T_3288 = bits(_WIRE_245, 14, 14) connect _WIRE_244.sw, _T_3288 node _T_3289 = bits(_WIRE_245, 15, 15) connect _WIRE_244.gf, _T_3289 node _T_3290 = bits(_WIRE_245, 16, 16) connect _WIRE_244.pf, _T_3290 node _T_3291 = bits(_WIRE_245, 17, 17) connect _WIRE_244.ae_stage2, _T_3291 node _T_3292 = bits(_WIRE_245, 18, 18) connect _WIRE_244.ae_final, _T_3292 node _T_3293 = bits(_WIRE_245, 19, 19) connect _WIRE_244.ae_ptw, _T_3293 node _T_3294 = bits(_WIRE_245, 20, 20) connect _WIRE_244.g, _T_3294 node _T_3295 = bits(_WIRE_245, 21, 21) connect _WIRE_244.u, _T_3295 node _T_3296 = bits(_WIRE_245, 41, 22) connect _WIRE_244.ppn, _T_3296 wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_247 : UInt<42> connect _WIRE_247, sectored_entries[0][7].data[3] node _T_3297 = bits(_WIRE_247, 0, 0) connect _WIRE_246.fragmented_superpage, _T_3297 node _T_3298 = bits(_WIRE_247, 1, 1) connect _WIRE_246.c, _T_3298 node _T_3299 = bits(_WIRE_247, 2, 2) connect _WIRE_246.eff, _T_3299 node _T_3300 = bits(_WIRE_247, 3, 3) connect _WIRE_246.paa, _T_3300 node _T_3301 = bits(_WIRE_247, 4, 4) connect _WIRE_246.pal, _T_3301 node _T_3302 = bits(_WIRE_247, 5, 5) connect _WIRE_246.ppp, _T_3302 node _T_3303 = bits(_WIRE_247, 6, 6) connect _WIRE_246.pr, _T_3303 node _T_3304 = bits(_WIRE_247, 7, 7) connect _WIRE_246.px, _T_3304 node _T_3305 = bits(_WIRE_247, 8, 8) connect _WIRE_246.pw, _T_3305 node _T_3306 = bits(_WIRE_247, 9, 9) connect _WIRE_246.hr, _T_3306 node _T_3307 = bits(_WIRE_247, 10, 10) connect _WIRE_246.hx, _T_3307 node _T_3308 = bits(_WIRE_247, 11, 11) connect _WIRE_246.hw, _T_3308 node _T_3309 = bits(_WIRE_247, 12, 12) connect _WIRE_246.sr, _T_3309 node _T_3310 = bits(_WIRE_247, 13, 13) connect _WIRE_246.sx, _T_3310 node _T_3311 = bits(_WIRE_247, 14, 14) connect _WIRE_246.sw, _T_3311 node _T_3312 = bits(_WIRE_247, 15, 15) connect _WIRE_246.gf, _T_3312 node _T_3313 = bits(_WIRE_247, 16, 16) connect _WIRE_246.pf, _T_3313 node _T_3314 = bits(_WIRE_247, 17, 17) connect _WIRE_246.ae_stage2, _T_3314 node _T_3315 = bits(_WIRE_247, 18, 18) connect _WIRE_246.ae_final, _T_3315 node _T_3316 = bits(_WIRE_247, 19, 19) connect _WIRE_246.ae_ptw, _T_3316 node _T_3317 = bits(_WIRE_247, 20, 20) connect _WIRE_246.g, _T_3317 node _T_3318 = bits(_WIRE_247, 21, 21) connect _WIRE_246.u, _T_3318 node _T_3319 = bits(_WIRE_247, 41, 22) connect _WIRE_246.ppn, _T_3319 node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0)) node _T_3322 = and(_T_3320, _T_3321) when _T_3322 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0)) node _T_3325 = and(_T_3323, _T_3324) when _T_3325 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0)) node _T_3328 = and(_T_3326, _T_3327) when _T_3328 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7) node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0)) node _T_3331 = and(_T_3329, _T_3330) when _T_3331 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) else : node _T_3332 = or(hv_7, hg_7) wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_249 : UInt<42> connect _WIRE_249, sectored_entries[0][7].data[0] node _T_3333 = bits(_WIRE_249, 0, 0) connect _WIRE_248.fragmented_superpage, _T_3333 node _T_3334 = bits(_WIRE_249, 1, 1) connect _WIRE_248.c, _T_3334 node _T_3335 = bits(_WIRE_249, 2, 2) connect _WIRE_248.eff, _T_3335 node _T_3336 = bits(_WIRE_249, 3, 3) connect _WIRE_248.paa, _T_3336 node _T_3337 = bits(_WIRE_249, 4, 4) connect _WIRE_248.pal, _T_3337 node _T_3338 = bits(_WIRE_249, 5, 5) connect _WIRE_248.ppp, _T_3338 node _T_3339 = bits(_WIRE_249, 6, 6) connect _WIRE_248.pr, _T_3339 node _T_3340 = bits(_WIRE_249, 7, 7) connect _WIRE_248.px, _T_3340 node _T_3341 = bits(_WIRE_249, 8, 8) connect _WIRE_248.pw, _T_3341 node _T_3342 = bits(_WIRE_249, 9, 9) connect _WIRE_248.hr, _T_3342 node _T_3343 = bits(_WIRE_249, 10, 10) connect _WIRE_248.hx, _T_3343 node _T_3344 = bits(_WIRE_249, 11, 11) connect _WIRE_248.hw, _T_3344 node _T_3345 = bits(_WIRE_249, 12, 12) connect _WIRE_248.sr, _T_3345 node _T_3346 = bits(_WIRE_249, 13, 13) connect _WIRE_248.sx, _T_3346 node _T_3347 = bits(_WIRE_249, 14, 14) connect _WIRE_248.sw, _T_3347 node _T_3348 = bits(_WIRE_249, 15, 15) connect _WIRE_248.gf, _T_3348 node _T_3349 = bits(_WIRE_249, 16, 16) connect _WIRE_248.pf, _T_3349 node _T_3350 = bits(_WIRE_249, 17, 17) connect _WIRE_248.ae_stage2, _T_3350 node _T_3351 = bits(_WIRE_249, 18, 18) connect _WIRE_248.ae_final, _T_3351 node _T_3352 = bits(_WIRE_249, 19, 19) connect _WIRE_248.ae_ptw, _T_3352 node _T_3353 = bits(_WIRE_249, 20, 20) connect _WIRE_248.g, _T_3353 node _T_3354 = bits(_WIRE_249, 21, 21) connect _WIRE_248.u, _T_3354 node _T_3355 = bits(_WIRE_249, 41, 22) connect _WIRE_248.ppn, _T_3355 wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_251 : UInt<42> connect _WIRE_251, sectored_entries[0][7].data[1] node _T_3356 = bits(_WIRE_251, 0, 0) connect _WIRE_250.fragmented_superpage, _T_3356 node _T_3357 = bits(_WIRE_251, 1, 1) connect _WIRE_250.c, _T_3357 node _T_3358 = bits(_WIRE_251, 2, 2) connect _WIRE_250.eff, _T_3358 node _T_3359 = bits(_WIRE_251, 3, 3) connect _WIRE_250.paa, _T_3359 node _T_3360 = bits(_WIRE_251, 4, 4) connect _WIRE_250.pal, _T_3360 node _T_3361 = bits(_WIRE_251, 5, 5) connect _WIRE_250.ppp, _T_3361 node _T_3362 = bits(_WIRE_251, 6, 6) connect _WIRE_250.pr, _T_3362 node _T_3363 = bits(_WIRE_251, 7, 7) connect _WIRE_250.px, _T_3363 node _T_3364 = bits(_WIRE_251, 8, 8) connect _WIRE_250.pw, _T_3364 node _T_3365 = bits(_WIRE_251, 9, 9) connect _WIRE_250.hr, _T_3365 node _T_3366 = bits(_WIRE_251, 10, 10) connect _WIRE_250.hx, _T_3366 node _T_3367 = bits(_WIRE_251, 11, 11) connect _WIRE_250.hw, _T_3367 node _T_3368 = bits(_WIRE_251, 12, 12) connect _WIRE_250.sr, _T_3368 node _T_3369 = bits(_WIRE_251, 13, 13) connect _WIRE_250.sx, _T_3369 node _T_3370 = bits(_WIRE_251, 14, 14) connect _WIRE_250.sw, _T_3370 node _T_3371 = bits(_WIRE_251, 15, 15) connect _WIRE_250.gf, _T_3371 node _T_3372 = bits(_WIRE_251, 16, 16) connect _WIRE_250.pf, _T_3372 node _T_3373 = bits(_WIRE_251, 17, 17) connect _WIRE_250.ae_stage2, _T_3373 node _T_3374 = bits(_WIRE_251, 18, 18) connect _WIRE_250.ae_final, _T_3374 node _T_3375 = bits(_WIRE_251, 19, 19) connect _WIRE_250.ae_ptw, _T_3375 node _T_3376 = bits(_WIRE_251, 20, 20) connect _WIRE_250.g, _T_3376 node _T_3377 = bits(_WIRE_251, 21, 21) connect _WIRE_250.u, _T_3377 node _T_3378 = bits(_WIRE_251, 41, 22) connect _WIRE_250.ppn, _T_3378 wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_253 : UInt<42> connect _WIRE_253, sectored_entries[0][7].data[2] node _T_3379 = bits(_WIRE_253, 0, 0) connect _WIRE_252.fragmented_superpage, _T_3379 node _T_3380 = bits(_WIRE_253, 1, 1) connect _WIRE_252.c, _T_3380 node _T_3381 = bits(_WIRE_253, 2, 2) connect _WIRE_252.eff, _T_3381 node _T_3382 = bits(_WIRE_253, 3, 3) connect _WIRE_252.paa, _T_3382 node _T_3383 = bits(_WIRE_253, 4, 4) connect _WIRE_252.pal, _T_3383 node _T_3384 = bits(_WIRE_253, 5, 5) connect _WIRE_252.ppp, _T_3384 node _T_3385 = bits(_WIRE_253, 6, 6) connect _WIRE_252.pr, _T_3385 node _T_3386 = bits(_WIRE_253, 7, 7) connect _WIRE_252.px, _T_3386 node _T_3387 = bits(_WIRE_253, 8, 8) connect _WIRE_252.pw, _T_3387 node _T_3388 = bits(_WIRE_253, 9, 9) connect _WIRE_252.hr, _T_3388 node _T_3389 = bits(_WIRE_253, 10, 10) connect _WIRE_252.hx, _T_3389 node _T_3390 = bits(_WIRE_253, 11, 11) connect _WIRE_252.hw, _T_3390 node _T_3391 = bits(_WIRE_253, 12, 12) connect _WIRE_252.sr, _T_3391 node _T_3392 = bits(_WIRE_253, 13, 13) connect _WIRE_252.sx, _T_3392 node _T_3393 = bits(_WIRE_253, 14, 14) connect _WIRE_252.sw, _T_3393 node _T_3394 = bits(_WIRE_253, 15, 15) connect _WIRE_252.gf, _T_3394 node _T_3395 = bits(_WIRE_253, 16, 16) connect _WIRE_252.pf, _T_3395 node _T_3396 = bits(_WIRE_253, 17, 17) connect _WIRE_252.ae_stage2, _T_3396 node _T_3397 = bits(_WIRE_253, 18, 18) connect _WIRE_252.ae_final, _T_3397 node _T_3398 = bits(_WIRE_253, 19, 19) connect _WIRE_252.ae_ptw, _T_3398 node _T_3399 = bits(_WIRE_253, 20, 20) connect _WIRE_252.g, _T_3399 node _T_3400 = bits(_WIRE_253, 21, 21) connect _WIRE_252.u, _T_3400 node _T_3401 = bits(_WIRE_253, 41, 22) connect _WIRE_252.ppn, _T_3401 wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_255 : UInt<42> connect _WIRE_255, sectored_entries[0][7].data[3] node _T_3402 = bits(_WIRE_255, 0, 0) connect _WIRE_254.fragmented_superpage, _T_3402 node _T_3403 = bits(_WIRE_255, 1, 1) connect _WIRE_254.c, _T_3403 node _T_3404 = bits(_WIRE_255, 2, 2) connect _WIRE_254.eff, _T_3404 node _T_3405 = bits(_WIRE_255, 3, 3) connect _WIRE_254.paa, _T_3405 node _T_3406 = bits(_WIRE_255, 4, 4) connect _WIRE_254.pal, _T_3406 node _T_3407 = bits(_WIRE_255, 5, 5) connect _WIRE_254.ppp, _T_3407 node _T_3408 = bits(_WIRE_255, 6, 6) connect _WIRE_254.pr, _T_3408 node _T_3409 = bits(_WIRE_255, 7, 7) connect _WIRE_254.px, _T_3409 node _T_3410 = bits(_WIRE_255, 8, 8) connect _WIRE_254.pw, _T_3410 node _T_3411 = bits(_WIRE_255, 9, 9) connect _WIRE_254.hr, _T_3411 node _T_3412 = bits(_WIRE_255, 10, 10) connect _WIRE_254.hx, _T_3412 node _T_3413 = bits(_WIRE_255, 11, 11) connect _WIRE_254.hw, _T_3413 node _T_3414 = bits(_WIRE_255, 12, 12) connect _WIRE_254.sr, _T_3414 node _T_3415 = bits(_WIRE_255, 13, 13) connect _WIRE_254.sx, _T_3415 node _T_3416 = bits(_WIRE_255, 14, 14) connect _WIRE_254.sw, _T_3416 node _T_3417 = bits(_WIRE_255, 15, 15) connect _WIRE_254.gf, _T_3417 node _T_3418 = bits(_WIRE_255, 16, 16) connect _WIRE_254.pf, _T_3418 node _T_3419 = bits(_WIRE_255, 17, 17) connect _WIRE_254.ae_stage2, _T_3419 node _T_3420 = bits(_WIRE_255, 18, 18) connect _WIRE_254.ae_final, _T_3420 node _T_3421 = bits(_WIRE_255, 19, 19) connect _WIRE_254.ae_ptw, _T_3421 node _T_3422 = bits(_WIRE_255, 20, 20) connect _WIRE_254.g, _T_3422 node _T_3423 = bits(_WIRE_255, 21, 21) connect _WIRE_254.u, _T_3423 node _T_3424 = bits(_WIRE_255, 41, 22) connect _WIRE_254.ppn, _T_3424 node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3425 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3426 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3427 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332) when _T_3428 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3429 = eq(hg_8, UInt<1>(0h0)) node _T_3430 = and(_T_3429, io.sfence.bits.rs1) when _T_3430 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3432 = bits(_T_3431, 26, 18) node _T_3433 = eq(_T_3432, UInt<1>(0h0)) node _T_3434 = or(ignore, _T_3433) node _T_3435 = and(tagMatch, _T_3434) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3437 = bits(_T_3436, 17, 9) node _T_3438 = eq(_T_3437, UInt<1>(0h0)) node _T_3439 = or(ignore_1, _T_3438) node _T_3440 = and(_T_3435, _T_3439) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3442 = bits(_T_3441, 8, 0) node _T_3443 = eq(_T_3442, UInt<1>(0h0)) node _T_3444 = or(ignore_2, _T_3443) node _T_3445 = and(_T_3440, _T_3444) when _T_3445 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn) node _T_3447 = shr(_T_3446, 18) node _T_3448 = eq(_T_3447, UInt<1>(0h0)) when _T_3448 : wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_257 : UInt<42> connect _WIRE_257, superpage_entries[0].data[0] node _T_3449 = bits(_WIRE_257, 0, 0) connect _WIRE_256.fragmented_superpage, _T_3449 node _T_3450 = bits(_WIRE_257, 1, 1) connect _WIRE_256.c, _T_3450 node _T_3451 = bits(_WIRE_257, 2, 2) connect _WIRE_256.eff, _T_3451 node _T_3452 = bits(_WIRE_257, 3, 3) connect _WIRE_256.paa, _T_3452 node _T_3453 = bits(_WIRE_257, 4, 4) connect _WIRE_256.pal, _T_3453 node _T_3454 = bits(_WIRE_257, 5, 5) connect _WIRE_256.ppp, _T_3454 node _T_3455 = bits(_WIRE_257, 6, 6) connect _WIRE_256.pr, _T_3455 node _T_3456 = bits(_WIRE_257, 7, 7) connect _WIRE_256.px, _T_3456 node _T_3457 = bits(_WIRE_257, 8, 8) connect _WIRE_256.pw, _T_3457 node _T_3458 = bits(_WIRE_257, 9, 9) connect _WIRE_256.hr, _T_3458 node _T_3459 = bits(_WIRE_257, 10, 10) connect _WIRE_256.hx, _T_3459 node _T_3460 = bits(_WIRE_257, 11, 11) connect _WIRE_256.hw, _T_3460 node _T_3461 = bits(_WIRE_257, 12, 12) connect _WIRE_256.sr, _T_3461 node _T_3462 = bits(_WIRE_257, 13, 13) connect _WIRE_256.sx, _T_3462 node _T_3463 = bits(_WIRE_257, 14, 14) connect _WIRE_256.sw, _T_3463 node _T_3464 = bits(_WIRE_257, 15, 15) connect _WIRE_256.gf, _T_3464 node _T_3465 = bits(_WIRE_257, 16, 16) connect _WIRE_256.pf, _T_3465 node _T_3466 = bits(_WIRE_257, 17, 17) connect _WIRE_256.ae_stage2, _T_3466 node _T_3467 = bits(_WIRE_257, 18, 18) connect _WIRE_256.ae_final, _T_3467 node _T_3468 = bits(_WIRE_257, 19, 19) connect _WIRE_256.ae_ptw, _T_3468 node _T_3469 = bits(_WIRE_257, 20, 20) connect _WIRE_256.g, _T_3469 node _T_3470 = bits(_WIRE_257, 21, 21) connect _WIRE_256.u, _T_3470 node _T_3471 = bits(_WIRE_257, 41, 22) connect _WIRE_256.ppn, _T_3471 node _T_3472 = eq(superpage_entries[0].tag_v, hv_8) node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage) when _T_3473 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3474 = eq(hg_8, UInt<1>(0h0)) node _T_3475 = and(_T_3474, io.sfence.bits.rs2) when _T_3475 : wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_259 : UInt<42> connect _WIRE_259, superpage_entries[0].data[0] node _T_3476 = bits(_WIRE_259, 0, 0) connect _WIRE_258.fragmented_superpage, _T_3476 node _T_3477 = bits(_WIRE_259, 1, 1) connect _WIRE_258.c, _T_3477 node _T_3478 = bits(_WIRE_259, 2, 2) connect _WIRE_258.eff, _T_3478 node _T_3479 = bits(_WIRE_259, 3, 3) connect _WIRE_258.paa, _T_3479 node _T_3480 = bits(_WIRE_259, 4, 4) connect _WIRE_258.pal, _T_3480 node _T_3481 = bits(_WIRE_259, 5, 5) connect _WIRE_258.ppp, _T_3481 node _T_3482 = bits(_WIRE_259, 6, 6) connect _WIRE_258.pr, _T_3482 node _T_3483 = bits(_WIRE_259, 7, 7) connect _WIRE_258.px, _T_3483 node _T_3484 = bits(_WIRE_259, 8, 8) connect _WIRE_258.pw, _T_3484 node _T_3485 = bits(_WIRE_259, 9, 9) connect _WIRE_258.hr, _T_3485 node _T_3486 = bits(_WIRE_259, 10, 10) connect _WIRE_258.hx, _T_3486 node _T_3487 = bits(_WIRE_259, 11, 11) connect _WIRE_258.hw, _T_3487 node _T_3488 = bits(_WIRE_259, 12, 12) connect _WIRE_258.sr, _T_3488 node _T_3489 = bits(_WIRE_259, 13, 13) connect _WIRE_258.sx, _T_3489 node _T_3490 = bits(_WIRE_259, 14, 14) connect _WIRE_258.sw, _T_3490 node _T_3491 = bits(_WIRE_259, 15, 15) connect _WIRE_258.gf, _T_3491 node _T_3492 = bits(_WIRE_259, 16, 16) connect _WIRE_258.pf, _T_3492 node _T_3493 = bits(_WIRE_259, 17, 17) connect _WIRE_258.ae_stage2, _T_3493 node _T_3494 = bits(_WIRE_259, 18, 18) connect _WIRE_258.ae_final, _T_3494 node _T_3495 = bits(_WIRE_259, 19, 19) connect _WIRE_258.ae_ptw, _T_3495 node _T_3496 = bits(_WIRE_259, 20, 20) connect _WIRE_258.g, _T_3496 node _T_3497 = bits(_WIRE_259, 21, 21) connect _WIRE_258.u, _T_3497 node _T_3498 = bits(_WIRE_259, 41, 22) connect _WIRE_258.ppn, _T_3498 node _T_3499 = eq(superpage_entries[0].tag_v, hv_8) node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0)) node _T_3501 = and(_T_3499, _T_3500) when _T_3501 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_3502 = or(hv_8, hg_8) wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_261 : UInt<42> connect _WIRE_261, superpage_entries[0].data[0] node _T_3503 = bits(_WIRE_261, 0, 0) connect _WIRE_260.fragmented_superpage, _T_3503 node _T_3504 = bits(_WIRE_261, 1, 1) connect _WIRE_260.c, _T_3504 node _T_3505 = bits(_WIRE_261, 2, 2) connect _WIRE_260.eff, _T_3505 node _T_3506 = bits(_WIRE_261, 3, 3) connect _WIRE_260.paa, _T_3506 node _T_3507 = bits(_WIRE_261, 4, 4) connect _WIRE_260.pal, _T_3507 node _T_3508 = bits(_WIRE_261, 5, 5) connect _WIRE_260.ppp, _T_3508 node _T_3509 = bits(_WIRE_261, 6, 6) connect _WIRE_260.pr, _T_3509 node _T_3510 = bits(_WIRE_261, 7, 7) connect _WIRE_260.px, _T_3510 node _T_3511 = bits(_WIRE_261, 8, 8) connect _WIRE_260.pw, _T_3511 node _T_3512 = bits(_WIRE_261, 9, 9) connect _WIRE_260.hr, _T_3512 node _T_3513 = bits(_WIRE_261, 10, 10) connect _WIRE_260.hx, _T_3513 node _T_3514 = bits(_WIRE_261, 11, 11) connect _WIRE_260.hw, _T_3514 node _T_3515 = bits(_WIRE_261, 12, 12) connect _WIRE_260.sr, _T_3515 node _T_3516 = bits(_WIRE_261, 13, 13) connect _WIRE_260.sx, _T_3516 node _T_3517 = bits(_WIRE_261, 14, 14) connect _WIRE_260.sw, _T_3517 node _T_3518 = bits(_WIRE_261, 15, 15) connect _WIRE_260.gf, _T_3518 node _T_3519 = bits(_WIRE_261, 16, 16) connect _WIRE_260.pf, _T_3519 node _T_3520 = bits(_WIRE_261, 17, 17) connect _WIRE_260.ae_stage2, _T_3520 node _T_3521 = bits(_WIRE_261, 18, 18) connect _WIRE_260.ae_final, _T_3521 node _T_3522 = bits(_WIRE_261, 19, 19) connect _WIRE_260.ae_ptw, _T_3522 node _T_3523 = bits(_WIRE_261, 20, 20) connect _WIRE_260.g, _T_3523 node _T_3524 = bits(_WIRE_261, 21, 21) connect _WIRE_260.u, _T_3524 node _T_3525 = bits(_WIRE_261, 41, 22) connect _WIRE_260.ppn, _T_3525 node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502) when _T_3526 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3527 = eq(hg_9, UInt<1>(0h0)) node _T_3528 = and(_T_3527, io.sfence.bits.rs1) when _T_3528 : node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9) node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3530 = bits(_T_3529, 26, 18) node _T_3531 = eq(_T_3530, UInt<1>(0h0)) node _T_3532 = or(ignore_3, _T_3531) node _T_3533 = and(tagMatch_1, _T_3532) node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3535 = bits(_T_3534, 17, 9) node _T_3536 = eq(_T_3535, UInt<1>(0h0)) node _T_3537 = or(ignore_4, _T_3536) node _T_3538 = and(_T_3533, _T_3537) node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h1)) node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3540 = bits(_T_3539, 8, 0) node _T_3541 = eq(_T_3540, UInt<1>(0h0)) node _T_3542 = or(ignore_5, _T_3541) node _T_3543 = and(_T_3538, _T_3542) when _T_3543 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn) node _T_3545 = shr(_T_3544, 18) node _T_3546 = eq(_T_3545, UInt<1>(0h0)) when _T_3546 : wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_263 : UInt<42> connect _WIRE_263, superpage_entries[1].data[0] node _T_3547 = bits(_WIRE_263, 0, 0) connect _WIRE_262.fragmented_superpage, _T_3547 node _T_3548 = bits(_WIRE_263, 1, 1) connect _WIRE_262.c, _T_3548 node _T_3549 = bits(_WIRE_263, 2, 2) connect _WIRE_262.eff, _T_3549 node _T_3550 = bits(_WIRE_263, 3, 3) connect _WIRE_262.paa, _T_3550 node _T_3551 = bits(_WIRE_263, 4, 4) connect _WIRE_262.pal, _T_3551 node _T_3552 = bits(_WIRE_263, 5, 5) connect _WIRE_262.ppp, _T_3552 node _T_3553 = bits(_WIRE_263, 6, 6) connect _WIRE_262.pr, _T_3553 node _T_3554 = bits(_WIRE_263, 7, 7) connect _WIRE_262.px, _T_3554 node _T_3555 = bits(_WIRE_263, 8, 8) connect _WIRE_262.pw, _T_3555 node _T_3556 = bits(_WIRE_263, 9, 9) connect _WIRE_262.hr, _T_3556 node _T_3557 = bits(_WIRE_263, 10, 10) connect _WIRE_262.hx, _T_3557 node _T_3558 = bits(_WIRE_263, 11, 11) connect _WIRE_262.hw, _T_3558 node _T_3559 = bits(_WIRE_263, 12, 12) connect _WIRE_262.sr, _T_3559 node _T_3560 = bits(_WIRE_263, 13, 13) connect _WIRE_262.sx, _T_3560 node _T_3561 = bits(_WIRE_263, 14, 14) connect _WIRE_262.sw, _T_3561 node _T_3562 = bits(_WIRE_263, 15, 15) connect _WIRE_262.gf, _T_3562 node _T_3563 = bits(_WIRE_263, 16, 16) connect _WIRE_262.pf, _T_3563 node _T_3564 = bits(_WIRE_263, 17, 17) connect _WIRE_262.ae_stage2, _T_3564 node _T_3565 = bits(_WIRE_263, 18, 18) connect _WIRE_262.ae_final, _T_3565 node _T_3566 = bits(_WIRE_263, 19, 19) connect _WIRE_262.ae_ptw, _T_3566 node _T_3567 = bits(_WIRE_263, 20, 20) connect _WIRE_262.g, _T_3567 node _T_3568 = bits(_WIRE_263, 21, 21) connect _WIRE_262.u, _T_3568 node _T_3569 = bits(_WIRE_263, 41, 22) connect _WIRE_262.ppn, _T_3569 node _T_3570 = eq(superpage_entries[1].tag_v, hv_9) node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage) when _T_3571 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3572 = eq(hg_9, UInt<1>(0h0)) node _T_3573 = and(_T_3572, io.sfence.bits.rs2) when _T_3573 : wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_265 : UInt<42> connect _WIRE_265, superpage_entries[1].data[0] node _T_3574 = bits(_WIRE_265, 0, 0) connect _WIRE_264.fragmented_superpage, _T_3574 node _T_3575 = bits(_WIRE_265, 1, 1) connect _WIRE_264.c, _T_3575 node _T_3576 = bits(_WIRE_265, 2, 2) connect _WIRE_264.eff, _T_3576 node _T_3577 = bits(_WIRE_265, 3, 3) connect _WIRE_264.paa, _T_3577 node _T_3578 = bits(_WIRE_265, 4, 4) connect _WIRE_264.pal, _T_3578 node _T_3579 = bits(_WIRE_265, 5, 5) connect _WIRE_264.ppp, _T_3579 node _T_3580 = bits(_WIRE_265, 6, 6) connect _WIRE_264.pr, _T_3580 node _T_3581 = bits(_WIRE_265, 7, 7) connect _WIRE_264.px, _T_3581 node _T_3582 = bits(_WIRE_265, 8, 8) connect _WIRE_264.pw, _T_3582 node _T_3583 = bits(_WIRE_265, 9, 9) connect _WIRE_264.hr, _T_3583 node _T_3584 = bits(_WIRE_265, 10, 10) connect _WIRE_264.hx, _T_3584 node _T_3585 = bits(_WIRE_265, 11, 11) connect _WIRE_264.hw, _T_3585 node _T_3586 = bits(_WIRE_265, 12, 12) connect _WIRE_264.sr, _T_3586 node _T_3587 = bits(_WIRE_265, 13, 13) connect _WIRE_264.sx, _T_3587 node _T_3588 = bits(_WIRE_265, 14, 14) connect _WIRE_264.sw, _T_3588 node _T_3589 = bits(_WIRE_265, 15, 15) connect _WIRE_264.gf, _T_3589 node _T_3590 = bits(_WIRE_265, 16, 16) connect _WIRE_264.pf, _T_3590 node _T_3591 = bits(_WIRE_265, 17, 17) connect _WIRE_264.ae_stage2, _T_3591 node _T_3592 = bits(_WIRE_265, 18, 18) connect _WIRE_264.ae_final, _T_3592 node _T_3593 = bits(_WIRE_265, 19, 19) connect _WIRE_264.ae_ptw, _T_3593 node _T_3594 = bits(_WIRE_265, 20, 20) connect _WIRE_264.g, _T_3594 node _T_3595 = bits(_WIRE_265, 21, 21) connect _WIRE_264.u, _T_3595 node _T_3596 = bits(_WIRE_265, 41, 22) connect _WIRE_264.ppn, _T_3596 node _T_3597 = eq(superpage_entries[1].tag_v, hv_9) node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0)) node _T_3599 = and(_T_3597, _T_3598) when _T_3599 : connect superpage_entries[1].valid[0], UInt<1>(0h0) else : node _T_3600 = or(hv_9, hg_9) wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_267 : UInt<42> connect _WIRE_267, superpage_entries[1].data[0] node _T_3601 = bits(_WIRE_267, 0, 0) connect _WIRE_266.fragmented_superpage, _T_3601 node _T_3602 = bits(_WIRE_267, 1, 1) connect _WIRE_266.c, _T_3602 node _T_3603 = bits(_WIRE_267, 2, 2) connect _WIRE_266.eff, _T_3603 node _T_3604 = bits(_WIRE_267, 3, 3) connect _WIRE_266.paa, _T_3604 node _T_3605 = bits(_WIRE_267, 4, 4) connect _WIRE_266.pal, _T_3605 node _T_3606 = bits(_WIRE_267, 5, 5) connect _WIRE_266.ppp, _T_3606 node _T_3607 = bits(_WIRE_267, 6, 6) connect _WIRE_266.pr, _T_3607 node _T_3608 = bits(_WIRE_267, 7, 7) connect _WIRE_266.px, _T_3608 node _T_3609 = bits(_WIRE_267, 8, 8) connect _WIRE_266.pw, _T_3609 node _T_3610 = bits(_WIRE_267, 9, 9) connect _WIRE_266.hr, _T_3610 node _T_3611 = bits(_WIRE_267, 10, 10) connect _WIRE_266.hx, _T_3611 node _T_3612 = bits(_WIRE_267, 11, 11) connect _WIRE_266.hw, _T_3612 node _T_3613 = bits(_WIRE_267, 12, 12) connect _WIRE_266.sr, _T_3613 node _T_3614 = bits(_WIRE_267, 13, 13) connect _WIRE_266.sx, _T_3614 node _T_3615 = bits(_WIRE_267, 14, 14) connect _WIRE_266.sw, _T_3615 node _T_3616 = bits(_WIRE_267, 15, 15) connect _WIRE_266.gf, _T_3616 node _T_3617 = bits(_WIRE_267, 16, 16) connect _WIRE_266.pf, _T_3617 node _T_3618 = bits(_WIRE_267, 17, 17) connect _WIRE_266.ae_stage2, _T_3618 node _T_3619 = bits(_WIRE_267, 18, 18) connect _WIRE_266.ae_final, _T_3619 node _T_3620 = bits(_WIRE_267, 19, 19) connect _WIRE_266.ae_ptw, _T_3620 node _T_3621 = bits(_WIRE_267, 20, 20) connect _WIRE_266.g, _T_3621 node _T_3622 = bits(_WIRE_267, 21, 21) connect _WIRE_266.u, _T_3622 node _T_3623 = bits(_WIRE_267, 41, 22) connect _WIRE_266.ppn, _T_3623 node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600) when _T_3624 : connect superpage_entries[1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3625 = eq(hg_10, UInt<1>(0h0)) node _T_3626 = and(_T_3625, io.sfence.bits.rs1) when _T_3626 : node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10) node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2) node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0)) node ignore_6 = or(_ignore_T_6, UInt<1>(0h0)) node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3628 = bits(_T_3627, 26, 18) node _T_3629 = eq(_T_3628, UInt<1>(0h0)) node _T_3630 = or(ignore_6, _T_3629) node _T_3631 = and(tagMatch_2, _T_3630) node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1)) node ignore_7 = or(_ignore_T_7, UInt<1>(0h0)) node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3633 = bits(_T_3632, 17, 9) node _T_3634 = eq(_T_3633, UInt<1>(0h0)) node _T_3635 = or(ignore_7, _T_3634) node _T_3636 = and(_T_3631, _T_3635) node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2)) node ignore_8 = or(_ignore_T_8, UInt<1>(0h1)) node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3638 = bits(_T_3637, 8, 0) node _T_3639 = eq(_T_3638, UInt<1>(0h0)) node _T_3640 = or(ignore_8, _T_3639) node _T_3641 = and(_T_3636, _T_3640) when _T_3641 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn) node _T_3643 = shr(_T_3642, 18) node _T_3644 = eq(_T_3643, UInt<1>(0h0)) when _T_3644 : wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_269 : UInt<42> connect _WIRE_269, superpage_entries[2].data[0] node _T_3645 = bits(_WIRE_269, 0, 0) connect _WIRE_268.fragmented_superpage, _T_3645 node _T_3646 = bits(_WIRE_269, 1, 1) connect _WIRE_268.c, _T_3646 node _T_3647 = bits(_WIRE_269, 2, 2) connect _WIRE_268.eff, _T_3647 node _T_3648 = bits(_WIRE_269, 3, 3) connect _WIRE_268.paa, _T_3648 node _T_3649 = bits(_WIRE_269, 4, 4) connect _WIRE_268.pal, _T_3649 node _T_3650 = bits(_WIRE_269, 5, 5) connect _WIRE_268.ppp, _T_3650 node _T_3651 = bits(_WIRE_269, 6, 6) connect _WIRE_268.pr, _T_3651 node _T_3652 = bits(_WIRE_269, 7, 7) connect _WIRE_268.px, _T_3652 node _T_3653 = bits(_WIRE_269, 8, 8) connect _WIRE_268.pw, _T_3653 node _T_3654 = bits(_WIRE_269, 9, 9) connect _WIRE_268.hr, _T_3654 node _T_3655 = bits(_WIRE_269, 10, 10) connect _WIRE_268.hx, _T_3655 node _T_3656 = bits(_WIRE_269, 11, 11) connect _WIRE_268.hw, _T_3656 node _T_3657 = bits(_WIRE_269, 12, 12) connect _WIRE_268.sr, _T_3657 node _T_3658 = bits(_WIRE_269, 13, 13) connect _WIRE_268.sx, _T_3658 node _T_3659 = bits(_WIRE_269, 14, 14) connect _WIRE_268.sw, _T_3659 node _T_3660 = bits(_WIRE_269, 15, 15) connect _WIRE_268.gf, _T_3660 node _T_3661 = bits(_WIRE_269, 16, 16) connect _WIRE_268.pf, _T_3661 node _T_3662 = bits(_WIRE_269, 17, 17) connect _WIRE_268.ae_stage2, _T_3662 node _T_3663 = bits(_WIRE_269, 18, 18) connect _WIRE_268.ae_final, _T_3663 node _T_3664 = bits(_WIRE_269, 19, 19) connect _WIRE_268.ae_ptw, _T_3664 node _T_3665 = bits(_WIRE_269, 20, 20) connect _WIRE_268.g, _T_3665 node _T_3666 = bits(_WIRE_269, 21, 21) connect _WIRE_268.u, _T_3666 node _T_3667 = bits(_WIRE_269, 41, 22) connect _WIRE_268.ppn, _T_3667 node _T_3668 = eq(superpage_entries[2].tag_v, hv_10) node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage) when _T_3669 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3670 = eq(hg_10, UInt<1>(0h0)) node _T_3671 = and(_T_3670, io.sfence.bits.rs2) when _T_3671 : wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_271 : UInt<42> connect _WIRE_271, superpage_entries[2].data[0] node _T_3672 = bits(_WIRE_271, 0, 0) connect _WIRE_270.fragmented_superpage, _T_3672 node _T_3673 = bits(_WIRE_271, 1, 1) connect _WIRE_270.c, _T_3673 node _T_3674 = bits(_WIRE_271, 2, 2) connect _WIRE_270.eff, _T_3674 node _T_3675 = bits(_WIRE_271, 3, 3) connect _WIRE_270.paa, _T_3675 node _T_3676 = bits(_WIRE_271, 4, 4) connect _WIRE_270.pal, _T_3676 node _T_3677 = bits(_WIRE_271, 5, 5) connect _WIRE_270.ppp, _T_3677 node _T_3678 = bits(_WIRE_271, 6, 6) connect _WIRE_270.pr, _T_3678 node _T_3679 = bits(_WIRE_271, 7, 7) connect _WIRE_270.px, _T_3679 node _T_3680 = bits(_WIRE_271, 8, 8) connect _WIRE_270.pw, _T_3680 node _T_3681 = bits(_WIRE_271, 9, 9) connect _WIRE_270.hr, _T_3681 node _T_3682 = bits(_WIRE_271, 10, 10) connect _WIRE_270.hx, _T_3682 node _T_3683 = bits(_WIRE_271, 11, 11) connect _WIRE_270.hw, _T_3683 node _T_3684 = bits(_WIRE_271, 12, 12) connect _WIRE_270.sr, _T_3684 node _T_3685 = bits(_WIRE_271, 13, 13) connect _WIRE_270.sx, _T_3685 node _T_3686 = bits(_WIRE_271, 14, 14) connect _WIRE_270.sw, _T_3686 node _T_3687 = bits(_WIRE_271, 15, 15) connect _WIRE_270.gf, _T_3687 node _T_3688 = bits(_WIRE_271, 16, 16) connect _WIRE_270.pf, _T_3688 node _T_3689 = bits(_WIRE_271, 17, 17) connect _WIRE_270.ae_stage2, _T_3689 node _T_3690 = bits(_WIRE_271, 18, 18) connect _WIRE_270.ae_final, _T_3690 node _T_3691 = bits(_WIRE_271, 19, 19) connect _WIRE_270.ae_ptw, _T_3691 node _T_3692 = bits(_WIRE_271, 20, 20) connect _WIRE_270.g, _T_3692 node _T_3693 = bits(_WIRE_271, 21, 21) connect _WIRE_270.u, _T_3693 node _T_3694 = bits(_WIRE_271, 41, 22) connect _WIRE_270.ppn, _T_3694 node _T_3695 = eq(superpage_entries[2].tag_v, hv_10) node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0)) node _T_3697 = and(_T_3695, _T_3696) when _T_3697 : connect superpage_entries[2].valid[0], UInt<1>(0h0) else : node _T_3698 = or(hv_10, hg_10) wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_273 : UInt<42> connect _WIRE_273, superpage_entries[2].data[0] node _T_3699 = bits(_WIRE_273, 0, 0) connect _WIRE_272.fragmented_superpage, _T_3699 node _T_3700 = bits(_WIRE_273, 1, 1) connect _WIRE_272.c, _T_3700 node _T_3701 = bits(_WIRE_273, 2, 2) connect _WIRE_272.eff, _T_3701 node _T_3702 = bits(_WIRE_273, 3, 3) connect _WIRE_272.paa, _T_3702 node _T_3703 = bits(_WIRE_273, 4, 4) connect _WIRE_272.pal, _T_3703 node _T_3704 = bits(_WIRE_273, 5, 5) connect _WIRE_272.ppp, _T_3704 node _T_3705 = bits(_WIRE_273, 6, 6) connect _WIRE_272.pr, _T_3705 node _T_3706 = bits(_WIRE_273, 7, 7) connect _WIRE_272.px, _T_3706 node _T_3707 = bits(_WIRE_273, 8, 8) connect _WIRE_272.pw, _T_3707 node _T_3708 = bits(_WIRE_273, 9, 9) connect _WIRE_272.hr, _T_3708 node _T_3709 = bits(_WIRE_273, 10, 10) connect _WIRE_272.hx, _T_3709 node _T_3710 = bits(_WIRE_273, 11, 11) connect _WIRE_272.hw, _T_3710 node _T_3711 = bits(_WIRE_273, 12, 12) connect _WIRE_272.sr, _T_3711 node _T_3712 = bits(_WIRE_273, 13, 13) connect _WIRE_272.sx, _T_3712 node _T_3713 = bits(_WIRE_273, 14, 14) connect _WIRE_272.sw, _T_3713 node _T_3714 = bits(_WIRE_273, 15, 15) connect _WIRE_272.gf, _T_3714 node _T_3715 = bits(_WIRE_273, 16, 16) connect _WIRE_272.pf, _T_3715 node _T_3716 = bits(_WIRE_273, 17, 17) connect _WIRE_272.ae_stage2, _T_3716 node _T_3717 = bits(_WIRE_273, 18, 18) connect _WIRE_272.ae_final, _T_3717 node _T_3718 = bits(_WIRE_273, 19, 19) connect _WIRE_272.ae_ptw, _T_3718 node _T_3719 = bits(_WIRE_273, 20, 20) connect _WIRE_272.g, _T_3719 node _T_3720 = bits(_WIRE_273, 21, 21) connect _WIRE_272.u, _T_3720 node _T_3721 = bits(_WIRE_273, 41, 22) connect _WIRE_272.ppn, _T_3721 node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698) when _T_3722 : connect superpage_entries[2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3723 = eq(hg_11, UInt<1>(0h0)) node _T_3724 = and(_T_3723, io.sfence.bits.rs1) when _T_3724 : node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11) node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3) node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0)) node ignore_9 = or(_ignore_T_9, UInt<1>(0h0)) node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3726 = bits(_T_3725, 26, 18) node _T_3727 = eq(_T_3726, UInt<1>(0h0)) node _T_3728 = or(ignore_9, _T_3727) node _T_3729 = and(tagMatch_3, _T_3728) node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1)) node ignore_10 = or(_ignore_T_10, UInt<1>(0h0)) node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3731 = bits(_T_3730, 17, 9) node _T_3732 = eq(_T_3731, UInt<1>(0h0)) node _T_3733 = or(ignore_10, _T_3732) node _T_3734 = and(_T_3729, _T_3733) node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2)) node ignore_11 = or(_ignore_T_11, UInt<1>(0h1)) node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3736 = bits(_T_3735, 8, 0) node _T_3737 = eq(_T_3736, UInt<1>(0h0)) node _T_3738 = or(ignore_11, _T_3737) node _T_3739 = and(_T_3734, _T_3738) when _T_3739 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn) node _T_3741 = shr(_T_3740, 18) node _T_3742 = eq(_T_3741, UInt<1>(0h0)) when _T_3742 : wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_275 : UInt<42> connect _WIRE_275, superpage_entries[3].data[0] node _T_3743 = bits(_WIRE_275, 0, 0) connect _WIRE_274.fragmented_superpage, _T_3743 node _T_3744 = bits(_WIRE_275, 1, 1) connect _WIRE_274.c, _T_3744 node _T_3745 = bits(_WIRE_275, 2, 2) connect _WIRE_274.eff, _T_3745 node _T_3746 = bits(_WIRE_275, 3, 3) connect _WIRE_274.paa, _T_3746 node _T_3747 = bits(_WIRE_275, 4, 4) connect _WIRE_274.pal, _T_3747 node _T_3748 = bits(_WIRE_275, 5, 5) connect _WIRE_274.ppp, _T_3748 node _T_3749 = bits(_WIRE_275, 6, 6) connect _WIRE_274.pr, _T_3749 node _T_3750 = bits(_WIRE_275, 7, 7) connect _WIRE_274.px, _T_3750 node _T_3751 = bits(_WIRE_275, 8, 8) connect _WIRE_274.pw, _T_3751 node _T_3752 = bits(_WIRE_275, 9, 9) connect _WIRE_274.hr, _T_3752 node _T_3753 = bits(_WIRE_275, 10, 10) connect _WIRE_274.hx, _T_3753 node _T_3754 = bits(_WIRE_275, 11, 11) connect _WIRE_274.hw, _T_3754 node _T_3755 = bits(_WIRE_275, 12, 12) connect _WIRE_274.sr, _T_3755 node _T_3756 = bits(_WIRE_275, 13, 13) connect _WIRE_274.sx, _T_3756 node _T_3757 = bits(_WIRE_275, 14, 14) connect _WIRE_274.sw, _T_3757 node _T_3758 = bits(_WIRE_275, 15, 15) connect _WIRE_274.gf, _T_3758 node _T_3759 = bits(_WIRE_275, 16, 16) connect _WIRE_274.pf, _T_3759 node _T_3760 = bits(_WIRE_275, 17, 17) connect _WIRE_274.ae_stage2, _T_3760 node _T_3761 = bits(_WIRE_275, 18, 18) connect _WIRE_274.ae_final, _T_3761 node _T_3762 = bits(_WIRE_275, 19, 19) connect _WIRE_274.ae_ptw, _T_3762 node _T_3763 = bits(_WIRE_275, 20, 20) connect _WIRE_274.g, _T_3763 node _T_3764 = bits(_WIRE_275, 21, 21) connect _WIRE_274.u, _T_3764 node _T_3765 = bits(_WIRE_275, 41, 22) connect _WIRE_274.ppn, _T_3765 node _T_3766 = eq(superpage_entries[3].tag_v, hv_11) node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage) when _T_3767 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3768 = eq(hg_11, UInt<1>(0h0)) node _T_3769 = and(_T_3768, io.sfence.bits.rs2) when _T_3769 : wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_277 : UInt<42> connect _WIRE_277, superpage_entries[3].data[0] node _T_3770 = bits(_WIRE_277, 0, 0) connect _WIRE_276.fragmented_superpage, _T_3770 node _T_3771 = bits(_WIRE_277, 1, 1) connect _WIRE_276.c, _T_3771 node _T_3772 = bits(_WIRE_277, 2, 2) connect _WIRE_276.eff, _T_3772 node _T_3773 = bits(_WIRE_277, 3, 3) connect _WIRE_276.paa, _T_3773 node _T_3774 = bits(_WIRE_277, 4, 4) connect _WIRE_276.pal, _T_3774 node _T_3775 = bits(_WIRE_277, 5, 5) connect _WIRE_276.ppp, _T_3775 node _T_3776 = bits(_WIRE_277, 6, 6) connect _WIRE_276.pr, _T_3776 node _T_3777 = bits(_WIRE_277, 7, 7) connect _WIRE_276.px, _T_3777 node _T_3778 = bits(_WIRE_277, 8, 8) connect _WIRE_276.pw, _T_3778 node _T_3779 = bits(_WIRE_277, 9, 9) connect _WIRE_276.hr, _T_3779 node _T_3780 = bits(_WIRE_277, 10, 10) connect _WIRE_276.hx, _T_3780 node _T_3781 = bits(_WIRE_277, 11, 11) connect _WIRE_276.hw, _T_3781 node _T_3782 = bits(_WIRE_277, 12, 12) connect _WIRE_276.sr, _T_3782 node _T_3783 = bits(_WIRE_277, 13, 13) connect _WIRE_276.sx, _T_3783 node _T_3784 = bits(_WIRE_277, 14, 14) connect _WIRE_276.sw, _T_3784 node _T_3785 = bits(_WIRE_277, 15, 15) connect _WIRE_276.gf, _T_3785 node _T_3786 = bits(_WIRE_277, 16, 16) connect _WIRE_276.pf, _T_3786 node _T_3787 = bits(_WIRE_277, 17, 17) connect _WIRE_276.ae_stage2, _T_3787 node _T_3788 = bits(_WIRE_277, 18, 18) connect _WIRE_276.ae_final, _T_3788 node _T_3789 = bits(_WIRE_277, 19, 19) connect _WIRE_276.ae_ptw, _T_3789 node _T_3790 = bits(_WIRE_277, 20, 20) connect _WIRE_276.g, _T_3790 node _T_3791 = bits(_WIRE_277, 21, 21) connect _WIRE_276.u, _T_3791 node _T_3792 = bits(_WIRE_277, 41, 22) connect _WIRE_276.ppn, _T_3792 node _T_3793 = eq(superpage_entries[3].tag_v, hv_11) node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0)) node _T_3795 = and(_T_3793, _T_3794) when _T_3795 : connect superpage_entries[3].valid[0], UInt<1>(0h0) else : node _T_3796 = or(hv_11, hg_11) wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_279 : UInt<42> connect _WIRE_279, superpage_entries[3].data[0] node _T_3797 = bits(_WIRE_279, 0, 0) connect _WIRE_278.fragmented_superpage, _T_3797 node _T_3798 = bits(_WIRE_279, 1, 1) connect _WIRE_278.c, _T_3798 node _T_3799 = bits(_WIRE_279, 2, 2) connect _WIRE_278.eff, _T_3799 node _T_3800 = bits(_WIRE_279, 3, 3) connect _WIRE_278.paa, _T_3800 node _T_3801 = bits(_WIRE_279, 4, 4) connect _WIRE_278.pal, _T_3801 node _T_3802 = bits(_WIRE_279, 5, 5) connect _WIRE_278.ppp, _T_3802 node _T_3803 = bits(_WIRE_279, 6, 6) connect _WIRE_278.pr, _T_3803 node _T_3804 = bits(_WIRE_279, 7, 7) connect _WIRE_278.px, _T_3804 node _T_3805 = bits(_WIRE_279, 8, 8) connect _WIRE_278.pw, _T_3805 node _T_3806 = bits(_WIRE_279, 9, 9) connect _WIRE_278.hr, _T_3806 node _T_3807 = bits(_WIRE_279, 10, 10) connect _WIRE_278.hx, _T_3807 node _T_3808 = bits(_WIRE_279, 11, 11) connect _WIRE_278.hw, _T_3808 node _T_3809 = bits(_WIRE_279, 12, 12) connect _WIRE_278.sr, _T_3809 node _T_3810 = bits(_WIRE_279, 13, 13) connect _WIRE_278.sx, _T_3810 node _T_3811 = bits(_WIRE_279, 14, 14) connect _WIRE_278.sw, _T_3811 node _T_3812 = bits(_WIRE_279, 15, 15) connect _WIRE_278.gf, _T_3812 node _T_3813 = bits(_WIRE_279, 16, 16) connect _WIRE_278.pf, _T_3813 node _T_3814 = bits(_WIRE_279, 17, 17) connect _WIRE_278.ae_stage2, _T_3814 node _T_3815 = bits(_WIRE_279, 18, 18) connect _WIRE_278.ae_final, _T_3815 node _T_3816 = bits(_WIRE_279, 19, 19) connect _WIRE_278.ae_ptw, _T_3816 node _T_3817 = bits(_WIRE_279, 20, 20) connect _WIRE_278.g, _T_3817 node _T_3818 = bits(_WIRE_279, 21, 21) connect _WIRE_278.u, _T_3818 node _T_3819 = bits(_WIRE_279, 41, 22) connect _WIRE_278.ppn, _T_3819 node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796) when _T_3820 : connect superpage_entries[3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_3821 = eq(hg_12, UInt<1>(0h0)) node _T_3822 = and(_T_3821, io.sfence.bits.rs1) when _T_3822 : node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12) node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4) node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0)) node ignore_12 = or(_ignore_T_12, UInt<1>(0h0)) node _T_3823 = xor(special_entry.tag_vpn, vpn) node _T_3824 = bits(_T_3823, 26, 18) node _T_3825 = eq(_T_3824, UInt<1>(0h0)) node _T_3826 = or(ignore_12, _T_3825) node _T_3827 = and(tagMatch_4, _T_3826) node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1)) node ignore_13 = or(_ignore_T_13, UInt<1>(0h0)) node _T_3828 = xor(special_entry.tag_vpn, vpn) node _T_3829 = bits(_T_3828, 17, 9) node _T_3830 = eq(_T_3829, UInt<1>(0h0)) node _T_3831 = or(ignore_13, _T_3830) node _T_3832 = and(_T_3827, _T_3831) node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2)) node ignore_14 = or(_ignore_T_14, UInt<1>(0h0)) node _T_3833 = xor(special_entry.tag_vpn, vpn) node _T_3834 = bits(_T_3833, 8, 0) node _T_3835 = eq(_T_3834, UInt<1>(0h0)) node _T_3836 = or(ignore_14, _T_3835) node _T_3837 = and(_T_3832, _T_3836) when _T_3837 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3838 = xor(special_entry.tag_vpn, vpn) node _T_3839 = shr(_T_3838, 18) node _T_3840 = eq(_T_3839, UInt<1>(0h0)) when _T_3840 : wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_281 : UInt<42> connect _WIRE_281, special_entry.data[0] node _T_3841 = bits(_WIRE_281, 0, 0) connect _WIRE_280.fragmented_superpage, _T_3841 node _T_3842 = bits(_WIRE_281, 1, 1) connect _WIRE_280.c, _T_3842 node _T_3843 = bits(_WIRE_281, 2, 2) connect _WIRE_280.eff, _T_3843 node _T_3844 = bits(_WIRE_281, 3, 3) connect _WIRE_280.paa, _T_3844 node _T_3845 = bits(_WIRE_281, 4, 4) connect _WIRE_280.pal, _T_3845 node _T_3846 = bits(_WIRE_281, 5, 5) connect _WIRE_280.ppp, _T_3846 node _T_3847 = bits(_WIRE_281, 6, 6) connect _WIRE_280.pr, _T_3847 node _T_3848 = bits(_WIRE_281, 7, 7) connect _WIRE_280.px, _T_3848 node _T_3849 = bits(_WIRE_281, 8, 8) connect _WIRE_280.pw, _T_3849 node _T_3850 = bits(_WIRE_281, 9, 9) connect _WIRE_280.hr, _T_3850 node _T_3851 = bits(_WIRE_281, 10, 10) connect _WIRE_280.hx, _T_3851 node _T_3852 = bits(_WIRE_281, 11, 11) connect _WIRE_280.hw, _T_3852 node _T_3853 = bits(_WIRE_281, 12, 12) connect _WIRE_280.sr, _T_3853 node _T_3854 = bits(_WIRE_281, 13, 13) connect _WIRE_280.sx, _T_3854 node _T_3855 = bits(_WIRE_281, 14, 14) connect _WIRE_280.sw, _T_3855 node _T_3856 = bits(_WIRE_281, 15, 15) connect _WIRE_280.gf, _T_3856 node _T_3857 = bits(_WIRE_281, 16, 16) connect _WIRE_280.pf, _T_3857 node _T_3858 = bits(_WIRE_281, 17, 17) connect _WIRE_280.ae_stage2, _T_3858 node _T_3859 = bits(_WIRE_281, 18, 18) connect _WIRE_280.ae_final, _T_3859 node _T_3860 = bits(_WIRE_281, 19, 19) connect _WIRE_280.ae_ptw, _T_3860 node _T_3861 = bits(_WIRE_281, 20, 20) connect _WIRE_280.g, _T_3861 node _T_3862 = bits(_WIRE_281, 21, 21) connect _WIRE_280.u, _T_3862 node _T_3863 = bits(_WIRE_281, 41, 22) connect _WIRE_280.ppn, _T_3863 node _T_3864 = eq(special_entry.tag_v, hv_12) node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage) when _T_3865 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3866 = eq(hg_12, UInt<1>(0h0)) node _T_3867 = and(_T_3866, io.sfence.bits.rs2) when _T_3867 : wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_283 : UInt<42> connect _WIRE_283, special_entry.data[0] node _T_3868 = bits(_WIRE_283, 0, 0) connect _WIRE_282.fragmented_superpage, _T_3868 node _T_3869 = bits(_WIRE_283, 1, 1) connect _WIRE_282.c, _T_3869 node _T_3870 = bits(_WIRE_283, 2, 2) connect _WIRE_282.eff, _T_3870 node _T_3871 = bits(_WIRE_283, 3, 3) connect _WIRE_282.paa, _T_3871 node _T_3872 = bits(_WIRE_283, 4, 4) connect _WIRE_282.pal, _T_3872 node _T_3873 = bits(_WIRE_283, 5, 5) connect _WIRE_282.ppp, _T_3873 node _T_3874 = bits(_WIRE_283, 6, 6) connect _WIRE_282.pr, _T_3874 node _T_3875 = bits(_WIRE_283, 7, 7) connect _WIRE_282.px, _T_3875 node _T_3876 = bits(_WIRE_283, 8, 8) connect _WIRE_282.pw, _T_3876 node _T_3877 = bits(_WIRE_283, 9, 9) connect _WIRE_282.hr, _T_3877 node _T_3878 = bits(_WIRE_283, 10, 10) connect _WIRE_282.hx, _T_3878 node _T_3879 = bits(_WIRE_283, 11, 11) connect _WIRE_282.hw, _T_3879 node _T_3880 = bits(_WIRE_283, 12, 12) connect _WIRE_282.sr, _T_3880 node _T_3881 = bits(_WIRE_283, 13, 13) connect _WIRE_282.sx, _T_3881 node _T_3882 = bits(_WIRE_283, 14, 14) connect _WIRE_282.sw, _T_3882 node _T_3883 = bits(_WIRE_283, 15, 15) connect _WIRE_282.gf, _T_3883 node _T_3884 = bits(_WIRE_283, 16, 16) connect _WIRE_282.pf, _T_3884 node _T_3885 = bits(_WIRE_283, 17, 17) connect _WIRE_282.ae_stage2, _T_3885 node _T_3886 = bits(_WIRE_283, 18, 18) connect _WIRE_282.ae_final, _T_3886 node _T_3887 = bits(_WIRE_283, 19, 19) connect _WIRE_282.ae_ptw, _T_3887 node _T_3888 = bits(_WIRE_283, 20, 20) connect _WIRE_282.g, _T_3888 node _T_3889 = bits(_WIRE_283, 21, 21) connect _WIRE_282.u, _T_3889 node _T_3890 = bits(_WIRE_283, 41, 22) connect _WIRE_282.ppn, _T_3890 node _T_3891 = eq(special_entry.tag_v, hv_12) node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0)) node _T_3893 = and(_T_3891, _T_3892) when _T_3893 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_3894 = or(hv_12, hg_12) wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_285 : UInt<42> connect _WIRE_285, special_entry.data[0] node _T_3895 = bits(_WIRE_285, 0, 0) connect _WIRE_284.fragmented_superpage, _T_3895 node _T_3896 = bits(_WIRE_285, 1, 1) connect _WIRE_284.c, _T_3896 node _T_3897 = bits(_WIRE_285, 2, 2) connect _WIRE_284.eff, _T_3897 node _T_3898 = bits(_WIRE_285, 3, 3) connect _WIRE_284.paa, _T_3898 node _T_3899 = bits(_WIRE_285, 4, 4) connect _WIRE_284.pal, _T_3899 node _T_3900 = bits(_WIRE_285, 5, 5) connect _WIRE_284.ppp, _T_3900 node _T_3901 = bits(_WIRE_285, 6, 6) connect _WIRE_284.pr, _T_3901 node _T_3902 = bits(_WIRE_285, 7, 7) connect _WIRE_284.px, _T_3902 node _T_3903 = bits(_WIRE_285, 8, 8) connect _WIRE_284.pw, _T_3903 node _T_3904 = bits(_WIRE_285, 9, 9) connect _WIRE_284.hr, _T_3904 node _T_3905 = bits(_WIRE_285, 10, 10) connect _WIRE_284.hx, _T_3905 node _T_3906 = bits(_WIRE_285, 11, 11) connect _WIRE_284.hw, _T_3906 node _T_3907 = bits(_WIRE_285, 12, 12) connect _WIRE_284.sr, _T_3907 node _T_3908 = bits(_WIRE_285, 13, 13) connect _WIRE_284.sx, _T_3908 node _T_3909 = bits(_WIRE_285, 14, 14) connect _WIRE_284.sw, _T_3909 node _T_3910 = bits(_WIRE_285, 15, 15) connect _WIRE_284.gf, _T_3910 node _T_3911 = bits(_WIRE_285, 16, 16) connect _WIRE_284.pf, _T_3911 node _T_3912 = bits(_WIRE_285, 17, 17) connect _WIRE_284.ae_stage2, _T_3912 node _T_3913 = bits(_WIRE_285, 18, 18) connect _WIRE_284.ae_final, _T_3913 node _T_3914 = bits(_WIRE_285, 19, 19) connect _WIRE_284.ae_ptw, _T_3914 node _T_3915 = bits(_WIRE_285, 20, 20) connect _WIRE_284.g, _T_3915 node _T_3916 = bits(_WIRE_285, 21, 21) connect _WIRE_284.u, _T_3916 node _T_3917 = bits(_WIRE_285, 41, 22) connect _WIRE_284.ppn, _T_3917 node _T_3918 = eq(special_entry.tag_v, _T_3894) when _T_3918 : connect special_entry.valid[0], UInt<1>(0h0) node _T_3919 = and(io.req.ready, io.req.valid) node _T_3920 = and(_T_3919, vsatp_mode_mismatch) when _T_3920 : wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_287 : UInt<42> connect _WIRE_287, sectored_entries[0][0].data[0] node _T_3921 = bits(_WIRE_287, 0, 0) connect _WIRE_286.fragmented_superpage, _T_3921 node _T_3922 = bits(_WIRE_287, 1, 1) connect _WIRE_286.c, _T_3922 node _T_3923 = bits(_WIRE_287, 2, 2) connect _WIRE_286.eff, _T_3923 node _T_3924 = bits(_WIRE_287, 3, 3) connect _WIRE_286.paa, _T_3924 node _T_3925 = bits(_WIRE_287, 4, 4) connect _WIRE_286.pal, _T_3925 node _T_3926 = bits(_WIRE_287, 5, 5) connect _WIRE_286.ppp, _T_3926 node _T_3927 = bits(_WIRE_287, 6, 6) connect _WIRE_286.pr, _T_3927 node _T_3928 = bits(_WIRE_287, 7, 7) connect _WIRE_286.px, _T_3928 node _T_3929 = bits(_WIRE_287, 8, 8) connect _WIRE_286.pw, _T_3929 node _T_3930 = bits(_WIRE_287, 9, 9) connect _WIRE_286.hr, _T_3930 node _T_3931 = bits(_WIRE_287, 10, 10) connect _WIRE_286.hx, _T_3931 node _T_3932 = bits(_WIRE_287, 11, 11) connect _WIRE_286.hw, _T_3932 node _T_3933 = bits(_WIRE_287, 12, 12) connect _WIRE_286.sr, _T_3933 node _T_3934 = bits(_WIRE_287, 13, 13) connect _WIRE_286.sx, _T_3934 node _T_3935 = bits(_WIRE_287, 14, 14) connect _WIRE_286.sw, _T_3935 node _T_3936 = bits(_WIRE_287, 15, 15) connect _WIRE_286.gf, _T_3936 node _T_3937 = bits(_WIRE_287, 16, 16) connect _WIRE_286.pf, _T_3937 node _T_3938 = bits(_WIRE_287, 17, 17) connect _WIRE_286.ae_stage2, _T_3938 node _T_3939 = bits(_WIRE_287, 18, 18) connect _WIRE_286.ae_final, _T_3939 node _T_3940 = bits(_WIRE_287, 19, 19) connect _WIRE_286.ae_ptw, _T_3940 node _T_3941 = bits(_WIRE_287, 20, 20) connect _WIRE_286.g, _T_3941 node _T_3942 = bits(_WIRE_287, 21, 21) connect _WIRE_286.u, _T_3942 node _T_3943 = bits(_WIRE_287, 41, 22) connect _WIRE_286.ppn, _T_3943 wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_289 : UInt<42> connect _WIRE_289, sectored_entries[0][0].data[1] node _T_3944 = bits(_WIRE_289, 0, 0) connect _WIRE_288.fragmented_superpage, _T_3944 node _T_3945 = bits(_WIRE_289, 1, 1) connect _WIRE_288.c, _T_3945 node _T_3946 = bits(_WIRE_289, 2, 2) connect _WIRE_288.eff, _T_3946 node _T_3947 = bits(_WIRE_289, 3, 3) connect _WIRE_288.paa, _T_3947 node _T_3948 = bits(_WIRE_289, 4, 4) connect _WIRE_288.pal, _T_3948 node _T_3949 = bits(_WIRE_289, 5, 5) connect _WIRE_288.ppp, _T_3949 node _T_3950 = bits(_WIRE_289, 6, 6) connect _WIRE_288.pr, _T_3950 node _T_3951 = bits(_WIRE_289, 7, 7) connect _WIRE_288.px, _T_3951 node _T_3952 = bits(_WIRE_289, 8, 8) connect _WIRE_288.pw, _T_3952 node _T_3953 = bits(_WIRE_289, 9, 9) connect _WIRE_288.hr, _T_3953 node _T_3954 = bits(_WIRE_289, 10, 10) connect _WIRE_288.hx, _T_3954 node _T_3955 = bits(_WIRE_289, 11, 11) connect _WIRE_288.hw, _T_3955 node _T_3956 = bits(_WIRE_289, 12, 12) connect _WIRE_288.sr, _T_3956 node _T_3957 = bits(_WIRE_289, 13, 13) connect _WIRE_288.sx, _T_3957 node _T_3958 = bits(_WIRE_289, 14, 14) connect _WIRE_288.sw, _T_3958 node _T_3959 = bits(_WIRE_289, 15, 15) connect _WIRE_288.gf, _T_3959 node _T_3960 = bits(_WIRE_289, 16, 16) connect _WIRE_288.pf, _T_3960 node _T_3961 = bits(_WIRE_289, 17, 17) connect _WIRE_288.ae_stage2, _T_3961 node _T_3962 = bits(_WIRE_289, 18, 18) connect _WIRE_288.ae_final, _T_3962 node _T_3963 = bits(_WIRE_289, 19, 19) connect _WIRE_288.ae_ptw, _T_3963 node _T_3964 = bits(_WIRE_289, 20, 20) connect _WIRE_288.g, _T_3964 node _T_3965 = bits(_WIRE_289, 21, 21) connect _WIRE_288.u, _T_3965 node _T_3966 = bits(_WIRE_289, 41, 22) connect _WIRE_288.ppn, _T_3966 wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_291 : UInt<42> connect _WIRE_291, sectored_entries[0][0].data[2] node _T_3967 = bits(_WIRE_291, 0, 0) connect _WIRE_290.fragmented_superpage, _T_3967 node _T_3968 = bits(_WIRE_291, 1, 1) connect _WIRE_290.c, _T_3968 node _T_3969 = bits(_WIRE_291, 2, 2) connect _WIRE_290.eff, _T_3969 node _T_3970 = bits(_WIRE_291, 3, 3) connect _WIRE_290.paa, _T_3970 node _T_3971 = bits(_WIRE_291, 4, 4) connect _WIRE_290.pal, _T_3971 node _T_3972 = bits(_WIRE_291, 5, 5) connect _WIRE_290.ppp, _T_3972 node _T_3973 = bits(_WIRE_291, 6, 6) connect _WIRE_290.pr, _T_3973 node _T_3974 = bits(_WIRE_291, 7, 7) connect _WIRE_290.px, _T_3974 node _T_3975 = bits(_WIRE_291, 8, 8) connect _WIRE_290.pw, _T_3975 node _T_3976 = bits(_WIRE_291, 9, 9) connect _WIRE_290.hr, _T_3976 node _T_3977 = bits(_WIRE_291, 10, 10) connect _WIRE_290.hx, _T_3977 node _T_3978 = bits(_WIRE_291, 11, 11) connect _WIRE_290.hw, _T_3978 node _T_3979 = bits(_WIRE_291, 12, 12) connect _WIRE_290.sr, _T_3979 node _T_3980 = bits(_WIRE_291, 13, 13) connect _WIRE_290.sx, _T_3980 node _T_3981 = bits(_WIRE_291, 14, 14) connect _WIRE_290.sw, _T_3981 node _T_3982 = bits(_WIRE_291, 15, 15) connect _WIRE_290.gf, _T_3982 node _T_3983 = bits(_WIRE_291, 16, 16) connect _WIRE_290.pf, _T_3983 node _T_3984 = bits(_WIRE_291, 17, 17) connect _WIRE_290.ae_stage2, _T_3984 node _T_3985 = bits(_WIRE_291, 18, 18) connect _WIRE_290.ae_final, _T_3985 node _T_3986 = bits(_WIRE_291, 19, 19) connect _WIRE_290.ae_ptw, _T_3986 node _T_3987 = bits(_WIRE_291, 20, 20) connect _WIRE_290.g, _T_3987 node _T_3988 = bits(_WIRE_291, 21, 21) connect _WIRE_290.u, _T_3988 node _T_3989 = bits(_WIRE_291, 41, 22) connect _WIRE_290.ppn, _T_3989 wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_293 : UInt<42> connect _WIRE_293, sectored_entries[0][0].data[3] node _T_3990 = bits(_WIRE_293, 0, 0) connect _WIRE_292.fragmented_superpage, _T_3990 node _T_3991 = bits(_WIRE_293, 1, 1) connect _WIRE_292.c, _T_3991 node _T_3992 = bits(_WIRE_293, 2, 2) connect _WIRE_292.eff, _T_3992 node _T_3993 = bits(_WIRE_293, 3, 3) connect _WIRE_292.paa, _T_3993 node _T_3994 = bits(_WIRE_293, 4, 4) connect _WIRE_292.pal, _T_3994 node _T_3995 = bits(_WIRE_293, 5, 5) connect _WIRE_292.ppp, _T_3995 node _T_3996 = bits(_WIRE_293, 6, 6) connect _WIRE_292.pr, _T_3996 node _T_3997 = bits(_WIRE_293, 7, 7) connect _WIRE_292.px, _T_3997 node _T_3998 = bits(_WIRE_293, 8, 8) connect _WIRE_292.pw, _T_3998 node _T_3999 = bits(_WIRE_293, 9, 9) connect _WIRE_292.hr, _T_3999 node _T_4000 = bits(_WIRE_293, 10, 10) connect _WIRE_292.hx, _T_4000 node _T_4001 = bits(_WIRE_293, 11, 11) connect _WIRE_292.hw, _T_4001 node _T_4002 = bits(_WIRE_293, 12, 12) connect _WIRE_292.sr, _T_4002 node _T_4003 = bits(_WIRE_293, 13, 13) connect _WIRE_292.sx, _T_4003 node _T_4004 = bits(_WIRE_293, 14, 14) connect _WIRE_292.sw, _T_4004 node _T_4005 = bits(_WIRE_293, 15, 15) connect _WIRE_292.gf, _T_4005 node _T_4006 = bits(_WIRE_293, 16, 16) connect _WIRE_292.pf, _T_4006 node _T_4007 = bits(_WIRE_293, 17, 17) connect _WIRE_292.ae_stage2, _T_4007 node _T_4008 = bits(_WIRE_293, 18, 18) connect _WIRE_292.ae_final, _T_4008 node _T_4009 = bits(_WIRE_293, 19, 19) connect _WIRE_292.ae_ptw, _T_4009 node _T_4010 = bits(_WIRE_293, 20, 20) connect _WIRE_292.g, _T_4010 node _T_4011 = bits(_WIRE_293, 21, 21) connect _WIRE_292.u, _T_4011 node _T_4012 = bits(_WIRE_293, 41, 22) connect _WIRE_292.ppn, _T_4012 node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4013 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4014 : connect sectored_entries[0][0].valid[1], UInt<1>(0h0) node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4015 : connect sectored_entries[0][0].valid[2], UInt<1>(0h0) node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_4016 : connect sectored_entries[0][0].valid[3], UInt<1>(0h0) wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_295 : UInt<42> connect _WIRE_295, sectored_entries[0][1].data[0] node _T_4017 = bits(_WIRE_295, 0, 0) connect _WIRE_294.fragmented_superpage, _T_4017 node _T_4018 = bits(_WIRE_295, 1, 1) connect _WIRE_294.c, _T_4018 node _T_4019 = bits(_WIRE_295, 2, 2) connect _WIRE_294.eff, _T_4019 node _T_4020 = bits(_WIRE_295, 3, 3) connect _WIRE_294.paa, _T_4020 node _T_4021 = bits(_WIRE_295, 4, 4) connect _WIRE_294.pal, _T_4021 node _T_4022 = bits(_WIRE_295, 5, 5) connect _WIRE_294.ppp, _T_4022 node _T_4023 = bits(_WIRE_295, 6, 6) connect _WIRE_294.pr, _T_4023 node _T_4024 = bits(_WIRE_295, 7, 7) connect _WIRE_294.px, _T_4024 node _T_4025 = bits(_WIRE_295, 8, 8) connect _WIRE_294.pw, _T_4025 node _T_4026 = bits(_WIRE_295, 9, 9) connect _WIRE_294.hr, _T_4026 node _T_4027 = bits(_WIRE_295, 10, 10) connect _WIRE_294.hx, _T_4027 node _T_4028 = bits(_WIRE_295, 11, 11) connect _WIRE_294.hw, _T_4028 node _T_4029 = bits(_WIRE_295, 12, 12) connect _WIRE_294.sr, _T_4029 node _T_4030 = bits(_WIRE_295, 13, 13) connect _WIRE_294.sx, _T_4030 node _T_4031 = bits(_WIRE_295, 14, 14) connect _WIRE_294.sw, _T_4031 node _T_4032 = bits(_WIRE_295, 15, 15) connect _WIRE_294.gf, _T_4032 node _T_4033 = bits(_WIRE_295, 16, 16) connect _WIRE_294.pf, _T_4033 node _T_4034 = bits(_WIRE_295, 17, 17) connect _WIRE_294.ae_stage2, _T_4034 node _T_4035 = bits(_WIRE_295, 18, 18) connect _WIRE_294.ae_final, _T_4035 node _T_4036 = bits(_WIRE_295, 19, 19) connect _WIRE_294.ae_ptw, _T_4036 node _T_4037 = bits(_WIRE_295, 20, 20) connect _WIRE_294.g, _T_4037 node _T_4038 = bits(_WIRE_295, 21, 21) connect _WIRE_294.u, _T_4038 node _T_4039 = bits(_WIRE_295, 41, 22) connect _WIRE_294.ppn, _T_4039 wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_297 : UInt<42> connect _WIRE_297, sectored_entries[0][1].data[1] node _T_4040 = bits(_WIRE_297, 0, 0) connect _WIRE_296.fragmented_superpage, _T_4040 node _T_4041 = bits(_WIRE_297, 1, 1) connect _WIRE_296.c, _T_4041 node _T_4042 = bits(_WIRE_297, 2, 2) connect _WIRE_296.eff, _T_4042 node _T_4043 = bits(_WIRE_297, 3, 3) connect _WIRE_296.paa, _T_4043 node _T_4044 = bits(_WIRE_297, 4, 4) connect _WIRE_296.pal, _T_4044 node _T_4045 = bits(_WIRE_297, 5, 5) connect _WIRE_296.ppp, _T_4045 node _T_4046 = bits(_WIRE_297, 6, 6) connect _WIRE_296.pr, _T_4046 node _T_4047 = bits(_WIRE_297, 7, 7) connect _WIRE_296.px, _T_4047 node _T_4048 = bits(_WIRE_297, 8, 8) connect _WIRE_296.pw, _T_4048 node _T_4049 = bits(_WIRE_297, 9, 9) connect _WIRE_296.hr, _T_4049 node _T_4050 = bits(_WIRE_297, 10, 10) connect _WIRE_296.hx, _T_4050 node _T_4051 = bits(_WIRE_297, 11, 11) connect _WIRE_296.hw, _T_4051 node _T_4052 = bits(_WIRE_297, 12, 12) connect _WIRE_296.sr, _T_4052 node _T_4053 = bits(_WIRE_297, 13, 13) connect _WIRE_296.sx, _T_4053 node _T_4054 = bits(_WIRE_297, 14, 14) connect _WIRE_296.sw, _T_4054 node _T_4055 = bits(_WIRE_297, 15, 15) connect _WIRE_296.gf, _T_4055 node _T_4056 = bits(_WIRE_297, 16, 16) connect _WIRE_296.pf, _T_4056 node _T_4057 = bits(_WIRE_297, 17, 17) connect _WIRE_296.ae_stage2, _T_4057 node _T_4058 = bits(_WIRE_297, 18, 18) connect _WIRE_296.ae_final, _T_4058 node _T_4059 = bits(_WIRE_297, 19, 19) connect _WIRE_296.ae_ptw, _T_4059 node _T_4060 = bits(_WIRE_297, 20, 20) connect _WIRE_296.g, _T_4060 node _T_4061 = bits(_WIRE_297, 21, 21) connect _WIRE_296.u, _T_4061 node _T_4062 = bits(_WIRE_297, 41, 22) connect _WIRE_296.ppn, _T_4062 wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_299 : UInt<42> connect _WIRE_299, sectored_entries[0][1].data[2] node _T_4063 = bits(_WIRE_299, 0, 0) connect _WIRE_298.fragmented_superpage, _T_4063 node _T_4064 = bits(_WIRE_299, 1, 1) connect _WIRE_298.c, _T_4064 node _T_4065 = bits(_WIRE_299, 2, 2) connect _WIRE_298.eff, _T_4065 node _T_4066 = bits(_WIRE_299, 3, 3) connect _WIRE_298.paa, _T_4066 node _T_4067 = bits(_WIRE_299, 4, 4) connect _WIRE_298.pal, _T_4067 node _T_4068 = bits(_WIRE_299, 5, 5) connect _WIRE_298.ppp, _T_4068 node _T_4069 = bits(_WIRE_299, 6, 6) connect _WIRE_298.pr, _T_4069 node _T_4070 = bits(_WIRE_299, 7, 7) connect _WIRE_298.px, _T_4070 node _T_4071 = bits(_WIRE_299, 8, 8) connect _WIRE_298.pw, _T_4071 node _T_4072 = bits(_WIRE_299, 9, 9) connect _WIRE_298.hr, _T_4072 node _T_4073 = bits(_WIRE_299, 10, 10) connect _WIRE_298.hx, _T_4073 node _T_4074 = bits(_WIRE_299, 11, 11) connect _WIRE_298.hw, _T_4074 node _T_4075 = bits(_WIRE_299, 12, 12) connect _WIRE_298.sr, _T_4075 node _T_4076 = bits(_WIRE_299, 13, 13) connect _WIRE_298.sx, _T_4076 node _T_4077 = bits(_WIRE_299, 14, 14) connect _WIRE_298.sw, _T_4077 node _T_4078 = bits(_WIRE_299, 15, 15) connect _WIRE_298.gf, _T_4078 node _T_4079 = bits(_WIRE_299, 16, 16) connect _WIRE_298.pf, _T_4079 node _T_4080 = bits(_WIRE_299, 17, 17) connect _WIRE_298.ae_stage2, _T_4080 node _T_4081 = bits(_WIRE_299, 18, 18) connect _WIRE_298.ae_final, _T_4081 node _T_4082 = bits(_WIRE_299, 19, 19) connect _WIRE_298.ae_ptw, _T_4082 node _T_4083 = bits(_WIRE_299, 20, 20) connect _WIRE_298.g, _T_4083 node _T_4084 = bits(_WIRE_299, 21, 21) connect _WIRE_298.u, _T_4084 node _T_4085 = bits(_WIRE_299, 41, 22) connect _WIRE_298.ppn, _T_4085 wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_301 : UInt<42> connect _WIRE_301, sectored_entries[0][1].data[3] node _T_4086 = bits(_WIRE_301, 0, 0) connect _WIRE_300.fragmented_superpage, _T_4086 node _T_4087 = bits(_WIRE_301, 1, 1) connect _WIRE_300.c, _T_4087 node _T_4088 = bits(_WIRE_301, 2, 2) connect _WIRE_300.eff, _T_4088 node _T_4089 = bits(_WIRE_301, 3, 3) connect _WIRE_300.paa, _T_4089 node _T_4090 = bits(_WIRE_301, 4, 4) connect _WIRE_300.pal, _T_4090 node _T_4091 = bits(_WIRE_301, 5, 5) connect _WIRE_300.ppp, _T_4091 node _T_4092 = bits(_WIRE_301, 6, 6) connect _WIRE_300.pr, _T_4092 node _T_4093 = bits(_WIRE_301, 7, 7) connect _WIRE_300.px, _T_4093 node _T_4094 = bits(_WIRE_301, 8, 8) connect _WIRE_300.pw, _T_4094 node _T_4095 = bits(_WIRE_301, 9, 9) connect _WIRE_300.hr, _T_4095 node _T_4096 = bits(_WIRE_301, 10, 10) connect _WIRE_300.hx, _T_4096 node _T_4097 = bits(_WIRE_301, 11, 11) connect _WIRE_300.hw, _T_4097 node _T_4098 = bits(_WIRE_301, 12, 12) connect _WIRE_300.sr, _T_4098 node _T_4099 = bits(_WIRE_301, 13, 13) connect _WIRE_300.sx, _T_4099 node _T_4100 = bits(_WIRE_301, 14, 14) connect _WIRE_300.sw, _T_4100 node _T_4101 = bits(_WIRE_301, 15, 15) connect _WIRE_300.gf, _T_4101 node _T_4102 = bits(_WIRE_301, 16, 16) connect _WIRE_300.pf, _T_4102 node _T_4103 = bits(_WIRE_301, 17, 17) connect _WIRE_300.ae_stage2, _T_4103 node _T_4104 = bits(_WIRE_301, 18, 18) connect _WIRE_300.ae_final, _T_4104 node _T_4105 = bits(_WIRE_301, 19, 19) connect _WIRE_300.ae_ptw, _T_4105 node _T_4106 = bits(_WIRE_301, 20, 20) connect _WIRE_300.g, _T_4106 node _T_4107 = bits(_WIRE_301, 21, 21) connect _WIRE_300.u, _T_4107 node _T_4108 = bits(_WIRE_301, 41, 22) connect _WIRE_300.ppn, _T_4108 node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4109 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4110 : connect sectored_entries[0][1].valid[1], UInt<1>(0h0) node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4111 : connect sectored_entries[0][1].valid[2], UInt<1>(0h0) node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_4112 : connect sectored_entries[0][1].valid[3], UInt<1>(0h0) wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_303 : UInt<42> connect _WIRE_303, sectored_entries[0][2].data[0] node _T_4113 = bits(_WIRE_303, 0, 0) connect _WIRE_302.fragmented_superpage, _T_4113 node _T_4114 = bits(_WIRE_303, 1, 1) connect _WIRE_302.c, _T_4114 node _T_4115 = bits(_WIRE_303, 2, 2) connect _WIRE_302.eff, _T_4115 node _T_4116 = bits(_WIRE_303, 3, 3) connect _WIRE_302.paa, _T_4116 node _T_4117 = bits(_WIRE_303, 4, 4) connect _WIRE_302.pal, _T_4117 node _T_4118 = bits(_WIRE_303, 5, 5) connect _WIRE_302.ppp, _T_4118 node _T_4119 = bits(_WIRE_303, 6, 6) connect _WIRE_302.pr, _T_4119 node _T_4120 = bits(_WIRE_303, 7, 7) connect _WIRE_302.px, _T_4120 node _T_4121 = bits(_WIRE_303, 8, 8) connect _WIRE_302.pw, _T_4121 node _T_4122 = bits(_WIRE_303, 9, 9) connect _WIRE_302.hr, _T_4122 node _T_4123 = bits(_WIRE_303, 10, 10) connect _WIRE_302.hx, _T_4123 node _T_4124 = bits(_WIRE_303, 11, 11) connect _WIRE_302.hw, _T_4124 node _T_4125 = bits(_WIRE_303, 12, 12) connect _WIRE_302.sr, _T_4125 node _T_4126 = bits(_WIRE_303, 13, 13) connect _WIRE_302.sx, _T_4126 node _T_4127 = bits(_WIRE_303, 14, 14) connect _WIRE_302.sw, _T_4127 node _T_4128 = bits(_WIRE_303, 15, 15) connect _WIRE_302.gf, _T_4128 node _T_4129 = bits(_WIRE_303, 16, 16) connect _WIRE_302.pf, _T_4129 node _T_4130 = bits(_WIRE_303, 17, 17) connect _WIRE_302.ae_stage2, _T_4130 node _T_4131 = bits(_WIRE_303, 18, 18) connect _WIRE_302.ae_final, _T_4131 node _T_4132 = bits(_WIRE_303, 19, 19) connect _WIRE_302.ae_ptw, _T_4132 node _T_4133 = bits(_WIRE_303, 20, 20) connect _WIRE_302.g, _T_4133 node _T_4134 = bits(_WIRE_303, 21, 21) connect _WIRE_302.u, _T_4134 node _T_4135 = bits(_WIRE_303, 41, 22) connect _WIRE_302.ppn, _T_4135 wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_305 : UInt<42> connect _WIRE_305, sectored_entries[0][2].data[1] node _T_4136 = bits(_WIRE_305, 0, 0) connect _WIRE_304.fragmented_superpage, _T_4136 node _T_4137 = bits(_WIRE_305, 1, 1) connect _WIRE_304.c, _T_4137 node _T_4138 = bits(_WIRE_305, 2, 2) connect _WIRE_304.eff, _T_4138 node _T_4139 = bits(_WIRE_305, 3, 3) connect _WIRE_304.paa, _T_4139 node _T_4140 = bits(_WIRE_305, 4, 4) connect _WIRE_304.pal, _T_4140 node _T_4141 = bits(_WIRE_305, 5, 5) connect _WIRE_304.ppp, _T_4141 node _T_4142 = bits(_WIRE_305, 6, 6) connect _WIRE_304.pr, _T_4142 node _T_4143 = bits(_WIRE_305, 7, 7) connect _WIRE_304.px, _T_4143 node _T_4144 = bits(_WIRE_305, 8, 8) connect _WIRE_304.pw, _T_4144 node _T_4145 = bits(_WIRE_305, 9, 9) connect _WIRE_304.hr, _T_4145 node _T_4146 = bits(_WIRE_305, 10, 10) connect _WIRE_304.hx, _T_4146 node _T_4147 = bits(_WIRE_305, 11, 11) connect _WIRE_304.hw, _T_4147 node _T_4148 = bits(_WIRE_305, 12, 12) connect _WIRE_304.sr, _T_4148 node _T_4149 = bits(_WIRE_305, 13, 13) connect _WIRE_304.sx, _T_4149 node _T_4150 = bits(_WIRE_305, 14, 14) connect _WIRE_304.sw, _T_4150 node _T_4151 = bits(_WIRE_305, 15, 15) connect _WIRE_304.gf, _T_4151 node _T_4152 = bits(_WIRE_305, 16, 16) connect _WIRE_304.pf, _T_4152 node _T_4153 = bits(_WIRE_305, 17, 17) connect _WIRE_304.ae_stage2, _T_4153 node _T_4154 = bits(_WIRE_305, 18, 18) connect _WIRE_304.ae_final, _T_4154 node _T_4155 = bits(_WIRE_305, 19, 19) connect _WIRE_304.ae_ptw, _T_4155 node _T_4156 = bits(_WIRE_305, 20, 20) connect _WIRE_304.g, _T_4156 node _T_4157 = bits(_WIRE_305, 21, 21) connect _WIRE_304.u, _T_4157 node _T_4158 = bits(_WIRE_305, 41, 22) connect _WIRE_304.ppn, _T_4158 wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_307 : UInt<42> connect _WIRE_307, sectored_entries[0][2].data[2] node _T_4159 = bits(_WIRE_307, 0, 0) connect _WIRE_306.fragmented_superpage, _T_4159 node _T_4160 = bits(_WIRE_307, 1, 1) connect _WIRE_306.c, _T_4160 node _T_4161 = bits(_WIRE_307, 2, 2) connect _WIRE_306.eff, _T_4161 node _T_4162 = bits(_WIRE_307, 3, 3) connect _WIRE_306.paa, _T_4162 node _T_4163 = bits(_WIRE_307, 4, 4) connect _WIRE_306.pal, _T_4163 node _T_4164 = bits(_WIRE_307, 5, 5) connect _WIRE_306.ppp, _T_4164 node _T_4165 = bits(_WIRE_307, 6, 6) connect _WIRE_306.pr, _T_4165 node _T_4166 = bits(_WIRE_307, 7, 7) connect _WIRE_306.px, _T_4166 node _T_4167 = bits(_WIRE_307, 8, 8) connect _WIRE_306.pw, _T_4167 node _T_4168 = bits(_WIRE_307, 9, 9) connect _WIRE_306.hr, _T_4168 node _T_4169 = bits(_WIRE_307, 10, 10) connect _WIRE_306.hx, _T_4169 node _T_4170 = bits(_WIRE_307, 11, 11) connect _WIRE_306.hw, _T_4170 node _T_4171 = bits(_WIRE_307, 12, 12) connect _WIRE_306.sr, _T_4171 node _T_4172 = bits(_WIRE_307, 13, 13) connect _WIRE_306.sx, _T_4172 node _T_4173 = bits(_WIRE_307, 14, 14) connect _WIRE_306.sw, _T_4173 node _T_4174 = bits(_WIRE_307, 15, 15) connect _WIRE_306.gf, _T_4174 node _T_4175 = bits(_WIRE_307, 16, 16) connect _WIRE_306.pf, _T_4175 node _T_4176 = bits(_WIRE_307, 17, 17) connect _WIRE_306.ae_stage2, _T_4176 node _T_4177 = bits(_WIRE_307, 18, 18) connect _WIRE_306.ae_final, _T_4177 node _T_4178 = bits(_WIRE_307, 19, 19) connect _WIRE_306.ae_ptw, _T_4178 node _T_4179 = bits(_WIRE_307, 20, 20) connect _WIRE_306.g, _T_4179 node _T_4180 = bits(_WIRE_307, 21, 21) connect _WIRE_306.u, _T_4180 node _T_4181 = bits(_WIRE_307, 41, 22) connect _WIRE_306.ppn, _T_4181 wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_309 : UInt<42> connect _WIRE_309, sectored_entries[0][2].data[3] node _T_4182 = bits(_WIRE_309, 0, 0) connect _WIRE_308.fragmented_superpage, _T_4182 node _T_4183 = bits(_WIRE_309, 1, 1) connect _WIRE_308.c, _T_4183 node _T_4184 = bits(_WIRE_309, 2, 2) connect _WIRE_308.eff, _T_4184 node _T_4185 = bits(_WIRE_309, 3, 3) connect _WIRE_308.paa, _T_4185 node _T_4186 = bits(_WIRE_309, 4, 4) connect _WIRE_308.pal, _T_4186 node _T_4187 = bits(_WIRE_309, 5, 5) connect _WIRE_308.ppp, _T_4187 node _T_4188 = bits(_WIRE_309, 6, 6) connect _WIRE_308.pr, _T_4188 node _T_4189 = bits(_WIRE_309, 7, 7) connect _WIRE_308.px, _T_4189 node _T_4190 = bits(_WIRE_309, 8, 8) connect _WIRE_308.pw, _T_4190 node _T_4191 = bits(_WIRE_309, 9, 9) connect _WIRE_308.hr, _T_4191 node _T_4192 = bits(_WIRE_309, 10, 10) connect _WIRE_308.hx, _T_4192 node _T_4193 = bits(_WIRE_309, 11, 11) connect _WIRE_308.hw, _T_4193 node _T_4194 = bits(_WIRE_309, 12, 12) connect _WIRE_308.sr, _T_4194 node _T_4195 = bits(_WIRE_309, 13, 13) connect _WIRE_308.sx, _T_4195 node _T_4196 = bits(_WIRE_309, 14, 14) connect _WIRE_308.sw, _T_4196 node _T_4197 = bits(_WIRE_309, 15, 15) connect _WIRE_308.gf, _T_4197 node _T_4198 = bits(_WIRE_309, 16, 16) connect _WIRE_308.pf, _T_4198 node _T_4199 = bits(_WIRE_309, 17, 17) connect _WIRE_308.ae_stage2, _T_4199 node _T_4200 = bits(_WIRE_309, 18, 18) connect _WIRE_308.ae_final, _T_4200 node _T_4201 = bits(_WIRE_309, 19, 19) connect _WIRE_308.ae_ptw, _T_4201 node _T_4202 = bits(_WIRE_309, 20, 20) connect _WIRE_308.g, _T_4202 node _T_4203 = bits(_WIRE_309, 21, 21) connect _WIRE_308.u, _T_4203 node _T_4204 = bits(_WIRE_309, 41, 22) connect _WIRE_308.ppn, _T_4204 node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4205 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4206 : connect sectored_entries[0][2].valid[1], UInt<1>(0h0) node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4207 : connect sectored_entries[0][2].valid[2], UInt<1>(0h0) node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_4208 : connect sectored_entries[0][2].valid[3], UInt<1>(0h0) wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_311 : UInt<42> connect _WIRE_311, sectored_entries[0][3].data[0] node _T_4209 = bits(_WIRE_311, 0, 0) connect _WIRE_310.fragmented_superpage, _T_4209 node _T_4210 = bits(_WIRE_311, 1, 1) connect _WIRE_310.c, _T_4210 node _T_4211 = bits(_WIRE_311, 2, 2) connect _WIRE_310.eff, _T_4211 node _T_4212 = bits(_WIRE_311, 3, 3) connect _WIRE_310.paa, _T_4212 node _T_4213 = bits(_WIRE_311, 4, 4) connect _WIRE_310.pal, _T_4213 node _T_4214 = bits(_WIRE_311, 5, 5) connect _WIRE_310.ppp, _T_4214 node _T_4215 = bits(_WIRE_311, 6, 6) connect _WIRE_310.pr, _T_4215 node _T_4216 = bits(_WIRE_311, 7, 7) connect _WIRE_310.px, _T_4216 node _T_4217 = bits(_WIRE_311, 8, 8) connect _WIRE_310.pw, _T_4217 node _T_4218 = bits(_WIRE_311, 9, 9) connect _WIRE_310.hr, _T_4218 node _T_4219 = bits(_WIRE_311, 10, 10) connect _WIRE_310.hx, _T_4219 node _T_4220 = bits(_WIRE_311, 11, 11) connect _WIRE_310.hw, _T_4220 node _T_4221 = bits(_WIRE_311, 12, 12) connect _WIRE_310.sr, _T_4221 node _T_4222 = bits(_WIRE_311, 13, 13) connect _WIRE_310.sx, _T_4222 node _T_4223 = bits(_WIRE_311, 14, 14) connect _WIRE_310.sw, _T_4223 node _T_4224 = bits(_WIRE_311, 15, 15) connect _WIRE_310.gf, _T_4224 node _T_4225 = bits(_WIRE_311, 16, 16) connect _WIRE_310.pf, _T_4225 node _T_4226 = bits(_WIRE_311, 17, 17) connect _WIRE_310.ae_stage2, _T_4226 node _T_4227 = bits(_WIRE_311, 18, 18) connect _WIRE_310.ae_final, _T_4227 node _T_4228 = bits(_WIRE_311, 19, 19) connect _WIRE_310.ae_ptw, _T_4228 node _T_4229 = bits(_WIRE_311, 20, 20) connect _WIRE_310.g, _T_4229 node _T_4230 = bits(_WIRE_311, 21, 21) connect _WIRE_310.u, _T_4230 node _T_4231 = bits(_WIRE_311, 41, 22) connect _WIRE_310.ppn, _T_4231 wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_313 : UInt<42> connect _WIRE_313, sectored_entries[0][3].data[1] node _T_4232 = bits(_WIRE_313, 0, 0) connect _WIRE_312.fragmented_superpage, _T_4232 node _T_4233 = bits(_WIRE_313, 1, 1) connect _WIRE_312.c, _T_4233 node _T_4234 = bits(_WIRE_313, 2, 2) connect _WIRE_312.eff, _T_4234 node _T_4235 = bits(_WIRE_313, 3, 3) connect _WIRE_312.paa, _T_4235 node _T_4236 = bits(_WIRE_313, 4, 4) connect _WIRE_312.pal, _T_4236 node _T_4237 = bits(_WIRE_313, 5, 5) connect _WIRE_312.ppp, _T_4237 node _T_4238 = bits(_WIRE_313, 6, 6) connect _WIRE_312.pr, _T_4238 node _T_4239 = bits(_WIRE_313, 7, 7) connect _WIRE_312.px, _T_4239 node _T_4240 = bits(_WIRE_313, 8, 8) connect _WIRE_312.pw, _T_4240 node _T_4241 = bits(_WIRE_313, 9, 9) connect _WIRE_312.hr, _T_4241 node _T_4242 = bits(_WIRE_313, 10, 10) connect _WIRE_312.hx, _T_4242 node _T_4243 = bits(_WIRE_313, 11, 11) connect _WIRE_312.hw, _T_4243 node _T_4244 = bits(_WIRE_313, 12, 12) connect _WIRE_312.sr, _T_4244 node _T_4245 = bits(_WIRE_313, 13, 13) connect _WIRE_312.sx, _T_4245 node _T_4246 = bits(_WIRE_313, 14, 14) connect _WIRE_312.sw, _T_4246 node _T_4247 = bits(_WIRE_313, 15, 15) connect _WIRE_312.gf, _T_4247 node _T_4248 = bits(_WIRE_313, 16, 16) connect _WIRE_312.pf, _T_4248 node _T_4249 = bits(_WIRE_313, 17, 17) connect _WIRE_312.ae_stage2, _T_4249 node _T_4250 = bits(_WIRE_313, 18, 18) connect _WIRE_312.ae_final, _T_4250 node _T_4251 = bits(_WIRE_313, 19, 19) connect _WIRE_312.ae_ptw, _T_4251 node _T_4252 = bits(_WIRE_313, 20, 20) connect _WIRE_312.g, _T_4252 node _T_4253 = bits(_WIRE_313, 21, 21) connect _WIRE_312.u, _T_4253 node _T_4254 = bits(_WIRE_313, 41, 22) connect _WIRE_312.ppn, _T_4254 wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_315 : UInt<42> connect _WIRE_315, sectored_entries[0][3].data[2] node _T_4255 = bits(_WIRE_315, 0, 0) connect _WIRE_314.fragmented_superpage, _T_4255 node _T_4256 = bits(_WIRE_315, 1, 1) connect _WIRE_314.c, _T_4256 node _T_4257 = bits(_WIRE_315, 2, 2) connect _WIRE_314.eff, _T_4257 node _T_4258 = bits(_WIRE_315, 3, 3) connect _WIRE_314.paa, _T_4258 node _T_4259 = bits(_WIRE_315, 4, 4) connect _WIRE_314.pal, _T_4259 node _T_4260 = bits(_WIRE_315, 5, 5) connect _WIRE_314.ppp, _T_4260 node _T_4261 = bits(_WIRE_315, 6, 6) connect _WIRE_314.pr, _T_4261 node _T_4262 = bits(_WIRE_315, 7, 7) connect _WIRE_314.px, _T_4262 node _T_4263 = bits(_WIRE_315, 8, 8) connect _WIRE_314.pw, _T_4263 node _T_4264 = bits(_WIRE_315, 9, 9) connect _WIRE_314.hr, _T_4264 node _T_4265 = bits(_WIRE_315, 10, 10) connect _WIRE_314.hx, _T_4265 node _T_4266 = bits(_WIRE_315, 11, 11) connect _WIRE_314.hw, _T_4266 node _T_4267 = bits(_WIRE_315, 12, 12) connect _WIRE_314.sr, _T_4267 node _T_4268 = bits(_WIRE_315, 13, 13) connect _WIRE_314.sx, _T_4268 node _T_4269 = bits(_WIRE_315, 14, 14) connect _WIRE_314.sw, _T_4269 node _T_4270 = bits(_WIRE_315, 15, 15) connect _WIRE_314.gf, _T_4270 node _T_4271 = bits(_WIRE_315, 16, 16) connect _WIRE_314.pf, _T_4271 node _T_4272 = bits(_WIRE_315, 17, 17) connect _WIRE_314.ae_stage2, _T_4272 node _T_4273 = bits(_WIRE_315, 18, 18) connect _WIRE_314.ae_final, _T_4273 node _T_4274 = bits(_WIRE_315, 19, 19) connect _WIRE_314.ae_ptw, _T_4274 node _T_4275 = bits(_WIRE_315, 20, 20) connect _WIRE_314.g, _T_4275 node _T_4276 = bits(_WIRE_315, 21, 21) connect _WIRE_314.u, _T_4276 node _T_4277 = bits(_WIRE_315, 41, 22) connect _WIRE_314.ppn, _T_4277 wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_317 : UInt<42> connect _WIRE_317, sectored_entries[0][3].data[3] node _T_4278 = bits(_WIRE_317, 0, 0) connect _WIRE_316.fragmented_superpage, _T_4278 node _T_4279 = bits(_WIRE_317, 1, 1) connect _WIRE_316.c, _T_4279 node _T_4280 = bits(_WIRE_317, 2, 2) connect _WIRE_316.eff, _T_4280 node _T_4281 = bits(_WIRE_317, 3, 3) connect _WIRE_316.paa, _T_4281 node _T_4282 = bits(_WIRE_317, 4, 4) connect _WIRE_316.pal, _T_4282 node _T_4283 = bits(_WIRE_317, 5, 5) connect _WIRE_316.ppp, _T_4283 node _T_4284 = bits(_WIRE_317, 6, 6) connect _WIRE_316.pr, _T_4284 node _T_4285 = bits(_WIRE_317, 7, 7) connect _WIRE_316.px, _T_4285 node _T_4286 = bits(_WIRE_317, 8, 8) connect _WIRE_316.pw, _T_4286 node _T_4287 = bits(_WIRE_317, 9, 9) connect _WIRE_316.hr, _T_4287 node _T_4288 = bits(_WIRE_317, 10, 10) connect _WIRE_316.hx, _T_4288 node _T_4289 = bits(_WIRE_317, 11, 11) connect _WIRE_316.hw, _T_4289 node _T_4290 = bits(_WIRE_317, 12, 12) connect _WIRE_316.sr, _T_4290 node _T_4291 = bits(_WIRE_317, 13, 13) connect _WIRE_316.sx, _T_4291 node _T_4292 = bits(_WIRE_317, 14, 14) connect _WIRE_316.sw, _T_4292 node _T_4293 = bits(_WIRE_317, 15, 15) connect _WIRE_316.gf, _T_4293 node _T_4294 = bits(_WIRE_317, 16, 16) connect _WIRE_316.pf, _T_4294 node _T_4295 = bits(_WIRE_317, 17, 17) connect _WIRE_316.ae_stage2, _T_4295 node _T_4296 = bits(_WIRE_317, 18, 18) connect _WIRE_316.ae_final, _T_4296 node _T_4297 = bits(_WIRE_317, 19, 19) connect _WIRE_316.ae_ptw, _T_4297 node _T_4298 = bits(_WIRE_317, 20, 20) connect _WIRE_316.g, _T_4298 node _T_4299 = bits(_WIRE_317, 21, 21) connect _WIRE_316.u, _T_4299 node _T_4300 = bits(_WIRE_317, 41, 22) connect _WIRE_316.ppn, _T_4300 node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4301 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4302 : connect sectored_entries[0][3].valid[1], UInt<1>(0h0) node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4303 : connect sectored_entries[0][3].valid[2], UInt<1>(0h0) node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_4304 : connect sectored_entries[0][3].valid[3], UInt<1>(0h0) wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_319 : UInt<42> connect _WIRE_319, sectored_entries[0][4].data[0] node _T_4305 = bits(_WIRE_319, 0, 0) connect _WIRE_318.fragmented_superpage, _T_4305 node _T_4306 = bits(_WIRE_319, 1, 1) connect _WIRE_318.c, _T_4306 node _T_4307 = bits(_WIRE_319, 2, 2) connect _WIRE_318.eff, _T_4307 node _T_4308 = bits(_WIRE_319, 3, 3) connect _WIRE_318.paa, _T_4308 node _T_4309 = bits(_WIRE_319, 4, 4) connect _WIRE_318.pal, _T_4309 node _T_4310 = bits(_WIRE_319, 5, 5) connect _WIRE_318.ppp, _T_4310 node _T_4311 = bits(_WIRE_319, 6, 6) connect _WIRE_318.pr, _T_4311 node _T_4312 = bits(_WIRE_319, 7, 7) connect _WIRE_318.px, _T_4312 node _T_4313 = bits(_WIRE_319, 8, 8) connect _WIRE_318.pw, _T_4313 node _T_4314 = bits(_WIRE_319, 9, 9) connect _WIRE_318.hr, _T_4314 node _T_4315 = bits(_WIRE_319, 10, 10) connect _WIRE_318.hx, _T_4315 node _T_4316 = bits(_WIRE_319, 11, 11) connect _WIRE_318.hw, _T_4316 node _T_4317 = bits(_WIRE_319, 12, 12) connect _WIRE_318.sr, _T_4317 node _T_4318 = bits(_WIRE_319, 13, 13) connect _WIRE_318.sx, _T_4318 node _T_4319 = bits(_WIRE_319, 14, 14) connect _WIRE_318.sw, _T_4319 node _T_4320 = bits(_WIRE_319, 15, 15) connect _WIRE_318.gf, _T_4320 node _T_4321 = bits(_WIRE_319, 16, 16) connect _WIRE_318.pf, _T_4321 node _T_4322 = bits(_WIRE_319, 17, 17) connect _WIRE_318.ae_stage2, _T_4322 node _T_4323 = bits(_WIRE_319, 18, 18) connect _WIRE_318.ae_final, _T_4323 node _T_4324 = bits(_WIRE_319, 19, 19) connect _WIRE_318.ae_ptw, _T_4324 node _T_4325 = bits(_WIRE_319, 20, 20) connect _WIRE_318.g, _T_4325 node _T_4326 = bits(_WIRE_319, 21, 21) connect _WIRE_318.u, _T_4326 node _T_4327 = bits(_WIRE_319, 41, 22) connect _WIRE_318.ppn, _T_4327 wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_321 : UInt<42> connect _WIRE_321, sectored_entries[0][4].data[1] node _T_4328 = bits(_WIRE_321, 0, 0) connect _WIRE_320.fragmented_superpage, _T_4328 node _T_4329 = bits(_WIRE_321, 1, 1) connect _WIRE_320.c, _T_4329 node _T_4330 = bits(_WIRE_321, 2, 2) connect _WIRE_320.eff, _T_4330 node _T_4331 = bits(_WIRE_321, 3, 3) connect _WIRE_320.paa, _T_4331 node _T_4332 = bits(_WIRE_321, 4, 4) connect _WIRE_320.pal, _T_4332 node _T_4333 = bits(_WIRE_321, 5, 5) connect _WIRE_320.ppp, _T_4333 node _T_4334 = bits(_WIRE_321, 6, 6) connect _WIRE_320.pr, _T_4334 node _T_4335 = bits(_WIRE_321, 7, 7) connect _WIRE_320.px, _T_4335 node _T_4336 = bits(_WIRE_321, 8, 8) connect _WIRE_320.pw, _T_4336 node _T_4337 = bits(_WIRE_321, 9, 9) connect _WIRE_320.hr, _T_4337 node _T_4338 = bits(_WIRE_321, 10, 10) connect _WIRE_320.hx, _T_4338 node _T_4339 = bits(_WIRE_321, 11, 11) connect _WIRE_320.hw, _T_4339 node _T_4340 = bits(_WIRE_321, 12, 12) connect _WIRE_320.sr, _T_4340 node _T_4341 = bits(_WIRE_321, 13, 13) connect _WIRE_320.sx, _T_4341 node _T_4342 = bits(_WIRE_321, 14, 14) connect _WIRE_320.sw, _T_4342 node _T_4343 = bits(_WIRE_321, 15, 15) connect _WIRE_320.gf, _T_4343 node _T_4344 = bits(_WIRE_321, 16, 16) connect _WIRE_320.pf, _T_4344 node _T_4345 = bits(_WIRE_321, 17, 17) connect _WIRE_320.ae_stage2, _T_4345 node _T_4346 = bits(_WIRE_321, 18, 18) connect _WIRE_320.ae_final, _T_4346 node _T_4347 = bits(_WIRE_321, 19, 19) connect _WIRE_320.ae_ptw, _T_4347 node _T_4348 = bits(_WIRE_321, 20, 20) connect _WIRE_320.g, _T_4348 node _T_4349 = bits(_WIRE_321, 21, 21) connect _WIRE_320.u, _T_4349 node _T_4350 = bits(_WIRE_321, 41, 22) connect _WIRE_320.ppn, _T_4350 wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_323 : UInt<42> connect _WIRE_323, sectored_entries[0][4].data[2] node _T_4351 = bits(_WIRE_323, 0, 0) connect _WIRE_322.fragmented_superpage, _T_4351 node _T_4352 = bits(_WIRE_323, 1, 1) connect _WIRE_322.c, _T_4352 node _T_4353 = bits(_WIRE_323, 2, 2) connect _WIRE_322.eff, _T_4353 node _T_4354 = bits(_WIRE_323, 3, 3) connect _WIRE_322.paa, _T_4354 node _T_4355 = bits(_WIRE_323, 4, 4) connect _WIRE_322.pal, _T_4355 node _T_4356 = bits(_WIRE_323, 5, 5) connect _WIRE_322.ppp, _T_4356 node _T_4357 = bits(_WIRE_323, 6, 6) connect _WIRE_322.pr, _T_4357 node _T_4358 = bits(_WIRE_323, 7, 7) connect _WIRE_322.px, _T_4358 node _T_4359 = bits(_WIRE_323, 8, 8) connect _WIRE_322.pw, _T_4359 node _T_4360 = bits(_WIRE_323, 9, 9) connect _WIRE_322.hr, _T_4360 node _T_4361 = bits(_WIRE_323, 10, 10) connect _WIRE_322.hx, _T_4361 node _T_4362 = bits(_WIRE_323, 11, 11) connect _WIRE_322.hw, _T_4362 node _T_4363 = bits(_WIRE_323, 12, 12) connect _WIRE_322.sr, _T_4363 node _T_4364 = bits(_WIRE_323, 13, 13) connect _WIRE_322.sx, _T_4364 node _T_4365 = bits(_WIRE_323, 14, 14) connect _WIRE_322.sw, _T_4365 node _T_4366 = bits(_WIRE_323, 15, 15) connect _WIRE_322.gf, _T_4366 node _T_4367 = bits(_WIRE_323, 16, 16) connect _WIRE_322.pf, _T_4367 node _T_4368 = bits(_WIRE_323, 17, 17) connect _WIRE_322.ae_stage2, _T_4368 node _T_4369 = bits(_WIRE_323, 18, 18) connect _WIRE_322.ae_final, _T_4369 node _T_4370 = bits(_WIRE_323, 19, 19) connect _WIRE_322.ae_ptw, _T_4370 node _T_4371 = bits(_WIRE_323, 20, 20) connect _WIRE_322.g, _T_4371 node _T_4372 = bits(_WIRE_323, 21, 21) connect _WIRE_322.u, _T_4372 node _T_4373 = bits(_WIRE_323, 41, 22) connect _WIRE_322.ppn, _T_4373 wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_325 : UInt<42> connect _WIRE_325, sectored_entries[0][4].data[3] node _T_4374 = bits(_WIRE_325, 0, 0) connect _WIRE_324.fragmented_superpage, _T_4374 node _T_4375 = bits(_WIRE_325, 1, 1) connect _WIRE_324.c, _T_4375 node _T_4376 = bits(_WIRE_325, 2, 2) connect _WIRE_324.eff, _T_4376 node _T_4377 = bits(_WIRE_325, 3, 3) connect _WIRE_324.paa, _T_4377 node _T_4378 = bits(_WIRE_325, 4, 4) connect _WIRE_324.pal, _T_4378 node _T_4379 = bits(_WIRE_325, 5, 5) connect _WIRE_324.ppp, _T_4379 node _T_4380 = bits(_WIRE_325, 6, 6) connect _WIRE_324.pr, _T_4380 node _T_4381 = bits(_WIRE_325, 7, 7) connect _WIRE_324.px, _T_4381 node _T_4382 = bits(_WIRE_325, 8, 8) connect _WIRE_324.pw, _T_4382 node _T_4383 = bits(_WIRE_325, 9, 9) connect _WIRE_324.hr, _T_4383 node _T_4384 = bits(_WIRE_325, 10, 10) connect _WIRE_324.hx, _T_4384 node _T_4385 = bits(_WIRE_325, 11, 11) connect _WIRE_324.hw, _T_4385 node _T_4386 = bits(_WIRE_325, 12, 12) connect _WIRE_324.sr, _T_4386 node _T_4387 = bits(_WIRE_325, 13, 13) connect _WIRE_324.sx, _T_4387 node _T_4388 = bits(_WIRE_325, 14, 14) connect _WIRE_324.sw, _T_4388 node _T_4389 = bits(_WIRE_325, 15, 15) connect _WIRE_324.gf, _T_4389 node _T_4390 = bits(_WIRE_325, 16, 16) connect _WIRE_324.pf, _T_4390 node _T_4391 = bits(_WIRE_325, 17, 17) connect _WIRE_324.ae_stage2, _T_4391 node _T_4392 = bits(_WIRE_325, 18, 18) connect _WIRE_324.ae_final, _T_4392 node _T_4393 = bits(_WIRE_325, 19, 19) connect _WIRE_324.ae_ptw, _T_4393 node _T_4394 = bits(_WIRE_325, 20, 20) connect _WIRE_324.g, _T_4394 node _T_4395 = bits(_WIRE_325, 21, 21) connect _WIRE_324.u, _T_4395 node _T_4396 = bits(_WIRE_325, 41, 22) connect _WIRE_324.ppn, _T_4396 node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4397 : connect sectored_entries[0][4].valid[0], UInt<1>(0h0) node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4398 : connect sectored_entries[0][4].valid[1], UInt<1>(0h0) node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4399 : connect sectored_entries[0][4].valid[2], UInt<1>(0h0) node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1)) when _T_4400 : connect sectored_entries[0][4].valid[3], UInt<1>(0h0) wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_327 : UInt<42> connect _WIRE_327, sectored_entries[0][5].data[0] node _T_4401 = bits(_WIRE_327, 0, 0) connect _WIRE_326.fragmented_superpage, _T_4401 node _T_4402 = bits(_WIRE_327, 1, 1) connect _WIRE_326.c, _T_4402 node _T_4403 = bits(_WIRE_327, 2, 2) connect _WIRE_326.eff, _T_4403 node _T_4404 = bits(_WIRE_327, 3, 3) connect _WIRE_326.paa, _T_4404 node _T_4405 = bits(_WIRE_327, 4, 4) connect _WIRE_326.pal, _T_4405 node _T_4406 = bits(_WIRE_327, 5, 5) connect _WIRE_326.ppp, _T_4406 node _T_4407 = bits(_WIRE_327, 6, 6) connect _WIRE_326.pr, _T_4407 node _T_4408 = bits(_WIRE_327, 7, 7) connect _WIRE_326.px, _T_4408 node _T_4409 = bits(_WIRE_327, 8, 8) connect _WIRE_326.pw, _T_4409 node _T_4410 = bits(_WIRE_327, 9, 9) connect _WIRE_326.hr, _T_4410 node _T_4411 = bits(_WIRE_327, 10, 10) connect _WIRE_326.hx, _T_4411 node _T_4412 = bits(_WIRE_327, 11, 11) connect _WIRE_326.hw, _T_4412 node _T_4413 = bits(_WIRE_327, 12, 12) connect _WIRE_326.sr, _T_4413 node _T_4414 = bits(_WIRE_327, 13, 13) connect _WIRE_326.sx, _T_4414 node _T_4415 = bits(_WIRE_327, 14, 14) connect _WIRE_326.sw, _T_4415 node _T_4416 = bits(_WIRE_327, 15, 15) connect _WIRE_326.gf, _T_4416 node _T_4417 = bits(_WIRE_327, 16, 16) connect _WIRE_326.pf, _T_4417 node _T_4418 = bits(_WIRE_327, 17, 17) connect _WIRE_326.ae_stage2, _T_4418 node _T_4419 = bits(_WIRE_327, 18, 18) connect _WIRE_326.ae_final, _T_4419 node _T_4420 = bits(_WIRE_327, 19, 19) connect _WIRE_326.ae_ptw, _T_4420 node _T_4421 = bits(_WIRE_327, 20, 20) connect _WIRE_326.g, _T_4421 node _T_4422 = bits(_WIRE_327, 21, 21) connect _WIRE_326.u, _T_4422 node _T_4423 = bits(_WIRE_327, 41, 22) connect _WIRE_326.ppn, _T_4423 wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_329 : UInt<42> connect _WIRE_329, sectored_entries[0][5].data[1] node _T_4424 = bits(_WIRE_329, 0, 0) connect _WIRE_328.fragmented_superpage, _T_4424 node _T_4425 = bits(_WIRE_329, 1, 1) connect _WIRE_328.c, _T_4425 node _T_4426 = bits(_WIRE_329, 2, 2) connect _WIRE_328.eff, _T_4426 node _T_4427 = bits(_WIRE_329, 3, 3) connect _WIRE_328.paa, _T_4427 node _T_4428 = bits(_WIRE_329, 4, 4) connect _WIRE_328.pal, _T_4428 node _T_4429 = bits(_WIRE_329, 5, 5) connect _WIRE_328.ppp, _T_4429 node _T_4430 = bits(_WIRE_329, 6, 6) connect _WIRE_328.pr, _T_4430 node _T_4431 = bits(_WIRE_329, 7, 7) connect _WIRE_328.px, _T_4431 node _T_4432 = bits(_WIRE_329, 8, 8) connect _WIRE_328.pw, _T_4432 node _T_4433 = bits(_WIRE_329, 9, 9) connect _WIRE_328.hr, _T_4433 node _T_4434 = bits(_WIRE_329, 10, 10) connect _WIRE_328.hx, _T_4434 node _T_4435 = bits(_WIRE_329, 11, 11) connect _WIRE_328.hw, _T_4435 node _T_4436 = bits(_WIRE_329, 12, 12) connect _WIRE_328.sr, _T_4436 node _T_4437 = bits(_WIRE_329, 13, 13) connect _WIRE_328.sx, _T_4437 node _T_4438 = bits(_WIRE_329, 14, 14) connect _WIRE_328.sw, _T_4438 node _T_4439 = bits(_WIRE_329, 15, 15) connect _WIRE_328.gf, _T_4439 node _T_4440 = bits(_WIRE_329, 16, 16) connect _WIRE_328.pf, _T_4440 node _T_4441 = bits(_WIRE_329, 17, 17) connect _WIRE_328.ae_stage2, _T_4441 node _T_4442 = bits(_WIRE_329, 18, 18) connect _WIRE_328.ae_final, _T_4442 node _T_4443 = bits(_WIRE_329, 19, 19) connect _WIRE_328.ae_ptw, _T_4443 node _T_4444 = bits(_WIRE_329, 20, 20) connect _WIRE_328.g, _T_4444 node _T_4445 = bits(_WIRE_329, 21, 21) connect _WIRE_328.u, _T_4445 node _T_4446 = bits(_WIRE_329, 41, 22) connect _WIRE_328.ppn, _T_4446 wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_331 : UInt<42> connect _WIRE_331, sectored_entries[0][5].data[2] node _T_4447 = bits(_WIRE_331, 0, 0) connect _WIRE_330.fragmented_superpage, _T_4447 node _T_4448 = bits(_WIRE_331, 1, 1) connect _WIRE_330.c, _T_4448 node _T_4449 = bits(_WIRE_331, 2, 2) connect _WIRE_330.eff, _T_4449 node _T_4450 = bits(_WIRE_331, 3, 3) connect _WIRE_330.paa, _T_4450 node _T_4451 = bits(_WIRE_331, 4, 4) connect _WIRE_330.pal, _T_4451 node _T_4452 = bits(_WIRE_331, 5, 5) connect _WIRE_330.ppp, _T_4452 node _T_4453 = bits(_WIRE_331, 6, 6) connect _WIRE_330.pr, _T_4453 node _T_4454 = bits(_WIRE_331, 7, 7) connect _WIRE_330.px, _T_4454 node _T_4455 = bits(_WIRE_331, 8, 8) connect _WIRE_330.pw, _T_4455 node _T_4456 = bits(_WIRE_331, 9, 9) connect _WIRE_330.hr, _T_4456 node _T_4457 = bits(_WIRE_331, 10, 10) connect _WIRE_330.hx, _T_4457 node _T_4458 = bits(_WIRE_331, 11, 11) connect _WIRE_330.hw, _T_4458 node _T_4459 = bits(_WIRE_331, 12, 12) connect _WIRE_330.sr, _T_4459 node _T_4460 = bits(_WIRE_331, 13, 13) connect _WIRE_330.sx, _T_4460 node _T_4461 = bits(_WIRE_331, 14, 14) connect _WIRE_330.sw, _T_4461 node _T_4462 = bits(_WIRE_331, 15, 15) connect _WIRE_330.gf, _T_4462 node _T_4463 = bits(_WIRE_331, 16, 16) connect _WIRE_330.pf, _T_4463 node _T_4464 = bits(_WIRE_331, 17, 17) connect _WIRE_330.ae_stage2, _T_4464 node _T_4465 = bits(_WIRE_331, 18, 18) connect _WIRE_330.ae_final, _T_4465 node _T_4466 = bits(_WIRE_331, 19, 19) connect _WIRE_330.ae_ptw, _T_4466 node _T_4467 = bits(_WIRE_331, 20, 20) connect _WIRE_330.g, _T_4467 node _T_4468 = bits(_WIRE_331, 21, 21) connect _WIRE_330.u, _T_4468 node _T_4469 = bits(_WIRE_331, 41, 22) connect _WIRE_330.ppn, _T_4469 wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_333 : UInt<42> connect _WIRE_333, sectored_entries[0][5].data[3] node _T_4470 = bits(_WIRE_333, 0, 0) connect _WIRE_332.fragmented_superpage, _T_4470 node _T_4471 = bits(_WIRE_333, 1, 1) connect _WIRE_332.c, _T_4471 node _T_4472 = bits(_WIRE_333, 2, 2) connect _WIRE_332.eff, _T_4472 node _T_4473 = bits(_WIRE_333, 3, 3) connect _WIRE_332.paa, _T_4473 node _T_4474 = bits(_WIRE_333, 4, 4) connect _WIRE_332.pal, _T_4474 node _T_4475 = bits(_WIRE_333, 5, 5) connect _WIRE_332.ppp, _T_4475 node _T_4476 = bits(_WIRE_333, 6, 6) connect _WIRE_332.pr, _T_4476 node _T_4477 = bits(_WIRE_333, 7, 7) connect _WIRE_332.px, _T_4477 node _T_4478 = bits(_WIRE_333, 8, 8) connect _WIRE_332.pw, _T_4478 node _T_4479 = bits(_WIRE_333, 9, 9) connect _WIRE_332.hr, _T_4479 node _T_4480 = bits(_WIRE_333, 10, 10) connect _WIRE_332.hx, _T_4480 node _T_4481 = bits(_WIRE_333, 11, 11) connect _WIRE_332.hw, _T_4481 node _T_4482 = bits(_WIRE_333, 12, 12) connect _WIRE_332.sr, _T_4482 node _T_4483 = bits(_WIRE_333, 13, 13) connect _WIRE_332.sx, _T_4483 node _T_4484 = bits(_WIRE_333, 14, 14) connect _WIRE_332.sw, _T_4484 node _T_4485 = bits(_WIRE_333, 15, 15) connect _WIRE_332.gf, _T_4485 node _T_4486 = bits(_WIRE_333, 16, 16) connect _WIRE_332.pf, _T_4486 node _T_4487 = bits(_WIRE_333, 17, 17) connect _WIRE_332.ae_stage2, _T_4487 node _T_4488 = bits(_WIRE_333, 18, 18) connect _WIRE_332.ae_final, _T_4488 node _T_4489 = bits(_WIRE_333, 19, 19) connect _WIRE_332.ae_ptw, _T_4489 node _T_4490 = bits(_WIRE_333, 20, 20) connect _WIRE_332.g, _T_4490 node _T_4491 = bits(_WIRE_333, 21, 21) connect _WIRE_332.u, _T_4491 node _T_4492 = bits(_WIRE_333, 41, 22) connect _WIRE_332.ppn, _T_4492 node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4493 : connect sectored_entries[0][5].valid[0], UInt<1>(0h0) node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4494 : connect sectored_entries[0][5].valid[1], UInt<1>(0h0) node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4495 : connect sectored_entries[0][5].valid[2], UInt<1>(0h0) node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1)) when _T_4496 : connect sectored_entries[0][5].valid[3], UInt<1>(0h0) wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_335 : UInt<42> connect _WIRE_335, sectored_entries[0][6].data[0] node _T_4497 = bits(_WIRE_335, 0, 0) connect _WIRE_334.fragmented_superpage, _T_4497 node _T_4498 = bits(_WIRE_335, 1, 1) connect _WIRE_334.c, _T_4498 node _T_4499 = bits(_WIRE_335, 2, 2) connect _WIRE_334.eff, _T_4499 node _T_4500 = bits(_WIRE_335, 3, 3) connect _WIRE_334.paa, _T_4500 node _T_4501 = bits(_WIRE_335, 4, 4) connect _WIRE_334.pal, _T_4501 node _T_4502 = bits(_WIRE_335, 5, 5) connect _WIRE_334.ppp, _T_4502 node _T_4503 = bits(_WIRE_335, 6, 6) connect _WIRE_334.pr, _T_4503 node _T_4504 = bits(_WIRE_335, 7, 7) connect _WIRE_334.px, _T_4504 node _T_4505 = bits(_WIRE_335, 8, 8) connect _WIRE_334.pw, _T_4505 node _T_4506 = bits(_WIRE_335, 9, 9) connect _WIRE_334.hr, _T_4506 node _T_4507 = bits(_WIRE_335, 10, 10) connect _WIRE_334.hx, _T_4507 node _T_4508 = bits(_WIRE_335, 11, 11) connect _WIRE_334.hw, _T_4508 node _T_4509 = bits(_WIRE_335, 12, 12) connect _WIRE_334.sr, _T_4509 node _T_4510 = bits(_WIRE_335, 13, 13) connect _WIRE_334.sx, _T_4510 node _T_4511 = bits(_WIRE_335, 14, 14) connect _WIRE_334.sw, _T_4511 node _T_4512 = bits(_WIRE_335, 15, 15) connect _WIRE_334.gf, _T_4512 node _T_4513 = bits(_WIRE_335, 16, 16) connect _WIRE_334.pf, _T_4513 node _T_4514 = bits(_WIRE_335, 17, 17) connect _WIRE_334.ae_stage2, _T_4514 node _T_4515 = bits(_WIRE_335, 18, 18) connect _WIRE_334.ae_final, _T_4515 node _T_4516 = bits(_WIRE_335, 19, 19) connect _WIRE_334.ae_ptw, _T_4516 node _T_4517 = bits(_WIRE_335, 20, 20) connect _WIRE_334.g, _T_4517 node _T_4518 = bits(_WIRE_335, 21, 21) connect _WIRE_334.u, _T_4518 node _T_4519 = bits(_WIRE_335, 41, 22) connect _WIRE_334.ppn, _T_4519 wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_337 : UInt<42> connect _WIRE_337, sectored_entries[0][6].data[1] node _T_4520 = bits(_WIRE_337, 0, 0) connect _WIRE_336.fragmented_superpage, _T_4520 node _T_4521 = bits(_WIRE_337, 1, 1) connect _WIRE_336.c, _T_4521 node _T_4522 = bits(_WIRE_337, 2, 2) connect _WIRE_336.eff, _T_4522 node _T_4523 = bits(_WIRE_337, 3, 3) connect _WIRE_336.paa, _T_4523 node _T_4524 = bits(_WIRE_337, 4, 4) connect _WIRE_336.pal, _T_4524 node _T_4525 = bits(_WIRE_337, 5, 5) connect _WIRE_336.ppp, _T_4525 node _T_4526 = bits(_WIRE_337, 6, 6) connect _WIRE_336.pr, _T_4526 node _T_4527 = bits(_WIRE_337, 7, 7) connect _WIRE_336.px, _T_4527 node _T_4528 = bits(_WIRE_337, 8, 8) connect _WIRE_336.pw, _T_4528 node _T_4529 = bits(_WIRE_337, 9, 9) connect _WIRE_336.hr, _T_4529 node _T_4530 = bits(_WIRE_337, 10, 10) connect _WIRE_336.hx, _T_4530 node _T_4531 = bits(_WIRE_337, 11, 11) connect _WIRE_336.hw, _T_4531 node _T_4532 = bits(_WIRE_337, 12, 12) connect _WIRE_336.sr, _T_4532 node _T_4533 = bits(_WIRE_337, 13, 13) connect _WIRE_336.sx, _T_4533 node _T_4534 = bits(_WIRE_337, 14, 14) connect _WIRE_336.sw, _T_4534 node _T_4535 = bits(_WIRE_337, 15, 15) connect _WIRE_336.gf, _T_4535 node _T_4536 = bits(_WIRE_337, 16, 16) connect _WIRE_336.pf, _T_4536 node _T_4537 = bits(_WIRE_337, 17, 17) connect _WIRE_336.ae_stage2, _T_4537 node _T_4538 = bits(_WIRE_337, 18, 18) connect _WIRE_336.ae_final, _T_4538 node _T_4539 = bits(_WIRE_337, 19, 19) connect _WIRE_336.ae_ptw, _T_4539 node _T_4540 = bits(_WIRE_337, 20, 20) connect _WIRE_336.g, _T_4540 node _T_4541 = bits(_WIRE_337, 21, 21) connect _WIRE_336.u, _T_4541 node _T_4542 = bits(_WIRE_337, 41, 22) connect _WIRE_336.ppn, _T_4542 wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_339 : UInt<42> connect _WIRE_339, sectored_entries[0][6].data[2] node _T_4543 = bits(_WIRE_339, 0, 0) connect _WIRE_338.fragmented_superpage, _T_4543 node _T_4544 = bits(_WIRE_339, 1, 1) connect _WIRE_338.c, _T_4544 node _T_4545 = bits(_WIRE_339, 2, 2) connect _WIRE_338.eff, _T_4545 node _T_4546 = bits(_WIRE_339, 3, 3) connect _WIRE_338.paa, _T_4546 node _T_4547 = bits(_WIRE_339, 4, 4) connect _WIRE_338.pal, _T_4547 node _T_4548 = bits(_WIRE_339, 5, 5) connect _WIRE_338.ppp, _T_4548 node _T_4549 = bits(_WIRE_339, 6, 6) connect _WIRE_338.pr, _T_4549 node _T_4550 = bits(_WIRE_339, 7, 7) connect _WIRE_338.px, _T_4550 node _T_4551 = bits(_WIRE_339, 8, 8) connect _WIRE_338.pw, _T_4551 node _T_4552 = bits(_WIRE_339, 9, 9) connect _WIRE_338.hr, _T_4552 node _T_4553 = bits(_WIRE_339, 10, 10) connect _WIRE_338.hx, _T_4553 node _T_4554 = bits(_WIRE_339, 11, 11) connect _WIRE_338.hw, _T_4554 node _T_4555 = bits(_WIRE_339, 12, 12) connect _WIRE_338.sr, _T_4555 node _T_4556 = bits(_WIRE_339, 13, 13) connect _WIRE_338.sx, _T_4556 node _T_4557 = bits(_WIRE_339, 14, 14) connect _WIRE_338.sw, _T_4557 node _T_4558 = bits(_WIRE_339, 15, 15) connect _WIRE_338.gf, _T_4558 node _T_4559 = bits(_WIRE_339, 16, 16) connect _WIRE_338.pf, _T_4559 node _T_4560 = bits(_WIRE_339, 17, 17) connect _WIRE_338.ae_stage2, _T_4560 node _T_4561 = bits(_WIRE_339, 18, 18) connect _WIRE_338.ae_final, _T_4561 node _T_4562 = bits(_WIRE_339, 19, 19) connect _WIRE_338.ae_ptw, _T_4562 node _T_4563 = bits(_WIRE_339, 20, 20) connect _WIRE_338.g, _T_4563 node _T_4564 = bits(_WIRE_339, 21, 21) connect _WIRE_338.u, _T_4564 node _T_4565 = bits(_WIRE_339, 41, 22) connect _WIRE_338.ppn, _T_4565 wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_341 : UInt<42> connect _WIRE_341, sectored_entries[0][6].data[3] node _T_4566 = bits(_WIRE_341, 0, 0) connect _WIRE_340.fragmented_superpage, _T_4566 node _T_4567 = bits(_WIRE_341, 1, 1) connect _WIRE_340.c, _T_4567 node _T_4568 = bits(_WIRE_341, 2, 2) connect _WIRE_340.eff, _T_4568 node _T_4569 = bits(_WIRE_341, 3, 3) connect _WIRE_340.paa, _T_4569 node _T_4570 = bits(_WIRE_341, 4, 4) connect _WIRE_340.pal, _T_4570 node _T_4571 = bits(_WIRE_341, 5, 5) connect _WIRE_340.ppp, _T_4571 node _T_4572 = bits(_WIRE_341, 6, 6) connect _WIRE_340.pr, _T_4572 node _T_4573 = bits(_WIRE_341, 7, 7) connect _WIRE_340.px, _T_4573 node _T_4574 = bits(_WIRE_341, 8, 8) connect _WIRE_340.pw, _T_4574 node _T_4575 = bits(_WIRE_341, 9, 9) connect _WIRE_340.hr, _T_4575 node _T_4576 = bits(_WIRE_341, 10, 10) connect _WIRE_340.hx, _T_4576 node _T_4577 = bits(_WIRE_341, 11, 11) connect _WIRE_340.hw, _T_4577 node _T_4578 = bits(_WIRE_341, 12, 12) connect _WIRE_340.sr, _T_4578 node _T_4579 = bits(_WIRE_341, 13, 13) connect _WIRE_340.sx, _T_4579 node _T_4580 = bits(_WIRE_341, 14, 14) connect _WIRE_340.sw, _T_4580 node _T_4581 = bits(_WIRE_341, 15, 15) connect _WIRE_340.gf, _T_4581 node _T_4582 = bits(_WIRE_341, 16, 16) connect _WIRE_340.pf, _T_4582 node _T_4583 = bits(_WIRE_341, 17, 17) connect _WIRE_340.ae_stage2, _T_4583 node _T_4584 = bits(_WIRE_341, 18, 18) connect _WIRE_340.ae_final, _T_4584 node _T_4585 = bits(_WIRE_341, 19, 19) connect _WIRE_340.ae_ptw, _T_4585 node _T_4586 = bits(_WIRE_341, 20, 20) connect _WIRE_340.g, _T_4586 node _T_4587 = bits(_WIRE_341, 21, 21) connect _WIRE_340.u, _T_4587 node _T_4588 = bits(_WIRE_341, 41, 22) connect _WIRE_340.ppn, _T_4588 node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4589 : connect sectored_entries[0][6].valid[0], UInt<1>(0h0) node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4590 : connect sectored_entries[0][6].valid[1], UInt<1>(0h0) node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4591 : connect sectored_entries[0][6].valid[2], UInt<1>(0h0) node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1)) when _T_4592 : connect sectored_entries[0][6].valid[3], UInt<1>(0h0) wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_343 : UInt<42> connect _WIRE_343, sectored_entries[0][7].data[0] node _T_4593 = bits(_WIRE_343, 0, 0) connect _WIRE_342.fragmented_superpage, _T_4593 node _T_4594 = bits(_WIRE_343, 1, 1) connect _WIRE_342.c, _T_4594 node _T_4595 = bits(_WIRE_343, 2, 2) connect _WIRE_342.eff, _T_4595 node _T_4596 = bits(_WIRE_343, 3, 3) connect _WIRE_342.paa, _T_4596 node _T_4597 = bits(_WIRE_343, 4, 4) connect _WIRE_342.pal, _T_4597 node _T_4598 = bits(_WIRE_343, 5, 5) connect _WIRE_342.ppp, _T_4598 node _T_4599 = bits(_WIRE_343, 6, 6) connect _WIRE_342.pr, _T_4599 node _T_4600 = bits(_WIRE_343, 7, 7) connect _WIRE_342.px, _T_4600 node _T_4601 = bits(_WIRE_343, 8, 8) connect _WIRE_342.pw, _T_4601 node _T_4602 = bits(_WIRE_343, 9, 9) connect _WIRE_342.hr, _T_4602 node _T_4603 = bits(_WIRE_343, 10, 10) connect _WIRE_342.hx, _T_4603 node _T_4604 = bits(_WIRE_343, 11, 11) connect _WIRE_342.hw, _T_4604 node _T_4605 = bits(_WIRE_343, 12, 12) connect _WIRE_342.sr, _T_4605 node _T_4606 = bits(_WIRE_343, 13, 13) connect _WIRE_342.sx, _T_4606 node _T_4607 = bits(_WIRE_343, 14, 14) connect _WIRE_342.sw, _T_4607 node _T_4608 = bits(_WIRE_343, 15, 15) connect _WIRE_342.gf, _T_4608 node _T_4609 = bits(_WIRE_343, 16, 16) connect _WIRE_342.pf, _T_4609 node _T_4610 = bits(_WIRE_343, 17, 17) connect _WIRE_342.ae_stage2, _T_4610 node _T_4611 = bits(_WIRE_343, 18, 18) connect _WIRE_342.ae_final, _T_4611 node _T_4612 = bits(_WIRE_343, 19, 19) connect _WIRE_342.ae_ptw, _T_4612 node _T_4613 = bits(_WIRE_343, 20, 20) connect _WIRE_342.g, _T_4613 node _T_4614 = bits(_WIRE_343, 21, 21) connect _WIRE_342.u, _T_4614 node _T_4615 = bits(_WIRE_343, 41, 22) connect _WIRE_342.ppn, _T_4615 wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_345 : UInt<42> connect _WIRE_345, sectored_entries[0][7].data[1] node _T_4616 = bits(_WIRE_345, 0, 0) connect _WIRE_344.fragmented_superpage, _T_4616 node _T_4617 = bits(_WIRE_345, 1, 1) connect _WIRE_344.c, _T_4617 node _T_4618 = bits(_WIRE_345, 2, 2) connect _WIRE_344.eff, _T_4618 node _T_4619 = bits(_WIRE_345, 3, 3) connect _WIRE_344.paa, _T_4619 node _T_4620 = bits(_WIRE_345, 4, 4) connect _WIRE_344.pal, _T_4620 node _T_4621 = bits(_WIRE_345, 5, 5) connect _WIRE_344.ppp, _T_4621 node _T_4622 = bits(_WIRE_345, 6, 6) connect _WIRE_344.pr, _T_4622 node _T_4623 = bits(_WIRE_345, 7, 7) connect _WIRE_344.px, _T_4623 node _T_4624 = bits(_WIRE_345, 8, 8) connect _WIRE_344.pw, _T_4624 node _T_4625 = bits(_WIRE_345, 9, 9) connect _WIRE_344.hr, _T_4625 node _T_4626 = bits(_WIRE_345, 10, 10) connect _WIRE_344.hx, _T_4626 node _T_4627 = bits(_WIRE_345, 11, 11) connect _WIRE_344.hw, _T_4627 node _T_4628 = bits(_WIRE_345, 12, 12) connect _WIRE_344.sr, _T_4628 node _T_4629 = bits(_WIRE_345, 13, 13) connect _WIRE_344.sx, _T_4629 node _T_4630 = bits(_WIRE_345, 14, 14) connect _WIRE_344.sw, _T_4630 node _T_4631 = bits(_WIRE_345, 15, 15) connect _WIRE_344.gf, _T_4631 node _T_4632 = bits(_WIRE_345, 16, 16) connect _WIRE_344.pf, _T_4632 node _T_4633 = bits(_WIRE_345, 17, 17) connect _WIRE_344.ae_stage2, _T_4633 node _T_4634 = bits(_WIRE_345, 18, 18) connect _WIRE_344.ae_final, _T_4634 node _T_4635 = bits(_WIRE_345, 19, 19) connect _WIRE_344.ae_ptw, _T_4635 node _T_4636 = bits(_WIRE_345, 20, 20) connect _WIRE_344.g, _T_4636 node _T_4637 = bits(_WIRE_345, 21, 21) connect _WIRE_344.u, _T_4637 node _T_4638 = bits(_WIRE_345, 41, 22) connect _WIRE_344.ppn, _T_4638 wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_347 : UInt<42> connect _WIRE_347, sectored_entries[0][7].data[2] node _T_4639 = bits(_WIRE_347, 0, 0) connect _WIRE_346.fragmented_superpage, _T_4639 node _T_4640 = bits(_WIRE_347, 1, 1) connect _WIRE_346.c, _T_4640 node _T_4641 = bits(_WIRE_347, 2, 2) connect _WIRE_346.eff, _T_4641 node _T_4642 = bits(_WIRE_347, 3, 3) connect _WIRE_346.paa, _T_4642 node _T_4643 = bits(_WIRE_347, 4, 4) connect _WIRE_346.pal, _T_4643 node _T_4644 = bits(_WIRE_347, 5, 5) connect _WIRE_346.ppp, _T_4644 node _T_4645 = bits(_WIRE_347, 6, 6) connect _WIRE_346.pr, _T_4645 node _T_4646 = bits(_WIRE_347, 7, 7) connect _WIRE_346.px, _T_4646 node _T_4647 = bits(_WIRE_347, 8, 8) connect _WIRE_346.pw, _T_4647 node _T_4648 = bits(_WIRE_347, 9, 9) connect _WIRE_346.hr, _T_4648 node _T_4649 = bits(_WIRE_347, 10, 10) connect _WIRE_346.hx, _T_4649 node _T_4650 = bits(_WIRE_347, 11, 11) connect _WIRE_346.hw, _T_4650 node _T_4651 = bits(_WIRE_347, 12, 12) connect _WIRE_346.sr, _T_4651 node _T_4652 = bits(_WIRE_347, 13, 13) connect _WIRE_346.sx, _T_4652 node _T_4653 = bits(_WIRE_347, 14, 14) connect _WIRE_346.sw, _T_4653 node _T_4654 = bits(_WIRE_347, 15, 15) connect _WIRE_346.gf, _T_4654 node _T_4655 = bits(_WIRE_347, 16, 16) connect _WIRE_346.pf, _T_4655 node _T_4656 = bits(_WIRE_347, 17, 17) connect _WIRE_346.ae_stage2, _T_4656 node _T_4657 = bits(_WIRE_347, 18, 18) connect _WIRE_346.ae_final, _T_4657 node _T_4658 = bits(_WIRE_347, 19, 19) connect _WIRE_346.ae_ptw, _T_4658 node _T_4659 = bits(_WIRE_347, 20, 20) connect _WIRE_346.g, _T_4659 node _T_4660 = bits(_WIRE_347, 21, 21) connect _WIRE_346.u, _T_4660 node _T_4661 = bits(_WIRE_347, 41, 22) connect _WIRE_346.ppn, _T_4661 wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_349 : UInt<42> connect _WIRE_349, sectored_entries[0][7].data[3] node _T_4662 = bits(_WIRE_349, 0, 0) connect _WIRE_348.fragmented_superpage, _T_4662 node _T_4663 = bits(_WIRE_349, 1, 1) connect _WIRE_348.c, _T_4663 node _T_4664 = bits(_WIRE_349, 2, 2) connect _WIRE_348.eff, _T_4664 node _T_4665 = bits(_WIRE_349, 3, 3) connect _WIRE_348.paa, _T_4665 node _T_4666 = bits(_WIRE_349, 4, 4) connect _WIRE_348.pal, _T_4666 node _T_4667 = bits(_WIRE_349, 5, 5) connect _WIRE_348.ppp, _T_4667 node _T_4668 = bits(_WIRE_349, 6, 6) connect _WIRE_348.pr, _T_4668 node _T_4669 = bits(_WIRE_349, 7, 7) connect _WIRE_348.px, _T_4669 node _T_4670 = bits(_WIRE_349, 8, 8) connect _WIRE_348.pw, _T_4670 node _T_4671 = bits(_WIRE_349, 9, 9) connect _WIRE_348.hr, _T_4671 node _T_4672 = bits(_WIRE_349, 10, 10) connect _WIRE_348.hx, _T_4672 node _T_4673 = bits(_WIRE_349, 11, 11) connect _WIRE_348.hw, _T_4673 node _T_4674 = bits(_WIRE_349, 12, 12) connect _WIRE_348.sr, _T_4674 node _T_4675 = bits(_WIRE_349, 13, 13) connect _WIRE_348.sx, _T_4675 node _T_4676 = bits(_WIRE_349, 14, 14) connect _WIRE_348.sw, _T_4676 node _T_4677 = bits(_WIRE_349, 15, 15) connect _WIRE_348.gf, _T_4677 node _T_4678 = bits(_WIRE_349, 16, 16) connect _WIRE_348.pf, _T_4678 node _T_4679 = bits(_WIRE_349, 17, 17) connect _WIRE_348.ae_stage2, _T_4679 node _T_4680 = bits(_WIRE_349, 18, 18) connect _WIRE_348.ae_final, _T_4680 node _T_4681 = bits(_WIRE_349, 19, 19) connect _WIRE_348.ae_ptw, _T_4681 node _T_4682 = bits(_WIRE_349, 20, 20) connect _WIRE_348.g, _T_4682 node _T_4683 = bits(_WIRE_349, 21, 21) connect _WIRE_348.u, _T_4683 node _T_4684 = bits(_WIRE_349, 41, 22) connect _WIRE_348.ppn, _T_4684 node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4685 : connect sectored_entries[0][7].valid[0], UInt<1>(0h0) node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4686 : connect sectored_entries[0][7].valid[1], UInt<1>(0h0) node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4687 : connect sectored_entries[0][7].valid[2], UInt<1>(0h0) node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1)) when _T_4688 : connect sectored_entries[0][7].valid[3], UInt<1>(0h0) wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_351 : UInt<42> connect _WIRE_351, superpage_entries[0].data[0] node _T_4689 = bits(_WIRE_351, 0, 0) connect _WIRE_350.fragmented_superpage, _T_4689 node _T_4690 = bits(_WIRE_351, 1, 1) connect _WIRE_350.c, _T_4690 node _T_4691 = bits(_WIRE_351, 2, 2) connect _WIRE_350.eff, _T_4691 node _T_4692 = bits(_WIRE_351, 3, 3) connect _WIRE_350.paa, _T_4692 node _T_4693 = bits(_WIRE_351, 4, 4) connect _WIRE_350.pal, _T_4693 node _T_4694 = bits(_WIRE_351, 5, 5) connect _WIRE_350.ppp, _T_4694 node _T_4695 = bits(_WIRE_351, 6, 6) connect _WIRE_350.pr, _T_4695 node _T_4696 = bits(_WIRE_351, 7, 7) connect _WIRE_350.px, _T_4696 node _T_4697 = bits(_WIRE_351, 8, 8) connect _WIRE_350.pw, _T_4697 node _T_4698 = bits(_WIRE_351, 9, 9) connect _WIRE_350.hr, _T_4698 node _T_4699 = bits(_WIRE_351, 10, 10) connect _WIRE_350.hx, _T_4699 node _T_4700 = bits(_WIRE_351, 11, 11) connect _WIRE_350.hw, _T_4700 node _T_4701 = bits(_WIRE_351, 12, 12) connect _WIRE_350.sr, _T_4701 node _T_4702 = bits(_WIRE_351, 13, 13) connect _WIRE_350.sx, _T_4702 node _T_4703 = bits(_WIRE_351, 14, 14) connect _WIRE_350.sw, _T_4703 node _T_4704 = bits(_WIRE_351, 15, 15) connect _WIRE_350.gf, _T_4704 node _T_4705 = bits(_WIRE_351, 16, 16) connect _WIRE_350.pf, _T_4705 node _T_4706 = bits(_WIRE_351, 17, 17) connect _WIRE_350.ae_stage2, _T_4706 node _T_4707 = bits(_WIRE_351, 18, 18) connect _WIRE_350.ae_final, _T_4707 node _T_4708 = bits(_WIRE_351, 19, 19) connect _WIRE_350.ae_ptw, _T_4708 node _T_4709 = bits(_WIRE_351, 20, 20) connect _WIRE_350.g, _T_4709 node _T_4710 = bits(_WIRE_351, 21, 21) connect _WIRE_350.u, _T_4710 node _T_4711 = bits(_WIRE_351, 41, 22) connect _WIRE_350.ppn, _T_4711 node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_4712 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_353 : UInt<42> connect _WIRE_353, superpage_entries[1].data[0] node _T_4713 = bits(_WIRE_353, 0, 0) connect _WIRE_352.fragmented_superpage, _T_4713 node _T_4714 = bits(_WIRE_353, 1, 1) connect _WIRE_352.c, _T_4714 node _T_4715 = bits(_WIRE_353, 2, 2) connect _WIRE_352.eff, _T_4715 node _T_4716 = bits(_WIRE_353, 3, 3) connect _WIRE_352.paa, _T_4716 node _T_4717 = bits(_WIRE_353, 4, 4) connect _WIRE_352.pal, _T_4717 node _T_4718 = bits(_WIRE_353, 5, 5) connect _WIRE_352.ppp, _T_4718 node _T_4719 = bits(_WIRE_353, 6, 6) connect _WIRE_352.pr, _T_4719 node _T_4720 = bits(_WIRE_353, 7, 7) connect _WIRE_352.px, _T_4720 node _T_4721 = bits(_WIRE_353, 8, 8) connect _WIRE_352.pw, _T_4721 node _T_4722 = bits(_WIRE_353, 9, 9) connect _WIRE_352.hr, _T_4722 node _T_4723 = bits(_WIRE_353, 10, 10) connect _WIRE_352.hx, _T_4723 node _T_4724 = bits(_WIRE_353, 11, 11) connect _WIRE_352.hw, _T_4724 node _T_4725 = bits(_WIRE_353, 12, 12) connect _WIRE_352.sr, _T_4725 node _T_4726 = bits(_WIRE_353, 13, 13) connect _WIRE_352.sx, _T_4726 node _T_4727 = bits(_WIRE_353, 14, 14) connect _WIRE_352.sw, _T_4727 node _T_4728 = bits(_WIRE_353, 15, 15) connect _WIRE_352.gf, _T_4728 node _T_4729 = bits(_WIRE_353, 16, 16) connect _WIRE_352.pf, _T_4729 node _T_4730 = bits(_WIRE_353, 17, 17) connect _WIRE_352.ae_stage2, _T_4730 node _T_4731 = bits(_WIRE_353, 18, 18) connect _WIRE_352.ae_final, _T_4731 node _T_4732 = bits(_WIRE_353, 19, 19) connect _WIRE_352.ae_ptw, _T_4732 node _T_4733 = bits(_WIRE_353, 20, 20) connect _WIRE_352.g, _T_4733 node _T_4734 = bits(_WIRE_353, 21, 21) connect _WIRE_352.u, _T_4734 node _T_4735 = bits(_WIRE_353, 41, 22) connect _WIRE_352.ppn, _T_4735 node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1)) when _T_4736 : connect superpage_entries[1].valid[0], UInt<1>(0h0) wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_355 : UInt<42> connect _WIRE_355, superpage_entries[2].data[0] node _T_4737 = bits(_WIRE_355, 0, 0) connect _WIRE_354.fragmented_superpage, _T_4737 node _T_4738 = bits(_WIRE_355, 1, 1) connect _WIRE_354.c, _T_4738 node _T_4739 = bits(_WIRE_355, 2, 2) connect _WIRE_354.eff, _T_4739 node _T_4740 = bits(_WIRE_355, 3, 3) connect _WIRE_354.paa, _T_4740 node _T_4741 = bits(_WIRE_355, 4, 4) connect _WIRE_354.pal, _T_4741 node _T_4742 = bits(_WIRE_355, 5, 5) connect _WIRE_354.ppp, _T_4742 node _T_4743 = bits(_WIRE_355, 6, 6) connect _WIRE_354.pr, _T_4743 node _T_4744 = bits(_WIRE_355, 7, 7) connect _WIRE_354.px, _T_4744 node _T_4745 = bits(_WIRE_355, 8, 8) connect _WIRE_354.pw, _T_4745 node _T_4746 = bits(_WIRE_355, 9, 9) connect _WIRE_354.hr, _T_4746 node _T_4747 = bits(_WIRE_355, 10, 10) connect _WIRE_354.hx, _T_4747 node _T_4748 = bits(_WIRE_355, 11, 11) connect _WIRE_354.hw, _T_4748 node _T_4749 = bits(_WIRE_355, 12, 12) connect _WIRE_354.sr, _T_4749 node _T_4750 = bits(_WIRE_355, 13, 13) connect _WIRE_354.sx, _T_4750 node _T_4751 = bits(_WIRE_355, 14, 14) connect _WIRE_354.sw, _T_4751 node _T_4752 = bits(_WIRE_355, 15, 15) connect _WIRE_354.gf, _T_4752 node _T_4753 = bits(_WIRE_355, 16, 16) connect _WIRE_354.pf, _T_4753 node _T_4754 = bits(_WIRE_355, 17, 17) connect _WIRE_354.ae_stage2, _T_4754 node _T_4755 = bits(_WIRE_355, 18, 18) connect _WIRE_354.ae_final, _T_4755 node _T_4756 = bits(_WIRE_355, 19, 19) connect _WIRE_354.ae_ptw, _T_4756 node _T_4757 = bits(_WIRE_355, 20, 20) connect _WIRE_354.g, _T_4757 node _T_4758 = bits(_WIRE_355, 21, 21) connect _WIRE_354.u, _T_4758 node _T_4759 = bits(_WIRE_355, 41, 22) connect _WIRE_354.ppn, _T_4759 node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1)) when _T_4760 : connect superpage_entries[2].valid[0], UInt<1>(0h0) wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_357 : UInt<42> connect _WIRE_357, superpage_entries[3].data[0] node _T_4761 = bits(_WIRE_357, 0, 0) connect _WIRE_356.fragmented_superpage, _T_4761 node _T_4762 = bits(_WIRE_357, 1, 1) connect _WIRE_356.c, _T_4762 node _T_4763 = bits(_WIRE_357, 2, 2) connect _WIRE_356.eff, _T_4763 node _T_4764 = bits(_WIRE_357, 3, 3) connect _WIRE_356.paa, _T_4764 node _T_4765 = bits(_WIRE_357, 4, 4) connect _WIRE_356.pal, _T_4765 node _T_4766 = bits(_WIRE_357, 5, 5) connect _WIRE_356.ppp, _T_4766 node _T_4767 = bits(_WIRE_357, 6, 6) connect _WIRE_356.pr, _T_4767 node _T_4768 = bits(_WIRE_357, 7, 7) connect _WIRE_356.px, _T_4768 node _T_4769 = bits(_WIRE_357, 8, 8) connect _WIRE_356.pw, _T_4769 node _T_4770 = bits(_WIRE_357, 9, 9) connect _WIRE_356.hr, _T_4770 node _T_4771 = bits(_WIRE_357, 10, 10) connect _WIRE_356.hx, _T_4771 node _T_4772 = bits(_WIRE_357, 11, 11) connect _WIRE_356.hw, _T_4772 node _T_4773 = bits(_WIRE_357, 12, 12) connect _WIRE_356.sr, _T_4773 node _T_4774 = bits(_WIRE_357, 13, 13) connect _WIRE_356.sx, _T_4774 node _T_4775 = bits(_WIRE_357, 14, 14) connect _WIRE_356.sw, _T_4775 node _T_4776 = bits(_WIRE_357, 15, 15) connect _WIRE_356.gf, _T_4776 node _T_4777 = bits(_WIRE_357, 16, 16) connect _WIRE_356.pf, _T_4777 node _T_4778 = bits(_WIRE_357, 17, 17) connect _WIRE_356.ae_stage2, _T_4778 node _T_4779 = bits(_WIRE_357, 18, 18) connect _WIRE_356.ae_final, _T_4779 node _T_4780 = bits(_WIRE_357, 19, 19) connect _WIRE_356.ae_ptw, _T_4780 node _T_4781 = bits(_WIRE_357, 20, 20) connect _WIRE_356.g, _T_4781 node _T_4782 = bits(_WIRE_357, 21, 21) connect _WIRE_356.u, _T_4782 node _T_4783 = bits(_WIRE_357, 41, 22) connect _WIRE_356.ppn, _T_4783 node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1)) when _T_4784 : connect superpage_entries[3].valid[0], UInt<1>(0h0) wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_359 : UInt<42> connect _WIRE_359, special_entry.data[0] node _T_4785 = bits(_WIRE_359, 0, 0) connect _WIRE_358.fragmented_superpage, _T_4785 node _T_4786 = bits(_WIRE_359, 1, 1) connect _WIRE_358.c, _T_4786 node _T_4787 = bits(_WIRE_359, 2, 2) connect _WIRE_358.eff, _T_4787 node _T_4788 = bits(_WIRE_359, 3, 3) connect _WIRE_358.paa, _T_4788 node _T_4789 = bits(_WIRE_359, 4, 4) connect _WIRE_358.pal, _T_4789 node _T_4790 = bits(_WIRE_359, 5, 5) connect _WIRE_358.ppp, _T_4790 node _T_4791 = bits(_WIRE_359, 6, 6) connect _WIRE_358.pr, _T_4791 node _T_4792 = bits(_WIRE_359, 7, 7) connect _WIRE_358.px, _T_4792 node _T_4793 = bits(_WIRE_359, 8, 8) connect _WIRE_358.pw, _T_4793 node _T_4794 = bits(_WIRE_359, 9, 9) connect _WIRE_358.hr, _T_4794 node _T_4795 = bits(_WIRE_359, 10, 10) connect _WIRE_358.hx, _T_4795 node _T_4796 = bits(_WIRE_359, 11, 11) connect _WIRE_358.hw, _T_4796 node _T_4797 = bits(_WIRE_359, 12, 12) connect _WIRE_358.sr, _T_4797 node _T_4798 = bits(_WIRE_359, 13, 13) connect _WIRE_358.sx, _T_4798 node _T_4799 = bits(_WIRE_359, 14, 14) connect _WIRE_358.sw, _T_4799 node _T_4800 = bits(_WIRE_359, 15, 15) connect _WIRE_358.gf, _T_4800 node _T_4801 = bits(_WIRE_359, 16, 16) connect _WIRE_358.pf, _T_4801 node _T_4802 = bits(_WIRE_359, 17, 17) connect _WIRE_358.ae_stage2, _T_4802 node _T_4803 = bits(_WIRE_359, 18, 18) connect _WIRE_358.ae_final, _T_4803 node _T_4804 = bits(_WIRE_359, 19, 19) connect _WIRE_358.ae_ptw, _T_4804 node _T_4805 = bits(_WIRE_359, 20, 20) connect _WIRE_358.g, _T_4805 node _T_4806 = bits(_WIRE_359, 21, 21) connect _WIRE_358.u, _T_4806 node _T_4807 = bits(_WIRE_359, 41, 22) connect _WIRE_358.ppn, _T_4807 node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_4808 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_4809 = asUInt(reset) node _T_4810 = or(multipleHits, _T_4809) when _T_4810 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][0].valid[1], UInt<1>(0h0) connect sectored_entries[0][0].valid[2], UInt<1>(0h0) connect sectored_entries[0][0].valid[3], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[1], UInt<1>(0h0) connect sectored_entries[0][1].valid[2], UInt<1>(0h0) connect sectored_entries[0][1].valid[3], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[1], UInt<1>(0h0) connect sectored_entries[0][2].valid[2], UInt<1>(0h0) connect sectored_entries[0][2].valid[3], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[1], UInt<1>(0h0) connect sectored_entries[0][3].valid[2], UInt<1>(0h0) connect sectored_entries[0][3].valid[3], UInt<1>(0h0) connect sectored_entries[0][4].valid[0], UInt<1>(0h0) connect sectored_entries[0][4].valid[1], UInt<1>(0h0) connect sectored_entries[0][4].valid[2], UInt<1>(0h0) connect sectored_entries[0][4].valid[3], UInt<1>(0h0) connect sectored_entries[0][5].valid[0], UInt<1>(0h0) connect sectored_entries[0][5].valid[1], UInt<1>(0h0) connect sectored_entries[0][5].valid[2], UInt<1>(0h0) connect sectored_entries[0][5].valid[3], UInt<1>(0h0) connect sectored_entries[0][6].valid[0], UInt<1>(0h0) connect sectored_entries[0][6].valid[1], UInt<1>(0h0) connect sectored_entries[0][6].valid[2], UInt<1>(0h0) connect sectored_entries[0][6].valid[3], UInt<1>(0h0) connect sectored_entries[0][7].valid[0], UInt<1>(0h0) connect sectored_entries[0][7].valid[1], UInt<1>(0h0) connect sectored_entries[0][7].valid[2], UInt<1>(0h0) connect sectored_entries[0][7].valid[3], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect superpage_entries[1].valid[0], UInt<1>(0h0) connect superpage_entries[2].valid[0], UInt<1>(0h0) connect superpage_entries[3].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_4813 = and(io.ptw.req.valid, _T_4812) node _T_4814 = eq(state, UInt<2>(0h3)) node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4816 = and(io.sfence.valid, _T_4815) node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4818 = and(_T_4816, _T_4817) node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_4820 = and(io.sfence.valid, _T_4819) node _T_4821 = and(_T_4820, io.sfence.bits.rs2) node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_4824 = and(_T_4822, _T_4823) node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_4826 = and(_T_4825, io.sfence.bits.rs2)

module DTLB_6( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input io_req_bits_passthrough, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_st, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_st, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_ma_st, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_must_alloc, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] output [1:0] io_resp_size, // @[TLB.scala:320:14] output [4:0] io_resp_cmd, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input io_ptw_gstatus_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire io_req_bits_passthrough_0 = io_req_bits_passthrough; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire _io_req_ready_T; // @[TLB.scala:631:25] wire [1:0] io_resp_size_0 = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd_0 = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_st_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_st_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_ma_st_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_must_alloc_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire _vm_enabled_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64] wire vm_enabled = _vm_enabled_T_1 & _vm_enabled_T_2; // @[TLB.scala:399:{45,61,64}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire _vsatp_mode_mismatch_T_2 = ~io_req_bits_passthrough_0; // @[TLB.scala:318:7, :399:64, :403:81] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T = do_refill | io_req_bits_passthrough_0; // @[TLB.scala:318:7, :408:29, :415:52] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_60 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_60; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_61; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_61; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_62 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_62; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_62; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_63; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_63; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_63; // @[package.scala:16:47] wire _GEN_64 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_64; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_64; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_65; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_65; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_65; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_66 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_66; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_66; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_67; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_67; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_68; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_68; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_69; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_69; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_70; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_70; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_70; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_71 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_71; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_71; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_72 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_72; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_72; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] _must_alloc_array_T_9 = {14{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] must_alloc_array = _must_alloc_array_T_7 | _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_73 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_73; // @[OneHot.scala:21:45] wire [1:0] _GEN_74 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_74; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_75 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_75; // @[OneHot.scala:21:45] wire [1:0] _GEN_76 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_76; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_77 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_77; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_78 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_78; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [13:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = |_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T | _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st_0 = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = |_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st_0 = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st_0 = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = |_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc_0 = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_109 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_109( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_185 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_30 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0

module AsyncResetSynchronizerShiftReg_w1_d3_i0_30( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_30 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s13k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_24 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s13k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s13k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<13>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<13>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<13>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<13>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_50 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_51 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32

module TLBuffer_a26d64s13k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [12:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [12:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [12:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_24 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s13k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s13k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule

Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_42 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_42 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags

module INToRecFN_i1_e8_s24_42(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_42 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 node _source_ok_T_33 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[2]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[3]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[4]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[5]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_38, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = and(_T_11, _T_24) node _T_94 = and(_T_93, _T_37) node _T_95 = and(_T_94, _T_50) node _T_96 = and(_T_95, _T_63) node _T_97 = and(_T_96, _T_76) node _T_98 = and(_T_97, _T_84) node _T_99 = and(_T_98, _T_92) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_99, UInt<1>(0h1), "") : assert_1 node _T_103 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_103 : node _T_104 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_105 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_106 = and(_T_104, _T_105) node _T_107 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_108 = shr(io.in.a.bits.source, 2) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = leq(UInt<1>(0h0), uncommonBits_5) node _T_111 = and(_T_109, _T_110) node _T_112 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_113 = and(_T_111, _T_112) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_114 = shr(io.in.a.bits.source, 2) node _T_115 = eq(_T_114, UInt<1>(0h1)) node _T_116 = leq(UInt<1>(0h0), uncommonBits_6) node _T_117 = and(_T_115, _T_116) node _T_118 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_119 = and(_T_117, _T_118) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_120 = shr(io.in.a.bits.source, 2) node _T_121 = eq(_T_120, UInt<2>(0h2)) node _T_122 = leq(UInt<1>(0h0), uncommonBits_7) node _T_123 = and(_T_121, _T_122) node _T_124 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_125 = and(_T_123, _T_124) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<2>(0h3)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_8) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_132 = shr(io.in.a.bits.source, 3) node _T_133 = eq(_T_132, UInt<3>(0h4)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_9) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_140 = or(_T_107, _T_113) node _T_141 = or(_T_140, _T_119) node _T_142 = or(_T_141, _T_125) node _T_143 = or(_T_142, _T_131) node _T_144 = or(_T_143, _T_137) node _T_145 = or(_T_144, _T_138) node _T_146 = or(_T_145, _T_139) node _T_147 = and(_T_106, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_150 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<14>(0h2000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<13>(0h1000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<18>(0h2f000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<17>(0h10000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<13>(0h1000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_181 = cvt(_T_180) node _T_182 = and(_T_181, asSInt(UInt<27>(0h4000000))) node _T_183 = asSInt(_T_182) node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0))) node _T_185 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_186 = cvt(_T_185) node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000))) node _T_188 = asSInt(_T_187) node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0))) node _T_190 = or(_T_154, _T_159) node _T_191 = or(_T_190, _T_164) node _T_192 = or(_T_191, _T_169) node _T_193 = or(_T_192, _T_174) node _T_194 = or(_T_193, _T_179) node _T_195 = or(_T_194, _T_184) node _T_196 = or(_T_195, _T_189) node _T_197 = and(_T_149, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = and(_T_148, _T_198) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_199, UInt<1>(0h1), "") : assert_2 node _T_203 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_204 = shr(io.in.a.bits.source, 2) node _T_205 = eq(_T_204, UInt<1>(0h0)) node _T_206 = leq(UInt<1>(0h0), uncommonBits_10) node _T_207 = and(_T_205, _T_206) node _T_208 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_210 = shr(io.in.a.bits.source, 2) node _T_211 = eq(_T_210, UInt<1>(0h1)) node _T_212 = leq(UInt<1>(0h0), uncommonBits_11) node _T_213 = and(_T_211, _T_212) node _T_214 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_215 = and(_T_213, _T_214) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_216 = shr(io.in.a.bits.source, 2) node _T_217 = eq(_T_216, UInt<2>(0h2)) node _T_218 = leq(UInt<1>(0h0), uncommonBits_12) node _T_219 = and(_T_217, _T_218) node _T_220 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_221 = and(_T_219, _T_220) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_222 = shr(io.in.a.bits.source, 2) node _T_223 = eq(_T_222, UInt<2>(0h3)) node _T_224 = leq(UInt<1>(0h0), uncommonBits_13) node _T_225 = and(_T_223, _T_224) node _T_226 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_227 = and(_T_225, _T_226) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_228 = shr(io.in.a.bits.source, 3) node _T_229 = eq(_T_228, UInt<3>(0h4)) node _T_230 = leq(UInt<1>(0h0), uncommonBits_14) node _T_231 = and(_T_229, _T_230) node _T_232 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_233 = and(_T_231, _T_232) node _T_234 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _WIRE : UInt<1>[8] connect _WIRE[0], _T_203 connect _WIRE[1], _T_209 connect _WIRE[2], _T_215 connect _WIRE[3], _T_221 connect _WIRE[4], _T_227 connect _WIRE[5], _T_233 connect _WIRE[6], _T_234 connect _WIRE[7], _T_235 node _T_236 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_237 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_238 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_239 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_241 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_242 = mux(_WIRE[5], _T_236, UInt<1>(0h0)) node _T_243 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_244 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_245 = or(_T_237, _T_238) node _T_246 = or(_T_245, _T_239) node _T_247 = or(_T_246, _T_240) node _T_248 = or(_T_247, _T_241) node _T_249 = or(_T_248, _T_242) node _T_250 = or(_T_249, _T_243) node _T_251 = or(_T_250, _T_244) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_251 node _T_252 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_253 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_254 = and(_T_252, _T_253) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<14>(0h2000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<13>(0h1000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<18>(0h2f000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<17>(0h10000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<27>(0h4000000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_292 = cvt(_T_291) node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000))) node _T_294 = asSInt(_T_293) node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0))) node _T_296 = or(_T_260, _T_265) node _T_297 = or(_T_296, _T_270) node _T_298 = or(_T_297, _T_275) node _T_299 = or(_T_298, _T_280) node _T_300 = or(_T_299, _T_285) node _T_301 = or(_T_300, _T_290) node _T_302 = or(_T_301, _T_295) node _T_303 = and(_T_255, _T_302) node _T_304 = or(UInt<1>(0h0), _T_303) node _T_305 = and(_WIRE_1, _T_304) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_305, UInt<1>(0h1), "") : assert_3 node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(source_ok, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_312 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_312, UInt<1>(0h1), "") : assert_5 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_319 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_319, UInt<1>(0h1), "") : assert_7 node _T_323 = not(io.in.a.bits.mask) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_324, UInt<1>(0h1), "") : assert_8 node _T_328 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_328, UInt<1>(0h1), "") : assert_9 node _T_332 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_332 : node _T_333 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_334 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_335 = and(_T_333, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_15) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_343 = shr(io.in.a.bits.source, 2) node _T_344 = eq(_T_343, UInt<1>(0h1)) node _T_345 = leq(UInt<1>(0h0), uncommonBits_16) node _T_346 = and(_T_344, _T_345) node _T_347 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_348 = and(_T_346, _T_347) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_349 = shr(io.in.a.bits.source, 2) node _T_350 = eq(_T_349, UInt<2>(0h2)) node _T_351 = leq(UInt<1>(0h0), uncommonBits_17) node _T_352 = and(_T_350, _T_351) node _T_353 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_354 = and(_T_352, _T_353) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_355 = shr(io.in.a.bits.source, 2) node _T_356 = eq(_T_355, UInt<2>(0h3)) node _T_357 = leq(UInt<1>(0h0), uncommonBits_18) node _T_358 = and(_T_356, _T_357) node _T_359 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_361 = shr(io.in.a.bits.source, 3) node _T_362 = eq(_T_361, UInt<3>(0h4)) node _T_363 = leq(UInt<1>(0h0), uncommonBits_19) node _T_364 = and(_T_362, _T_363) node _T_365 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_366 = and(_T_364, _T_365) node _T_367 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_369 = or(_T_336, _T_342) node _T_370 = or(_T_369, _T_348) node _T_371 = or(_T_370, _T_354) node _T_372 = or(_T_371, _T_360) node _T_373 = or(_T_372, _T_366) node _T_374 = or(_T_373, _T_367) node _T_375 = or(_T_374, _T_368) node _T_376 = and(_T_335, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<13>(0h1000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<17>(0h10000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<18>(0h2f000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<17>(0h10000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<13>(0h1000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_383, _T_388) node _T_420 = or(_T_419, _T_393) node _T_421 = or(_T_420, _T_398) node _T_422 = or(_T_421, _T_403) node _T_423 = or(_T_422, _T_408) node _T_424 = or(_T_423, _T_413) node _T_425 = or(_T_424, _T_418) node _T_426 = and(_T_378, _T_425) node _T_427 = or(UInt<1>(0h0), _T_426) node _T_428 = and(_T_377, _T_427) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_428, UInt<1>(0h1), "") : assert_10 node _T_432 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<1>(0h0)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_20) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<1>(0h1)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_21) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<2>(0h2)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_22) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_451 = shr(io.in.a.bits.source, 2) node _T_452 = eq(_T_451, UInt<2>(0h3)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_23) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_456 = and(_T_454, _T_455) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_457 = shr(io.in.a.bits.source, 3) node _T_458 = eq(_T_457, UInt<3>(0h4)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_24) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h28)) wire _WIRE_2 : UInt<1>[8] connect _WIRE_2[0], _T_432 connect _WIRE_2[1], _T_438 connect _WIRE_2[2], _T_444 connect _WIRE_2[3], _T_450 connect _WIRE_2[4], _T_456 connect _WIRE_2[5], _T_462 connect _WIRE_2[6], _T_463 connect _WIRE_2[7], _T_464 node _T_465 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_466 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_469 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE_2[5], _T_465, UInt<1>(0h0)) node _T_472 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = or(_T_466, _T_467) node _T_475 = or(_T_474, _T_468) node _T_476 = or(_T_475, _T_469) node _T_477 = or(_T_476, _T_470) node _T_478 = or(_T_477, _T_471) node _T_479 = or(_T_478, _T_472) node _T_480 = or(_T_479, _T_473) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_480 node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_483 = and(_T_481, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_486 = cvt(_T_485) node _T_487 = and(_T_486, asSInt(UInt<14>(0h2000))) node _T_488 = asSInt(_T_487) node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0))) node _T_490 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_491 = cvt(_T_490) node _T_492 = and(_T_491, asSInt(UInt<13>(0h1000))) node _T_493 = asSInt(_T_492) node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0))) node _T_495 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<17>(0h10000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<18>(0h2f000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_506 = cvt(_T_505) node _T_507 = and(_T_506, asSInt(UInt<17>(0h10000))) node _T_508 = asSInt(_T_507) node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0))) node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<13>(0h1000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = or(_T_489, _T_494) node _T_526 = or(_T_525, _T_499) node _T_527 = or(_T_526, _T_504) node _T_528 = or(_T_527, _T_509) node _T_529 = or(_T_528, _T_514) node _T_530 = or(_T_529, _T_519) node _T_531 = or(_T_530, _T_524) node _T_532 = and(_T_484, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = and(_WIRE_3, _T_533) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_534, UInt<1>(0h1), "") : assert_11 node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(source_ok, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_541 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_541, UInt<1>(0h1), "") : assert_13 node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(is_aligned, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_548 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_548, UInt<1>(0h1), "") : assert_15 node _T_552 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_552, UInt<1>(0h1), "") : assert_16 node _T_556 = not(io.in.a.bits.mask) node _T_557 = eq(_T_556, UInt<1>(0h0)) node _T_558 = asUInt(reset) node _T_559 = eq(_T_558, UInt<1>(0h0)) when _T_559 : node _T_560 = eq(_T_557, UInt<1>(0h0)) when _T_560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_557, UInt<1>(0h1), "") : assert_17 node _T_561 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_561, UInt<1>(0h1), "") : assert_18 node _T_565 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_565 : node _T_566 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_567 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_568 = and(_T_566, _T_567) node _T_569 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_570 = shr(io.in.a.bits.source, 2) node _T_571 = eq(_T_570, UInt<1>(0h0)) node _T_572 = leq(UInt<1>(0h0), uncommonBits_25) node _T_573 = and(_T_571, _T_572) node _T_574 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_575 = and(_T_573, _T_574) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_576 = shr(io.in.a.bits.source, 2) node _T_577 = eq(_T_576, UInt<1>(0h1)) node _T_578 = leq(UInt<1>(0h0), uncommonBits_26) node _T_579 = and(_T_577, _T_578) node _T_580 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<2>(0h2)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_27) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_588 = shr(io.in.a.bits.source, 2) node _T_589 = eq(_T_588, UInt<2>(0h3)) node _T_590 = leq(UInt<1>(0h0), uncommonBits_28) node _T_591 = and(_T_589, _T_590) node _T_592 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_593 = and(_T_591, _T_592) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_594 = shr(io.in.a.bits.source, 3) node _T_595 = eq(_T_594, UInt<3>(0h4)) node _T_596 = leq(UInt<1>(0h0), uncommonBits_29) node _T_597 = and(_T_595, _T_596) node _T_598 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_602 = or(_T_569, _T_575) node _T_603 = or(_T_602, _T_581) node _T_604 = or(_T_603, _T_587) node _T_605 = or(_T_604, _T_593) node _T_606 = or(_T_605, _T_599) node _T_607 = or(_T_606, _T_600) node _T_608 = or(_T_607, _T_601) node _T_609 = and(_T_568, _T_608) node _T_610 = or(UInt<1>(0h0), _T_609) node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_T_610, UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_610, UInt<1>(0h1), "") : assert_19 node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<17>(0h10000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<18>(0h2f000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<17>(0h10000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<13>(0h1000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = or(_T_632, _T_637) node _T_664 = or(_T_663, _T_642) node _T_665 = or(_T_664, _T_647) node _T_666 = or(_T_665, _T_652) node _T_667 = or(_T_666, _T_657) node _T_668 = or(_T_667, _T_662) node _T_669 = and(_T_627, _T_668) node _T_670 = or(UInt<1>(0h0), _T_623) node _T_671 = or(_T_670, _T_669) node _T_672 = asUInt(reset) node _T_673 = eq(_T_672, UInt<1>(0h0)) when _T_673 : node _T_674 = eq(_T_671, UInt<1>(0h0)) when _T_674 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_671, UInt<1>(0h1), "") : assert_20 node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(source_ok, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(is_aligned, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_681 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_682 = asUInt(reset) node _T_683 = eq(_T_682, UInt<1>(0h0)) when _T_683 : node _T_684 = eq(_T_681, UInt<1>(0h0)) when _T_684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_681, UInt<1>(0h1), "") : assert_23 node _T_685 = eq(io.in.a.bits.mask, mask) node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_T_685, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_685, UInt<1>(0h1), "") : assert_24 node _T_689 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_689, UInt<1>(0h1), "") : assert_25 node _T_693 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_693 : node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_696 = and(_T_694, _T_695) node _T_697 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_698 = shr(io.in.a.bits.source, 2) node _T_699 = eq(_T_698, UInt<1>(0h0)) node _T_700 = leq(UInt<1>(0h0), uncommonBits_30) node _T_701 = and(_T_699, _T_700) node _T_702 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_703 = and(_T_701, _T_702) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_704 = shr(io.in.a.bits.source, 2) node _T_705 = eq(_T_704, UInt<1>(0h1)) node _T_706 = leq(UInt<1>(0h0), uncommonBits_31) node _T_707 = and(_T_705, _T_706) node _T_708 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_710 = shr(io.in.a.bits.source, 2) node _T_711 = eq(_T_710, UInt<2>(0h2)) node _T_712 = leq(UInt<1>(0h0), uncommonBits_32) node _T_713 = and(_T_711, _T_712) node _T_714 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_715 = and(_T_713, _T_714) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_716 = shr(io.in.a.bits.source, 2) node _T_717 = eq(_T_716, UInt<2>(0h3)) node _T_718 = leq(UInt<1>(0h0), uncommonBits_33) node _T_719 = and(_T_717, _T_718) node _T_720 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_722 = shr(io.in.a.bits.source, 3) node _T_723 = eq(_T_722, UInt<3>(0h4)) node _T_724 = leq(UInt<1>(0h0), uncommonBits_34) node _T_725 = and(_T_723, _T_724) node _T_726 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_727 = and(_T_725, _T_726) node _T_728 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_729 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_730 = or(_T_697, _T_703) node _T_731 = or(_T_730, _T_709) node _T_732 = or(_T_731, _T_715) node _T_733 = or(_T_732, _T_721) node _T_734 = or(_T_733, _T_727) node _T_735 = or(_T_734, _T_728) node _T_736 = or(_T_735, _T_729) node _T_737 = and(_T_696, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_740 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_741 = and(_T_739, _T_740) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = and(_T_742, _T_747) node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_751 = and(_T_749, _T_750) node _T_752 = or(UInt<1>(0h0), _T_751) node _T_753 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<14>(0h2000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_759 = cvt(_T_758) node _T_760 = and(_T_759, asSInt(UInt<18>(0h2f000))) node _T_761 = asSInt(_T_760) node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) node _T_763 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_764 = cvt(_T_763) node _T_765 = and(_T_764, asSInt(UInt<17>(0h10000))) node _T_766 = asSInt(_T_765) node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0))) node _T_768 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<13>(0h1000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<27>(0h4000000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = or(_T_757, _T_762) node _T_784 = or(_T_783, _T_767) node _T_785 = or(_T_784, _T_772) node _T_786 = or(_T_785, _T_777) node _T_787 = or(_T_786, _T_782) node _T_788 = and(_T_752, _T_787) node _T_789 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_790 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = and(_T_789, _T_794) node _T_796 = or(UInt<1>(0h0), _T_748) node _T_797 = or(_T_796, _T_788) node _T_798 = or(_T_797, _T_795) node _T_799 = and(_T_738, _T_798) node _T_800 = asUInt(reset) node _T_801 = eq(_T_800, UInt<1>(0h0)) when _T_801 : node _T_802 = eq(_T_799, UInt<1>(0h0)) when _T_802 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_799, UInt<1>(0h1), "") : assert_26 node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(source_ok, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(is_aligned, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_809 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_809, UInt<1>(0h1), "") : assert_29 node _T_813 = eq(io.in.a.bits.mask, mask) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_813, UInt<1>(0h1), "") : assert_30 node _T_817 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_817 : node _T_818 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_819 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_820 = and(_T_818, _T_819) node _T_821 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_822 = shr(io.in.a.bits.source, 2) node _T_823 = eq(_T_822, UInt<1>(0h0)) node _T_824 = leq(UInt<1>(0h0), uncommonBits_35) node _T_825 = and(_T_823, _T_824) node _T_826 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_827 = and(_T_825, _T_826) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_828 = shr(io.in.a.bits.source, 2) node _T_829 = eq(_T_828, UInt<1>(0h1)) node _T_830 = leq(UInt<1>(0h0), uncommonBits_36) node _T_831 = and(_T_829, _T_830) node _T_832 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_833 = and(_T_831, _T_832) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_834 = shr(io.in.a.bits.source, 2) node _T_835 = eq(_T_834, UInt<2>(0h2)) node _T_836 = leq(UInt<1>(0h0), uncommonBits_37) node _T_837 = and(_T_835, _T_836) node _T_838 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_839 = and(_T_837, _T_838) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_840 = shr(io.in.a.bits.source, 2) node _T_841 = eq(_T_840, UInt<2>(0h3)) node _T_842 = leq(UInt<1>(0h0), uncommonBits_38) node _T_843 = and(_T_841, _T_842) node _T_844 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_845 = and(_T_843, _T_844) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_846 = shr(io.in.a.bits.source, 3) node _T_847 = eq(_T_846, UInt<3>(0h4)) node _T_848 = leq(UInt<1>(0h0), uncommonBits_39) node _T_849 = and(_T_847, _T_848) node _T_850 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_853 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_854 = or(_T_821, _T_827) node _T_855 = or(_T_854, _T_833) node _T_856 = or(_T_855, _T_839) node _T_857 = or(_T_856, _T_845) node _T_858 = or(_T_857, _T_851) node _T_859 = or(_T_858, _T_852) node _T_860 = or(_T_859, _T_853) node _T_861 = and(_T_820, _T_860) node _T_862 = or(UInt<1>(0h0), _T_861) node _T_863 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_864 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_865 = and(_T_863, _T_864) node _T_866 = or(UInt<1>(0h0), _T_865) node _T_867 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<13>(0h1000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = and(_T_866, _T_871) node _T_873 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_874 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_875 = and(_T_873, _T_874) node _T_876 = or(UInt<1>(0h0), _T_875) node _T_877 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<14>(0h2000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<18>(0h2f000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<17>(0h10000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<27>(0h4000000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<13>(0h1000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = or(_T_881, _T_886) node _T_908 = or(_T_907, _T_891) node _T_909 = or(_T_908, _T_896) node _T_910 = or(_T_909, _T_901) node _T_911 = or(_T_910, _T_906) node _T_912 = and(_T_876, _T_911) node _T_913 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_914 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = and(_T_913, _T_918) node _T_920 = or(UInt<1>(0h0), _T_872) node _T_921 = or(_T_920, _T_912) node _T_922 = or(_T_921, _T_919) node _T_923 = and(_T_862, _T_922) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_923, UInt<1>(0h1), "") : assert_31 node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(source_ok, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(is_aligned, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_933 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_933, UInt<1>(0h1), "") : assert_34 node _T_937 = not(mask) node _T_938 = and(io.in.a.bits.mask, _T_937) node _T_939 = eq(_T_938, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_939, UInt<1>(0h1), "") : assert_35 node _T_943 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_943 : node _T_944 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_945 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_946 = and(_T_944, _T_945) node _T_947 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_948 = shr(io.in.a.bits.source, 2) node _T_949 = eq(_T_948, UInt<1>(0h0)) node _T_950 = leq(UInt<1>(0h0), uncommonBits_40) node _T_951 = and(_T_949, _T_950) node _T_952 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<1>(0h1)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_41) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_959 = and(_T_957, _T_958) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_960 = shr(io.in.a.bits.source, 2) node _T_961 = eq(_T_960, UInt<2>(0h2)) node _T_962 = leq(UInt<1>(0h0), uncommonBits_42) node _T_963 = and(_T_961, _T_962) node _T_964 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_966 = shr(io.in.a.bits.source, 2) node _T_967 = eq(_T_966, UInt<2>(0h3)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_43) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_971 = and(_T_969, _T_970) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_972 = shr(io.in.a.bits.source, 3) node _T_973 = eq(_T_972, UInt<3>(0h4)) node _T_974 = leq(UInt<1>(0h0), uncommonBits_44) node _T_975 = and(_T_973, _T_974) node _T_976 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_977 = and(_T_975, _T_976) node _T_978 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_979 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_980 = or(_T_947, _T_953) node _T_981 = or(_T_980, _T_959) node _T_982 = or(_T_981, _T_965) node _T_983 = or(_T_982, _T_971) node _T_984 = or(_T_983, _T_977) node _T_985 = or(_T_984, _T_978) node _T_986 = or(_T_985, _T_979) node _T_987 = and(_T_946, _T_986) node _T_988 = or(UInt<1>(0h0), _T_987) node _T_989 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_990 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_991 = and(_T_989, _T_990) node _T_992 = or(UInt<1>(0h0), _T_991) node _T_993 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_994 = cvt(_T_993) node _T_995 = and(_T_994, asSInt(UInt<14>(0h2000))) node _T_996 = asSInt(_T_995) node _T_997 = eq(_T_996, asSInt(UInt<1>(0h0))) node _T_998 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1004 = cvt(_T_1003) node _T_1005 = and(_T_1004, asSInt(UInt<18>(0h2f000))) node _T_1006 = asSInt(_T_1005) node _T_1007 = eq(_T_1006, asSInt(UInt<1>(0h0))) node _T_1008 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1009 = cvt(_T_1008) node _T_1010 = and(_T_1009, asSInt(UInt<17>(0h10000))) node _T_1011 = asSInt(_T_1010) node _T_1012 = eq(_T_1011, asSInt(UInt<1>(0h0))) node _T_1013 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1014 = cvt(_T_1013) node _T_1015 = and(_T_1014, asSInt(UInt<13>(0h1000))) node _T_1016 = asSInt(_T_1015) node _T_1017 = eq(_T_1016, asSInt(UInt<1>(0h0))) node _T_1018 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1019 = cvt(_T_1018) node _T_1020 = and(_T_1019, asSInt(UInt<27>(0h4000000))) node _T_1021 = asSInt(_T_1020) node _T_1022 = eq(_T_1021, asSInt(UInt<1>(0h0))) node _T_1023 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<13>(0h1000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = or(_T_997, _T_1002) node _T_1029 = or(_T_1028, _T_1007) node _T_1030 = or(_T_1029, _T_1012) node _T_1031 = or(_T_1030, _T_1017) node _T_1032 = or(_T_1031, _T_1022) node _T_1033 = or(_T_1032, _T_1027) node _T_1034 = and(_T_992, _T_1033) node _T_1035 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1036 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1037 = cvt(_T_1036) node _T_1038 = and(_T_1037, asSInt(UInt<17>(0h10000))) node _T_1039 = asSInt(_T_1038) node _T_1040 = eq(_T_1039, asSInt(UInt<1>(0h0))) node _T_1041 = and(_T_1035, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1034) node _T_1043 = or(_T_1042, _T_1041) node _T_1044 = and(_T_988, _T_1043) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_36 node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(source_ok, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(is_aligned, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1054 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_39 node _T_1058 = eq(io.in.a.bits.mask, mask) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_40 node _T_1062 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1062 : node _T_1063 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1064 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1065 = and(_T_1063, _T_1064) node _T_1066 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_1067 = shr(io.in.a.bits.source, 2) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) node _T_1069 = leq(UInt<1>(0h0), uncommonBits_45) node _T_1070 = and(_T_1068, _T_1069) node _T_1071 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_1072 = and(_T_1070, _T_1071) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_1073 = shr(io.in.a.bits.source, 2) node _T_1074 = eq(_T_1073, UInt<1>(0h1)) node _T_1075 = leq(UInt<1>(0h0), uncommonBits_46) node _T_1076 = and(_T_1074, _T_1075) node _T_1077 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<2>(0h2)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_47) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<2>(0h3)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_1091 = shr(io.in.a.bits.source, 3) node _T_1092 = eq(_T_1091, UInt<3>(0h4)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1099 = or(_T_1066, _T_1072) node _T_1100 = or(_T_1099, _T_1078) node _T_1101 = or(_T_1100, _T_1084) node _T_1102 = or(_T_1101, _T_1090) node _T_1103 = or(_T_1102, _T_1096) node _T_1104 = or(_T_1103, _T_1097) node _T_1105 = or(_T_1104, _T_1098) node _T_1106 = and(_T_1065, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1109 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = or(UInt<1>(0h0), _T_1110) node _T_1112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<14>(0h2000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1118 = cvt(_T_1117) node _T_1119 = and(_T_1118, asSInt(UInt<13>(0h1000))) node _T_1120 = asSInt(_T_1119) node _T_1121 = eq(_T_1120, asSInt(UInt<1>(0h0))) node _T_1122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1123 = cvt(_T_1122) node _T_1124 = and(_T_1123, asSInt(UInt<18>(0h2f000))) node _T_1125 = asSInt(_T_1124) node _T_1126 = eq(_T_1125, asSInt(UInt<1>(0h0))) node _T_1127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1128 = cvt(_T_1127) node _T_1129 = and(_T_1128, asSInt(UInt<17>(0h10000))) node _T_1130 = asSInt(_T_1129) node _T_1131 = eq(_T_1130, asSInt(UInt<1>(0h0))) node _T_1132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1133 = cvt(_T_1132) node _T_1134 = and(_T_1133, asSInt(UInt<13>(0h1000))) node _T_1135 = asSInt(_T_1134) node _T_1136 = eq(_T_1135, asSInt(UInt<1>(0h0))) node _T_1137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<27>(0h4000000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<13>(0h1000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = or(_T_1116, _T_1121) node _T_1148 = or(_T_1147, _T_1126) node _T_1149 = or(_T_1148, _T_1131) node _T_1150 = or(_T_1149, _T_1136) node _T_1151 = or(_T_1150, _T_1141) node _T_1152 = or(_T_1151, _T_1146) node _T_1153 = and(_T_1111, _T_1152) node _T_1154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1155 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1156 = cvt(_T_1155) node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000))) node _T_1158 = asSInt(_T_1157) node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0))) node _T_1160 = and(_T_1154, _T_1159) node _T_1161 = or(UInt<1>(0h0), _T_1153) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = and(_T_1107, _T_1162) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_41 node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(source_ok, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(is_aligned, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1173 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_44 node _T_1177 = eq(io.in.a.bits.mask, mask) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_45 node _T_1181 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1181 : node _T_1182 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1183 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1184 = and(_T_1182, _T_1183) node _T_1185 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1186 = shr(io.in.a.bits.source, 2) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) node _T_1188 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1189 = and(_T_1187, _T_1188) node _T_1190 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1191 = and(_T_1189, _T_1190) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1192 = shr(io.in.a.bits.source, 2) node _T_1193 = eq(_T_1192, UInt<1>(0h1)) node _T_1194 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1195 = and(_T_1193, _T_1194) node _T_1196 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1197 = and(_T_1195, _T_1196) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_1198 = shr(io.in.a.bits.source, 2) node _T_1199 = eq(_T_1198, UInt<2>(0h2)) node _T_1200 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1201 = and(_T_1199, _T_1200) node _T_1202 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_1203 = and(_T_1201, _T_1202) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_1204 = shr(io.in.a.bits.source, 2) node _T_1205 = eq(_T_1204, UInt<2>(0h3)) node _T_1206 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1207 = and(_T_1205, _T_1206) node _T_1208 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_1209 = and(_T_1207, _T_1208) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_1210 = shr(io.in.a.bits.source, 3) node _T_1211 = eq(_T_1210, UInt<3>(0h4)) node _T_1212 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1218 = or(_T_1185, _T_1191) node _T_1219 = or(_T_1218, _T_1197) node _T_1220 = or(_T_1219, _T_1203) node _T_1221 = or(_T_1220, _T_1209) node _T_1222 = or(_T_1221, _T_1215) node _T_1223 = or(_T_1222, _T_1216) node _T_1224 = or(_T_1223, _T_1217) node _T_1225 = and(_T_1184, _T_1224) node _T_1226 = or(UInt<1>(0h0), _T_1225) node _T_1227 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1228 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1229 = and(_T_1227, _T_1228) node _T_1230 = or(UInt<1>(0h0), _T_1229) node _T_1231 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1232 = cvt(_T_1231) node _T_1233 = and(_T_1232, asSInt(UInt<13>(0h1000))) node _T_1234 = asSInt(_T_1233) node _T_1235 = eq(_T_1234, asSInt(UInt<1>(0h0))) node _T_1236 = and(_T_1230, _T_1235) node _T_1237 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1238 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<14>(0h2000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<27>(0h4000000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<13>(0h1000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = or(_T_1242, _T_1247) node _T_1274 = or(_T_1273, _T_1252) node _T_1275 = or(_T_1274, _T_1257) node _T_1276 = or(_T_1275, _T_1262) node _T_1277 = or(_T_1276, _T_1267) node _T_1278 = or(_T_1277, _T_1272) node _T_1279 = and(_T_1237, _T_1278) node _T_1280 = or(UInt<1>(0h0), _T_1236) node _T_1281 = or(_T_1280, _T_1279) node _T_1282 = and(_T_1226, _T_1281) node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(_T_1282, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1282, UInt<1>(0h1), "") : assert_46 node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(source_ok, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(is_aligned, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1292 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1293 = asUInt(reset) node _T_1294 = eq(_T_1293, UInt<1>(0h0)) when _T_1294 : node _T_1295 = eq(_T_1292, UInt<1>(0h0)) when _T_1295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1292, UInt<1>(0h1), "") : assert_49 node _T_1296 = eq(io.in.a.bits.mask, mask) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_50 node _T_1300 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1304 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_52 node _source_ok_T_39 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_40 = shr(io.in.d.bits.source, 2) node _source_ok_T_41 = eq(_source_ok_T_40, UInt<1>(0h0)) node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_T_44 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_46 = shr(io.in.d.bits.source, 2) node _source_ok_T_47 = eq(_source_ok_T_46, UInt<1>(0h1)) node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_T_50 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_52 = shr(io.in.d.bits.source, 2) node _source_ok_T_53 = eq(_source_ok_T_52, UInt<2>(0h2)) node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_58 = shr(io.in.d.bits.source, 2) node _source_ok_T_59 = eq(_source_ok_T_58, UInt<2>(0h3)) node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_64 = shr(io.in.d.bits.source, 3) node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h4)) node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h28)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_39 connect _source_ok_WIRE_1[1], _source_ok_T_45 connect _source_ok_WIRE_1[2], _source_ok_T_51 connect _source_ok_WIRE_1[3], _source_ok_T_57 connect _source_ok_WIRE_1[4], _source_ok_T_63 connect _source_ok_WIRE_1[5], _source_ok_T_69 connect _source_ok_WIRE_1[6], _source_ok_T_70 connect _source_ok_WIRE_1[7], _source_ok_T_71 node _source_ok_T_72 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[2]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[3]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[4]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[5]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_77, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1308 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1312 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_54 node _T_1316 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_55 node _T_1320 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(_T_1320, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1320, UInt<1>(0h1), "") : assert_56 node _T_1324 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_57 node _T_1328 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1328 : node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(source_ok_1, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(sink_ok, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1335 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_60 node _T_1339 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_61 node _T_1343 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_62 node _T_1347 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_63 node _T_1351 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1352 = or(UInt<1>(0h1), _T_1351) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_64 node _T_1356 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1356 : node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(source_ok_1, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1360 = asUInt(reset) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(sink_ok, UInt<1>(0h0)) when _T_1362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1363 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1364 = asUInt(reset) node _T_1365 = eq(_T_1364, UInt<1>(0h0)) when _T_1365 : node _T_1366 = eq(_T_1363, UInt<1>(0h0)) when _T_1366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1363, UInt<1>(0h1), "") : assert_67 node _T_1367 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_68 node _T_1371 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_69 node _T_1375 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1376 = or(_T_1375, io.in.d.bits.corrupt) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_70 node _T_1380 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1381 = or(UInt<1>(0h1), _T_1380) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_71 node _T_1385 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1385 : node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(source_ok_1, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1389 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_73 node _T_1393 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_74 node _T_1397 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1398 = or(UInt<1>(0h1), _T_1397) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_75 node _T_1402 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1402 : node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(source_ok_1, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1406 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_77 node _T_1410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1411 = or(_T_1410, io.in.d.bits.corrupt) node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(_T_1411, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1411, UInt<1>(0h1), "") : assert_78 node _T_1415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1416 = or(UInt<1>(0h1), _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_79 node _T_1420 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1420 : node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(source_ok_1, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1425 = asUInt(reset) node _T_1426 = eq(_T_1425, UInt<1>(0h0)) when _T_1426 : node _T_1427 = eq(_T_1424, UInt<1>(0h0)) when _T_1427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1424, UInt<1>(0h1), "") : assert_81 node _T_1428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_82 node _T_1432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1433 = or(UInt<1>(0h1), _T_1432) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<128>(0h0) connect _WIRE_4.bits.mask, UInt<16>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<6>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1437 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1438 = asUInt(reset) node _T_1439 = eq(_T_1438, UInt<1>(0h0)) when _T_1439 : node _T_1440 = eq(_T_1437, UInt<1>(0h0)) when _T_1440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1437, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<6>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1441 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1445 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1449 = eq(a_first, UInt<1>(0h0)) node _T_1450 = and(io.in.a.valid, _T_1449) when _T_1450 : node _T_1451 = eq(io.in.a.bits.opcode, opcode) node _T_1452 = asUInt(reset) node _T_1453 = eq(_T_1452, UInt<1>(0h0)) when _T_1453 : node _T_1454 = eq(_T_1451, UInt<1>(0h0)) when _T_1454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1451, UInt<1>(0h1), "") : assert_87 node _T_1455 = eq(io.in.a.bits.param, param) node _T_1456 = asUInt(reset) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(_T_1455, UInt<1>(0h0)) when _T_1458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1455, UInt<1>(0h1), "") : assert_88 node _T_1459 = eq(io.in.a.bits.size, size) node _T_1460 = asUInt(reset) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) when _T_1461 : node _T_1462 = eq(_T_1459, UInt<1>(0h0)) when _T_1462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1459, UInt<1>(0h1), "") : assert_89 node _T_1463 = eq(io.in.a.bits.source, source) node _T_1464 = asUInt(reset) node _T_1465 = eq(_T_1464, UInt<1>(0h0)) when _T_1465 : node _T_1466 = eq(_T_1463, UInt<1>(0h0)) when _T_1466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1463, UInt<1>(0h1), "") : assert_90 node _T_1467 = eq(io.in.a.bits.address, address) node _T_1468 = asUInt(reset) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(_T_1467, UInt<1>(0h0)) when _T_1470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1467, UInt<1>(0h1), "") : assert_91 node _T_1471 = and(io.in.a.ready, io.in.a.valid) node _T_1472 = and(_T_1471, a_first) when _T_1472 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1473 = eq(d_first, UInt<1>(0h0)) node _T_1474 = and(io.in.d.valid, _T_1473) when _T_1474 : node _T_1475 = eq(io.in.d.bits.opcode, opcode_1) node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(_T_1475, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1475, UInt<1>(0h1), "") : assert_92 node _T_1479 = eq(io.in.d.bits.param, param_1) node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(_T_1479, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1479, UInt<1>(0h1), "") : assert_93 node _T_1483 = eq(io.in.d.bits.size, size_1) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_94 node _T_1487 = eq(io.in.d.bits.source, source_1) node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(_T_1487, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1487, UInt<1>(0h1), "") : assert_95 node _T_1491 = eq(io.in.d.bits.sink, sink) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_96 node _T_1495 = eq(io.in.d.bits.denied, denied) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_97 node _T_1499 = and(io.in.d.ready, io.in.d.valid) node _T_1500 = and(_T_1499, d_first) when _T_1500 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<41>, clock, reset, UInt<41>(0h0) regreset inflight_opcodes : UInt<164>, clock, reset, UInt<164>(0h0) regreset inflight_sizes : UInt<328>, clock, reset, UInt<328>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<41> connect a_set, UInt<41>(0h0) wire a_set_wo_ready : UInt<41> connect a_set_wo_ready, UInt<41>(0h0) wire a_opcodes_set : UInt<164> connect a_opcodes_set, UInt<164>(0h0) wire a_sizes_set : UInt<328> connect a_sizes_set, UInt<328>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1501 = and(io.in.a.valid, a_first_1) node _T_1502 = and(_T_1501, UInt<1>(0h1)) when _T_1502 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1503 = and(io.in.a.ready, io.in.a.valid) node _T_1504 = and(_T_1503, a_first_1) node _T_1505 = and(_T_1504, UInt<1>(0h1)) when _T_1505 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1506 = dshr(inflight, io.in.a.bits.source) node _T_1507 = bits(_T_1506, 0, 0) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) node _T_1509 = asUInt(reset) node _T_1510 = eq(_T_1509, UInt<1>(0h0)) when _T_1510 : node _T_1511 = eq(_T_1508, UInt<1>(0h0)) when _T_1511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1508, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<41> connect d_clr, UInt<41>(0h0) wire d_clr_wo_ready : UInt<41> connect d_clr_wo_ready, UInt<41>(0h0) wire d_opcodes_clr : UInt<164> connect d_opcodes_clr, UInt<164>(0h0) wire d_sizes_clr : UInt<328> connect d_sizes_clr, UInt<328>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1512 = and(io.in.d.valid, d_first_1) node _T_1513 = and(_T_1512, UInt<1>(0h1)) node _T_1514 = eq(d_release_ack, UInt<1>(0h0)) node _T_1515 = and(_T_1513, _T_1514) when _T_1515 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1516 = and(io.in.d.ready, io.in.d.valid) node _T_1517 = and(_T_1516, d_first_1) node _T_1518 = and(_T_1517, UInt<1>(0h1)) node _T_1519 = eq(d_release_ack, UInt<1>(0h0)) node _T_1520 = and(_T_1518, _T_1519) when _T_1520 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1521 = and(io.in.d.valid, d_first_1) node _T_1522 = and(_T_1521, UInt<1>(0h1)) node _T_1523 = eq(d_release_ack, UInt<1>(0h0)) node _T_1524 = and(_T_1522, _T_1523) when _T_1524 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1525 = dshr(inflight, io.in.d.bits.source) node _T_1526 = bits(_T_1525, 0, 0) node _T_1527 = or(_T_1526, same_cycle_resp) node _T_1528 = asUInt(reset) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(_T_1527, UInt<1>(0h0)) when _T_1530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1527, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1531 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1532 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1533 = or(_T_1531, _T_1532) node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(_T_1533, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1533, UInt<1>(0h1), "") : assert_100 node _T_1537 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_101 else : node _T_1541 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1542 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1543 = or(_T_1541, _T_1542) node _T_1544 = asUInt(reset) node _T_1545 = eq(_T_1544, UInt<1>(0h0)) when _T_1545 : node _T_1546 = eq(_T_1543, UInt<1>(0h0)) when _T_1546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1543, UInt<1>(0h1), "") : assert_102 node _T_1547 = eq(io.in.d.bits.size, a_size_lookup) node _T_1548 = asUInt(reset) node _T_1549 = eq(_T_1548, UInt<1>(0h0)) when _T_1549 : node _T_1550 = eq(_T_1547, UInt<1>(0h0)) when _T_1550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1547, UInt<1>(0h1), "") : assert_103 node _T_1551 = and(io.in.d.valid, d_first_1) node _T_1552 = and(_T_1551, a_first_1) node _T_1553 = and(_T_1552, io.in.a.valid) node _T_1554 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1555 = and(_T_1553, _T_1554) node _T_1556 = eq(d_release_ack, UInt<1>(0h0)) node _T_1557 = and(_T_1555, _T_1556) when _T_1557 : node _T_1558 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1559 = or(_T_1558, io.in.a.ready) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_104 node _T_1563 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1564 = orr(a_set_wo_ready) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = or(_T_1563, _T_1565) node _T_1567 = asUInt(reset) node _T_1568 = eq(_T_1567, UInt<1>(0h0)) when _T_1568 : node _T_1569 = eq(_T_1566, UInt<1>(0h0)) when _T_1569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1566, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_4 node _T_1570 = orr(inflight) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) node _T_1572 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1573 = or(_T_1571, _T_1572) node _T_1574 = lt(watchdog, plusarg_reader.out) node _T_1575 = or(_T_1573, _T_1574) node _T_1576 = asUInt(reset) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(_T_1575, UInt<1>(0h0)) when _T_1578 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1575, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1579 = and(io.in.a.ready, io.in.a.valid) node _T_1580 = and(io.in.d.ready, io.in.d.valid) node _T_1581 = or(_T_1579, _T_1580) when _T_1581 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<41>, clock, reset, UInt<41>(0h0) regreset inflight_opcodes_1 : UInt<164>, clock, reset, UInt<164>(0h0) regreset inflight_sizes_1 : UInt<328>, clock, reset, UInt<328>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<6>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<6>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<41> connect c_set, UInt<41>(0h0) wire c_set_wo_ready : UInt<41> connect c_set_wo_ready, UInt<41>(0h0) wire c_opcodes_set : UInt<164> connect c_opcodes_set, UInt<164>(0h0) wire c_sizes_set : UInt<328> connect c_sizes_set, UInt<328>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<6>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1582 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<6>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1583 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1584 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = and(_T_1582, _T_1585) when _T_1586 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<6>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1587 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1588 = and(_T_1587, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<6>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1589 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1590 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1591 = and(_T_1589, _T_1590) node _T_1592 = and(_T_1588, _T_1591) when _T_1592 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<6>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<6>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1593 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1594 = bits(_T_1593, 0, 0) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) node _T_1596 = asUInt(reset) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) when _T_1597 : node _T_1598 = eq(_T_1595, UInt<1>(0h0)) when _T_1598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1595, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<41> connect d_clr_1, UInt<41>(0h0) wire d_clr_wo_ready_1 : UInt<41> connect d_clr_wo_ready_1, UInt<41>(0h0) wire d_opcodes_clr_1 : UInt<164> connect d_opcodes_clr_1, UInt<164>(0h0) wire d_sizes_clr_1 : UInt<328> connect d_sizes_clr_1, UInt<328>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1599 = and(io.in.d.valid, d_first_2) node _T_1600 = and(_T_1599, UInt<1>(0h1)) node _T_1601 = and(_T_1600, d_release_ack_1) when _T_1601 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1602 = and(io.in.d.ready, io.in.d.valid) node _T_1603 = and(_T_1602, d_first_2) node _T_1604 = and(_T_1603, UInt<1>(0h1)) node _T_1605 = and(_T_1604, d_release_ack_1) when _T_1605 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1606 = and(io.in.d.valid, d_first_2) node _T_1607 = and(_T_1606, UInt<1>(0h1)) node _T_1608 = and(_T_1607, d_release_ack_1) when _T_1608 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1609 = dshr(inflight_1, io.in.d.bits.source) node _T_1610 = bits(_T_1609, 0, 0) node _T_1611 = or(_T_1610, same_cycle_resp_1) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<6>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1615 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_109 else : node _T_1619 = eq(io.in.d.bits.size, c_size_lookup) node _T_1620 = asUInt(reset) node _T_1621 = eq(_T_1620, UInt<1>(0h0)) when _T_1621 : node _T_1622 = eq(_T_1619, UInt<1>(0h0)) when _T_1622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1619, UInt<1>(0h1), "") : assert_110 node _T_1623 = and(io.in.d.valid, d_first_2) node _T_1624 = and(_T_1623, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<6>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1625 = and(_T_1624, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<6>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1626 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1627 = and(_T_1625, _T_1626) node _T_1628 = and(_T_1627, d_release_ack_1) node _T_1629 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1630 = and(_T_1628, _T_1629) when _T_1630 : node _T_1631 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<128>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<6>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1632 = or(_T_1631, _WIRE_27.ready) node _T_1633 = asUInt(reset) node _T_1634 = eq(_T_1633, UInt<1>(0h0)) when _T_1634 : node _T_1635 = eq(_T_1632, UInt<1>(0h0)) when _T_1635 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1632, UInt<1>(0h1), "") : assert_111 node _T_1636 = orr(c_set_wo_ready) when _T_1636 : node _T_1637 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1638 = asUInt(reset) node _T_1639 = eq(_T_1638, UInt<1>(0h0)) when _T_1639 : node _T_1640 = eq(_T_1637, UInt<1>(0h0)) when _T_1640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1637, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_5 node _T_1641 = orr(inflight_1) node _T_1642 = eq(_T_1641, UInt<1>(0h0)) node _T_1643 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1644 = or(_T_1642, _T_1643) node _T_1645 = lt(watchdog_1, plusarg_reader_1.out) node _T_1646 = or(_T_1644, _T_1645) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:207:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<128>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<6>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1650 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1651 = and(io.in.d.ready, io.in.d.valid) node _T_1652 = or(_T_1650, _T_1651) when _T_1652 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_2( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74] wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [515:0] _c_sizes_set_T_1 = 516'h0; // @[Monitor.scala:768:52] wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77] wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35] wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35] wire [327:0] c_sizes_set = 328'h0; // @[Monitor.scala:741:34] wire [163:0] c_opcodes_set = 164'h0; // @[Monitor.scala:740:34] wire [40:0] c_set = 41'h0; // @[Monitor.scala:738:34] wire [40:0] c_set_wo_ready = 41'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 6'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_38 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_40 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_46 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_52 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_58 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_41 = _source_ok_T_40 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_47 = _source_ok_T_46 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_53 = _source_ok_T_52 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 4'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_64 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_65 = _source_ok_T_64 == 3'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_69 = _source_ok_T_67 & _source_ok_T_68; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire _source_ok_T_70 = io_in_d_bits_source_0 == 6'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire _source_ok_T_71 = io_in_d_bits_source_0 == 6'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_77 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1579 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1579; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1579; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1652 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1652; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1652; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [40:0] inflight; // @[Monitor.scala:614:27] reg [163:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [327:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [40:0] a_set; // @[Monitor.scala:626:34] wire [40:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [163:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [327:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [163:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [163:0] _a_opcode_lookup_T_6 = {160'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [163:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [8:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [327:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [327:0] _a_size_lookup_T_6 = {320'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [327:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[327:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_3 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1505 = _T_1579 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1505 ? _a_set_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1505 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1505 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1505 ? _a_opcodes_set_T_1[163:0] : 164'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [8:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [515:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1505 ? _a_sizes_set_T_1[327:0] : 328'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [40:0] d_clr; // @[Monitor.scala:664:34] wire [40:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [163:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [327:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1551 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1551 & ~d_release_ack ? _d_clr_wo_ready_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1520 = _T_1652 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1520 ? _d_clr_T[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1520 ? _d_opcodes_clr_T_5[163:0] : 164'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1520 ? _d_sizes_clr_T_5[327:0] : 328'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [40:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [40:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [40:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [163:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [163:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [163:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [327:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [327:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [327:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [40:0] inflight_1; // @[Monitor.scala:726:35] wire [40:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [163:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [163:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [327:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [327:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [163:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [163:0] _c_opcode_lookup_T_6 = {160'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [163:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[163:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [327:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [327:0] _c_size_lookup_T_6 = {320'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [327:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[327:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [40:0] d_clr_1; // @[Monitor.scala:774:34] wire [40:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [163:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [327:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1623 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1623 & d_release_ack_1 ? _d_clr_wo_ready_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire _T_1605 = _T_1652 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1605 ? _d_clr_T_1[40:0] : 41'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1605 ? _d_opcodes_clr_T_11[163:0] : 164'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1605 ? _d_sizes_clr_T_11[327:0] : 328'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113] wire [40:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [40:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [163:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [163:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [327:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [327:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]

Generate the Verilog code corresponding to this FIRRTL code module AccPipe_5 : input clock : Clock input reset : Reset output io : { flip op1 : SInt<32>, flip op2 : SInt<32>, sum : SInt<32>} node _io_sum_T = add(io.op1, io.op2) node _io_sum_T_1 = tail(_io_sum_T, 1) node _io_sum_T_2 = asSInt(_io_sum_T_1) reg io_sum_r : SInt<32>, clock when UInt<1>(0h1) : connect io_sum_r, _io_sum_T_2 connect io.sum, io_sum_r

module AccPipe_5( // @[AccumulatorMem.scala:63:7] input clock, // @[AccumulatorMem.scala:63:7] input reset, // @[AccumulatorMem.scala:63:7] input [31:0] io_op1, // @[AccumulatorMem.scala:64:14] input [31:0] io_op2, // @[AccumulatorMem.scala:64:14] output [31:0] io_sum // @[AccumulatorMem.scala:64:14] ); wire [31:0] io_op1_0 = io_op1; // @[AccumulatorMem.scala:63:7] wire [31:0] io_op2_0 = io_op2; // @[AccumulatorMem.scala:63:7] wire [31:0] io_sum_0; // @[AccumulatorMem.scala:63:7] wire [32:0] _io_sum_T = {io_op1_0[31], io_op1_0} + {io_op2_0[31], io_op2_0}; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_1 = _io_sum_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _io_sum_T_2 = _io_sum_T_1; // @[Arithmetic.scala:94:38] reg [31:0] io_sum_r; // @[AccumulatorMem.scala:70:26] assign io_sum_0 = io_sum_r; // @[AccumulatorMem.scala:63:7, :70:26] always @(posedge clock) // @[AccumulatorMem.scala:63:7] io_sum_r <= _io_sum_T_2; // @[Arithmetic.scala:94:38] assign io_sum = io_sum_0; // @[AccumulatorMem.scala:63:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<17>(0h10000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<17>(0h10000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<17>(0h10000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<17>(0h10000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1294 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1295 = cvt(_T_1294) node _T_1296 = and(_T_1295, asSInt(UInt<17>(0h10000))) node _T_1297 = asSInt(_T_1296) node _T_1298 = eq(_T_1297, asSInt(UInt<1>(0h0))) node _T_1299 = and(_T_1293, _T_1298) node _T_1300 = or(UInt<1>(0h0), _T_1299) node _T_1301 = and(_T_1292, _T_1300) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_26 node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(source_ok, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(is_aligned, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1311 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_29 node _T_1315 = eq(io.in.a.bits.mask, mask) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_30 node _T_1319 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1321 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1324 = shr(io.in.a.bits.source, 2) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) node _T_1326 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1327 = and(_T_1325, _T_1326) node _T_1328 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1329 = and(_T_1327, _T_1328) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1330 = shr(io.in.a.bits.source, 2) node _T_1331 = eq(_T_1330, UInt<1>(0h1)) node _T_1332 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1333 = and(_T_1331, _T_1332) node _T_1334 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1335 = and(_T_1333, _T_1334) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1336 = shr(io.in.a.bits.source, 2) node _T_1337 = eq(_T_1336, UInt<2>(0h2)) node _T_1338 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1341 = and(_T_1339, _T_1340) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1342 = shr(io.in.a.bits.source, 2) node _T_1343 = eq(_T_1342, UInt<2>(0h3)) node _T_1344 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1345 = and(_T_1343, _T_1344) node _T_1346 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1349 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1350 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1360 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1361 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1362 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1384 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1385 = or(_T_1323, _T_1329) node _T_1386 = or(_T_1385, _T_1335) node _T_1387 = or(_T_1386, _T_1341) node _T_1388 = or(_T_1387, _T_1347) node _T_1389 = or(_T_1388, _T_1348) node _T_1390 = or(_T_1389, _T_1349) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = and(_T_1322, _T_1425) node _T_1427 = or(UInt<1>(0h0), _T_1426) node _T_1428 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1429 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1430 = cvt(_T_1429) node _T_1431 = and(_T_1430, asSInt(UInt<17>(0h10000))) node _T_1432 = asSInt(_T_1431) node _T_1433 = eq(_T_1432, asSInt(UInt<1>(0h0))) node _T_1434 = and(_T_1428, _T_1433) node _T_1435 = or(UInt<1>(0h0), _T_1434) node _T_1436 = and(_T_1427, _T_1435) node _T_1437 = asUInt(reset) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : node _T_1439 = eq(_T_1436, UInt<1>(0h0)) when _T_1439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1436, UInt<1>(0h1), "") : assert_31 node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(source_ok, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(is_aligned, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1446 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1447 = asUInt(reset) node _T_1448 = eq(_T_1447, UInt<1>(0h0)) when _T_1448 : node _T_1449 = eq(_T_1446, UInt<1>(0h0)) when _T_1449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1446, UInt<1>(0h1), "") : assert_34 node _T_1450 = not(mask) node _T_1451 = and(io.in.a.bits.mask, _T_1450) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_35 node _T_1456 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1456 : node _T_1457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1459 = and(_T_1457, _T_1458) node _T_1460 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1461 = shr(io.in.a.bits.source, 2) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) node _T_1463 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1466 = and(_T_1464, _T_1465) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h1)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<2>(0h2)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h3)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _T_1485 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1486 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1487 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1488 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1489 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1490 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1521 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1522 = or(_T_1460, _T_1466) node _T_1523 = or(_T_1522, _T_1472) node _T_1524 = or(_T_1523, _T_1478) node _T_1525 = or(_T_1524, _T_1484) node _T_1526 = or(_T_1525, _T_1485) node _T_1527 = or(_T_1526, _T_1486) node _T_1528 = or(_T_1527, _T_1487) node _T_1529 = or(_T_1528, _T_1488) node _T_1530 = or(_T_1529, _T_1489) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = and(_T_1459, _T_1562) node _T_1564 = or(UInt<1>(0h0), _T_1563) node _T_1565 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1566 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1567 = cvt(_T_1566) node _T_1568 = and(_T_1567, asSInt(UInt<17>(0h10000))) node _T_1569 = asSInt(_T_1568) node _T_1570 = eq(_T_1569, asSInt(UInt<1>(0h0))) node _T_1571 = and(_T_1565, _T_1570) node _T_1572 = or(UInt<1>(0h0), _T_1571) node _T_1573 = and(_T_1564, _T_1572) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_36 node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(source_ok, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(is_aligned, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1583 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(_T_1583, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1583, UInt<1>(0h1), "") : assert_39 node _T_1587 = eq(io.in.a.bits.mask, mask) node _T_1588 = asUInt(reset) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(_T_1587, UInt<1>(0h0)) when _T_1590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1587, UInt<1>(0h1), "") : assert_40 node _T_1591 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1591 : node _T_1592 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1593 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1594 = and(_T_1592, _T_1593) node _T_1595 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1596 = shr(io.in.a.bits.source, 2) node _T_1597 = eq(_T_1596, UInt<1>(0h0)) node _T_1598 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1601 = and(_T_1599, _T_1600) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h1)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<2>(0h2)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h3)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _T_1620 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1621 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1622 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1623 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1624 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1625 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1632 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1633 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1634 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1635 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1636 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1637 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1656 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1657 = or(_T_1595, _T_1601) node _T_1658 = or(_T_1657, _T_1607) node _T_1659 = or(_T_1658, _T_1613) node _T_1660 = or(_T_1659, _T_1619) node _T_1661 = or(_T_1660, _T_1620) node _T_1662 = or(_T_1661, _T_1621) node _T_1663 = or(_T_1662, _T_1622) node _T_1664 = or(_T_1663, _T_1623) node _T_1665 = or(_T_1664, _T_1624) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = and(_T_1594, _T_1697) node _T_1699 = or(UInt<1>(0h0), _T_1698) node _T_1700 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1701 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1702 = cvt(_T_1701) node _T_1703 = and(_T_1702, asSInt(UInt<17>(0h10000))) node _T_1704 = asSInt(_T_1703) node _T_1705 = eq(_T_1704, asSInt(UInt<1>(0h0))) node _T_1706 = and(_T_1700, _T_1705) node _T_1707 = or(UInt<1>(0h0), _T_1706) node _T_1708 = and(_T_1699, _T_1707) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_41 node _T_1712 = asUInt(reset) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) when _T_1713 : node _T_1714 = eq(source_ok, UInt<1>(0h0)) when _T_1714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(is_aligned, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1718 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1719 = asUInt(reset) node _T_1720 = eq(_T_1719, UInt<1>(0h0)) when _T_1720 : node _T_1721 = eq(_T_1718, UInt<1>(0h0)) when _T_1721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1718, UInt<1>(0h1), "") : assert_44 node _T_1722 = eq(io.in.a.bits.mask, mask) node _T_1723 = asUInt(reset) node _T_1724 = eq(_T_1723, UInt<1>(0h0)) when _T_1724 : node _T_1725 = eq(_T_1722, UInt<1>(0h0)) when _T_1725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1722, UInt<1>(0h1), "") : assert_45 node _T_1726 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1726 : node _T_1727 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1728 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1729 = and(_T_1727, _T_1728) node _T_1730 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1731 = shr(io.in.a.bits.source, 2) node _T_1732 = eq(_T_1731, UInt<1>(0h0)) node _T_1733 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1734 = and(_T_1732, _T_1733) node _T_1735 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1736 = and(_T_1734, _T_1735) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h1)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<2>(0h2)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h3)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _T_1755 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1756 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1757 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1758 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1759 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1760 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1767 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1768 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1769 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1770 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1771 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1772 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1791 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1792 = or(_T_1730, _T_1736) node _T_1793 = or(_T_1792, _T_1742) node _T_1794 = or(_T_1793, _T_1748) node _T_1795 = or(_T_1794, _T_1754) node _T_1796 = or(_T_1795, _T_1755) node _T_1797 = or(_T_1796, _T_1756) node _T_1798 = or(_T_1797, _T_1757) node _T_1799 = or(_T_1798, _T_1758) node _T_1800 = or(_T_1799, _T_1759) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = and(_T_1729, _T_1832) node _T_1834 = or(UInt<1>(0h0), _T_1833) node _T_1835 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1836 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1837 = cvt(_T_1836) node _T_1838 = and(_T_1837, asSInt(UInt<17>(0h10000))) node _T_1839 = asSInt(_T_1838) node _T_1840 = eq(_T_1839, asSInt(UInt<1>(0h0))) node _T_1841 = and(_T_1835, _T_1840) node _T_1842 = or(UInt<1>(0h0), _T_1841) node _T_1843 = and(_T_1834, _T_1842) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_46 node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(source_ok, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(is_aligned, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1853 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_49 node _T_1857 = eq(io.in.a.bits.mask, mask) node _T_1858 = asUInt(reset) node _T_1859 = eq(_T_1858, UInt<1>(0h0)) when _T_1859 : node _T_1860 = eq(_T_1857, UInt<1>(0h0)) when _T_1860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1857, UInt<1>(0h1), "") : assert_50 node _T_1861 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1862 = asUInt(reset) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) when _T_1863 : node _T_1864 = eq(_T_1861, UInt<1>(0h0)) when _T_1864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1861, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1865 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1866 = asUInt(reset) node _T_1867 = eq(_T_1866, UInt<1>(0h0)) when _T_1867 : node _T_1868 = eq(_T_1865, UInt<1>(0h0)) when _T_1868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1865, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1869 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1869 : node _T_1870 = asUInt(reset) node _T_1871 = eq(_T_1870, UInt<1>(0h0)) when _T_1871 : node _T_1872 = eq(source_ok_1, UInt<1>(0h0)) when _T_1872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1873 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1874 = asUInt(reset) node _T_1875 = eq(_T_1874, UInt<1>(0h0)) when _T_1875 : node _T_1876 = eq(_T_1873, UInt<1>(0h0)) when _T_1876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1873, UInt<1>(0h1), "") : assert_54 node _T_1877 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1878 = asUInt(reset) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) when _T_1879 : node _T_1880 = eq(_T_1877, UInt<1>(0h0)) when _T_1880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1877, UInt<1>(0h1), "") : assert_55 node _T_1881 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1882 = asUInt(reset) node _T_1883 = eq(_T_1882, UInt<1>(0h0)) when _T_1883 : node _T_1884 = eq(_T_1881, UInt<1>(0h0)) when _T_1884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1881, UInt<1>(0h1), "") : assert_56 node _T_1885 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1886 = asUInt(reset) node _T_1887 = eq(_T_1886, UInt<1>(0h0)) when _T_1887 : node _T_1888 = eq(_T_1885, UInt<1>(0h0)) when _T_1888 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1885, UInt<1>(0h1), "") : assert_57 node _T_1889 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1889 : node _T_1890 = asUInt(reset) node _T_1891 = eq(_T_1890, UInt<1>(0h0)) when _T_1891 : node _T_1892 = eq(source_ok_1, UInt<1>(0h0)) when _T_1892 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1893 = asUInt(reset) node _T_1894 = eq(_T_1893, UInt<1>(0h0)) when _T_1894 : node _T_1895 = eq(sink_ok, UInt<1>(0h0)) when _T_1895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1896 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1897 = asUInt(reset) node _T_1898 = eq(_T_1897, UInt<1>(0h0)) when _T_1898 : node _T_1899 = eq(_T_1896, UInt<1>(0h0)) when _T_1899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1896, UInt<1>(0h1), "") : assert_60 node _T_1900 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1901 = asUInt(reset) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(_T_1900, UInt<1>(0h0)) when _T_1903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1900, UInt<1>(0h1), "") : assert_61 node _T_1904 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1905 = asUInt(reset) node _T_1906 = eq(_T_1905, UInt<1>(0h0)) when _T_1906 : node _T_1907 = eq(_T_1904, UInt<1>(0h0)) when _T_1907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1904, UInt<1>(0h1), "") : assert_62 node _T_1908 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_63 node _T_1912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1913 = or(UInt<1>(0h0), _T_1912) node _T_1914 = asUInt(reset) node _T_1915 = eq(_T_1914, UInt<1>(0h0)) when _T_1915 : node _T_1916 = eq(_T_1913, UInt<1>(0h0)) when _T_1916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1913, UInt<1>(0h1), "") : assert_64 node _T_1917 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1917 : node _T_1918 = asUInt(reset) node _T_1919 = eq(_T_1918, UInt<1>(0h0)) when _T_1919 : node _T_1920 = eq(source_ok_1, UInt<1>(0h0)) when _T_1920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1921 = asUInt(reset) node _T_1922 = eq(_T_1921, UInt<1>(0h0)) when _T_1922 : node _T_1923 = eq(sink_ok, UInt<1>(0h0)) when _T_1923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1924 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1925 = asUInt(reset) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(_T_1924, UInt<1>(0h0)) when _T_1927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1924, UInt<1>(0h1), "") : assert_67 node _T_1928 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1929 = asUInt(reset) node _T_1930 = eq(_T_1929, UInt<1>(0h0)) when _T_1930 : node _T_1931 = eq(_T_1928, UInt<1>(0h0)) when _T_1931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1928, UInt<1>(0h1), "") : assert_68 node _T_1932 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1933 = asUInt(reset) node _T_1934 = eq(_T_1933, UInt<1>(0h0)) when _T_1934 : node _T_1935 = eq(_T_1932, UInt<1>(0h0)) when _T_1935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1932, UInt<1>(0h1), "") : assert_69 node _T_1936 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1937 = or(_T_1936, io.in.d.bits.corrupt) node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(_T_1937, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1937, UInt<1>(0h1), "") : assert_70 node _T_1941 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1942 = or(UInt<1>(0h0), _T_1941) node _T_1943 = asUInt(reset) node _T_1944 = eq(_T_1943, UInt<1>(0h0)) when _T_1944 : node _T_1945 = eq(_T_1942, UInt<1>(0h0)) when _T_1945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1942, UInt<1>(0h1), "") : assert_71 node _T_1946 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1946 : node _T_1947 = asUInt(reset) node _T_1948 = eq(_T_1947, UInt<1>(0h0)) when _T_1948 : node _T_1949 = eq(source_ok_1, UInt<1>(0h0)) when _T_1949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1950 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1951 = asUInt(reset) node _T_1952 = eq(_T_1951, UInt<1>(0h0)) when _T_1952 : node _T_1953 = eq(_T_1950, UInt<1>(0h0)) when _T_1953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1950, UInt<1>(0h1), "") : assert_73 node _T_1954 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1955 = asUInt(reset) node _T_1956 = eq(_T_1955, UInt<1>(0h0)) when _T_1956 : node _T_1957 = eq(_T_1954, UInt<1>(0h0)) when _T_1957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1954, UInt<1>(0h1), "") : assert_74 node _T_1958 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1959 = or(UInt<1>(0h0), _T_1958) node _T_1960 = asUInt(reset) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) when _T_1961 : node _T_1962 = eq(_T_1959, UInt<1>(0h0)) when _T_1962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1959, UInt<1>(0h1), "") : assert_75 node _T_1963 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1963 : node _T_1964 = asUInt(reset) node _T_1965 = eq(_T_1964, UInt<1>(0h0)) when _T_1965 : node _T_1966 = eq(source_ok_1, UInt<1>(0h0)) when _T_1966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1967 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1968 = asUInt(reset) node _T_1969 = eq(_T_1968, UInt<1>(0h0)) when _T_1969 : node _T_1970 = eq(_T_1967, UInt<1>(0h0)) when _T_1970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1967, UInt<1>(0h1), "") : assert_77 node _T_1971 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1972 = or(_T_1971, io.in.d.bits.corrupt) node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(_T_1972, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1972, UInt<1>(0h1), "") : assert_78 node _T_1976 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1977 = or(UInt<1>(0h0), _T_1976) node _T_1978 = asUInt(reset) node _T_1979 = eq(_T_1978, UInt<1>(0h0)) when _T_1979 : node _T_1980 = eq(_T_1977, UInt<1>(0h0)) when _T_1980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1977, UInt<1>(0h1), "") : assert_79 node _T_1981 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1981 : node _T_1982 = asUInt(reset) node _T_1983 = eq(_T_1982, UInt<1>(0h0)) when _T_1983 : node _T_1984 = eq(source_ok_1, UInt<1>(0h0)) when _T_1984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1985 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1986 = asUInt(reset) node _T_1987 = eq(_T_1986, UInt<1>(0h0)) when _T_1987 : node _T_1988 = eq(_T_1985, UInt<1>(0h0)) when _T_1988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1985, UInt<1>(0h1), "") : assert_81 node _T_1989 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1990 = asUInt(reset) node _T_1991 = eq(_T_1990, UInt<1>(0h0)) when _T_1991 : node _T_1992 = eq(_T_1989, UInt<1>(0h0)) when _T_1992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1989, UInt<1>(0h1), "") : assert_82 node _T_1993 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1994 = or(UInt<1>(0h0), _T_1993) node _T_1995 = asUInt(reset) node _T_1996 = eq(_T_1995, UInt<1>(0h0)) when _T_1996 : node _T_1997 = eq(_T_1994, UInt<1>(0h0)) when _T_1997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1994, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<17>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1998 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1999 = asUInt(reset) node _T_2000 = eq(_T_1999, UInt<1>(0h0)) when _T_2000 : node _T_2001 = eq(_T_1998, UInt<1>(0h0)) when _T_2001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1998, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2002 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2003 = asUInt(reset) node _T_2004 = eq(_T_2003, UInt<1>(0h0)) when _T_2004 : node _T_2005 = eq(_T_2002, UInt<1>(0h0)) when _T_2005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2002, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2006 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2007 = asUInt(reset) node _T_2008 = eq(_T_2007, UInt<1>(0h0)) when _T_2008 : node _T_2009 = eq(_T_2006, UInt<1>(0h0)) when _T_2009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2006, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2010 = eq(a_first, UInt<1>(0h0)) node _T_2011 = and(io.in.a.valid, _T_2010) when _T_2011 : node _T_2012 = eq(io.in.a.bits.opcode, opcode) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_87 node _T_2016 = eq(io.in.a.bits.param, param) node _T_2017 = asUInt(reset) node _T_2018 = eq(_T_2017, UInt<1>(0h0)) when _T_2018 : node _T_2019 = eq(_T_2016, UInt<1>(0h0)) when _T_2019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2016, UInt<1>(0h1), "") : assert_88 node _T_2020 = eq(io.in.a.bits.size, size) node _T_2021 = asUInt(reset) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(_T_2020, UInt<1>(0h0)) when _T_2023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2020, UInt<1>(0h1), "") : assert_89 node _T_2024 = eq(io.in.a.bits.source, source) node _T_2025 = asUInt(reset) node _T_2026 = eq(_T_2025, UInt<1>(0h0)) when _T_2026 : node _T_2027 = eq(_T_2024, UInt<1>(0h0)) when _T_2027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2024, UInt<1>(0h1), "") : assert_90 node _T_2028 = eq(io.in.a.bits.address, address) node _T_2029 = asUInt(reset) node _T_2030 = eq(_T_2029, UInt<1>(0h0)) when _T_2030 : node _T_2031 = eq(_T_2028, UInt<1>(0h0)) when _T_2031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2028, UInt<1>(0h1), "") : assert_91 node _T_2032 = and(io.in.a.ready, io.in.a.valid) node _T_2033 = and(_T_2032, a_first) when _T_2033 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2034 = eq(d_first, UInt<1>(0h0)) node _T_2035 = and(io.in.d.valid, _T_2034) when _T_2035 : node _T_2036 = eq(io.in.d.bits.opcode, opcode_1) node _T_2037 = asUInt(reset) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) when _T_2038 : node _T_2039 = eq(_T_2036, UInt<1>(0h0)) when _T_2039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2036, UInt<1>(0h1), "") : assert_92 node _T_2040 = eq(io.in.d.bits.param, param_1) node _T_2041 = asUInt(reset) node _T_2042 = eq(_T_2041, UInt<1>(0h0)) when _T_2042 : node _T_2043 = eq(_T_2040, UInt<1>(0h0)) when _T_2043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2040, UInt<1>(0h1), "") : assert_93 node _T_2044 = eq(io.in.d.bits.size, size_1) node _T_2045 = asUInt(reset) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(_T_2044, UInt<1>(0h0)) when _T_2047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2044, UInt<1>(0h1), "") : assert_94 node _T_2048 = eq(io.in.d.bits.source, source_1) node _T_2049 = asUInt(reset) node _T_2050 = eq(_T_2049, UInt<1>(0h0)) when _T_2050 : node _T_2051 = eq(_T_2048, UInt<1>(0h0)) when _T_2051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2048, UInt<1>(0h1), "") : assert_95 node _T_2052 = eq(io.in.d.bits.sink, sink) node _T_2053 = asUInt(reset) node _T_2054 = eq(_T_2053, UInt<1>(0h0)) when _T_2054 : node _T_2055 = eq(_T_2052, UInt<1>(0h0)) when _T_2055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2052, UInt<1>(0h1), "") : assert_96 node _T_2056 = eq(io.in.d.bits.denied, denied) node _T_2057 = asUInt(reset) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(_T_2056, UInt<1>(0h0)) when _T_2059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2056, UInt<1>(0h1), "") : assert_97 node _T_2060 = and(io.in.d.ready, io.in.d.valid) node _T_2061 = and(_T_2060, d_first) when _T_2061 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2062 = and(io.in.a.valid, a_first_1) node _T_2063 = and(_T_2062, UInt<1>(0h1)) when _T_2063 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2064 = and(io.in.a.ready, io.in.a.valid) node _T_2065 = and(_T_2064, a_first_1) node _T_2066 = and(_T_2065, UInt<1>(0h1)) when _T_2066 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2067 = dshr(inflight, io.in.a.bits.source) node _T_2068 = bits(_T_2067, 0, 0) node _T_2069 = eq(_T_2068, UInt<1>(0h0)) node _T_2070 = asUInt(reset) node _T_2071 = eq(_T_2070, UInt<1>(0h0)) when _T_2071 : node _T_2072 = eq(_T_2069, UInt<1>(0h0)) when _T_2072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2069, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2073 = and(io.in.d.valid, d_first_1) node _T_2074 = and(_T_2073, UInt<1>(0h1)) node _T_2075 = eq(d_release_ack, UInt<1>(0h0)) node _T_2076 = and(_T_2074, _T_2075) when _T_2076 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2077 = and(io.in.d.ready, io.in.d.valid) node _T_2078 = and(_T_2077, d_first_1) node _T_2079 = and(_T_2078, UInt<1>(0h1)) node _T_2080 = eq(d_release_ack, UInt<1>(0h0)) node _T_2081 = and(_T_2079, _T_2080) when _T_2081 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2082 = and(io.in.d.valid, d_first_1) node _T_2083 = and(_T_2082, UInt<1>(0h1)) node _T_2084 = eq(d_release_ack, UInt<1>(0h0)) node _T_2085 = and(_T_2083, _T_2084) when _T_2085 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2086 = dshr(inflight, io.in.d.bits.source) node _T_2087 = bits(_T_2086, 0, 0) node _T_2088 = or(_T_2087, same_cycle_resp) node _T_2089 = asUInt(reset) node _T_2090 = eq(_T_2089, UInt<1>(0h0)) when _T_2090 : node _T_2091 = eq(_T_2088, UInt<1>(0h0)) when _T_2091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2088, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2092 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2093 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2094 = or(_T_2092, _T_2093) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_100 node _T_2098 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2099 = asUInt(reset) node _T_2100 = eq(_T_2099, UInt<1>(0h0)) when _T_2100 : node _T_2101 = eq(_T_2098, UInt<1>(0h0)) when _T_2101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2098, UInt<1>(0h1), "") : assert_101 else : node _T_2102 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2103 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2104 = or(_T_2102, _T_2103) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_102 node _T_2108 = eq(io.in.d.bits.size, a_size_lookup) node _T_2109 = asUInt(reset) node _T_2110 = eq(_T_2109, UInt<1>(0h0)) when _T_2110 : node _T_2111 = eq(_T_2108, UInt<1>(0h0)) when _T_2111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2108, UInt<1>(0h1), "") : assert_103 node _T_2112 = and(io.in.d.valid, d_first_1) node _T_2113 = and(_T_2112, a_first_1) node _T_2114 = and(_T_2113, io.in.a.valid) node _T_2115 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2116 = and(_T_2114, _T_2115) node _T_2117 = eq(d_release_ack, UInt<1>(0h0)) node _T_2118 = and(_T_2116, _T_2117) when _T_2118 : node _T_2119 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2120 = or(_T_2119, io.in.a.ready) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_110 node _T_2124 = orr(inflight) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) node _T_2126 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2127 = or(_T_2125, _T_2126) node _T_2128 = lt(watchdog, plusarg_reader.out) node _T_2129 = or(_T_2127, _T_2128) node _T_2130 = asUInt(reset) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) when _T_2131 : node _T_2132 = eq(_T_2129, UInt<1>(0h0)) when _T_2132 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2129, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2133 = and(io.in.a.ready, io.in.a.valid) node _T_2134 = and(io.in.d.ready, io.in.d.valid) node _T_2135 = or(_T_2133, _T_2134) when _T_2135 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2136 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2137 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2138 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2139 = and(_T_2137, _T_2138) node _T_2140 = and(_T_2136, _T_2139) when _T_2140 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2141 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2142 = and(_T_2141, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2143 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2147 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2148 = bits(_T_2147, 0, 0) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) node _T_2150 = asUInt(reset) node _T_2151 = eq(_T_2150, UInt<1>(0h0)) when _T_2151 : node _T_2152 = eq(_T_2149, UInt<1>(0h0)) when _T_2152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2149, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2153 = and(io.in.d.valid, d_first_2) node _T_2154 = and(_T_2153, UInt<1>(0h1)) node _T_2155 = and(_T_2154, d_release_ack_1) when _T_2155 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2156 = and(io.in.d.ready, io.in.d.valid) node _T_2157 = and(_T_2156, d_first_2) node _T_2158 = and(_T_2157, UInt<1>(0h1)) node _T_2159 = and(_T_2158, d_release_ack_1) when _T_2159 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2160 = and(io.in.d.valid, d_first_2) node _T_2161 = and(_T_2160, UInt<1>(0h1)) node _T_2162 = and(_T_2161, d_release_ack_1) when _T_2162 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2163 = dshr(inflight_1, io.in.d.bits.source) node _T_2164 = bits(_T_2163, 0, 0) node _T_2165 = or(_T_2164, same_cycle_resp_1) node _T_2166 = asUInt(reset) node _T_2167 = eq(_T_2166, UInt<1>(0h0)) when _T_2167 : node _T_2168 = eq(_T_2165, UInt<1>(0h0)) when _T_2168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2165, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2169 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2170 = asUInt(reset) node _T_2171 = eq(_T_2170, UInt<1>(0h0)) when _T_2171 : node _T_2172 = eq(_T_2169, UInt<1>(0h0)) when _T_2172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2169, UInt<1>(0h1), "") : assert_108 else : node _T_2173 = eq(io.in.d.bits.size, c_size_lookup) node _T_2174 = asUInt(reset) node _T_2175 = eq(_T_2174, UInt<1>(0h0)) when _T_2175 : node _T_2176 = eq(_T_2173, UInt<1>(0h0)) when _T_2176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2173, UInt<1>(0h1), "") : assert_109 node _T_2177 = and(io.in.d.valid, d_first_2) node _T_2178 = and(_T_2177, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2179 = and(_T_2178, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2180 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2181 = and(_T_2179, _T_2180) node _T_2182 = and(_T_2181, d_release_ack_1) node _T_2183 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2184 = and(_T_2182, _T_2183) when _T_2184 : node _T_2185 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<17>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2186 = or(_T_2185, _WIRE_27.ready) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_111 node _T_2190 = orr(inflight_1) node _T_2191 = eq(_T_2190, UInt<1>(0h0)) node _T_2192 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2193 = or(_T_2191, _T_2192) node _T_2194 = lt(watchdog_1, plusarg_reader_1.out) node _T_2195 = or(_T_2193, _T_2194) node _T_2196 = asUInt(reset) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) when _T_2197 : node _T_2198 = eq(_T_2195, UInt<1>(0h0)) when _T_2198 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2195, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<17>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2199 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2200 = and(io.in.d.ready, io.in.d.valid) node _T_2201 = or(_T_2199, _T_2200) when _T_2201 : connect watchdog_1, UInt<1>(0h0)

module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN = a_first_done & a_first_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]

Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_21 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3

module RecFNToRecFN_21( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ShiftQueue_7 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, count : UInt<3>, mask : UInt<5>} wire _valid_WIRE : UInt<1>[5] connect _valid_WIRE[0], UInt<1>(0h0) connect _valid_WIRE[1], UInt<1>(0h0) connect _valid_WIRE[2], UInt<1>(0h0) connect _valid_WIRE[3], UInt<1>(0h0) connect _valid_WIRE[4], UInt<1>(0h0) regreset valid : UInt<1>[5], clock, reset, _valid_WIRE reg elts : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}[5], clock node wdata = mux(valid[1], elts[1], io.enq.bits) node _wen_T = and(io.enq.ready, io.enq.valid) node _wen_T_1 = or(UInt<1>(0h0), valid[0]) node _wen_T_2 = and(_wen_T, _wen_T_1) node _wen_T_3 = or(valid[1], _wen_T_2) node _wen_T_4 = and(io.enq.ready, io.enq.valid) node _wen_T_5 = and(_wen_T_4, UInt<1>(0h1)) node _wen_T_6 = eq(valid[0], UInt<1>(0h0)) node _wen_T_7 = and(_wen_T_5, _wen_T_6) node wen = mux(io.deq.ready, _wen_T_3, _wen_T_7) when wen : connect elts[0], wdata node _valid_0_T = and(io.enq.ready, io.enq.valid) node _valid_0_T_1 = or(UInt<1>(0h0), valid[0]) node _valid_0_T_2 = and(_valid_0_T, _valid_0_T_1) node _valid_0_T_3 = or(valid[1], _valid_0_T_2) node _valid_0_T_4 = and(io.enq.ready, io.enq.valid) node _valid_0_T_5 = and(_valid_0_T_4, UInt<1>(0h1)) node _valid_0_T_6 = or(_valid_0_T_5, valid[0]) node _valid_0_T_7 = mux(io.deq.ready, _valid_0_T_3, _valid_0_T_6) connect valid[0], _valid_0_T_7 node wdata_1 = mux(valid[2], elts[2], io.enq.bits) node _wen_T_8 = and(io.enq.ready, io.enq.valid) node _wen_T_9 = or(UInt<1>(0h0), valid[1]) node _wen_T_10 = and(_wen_T_8, _wen_T_9) node _wen_T_11 = or(valid[2], _wen_T_10) node _wen_T_12 = and(io.enq.ready, io.enq.valid) node _wen_T_13 = and(_wen_T_12, valid[0]) node _wen_T_14 = eq(valid[1], UInt<1>(0h0)) node _wen_T_15 = and(_wen_T_13, _wen_T_14) node wen_1 = mux(io.deq.ready, _wen_T_11, _wen_T_15) when wen_1 : connect elts[1], wdata_1 node _valid_1_T = and(io.enq.ready, io.enq.valid) node _valid_1_T_1 = or(UInt<1>(0h0), valid[1]) node _valid_1_T_2 = and(_valid_1_T, _valid_1_T_1) node _valid_1_T_3 = or(valid[2], _valid_1_T_2) node _valid_1_T_4 = and(io.enq.ready, io.enq.valid) node _valid_1_T_5 = and(_valid_1_T_4, valid[0]) node _valid_1_T_6 = or(_valid_1_T_5, valid[1]) node _valid_1_T_7 = mux(io.deq.ready, _valid_1_T_3, _valid_1_T_6) connect valid[1], _valid_1_T_7 node wdata_2 = mux(valid[3], elts[3], io.enq.bits) node _wen_T_16 = and(io.enq.ready, io.enq.valid) node _wen_T_17 = or(UInt<1>(0h0), valid[2]) node _wen_T_18 = and(_wen_T_16, _wen_T_17) node _wen_T_19 = or(valid[3], _wen_T_18) node _wen_T_20 = and(io.enq.ready, io.enq.valid) node _wen_T_21 = and(_wen_T_20, valid[1]) node _wen_T_22 = eq(valid[2], UInt<1>(0h0)) node _wen_T_23 = and(_wen_T_21, _wen_T_22) node wen_2 = mux(io.deq.ready, _wen_T_19, _wen_T_23) when wen_2 : connect elts[2], wdata_2 node _valid_2_T = and(io.enq.ready, io.enq.valid) node _valid_2_T_1 = or(UInt<1>(0h0), valid[2]) node _valid_2_T_2 = and(_valid_2_T, _valid_2_T_1) node _valid_2_T_3 = or(valid[3], _valid_2_T_2) node _valid_2_T_4 = and(io.enq.ready, io.enq.valid) node _valid_2_T_5 = and(_valid_2_T_4, valid[1]) node _valid_2_T_6 = or(_valid_2_T_5, valid[2]) node _valid_2_T_7 = mux(io.deq.ready, _valid_2_T_3, _valid_2_T_6) connect valid[2], _valid_2_T_7 node wdata_3 = mux(valid[4], elts[4], io.enq.bits) node _wen_T_24 = and(io.enq.ready, io.enq.valid) node _wen_T_25 = or(UInt<1>(0h0), valid[3]) node _wen_T_26 = and(_wen_T_24, _wen_T_25) node _wen_T_27 = or(valid[4], _wen_T_26) node _wen_T_28 = and(io.enq.ready, io.enq.valid) node _wen_T_29 = and(_wen_T_28, valid[2]) node _wen_T_30 = eq(valid[3], UInt<1>(0h0)) node _wen_T_31 = and(_wen_T_29, _wen_T_30) node wen_3 = mux(io.deq.ready, _wen_T_27, _wen_T_31) when wen_3 : connect elts[3], wdata_3 node _valid_3_T = and(io.enq.ready, io.enq.valid) node _valid_3_T_1 = or(UInt<1>(0h0), valid[3]) node _valid_3_T_2 = and(_valid_3_T, _valid_3_T_1) node _valid_3_T_3 = or(valid[4], _valid_3_T_2) node _valid_3_T_4 = and(io.enq.ready, io.enq.valid) node _valid_3_T_5 = and(_valid_3_T_4, valid[2]) node _valid_3_T_6 = or(_valid_3_T_5, valid[3]) node _valid_3_T_7 = mux(io.deq.ready, _valid_3_T_3, _valid_3_T_6) connect valid[3], _valid_3_T_7 node _wen_T_32 = and(io.enq.ready, io.enq.valid) node _wen_T_33 = or(UInt<1>(0h0), valid[4]) node _wen_T_34 = and(_wen_T_32, _wen_T_33) node _wen_T_35 = or(UInt<1>(0h0), _wen_T_34) node _wen_T_36 = and(io.enq.ready, io.enq.valid) node _wen_T_37 = and(_wen_T_36, valid[3]) node _wen_T_38 = eq(valid[4], UInt<1>(0h0)) node _wen_T_39 = and(_wen_T_37, _wen_T_38) node wen_4 = mux(io.deq.ready, _wen_T_35, _wen_T_39) when wen_4 : connect elts[4], io.enq.bits node _valid_4_T = and(io.enq.ready, io.enq.valid) node _valid_4_T_1 = or(UInt<1>(0h0), valid[4]) node _valid_4_T_2 = and(_valid_4_T, _valid_4_T_1) node _valid_4_T_3 = or(UInt<1>(0h0), _valid_4_T_2) node _valid_4_T_4 = and(io.enq.ready, io.enq.valid) node _valid_4_T_5 = and(_valid_4_T_4, valid[3]) node _valid_4_T_6 = or(_valid_4_T_5, valid[4]) node _valid_4_T_7 = mux(io.deq.ready, _valid_4_T_3, _valid_4_T_6) connect valid[4], _valid_4_T_7 node _io_enq_ready_T = eq(valid[4], UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T connect io.deq.valid, valid[0] connect io.deq.bits, elts[0] when io.enq.valid : connect io.deq.valid, UInt<1>(0h1) node _T = eq(valid[0], UInt<1>(0h0)) when _T : connect io.deq.bits, io.enq.bits node io_mask_lo = cat(valid[1], valid[0]) node io_mask_hi_hi = cat(valid[4], valid[3]) node io_mask_hi = cat(io_mask_hi_hi, valid[2]) node _io_mask_T = cat(io_mask_hi, io_mask_lo) connect io.mask, _io_mask_T node _io_count_T = bits(io.mask, 0, 0) node _io_count_T_1 = bits(io.mask, 1, 1) node _io_count_T_2 = bits(io.mask, 2, 2) node _io_count_T_3 = bits(io.mask, 3, 3) node _io_count_T_4 = bits(io.mask, 4, 4) node _io_count_T_5 = add(_io_count_T, _io_count_T_1) node _io_count_T_6 = bits(_io_count_T_5, 1, 0) node _io_count_T_7 = add(_io_count_T_3, _io_count_T_4) node _io_count_T_8 = bits(_io_count_T_7, 1, 0) node _io_count_T_9 = add(_io_count_T_2, _io_count_T_8) node _io_count_T_10 = bits(_io_count_T_9, 1, 0) node _io_count_T_11 = add(_io_count_T_6, _io_count_T_10) node _io_count_T_12 = bits(_io_count_T_11, 2, 0) connect io.count, _io_count_T_12

module ShiftQueue_7( // @[ShiftQueue.scala:12:7] input clock, // @[ShiftQueue.scala:12:7] input reset, // @[ShiftQueue.scala:12:7] output io_enq_ready, // @[ShiftQueue.scala:17:14] input io_enq_valid, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_taken, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_btb_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] input [38:0] io_enq_bits_btb_target, // @[ShiftQueue.scala:17:14] input [4:0] io_enq_bits_btb_entry, // @[ShiftQueue.scala:17:14] input [7:0] io_enq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] input io_enq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] input [39:0] io_enq_bits_pc, // @[ShiftQueue.scala:17:14] input [31:0] io_enq_bits_data, // @[ShiftQueue.scala:17:14] input [1:0] io_enq_bits_mask, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] input io_enq_bits_replay, // @[ShiftQueue.scala:17:14] input io_deq_ready, // @[ShiftQueue.scala:17:14] output io_deq_valid, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_cfiType, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_taken, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_btb_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bridx, // @[ShiftQueue.scala:17:14] output [38:0] io_deq_bits_btb_target, // @[ShiftQueue.scala:17:14] output [4:0] io_deq_bits_btb_entry, // @[ShiftQueue.scala:17:14] output [7:0] io_deq_bits_btb_bht_history, // @[ShiftQueue.scala:17:14] output io_deq_bits_btb_bht_value, // @[ShiftQueue.scala:17:14] output [39:0] io_deq_bits_pc, // @[ShiftQueue.scala:17:14] output [31:0] io_deq_bits_data, // @[ShiftQueue.scala:17:14] output [1:0] io_deq_bits_mask, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_pf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_gf_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_xcpt_ae_inst, // @[ShiftQueue.scala:17:14] output io_deq_bits_replay, // @[ShiftQueue.scala:17:14] output [4:0] io_mask // @[ShiftQueue.scala:17:14] ); wire io_enq_valid_0 = io_enq_valid; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_cfiType_0 = io_enq_bits_btb_cfiType; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_taken_0 = io_enq_bits_btb_taken; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_btb_mask_0 = io_enq_bits_btb_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bridx_0 = io_enq_bits_btb_bridx; // @[ShiftQueue.scala:12:7] wire [38:0] io_enq_bits_btb_target_0 = io_enq_bits_btb_target; // @[ShiftQueue.scala:12:7] wire [4:0] io_enq_bits_btb_entry_0 = io_enq_bits_btb_entry; // @[ShiftQueue.scala:12:7] wire [7:0] io_enq_bits_btb_bht_history_0 = io_enq_bits_btb_bht_history; // @[ShiftQueue.scala:12:7] wire io_enq_bits_btb_bht_value_0 = io_enq_bits_btb_bht_value; // @[ShiftQueue.scala:12:7] wire [39:0] io_enq_bits_pc_0 = io_enq_bits_pc; // @[ShiftQueue.scala:12:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[ShiftQueue.scala:12:7] wire [1:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_pf_inst_0 = io_enq_bits_xcpt_pf_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_ae_inst_0 = io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala:12:7] wire io_enq_bits_replay_0 = io_enq_bits_replay; // @[ShiftQueue.scala:12:7] wire io_deq_ready_0 = io_deq_ready; // @[ShiftQueue.scala:12:7] wire io_enq_bits_xcpt_gf_inst = 1'h0; // @[ShiftQueue.scala:12:7] wire _valid_WIRE_0 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_1 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_2 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_3 = 1'h0; // @[ShiftQueue.scala:21:38] wire _valid_WIRE_4 = 1'h0; // @[ShiftQueue.scala:21:38] wire _io_enq_ready_T; // @[ShiftQueue.scala:40:19] wire [2:0] _io_count_T_12; // @[ShiftQueue.scala:54:23] wire [4:0] _io_mask_T; // @[ShiftQueue.scala:53:20] wire io_enq_ready_0; // @[ShiftQueue.scala:12:7] wire [7:0] io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] wire [38:0] io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] wire [4:0] io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] wire [39:0] io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] wire [31:0] io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] wire [1:0] io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] wire io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] wire io_deq_valid_0; // @[ShiftQueue.scala:12:7] wire [2:0] io_count; // @[ShiftQueue.scala:12:7] wire [4:0] io_mask_0; // @[ShiftQueue.scala:12:7] reg valid_0; // @[ShiftQueue.scala:21:30] wire _wen_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_0_T_1 = valid_0; // @[ShiftQueue.scala:21:30, :36:67] reg valid_1; // @[ShiftQueue.scala:21:30] wire _wen_T_9 = valid_1; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_1_T_1 = valid_1; // @[ShiftQueue.scala:21:30, :36:67] reg valid_2; // @[ShiftQueue.scala:21:30] wire _wen_T_17 = valid_2; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_2_T_1 = valid_2; // @[ShiftQueue.scala:21:30, :36:67] reg valid_3; // @[ShiftQueue.scala:21:30] wire _wen_T_25 = valid_3; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_3_T_1 = valid_3; // @[ShiftQueue.scala:21:30, :36:67] reg valid_4; // @[ShiftQueue.scala:21:30] wire _wen_T_33 = valid_4; // @[ShiftQueue.scala:21:30, :30:67] wire _valid_4_T_1 = valid_4; // @[ShiftQueue.scala:21:30, :36:67] reg [1:0] elts_0_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_0_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_0_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_0_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_0_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_0_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_0_mask; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_0_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_0_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_1_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_1_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_1_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_1_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_1_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_1_mask; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_1_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_2_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_2_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_2_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_2_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_2_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_2_mask; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_2_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_3_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_3_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_3_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_3_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_3_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_3_mask; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_3_replay; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_cfiType; // @[ShiftQueue.scala:22:25] reg elts_4_btb_taken; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_btb_mask; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bridx; // @[ShiftQueue.scala:22:25] reg [38:0] elts_4_btb_target; // @[ShiftQueue.scala:22:25] reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala:22:25] reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala:22:25] reg elts_4_btb_bht_value; // @[ShiftQueue.scala:22:25] reg [39:0] elts_4_pc; // @[ShiftQueue.scala:22:25] reg [31:0] elts_4_data; // @[ShiftQueue.scala:22:25] reg [1:0] elts_4_mask; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_pf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25] reg elts_4_xcpt_ae_inst; // @[ShiftQueue.scala:22:25] reg elts_4_replay; // @[ShiftQueue.scala:22:25] wire [1:0] wdata_btb_cfiType = valid_1 ? elts_1_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_taken = valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_btb_mask = valid_1 ? elts_1_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bridx = valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_btb_target = valid_1 ? elts_1_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_btb_entry = valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_btb_bht_history = valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_btb_bht_value = valid_1 ? elts_1_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_pc = valid_1 ? elts_1_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_data = valid_1 ? elts_1_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_mask = valid_1 ? elts_1_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_pf_inst = valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_xcpt_gf_inst = valid_1 & elts_1_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_xcpt_ae_inst = valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_replay = valid_1 ? elts_1_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _GEN = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _wen_T; // @[Decoupled.scala:51:35] assign _wen_T = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_4; // @[Decoupled.scala:51:35] assign _wen_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T; // @[Decoupled.scala:51:35] assign _valid_0_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_0_T_4; // @[Decoupled.scala:51:35] assign _valid_0_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_8; // @[Decoupled.scala:51:35] assign _wen_T_8 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_12; // @[Decoupled.scala:51:35] assign _wen_T_12 = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T; // @[Decoupled.scala:51:35] assign _valid_1_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_1_T_4; // @[Decoupled.scala:51:35] assign _valid_1_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_16; // @[Decoupled.scala:51:35] assign _wen_T_16 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_20; // @[Decoupled.scala:51:35] assign _wen_T_20 = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T; // @[Decoupled.scala:51:35] assign _valid_2_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_2_T_4; // @[Decoupled.scala:51:35] assign _valid_2_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_24; // @[Decoupled.scala:51:35] assign _wen_T_24 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_28; // @[Decoupled.scala:51:35] assign _wen_T_28 = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T; // @[Decoupled.scala:51:35] assign _valid_3_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_3_T_4; // @[Decoupled.scala:51:35] assign _valid_3_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_32; // @[Decoupled.scala:51:35] assign _wen_T_32 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_36; // @[Decoupled.scala:51:35] assign _wen_T_36 = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T; // @[Decoupled.scala:51:35] assign _valid_4_T = _GEN; // @[Decoupled.scala:51:35] wire _valid_4_T_4; // @[Decoupled.scala:51:35] assign _valid_4_T_4 = _GEN; // @[Decoupled.scala:51:35] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Decoupled.scala:51:35] wire _wen_T_3 = valid_1 | _wen_T_2; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_5 = _wen_T_4; // @[Decoupled.scala:51:35] wire _wen_T_6 = ~valid_0; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_7 = _wen_T_5 & _wen_T_6; // @[ShiftQueue.scala:31:{23,43,46}] wire wen = io_deq_ready_0 ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_0_T_2 = _valid_0_T & _valid_0_T_1; // @[Decoupled.scala:51:35] wire _valid_0_T_3 = valid_1 | _valid_0_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_0_T_5 = _valid_0_T_4; // @[Decoupled.scala:51:35] wire _valid_0_T_6 = _valid_0_T_5 | valid_0; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_0_T_7 = io_deq_ready_0 ? _valid_0_T_3 : _valid_0_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_1_btb_cfiType = valid_2 ? elts_2_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_taken = valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_btb_mask = valid_2 ? elts_2_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bridx = valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_1_btb_target = valid_2 ? elts_2_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_1_btb_entry = valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_1_btb_bht_history = valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_btb_bht_value = valid_2 ? elts_2_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_1_pc = valid_2 ? elts_2_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_1_data = valid_2 ? elts_2_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_1_mask = valid_2 ? elts_2_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_pf_inst = valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_xcpt_gf_inst = valid_2 & elts_2_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_1_xcpt_ae_inst = valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_1_replay = valid_2 ? elts_2_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_10 = _wen_T_8 & _wen_T_9; // @[Decoupled.scala:51:35] wire _wen_T_11 = valid_2 | _wen_T_10; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_13 = _wen_T_12 & valid_0; // @[Decoupled.scala:51:35] wire _wen_T_14 = ~valid_1; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_15 = _wen_T_13 & _wen_T_14; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_1 = io_deq_ready_0 ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_1_T_2 = _valid_1_T & _valid_1_T_1; // @[Decoupled.scala:51:35] wire _valid_1_T_3 = valid_2 | _valid_1_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_1_T_5 = _valid_1_T_4 & valid_0; // @[Decoupled.scala:51:35] wire _valid_1_T_6 = _valid_1_T_5 | valid_1; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_1_T_7 = io_deq_ready_0 ? _valid_1_T_3 : _valid_1_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_2_btb_cfiType = valid_3 ? elts_3_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_taken = valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_btb_mask = valid_3 ? elts_3_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bridx = valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_2_btb_target = valid_3 ? elts_3_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_2_btb_entry = valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_2_btb_bht_history = valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_btb_bht_value = valid_3 ? elts_3_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_2_pc = valid_3 ? elts_3_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_2_data = valid_3 ? elts_3_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_2_mask = valid_3 ? elts_3_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_pf_inst = valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_xcpt_gf_inst = valid_3 & elts_3_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_2_xcpt_ae_inst = valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_2_replay = valid_3 ? elts_3_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_18 = _wen_T_16 & _wen_T_17; // @[Decoupled.scala:51:35] wire _wen_T_19 = valid_3 | _wen_T_18; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_21 = _wen_T_20 & valid_1; // @[Decoupled.scala:51:35] wire _wen_T_22 = ~valid_2; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_23 = _wen_T_21 & _wen_T_22; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_2 = io_deq_ready_0 ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_2_T_2 = _valid_2_T & _valid_2_T_1; // @[Decoupled.scala:51:35] wire _valid_2_T_3 = valid_3 | _valid_2_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_2_T_5 = _valid_2_T_4 & valid_1; // @[Decoupled.scala:51:35] wire _valid_2_T_6 = _valid_2_T_5 | valid_2; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_2_T_7 = io_deq_ready_0 ? _valid_2_T_3 : _valid_2_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire [1:0] wdata_3_btb_cfiType = valid_4 ? elts_4_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_taken = valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_btb_mask = valid_4 ? elts_4_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bridx = valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [38:0] wdata_3_btb_target = valid_4 ? elts_4_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [4:0] wdata_3_btb_entry = valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [7:0] wdata_3_btb_bht_history = valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_btb_bht_value = valid_4 ? elts_4_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [39:0] wdata_3_pc = valid_4 ? elts_4_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [31:0] wdata_3_data = valid_4 ? elts_4_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire [1:0] wdata_3_mask = valid_4 ? elts_4_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_pf_inst = valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_xcpt_gf_inst = valid_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:21:30, :22:25, :27:57] wire wdata_3_xcpt_ae_inst = valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire wdata_3_replay = valid_4 ? elts_4_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :27:57] wire _wen_T_26 = _wen_T_24 & _wen_T_25; // @[Decoupled.scala:51:35] wire _wen_T_27 = valid_4 | _wen_T_26; // @[ShiftQueue.scala:21:30, :30:{28,43}] wire _wen_T_29 = _wen_T_28 & valid_2; // @[Decoupled.scala:51:35] wire _wen_T_30 = ~valid_3; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_31 = _wen_T_29 & _wen_T_30; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_3 = io_deq_ready_0 ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_3_T_2 = _valid_3_T & _valid_3_T_1; // @[Decoupled.scala:51:35] wire _valid_3_T_3 = valid_4 | _valid_3_T_2; // @[ShiftQueue.scala:21:30, :36:{28,43}] wire _valid_3_T_5 = _valid_3_T_4 & valid_2; // @[Decoupled.scala:51:35] wire _valid_3_T_6 = _valid_3_T_5 | valid_3; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_3_T_7 = io_deq_ready_0 ? _valid_3_T_3 : _valid_3_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] wire _wen_T_34 = _wen_T_32 & _wen_T_33; // @[Decoupled.scala:51:35] wire _wen_T_35 = _wen_T_34; // @[ShiftQueue.scala:30:{28,43}] wire _wen_T_37 = _wen_T_36 & valid_3; // @[Decoupled.scala:51:35] wire _wen_T_38 = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46] wire _wen_T_39 = _wen_T_37 & _wen_T_38; // @[ShiftQueue.scala:31:{23,43,46}] wire wen_4 = io_deq_ready_0 ? _wen_T_35 : _wen_T_39; // @[ShiftQueue.scala:12:7, :29:10, :30:28, :31:43] wire _valid_4_T_2 = _valid_4_T & _valid_4_T_1; // @[Decoupled.scala:51:35] wire _valid_4_T_3 = _valid_4_T_2; // @[ShiftQueue.scala:36:{28,43}] wire _valid_4_T_5 = _valid_4_T_4 & valid_3; // @[Decoupled.scala:51:35] wire _valid_4_T_6 = _valid_4_T_5 | valid_4; // @[ShiftQueue.scala:21:30, :37:{23,43}] wire _valid_4_T_7 = io_deq_ready_0 ? _valid_4_T_3 : _valid_4_T_6; // @[ShiftQueue.scala:12:7, :35:10, :36:28, :37:43] assign _io_enq_ready_T = ~valid_4; // @[ShiftQueue.scala:21:30, :31:46, :40:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[ShiftQueue.scala:12:7, :40:19] assign io_deq_valid_0 = io_enq_valid_0 | valid_0; // @[ShiftQueue.scala:12:7, :21:30, :41:16, :45:{25,40}] assign io_deq_bits_btb_cfiType_0 = valid_0 ? elts_0_btb_cfiType : io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_taken_0 = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_mask_0 = valid_0 ? elts_0_btb_mask : io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bridx_0 = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_target_0 = valid_0 ? elts_0_btb_target : io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_entry_0 = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_history_0 = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_btb_bht_value_0 = valid_0 ? elts_0_btb_bht_value : io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_pc_0 = valid_0 ? elts_0_pc : io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_data_0 = valid_0 ? elts_0_data : io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_mask_0 = valid_0 ? elts_0_mask : io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_pf_inst_0 = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_gf_inst_0 = valid_0 & elts_0_xcpt_gf_inst; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_xcpt_ae_inst_0 = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] assign io_deq_bits_replay_0 = valid_0 ? elts_0_replay : io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :21:30, :22:25, :42:15, :46:{22,36}] wire [1:0] io_mask_lo = {valid_1, valid_0}; // @[ShiftQueue.scala:21:30, :53:20] wire [1:0] io_mask_hi_hi = {valid_4, valid_3}; // @[ShiftQueue.scala:21:30, :53:20] wire [2:0] io_mask_hi = {io_mask_hi_hi, valid_2}; // @[ShiftQueue.scala:21:30, :53:20] assign _io_mask_T = {io_mask_hi, io_mask_lo}; // @[ShiftQueue.scala:53:20] assign io_mask_0 = _io_mask_T; // @[ShiftQueue.scala:12:7, :53:20] wire _io_count_T = io_mask_0[0]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_1 = io_mask_0[1]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_2 = io_mask_0[2]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_3 = io_mask_0[3]; // @[ShiftQueue.scala:12:7, :54:23] wire _io_count_T_4 = io_mask_0[4]; // @[ShiftQueue.scala:12:7, :54:23] wire [1:0] _io_count_T_5 = {1'h0, _io_count_T} + {1'h0, _io_count_T_1}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_6 = _io_count_T_5; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_7 = {1'h0, _io_count_T_3} + {1'h0, _io_count_T_4}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_8 = _io_count_T_7; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_9 = {2'h0, _io_count_T_2} + {1'h0, _io_count_T_8}; // @[ShiftQueue.scala:54:23] wire [1:0] _io_count_T_10 = _io_count_T_9[1:0]; // @[ShiftQueue.scala:54:23] wire [2:0] _io_count_T_11 = {1'h0, _io_count_T_6} + {1'h0, _io_count_T_10}; // @[ShiftQueue.scala:54:23] assign _io_count_T_12 = _io_count_T_11; // @[ShiftQueue.scala:54:23] assign io_count = _io_count_T_12; // @[ShiftQueue.scala:12:7, :54:23] always @(posedge clock) begin // @[ShiftQueue.scala:12:7] if (reset) begin // @[ShiftQueue.scala:12:7] valid_0 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_1 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_2 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_3 <= 1'h0; // @[ShiftQueue.scala:21:30] valid_4 <= 1'h0; // @[ShiftQueue.scala:21:30] end else begin // @[ShiftQueue.scala:12:7] valid_0 <= _valid_0_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_1 <= _valid_1_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_2 <= _valid_2_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_3 <= _valid_3_T_7; // @[ShiftQueue.scala:21:30, :35:10] valid_4 <= _valid_4_T_7; // @[ShiftQueue.scala:21:30, :35:10] end if (wen) begin // @[ShiftQueue.scala:29:10] elts_0_btb_cfiType <= wdata_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_taken <= wdata_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_mask <= wdata_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bridx <= wdata_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_target <= wdata_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_entry <= wdata_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_history <= wdata_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_0_btb_bht_value <= wdata_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_0_pc <= wdata_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_0_data <= wdata_data; // @[ShiftQueue.scala:22:25, :27:57] elts_0_mask <= wdata_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_pf_inst <= wdata_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_gf_inst <= wdata_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_xcpt_ae_inst <= wdata_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_0_replay <= wdata_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_1) begin // @[ShiftQueue.scala:29:10] elts_1_btb_cfiType <= wdata_1_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_taken <= wdata_1_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_mask <= wdata_1_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bridx <= wdata_1_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_target <= wdata_1_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_entry <= wdata_1_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_history <= wdata_1_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_1_btb_bht_value <= wdata_1_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_1_pc <= wdata_1_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_1_data <= wdata_1_data; // @[ShiftQueue.scala:22:25, :27:57] elts_1_mask <= wdata_1_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_pf_inst <= wdata_1_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_gf_inst <= wdata_1_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_xcpt_ae_inst <= wdata_1_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_1_replay <= wdata_1_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_2) begin // @[ShiftQueue.scala:29:10] elts_2_btb_cfiType <= wdata_2_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_taken <= wdata_2_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_mask <= wdata_2_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bridx <= wdata_2_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_target <= wdata_2_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_entry <= wdata_2_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_history <= wdata_2_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_2_btb_bht_value <= wdata_2_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_2_pc <= wdata_2_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_2_data <= wdata_2_data; // @[ShiftQueue.scala:22:25, :27:57] elts_2_mask <= wdata_2_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_pf_inst <= wdata_2_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_gf_inst <= wdata_2_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_xcpt_ae_inst <= wdata_2_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_2_replay <= wdata_2_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_3) begin // @[ShiftQueue.scala:29:10] elts_3_btb_cfiType <= wdata_3_btb_cfiType; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_taken <= wdata_3_btb_taken; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_mask <= wdata_3_btb_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bridx <= wdata_3_btb_bridx; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_target <= wdata_3_btb_target; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_entry <= wdata_3_btb_entry; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_history <= wdata_3_btb_bht_history; // @[ShiftQueue.scala:22:25, :27:57] elts_3_btb_bht_value <= wdata_3_btb_bht_value; // @[ShiftQueue.scala:22:25, :27:57] elts_3_pc <= wdata_3_pc; // @[ShiftQueue.scala:22:25, :27:57] elts_3_data <= wdata_3_data; // @[ShiftQueue.scala:22:25, :27:57] elts_3_mask <= wdata_3_mask; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_pf_inst <= wdata_3_xcpt_pf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_gf_inst <= wdata_3_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_xcpt_ae_inst <= wdata_3_xcpt_ae_inst; // @[ShiftQueue.scala:22:25, :27:57] elts_3_replay <= wdata_3_replay; // @[ShiftQueue.scala:22:25, :27:57] end if (wen_4) begin // @[ShiftQueue.scala:29:10] elts_4_btb_cfiType <= io_enq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_taken <= io_enq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_mask <= io_enq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bridx <= io_enq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_target <= io_enq_bits_btb_target_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_entry <= io_enq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_history <= io_enq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_btb_bht_value <= io_enq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_pc <= io_enq_bits_pc_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_data <= io_enq_bits_data_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_mask <= io_enq_bits_mask_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7, :22:25] elts_4_replay <= io_enq_bits_replay_0; // @[ShiftQueue.scala:12:7, :22:25] end elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst; // @[ShiftQueue.scala:22:25, :29:10, :32:{16,26}] always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[ShiftQueue.scala:12:7] assign io_deq_valid = io_deq_valid_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_cfiType = io_deq_bits_btb_cfiType_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_taken = io_deq_bits_btb_taken_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_mask = io_deq_bits_btb_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bridx = io_deq_bits_btb_bridx_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_target = io_deq_bits_btb_target_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_entry = io_deq_bits_btb_entry_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_history = io_deq_bits_btb_bht_history_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_btb_bht_value = io_deq_bits_btb_bht_value_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_pc = io_deq_bits_pc_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_pf_inst = io_deq_bits_xcpt_pf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_gf_inst = io_deq_bits_xcpt_gf_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_xcpt_ae_inst = io_deq_bits_xcpt_ae_inst_0; // @[ShiftQueue.scala:12:7] assign io_deq_bits_replay = io_deq_bits_replay_0; // @[ShiftQueue.scala:12:7] assign io_mask = io_mask_0; // @[ShiftQueue.scala:12:7] endmodule

Generate the Verilog code corresponding to this FIRRTL code module ProbePicker : input clock : Clock input reset : Reset output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready inst monitor of TLMonitor_30 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_31 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeOut, nodeIn connect x1_nodeOut, nodeIn_1

module ProbePicker( // @[ProbePicker.scala:42:9] input clock, // @[ProbePicker.scala:42:9] input reset, // @[ProbePicker.scala:42:9] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLMonitor_30 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_0_a_ready), .io_in_a_valid (auto_in_0_a_valid), .io_in_a_bits_opcode (auto_in_0_a_bits_opcode), .io_in_a_bits_param (auto_in_0_a_bits_param), .io_in_a_bits_size (auto_in_0_a_bits_size), .io_in_a_bits_source (auto_in_0_a_bits_source), .io_in_a_bits_address (auto_in_0_a_bits_address), .io_in_a_bits_mask (auto_in_0_a_bits_mask), .io_in_a_bits_corrupt (auto_in_0_a_bits_corrupt), .io_in_d_ready (auto_in_0_d_ready), .io_in_d_valid (auto_out_0_d_valid), .io_in_d_bits_opcode (auto_out_0_d_bits_opcode), .io_in_d_bits_size (auto_out_0_d_bits_size), .io_in_d_bits_source (auto_out_0_d_bits_source), .io_in_d_bits_denied (auto_out_0_d_bits_denied), .io_in_d_bits_corrupt (auto_out_0_d_bits_corrupt) ); // @[Nodes.scala:27:25] TLMonitor_31 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_out_1_a_ready), .io_in_a_valid (auto_in_1_a_valid), .io_in_a_bits_opcode (auto_in_1_a_bits_opcode), .io_in_a_bits_param (auto_in_1_a_bits_param), .io_in_a_bits_size (auto_in_1_a_bits_size), .io_in_a_bits_source (auto_in_1_a_bits_source), .io_in_a_bits_address (auto_in_1_a_bits_address), .io_in_a_bits_mask (auto_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_in_1_a_bits_corrupt), .io_in_d_ready (auto_in_1_d_ready), .io_in_d_valid (auto_out_1_d_valid), .io_in_d_bits_opcode (auto_out_1_d_bits_opcode), .io_in_d_bits_param (auto_out_1_d_bits_param), .io_in_d_bits_size (auto_out_1_d_bits_size), .io_in_d_bits_source (auto_out_1_d_bits_source), .io_in_d_bits_sink (auto_out_1_d_bits_sink), .io_in_d_bits_denied (auto_out_1_d_bits_denied), .io_in_d_bits_corrupt (auto_out_1_d_bits_corrupt) ); // @[Nodes.scala:27:25] assign auto_in_1_a_ready = auto_out_1_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_1_d_valid = auto_out_1_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_opcode = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_param = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_size = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_source = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_sink = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_denied = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_data = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_corrupt = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_in_0_a_ready = auto_out_0_a_ready; // @[ProbePicker.scala:42:9] assign auto_in_0_d_valid = auto_out_0_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_opcode = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_size = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_source = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_denied = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_data = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_corrupt = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_a_valid = auto_in_1_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_opcode = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_param = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_size = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_source = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_address = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_mask = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_data = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_d_ready = auto_in_1_d_ready; // @[ProbePicker.scala:42:9] assign auto_out_0_a_valid = auto_in_0_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_opcode = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_param = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_size = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_source = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_address = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_mask = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_data = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_0_d_ready = auto_in_0_d_ready; // @[ProbePicker.scala:42:9] endmodule